Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 41
- Errors: 0
- Boot result: PASS
1 19:59:55.535231 lava-dispatcher, installed at version: 2023.08
2 19:59:55.535432 start: 0 validate
3 19:59:55.535562 Start time: 2023-10-28 19:59:55.535555+00:00 (UTC)
4 19:59:55.535675 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:59:55.535876 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 19:59:55.806635 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:59:55.807376 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:59:56.078925 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:59:56.079797 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:59:56.350795 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:59:56.351535 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:59:56.621246 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:59:56.622028 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:59:56.891871 validate duration: 1.36
16 19:59:56.893123 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:59:56.893666 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:59:56.894178 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:59:56.894806 Not decompressing ramdisk as can be used compressed.
20 19:59:56.895323 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/initrd.cpio.gz
21 19:59:56.895690 saving as /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/ramdisk/initrd.cpio.gz
22 19:59:56.896123 total size: 5625687 (5 MB)
23 19:59:56.901375 progress 0 % (0 MB)
24 19:59:56.910582 progress 5 % (0 MB)
25 19:59:56.916831 progress 10 % (0 MB)
26 19:59:56.920762 progress 15 % (0 MB)
27 19:59:56.924515 progress 20 % (1 MB)
28 19:59:56.927582 progress 25 % (1 MB)
29 19:59:56.930507 progress 30 % (1 MB)
30 19:59:56.933239 progress 35 % (1 MB)
31 19:59:56.935437 progress 40 % (2 MB)
32 19:59:56.937816 progress 45 % (2 MB)
33 19:59:56.939754 progress 50 % (2 MB)
34 19:59:56.941904 progress 55 % (2 MB)
35 19:59:56.943867 progress 60 % (3 MB)
36 19:59:56.945585 progress 65 % (3 MB)
37 19:59:56.947492 progress 70 % (3 MB)
38 19:59:56.949055 progress 75 % (4 MB)
39 19:59:56.950789 progress 80 % (4 MB)
40 19:59:56.952340 progress 85 % (4 MB)
41 19:59:56.953934 progress 90 % (4 MB)
42 19:59:56.955522 progress 95 % (5 MB)
43 19:59:56.956964 progress 100 % (5 MB)
44 19:59:56.957174 5 MB downloaded in 0.06 s (87.85 MB/s)
45 19:59:56.957319 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:59:56.957553 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:59:56.957638 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:59:56.957720 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:59:56.957853 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:59:56.957924 saving as /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/kernel/Image
52 19:59:56.957984 total size: 49304064 (47 MB)
53 19:59:56.958045 No compression specified
54 19:59:56.959124 progress 0 % (0 MB)
55 19:59:56.971966 progress 5 % (2 MB)
56 19:59:56.984929 progress 10 % (4 MB)
57 19:59:56.997708 progress 15 % (7 MB)
58 19:59:57.010483 progress 20 % (9 MB)
59 19:59:57.023313 progress 25 % (11 MB)
60 19:59:57.035940 progress 30 % (14 MB)
61 19:59:57.048539 progress 35 % (16 MB)
62 19:59:57.061131 progress 40 % (18 MB)
63 19:59:57.073933 progress 45 % (21 MB)
64 19:59:57.086991 progress 50 % (23 MB)
65 19:59:57.099947 progress 55 % (25 MB)
66 19:59:57.112852 progress 60 % (28 MB)
67 19:59:57.125395 progress 65 % (30 MB)
68 19:59:57.137720 progress 70 % (32 MB)
69 19:59:57.150028 progress 75 % (35 MB)
70 19:59:57.162378 progress 80 % (37 MB)
71 19:59:57.174798 progress 85 % (39 MB)
72 19:59:57.187804 progress 90 % (42 MB)
73 19:59:57.200314 progress 95 % (44 MB)
74 19:59:57.212906 progress 100 % (47 MB)
75 19:59:57.213109 47 MB downloaded in 0.26 s (184.30 MB/s)
76 19:59:57.213258 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:59:57.213486 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:59:57.213572 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:59:57.213658 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:59:57.213799 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:59:57.213870 saving as /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/dtb/mt8192-asurada-spherion-r0.dtb
83 19:59:57.213930 total size: 47278 (0 MB)
84 19:59:57.213990 No compression specified
85 19:59:57.215194 progress 69 % (0 MB)
86 19:59:57.215463 progress 100 % (0 MB)
87 19:59:57.215614 0 MB downloaded in 0.00 s (26.81 MB/s)
88 19:59:57.215758 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:59:57.215989 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:59:57.216071 start: 1.4 download-retry (timeout 00:10:00) [common]
92 19:59:57.216151 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 19:59:57.216264 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 19:59:57.216333 saving as /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/nfsrootfs/full.rootfs.tar
95 19:59:57.216393 total size: 195204440 (186 MB)
96 19:59:57.216452 Using unxz to decompress xz
97 19:59:57.220452 progress 0 % (0 MB)
98 19:59:57.764228 progress 5 % (9 MB)
99 19:59:58.254536 progress 10 % (18 MB)
100 19:59:58.832001 progress 15 % (27 MB)
101 19:59:59.111310 progress 20 % (37 MB)
102 19:59:59.560452 progress 25 % (46 MB)
103 20:00:00.119086 progress 30 % (55 MB)
104 20:00:00.666695 progress 35 % (65 MB)
105 20:00:01.209357 progress 40 % (74 MB)
106 20:00:01.768523 progress 45 % (83 MB)
107 20:00:02.364370 progress 50 % (93 MB)
108 20:00:02.956955 progress 55 % (102 MB)
109 20:00:03.595541 progress 60 % (111 MB)
110 20:00:03.968348 progress 65 % (121 MB)
111 20:00:04.048010 progress 70 % (130 MB)
112 20:00:04.185712 progress 75 % (139 MB)
113 20:00:04.265598 progress 80 % (148 MB)
114 20:00:04.310819 progress 85 % (158 MB)
115 20:00:04.400950 progress 90 % (167 MB)
116 20:00:04.772265 progress 95 % (176 MB)
117 20:00:05.335370 progress 100 % (186 MB)
118 20:00:05.340195 186 MB downloaded in 8.12 s (22.92 MB/s)
119 20:00:05.340452 end: 1.4.1 http-download (duration 00:00:08) [common]
121 20:00:05.340798 end: 1.4 download-retry (duration 00:00:08) [common]
122 20:00:05.340896 start: 1.5 download-retry (timeout 00:09:52) [common]
123 20:00:05.340981 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 20:00:05.341135 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 20:00:05.341204 saving as /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/modules/modules.tar
126 20:00:05.341270 total size: 8635496 (8 MB)
127 20:00:05.341336 Using unxz to decompress xz
128 20:00:05.345423 progress 0 % (0 MB)
129 20:00:05.366795 progress 5 % (0 MB)
130 20:00:05.388747 progress 10 % (0 MB)
131 20:00:05.414783 progress 15 % (1 MB)
132 20:00:05.440192 progress 20 % (1 MB)
133 20:00:05.465517 progress 25 % (2 MB)
134 20:00:05.493448 progress 30 % (2 MB)
135 20:00:05.518427 progress 35 % (2 MB)
136 20:00:05.543115 progress 40 % (3 MB)
137 20:00:05.567016 progress 45 % (3 MB)
138 20:00:05.593075 progress 50 % (4 MB)
139 20:00:05.618171 progress 55 % (4 MB)
140 20:00:05.644218 progress 60 % (4 MB)
141 20:00:05.666709 progress 65 % (5 MB)
142 20:00:05.691276 progress 70 % (5 MB)
143 20:00:05.715563 progress 75 % (6 MB)
144 20:00:05.741566 progress 80 % (6 MB)
145 20:00:05.773733 progress 85 % (7 MB)
146 20:00:05.799344 progress 90 % (7 MB)
147 20:00:05.823432 progress 95 % (7 MB)
148 20:00:05.846092 progress 100 % (8 MB)
149 20:00:05.851663 8 MB downloaded in 0.51 s (16.14 MB/s)
150 20:00:05.851916 end: 1.5.1 http-download (duration 00:00:01) [common]
152 20:00:05.852174 end: 1.5 download-retry (duration 00:00:01) [common]
153 20:00:05.852265 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 20:00:05.852361 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 20:00:09.474846 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11899622/extract-nfsrootfs-dl4xqeyi
156 20:00:09.475047 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 20:00:09.475146 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 20:00:09.475317 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial
159 20:00:09.475457 makedir: /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin
160 20:00:09.475588 makedir: /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/tests
161 20:00:09.475691 makedir: /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/results
162 20:00:09.475978 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-add-keys
163 20:00:09.476125 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-add-sources
164 20:00:09.476255 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-background-process-start
165 20:00:09.476385 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-background-process-stop
166 20:00:09.476511 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-common-functions
167 20:00:09.476636 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-echo-ipv4
168 20:00:09.476767 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-install-packages
169 20:00:09.476892 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-installed-packages
170 20:00:09.477015 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-os-build
171 20:00:09.477140 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-probe-channel
172 20:00:09.477265 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-probe-ip
173 20:00:09.477389 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-target-ip
174 20:00:09.477514 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-target-mac
175 20:00:09.477637 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-target-storage
176 20:00:09.477764 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-test-case
177 20:00:09.477889 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-test-event
178 20:00:09.478013 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-test-feedback
179 20:00:09.478137 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-test-raise
180 20:00:09.478260 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-test-reference
181 20:00:09.478385 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-test-runner
182 20:00:09.478508 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-test-set
183 20:00:09.478633 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-test-shell
184 20:00:09.478765 Updating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-add-keys (debian)
185 20:00:09.478916 Updating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-add-sources (debian)
186 20:00:09.479059 Updating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-install-packages (debian)
187 20:00:09.479199 Updating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-installed-packages (debian)
188 20:00:09.479338 Updating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/bin/lava-os-build (debian)
189 20:00:09.479459 Creating /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/environment
190 20:00:09.479583 LAVA metadata
191 20:00:09.479656 - LAVA_JOB_ID=11899622
192 20:00:09.479724 - LAVA_DISPATCHER_IP=192.168.201.1
193 20:00:09.479869 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 20:00:09.479936 skipped lava-vland-overlay
195 20:00:09.480010 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 20:00:09.480088 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 20:00:09.480161 skipped lava-multinode-overlay
198 20:00:09.480235 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 20:00:09.480314 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 20:00:09.480386 Loading test definitions
201 20:00:09.480476 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 20:00:09.480545 Using /lava-11899622 at stage 0
203 20:00:09.480834 uuid=11899622_1.6.2.3.1 testdef=None
204 20:00:09.480922 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 20:00:09.481009 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 20:00:09.481456 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 20:00:09.481772 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 20:00:09.482333 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 20:00:09.482559 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 20:00:09.483094 runner path: /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/0/tests/0_timesync-off test_uuid 11899622_1.6.2.3.1
213 20:00:09.483251 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 20:00:09.483472 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 20:00:09.483543 Using /lava-11899622 at stage 0
217 20:00:09.483638 Fetching tests from https://github.com/kernelci/test-definitions.git
218 20:00:09.483714 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/0/tests/1_kselftest-alsa'
219 20:00:11.935009 Running '/usr/bin/git checkout kernelci.org
220 20:00:12.082538 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 20:00:12.083270 uuid=11899622_1.6.2.3.5 testdef=None
222 20:00:12.083425 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 20:00:12.083685 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 20:00:12.084478 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 20:00:12.084712 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 20:00:12.085663 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 20:00:12.085891 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 20:00:12.086803 runner path: /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/0/tests/1_kselftest-alsa test_uuid 11899622_1.6.2.3.5
232 20:00:12.086897 BOARD='mt8192-asurada-spherion-r0'
233 20:00:12.086962 BRANCH='cip-gitlab'
234 20:00:12.087024 SKIPFILE='/dev/null'
235 20:00:12.087081 SKIP_INSTALL='True'
236 20:00:12.087135 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 20:00:12.087193 TST_CASENAME=''
238 20:00:12.087247 TST_CMDFILES='alsa'
239 20:00:12.087387 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 20:00:12.087589 Creating lava-test-runner.conf files
242 20:00:12.087652 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899622/lava-overlay-h17ueial/lava-11899622/0 for stage 0
243 20:00:12.087766 - 0_timesync-off
244 20:00:12.087846 - 1_kselftest-alsa
245 20:00:12.087940 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 20:00:12.088028 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 20:00:19.554210 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 20:00:19.554398 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 20:00:19.554489 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 20:00:19.554587 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 20:00:19.554676 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 20:00:19.722379 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 20:00:19.722769 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 20:00:19.722890 extracting modules file /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899622/extract-nfsrootfs-dl4xqeyi
255 20:00:19.947010 extracting modules file /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899622/extract-overlay-ramdisk-ki6rf1bc/ramdisk
256 20:00:20.181646 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 20:00:20.181816 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 20:00:20.181911 [common] Applying overlay to NFS
259 20:00:20.181985 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899622/compress-overlay-syrly5m9/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11899622/extract-nfsrootfs-dl4xqeyi
260 20:00:21.091281 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 20:00:21.091449 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 20:00:21.091544 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 20:00:21.091638 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 20:00:21.091804 Building ramdisk /var/lib/lava/dispatcher/tmp/11899622/extract-overlay-ramdisk-ki6rf1bc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11899622/extract-overlay-ramdisk-ki6rf1bc/ramdisk
265 20:00:21.442244 >> 130498 blocks
266 20:00:23.461120 rename /var/lib/lava/dispatcher/tmp/11899622/extract-overlay-ramdisk-ki6rf1bc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/ramdisk/ramdisk.cpio.gz
267 20:00:23.461568 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 20:00:23.461687 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 20:00:23.461788 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 20:00:23.461899 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/kernel/Image'
271 20:00:35.284444 Returned 0 in 11 seconds
272 20:00:35.385426 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/kernel/image.itb
273 20:00:35.800351 output: FIT description: Kernel Image image with one or more FDT blobs
274 20:00:35.800740 output: Created: Sat Oct 28 21:00:35 2023
275 20:00:35.800814 output: Image 0 (kernel-1)
276 20:00:35.800879 output: Description:
277 20:00:35.800961 output: Created: Sat Oct 28 21:00:35 2023
278 20:00:35.801036 output: Type: Kernel Image
279 20:00:35.801096 output: Compression: lzma compressed
280 20:00:35.801157 output: Data Size: 11047522 Bytes = 10788.60 KiB = 10.54 MiB
281 20:00:35.801217 output: Architecture: AArch64
282 20:00:35.801276 output: OS: Linux
283 20:00:35.801333 output: Load Address: 0x00000000
284 20:00:35.801389 output: Entry Point: 0x00000000
285 20:00:35.801445 output: Hash algo: crc32
286 20:00:35.801502 output: Hash value: da40eda2
287 20:00:35.801559 output: Image 1 (fdt-1)
288 20:00:35.801615 output: Description: mt8192-asurada-spherion-r0
289 20:00:35.801668 output: Created: Sat Oct 28 21:00:35 2023
290 20:00:35.801721 output: Type: Flat Device Tree
291 20:00:35.801774 output: Compression: uncompressed
292 20:00:35.801826 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 20:00:35.801879 output: Architecture: AArch64
294 20:00:35.801931 output: Hash algo: crc32
295 20:00:35.801983 output: Hash value: cc4352de
296 20:00:35.802035 output: Image 2 (ramdisk-1)
297 20:00:35.802087 output: Description: unavailable
298 20:00:35.802139 output: Created: Sat Oct 28 21:00:35 2023
299 20:00:35.802192 output: Type: RAMDisk Image
300 20:00:35.802244 output: Compression: Unknown Compression
301 20:00:35.802296 output: Data Size: 18761246 Bytes = 18321.53 KiB = 17.89 MiB
302 20:00:35.802348 output: Architecture: AArch64
303 20:00:35.802400 output: OS: Linux
304 20:00:35.802452 output: Load Address: unavailable
305 20:00:35.802504 output: Entry Point: unavailable
306 20:00:35.802555 output: Hash algo: crc32
307 20:00:35.802607 output: Hash value: 1c11bebd
308 20:00:35.802659 output: Default Configuration: 'conf-1'
309 20:00:35.802711 output: Configuration 0 (conf-1)
310 20:00:35.802762 output: Description: mt8192-asurada-spherion-r0
311 20:00:35.802814 output: Kernel: kernel-1
312 20:00:35.802866 output: Init Ramdisk: ramdisk-1
313 20:00:35.802953 output: FDT: fdt-1
314 20:00:35.803033 output: Loadables: kernel-1
315 20:00:35.803132 output:
316 20:00:35.803344 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 20:00:35.803443 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 20:00:35.803547 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 20:00:35.803642 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 20:00:35.803748 No LXC device requested
321 20:00:35.803857 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 20:00:35.803943 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 20:00:35.804021 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 20:00:35.804094 Checking files for TFTP limit of 4294967296 bytes.
325 20:00:35.804594 end: 1 tftp-deploy (duration 00:00:39) [common]
326 20:00:35.804698 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 20:00:35.804792 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 20:00:35.804932 substitutions:
329 20:00:35.805047 - {DTB}: 11899622/tftp-deploy-rghlf70a/dtb/mt8192-asurada-spherion-r0.dtb
330 20:00:35.805142 - {INITRD}: 11899622/tftp-deploy-rghlf70a/ramdisk/ramdisk.cpio.gz
331 20:00:35.805201 - {KERNEL}: 11899622/tftp-deploy-rghlf70a/kernel/Image
332 20:00:35.805260 - {LAVA_MAC}: None
333 20:00:35.805317 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11899622/extract-nfsrootfs-dl4xqeyi
334 20:00:35.805374 - {NFS_SERVER_IP}: 192.168.201.1
335 20:00:35.805429 - {PRESEED_CONFIG}: None
336 20:00:35.805484 - {PRESEED_LOCAL}: None
337 20:00:35.805537 - {RAMDISK}: 11899622/tftp-deploy-rghlf70a/ramdisk/ramdisk.cpio.gz
338 20:00:35.805592 - {ROOT_PART}: None
339 20:00:35.805645 - {ROOT}: None
340 20:00:35.805698 - {SERVER_IP}: 192.168.201.1
341 20:00:35.805752 - {TEE}: None
342 20:00:35.805807 Parsed boot commands:
343 20:00:35.805860 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 20:00:35.806048 Parsed boot commands: tftpboot 192.168.201.1 11899622/tftp-deploy-rghlf70a/kernel/image.itb 11899622/tftp-deploy-rghlf70a/kernel/cmdline
345 20:00:35.806140 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 20:00:35.806225 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 20:00:35.806320 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 20:00:35.806407 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 20:00:35.806478 Not connected, no need to disconnect.
350 20:00:35.806552 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 20:00:35.806632 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 20:00:35.806700 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 20:00:35.810830 Setting prompt string to ['lava-test: # ']
354 20:00:35.811194 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 20:00:35.811302 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 20:00:35.811399 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 20:00:35.811531 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 20:00:35.811737 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 20:00:40.961100 >> Command sent successfully.
360 20:00:40.967432 Returned 0 in 5 seconds
361 20:00:41.068220 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 20:00:41.069788 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 20:00:41.070381 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 20:00:41.070899 Setting prompt string to 'Starting depthcharge on Spherion...'
366 20:00:41.071318 Changing prompt to 'Starting depthcharge on Spherion...'
367 20:00:41.071777 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 20:00:41.073118 [Enter `^Ec?' for help]
369 20:00:41.237494
370 20:00:41.238037
371 20:00:41.238401 F0: 102B 0000
372 20:00:41.238757
373 20:00:41.239072 F3: 1001 0000 [0200]
374 20:00:41.239375
375 20:00:41.241498 F3: 1001 0000
376 20:00:41.241928
377 20:00:41.242269 F7: 102D 0000
378 20:00:41.242589
379 20:00:41.244950 F1: 0000 0000
380 20:00:41.245525
381 20:00:41.245926 V0: 0000 0000 [0001]
382 20:00:41.246257
383 20:00:41.246573 00: 0007 8000
384 20:00:41.246902
385 20:00:41.248722 01: 0000 0000
386 20:00:41.249265
387 20:00:41.249617 BP: 0C00 0209 [0000]
388 20:00:41.249981
389 20:00:41.252405 G0: 1182 0000
390 20:00:41.252948
391 20:00:41.253297 EC: 0000 0021 [4000]
392 20:00:41.253621
393 20:00:41.256424 S7: 0000 0000 [0000]
394 20:00:41.256851
395 20:00:41.257192 CC: 0000 0000 [0001]
396 20:00:41.257514
397 20:00:41.259960 T0: 0000 0040 [010F]
398 20:00:41.260394
399 20:00:41.260738 Jump to BL
400 20:00:41.261064
401 20:00:41.284377
402 20:00:41.284910
403 20:00:41.285256
404 20:00:41.291103 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 20:00:41.295491 ARM64: Exception handlers installed.
406 20:00:41.298572 ARM64: Testing exception
407 20:00:41.302471 ARM64: Done test exception
408 20:00:41.309641 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 20:00:41.320164 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 20:00:41.327485 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 20:00:41.337343 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 20:00:41.344500 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 20:00:41.350856 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 20:00:41.361121 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 20:00:41.368619 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 20:00:41.387611 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 20:00:41.391356 WDT: Last reset was cold boot
418 20:00:41.394049 SPI1(PAD0) initialized at 2873684 Hz
419 20:00:41.398006 SPI5(PAD0) initialized at 992727 Hz
420 20:00:41.401054 VBOOT: Loading verstage.
421 20:00:41.407357 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 20:00:41.411151 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 20:00:41.414387 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 20:00:41.417865 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 20:00:41.425251 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 20:00:41.431470 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 20:00:41.442973 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 20:00:41.443584
429 20:00:41.444024
430 20:00:41.452686 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 20:00:41.456125 ARM64: Exception handlers installed.
432 20:00:41.459138 ARM64: Testing exception
433 20:00:41.462071 ARM64: Done test exception
434 20:00:41.465733 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 20:00:41.469230 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 20:00:41.483516 Probing TPM: . done!
437 20:00:41.484125 TPM ready after 0 ms
438 20:00:41.490998 Connected to device vid:did:rid of 1ae0:0028:00
439 20:00:41.500165 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 20:00:41.538488 Initialized TPM device CR50 revision 0
441 20:00:41.550935 tlcl_send_startup: Startup return code is 0
442 20:00:41.551507 TPM: setup succeeded
443 20:00:41.561984 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 20:00:41.570709 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 20:00:41.577499 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 20:00:41.588941 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 20:00:41.592446 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 20:00:41.595628 in-header: 03 07 00 00 08 00 00 00
449 20:00:41.599245 in-data: aa e4 47 04 13 02 00 00
450 20:00:41.602505 Chrome EC: UHEPI supported
451 20:00:41.609417 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 20:00:41.612415 in-header: 03 ad 00 00 08 00 00 00
453 20:00:41.615531 in-data: 00 20 20 08 00 00 00 00
454 20:00:41.615649 Phase 1
455 20:00:41.618735 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 20:00:41.625404 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 20:00:41.633284 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 20:00:41.635222 Recovery requested (1009000e)
459 20:00:41.639130 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 20:00:41.647885 tlcl_extend: response is 0
461 20:00:41.656405 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 20:00:41.661630 tlcl_extend: response is 0
463 20:00:41.667797 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 20:00:41.688506 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 20:00:41.695090 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 20:00:41.695200
467 20:00:41.695270
468 20:00:41.705763 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 20:00:41.709045 ARM64: Exception handlers installed.
470 20:00:41.709136 ARM64: Testing exception
471 20:00:41.712316 ARM64: Done test exception
472 20:00:41.734273 pmic_efuse_setting: Set efuses in 11 msecs
473 20:00:41.738498 pmwrap_interface_init: Select PMIF_VLD_RDY
474 20:00:41.745627 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 20:00:41.748366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 20:00:41.752390 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 20:00:41.758580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 20:00:41.762120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 20:00:41.769333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 20:00:41.772578 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 20:00:41.775616 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 20:00:41.782943 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 20:00:41.786312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 20:00:41.792254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 20:00:41.795510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 20:00:41.799188 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 20:00:41.805872 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 20:00:41.812048 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 20:00:41.818639 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 20:00:41.822132 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 20:00:41.828838 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 20:00:41.835350 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 20:00:41.841856 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 20:00:41.845112 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 20:00:41.852630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 20:00:41.856310 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 20:00:41.863739 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 20:00:41.866876 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 20:00:41.873934 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 20:00:41.877185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 20:00:41.884133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 20:00:41.887441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 20:00:41.894502 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 20:00:41.897903 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 20:00:41.901410 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 20:00:41.908161 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 20:00:41.911581 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 20:00:41.918518 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 20:00:41.922495 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 20:00:41.928899 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 20:00:41.931700 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 20:00:41.939205 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 20:00:41.942817 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 20:00:41.946282 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 20:00:41.950181 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 20:00:41.953536 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 20:00:41.961178 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 20:00:41.963864 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 20:00:41.967158 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 20:00:41.973446 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 20:00:41.976843 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 20:00:41.980810 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 20:00:41.983656 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 20:00:41.990688 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 20:00:41.996701 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 20:00:42.006745 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 20:00:42.010700 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 20:00:42.017190 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 20:00:42.026971 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 20:00:42.030142 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 20:00:42.036492 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 20:00:42.039876 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 20:00:42.046784 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2a
534 20:00:42.053010 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 20:00:42.056512 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 20:00:42.063230 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 20:00:42.071085 [RTC]rtc_get_frequency_meter,154: input=15, output=834
538 20:00:42.081347 [RTC]rtc_get_frequency_meter,154: input=7, output=708
539 20:00:42.090519 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 20:00:42.100154 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 20:00:42.109697 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 20:00:42.118749 [RTC]rtc_get_frequency_meter,154: input=12, output=788
543 20:00:42.129335 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 20:00:42.131655 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 20:00:42.139549 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 20:00:42.142409 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 20:00:42.145784 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 20:00:42.152435 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 20:00:42.155646 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 20:00:42.159396 ADC[4]: Raw value=905988 ID=7
551 20:00:42.160008 ADC[3]: Raw value=213282 ID=1
552 20:00:42.163540 RAM Code: 0x71
553 20:00:42.165861 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 20:00:42.172663 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 20:00:42.179192 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 20:00:42.186264 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 20:00:42.188954 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 20:00:42.192479 in-header: 03 07 00 00 08 00 00 00
559 20:00:42.195435 in-data: aa e4 47 04 13 02 00 00
560 20:00:42.199450 Chrome EC: UHEPI supported
561 20:00:42.205690 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 20:00:42.209311 in-header: 03 dd 00 00 08 00 00 00
563 20:00:42.212400 in-data: 90 20 60 08 00 00 00 00
564 20:00:42.215826 MRC: failed to locate region type 0.
565 20:00:42.222449 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 20:00:42.225486 DRAM-K: Running full calibration
567 20:00:42.231934 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 20:00:42.232404 header.status = 0x0
569 20:00:42.235413 header.version = 0x6 (expected: 0x6)
570 20:00:42.238754 header.size = 0xd00 (expected: 0xd00)
571 20:00:42.242106 header.flags = 0x0
572 20:00:42.248719 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 20:00:42.266164 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 20:00:42.273343 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 20:00:42.275311 dram_init: ddr_geometry: 2
576 20:00:42.278941 [EMI] MDL number = 2
577 20:00:42.279415 [EMI] Get MDL freq = 0
578 20:00:42.282590 dram_init: ddr_type: 0
579 20:00:42.283055 is_discrete_lpddr4: 1
580 20:00:42.285744 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 20:00:42.286385
582 20:00:42.286763
583 20:00:42.288660 [Bian_co] ETT version 0.0.0.1
584 20:00:42.295362 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 20:00:42.295839
586 20:00:42.298842 dramc_set_vcore_voltage set vcore to 650000
587 20:00:42.299261 Read voltage for 800, 4
588 20:00:42.302215 Vio18 = 0
589 20:00:42.302770 Vcore = 650000
590 20:00:42.303155 Vdram = 0
591 20:00:42.305641 Vddq = 0
592 20:00:42.306162 Vmddr = 0
593 20:00:42.309066 dram_init: config_dvfs: 1
594 20:00:42.312275 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 20:00:42.318643 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 20:00:42.321938 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 20:00:42.326423 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 20:00:42.328879 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 20:00:42.332289 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 20:00:42.335165 MEM_TYPE=3, freq_sel=18
601 20:00:42.338610 sv_algorithm_assistance_LP4_1600
602 20:00:42.342111 ============ PULL DRAM RESETB DOWN ============
603 20:00:42.345241 ========== PULL DRAM RESETB DOWN end =========
604 20:00:42.351965 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 20:00:42.355605 ===================================
606 20:00:42.359355 LPDDR4 DRAM CONFIGURATION
607 20:00:42.362410 ===================================
608 20:00:42.362938 EX_ROW_EN[0] = 0x0
609 20:00:42.365331 EX_ROW_EN[1] = 0x0
610 20:00:42.365756 LP4Y_EN = 0x0
611 20:00:42.368988 WORK_FSP = 0x0
612 20:00:42.369514 WL = 0x2
613 20:00:42.371943 RL = 0x2
614 20:00:42.372466 BL = 0x2
615 20:00:42.375927 RPST = 0x0
616 20:00:42.376447 RD_PRE = 0x0
617 20:00:42.378751 WR_PRE = 0x1
618 20:00:42.379200 WR_PST = 0x0
619 20:00:42.382495 DBI_WR = 0x0
620 20:00:42.383046 DBI_RD = 0x0
621 20:00:42.385922 OTF = 0x1
622 20:00:42.389838 ===================================
623 20:00:42.391921 ===================================
624 20:00:42.392344 ANA top config
625 20:00:42.395066 ===================================
626 20:00:42.398466 DLL_ASYNC_EN = 0
627 20:00:42.401609 ALL_SLAVE_EN = 1
628 20:00:42.405081 NEW_RANK_MODE = 1
629 20:00:42.408357 DLL_IDLE_MODE = 1
630 20:00:42.408780 LP45_APHY_COMB_EN = 1
631 20:00:42.411545 TX_ODT_DIS = 1
632 20:00:42.414932 NEW_8X_MODE = 1
633 20:00:42.418431 ===================================
634 20:00:42.422100 ===================================
635 20:00:42.425293 data_rate = 1600
636 20:00:42.427992 CKR = 1
637 20:00:42.428416 DQ_P2S_RATIO = 8
638 20:00:42.431814 ===================================
639 20:00:42.434986 CA_P2S_RATIO = 8
640 20:00:42.438304 DQ_CA_OPEN = 0
641 20:00:42.442025 DQ_SEMI_OPEN = 0
642 20:00:42.445158 CA_SEMI_OPEN = 0
643 20:00:42.448729 CA_FULL_RATE = 0
644 20:00:42.449287 DQ_CKDIV4_EN = 1
645 20:00:42.451789 CA_CKDIV4_EN = 1
646 20:00:42.454897 CA_PREDIV_EN = 0
647 20:00:42.458306 PH8_DLY = 0
648 20:00:42.461553 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 20:00:42.465199 DQ_AAMCK_DIV = 4
650 20:00:42.465724 CA_AAMCK_DIV = 4
651 20:00:42.468386 CA_ADMCK_DIV = 4
652 20:00:42.472258 DQ_TRACK_CA_EN = 0
653 20:00:42.474692 CA_PICK = 800
654 20:00:42.477783 CA_MCKIO = 800
655 20:00:42.481559 MCKIO_SEMI = 0
656 20:00:42.484854 PLL_FREQ = 3068
657 20:00:42.485379 DQ_UI_PI_RATIO = 32
658 20:00:42.488147 CA_UI_PI_RATIO = 0
659 20:00:42.491365 ===================================
660 20:00:42.494512 ===================================
661 20:00:42.498064 memory_type:LPDDR4
662 20:00:42.501208 GP_NUM : 10
663 20:00:42.501741 SRAM_EN : 1
664 20:00:42.504294 MD32_EN : 0
665 20:00:42.507960 ===================================
666 20:00:42.511012 [ANA_INIT] >>>>>>>>>>>>>>
667 20:00:42.511583 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 20:00:42.514220 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 20:00:42.517715 ===================================
670 20:00:42.521607 data_rate = 1600,PCW = 0X7600
671 20:00:42.524465 ===================================
672 20:00:42.528075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 20:00:42.534777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 20:00:42.541865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 20:00:42.544249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 20:00:42.547993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 20:00:42.551067 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 20:00:42.554306 [ANA_INIT] flow start
679 20:00:42.554879 [ANA_INIT] PLL >>>>>>>>
680 20:00:42.557794 [ANA_INIT] PLL <<<<<<<<
681 20:00:42.561487 [ANA_INIT] MIDPI >>>>>>>>
682 20:00:42.562110 [ANA_INIT] MIDPI <<<<<<<<
683 20:00:42.564195 [ANA_INIT] DLL >>>>>>>>
684 20:00:42.567922 [ANA_INIT] flow end
685 20:00:42.570966 ============ LP4 DIFF to SE enter ============
686 20:00:42.574941 ============ LP4 DIFF to SE exit ============
687 20:00:42.577294 [ANA_INIT] <<<<<<<<<<<<<
688 20:00:42.580957 [Flow] Enable top DCM control >>>>>
689 20:00:42.584318 [Flow] Enable top DCM control <<<<<
690 20:00:42.587633 Enable DLL master slave shuffle
691 20:00:42.590754 ==============================================================
692 20:00:42.594273 Gating Mode config
693 20:00:42.600428 ==============================================================
694 20:00:42.600996 Config description:
695 20:00:42.611189 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 20:00:42.617219 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 20:00:42.624213 SELPH_MODE 0: By rank 1: By Phase
698 20:00:42.627333 ==============================================================
699 20:00:42.630538 GAT_TRACK_EN = 1
700 20:00:42.633485 RX_GATING_MODE = 2
701 20:00:42.636961 RX_GATING_TRACK_MODE = 2
702 20:00:42.640588 SELPH_MODE = 1
703 20:00:42.643718 PICG_EARLY_EN = 1
704 20:00:42.647241 VALID_LAT_VALUE = 1
705 20:00:42.650403 ==============================================================
706 20:00:42.653888 Enter into Gating configuration >>>>
707 20:00:42.657473 Exit from Gating configuration <<<<
708 20:00:42.660681 Enter into DVFS_PRE_config >>>>>
709 20:00:42.674008 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 20:00:42.676687 Exit from DVFS_PRE_config <<<<<
711 20:00:42.679845 Enter into PICG configuration >>>>
712 20:00:42.683497 Exit from PICG configuration <<<<
713 20:00:42.684135 [RX_INPUT] configuration >>>>>
714 20:00:42.687164 [RX_INPUT] configuration <<<<<
715 20:00:42.693204 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 20:00:42.696806 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 20:00:42.704237 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 20:00:42.711361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 20:00:42.715259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 20:00:42.723657 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 20:00:42.726160 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 20:00:42.729750 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 20:00:42.733037 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 20:00:42.740308 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 20:00:42.744426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 20:00:42.747510 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 20:00:42.751554 ===================================
728 20:00:42.754901 LPDDR4 DRAM CONFIGURATION
729 20:00:42.758679 ===================================
730 20:00:42.759301 EX_ROW_EN[0] = 0x0
731 20:00:42.762039 EX_ROW_EN[1] = 0x0
732 20:00:42.762623 LP4Y_EN = 0x0
733 20:00:42.765402 WORK_FSP = 0x0
734 20:00:42.765962 WL = 0x2
735 20:00:42.769419 RL = 0x2
736 20:00:42.770012 BL = 0x2
737 20:00:42.772695 RPST = 0x0
738 20:00:42.773328 RD_PRE = 0x0
739 20:00:42.773720 WR_PRE = 0x1
740 20:00:42.776666 WR_PST = 0x0
741 20:00:42.777189 DBI_WR = 0x0
742 20:00:42.780531 DBI_RD = 0x0
743 20:00:42.781006 OTF = 0x1
744 20:00:42.784043 ===================================
745 20:00:42.787395 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 20:00:42.791665 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 20:00:42.798527 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 20:00:42.802079 ===================================
749 20:00:42.802673 LPDDR4 DRAM CONFIGURATION
750 20:00:42.805791 ===================================
751 20:00:42.809212 EX_ROW_EN[0] = 0x10
752 20:00:42.809688 EX_ROW_EN[1] = 0x0
753 20:00:42.813029 LP4Y_EN = 0x0
754 20:00:42.813501 WORK_FSP = 0x0
755 20:00:42.817991 WL = 0x2
756 20:00:42.818466 RL = 0x2
757 20:00:42.818845 BL = 0x2
758 20:00:42.820863 RPST = 0x0
759 20:00:42.821420 RD_PRE = 0x0
760 20:00:42.824827 WR_PRE = 0x1
761 20:00:42.825323 WR_PST = 0x0
762 20:00:42.828055 DBI_WR = 0x0
763 20:00:42.828502 DBI_RD = 0x0
764 20:00:42.831827 OTF = 0x1
765 20:00:42.835590 ===================================
766 20:00:42.839186 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 20:00:42.843811 nWR fixed to 40
768 20:00:42.847466 [ModeRegInit_LP4] CH0 RK0
769 20:00:42.848006 [ModeRegInit_LP4] CH0 RK1
770 20:00:42.851219 [ModeRegInit_LP4] CH1 RK0
771 20:00:42.854489 [ModeRegInit_LP4] CH1 RK1
772 20:00:42.855100 match AC timing 13
773 20:00:42.858084 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 20:00:42.861697 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 20:00:42.868013 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 20:00:42.872866 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 20:00:42.878390 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 20:00:42.878919 [EMI DOE] emi_dcm 0
779 20:00:42.881844 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 20:00:42.882421 ==
781 20:00:42.885457 Dram Type= 6, Freq= 0, CH_0, rank 0
782 20:00:42.891960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 20:00:42.892599 ==
784 20:00:42.895208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 20:00:42.901746 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 20:00:42.911816 [CA 0] Center 37 (6~68) winsize 63
787 20:00:42.914898 [CA 1] Center 37 (7~67) winsize 61
788 20:00:42.918081 [CA 2] Center 34 (4~65) winsize 62
789 20:00:42.921670 [CA 3] Center 34 (4~65) winsize 62
790 20:00:42.925015 [CA 4] Center 33 (3~64) winsize 62
791 20:00:42.928813 [CA 5] Center 33 (3~64) winsize 62
792 20:00:42.929376
793 20:00:42.932118 [CmdBusTrainingLP45] Vref(ca) range 1: 28
794 20:00:42.932592
795 20:00:42.934949 [CATrainingPosCal] consider 1 rank data
796 20:00:42.939042 u2DelayCellTimex100 = 270/100 ps
797 20:00:42.941812 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 20:00:42.945196 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
799 20:00:42.951797 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 20:00:42.954809 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 20:00:42.958332 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 20:00:42.962090 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 20:00:42.962670
804 20:00:42.964539 CA PerBit enable=1, Macro0, CA PI delay=33
805 20:00:42.965012
806 20:00:42.967828 [CBTSetCACLKResult] CA Dly = 33
807 20:00:42.968305 CS Dly: 6 (0~37)
808 20:00:42.968688 ==
809 20:00:42.971588 Dram Type= 6, Freq= 0, CH_0, rank 1
810 20:00:42.977922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 20:00:42.978468 ==
812 20:00:42.981946 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 20:00:42.988029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 20:00:42.997704 [CA 0] Center 37 (6~68) winsize 63
815 20:00:43.000786 [CA 1] Center 37 (6~68) winsize 63
816 20:00:43.004623 [CA 2] Center 34 (4~65) winsize 62
817 20:00:43.007555 [CA 3] Center 34 (4~65) winsize 62
818 20:00:43.010550 [CA 4] Center 33 (3~64) winsize 62
819 20:00:43.014503 [CA 5] Center 33 (2~64) winsize 63
820 20:00:43.015068
821 20:00:43.017207 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 20:00:43.017675
823 20:00:43.020931 [CATrainingPosCal] consider 2 rank data
824 20:00:43.024583 u2DelayCellTimex100 = 270/100 ps
825 20:00:43.027986 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
826 20:00:43.031079 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
827 20:00:43.037651 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 20:00:43.041002 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 20:00:43.044334 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 20:00:43.048532 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 20:00:43.049096
832 20:00:43.052198 CA PerBit enable=1, Macro0, CA PI delay=33
833 20:00:43.052682
834 20:00:43.053051 [CBTSetCACLKResult] CA Dly = 33
835 20:00:43.056093 CS Dly: 6 (0~38)
836 20:00:43.056559
837 20:00:43.059607 ----->DramcWriteLeveling(PI) begin...
838 20:00:43.060116 ==
839 20:00:43.063796 Dram Type= 6, Freq= 0, CH_0, rank 0
840 20:00:43.066068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 20:00:43.066626 ==
842 20:00:43.070379 Write leveling (Byte 0): 33 => 33
843 20:00:43.073395 Write leveling (Byte 1): 29 => 29
844 20:00:43.076621 DramcWriteLeveling(PI) end<-----
845 20:00:43.077042
846 20:00:43.077378 ==
847 20:00:43.079657 Dram Type= 6, Freq= 0, CH_0, rank 0
848 20:00:43.083446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 20:00:43.084032 ==
850 20:00:43.087302 [Gating] SW mode calibration
851 20:00:43.093867 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 20:00:43.099536 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 20:00:43.103789 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 20:00:43.106588 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 20:00:43.113129 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 20:00:43.116424 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 20:00:43.119649 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 20:00:43.126326 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 20:00:43.130288 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 20:00:43.133521 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 20:00:43.139671 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 20:00:43.143474 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 20:00:43.146601 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 20:00:43.152827 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 20:00:43.156991 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 20:00:43.159756 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 20:00:43.166117 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 20:00:43.169512 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 20:00:43.172874 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 20:00:43.179344 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
871 20:00:43.183115 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 20:00:43.186289 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 20:00:43.192691 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 20:00:43.196483 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 20:00:43.199220 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 20:00:43.202789 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 20:00:43.209420 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 20:00:43.212740 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 20:00:43.216304 0 9 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
880 20:00:43.222652 0 9 12 | B1->B0 | 2a29 3434 | 1 1 | (0 0) (1 1)
881 20:00:43.226240 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 20:00:43.229241 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 20:00:43.235880 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 20:00:43.239588 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 20:00:43.242859 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 20:00:43.249230 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 20:00:43.252417 0 10 8 | B1->B0 | 3434 2929 | 0 0 | (1 0) (0 0)
888 20:00:43.256146 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
889 20:00:43.262378 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 20:00:43.266183 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 20:00:43.269006 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 20:00:43.275683 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 20:00:43.279031 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 20:00:43.282243 0 11 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
895 20:00:43.289298 0 11 8 | B1->B0 | 2727 3737 | 0 0 | (0 0) (0 0)
896 20:00:43.292514 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
897 20:00:43.295702 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 20:00:43.302230 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 20:00:43.306014 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 20:00:43.309227 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 20:00:43.315626 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 20:00:43.318996 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 20:00:43.322192 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 20:00:43.329125 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 20:00:43.332583 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 20:00:43.335329 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 20:00:43.342200 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 20:00:43.345364 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 20:00:43.348571 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 20:00:43.352169 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 20:00:43.359239 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 20:00:43.361851 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 20:00:43.365272 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 20:00:43.371905 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 20:00:43.375187 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 20:00:43.378269 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 20:00:43.385244 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 20:00:43.388320 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 20:00:43.391985 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 20:00:43.398164 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 20:00:43.401534 Total UI for P1: 0, mck2ui 16
922 20:00:43.405190 best dqsien dly found for B0: ( 0, 14, 6)
923 20:00:43.408207 Total UI for P1: 0, mck2ui 16
924 20:00:43.411426 best dqsien dly found for B1: ( 0, 14, 8)
925 20:00:43.415061 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 20:00:43.418547 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 20:00:43.418966
928 20:00:43.421696 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 20:00:43.424640 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 20:00:43.428643 [Gating] SW calibration Done
931 20:00:43.429186 ==
932 20:00:43.432201 Dram Type= 6, Freq= 0, CH_0, rank 0
933 20:00:43.436759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 20:00:43.437260 ==
935 20:00:43.437603 RX Vref Scan: 0
936 20:00:43.439149
937 20:00:43.439804 RX Vref 0 -> 0, step: 1
938 20:00:43.440163
939 20:00:43.442323 RX Delay -130 -> 252, step: 16
940 20:00:43.445896 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 20:00:43.449250 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 20:00:43.456603 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 20:00:43.459523 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 20:00:43.463306 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 20:00:43.466235 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 20:00:43.470211 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
947 20:00:43.474098 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 20:00:43.477192 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 20:00:43.484260 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 20:00:43.487973 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 20:00:43.491651 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 20:00:43.495294 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
953 20:00:43.499045 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 20:00:43.502778 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 20:00:43.506930 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 20:00:43.507671 ==
957 20:00:43.509943 Dram Type= 6, Freq= 0, CH_0, rank 0
958 20:00:43.513923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 20:00:43.514650 ==
960 20:00:43.516945 DQS Delay:
961 20:00:43.517363 DQS0 = 0, DQS1 = 0
962 20:00:43.517750 DQM Delay:
963 20:00:43.520110 DQM0 = 85, DQM1 = 71
964 20:00:43.520528 DQ Delay:
965 20:00:43.523422 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 20:00:43.526863 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
967 20:00:43.530610 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 20:00:43.533899 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
969 20:00:43.534358
970 20:00:43.534693
971 20:00:43.535006 ==
972 20:00:43.537157 Dram Type= 6, Freq= 0, CH_0, rank 0
973 20:00:43.543594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 20:00:43.544215 ==
975 20:00:43.544623
976 20:00:43.545021
977 20:00:43.545353 TX Vref Scan disable
978 20:00:43.547374 == TX Byte 0 ==
979 20:00:43.550280 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 20:00:43.556963 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 20:00:43.557525 == TX Byte 1 ==
982 20:00:43.560618 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 20:00:43.564115 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 20:00:43.567706 ==
985 20:00:43.568174 Dram Type= 6, Freq= 0, CH_0, rank 0
986 20:00:43.574268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 20:00:43.574840 ==
988 20:00:43.587489 TX Vref=22, minBit 12, minWin=26, winSum=440
989 20:00:43.590984 TX Vref=24, minBit 8, minWin=27, winSum=446
990 20:00:43.594672 TX Vref=26, minBit 8, minWin=27, winSum=448
991 20:00:43.597742 TX Vref=28, minBit 8, minWin=27, winSum=450
992 20:00:43.601042 TX Vref=30, minBit 8, minWin=27, winSum=448
993 20:00:43.604272 TX Vref=32, minBit 7, minWin=27, winSum=446
994 20:00:43.611342 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 28
995 20:00:43.611952
996 20:00:43.614857 Final TX Range 1 Vref 28
997 20:00:43.615426
998 20:00:43.615854 ==
999 20:00:43.618299 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 20:00:43.621115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 20:00:43.621585 ==
1002 20:00:43.622001
1003 20:00:43.622347
1004 20:00:43.624031 TX Vref Scan disable
1005 20:00:43.627435 == TX Byte 0 ==
1006 20:00:43.630779 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 20:00:43.635173 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 20:00:43.638028 == TX Byte 1 ==
1009 20:00:43.640723 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 20:00:43.645109 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 20:00:43.645676
1012 20:00:43.646052 [DATLAT]
1013 20:00:43.649114 Freq=800, CH0 RK0
1014 20:00:43.649677
1015 20:00:43.651268 DATLAT Default: 0xa
1016 20:00:43.651755 0, 0xFFFF, sum = 0
1017 20:00:43.654117 1, 0xFFFF, sum = 0
1018 20:00:43.654704 2, 0xFFFF, sum = 0
1019 20:00:43.657203 3, 0xFFFF, sum = 0
1020 20:00:43.657672 4, 0xFFFF, sum = 0
1021 20:00:43.660398 5, 0xFFFF, sum = 0
1022 20:00:43.660865 6, 0xFFFF, sum = 0
1023 20:00:43.664307 7, 0xFFFF, sum = 0
1024 20:00:43.664881 8, 0xFFFF, sum = 0
1025 20:00:43.667271 9, 0x0, sum = 1
1026 20:00:43.667838 10, 0x0, sum = 2
1027 20:00:43.670671 11, 0x0, sum = 3
1028 20:00:43.671228 12, 0x0, sum = 4
1029 20:00:43.674134 best_step = 10
1030 20:00:43.674683
1031 20:00:43.675047 ==
1032 20:00:43.676902 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 20:00:43.680297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 20:00:43.680757 ==
1035 20:00:43.681122 RX Vref Scan: 1
1036 20:00:43.683566
1037 20:00:43.684093 Set Vref Range= 32 -> 127
1038 20:00:43.684492
1039 20:00:43.687223 RX Vref 32 -> 127, step: 1
1040 20:00:43.687827
1041 20:00:43.690838 RX Delay -111 -> 252, step: 8
1042 20:00:43.691391
1043 20:00:43.693821 Set Vref, RX VrefLevel [Byte0]: 32
1044 20:00:43.697364 [Byte1]: 32
1045 20:00:43.697957
1046 20:00:43.700369 Set Vref, RX VrefLevel [Byte0]: 33
1047 20:00:43.703404 [Byte1]: 33
1048 20:00:43.707048
1049 20:00:43.707597 Set Vref, RX VrefLevel [Byte0]: 34
1050 20:00:43.710494 [Byte1]: 34
1051 20:00:43.714719
1052 20:00:43.715267 Set Vref, RX VrefLevel [Byte0]: 35
1053 20:00:43.718238 [Byte1]: 35
1054 20:00:43.722360
1055 20:00:43.722928 Set Vref, RX VrefLevel [Byte0]: 36
1056 20:00:43.725954 [Byte1]: 36
1057 20:00:43.731014
1058 20:00:43.731575 Set Vref, RX VrefLevel [Byte0]: 37
1059 20:00:43.733547 [Byte1]: 37
1060 20:00:43.738433
1061 20:00:43.738983 Set Vref, RX VrefLevel [Byte0]: 38
1062 20:00:43.741200 [Byte1]: 38
1063 20:00:43.745086
1064 20:00:43.745647 Set Vref, RX VrefLevel [Byte0]: 39
1065 20:00:43.748631 [Byte1]: 39
1066 20:00:43.752705
1067 20:00:43.753179 Set Vref, RX VrefLevel [Byte0]: 40
1068 20:00:43.756117 [Byte1]: 40
1069 20:00:43.760440
1070 20:00:43.761018 Set Vref, RX VrefLevel [Byte0]: 41
1071 20:00:43.764218 [Byte1]: 41
1072 20:00:43.768473
1073 20:00:43.769048 Set Vref, RX VrefLevel [Byte0]: 42
1074 20:00:43.771784 [Byte1]: 42
1075 20:00:43.775767
1076 20:00:43.776346 Set Vref, RX VrefLevel [Byte0]: 43
1077 20:00:43.779175 [Byte1]: 43
1078 20:00:43.783576
1079 20:00:43.784192 Set Vref, RX VrefLevel [Byte0]: 44
1080 20:00:43.787194 [Byte1]: 44
1081 20:00:43.791438
1082 20:00:43.792043 Set Vref, RX VrefLevel [Byte0]: 45
1083 20:00:43.794159 [Byte1]: 45
1084 20:00:43.799268
1085 20:00:43.799856 Set Vref, RX VrefLevel [Byte0]: 46
1086 20:00:43.801914 [Byte1]: 46
1087 20:00:43.806479
1088 20:00:43.807049 Set Vref, RX VrefLevel [Byte0]: 47
1089 20:00:43.809694 [Byte1]: 47
1090 20:00:43.814011
1091 20:00:43.814564 Set Vref, RX VrefLevel [Byte0]: 48
1092 20:00:43.817368 [Byte1]: 48
1093 20:00:43.821790
1094 20:00:43.822340 Set Vref, RX VrefLevel [Byte0]: 49
1095 20:00:43.824582 [Byte1]: 49
1096 20:00:43.829717
1097 20:00:43.830265 Set Vref, RX VrefLevel [Byte0]: 50
1098 20:00:43.832904 [Byte1]: 50
1099 20:00:43.836925
1100 20:00:43.837473 Set Vref, RX VrefLevel [Byte0]: 51
1101 20:00:43.841483 [Byte1]: 51
1102 20:00:43.844548
1103 20:00:43.845160 Set Vref, RX VrefLevel [Byte0]: 52
1104 20:00:43.849232 [Byte1]: 52
1105 20:00:43.852296
1106 20:00:43.852756 Set Vref, RX VrefLevel [Byte0]: 53
1107 20:00:43.855917 [Byte1]: 53
1108 20:00:43.860164
1109 20:00:43.860714 Set Vref, RX VrefLevel [Byte0]: 54
1110 20:00:43.863145 [Byte1]: 54
1111 20:00:43.867520
1112 20:00:43.868133 Set Vref, RX VrefLevel [Byte0]: 55
1113 20:00:43.870719 [Byte1]: 55
1114 20:00:43.875065
1115 20:00:43.875614 Set Vref, RX VrefLevel [Byte0]: 56
1116 20:00:43.878436 [Byte1]: 56
1117 20:00:43.883448
1118 20:00:43.884079 Set Vref, RX VrefLevel [Byte0]: 57
1119 20:00:43.885888 [Byte1]: 57
1120 20:00:43.890392
1121 20:00:43.890944 Set Vref, RX VrefLevel [Byte0]: 58
1122 20:00:43.893714 [Byte1]: 58
1123 20:00:43.898089
1124 20:00:43.898642 Set Vref, RX VrefLevel [Byte0]: 59
1125 20:00:43.901175 [Byte1]: 59
1126 20:00:43.906925
1127 20:00:43.907465 Set Vref, RX VrefLevel [Byte0]: 60
1128 20:00:43.909506 [Byte1]: 60
1129 20:00:43.913969
1130 20:00:43.914522 Set Vref, RX VrefLevel [Byte0]: 61
1131 20:00:43.916577 [Byte1]: 61
1132 20:00:43.922318
1133 20:00:43.922927 Set Vref, RX VrefLevel [Byte0]: 62
1134 20:00:43.923872 [Byte1]: 62
1135 20:00:43.929212
1136 20:00:43.929771 Set Vref, RX VrefLevel [Byte0]: 63
1137 20:00:43.931766 [Byte1]: 63
1138 20:00:43.936337
1139 20:00:43.936894 Set Vref, RX VrefLevel [Byte0]: 64
1140 20:00:43.939595 [Byte1]: 64
1141 20:00:43.944714
1142 20:00:43.945282 Set Vref, RX VrefLevel [Byte0]: 65
1143 20:00:43.947298 [Byte1]: 65
1144 20:00:43.951502
1145 20:00:43.952125 Set Vref, RX VrefLevel [Byte0]: 66
1146 20:00:43.955183 [Byte1]: 66
1147 20:00:43.959542
1148 20:00:43.960169 Set Vref, RX VrefLevel [Byte0]: 67
1149 20:00:43.963507 [Byte1]: 67
1150 20:00:43.967205
1151 20:00:43.967796 Set Vref, RX VrefLevel [Byte0]: 68
1152 20:00:43.970819 [Byte1]: 68
1153 20:00:43.975076
1154 20:00:43.975649 Set Vref, RX VrefLevel [Byte0]: 69
1155 20:00:43.978286 [Byte1]: 69
1156 20:00:43.982331
1157 20:00:43.982785 Set Vref, RX VrefLevel [Byte0]: 70
1158 20:00:43.985484 [Byte1]: 70
1159 20:00:43.990080
1160 20:00:43.990534 Set Vref, RX VrefLevel [Byte0]: 71
1161 20:00:43.993151 [Byte1]: 71
1162 20:00:43.997824
1163 20:00:43.998440 Set Vref, RX VrefLevel [Byte0]: 72
1164 20:00:44.001038 [Byte1]: 72
1165 20:00:44.005469
1166 20:00:44.005985 Set Vref, RX VrefLevel [Byte0]: 73
1167 20:00:44.008857 [Byte1]: 73
1168 20:00:44.012908
1169 20:00:44.013362 Set Vref, RX VrefLevel [Byte0]: 74
1170 20:00:44.016664 [Byte1]: 74
1171 20:00:44.020646
1172 20:00:44.021194 Set Vref, RX VrefLevel [Byte0]: 75
1173 20:00:44.023671 [Byte1]: 75
1174 20:00:44.028110
1175 20:00:44.028655 Set Vref, RX VrefLevel [Byte0]: 76
1176 20:00:44.031542 [Byte1]: 76
1177 20:00:44.035698
1178 20:00:44.036226 Set Vref, RX VrefLevel [Byte0]: 77
1179 20:00:44.039484 [Byte1]: 77
1180 20:00:44.044384
1181 20:00:44.044877 Set Vref, RX VrefLevel [Byte0]: 78
1182 20:00:44.047635 [Byte1]: 78
1183 20:00:44.051430
1184 20:00:44.052068 Set Vref, RX VrefLevel [Byte0]: 79
1185 20:00:44.055092 [Byte1]: 79
1186 20:00:44.059345
1187 20:00:44.059983 Set Vref, RX VrefLevel [Byte0]: 80
1188 20:00:44.062931 [Byte1]: 80
1189 20:00:44.066691
1190 20:00:44.067349 Final RX Vref Byte 0 = 61 to rank0
1191 20:00:44.070131 Final RX Vref Byte 1 = 51 to rank0
1192 20:00:44.074284 Final RX Vref Byte 0 = 61 to rank1
1193 20:00:44.077407 Final RX Vref Byte 1 = 51 to rank1==
1194 20:00:44.080786 Dram Type= 6, Freq= 0, CH_0, rank 0
1195 20:00:44.085265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 20:00:44.085727 ==
1197 20:00:44.086092 DQS Delay:
1198 20:00:44.088288 DQS0 = 0, DQS1 = 0
1199 20:00:44.088906 DQM Delay:
1200 20:00:44.091602 DQM0 = 86, DQM1 = 76
1201 20:00:44.092138 DQ Delay:
1202 20:00:44.095399 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1203 20:00:44.098615 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1204 20:00:44.102523 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1205 20:00:44.106151 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1206 20:00:44.106615
1207 20:00:44.107036
1208 20:00:44.113285 [DQSOSCAuto] RK0, (LSB)MR18= 0x4729, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1209 20:00:44.117844 CH0 RK0: MR19=606, MR18=4729
1210 20:00:44.121212 CH0_RK0: MR19=0x606, MR18=0x4729, DQSOSC=392, MR23=63, INC=96, DEC=64
1211 20:00:44.121674
1212 20:00:44.123864 ----->DramcWriteLeveling(PI) begin...
1213 20:00:44.124332 ==
1214 20:00:44.127509 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 20:00:44.131271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1216 20:00:44.134822 ==
1217 20:00:44.135248 Write leveling (Byte 0): 32 => 32
1218 20:00:44.140152 Write leveling (Byte 1): 28 => 28
1219 20:00:44.142629 DramcWriteLeveling(PI) end<-----
1220 20:00:44.143227
1221 20:00:44.143822 ==
1222 20:00:44.145990 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 20:00:44.149782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 20:00:44.150497 ==
1225 20:00:44.153938 [Gating] SW mode calibration
1226 20:00:44.201313 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1227 20:00:44.202248 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1228 20:00:44.202645 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1229 20:00:44.202996 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1230 20:00:44.203333 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1231 20:00:44.203763 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 20:00:44.204112 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 20:00:44.204431 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 20:00:44.204934 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 20:00:44.205479 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 20:00:44.245301 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 20:00:44.245923 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 20:00:44.246462 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 20:00:44.247307 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 20:00:44.247719 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 20:00:44.248234 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 20:00:44.248687 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 20:00:44.249132 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 20:00:44.249568 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 20:00:44.250204 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 20:00:44.289362 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1247 20:00:44.290323 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 20:00:44.290754 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 20:00:44.291228 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 20:00:44.291818 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 20:00:44.292261 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 20:00:44.292710 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 20:00:44.293155 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 20:00:44.293591 0 9 8 | B1->B0 | 2424 2e2d | 0 1 | (0 0) (1 1)
1255 20:00:44.294129 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1256 20:00:44.295316 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 20:00:44.299529 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 20:00:44.302467 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 20:00:44.305992 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 20:00:44.310031 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 20:00:44.313440 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
1262 20:00:44.320151 0 10 8 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (1 0)
1263 20:00:44.323919 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1264 20:00:44.327630 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 20:00:44.331567 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 20:00:44.338661 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 20:00:44.342327 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 20:00:44.346529 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 20:00:44.349601 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1270 20:00:44.353686 0 11 8 | B1->B0 | 2c2c 3d3d | 0 0 | (0 0) (1 1)
1271 20:00:44.357084 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1272 20:00:44.364556 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 20:00:44.368083 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 20:00:44.371541 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 20:00:44.375226 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 20:00:44.382231 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 20:00:44.387105 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1278 20:00:44.390027 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1279 20:00:44.393213 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 20:00:44.397521 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 20:00:44.404247 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 20:00:44.407417 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 20:00:44.411344 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 20:00:44.414667 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 20:00:44.418691 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 20:00:44.425793 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 20:00:44.429394 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 20:00:44.432732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 20:00:44.439295 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 20:00:44.442381 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 20:00:44.446021 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 20:00:44.449740 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 20:00:44.455938 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 20:00:44.459434 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1295 20:00:44.462481 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1296 20:00:44.465954 Total UI for P1: 0, mck2ui 16
1297 20:00:44.469048 best dqsien dly found for B0: ( 0, 14, 8)
1298 20:00:44.475605 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1299 20:00:44.478971 Total UI for P1: 0, mck2ui 16
1300 20:00:44.482448 best dqsien dly found for B1: ( 0, 14, 10)
1301 20:00:44.485983 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1302 20:00:44.489443 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1303 20:00:44.489996
1304 20:00:44.492882 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1305 20:00:44.495593 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1306 20:00:44.498719 [Gating] SW calibration Done
1307 20:00:44.499269 ==
1308 20:00:44.502649 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 20:00:44.505384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 20:00:44.505845 ==
1311 20:00:44.508701 RX Vref Scan: 0
1312 20:00:44.509220
1313 20:00:44.509585 RX Vref 0 -> 0, step: 1
1314 20:00:44.512248
1315 20:00:44.512708 RX Delay -130 -> 252, step: 16
1316 20:00:44.518989 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1317 20:00:44.522120 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1318 20:00:44.525128 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1319 20:00:44.528731 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1320 20:00:44.531863 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1321 20:00:44.538816 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1322 20:00:44.542434 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1323 20:00:44.545473 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1324 20:00:44.548946 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1325 20:00:44.552109 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1326 20:00:44.558682 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1327 20:00:44.561737 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1328 20:00:44.565346 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1329 20:00:44.568782 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1330 20:00:44.572346 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1331 20:00:44.578982 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1332 20:00:44.579422 ==
1333 20:00:44.582193 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 20:00:44.585648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 20:00:44.586165 ==
1336 20:00:44.586499 DQS Delay:
1337 20:00:44.588920 DQS0 = 0, DQS1 = 0
1338 20:00:44.589432 DQM Delay:
1339 20:00:44.591947 DQM0 = 83, DQM1 = 77
1340 20:00:44.592379 DQ Delay:
1341 20:00:44.595776 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1342 20:00:44.599171 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1343 20:00:44.602417 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1344 20:00:44.605123 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1345 20:00:44.605538
1346 20:00:44.605870
1347 20:00:44.606176 ==
1348 20:00:44.608938 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 20:00:44.611693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 20:00:44.612150 ==
1351 20:00:44.615903
1352 20:00:44.616406
1353 20:00:44.616745 TX Vref Scan disable
1354 20:00:44.618757 == TX Byte 0 ==
1355 20:00:44.622476 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1356 20:00:44.625713 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1357 20:00:44.628353 == TX Byte 1 ==
1358 20:00:44.631826 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1359 20:00:44.634961 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1360 20:00:44.635376 ==
1361 20:00:44.638014 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 20:00:44.644615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 20:00:44.645031 ==
1364 20:00:44.657235 TX Vref=22, minBit 8, minWin=27, winSum=444
1365 20:00:44.661131 TX Vref=24, minBit 9, minWin=27, winSum=443
1366 20:00:44.663979 TX Vref=26, minBit 9, minWin=27, winSum=446
1367 20:00:44.667482 TX Vref=28, minBit 8, minWin=27, winSum=445
1368 20:00:44.670929 TX Vref=30, minBit 9, minWin=27, winSum=445
1369 20:00:44.674153 TX Vref=32, minBit 9, minWin=27, winSum=448
1370 20:00:44.680649 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 32
1371 20:00:44.681189
1372 20:00:44.683689 Final TX Range 1 Vref 32
1373 20:00:44.684135
1374 20:00:44.684459 ==
1375 20:00:44.687759 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 20:00:44.690631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 20:00:44.691142 ==
1378 20:00:44.693608
1379 20:00:44.694015
1380 20:00:44.694337 TX Vref Scan disable
1381 20:00:44.697887 == TX Byte 0 ==
1382 20:00:44.701052 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1383 20:00:44.704186 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1384 20:00:44.707590 == TX Byte 1 ==
1385 20:00:44.710670 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1386 20:00:44.714090 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1387 20:00:44.717702
1388 20:00:44.718210 [DATLAT]
1389 20:00:44.718537 Freq=800, CH0 RK1
1390 20:00:44.718843
1391 20:00:44.720995 DATLAT Default: 0xa
1392 20:00:44.721506 0, 0xFFFF, sum = 0
1393 20:00:44.724238 1, 0xFFFF, sum = 0
1394 20:00:44.724655 2, 0xFFFF, sum = 0
1395 20:00:44.727532 3, 0xFFFF, sum = 0
1396 20:00:44.731037 4, 0xFFFF, sum = 0
1397 20:00:44.731548 5, 0xFFFF, sum = 0
1398 20:00:44.734120 6, 0xFFFF, sum = 0
1399 20:00:44.734635 7, 0xFFFF, sum = 0
1400 20:00:44.737307 8, 0xFFFF, sum = 0
1401 20:00:44.737724 9, 0x0, sum = 1
1402 20:00:44.738063 10, 0x0, sum = 2
1403 20:00:44.740910 11, 0x0, sum = 3
1404 20:00:44.741426 12, 0x0, sum = 4
1405 20:00:44.743696 best_step = 10
1406 20:00:44.744160
1407 20:00:44.744486 ==
1408 20:00:44.747818 Dram Type= 6, Freq= 0, CH_0, rank 1
1409 20:00:44.751171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 20:00:44.751677 ==
1411 20:00:44.754015 RX Vref Scan: 0
1412 20:00:44.754522
1413 20:00:44.754849 RX Vref 0 -> 0, step: 1
1414 20:00:44.755152
1415 20:00:44.757724 RX Delay -111 -> 252, step: 8
1416 20:00:44.764339 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1417 20:00:44.767628 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1418 20:00:44.771063 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1419 20:00:44.775063 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1420 20:00:44.777509 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1421 20:00:44.783904 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1422 20:00:44.787370 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1423 20:00:44.790784 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1424 20:00:44.794268 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1425 20:00:44.796968 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1426 20:00:44.804540 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1427 20:00:44.807379 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1428 20:00:44.810485 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1429 20:00:44.813901 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1430 20:00:44.820580 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1431 20:00:44.823988 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1432 20:00:44.824489 ==
1433 20:00:44.827463 Dram Type= 6, Freq= 0, CH_0, rank 1
1434 20:00:44.830981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 20:00:44.831489 ==
1436 20:00:44.834242 DQS Delay:
1437 20:00:44.834744 DQS0 = 0, DQS1 = 0
1438 20:00:44.835070 DQM Delay:
1439 20:00:44.837057 DQM0 = 85, DQM1 = 77
1440 20:00:44.837466 DQ Delay:
1441 20:00:44.840671 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =84
1442 20:00:44.844003 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =92
1443 20:00:44.846991 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1444 20:00:44.850890 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1445 20:00:44.851396
1446 20:00:44.851720
1447 20:00:44.860548 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1448 20:00:44.861065 CH0 RK1: MR19=606, MR18=3C02
1449 20:00:44.866979 CH0_RK1: MR19=0x606, MR18=0x3C02, DQSOSC=394, MR23=63, INC=95, DEC=63
1450 20:00:44.870416 [RxdqsGatingPostProcess] freq 800
1451 20:00:44.877409 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1452 20:00:44.880646 Pre-setting of DQS Precalculation
1453 20:00:44.883571 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1454 20:00:44.884032 ==
1455 20:00:44.887700 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 20:00:44.893804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 20:00:44.894344 ==
1458 20:00:44.896782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1459 20:00:44.903107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1460 20:00:44.912682 [CA 0] Center 36 (6~67) winsize 62
1461 20:00:44.915516 [CA 1] Center 36 (6~67) winsize 62
1462 20:00:44.919114 [CA 2] Center 34 (4~65) winsize 62
1463 20:00:44.922777 [CA 3] Center 34 (3~65) winsize 63
1464 20:00:44.925769 [CA 4] Center 34 (4~65) winsize 62
1465 20:00:44.929353 [CA 5] Center 34 (3~65) winsize 63
1466 20:00:44.929856
1467 20:00:44.932555 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1468 20:00:44.933064
1469 20:00:44.935802 [CATrainingPosCal] consider 1 rank data
1470 20:00:44.939357 u2DelayCellTimex100 = 270/100 ps
1471 20:00:44.942759 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 20:00:44.946183 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1473 20:00:44.952986 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 20:00:44.956609 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1475 20:00:44.959236 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 20:00:44.962483 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1477 20:00:44.962993
1478 20:00:44.966042 CA PerBit enable=1, Macro0, CA PI delay=34
1479 20:00:44.966550
1480 20:00:44.969326 [CBTSetCACLKResult] CA Dly = 34
1481 20:00:44.969845 CS Dly: 4 (0~35)
1482 20:00:44.972216 ==
1483 20:00:44.972730 Dram Type= 6, Freq= 0, CH_1, rank 1
1484 20:00:44.979322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 20:00:44.979875 ==
1486 20:00:44.982097 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1487 20:00:44.988976 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1488 20:00:44.998771 [CA 0] Center 36 (6~67) winsize 62
1489 20:00:45.001672 [CA 1] Center 36 (6~67) winsize 62
1490 20:00:45.005147 [CA 2] Center 34 (4~65) winsize 62
1491 20:00:45.008422 [CA 3] Center 34 (3~65) winsize 63
1492 20:00:45.011627 [CA 4] Center 34 (4~65) winsize 62
1493 20:00:45.015049 [CA 5] Center 34 (3~65) winsize 63
1494 20:00:45.015554
1495 20:00:45.018835 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1496 20:00:45.019345
1497 20:00:45.021545 [CATrainingPosCal] consider 2 rank data
1498 20:00:45.025205 u2DelayCellTimex100 = 270/100 ps
1499 20:00:45.028238 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1500 20:00:45.035503 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1501 20:00:45.038357 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1502 20:00:45.041743 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1503 20:00:45.045153 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1504 20:00:45.048614 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1505 20:00:45.049117
1506 20:00:45.051663 CA PerBit enable=1, Macro0, CA PI delay=34
1507 20:00:45.052221
1508 20:00:45.055534 [CBTSetCACLKResult] CA Dly = 34
1509 20:00:45.058153 CS Dly: 5 (0~38)
1510 20:00:45.058690
1511 20:00:45.061767 ----->DramcWriteLeveling(PI) begin...
1512 20:00:45.062280 ==
1513 20:00:45.065368 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 20:00:45.068970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 20:00:45.069481 ==
1516 20:00:45.071496 Write leveling (Byte 0): 25 => 25
1517 20:00:45.075303 Write leveling (Byte 1): 29 => 29
1518 20:00:45.078162 DramcWriteLeveling(PI) end<-----
1519 20:00:45.078569
1520 20:00:45.078893 ==
1521 20:00:45.081367 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 20:00:45.085135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 20:00:45.085553 ==
1524 20:00:45.087717 [Gating] SW mode calibration
1525 20:00:45.094604 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1526 20:00:45.100950 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1527 20:00:45.104668 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1528 20:00:45.108154 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1529 20:00:45.114694 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1530 20:00:45.118143 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 20:00:45.121575 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 20:00:45.127987 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 20:00:45.131496 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 20:00:45.134531 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 20:00:45.141287 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 20:00:45.144469 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 20:00:45.147888 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 20:00:45.154370 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 20:00:45.157727 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 20:00:45.161279 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 20:00:45.164809 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 20:00:45.170904 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 20:00:45.174136 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 20:00:45.177757 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1545 20:00:45.184262 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1546 20:00:45.187992 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 20:00:45.191246 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 20:00:45.197565 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 20:00:45.200599 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 20:00:45.204486 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 20:00:45.210365 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 20:00:45.214329 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1553 20:00:45.217696 0 9 8 | B1->B0 | 2c2c 3232 | 0 0 | (0 0) (0 0)
1554 20:00:45.224147 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 20:00:45.227110 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 20:00:45.230376 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 20:00:45.236867 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 20:00:45.240199 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 20:00:45.243619 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 20:00:45.250486 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
1561 20:00:45.253453 0 10 8 | B1->B0 | 2d2d 2929 | 1 0 | (1 0) (0 0)
1562 20:00:45.256933 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 20:00:45.263713 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 20:00:45.266895 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 20:00:45.270100 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 20:00:45.276512 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 20:00:45.279984 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 20:00:45.282997 0 11 4 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1569 20:00:45.289867 0 11 8 | B1->B0 | 3939 3c3c | 1 0 | (0 0) (1 1)
1570 20:00:45.294144 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 20:00:45.297305 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 20:00:45.304091 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 20:00:45.307597 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 20:00:45.310291 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 20:00:45.317517 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 20:00:45.320622 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1577 20:00:45.323001 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1578 20:00:45.329697 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 20:00:45.333931 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 20:00:45.336050 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 20:00:45.343214 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 20:00:45.346930 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 20:00:45.349292 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 20:00:45.355934 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 20:00:45.359593 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 20:00:45.362607 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 20:00:45.369301 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 20:00:45.372543 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 20:00:45.376034 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 20:00:45.382437 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 20:00:45.386017 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 20:00:45.389188 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1593 20:00:45.395970 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1594 20:00:45.396529 Total UI for P1: 0, mck2ui 16
1595 20:00:45.402496 best dqsien dly found for B0: ( 0, 14, 4)
1596 20:00:45.403050 Total UI for P1: 0, mck2ui 16
1597 20:00:45.406149 best dqsien dly found for B1: ( 0, 14, 6)
1598 20:00:45.413098 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1599 20:00:45.415690 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1600 20:00:45.416280
1601 20:00:45.419309 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1602 20:00:45.422747 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1603 20:00:45.425808 [Gating] SW calibration Done
1604 20:00:45.426364 ==
1605 20:00:45.429285 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 20:00:45.432645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 20:00:45.433201 ==
1608 20:00:45.433564 RX Vref Scan: 0
1609 20:00:45.435715
1610 20:00:45.436315 RX Vref 0 -> 0, step: 1
1611 20:00:45.436686
1612 20:00:45.438850 RX Delay -130 -> 252, step: 16
1613 20:00:45.442416 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1614 20:00:45.449140 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1615 20:00:45.453016 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1616 20:00:45.455781 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1617 20:00:45.459085 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1618 20:00:45.462385 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1619 20:00:45.468890 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1620 20:00:45.472031 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1621 20:00:45.475832 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1622 20:00:45.478932 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1623 20:00:45.482183 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1624 20:00:45.489466 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1625 20:00:45.491693 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1626 20:00:45.495359 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1627 20:00:45.498502 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1628 20:00:45.501931 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1629 20:00:45.505317 ==
1630 20:00:45.508768 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 20:00:45.512276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 20:00:45.512952 ==
1633 20:00:45.513329 DQS Delay:
1634 20:00:45.515095 DQS0 = 0, DQS1 = 0
1635 20:00:45.515548 DQM Delay:
1636 20:00:45.518615 DQM0 = 89, DQM1 = 78
1637 20:00:45.519174 DQ Delay:
1638 20:00:45.522084 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1639 20:00:45.525457 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1640 20:00:45.528500 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1641 20:00:45.532817 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1642 20:00:45.533371
1643 20:00:45.533737
1644 20:00:45.534075 ==
1645 20:00:45.535208 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 20:00:45.538536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 20:00:45.538995 ==
1648 20:00:45.539363
1649 20:00:45.539697
1650 20:00:45.542128 TX Vref Scan disable
1651 20:00:45.545260 == TX Byte 0 ==
1652 20:00:45.548312 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1653 20:00:45.553161 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1654 20:00:45.554914 == TX Byte 1 ==
1655 20:00:45.558388 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1656 20:00:45.561491 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1657 20:00:45.562047 ==
1658 20:00:45.564951 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 20:00:45.571379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 20:00:45.571979 ==
1661 20:00:45.583476 TX Vref=22, minBit 10, minWin=26, winSum=442
1662 20:00:45.586538 TX Vref=24, minBit 0, minWin=27, winSum=445
1663 20:00:45.590106 TX Vref=26, minBit 9, minWin=27, winSum=446
1664 20:00:45.594186 TX Vref=28, minBit 10, minWin=27, winSum=447
1665 20:00:45.596500 TX Vref=30, minBit 10, minWin=27, winSum=446
1666 20:00:45.603150 TX Vref=32, minBit 0, minWin=27, winSum=442
1667 20:00:45.607060 [TxChooseVref] Worse bit 10, Min win 27, Win sum 447, Final Vref 28
1668 20:00:45.607519
1669 20:00:45.609768 Final TX Range 1 Vref 28
1670 20:00:45.610475
1671 20:00:45.610860 ==
1672 20:00:45.613264 Dram Type= 6, Freq= 0, CH_1, rank 0
1673 20:00:45.616324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1674 20:00:45.619510 ==
1675 20:00:45.620004
1676 20:00:45.620367
1677 20:00:45.620701 TX Vref Scan disable
1678 20:00:45.623459 == TX Byte 0 ==
1679 20:00:45.626895 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1680 20:00:45.630360 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1681 20:00:45.634235 == TX Byte 1 ==
1682 20:00:45.636754 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1683 20:00:45.643839 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1684 20:00:45.644255
1685 20:00:45.644580 [DATLAT]
1686 20:00:45.644881 Freq=800, CH1 RK0
1687 20:00:45.645172
1688 20:00:45.646680 DATLAT Default: 0xa
1689 20:00:45.647093 0, 0xFFFF, sum = 0
1690 20:00:45.650178 1, 0xFFFF, sum = 0
1691 20:00:45.650599 2, 0xFFFF, sum = 0
1692 20:00:45.653389 3, 0xFFFF, sum = 0
1693 20:00:45.656572 4, 0xFFFF, sum = 0
1694 20:00:45.656990 5, 0xFFFF, sum = 0
1695 20:00:45.659701 6, 0xFFFF, sum = 0
1696 20:00:45.660145 7, 0xFFFF, sum = 0
1697 20:00:45.664024 8, 0xFFFF, sum = 0
1698 20:00:45.664453 9, 0x0, sum = 1
1699 20:00:45.666807 10, 0x0, sum = 2
1700 20:00:45.667229 11, 0x0, sum = 3
1701 20:00:45.667567 12, 0x0, sum = 4
1702 20:00:45.669872 best_step = 10
1703 20:00:45.670285
1704 20:00:45.670611 ==
1705 20:00:45.673081 Dram Type= 6, Freq= 0, CH_1, rank 0
1706 20:00:45.676822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1707 20:00:45.677240 ==
1708 20:00:45.679831 RX Vref Scan: 1
1709 20:00:45.680246
1710 20:00:45.683525 Set Vref Range= 32 -> 127
1711 20:00:45.684035
1712 20:00:45.684377 RX Vref 32 -> 127, step: 1
1713 20:00:45.684794
1714 20:00:45.686387 RX Delay -95 -> 252, step: 8
1715 20:00:45.686867
1716 20:00:45.689841 Set Vref, RX VrefLevel [Byte0]: 32
1717 20:00:45.693285 [Byte1]: 32
1718 20:00:45.693703
1719 20:00:45.696295 Set Vref, RX VrefLevel [Byte0]: 33
1720 20:00:45.699839 [Byte1]: 33
1721 20:00:45.703697
1722 20:00:45.704151 Set Vref, RX VrefLevel [Byte0]: 34
1723 20:00:45.707223 [Byte1]: 34
1724 20:00:45.711631
1725 20:00:45.711975 Set Vref, RX VrefLevel [Byte0]: 35
1726 20:00:45.714824 [Byte1]: 35
1727 20:00:45.718933
1728 20:00:45.719236 Set Vref, RX VrefLevel [Byte0]: 36
1729 20:00:45.722202 [Byte1]: 36
1730 20:00:45.726393
1731 20:00:45.726688 Set Vref, RX VrefLevel [Byte0]: 37
1732 20:00:45.730008 [Byte1]: 37
1733 20:00:45.734247
1734 20:00:45.734636 Set Vref, RX VrefLevel [Byte0]: 38
1735 20:00:45.737260 [Byte1]: 38
1736 20:00:45.741816
1737 20:00:45.742209 Set Vref, RX VrefLevel [Byte0]: 39
1738 20:00:45.745011 [Byte1]: 39
1739 20:00:45.749353
1740 20:00:45.749744 Set Vref, RX VrefLevel [Byte0]: 40
1741 20:00:45.752951 [Byte1]: 40
1742 20:00:45.757781
1743 20:00:45.758350 Set Vref, RX VrefLevel [Byte0]: 41
1744 20:00:45.760467 [Byte1]: 41
1745 20:00:45.764613
1746 20:00:45.765067 Set Vref, RX VrefLevel [Byte0]: 42
1747 20:00:45.767912 [Byte1]: 42
1748 20:00:45.772636
1749 20:00:45.773196 Set Vref, RX VrefLevel [Byte0]: 43
1750 20:00:45.776084 [Byte1]: 43
1751 20:00:45.780107
1752 20:00:45.780665 Set Vref, RX VrefLevel [Byte0]: 44
1753 20:00:45.786086 [Byte1]: 44
1754 20:00:45.786638
1755 20:00:45.789777 Set Vref, RX VrefLevel [Byte0]: 45
1756 20:00:45.793102 [Byte1]: 45
1757 20:00:45.793657
1758 20:00:45.796487 Set Vref, RX VrefLevel [Byte0]: 46
1759 20:00:45.799776 [Byte1]: 46
1760 20:00:45.800238
1761 20:00:45.803052 Set Vref, RX VrefLevel [Byte0]: 47
1762 20:00:45.806183 [Byte1]: 47
1763 20:00:45.810675
1764 20:00:45.811131 Set Vref, RX VrefLevel [Byte0]: 48
1765 20:00:45.813746 [Byte1]: 48
1766 20:00:45.817873
1767 20:00:45.818371 Set Vref, RX VrefLevel [Byte0]: 49
1768 20:00:45.821330 [Byte1]: 49
1769 20:00:45.825784
1770 20:00:45.826346 Set Vref, RX VrefLevel [Byte0]: 50
1771 20:00:45.828732 [Byte1]: 50
1772 20:00:45.833022
1773 20:00:45.833555 Set Vref, RX VrefLevel [Byte0]: 51
1774 20:00:45.836139 [Byte1]: 51
1775 20:00:45.840854
1776 20:00:45.841405 Set Vref, RX VrefLevel [Byte0]: 52
1777 20:00:45.844069 [Byte1]: 52
1778 20:00:45.848203
1779 20:00:45.848760 Set Vref, RX VrefLevel [Byte0]: 53
1780 20:00:45.851806 [Byte1]: 53
1781 20:00:45.856114
1782 20:00:45.856686 Set Vref, RX VrefLevel [Byte0]: 54
1783 20:00:45.859633 [Byte1]: 54
1784 20:00:45.863700
1785 20:00:45.864299 Set Vref, RX VrefLevel [Byte0]: 55
1786 20:00:45.866720 [Byte1]: 55
1787 20:00:45.870843
1788 20:00:45.871303 Set Vref, RX VrefLevel [Byte0]: 56
1789 20:00:45.874081 [Byte1]: 56
1790 20:00:45.878780
1791 20:00:45.879331 Set Vref, RX VrefLevel [Byte0]: 57
1792 20:00:45.885430 [Byte1]: 57
1793 20:00:45.885981
1794 20:00:45.888876 Set Vref, RX VrefLevel [Byte0]: 58
1795 20:00:45.891865 [Byte1]: 58
1796 20:00:45.892419
1797 20:00:45.895474 Set Vref, RX VrefLevel [Byte0]: 59
1798 20:00:45.898401 [Byte1]: 59
1799 20:00:45.898954
1800 20:00:45.902014 Set Vref, RX VrefLevel [Byte0]: 60
1801 20:00:45.905014 [Byte1]: 60
1802 20:00:45.909604
1803 20:00:45.910155 Set Vref, RX VrefLevel [Byte0]: 61
1804 20:00:45.912985 [Byte1]: 61
1805 20:00:45.916462
1806 20:00:45.916923 Set Vref, RX VrefLevel [Byte0]: 62
1807 20:00:45.920260 [Byte1]: 62
1808 20:00:45.924136
1809 20:00:45.924592 Set Vref, RX VrefLevel [Byte0]: 63
1810 20:00:45.927370 [Byte1]: 63
1811 20:00:45.931661
1812 20:00:45.932286 Set Vref, RX VrefLevel [Byte0]: 64
1813 20:00:45.935236 [Byte1]: 64
1814 20:00:45.939954
1815 20:00:45.940507 Set Vref, RX VrefLevel [Byte0]: 65
1816 20:00:45.943134 [Byte1]: 65
1817 20:00:45.947460
1818 20:00:45.948078 Set Vref, RX VrefLevel [Byte0]: 66
1819 20:00:45.950381 [Byte1]: 66
1820 20:00:45.954867
1821 20:00:45.955422 Set Vref, RX VrefLevel [Byte0]: 67
1822 20:00:45.957906 [Byte1]: 67
1823 20:00:45.962699
1824 20:00:45.963248 Set Vref, RX VrefLevel [Byte0]: 68
1825 20:00:45.965344 [Byte1]: 68
1826 20:00:45.970208
1827 20:00:45.970772 Set Vref, RX VrefLevel [Byte0]: 69
1828 20:00:45.973014 [Byte1]: 69
1829 20:00:45.977557
1830 20:00:45.978115 Set Vref, RX VrefLevel [Byte0]: 70
1831 20:00:45.980814 [Byte1]: 70
1832 20:00:45.985237
1833 20:00:45.985821 Set Vref, RX VrefLevel [Byte0]: 71
1834 20:00:45.988081 [Byte1]: 71
1835 20:00:45.992817
1836 20:00:45.993368 Set Vref, RX VrefLevel [Byte0]: 72
1837 20:00:45.996627 [Byte1]: 72
1838 20:00:46.000445
1839 20:00:46.000992 Set Vref, RX VrefLevel [Byte0]: 73
1840 20:00:46.004407 [Byte1]: 73
1841 20:00:46.007936
1842 20:00:46.008507 Set Vref, RX VrefLevel [Byte0]: 74
1843 20:00:46.011356 [Byte1]: 74
1844 20:00:46.015287
1845 20:00:46.015980 Set Vref, RX VrefLevel [Byte0]: 75
1846 20:00:46.018562 [Byte1]: 75
1847 20:00:46.023414
1848 20:00:46.024006 Set Vref, RX VrefLevel [Byte0]: 76
1849 20:00:46.026447 [Byte1]: 76
1850 20:00:46.030588
1851 20:00:46.031142 Final RX Vref Byte 0 = 55 to rank0
1852 20:00:46.034228 Final RX Vref Byte 1 = 65 to rank0
1853 20:00:46.037097 Final RX Vref Byte 0 = 55 to rank1
1854 20:00:46.040494 Final RX Vref Byte 1 = 65 to rank1==
1855 20:00:46.044008 Dram Type= 6, Freq= 0, CH_1, rank 0
1856 20:00:46.049993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 20:00:46.050539 ==
1858 20:00:46.050911 DQS Delay:
1859 20:00:46.053657 DQS0 = 0, DQS1 = 0
1860 20:00:46.054210 DQM Delay:
1861 20:00:46.054581 DQM0 = 86, DQM1 = 78
1862 20:00:46.057091 DQ Delay:
1863 20:00:46.059993 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1864 20:00:46.063809 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1865 20:00:46.066980 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1866 20:00:46.070073 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1867 20:00:46.070629
1868 20:00:46.070995
1869 20:00:46.076611 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1870 20:00:46.079605 CH1 RK0: MR19=606, MR18=2C19
1871 20:00:46.086261 CH1_RK0: MR19=0x606, MR18=0x2C19, DQSOSC=398, MR23=63, INC=93, DEC=62
1872 20:00:46.086803
1873 20:00:46.089594 ----->DramcWriteLeveling(PI) begin...
1874 20:00:46.090155 ==
1875 20:00:46.092897 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 20:00:46.096260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 20:00:46.096818 ==
1878 20:00:46.099900 Write leveling (Byte 0): 27 => 27
1879 20:00:46.103191 Write leveling (Byte 1): 30 => 30
1880 20:00:46.106586 DramcWriteLeveling(PI) end<-----
1881 20:00:46.107139
1882 20:00:46.107505 ==
1883 20:00:46.109825 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 20:00:46.112572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1885 20:00:46.116780 ==
1886 20:00:46.117338 [Gating] SW mode calibration
1887 20:00:46.126536 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1888 20:00:46.129449 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1889 20:00:46.133052 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1890 20:00:46.139549 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1891 20:00:46.143166 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1892 20:00:46.146051 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 20:00:46.152703 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 20:00:46.157135 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 20:00:46.159478 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 20:00:46.166126 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 20:00:46.169180 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 20:00:46.172731 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 20:00:46.179410 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 20:00:46.182789 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 20:00:46.185916 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 20:00:46.192174 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 20:00:46.195763 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 20:00:46.198878 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 20:00:46.206100 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 20:00:46.208958 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1907 20:00:46.212421 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 20:00:46.218773 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 20:00:46.222546 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 20:00:46.225872 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 20:00:46.232482 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 20:00:46.235523 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 20:00:46.238705 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 20:00:46.245545 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 20:00:46.248772 0 9 8 | B1->B0 | 3131 2424 | 1 0 | (1 1) (0 0)
1916 20:00:46.252111 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 20:00:46.258633 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 20:00:46.261943 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 20:00:46.265270 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 20:00:46.271653 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 20:00:46.274906 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1922 20:00:46.278576 0 10 4 | B1->B0 | 3232 3434 | 1 0 | (1 0) (0 0)
1923 20:00:46.284782 0 10 8 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (1 0)
1924 20:00:46.288364 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 20:00:46.291541 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 20:00:46.295415 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 20:00:46.302173 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 20:00:46.305475 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 20:00:46.308365 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 20:00:46.315301 0 11 4 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
1931 20:00:46.318374 0 11 8 | B1->B0 | 4242 3636 | 0 0 | (0 0) (0 0)
1932 20:00:46.321932 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1933 20:00:46.328499 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 20:00:46.332112 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 20:00:46.334735 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 20:00:46.341975 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 20:00:46.344626 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 20:00:46.348346 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 20:00:46.354871 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1940 20:00:46.358490 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 20:00:46.361410 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 20:00:46.368023 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 20:00:46.371321 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 20:00:46.374666 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 20:00:46.381371 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 20:00:46.384036 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 20:00:46.387842 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 20:00:46.394522 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 20:00:46.397686 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 20:00:46.400586 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 20:00:46.407696 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 20:00:46.410511 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 20:00:46.414639 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1954 20:00:46.420719 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1955 20:00:46.423923 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1956 20:00:46.426976 Total UI for P1: 0, mck2ui 16
1957 20:00:46.430337 best dqsien dly found for B0: ( 0, 14, 6)
1958 20:00:46.433945 Total UI for P1: 0, mck2ui 16
1959 20:00:46.437246 best dqsien dly found for B1: ( 0, 14, 2)
1960 20:00:46.440267 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1961 20:00:46.443657 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1962 20:00:46.444267
1963 20:00:46.446976 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1964 20:00:46.450002 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1965 20:00:46.453928 [Gating] SW calibration Done
1966 20:00:46.454477 ==
1967 20:00:46.456762 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 20:00:46.463238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 20:00:46.463837 ==
1970 20:00:46.464221 RX Vref Scan: 0
1971 20:00:46.464569
1972 20:00:46.466502 RX Vref 0 -> 0, step: 1
1973 20:00:46.466959
1974 20:00:46.469885 RX Delay -130 -> 252, step: 16
1975 20:00:46.472999 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1976 20:00:46.476772 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1977 20:00:46.479990 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1978 20:00:46.483664 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1979 20:00:46.490147 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1980 20:00:46.494374 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1981 20:00:46.497020 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1982 20:00:46.500803 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1983 20:00:46.503884 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1984 20:00:46.510036 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1985 20:00:46.513382 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1986 20:00:46.516289 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1987 20:00:46.519569 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1988 20:00:46.526218 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1989 20:00:46.529628 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1990 20:00:46.533227 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1991 20:00:46.533791 ==
1992 20:00:46.536619 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 20:00:46.539332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 20:00:46.543548 ==
1995 20:00:46.544159 DQS Delay:
1996 20:00:46.544532 DQS0 = 0, DQS1 = 0
1997 20:00:46.545985 DQM Delay:
1998 20:00:46.546441 DQM0 = 87, DQM1 = 79
1999 20:00:46.549435 DQ Delay:
2000 20:00:46.549895 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
2001 20:00:46.552728 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2002 20:00:46.556407 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
2003 20:00:46.560301 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2004 20:00:46.562654
2005 20:00:46.563110
2006 20:00:46.563476 ==
2007 20:00:46.565990 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 20:00:46.569509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 20:00:46.570065 ==
2010 20:00:46.570437
2011 20:00:46.570774
2012 20:00:46.572660 TX Vref Scan disable
2013 20:00:46.573207 == TX Byte 0 ==
2014 20:00:46.579699 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2015 20:00:46.583216 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2016 20:00:46.583809 == TX Byte 1 ==
2017 20:00:46.588954 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2018 20:00:46.592660 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2019 20:00:46.593216 ==
2020 20:00:46.595946 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 20:00:46.599550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 20:00:46.600171 ==
2023 20:00:46.612924 TX Vref=22, minBit 8, minWin=27, winSum=446
2024 20:00:46.616426 TX Vref=24, minBit 8, minWin=27, winSum=450
2025 20:00:46.620005 TX Vref=26, minBit 13, minWin=27, winSum=453
2026 20:00:46.622908 TX Vref=28, minBit 8, minWin=27, winSum=452
2027 20:00:46.626250 TX Vref=30, minBit 8, minWin=27, winSum=448
2028 20:00:46.632652 TX Vref=32, minBit 8, minWin=27, winSum=449
2029 20:00:46.636456 [TxChooseVref] Worse bit 13, Min win 27, Win sum 453, Final Vref 26
2030 20:00:46.637034
2031 20:00:46.639898 Final TX Range 1 Vref 26
2032 20:00:46.640457
2033 20:00:46.640830 ==
2034 20:00:46.642578 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 20:00:46.649143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 20:00:46.649763 ==
2037 20:00:46.650133
2038 20:00:46.650474
2039 20:00:46.650803 TX Vref Scan disable
2040 20:00:46.652945 == TX Byte 0 ==
2041 20:00:46.657095 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2042 20:00:46.663004 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2043 20:00:46.663565 == TX Byte 1 ==
2044 20:00:46.666694 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2045 20:00:46.673511 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2046 20:00:46.674068
2047 20:00:46.674431 [DATLAT]
2048 20:00:46.674772 Freq=800, CH1 RK1
2049 20:00:46.675098
2050 20:00:46.676540 DATLAT Default: 0xa
2051 20:00:46.676999 0, 0xFFFF, sum = 0
2052 20:00:46.679566 1, 0xFFFF, sum = 0
2053 20:00:46.680082 2, 0xFFFF, sum = 0
2054 20:00:46.683077 3, 0xFFFF, sum = 0
2055 20:00:46.683640 4, 0xFFFF, sum = 0
2056 20:00:46.686441 5, 0xFFFF, sum = 0
2057 20:00:46.689342 6, 0xFFFF, sum = 0
2058 20:00:46.689861 7, 0xFFFF, sum = 0
2059 20:00:46.693145 8, 0xFFFF, sum = 0
2060 20:00:46.693820 9, 0x0, sum = 1
2061 20:00:46.696432 10, 0x0, sum = 2
2062 20:00:46.696912 11, 0x0, sum = 3
2063 20:00:46.697405 12, 0x0, sum = 4
2064 20:00:46.699442 best_step = 10
2065 20:00:46.699948
2066 20:00:46.700428 ==
2067 20:00:46.702979 Dram Type= 6, Freq= 0, CH_1, rank 1
2068 20:00:46.706289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2069 20:00:46.706867 ==
2070 20:00:46.709648 RX Vref Scan: 0
2071 20:00:46.710222
2072 20:00:46.710708 RX Vref 0 -> 0, step: 1
2073 20:00:46.712404
2074 20:00:46.712910 RX Delay -95 -> 252, step: 8
2075 20:00:46.719542 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2076 20:00:46.723291 iDelay=217, Bit 1, Center 84 (-23 ~ 192) 216
2077 20:00:46.726681 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2078 20:00:46.729634 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2079 20:00:46.736184 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2080 20:00:46.739216 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2081 20:00:46.742484 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2082 20:00:46.746173 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2083 20:00:46.749781 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2084 20:00:46.755688 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2085 20:00:46.759598 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2086 20:00:46.762411 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2087 20:00:46.766362 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2088 20:00:46.769481 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2089 20:00:46.776219 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2090 20:00:46.779241 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2091 20:00:46.779673 ==
2092 20:00:46.782425 Dram Type= 6, Freq= 0, CH_1, rank 1
2093 20:00:46.785781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2094 20:00:46.786243 ==
2095 20:00:46.789015 DQS Delay:
2096 20:00:46.789441 DQS0 = 0, DQS1 = 0
2097 20:00:46.789884 DQM Delay:
2098 20:00:46.792297 DQM0 = 88, DQM1 = 78
2099 20:00:46.792726 DQ Delay:
2100 20:00:46.795658 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =84
2101 20:00:46.799024 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2102 20:00:46.802718 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2103 20:00:46.805554 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2104 20:00:46.805987
2105 20:00:46.806424
2106 20:00:46.816185 [DQSOSCAuto] RK1, (LSB)MR18= 0x160f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2107 20:00:46.818874 CH1 RK1: MR19=606, MR18=160F
2108 20:00:46.822204 CH1_RK1: MR19=0x606, MR18=0x160F, DQSOSC=404, MR23=63, INC=90, DEC=60
2109 20:00:46.825710 [RxdqsGatingPostProcess] freq 800
2110 20:00:46.832533 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2111 20:00:46.836112 Pre-setting of DQS Precalculation
2112 20:00:46.839260 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2113 20:00:46.848878 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2114 20:00:46.856400 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2115 20:00:46.856932
2116 20:00:46.857380
2117 20:00:46.858615 [Calibration Summary] 1600 Mbps
2118 20:00:46.859047 CH 0, Rank 0
2119 20:00:46.862199 SW Impedance : PASS
2120 20:00:46.862725 DUTY Scan : NO K
2121 20:00:46.865377 ZQ Calibration : PASS
2122 20:00:46.868464 Jitter Meter : NO K
2123 20:00:46.868895 CBT Training : PASS
2124 20:00:46.872092 Write leveling : PASS
2125 20:00:46.875597 RX DQS gating : PASS
2126 20:00:46.876178 RX DQ/DQS(RDDQC) : PASS
2127 20:00:46.878447 TX DQ/DQS : PASS
2128 20:00:46.882227 RX DATLAT : PASS
2129 20:00:46.882785 RX DQ/DQS(Engine): PASS
2130 20:00:46.885091 TX OE : NO K
2131 20:00:46.885524 All Pass.
2132 20:00:46.886079
2133 20:00:46.888882 CH 0, Rank 1
2134 20:00:46.889311 SW Impedance : PASS
2135 20:00:46.891601 DUTY Scan : NO K
2136 20:00:46.892081 ZQ Calibration : PASS
2137 20:00:46.895196 Jitter Meter : NO K
2138 20:00:46.899822 CBT Training : PASS
2139 20:00:46.900346 Write leveling : PASS
2140 20:00:46.901579 RX DQS gating : PASS
2141 20:00:46.905562 RX DQ/DQS(RDDQC) : PASS
2142 20:00:46.906094 TX DQ/DQS : PASS
2143 20:00:46.908391 RX DATLAT : PASS
2144 20:00:46.911927 RX DQ/DQS(Engine): PASS
2145 20:00:46.912458 TX OE : NO K
2146 20:00:46.915122 All Pass.
2147 20:00:46.915654
2148 20:00:46.916137 CH 1, Rank 0
2149 20:00:46.919389 SW Impedance : PASS
2150 20:00:46.919971 DUTY Scan : NO K
2151 20:00:46.921508 ZQ Calibration : PASS
2152 20:00:46.925733 Jitter Meter : NO K
2153 20:00:46.926267 CBT Training : PASS
2154 20:00:46.928466 Write leveling : PASS
2155 20:00:46.931870 RX DQS gating : PASS
2156 20:00:46.932401 RX DQ/DQS(RDDQC) : PASS
2157 20:00:46.935381 TX DQ/DQS : PASS
2158 20:00:46.938772 RX DATLAT : PASS
2159 20:00:46.939223 RX DQ/DQS(Engine): PASS
2160 20:00:46.941716 TX OE : NO K
2161 20:00:46.942256 All Pass.
2162 20:00:46.942698
2163 20:00:46.945158 CH 1, Rank 1
2164 20:00:46.945693 SW Impedance : PASS
2165 20:00:46.948229 DUTY Scan : NO K
2166 20:00:46.948658 ZQ Calibration : PASS
2167 20:00:46.952272 Jitter Meter : NO K
2168 20:00:46.954829 CBT Training : PASS
2169 20:00:46.955258 Write leveling : PASS
2170 20:00:46.958521 RX DQS gating : PASS
2171 20:00:46.962147 RX DQ/DQS(RDDQC) : PASS
2172 20:00:46.962695 TX DQ/DQS : PASS
2173 20:00:46.965450 RX DATLAT : PASS
2174 20:00:46.968110 RX DQ/DQS(Engine): PASS
2175 20:00:46.968644 TX OE : NO K
2176 20:00:46.971373 All Pass.
2177 20:00:46.971883
2178 20:00:46.972363 DramC Write-DBI off
2179 20:00:46.974967 PER_BANK_REFRESH: Hybrid Mode
2180 20:00:46.975439 TX_TRACKING: ON
2181 20:00:46.978070 [GetDramInforAfterCalByMRR] Vendor 6.
2182 20:00:46.985042 [GetDramInforAfterCalByMRR] Revision 606.
2183 20:00:46.988243 [GetDramInforAfterCalByMRR] Revision 2 0.
2184 20:00:46.988720 MR0 0x3b3b
2185 20:00:46.989206 MR8 0x5151
2186 20:00:46.991390 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2187 20:00:46.991905
2188 20:00:46.995142 MR0 0x3b3b
2189 20:00:46.995611 MR8 0x5151
2190 20:00:46.997974 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2191 20:00:46.998451
2192 20:00:47.008174 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2193 20:00:47.011475 [FAST_K] Save calibration result to emmc
2194 20:00:47.014485 [FAST_K] Save calibration result to emmc
2195 20:00:47.018956 dram_init: config_dvfs: 1
2196 20:00:47.021196 dramc_set_vcore_voltage set vcore to 662500
2197 20:00:47.024866 Read voltage for 1200, 2
2198 20:00:47.025419 Vio18 = 0
2199 20:00:47.025783 Vcore = 662500
2200 20:00:47.027850 Vdram = 0
2201 20:00:47.028403 Vddq = 0
2202 20:00:47.028766 Vmddr = 0
2203 20:00:47.034733 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2204 20:00:47.037574 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2205 20:00:47.041143 MEM_TYPE=3, freq_sel=15
2206 20:00:47.044340 sv_algorithm_assistance_LP4_1600
2207 20:00:47.048250 ============ PULL DRAM RESETB DOWN ============
2208 20:00:47.050790 ========== PULL DRAM RESETB DOWN end =========
2209 20:00:47.058451 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2210 20:00:47.061028 ===================================
2211 20:00:47.064123 LPDDR4 DRAM CONFIGURATION
2212 20:00:47.067840 ===================================
2213 20:00:47.068400 EX_ROW_EN[0] = 0x0
2214 20:00:47.070907 EX_ROW_EN[1] = 0x0
2215 20:00:47.071460 LP4Y_EN = 0x0
2216 20:00:47.074011 WORK_FSP = 0x0
2217 20:00:47.074468 WL = 0x4
2218 20:00:47.077282 RL = 0x4
2219 20:00:47.077739 BL = 0x2
2220 20:00:47.080809 RPST = 0x0
2221 20:00:47.081364 RD_PRE = 0x0
2222 20:00:47.084087 WR_PRE = 0x1
2223 20:00:47.084640 WR_PST = 0x0
2224 20:00:47.087286 DBI_WR = 0x0
2225 20:00:47.090370 DBI_RD = 0x0
2226 20:00:47.090828 OTF = 0x1
2227 20:00:47.094196 ===================================
2228 20:00:47.097243 ===================================
2229 20:00:47.097796 ANA top config
2230 20:00:47.100545 ===================================
2231 20:00:47.103839 DLL_ASYNC_EN = 0
2232 20:00:47.107170 ALL_SLAVE_EN = 0
2233 20:00:47.110449 NEW_RANK_MODE = 1
2234 20:00:47.114584 DLL_IDLE_MODE = 1
2235 20:00:47.115139 LP45_APHY_COMB_EN = 1
2236 20:00:47.117456 TX_ODT_DIS = 1
2237 20:00:47.120343 NEW_8X_MODE = 1
2238 20:00:47.123861 ===================================
2239 20:00:47.126897 ===================================
2240 20:00:47.130357 data_rate = 2400
2241 20:00:47.133498 CKR = 1
2242 20:00:47.133956 DQ_P2S_RATIO = 8
2243 20:00:47.136667 ===================================
2244 20:00:47.140416 CA_P2S_RATIO = 8
2245 20:00:47.143247 DQ_CA_OPEN = 0
2246 20:00:47.146924 DQ_SEMI_OPEN = 0
2247 20:00:47.150584 CA_SEMI_OPEN = 0
2248 20:00:47.154078 CA_FULL_RATE = 0
2249 20:00:47.154649 DQ_CKDIV4_EN = 0
2250 20:00:47.156795 CA_CKDIV4_EN = 0
2251 20:00:47.160142 CA_PREDIV_EN = 0
2252 20:00:47.163326 PH8_DLY = 17
2253 20:00:47.166504 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2254 20:00:47.170354 DQ_AAMCK_DIV = 4
2255 20:00:47.170916 CA_AAMCK_DIV = 4
2256 20:00:47.174424 CA_ADMCK_DIV = 4
2257 20:00:47.176249 DQ_TRACK_CA_EN = 0
2258 20:00:47.180024 CA_PICK = 1200
2259 20:00:47.183419 CA_MCKIO = 1200
2260 20:00:47.186819 MCKIO_SEMI = 0
2261 20:00:47.189345 PLL_FREQ = 2366
2262 20:00:47.192845 DQ_UI_PI_RATIO = 32
2263 20:00:47.192925 CA_UI_PI_RATIO = 0
2264 20:00:47.196013 ===================================
2265 20:00:47.200496 ===================================
2266 20:00:47.203052 memory_type:LPDDR4
2267 20:00:47.206116 GP_NUM : 10
2268 20:00:47.206569 SRAM_EN : 1
2269 20:00:47.209700 MD32_EN : 0
2270 20:00:47.213374 ===================================
2271 20:00:47.216038 [ANA_INIT] >>>>>>>>>>>>>>
2272 20:00:47.219548 <<<<<< [CONFIGURE PHASE]: ANA_TX
2273 20:00:47.222524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2274 20:00:47.226057 ===================================
2275 20:00:47.226354 data_rate = 2400,PCW = 0X5b00
2276 20:00:47.229294 ===================================
2277 20:00:47.233350 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2278 20:00:47.239209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2279 20:00:47.245733 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2280 20:00:47.249247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2281 20:00:47.252426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2282 20:00:47.255487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2283 20:00:47.259626 [ANA_INIT] flow start
2284 20:00:47.262116 [ANA_INIT] PLL >>>>>>>>
2285 20:00:47.262410 [ANA_INIT] PLL <<<<<<<<
2286 20:00:47.265581 [ANA_INIT] MIDPI >>>>>>>>
2287 20:00:47.269355 [ANA_INIT] MIDPI <<<<<<<<
2288 20:00:47.269699 [ANA_INIT] DLL >>>>>>>>
2289 20:00:47.272554 [ANA_INIT] DLL <<<<<<<<
2290 20:00:47.275925 [ANA_INIT] flow end
2291 20:00:47.279049 ============ LP4 DIFF to SE enter ============
2292 20:00:47.282481 ============ LP4 DIFF to SE exit ============
2293 20:00:47.286534 [ANA_INIT] <<<<<<<<<<<<<
2294 20:00:47.288768 [Flow] Enable top DCM control >>>>>
2295 20:00:47.292637 [Flow] Enable top DCM control <<<<<
2296 20:00:47.296047 Enable DLL master slave shuffle
2297 20:00:47.299029 ==============================================================
2298 20:00:47.302902 Gating Mode config
2299 20:00:47.309493 ==============================================================
2300 20:00:47.310060 Config description:
2301 20:00:47.318723 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2302 20:00:47.326088 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2303 20:00:47.328865 SELPH_MODE 0: By rank 1: By Phase
2304 20:00:47.335578 ==============================================================
2305 20:00:47.339039 GAT_TRACK_EN = 1
2306 20:00:47.342036 RX_GATING_MODE = 2
2307 20:00:47.345342 RX_GATING_TRACK_MODE = 2
2308 20:00:47.348685 SELPH_MODE = 1
2309 20:00:47.352066 PICG_EARLY_EN = 1
2310 20:00:47.355208 VALID_LAT_VALUE = 1
2311 20:00:47.358572 ==============================================================
2312 20:00:47.362012 Enter into Gating configuration >>>>
2313 20:00:47.364950 Exit from Gating configuration <<<<
2314 20:00:47.368223 Enter into DVFS_PRE_config >>>>>
2315 20:00:47.381689 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2316 20:00:47.384805 Exit from DVFS_PRE_config <<<<<
2317 20:00:47.385268 Enter into PICG configuration >>>>
2318 20:00:47.388421 Exit from PICG configuration <<<<
2319 20:00:47.391648 [RX_INPUT] configuration >>>>>
2320 20:00:47.395016 [RX_INPUT] configuration <<<<<
2321 20:00:47.401276 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2322 20:00:47.405265 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2323 20:00:47.412091 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2324 20:00:47.418405 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2325 20:00:47.425104 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2326 20:00:47.431570 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2327 20:00:47.435098 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2328 20:00:47.438147 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2329 20:00:47.442324 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2330 20:00:47.448076 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2331 20:00:47.451600 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2332 20:00:47.454419 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 20:00:47.458266 ===================================
2334 20:00:47.461390 LPDDR4 DRAM CONFIGURATION
2335 20:00:47.464405 ===================================
2336 20:00:47.468108 EX_ROW_EN[0] = 0x0
2337 20:00:47.468666 EX_ROW_EN[1] = 0x0
2338 20:00:47.471587 LP4Y_EN = 0x0
2339 20:00:47.472184 WORK_FSP = 0x0
2340 20:00:47.474881 WL = 0x4
2341 20:00:47.475437 RL = 0x4
2342 20:00:47.477851 BL = 0x2
2343 20:00:47.478314 RPST = 0x0
2344 20:00:47.480920 RD_PRE = 0x0
2345 20:00:47.481478 WR_PRE = 0x1
2346 20:00:47.484713 WR_PST = 0x0
2347 20:00:47.485270 DBI_WR = 0x0
2348 20:00:47.487744 DBI_RD = 0x0
2349 20:00:47.488211 OTF = 0x1
2350 20:00:47.490709 ===================================
2351 20:00:47.497418 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2352 20:00:47.500869 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2353 20:00:47.504121 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2354 20:00:47.507200 ===================================
2355 20:00:47.510778 LPDDR4 DRAM CONFIGURATION
2356 20:00:47.514316 ===================================
2357 20:00:47.518574 EX_ROW_EN[0] = 0x10
2358 20:00:47.519140 EX_ROW_EN[1] = 0x0
2359 20:00:47.520696 LP4Y_EN = 0x0
2360 20:00:47.521160 WORK_FSP = 0x0
2361 20:00:47.524071 WL = 0x4
2362 20:00:47.524859 RL = 0x4
2363 20:00:47.527344 BL = 0x2
2364 20:00:47.527852 RPST = 0x0
2365 20:00:47.530509 RD_PRE = 0x0
2366 20:00:47.530963 WR_PRE = 0x1
2367 20:00:47.533661 WR_PST = 0x0
2368 20:00:47.534121 DBI_WR = 0x0
2369 20:00:47.537235 DBI_RD = 0x0
2370 20:00:47.537692 OTF = 0x1
2371 20:00:47.540575 ===================================
2372 20:00:47.547443 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2373 20:00:47.547770 ==
2374 20:00:47.551075 Dram Type= 6, Freq= 0, CH_0, rank 0
2375 20:00:47.557837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 20:00:47.558238 ==
2377 20:00:47.558489 [Duty_Offset_Calibration]
2378 20:00:47.560535 B0:1 B1:-1 CA:0
2379 20:00:47.560932
2380 20:00:47.564528 [DutyScan_Calibration_Flow] k_type=0
2381 20:00:47.572536
2382 20:00:47.572928 ==CLK 0==
2383 20:00:47.576330 Final CLK duty delay cell = 0
2384 20:00:47.579660 [0] MAX Duty = 5094%(X100), DQS PI = 16
2385 20:00:47.582826 [0] MIN Duty = 4875%(X100), DQS PI = 8
2386 20:00:47.583384 [0] AVG Duty = 4984%(X100)
2387 20:00:47.586056
2388 20:00:47.586612 CH0 CLK Duty spec in!! Max-Min= 219%
2389 20:00:47.592576 [DutyScan_Calibration_Flow] ====Done====
2390 20:00:47.593042
2391 20:00:47.596546 [DutyScan_Calibration_Flow] k_type=1
2392 20:00:47.611713
2393 20:00:47.612310 ==DQS 0 ==
2394 20:00:47.614599 Final DQS duty delay cell = -4
2395 20:00:47.617979 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2396 20:00:47.620951 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2397 20:00:47.624451 [-4] AVG Duty = 4968%(X100)
2398 20:00:47.625064
2399 20:00:47.625665 ==DQS 1 ==
2400 20:00:47.627888 Final DQS duty delay cell = 0
2401 20:00:47.631331 [0] MAX Duty = 5124%(X100), DQS PI = 4
2402 20:00:47.634181 [0] MIN Duty = 5000%(X100), DQS PI = 22
2403 20:00:47.637458 [0] AVG Duty = 5062%(X100)
2404 20:00:47.637918
2405 20:00:47.641349 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2406 20:00:47.641933
2407 20:00:47.644637 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2408 20:00:47.647657 [DutyScan_Calibration_Flow] ====Done====
2409 20:00:47.648153
2410 20:00:47.651180 [DutyScan_Calibration_Flow] k_type=3
2411 20:00:47.669000
2412 20:00:47.669557 ==DQM 0 ==
2413 20:00:47.672352 Final DQM duty delay cell = 0
2414 20:00:47.675880 [0] MAX Duty = 5062%(X100), DQS PI = 40
2415 20:00:47.678638 [0] MIN Duty = 4875%(X100), DQS PI = 6
2416 20:00:47.679099 [0] AVG Duty = 4968%(X100)
2417 20:00:47.682272
2418 20:00:47.682831 ==DQM 1 ==
2419 20:00:47.685486 Final DQM duty delay cell = 4
2420 20:00:47.688759 [4] MAX Duty = 5187%(X100), DQS PI = 14
2421 20:00:47.692034 [4] MIN Duty = 5000%(X100), DQS PI = 22
2422 20:00:47.695791 [4] AVG Duty = 5093%(X100)
2423 20:00:47.696357
2424 20:00:47.698681 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2425 20:00:47.699240
2426 20:00:47.701816 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2427 20:00:47.705592 [DutyScan_Calibration_Flow] ====Done====
2428 20:00:47.706149
2429 20:00:47.708662 [DutyScan_Calibration_Flow] k_type=2
2430 20:00:47.723640
2431 20:00:47.724290 ==DQ 0 ==
2432 20:00:47.727599 Final DQ duty delay cell = -4
2433 20:00:47.730578 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2434 20:00:47.733820 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2435 20:00:47.736946 [-4] AVG Duty = 4969%(X100)
2436 20:00:47.737507
2437 20:00:47.737872 ==DQ 1 ==
2438 20:00:47.740359 Final DQ duty delay cell = -4
2439 20:00:47.743817 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2440 20:00:47.747047 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2441 20:00:47.750654 [-4] AVG Duty = 4922%(X100)
2442 20:00:47.751208
2443 20:00:47.754575 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2444 20:00:47.755134
2445 20:00:47.757067 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2446 20:00:47.760382 [DutyScan_Calibration_Flow] ====Done====
2447 20:00:47.760960 ==
2448 20:00:47.763237 Dram Type= 6, Freq= 0, CH_1, rank 0
2449 20:00:47.766889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2450 20:00:47.767606 ==
2451 20:00:47.770207 [Duty_Offset_Calibration]
2452 20:00:47.770765 B0:-1 B1:1 CA:2
2453 20:00:47.771132
2454 20:00:47.773652 [DutyScan_Calibration_Flow] k_type=0
2455 20:00:47.784711
2456 20:00:47.785265 ==CLK 0==
2457 20:00:47.787449 Final CLK duty delay cell = 0
2458 20:00:47.790609 [0] MAX Duty = 5156%(X100), DQS PI = 22
2459 20:00:47.794697 [0] MIN Duty = 4969%(X100), DQS PI = 62
2460 20:00:47.798008 [0] AVG Duty = 5062%(X100)
2461 20:00:47.798568
2462 20:00:47.800959 CH1 CLK Duty spec in!! Max-Min= 187%
2463 20:00:47.804286 [DutyScan_Calibration_Flow] ====Done====
2464 20:00:47.804837
2465 20:00:47.807281 [DutyScan_Calibration_Flow] k_type=1
2466 20:00:47.823710
2467 20:00:47.824299 ==DQS 0 ==
2468 20:00:47.826795 Final DQS duty delay cell = 0
2469 20:00:47.830576 [0] MAX Duty = 5156%(X100), DQS PI = 48
2470 20:00:47.833169 [0] MIN Duty = 4907%(X100), DQS PI = 8
2471 20:00:47.836595 [0] AVG Duty = 5031%(X100)
2472 20:00:47.837011
2473 20:00:47.837342 ==DQS 1 ==
2474 20:00:47.839834 Final DQS duty delay cell = 0
2475 20:00:47.843595 [0] MAX Duty = 5094%(X100), DQS PI = 12
2476 20:00:47.846375 [0] MIN Duty = 4969%(X100), DQS PI = 58
2477 20:00:47.849745 [0] AVG Duty = 5031%(X100)
2478 20:00:47.850288
2479 20:00:47.853220 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2480 20:00:47.853744
2481 20:00:47.856428 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2482 20:00:47.859661 [DutyScan_Calibration_Flow] ====Done====
2483 20:00:47.860238
2484 20:00:47.862799 [DutyScan_Calibration_Flow] k_type=3
2485 20:00:47.879104
2486 20:00:47.879595 ==DQM 0 ==
2487 20:00:47.882341 Final DQM duty delay cell = -4
2488 20:00:47.885617 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2489 20:00:47.889181 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2490 20:00:47.892295 [-4] AVG Duty = 4937%(X100)
2491 20:00:47.892723
2492 20:00:47.893059 ==DQM 1 ==
2493 20:00:47.896196 Final DQM duty delay cell = 0
2494 20:00:47.898926 [0] MAX Duty = 5187%(X100), DQS PI = 6
2495 20:00:47.902234 [0] MIN Duty = 5000%(X100), DQS PI = 28
2496 20:00:47.905498 [0] AVG Duty = 5093%(X100)
2497 20:00:47.905918
2498 20:00:47.908869 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2499 20:00:47.909359
2500 20:00:47.912458 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2501 20:00:47.916014 [DutyScan_Calibration_Flow] ====Done====
2502 20:00:47.916521
2503 20:00:47.919097 [DutyScan_Calibration_Flow] k_type=2
2504 20:00:47.936374
2505 20:00:47.936925 ==DQ 0 ==
2506 20:00:47.939664 Final DQ duty delay cell = 0
2507 20:00:47.943204 [0] MAX Duty = 5187%(X100), DQS PI = 32
2508 20:00:47.945832 [0] MIN Duty = 4907%(X100), DQS PI = 6
2509 20:00:47.946296 [0] AVG Duty = 5047%(X100)
2510 20:00:47.946668
2511 20:00:47.949089 ==DQ 1 ==
2512 20:00:47.952583 Final DQ duty delay cell = 0
2513 20:00:47.956164 [0] MAX Duty = 5093%(X100), DQS PI = 6
2514 20:00:47.959676 [0] MIN Duty = 4969%(X100), DQS PI = 0
2515 20:00:47.960303 [0] AVG Duty = 5031%(X100)
2516 20:00:47.960677
2517 20:00:47.963471 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2518 20:00:47.964018
2519 20:00:47.966163 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2520 20:00:47.972608 [DutyScan_Calibration_Flow] ====Done====
2521 20:00:47.975999 nWR fixed to 30
2522 20:00:47.976550 [ModeRegInit_LP4] CH0 RK0
2523 20:00:47.979600 [ModeRegInit_LP4] CH0 RK1
2524 20:00:47.982212 [ModeRegInit_LP4] CH1 RK0
2525 20:00:47.982673 [ModeRegInit_LP4] CH1 RK1
2526 20:00:47.985846 match AC timing 7
2527 20:00:47.989296 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2528 20:00:47.992257 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2529 20:00:47.999169 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2530 20:00:48.002218 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2531 20:00:48.009193 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2532 20:00:48.009752 ==
2533 20:00:48.013789 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 20:00:48.015637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 20:00:48.016120 ==
2536 20:00:48.022300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2537 20:00:48.028966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=23, u1VrefScanEnd=33
2538 20:00:48.035898 [CA 0] Center 39 (9~70) winsize 62
2539 20:00:48.039510 [CA 1] Center 39 (9~69) winsize 61
2540 20:00:48.042567 [CA 2] Center 35 (5~66) winsize 62
2541 20:00:48.045589 [CA 3] Center 35 (5~66) winsize 62
2542 20:00:48.049116 [CA 4] Center 33 (4~63) winsize 60
2543 20:00:48.053016 [CA 5] Center 33 (3~63) winsize 61
2544 20:00:48.053570
2545 20:00:48.055717 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2546 20:00:48.056316
2547 20:00:48.059270 [CATrainingPosCal] consider 1 rank data
2548 20:00:48.062427 u2DelayCellTimex100 = 270/100 ps
2549 20:00:48.065897 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2550 20:00:48.072028 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2551 20:00:48.075127 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2552 20:00:48.079083 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2553 20:00:48.081935 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2554 20:00:48.085413 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2555 20:00:48.085963
2556 20:00:48.088369 CA PerBit enable=1, Macro0, CA PI delay=33
2557 20:00:48.088905
2558 20:00:48.092231 [CBTSetCACLKResult] CA Dly = 33
2559 20:00:48.095973 CS Dly: 8 (0~39)
2560 20:00:48.096548 ==
2561 20:00:48.098701 Dram Type= 6, Freq= 0, CH_0, rank 1
2562 20:00:48.102192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 20:00:48.102709 ==
2564 20:00:48.108637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2565 20:00:48.111967 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2566 20:00:48.121506 [CA 0] Center 39 (8~70) winsize 63
2567 20:00:48.125452 [CA 1] Center 39 (9~70) winsize 62
2568 20:00:48.128228 [CA 2] Center 35 (5~66) winsize 62
2569 20:00:48.131468 [CA 3] Center 34 (4~65) winsize 62
2570 20:00:48.135100 [CA 4] Center 33 (3~64) winsize 62
2571 20:00:48.138284 [CA 5] Center 33 (3~63) winsize 61
2572 20:00:48.138842
2573 20:00:48.141699 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2574 20:00:48.142260
2575 20:00:48.144421 [CATrainingPosCal] consider 2 rank data
2576 20:00:48.148120 u2DelayCellTimex100 = 270/100 ps
2577 20:00:48.151640 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2578 20:00:48.158089 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2579 20:00:48.161665 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2580 20:00:48.164722 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2581 20:00:48.168118 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2582 20:00:48.171236 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2583 20:00:48.171848
2584 20:00:48.174927 CA PerBit enable=1, Macro0, CA PI delay=33
2585 20:00:48.175478
2586 20:00:48.177847 [CBTSetCACLKResult] CA Dly = 33
2587 20:00:48.178404 CS Dly: 8 (0~40)
2588 20:00:48.181224
2589 20:00:48.184627 ----->DramcWriteLeveling(PI) begin...
2590 20:00:48.185194 ==
2591 20:00:48.187936 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 20:00:48.191222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 20:00:48.191687 ==
2594 20:00:48.194387 Write leveling (Byte 0): 33 => 33
2595 20:00:48.197671 Write leveling (Byte 1): 29 => 29
2596 20:00:48.200915 DramcWriteLeveling(PI) end<-----
2597 20:00:48.201475
2598 20:00:48.201846 ==
2599 20:00:48.204011 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 20:00:48.208319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 20:00:48.208892 ==
2602 20:00:48.211262 [Gating] SW mode calibration
2603 20:00:48.217590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2604 20:00:48.224497 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2605 20:00:48.227805 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2606 20:00:48.230462 0 15 4 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
2607 20:00:48.237356 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 20:00:48.240859 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 20:00:48.244416 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 20:00:48.251115 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 20:00:48.254294 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 20:00:48.257249 0 15 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
2613 20:00:48.263998 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (0 1) (0 0)
2614 20:00:48.267034 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 20:00:48.270220 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 20:00:48.277011 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 20:00:48.280651 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 20:00:48.283840 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 20:00:48.290344 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 20:00:48.293529 1 0 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
2621 20:00:48.296904 1 1 0 | B1->B0 | 2928 4545 | 1 0 | (0 0) (0 0)
2622 20:00:48.303996 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2623 20:00:48.306894 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 20:00:48.310420 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 20:00:48.316693 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 20:00:48.320008 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 20:00:48.324520 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 20:00:48.329860 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2629 20:00:48.333586 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2630 20:00:48.336464 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 20:00:48.344452 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 20:00:48.346313 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 20:00:48.349693 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 20:00:48.356048 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 20:00:48.359838 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 20:00:48.364115 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 20:00:48.369356 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 20:00:48.372988 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 20:00:48.376280 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 20:00:48.383566 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 20:00:48.386106 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 20:00:48.389046 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 20:00:48.396224 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 20:00:48.399222 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2645 20:00:48.402624 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2646 20:00:48.405749 Total UI for P1: 0, mck2ui 16
2647 20:00:48.409191 best dqsien dly found for B0: ( 1, 3, 28)
2648 20:00:48.413111 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2649 20:00:48.416101 Total UI for P1: 0, mck2ui 16
2650 20:00:48.419346 best dqsien dly found for B1: ( 1, 4, 0)
2651 20:00:48.422919 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2652 20:00:48.428707 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2653 20:00:48.429387
2654 20:00:48.432372 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2655 20:00:48.435482 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2656 20:00:48.438574 [Gating] SW calibration Done
2657 20:00:48.439056 ==
2658 20:00:48.442158 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 20:00:48.445477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 20:00:48.446103 ==
2661 20:00:48.448910 RX Vref Scan: 0
2662 20:00:48.449368
2663 20:00:48.449733 RX Vref 0 -> 0, step: 1
2664 20:00:48.450077
2665 20:00:48.451829 RX Delay -40 -> 252, step: 8
2666 20:00:48.455218 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2667 20:00:48.458670 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2668 20:00:48.465347 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2669 20:00:48.468969 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2670 20:00:48.471886 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2671 20:00:48.475537 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2672 20:00:48.478749 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2673 20:00:48.485634 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2674 20:00:48.488755 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2675 20:00:48.491541 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2676 20:00:48.495079 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2677 20:00:48.499008 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2678 20:00:48.505054 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2679 20:00:48.508660 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2680 20:00:48.511649 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2681 20:00:48.515478 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2682 20:00:48.516078 ==
2683 20:00:48.518309 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 20:00:48.525382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 20:00:48.525940 ==
2686 20:00:48.526312 DQS Delay:
2687 20:00:48.528115 DQS0 = 0, DQS1 = 0
2688 20:00:48.528573 DQM Delay:
2689 20:00:48.532301 DQM0 = 119, DQM1 = 106
2690 20:00:48.532762 DQ Delay:
2691 20:00:48.534859 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2692 20:00:48.538270 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2693 20:00:48.541432 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2694 20:00:48.544638 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2695 20:00:48.545113
2696 20:00:48.545476
2697 20:00:48.545914 ==
2698 20:00:48.548108 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 20:00:48.554571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 20:00:48.555183 ==
2701 20:00:48.555575
2702 20:00:48.555986
2703 20:00:48.556322 TX Vref Scan disable
2704 20:00:48.558179 == TX Byte 0 ==
2705 20:00:48.561153 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2706 20:00:48.568383 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2707 20:00:48.568942 == TX Byte 1 ==
2708 20:00:48.571549 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2709 20:00:48.577779 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2710 20:00:48.578350 ==
2711 20:00:48.581081 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 20:00:48.585055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 20:00:48.585608 ==
2714 20:00:48.595868 TX Vref=22, minBit 7, minWin=25, winSum=417
2715 20:00:48.599461 TX Vref=24, minBit 0, minWin=26, winSum=426
2716 20:00:48.602913 TX Vref=26, minBit 10, minWin=25, winSum=429
2717 20:00:48.606231 TX Vref=28, minBit 5, minWin=26, winSum=435
2718 20:00:48.609210 TX Vref=30, minBit 5, minWin=26, winSum=431
2719 20:00:48.616023 TX Vref=32, minBit 4, minWin=26, winSum=429
2720 20:00:48.619751 [TxChooseVref] Worse bit 5, Min win 26, Win sum 435, Final Vref 28
2721 20:00:48.620312
2722 20:00:48.622550 Final TX Range 1 Vref 28
2723 20:00:48.623104
2724 20:00:48.623472 ==
2725 20:00:48.626127 Dram Type= 6, Freq= 0, CH_0, rank 0
2726 20:00:48.629810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2727 20:00:48.630370 ==
2728 20:00:48.632719
2729 20:00:48.633178
2730 20:00:48.633549 TX Vref Scan disable
2731 20:00:48.635708 == TX Byte 0 ==
2732 20:00:48.639277 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2733 20:00:48.642866 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2734 20:00:48.646185 == TX Byte 1 ==
2735 20:00:48.649726 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2736 20:00:48.652656 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2737 20:00:48.656078
2738 20:00:48.656627 [DATLAT]
2739 20:00:48.657003 Freq=1200, CH0 RK0
2740 20:00:48.657352
2741 20:00:48.659218 DATLAT Default: 0xd
2742 20:00:48.659792 0, 0xFFFF, sum = 0
2743 20:00:48.662327 1, 0xFFFF, sum = 0
2744 20:00:48.665722 2, 0xFFFF, sum = 0
2745 20:00:48.666307 3, 0xFFFF, sum = 0
2746 20:00:48.669335 4, 0xFFFF, sum = 0
2747 20:00:48.669893 5, 0xFFFF, sum = 0
2748 20:00:48.672452 6, 0xFFFF, sum = 0
2749 20:00:48.673095 7, 0xFFFF, sum = 0
2750 20:00:48.675569 8, 0xFFFF, sum = 0
2751 20:00:48.676221 9, 0xFFFF, sum = 0
2752 20:00:48.679193 10, 0xFFFF, sum = 0
2753 20:00:48.679797 11, 0xFFFF, sum = 0
2754 20:00:48.682693 12, 0x0, sum = 1
2755 20:00:48.683160 13, 0x0, sum = 2
2756 20:00:48.685531 14, 0x0, sum = 3
2757 20:00:48.686097 15, 0x0, sum = 4
2758 20:00:48.688717 best_step = 13
2759 20:00:48.689242
2760 20:00:48.689617 ==
2761 20:00:48.692198 Dram Type= 6, Freq= 0, CH_0, rank 0
2762 20:00:48.695365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2763 20:00:48.695884 ==
2764 20:00:48.696266 RX Vref Scan: 1
2765 20:00:48.696743
2766 20:00:48.698848 Set Vref Range= 32 -> 127
2767 20:00:48.699500
2768 20:00:48.702127 RX Vref 32 -> 127, step: 1
2769 20:00:48.702738
2770 20:00:48.705947 RX Delay -21 -> 252, step: 4
2771 20:00:48.706447
2772 20:00:48.709391 Set Vref, RX VrefLevel [Byte0]: 32
2773 20:00:48.712326 [Byte1]: 32
2774 20:00:48.712878
2775 20:00:48.715585 Set Vref, RX VrefLevel [Byte0]: 33
2776 20:00:48.719575 [Byte1]: 33
2777 20:00:48.722444
2778 20:00:48.722998 Set Vref, RX VrefLevel [Byte0]: 34
2779 20:00:48.725857 [Byte1]: 34
2780 20:00:48.730434
2781 20:00:48.731047 Set Vref, RX VrefLevel [Byte0]: 35
2782 20:00:48.733358 [Byte1]: 35
2783 20:00:48.738342
2784 20:00:48.738896 Set Vref, RX VrefLevel [Byte0]: 36
2785 20:00:48.741599 [Byte1]: 36
2786 20:00:48.746015
2787 20:00:48.746644 Set Vref, RX VrefLevel [Byte0]: 37
2788 20:00:48.749415 [Byte1]: 37
2789 20:00:48.753982
2790 20:00:48.754534 Set Vref, RX VrefLevel [Byte0]: 38
2791 20:00:48.757318 [Byte1]: 38
2792 20:00:48.762013
2793 20:00:48.762565 Set Vref, RX VrefLevel [Byte0]: 39
2794 20:00:48.765496 [Byte1]: 39
2795 20:00:48.770149
2796 20:00:48.770698 Set Vref, RX VrefLevel [Byte0]: 40
2797 20:00:48.773259 [Byte1]: 40
2798 20:00:48.778360
2799 20:00:48.778922 Set Vref, RX VrefLevel [Byte0]: 41
2800 20:00:48.781056 [Byte1]: 41
2801 20:00:48.785741
2802 20:00:48.786296 Set Vref, RX VrefLevel [Byte0]: 42
2803 20:00:48.789781 [Byte1]: 42
2804 20:00:48.793487
2805 20:00:48.793960 Set Vref, RX VrefLevel [Byte0]: 43
2806 20:00:48.797233 [Byte1]: 43
2807 20:00:48.801975
2808 20:00:48.802530 Set Vref, RX VrefLevel [Byte0]: 44
2809 20:00:48.804895 [Byte1]: 44
2810 20:00:48.809625
2811 20:00:48.810175 Set Vref, RX VrefLevel [Byte0]: 45
2812 20:00:48.812906 [Byte1]: 45
2813 20:00:48.817725
2814 20:00:48.818281 Set Vref, RX VrefLevel [Byte0]: 46
2815 20:00:48.820917 [Byte1]: 46
2816 20:00:48.825610
2817 20:00:48.826157 Set Vref, RX VrefLevel [Byte0]: 47
2818 20:00:48.829371 [Byte1]: 47
2819 20:00:48.833380
2820 20:00:48.833840 Set Vref, RX VrefLevel [Byte0]: 48
2821 20:00:48.836331 [Byte1]: 48
2822 20:00:48.841185
2823 20:00:48.841740 Set Vref, RX VrefLevel [Byte0]: 49
2824 20:00:48.844348 [Byte1]: 49
2825 20:00:48.849020
2826 20:00:48.849568 Set Vref, RX VrefLevel [Byte0]: 50
2827 20:00:48.852542 [Byte1]: 50
2828 20:00:48.857175
2829 20:00:48.857724 Set Vref, RX VrefLevel [Byte0]: 51
2830 20:00:48.860532 [Byte1]: 51
2831 20:00:48.865438
2832 20:00:48.865989 Set Vref, RX VrefLevel [Byte0]: 52
2833 20:00:48.868287 [Byte1]: 52
2834 20:00:48.872834
2835 20:00:48.873380 Set Vref, RX VrefLevel [Byte0]: 53
2836 20:00:48.876368 [Byte1]: 53
2837 20:00:48.880869
2838 20:00:48.881422 Set Vref, RX VrefLevel [Byte0]: 54
2839 20:00:48.884418 [Byte1]: 54
2840 20:00:48.889315
2841 20:00:48.891813 Set Vref, RX VrefLevel [Byte0]: 55
2842 20:00:48.894885 [Byte1]: 55
2843 20:00:48.895346
2844 20:00:48.898639 Set Vref, RX VrefLevel [Byte0]: 56
2845 20:00:48.901949 [Byte1]: 56
2846 20:00:48.902514
2847 20:00:48.905090 Set Vref, RX VrefLevel [Byte0]: 57
2848 20:00:48.908497 [Byte1]: 57
2849 20:00:48.912462
2850 20:00:48.912932 Set Vref, RX VrefLevel [Byte0]: 58
2851 20:00:48.915816 [Byte1]: 58
2852 20:00:48.920307
2853 20:00:48.920770 Set Vref, RX VrefLevel [Byte0]: 59
2854 20:00:48.924225 [Byte1]: 59
2855 20:00:48.928341
2856 20:00:48.928900 Set Vref, RX VrefLevel [Byte0]: 60
2857 20:00:48.931494 [Byte1]: 60
2858 20:00:48.936280
2859 20:00:48.936740 Set Vref, RX VrefLevel [Byte0]: 61
2860 20:00:48.939497 [Byte1]: 61
2861 20:00:48.944617
2862 20:00:48.945074 Set Vref, RX VrefLevel [Byte0]: 62
2863 20:00:48.948131 [Byte1]: 62
2864 20:00:48.951884
2865 20:00:48.952330 Set Vref, RX VrefLevel [Byte0]: 63
2866 20:00:48.955366 [Byte1]: 63
2867 20:00:48.960092
2868 20:00:48.960507 Set Vref, RX VrefLevel [Byte0]: 64
2869 20:00:48.963486 [Byte1]: 64
2870 20:00:48.968463
2871 20:00:48.968895 Set Vref, RX VrefLevel [Byte0]: 65
2872 20:00:48.971625 [Byte1]: 65
2873 20:00:48.976062
2874 20:00:48.976638 Set Vref, RX VrefLevel [Byte0]: 66
2875 20:00:48.979698 [Byte1]: 66
2876 20:00:48.983936
2877 20:00:48.984446 Set Vref, RX VrefLevel [Byte0]: 67
2878 20:00:48.987663 [Byte1]: 67
2879 20:00:48.991545
2880 20:00:48.992009 Set Vref, RX VrefLevel [Byte0]: 68
2881 20:00:48.995275 [Byte1]: 68
2882 20:00:48.999842
2883 20:00:49.000302 Set Vref, RX VrefLevel [Byte0]: 69
2884 20:00:49.003474 [Byte1]: 69
2885 20:00:49.008268
2886 20:00:49.008725 Set Vref, RX VrefLevel [Byte0]: 70
2887 20:00:49.010850 [Byte1]: 70
2888 20:00:49.015385
2889 20:00:49.015952 Set Vref, RX VrefLevel [Byte0]: 71
2890 20:00:49.018793 [Byte1]: 71
2891 20:00:49.024655
2892 20:00:49.025167 Set Vref, RX VrefLevel [Byte0]: 72
2893 20:00:49.027334 [Byte1]: 72
2894 20:00:49.031648
2895 20:00:49.032216 Set Vref, RX VrefLevel [Byte0]: 73
2896 20:00:49.034508 [Byte1]: 73
2897 20:00:49.039593
2898 20:00:49.040040 Set Vref, RX VrefLevel [Byte0]: 74
2899 20:00:49.043458 [Byte1]: 74
2900 20:00:49.047661
2901 20:00:49.048126 Set Vref, RX VrefLevel [Byte0]: 75
2902 20:00:49.050739 [Byte1]: 75
2903 20:00:49.054905
2904 20:00:49.055323 Final RX Vref Byte 0 = 63 to rank0
2905 20:00:49.058170 Final RX Vref Byte 1 = 49 to rank0
2906 20:00:49.061767 Final RX Vref Byte 0 = 63 to rank1
2907 20:00:49.065210 Final RX Vref Byte 1 = 49 to rank1==
2908 20:00:49.068620 Dram Type= 6, Freq= 0, CH_0, rank 0
2909 20:00:49.075155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 20:00:49.075579 ==
2911 20:00:49.075974 DQS Delay:
2912 20:00:49.078066 DQS0 = 0, DQS1 = 0
2913 20:00:49.078497 DQM Delay:
2914 20:00:49.078833 DQM0 = 119, DQM1 = 106
2915 20:00:49.081802 DQ Delay:
2916 20:00:49.084931 DQ0 =116, DQ1 =118, DQ2 =116, DQ3 =116
2917 20:00:49.088125 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =126
2918 20:00:49.091860 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2919 20:00:49.095118 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2920 20:00:49.095537
2921 20:00:49.095940
2922 20:00:49.104717 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2923 20:00:49.105537 CH0 RK0: MR19=403, MR18=11FD
2924 20:00:49.111483 CH0_RK0: MR19=0x403, MR18=0x11FD, DQSOSC=403, MR23=63, INC=40, DEC=26
2925 20:00:49.111990
2926 20:00:49.114539 ----->DramcWriteLeveling(PI) begin...
2927 20:00:49.114961 ==
2928 20:00:49.117910 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 20:00:49.124622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 20:00:49.125239 ==
2931 20:00:49.128189 Write leveling (Byte 0): 30 => 30
2932 20:00:49.131151 Write leveling (Byte 1): 30 => 30
2933 20:00:49.131572 DramcWriteLeveling(PI) end<-----
2934 20:00:49.131965
2935 20:00:49.134417 ==
2936 20:00:49.137860 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 20:00:49.141123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 20:00:49.141544 ==
2939 20:00:49.144532 [Gating] SW mode calibration
2940 20:00:49.151322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2941 20:00:49.154767 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2942 20:00:49.161020 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2943 20:00:49.164283 0 15 4 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
2944 20:00:49.167554 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2945 20:00:49.174374 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2946 20:00:49.177935 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2947 20:00:49.181339 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 20:00:49.187836 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2949 20:00:49.190689 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
2950 20:00:49.194465 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2951 20:00:49.201334 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2952 20:00:49.204227 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2953 20:00:49.207340 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 20:00:49.214292 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 20:00:49.218215 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 20:00:49.220915 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 20:00:49.227330 1 0 28 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
2958 20:00:49.230404 1 1 0 | B1->B0 | 3a39 4646 | 1 0 | (1 1) (0 0)
2959 20:00:49.233999 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 20:00:49.240215 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 20:00:49.243626 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 20:00:49.246969 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 20:00:49.253458 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 20:00:49.256822 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2965 20:00:49.260417 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2966 20:00:49.267110 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2967 20:00:49.270266 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 20:00:49.273588 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 20:00:49.280424 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 20:00:49.283265 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 20:00:49.286679 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 20:00:49.293354 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 20:00:49.296725 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 20:00:49.300445 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 20:00:49.303229 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 20:00:49.310877 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 20:00:49.313826 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 20:00:49.317213 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 20:00:49.323955 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 20:00:49.326612 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 20:00:49.329917 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2982 20:00:49.336668 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2983 20:00:49.340754 Total UI for P1: 0, mck2ui 16
2984 20:00:49.343506 best dqsien dly found for B0: ( 1, 3, 28)
2985 20:00:49.346497 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2986 20:00:49.350121 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 20:00:49.353537 Total UI for P1: 0, mck2ui 16
2988 20:00:49.356414 best dqsien dly found for B1: ( 1, 4, 2)
2989 20:00:49.360025 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2990 20:00:49.363484 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2991 20:00:49.364003
2992 20:00:49.370189 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2993 20:00:49.373326 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2994 20:00:49.373793 [Gating] SW calibration Done
2995 20:00:49.376413 ==
2996 20:00:49.379792 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 20:00:49.382757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 20:00:49.383299 ==
2999 20:00:49.383677 RX Vref Scan: 0
3000 20:00:49.384087
3001 20:00:49.386396 RX Vref 0 -> 0, step: 1
3002 20:00:49.387087
3003 20:00:49.389444 RX Delay -40 -> 252, step: 8
3004 20:00:49.393065 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3005 20:00:49.396304 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
3006 20:00:49.403866 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
3007 20:00:49.406225 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3008 20:00:49.409888 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3009 20:00:49.413075 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3010 20:00:49.416459 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3011 20:00:49.423046 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3012 20:00:49.425897 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3013 20:00:49.429655 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3014 20:00:49.432599 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3015 20:00:49.435944 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3016 20:00:49.442589 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3017 20:00:49.446264 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3018 20:00:49.449894 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3019 20:00:49.452212 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3020 20:00:49.452675 ==
3021 20:00:49.456367 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 20:00:49.462303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 20:00:49.462861 ==
3024 20:00:49.463302 DQS Delay:
3025 20:00:49.466075 DQS0 = 0, DQS1 = 0
3026 20:00:49.466627 DQM Delay:
3027 20:00:49.466995 DQM0 = 117, DQM1 = 108
3028 20:00:49.468727 DQ Delay:
3029 20:00:49.472347 DQ0 =115, DQ1 =123, DQ2 =115, DQ3 =115
3030 20:00:49.475468 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3031 20:00:49.479350 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3032 20:00:49.482185 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3033 20:00:49.482646
3034 20:00:49.483013
3035 20:00:49.483452 ==
3036 20:00:49.485977 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 20:00:49.488747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 20:00:49.489213 ==
3039 20:00:49.492233
3040 20:00:49.492692
3041 20:00:49.493059 TX Vref Scan disable
3042 20:00:49.495711 == TX Byte 0 ==
3043 20:00:49.498991 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3044 20:00:49.502249 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3045 20:00:49.505910 == TX Byte 1 ==
3046 20:00:49.508873 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3047 20:00:49.512104 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3048 20:00:49.512665 ==
3049 20:00:49.515530 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 20:00:49.522169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 20:00:49.522722 ==
3052 20:00:49.532666 TX Vref=22, minBit 2, minWin=25, winSum=421
3053 20:00:49.536683 TX Vref=24, minBit 1, minWin=26, winSum=429
3054 20:00:49.539394 TX Vref=26, minBit 0, minWin=26, winSum=432
3055 20:00:49.542887 TX Vref=28, minBit 2, minWin=26, winSum=432
3056 20:00:49.546745 TX Vref=30, minBit 4, minWin=26, winSum=432
3057 20:00:49.549641 TX Vref=32, minBit 10, minWin=26, winSum=436
3058 20:00:49.556052 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 32
3059 20:00:49.556604
3060 20:00:49.559580 Final TX Range 1 Vref 32
3061 20:00:49.560167
3062 20:00:49.560543 ==
3063 20:00:49.562968 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 20:00:49.566170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 20:00:49.566716 ==
3066 20:00:49.569376
3067 20:00:49.569920
3068 20:00:49.570292 TX Vref Scan disable
3069 20:00:49.572369 == TX Byte 0 ==
3070 20:00:49.576242 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3071 20:00:49.583163 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3072 20:00:49.583715 == TX Byte 1 ==
3073 20:00:49.585992 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3074 20:00:49.592309 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3075 20:00:49.592849
3076 20:00:49.593215 [DATLAT]
3077 20:00:49.593557 Freq=1200, CH0 RK1
3078 20:00:49.593915
3079 20:00:49.595498 DATLAT Default: 0xd
3080 20:00:49.596012 0, 0xFFFF, sum = 0
3081 20:00:49.598789 1, 0xFFFF, sum = 0
3082 20:00:49.602542 2, 0xFFFF, sum = 0
3083 20:00:49.603098 3, 0xFFFF, sum = 0
3084 20:00:49.605747 4, 0xFFFF, sum = 0
3085 20:00:49.606219 5, 0xFFFF, sum = 0
3086 20:00:49.608756 6, 0xFFFF, sum = 0
3087 20:00:49.609224 7, 0xFFFF, sum = 0
3088 20:00:49.612414 8, 0xFFFF, sum = 0
3089 20:00:49.612881 9, 0xFFFF, sum = 0
3090 20:00:49.615641 10, 0xFFFF, sum = 0
3091 20:00:49.616311 11, 0xFFFF, sum = 0
3092 20:00:49.619155 12, 0x0, sum = 1
3093 20:00:49.619624 13, 0x0, sum = 2
3094 20:00:49.622458 14, 0x0, sum = 3
3095 20:00:49.623028 15, 0x0, sum = 4
3096 20:00:49.625407 best_step = 13
3097 20:00:49.625956
3098 20:00:49.626331 ==
3099 20:00:49.629000 Dram Type= 6, Freq= 0, CH_0, rank 1
3100 20:00:49.632048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 20:00:49.632514 ==
3102 20:00:49.632881 RX Vref Scan: 0
3103 20:00:49.635910
3104 20:00:49.636318 RX Vref 0 -> 0, step: 1
3105 20:00:49.636665
3106 20:00:49.638588 RX Delay -21 -> 252, step: 4
3107 20:00:49.645643 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3108 20:00:49.648748 iDelay=195, Bit 1, Center 120 (47 ~ 194) 148
3109 20:00:49.652750 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3110 20:00:49.655132 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3111 20:00:49.658624 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3112 20:00:49.665273 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3113 20:00:49.668866 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3114 20:00:49.672288 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3115 20:00:49.675209 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3116 20:00:49.679002 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3117 20:00:49.682237 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3118 20:00:49.688700 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3119 20:00:49.692296 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3120 20:00:49.695047 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3121 20:00:49.698576 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3122 20:00:49.705093 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3123 20:00:49.705660 ==
3124 20:00:49.708204 Dram Type= 6, Freq= 0, CH_0, rank 1
3125 20:00:49.711270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 20:00:49.711770 ==
3127 20:00:49.712150 DQS Delay:
3128 20:00:49.715451 DQS0 = 0, DQS1 = 0
3129 20:00:49.716165 DQM Delay:
3130 20:00:49.718505 DQM0 = 116, DQM1 = 108
3131 20:00:49.719061 DQ Delay:
3132 20:00:49.721642 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =112
3133 20:00:49.724828 DQ4 =116, DQ5 =112, DQ6 =124, DQ7 =124
3134 20:00:49.729067 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3135 20:00:49.731692 DQ12 =114, DQ13 =116, DQ14 =118, DQ15 =116
3136 20:00:49.732197
3137 20:00:49.732566
3138 20:00:49.741687 [DQSOSCAuto] RK1, (LSB)MR18= 0xee8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 404 ps
3139 20:00:49.744813 CH0 RK1: MR19=403, MR18=EE8
3140 20:00:49.747990 CH0_RK1: MR19=0x403, MR18=0xEE8, DQSOSC=404, MR23=63, INC=40, DEC=26
3141 20:00:49.751363 [RxdqsGatingPostProcess] freq 1200
3142 20:00:49.757649 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3143 20:00:49.761377 best DQS0 dly(2T, 0.5T) = (0, 11)
3144 20:00:49.765417 best DQS1 dly(2T, 0.5T) = (0, 12)
3145 20:00:49.768232 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3146 20:00:49.771306 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3147 20:00:49.774798 best DQS0 dly(2T, 0.5T) = (0, 11)
3148 20:00:49.777970 best DQS1 dly(2T, 0.5T) = (0, 12)
3149 20:00:49.781557 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3150 20:00:49.784324 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3151 20:00:49.784791 Pre-setting of DQS Precalculation
3152 20:00:49.791412 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3153 20:00:49.792018 ==
3154 20:00:49.794394 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 20:00:49.797998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 20:00:49.798461 ==
3157 20:00:49.804736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 20:00:49.811009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3159 20:00:49.818571 [CA 0] Center 37 (7~68) winsize 62
3160 20:00:49.821835 [CA 1] Center 37 (7~68) winsize 62
3161 20:00:49.825620 [CA 2] Center 34 (4~64) winsize 61
3162 20:00:49.829158 [CA 3] Center 33 (3~64) winsize 62
3163 20:00:49.832091 [CA 4] Center 34 (5~64) winsize 60
3164 20:00:49.835251 [CA 5] Center 33 (3~64) winsize 62
3165 20:00:49.835875
3166 20:00:49.838592 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3167 20:00:49.839249
3168 20:00:49.841913 [CATrainingPosCal] consider 1 rank data
3169 20:00:49.845451 u2DelayCellTimex100 = 270/100 ps
3170 20:00:49.848600 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3171 20:00:49.852362 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3172 20:00:49.858389 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3173 20:00:49.862042 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3174 20:00:49.865300 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3175 20:00:49.868391 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3176 20:00:49.868847
3177 20:00:49.872087 CA PerBit enable=1, Macro0, CA PI delay=33
3178 20:00:49.872645
3179 20:00:49.876187 [CBTSetCACLKResult] CA Dly = 33
3180 20:00:49.876744 CS Dly: 6 (0~37)
3181 20:00:49.878608 ==
3182 20:00:49.879162 Dram Type= 6, Freq= 0, CH_1, rank 1
3183 20:00:49.885739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 20:00:49.886301 ==
3185 20:00:49.888500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3186 20:00:49.895285 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3187 20:00:49.904579 [CA 0] Center 37 (7~68) winsize 62
3188 20:00:49.907910 [CA 1] Center 38 (8~68) winsize 61
3189 20:00:49.911644 [CA 2] Center 34 (4~65) winsize 62
3190 20:00:49.914607 [CA 3] Center 33 (3~64) winsize 62
3191 20:00:49.917748 [CA 4] Center 34 (4~65) winsize 62
3192 20:00:49.920731 [CA 5] Center 33 (3~64) winsize 62
3193 20:00:49.921190
3194 20:00:49.924606 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3195 20:00:49.925156
3196 20:00:49.927467 [CATrainingPosCal] consider 2 rank data
3197 20:00:49.931330 u2DelayCellTimex100 = 270/100 ps
3198 20:00:49.934346 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3199 20:00:49.937390 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3200 20:00:49.944338 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3201 20:00:49.947537 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3202 20:00:49.950563 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3203 20:00:49.954233 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3204 20:00:49.954791
3205 20:00:49.957316 CA PerBit enable=1, Macro0, CA PI delay=33
3206 20:00:49.957784
3207 20:00:49.960544 [CBTSetCACLKResult] CA Dly = 33
3208 20:00:49.961000 CS Dly: 7 (0~40)
3209 20:00:49.964089
3210 20:00:49.967129 ----->DramcWriteLeveling(PI) begin...
3211 20:00:49.967595 ==
3212 20:00:49.970404 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 20:00:49.974335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 20:00:49.974915 ==
3215 20:00:49.977994 Write leveling (Byte 0): 25 => 25
3216 20:00:49.981015 Write leveling (Byte 1): 27 => 27
3217 20:00:49.983856 DramcWriteLeveling(PI) end<-----
3218 20:00:49.984411
3219 20:00:49.984796 ==
3220 20:00:49.987445 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 20:00:49.991292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 20:00:49.991977 ==
3223 20:00:49.993721 [Gating] SW mode calibration
3224 20:00:50.000690 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3225 20:00:50.007953 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3226 20:00:50.010418 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3227 20:00:50.014109 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3228 20:00:50.020436 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3229 20:00:50.024331 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3230 20:00:50.027829 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3231 20:00:50.030894 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3232 20:00:50.037030 0 15 24 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
3233 20:00:50.040940 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3234 20:00:50.043587 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3235 20:00:50.050018 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3236 20:00:50.053720 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3237 20:00:50.056514 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3238 20:00:50.063346 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3239 20:00:50.067084 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3240 20:00:50.073087 1 0 24 | B1->B0 | 2424 3131 | 0 1 | (0 0) (0 0)
3241 20:00:50.076515 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3242 20:00:50.079991 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3243 20:00:50.086357 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 20:00:50.089762 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 20:00:50.092870 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 20:00:50.096264 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 20:00:50.103268 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 20:00:50.106577 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3249 20:00:50.109553 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3250 20:00:50.116924 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 20:00:50.119919 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 20:00:50.123187 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 20:00:50.129421 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 20:00:50.132999 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 20:00:50.136089 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 20:00:50.142823 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 20:00:50.146428 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 20:00:50.149577 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 20:00:50.155782 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 20:00:50.159200 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 20:00:50.163068 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 20:00:50.169825 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 20:00:50.172586 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 20:00:50.176176 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3265 20:00:50.182845 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3266 20:00:50.183403 Total UI for P1: 0, mck2ui 16
3267 20:00:50.189329 best dqsien dly found for B0: ( 1, 3, 24)
3268 20:00:50.189896 Total UI for P1: 0, mck2ui 16
3269 20:00:50.195903 best dqsien dly found for B1: ( 1, 3, 24)
3270 20:00:50.199184 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3271 20:00:50.202447 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3272 20:00:50.202904
3273 20:00:50.205933 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3274 20:00:50.209203 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3275 20:00:50.212466 [Gating] SW calibration Done
3276 20:00:50.212877 ==
3277 20:00:50.216460 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 20:00:50.218999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 20:00:50.219417 ==
3280 20:00:50.222500 RX Vref Scan: 0
3281 20:00:50.222912
3282 20:00:50.223242 RX Vref 0 -> 0, step: 1
3283 20:00:50.223557
3284 20:00:50.225883 RX Delay -40 -> 252, step: 8
3285 20:00:50.229273 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3286 20:00:50.236039 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3287 20:00:50.239281 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3288 20:00:50.242656 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3289 20:00:50.245830 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3290 20:00:50.249295 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3291 20:00:50.255666 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3292 20:00:50.259303 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3293 20:00:50.262888 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3294 20:00:50.266623 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3295 20:00:50.269703 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3296 20:00:50.272439 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3297 20:00:50.278612 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3298 20:00:50.282321 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3299 20:00:50.285662 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3300 20:00:50.289194 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3301 20:00:50.292006 ==
3302 20:00:50.292550 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 20:00:50.298855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 20:00:50.299336 ==
3305 20:00:50.299701 DQS Delay:
3306 20:00:50.302251 DQS0 = 0, DQS1 = 0
3307 20:00:50.302752 DQM Delay:
3308 20:00:50.305765 DQM0 = 118, DQM1 = 109
3309 20:00:50.306321 DQ Delay:
3310 20:00:50.308582 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3311 20:00:50.312131 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3312 20:00:50.315640 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3313 20:00:50.318753 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3314 20:00:50.319473
3315 20:00:50.319946
3316 20:00:50.320304 ==
3317 20:00:50.321890 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 20:00:50.328829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 20:00:50.329393 ==
3320 20:00:50.329766
3321 20:00:50.330102
3322 20:00:50.330425 TX Vref Scan disable
3323 20:00:50.331647 == TX Byte 0 ==
3324 20:00:50.335655 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3325 20:00:50.341905 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3326 20:00:50.342566 == TX Byte 1 ==
3327 20:00:50.345085 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3328 20:00:50.351519 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3329 20:00:50.352111 ==
3330 20:00:50.354729 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 20:00:50.358188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 20:00:50.358644 ==
3333 20:00:50.369704 TX Vref=22, minBit 11, minWin=24, winSum=415
3334 20:00:50.373101 TX Vref=24, minBit 10, minWin=25, winSum=420
3335 20:00:50.376477 TX Vref=26, minBit 11, minWin=25, winSum=427
3336 20:00:50.379946 TX Vref=28, minBit 9, minWin=25, winSum=431
3337 20:00:50.383224 TX Vref=30, minBit 9, minWin=25, winSum=428
3338 20:00:50.389959 TX Vref=32, minBit 9, minWin=25, winSum=427
3339 20:00:50.393505 [TxChooseVref] Worse bit 9, Min win 25, Win sum 431, Final Vref 28
3340 20:00:50.393969
3341 20:00:50.396344 Final TX Range 1 Vref 28
3342 20:00:50.396816
3343 20:00:50.397254 ==
3344 20:00:50.399371 Dram Type= 6, Freq= 0, CH_1, rank 0
3345 20:00:50.403167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3346 20:00:50.406708 ==
3347 20:00:50.407419
3348 20:00:50.407993
3349 20:00:50.408349 TX Vref Scan disable
3350 20:00:50.409525 == TX Byte 0 ==
3351 20:00:50.413114 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3352 20:00:50.419627 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3353 20:00:50.420252 == TX Byte 1 ==
3354 20:00:50.422854 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3355 20:00:50.429525 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3356 20:00:50.430276
3357 20:00:50.430662 [DATLAT]
3358 20:00:50.431003 Freq=1200, CH1 RK0
3359 20:00:50.431336
3360 20:00:50.432334 DATLAT Default: 0xd
3361 20:00:50.435637 0, 0xFFFF, sum = 0
3362 20:00:50.436146 1, 0xFFFF, sum = 0
3363 20:00:50.439102 2, 0xFFFF, sum = 0
3364 20:00:50.439560 3, 0xFFFF, sum = 0
3365 20:00:50.442511 4, 0xFFFF, sum = 0
3366 20:00:50.442980 5, 0xFFFF, sum = 0
3367 20:00:50.446160 6, 0xFFFF, sum = 0
3368 20:00:50.446629 7, 0xFFFF, sum = 0
3369 20:00:50.449027 8, 0xFFFF, sum = 0
3370 20:00:50.449497 9, 0xFFFF, sum = 0
3371 20:00:50.452770 10, 0xFFFF, sum = 0
3372 20:00:50.453234 11, 0xFFFF, sum = 0
3373 20:00:50.455953 12, 0x0, sum = 1
3374 20:00:50.456572 13, 0x0, sum = 2
3375 20:00:50.459109 14, 0x0, sum = 3
3376 20:00:50.459561 15, 0x0, sum = 4
3377 20:00:50.462163 best_step = 13
3378 20:00:50.462569
3379 20:00:50.462892 ==
3380 20:00:50.466100 Dram Type= 6, Freq= 0, CH_1, rank 0
3381 20:00:50.468596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3382 20:00:50.469010 ==
3383 20:00:50.472303 RX Vref Scan: 1
3384 20:00:50.472805
3385 20:00:50.473137 Set Vref Range= 32 -> 127
3386 20:00:50.473448
3387 20:00:50.475244 RX Vref 32 -> 127, step: 1
3388 20:00:50.475654
3389 20:00:50.479203 RX Delay -21 -> 252, step: 4
3390 20:00:50.479711
3391 20:00:50.482521 Set Vref, RX VrefLevel [Byte0]: 32
3392 20:00:50.485908 [Byte1]: 32
3393 20:00:50.486413
3394 20:00:50.488739 Set Vref, RX VrefLevel [Byte0]: 33
3395 20:00:50.492340 [Byte1]: 33
3396 20:00:50.496073
3397 20:00:50.496541 Set Vref, RX VrefLevel [Byte0]: 34
3398 20:00:50.499714 [Byte1]: 34
3399 20:00:50.504515
3400 20:00:50.505069 Set Vref, RX VrefLevel [Byte0]: 35
3401 20:00:50.510522 [Byte1]: 35
3402 20:00:50.511064
3403 20:00:50.514224 Set Vref, RX VrefLevel [Byte0]: 36
3404 20:00:50.517323 [Byte1]: 36
3405 20:00:50.517891
3406 20:00:50.520591 Set Vref, RX VrefLevel [Byte0]: 37
3407 20:00:50.524275 [Byte1]: 37
3408 20:00:50.528057
3409 20:00:50.528631 Set Vref, RX VrefLevel [Byte0]: 38
3410 20:00:50.530900 [Byte1]: 38
3411 20:00:50.535889
3412 20:00:50.536436 Set Vref, RX VrefLevel [Byte0]: 39
3413 20:00:50.539634 [Byte1]: 39
3414 20:00:50.543396
3415 20:00:50.543899 Set Vref, RX VrefLevel [Byte0]: 40
3416 20:00:50.548100 [Byte1]: 40
3417 20:00:50.551267
3418 20:00:50.551746 Set Vref, RX VrefLevel [Byte0]: 41
3419 20:00:50.555240 [Byte1]: 41
3420 20:00:50.559956
3421 20:00:50.560504 Set Vref, RX VrefLevel [Byte0]: 42
3422 20:00:50.563299 [Byte1]: 42
3423 20:00:50.568088
3424 20:00:50.568637 Set Vref, RX VrefLevel [Byte0]: 43
3425 20:00:50.570897 [Byte1]: 43
3426 20:00:50.575372
3427 20:00:50.575988 Set Vref, RX VrefLevel [Byte0]: 44
3428 20:00:50.578612 [Byte1]: 44
3429 20:00:50.583375
3430 20:00:50.583977 Set Vref, RX VrefLevel [Byte0]: 45
3431 20:00:50.586538 [Byte1]: 45
3432 20:00:50.591460
3433 20:00:50.592059 Set Vref, RX VrefLevel [Byte0]: 46
3434 20:00:50.594698 [Byte1]: 46
3435 20:00:50.599362
3436 20:00:50.599973 Set Vref, RX VrefLevel [Byte0]: 47
3437 20:00:50.602460 [Byte1]: 47
3438 20:00:50.607289
3439 20:00:50.607872 Set Vref, RX VrefLevel [Byte0]: 48
3440 20:00:50.609886 [Byte1]: 48
3441 20:00:50.615574
3442 20:00:50.616150 Set Vref, RX VrefLevel [Byte0]: 49
3443 20:00:50.618614 [Byte1]: 49
3444 20:00:50.622726
3445 20:00:50.623277 Set Vref, RX VrefLevel [Byte0]: 50
3446 20:00:50.626150 [Byte1]: 50
3447 20:00:50.631036
3448 20:00:50.631588 Set Vref, RX VrefLevel [Byte0]: 51
3449 20:00:50.635032 [Byte1]: 51
3450 20:00:50.638637
3451 20:00:50.641773 Set Vref, RX VrefLevel [Byte0]: 52
3452 20:00:50.645144 [Byte1]: 52
3453 20:00:50.645605
3454 20:00:50.648195 Set Vref, RX VrefLevel [Byte0]: 53
3455 20:00:50.651367 [Byte1]: 53
3456 20:00:50.651858
3457 20:00:50.655200 Set Vref, RX VrefLevel [Byte0]: 54
3458 20:00:50.657968 [Byte1]: 54
3459 20:00:50.662606
3460 20:00:50.663160 Set Vref, RX VrefLevel [Byte0]: 55
3461 20:00:50.665811 [Byte1]: 55
3462 20:00:50.670219
3463 20:00:50.670773 Set Vref, RX VrefLevel [Byte0]: 56
3464 20:00:50.674482 [Byte1]: 56
3465 20:00:50.678318
3466 20:00:50.678870 Set Vref, RX VrefLevel [Byte0]: 57
3467 20:00:50.681822 [Byte1]: 57
3468 20:00:50.686347
3469 20:00:50.686901 Set Vref, RX VrefLevel [Byte0]: 58
3470 20:00:50.689533 [Byte1]: 58
3471 20:00:50.694103
3472 20:00:50.694557 Set Vref, RX VrefLevel [Byte0]: 59
3473 20:00:50.697993 [Byte1]: 59
3474 20:00:50.702276
3475 20:00:50.702825 Set Vref, RX VrefLevel [Byte0]: 60
3476 20:00:50.705886 [Byte1]: 60
3477 20:00:50.710094
3478 20:00:50.710649 Set Vref, RX VrefLevel [Byte0]: 61
3479 20:00:50.713135 [Byte1]: 61
3480 20:00:50.717897
3481 20:00:50.718476 Set Vref, RX VrefLevel [Byte0]: 62
3482 20:00:50.721487 [Byte1]: 62
3483 20:00:50.725631
3484 20:00:50.726184 Set Vref, RX VrefLevel [Byte0]: 63
3485 20:00:50.729309 [Byte1]: 63
3486 20:00:50.733616
3487 20:00:50.734164 Set Vref, RX VrefLevel [Byte0]: 64
3488 20:00:50.737867 [Byte1]: 64
3489 20:00:50.741616
3490 20:00:50.742169 Set Vref, RX VrefLevel [Byte0]: 65
3491 20:00:50.744412 [Byte1]: 65
3492 20:00:50.749422
3493 20:00:50.749875 Set Vref, RX VrefLevel [Byte0]: 66
3494 20:00:50.752407 [Byte1]: 66
3495 20:00:50.757450
3496 20:00:50.758009 Set Vref, RX VrefLevel [Byte0]: 67
3497 20:00:50.760367 [Byte1]: 67
3498 20:00:50.765365
3499 20:00:50.765923 Set Vref, RX VrefLevel [Byte0]: 68
3500 20:00:50.768649 [Byte1]: 68
3501 20:00:50.773159
3502 20:00:50.773707 Final RX Vref Byte 0 = 49 to rank0
3503 20:00:50.776572 Final RX Vref Byte 1 = 53 to rank0
3504 20:00:50.780136 Final RX Vref Byte 0 = 49 to rank1
3505 20:00:50.783539 Final RX Vref Byte 1 = 53 to rank1==
3506 20:00:50.786245 Dram Type= 6, Freq= 0, CH_1, rank 0
3507 20:00:50.793232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 20:00:50.793796 ==
3509 20:00:50.794163 DQS Delay:
3510 20:00:50.794503 DQS0 = 0, DQS1 = 0
3511 20:00:50.796957 DQM Delay:
3512 20:00:50.797427 DQM0 = 116, DQM1 = 110
3513 20:00:50.800194 DQ Delay:
3514 20:00:50.803452 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =110
3515 20:00:50.806848 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =116
3516 20:00:50.810127 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =98
3517 20:00:50.813601 DQ12 =116, DQ13 =116, DQ14 =120, DQ15 =118
3518 20:00:50.814157
3519 20:00:50.814521
3520 20:00:50.823030 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3521 20:00:50.823592 CH1 RK0: MR19=403, MR18=4F7
3522 20:00:50.829565 CH1_RK0: MR19=0x403, MR18=0x4F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3523 20:00:50.830122
3524 20:00:50.833347 ----->DramcWriteLeveling(PI) begin...
3525 20:00:50.833909 ==
3526 20:00:50.836309 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 20:00:50.840308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 20:00:50.843458 ==
3529 20:00:50.844096 Write leveling (Byte 0): 24 => 24
3530 20:00:50.845958 Write leveling (Byte 1): 27 => 27
3531 20:00:50.849396 DramcWriteLeveling(PI) end<-----
3532 20:00:50.849850
3533 20:00:50.850215 ==
3534 20:00:50.853054 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 20:00:50.859301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 20:00:50.859937 ==
3537 20:00:50.860456 [Gating] SW mode calibration
3538 20:00:50.869191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3539 20:00:50.872926 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3540 20:00:50.878955 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3541 20:00:50.882390 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 20:00:50.885912 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 20:00:50.892120 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3544 20:00:50.895901 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3545 20:00:50.898788 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3546 20:00:50.905775 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
3547 20:00:50.909081 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (1 0) (0 1)
3548 20:00:50.912077 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 20:00:50.918966 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 20:00:50.922255 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 20:00:50.925396 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3552 20:00:50.931876 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3553 20:00:50.935222 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3554 20:00:50.938732 1 0 24 | B1->B0 | 3939 2827 | 0 1 | (0 0) (0 0)
3555 20:00:50.944842 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3556 20:00:50.948111 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 20:00:50.952096 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 20:00:50.958708 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 20:00:50.961479 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 20:00:50.964638 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 20:00:50.971285 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3562 20:00:50.974899 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 20:00:50.978032 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3564 20:00:50.985469 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 20:00:50.987558 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 20:00:50.991530 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 20:00:50.998399 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 20:00:51.000808 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 20:00:51.004298 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 20:00:51.011298 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 20:00:51.014655 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 20:00:51.017531 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 20:00:51.024323 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 20:00:51.027381 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 20:00:51.031115 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 20:00:51.037696 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 20:00:51.041252 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 20:00:51.043916 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3579 20:00:51.047800 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3580 20:00:51.054214 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3581 20:00:51.057650 Total UI for P1: 0, mck2ui 16
3582 20:00:51.061103 best dqsien dly found for B0: ( 1, 3, 28)
3583 20:00:51.064144 Total UI for P1: 0, mck2ui 16
3584 20:00:51.067870 best dqsien dly found for B1: ( 1, 3, 26)
3585 20:00:51.070972 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3586 20:00:51.074469 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3587 20:00:51.075036
3588 20:00:51.077387 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3589 20:00:51.080573 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3590 20:00:51.084074 [Gating] SW calibration Done
3591 20:00:51.084539 ==
3592 20:00:51.087801 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 20:00:51.090646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 20:00:51.091226 ==
3595 20:00:51.093754 RX Vref Scan: 0
3596 20:00:51.094217
3597 20:00:51.096804 RX Vref 0 -> 0, step: 1
3598 20:00:51.097271
3599 20:00:51.097742 RX Delay -40 -> 252, step: 8
3600 20:00:51.103882 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3601 20:00:51.107289 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3602 20:00:51.110327 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3603 20:00:51.113973 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3604 20:00:51.120813 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3605 20:00:51.123528 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3606 20:00:51.127093 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3607 20:00:51.130628 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3608 20:00:51.133741 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3609 20:00:51.137472 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3610 20:00:51.143356 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3611 20:00:51.146458 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3612 20:00:51.150244 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3613 20:00:51.153705 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3614 20:00:51.159396 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3615 20:00:51.163284 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3616 20:00:51.163875 ==
3617 20:00:51.166342 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 20:00:51.169445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 20:00:51.170004 ==
3620 20:00:51.173281 DQS Delay:
3621 20:00:51.173740 DQS0 = 0, DQS1 = 0
3622 20:00:51.174106 DQM Delay:
3623 20:00:51.175815 DQM0 = 116, DQM1 = 110
3624 20:00:51.176278 DQ Delay:
3625 20:00:51.179231 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3626 20:00:51.183124 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3627 20:00:51.189125 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3628 20:00:51.192347 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3629 20:00:51.192865
3630 20:00:51.193245
3631 20:00:51.193589 ==
3632 20:00:51.195537 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 20:00:51.199046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 20:00:51.199513 ==
3635 20:00:51.199942
3636 20:00:51.200290
3637 20:00:51.202844 TX Vref Scan disable
3638 20:00:51.205546 == TX Byte 0 ==
3639 20:00:51.209334 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3640 20:00:51.212681 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3641 20:00:51.216179 == TX Byte 1 ==
3642 20:00:51.219068 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3643 20:00:51.222139 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3644 20:00:51.222699 ==
3645 20:00:51.225712 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 20:00:51.228532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 20:00:51.231448 ==
3648 20:00:51.241937 TX Vref=22, minBit 9, minWin=25, winSum=426
3649 20:00:51.245080 TX Vref=24, minBit 9, minWin=25, winSum=429
3650 20:00:51.248404 TX Vref=26, minBit 3, minWin=26, winSum=434
3651 20:00:51.252103 TX Vref=28, minBit 9, minWin=26, winSum=435
3652 20:00:51.254871 TX Vref=30, minBit 9, minWin=26, winSum=439
3653 20:00:51.261827 TX Vref=32, minBit 7, minWin=26, winSum=435
3654 20:00:51.265856 [TxChooseVref] Worse bit 9, Min win 26, Win sum 439, Final Vref 30
3655 20:00:51.266504
3656 20:00:51.268409 Final TX Range 1 Vref 30
3657 20:00:51.268832
3658 20:00:51.269186 ==
3659 20:00:51.271330 Dram Type= 6, Freq= 0, CH_1, rank 1
3660 20:00:51.275019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3661 20:00:51.278223 ==
3662 20:00:51.278750
3663 20:00:51.279096
3664 20:00:51.279510 TX Vref Scan disable
3665 20:00:51.282122 == TX Byte 0 ==
3666 20:00:51.284743 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3667 20:00:51.291975 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3668 20:00:51.292571 == TX Byte 1 ==
3669 20:00:51.294773 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3670 20:00:51.301514 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3671 20:00:51.301941
3672 20:00:51.302273 [DATLAT]
3673 20:00:51.302588 Freq=1200, CH1 RK1
3674 20:00:51.302895
3675 20:00:51.304913 DATLAT Default: 0xd
3676 20:00:51.305382 0, 0xFFFF, sum = 0
3677 20:00:51.307835 1, 0xFFFF, sum = 0
3678 20:00:51.311504 2, 0xFFFF, sum = 0
3679 20:00:51.312028 3, 0xFFFF, sum = 0
3680 20:00:51.315475 4, 0xFFFF, sum = 0
3681 20:00:51.316176 5, 0xFFFF, sum = 0
3682 20:00:51.318015 6, 0xFFFF, sum = 0
3683 20:00:51.318438 7, 0xFFFF, sum = 0
3684 20:00:51.321339 8, 0xFFFF, sum = 0
3685 20:00:51.321763 9, 0xFFFF, sum = 0
3686 20:00:51.325017 10, 0xFFFF, sum = 0
3687 20:00:51.325737 11, 0xFFFF, sum = 0
3688 20:00:51.328107 12, 0x0, sum = 1
3689 20:00:51.328556 13, 0x0, sum = 2
3690 20:00:51.331396 14, 0x0, sum = 3
3691 20:00:51.331875 15, 0x0, sum = 4
3692 20:00:51.334367 best_step = 13
3693 20:00:51.334787
3694 20:00:51.335120 ==
3695 20:00:51.337693 Dram Type= 6, Freq= 0, CH_1, rank 1
3696 20:00:51.341576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3697 20:00:51.342001 ==
3698 20:00:51.342342 RX Vref Scan: 0
3699 20:00:51.344572
3700 20:00:51.344991 RX Vref 0 -> 0, step: 1
3701 20:00:51.345328
3702 20:00:51.347562 RX Delay -21 -> 252, step: 4
3703 20:00:51.354614 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3704 20:00:51.357455 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3705 20:00:51.361491 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3706 20:00:51.364334 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3707 20:00:51.368084 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3708 20:00:51.374671 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3709 20:00:51.377246 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3710 20:00:51.381120 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3711 20:00:51.384160 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3712 20:00:51.387484 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3713 20:00:51.393914 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3714 20:00:51.396988 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3715 20:00:51.400357 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3716 20:00:51.403928 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3717 20:00:51.410338 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3718 20:00:51.413868 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3719 20:00:51.414382 ==
3720 20:00:51.417280 Dram Type= 6, Freq= 0, CH_1, rank 1
3721 20:00:51.420429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3722 20:00:51.420939 ==
3723 20:00:51.423680 DQS Delay:
3724 20:00:51.424229 DQS0 = 0, DQS1 = 0
3725 20:00:51.424569 DQM Delay:
3726 20:00:51.426982 DQM0 = 116, DQM1 = 109
3727 20:00:51.427490 DQ Delay:
3728 20:00:51.430196 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3729 20:00:51.433848 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =116
3730 20:00:51.436764 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3731 20:00:51.443225 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3732 20:00:51.443750
3733 20:00:51.444102
3734 20:00:51.450227 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3735 20:00:51.452804 CH1 RK1: MR19=303, MR18=F3EE
3736 20:00:51.459652 CH1_RK1: MR19=0x303, MR18=0xF3EE, DQSOSC=415, MR23=63, INC=38, DEC=25
3737 20:00:51.463080 [RxdqsGatingPostProcess] freq 1200
3738 20:00:51.466913 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3739 20:00:51.469783 best DQS0 dly(2T, 0.5T) = (0, 11)
3740 20:00:51.473308 best DQS1 dly(2T, 0.5T) = (0, 11)
3741 20:00:51.476029 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3742 20:00:51.479589 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3743 20:00:51.482966 best DQS0 dly(2T, 0.5T) = (0, 11)
3744 20:00:51.486189 best DQS1 dly(2T, 0.5T) = (0, 11)
3745 20:00:51.489456 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3746 20:00:51.492906 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3747 20:00:51.496609 Pre-setting of DQS Precalculation
3748 20:00:51.499026 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3749 20:00:51.509279 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3750 20:00:51.516027 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3751 20:00:51.516553
3752 20:00:51.516897
3753 20:00:51.519182 [Calibration Summary] 2400 Mbps
3754 20:00:51.519699 CH 0, Rank 0
3755 20:00:51.522409 SW Impedance : PASS
3756 20:00:51.525801 DUTY Scan : NO K
3757 20:00:51.526311 ZQ Calibration : PASS
3758 20:00:51.528541 Jitter Meter : NO K
3759 20:00:51.531975 CBT Training : PASS
3760 20:00:51.532398 Write leveling : PASS
3761 20:00:51.535384 RX DQS gating : PASS
3762 20:00:51.535932 RX DQ/DQS(RDDQC) : PASS
3763 20:00:51.538743 TX DQ/DQS : PASS
3764 20:00:51.542238 RX DATLAT : PASS
3765 20:00:51.542757 RX DQ/DQS(Engine): PASS
3766 20:00:51.545141 TX OE : NO K
3767 20:00:51.545655 All Pass.
3768 20:00:51.545997
3769 20:00:51.548317 CH 0, Rank 1
3770 20:00:51.548777 SW Impedance : PASS
3771 20:00:51.552028 DUTY Scan : NO K
3772 20:00:51.554809 ZQ Calibration : PASS
3773 20:00:51.555226 Jitter Meter : NO K
3774 20:00:51.558311 CBT Training : PASS
3775 20:00:51.561535 Write leveling : PASS
3776 20:00:51.561970 RX DQS gating : PASS
3777 20:00:51.564869 RX DQ/DQS(RDDQC) : PASS
3778 20:00:51.568218 TX DQ/DQS : PASS
3779 20:00:51.568636 RX DATLAT : PASS
3780 20:00:51.571485 RX DQ/DQS(Engine): PASS
3781 20:00:51.574888 TX OE : NO K
3782 20:00:51.575442 All Pass.
3783 20:00:51.575851
3784 20:00:51.576201 CH 1, Rank 0
3785 20:00:51.578399 SW Impedance : PASS
3786 20:00:51.581859 DUTY Scan : NO K
3787 20:00:51.582447 ZQ Calibration : PASS
3788 20:00:51.584496 Jitter Meter : NO K
3789 20:00:51.588179 CBT Training : PASS
3790 20:00:51.588793 Write leveling : PASS
3791 20:00:51.591583 RX DQS gating : PASS
3792 20:00:51.594715 RX DQ/DQS(RDDQC) : PASS
3793 20:00:51.595221 TX DQ/DQS : PASS
3794 20:00:51.598300 RX DATLAT : PASS
3795 20:00:51.601394 RX DQ/DQS(Engine): PASS
3796 20:00:51.601948 TX OE : NO K
3797 20:00:51.602322 All Pass.
3798 20:00:51.604735
3799 20:00:51.605191 CH 1, Rank 1
3800 20:00:51.607496 SW Impedance : PASS
3801 20:00:51.607948 DUTY Scan : NO K
3802 20:00:51.611271 ZQ Calibration : PASS
3803 20:00:51.614838 Jitter Meter : NO K
3804 20:00:51.615400 CBT Training : PASS
3805 20:00:51.617835 Write leveling : PASS
3806 20:00:51.618385 RX DQS gating : PASS
3807 20:00:51.621156 RX DQ/DQS(RDDQC) : PASS
3808 20:00:51.624270 TX DQ/DQS : PASS
3809 20:00:51.624733 RX DATLAT : PASS
3810 20:00:51.628372 RX DQ/DQS(Engine): PASS
3811 20:00:51.630984 TX OE : NO K
3812 20:00:51.631446 All Pass.
3813 20:00:51.631873
3814 20:00:51.634513 DramC Write-DBI off
3815 20:00:51.634974 PER_BANK_REFRESH: Hybrid Mode
3816 20:00:51.637669 TX_TRACKING: ON
3817 20:00:51.647906 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3818 20:00:51.650399 [FAST_K] Save calibration result to emmc
3819 20:00:51.654134 dramc_set_vcore_voltage set vcore to 650000
3820 20:00:51.654555 Read voltage for 600, 5
3821 20:00:51.657461 Vio18 = 0
3822 20:00:51.657874 Vcore = 650000
3823 20:00:51.658206 Vdram = 0
3824 20:00:51.660876 Vddq = 0
3825 20:00:51.661288 Vmddr = 0
3826 20:00:51.667249 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3827 20:00:51.670737 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3828 20:00:51.673728 MEM_TYPE=3, freq_sel=19
3829 20:00:51.677238 sv_algorithm_assistance_LP4_1600
3830 20:00:51.680416 ============ PULL DRAM RESETB DOWN ============
3831 20:00:51.683867 ========== PULL DRAM RESETB DOWN end =========
3832 20:00:51.690363 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3833 20:00:51.693913 ===================================
3834 20:00:51.694427 LPDDR4 DRAM CONFIGURATION
3835 20:00:51.697080 ===================================
3836 20:00:51.700658 EX_ROW_EN[0] = 0x0
3837 20:00:51.704061 EX_ROW_EN[1] = 0x0
3838 20:00:51.704576 LP4Y_EN = 0x0
3839 20:00:51.707290 WORK_FSP = 0x0
3840 20:00:51.707706 WL = 0x2
3841 20:00:51.710273 RL = 0x2
3842 20:00:51.710781 BL = 0x2
3843 20:00:51.713577 RPST = 0x0
3844 20:00:51.714108 RD_PRE = 0x0
3845 20:00:51.716696 WR_PRE = 0x1
3846 20:00:51.717206 WR_PST = 0x0
3847 20:00:51.720310 DBI_WR = 0x0
3848 20:00:51.720825 DBI_RD = 0x0
3849 20:00:51.724050 OTF = 0x1
3850 20:00:51.726908 ===================================
3851 20:00:51.730455 ===================================
3852 20:00:51.730873 ANA top config
3853 20:00:51.732925 ===================================
3854 20:00:51.736765 DLL_ASYNC_EN = 0
3855 20:00:51.740356 ALL_SLAVE_EN = 1
3856 20:00:51.743361 NEW_RANK_MODE = 1
3857 20:00:51.743925 DLL_IDLE_MODE = 1
3858 20:00:51.747121 LP45_APHY_COMB_EN = 1
3859 20:00:51.749789 TX_ODT_DIS = 1
3860 20:00:51.753129 NEW_8X_MODE = 1
3861 20:00:51.756720 ===================================
3862 20:00:51.759716 ===================================
3863 20:00:51.763140 data_rate = 1200
3864 20:00:51.763658 CKR = 1
3865 20:00:51.767355 DQ_P2S_RATIO = 8
3866 20:00:51.769786 ===================================
3867 20:00:51.773015 CA_P2S_RATIO = 8
3868 20:00:51.776785 DQ_CA_OPEN = 0
3869 20:00:51.779618 DQ_SEMI_OPEN = 0
3870 20:00:51.782713 CA_SEMI_OPEN = 0
3871 20:00:51.783220 CA_FULL_RATE = 0
3872 20:00:51.786276 DQ_CKDIV4_EN = 1
3873 20:00:51.789289 CA_CKDIV4_EN = 1
3874 20:00:51.792549 CA_PREDIV_EN = 0
3875 20:00:51.796275 PH8_DLY = 0
3876 20:00:51.799574 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3877 20:00:51.800130 DQ_AAMCK_DIV = 4
3878 20:00:51.802339 CA_AAMCK_DIV = 4
3879 20:00:51.806319 CA_ADMCK_DIV = 4
3880 20:00:51.809037 DQ_TRACK_CA_EN = 0
3881 20:00:51.812357 CA_PICK = 600
3882 20:00:51.815789 CA_MCKIO = 600
3883 20:00:51.819128 MCKIO_SEMI = 0
3884 20:00:51.822316 PLL_FREQ = 2288
3885 20:00:51.822897 DQ_UI_PI_RATIO = 32
3886 20:00:51.825786 CA_UI_PI_RATIO = 0
3887 20:00:51.828953 ===================================
3888 20:00:51.832650 ===================================
3889 20:00:51.835439 memory_type:LPDDR4
3890 20:00:51.839355 GP_NUM : 10
3891 20:00:51.839956 SRAM_EN : 1
3892 20:00:51.842522 MD32_EN : 0
3893 20:00:51.846406 ===================================
3894 20:00:51.848686 [ANA_INIT] >>>>>>>>>>>>>>
3895 20:00:51.849154 <<<<<< [CONFIGURE PHASE]: ANA_TX
3896 20:00:51.852110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3897 20:00:51.855532 ===================================
3898 20:00:51.859318 data_rate = 1200,PCW = 0X5800
3899 20:00:51.861964 ===================================
3900 20:00:51.865621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3901 20:00:51.872021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3902 20:00:51.878563 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3903 20:00:51.881988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3904 20:00:51.885151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3905 20:00:51.888461 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3906 20:00:51.892009 [ANA_INIT] flow start
3907 20:00:51.892562 [ANA_INIT] PLL >>>>>>>>
3908 20:00:51.895015 [ANA_INIT] PLL <<<<<<<<
3909 20:00:51.898006 [ANA_INIT] MIDPI >>>>>>>>
3910 20:00:51.901347 [ANA_INIT] MIDPI <<<<<<<<
3911 20:00:51.901811 [ANA_INIT] DLL >>>>>>>>
3912 20:00:51.904855 [ANA_INIT] flow end
3913 20:00:51.907996 ============ LP4 DIFF to SE enter ============
3914 20:00:51.911568 ============ LP4 DIFF to SE exit ============
3915 20:00:51.914332 [ANA_INIT] <<<<<<<<<<<<<
3916 20:00:51.918068 [Flow] Enable top DCM control >>>>>
3917 20:00:51.921357 [Flow] Enable top DCM control <<<<<
3918 20:00:51.924763 Enable DLL master slave shuffle
3919 20:00:51.931352 ==============================================================
3920 20:00:51.931956 Gating Mode config
3921 20:00:51.938957 ==============================================================
3922 20:00:51.939508 Config description:
3923 20:00:51.947771 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3924 20:00:51.954124 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3925 20:00:51.960699 SELPH_MODE 0: By rank 1: By Phase
3926 20:00:51.963846 ==============================================================
3927 20:00:51.968036 GAT_TRACK_EN = 1
3928 20:00:51.971291 RX_GATING_MODE = 2
3929 20:00:51.974565 RX_GATING_TRACK_MODE = 2
3930 20:00:51.977093 SELPH_MODE = 1
3931 20:00:51.980662 PICG_EARLY_EN = 1
3932 20:00:51.984187 VALID_LAT_VALUE = 1
3933 20:00:51.990557 ==============================================================
3934 20:00:51.994220 Enter into Gating configuration >>>>
3935 20:00:51.997389 Exit from Gating configuration <<<<
3936 20:00:52.000200 Enter into DVFS_PRE_config >>>>>
3937 20:00:52.010498 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3938 20:00:52.013675 Exit from DVFS_PRE_config <<<<<
3939 20:00:52.016769 Enter into PICG configuration >>>>
3940 20:00:52.020472 Exit from PICG configuration <<<<
3941 20:00:52.023916 [RX_INPUT] configuration >>>>>
3942 20:00:52.024381 [RX_INPUT] configuration <<<<<
3943 20:00:52.030265 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3944 20:00:52.037055 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3945 20:00:52.043364 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3946 20:00:52.046865 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3947 20:00:52.053296 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3948 20:00:52.059861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3949 20:00:52.062957 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3950 20:00:52.066506 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3951 20:00:52.072722 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3952 20:00:52.076542 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3953 20:00:52.080143 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3954 20:00:52.086426 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3955 20:00:52.089195 ===================================
3956 20:00:52.089659 LPDDR4 DRAM CONFIGURATION
3957 20:00:52.093343 ===================================
3958 20:00:52.096475 EX_ROW_EN[0] = 0x0
3959 20:00:52.099408 EX_ROW_EN[1] = 0x0
3960 20:00:52.100051 LP4Y_EN = 0x0
3961 20:00:52.102678 WORK_FSP = 0x0
3962 20:00:52.103140 WL = 0x2
3963 20:00:52.105882 RL = 0x2
3964 20:00:52.106439 BL = 0x2
3965 20:00:52.109180 RPST = 0x0
3966 20:00:52.109733 RD_PRE = 0x0
3967 20:00:52.112740 WR_PRE = 0x1
3968 20:00:52.113303 WR_PST = 0x0
3969 20:00:52.115996 DBI_WR = 0x0
3970 20:00:52.116558 DBI_RD = 0x0
3971 20:00:52.119098 OTF = 0x1
3972 20:00:52.122372 ===================================
3973 20:00:52.125528 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3974 20:00:52.129061 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3975 20:00:52.135774 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3976 20:00:52.139013 ===================================
3977 20:00:52.139576 LPDDR4 DRAM CONFIGURATION
3978 20:00:52.142618 ===================================
3979 20:00:52.145700 EX_ROW_EN[0] = 0x10
3980 20:00:52.148858 EX_ROW_EN[1] = 0x0
3981 20:00:52.149418 LP4Y_EN = 0x0
3982 20:00:52.151939 WORK_FSP = 0x0
3983 20:00:52.152513 WL = 0x2
3984 20:00:52.155317 RL = 0x2
3985 20:00:52.155915 BL = 0x2
3986 20:00:52.158824 RPST = 0x0
3987 20:00:52.159395 RD_PRE = 0x0
3988 20:00:52.161686 WR_PRE = 0x1
3989 20:00:52.162145 WR_PST = 0x0
3990 20:00:52.165483 DBI_WR = 0x0
3991 20:00:52.166032 DBI_RD = 0x0
3992 20:00:52.169102 OTF = 0x1
3993 20:00:52.172321 ===================================
3994 20:00:52.178655 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3995 20:00:52.181793 nWR fixed to 30
3996 20:00:52.185211 [ModeRegInit_LP4] CH0 RK0
3997 20:00:52.185768 [ModeRegInit_LP4] CH0 RK1
3998 20:00:52.188203 [ModeRegInit_LP4] CH1 RK0
3999 20:00:52.192417 [ModeRegInit_LP4] CH1 RK1
4000 20:00:52.192977 match AC timing 17
4001 20:00:52.198565 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4002 20:00:52.201367 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4003 20:00:52.205052 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4004 20:00:52.211446 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4005 20:00:52.214820 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4006 20:00:52.215290 ==
4007 20:00:52.218132 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 20:00:52.221243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 20:00:52.221715 ==
4010 20:00:52.227961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4011 20:00:52.234506 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4012 20:00:52.237480 [CA 0] Center 36 (6~66) winsize 61
4013 20:00:52.240881 [CA 1] Center 36 (6~66) winsize 61
4014 20:00:52.244612 [CA 2] Center 34 (4~65) winsize 62
4015 20:00:52.247538 [CA 3] Center 34 (4~65) winsize 62
4016 20:00:52.251045 [CA 4] Center 33 (3~64) winsize 62
4017 20:00:52.254000 [CA 5] Center 33 (3~64) winsize 62
4018 20:00:52.254469
4019 20:00:52.257771 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4020 20:00:52.258325
4021 20:00:52.260764 [CATrainingPosCal] consider 1 rank data
4022 20:00:52.264369 u2DelayCellTimex100 = 270/100 ps
4023 20:00:52.267682 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4024 20:00:52.270926 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4025 20:00:52.274198 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4026 20:00:52.277442 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4027 20:00:52.283750 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4028 20:00:52.287073 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4029 20:00:52.287625
4030 20:00:52.291334 CA PerBit enable=1, Macro0, CA PI delay=33
4031 20:00:52.291937
4032 20:00:52.294222 [CBTSetCACLKResult] CA Dly = 33
4033 20:00:52.294772 CS Dly: 5 (0~36)
4034 20:00:52.295145 ==
4035 20:00:52.297608 Dram Type= 6, Freq= 0, CH_0, rank 1
4036 20:00:52.303923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 20:00:52.304536 ==
4038 20:00:52.307054 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4039 20:00:52.313498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4040 20:00:52.316710 [CA 0] Center 36 (6~66) winsize 61
4041 20:00:52.319889 [CA 1] Center 36 (6~66) winsize 61
4042 20:00:52.323413 [CA 2] Center 34 (3~65) winsize 63
4043 20:00:52.326468 [CA 3] Center 33 (3~64) winsize 62
4044 20:00:52.329777 [CA 4] Center 33 (3~64) winsize 62
4045 20:00:52.333262 [CA 5] Center 33 (2~64) winsize 63
4046 20:00:52.333494
4047 20:00:52.336252 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4048 20:00:52.336487
4049 20:00:52.339611 [CATrainingPosCal] consider 2 rank data
4050 20:00:52.343299 u2DelayCellTimex100 = 270/100 ps
4051 20:00:52.346590 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4052 20:00:52.352618 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4053 20:00:52.355832 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4054 20:00:52.359093 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4055 20:00:52.362741 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4056 20:00:52.365944 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4057 20:00:52.366047
4058 20:00:52.368943 CA PerBit enable=1, Macro0, CA PI delay=33
4059 20:00:52.369046
4060 20:00:52.372415 [CBTSetCACLKResult] CA Dly = 33
4061 20:00:52.375890 CS Dly: 5 (0~37)
4062 20:00:52.375995
4063 20:00:52.379336 ----->DramcWriteLeveling(PI) begin...
4064 20:00:52.379442 ==
4065 20:00:52.382201 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 20:00:52.385666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 20:00:52.385771 ==
4068 20:00:52.389071 Write leveling (Byte 0): 36 => 36
4069 20:00:52.392238 Write leveling (Byte 1): 29 => 29
4070 20:00:52.395401 DramcWriteLeveling(PI) end<-----
4071 20:00:52.395506
4072 20:00:52.395614 ==
4073 20:00:52.398840 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 20:00:52.402207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 20:00:52.402316 ==
4076 20:00:52.405661 [Gating] SW mode calibration
4077 20:00:52.412279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4078 20:00:52.418634 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4079 20:00:52.423143 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4080 20:00:52.425713 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4081 20:00:52.432185 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4082 20:00:52.435786 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4083 20:00:52.438699 0 9 16 | B1->B0 | 2f2f 2525 | 1 1 | (1 1) (1 0)
4084 20:00:52.445342 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 20:00:52.448584 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 20:00:52.451892 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 20:00:52.458578 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 20:00:52.461820 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4089 20:00:52.464654 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4090 20:00:52.472213 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4091 20:00:52.474707 0 10 16 | B1->B0 | 3232 3d3d | 1 1 | (0 0) (0 0)
4092 20:00:52.477753 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 20:00:52.484976 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 20:00:52.488055 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 20:00:52.491676 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 20:00:52.498122 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 20:00:52.501662 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4098 20:00:52.504577 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4099 20:00:52.511099 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4100 20:00:52.514269 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 20:00:52.518187 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 20:00:52.524372 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 20:00:52.528510 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 20:00:52.530965 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 20:00:52.537625 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 20:00:52.541196 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 20:00:52.544477 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 20:00:52.551434 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 20:00:52.554238 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 20:00:52.557631 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 20:00:52.564609 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 20:00:52.567540 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 20:00:52.571043 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 20:00:52.577609 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4115 20:00:52.580972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4116 20:00:52.584089 Total UI for P1: 0, mck2ui 16
4117 20:00:52.587606 best dqsien dly found for B0: ( 0, 13, 12)
4118 20:00:52.590602 Total UI for P1: 0, mck2ui 16
4119 20:00:52.594066 best dqsien dly found for B1: ( 0, 13, 12)
4120 20:00:52.597305 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4121 20:00:52.600819 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4122 20:00:52.601460
4123 20:00:52.604178 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4124 20:00:52.610794 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4125 20:00:52.611376 [Gating] SW calibration Done
4126 20:00:52.611785 ==
4127 20:00:52.613561 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 20:00:52.620236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 20:00:52.620794 ==
4130 20:00:52.621170 RX Vref Scan: 0
4131 20:00:52.621520
4132 20:00:52.623549 RX Vref 0 -> 0, step: 1
4133 20:00:52.624149
4134 20:00:52.627239 RX Delay -230 -> 252, step: 16
4135 20:00:52.630774 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4136 20:00:52.633807 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4137 20:00:52.639945 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4138 20:00:52.643603 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4139 20:00:52.646444 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4140 20:00:52.649991 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4141 20:00:52.652764 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4142 20:00:52.659939 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4143 20:00:52.662864 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4144 20:00:52.666454 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4145 20:00:52.669476 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4146 20:00:52.676483 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4147 20:00:52.679586 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4148 20:00:52.682693 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4149 20:00:52.686500 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4150 20:00:52.692587 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4151 20:00:52.693147 ==
4152 20:00:52.696184 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 20:00:52.699083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 20:00:52.699544 ==
4155 20:00:52.699955 DQS Delay:
4156 20:00:52.702144 DQS0 = 0, DQS1 = 0
4157 20:00:52.702667 DQM Delay:
4158 20:00:52.705762 DQM0 = 42, DQM1 = 31
4159 20:00:52.706215 DQ Delay:
4160 20:00:52.709129 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4161 20:00:52.712621 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4162 20:00:52.715932 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4163 20:00:52.718917 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4164 20:00:52.719470
4165 20:00:52.719950
4166 20:00:52.720310 ==
4167 20:00:52.722222 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 20:00:52.728660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 20:00:52.729218 ==
4170 20:00:52.729589
4171 20:00:52.729930
4172 20:00:52.730255 TX Vref Scan disable
4173 20:00:52.732383 == TX Byte 0 ==
4174 20:00:52.735562 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4175 20:00:52.742257 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4176 20:00:52.742813 == TX Byte 1 ==
4177 20:00:52.745591 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4178 20:00:52.752171 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4179 20:00:52.752850 ==
4180 20:00:52.755275 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 20:00:52.759285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 20:00:52.759902 ==
4183 20:00:52.760282
4184 20:00:52.760623
4185 20:00:52.761866 TX Vref Scan disable
4186 20:00:52.765308 == TX Byte 0 ==
4187 20:00:52.768306 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4188 20:00:52.773149 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4189 20:00:52.774883 == TX Byte 1 ==
4190 20:00:52.778877 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4191 20:00:52.782590 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4192 20:00:52.783147
4193 20:00:52.784821 [DATLAT]
4194 20:00:52.785283 Freq=600, CH0 RK0
4195 20:00:52.785649
4196 20:00:52.788496 DATLAT Default: 0x9
4197 20:00:52.788952 0, 0xFFFF, sum = 0
4198 20:00:52.791861 1, 0xFFFF, sum = 0
4199 20:00:52.792423 2, 0xFFFF, sum = 0
4200 20:00:52.795066 3, 0xFFFF, sum = 0
4201 20:00:52.795627 4, 0xFFFF, sum = 0
4202 20:00:52.798547 5, 0xFFFF, sum = 0
4203 20:00:52.799018 6, 0xFFFF, sum = 0
4204 20:00:52.801625 7, 0xFFFF, sum = 0
4205 20:00:52.802276 8, 0x0, sum = 1
4206 20:00:52.805011 9, 0x0, sum = 2
4207 20:00:52.805538 10, 0x0, sum = 3
4208 20:00:52.808165 11, 0x0, sum = 4
4209 20:00:52.808636 best_step = 9
4210 20:00:52.809012
4211 20:00:52.809343 ==
4212 20:00:52.811877 Dram Type= 6, Freq= 0, CH_0, rank 0
4213 20:00:52.814986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 20:00:52.818729 ==
4215 20:00:52.819242 RX Vref Scan: 1
4216 20:00:52.819581
4217 20:00:52.821641 RX Vref 0 -> 0, step: 1
4218 20:00:52.822154
4219 20:00:52.825015 RX Delay -195 -> 252, step: 8
4220 20:00:52.825444
4221 20:00:52.829961 Set Vref, RX VrefLevel [Byte0]: 63
4222 20:00:52.830390 [Byte1]: 49
4223 20:00:52.833112
4224 20:00:52.833533 Final RX Vref Byte 0 = 63 to rank0
4225 20:00:52.836388 Final RX Vref Byte 1 = 49 to rank0
4226 20:00:52.839835 Final RX Vref Byte 0 = 63 to rank1
4227 20:00:52.843116 Final RX Vref Byte 1 = 49 to rank1==
4228 20:00:52.846319 Dram Type= 6, Freq= 0, CH_0, rank 0
4229 20:00:52.853158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 20:00:52.853683 ==
4231 20:00:52.854033 DQS Delay:
4232 20:00:52.855820 DQS0 = 0, DQS1 = 0
4233 20:00:52.856361 DQM Delay:
4234 20:00:52.856698 DQM0 = 44, DQM1 = 32
4235 20:00:52.859463 DQ Delay:
4236 20:00:52.862953 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4237 20:00:52.866306 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =52
4238 20:00:52.869772 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4239 20:00:52.872909 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4240 20:00:52.873467
4241 20:00:52.873835
4242 20:00:52.879525 [DQSOSCAuto] RK0, (LSB)MR18= 0x6941, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4243 20:00:52.882656 CH0 RK0: MR19=808, MR18=6941
4244 20:00:52.889388 CH0_RK0: MR19=0x808, MR18=0x6941, DQSOSC=390, MR23=63, INC=172, DEC=114
4245 20:00:52.889941
4246 20:00:52.892402 ----->DramcWriteLeveling(PI) begin...
4247 20:00:52.892876 ==
4248 20:00:52.896089 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 20:00:52.899264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 20:00:52.899776 ==
4251 20:00:52.902711 Write leveling (Byte 0): 33 => 33
4252 20:00:52.905840 Write leveling (Byte 1): 29 => 29
4253 20:00:52.909408 DramcWriteLeveling(PI) end<-----
4254 20:00:52.909960
4255 20:00:52.910334 ==
4256 20:00:52.911992 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 20:00:52.915621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 20:00:52.916224 ==
4259 20:00:52.919255 [Gating] SW mode calibration
4260 20:00:52.925991 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4261 20:00:52.932596 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4262 20:00:52.935370 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4263 20:00:52.942029 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4264 20:00:52.945230 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4265 20:00:52.948495 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4266 20:00:52.955041 0 9 16 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (0 0)
4267 20:00:52.958656 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 20:00:52.962051 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 20:00:52.968565 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 20:00:52.972001 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 20:00:52.975241 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 20:00:52.981592 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4273 20:00:52.985347 0 10 12 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
4274 20:00:52.988361 0 10 16 | B1->B0 | 3938 3f3f | 1 1 | (0 0) (0 0)
4275 20:00:52.994929 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 20:00:52.997982 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 20:00:53.002081 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 20:00:53.008255 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 20:00:53.011499 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 20:00:53.015105 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 20:00:53.021519 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4282 20:00:53.024411 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4283 20:00:53.028101 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 20:00:53.035171 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 20:00:53.037539 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 20:00:53.040836 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 20:00:53.047452 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 20:00:53.050926 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 20:00:53.054184 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 20:00:53.061627 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 20:00:53.064249 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 20:00:53.067623 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 20:00:53.074364 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 20:00:53.077281 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 20:00:53.080947 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 20:00:53.087630 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 20:00:53.091057 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4298 20:00:53.094327 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 20:00:53.096989 Total UI for P1: 0, mck2ui 16
4300 20:00:53.100633 best dqsien dly found for B0: ( 0, 13, 12)
4301 20:00:53.103450 Total UI for P1: 0, mck2ui 16
4302 20:00:53.106901 best dqsien dly found for B1: ( 0, 13, 12)
4303 20:00:53.110453 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4304 20:00:53.113828 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4305 20:00:53.114385
4306 20:00:53.120350 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4307 20:00:53.123346 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4308 20:00:53.126588 [Gating] SW calibration Done
4309 20:00:53.127143 ==
4310 20:00:53.129974 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 20:00:53.133312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 20:00:53.133866 ==
4313 20:00:53.134242 RX Vref Scan: 0
4314 20:00:53.134590
4315 20:00:53.136543 RX Vref 0 -> 0, step: 1
4316 20:00:53.137005
4317 20:00:53.140505 RX Delay -230 -> 252, step: 16
4318 20:00:53.143549 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4319 20:00:53.149637 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4320 20:00:53.152768 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4321 20:00:53.156163 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4322 20:00:53.159606 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4323 20:00:53.162954 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4324 20:00:53.169660 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4325 20:00:53.172954 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4326 20:00:53.176599 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4327 20:00:53.179515 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4328 20:00:53.185989 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4329 20:00:53.189678 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4330 20:00:53.192882 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4331 20:00:53.196119 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4332 20:00:53.202449 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4333 20:00:53.206191 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4334 20:00:53.206657 ==
4335 20:00:53.209003 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 20:00:53.212891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 20:00:53.213453 ==
4338 20:00:53.215713 DQS Delay:
4339 20:00:53.216315 DQS0 = 0, DQS1 = 0
4340 20:00:53.218883 DQM Delay:
4341 20:00:53.219439 DQM0 = 45, DQM1 = 37
4342 20:00:53.219854 DQ Delay:
4343 20:00:53.221824 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4344 20:00:53.225576 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4345 20:00:53.228767 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4346 20:00:53.232013 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4347 20:00:53.232648
4348 20:00:53.233032
4349 20:00:53.235086 ==
4350 20:00:53.235642 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 20:00:53.242053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 20:00:53.242615 ==
4353 20:00:53.242992
4354 20:00:53.243339
4355 20:00:53.244671 TX Vref Scan disable
4356 20:00:53.245135 == TX Byte 0 ==
4357 20:00:53.251509 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4358 20:00:53.255303 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4359 20:00:53.255925 == TX Byte 1 ==
4360 20:00:53.261346 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4361 20:00:53.264464 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4362 20:00:53.264992 ==
4363 20:00:53.267749 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 20:00:53.271115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 20:00:53.271575 ==
4366 20:00:53.272003
4367 20:00:53.272347
4368 20:00:53.275012 TX Vref Scan disable
4369 20:00:53.277616 == TX Byte 0 ==
4370 20:00:53.281044 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4371 20:00:53.288458 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4372 20:00:53.288973 == TX Byte 1 ==
4373 20:00:53.291299 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4374 20:00:53.297617 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4375 20:00:53.298295
4376 20:00:53.298649 [DATLAT]
4377 20:00:53.298963 Freq=600, CH0 RK1
4378 20:00:53.299323
4379 20:00:53.300717 DATLAT Default: 0x9
4380 20:00:53.301136 0, 0xFFFF, sum = 0
4381 20:00:53.304261 1, 0xFFFF, sum = 0
4382 20:00:53.307325 2, 0xFFFF, sum = 0
4383 20:00:53.307791 3, 0xFFFF, sum = 0
4384 20:00:53.310793 4, 0xFFFF, sum = 0
4385 20:00:53.311373 5, 0xFFFF, sum = 0
4386 20:00:53.314919 6, 0xFFFF, sum = 0
4387 20:00:53.315530 7, 0xFFFF, sum = 0
4388 20:00:53.317418 8, 0x0, sum = 1
4389 20:00:53.317837 9, 0x0, sum = 2
4390 20:00:53.320602 10, 0x0, sum = 3
4391 20:00:53.321118 11, 0x0, sum = 4
4392 20:00:53.321528 best_step = 9
4393 20:00:53.321845
4394 20:00:53.323929 ==
4395 20:00:53.324436 Dram Type= 6, Freq= 0, CH_0, rank 1
4396 20:00:53.330529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 20:00:53.331048 ==
4398 20:00:53.331387 RX Vref Scan: 0
4399 20:00:53.331699
4400 20:00:53.333528 RX Vref 0 -> 0, step: 1
4401 20:00:53.333944
4402 20:00:53.337364 RX Delay -179 -> 252, step: 8
4403 20:00:53.343763 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4404 20:00:53.347250 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4405 20:00:53.350254 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4406 20:00:53.353933 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4407 20:00:53.356983 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4408 20:00:53.363277 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4409 20:00:53.366551 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4410 20:00:53.370473 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4411 20:00:53.373367 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4412 20:00:53.379790 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4413 20:00:53.382879 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4414 20:00:53.386992 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4415 20:00:53.389482 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4416 20:00:53.396914 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4417 20:00:53.399488 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4418 20:00:53.402915 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4419 20:00:53.403509 ==
4420 20:00:53.405878 Dram Type= 6, Freq= 0, CH_0, rank 1
4421 20:00:53.412534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 20:00:53.413035 ==
4423 20:00:53.413375 DQS Delay:
4424 20:00:53.413689 DQS0 = 0, DQS1 = 0
4425 20:00:53.416181 DQM Delay:
4426 20:00:53.416906 DQM0 = 40, DQM1 = 36
4427 20:00:53.419282 DQ Delay:
4428 20:00:53.423450 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =36
4429 20:00:53.425892 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4430 20:00:53.429168 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4431 20:00:53.432353 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4432 20:00:53.432863
4433 20:00:53.433198
4434 20:00:53.439495 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4435 20:00:53.442453 CH0 RK1: MR19=808, MR18=5F12
4436 20:00:53.448676 CH0_RK1: MR19=0x808, MR18=0x5F12, DQSOSC=391, MR23=63, INC=171, DEC=114
4437 20:00:53.451999 [RxdqsGatingPostProcess] freq 600
4438 20:00:53.455303 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4439 20:00:53.458577 Pre-setting of DQS Precalculation
4440 20:00:53.465081 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4441 20:00:53.465581 ==
4442 20:00:53.469060 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 20:00:53.472221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 20:00:53.472841 ==
4445 20:00:53.478242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 20:00:53.485056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4447 20:00:53.488181 [CA 0] Center 35 (5~66) winsize 62
4448 20:00:53.491463 [CA 1] Center 35 (5~66) winsize 62
4449 20:00:53.494721 [CA 2] Center 34 (4~65) winsize 62
4450 20:00:53.498626 [CA 3] Center 33 (3~64) winsize 62
4451 20:00:53.501161 [CA 4] Center 34 (4~65) winsize 62
4452 20:00:53.504873 [CA 5] Center 33 (3~64) winsize 62
4453 20:00:53.505284
4454 20:00:53.508039 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4455 20:00:53.508610
4456 20:00:53.511472 [CATrainingPosCal] consider 1 rank data
4457 20:00:53.515182 u2DelayCellTimex100 = 270/100 ps
4458 20:00:53.518120 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4459 20:00:53.521312 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4460 20:00:53.524400 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 20:00:53.527851 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4462 20:00:53.531275 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 20:00:53.534304 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 20:00:53.534714
4465 20:00:53.541410 CA PerBit enable=1, Macro0, CA PI delay=33
4466 20:00:53.541914
4467 20:00:53.544277 [CBTSetCACLKResult] CA Dly = 33
4468 20:00:53.544689 CS Dly: 5 (0~36)
4469 20:00:53.545016 ==
4470 20:00:53.547833 Dram Type= 6, Freq= 0, CH_1, rank 1
4471 20:00:53.551821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 20:00:53.552375 ==
4473 20:00:53.557493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4474 20:00:53.564365 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4475 20:00:53.567658 [CA 0] Center 35 (5~66) winsize 62
4476 20:00:53.571181 [CA 1] Center 36 (6~66) winsize 61
4477 20:00:53.574189 [CA 2] Center 34 (4~65) winsize 62
4478 20:00:53.577790 [CA 3] Center 34 (3~65) winsize 63
4479 20:00:53.580792 [CA 4] Center 34 (4~65) winsize 62
4480 20:00:53.584215 [CA 5] Center 34 (3~65) winsize 63
4481 20:00:53.584767
4482 20:00:53.587519 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4483 20:00:53.588111
4484 20:00:53.590879 [CATrainingPosCal] consider 2 rank data
4485 20:00:53.593981 u2DelayCellTimex100 = 270/100 ps
4486 20:00:53.597212 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4487 20:00:53.600245 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4488 20:00:53.603579 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4489 20:00:53.607806 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4490 20:00:53.614315 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4491 20:00:53.617083 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4492 20:00:53.617639
4493 20:00:53.620515 CA PerBit enable=1, Macro0, CA PI delay=33
4494 20:00:53.621078
4495 20:00:53.623687 [CBTSetCACLKResult] CA Dly = 33
4496 20:00:53.624276 CS Dly: 5 (0~36)
4497 20:00:53.624650
4498 20:00:53.627652 ----->DramcWriteLeveling(PI) begin...
4499 20:00:53.628254 ==
4500 20:00:53.630632 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 20:00:53.636922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 20:00:53.637482 ==
4503 20:00:53.641142 Write leveling (Byte 0): 30 => 30
4504 20:00:53.643624 Write leveling (Byte 1): 31 => 31
4505 20:00:53.646822 DramcWriteLeveling(PI) end<-----
4506 20:00:53.647381
4507 20:00:53.647797 ==
4508 20:00:53.650362 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 20:00:53.653389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 20:00:53.653858 ==
4511 20:00:53.657649 [Gating] SW mode calibration
4512 20:00:53.663608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4513 20:00:53.666358 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4514 20:00:53.673166 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4515 20:00:53.676414 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4516 20:00:53.679669 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4517 20:00:53.686368 0 9 12 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 1)
4518 20:00:53.689832 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4519 20:00:53.693254 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 20:00:53.699770 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 20:00:53.703385 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 20:00:53.706341 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 20:00:53.713131 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4524 20:00:53.716112 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4525 20:00:53.719991 0 10 12 | B1->B0 | 2d2d 3b3b | 1 1 | (0 0) (0 0)
4526 20:00:53.726236 0 10 16 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4527 20:00:53.729426 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 20:00:53.732944 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 20:00:53.739121 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 20:00:53.742312 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 20:00:53.745488 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 20:00:53.751835 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 20:00:53.755537 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4534 20:00:53.761642 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 20:00:53.765123 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 20:00:53.768341 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 20:00:53.775078 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 20:00:53.778416 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 20:00:53.781689 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 20:00:53.788989 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 20:00:53.792100 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 20:00:53.794908 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 20:00:53.798707 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 20:00:53.804588 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 20:00:53.808082 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 20:00:53.814947 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 20:00:53.818382 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 20:00:53.821391 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 20:00:53.824428 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4550 20:00:53.831478 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4551 20:00:53.835187 Total UI for P1: 0, mck2ui 16
4552 20:00:53.838179 best dqsien dly found for B0: ( 0, 13, 12)
4553 20:00:53.841328 Total UI for P1: 0, mck2ui 16
4554 20:00:53.845315 best dqsien dly found for B1: ( 0, 13, 12)
4555 20:00:53.848462 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4556 20:00:53.851393 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4557 20:00:53.851987
4558 20:00:53.854708 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4559 20:00:53.857709 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4560 20:00:53.860702 [Gating] SW calibration Done
4561 20:00:53.861169 ==
4562 20:00:53.864274 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 20:00:53.867325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 20:00:53.870667 ==
4565 20:00:53.871228 RX Vref Scan: 0
4566 20:00:53.871604
4567 20:00:53.874162 RX Vref 0 -> 0, step: 1
4568 20:00:53.874731
4569 20:00:53.877273 RX Delay -230 -> 252, step: 16
4570 20:00:53.880909 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4571 20:00:53.884107 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4572 20:00:53.887851 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4573 20:00:53.894081 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4574 20:00:53.897663 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4575 20:00:53.900206 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4576 20:00:53.904365 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4577 20:00:53.907341 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4578 20:00:53.913420 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4579 20:00:53.917001 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4580 20:00:53.920106 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4581 20:00:53.923544 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4582 20:00:53.929831 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4583 20:00:53.933530 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4584 20:00:53.936458 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4585 20:00:53.940228 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4586 20:00:53.943332 ==
4587 20:00:53.946973 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 20:00:53.950072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 20:00:53.950632 ==
4590 20:00:53.951006 DQS Delay:
4591 20:00:53.953783 DQS0 = 0, DQS1 = 0
4592 20:00:53.954340 DQM Delay:
4593 20:00:53.956346 DQM0 = 45, DQM1 = 36
4594 20:00:53.956812 DQ Delay:
4595 20:00:53.959649 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4596 20:00:53.962886 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4597 20:00:53.966296 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4598 20:00:53.970467 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4599 20:00:53.971036
4600 20:00:53.971522
4601 20:00:53.972033 ==
4602 20:00:53.972882 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 20:00:53.976020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 20:00:53.976585 ==
4605 20:00:53.977072
4606 20:00:53.977523
4607 20:00:53.979808 TX Vref Scan disable
4608 20:00:53.983476 == TX Byte 0 ==
4609 20:00:53.986426 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4610 20:00:53.989503 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4611 20:00:53.992659 == TX Byte 1 ==
4612 20:00:53.996082 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4613 20:00:53.999368 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4614 20:00:54.000025 ==
4615 20:00:54.002922 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 20:00:54.009295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 20:00:54.009864 ==
4618 20:00:54.010363
4619 20:00:54.010824
4620 20:00:54.011275 TX Vref Scan disable
4621 20:00:54.013912 == TX Byte 0 ==
4622 20:00:54.016807 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4623 20:00:54.023526 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4624 20:00:54.024150 == TX Byte 1 ==
4625 20:00:54.026860 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4626 20:00:54.033560 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4627 20:00:54.034135
4628 20:00:54.034506 [DATLAT]
4629 20:00:54.034853 Freq=600, CH1 RK0
4630 20:00:54.035193
4631 20:00:54.043396 DATLAT Default: 0x9
4632 20:00:54.044015 0, 0xFFFF, sum = 0
4633 20:00:54.044412 1, 0xFFFF, sum = 0
4634 20:00:54.044768 2, 0xFFFF, sum = 0
4635 20:00:54.045468 3, 0xFFFF, sum = 0
4636 20:00:54.046409 4, 0xFFFF, sum = 0
4637 20:00:54.046849 5, 0xFFFF, sum = 0
4638 20:00:54.050126 6, 0xFFFF, sum = 0
4639 20:00:54.050700 7, 0xFFFF, sum = 0
4640 20:00:54.053114 8, 0x0, sum = 1
4641 20:00:54.053584 9, 0x0, sum = 2
4642 20:00:54.053998 10, 0x0, sum = 3
4643 20:00:54.057152 11, 0x0, sum = 4
4644 20:00:54.057725 best_step = 9
4645 20:00:54.058102
4646 20:00:54.058445 ==
4647 20:00:54.060125 Dram Type= 6, Freq= 0, CH_1, rank 0
4648 20:00:54.066817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 20:00:54.067281 ==
4650 20:00:54.067655 RX Vref Scan: 1
4651 20:00:54.068060
4652 20:00:54.070611 RX Vref 0 -> 0, step: 1
4653 20:00:54.071182
4654 20:00:54.073173 RX Delay -195 -> 252, step: 8
4655 20:00:54.073638
4656 20:00:54.077377 Set Vref, RX VrefLevel [Byte0]: 49
4657 20:00:54.079543 [Byte1]: 53
4658 20:00:54.080120
4659 20:00:54.083131 Final RX Vref Byte 0 = 49 to rank0
4660 20:00:54.086777 Final RX Vref Byte 1 = 53 to rank0
4661 20:00:54.089755 Final RX Vref Byte 0 = 49 to rank1
4662 20:00:54.092788 Final RX Vref Byte 1 = 53 to rank1==
4663 20:00:54.095862 Dram Type= 6, Freq= 0, CH_1, rank 0
4664 20:00:54.099968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 20:00:54.102610 ==
4666 20:00:54.103178 DQS Delay:
4667 20:00:54.103672 DQS0 = 0, DQS1 = 0
4668 20:00:54.105782 DQM Delay:
4669 20:00:54.106254 DQM0 = 48, DQM1 = 36
4670 20:00:54.109492 DQ Delay:
4671 20:00:54.112572 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4672 20:00:54.113145 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4673 20:00:54.115899 DQ8 =24, DQ9 =28, DQ10 =40, DQ11 =28
4674 20:00:54.122527 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =48
4675 20:00:54.123090
4676 20:00:54.123462
4677 20:00:54.128874 [DQSOSCAuto] RK0, (LSB)MR18= 0x5035, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4678 20:00:54.132997 CH1 RK0: MR19=808, MR18=5035
4679 20:00:54.138795 CH1_RK0: MR19=0x808, MR18=0x5035, DQSOSC=394, MR23=63, INC=168, DEC=112
4680 20:00:54.139366
4681 20:00:54.142334 ----->DramcWriteLeveling(PI) begin...
4682 20:00:54.142897 ==
4683 20:00:54.145235 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 20:00:54.148662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 20:00:54.149230 ==
4686 20:00:54.151848 Write leveling (Byte 0): 30 => 30
4687 20:00:54.155006 Write leveling (Byte 1): 30 => 30
4688 20:00:54.158017 DramcWriteLeveling(PI) end<-----
4689 20:00:54.158520
4690 20:00:54.158999 ==
4691 20:00:54.161893 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 20:00:54.165030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 20:00:54.168456 ==
4694 20:00:54.168931 [Gating] SW mode calibration
4695 20:00:54.175133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4696 20:00:54.181477 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4697 20:00:54.185042 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4698 20:00:54.191762 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4699 20:00:54.194997 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4700 20:00:54.198434 0 9 12 | B1->B0 | 2f2f 3333 | 0 0 | (0 0) (0 0)
4701 20:00:54.204622 0 9 16 | B1->B0 | 2424 2525 | 0 1 | (0 0) (1 0)
4702 20:00:54.207961 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 20:00:54.211111 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 20:00:54.217760 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 20:00:54.220726 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 20:00:54.224357 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4707 20:00:54.230985 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4708 20:00:54.234239 0 10 12 | B1->B0 | 3333 2c2c | 1 0 | (1 1) (0 0)
4709 20:00:54.237665 0 10 16 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
4710 20:00:54.243948 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 20:00:54.247607 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 20:00:54.250663 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 20:00:54.257244 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 20:00:54.260267 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 20:00:54.263428 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 20:00:54.270604 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4717 20:00:54.274021 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4718 20:00:54.277489 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 20:00:54.283394 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 20:00:54.286576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 20:00:54.290075 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 20:00:54.296457 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 20:00:54.300051 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 20:00:54.303382 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 20:00:54.310656 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 20:00:54.313218 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 20:00:54.316312 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 20:00:54.323645 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 20:00:54.326082 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 20:00:54.329710 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 20:00:54.336693 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 20:00:54.339711 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4733 20:00:54.343239 Total UI for P1: 0, mck2ui 16
4734 20:00:54.346020 best dqsien dly found for B1: ( 0, 13, 10)
4735 20:00:54.350164 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4736 20:00:54.353062 Total UI for P1: 0, mck2ui 16
4737 20:00:54.355909 best dqsien dly found for B0: ( 0, 13, 12)
4738 20:00:54.359858 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4739 20:00:54.366101 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4740 20:00:54.366668
4741 20:00:54.369149 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4742 20:00:54.372491 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4743 20:00:54.375929 [Gating] SW calibration Done
4744 20:00:54.376488 ==
4745 20:00:54.379214 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 20:00:54.382265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 20:00:54.382835 ==
4748 20:00:54.386285 RX Vref Scan: 0
4749 20:00:54.386846
4750 20:00:54.387213 RX Vref 0 -> 0, step: 1
4751 20:00:54.387551
4752 20:00:54.388684 RX Delay -230 -> 252, step: 16
4753 20:00:54.392731 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4754 20:00:54.398784 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4755 20:00:54.401751 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4756 20:00:54.406369 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4757 20:00:54.409101 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4758 20:00:54.415090 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4759 20:00:54.418198 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4760 20:00:54.421534 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4761 20:00:54.425536 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4762 20:00:54.431669 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4763 20:00:54.434708 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4764 20:00:54.438547 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4765 20:00:54.441501 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4766 20:00:54.448757 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4767 20:00:54.452037 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4768 20:00:54.454918 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4769 20:00:54.455476 ==
4770 20:00:54.458347 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 20:00:54.461504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 20:00:54.462062 ==
4773 20:00:54.464638 DQS Delay:
4774 20:00:54.465127 DQS0 = 0, DQS1 = 0
4775 20:00:54.467714 DQM Delay:
4776 20:00:54.468215 DQM0 = 44, DQM1 = 38
4777 20:00:54.468578 DQ Delay:
4778 20:00:54.471409 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4779 20:00:54.474840 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4780 20:00:54.478097 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4781 20:00:54.481144 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4782 20:00:54.481600
4783 20:00:54.481962
4784 20:00:54.484412 ==
4785 20:00:54.488038 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 20:00:54.491197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 20:00:54.491798 ==
4788 20:00:54.492181
4789 20:00:54.492518
4790 20:00:54.494783 TX Vref Scan disable
4791 20:00:54.495350 == TX Byte 0 ==
4792 20:00:54.501125 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4793 20:00:54.504307 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4794 20:00:54.504862 == TX Byte 1 ==
4795 20:00:54.511098 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4796 20:00:54.514210 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4797 20:00:54.514768 ==
4798 20:00:54.517602 Dram Type= 6, Freq= 0, CH_1, rank 1
4799 20:00:54.520945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4800 20:00:54.521420 ==
4801 20:00:54.521792
4802 20:00:54.522123
4803 20:00:54.524092 TX Vref Scan disable
4804 20:00:54.527380 == TX Byte 0 ==
4805 20:00:54.531096 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4806 20:00:54.534925 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4807 20:00:54.537581 == TX Byte 1 ==
4808 20:00:54.540912 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4809 20:00:54.543991 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4810 20:00:54.544472
4811 20:00:54.547394 [DATLAT]
4812 20:00:54.547897 Freq=600, CH1 RK1
4813 20:00:54.548271
4814 20:00:54.550421 DATLAT Default: 0x9
4815 20:00:54.550875 0, 0xFFFF, sum = 0
4816 20:00:54.553727 1, 0xFFFF, sum = 0
4817 20:00:54.554189 2, 0xFFFF, sum = 0
4818 20:00:54.556889 3, 0xFFFF, sum = 0
4819 20:00:54.557349 4, 0xFFFF, sum = 0
4820 20:00:54.560223 5, 0xFFFF, sum = 0
4821 20:00:54.564340 6, 0xFFFF, sum = 0
4822 20:00:54.565004 7, 0xFFFF, sum = 0
4823 20:00:54.565705 8, 0x0, sum = 1
4824 20:00:54.566800 9, 0x0, sum = 2
4825 20:00:54.567271 10, 0x0, sum = 3
4826 20:00:54.570180 11, 0x0, sum = 4
4827 20:00:54.570650 best_step = 9
4828 20:00:54.571021
4829 20:00:54.571361 ==
4830 20:00:54.573372 Dram Type= 6, Freq= 0, CH_1, rank 1
4831 20:00:54.579831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4832 20:00:54.580256 ==
4833 20:00:54.580596 RX Vref Scan: 0
4834 20:00:54.580915
4835 20:00:54.583362 RX Vref 0 -> 0, step: 1
4836 20:00:54.583917
4837 20:00:54.586464 RX Delay -195 -> 252, step: 8
4838 20:00:54.589928 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4839 20:00:54.596755 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4840 20:00:54.600253 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4841 20:00:54.603825 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4842 20:00:54.606854 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4843 20:00:54.613031 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4844 20:00:54.617418 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4845 20:00:54.620282 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4846 20:00:54.622947 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4847 20:00:54.626385 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4848 20:00:54.633118 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4849 20:00:54.636343 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4850 20:00:54.639355 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4851 20:00:54.642975 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4852 20:00:54.649430 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4853 20:00:54.652555 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4854 20:00:54.652975 ==
4855 20:00:54.655946 Dram Type= 6, Freq= 0, CH_1, rank 1
4856 20:00:54.659572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4857 20:00:54.660145 ==
4858 20:00:54.662467 DQS Delay:
4859 20:00:54.662928 DQS0 = 0, DQS1 = 0
4860 20:00:54.665567 DQM Delay:
4861 20:00:54.666271 DQM0 = 45, DQM1 = 37
4862 20:00:54.666661 DQ Delay:
4863 20:00:54.669013 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4864 20:00:54.672553 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4865 20:00:54.675307 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4866 20:00:54.678974 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4867 20:00:54.679527
4868 20:00:54.679970
4869 20:00:54.688807 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4870 20:00:54.692599 CH1 RK1: MR19=808, MR18=2B20
4871 20:00:54.698669 CH1_RK1: MR19=0x808, MR18=0x2B20, DQSOSC=401, MR23=63, INC=163, DEC=108
4872 20:00:54.702033 [RxdqsGatingPostProcess] freq 600
4873 20:00:54.705250 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4874 20:00:54.708507 Pre-setting of DQS Precalculation
4875 20:00:54.715307 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4876 20:00:54.721610 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4877 20:00:54.728422 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4878 20:00:54.728986
4879 20:00:54.729361
4880 20:00:54.731704 [Calibration Summary] 1200 Mbps
4881 20:00:54.732326 CH 0, Rank 0
4882 20:00:54.734801 SW Impedance : PASS
4883 20:00:54.738403 DUTY Scan : NO K
4884 20:00:54.738950 ZQ Calibration : PASS
4885 20:00:54.741319 Jitter Meter : NO K
4886 20:00:54.744859 CBT Training : PASS
4887 20:00:54.745408 Write leveling : PASS
4888 20:00:54.748229 RX DQS gating : PASS
4889 20:00:54.748779 RX DQ/DQS(RDDQC) : PASS
4890 20:00:54.751298 TX DQ/DQS : PASS
4891 20:00:54.755016 RX DATLAT : PASS
4892 20:00:54.755561 RX DQ/DQS(Engine): PASS
4893 20:00:54.758753 TX OE : NO K
4894 20:00:54.759308 All Pass.
4895 20:00:54.759680
4896 20:00:54.761026 CH 0, Rank 1
4897 20:00:54.761490 SW Impedance : PASS
4898 20:00:54.765192 DUTY Scan : NO K
4899 20:00:54.767616 ZQ Calibration : PASS
4900 20:00:54.768287 Jitter Meter : NO K
4901 20:00:54.770969 CBT Training : PASS
4902 20:00:54.774471 Write leveling : PASS
4903 20:00:54.775027 RX DQS gating : PASS
4904 20:00:54.778282 RX DQ/DQS(RDDQC) : PASS
4905 20:00:54.782099 TX DQ/DQS : PASS
4906 20:00:54.782657 RX DATLAT : PASS
4907 20:00:54.784304 RX DQ/DQS(Engine): PASS
4908 20:00:54.787884 TX OE : NO K
4909 20:00:54.788437 All Pass.
4910 20:00:54.788812
4911 20:00:54.789157 CH 1, Rank 0
4912 20:00:54.790565 SW Impedance : PASS
4913 20:00:54.794327 DUTY Scan : NO K
4914 20:00:54.794881 ZQ Calibration : PASS
4915 20:00:54.797141 Jitter Meter : NO K
4916 20:00:54.800359 CBT Training : PASS
4917 20:00:54.800822 Write leveling : PASS
4918 20:00:54.803953 RX DQS gating : PASS
4919 20:00:54.807038 RX DQ/DQS(RDDQC) : PASS
4920 20:00:54.807517 TX DQ/DQS : PASS
4921 20:00:54.810803 RX DATLAT : PASS
4922 20:00:54.813910 RX DQ/DQS(Engine): PASS
4923 20:00:54.814463 TX OE : NO K
4924 20:00:54.817169 All Pass.
4925 20:00:54.817719
4926 20:00:54.818088 CH 1, Rank 1
4927 20:00:54.820162 SW Impedance : PASS
4928 20:00:54.820630 DUTY Scan : NO K
4929 20:00:54.823600 ZQ Calibration : PASS
4930 20:00:54.826906 Jitter Meter : NO K
4931 20:00:54.827462 CBT Training : PASS
4932 20:00:54.830507 Write leveling : PASS
4933 20:00:54.833512 RX DQS gating : PASS
4934 20:00:54.834064 RX DQ/DQS(RDDQC) : PASS
4935 20:00:54.836593 TX DQ/DQS : PASS
4936 20:00:54.840707 RX DATLAT : PASS
4937 20:00:54.841261 RX DQ/DQS(Engine): PASS
4938 20:00:54.844102 TX OE : NO K
4939 20:00:54.844658 All Pass.
4940 20:00:54.845038
4941 20:00:54.846795 DramC Write-DBI off
4942 20:00:54.850140 PER_BANK_REFRESH: Hybrid Mode
4943 20:00:54.850610 TX_TRACKING: ON
4944 20:00:54.859975 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4945 20:00:54.863187 [FAST_K] Save calibration result to emmc
4946 20:00:54.866577 dramc_set_vcore_voltage set vcore to 662500
4947 20:00:54.869819 Read voltage for 933, 3
4948 20:00:54.870375 Vio18 = 0
4949 20:00:54.870745 Vcore = 662500
4950 20:00:54.873087 Vdram = 0
4951 20:00:54.873545 Vddq = 0
4952 20:00:54.873907 Vmddr = 0
4953 20:00:54.880037 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4954 20:00:54.883571 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4955 20:00:54.886800 MEM_TYPE=3, freq_sel=17
4956 20:00:54.889900 sv_algorithm_assistance_LP4_1600
4957 20:00:54.893394 ============ PULL DRAM RESETB DOWN ============
4958 20:00:54.897111 ========== PULL DRAM RESETB DOWN end =========
4959 20:00:54.902812 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4960 20:00:54.906121 ===================================
4961 20:00:54.906681 LPDDR4 DRAM CONFIGURATION
4962 20:00:54.909224 ===================================
4963 20:00:54.912928 EX_ROW_EN[0] = 0x0
4964 20:00:54.915970 EX_ROW_EN[1] = 0x0
4965 20:00:54.916520 LP4Y_EN = 0x0
4966 20:00:54.920108 WORK_FSP = 0x0
4967 20:00:54.920666 WL = 0x3
4968 20:00:54.922374 RL = 0x3
4969 20:00:54.922850 BL = 0x2
4970 20:00:54.926192 RPST = 0x0
4971 20:00:54.926761 RD_PRE = 0x0
4972 20:00:54.929030 WR_PRE = 0x1
4973 20:00:54.929490 WR_PST = 0x0
4974 20:00:54.932678 DBI_WR = 0x0
4975 20:00:54.933232 DBI_RD = 0x0
4976 20:00:54.935875 OTF = 0x1
4977 20:00:54.939098 ===================================
4978 20:00:54.942355 ===================================
4979 20:00:54.942894 ANA top config
4980 20:00:54.945943 ===================================
4981 20:00:54.948765 DLL_ASYNC_EN = 0
4982 20:00:54.952542 ALL_SLAVE_EN = 1
4983 20:00:54.956141 NEW_RANK_MODE = 1
4984 20:00:54.958528 DLL_IDLE_MODE = 1
4985 20:00:54.958973 LP45_APHY_COMB_EN = 1
4986 20:00:54.962090 TX_ODT_DIS = 1
4987 20:00:54.965467 NEW_8X_MODE = 1
4988 20:00:54.968578 ===================================
4989 20:00:54.972319 ===================================
4990 20:00:54.975575 data_rate = 1866
4991 20:00:54.978394 CKR = 1
4992 20:00:54.978948 DQ_P2S_RATIO = 8
4993 20:00:54.981791 ===================================
4994 20:00:54.985573 CA_P2S_RATIO = 8
4995 20:00:54.988252 DQ_CA_OPEN = 0
4996 20:00:54.991885 DQ_SEMI_OPEN = 0
4997 20:00:54.995041 CA_SEMI_OPEN = 0
4998 20:00:54.998417 CA_FULL_RATE = 0
4999 20:00:54.998971 DQ_CKDIV4_EN = 1
5000 20:00:55.002029 CA_CKDIV4_EN = 1
5001 20:00:55.004962 CA_PREDIV_EN = 0
5002 20:00:55.008777 PH8_DLY = 0
5003 20:00:55.011614 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5004 20:00:55.014908 DQ_AAMCK_DIV = 4
5005 20:00:55.015460 CA_AAMCK_DIV = 4
5006 20:00:55.017968 CA_ADMCK_DIV = 4
5007 20:00:55.021414 DQ_TRACK_CA_EN = 0
5008 20:00:55.024837 CA_PICK = 933
5009 20:00:55.028793 CA_MCKIO = 933
5010 20:00:55.031422 MCKIO_SEMI = 0
5011 20:00:55.034756 PLL_FREQ = 3732
5012 20:00:55.038288 DQ_UI_PI_RATIO = 32
5013 20:00:55.038840 CA_UI_PI_RATIO = 0
5014 20:00:55.041112 ===================================
5015 20:00:55.044346 ===================================
5016 20:00:55.047990 memory_type:LPDDR4
5017 20:00:55.051446 GP_NUM : 10
5018 20:00:55.052061 SRAM_EN : 1
5019 20:00:55.054653 MD32_EN : 0
5020 20:00:55.057579 ===================================
5021 20:00:55.061479 [ANA_INIT] >>>>>>>>>>>>>>
5022 20:00:55.062040 <<<<<< [CONFIGURE PHASE]: ANA_TX
5023 20:00:55.067756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5024 20:00:55.071087 ===================================
5025 20:00:55.071776 data_rate = 1866,PCW = 0X8f00
5026 20:00:55.074218 ===================================
5027 20:00:55.077941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5028 20:00:55.084252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5029 20:00:55.090666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5030 20:00:55.093881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5031 20:00:55.097182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5032 20:00:55.100686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5033 20:00:55.104550 [ANA_INIT] flow start
5034 20:00:55.107385 [ANA_INIT] PLL >>>>>>>>
5035 20:00:55.107992 [ANA_INIT] PLL <<<<<<<<
5036 20:00:55.111017 [ANA_INIT] MIDPI >>>>>>>>
5037 20:00:55.114258 [ANA_INIT] MIDPI <<<<<<<<
5038 20:00:55.114816 [ANA_INIT] DLL >>>>>>>>
5039 20:00:55.116730 [ANA_INIT] flow end
5040 20:00:55.120643 ============ LP4 DIFF to SE enter ============
5041 20:00:55.123580 ============ LP4 DIFF to SE exit ============
5042 20:00:55.127065 [ANA_INIT] <<<<<<<<<<<<<
5043 20:00:55.130372 [Flow] Enable top DCM control >>>>>
5044 20:00:55.133536 [Flow] Enable top DCM control <<<<<
5045 20:00:55.136966 Enable DLL master slave shuffle
5046 20:00:55.143225 ==============================================================
5047 20:00:55.143810 Gating Mode config
5048 20:00:55.149953 ==============================================================
5049 20:00:55.153200 Config description:
5050 20:00:55.159858 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5051 20:00:55.166165 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5052 20:00:55.173020 SELPH_MODE 0: By rank 1: By Phase
5053 20:00:55.179688 ==============================================================
5054 20:00:55.182955 GAT_TRACK_EN = 1
5055 20:00:55.183508 RX_GATING_MODE = 2
5056 20:00:55.186313 RX_GATING_TRACK_MODE = 2
5057 20:00:55.189185 SELPH_MODE = 1
5058 20:00:55.192539 PICG_EARLY_EN = 1
5059 20:00:55.196322 VALID_LAT_VALUE = 1
5060 20:00:55.202812 ==============================================================
5061 20:00:55.206156 Enter into Gating configuration >>>>
5062 20:00:55.209041 Exit from Gating configuration <<<<
5063 20:00:55.212541 Enter into DVFS_PRE_config >>>>>
5064 20:00:55.223176 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5065 20:00:55.225992 Exit from DVFS_PRE_config <<<<<
5066 20:00:55.228666 Enter into PICG configuration >>>>
5067 20:00:55.232419 Exit from PICG configuration <<<<
5068 20:00:55.235908 [RX_INPUT] configuration >>>>>
5069 20:00:55.239313 [RX_INPUT] configuration <<<<<
5070 20:00:55.242248 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5071 20:00:55.248949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5072 20:00:55.255461 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5073 20:00:55.261863 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5074 20:00:55.265702 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5075 20:00:55.271797 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5076 20:00:55.275269 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5077 20:00:55.281950 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5078 20:00:55.285144 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5079 20:00:55.288525 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5080 20:00:55.291910 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5081 20:00:55.299105 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5082 20:00:55.301312 ===================================
5083 20:00:55.304573 LPDDR4 DRAM CONFIGURATION
5084 20:00:55.307934 ===================================
5085 20:00:55.308402 EX_ROW_EN[0] = 0x0
5086 20:00:55.312058 EX_ROW_EN[1] = 0x0
5087 20:00:55.312623 LP4Y_EN = 0x0
5088 20:00:55.314816 WORK_FSP = 0x0
5089 20:00:55.315366 WL = 0x3
5090 20:00:55.318339 RL = 0x3
5091 20:00:55.318896 BL = 0x2
5092 20:00:55.321437 RPST = 0x0
5093 20:00:55.321905 RD_PRE = 0x0
5094 20:00:55.324445 WR_PRE = 0x1
5095 20:00:55.327891 WR_PST = 0x0
5096 20:00:55.328436 DBI_WR = 0x0
5097 20:00:55.331412 DBI_RD = 0x0
5098 20:00:55.332126 OTF = 0x1
5099 20:00:55.335692 ===================================
5100 20:00:55.337689 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5101 20:00:55.341517 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5102 20:00:55.348217 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5103 20:00:55.351049 ===================================
5104 20:00:55.354626 LPDDR4 DRAM CONFIGURATION
5105 20:00:55.357997 ===================================
5106 20:00:55.358458 EX_ROW_EN[0] = 0x10
5107 20:00:55.361544 EX_ROW_EN[1] = 0x0
5108 20:00:55.362130 LP4Y_EN = 0x0
5109 20:00:55.364086 WORK_FSP = 0x0
5110 20:00:55.364547 WL = 0x3
5111 20:00:55.367659 RL = 0x3
5112 20:00:55.368257 BL = 0x2
5113 20:00:55.371330 RPST = 0x0
5114 20:00:55.371844 RD_PRE = 0x0
5115 20:00:55.374474 WR_PRE = 0x1
5116 20:00:55.377630 WR_PST = 0x0
5117 20:00:55.378180 DBI_WR = 0x0
5118 20:00:55.380680 DBI_RD = 0x0
5119 20:00:55.381138 OTF = 0x1
5120 20:00:55.383632 ===================================
5121 20:00:55.390784 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5122 20:00:55.394563 nWR fixed to 30
5123 20:00:55.397765 [ModeRegInit_LP4] CH0 RK0
5124 20:00:55.398355 [ModeRegInit_LP4] CH0 RK1
5125 20:00:55.401081 [ModeRegInit_LP4] CH1 RK0
5126 20:00:55.404298 [ModeRegInit_LP4] CH1 RK1
5127 20:00:55.404758 match AC timing 9
5128 20:00:55.410755 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5129 20:00:55.414074 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5130 20:00:55.417433 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5131 20:00:55.424007 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5132 20:00:55.427099 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5133 20:00:55.427655 ==
5134 20:00:55.430527 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 20:00:55.434297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 20:00:55.436857 ==
5137 20:00:55.440822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 20:00:55.446991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5139 20:00:55.450346 [CA 0] Center 38 (7~69) winsize 63
5140 20:00:55.453987 [CA 1] Center 37 (7~68) winsize 62
5141 20:00:55.457192 [CA 2] Center 34 (4~65) winsize 62
5142 20:00:55.460525 [CA 3] Center 35 (5~65) winsize 61
5143 20:00:55.463554 [CA 4] Center 33 (3~64) winsize 62
5144 20:00:55.466943 [CA 5] Center 33 (3~64) winsize 62
5145 20:00:55.467494
5146 20:00:55.469900 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5147 20:00:55.470584
5148 20:00:55.473717 [CATrainingPosCal] consider 1 rank data
5149 20:00:55.476655 u2DelayCellTimex100 = 270/100 ps
5150 20:00:55.480346 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5151 20:00:55.483613 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5152 20:00:55.486803 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5153 20:00:55.493707 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5154 20:00:55.496632 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5155 20:00:55.499624 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5156 20:00:55.500125
5157 20:00:55.503266 CA PerBit enable=1, Macro0, CA PI delay=33
5158 20:00:55.503809
5159 20:00:55.506110 [CBTSetCACLKResult] CA Dly = 33
5160 20:00:55.506574 CS Dly: 7 (0~38)
5161 20:00:55.506943 ==
5162 20:00:55.509695 Dram Type= 6, Freq= 0, CH_0, rank 1
5163 20:00:55.516427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 20:00:55.516981 ==
5165 20:00:55.519662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5166 20:00:55.526733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5167 20:00:55.529659 [CA 0] Center 37 (7~68) winsize 62
5168 20:00:55.532957 [CA 1] Center 37 (7~68) winsize 62
5169 20:00:55.536297 [CA 2] Center 34 (4~65) winsize 62
5170 20:00:55.539136 [CA 3] Center 34 (4~65) winsize 62
5171 20:00:55.542348 [CA 4] Center 33 (3~64) winsize 62
5172 20:00:55.545662 [CA 5] Center 32 (2~63) winsize 62
5173 20:00:55.546124
5174 20:00:55.549118 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5175 20:00:55.549665
5176 20:00:55.552571 [CATrainingPosCal] consider 2 rank data
5177 20:00:55.555567 u2DelayCellTimex100 = 270/100 ps
5178 20:00:55.559241 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5179 20:00:55.565672 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5180 20:00:55.570259 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5181 20:00:55.571901 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5182 20:00:55.575800 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5183 20:00:55.579602 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5184 20:00:55.580244
5185 20:00:55.581714 CA PerBit enable=1, Macro0, CA PI delay=33
5186 20:00:55.582179
5187 20:00:55.585123 [CBTSetCACLKResult] CA Dly = 33
5188 20:00:55.589061 CS Dly: 7 (0~39)
5189 20:00:55.589634
5190 20:00:55.591916 ----->DramcWriteLeveling(PI) begin...
5191 20:00:55.592389 ==
5192 20:00:55.595923 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 20:00:55.598746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 20:00:55.599217 ==
5195 20:00:55.601945 Write leveling (Byte 0): 32 => 32
5196 20:00:55.604910 Write leveling (Byte 1): 30 => 30
5197 20:00:55.608940 DramcWriteLeveling(PI) end<-----
5198 20:00:55.609515
5199 20:00:55.609886 ==
5200 20:00:55.611953 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 20:00:55.615356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 20:00:55.615966 ==
5203 20:00:55.618413 [Gating] SW mode calibration
5204 20:00:55.625032 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5205 20:00:55.631600 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5206 20:00:55.635296 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5207 20:00:55.641382 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5208 20:00:55.645024 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 20:00:55.648325 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 20:00:55.651972 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 20:00:55.658184 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5212 20:00:55.661550 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5213 20:00:55.664688 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
5214 20:00:55.671404 0 15 0 | B1->B0 | 3232 2727 | 1 0 | (1 0) (1 0)
5215 20:00:55.674935 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5216 20:00:55.677754 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 20:00:55.684130 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 20:00:55.687617 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 20:00:55.691366 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5220 20:00:55.698103 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5221 20:00:55.700881 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
5222 20:00:55.704403 1 0 0 | B1->B0 | 3332 4444 | 1 0 | (0 0) (0 0)
5223 20:00:55.710609 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 20:00:55.714004 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 20:00:55.717544 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 20:00:55.724775 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 20:00:55.727369 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 20:00:55.730695 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5229 20:00:55.737494 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5230 20:00:55.740393 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5231 20:00:55.743767 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 20:00:55.750642 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 20:00:55.753874 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 20:00:55.756956 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 20:00:55.763590 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 20:00:55.767997 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 20:00:55.770256 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 20:00:55.777171 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 20:00:55.780033 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 20:00:55.783846 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 20:00:55.790206 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 20:00:55.793324 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 20:00:55.796525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 20:00:55.802949 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5245 20:00:55.806464 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5246 20:00:55.809535 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5247 20:00:55.813280 Total UI for P1: 0, mck2ui 16
5248 20:00:55.816446 best dqsien dly found for B0: ( 1, 2, 26)
5249 20:00:55.823172 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5250 20:00:55.823788 Total UI for P1: 0, mck2ui 16
5251 20:00:55.829675 best dqsien dly found for B1: ( 1, 3, 0)
5252 20:00:55.833720 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5253 20:00:55.836355 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5254 20:00:55.836917
5255 20:00:55.839472 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5256 20:00:55.843168 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5257 20:00:55.846396 [Gating] SW calibration Done
5258 20:00:55.846952 ==
5259 20:00:55.849685 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 20:00:55.852704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 20:00:55.853176 ==
5262 20:00:55.856617 RX Vref Scan: 0
5263 20:00:55.857176
5264 20:00:55.857547 RX Vref 0 -> 0, step: 1
5265 20:00:55.857895
5266 20:00:55.859006 RX Delay -80 -> 252, step: 8
5267 20:00:55.865818 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5268 20:00:55.868923 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5269 20:00:55.872222 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5270 20:00:55.875656 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5271 20:00:55.879358 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5272 20:00:55.882162 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5273 20:00:55.889120 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5274 20:00:55.892127 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5275 20:00:55.895697 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5276 20:00:55.899023 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5277 20:00:55.902170 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5278 20:00:55.908548 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5279 20:00:55.911874 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5280 20:00:55.915183 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5281 20:00:55.918799 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5282 20:00:55.922362 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5283 20:00:55.925016 ==
5284 20:00:55.925477 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 20:00:55.932112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 20:00:55.932573 ==
5287 20:00:55.932937 DQS Delay:
5288 20:00:55.935098 DQS0 = 0, DQS1 = 0
5289 20:00:55.935674 DQM Delay:
5290 20:00:55.938345 DQM0 = 97, DQM1 = 85
5291 20:00:55.938896 DQ Delay:
5292 20:00:55.941919 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5293 20:00:55.945180 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5294 20:00:55.948375 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5295 20:00:55.951600 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5296 20:00:55.952207
5297 20:00:55.952580
5298 20:00:55.952922 ==
5299 20:00:55.954890 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 20:00:55.958346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 20:00:55.958906 ==
5302 20:00:55.959278
5303 20:00:55.959620
5304 20:00:55.961497 TX Vref Scan disable
5305 20:00:55.964852 == TX Byte 0 ==
5306 20:00:55.968098 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5307 20:00:55.971529 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5308 20:00:55.974545 == TX Byte 1 ==
5309 20:00:55.977947 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5310 20:00:55.981027 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5311 20:00:55.981497 ==
5312 20:00:55.984431 Dram Type= 6, Freq= 0, CH_0, rank 0
5313 20:00:55.991436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 20:00:55.992228 ==
5315 20:00:55.992624
5316 20:00:55.992964
5317 20:00:55.993291 TX Vref Scan disable
5318 20:00:55.995299 == TX Byte 0 ==
5319 20:00:55.998478 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5320 20:00:56.005176 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5321 20:00:56.005726 == TX Byte 1 ==
5322 20:00:56.008350 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5323 20:00:56.015326 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5324 20:00:56.015955
5325 20:00:56.016337 [DATLAT]
5326 20:00:56.016679 Freq=933, CH0 RK0
5327 20:00:56.017013
5328 20:00:56.018064 DATLAT Default: 0xd
5329 20:00:56.018519 0, 0xFFFF, sum = 0
5330 20:00:56.021532 1, 0xFFFF, sum = 0
5331 20:00:56.025192 2, 0xFFFF, sum = 0
5332 20:00:56.025755 3, 0xFFFF, sum = 0
5333 20:00:56.028042 4, 0xFFFF, sum = 0
5334 20:00:56.028512 5, 0xFFFF, sum = 0
5335 20:00:56.032199 6, 0xFFFF, sum = 0
5336 20:00:56.032756 7, 0xFFFF, sum = 0
5337 20:00:56.034854 8, 0xFFFF, sum = 0
5338 20:00:56.035417 9, 0xFFFF, sum = 0
5339 20:00:56.037855 10, 0x0, sum = 1
5340 20:00:56.038322 11, 0x0, sum = 2
5341 20:00:56.041232 12, 0x0, sum = 3
5342 20:00:56.041796 13, 0x0, sum = 4
5343 20:00:56.042172 best_step = 11
5344 20:00:56.044540
5345 20:00:56.045002 ==
5346 20:00:56.048435 Dram Type= 6, Freq= 0, CH_0, rank 0
5347 20:00:56.051386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 20:00:56.051973 ==
5349 20:00:56.052349 RX Vref Scan: 1
5350 20:00:56.052740
5351 20:00:56.054267 RX Vref 0 -> 0, step: 1
5352 20:00:56.054833
5353 20:00:56.057809 RX Delay -61 -> 252, step: 4
5354 20:00:56.058269
5355 20:00:56.061070 Set Vref, RX VrefLevel [Byte0]: 63
5356 20:00:56.064681 [Byte1]: 49
5357 20:00:56.068346
5358 20:00:56.068896 Final RX Vref Byte 0 = 63 to rank0
5359 20:00:56.071095 Final RX Vref Byte 1 = 49 to rank0
5360 20:00:56.074244 Final RX Vref Byte 0 = 63 to rank1
5361 20:00:56.077468 Final RX Vref Byte 1 = 49 to rank1==
5362 20:00:56.080742 Dram Type= 6, Freq= 0, CH_0, rank 0
5363 20:00:56.087068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 20:00:56.087528 ==
5365 20:00:56.087976 DQS Delay:
5366 20:00:56.090329 DQS0 = 0, DQS1 = 0
5367 20:00:56.090780 DQM Delay:
5368 20:00:56.091140 DQM0 = 97, DQM1 = 85
5369 20:00:56.093864 DQ Delay:
5370 20:00:56.097247 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5371 20:00:56.100260 DQ4 =96, DQ5 =88, DQ6 =110, DQ7 =106
5372 20:00:56.103761 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5373 20:00:56.106932 DQ12 =88, DQ13 =90, DQ14 =96, DQ15 =92
5374 20:00:56.107388
5375 20:00:56.107780
5376 20:00:56.114255 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
5377 20:00:56.117072 CH0 RK0: MR19=505, MR18=2C13
5378 20:00:56.123923 CH0_RK0: MR19=0x505, MR18=0x2C13, DQSOSC=408, MR23=63, INC=65, DEC=43
5379 20:00:56.124468
5380 20:00:56.127117 ----->DramcWriteLeveling(PI) begin...
5381 20:00:56.127671 ==
5382 20:00:56.130047 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 20:00:56.133271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 20:00:56.133722 ==
5385 20:00:56.136894 Write leveling (Byte 0): 33 => 33
5386 20:00:56.140549 Write leveling (Byte 1): 29 => 29
5387 20:00:56.143429 DramcWriteLeveling(PI) end<-----
5388 20:00:56.144042
5389 20:00:56.144410 ==
5390 20:00:56.147485 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 20:00:56.153564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 20:00:56.154121 ==
5393 20:00:56.154486 [Gating] SW mode calibration
5394 20:00:56.163400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5395 20:00:56.166192 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5396 20:00:56.169954 0 14 0 | B1->B0 | 2929 3333 | 0 0 | (0 0) (0 0)
5397 20:00:56.176208 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 20:00:56.180208 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 20:00:56.183382 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 20:00:56.189940 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 20:00:56.192555 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 20:00:56.196077 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5403 20:00:56.203077 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
5404 20:00:56.205804 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5405 20:00:56.209350 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 20:00:56.215592 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 20:00:56.219358 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 20:00:56.226045 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 20:00:56.229673 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5410 20:00:56.232673 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5411 20:00:56.239288 0 15 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5412 20:00:56.242210 1 0 0 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5413 20:00:56.245880 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 20:00:56.251797 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 20:00:56.255385 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 20:00:56.258797 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 20:00:56.264975 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 20:00:56.268417 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 20:00:56.271617 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5420 20:00:56.277936 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5421 20:00:56.281952 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 20:00:56.284713 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 20:00:56.291658 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 20:00:56.294946 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 20:00:56.298314 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 20:00:56.304495 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 20:00:56.308086 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 20:00:56.311115 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 20:00:56.317985 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 20:00:56.321490 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 20:00:56.325539 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 20:00:56.331053 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 20:00:56.334631 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 20:00:56.338136 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 20:00:56.344764 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5436 20:00:56.347917 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5437 20:00:56.350709 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 20:00:56.354467 Total UI for P1: 0, mck2ui 16
5439 20:00:56.357354 best dqsien dly found for B0: ( 1, 2, 30)
5440 20:00:56.360742 Total UI for P1: 0, mck2ui 16
5441 20:00:56.364042 best dqsien dly found for B1: ( 1, 3, 0)
5442 20:00:56.367178 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5443 20:00:56.371116 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5444 20:00:56.371822
5445 20:00:56.374346 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5446 20:00:56.381303 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5447 20:00:56.381869 [Gating] SW calibration Done
5448 20:00:56.382245 ==
5449 20:00:56.383467 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 20:00:56.390365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 20:00:56.390930 ==
5452 20:00:56.391298 RX Vref Scan: 0
5453 20:00:56.391644
5454 20:00:56.393797 RX Vref 0 -> 0, step: 1
5455 20:00:56.394355
5456 20:00:56.397256 RX Delay -80 -> 252, step: 8
5457 20:00:56.399961 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5458 20:00:56.403803 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5459 20:00:56.406661 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5460 20:00:56.413621 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5461 20:00:56.416808 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5462 20:00:56.420022 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5463 20:00:56.423095 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5464 20:00:56.426290 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5465 20:00:56.429917 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5466 20:00:56.436435 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5467 20:00:56.439538 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5468 20:00:56.442925 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5469 20:00:56.445928 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5470 20:00:56.449453 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5471 20:00:56.456140 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5472 20:00:56.459539 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5473 20:00:56.460145 ==
5474 20:00:56.463503 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 20:00:56.466776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 20:00:56.467239 ==
5477 20:00:56.469297 DQS Delay:
5478 20:00:56.469758 DQS0 = 0, DQS1 = 0
5479 20:00:56.470125 DQM Delay:
5480 20:00:56.472585 DQM0 = 98, DQM1 = 87
5481 20:00:56.473053 DQ Delay:
5482 20:00:56.475514 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5483 20:00:56.478884 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5484 20:00:56.482290 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5485 20:00:56.485713 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5486 20:00:56.486289
5487 20:00:56.486659
5488 20:00:56.486995 ==
5489 20:00:56.488687 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 20:00:56.495446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 20:00:56.496056 ==
5492 20:00:56.496424
5493 20:00:56.496761
5494 20:00:56.497083 TX Vref Scan disable
5495 20:00:56.499648 == TX Byte 0 ==
5496 20:00:56.502538 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5497 20:00:56.509500 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5498 20:00:56.509978 == TX Byte 1 ==
5499 20:00:56.512609 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5500 20:00:56.519870 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5501 20:00:56.520422 ==
5502 20:00:56.523211 Dram Type= 6, Freq= 0, CH_0, rank 1
5503 20:00:56.525863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 20:00:56.526323 ==
5505 20:00:56.526741
5506 20:00:56.527081
5507 20:00:56.529232 TX Vref Scan disable
5508 20:00:56.529792 == TX Byte 0 ==
5509 20:00:56.536173 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5510 20:00:56.539363 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5511 20:00:56.539974 == TX Byte 1 ==
5512 20:00:56.545996 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5513 20:00:56.548973 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5514 20:00:56.549533
5515 20:00:56.549900 [DATLAT]
5516 20:00:56.552684 Freq=933, CH0 RK1
5517 20:00:56.553234
5518 20:00:56.553603 DATLAT Default: 0xb
5519 20:00:56.555534 0, 0xFFFF, sum = 0
5520 20:00:56.556155 1, 0xFFFF, sum = 0
5521 20:00:56.558965 2, 0xFFFF, sum = 0
5522 20:00:56.561957 3, 0xFFFF, sum = 0
5523 20:00:56.562422 4, 0xFFFF, sum = 0
5524 20:00:56.565466 5, 0xFFFF, sum = 0
5525 20:00:56.565937 6, 0xFFFF, sum = 0
5526 20:00:56.568815 7, 0xFFFF, sum = 0
5527 20:00:56.569285 8, 0xFFFF, sum = 0
5528 20:00:56.572545 9, 0xFFFF, sum = 0
5529 20:00:56.573016 10, 0x0, sum = 1
5530 20:00:56.575481 11, 0x0, sum = 2
5531 20:00:56.576242 12, 0x0, sum = 3
5532 20:00:56.578708 13, 0x0, sum = 4
5533 20:00:56.579275 best_step = 11
5534 20:00:56.579645
5535 20:00:56.580044 ==
5536 20:00:56.581930 Dram Type= 6, Freq= 0, CH_0, rank 1
5537 20:00:56.585023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 20:00:56.585590 ==
5539 20:00:56.588269 RX Vref Scan: 0
5540 20:00:56.588730
5541 20:00:56.591664 RX Vref 0 -> 0, step: 1
5542 20:00:56.592183
5543 20:00:56.592555 RX Delay -61 -> 252, step: 4
5544 20:00:56.600196 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5545 20:00:56.603269 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5546 20:00:56.606321 iDelay=203, Bit 2, Center 92 (-1 ~ 186) 188
5547 20:00:56.610313 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5548 20:00:56.613340 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5549 20:00:56.619883 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5550 20:00:56.622804 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5551 20:00:56.626149 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5552 20:00:56.629756 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5553 20:00:56.632861 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5554 20:00:56.639410 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5555 20:00:56.643159 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5556 20:00:56.646254 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5557 20:00:56.649319 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5558 20:00:56.653050 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5559 20:00:56.659450 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5560 20:00:56.660064 ==
5561 20:00:56.662845 Dram Type= 6, Freq= 0, CH_0, rank 1
5562 20:00:56.665914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 20:00:56.666374 ==
5564 20:00:56.666743 DQS Delay:
5565 20:00:56.669181 DQS0 = 0, DQS1 = 0
5566 20:00:56.669743 DQM Delay:
5567 20:00:56.672654 DQM0 = 95, DQM1 = 86
5568 20:00:56.673115 DQ Delay:
5569 20:00:56.676136 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =92
5570 20:00:56.679106 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5571 20:00:56.682384 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5572 20:00:56.685738 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =92
5573 20:00:56.686298
5574 20:00:56.686669
5575 20:00:56.695576 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfa, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 408 ps
5576 20:00:56.696170 CH0 RK1: MR19=504, MR18=2BFA
5577 20:00:56.702342 CH0_RK1: MR19=0x504, MR18=0x2BFA, DQSOSC=408, MR23=63, INC=65, DEC=43
5578 20:00:56.705656 [RxdqsGatingPostProcess] freq 933
5579 20:00:56.712030 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5580 20:00:56.715473 best DQS0 dly(2T, 0.5T) = (0, 10)
5581 20:00:56.718793 best DQS1 dly(2T, 0.5T) = (0, 11)
5582 20:00:56.722485 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5583 20:00:56.725071 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5584 20:00:56.729132 best DQS0 dly(2T, 0.5T) = (0, 10)
5585 20:00:56.729691 best DQS1 dly(2T, 0.5T) = (0, 11)
5586 20:00:56.731972 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5587 20:00:56.735523 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5588 20:00:56.738835 Pre-setting of DQS Precalculation
5589 20:00:56.745837 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5590 20:00:56.746408 ==
5591 20:00:56.748188 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 20:00:56.751579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 20:00:56.752193 ==
5594 20:00:56.758774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 20:00:56.764779 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5596 20:00:56.768219 [CA 0] Center 36 (6~67) winsize 62
5597 20:00:56.771470 [CA 1] Center 36 (6~67) winsize 62
5598 20:00:56.774741 [CA 2] Center 34 (4~65) winsize 62
5599 20:00:56.777976 [CA 3] Center 33 (3~64) winsize 62
5600 20:00:56.781124 [CA 4] Center 34 (4~64) winsize 61
5601 20:00:56.784930 [CA 5] Center 33 (3~64) winsize 62
5602 20:00:56.785485
5603 20:00:56.787615 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5604 20:00:56.788126
5605 20:00:56.791617 [CATrainingPosCal] consider 1 rank data
5606 20:00:56.795385 u2DelayCellTimex100 = 270/100 ps
5607 20:00:56.797573 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5608 20:00:56.801180 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5609 20:00:56.804408 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5610 20:00:56.807807 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5611 20:00:56.811103 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5612 20:00:56.814669 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5613 20:00:56.815129
5614 20:00:56.821095 CA PerBit enable=1, Macro0, CA PI delay=33
5615 20:00:56.821646
5616 20:00:56.824503 [CBTSetCACLKResult] CA Dly = 33
5617 20:00:56.824962 CS Dly: 6 (0~37)
5618 20:00:56.825330 ==
5619 20:00:56.827446 Dram Type= 6, Freq= 0, CH_1, rank 1
5620 20:00:56.830790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 20:00:56.831250 ==
5622 20:00:56.837414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5623 20:00:56.844926 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5624 20:00:56.847110 [CA 0] Center 36 (6~67) winsize 62
5625 20:00:56.851105 [CA 1] Center 36 (6~67) winsize 62
5626 20:00:56.854209 [CA 2] Center 34 (4~65) winsize 62
5627 20:00:56.857329 [CA 3] Center 33 (3~64) winsize 62
5628 20:00:56.860556 [CA 4] Center 34 (3~65) winsize 63
5629 20:00:56.864038 [CA 5] Center 33 (3~64) winsize 62
5630 20:00:56.864500
5631 20:00:56.867468 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5632 20:00:56.867959
5633 20:00:56.870851 [CATrainingPosCal] consider 2 rank data
5634 20:00:56.873897 u2DelayCellTimex100 = 270/100 ps
5635 20:00:56.877249 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5636 20:00:56.881109 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5637 20:00:56.883657 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5638 20:00:56.887399 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5639 20:00:56.893942 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5640 20:00:56.897611 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5641 20:00:56.898172
5642 20:00:56.899792 CA PerBit enable=1, Macro0, CA PI delay=33
5643 20:00:56.900257
5644 20:00:56.903178 [CBTSetCACLKResult] CA Dly = 33
5645 20:00:56.903639 CS Dly: 7 (0~39)
5646 20:00:56.904054
5647 20:00:56.906524 ----->DramcWriteLeveling(PI) begin...
5648 20:00:56.906993 ==
5649 20:00:56.911156 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 20:00:56.916557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 20:00:56.917029 ==
5652 20:00:56.920532 Write leveling (Byte 0): 27 => 27
5653 20:00:56.923509 Write leveling (Byte 1): 30 => 30
5654 20:00:56.924120 DramcWriteLeveling(PI) end<-----
5655 20:00:56.926796
5656 20:00:56.927323 ==
5657 20:00:56.930255 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 20:00:56.933186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 20:00:56.933751 ==
5660 20:00:56.936662 [Gating] SW mode calibration
5661 20:00:56.942921 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5662 20:00:56.949380 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5663 20:00:56.953222 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5664 20:00:56.956443 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 20:00:56.962675 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 20:00:56.966038 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 20:00:56.969355 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5668 20:00:56.975872 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5669 20:00:56.979285 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5670 20:00:56.982400 0 14 28 | B1->B0 | 2727 2828 | 0 0 | (1 0) (0 0)
5671 20:00:56.989384 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5672 20:00:56.992649 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 20:00:56.995750 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 20:00:57.002187 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 20:00:57.005260 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5676 20:00:57.008468 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5677 20:00:57.015575 0 15 24 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
5678 20:00:57.019034 0 15 28 | B1->B0 | 3b3b 3b3b | 0 1 | (0 0) (0 0)
5679 20:00:57.021891 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 20:00:57.028573 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 20:00:57.032132 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 20:00:57.035357 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 20:00:57.041833 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 20:00:57.045060 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5685 20:00:57.048437 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5686 20:00:57.055036 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5687 20:00:57.058150 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 20:00:57.061293 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 20:00:57.068318 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 20:00:57.071564 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 20:00:57.075237 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 20:00:57.078319 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 20:00:57.084952 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 20:00:57.088274 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 20:00:57.091689 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 20:00:57.098325 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 20:00:57.101157 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 20:00:57.107952 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 20:00:57.111185 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 20:00:57.114762 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 20:00:57.117575 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5702 20:00:57.124654 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5703 20:00:57.127483 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5704 20:00:57.131024 Total UI for P1: 0, mck2ui 16
5705 20:00:57.134275 best dqsien dly found for B0: ( 1, 2, 26)
5706 20:00:57.137923 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5707 20:00:57.141167 Total UI for P1: 0, mck2ui 16
5708 20:00:57.144429 best dqsien dly found for B1: ( 1, 2, 28)
5709 20:00:57.147849 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5710 20:00:57.154075 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5711 20:00:57.154635
5712 20:00:57.157234 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5713 20:00:57.160459 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5714 20:00:57.163762 [Gating] SW calibration Done
5715 20:00:57.164317 ==
5716 20:00:57.166971 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 20:00:57.170660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 20:00:57.171216 ==
5719 20:00:57.174093 RX Vref Scan: 0
5720 20:00:57.174653
5721 20:00:57.175024 RX Vref 0 -> 0, step: 1
5722 20:00:57.175372
5723 20:00:57.176873 RX Delay -80 -> 252, step: 8
5724 20:00:57.181015 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5725 20:00:57.183487 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5726 20:00:57.190402 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5727 20:00:57.193709 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5728 20:00:57.197198 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5729 20:00:57.200547 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5730 20:00:57.203535 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5731 20:00:57.206427 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5732 20:00:57.213717 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5733 20:00:57.216595 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5734 20:00:57.220679 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5735 20:00:57.223308 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5736 20:00:57.227118 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5737 20:00:57.233106 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5738 20:00:57.236804 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5739 20:00:57.239813 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5740 20:00:57.240281 ==
5741 20:00:57.243075 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 20:00:57.246627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 20:00:57.247338 ==
5744 20:00:57.249498 DQS Delay:
5745 20:00:57.249955 DQS0 = 0, DQS1 = 0
5746 20:00:57.253169 DQM Delay:
5747 20:00:57.253731 DQM0 = 100, DQM1 = 90
5748 20:00:57.254104 DQ Delay:
5749 20:00:57.256330 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5750 20:00:57.259946 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =95
5751 20:00:57.262761 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5752 20:00:57.266015 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5753 20:00:57.269006
5754 20:00:57.269461
5755 20:00:57.269825 ==
5756 20:00:57.272354 Dram Type= 6, Freq= 0, CH_1, rank 0
5757 20:00:57.276054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 20:00:57.276629 ==
5759 20:00:57.277000
5760 20:00:57.277338
5761 20:00:57.279008 TX Vref Scan disable
5762 20:00:57.279472 == TX Byte 0 ==
5763 20:00:57.285893 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5764 20:00:57.289380 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5765 20:00:57.289946 == TX Byte 1 ==
5766 20:00:57.295993 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5767 20:00:57.299465 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5768 20:00:57.300089 ==
5769 20:00:57.302306 Dram Type= 6, Freq= 0, CH_1, rank 0
5770 20:00:57.305675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 20:00:57.306140 ==
5772 20:00:57.306568
5773 20:00:57.306925
5774 20:00:57.308894 TX Vref Scan disable
5775 20:00:57.312401 == TX Byte 0 ==
5776 20:00:57.315665 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5777 20:00:57.318868 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5778 20:00:57.322148 == TX Byte 1 ==
5779 20:00:57.325403 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5780 20:00:57.332534 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5781 20:00:57.333092
5782 20:00:57.333455 [DATLAT]
5783 20:00:57.333791 Freq=933, CH1 RK0
5784 20:00:57.334124
5785 20:00:57.335089 DATLAT Default: 0xd
5786 20:00:57.335545 0, 0xFFFF, sum = 0
5787 20:00:57.338315 1, 0xFFFF, sum = 0
5788 20:00:57.341588 2, 0xFFFF, sum = 0
5789 20:00:57.342053 3, 0xFFFF, sum = 0
5790 20:00:57.345031 4, 0xFFFF, sum = 0
5791 20:00:57.345602 5, 0xFFFF, sum = 0
5792 20:00:57.348229 6, 0xFFFF, sum = 0
5793 20:00:57.348793 7, 0xFFFF, sum = 0
5794 20:00:57.351783 8, 0xFFFF, sum = 0
5795 20:00:57.352353 9, 0xFFFF, sum = 0
5796 20:00:57.355107 10, 0x0, sum = 1
5797 20:00:57.355679 11, 0x0, sum = 2
5798 20:00:57.358139 12, 0x0, sum = 3
5799 20:00:57.358710 13, 0x0, sum = 4
5800 20:00:57.361681 best_step = 11
5801 20:00:57.362194
5802 20:00:57.362567 ==
5803 20:00:57.364617 Dram Type= 6, Freq= 0, CH_1, rank 0
5804 20:00:57.368141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 20:00:57.368714 ==
5806 20:00:57.369086 RX Vref Scan: 1
5807 20:00:57.369431
5808 20:00:57.371395 RX Vref 0 -> 0, step: 1
5809 20:00:57.372001
5810 20:00:57.374830 RX Delay -69 -> 252, step: 4
5811 20:00:57.375305
5812 20:00:57.378089 Set Vref, RX VrefLevel [Byte0]: 49
5813 20:00:57.380836 [Byte1]: 53
5814 20:00:57.384448
5815 20:00:57.384935 Final RX Vref Byte 0 = 49 to rank0
5816 20:00:57.387498 Final RX Vref Byte 1 = 53 to rank0
5817 20:00:57.391125 Final RX Vref Byte 0 = 49 to rank1
5818 20:00:57.394702 Final RX Vref Byte 1 = 53 to rank1==
5819 20:00:57.397696 Dram Type= 6, Freq= 0, CH_1, rank 0
5820 20:00:57.404201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 20:00:57.404753 ==
5822 20:00:57.405125 DQS Delay:
5823 20:00:57.407695 DQS0 = 0, DQS1 = 0
5824 20:00:57.408188 DQM Delay:
5825 20:00:57.408556 DQM0 = 101, DQM1 = 93
5826 20:00:57.410953 DQ Delay:
5827 20:00:57.414318 DQ0 =106, DQ1 =94, DQ2 =94, DQ3 =98
5828 20:00:57.417699 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5829 20:00:57.421116 DQ8 =80, DQ9 =84, DQ10 =96, DQ11 =84
5830 20:00:57.424367 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5831 20:00:57.424924
5832 20:00:57.425297
5833 20:00:57.430789 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5834 20:00:57.434315 CH1 RK0: MR19=505, MR18=1E0E
5835 20:00:57.440886 CH1_RK0: MR19=0x505, MR18=0x1E0E, DQSOSC=412, MR23=63, INC=63, DEC=42
5836 20:00:57.441446
5837 20:00:57.444170 ----->DramcWriteLeveling(PI) begin...
5838 20:00:57.444733 ==
5839 20:00:57.447369 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 20:00:57.450825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 20:00:57.451301 ==
5842 20:00:57.454189 Write leveling (Byte 0): 27 => 27
5843 20:00:57.457815 Write leveling (Byte 1): 28 => 28
5844 20:00:57.460507 DramcWriteLeveling(PI) end<-----
5845 20:00:57.461059
5846 20:00:57.461426 ==
5847 20:00:57.463636 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 20:00:57.470165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 20:00:57.470749 ==
5850 20:00:57.473340 [Gating] SW mode calibration
5851 20:00:57.480173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5852 20:00:57.483875 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5853 20:00:57.489711 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 20:00:57.493675 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 20:00:57.496340 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 20:00:57.503335 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5857 20:00:57.506413 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5858 20:00:57.510594 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5859 20:00:57.516420 0 14 24 | B1->B0 | 3030 3333 | 0 0 | (0 1) (0 1)
5860 20:00:57.520365 0 14 28 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
5861 20:00:57.523497 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 20:00:57.529701 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 20:00:57.532865 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 20:00:57.536486 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5865 20:00:57.543045 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5866 20:00:57.546534 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5867 20:00:57.549060 0 15 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5868 20:00:57.555666 0 15 28 | B1->B0 | 3b3b 3333 | 0 0 | (1 1) (1 1)
5869 20:00:57.559215 1 0 0 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5870 20:00:57.562288 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 20:00:57.568904 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 20:00:57.571933 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 20:00:57.575818 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 20:00:57.581897 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5875 20:00:57.585338 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5876 20:00:57.588585 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 20:00:57.595221 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 20:00:57.598798 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 20:00:57.602055 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 20:00:57.608350 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 20:00:57.611522 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 20:00:57.614899 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 20:00:57.621997 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 20:00:57.624853 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 20:00:57.628398 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 20:00:57.634868 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 20:00:57.638347 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 20:00:57.641886 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 20:00:57.648121 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 20:00:57.651374 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 20:00:57.654918 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5892 20:00:57.660865 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5893 20:00:57.664108 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5894 20:00:57.667774 Total UI for P1: 0, mck2ui 16
5895 20:00:57.670964 best dqsien dly found for B0: ( 1, 2, 30)
5896 20:00:57.674628 Total UI for P1: 0, mck2ui 16
5897 20:00:57.677328 best dqsien dly found for B1: ( 1, 2, 26)
5898 20:00:57.680721 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5899 20:00:57.683985 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5900 20:00:57.684453
5901 20:00:57.687486 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5902 20:00:57.690307 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5903 20:00:57.693952 [Gating] SW calibration Done
5904 20:00:57.694393 ==
5905 20:00:57.697260 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 20:00:57.701314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 20:00:57.704284 ==
5908 20:00:57.704727 RX Vref Scan: 0
5909 20:00:57.705065
5910 20:00:57.707491 RX Vref 0 -> 0, step: 1
5911 20:00:57.707960
5912 20:00:57.710864 RX Delay -80 -> 252, step: 8
5913 20:00:57.713653 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5914 20:00:57.717406 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5915 20:00:57.720691 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5916 20:00:57.724163 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5917 20:00:57.727369 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5918 20:00:57.733978 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5919 20:00:57.736893 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5920 20:00:57.740272 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5921 20:00:57.744013 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5922 20:00:57.747248 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5923 20:00:57.753773 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5924 20:00:57.756994 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5925 20:00:57.760268 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5926 20:00:57.763442 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5927 20:00:57.766865 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5928 20:00:57.773813 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5929 20:00:57.774397 ==
5930 20:00:57.776661 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 20:00:57.780171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 20:00:57.780762 ==
5933 20:00:57.781138 DQS Delay:
5934 20:00:57.783192 DQS0 = 0, DQS1 = 0
5935 20:00:57.783654 DQM Delay:
5936 20:00:57.786477 DQM0 = 100, DQM1 = 90
5937 20:00:57.787032 DQ Delay:
5938 20:00:57.789622 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5939 20:00:57.792780 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5940 20:00:57.796129 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5941 20:00:57.799576 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5942 20:00:57.800196
5943 20:00:57.800572
5944 20:00:57.800916 ==
5945 20:00:57.802817 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 20:00:57.806312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 20:00:57.809523 ==
5948 20:00:57.810114
5949 20:00:57.810519
5950 20:00:57.810878 TX Vref Scan disable
5951 20:00:57.812398 == TX Byte 0 ==
5952 20:00:57.815981 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5953 20:00:57.819503 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5954 20:00:57.823303 == TX Byte 1 ==
5955 20:00:57.826032 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5956 20:00:57.829409 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5957 20:00:57.832633 ==
5958 20:00:57.835838 Dram Type= 6, Freq= 0, CH_1, rank 1
5959 20:00:57.839662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5960 20:00:57.840266 ==
5961 20:00:57.840644
5962 20:00:57.840986
5963 20:00:57.842169 TX Vref Scan disable
5964 20:00:57.842632 == TX Byte 0 ==
5965 20:00:57.848997 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5966 20:00:57.852559 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5967 20:00:57.853111 == TX Byte 1 ==
5968 20:00:57.858676 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5969 20:00:57.862218 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5970 20:00:57.862686
5971 20:00:57.863058 [DATLAT]
5972 20:00:57.865100 Freq=933, CH1 RK1
5973 20:00:57.865569
5974 20:00:57.865941 DATLAT Default: 0xb
5975 20:00:57.868508 0, 0xFFFF, sum = 0
5976 20:00:57.873116 1, 0xFFFF, sum = 0
5977 20:00:57.873633 2, 0xFFFF, sum = 0
5978 20:00:57.875541 3, 0xFFFF, sum = 0
5979 20:00:57.876020 4, 0xFFFF, sum = 0
5980 20:00:57.878757 5, 0xFFFF, sum = 0
5981 20:00:57.879284 6, 0xFFFF, sum = 0
5982 20:00:57.881656 7, 0xFFFF, sum = 0
5983 20:00:57.882084 8, 0xFFFF, sum = 0
5984 20:00:57.884986 9, 0xFFFF, sum = 0
5985 20:00:57.885413 10, 0x0, sum = 1
5986 20:00:57.888155 11, 0x0, sum = 2
5987 20:00:57.888580 12, 0x0, sum = 3
5988 20:00:57.891475 13, 0x0, sum = 4
5989 20:00:57.891935 best_step = 11
5990 20:00:57.892279
5991 20:00:57.892597 ==
5992 20:00:57.894829 Dram Type= 6, Freq= 0, CH_1, rank 1
5993 20:00:57.898390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5994 20:00:57.898923 ==
5995 20:00:57.901626 RX Vref Scan: 0
5996 20:00:57.902072
5997 20:00:57.904984 RX Vref 0 -> 0, step: 1
5998 20:00:57.905626
5999 20:00:57.905967 RX Delay -61 -> 252, step: 4
6000 20:00:57.913224 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6001 20:00:57.916180 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6002 20:00:57.919091 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6003 20:00:57.922730 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6004 20:00:57.925711 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6005 20:00:57.932508 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6006 20:00:57.935953 iDelay=207, Bit 6, Center 118 (31 ~ 206) 176
6007 20:00:57.938911 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6008 20:00:57.942416 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
6009 20:00:57.945581 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6010 20:00:57.952047 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
6011 20:00:57.955546 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6012 20:00:57.958653 iDelay=207, Bit 12, Center 100 (7 ~ 194) 188
6013 20:00:57.962855 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
6014 20:00:57.965899 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6015 20:00:57.968949 iDelay=207, Bit 15, Center 100 (7 ~ 194) 188
6016 20:00:57.972234 ==
6017 20:00:57.975240 Dram Type= 6, Freq= 0, CH_1, rank 1
6018 20:00:57.978915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6019 20:00:57.979437 ==
6020 20:00:57.979830 DQS Delay:
6021 20:00:57.982780 DQS0 = 0, DQS1 = 0
6022 20:00:57.983406 DQM Delay:
6023 20:00:57.985402 DQM0 = 101, DQM1 = 92
6024 20:00:57.985821 DQ Delay:
6025 20:00:57.988314 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
6026 20:00:57.991935 DQ4 =98, DQ5 =110, DQ6 =118, DQ7 =98
6027 20:00:57.995058 DQ8 =84, DQ9 =84, DQ10 =92, DQ11 =84
6028 20:00:57.998568 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =100
6029 20:00:57.999078
6030 20:00:57.999419
6031 20:00:58.008436 [DQSOSCAuto] RK1, (LSB)MR18= 0x700, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 419 ps
6032 20:00:58.009020 CH1 RK1: MR19=505, MR18=700
6033 20:00:58.015146 CH1_RK1: MR19=0x505, MR18=0x700, DQSOSC=419, MR23=63, INC=61, DEC=41
6034 20:00:58.018382 [RxdqsGatingPostProcess] freq 933
6035 20:00:58.025108 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6036 20:00:58.028125 best DQS0 dly(2T, 0.5T) = (0, 10)
6037 20:00:58.031444 best DQS1 dly(2T, 0.5T) = (0, 10)
6038 20:00:58.034693 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6039 20:00:58.038297 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6040 20:00:58.041727 best DQS0 dly(2T, 0.5T) = (0, 10)
6041 20:00:58.042295 best DQS1 dly(2T, 0.5T) = (0, 10)
6042 20:00:58.044361 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6043 20:00:58.047866 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6044 20:00:58.050879 Pre-setting of DQS Precalculation
6045 20:00:58.057781 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6046 20:00:58.064176 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6047 20:00:58.070897 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6048 20:00:58.071454
6049 20:00:58.071878
6050 20:00:58.074625 [Calibration Summary] 1866 Mbps
6051 20:00:58.077538 CH 0, Rank 0
6052 20:00:58.078267 SW Impedance : PASS
6053 20:00:58.080423 DUTY Scan : NO K
6054 20:00:58.083873 ZQ Calibration : PASS
6055 20:00:58.084471 Jitter Meter : NO K
6056 20:00:58.087578 CBT Training : PASS
6057 20:00:58.088178 Write leveling : PASS
6058 20:00:58.090766 RX DQS gating : PASS
6059 20:00:58.094396 RX DQ/DQS(RDDQC) : PASS
6060 20:00:58.094952 TX DQ/DQS : PASS
6061 20:00:58.097627 RX DATLAT : PASS
6062 20:00:58.100560 RX DQ/DQS(Engine): PASS
6063 20:00:58.101113 TX OE : NO K
6064 20:00:58.104750 All Pass.
6065 20:00:58.105300
6066 20:00:58.105690 CH 0, Rank 1
6067 20:00:58.106809 SW Impedance : PASS
6068 20:00:58.107269 DUTY Scan : NO K
6069 20:00:58.110408 ZQ Calibration : PASS
6070 20:00:58.113715 Jitter Meter : NO K
6071 20:00:58.114179 CBT Training : PASS
6072 20:00:58.117241 Write leveling : PASS
6073 20:00:58.120276 RX DQS gating : PASS
6074 20:00:58.120736 RX DQ/DQS(RDDQC) : PASS
6075 20:00:58.123389 TX DQ/DQS : PASS
6076 20:00:58.126900 RX DATLAT : PASS
6077 20:00:58.127453 RX DQ/DQS(Engine): PASS
6078 20:00:58.129970 TX OE : NO K
6079 20:00:58.130428 All Pass.
6080 20:00:58.130797
6081 20:00:58.133262 CH 1, Rank 0
6082 20:00:58.133735 SW Impedance : PASS
6083 20:00:58.136824 DUTY Scan : NO K
6084 20:00:58.140257 ZQ Calibration : PASS
6085 20:00:58.140807 Jitter Meter : NO K
6086 20:00:58.142902 CBT Training : PASS
6087 20:00:58.146190 Write leveling : PASS
6088 20:00:58.146748 RX DQS gating : PASS
6089 20:00:58.150118 RX DQ/DQS(RDDQC) : PASS
6090 20:00:58.153397 TX DQ/DQS : PASS
6091 20:00:58.153956 RX DATLAT : PASS
6092 20:00:58.156197 RX DQ/DQS(Engine): PASS
6093 20:00:58.159896 TX OE : NO K
6094 20:00:58.160517 All Pass.
6095 20:00:58.161000
6096 20:00:58.161323 CH 1, Rank 1
6097 20:00:58.162910 SW Impedance : PASS
6098 20:00:58.166867 DUTY Scan : NO K
6099 20:00:58.167376 ZQ Calibration : PASS
6100 20:00:58.170628 Jitter Meter : NO K
6101 20:00:58.171044 CBT Training : PASS
6102 20:00:58.173080 Write leveling : PASS
6103 20:00:58.176342 RX DQS gating : PASS
6104 20:00:58.176761 RX DQ/DQS(RDDQC) : PASS
6105 20:00:58.179619 TX DQ/DQS : PASS
6106 20:00:58.183037 RX DATLAT : PASS
6107 20:00:58.183544 RX DQ/DQS(Engine): PASS
6108 20:00:58.185907 TX OE : NO K
6109 20:00:58.186464 All Pass.
6110 20:00:58.186813
6111 20:00:58.189942 DramC Write-DBI off
6112 20:00:58.192525 PER_BANK_REFRESH: Hybrid Mode
6113 20:00:58.192946 TX_TRACKING: ON
6114 20:00:58.202642 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6115 20:00:58.205979 [FAST_K] Save calibration result to emmc
6116 20:00:58.208926 dramc_set_vcore_voltage set vcore to 650000
6117 20:00:58.212882 Read voltage for 400, 6
6118 20:00:58.213389 Vio18 = 0
6119 20:00:58.216885 Vcore = 650000
6120 20:00:58.217391 Vdram = 0
6121 20:00:58.217727 Vddq = 0
6122 20:00:58.218033 Vmddr = 0
6123 20:00:58.222555 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6124 20:00:58.228972 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6125 20:00:58.229546 MEM_TYPE=3, freq_sel=20
6126 20:00:58.232399 sv_algorithm_assistance_LP4_800
6127 20:00:58.235866 ============ PULL DRAM RESETB DOWN ============
6128 20:00:58.241897 ========== PULL DRAM RESETB DOWN end =========
6129 20:00:58.245480 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6130 20:00:58.249367 ===================================
6131 20:00:58.252070 LPDDR4 DRAM CONFIGURATION
6132 20:00:58.255967 ===================================
6133 20:00:58.256513 EX_ROW_EN[0] = 0x0
6134 20:00:58.258894 EX_ROW_EN[1] = 0x0
6135 20:00:58.259446 LP4Y_EN = 0x0
6136 20:00:58.261957 WORK_FSP = 0x0
6137 20:00:58.262509 WL = 0x2
6138 20:00:58.265174 RL = 0x2
6139 20:00:58.268985 BL = 0x2
6140 20:00:58.269545 RPST = 0x0
6141 20:00:58.271432 RD_PRE = 0x0
6142 20:00:58.271924 WR_PRE = 0x1
6143 20:00:58.274930 WR_PST = 0x0
6144 20:00:58.275500 DBI_WR = 0x0
6145 20:00:58.278813 DBI_RD = 0x0
6146 20:00:58.279365 OTF = 0x1
6147 20:00:58.282461 ===================================
6148 20:00:58.285233 ===================================
6149 20:00:58.288618 ANA top config
6150 20:00:58.291870 ===================================
6151 20:00:58.292336 DLL_ASYNC_EN = 0
6152 20:00:58.295195 ALL_SLAVE_EN = 1
6153 20:00:58.298576 NEW_RANK_MODE = 1
6154 20:00:58.302180 DLL_IDLE_MODE = 1
6155 20:00:58.302733 LP45_APHY_COMB_EN = 1
6156 20:00:58.305536 TX_ODT_DIS = 1
6157 20:00:58.308074 NEW_8X_MODE = 1
6158 20:00:58.311661 ===================================
6159 20:00:58.315124 ===================================
6160 20:00:58.318254 data_rate = 800
6161 20:00:58.321741 CKR = 1
6162 20:00:58.324473 DQ_P2S_RATIO = 4
6163 20:00:58.328109 ===================================
6164 20:00:58.328666 CA_P2S_RATIO = 4
6165 20:00:58.331257 DQ_CA_OPEN = 0
6166 20:00:58.334299 DQ_SEMI_OPEN = 1
6167 20:00:58.337958 CA_SEMI_OPEN = 1
6168 20:00:58.340964 CA_FULL_RATE = 0
6169 20:00:58.344386 DQ_CKDIV4_EN = 0
6170 20:00:58.347872 CA_CKDIV4_EN = 1
6171 20:00:58.348431 CA_PREDIV_EN = 0
6172 20:00:58.351539 PH8_DLY = 0
6173 20:00:58.354613 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6174 20:00:58.357507 DQ_AAMCK_DIV = 0
6175 20:00:58.360569 CA_AAMCK_DIV = 0
6176 20:00:58.364555 CA_ADMCK_DIV = 4
6177 20:00:58.365168 DQ_TRACK_CA_EN = 0
6178 20:00:58.367460 CA_PICK = 800
6179 20:00:58.371176 CA_MCKIO = 400
6180 20:00:58.374030 MCKIO_SEMI = 400
6181 20:00:58.377424 PLL_FREQ = 3016
6182 20:00:58.380422 DQ_UI_PI_RATIO = 32
6183 20:00:58.384074 CA_UI_PI_RATIO = 32
6184 20:00:58.387106 ===================================
6185 20:00:58.390642 ===================================
6186 20:00:58.391107 memory_type:LPDDR4
6187 20:00:58.393517 GP_NUM : 10
6188 20:00:58.397053 SRAM_EN : 1
6189 20:00:58.397550 MD32_EN : 0
6190 20:00:58.400434 ===================================
6191 20:00:58.403959 [ANA_INIT] >>>>>>>>>>>>>>
6192 20:00:58.407249 <<<<<< [CONFIGURE PHASE]: ANA_TX
6193 20:00:58.410010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6194 20:00:58.413794 ===================================
6195 20:00:58.416791 data_rate = 800,PCW = 0X7400
6196 20:00:58.420804 ===================================
6197 20:00:58.423856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6198 20:00:58.427577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6199 20:00:58.440544 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6200 20:00:58.443387 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6201 20:00:58.447086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6202 20:00:58.450703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6203 20:00:58.452921 [ANA_INIT] flow start
6204 20:00:58.457177 [ANA_INIT] PLL >>>>>>>>
6205 20:00:58.457654 [ANA_INIT] PLL <<<<<<<<
6206 20:00:58.459654 [ANA_INIT] MIDPI >>>>>>>>
6207 20:00:58.463164 [ANA_INIT] MIDPI <<<<<<<<
6208 20:00:58.463805 [ANA_INIT] DLL >>>>>>>>
6209 20:00:58.466887 [ANA_INIT] flow end
6210 20:00:58.470046 ============ LP4 DIFF to SE enter ============
6211 20:00:58.477145 ============ LP4 DIFF to SE exit ============
6212 20:00:58.477704 [ANA_INIT] <<<<<<<<<<<<<
6213 20:00:58.479933 [Flow] Enable top DCM control >>>>>
6214 20:00:58.483106 [Flow] Enable top DCM control <<<<<
6215 20:00:58.486089 Enable DLL master slave shuffle
6216 20:00:58.493105 ==============================================================
6217 20:00:58.493570 Gating Mode config
6218 20:00:58.499916 ==============================================================
6219 20:00:58.502567 Config description:
6220 20:00:58.512883 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6221 20:00:58.519152 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6222 20:00:58.522551 SELPH_MODE 0: By rank 1: By Phase
6223 20:00:58.529274 ==============================================================
6224 20:00:58.532579 GAT_TRACK_EN = 0
6225 20:00:58.536356 RX_GATING_MODE = 2
6226 20:00:58.536914 RX_GATING_TRACK_MODE = 2
6227 20:00:58.538880 SELPH_MODE = 1
6228 20:00:58.542090 PICG_EARLY_EN = 1
6229 20:00:58.545752 VALID_LAT_VALUE = 1
6230 20:00:58.551980 ==============================================================
6231 20:00:58.555457 Enter into Gating configuration >>>>
6232 20:00:58.558245 Exit from Gating configuration <<<<
6233 20:00:58.561654 Enter into DVFS_PRE_config >>>>>
6234 20:00:58.571456 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6235 20:00:58.575263 Exit from DVFS_PRE_config <<<<<
6236 20:00:58.578108 Enter into PICG configuration >>>>
6237 20:00:58.581839 Exit from PICG configuration <<<<
6238 20:00:58.584971 [RX_INPUT] configuration >>>>>
6239 20:00:58.587859 [RX_INPUT] configuration <<<<<
6240 20:00:58.591598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6241 20:00:58.598105 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6242 20:00:58.605271 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6243 20:00:58.611164 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6244 20:00:58.617707 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6245 20:00:58.621162 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6246 20:00:58.628404 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6247 20:00:58.631153 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6248 20:00:58.634871 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6249 20:00:58.641444 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6250 20:00:58.644543 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6251 20:00:58.647567 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6252 20:00:58.650862 ===================================
6253 20:00:58.654426 LPDDR4 DRAM CONFIGURATION
6254 20:00:58.657162 ===================================
6255 20:00:58.657616 EX_ROW_EN[0] = 0x0
6256 20:00:58.660519 EX_ROW_EN[1] = 0x0
6257 20:00:58.661074 LP4Y_EN = 0x0
6258 20:00:58.664312 WORK_FSP = 0x0
6259 20:00:58.667159 WL = 0x2
6260 20:00:58.667720 RL = 0x2
6261 20:00:58.670581 BL = 0x2
6262 20:00:58.671187 RPST = 0x0
6263 20:00:58.674533 RD_PRE = 0x0
6264 20:00:58.675092 WR_PRE = 0x1
6265 20:00:58.677438 WR_PST = 0x0
6266 20:00:58.677993 DBI_WR = 0x0
6267 20:00:58.680393 DBI_RD = 0x0
6268 20:00:58.680947 OTF = 0x1
6269 20:00:58.683906 ===================================
6270 20:00:58.686953 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6271 20:00:58.693859 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6272 20:00:58.697131 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6273 20:00:58.700019 ===================================
6274 20:00:58.703353 LPDDR4 DRAM CONFIGURATION
6275 20:00:58.706984 ===================================
6276 20:00:58.707544 EX_ROW_EN[0] = 0x10
6277 20:00:58.709963 EX_ROW_EN[1] = 0x0
6278 20:00:58.710421 LP4Y_EN = 0x0
6279 20:00:58.713360 WORK_FSP = 0x0
6280 20:00:58.716441 WL = 0x2
6281 20:00:58.716977 RL = 0x2
6282 20:00:58.719664 BL = 0x2
6283 20:00:58.720165 RPST = 0x0
6284 20:00:58.724117 RD_PRE = 0x0
6285 20:00:58.724669 WR_PRE = 0x1
6286 20:00:58.726500 WR_PST = 0x0
6287 20:00:58.727051 DBI_WR = 0x0
6288 20:00:58.729893 DBI_RD = 0x0
6289 20:00:58.730443 OTF = 0x1
6290 20:00:58.732879 ===================================
6291 20:00:58.739649 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6292 20:00:58.744069 nWR fixed to 30
6293 20:00:58.747459 [ModeRegInit_LP4] CH0 RK0
6294 20:00:58.748065 [ModeRegInit_LP4] CH0 RK1
6295 20:00:58.750688 [ModeRegInit_LP4] CH1 RK0
6296 20:00:58.754356 [ModeRegInit_LP4] CH1 RK1
6297 20:00:58.754908 match AC timing 19
6298 20:00:58.760380 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6299 20:00:58.763671 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6300 20:00:58.766714 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6301 20:00:58.773858 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6302 20:00:58.776736 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6303 20:00:58.777196 ==
6304 20:00:58.780012 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 20:00:58.783334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 20:00:58.783922 ==
6307 20:00:58.789738 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6308 20:00:58.796409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6309 20:00:58.800475 [CA 0] Center 36 (8~64) winsize 57
6310 20:00:58.803806 [CA 1] Center 36 (8~64) winsize 57
6311 20:00:58.806795 [CA 2] Center 36 (8~64) winsize 57
6312 20:00:58.809334 [CA 3] Center 36 (8~64) winsize 57
6313 20:00:58.812770 [CA 4] Center 36 (8~64) winsize 57
6314 20:00:58.817021 [CA 5] Center 36 (8~64) winsize 57
6315 20:00:58.817562
6316 20:00:58.819378 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6317 20:00:58.819877
6318 20:00:58.822609 [CATrainingPosCal] consider 1 rank data
6319 20:00:58.826114 u2DelayCellTimex100 = 270/100 ps
6320 20:00:58.829313 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 20:00:58.832609 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 20:00:58.835989 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 20:00:58.839716 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 20:00:58.843085 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 20:00:58.845964 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 20:00:58.846518
6327 20:00:58.853001 CA PerBit enable=1, Macro0, CA PI delay=36
6328 20:00:58.853560
6329 20:00:58.853927 [CBTSetCACLKResult] CA Dly = 36
6330 20:00:58.855896 CS Dly: 1 (0~32)
6331 20:00:58.856455 ==
6332 20:00:58.859054 Dram Type= 6, Freq= 0, CH_0, rank 1
6333 20:00:58.862526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 20:00:58.863082 ==
6335 20:00:58.869021 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6336 20:00:58.876061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6337 20:00:58.878816 [CA 0] Center 36 (8~64) winsize 57
6338 20:00:58.882472 [CA 1] Center 36 (8~64) winsize 57
6339 20:00:58.885903 [CA 2] Center 36 (8~64) winsize 57
6340 20:00:58.888387 [CA 3] Center 36 (8~64) winsize 57
6341 20:00:58.891684 [CA 4] Center 36 (8~64) winsize 57
6342 20:00:58.892198 [CA 5] Center 36 (8~64) winsize 57
6343 20:00:58.896388
6344 20:00:58.898262 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6345 20:00:58.898718
6346 20:00:58.901803 [CATrainingPosCal] consider 2 rank data
6347 20:00:58.904928 u2DelayCellTimex100 = 270/100 ps
6348 20:00:58.908509 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 20:00:58.911571 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 20:00:58.915129 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 20:00:58.918172 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6352 20:00:58.921315 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6353 20:00:58.925098 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6354 20:00:58.925694
6355 20:00:58.928038 CA PerBit enable=1, Macro0, CA PI delay=36
6356 20:00:58.931140
6357 20:00:58.931756 [CBTSetCACLKResult] CA Dly = 36
6358 20:00:58.934817 CS Dly: 1 (0~32)
6359 20:00:58.935366
6360 20:00:58.937871 ----->DramcWriteLeveling(PI) begin...
6361 20:00:58.938331 ==
6362 20:00:58.941113 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 20:00:58.944274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 20:00:58.944690 ==
6365 20:00:58.947798 Write leveling (Byte 0): 40 => 8
6366 20:00:58.951057 Write leveling (Byte 1): 32 => 0
6367 20:00:58.954401 DramcWriteLeveling(PI) end<-----
6368 20:00:58.954811
6369 20:00:58.955138 ==
6370 20:00:58.957435 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 20:00:58.961736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 20:00:58.964742 ==
6373 20:00:58.965254 [Gating] SW mode calibration
6374 20:00:58.973947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6375 20:00:58.977251 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6376 20:00:58.980671 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6377 20:00:58.987396 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6378 20:00:58.990402 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6379 20:00:58.993893 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6380 20:00:59.000080 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 20:00:59.003827 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6382 20:00:59.006647 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6383 20:00:59.013685 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6384 20:00:59.016551 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6385 20:00:59.020342 Total UI for P1: 0, mck2ui 16
6386 20:00:59.023493 best dqsien dly found for B0: ( 0, 14, 24)
6387 20:00:59.026688 Total UI for P1: 0, mck2ui 16
6388 20:00:59.030059 best dqsien dly found for B1: ( 0, 14, 24)
6389 20:00:59.033628 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6390 20:00:59.036972 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6391 20:00:59.037485
6392 20:00:59.039821 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6393 20:00:59.046589 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6394 20:00:59.047150 [Gating] SW calibration Done
6395 20:00:59.047620 ==
6396 20:00:59.050089 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 20:00:59.056478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 20:00:59.057003 ==
6399 20:00:59.057339 RX Vref Scan: 0
6400 20:00:59.057648
6401 20:00:59.059530 RX Vref 0 -> 0, step: 1
6402 20:00:59.059974
6403 20:00:59.063035 RX Delay -410 -> 252, step: 16
6404 20:00:59.066487 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6405 20:00:59.069597 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6406 20:00:59.076293 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6407 20:00:59.079235 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6408 20:00:59.082696 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6409 20:00:59.086381 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6410 20:00:59.092470 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6411 20:00:59.096319 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6412 20:00:59.099228 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6413 20:00:59.102720 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6414 20:00:59.109257 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6415 20:00:59.112629 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6416 20:00:59.116125 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6417 20:00:59.122213 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6418 20:00:59.125710 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6419 20:00:59.129192 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6420 20:00:59.129739 ==
6421 20:00:59.132406 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 20:00:59.136616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 20:00:59.139026 ==
6424 20:00:59.139435 DQS Delay:
6425 20:00:59.139791 DQS0 = 43, DQS1 = 59
6426 20:00:59.141992 DQM Delay:
6427 20:00:59.142400 DQM0 = 10, DQM1 = 13
6428 20:00:59.145476 DQ Delay:
6429 20:00:59.146265 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6430 20:00:59.149184 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6431 20:00:59.151784 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6432 20:00:59.155053 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6433 20:00:59.155605
6434 20:00:59.156025
6435 20:00:59.158616 ==
6436 20:00:59.162153 Dram Type= 6, Freq= 0, CH_0, rank 0
6437 20:00:59.165221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 20:00:59.165767 ==
6439 20:00:59.166239
6440 20:00:59.166689
6441 20:00:59.168288 TX Vref Scan disable
6442 20:00:59.168769 == TX Byte 0 ==
6443 20:00:59.171720 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6444 20:00:59.178412 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6445 20:00:59.178927 == TX Byte 1 ==
6446 20:00:59.182445 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6447 20:00:59.188664 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6448 20:00:59.189327 ==
6449 20:00:59.191597 Dram Type= 6, Freq= 0, CH_0, rank 0
6450 20:00:59.195085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 20:00:59.195607 ==
6452 20:00:59.196014
6453 20:00:59.196329
6454 20:00:59.198348 TX Vref Scan disable
6455 20:00:59.198857 == TX Byte 0 ==
6456 20:00:59.205655 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6457 20:00:59.208651 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6458 20:00:59.209072 == TX Byte 1 ==
6459 20:00:59.214908 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6460 20:00:59.217827 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6461 20:00:59.218317
6462 20:00:59.218665 [DATLAT]
6463 20:00:59.221400 Freq=400, CH0 RK0
6464 20:00:59.221813
6465 20:00:59.222140 DATLAT Default: 0xf
6466 20:00:59.224964 0, 0xFFFF, sum = 0
6467 20:00:59.225480 1, 0xFFFF, sum = 0
6468 20:00:59.228176 2, 0xFFFF, sum = 0
6469 20:00:59.228693 3, 0xFFFF, sum = 0
6470 20:00:59.231244 4, 0xFFFF, sum = 0
6471 20:00:59.231789 5, 0xFFFF, sum = 0
6472 20:00:59.235121 6, 0xFFFF, sum = 0
6473 20:00:59.235635 7, 0xFFFF, sum = 0
6474 20:00:59.238603 8, 0xFFFF, sum = 0
6475 20:00:59.239119 9, 0xFFFF, sum = 0
6476 20:00:59.241121 10, 0xFFFF, sum = 0
6477 20:00:59.244705 11, 0xFFFF, sum = 0
6478 20:00:59.245223 12, 0xFFFF, sum = 0
6479 20:00:59.247882 13, 0x0, sum = 1
6480 20:00:59.248401 14, 0x0, sum = 2
6481 20:00:59.251267 15, 0x0, sum = 3
6482 20:00:59.251856 16, 0x0, sum = 4
6483 20:00:59.252203 best_step = 14
6484 20:00:59.252511
6485 20:00:59.254257 ==
6486 20:00:59.257618 Dram Type= 6, Freq= 0, CH_0, rank 0
6487 20:00:59.260579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 20:00:59.261094 ==
6489 20:00:59.261429 RX Vref Scan: 1
6490 20:00:59.261744
6491 20:00:59.264380 RX Vref 0 -> 0, step: 1
6492 20:00:59.264893
6493 20:00:59.267555 RX Delay -359 -> 252, step: 8
6494 20:00:59.268143
6495 20:00:59.271054 Set Vref, RX VrefLevel [Byte0]: 63
6496 20:00:59.273957 [Byte1]: 49
6497 20:00:59.278634
6498 20:00:59.279145 Final RX Vref Byte 0 = 63 to rank0
6499 20:00:59.281199 Final RX Vref Byte 1 = 49 to rank0
6500 20:00:59.284554 Final RX Vref Byte 0 = 63 to rank1
6501 20:00:59.287835 Final RX Vref Byte 1 = 49 to rank1==
6502 20:00:59.291154 Dram Type= 6, Freq= 0, CH_0, rank 0
6503 20:00:59.297714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 20:00:59.298247 ==
6505 20:00:59.298585 DQS Delay:
6506 20:00:59.301373 DQS0 = 44, DQS1 = 60
6507 20:00:59.301888 DQM Delay:
6508 20:00:59.302222 DQM0 = 8, DQM1 = 12
6509 20:00:59.303960 DQ Delay:
6510 20:00:59.307717 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6511 20:00:59.310515 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =20
6512 20:00:59.310926 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6513 20:00:59.314213 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6514 20:00:59.317780
6515 20:00:59.318192
6516 20:00:59.324218 [DQSOSCAuto] RK0, (LSB)MR18= 0xbc80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6517 20:00:59.327890 CH0 RK0: MR19=C0C, MR18=BC80
6518 20:00:59.333948 CH0_RK0: MR19=0xC0C, MR18=0xBC80, DQSOSC=386, MR23=63, INC=396, DEC=264
6519 20:00:59.334538 ==
6520 20:00:59.337723 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 20:00:59.341134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 20:00:59.341698 ==
6523 20:00:59.343841 [Gating] SW mode calibration
6524 20:00:59.350923 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6525 20:00:59.357335 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6526 20:00:59.360594 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6527 20:00:59.363624 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6528 20:00:59.370510 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6529 20:00:59.373476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6530 20:00:59.376901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 20:00:59.383412 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6532 20:00:59.386602 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6533 20:00:59.389820 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6534 20:00:59.397078 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6535 20:00:59.397636 Total UI for P1: 0, mck2ui 16
6536 20:00:59.403321 best dqsien dly found for B0: ( 0, 14, 24)
6537 20:00:59.403925 Total UI for P1: 0, mck2ui 16
6538 20:00:59.409736 best dqsien dly found for B1: ( 0, 14, 24)
6539 20:00:59.412840 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6540 20:00:59.416276 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6541 20:00:59.416829
6542 20:00:59.420188 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6543 20:00:59.422964 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6544 20:00:59.426322 [Gating] SW calibration Done
6545 20:00:59.426873 ==
6546 20:00:59.429672 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 20:00:59.432517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 20:00:59.433002 ==
6549 20:00:59.436289 RX Vref Scan: 0
6550 20:00:59.436841
6551 20:00:59.437210 RX Vref 0 -> 0, step: 1
6552 20:00:59.439184
6553 20:00:59.439633 RX Delay -410 -> 252, step: 16
6554 20:00:59.446162 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6555 20:00:59.449206 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6556 20:00:59.452788 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6557 20:00:59.456108 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6558 20:00:59.462808 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6559 20:00:59.466269 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6560 20:00:59.468759 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6561 20:00:59.475549 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6562 20:00:59.479330 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6563 20:00:59.482221 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6564 20:00:59.485656 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6565 20:00:59.492008 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6566 20:00:59.495081 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6567 20:00:59.498569 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6568 20:00:59.502182 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6569 20:00:59.509297 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6570 20:00:59.509846 ==
6571 20:00:59.511670 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 20:00:59.515166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 20:00:59.515792 ==
6574 20:00:59.516181 DQS Delay:
6575 20:00:59.518195 DQS0 = 43, DQS1 = 59
6576 20:00:59.518650 DQM Delay:
6577 20:00:59.521976 DQM0 = 10, DQM1 = 16
6578 20:00:59.522530 DQ Delay:
6579 20:00:59.525236 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6580 20:00:59.528632 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6581 20:00:59.531887 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6582 20:00:59.535172 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6583 20:00:59.535754
6584 20:00:59.536127
6585 20:00:59.536459 ==
6586 20:00:59.538679 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 20:00:59.541822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 20:00:59.542379 ==
6589 20:00:59.542744
6590 20:00:59.544581
6591 20:00:59.545034 TX Vref Scan disable
6592 20:00:59.548320 == TX Byte 0 ==
6593 20:00:59.551857 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6594 20:00:59.554941 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6595 20:00:59.558200 == TX Byte 1 ==
6596 20:00:59.562155 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6597 20:00:59.565234 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6598 20:00:59.565786 ==
6599 20:00:59.567950 Dram Type= 6, Freq= 0, CH_0, rank 1
6600 20:00:59.571475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 20:00:59.574276 ==
6602 20:00:59.574733
6603 20:00:59.575098
6604 20:00:59.575435 TX Vref Scan disable
6605 20:00:59.578033 == TX Byte 0 ==
6606 20:00:59.581410 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6607 20:00:59.584623 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6608 20:00:59.588246 == TX Byte 1 ==
6609 20:00:59.590971 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6610 20:00:59.593925 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6611 20:00:59.594394
6612 20:00:59.597945 [DATLAT]
6613 20:00:59.598494 Freq=400, CH0 RK1
6614 20:00:59.598867
6615 20:00:59.601062 DATLAT Default: 0xe
6616 20:00:59.601520 0, 0xFFFF, sum = 0
6617 20:00:59.603978 1, 0xFFFF, sum = 0
6618 20:00:59.604445 2, 0xFFFF, sum = 0
6619 20:00:59.606996 3, 0xFFFF, sum = 0
6620 20:00:59.607463 4, 0xFFFF, sum = 0
6621 20:00:59.610431 5, 0xFFFF, sum = 0
6622 20:00:59.610893 6, 0xFFFF, sum = 0
6623 20:00:59.614461 7, 0xFFFF, sum = 0
6624 20:00:59.615033 8, 0xFFFF, sum = 0
6625 20:00:59.617364 9, 0xFFFF, sum = 0
6626 20:00:59.617924 10, 0xFFFF, sum = 0
6627 20:00:59.620476 11, 0xFFFF, sum = 0
6628 20:00:59.623836 12, 0xFFFF, sum = 0
6629 20:00:59.624274 13, 0x0, sum = 1
6630 20:00:59.624641 14, 0x0, sum = 2
6631 20:00:59.627324 15, 0x0, sum = 3
6632 20:00:59.627933 16, 0x0, sum = 4
6633 20:00:59.630402 best_step = 14
6634 20:00:59.630950
6635 20:00:59.631317 ==
6636 20:00:59.633531 Dram Type= 6, Freq= 0, CH_0, rank 1
6637 20:00:59.637102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 20:00:59.637662 ==
6639 20:00:59.640490 RX Vref Scan: 0
6640 20:00:59.641045
6641 20:00:59.641418 RX Vref 0 -> 0, step: 1
6642 20:00:59.643707
6643 20:00:59.644304 RX Delay -359 -> 252, step: 8
6644 20:00:59.652393 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6645 20:00:59.655256 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6646 20:00:59.659555 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6647 20:00:59.665059 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6648 20:00:59.668390 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6649 20:00:59.672256 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6650 20:00:59.675107 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6651 20:00:59.681727 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6652 20:00:59.685450 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6653 20:00:59.688442 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6654 20:00:59.691620 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6655 20:00:59.698180 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6656 20:00:59.701341 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6657 20:00:59.704274 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6658 20:00:59.707491 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6659 20:00:59.714386 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6660 20:00:59.714947 ==
6661 20:00:59.718039 Dram Type= 6, Freq= 0, CH_0, rank 1
6662 20:00:59.721462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 20:00:59.722018 ==
6664 20:00:59.724281 DQS Delay:
6665 20:00:59.724753 DQS0 = 44, DQS1 = 60
6666 20:00:59.725139 DQM Delay:
6667 20:00:59.727518 DQM0 = 7, DQM1 = 14
6668 20:00:59.728039 DQ Delay:
6669 20:00:59.731785 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6670 20:00:59.734575 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6671 20:00:59.737585 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6672 20:00:59.741366 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6673 20:00:59.741923
6674 20:00:59.742292
6675 20:00:59.747593 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf3b, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6676 20:00:59.750835 CH0 RK1: MR19=C0C, MR18=AF3B
6677 20:00:59.757251 CH0_RK1: MR19=0xC0C, MR18=0xAF3B, DQSOSC=388, MR23=63, INC=392, DEC=261
6678 20:00:59.762293 [RxdqsGatingPostProcess] freq 400
6679 20:00:59.767128 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6680 20:00:59.770678 best DQS0 dly(2T, 0.5T) = (0, 10)
6681 20:00:59.773930 best DQS1 dly(2T, 0.5T) = (0, 10)
6682 20:00:59.777222 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6683 20:00:59.780621 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6684 20:00:59.781179 best DQS0 dly(2T, 0.5T) = (0, 10)
6685 20:00:59.783937 best DQS1 dly(2T, 0.5T) = (0, 10)
6686 20:00:59.788352 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6687 20:00:59.790374 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6688 20:00:59.793575 Pre-setting of DQS Precalculation
6689 20:00:59.800319 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6690 20:00:59.800909 ==
6691 20:00:59.803328 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 20:00:59.806612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 20:00:59.807076 ==
6694 20:00:59.813364 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6695 20:00:59.819908 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6696 20:00:59.822980 [CA 0] Center 36 (8~64) winsize 57
6697 20:00:59.827142 [CA 1] Center 36 (8~64) winsize 57
6698 20:00:59.827676 [CA 2] Center 36 (8~64) winsize 57
6699 20:00:59.830295 [CA 3] Center 36 (8~64) winsize 57
6700 20:00:59.833501 [CA 4] Center 36 (8~64) winsize 57
6701 20:00:59.836596 [CA 5] Center 36 (8~64) winsize 57
6702 20:00:59.837048
6703 20:00:59.839605 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6704 20:00:59.843782
6705 20:00:59.846476 [CATrainingPosCal] consider 1 rank data
6706 20:00:59.846986 u2DelayCellTimex100 = 270/100 ps
6707 20:00:59.853283 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 20:00:59.857591 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 20:00:59.860897 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 20:00:59.862908 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 20:00:59.866286 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 20:00:59.869516 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 20:00:59.869939
6714 20:00:59.873629 CA PerBit enable=1, Macro0, CA PI delay=36
6715 20:00:59.874172
6716 20:00:59.876063 [CBTSetCACLKResult] CA Dly = 36
6717 20:00:59.879681 CS Dly: 1 (0~32)
6718 20:00:59.880167 ==
6719 20:00:59.882965 Dram Type= 6, Freq= 0, CH_1, rank 1
6720 20:00:59.886355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 20:00:59.886910 ==
6722 20:00:59.892789 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6723 20:00:59.899219 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6724 20:00:59.903356 [CA 0] Center 36 (8~64) winsize 57
6725 20:00:59.903963 [CA 1] Center 36 (8~64) winsize 57
6726 20:00:59.906276 [CA 2] Center 36 (8~64) winsize 57
6727 20:00:59.909324 [CA 3] Center 36 (8~64) winsize 57
6728 20:00:59.911958 [CA 4] Center 36 (8~64) winsize 57
6729 20:00:59.916049 [CA 5] Center 36 (8~64) winsize 57
6730 20:00:59.916604
6731 20:00:59.918837 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6732 20:00:59.919391
6733 20:00:59.922960 [CATrainingPosCal] consider 2 rank data
6734 20:00:59.925476 u2DelayCellTimex100 = 270/100 ps
6735 20:00:59.928966 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 20:00:59.935547 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 20:00:59.938858 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 20:00:59.942434 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6739 20:00:59.945340 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6740 20:00:59.948729 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6741 20:00:59.949308
6742 20:00:59.952250 CA PerBit enable=1, Macro0, CA PI delay=36
6743 20:00:59.952871
6744 20:00:59.955828 [CBTSetCACLKResult] CA Dly = 36
6745 20:00:59.958796 CS Dly: 1 (0~32)
6746 20:00:59.959348
6747 20:00:59.962313 ----->DramcWriteLeveling(PI) begin...
6748 20:00:59.962880 ==
6749 20:00:59.965366 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 20:00:59.968439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 20:00:59.968902 ==
6752 20:00:59.971954 Write leveling (Byte 0): 40 => 8
6753 20:00:59.975004 Write leveling (Byte 1): 32 => 0
6754 20:00:59.978582 DramcWriteLeveling(PI) end<-----
6755 20:00:59.979063
6756 20:00:59.979427 ==
6757 20:00:59.981918 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 20:00:59.985066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 20:00:59.985629 ==
6760 20:00:59.988476 [Gating] SW mode calibration
6761 20:00:59.994986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6762 20:01:00.002110 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6763 20:01:00.005014 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6764 20:01:00.008661 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6765 20:01:00.014862 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6766 20:01:00.018276 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6767 20:01:00.021293 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 20:01:00.028448 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6769 20:01:00.031544 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6770 20:01:00.034927 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6771 20:01:00.041316 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6772 20:01:00.041871 Total UI for P1: 0, mck2ui 16
6773 20:01:00.047882 best dqsien dly found for B0: ( 0, 14, 24)
6774 20:01:00.048440 Total UI for P1: 0, mck2ui 16
6775 20:01:00.054541 best dqsien dly found for B1: ( 0, 14, 24)
6776 20:01:00.057776 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6777 20:01:00.060925 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6778 20:01:00.061484
6779 20:01:00.064398 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6780 20:01:00.067688 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6781 20:01:00.071083 [Gating] SW calibration Done
6782 20:01:00.071637 ==
6783 20:01:00.074438 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 20:01:00.077375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 20:01:00.077832 ==
6786 20:01:00.080839 RX Vref Scan: 0
6787 20:01:00.081390
6788 20:01:00.081755 RX Vref 0 -> 0, step: 1
6789 20:01:00.084468
6790 20:01:00.085028 RX Delay -410 -> 252, step: 16
6791 20:01:00.090874 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6792 20:01:00.094241 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6793 20:01:00.097103 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6794 20:01:00.100713 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6795 20:01:00.107371 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6796 20:01:00.111379 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6797 20:01:00.114038 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6798 20:01:00.117328 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6799 20:01:00.124342 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6800 20:01:00.127181 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6801 20:01:00.130572 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6802 20:01:00.137011 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6803 20:01:00.140334 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6804 20:01:00.143842 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6805 20:01:00.146519 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6806 20:01:00.153573 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6807 20:01:00.154155 ==
6808 20:01:00.156355 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 20:01:00.160168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 20:01:00.160740 ==
6811 20:01:00.161233 DQS Delay:
6812 20:01:00.163563 DQS0 = 43, DQS1 = 51
6813 20:01:00.164199 DQM Delay:
6814 20:01:00.166494 DQM0 = 12, DQM1 = 14
6815 20:01:00.166964 DQ Delay:
6816 20:01:00.169874 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6817 20:01:00.173367 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6818 20:01:00.176413 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6819 20:01:00.179508 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6820 20:01:00.179995
6821 20:01:00.180362
6822 20:01:00.180692 ==
6823 20:01:00.183360 Dram Type= 6, Freq= 0, CH_1, rank 0
6824 20:01:00.186304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 20:01:00.186858 ==
6826 20:01:00.187222
6827 20:01:00.187649
6828 20:01:00.189674 TX Vref Scan disable
6829 20:01:00.193383 == TX Byte 0 ==
6830 20:01:00.196147 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6831 20:01:00.199377 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6832 20:01:00.203316 == TX Byte 1 ==
6833 20:01:00.206097 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6834 20:01:00.209010 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6835 20:01:00.209457 ==
6836 20:01:00.212414 Dram Type= 6, Freq= 0, CH_1, rank 0
6837 20:01:00.215836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 20:01:00.219208 ==
6839 20:01:00.219633
6840 20:01:00.220110
6841 20:01:00.220521 TX Vref Scan disable
6842 20:01:00.222429 == TX Byte 0 ==
6843 20:01:00.225712 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6844 20:01:00.229658 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6845 20:01:00.232390 == TX Byte 1 ==
6846 20:01:00.235885 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6847 20:01:00.239428 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6848 20:01:00.240026
6849 20:01:00.242527 [DATLAT]
6850 20:01:00.242939 Freq=400, CH1 RK0
6851 20:01:00.243269
6852 20:01:00.245915 DATLAT Default: 0xf
6853 20:01:00.246329 0, 0xFFFF, sum = 0
6854 20:01:00.248986 1, 0xFFFF, sum = 0
6855 20:01:00.249526 2, 0xFFFF, sum = 0
6856 20:01:00.252010 3, 0xFFFF, sum = 0
6857 20:01:00.252428 4, 0xFFFF, sum = 0
6858 20:01:00.255333 5, 0xFFFF, sum = 0
6859 20:01:00.255896 6, 0xFFFF, sum = 0
6860 20:01:00.258957 7, 0xFFFF, sum = 0
6861 20:01:00.259382 8, 0xFFFF, sum = 0
6862 20:01:00.261921 9, 0xFFFF, sum = 0
6863 20:01:00.262340 10, 0xFFFF, sum = 0
6864 20:01:00.265753 11, 0xFFFF, sum = 0
6865 20:01:00.268396 12, 0xFFFF, sum = 0
6866 20:01:00.268815 13, 0x0, sum = 1
6867 20:01:00.271848 14, 0x0, sum = 2
6868 20:01:00.272284 15, 0x0, sum = 3
6869 20:01:00.272622 16, 0x0, sum = 4
6870 20:01:00.275452 best_step = 14
6871 20:01:00.275901
6872 20:01:00.276235 ==
6873 20:01:00.279047 Dram Type= 6, Freq= 0, CH_1, rank 0
6874 20:01:00.282386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 20:01:00.282934 ==
6876 20:01:00.285453 RX Vref Scan: 1
6877 20:01:00.285969
6878 20:01:00.288546 RX Vref 0 -> 0, step: 1
6879 20:01:00.288991
6880 20:01:00.289333 RX Delay -343 -> 252, step: 8
6881 20:01:00.289645
6882 20:01:00.291808 Set Vref, RX VrefLevel [Byte0]: 49
6883 20:01:00.294914 [Byte1]: 53
6884 20:01:00.300280
6885 20:01:00.300691 Final RX Vref Byte 0 = 49 to rank0
6886 20:01:00.303446 Final RX Vref Byte 1 = 53 to rank0
6887 20:01:00.307018 Final RX Vref Byte 0 = 49 to rank1
6888 20:01:00.310592 Final RX Vref Byte 1 = 53 to rank1==
6889 20:01:00.313318 Dram Type= 6, Freq= 0, CH_1, rank 0
6890 20:01:00.320463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 20:01:00.320992 ==
6892 20:01:00.321409 DQS Delay:
6893 20:01:00.323232 DQS0 = 44, DQS1 = 56
6894 20:01:00.323642 DQM Delay:
6895 20:01:00.324050 DQM0 = 8, DQM1 = 12
6896 20:01:00.326701 DQ Delay:
6897 20:01:00.330768 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6898 20:01:00.333696 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6899 20:01:00.334207 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6900 20:01:00.336367 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =20
6901 20:01:00.341068
6902 20:01:00.341598
6903 20:01:00.346506 [DQSOSCAuto] RK0, (LSB)MR18= 0x986f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6904 20:01:00.350156 CH1 RK0: MR19=C0C, MR18=986F
6905 20:01:00.356371 CH1_RK0: MR19=0xC0C, MR18=0x986F, DQSOSC=390, MR23=63, INC=388, DEC=258
6906 20:01:00.356888 ==
6907 20:01:00.359599 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 20:01:00.363255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 20:01:00.363824 ==
6910 20:01:00.366167 [Gating] SW mode calibration
6911 20:01:00.372837 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6912 20:01:00.379700 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6913 20:01:00.383012 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6914 20:01:00.386564 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6915 20:01:00.392832 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6916 20:01:00.395781 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6917 20:01:00.399071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 20:01:00.405919 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6919 20:01:00.408980 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6920 20:01:00.412179 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6921 20:01:00.419266 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6922 20:01:00.419833 Total UI for P1: 0, mck2ui 16
6923 20:01:00.425923 best dqsien dly found for B0: ( 0, 14, 24)
6924 20:01:00.426442 Total UI for P1: 0, mck2ui 16
6925 20:01:00.432645 best dqsien dly found for B1: ( 0, 14, 24)
6926 20:01:00.436511 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6927 20:01:00.438713 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6928 20:01:00.439231
6929 20:01:00.442058 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6930 20:01:00.445567 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6931 20:01:00.448642 [Gating] SW calibration Done
6932 20:01:00.449160 ==
6933 20:01:00.452297 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 20:01:00.455118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 20:01:00.455635 ==
6936 20:01:00.458651 RX Vref Scan: 0
6937 20:01:00.459182
6938 20:01:00.461714 RX Vref 0 -> 0, step: 1
6939 20:01:00.462126
6940 20:01:00.462457 RX Delay -410 -> 252, step: 16
6941 20:01:00.468798 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6942 20:01:00.471658 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6943 20:01:00.475303 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6944 20:01:00.481457 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6945 20:01:00.484873 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6946 20:01:00.488217 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6947 20:01:00.491458 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6948 20:01:00.498691 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6949 20:01:00.501554 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6950 20:01:00.504506 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6951 20:01:00.508252 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6952 20:01:00.514687 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6953 20:01:00.518235 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6954 20:01:00.520823 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6955 20:01:00.524423 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6956 20:01:00.531356 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6957 20:01:00.531979 ==
6958 20:01:00.534591 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 20:01:00.537844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 20:01:00.538278 ==
6961 20:01:00.538610 DQS Delay:
6962 20:01:00.541363 DQS0 = 51, DQS1 = 51
6963 20:01:00.541877 DQM Delay:
6964 20:01:00.544747 DQM0 = 19, DQM1 = 14
6965 20:01:00.545263 DQ Delay:
6966 20:01:00.547868 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6967 20:01:00.551046 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6968 20:01:00.554341 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6969 20:01:00.557305 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6970 20:01:00.557722
6971 20:01:00.558048
6972 20:01:00.558349 ==
6973 20:01:00.561127 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 20:01:00.564013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 20:01:00.564529 ==
6976 20:01:00.567249
6977 20:01:00.567658
6978 20:01:00.568043 TX Vref Scan disable
6979 20:01:00.571010 == TX Byte 0 ==
6980 20:01:00.574409 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6981 20:01:00.577312 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6982 20:01:00.580766 == TX Byte 1 ==
6983 20:01:00.583965 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6984 20:01:00.587536 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6985 20:01:00.588129 ==
6986 20:01:00.590604 Dram Type= 6, Freq= 0, CH_1, rank 1
6987 20:01:00.594002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6988 20:01:00.596940 ==
6989 20:01:00.597454
6990 20:01:00.597910
6991 20:01:00.598234 TX Vref Scan disable
6992 20:01:00.600381 == TX Byte 0 ==
6993 20:01:00.603405 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6994 20:01:00.607413 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6995 20:01:00.610278 == TX Byte 1 ==
6996 20:01:00.613625 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6997 20:01:00.616941 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6998 20:01:00.617493
6999 20:01:00.620579 [DATLAT]
7000 20:01:00.620993 Freq=400, CH1 RK1
7001 20:01:00.621329
7002 20:01:00.623300 DATLAT Default: 0xe
7003 20:01:00.623789 0, 0xFFFF, sum = 0
7004 20:01:00.627070 1, 0xFFFF, sum = 0
7005 20:01:00.627590 2, 0xFFFF, sum = 0
7006 20:01:00.630342 3, 0xFFFF, sum = 0
7007 20:01:00.630864 4, 0xFFFF, sum = 0
7008 20:01:00.633705 5, 0xFFFF, sum = 0
7009 20:01:00.634224 6, 0xFFFF, sum = 0
7010 20:01:00.636556 7, 0xFFFF, sum = 0
7011 20:01:00.636977 8, 0xFFFF, sum = 0
7012 20:01:00.640284 9, 0xFFFF, sum = 0
7013 20:01:00.640810 10, 0xFFFF, sum = 0
7014 20:01:00.643682 11, 0xFFFF, sum = 0
7015 20:01:00.646629 12, 0xFFFF, sum = 0
7016 20:01:00.647147 13, 0x0, sum = 1
7017 20:01:00.647485 14, 0x0, sum = 2
7018 20:01:00.650173 15, 0x0, sum = 3
7019 20:01:00.650687 16, 0x0, sum = 4
7020 20:01:00.653327 best_step = 14
7021 20:01:00.653842
7022 20:01:00.654175 ==
7023 20:01:00.656583 Dram Type= 6, Freq= 0, CH_1, rank 1
7024 20:01:00.660051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7025 20:01:00.660570 ==
7026 20:01:00.662849 RX Vref Scan: 0
7027 20:01:00.663316
7028 20:01:00.663652 RX Vref 0 -> 0, step: 1
7029 20:01:00.666017
7030 20:01:00.666530 RX Delay -343 -> 252, step: 8
7031 20:01:00.675105 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7032 20:01:00.678035 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7033 20:01:00.681674 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7034 20:01:00.688317 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7035 20:01:00.691410 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7036 20:01:00.694634 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7037 20:01:00.697536 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7038 20:01:00.704327 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7039 20:01:00.707757 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7040 20:01:00.711149 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7041 20:01:00.714319 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7042 20:01:00.720842 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7043 20:01:00.724981 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7044 20:01:00.727539 iDelay=225, Bit 13, Center -36 (-279 ~ 208) 488
7045 20:01:00.731053 iDelay=225, Bit 14, Center -36 (-279 ~ 208) 488
7046 20:01:00.737554 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7047 20:01:00.738055 ==
7048 20:01:00.740767 Dram Type= 6, Freq= 0, CH_1, rank 1
7049 20:01:00.744233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7050 20:01:00.744753 ==
7051 20:01:00.745088 DQS Delay:
7052 20:01:00.747645 DQS0 = 48, DQS1 = 56
7053 20:01:00.748231 DQM Delay:
7054 20:01:00.750842 DQM0 = 12, DQM1 = 12
7055 20:01:00.751351 DQ Delay:
7056 20:01:00.754393 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7057 20:01:00.757136 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
7058 20:01:00.760540 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7059 20:01:00.764267 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
7060 20:01:00.764899
7061 20:01:00.765244
7062 20:01:00.770480 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7063 20:01:00.774306 CH1 RK1: MR19=C0C, MR18=6C5B
7064 20:01:00.780596 CH1_RK1: MR19=0xC0C, MR18=0x6C5B, DQSOSC=396, MR23=63, INC=376, DEC=251
7065 20:01:00.784194 [RxdqsGatingPostProcess] freq 400
7066 20:01:00.790175 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7067 20:01:00.793444 best DQS0 dly(2T, 0.5T) = (0, 10)
7068 20:01:00.797121 best DQS1 dly(2T, 0.5T) = (0, 10)
7069 20:01:00.800665 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7070 20:01:00.804042 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7071 20:01:00.807066 best DQS0 dly(2T, 0.5T) = (0, 10)
7072 20:01:00.807581 best DQS1 dly(2T, 0.5T) = (0, 10)
7073 20:01:00.810297 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7074 20:01:00.813331 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7075 20:01:00.816327 Pre-setting of DQS Precalculation
7076 20:01:00.823005 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7077 20:01:00.829475 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7078 20:01:00.836050 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7079 20:01:00.836598
7080 20:01:00.836962
7081 20:01:00.840024 [Calibration Summary] 800 Mbps
7082 20:01:00.843246 CH 0, Rank 0
7083 20:01:00.843867 SW Impedance : PASS
7084 20:01:00.846515 DUTY Scan : NO K
7085 20:01:00.849361 ZQ Calibration : PASS
7086 20:01:00.849817 Jitter Meter : NO K
7087 20:01:00.852890 CBT Training : PASS
7088 20:01:00.853486 Write leveling : PASS
7089 20:01:00.855992 RX DQS gating : PASS
7090 20:01:00.859569 RX DQ/DQS(RDDQC) : PASS
7091 20:01:00.860184 TX DQ/DQS : PASS
7092 20:01:00.863088 RX DATLAT : PASS
7093 20:01:00.866372 RX DQ/DQS(Engine): PASS
7094 20:01:00.866960 TX OE : NO K
7095 20:01:00.869264 All Pass.
7096 20:01:00.869716
7097 20:01:00.870079 CH 0, Rank 1
7098 20:01:00.873118 SW Impedance : PASS
7099 20:01:00.873671 DUTY Scan : NO K
7100 20:01:00.876584 ZQ Calibration : PASS
7101 20:01:00.879571 Jitter Meter : NO K
7102 20:01:00.880181 CBT Training : PASS
7103 20:01:00.882480 Write leveling : NO K
7104 20:01:00.885909 RX DQS gating : PASS
7105 20:01:00.886464 RX DQ/DQS(RDDQC) : PASS
7106 20:01:00.889252 TX DQ/DQS : PASS
7107 20:01:00.892671 RX DATLAT : PASS
7108 20:01:00.893298 RX DQ/DQS(Engine): PASS
7109 20:01:00.895711 TX OE : NO K
7110 20:01:00.896302 All Pass.
7111 20:01:00.896664
7112 20:01:00.899194 CH 1, Rank 0
7113 20:01:00.899977 SW Impedance : PASS
7114 20:01:00.902511 DUTY Scan : NO K
7115 20:01:00.906099 ZQ Calibration : PASS
7116 20:01:00.906653 Jitter Meter : NO K
7117 20:01:00.909178 CBT Training : PASS
7118 20:01:00.912205 Write leveling : PASS
7119 20:01:00.912660 RX DQS gating : PASS
7120 20:01:00.915836 RX DQ/DQS(RDDQC) : PASS
7121 20:01:00.916294 TX DQ/DQS : PASS
7122 20:01:00.919369 RX DATLAT : PASS
7123 20:01:00.922392 RX DQ/DQS(Engine): PASS
7124 20:01:00.923007 TX OE : NO K
7125 20:01:00.925223 All Pass.
7126 20:01:00.925673
7127 20:01:00.926036 CH 1, Rank 1
7128 20:01:00.928932 SW Impedance : PASS
7129 20:01:00.929483 DUTY Scan : NO K
7130 20:01:00.932352 ZQ Calibration : PASS
7131 20:01:00.935711 Jitter Meter : NO K
7132 20:01:00.936311 CBT Training : PASS
7133 20:01:00.938873 Write leveling : NO K
7134 20:01:00.942171 RX DQS gating : PASS
7135 20:01:00.942628 RX DQ/DQS(RDDQC) : PASS
7136 20:01:00.945796 TX DQ/DQS : PASS
7137 20:01:00.949047 RX DATLAT : PASS
7138 20:01:00.949605 RX DQ/DQS(Engine): PASS
7139 20:01:00.952007 TX OE : NO K
7140 20:01:00.952564 All Pass.
7141 20:01:00.952931
7142 20:01:00.955227 DramC Write-DBI off
7143 20:01:00.958620 PER_BANK_REFRESH: Hybrid Mode
7144 20:01:00.959075 TX_TRACKING: ON
7145 20:01:00.968283 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7146 20:01:00.972290 [FAST_K] Save calibration result to emmc
7147 20:01:00.974936 dramc_set_vcore_voltage set vcore to 725000
7148 20:01:00.978404 Read voltage for 1600, 0
7149 20:01:00.978860 Vio18 = 0
7150 20:01:00.979226 Vcore = 725000
7151 20:01:00.981629 Vdram = 0
7152 20:01:00.982080 Vddq = 0
7153 20:01:00.982444 Vmddr = 0
7154 20:01:00.988264 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7155 20:01:00.991472 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7156 20:01:00.995199 MEM_TYPE=3, freq_sel=13
7157 20:01:00.998585 sv_algorithm_assistance_LP4_3733
7158 20:01:01.001978 ============ PULL DRAM RESETB DOWN ============
7159 20:01:01.007919 ========== PULL DRAM RESETB DOWN end =========
7160 20:01:01.011476 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7161 20:01:01.014780 ===================================
7162 20:01:01.018098 LPDDR4 DRAM CONFIGURATION
7163 20:01:01.022269 ===================================
7164 20:01:01.022885 EX_ROW_EN[0] = 0x0
7165 20:01:01.024331 EX_ROW_EN[1] = 0x0
7166 20:01:01.024788 LP4Y_EN = 0x0
7167 20:01:01.028552 WORK_FSP = 0x1
7168 20:01:01.029008 WL = 0x5
7169 20:01:01.031028 RL = 0x5
7170 20:01:01.031482 BL = 0x2
7171 20:01:01.034393 RPST = 0x0
7172 20:01:01.037976 RD_PRE = 0x0
7173 20:01:01.038495 WR_PRE = 0x1
7174 20:01:01.041315 WR_PST = 0x1
7175 20:01:01.041864 DBI_WR = 0x0
7176 20:01:01.044262 DBI_RD = 0x0
7177 20:01:01.044815 OTF = 0x1
7178 20:01:01.048112 ===================================
7179 20:01:01.051434 ===================================
7180 20:01:01.054124 ANA top config
7181 20:01:01.057688 ===================================
7182 20:01:01.058244 DLL_ASYNC_EN = 0
7183 20:01:01.060863 ALL_SLAVE_EN = 0
7184 20:01:01.063783 NEW_RANK_MODE = 1
7185 20:01:01.067318 DLL_IDLE_MODE = 1
7186 20:01:01.067916 LP45_APHY_COMB_EN = 1
7187 20:01:01.070134 TX_ODT_DIS = 0
7188 20:01:01.073569 NEW_8X_MODE = 1
7189 20:01:01.077104 ===================================
7190 20:01:01.080673 ===================================
7191 20:01:01.083891 data_rate = 3200
7192 20:01:01.087174 CKR = 1
7193 20:01:01.090198 DQ_P2S_RATIO = 8
7194 20:01:01.093617 ===================================
7195 20:01:01.094170 CA_P2S_RATIO = 8
7196 20:01:01.096859 DQ_CA_OPEN = 0
7197 20:01:01.100706 DQ_SEMI_OPEN = 0
7198 20:01:01.103013 CA_SEMI_OPEN = 0
7199 20:01:01.106971 CA_FULL_RATE = 0
7200 20:01:01.110765 DQ_CKDIV4_EN = 0
7201 20:01:01.113423 CA_CKDIV4_EN = 0
7202 20:01:01.113959 CA_PREDIV_EN = 0
7203 20:01:01.116406 PH8_DLY = 12
7204 20:01:01.119882 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7205 20:01:01.123130 DQ_AAMCK_DIV = 4
7206 20:01:01.126521 CA_AAMCK_DIV = 4
7207 20:01:01.129258 CA_ADMCK_DIV = 4
7208 20:01:01.129715 DQ_TRACK_CA_EN = 0
7209 20:01:01.132887 CA_PICK = 1600
7210 20:01:01.136527 CA_MCKIO = 1600
7211 20:01:01.139895 MCKIO_SEMI = 0
7212 20:01:01.143305 PLL_FREQ = 3068
7213 20:01:01.146277 DQ_UI_PI_RATIO = 32
7214 20:01:01.149646 CA_UI_PI_RATIO = 0
7215 20:01:01.153360 ===================================
7216 20:01:01.156132 ===================================
7217 20:01:01.156690 memory_type:LPDDR4
7218 20:01:01.159703 GP_NUM : 10
7219 20:01:01.162978 SRAM_EN : 1
7220 20:01:01.163534 MD32_EN : 0
7221 20:01:01.166382 ===================================
7222 20:01:01.169425 [ANA_INIT] >>>>>>>>>>>>>>
7223 20:01:01.173041 <<<<<< [CONFIGURE PHASE]: ANA_TX
7224 20:01:01.176429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7225 20:01:01.179342 ===================================
7226 20:01:01.182387 data_rate = 3200,PCW = 0X7600
7227 20:01:01.187433 ===================================
7228 20:01:01.189232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7229 20:01:01.192419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7230 20:01:01.199006 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7231 20:01:01.203060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7232 20:01:01.205590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7233 20:01:01.209268 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7234 20:01:01.212559 [ANA_INIT] flow start
7235 20:01:01.215888 [ANA_INIT] PLL >>>>>>>>
7236 20:01:01.216342 [ANA_INIT] PLL <<<<<<<<
7237 20:01:01.219137 [ANA_INIT] MIDPI >>>>>>>>
7238 20:01:01.222182 [ANA_INIT] MIDPI <<<<<<<<
7239 20:01:01.226244 [ANA_INIT] DLL >>>>>>>>
7240 20:01:01.226799 [ANA_INIT] DLL <<<<<<<<
7241 20:01:01.228668 [ANA_INIT] flow end
7242 20:01:01.232354 ============ LP4 DIFF to SE enter ============
7243 20:01:01.236136 ============ LP4 DIFF to SE exit ============
7244 20:01:01.239107 [ANA_INIT] <<<<<<<<<<<<<
7245 20:01:01.242354 [Flow] Enable top DCM control >>>>>
7246 20:01:01.245729 [Flow] Enable top DCM control <<<<<
7247 20:01:01.248816 Enable DLL master slave shuffle
7248 20:01:01.255905 ==============================================================
7249 20:01:01.256468 Gating Mode config
7250 20:01:01.262275 ==============================================================
7251 20:01:01.262829 Config description:
7252 20:01:01.272001 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7253 20:01:01.278966 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7254 20:01:01.285171 SELPH_MODE 0: By rank 1: By Phase
7255 20:01:01.288527 ==============================================================
7256 20:01:01.292211 GAT_TRACK_EN = 1
7257 20:01:01.294816 RX_GATING_MODE = 2
7258 20:01:01.298091 RX_GATING_TRACK_MODE = 2
7259 20:01:01.301464 SELPH_MODE = 1
7260 20:01:01.304954 PICG_EARLY_EN = 1
7261 20:01:01.307894 VALID_LAT_VALUE = 1
7262 20:01:01.314299 ==============================================================
7263 20:01:01.317999 Enter into Gating configuration >>>>
7264 20:01:01.321042 Exit from Gating configuration <<<<
7265 20:01:01.324666 Enter into DVFS_PRE_config >>>>>
7266 20:01:01.334238 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7267 20:01:01.337684 Exit from DVFS_PRE_config <<<<<
7268 20:01:01.341038 Enter into PICG configuration >>>>
7269 20:01:01.344324 Exit from PICG configuration <<<<
7270 20:01:01.347642 [RX_INPUT] configuration >>>>>
7271 20:01:01.348126 [RX_INPUT] configuration <<<<<
7272 20:01:01.353867 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7273 20:01:01.360599 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7274 20:01:01.367669 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7275 20:01:01.370485 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7276 20:01:01.377524 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7277 20:01:01.383895 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7278 20:01:01.387493 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7279 20:01:01.393729 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7280 20:01:01.396765 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7281 20:01:01.400576 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7282 20:01:01.404034 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7283 20:01:01.410655 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7284 20:01:01.413670 ===================================
7285 20:01:01.414310 LPDDR4 DRAM CONFIGURATION
7286 20:01:01.417042 ===================================
7287 20:01:01.420590 EX_ROW_EN[0] = 0x0
7288 20:01:01.423505 EX_ROW_EN[1] = 0x0
7289 20:01:01.424013 LP4Y_EN = 0x0
7290 20:01:01.427029 WORK_FSP = 0x1
7291 20:01:01.427582 WL = 0x5
7292 20:01:01.430498 RL = 0x5
7293 20:01:01.431050 BL = 0x2
7294 20:01:01.433443 RPST = 0x0
7295 20:01:01.433997 RD_PRE = 0x0
7296 20:01:01.437307 WR_PRE = 0x1
7297 20:01:01.437858 WR_PST = 0x1
7298 20:01:01.439894 DBI_WR = 0x0
7299 20:01:01.440349 DBI_RD = 0x0
7300 20:01:01.443306 OTF = 0x1
7301 20:01:01.446732 ===================================
7302 20:01:01.450137 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7303 20:01:01.453525 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7304 20:01:01.460375 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7305 20:01:01.463250 ===================================
7306 20:01:01.463845 LPDDR4 DRAM CONFIGURATION
7307 20:01:01.467199 ===================================
7308 20:01:01.469912 EX_ROW_EN[0] = 0x10
7309 20:01:01.472901 EX_ROW_EN[1] = 0x0
7310 20:01:01.473530 LP4Y_EN = 0x0
7311 20:01:01.476965 WORK_FSP = 0x1
7312 20:01:01.477520 WL = 0x5
7313 20:01:01.480260 RL = 0x5
7314 20:01:01.480813 BL = 0x2
7315 20:01:01.482738 RPST = 0x0
7316 20:01:01.483191 RD_PRE = 0x0
7317 20:01:01.486504 WR_PRE = 0x1
7318 20:01:01.487062 WR_PST = 0x1
7319 20:01:01.490075 DBI_WR = 0x0
7320 20:01:01.490628 DBI_RD = 0x0
7321 20:01:01.493040 OTF = 0x1
7322 20:01:01.496240 ===================================
7323 20:01:01.502959 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7324 20:01:01.503518 ==
7325 20:01:01.505935 Dram Type= 6, Freq= 0, CH_0, rank 0
7326 20:01:01.509064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7327 20:01:01.509523 ==
7328 20:01:01.512907 [Duty_Offset_Calibration]
7329 20:01:01.513459 B0:1 B1:-1 CA:0
7330 20:01:01.513831
7331 20:01:01.516089 [DutyScan_Calibration_Flow] k_type=0
7332 20:01:01.527654
7333 20:01:01.528258 ==CLK 0==
7334 20:01:01.530325 Final CLK duty delay cell = 0
7335 20:01:01.533406 [0] MAX Duty = 5124%(X100), DQS PI = 22
7336 20:01:01.536803 [0] MIN Duty = 4907%(X100), DQS PI = 4
7337 20:01:01.537361 [0] AVG Duty = 5015%(X100)
7338 20:01:01.540049
7339 20:01:01.543787 CH0 CLK Duty spec in!! Max-Min= 217%
7340 20:01:01.546792 [DutyScan_Calibration_Flow] ====Done====
7341 20:01:01.547343
7342 20:01:01.550651 [DutyScan_Calibration_Flow] k_type=1
7343 20:01:01.566621
7344 20:01:01.567176 ==DQS 0 ==
7345 20:01:01.569582 Final DQS duty delay cell = -4
7346 20:01:01.572547 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7347 20:01:01.576047 [-4] MIN Duty = 4844%(X100), DQS PI = 10
7348 20:01:01.579325 [-4] AVG Duty = 4922%(X100)
7349 20:01:01.579945
7350 20:01:01.580322 ==DQS 1 ==
7351 20:01:01.582886 Final DQS duty delay cell = 0
7352 20:01:01.585969 [0] MAX Duty = 5187%(X100), DQS PI = 4
7353 20:01:01.589581 [0] MIN Duty = 5031%(X100), DQS PI = 18
7354 20:01:01.592465 [0] AVG Duty = 5109%(X100)
7355 20:01:01.593020
7356 20:01:01.596038 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7357 20:01:01.596592
7358 20:01:01.599106 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7359 20:01:01.602269 [DutyScan_Calibration_Flow] ====Done====
7360 20:01:01.602723
7361 20:01:01.605635 [DutyScan_Calibration_Flow] k_type=3
7362 20:01:01.623599
7363 20:01:01.624080 ==DQM 0 ==
7364 20:01:01.627829 Final DQM duty delay cell = 0
7365 20:01:01.630511 [0] MAX Duty = 5124%(X100), DQS PI = 20
7366 20:01:01.633607 [0] MIN Duty = 4907%(X100), DQS PI = 8
7367 20:01:01.636693 [0] AVG Duty = 5015%(X100)
7368 20:01:01.637106
7369 20:01:01.637427 ==DQM 1 ==
7370 20:01:01.639933 Final DQM duty delay cell = 0
7371 20:01:01.643232 [0] MAX Duty = 5000%(X100), DQS PI = 4
7372 20:01:01.646589 [0] MIN Duty = 4813%(X100), DQS PI = 20
7373 20:01:01.650566 [0] AVG Duty = 4906%(X100)
7374 20:01:01.651092
7375 20:01:01.653413 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7376 20:01:01.653915
7377 20:01:01.656351 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7378 20:01:01.659770 [DutyScan_Calibration_Flow] ====Done====
7379 20:01:01.660226
7380 20:01:01.663271 [DutyScan_Calibration_Flow] k_type=2
7381 20:01:01.679973
7382 20:01:01.680511 ==DQ 0 ==
7383 20:01:01.683378 Final DQ duty delay cell = -4
7384 20:01:01.686528 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7385 20:01:01.690545 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7386 20:01:01.692875 [-4] AVG Duty = 4953%(X100)
7387 20:01:01.693428
7388 20:01:01.693790 ==DQ 1 ==
7389 20:01:01.696328 Final DQ duty delay cell = 0
7390 20:01:01.699506 [0] MAX Duty = 5125%(X100), DQS PI = 4
7391 20:01:01.702945 [0] MIN Duty = 4969%(X100), DQS PI = 38
7392 20:01:01.705866 [0] AVG Duty = 5047%(X100)
7393 20:01:01.706618
7394 20:01:01.709373 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7395 20:01:01.709928
7396 20:01:01.713236 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7397 20:01:01.716477 [DutyScan_Calibration_Flow] ====Done====
7398 20:01:01.716935 ==
7399 20:01:01.720038 Dram Type= 6, Freq= 0, CH_1, rank 0
7400 20:01:01.722937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7401 20:01:01.723500 ==
7402 20:01:01.726239 [Duty_Offset_Calibration]
7403 20:01:01.726802 B0:-1 B1:1 CA:2
7404 20:01:01.727170
7405 20:01:01.729082 [DutyScan_Calibration_Flow] k_type=0
7406 20:01:01.740595
7407 20:01:01.741147 ==CLK 0==
7408 20:01:01.743911 Final CLK duty delay cell = 0
7409 20:01:01.747698 [0] MAX Duty = 5187%(X100), DQS PI = 22
7410 20:01:01.750448 [0] MIN Duty = 4969%(X100), DQS PI = 0
7411 20:01:01.753575 [0] AVG Duty = 5078%(X100)
7412 20:01:01.754135
7413 20:01:01.756971 CH1 CLK Duty spec in!! Max-Min= 218%
7414 20:01:01.760106 [DutyScan_Calibration_Flow] ====Done====
7415 20:01:01.760654
7416 20:01:01.763578 [DutyScan_Calibration_Flow] k_type=1
7417 20:01:01.780191
7418 20:01:01.780734 ==DQS 0 ==
7419 20:01:01.783371 Final DQS duty delay cell = 0
7420 20:01:01.787185 [0] MAX Duty = 5124%(X100), DQS PI = 18
7421 20:01:01.790353 [0] MIN Duty = 4907%(X100), DQS PI = 10
7422 20:01:01.793396 [0] AVG Duty = 5015%(X100)
7423 20:01:01.793949
7424 20:01:01.794313 ==DQS 1 ==
7425 20:01:01.796489 Final DQS duty delay cell = 0
7426 20:01:01.799566 [0] MAX Duty = 5124%(X100), DQS PI = 26
7427 20:01:01.803508 [0] MIN Duty = 4969%(X100), DQS PI = 54
7428 20:01:01.806409 [0] AVG Duty = 5046%(X100)
7429 20:01:01.807228
7430 20:01:01.809644 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7431 20:01:01.810222
7432 20:01:01.812954 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7433 20:01:01.816607 [DutyScan_Calibration_Flow] ====Done====
7434 20:01:01.817065
7435 20:01:01.819386 [DutyScan_Calibration_Flow] k_type=3
7436 20:01:01.837103
7437 20:01:01.837656 ==DQM 0 ==
7438 20:01:01.840440 Final DQM duty delay cell = 0
7439 20:01:01.844602 [0] MAX Duty = 5218%(X100), DQS PI = 18
7440 20:01:01.847191 [0] MIN Duty = 5000%(X100), DQS PI = 10
7441 20:01:01.850519 [0] AVG Duty = 5109%(X100)
7442 20:01:01.851073
7443 20:01:01.851577 ==DQM 1 ==
7444 20:01:01.853837 Final DQM duty delay cell = 0
7445 20:01:01.856933 [0] MAX Duty = 5156%(X100), DQS PI = 2
7446 20:01:01.860620 [0] MIN Duty = 4969%(X100), DQS PI = 34
7447 20:01:01.864249 [0] AVG Duty = 5062%(X100)
7448 20:01:01.864806
7449 20:01:01.866758 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7450 20:01:01.867217
7451 20:01:01.870340 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7452 20:01:01.873865 [DutyScan_Calibration_Flow] ====Done====
7453 20:01:01.874432
7454 20:01:01.877956 [DutyScan_Calibration_Flow] k_type=2
7455 20:01:01.894336
7456 20:01:01.894892 ==DQ 0 ==
7457 20:01:01.897374 Final DQ duty delay cell = 0
7458 20:01:01.900572 [0] MAX Duty = 5187%(X100), DQS PI = 32
7459 20:01:01.904450 [0] MIN Duty = 4906%(X100), DQS PI = 10
7460 20:01:01.905022 [0] AVG Duty = 5046%(X100)
7461 20:01:01.907347
7462 20:01:01.908295 ==DQ 1 ==
7463 20:01:01.910536 Final DQ duty delay cell = 0
7464 20:01:01.913975 [0] MAX Duty = 5156%(X100), DQS PI = 8
7465 20:01:01.917061 [0] MIN Duty = 4969%(X100), DQS PI = 32
7466 20:01:01.917524 [0] AVG Duty = 5062%(X100)
7467 20:01:01.920526
7468 20:01:01.924131 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7469 20:01:01.924691
7470 20:01:01.927132 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7471 20:01:01.929959 [DutyScan_Calibration_Flow] ====Done====
7472 20:01:01.933429 nWR fixed to 30
7473 20:01:01.936906 [ModeRegInit_LP4] CH0 RK0
7474 20:01:01.937467 [ModeRegInit_LP4] CH0 RK1
7475 20:01:01.940277 [ModeRegInit_LP4] CH1 RK0
7476 20:01:01.943616 [ModeRegInit_LP4] CH1 RK1
7477 20:01:01.944224 match AC timing 5
7478 20:01:01.950022 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7479 20:01:01.953416 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7480 20:01:01.956954 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7481 20:01:01.963210 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7482 20:01:01.966160 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7483 20:01:01.966624 [MiockJmeterHQA]
7484 20:01:01.966997
7485 20:01:01.970202 [DramcMiockJmeter] u1RxGatingPI = 0
7486 20:01:01.973241 0 : 4252, 4027
7487 20:01:01.973809 4 : 4252, 4027
7488 20:01:01.976436 8 : 4259, 4032
7489 20:01:01.977002 12 : 4368, 4140
7490 20:01:01.980053 16 : 4252, 4027
7491 20:01:01.980620 20 : 4252, 4027
7492 20:01:01.980995 24 : 4253, 4027
7493 20:01:01.982965 28 : 4253, 4026
7494 20:01:01.983450 32 : 4360, 4138
7495 20:01:01.986964 36 : 4253, 4026
7496 20:01:01.987426 40 : 4250, 4027
7497 20:01:01.989428 44 : 4249, 4027
7498 20:01:01.989993 48 : 4253, 4029
7499 20:01:01.992422 52 : 4250, 4027
7500 20:01:01.992892 56 : 4360, 4137
7501 20:01:01.993266 60 : 4361, 4137
7502 20:01:01.996181 64 : 4249, 4027
7503 20:01:01.996750 68 : 4250, 4026
7504 20:01:01.999360 72 : 4250, 4027
7505 20:01:01.999951 76 : 4249, 4027
7506 20:01:02.002412 80 : 4253, 4029
7507 20:01:02.002874 84 : 4361, 4137
7508 20:01:02.005977 88 : 4250, 4026
7509 20:01:02.006543 92 : 4250, 441
7510 20:01:02.006925 96 : 4360, 0
7511 20:01:02.008897 100 : 4249, 0
7512 20:01:02.009559 104 : 4250, 0
7513 20:01:02.012372 108 : 4250, 0
7514 20:01:02.012860 112 : 4249, 0
7515 20:01:02.013353 116 : 4249, 0
7516 20:01:02.015639 120 : 4252, 0
7517 20:01:02.016176 124 : 4250, 0
7518 20:01:02.016675 128 : 4250, 0
7519 20:01:02.018784 132 : 4363, 0
7520 20:01:02.019249 136 : 4361, 0
7521 20:01:02.022768 140 : 4249, 0
7522 20:01:02.023340 144 : 4250, 0
7523 20:01:02.023714 148 : 4250, 0
7524 20:01:02.025991 152 : 4250, 0
7525 20:01:02.026457 156 : 4250, 0
7526 20:01:02.029374 160 : 4250, 0
7527 20:01:02.029941 164 : 4250, 0
7528 20:01:02.030316 168 : 4250, 0
7529 20:01:02.032549 172 : 4252, 0
7530 20:01:02.033015 176 : 4360, 0
7531 20:01:02.035466 180 : 4360, 0
7532 20:01:02.035982 184 : 4248, 0
7533 20:01:02.036358 188 : 4361, 0
7534 20:01:02.038936 192 : 4249, 0
7535 20:01:02.039402 196 : 4250, 0
7536 20:01:02.042277 200 : 4250, 0
7537 20:01:02.042842 204 : 4249, 0
7538 20:01:02.043216 208 : 4250, 0
7539 20:01:02.045473 212 : 4253, 0
7540 20:01:02.046032 216 : 4249, 0
7541 20:01:02.046411 220 : 4250, 0
7542 20:01:02.048965 224 : 4252, 231
7543 20:01:02.049538 228 : 4360, 3457
7544 20:01:02.052389 232 : 4250, 4027
7545 20:01:02.052955 236 : 4250, 4026
7546 20:01:02.055999 240 : 4361, 4137
7547 20:01:02.056562 244 : 4250, 4027
7548 20:01:02.059029 248 : 4249, 4027
7549 20:01:02.059593 252 : 4250, 4026
7550 20:01:02.061806 256 : 4253, 4029
7551 20:01:02.062271 260 : 4249, 4027
7552 20:01:02.065362 264 : 4249, 4027
7553 20:01:02.065933 268 : 4360, 4137
7554 20:01:02.069171 272 : 4250, 4027
7555 20:01:02.069740 276 : 4250, 4027
7556 20:01:02.070117 280 : 4361, 4137
7557 20:01:02.071776 284 : 4249, 4027
7558 20:01:02.072246 288 : 4250, 4027
7559 20:01:02.075341 292 : 4363, 4140
7560 20:01:02.075993 296 : 4250, 4027
7561 20:01:02.079211 300 : 4249, 4027
7562 20:01:02.079838 304 : 4250, 4026
7563 20:01:02.081669 308 : 4253, 4029
7564 20:01:02.082136 312 : 4250, 4027
7565 20:01:02.085140 316 : 4249, 4027
7566 20:01:02.085605 320 : 4361, 4137
7567 20:01:02.088621 324 : 4250, 4026
7568 20:01:02.089188 328 : 4250, 4027
7569 20:01:02.091715 332 : 4360, 4138
7570 20:01:02.092216 336 : 4249, 3837
7571 20:01:02.095662 340 : 4250, 2047
7572 20:01:02.096273
7573 20:01:02.096649 MIOCK jitter meter ch=0
7574 20:01:02.096994
7575 20:01:02.098401 1T = (340-92) = 248 dly cells
7576 20:01:02.105170 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7577 20:01:02.105733 ==
7578 20:01:02.108273 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 20:01:02.111551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 20:01:02.112063 ==
7581 20:01:02.119311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7582 20:01:02.121813 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7583 20:01:02.124681 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7584 20:01:02.131996 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7585 20:01:02.141070 [CA 0] Center 43 (13~74) winsize 62
7586 20:01:02.144517 [CA 1] Center 43 (13~73) winsize 61
7587 20:01:02.147669 [CA 2] Center 39 (10~68) winsize 59
7588 20:01:02.151038 [CA 3] Center 38 (9~68) winsize 60
7589 20:01:02.154531 [CA 4] Center 37 (8~66) winsize 59
7590 20:01:02.157695 [CA 5] Center 36 (7~66) winsize 60
7591 20:01:02.158258
7592 20:01:02.161172 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7593 20:01:02.161809
7594 20:01:02.164664 [CATrainingPosCal] consider 1 rank data
7595 20:01:02.168035 u2DelayCellTimex100 = 262/100 ps
7596 20:01:02.171316 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7597 20:01:02.177413 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7598 20:01:02.181007 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7599 20:01:02.183993 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7600 20:01:02.187350 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7601 20:01:02.191268 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7602 20:01:02.191871
7603 20:01:02.193968 CA PerBit enable=1, Macro0, CA PI delay=36
7604 20:01:02.194528
7605 20:01:02.196911 [CBTSetCACLKResult] CA Dly = 36
7606 20:01:02.200383 CS Dly: 12 (0~43)
7607 20:01:02.203651 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7608 20:01:02.207007 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7609 20:01:02.207565 ==
7610 20:01:02.209919 Dram Type= 6, Freq= 0, CH_0, rank 1
7611 20:01:02.216630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 20:01:02.217116 ==
7613 20:01:02.220120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7614 20:01:02.226741 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7615 20:01:02.230131 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7616 20:01:02.236646 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7617 20:01:02.244791 [CA 0] Center 42 (12~73) winsize 62
7618 20:01:02.248204 [CA 1] Center 43 (13~73) winsize 61
7619 20:01:02.251844 [CA 2] Center 37 (8~67) winsize 60
7620 20:01:02.254334 [CA 3] Center 37 (7~67) winsize 61
7621 20:01:02.258107 [CA 4] Center 35 (6~65) winsize 60
7622 20:01:02.262049 [CA 5] Center 35 (5~65) winsize 61
7623 20:01:02.262623
7624 20:01:02.264434 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7625 20:01:02.264912
7626 20:01:02.267844 [CATrainingPosCal] consider 2 rank data
7627 20:01:02.271305 u2DelayCellTimex100 = 262/100 ps
7628 20:01:02.278503 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7629 20:01:02.281141 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7630 20:01:02.284220 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7631 20:01:02.287868 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7632 20:01:02.291593 CA4 delay=36 (8~65),Diff = 0 PI (0 cell)
7633 20:01:02.294396 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7634 20:01:02.294969
7635 20:01:02.297551 CA PerBit enable=1, Macro0, CA PI delay=36
7636 20:01:02.298122
7637 20:01:02.300620 [CBTSetCACLKResult] CA Dly = 36
7638 20:01:02.304114 CS Dly: 12 (0~43)
7639 20:01:02.307670 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7640 20:01:02.310550 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7641 20:01:02.311151
7642 20:01:02.314084 ----->DramcWriteLeveling(PI) begin...
7643 20:01:02.314648 ==
7644 20:01:02.316961 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 20:01:02.323867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 20:01:02.324426 ==
7647 20:01:02.327075 Write leveling (Byte 0): 36 => 36
7648 20:01:02.330522 Write leveling (Byte 1): 27 => 27
7649 20:01:02.331082 DramcWriteLeveling(PI) end<-----
7650 20:01:02.334424
7651 20:01:02.334982 ==
7652 20:01:02.337391 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 20:01:02.340284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 20:01:02.340750 ==
7655 20:01:02.343950 [Gating] SW mode calibration
7656 20:01:02.350166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7657 20:01:02.356871 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7658 20:01:02.360286 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 20:01:02.363637 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 20:01:02.366487 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 20:01:02.372904 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7662 20:01:02.376664 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7663 20:01:02.379920 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7664 20:01:02.386187 1 4 24 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
7665 20:01:02.390118 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7666 20:01:02.396347 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7667 20:01:02.399291 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7668 20:01:02.402592 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7669 20:01:02.409374 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7670 20:01:02.412395 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7671 20:01:02.415401 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7672 20:01:02.422534 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7673 20:01:02.425601 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 20:01:02.428547 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7675 20:01:02.435205 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7676 20:01:02.439158 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7677 20:01:02.442459 1 6 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7678 20:01:02.448608 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7679 20:01:02.451557 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7680 20:01:02.454712 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7681 20:01:02.461521 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7682 20:01:02.464758 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7683 20:01:02.468296 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7684 20:01:02.475339 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7685 20:01:02.478592 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7686 20:01:02.481192 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7687 20:01:02.487936 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7688 20:01:02.491227 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 20:01:02.494774 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 20:01:02.500747 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 20:01:02.504468 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 20:01:02.507490 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 20:01:02.514243 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 20:01:02.517018 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 20:01:02.520322 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 20:01:02.527569 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 20:01:02.530557 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 20:01:02.533923 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 20:01:02.540339 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 20:01:02.543473 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7701 20:01:02.546999 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7702 20:01:02.553949 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7703 20:01:02.557073 Total UI for P1: 0, mck2ui 16
7704 20:01:02.560959 best dqsien dly found for B0: ( 1, 9, 10)
7705 20:01:02.563547 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7706 20:01:02.567433 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7707 20:01:02.573890 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7708 20:01:02.577112 Total UI for P1: 0, mck2ui 16
7709 20:01:02.580429 best dqsien dly found for B1: ( 1, 9, 22)
7710 20:01:02.584274 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7711 20:01:02.587226 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7712 20:01:02.587839
7713 20:01:02.590046 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7714 20:01:02.593100 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7715 20:01:02.596622 [Gating] SW calibration Done
7716 20:01:02.597190 ==
7717 20:01:02.599605 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 20:01:02.602896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 20:01:02.603378 ==
7720 20:01:02.606299 RX Vref Scan: 0
7721 20:01:02.606865
7722 20:01:02.609591 RX Vref 0 -> 0, step: 1
7723 20:01:02.610160
7724 20:01:02.610654 RX Delay 0 -> 252, step: 8
7725 20:01:02.616195 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7726 20:01:02.619901 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7727 20:01:02.623538 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7728 20:01:02.626207 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7729 20:01:02.630051 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7730 20:01:02.636020 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
7731 20:01:02.639518 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7732 20:01:02.642430 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7733 20:01:02.645892 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7734 20:01:02.649190 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7735 20:01:02.655952 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7736 20:01:02.659425 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7737 20:01:02.662301 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7738 20:01:02.665987 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7739 20:01:02.672394 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7740 20:01:02.675795 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7741 20:01:02.676259 ==
7742 20:01:02.678968 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 20:01:02.682037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 20:01:02.682502 ==
7745 20:01:02.682872 DQS Delay:
7746 20:01:02.685239 DQS0 = 0, DQS1 = 0
7747 20:01:02.685694 DQM Delay:
7748 20:01:02.688852 DQM0 = 134, DQM1 = 126
7749 20:01:02.689310 DQ Delay:
7750 20:01:02.692048 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7751 20:01:02.695877 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
7752 20:01:02.698819 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7753 20:01:02.705710 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7754 20:01:02.706228
7755 20:01:02.706561
7756 20:01:02.706865 ==
7757 20:01:02.708978 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 20:01:02.712100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 20:01:02.712517 ==
7760 20:01:02.712848
7761 20:01:02.713300
7762 20:01:02.715558 TX Vref Scan disable
7763 20:01:02.716009 == TX Byte 0 ==
7764 20:01:02.722234 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7765 20:01:02.725143 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7766 20:01:02.725657 == TX Byte 1 ==
7767 20:01:02.732128 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7768 20:01:02.735329 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7769 20:01:02.735893 ==
7770 20:01:02.738506 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 20:01:02.741588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 20:01:02.742011 ==
7773 20:01:02.756495
7774 20:01:02.759901 TX Vref early break, caculate TX vref
7775 20:01:02.763294 TX Vref=16, minBit 4, minWin=22, winSum=367
7776 20:01:02.766518 TX Vref=18, minBit 0, minWin=23, winSum=380
7777 20:01:02.769632 TX Vref=20, minBit 1, minWin=23, winSum=393
7778 20:01:02.772928 TX Vref=22, minBit 1, minWin=24, winSum=398
7779 20:01:02.776153 TX Vref=24, minBit 0, minWin=24, winSum=404
7780 20:01:02.782734 TX Vref=26, minBit 2, minWin=25, winSum=414
7781 20:01:02.786485 TX Vref=28, minBit 0, minWin=25, winSum=418
7782 20:01:02.789672 TX Vref=30, minBit 0, minWin=24, winSum=412
7783 20:01:02.792311 TX Vref=32, minBit 0, minWin=24, winSum=399
7784 20:01:02.796446 TX Vref=34, minBit 4, minWin=23, winSum=391
7785 20:01:02.802219 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
7786 20:01:02.802792
7787 20:01:02.805686 Final TX Range 0 Vref 28
7788 20:01:02.806150
7789 20:01:02.806513 ==
7790 20:01:02.808651 Dram Type= 6, Freq= 0, CH_0, rank 0
7791 20:01:02.812329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7792 20:01:02.812791 ==
7793 20:01:02.813153
7794 20:01:02.813488
7795 20:01:02.815438 TX Vref Scan disable
7796 20:01:02.822193 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7797 20:01:02.822604 == TX Byte 0 ==
7798 20:01:02.825560 u2DelayCellOfst[0]=14 cells (4 PI)
7799 20:01:02.828686 u2DelayCellOfst[1]=18 cells (5 PI)
7800 20:01:02.832223 u2DelayCellOfst[2]=14 cells (4 PI)
7801 20:01:02.835713 u2DelayCellOfst[3]=14 cells (4 PI)
7802 20:01:02.838432 u2DelayCellOfst[4]=11 cells (3 PI)
7803 20:01:02.842050 u2DelayCellOfst[5]=0 cells (0 PI)
7804 20:01:02.845160 u2DelayCellOfst[6]=18 cells (5 PI)
7805 20:01:02.848229 u2DelayCellOfst[7]=22 cells (6 PI)
7806 20:01:02.852203 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7807 20:01:02.854886 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7808 20:01:02.858685 == TX Byte 1 ==
7809 20:01:02.862559 u2DelayCellOfst[8]=0 cells (0 PI)
7810 20:01:02.865208 u2DelayCellOfst[9]=0 cells (0 PI)
7811 20:01:02.868196 u2DelayCellOfst[10]=3 cells (1 PI)
7812 20:01:02.871715 u2DelayCellOfst[11]=0 cells (0 PI)
7813 20:01:02.874768 u2DelayCellOfst[12]=11 cells (3 PI)
7814 20:01:02.878076 u2DelayCellOfst[13]=11 cells (3 PI)
7815 20:01:02.881644 u2DelayCellOfst[14]=14 cells (4 PI)
7816 20:01:02.882160 u2DelayCellOfst[15]=11 cells (3 PI)
7817 20:01:02.888653 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7818 20:01:02.891326 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7819 20:01:02.894525 DramC Write-DBI on
7820 20:01:02.895038 ==
7821 20:01:02.897896 Dram Type= 6, Freq= 0, CH_0, rank 0
7822 20:01:02.900925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7823 20:01:02.901442 ==
7824 20:01:02.901777
7825 20:01:02.902082
7826 20:01:02.904312 TX Vref Scan disable
7827 20:01:02.907343 == TX Byte 0 ==
7828 20:01:02.911165 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7829 20:01:02.911680 == TX Byte 1 ==
7830 20:01:02.917388 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7831 20:01:02.917861 DramC Write-DBI off
7832 20:01:02.918190
7833 20:01:02.918499 [DATLAT]
7834 20:01:02.921477 Freq=1600, CH0 RK0
7835 20:01:02.921988
7836 20:01:02.924341 DATLAT Default: 0xf
7837 20:01:02.924862 0, 0xFFFF, sum = 0
7838 20:01:02.927451 1, 0xFFFF, sum = 0
7839 20:01:02.928092 2, 0xFFFF, sum = 0
7840 20:01:02.930371 3, 0xFFFF, sum = 0
7841 20:01:02.930790 4, 0xFFFF, sum = 0
7842 20:01:02.934262 5, 0xFFFF, sum = 0
7843 20:01:02.934781 6, 0xFFFF, sum = 0
7844 20:01:02.936979 7, 0xFFFF, sum = 0
7845 20:01:02.937395 8, 0xFFFF, sum = 0
7846 20:01:02.940746 9, 0xFFFF, sum = 0
7847 20:01:02.941294 10, 0xFFFF, sum = 0
7848 20:01:02.943464 11, 0xFFFF, sum = 0
7849 20:01:02.943924 12, 0xFFFF, sum = 0
7850 20:01:02.947169 13, 0xFFFF, sum = 0
7851 20:01:02.947688 14, 0x0, sum = 1
7852 20:01:02.950222 15, 0x0, sum = 2
7853 20:01:02.950738 16, 0x0, sum = 3
7854 20:01:02.953716 17, 0x0, sum = 4
7855 20:01:02.954233 best_step = 15
7856 20:01:02.954562
7857 20:01:02.954867 ==
7858 20:01:02.956629 Dram Type= 6, Freq= 0, CH_0, rank 0
7859 20:01:02.963976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7860 20:01:02.964631 ==
7861 20:01:02.965092 RX Vref Scan: 1
7862 20:01:02.965421
7863 20:01:02.967881 Set Vref Range= 24 -> 127
7864 20:01:02.968296
7865 20:01:02.970517 RX Vref 24 -> 127, step: 1
7866 20:01:02.971026
7867 20:01:02.973489 RX Delay 11 -> 252, step: 4
7868 20:01:02.974004
7869 20:01:02.976683 Set Vref, RX VrefLevel [Byte0]: 24
7870 20:01:02.980194 [Byte1]: 24
7871 20:01:02.980704
7872 20:01:02.983451 Set Vref, RX VrefLevel [Byte0]: 25
7873 20:01:02.987046 [Byte1]: 25
7874 20:01:02.987557
7875 20:01:02.989669 Set Vref, RX VrefLevel [Byte0]: 26
7876 20:01:02.993101 [Byte1]: 26
7877 20:01:02.996591
7878 20:01:02.997103 Set Vref, RX VrefLevel [Byte0]: 27
7879 20:01:02.999692 [Byte1]: 27
7880 20:01:03.004424
7881 20:01:03.004861 Set Vref, RX VrefLevel [Byte0]: 28
7882 20:01:03.007778 [Byte1]: 28
7883 20:01:03.011921
7884 20:01:03.012432 Set Vref, RX VrefLevel [Byte0]: 29
7885 20:01:03.014908 [Byte1]: 29
7886 20:01:03.019172
7887 20:01:03.019601 Set Vref, RX VrefLevel [Byte0]: 30
7888 20:01:03.023125 [Byte1]: 30
7889 20:01:03.026876
7890 20:01:03.027383 Set Vref, RX VrefLevel [Byte0]: 31
7891 20:01:03.030267 [Byte1]: 31
7892 20:01:03.034368
7893 20:01:03.034873 Set Vref, RX VrefLevel [Byte0]: 32
7894 20:01:03.037984 [Byte1]: 32
7895 20:01:03.042471
7896 20:01:03.042975 Set Vref, RX VrefLevel [Byte0]: 33
7897 20:01:03.045487 [Byte1]: 33
7898 20:01:03.050028
7899 20:01:03.050530 Set Vref, RX VrefLevel [Byte0]: 34
7900 20:01:03.053003 [Byte1]: 34
7901 20:01:03.057645
7902 20:01:03.058146 Set Vref, RX VrefLevel [Byte0]: 35
7903 20:01:03.060659 [Byte1]: 35
7904 20:01:03.064882
7905 20:01:03.065390 Set Vref, RX VrefLevel [Byte0]: 36
7906 20:01:03.068100 [Byte1]: 36
7907 20:01:03.072463
7908 20:01:03.073013 Set Vref, RX VrefLevel [Byte0]: 37
7909 20:01:03.076267 [Byte1]: 37
7910 20:01:03.080218
7911 20:01:03.080724 Set Vref, RX VrefLevel [Byte0]: 38
7912 20:01:03.083254 [Byte1]: 38
7913 20:01:03.087826
7914 20:01:03.088352 Set Vref, RX VrefLevel [Byte0]: 39
7915 20:01:03.091053 [Byte1]: 39
7916 20:01:03.095821
7917 20:01:03.096325 Set Vref, RX VrefLevel [Byte0]: 40
7918 20:01:03.098494 [Byte1]: 40
7919 20:01:03.102866
7920 20:01:03.103379 Set Vref, RX VrefLevel [Byte0]: 41
7921 20:01:03.106539 [Byte1]: 41
7922 20:01:03.110930
7923 20:01:03.111461 Set Vref, RX VrefLevel [Byte0]: 42
7924 20:01:03.113995 [Byte1]: 42
7925 20:01:03.118242
7926 20:01:03.118650 Set Vref, RX VrefLevel [Byte0]: 43
7927 20:01:03.121560 [Byte1]: 43
7928 20:01:03.126249
7929 20:01:03.126659 Set Vref, RX VrefLevel [Byte0]: 44
7930 20:01:03.128972 [Byte1]: 44
7931 20:01:03.133354
7932 20:01:03.133874 Set Vref, RX VrefLevel [Byte0]: 45
7933 20:01:03.136975 [Byte1]: 45
7934 20:01:03.141543
7935 20:01:03.144048 Set Vref, RX VrefLevel [Byte0]: 46
7936 20:01:03.147712 [Byte1]: 46
7937 20:01:03.148273
7938 20:01:03.150933 Set Vref, RX VrefLevel [Byte0]: 47
7939 20:01:03.154196 [Byte1]: 47
7940 20:01:03.154713
7941 20:01:03.157641 Set Vref, RX VrefLevel [Byte0]: 48
7942 20:01:03.161307 [Byte1]: 48
7943 20:01:03.164090
7944 20:01:03.164507 Set Vref, RX VrefLevel [Byte0]: 49
7945 20:01:03.167360 [Byte1]: 49
7946 20:01:03.171288
7947 20:01:03.171697 Set Vref, RX VrefLevel [Byte0]: 50
7948 20:01:03.178236 [Byte1]: 50
7949 20:01:03.178756
7950 20:01:03.181287 Set Vref, RX VrefLevel [Byte0]: 51
7951 20:01:03.184376 [Byte1]: 51
7952 20:01:03.184788
7953 20:01:03.188591 Set Vref, RX VrefLevel [Byte0]: 52
7954 20:01:03.191759 [Byte1]: 52
7955 20:01:03.194871
7956 20:01:03.195376 Set Vref, RX VrefLevel [Byte0]: 53
7957 20:01:03.197838 [Byte1]: 53
7958 20:01:03.202232
7959 20:01:03.202872 Set Vref, RX VrefLevel [Byte0]: 54
7960 20:01:03.205405 [Byte1]: 54
7961 20:01:03.209543
7962 20:01:03.210051 Set Vref, RX VrefLevel [Byte0]: 55
7963 20:01:03.213004 [Byte1]: 55
7964 20:01:03.216848
7965 20:01:03.217283 Set Vref, RX VrefLevel [Byte0]: 56
7966 20:01:03.220337 [Byte1]: 56
7967 20:01:03.224633
7968 20:01:03.225049 Set Vref, RX VrefLevel [Byte0]: 57
7969 20:01:03.228202 [Byte1]: 57
7970 20:01:03.232580
7971 20:01:03.233114 Set Vref, RX VrefLevel [Byte0]: 58
7972 20:01:03.235709 [Byte1]: 58
7973 20:01:03.240694
7974 20:01:03.243950 Set Vref, RX VrefLevel [Byte0]: 59
7975 20:01:03.247078 [Byte1]: 59
7976 20:01:03.247625
7977 20:01:03.250287 Set Vref, RX VrefLevel [Byte0]: 60
7978 20:01:03.253111 [Byte1]: 60
7979 20:01:03.253730
7980 20:01:03.256400 Set Vref, RX VrefLevel [Byte0]: 61
7981 20:01:03.259897 [Byte1]: 61
7982 20:01:03.263003
7983 20:01:03.263555 Set Vref, RX VrefLevel [Byte0]: 62
7984 20:01:03.266337 [Byte1]: 62
7985 20:01:03.270881
7986 20:01:03.271434 Set Vref, RX VrefLevel [Byte0]: 63
7987 20:01:03.274315 [Byte1]: 63
7988 20:01:03.278558
7989 20:01:03.279108 Set Vref, RX VrefLevel [Byte0]: 64
7990 20:01:03.281763 [Byte1]: 64
7991 20:01:03.285718
7992 20:01:03.286213 Set Vref, RX VrefLevel [Byte0]: 65
7993 20:01:03.289170 [Byte1]: 65
7994 20:01:03.293374
7995 20:01:03.293929 Set Vref, RX VrefLevel [Byte0]: 66
7996 20:01:03.296490 [Byte1]: 66
7997 20:01:03.300977
7998 20:01:03.301541 Set Vref, RX VrefLevel [Byte0]: 67
7999 20:01:03.304271 [Byte1]: 67
8000 20:01:03.308623
8001 20:01:03.309174 Set Vref, RX VrefLevel [Byte0]: 68
8002 20:01:03.312312 [Byte1]: 68
8003 20:01:03.316146
8004 20:01:03.316606 Set Vref, RX VrefLevel [Byte0]: 69
8005 20:01:03.319279 [Byte1]: 69
8006 20:01:03.323914
8007 20:01:03.324468 Set Vref, RX VrefLevel [Byte0]: 70
8008 20:01:03.326945 [Byte1]: 70
8009 20:01:03.331254
8010 20:01:03.331706 Set Vref, RX VrefLevel [Byte0]: 71
8011 20:01:03.334486 [Byte1]: 71
8012 20:01:03.338945
8013 20:01:03.339536 Set Vref, RX VrefLevel [Byte0]: 72
8014 20:01:03.342222 [Byte1]: 72
8015 20:01:03.346714
8016 20:01:03.347221 Set Vref, RX VrefLevel [Byte0]: 73
8017 20:01:03.349987 [Byte1]: 73
8018 20:01:03.354780
8019 20:01:03.355292 Set Vref, RX VrefLevel [Byte0]: 74
8020 20:01:03.358028 [Byte1]: 74
8021 20:01:03.362923
8022 20:01:03.363431 Set Vref, RX VrefLevel [Byte0]: 75
8023 20:01:03.365561 [Byte1]: 75
8024 20:01:03.369589
8025 20:01:03.370098 Set Vref, RX VrefLevel [Byte0]: 76
8026 20:01:03.372666 [Byte1]: 76
8027 20:01:03.377105
8028 20:01:03.377614 Set Vref, RX VrefLevel [Byte0]: 77
8029 20:01:03.380096 [Byte1]: 77
8030 20:01:03.384521
8031 20:01:03.384934 Set Vref, RX VrefLevel [Byte0]: 78
8032 20:01:03.388082 [Byte1]: 78
8033 20:01:03.392735
8034 20:01:03.393243 Set Vref, RX VrefLevel [Byte0]: 79
8035 20:01:03.395706 [Byte1]: 79
8036 20:01:03.399883
8037 20:01:03.400390 Set Vref, RX VrefLevel [Byte0]: 80
8038 20:01:03.403320 [Byte1]: 80
8039 20:01:03.407472
8040 20:01:03.408138 Final RX Vref Byte 0 = 68 to rank0
8041 20:01:03.410860 Final RX Vref Byte 1 = 55 to rank0
8042 20:01:03.413762 Final RX Vref Byte 0 = 68 to rank1
8043 20:01:03.417292 Final RX Vref Byte 1 = 55 to rank1==
8044 20:01:03.420591 Dram Type= 6, Freq= 0, CH_0, rank 0
8045 20:01:03.427247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 20:01:03.427806 ==
8047 20:01:03.428150 DQS Delay:
8048 20:01:03.430533 DQS0 = 0, DQS1 = 0
8049 20:01:03.430972 DQM Delay:
8050 20:01:03.431307 DQM0 = 134, DQM1 = 122
8051 20:01:03.433427 DQ Delay:
8052 20:01:03.437312 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =132
8053 20:01:03.440569 DQ4 =136, DQ5 =122, DQ6 =140, DQ7 =142
8054 20:01:03.443339 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =116
8055 20:01:03.447195 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8056 20:01:03.447704
8057 20:01:03.448092
8058 20:01:03.448419
8059 20:01:03.450068 [DramC_TX_OE_Calibration] TA2
8060 20:01:03.453216 Original DQ_B0 (3 6) =30, OEN = 27
8061 20:01:03.456960 Original DQ_B1 (3 6) =30, OEN = 27
8062 20:01:03.460243 24, 0x0, End_B0=24 End_B1=24
8063 20:01:03.463457 25, 0x0, End_B0=25 End_B1=25
8064 20:01:03.464036 26, 0x0, End_B0=26 End_B1=26
8065 20:01:03.466548 27, 0x0, End_B0=27 End_B1=27
8066 20:01:03.469931 28, 0x0, End_B0=28 End_B1=28
8067 20:01:03.473639 29, 0x0, End_B0=29 End_B1=29
8068 20:01:03.476545 30, 0x0, End_B0=30 End_B1=30
8069 20:01:03.477055 31, 0x4141, End_B0=30 End_B1=30
8070 20:01:03.479878 Byte0 end_step=30 best_step=27
8071 20:01:03.484388 Byte1 end_step=30 best_step=27
8072 20:01:03.486447 Byte0 TX OE(2T, 0.5T) = (3, 3)
8073 20:01:03.490229 Byte1 TX OE(2T, 0.5T) = (3, 3)
8074 20:01:03.490738
8075 20:01:03.491066
8076 20:01:03.495839 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
8077 20:01:03.499335 CH0 RK0: MR19=303, MR18=1F10
8078 20:01:03.506142 CH0_RK0: MR19=0x303, MR18=0x1F10, DQSOSC=394, MR23=63, INC=23, DEC=15
8079 20:01:03.506654
8080 20:01:03.509460 ----->DramcWriteLeveling(PI) begin...
8081 20:01:03.510036 ==
8082 20:01:03.512840 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 20:01:03.516042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 20:01:03.516689 ==
8085 20:01:03.519062 Write leveling (Byte 0): 33 => 33
8086 20:01:03.522721 Write leveling (Byte 1): 27 => 27
8087 20:01:03.525628 DramcWriteLeveling(PI) end<-----
8088 20:01:03.526042
8089 20:01:03.526369 ==
8090 20:01:03.529035 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 20:01:03.535624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 20:01:03.536204 ==
8093 20:01:03.536549 [Gating] SW mode calibration
8094 20:01:03.545418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8095 20:01:03.548865 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8096 20:01:03.555893 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 20:01:03.559200 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 20:01:03.562468 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 20:01:03.568764 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8100 20:01:03.571841 1 4 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8101 20:01:03.575192 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
8102 20:01:03.582351 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8103 20:01:03.585611 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8104 20:01:03.588145 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8105 20:01:03.594997 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8106 20:01:03.598668 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8107 20:01:03.601311 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
8108 20:01:03.608425 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8109 20:01:03.611625 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8110 20:01:03.614926 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 20:01:03.621769 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 20:01:03.625100 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 20:01:03.627834 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 20:01:03.634477 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 20:01:03.637616 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8116 20:01:03.641471 1 6 16 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8117 20:01:03.647986 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8118 20:01:03.651853 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 20:01:03.654220 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 20:01:03.661236 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 20:01:03.664170 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 20:01:03.667979 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 20:01:03.674388 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8124 20:01:03.677617 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8125 20:01:03.680675 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8126 20:01:03.687221 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8127 20:01:03.690606 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 20:01:03.693805 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 20:01:03.700424 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 20:01:03.703710 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 20:01:03.707299 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 20:01:03.714342 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 20:01:03.717261 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 20:01:03.720364 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 20:01:03.726723 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 20:01:03.730017 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 20:01:03.733295 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 20:01:03.740513 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 20:01:03.743422 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8140 20:01:03.746598 Total UI for P1: 0, mck2ui 16
8141 20:01:03.750042 best dqsien dly found for B0: ( 1, 9, 10)
8142 20:01:03.753244 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8143 20:01:03.759647 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8144 20:01:03.760248 Total UI for P1: 0, mck2ui 16
8145 20:01:03.766292 best dqsien dly found for B1: ( 1, 9, 14)
8146 20:01:03.769320 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8147 20:01:03.773130 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8148 20:01:03.773686
8149 20:01:03.775953 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8150 20:01:03.779975 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8151 20:01:03.782831 [Gating] SW calibration Done
8152 20:01:03.783285 ==
8153 20:01:03.786354 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 20:01:03.789170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 20:01:03.789632 ==
8156 20:01:03.792695 RX Vref Scan: 0
8157 20:01:03.793268
8158 20:01:03.793640 RX Vref 0 -> 0, step: 1
8159 20:01:03.793987
8160 20:01:03.796652 RX Delay 0 -> 252, step: 8
8161 20:01:03.798968 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8162 20:01:03.805481 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8163 20:01:03.809120 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8164 20:01:03.812674 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8165 20:01:03.816529 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8166 20:01:03.819068 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8167 20:01:03.825787 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8168 20:01:03.829283 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8169 20:01:03.832119 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8170 20:01:03.836174 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8171 20:01:03.842832 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8172 20:01:03.845667 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8173 20:01:03.848668 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8174 20:01:03.851941 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8175 20:01:03.855291 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8176 20:01:03.862181 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8177 20:01:03.862931 ==
8178 20:01:03.865297 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 20:01:03.868503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 20:01:03.869065 ==
8181 20:01:03.869439 DQS Delay:
8182 20:01:03.872008 DQS0 = 0, DQS1 = 0
8183 20:01:03.872560 DQM Delay:
8184 20:01:03.875406 DQM0 = 133, DQM1 = 127
8185 20:01:03.875997 DQ Delay:
8186 20:01:03.878277 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =127
8187 20:01:03.881705 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8188 20:01:03.884545 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8189 20:01:03.891844 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8190 20:01:03.892394
8191 20:01:03.892763
8192 20:01:03.893099 ==
8193 20:01:03.895419 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 20:01:03.897978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 20:01:03.898439 ==
8196 20:01:03.898801
8197 20:01:03.899136
8198 20:01:03.901909 TX Vref Scan disable
8199 20:01:03.902459 == TX Byte 0 ==
8200 20:01:03.908339 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8201 20:01:03.911321 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8202 20:01:03.912055 == TX Byte 1 ==
8203 20:01:03.917742 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8204 20:01:03.920872 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8205 20:01:03.921331 ==
8206 20:01:03.924621 Dram Type= 6, Freq= 0, CH_0, rank 1
8207 20:01:03.927523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8208 20:01:03.928128 ==
8209 20:01:03.942513
8210 20:01:03.945113 TX Vref early break, caculate TX vref
8211 20:01:03.949072 TX Vref=16, minBit 1, minWin=22, winSum=378
8212 20:01:03.952326 TX Vref=18, minBit 0, minWin=23, winSum=383
8213 20:01:03.955249 TX Vref=20, minBit 0, minWin=24, winSum=395
8214 20:01:03.958495 TX Vref=22, minBit 0, minWin=24, winSum=402
8215 20:01:03.962289 TX Vref=24, minBit 1, minWin=25, winSum=411
8216 20:01:03.968229 TX Vref=26, minBit 1, minWin=24, winSum=411
8217 20:01:03.971775 TX Vref=28, minBit 0, minWin=25, winSum=409
8218 20:01:03.975132 TX Vref=30, minBit 2, minWin=24, winSum=403
8219 20:01:03.978165 TX Vref=32, minBit 0, minWin=24, winSum=397
8220 20:01:03.981732 TX Vref=34, minBit 1, minWin=23, winSum=386
8221 20:01:03.988035 [TxChooseVref] Worse bit 1, Min win 25, Win sum 411, Final Vref 24
8222 20:01:03.988575
8223 20:01:03.991864 Final TX Range 0 Vref 24
8224 20:01:03.992421
8225 20:01:03.992783 ==
8226 20:01:03.994897 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 20:01:03.998507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 20:01:03.999062 ==
8229 20:01:03.999427
8230 20:01:03.999801
8231 20:01:04.001021 TX Vref Scan disable
8232 20:01:04.008094 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8233 20:01:04.008672 == TX Byte 0 ==
8234 20:01:04.011640 u2DelayCellOfst[0]=14 cells (4 PI)
8235 20:01:04.014465 u2DelayCellOfst[1]=18 cells (5 PI)
8236 20:01:04.018055 u2DelayCellOfst[2]=14 cells (4 PI)
8237 20:01:04.020938 u2DelayCellOfst[3]=18 cells (5 PI)
8238 20:01:04.024369 u2DelayCellOfst[4]=11 cells (3 PI)
8239 20:01:04.027931 u2DelayCellOfst[5]=0 cells (0 PI)
8240 20:01:04.031169 u2DelayCellOfst[6]=22 cells (6 PI)
8241 20:01:04.034536 u2DelayCellOfst[7]=22 cells (6 PI)
8242 20:01:04.037475 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8243 20:01:04.041458 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8244 20:01:04.044652 == TX Byte 1 ==
8245 20:01:04.047681 u2DelayCellOfst[8]=0 cells (0 PI)
8246 20:01:04.051079 u2DelayCellOfst[9]=0 cells (0 PI)
8247 20:01:04.054130 u2DelayCellOfst[10]=7 cells (2 PI)
8248 20:01:04.057149 u2DelayCellOfst[11]=3 cells (1 PI)
8249 20:01:04.060617 u2DelayCellOfst[12]=11 cells (3 PI)
8250 20:01:04.061169 u2DelayCellOfst[13]=11 cells (3 PI)
8251 20:01:04.064173 u2DelayCellOfst[14]=14 cells (4 PI)
8252 20:01:04.067298 u2DelayCellOfst[15]=11 cells (3 PI)
8253 20:01:04.074022 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8254 20:01:04.076975 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8255 20:01:04.080338 DramC Write-DBI on
8256 20:01:04.080895 ==
8257 20:01:04.083660 Dram Type= 6, Freq= 0, CH_0, rank 1
8258 20:01:04.086914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 20:01:04.087455 ==
8260 20:01:04.087866
8261 20:01:04.088210
8262 20:01:04.090420 TX Vref Scan disable
8263 20:01:04.090974 == TX Byte 0 ==
8264 20:01:04.096586 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8265 20:01:04.097144 == TX Byte 1 ==
8266 20:01:04.100068 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8267 20:01:04.103382 DramC Write-DBI off
8268 20:01:04.103971
8269 20:01:04.104340 [DATLAT]
8270 20:01:04.106995 Freq=1600, CH0 RK1
8271 20:01:04.107550
8272 20:01:04.107983 DATLAT Default: 0xf
8273 20:01:04.109944 0, 0xFFFF, sum = 0
8274 20:01:04.110513 1, 0xFFFF, sum = 0
8275 20:01:04.113315 2, 0xFFFF, sum = 0
8276 20:01:04.116797 3, 0xFFFF, sum = 0
8277 20:01:04.117361 4, 0xFFFF, sum = 0
8278 20:01:04.119934 5, 0xFFFF, sum = 0
8279 20:01:04.120545 6, 0xFFFF, sum = 0
8280 20:01:04.123807 7, 0xFFFF, sum = 0
8281 20:01:04.124279 8, 0xFFFF, sum = 0
8282 20:01:04.126552 9, 0xFFFF, sum = 0
8283 20:01:04.127122 10, 0xFFFF, sum = 0
8284 20:01:04.129734 11, 0xFFFF, sum = 0
8285 20:01:04.130306 12, 0xFFFF, sum = 0
8286 20:01:04.133331 13, 0xFFFF, sum = 0
8287 20:01:04.133905 14, 0x0, sum = 1
8288 20:01:04.137069 15, 0x0, sum = 2
8289 20:01:04.137543 16, 0x0, sum = 3
8290 20:01:04.139780 17, 0x0, sum = 4
8291 20:01:04.140253 best_step = 15
8292 20:01:04.140622
8293 20:01:04.140962 ==
8294 20:01:04.142847 Dram Type= 6, Freq= 0, CH_0, rank 1
8295 20:01:04.146207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 20:01:04.150420 ==
8297 20:01:04.150983 RX Vref Scan: 0
8298 20:01:04.151353
8299 20:01:04.153476 RX Vref 0 -> 0, step: 1
8300 20:01:04.154042
8301 20:01:04.156604 RX Delay 11 -> 252, step: 4
8302 20:01:04.159889 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8303 20:01:04.162997 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8304 20:01:04.166030 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8305 20:01:04.172711 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8306 20:01:04.176139 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8307 20:01:04.179868 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8308 20:01:04.182555 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8309 20:01:04.185779 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8310 20:01:04.192616 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8311 20:01:04.195959 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8312 20:01:04.199775 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8313 20:01:04.202394 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8314 20:01:04.208846 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8315 20:01:04.212650 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8316 20:01:04.215372 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8317 20:01:04.218905 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8318 20:01:04.219452 ==
8319 20:01:04.221870 Dram Type= 6, Freq= 0, CH_0, rank 1
8320 20:01:04.228526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 20:01:04.229093 ==
8322 20:01:04.229462 DQS Delay:
8323 20:01:04.229801 DQS0 = 0, DQS1 = 0
8324 20:01:04.232320 DQM Delay:
8325 20:01:04.232874 DQM0 = 129, DQM1 = 125
8326 20:01:04.235358 DQ Delay:
8327 20:01:04.238791 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =126
8328 20:01:04.242157 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =140
8329 20:01:04.245065 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =120
8330 20:01:04.249052 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8331 20:01:04.249613
8332 20:01:04.250136
8333 20:01:04.250647
8334 20:01:04.251930 [DramC_TX_OE_Calibration] TA2
8335 20:01:04.255574 Original DQ_B0 (3 6) =30, OEN = 27
8336 20:01:04.258995 Original DQ_B1 (3 6) =30, OEN = 27
8337 20:01:04.262266 24, 0x0, End_B0=24 End_B1=24
8338 20:01:04.262834 25, 0x0, End_B0=25 End_B1=25
8339 20:01:04.265587 26, 0x0, End_B0=26 End_B1=26
8340 20:01:04.268885 27, 0x0, End_B0=27 End_B1=27
8341 20:01:04.272159 28, 0x0, End_B0=28 End_B1=28
8342 20:01:04.275078 29, 0x0, End_B0=29 End_B1=29
8343 20:01:04.275645 30, 0x0, End_B0=30 End_B1=30
8344 20:01:04.278318 31, 0x4141, End_B0=30 End_B1=30
8345 20:01:04.282046 Byte0 end_step=30 best_step=27
8346 20:01:04.285407 Byte1 end_step=30 best_step=27
8347 20:01:04.288049 Byte0 TX OE(2T, 0.5T) = (3, 3)
8348 20:01:04.291623 Byte1 TX OE(2T, 0.5T) = (3, 3)
8349 20:01:04.292210
8350 20:01:04.292578
8351 20:01:04.298013 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8352 20:01:04.301704 CH0 RK1: MR19=303, MR18=2104
8353 20:01:04.308310 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8354 20:01:04.311084 [RxdqsGatingPostProcess] freq 1600
8355 20:01:04.315056 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8356 20:01:04.317777 best DQS0 dly(2T, 0.5T) = (1, 1)
8357 20:01:04.321097 best DQS1 dly(2T, 0.5T) = (1, 1)
8358 20:01:04.324207 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8359 20:01:04.327469 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8360 20:01:04.330726 best DQS0 dly(2T, 0.5T) = (1, 1)
8361 20:01:04.334174 best DQS1 dly(2T, 0.5T) = (1, 1)
8362 20:01:04.337435 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8363 20:01:04.340917 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8364 20:01:04.344021 Pre-setting of DQS Precalculation
8365 20:01:04.347951 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8366 20:01:04.348368 ==
8367 20:01:04.350633 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 20:01:04.358798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 20:01:04.359316 ==
8370 20:01:04.360753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8371 20:01:04.367508 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8372 20:01:04.370762 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8373 20:01:04.377547 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8374 20:01:04.385153 [CA 0] Center 41 (12~71) winsize 60
8375 20:01:04.388221 [CA 1] Center 42 (12~72) winsize 61
8376 20:01:04.391823 [CA 2] Center 37 (8~66) winsize 59
8377 20:01:04.394543 [CA 3] Center 36 (7~65) winsize 59
8378 20:01:04.397941 [CA 4] Center 36 (7~66) winsize 60
8379 20:01:04.401564 [CA 5] Center 36 (7~66) winsize 60
8380 20:01:04.402125
8381 20:01:04.405135 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8382 20:01:04.405696
8383 20:01:04.411278 [CATrainingPosCal] consider 1 rank data
8384 20:01:04.411884 u2DelayCellTimex100 = 262/100 ps
8385 20:01:04.418136 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8386 20:01:04.421045 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8387 20:01:04.424141 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8388 20:01:04.427424 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8389 20:01:04.430748 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8390 20:01:04.434573 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8391 20:01:04.435131
8392 20:01:04.437498 CA PerBit enable=1, Macro0, CA PI delay=36
8393 20:01:04.437956
8394 20:01:04.440901 [CBTSetCACLKResult] CA Dly = 36
8395 20:01:04.443908 CS Dly: 10 (0~41)
8396 20:01:04.447054 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8397 20:01:04.450726 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8398 20:01:04.451295 ==
8399 20:01:04.454023 Dram Type= 6, Freq= 0, CH_1, rank 1
8400 20:01:04.460751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 20:01:04.461313 ==
8402 20:01:04.463594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8403 20:01:04.470438 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8404 20:01:04.473619 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8405 20:01:04.480426 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8406 20:01:04.488205 [CA 0] Center 42 (13~72) winsize 60
8407 20:01:04.491425 [CA 1] Center 42 (13~72) winsize 60
8408 20:01:04.494430 [CA 2] Center 37 (8~67) winsize 60
8409 20:01:04.498702 [CA 3] Center 37 (8~67) winsize 60
8410 20:01:04.501425 [CA 4] Center 37 (8~67) winsize 60
8411 20:01:04.504637 [CA 5] Center 36 (7~66) winsize 60
8412 20:01:04.505195
8413 20:01:04.507761 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8414 20:01:04.508317
8415 20:01:04.515175 [CATrainingPosCal] consider 2 rank data
8416 20:01:04.515791 u2DelayCellTimex100 = 262/100 ps
8417 20:01:04.520655 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8418 20:01:04.524267 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8419 20:01:04.527445 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8420 20:01:04.531439 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8421 20:01:04.534256 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8422 20:01:04.537548 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8423 20:01:04.538110
8424 20:01:04.540683 CA PerBit enable=1, Macro0, CA PI delay=36
8425 20:01:04.541242
8426 20:01:04.544433 [CBTSetCACLKResult] CA Dly = 36
8427 20:01:04.546979 CS Dly: 11 (0~43)
8428 20:01:04.550523 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8429 20:01:04.553901 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8430 20:01:04.554459
8431 20:01:04.557112 ----->DramcWriteLeveling(PI) begin...
8432 20:01:04.557673 ==
8433 20:01:04.560287 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 20:01:04.567826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 20:01:04.568454 ==
8436 20:01:04.570143 Write leveling (Byte 0): 23 => 23
8437 20:01:04.573478 Write leveling (Byte 1): 25 => 25
8438 20:01:04.576889 DramcWriteLeveling(PI) end<-----
8439 20:01:04.577443
8440 20:01:04.577805 ==
8441 20:01:04.580135 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 20:01:04.583503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 20:01:04.584107 ==
8444 20:01:04.586823 [Gating] SW mode calibration
8445 20:01:04.593416 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8446 20:01:04.600126 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8447 20:01:04.603264 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 20:01:04.606896 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 20:01:04.612780 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8450 20:01:04.616397 1 4 12 | B1->B0 | 2928 2f2f | 1 0 | (1 1) (0 0)
8451 20:01:04.619784 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8452 20:01:04.626288 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 20:01:04.629906 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 20:01:04.633532 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8455 20:01:04.639352 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8456 20:01:04.642932 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8457 20:01:04.646392 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8458 20:01:04.652431 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (1 0)
8459 20:01:04.656280 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8460 20:01:04.659055 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 20:01:04.665715 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 20:01:04.668894 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 20:01:04.672043 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 20:01:04.678602 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 20:01:04.682122 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 20:01:04.685251 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8467 20:01:04.691639 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 20:01:04.695187 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 20:01:04.698538 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 20:01:04.705137 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 20:01:04.708196 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 20:01:04.711945 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 20:01:04.718985 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8474 20:01:04.721314 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8475 20:01:04.725135 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8476 20:01:04.731705 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 20:01:04.735375 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 20:01:04.738892 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 20:01:04.745124 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 20:01:04.748089 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 20:01:04.751745 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 20:01:04.758211 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 20:01:04.761856 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 20:01:04.764657 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 20:01:04.770826 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 20:01:04.774847 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 20:01:04.778455 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 20:01:04.784015 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 20:01:04.787805 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8490 20:01:04.791324 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8491 20:01:04.797900 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 20:01:04.798454 Total UI for P1: 0, mck2ui 16
8493 20:01:04.803987 best dqsien dly found for B0: ( 1, 9, 10)
8494 20:01:04.804547 Total UI for P1: 0, mck2ui 16
8495 20:01:04.807617 best dqsien dly found for B1: ( 1, 9, 12)
8496 20:01:04.814252 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8497 20:01:04.817454 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8498 20:01:04.817914
8499 20:01:04.820537 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8500 20:01:04.824249 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8501 20:01:04.827661 [Gating] SW calibration Done
8502 20:01:04.828174 ==
8503 20:01:04.830424 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 20:01:04.833568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 20:01:04.834046 ==
8506 20:01:04.836862 RX Vref Scan: 0
8507 20:01:04.837332
8508 20:01:04.837812 RX Vref 0 -> 0, step: 1
8509 20:01:04.838269
8510 20:01:04.840314 RX Delay 0 -> 252, step: 8
8511 20:01:04.843921 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8512 20:01:04.850539 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8513 20:01:04.854360 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8514 20:01:04.856405 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8515 20:01:04.860316 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8516 20:01:04.864627 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8517 20:01:04.870502 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8518 20:01:04.873537 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8519 20:01:04.876793 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8520 20:01:04.880393 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8521 20:01:04.883305 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8522 20:01:04.889985 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8523 20:01:04.893429 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8524 20:01:04.896379 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8525 20:01:04.899946 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8526 20:01:04.906447 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8527 20:01:04.906998 ==
8528 20:01:04.909818 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 20:01:04.912910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 20:01:04.913470 ==
8531 20:01:04.913840 DQS Delay:
8532 20:01:04.916393 DQS0 = 0, DQS1 = 0
8533 20:01:04.916948 DQM Delay:
8534 20:01:04.919583 DQM0 = 137, DQM1 = 128
8535 20:01:04.920173 DQ Delay:
8536 20:01:04.922483 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8537 20:01:04.925836 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8538 20:01:04.929068 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
8539 20:01:04.935884 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8540 20:01:04.936447
8541 20:01:04.936819
8542 20:01:04.937157 ==
8543 20:01:04.939767 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 20:01:04.942604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 20:01:04.943165 ==
8546 20:01:04.943536
8547 20:01:04.943967
8548 20:01:04.945656 TX Vref Scan disable
8549 20:01:04.946129 == TX Byte 0 ==
8550 20:01:04.953085 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8551 20:01:04.955779 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8552 20:01:04.956364 == TX Byte 1 ==
8553 20:01:04.962731 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8554 20:01:04.965485 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8555 20:01:04.966060 ==
8556 20:01:04.968803 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 20:01:04.971780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 20:01:04.972261 ==
8559 20:01:04.986305
8560 20:01:04.988470 TX Vref early break, caculate TX vref
8561 20:01:04.992441 TX Vref=16, minBit 5, minWin=21, winSum=374
8562 20:01:04.995643 TX Vref=18, minBit 5, minWin=21, winSum=381
8563 20:01:04.999071 TX Vref=20, minBit 5, minWin=22, winSum=391
8564 20:01:05.002331 TX Vref=22, minBit 6, minWin=23, winSum=402
8565 20:01:05.005569 TX Vref=24, minBit 5, minWin=23, winSum=411
8566 20:01:05.012281 TX Vref=26, minBit 0, minWin=24, winSum=418
8567 20:01:05.015706 TX Vref=28, minBit 0, minWin=24, winSum=418
8568 20:01:05.019039 TX Vref=30, minBit 5, minWin=23, winSum=408
8569 20:01:05.022236 TX Vref=32, minBit 5, minWin=22, winSum=402
8570 20:01:05.025439 TX Vref=34, minBit 0, minWin=23, winSum=393
8571 20:01:05.032240 [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 26
8572 20:01:05.032972
8573 20:01:05.035428 Final TX Range 0 Vref 26
8574 20:01:05.035922
8575 20:01:05.036287 ==
8576 20:01:05.038353 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 20:01:05.041985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 20:01:05.042543 ==
8579 20:01:05.042908
8580 20:01:05.043246
8581 20:01:05.044933 TX Vref Scan disable
8582 20:01:05.052086 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8583 20:01:05.052640 == TX Byte 0 ==
8584 20:01:05.055085 u2DelayCellOfst[0]=18 cells (5 PI)
8585 20:01:05.058274 u2DelayCellOfst[1]=14 cells (4 PI)
8586 20:01:05.061650 u2DelayCellOfst[2]=0 cells (0 PI)
8587 20:01:05.064814 u2DelayCellOfst[3]=7 cells (2 PI)
8588 20:01:05.068455 u2DelayCellOfst[4]=11 cells (3 PI)
8589 20:01:05.072061 u2DelayCellOfst[5]=22 cells (6 PI)
8590 20:01:05.075286 u2DelayCellOfst[6]=22 cells (6 PI)
8591 20:01:05.078436 u2DelayCellOfst[7]=7 cells (2 PI)
8592 20:01:05.081739 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8593 20:01:05.084588 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8594 20:01:05.088097 == TX Byte 1 ==
8595 20:01:05.091525 u2DelayCellOfst[8]=0 cells (0 PI)
8596 20:01:05.092125 u2DelayCellOfst[9]=3 cells (1 PI)
8597 20:01:05.094770 u2DelayCellOfst[10]=11 cells (3 PI)
8598 20:01:05.098506 u2DelayCellOfst[11]=7 cells (2 PI)
8599 20:01:05.101180 u2DelayCellOfst[12]=14 cells (4 PI)
8600 20:01:05.105458 u2DelayCellOfst[13]=18 cells (5 PI)
8601 20:01:05.108144 u2DelayCellOfst[14]=18 cells (5 PI)
8602 20:01:05.111492 u2DelayCellOfst[15]=18 cells (5 PI)
8603 20:01:05.117925 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8604 20:01:05.121840 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8605 20:01:05.122396 DramC Write-DBI on
8606 20:01:05.122763 ==
8607 20:01:05.124332 Dram Type= 6, Freq= 0, CH_1, rank 0
8608 20:01:05.131092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8609 20:01:05.131645 ==
8610 20:01:05.132069
8611 20:01:05.132410
8612 20:01:05.132732 TX Vref Scan disable
8613 20:01:05.134799 == TX Byte 0 ==
8614 20:01:05.138530 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8615 20:01:05.141770 == TX Byte 1 ==
8616 20:01:05.144847 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8617 20:01:05.148421 DramC Write-DBI off
8618 20:01:05.149030
8619 20:01:05.149400 [DATLAT]
8620 20:01:05.149739 Freq=1600, CH1 RK0
8621 20:01:05.150068
8622 20:01:05.151437 DATLAT Default: 0xf
8623 20:01:05.151936 0, 0xFFFF, sum = 0
8624 20:01:05.154806 1, 0xFFFF, sum = 0
8625 20:01:05.158543 2, 0xFFFF, sum = 0
8626 20:01:05.159098 3, 0xFFFF, sum = 0
8627 20:01:05.162067 4, 0xFFFF, sum = 0
8628 20:01:05.162630 5, 0xFFFF, sum = 0
8629 20:01:05.165082 6, 0xFFFF, sum = 0
8630 20:01:05.165642 7, 0xFFFF, sum = 0
8631 20:01:05.168332 8, 0xFFFF, sum = 0
8632 20:01:05.168894 9, 0xFFFF, sum = 0
8633 20:01:05.172160 10, 0xFFFF, sum = 0
8634 20:01:05.172722 11, 0xFFFF, sum = 0
8635 20:01:05.174450 12, 0xFFFF, sum = 0
8636 20:01:05.174929 13, 0xFFFF, sum = 0
8637 20:01:05.178087 14, 0x0, sum = 1
8638 20:01:05.178671 15, 0x0, sum = 2
8639 20:01:05.181085 16, 0x0, sum = 3
8640 20:01:05.181697 17, 0x0, sum = 4
8641 20:01:05.184712 best_step = 15
8642 20:01:05.185185
8643 20:01:05.185670 ==
8644 20:01:05.187680 Dram Type= 6, Freq= 0, CH_1, rank 0
8645 20:01:05.191455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8646 20:01:05.192079 ==
8647 20:01:05.194267 RX Vref Scan: 1
8648 20:01:05.194840
8649 20:01:05.195328 Set Vref Range= 24 -> 127
8650 20:01:05.195840
8651 20:01:05.198438 RX Vref 24 -> 127, step: 1
8652 20:01:05.199017
8653 20:01:05.201592 RX Delay 11 -> 252, step: 4
8654 20:01:05.202175
8655 20:01:05.204414 Set Vref, RX VrefLevel [Byte0]: 24
8656 20:01:05.207454 [Byte1]: 24
8657 20:01:05.208066
8658 20:01:05.210849 Set Vref, RX VrefLevel [Byte0]: 25
8659 20:01:05.214150 [Byte1]: 25
8660 20:01:05.218077
8661 20:01:05.218650 Set Vref, RX VrefLevel [Byte0]: 26
8662 20:01:05.224160 [Byte1]: 26
8663 20:01:05.224634
8664 20:01:05.227562 Set Vref, RX VrefLevel [Byte0]: 27
8665 20:01:05.230912 [Byte1]: 27
8666 20:01:05.231484
8667 20:01:05.234220 Set Vref, RX VrefLevel [Byte0]: 28
8668 20:01:05.237299 [Byte1]: 28
8669 20:01:05.240739
8670 20:01:05.241169 Set Vref, RX VrefLevel [Byte0]: 29
8671 20:01:05.243994 [Byte1]: 29
8672 20:01:05.248128
8673 20:01:05.248640 Set Vref, RX VrefLevel [Byte0]: 30
8674 20:01:05.252352 [Byte1]: 30
8675 20:01:05.256186
8676 20:01:05.256695 Set Vref, RX VrefLevel [Byte0]: 31
8677 20:01:05.259157 [Byte1]: 31
8678 20:01:05.263403
8679 20:01:05.263988 Set Vref, RX VrefLevel [Byte0]: 32
8680 20:01:05.266917 [Byte1]: 32
8681 20:01:05.271139
8682 20:01:05.271690 Set Vref, RX VrefLevel [Byte0]: 33
8683 20:01:05.274244 [Byte1]: 33
8684 20:01:05.278887
8685 20:01:05.279444 Set Vref, RX VrefLevel [Byte0]: 34
8686 20:01:05.281933 [Byte1]: 34
8687 20:01:05.286946
8688 20:01:05.287502 Set Vref, RX VrefLevel [Byte0]: 35
8689 20:01:05.289562 [Byte1]: 35
8690 20:01:05.293888
8691 20:01:05.294437 Set Vref, RX VrefLevel [Byte0]: 36
8692 20:01:05.297211 [Byte1]: 36
8693 20:01:05.301339
8694 20:01:05.301889 Set Vref, RX VrefLevel [Byte0]: 37
8695 20:01:05.304854 [Byte1]: 37
8696 20:01:05.309915
8697 20:01:05.310463 Set Vref, RX VrefLevel [Byte0]: 38
8698 20:01:05.312237 [Byte1]: 38
8699 20:01:05.316831
8700 20:01:05.317381 Set Vref, RX VrefLevel [Byte0]: 39
8701 20:01:05.320127 [Byte1]: 39
8702 20:01:05.324083
8703 20:01:05.324539 Set Vref, RX VrefLevel [Byte0]: 40
8704 20:01:05.327789 [Byte1]: 40
8705 20:01:05.331895
8706 20:01:05.332460 Set Vref, RX VrefLevel [Byte0]: 41
8707 20:01:05.335169 [Byte1]: 41
8708 20:01:05.340314
8709 20:01:05.340883 Set Vref, RX VrefLevel [Byte0]: 42
8710 20:01:05.343433 [Byte1]: 42
8711 20:01:05.348651
8712 20:01:05.349209 Set Vref, RX VrefLevel [Byte0]: 43
8713 20:01:05.350317 [Byte1]: 43
8714 20:01:05.354766
8715 20:01:05.355318 Set Vref, RX VrefLevel [Byte0]: 44
8716 20:01:05.357910 [Byte1]: 44
8717 20:01:05.362487
8718 20:01:05.363034 Set Vref, RX VrefLevel [Byte0]: 45
8719 20:01:05.365975 [Byte1]: 45
8720 20:01:05.370384
8721 20:01:05.370942 Set Vref, RX VrefLevel [Byte0]: 46
8722 20:01:05.373161 [Byte1]: 46
8723 20:01:05.377568
8724 20:01:05.378121 Set Vref, RX VrefLevel [Byte0]: 47
8725 20:01:05.381295 [Byte1]: 47
8726 20:01:05.385181
8727 20:01:05.385732 Set Vref, RX VrefLevel [Byte0]: 48
8728 20:01:05.389016 [Byte1]: 48
8729 20:01:05.393095
8730 20:01:05.393649 Set Vref, RX VrefLevel [Byte0]: 49
8731 20:01:05.396296 [Byte1]: 49
8732 20:01:05.400646
8733 20:01:05.401219 Set Vref, RX VrefLevel [Byte0]: 50
8734 20:01:05.403701 [Byte1]: 50
8735 20:01:05.408188
8736 20:01:05.408758 Set Vref, RX VrefLevel [Byte0]: 51
8737 20:01:05.411635 [Byte1]: 51
8738 20:01:05.416517
8739 20:01:05.417127 Set Vref, RX VrefLevel [Byte0]: 52
8740 20:01:05.418760 [Byte1]: 52
8741 20:01:05.423169
8742 20:01:05.423641 Set Vref, RX VrefLevel [Byte0]: 53
8743 20:01:05.426542 [Byte1]: 53
8744 20:01:05.430710
8745 20:01:05.431182 Set Vref, RX VrefLevel [Byte0]: 54
8746 20:01:05.434227 [Byte1]: 54
8747 20:01:05.438586
8748 20:01:05.439159 Set Vref, RX VrefLevel [Byte0]: 55
8749 20:01:05.441872 [Byte1]: 55
8750 20:01:05.446031
8751 20:01:05.446611 Set Vref, RX VrefLevel [Byte0]: 56
8752 20:01:05.449525 [Byte1]: 56
8753 20:01:05.453764
8754 20:01:05.454342 Set Vref, RX VrefLevel [Byte0]: 57
8755 20:01:05.457424 [Byte1]: 57
8756 20:01:05.461525
8757 20:01:05.462095 Set Vref, RX VrefLevel [Byte0]: 58
8758 20:01:05.464761 [Byte1]: 58
8759 20:01:05.469147
8760 20:01:05.469721 Set Vref, RX VrefLevel [Byte0]: 59
8761 20:01:05.472424 [Byte1]: 59
8762 20:01:05.476481
8763 20:01:05.477056 Set Vref, RX VrefLevel [Byte0]: 60
8764 20:01:05.479878 [Byte1]: 60
8765 20:01:05.484818
8766 20:01:05.485437 Set Vref, RX VrefLevel [Byte0]: 61
8767 20:01:05.488295 [Byte1]: 61
8768 20:01:05.491923
8769 20:01:05.492397 Set Vref, RX VrefLevel [Byte0]: 62
8770 20:01:05.495391 [Byte1]: 62
8771 20:01:05.499776
8772 20:01:05.500355 Set Vref, RX VrefLevel [Byte0]: 63
8773 20:01:05.503054 [Byte1]: 63
8774 20:01:05.507051
8775 20:01:05.507623 Set Vref, RX VrefLevel [Byte0]: 64
8776 20:01:05.510070 [Byte1]: 64
8777 20:01:05.514787
8778 20:01:05.515362 Set Vref, RX VrefLevel [Byte0]: 65
8779 20:01:05.521053 [Byte1]: 65
8780 20:01:05.521631
8781 20:01:05.524223 Set Vref, RX VrefLevel [Byte0]: 66
8782 20:01:05.527484 [Byte1]: 66
8783 20:01:05.528150
8784 20:01:05.530603 Set Vref, RX VrefLevel [Byte0]: 67
8785 20:01:05.534050 [Byte1]: 67
8786 20:01:05.537409
8787 20:01:05.537958 Set Vref, RX VrefLevel [Byte0]: 68
8788 20:01:05.540408 [Byte1]: 68
8789 20:01:05.545027
8790 20:01:05.545576 Set Vref, RX VrefLevel [Byte0]: 69
8791 20:01:05.548201 [Byte1]: 69
8792 20:01:05.552884
8793 20:01:05.553433 Set Vref, RX VrefLevel [Byte0]: 70
8794 20:01:05.555955 [Byte1]: 70
8795 20:01:05.560176
8796 20:01:05.560742 Set Vref, RX VrefLevel [Byte0]: 71
8797 20:01:05.563519 [Byte1]: 71
8798 20:01:05.567898
8799 20:01:05.568442 Set Vref, RX VrefLevel [Byte0]: 72
8800 20:01:05.571461 [Byte1]: 72
8801 20:01:05.575922
8802 20:01:05.576501 Set Vref, RX VrefLevel [Byte0]: 73
8803 20:01:05.579199 [Byte1]: 73
8804 20:01:05.583278
8805 20:01:05.583873 Final RX Vref Byte 0 = 54 to rank0
8806 20:01:05.586265 Final RX Vref Byte 1 = 59 to rank0
8807 20:01:05.589894 Final RX Vref Byte 0 = 54 to rank1
8808 20:01:05.592967 Final RX Vref Byte 1 = 59 to rank1==
8809 20:01:05.596296 Dram Type= 6, Freq= 0, CH_1, rank 0
8810 20:01:05.603015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 20:01:05.603589 ==
8812 20:01:05.603986 DQS Delay:
8813 20:01:05.605944 DQS0 = 0, DQS1 = 0
8814 20:01:05.606399 DQM Delay:
8815 20:01:05.606757 DQM0 = 133, DQM1 = 127
8816 20:01:05.609795 DQ Delay:
8817 20:01:05.612897 DQ0 =140, DQ1 =126, DQ2 =122, DQ3 =130
8818 20:01:05.616622 DQ4 =130, DQ5 =148, DQ6 =142, DQ7 =128
8819 20:01:05.619071 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8820 20:01:05.622318 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8821 20:01:05.622896
8822 20:01:05.623379
8823 20:01:05.623958
8824 20:01:05.626173 [DramC_TX_OE_Calibration] TA2
8825 20:01:05.629040 Original DQ_B0 (3 6) =30, OEN = 27
8826 20:01:05.632270 Original DQ_B1 (3 6) =30, OEN = 27
8827 20:01:05.635934 24, 0x0, End_B0=24 End_B1=24
8828 20:01:05.636397 25, 0x0, End_B0=25 End_B1=25
8829 20:01:05.639226 26, 0x0, End_B0=26 End_B1=26
8830 20:01:05.642431 27, 0x0, End_B0=27 End_B1=27
8831 20:01:05.645998 28, 0x0, End_B0=28 End_B1=28
8832 20:01:05.648840 29, 0x0, End_B0=29 End_B1=29
8833 20:01:05.649262 30, 0x0, End_B0=30 End_B1=30
8834 20:01:05.652424 31, 0x4141, End_B0=30 End_B1=30
8835 20:01:05.656394 Byte0 end_step=30 best_step=27
8836 20:01:05.659029 Byte1 end_step=30 best_step=27
8837 20:01:05.662265 Byte0 TX OE(2T, 0.5T) = (3, 3)
8838 20:01:05.665602 Byte1 TX OE(2T, 0.5T) = (3, 3)
8839 20:01:05.666122
8840 20:01:05.666459
8841 20:01:05.671986 [DQSOSCAuto] RK0, (LSB)MR18= 0x170c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8842 20:01:05.675652 CH1 RK0: MR19=303, MR18=170C
8843 20:01:05.682642 CH1_RK0: MR19=0x303, MR18=0x170C, DQSOSC=398, MR23=63, INC=23, DEC=15
8844 20:01:05.683165
8845 20:01:05.685156 ----->DramcWriteLeveling(PI) begin...
8846 20:01:05.685750 ==
8847 20:01:05.689036 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 20:01:05.691962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 20:01:05.692478 ==
8850 20:01:05.695529 Write leveling (Byte 0): 26 => 26
8851 20:01:05.698423 Write leveling (Byte 1): 26 => 26
8852 20:01:05.702137 DramcWriteLeveling(PI) end<-----
8853 20:01:05.702655
8854 20:01:05.702990 ==
8855 20:01:05.705233 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 20:01:05.708478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 20:01:05.711715 ==
8858 20:01:05.712285 [Gating] SW mode calibration
8859 20:01:05.721283 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8860 20:01:05.725288 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8861 20:01:05.728016 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 20:01:05.734711 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 20:01:05.738209 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
8864 20:01:05.741071 1 4 12 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8865 20:01:05.747860 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8866 20:01:05.751267 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8867 20:01:05.754800 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8868 20:01:05.761024 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8869 20:01:05.764175 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8870 20:01:05.767834 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8871 20:01:05.774285 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (1 0) (1 0)
8872 20:01:05.778025 1 5 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 0)
8873 20:01:05.781359 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 20:01:05.787535 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 20:01:05.791186 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 20:01:05.794180 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 20:01:05.801061 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 20:01:05.804038 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8879 20:01:05.807811 1 6 8 | B1->B0 | 3131 2323 | 1 0 | (0 0) (0 0)
8880 20:01:05.813796 1 6 12 | B1->B0 | 4646 2727 | 0 0 | (0 0) (0 0)
8881 20:01:05.817547 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8882 20:01:05.820315 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8883 20:01:05.827363 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8884 20:01:05.830422 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 20:01:05.834287 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8886 20:01:05.840150 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 20:01:05.843376 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8888 20:01:05.847358 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8889 20:01:05.853735 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8890 20:01:05.856442 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 20:01:05.859997 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 20:01:05.866795 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 20:01:05.870042 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 20:01:05.873043 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 20:01:05.879761 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 20:01:05.883658 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 20:01:05.886785 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 20:01:05.892995 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 20:01:05.897162 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 20:01:05.899837 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 20:01:05.905897 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 20:01:05.910144 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 20:01:05.913633 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8904 20:01:05.919637 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8905 20:01:05.923124 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8906 20:01:05.926244 Total UI for P1: 0, mck2ui 16
8907 20:01:05.929317 best dqsien dly found for B1: ( 1, 9, 10)
8908 20:01:05.932990 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8909 20:01:05.935809 Total UI for P1: 0, mck2ui 16
8910 20:01:05.939146 best dqsien dly found for B0: ( 1, 9, 14)
8911 20:01:05.942198 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8912 20:01:05.945949 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8913 20:01:05.949556
8914 20:01:05.952160 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8915 20:01:05.955910 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8916 20:01:05.958896 [Gating] SW calibration Done
8917 20:01:05.959472 ==
8918 20:01:05.962491 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 20:01:05.965505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 20:01:05.966074 ==
8921 20:01:05.968501 RX Vref Scan: 0
8922 20:01:05.969096
8923 20:01:05.969545 RX Vref 0 -> 0, step: 1
8924 20:01:05.969899
8925 20:01:05.972368 RX Delay 0 -> 252, step: 8
8926 20:01:05.975684 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8927 20:01:05.979092 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8928 20:01:05.985220 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8929 20:01:05.989009 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8930 20:01:05.991945 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8931 20:01:05.995111 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8932 20:01:05.998682 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8933 20:01:06.004936 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8934 20:01:06.008086 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8935 20:01:06.011671 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8936 20:01:06.015175 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8937 20:01:06.021608 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8938 20:01:06.024519 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8939 20:01:06.028102 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8940 20:01:06.031355 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8941 20:01:06.034773 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8942 20:01:06.038102 ==
8943 20:01:06.041531 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 20:01:06.044990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 20:01:06.045546 ==
8946 20:01:06.045912 DQS Delay:
8947 20:01:06.047933 DQS0 = 0, DQS1 = 0
8948 20:01:06.048397 DQM Delay:
8949 20:01:06.051048 DQM0 = 136, DQM1 = 129
8950 20:01:06.051604 DQ Delay:
8951 20:01:06.054944 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8952 20:01:06.058169 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8953 20:01:06.061061 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8954 20:01:06.064603 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8955 20:01:06.065162
8956 20:01:06.065523
8957 20:01:06.067822 ==
8958 20:01:06.071192 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 20:01:06.074267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 20:01:06.074828 ==
8961 20:01:06.075199
8962 20:01:06.075646
8963 20:01:06.077577 TX Vref Scan disable
8964 20:01:06.078137 == TX Byte 0 ==
8965 20:01:06.080668 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8966 20:01:06.087338 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8967 20:01:06.087949 == TX Byte 1 ==
8968 20:01:06.093958 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8969 20:01:06.097055 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8970 20:01:06.097617 ==
8971 20:01:06.100967 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 20:01:06.104784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 20:01:06.105352 ==
8974 20:01:06.117265
8975 20:01:06.120680 TX Vref early break, caculate TX vref
8976 20:01:06.124328 TX Vref=16, minBit 8, minWin=23, winSum=386
8977 20:01:06.127189 TX Vref=18, minBit 9, minWin=23, winSum=398
8978 20:01:06.130278 TX Vref=20, minBit 8, minWin=24, winSum=409
8979 20:01:06.134181 TX Vref=22, minBit 1, minWin=25, winSum=415
8980 20:01:06.136885 TX Vref=24, minBit 0, minWin=25, winSum=425
8981 20:01:06.143842 TX Vref=26, minBit 0, minWin=25, winSum=428
8982 20:01:06.147152 TX Vref=28, minBit 0, minWin=25, winSum=425
8983 20:01:06.150526 TX Vref=30, minBit 0, minWin=25, winSum=425
8984 20:01:06.153394 TX Vref=32, minBit 0, minWin=25, winSum=411
8985 20:01:06.156530 TX Vref=34, minBit 0, minWin=24, winSum=405
8986 20:01:06.163524 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 26
8987 20:01:06.164138
8988 20:01:06.166698 Final TX Range 0 Vref 26
8989 20:01:06.167252
8990 20:01:06.167622 ==
8991 20:01:06.170418 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 20:01:06.173850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 20:01:06.174409 ==
8994 20:01:06.174781
8995 20:01:06.175118
8996 20:01:06.176944 TX Vref Scan disable
8997 20:01:06.183412 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8998 20:01:06.184049 == TX Byte 0 ==
8999 20:01:06.186427 u2DelayCellOfst[0]=22 cells (6 PI)
9000 20:01:06.190049 u2DelayCellOfst[1]=14 cells (4 PI)
9001 20:01:06.193331 u2DelayCellOfst[2]=0 cells (0 PI)
9002 20:01:06.196038 u2DelayCellOfst[3]=7 cells (2 PI)
9003 20:01:06.200505 u2DelayCellOfst[4]=11 cells (3 PI)
9004 20:01:06.203076 u2DelayCellOfst[5]=22 cells (6 PI)
9005 20:01:06.206396 u2DelayCellOfst[6]=22 cells (6 PI)
9006 20:01:06.209961 u2DelayCellOfst[7]=7 cells (2 PI)
9007 20:01:06.212489 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
9008 20:01:06.216042 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
9009 20:01:06.219646 == TX Byte 1 ==
9010 20:01:06.222517 u2DelayCellOfst[8]=0 cells (0 PI)
9011 20:01:06.226270 u2DelayCellOfst[9]=3 cells (1 PI)
9012 20:01:06.229443 u2DelayCellOfst[10]=11 cells (3 PI)
9013 20:01:06.230001 u2DelayCellOfst[11]=7 cells (2 PI)
9014 20:01:06.232823 u2DelayCellOfst[12]=14 cells (4 PI)
9015 20:01:06.235485 u2DelayCellOfst[13]=18 cells (5 PI)
9016 20:01:06.239340 u2DelayCellOfst[14]=18 cells (5 PI)
9017 20:01:06.242935 u2DelayCellOfst[15]=18 cells (5 PI)
9018 20:01:06.249266 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9019 20:01:06.252363 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9020 20:01:06.252927 DramC Write-DBI on
9021 20:01:06.253298 ==
9022 20:01:06.256400 Dram Type= 6, Freq= 0, CH_1, rank 1
9023 20:01:06.262277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9024 20:01:06.262841 ==
9025 20:01:06.263208
9026 20:01:06.263545
9027 20:01:06.265893 TX Vref Scan disable
9028 20:01:06.266453 == TX Byte 0 ==
9029 20:01:06.272472 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
9030 20:01:06.273043 == TX Byte 1 ==
9031 20:01:06.275623 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9032 20:01:06.278702 DramC Write-DBI off
9033 20:01:06.279254
9034 20:01:06.279621 [DATLAT]
9035 20:01:06.282156 Freq=1600, CH1 RK1
9036 20:01:06.282714
9037 20:01:06.283080 DATLAT Default: 0xf
9038 20:01:06.285332 0, 0xFFFF, sum = 0
9039 20:01:06.285901 1, 0xFFFF, sum = 0
9040 20:01:06.288570 2, 0xFFFF, sum = 0
9041 20:01:06.289135 3, 0xFFFF, sum = 0
9042 20:01:06.291703 4, 0xFFFF, sum = 0
9043 20:01:06.292215 5, 0xFFFF, sum = 0
9044 20:01:06.295268 6, 0xFFFF, sum = 0
9045 20:01:06.295881 7, 0xFFFF, sum = 0
9046 20:01:06.299180 8, 0xFFFF, sum = 0
9047 20:01:06.301648 9, 0xFFFF, sum = 0
9048 20:01:06.302219 10, 0xFFFF, sum = 0
9049 20:01:06.304833 11, 0xFFFF, sum = 0
9050 20:01:06.305340 12, 0xFFFF, sum = 0
9051 20:01:06.308233 13, 0xFFFF, sum = 0
9052 20:01:06.308801 14, 0x0, sum = 1
9053 20:01:06.311982 15, 0x0, sum = 2
9054 20:01:06.312555 16, 0x0, sum = 3
9055 20:01:06.315041 17, 0x0, sum = 4
9056 20:01:06.315507 best_step = 15
9057 20:01:06.315909
9058 20:01:06.316252 ==
9059 20:01:06.318124 Dram Type= 6, Freq= 0, CH_1, rank 1
9060 20:01:06.321172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9061 20:01:06.324656 ==
9062 20:01:06.325223 RX Vref Scan: 0
9063 20:01:06.325602
9064 20:01:06.327912 RX Vref 0 -> 0, step: 1
9065 20:01:06.328461
9066 20:01:06.331471 RX Delay 11 -> 252, step: 4
9067 20:01:06.334921 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9068 20:01:06.337679 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9069 20:01:06.341803 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9070 20:01:06.347676 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9071 20:01:06.350930 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9072 20:01:06.354428 iDelay=203, Bit 5, Center 142 (91 ~ 194) 104
9073 20:01:06.357680 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9074 20:01:06.361336 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9075 20:01:06.367490 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9076 20:01:06.370992 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9077 20:01:06.374257 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9078 20:01:06.377593 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9079 20:01:06.384207 iDelay=203, Bit 12, Center 138 (83 ~ 194) 112
9080 20:01:06.387774 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9081 20:01:06.390808 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9082 20:01:06.394595 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9083 20:01:06.395158 ==
9084 20:01:06.397238 Dram Type= 6, Freq= 0, CH_1, rank 1
9085 20:01:06.403930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9086 20:01:06.404479 ==
9087 20:01:06.404851 DQS Delay:
9088 20:01:06.405196 DQS0 = 0, DQS1 = 0
9089 20:01:06.407024 DQM Delay:
9090 20:01:06.407585 DQM0 = 133, DQM1 = 127
9091 20:01:06.410847 DQ Delay:
9092 20:01:06.413622 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9093 20:01:06.416779 DQ4 =132, DQ5 =142, DQ6 =146, DQ7 =130
9094 20:01:06.420331 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =118
9095 20:01:06.424110 DQ12 =138, DQ13 =134, DQ14 =134, DQ15 =138
9096 20:01:06.424709
9097 20:01:06.425077
9098 20:01:06.425416
9099 20:01:06.426501 [DramC_TX_OE_Calibration] TA2
9100 20:01:06.430265 Original DQ_B0 (3 6) =30, OEN = 27
9101 20:01:06.433232 Original DQ_B1 (3 6) =30, OEN = 27
9102 20:01:06.436814 24, 0x0, End_B0=24 End_B1=24
9103 20:01:06.437302 25, 0x0, End_B0=25 End_B1=25
9104 20:01:06.439921 26, 0x0, End_B0=26 End_B1=26
9105 20:01:06.444111 27, 0x0, End_B0=27 End_B1=27
9106 20:01:06.446913 28, 0x0, End_B0=28 End_B1=28
9107 20:01:06.450488 29, 0x0, End_B0=29 End_B1=29
9108 20:01:06.451230 30, 0x0, End_B0=30 End_B1=30
9109 20:01:06.453494 31, 0x4141, End_B0=30 End_B1=30
9110 20:01:06.456507 Byte0 end_step=30 best_step=27
9111 20:01:06.459855 Byte1 end_step=30 best_step=27
9112 20:01:06.463517 Byte0 TX OE(2T, 0.5T) = (3, 3)
9113 20:01:06.467016 Byte1 TX OE(2T, 0.5T) = (3, 3)
9114 20:01:06.467597
9115 20:01:06.468009
9116 20:01:06.473506 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9117 20:01:06.476948 CH1 RK1: MR19=303, MR18=E0A
9118 20:01:06.483006 CH1_RK1: MR19=0x303, MR18=0xE0A, DQSOSC=402, MR23=63, INC=22, DEC=15
9119 20:01:06.486573 [RxdqsGatingPostProcess] freq 1600
9120 20:01:06.489421 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9121 20:01:06.493135 best DQS0 dly(2T, 0.5T) = (1, 1)
9122 20:01:06.496116 best DQS1 dly(2T, 0.5T) = (1, 1)
9123 20:01:06.499873 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9124 20:01:06.502599 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9125 20:01:06.506491 best DQS0 dly(2T, 0.5T) = (1, 1)
9126 20:01:06.509723 best DQS1 dly(2T, 0.5T) = (1, 1)
9127 20:01:06.512230 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9128 20:01:06.515904 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9129 20:01:06.519222 Pre-setting of DQS Precalculation
9130 20:01:06.522199 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9131 20:01:06.528918 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9132 20:01:06.539084 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9133 20:01:06.539639
9134 20:01:06.540067
9135 20:01:06.542302 [Calibration Summary] 3200 Mbps
9136 20:01:06.542858 CH 0, Rank 0
9137 20:01:06.545846 SW Impedance : PASS
9138 20:01:06.546408 DUTY Scan : NO K
9139 20:01:06.549947 ZQ Calibration : PASS
9140 20:01:06.552384 Jitter Meter : NO K
9141 20:01:06.552843 CBT Training : PASS
9142 20:01:06.555338 Write leveling : PASS
9143 20:01:06.558579 RX DQS gating : PASS
9144 20:01:06.559141 RX DQ/DQS(RDDQC) : PASS
9145 20:01:06.561871 TX DQ/DQS : PASS
9146 20:01:06.565130 RX DATLAT : PASS
9147 20:01:06.565590 RX DQ/DQS(Engine): PASS
9148 20:01:06.568263 TX OE : PASS
9149 20:01:06.568827 All Pass.
9150 20:01:06.569201
9151 20:01:06.572064 CH 0, Rank 1
9152 20:01:06.572619 SW Impedance : PASS
9153 20:01:06.574947 DUTY Scan : NO K
9154 20:01:06.575514 ZQ Calibration : PASS
9155 20:01:06.578128 Jitter Meter : NO K
9156 20:01:06.581829 CBT Training : PASS
9157 20:01:06.582404 Write leveling : PASS
9158 20:01:06.584805 RX DQS gating : PASS
9159 20:01:06.588707 RX DQ/DQS(RDDQC) : PASS
9160 20:01:06.589273 TX DQ/DQS : PASS
9161 20:01:06.591608 RX DATLAT : PASS
9162 20:01:06.594939 RX DQ/DQS(Engine): PASS
9163 20:01:06.595499 TX OE : PASS
9164 20:01:06.598304 All Pass.
9165 20:01:06.598858
9166 20:01:06.599228 CH 1, Rank 0
9167 20:01:06.601282 SW Impedance : PASS
9168 20:01:06.601839 DUTY Scan : NO K
9169 20:01:06.604680 ZQ Calibration : PASS
9170 20:01:06.608132 Jitter Meter : NO K
9171 20:01:06.608697 CBT Training : PASS
9172 20:01:06.611458 Write leveling : PASS
9173 20:01:06.614545 RX DQS gating : PASS
9174 20:01:06.615106 RX DQ/DQS(RDDQC) : PASS
9175 20:01:06.617515 TX DQ/DQS : PASS
9176 20:01:06.621294 RX DATLAT : PASS
9177 20:01:06.621891 RX DQ/DQS(Engine): PASS
9178 20:01:06.624110 TX OE : PASS
9179 20:01:06.624570 All Pass.
9180 20:01:06.624940
9181 20:01:06.627396 CH 1, Rank 1
9182 20:01:06.627901 SW Impedance : PASS
9183 20:01:06.630964 DUTY Scan : NO K
9184 20:01:06.634172 ZQ Calibration : PASS
9185 20:01:06.634631 Jitter Meter : NO K
9186 20:01:06.637311 CBT Training : PASS
9187 20:01:06.640831 Write leveling : PASS
9188 20:01:06.641279 RX DQS gating : PASS
9189 20:01:06.643865 RX DQ/DQS(RDDQC) : PASS
9190 20:01:06.647788 TX DQ/DQS : PASS
9191 20:01:06.648206 RX DATLAT : PASS
9192 20:01:06.650943 RX DQ/DQS(Engine): PASS
9193 20:01:06.651451 TX OE : PASS
9194 20:01:06.653887 All Pass.
9195 20:01:06.654395
9196 20:01:06.654729 DramC Write-DBI on
9197 20:01:06.657594 PER_BANK_REFRESH: Hybrid Mode
9198 20:01:06.660772 TX_TRACKING: ON
9199 20:01:06.667172 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9200 20:01:06.677166 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9201 20:01:06.683893 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9202 20:01:06.687018 [FAST_K] Save calibration result to emmc
9203 20:01:06.690904 sync common calibartion params.
9204 20:01:06.693269 sync cbt_mode0:1, 1:1
9205 20:01:06.693731 dram_init: ddr_geometry: 2
9206 20:01:06.696902 dram_init: ddr_geometry: 2
9207 20:01:06.699869 dram_init: ddr_geometry: 2
9208 20:01:06.700334 0:dram_rank_size:100000000
9209 20:01:06.703392 1:dram_rank_size:100000000
9210 20:01:06.710265 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9211 20:01:06.713379 DFS_SHUFFLE_HW_MODE: ON
9212 20:01:06.716728 dramc_set_vcore_voltage set vcore to 725000
9213 20:01:06.717283 Read voltage for 1600, 0
9214 20:01:06.720183 Vio18 = 0
9215 20:01:06.720736 Vcore = 725000
9216 20:01:06.721104 Vdram = 0
9217 20:01:06.723625 Vddq = 0
9218 20:01:06.724226 Vmddr = 0
9219 20:01:06.726623 switch to 3200 Mbps bootup
9220 20:01:06.727081 [DramcRunTimeConfig]
9221 20:01:06.727453 PHYPLL
9222 20:01:06.730085 DPM_CONTROL_AFTERK: ON
9223 20:01:06.733172 PER_BANK_REFRESH: ON
9224 20:01:06.733738 REFRESH_OVERHEAD_REDUCTION: ON
9225 20:01:06.736766 CMD_PICG_NEW_MODE: OFF
9226 20:01:06.739454 XRTWTW_NEW_MODE: ON
9227 20:01:06.739957 XRTRTR_NEW_MODE: ON
9228 20:01:06.743094 TX_TRACKING: ON
9229 20:01:06.743554 RDSEL_TRACKING: OFF
9230 20:01:06.746364 DQS Precalculation for DVFS: ON
9231 20:01:06.749474 RX_TRACKING: OFF
9232 20:01:06.750031 HW_GATING DBG: ON
9233 20:01:06.752835 ZQCS_ENABLE_LP4: ON
9234 20:01:06.753291 RX_PICG_NEW_MODE: ON
9235 20:01:06.756173 TX_PICG_NEW_MODE: ON
9236 20:01:06.756655 ENABLE_RX_DCM_DPHY: ON
9237 20:01:06.759655 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9238 20:01:06.762874 DUMMY_READ_FOR_TRACKING: OFF
9239 20:01:06.766123 !!! SPM_CONTROL_AFTERK: OFF
9240 20:01:06.769585 !!! SPM could not control APHY
9241 20:01:06.770142 IMPEDANCE_TRACKING: ON
9242 20:01:06.772441 TEMP_SENSOR: ON
9243 20:01:06.772897 HW_SAVE_FOR_SR: OFF
9244 20:01:06.776369 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9245 20:01:06.779380 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9246 20:01:06.782699 Read ODT Tracking: ON
9247 20:01:06.785955 Refresh Rate DeBounce: ON
9248 20:01:06.786510 DFS_NO_QUEUE_FLUSH: ON
9249 20:01:06.789122 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9250 20:01:06.792497 ENABLE_DFS_RUNTIME_MRW: OFF
9251 20:01:06.795457 DDR_RESERVE_NEW_MODE: ON
9252 20:01:06.795933 MR_CBT_SWITCH_FREQ: ON
9253 20:01:06.799125 =========================
9254 20:01:06.818279 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9255 20:01:06.821107 dram_init: ddr_geometry: 2
9256 20:01:06.839602 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9257 20:01:06.842539 dram_init: dram init end (result: 0)
9258 20:01:06.849109 DRAM-K: Full calibration passed in 24612 msecs
9259 20:01:06.852255 MRC: failed to locate region type 0.
9260 20:01:06.852687 DRAM rank0 size:0x100000000,
9261 20:01:06.855697 DRAM rank1 size=0x100000000
9262 20:01:06.866066 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9263 20:01:06.872438 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9264 20:01:06.879504 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9265 20:01:06.889039 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9266 20:01:06.889536 DRAM rank0 size:0x100000000,
9267 20:01:06.892152 DRAM rank1 size=0x100000000
9268 20:01:06.892630 CBMEM:
9269 20:01:06.895317 IMD: root @ 0xfffff000 254 entries.
9270 20:01:06.900059 IMD: root @ 0xffffec00 62 entries.
9271 20:01:06.901869 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9272 20:01:06.908784 WARNING: RO_VPD is uninitialized or empty.
9273 20:01:06.911641 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9274 20:01:06.919412 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9275 20:01:06.931890 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9276 20:01:06.943916 BS: romstage times (exec / console): total (unknown) / 24105 ms
9277 20:01:06.944478
9278 20:01:06.944845
9279 20:01:06.953230 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9280 20:01:06.957093 ARM64: Exception handlers installed.
9281 20:01:06.959840 ARM64: Testing exception
9282 20:01:06.963654 ARM64: Done test exception
9283 20:01:06.964274 Enumerating buses...
9284 20:01:06.966909 Show all devs... Before device enumeration.
9285 20:01:06.969924 Root Device: enabled 1
9286 20:01:06.973787 CPU_CLUSTER: 0: enabled 1
9287 20:01:06.974341 CPU: 00: enabled 1
9288 20:01:06.976524 Compare with tree...
9289 20:01:06.976974 Root Device: enabled 1
9290 20:01:06.980522 CPU_CLUSTER: 0: enabled 1
9291 20:01:06.983236 CPU: 00: enabled 1
9292 20:01:06.983839 Root Device scanning...
9293 20:01:06.986405 scan_static_bus for Root Device
9294 20:01:06.989665 CPU_CLUSTER: 0 enabled
9295 20:01:06.992805 scan_static_bus for Root Device done
9296 20:01:06.997151 scan_bus: bus Root Device finished in 8 msecs
9297 20:01:06.997708 done
9298 20:01:07.003234 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9299 20:01:07.006743 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9300 20:01:07.012933 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9301 20:01:07.016467 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9302 20:01:07.019816 Allocating resources...
9303 20:01:07.022741 Reading resources...
9304 20:01:07.025863 Root Device read_resources bus 0 link: 0
9305 20:01:07.029445 DRAM rank0 size:0x100000000,
9306 20:01:07.029998 DRAM rank1 size=0x100000000
9307 20:01:07.036143 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9308 20:01:07.036719 CPU: 00 missing read_resources
9309 20:01:07.042928 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9310 20:01:07.045838 Root Device read_resources bus 0 link: 0 done
9311 20:01:07.048817 Done reading resources.
9312 20:01:07.052698 Show resources in subtree (Root Device)...After reading.
9313 20:01:07.056110 Root Device child on link 0 CPU_CLUSTER: 0
9314 20:01:07.059146 CPU_CLUSTER: 0 child on link 0 CPU: 00
9315 20:01:07.069109 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9316 20:01:07.069666 CPU: 00
9317 20:01:07.072622 Root Device assign_resources, bus 0 link: 0
9318 20:01:07.075353 CPU_CLUSTER: 0 missing set_resources
9319 20:01:07.082624 Root Device assign_resources, bus 0 link: 0 done
9320 20:01:07.083233 Done setting resources.
9321 20:01:07.089271 Show resources in subtree (Root Device)...After assigning values.
9322 20:01:07.092259 Root Device child on link 0 CPU_CLUSTER: 0
9323 20:01:07.095147 CPU_CLUSTER: 0 child on link 0 CPU: 00
9324 20:01:07.105598 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9325 20:01:07.106157 CPU: 00
9326 20:01:07.108570 Done allocating resources.
9327 20:01:07.115222 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9328 20:01:07.115807 Enabling resources...
9329 20:01:07.118267 done.
9330 20:01:07.121662 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9331 20:01:07.125346 Initializing devices...
9332 20:01:07.125952 Root Device init
9333 20:01:07.128058 init hardware done!
9334 20:01:07.128565 0x00000018: ctrlr->caps
9335 20:01:07.131390 52.000 MHz: ctrlr->f_max
9336 20:01:07.134935 0.400 MHz: ctrlr->f_min
9337 20:01:07.135497 0x40ff8080: ctrlr->voltages
9338 20:01:07.138271 sclk: 390625
9339 20:01:07.138808 Bus Width = 1
9340 20:01:07.142993 sclk: 390625
9341 20:01:07.143563 Bus Width = 1
9342 20:01:07.145005 Early init status = 3
9343 20:01:07.148258 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9344 20:01:07.152201 in-header: 03 fc 00 00 01 00 00 00
9345 20:01:07.156028 in-data: 00
9346 20:01:07.158959 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9347 20:01:07.164167 in-header: 03 fd 00 00 00 00 00 00
9348 20:01:07.167251 in-data:
9349 20:01:07.171170 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9350 20:01:07.175076 in-header: 03 fc 00 00 01 00 00 00
9351 20:01:07.178261 in-data: 00
9352 20:01:07.181913 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9353 20:01:07.189206 in-header: 03 fd 00 00 00 00 00 00
9354 20:01:07.191903 in-data:
9355 20:01:07.194937 [SSUSB] Setting up USB HOST controller...
9356 20:01:07.198746 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9357 20:01:07.202019 [SSUSB] phy power-on done.
9358 20:01:07.204800 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9359 20:01:07.211541 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9360 20:01:07.214609 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9361 20:01:07.221247 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9362 20:01:07.227910 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9363 20:01:07.234577 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9364 20:01:07.241489 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9365 20:01:07.247620 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9366 20:01:07.250858 SPM: binary array size = 0x9dc
9367 20:01:07.254182 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9368 20:01:07.261299 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9369 20:01:07.267998 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9370 20:01:07.274863 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9371 20:01:07.278316 configure_display: Starting display init
9372 20:01:07.312074 anx7625_power_on_init: Init interface.
9373 20:01:07.314933 anx7625_disable_pd_protocol: Disabled PD feature.
9374 20:01:07.318507 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9375 20:01:07.346326 anx7625_start_dp_work: Secure OCM version=00
9376 20:01:07.349468 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9377 20:01:07.367635 sp_tx_get_edid_block: EDID Block = 1
9378 20:01:07.466770 Extracted contents:
9379 20:01:07.469925 header: 00 ff ff ff ff ff ff 00
9380 20:01:07.473851 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9381 20:01:07.476664 version: 01 04
9382 20:01:07.480122 basic params: 95 1f 11 78 0a
9383 20:01:07.483377 chroma info: 76 90 94 55 54 90 27 21 50 54
9384 20:01:07.486657 established: 00 00 00
9385 20:01:07.493432 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9386 20:01:07.496656 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9387 20:01:07.503343 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9388 20:01:07.509866 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9389 20:01:07.516630 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9390 20:01:07.519765 extensions: 00
9391 20:01:07.520326 checksum: fb
9392 20:01:07.520689
9393 20:01:07.523201 Manufacturer: IVO Model 57d Serial Number 0
9394 20:01:07.527141 Made week 0 of 2020
9395 20:01:07.529587 EDID version: 1.4
9396 20:01:07.530042 Digital display
9397 20:01:07.532581 6 bits per primary color channel
9398 20:01:07.533168 DisplayPort interface
9399 20:01:07.535923 Maximum image size: 31 cm x 17 cm
9400 20:01:07.539282 Gamma: 220%
9401 20:01:07.539861 Check DPMS levels
9402 20:01:07.546133 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9403 20:01:07.549526 First detailed timing is preferred timing
9404 20:01:07.550087 Established timings supported:
9405 20:01:07.552676 Standard timings supported:
9406 20:01:07.555650 Detailed timings
9407 20:01:07.559285 Hex of detail: 383680a07038204018303c0035ae10000019
9408 20:01:07.565937 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9409 20:01:07.568932 0780 0798 07c8 0820 hborder 0
9410 20:01:07.572478 0438 043b 0447 0458 vborder 0
9411 20:01:07.576448 -hsync -vsync
9412 20:01:07.577054 Did detailed timing
9413 20:01:07.582642 Hex of detail: 000000000000000000000000000000000000
9414 20:01:07.585607 Manufacturer-specified data, tag 0
9415 20:01:07.588556 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9416 20:01:07.592434 ASCII string: InfoVision
9417 20:01:07.595206 Hex of detail: 000000fe00523134304e574635205248200a
9418 20:01:07.598472 ASCII string: R140NWF5 RH
9419 20:01:07.599024 Checksum
9420 20:01:07.602150 Checksum: 0xfb (valid)
9421 20:01:07.605637 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9422 20:01:07.608631 DSI data_rate: 832800000 bps
9423 20:01:07.615086 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9424 20:01:07.618707 anx7625_parse_edid: pixelclock(138800).
9425 20:01:07.621933 hactive(1920), hsync(48), hfp(24), hbp(88)
9426 20:01:07.624793 vactive(1080), vsync(12), vfp(3), vbp(17)
9427 20:01:07.628326 anx7625_dsi_config: config dsi.
9428 20:01:07.634971 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9429 20:01:07.648639 anx7625_dsi_config: success to config DSI
9430 20:01:07.652413 anx7625_dp_start: MIPI phy setup OK.
9431 20:01:07.655170 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9432 20:01:07.658747 mtk_ddp_mode_set invalid vrefresh 60
9433 20:01:07.662258 main_disp_path_setup
9434 20:01:07.662812 ovl_layer_smi_id_en
9435 20:01:07.665017 ovl_layer_smi_id_en
9436 20:01:07.665477 ccorr_config
9437 20:01:07.665842 aal_config
9438 20:01:07.669267 gamma_config
9439 20:01:07.669820 postmask_config
9440 20:01:07.671921 dither_config
9441 20:01:07.675615 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9442 20:01:07.682638 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9443 20:01:07.684841 Root Device init finished in 556 msecs
9444 20:01:07.688239 CPU_CLUSTER: 0 init
9445 20:01:07.695130 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9446 20:01:07.702180 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9447 20:01:07.702744 APU_MBOX 0x190000b0 = 0x10001
9448 20:01:07.705073 APU_MBOX 0x190001b0 = 0x10001
9449 20:01:07.707858 APU_MBOX 0x190005b0 = 0x10001
9450 20:01:07.711328 APU_MBOX 0x190006b0 = 0x10001
9451 20:01:07.717932 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9452 20:01:07.728337 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9453 20:01:07.740698 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9454 20:01:07.746635 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9455 20:01:07.758495 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9456 20:01:07.767412 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9457 20:01:07.771360 CPU_CLUSTER: 0 init finished in 81 msecs
9458 20:01:07.774310 Devices initialized
9459 20:01:07.777833 Show all devs... After init.
9460 20:01:07.778310 Root Device: enabled 1
9461 20:01:07.781472 CPU_CLUSTER: 0: enabled 1
9462 20:01:07.784440 CPU: 00: enabled 1
9463 20:01:07.787379 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9464 20:01:07.791583 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9465 20:01:07.793788 ELOG: NV offset 0x57f000 size 0x1000
9466 20:01:07.800695 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9467 20:01:07.807900 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9468 20:01:07.810720 ELOG: Event(17) added with size 13 at 2023-10-28 20:01:07 UTC
9469 20:01:07.816835 out: cmd=0x121: 03 db 21 01 00 00 00 00
9470 20:01:07.820912 in-header: 03 cb 00 00 2c 00 00 00
9471 20:01:07.830299 in-data: 94 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9472 20:01:07.837125 ELOG: Event(A1) added with size 10 at 2023-10-28 20:01:07 UTC
9473 20:01:07.843242 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9474 20:01:07.849953 ELOG: Event(A0) added with size 9 at 2023-10-28 20:01:07 UTC
9475 20:01:07.853637 elog_add_boot_reason: Logged dev mode boot
9476 20:01:07.859824 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9477 20:01:07.860305 Finalize devices...
9478 20:01:07.863628 Devices finalized
9479 20:01:07.866586 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9480 20:01:07.869793 Writing coreboot table at 0xffe64000
9481 20:01:07.873465 0. 000000000010a000-0000000000113fff: RAMSTAGE
9482 20:01:07.879710 1. 0000000040000000-00000000400fffff: RAM
9483 20:01:07.882848 2. 0000000040100000-000000004032afff: RAMSTAGE
9484 20:01:07.886215 3. 000000004032b000-00000000545fffff: RAM
9485 20:01:07.889372 4. 0000000054600000-000000005465ffff: BL31
9486 20:01:07.894014 5. 0000000054660000-00000000ffe63fff: RAM
9487 20:01:07.899099 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9488 20:01:07.902421 7. 0000000100000000-000000023fffffff: RAM
9489 20:01:07.906069 Passing 5 GPIOs to payload:
9490 20:01:07.909125 NAME | PORT | POLARITY | VALUE
9491 20:01:07.915619 EC in RW | 0x000000aa | low | undefined
9492 20:01:07.918869 EC interrupt | 0x00000005 | low | undefined
9493 20:01:07.925422 TPM interrupt | 0x000000ab | high | undefined
9494 20:01:07.928558 SD card detect | 0x00000011 | high | undefined
9495 20:01:07.931931 speaker enable | 0x00000093 | high | undefined
9496 20:01:07.935055 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9497 20:01:07.938872 in-header: 03 f9 00 00 02 00 00 00
9498 20:01:07.942333 in-data: 02 00
9499 20:01:07.945721 ADC[4]: Raw value=904139 ID=7
9500 20:01:07.948733 ADC[3]: Raw value=213652 ID=1
9501 20:01:07.949166 RAM Code: 0x71
9502 20:01:07.953270 ADC[6]: Raw value=75406 ID=0
9503 20:01:07.956163 ADC[5]: Raw value=212912 ID=1
9504 20:01:07.956602 SKU Code: 0x1
9505 20:01:07.962647 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a16d
9506 20:01:07.963080 coreboot table: 964 bytes.
9507 20:01:07.965480 IMD ROOT 0. 0xfffff000 0x00001000
9508 20:01:07.968975 IMD SMALL 1. 0xffffe000 0x00001000
9509 20:01:07.972000 RO MCACHE 2. 0xffffc000 0x00001104
9510 20:01:07.975383 CONSOLE 3. 0xfff7c000 0x00080000
9511 20:01:07.979199 FMAP 4. 0xfff7b000 0x00000452
9512 20:01:07.981943 TIME STAMP 5. 0xfff7a000 0x00000910
9513 20:01:07.985281 VBOOT WORK 6. 0xfff66000 0x00014000
9514 20:01:07.988632 RAMOOPS 7. 0xffe66000 0x00100000
9515 20:01:07.992010 COREBOOT 8. 0xffe64000 0x00002000
9516 20:01:07.995039 IMD small region:
9517 20:01:07.999273 IMD ROOT 0. 0xffffec00 0x00000400
9518 20:01:08.001782 VPD 1. 0xffffeb80 0x0000006c
9519 20:01:08.005878 MMC STATUS 2. 0xffffeb60 0x00000004
9520 20:01:08.011542 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9521 20:01:08.012306 Probing TPM: done!
9522 20:01:08.018762 Connected to device vid:did:rid of 1ae0:0028:00
9523 20:01:08.025355 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9524 20:01:08.028897 Initialized TPM device CR50 revision 0
9525 20:01:08.032308 Checking cr50 for pending updates
9526 20:01:08.037503 Reading cr50 TPM mode
9527 20:01:08.045808 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9528 20:01:08.052437 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9529 20:01:08.092520 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9530 20:01:08.095789 Checking segment from ROM address 0x40100000
9531 20:01:08.099181 Checking segment from ROM address 0x4010001c
9532 20:01:08.105930 Loading segment from ROM address 0x40100000
9533 20:01:08.106484 code (compression=0)
9534 20:01:08.115967 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9535 20:01:08.122405 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9536 20:01:08.122938 it's not compressed!
9537 20:01:08.129207 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9538 20:01:08.135460 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9539 20:01:08.153142 Loading segment from ROM address 0x4010001c
9540 20:01:08.153713 Entry Point 0x80000000
9541 20:01:08.156314 Loaded segments
9542 20:01:08.159834 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9543 20:01:08.166962 Jumping to boot code at 0x80000000(0xffe64000)
9544 20:01:08.173355 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9545 20:01:08.180027 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9546 20:01:08.187866 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9547 20:01:08.191326 Checking segment from ROM address 0x40100000
9548 20:01:08.194385 Checking segment from ROM address 0x4010001c
9549 20:01:08.200741 Loading segment from ROM address 0x40100000
9550 20:01:08.201317 code (compression=1)
9551 20:01:08.207334 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9552 20:01:08.217124 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9553 20:01:08.217669 using LZMA
9554 20:01:08.226041 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9555 20:01:08.232890 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9556 20:01:08.236490 Loading segment from ROM address 0x4010001c
9557 20:01:08.237043 Entry Point 0x54601000
9558 20:01:08.239155 Loaded segments
9559 20:01:08.242711 NOTICE: MT8192 bl31_setup
9560 20:01:08.250654 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9561 20:01:08.253290 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9562 20:01:08.256503 WARNING: region 0:
9563 20:01:08.259971 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9564 20:01:08.260524 WARNING: region 1:
9565 20:01:08.266693 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9566 20:01:08.269941 WARNING: region 2:
9567 20:01:08.272592 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9568 20:01:08.275952 WARNING: region 3:
9569 20:01:08.279634 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9570 20:01:08.282654 WARNING: region 4:
9571 20:01:08.289856 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9572 20:01:08.290415 WARNING: region 5:
9573 20:01:08.292702 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9574 20:01:08.295825 WARNING: region 6:
9575 20:01:08.299599 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9576 20:01:08.302695 WARNING: region 7:
9577 20:01:08.306048 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9578 20:01:08.312977 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9579 20:01:08.315892 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9580 20:01:08.319874 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9581 20:01:08.325706 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9582 20:01:08.329362 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9583 20:01:08.335674 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9584 20:01:08.339211 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9585 20:01:08.342123 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9586 20:01:08.348618 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9587 20:01:08.352237 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9588 20:01:08.355705 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9589 20:01:08.362742 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9590 20:01:08.365999 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9591 20:01:08.369300 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9592 20:01:08.375790 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9593 20:01:08.379108 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9594 20:01:08.385918 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9595 20:01:08.389358 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9596 20:01:08.392485 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9597 20:01:08.399066 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9598 20:01:08.402557 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9599 20:01:08.408840 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9600 20:01:08.412274 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9601 20:01:08.415524 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9602 20:01:08.422097 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9603 20:01:08.426373 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9604 20:01:08.432360 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9605 20:01:08.435496 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9606 20:01:08.439039 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9607 20:01:08.445197 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9608 20:01:08.449266 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9609 20:01:08.455494 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9610 20:01:08.458999 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9611 20:01:08.462163 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9612 20:01:08.465713 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9613 20:01:08.471866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9614 20:01:08.475213 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9615 20:01:08.478763 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9616 20:01:08.481769 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9617 20:01:08.488837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9618 20:01:08.492007 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9619 20:01:08.495341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9620 20:01:08.498254 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9621 20:01:08.505507 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9622 20:01:08.508929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9623 20:01:08.511865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9624 20:01:08.515233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9625 20:01:08.521823 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9626 20:01:08.525145 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9627 20:01:08.531610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9628 20:01:08.535329 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9629 20:01:08.538555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9630 20:01:08.545153 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9631 20:01:08.548354 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9632 20:01:08.554837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9633 20:01:08.557905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9634 20:01:08.564773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9635 20:01:08.568451 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9636 20:01:08.572189 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9637 20:01:08.578748 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9638 20:01:08.581220 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9639 20:01:08.588098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9640 20:01:08.591061 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9641 20:01:08.597465 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9642 20:01:08.601431 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9643 20:01:08.607883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9644 20:01:08.611142 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9645 20:01:08.614393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9646 20:01:08.620668 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9647 20:01:08.624207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9648 20:01:08.631025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9649 20:01:08.634173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9650 20:01:08.640850 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9651 20:01:08.644086 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9652 20:01:08.650619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9653 20:01:08.653846 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9654 20:01:08.656970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9655 20:01:08.663834 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9656 20:01:08.667215 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9657 20:01:08.673913 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9658 20:01:08.677231 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9659 20:01:08.683862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9660 20:01:08.687106 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9661 20:01:08.693738 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9662 20:01:08.696842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9663 20:01:08.700481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9664 20:01:08.707123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9665 20:01:08.710232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9666 20:01:08.716894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9667 20:01:08.720303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9668 20:01:08.726759 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9669 20:01:08.730127 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9670 20:01:08.736536 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9671 20:01:08.739953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9672 20:01:08.743101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9673 20:01:08.750015 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9674 20:01:08.752958 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9675 20:01:08.756392 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9676 20:01:08.763649 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9677 20:01:08.766709 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9678 20:01:08.769577 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9679 20:01:08.776359 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9680 20:01:08.779903 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9681 20:01:08.783506 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9682 20:01:08.789849 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9683 20:01:08.792982 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9684 20:01:08.799348 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9685 20:01:08.803060 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9686 20:01:08.806519 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9687 20:01:08.812718 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9688 20:01:08.815984 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9689 20:01:08.822955 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9690 20:01:08.826018 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9691 20:01:08.832569 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9692 20:01:08.835583 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9693 20:01:08.839151 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9694 20:01:08.842372 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9695 20:01:08.848676 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9696 20:01:08.852196 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9697 20:01:08.856478 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9698 20:01:08.862634 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9699 20:01:08.865875 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9700 20:01:08.869336 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9701 20:01:08.871849 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9702 20:01:08.879019 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9703 20:01:08.881820 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9704 20:01:08.888925 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9705 20:01:08.891794 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9706 20:01:08.898611 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9707 20:01:08.901960 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9708 20:01:08.905128 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9709 20:01:08.912069 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9710 20:01:08.915251 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9711 20:01:08.921849 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9712 20:01:08.925374 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9713 20:01:08.928376 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9714 20:01:08.936003 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9715 20:01:08.938393 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9716 20:01:08.941748 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9717 20:01:08.947867 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9718 20:01:08.951841 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9719 20:01:08.957862 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9720 20:01:08.961513 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9721 20:01:08.965148 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9722 20:01:08.971243 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9723 20:01:08.974580 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9724 20:01:08.981442 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9725 20:01:08.984690 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9726 20:01:08.987958 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9727 20:01:08.994473 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9728 20:01:08.997943 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9729 20:01:09.004683 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9730 20:01:09.008576 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9731 20:01:09.011227 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9732 20:01:09.018063 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9733 20:01:09.021313 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9734 20:01:09.027670 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9735 20:01:09.031003 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9736 20:01:09.034792 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9737 20:01:09.041524 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9738 20:01:09.044131 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9739 20:01:09.051116 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9740 20:01:09.054378 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9741 20:01:09.057307 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9742 20:01:09.063914 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9743 20:01:09.067627 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9744 20:01:09.074510 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9745 20:01:09.077175 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9746 20:01:09.080444 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9747 20:01:09.086977 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9748 20:01:09.091327 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9749 20:01:09.096955 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9750 20:01:09.100040 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9751 20:01:09.103825 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9752 20:01:09.110147 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9753 20:01:09.113197 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9754 20:01:09.120092 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9755 20:01:09.123616 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9756 20:01:09.126542 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9757 20:01:09.133386 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9758 20:01:09.136317 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9759 20:01:09.143076 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9760 20:01:09.146568 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9761 20:01:09.149998 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9762 20:01:09.156213 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9763 20:01:09.159402 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9764 20:01:09.166498 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9765 20:01:09.169369 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9766 20:01:09.173003 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9767 20:01:09.179043 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9768 20:01:09.182706 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9769 20:01:09.189012 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9770 20:01:09.192223 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9771 20:01:09.195756 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9772 20:01:09.202691 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9773 20:01:09.205578 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9774 20:01:09.212292 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9775 20:01:09.215509 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9776 20:01:09.222572 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9777 20:01:09.225379 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9778 20:01:09.228549 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9779 20:01:09.235701 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9780 20:01:09.238741 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9781 20:01:09.245084 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9782 20:01:09.248599 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9783 20:01:09.255246 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9784 20:01:09.258752 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9785 20:01:09.262348 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9786 20:01:09.268546 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9787 20:01:09.271986 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9788 20:01:09.278922 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9789 20:01:09.281111 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9790 20:01:09.288000 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9791 20:01:09.291596 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9792 20:01:09.294606 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9793 20:01:09.301246 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9794 20:01:09.304606 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9795 20:01:09.311272 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9796 20:01:09.315185 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9797 20:01:09.321016 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9798 20:01:09.324131 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9799 20:01:09.327464 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9800 20:01:09.333997 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9801 20:01:09.337670 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9802 20:01:09.344104 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9803 20:01:09.347076 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9804 20:01:09.353710 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9805 20:01:09.357028 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9806 20:01:09.361119 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9807 20:01:09.366970 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9808 20:01:09.371040 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9809 20:01:09.373691 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9810 20:01:09.376903 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9811 20:01:09.384183 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9812 20:01:09.387143 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9813 20:01:09.390019 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9814 20:01:09.396314 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9815 20:01:09.400074 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9816 20:01:09.406707 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9817 20:01:09.410121 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9818 20:01:09.413445 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9819 20:01:09.419546 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9820 20:01:09.423100 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9821 20:01:09.426843 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9822 20:01:09.432858 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9823 20:01:09.436401 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9824 20:01:09.442862 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9825 20:01:09.446607 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9826 20:01:09.449193 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9827 20:01:09.456087 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9828 20:01:09.459607 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9829 20:01:09.463314 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9830 20:01:09.469325 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9831 20:01:09.472403 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9832 20:01:09.479772 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9833 20:01:09.482720 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9834 20:01:09.485882 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9835 20:01:09.492651 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9836 20:01:09.495590 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9837 20:01:09.498712 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9838 20:01:09.505683 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9839 20:01:09.508791 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9840 20:01:09.515571 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9841 20:01:09.518895 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9842 20:01:09.522368 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9843 20:01:09.528994 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9844 20:01:09.531774 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9845 20:01:09.538771 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9846 20:01:09.542051 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9847 20:01:09.544736 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9848 20:01:09.548323 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9849 20:01:09.551783 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9850 20:01:09.558597 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9851 20:01:09.561371 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9852 20:01:09.564747 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9853 20:01:09.568059 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9854 20:01:09.574584 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9855 20:01:09.578466 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9856 20:01:09.581925 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9857 20:01:09.584383 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9858 20:01:09.591514 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9859 20:01:09.594420 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9860 20:01:09.600738 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9861 20:01:09.604706 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9862 20:01:09.607706 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9863 20:01:09.614372 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9864 20:01:09.618189 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9865 20:01:09.623924 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9866 20:01:09.627238 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9867 20:01:09.630700 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9868 20:01:09.637750 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9869 20:01:09.640821 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9870 20:01:09.647665 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9871 20:01:09.651052 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9872 20:01:09.657018 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9873 20:01:09.660299 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9874 20:01:09.667110 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9875 20:01:09.670069 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9876 20:01:09.673964 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9877 20:01:09.680149 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9878 20:01:09.683527 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9879 20:01:09.690160 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9880 20:01:09.693862 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9881 20:01:09.697111 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9882 20:01:09.703641 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9883 20:01:09.707277 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9884 20:01:09.713383 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9885 20:01:09.716469 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9886 20:01:09.720085 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9887 20:01:09.726360 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9888 20:01:09.729921 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9889 20:01:09.736449 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9890 20:01:09.739476 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9891 20:01:09.742884 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9892 20:01:09.749727 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9893 20:01:09.752373 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9894 20:01:09.759408 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9895 20:01:09.762655 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9896 20:01:09.769099 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9897 20:01:09.772078 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9898 20:01:09.779104 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9899 20:01:09.782657 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9900 20:01:09.785689 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9901 20:01:09.792003 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9902 20:01:09.795692 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9903 20:01:09.802457 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9904 20:01:09.805349 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9905 20:01:09.808701 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9906 20:01:09.816190 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9907 20:01:09.818709 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9908 20:01:09.825811 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9909 20:01:09.829083 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9910 20:01:09.831650 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9911 20:01:09.838774 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9912 20:01:09.841620 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9913 20:01:09.848137 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9914 20:01:09.851659 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9915 20:01:09.858116 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9916 20:01:09.861048 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9917 20:01:09.864409 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9918 20:01:09.871409 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9919 20:01:09.874585 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9920 20:01:09.881532 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9921 20:01:09.884580 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9922 20:01:09.891080 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9923 20:01:09.894405 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9924 20:01:09.897645 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9925 20:01:09.904258 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9926 20:01:09.907515 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9927 20:01:09.914471 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9928 20:01:09.917494 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9929 20:01:09.924359 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9930 20:01:09.927423 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9931 20:01:09.930760 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9932 20:01:09.937670 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9933 20:01:09.940230 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9934 20:01:09.946970 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9935 20:01:09.950667 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9936 20:01:09.956573 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9937 20:01:09.960051 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9938 20:01:09.963291 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9939 20:01:09.970222 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9940 20:01:09.973532 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9941 20:01:09.980438 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9942 20:01:09.982992 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9943 20:01:09.990424 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9944 20:01:09.993869 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9945 20:01:09.999589 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9946 20:01:10.003137 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9947 20:01:10.006674 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9948 20:01:10.013182 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9949 20:01:10.016043 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9950 20:01:10.022964 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9951 20:01:10.026117 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9952 20:01:10.032582 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9953 20:01:10.036031 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9954 20:01:10.042756 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9955 20:01:10.045878 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9956 20:01:10.050081 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9957 20:01:10.056433 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9958 20:01:10.059306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9959 20:01:10.065613 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9960 20:01:10.069024 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9961 20:01:10.075554 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9962 20:01:10.079152 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9963 20:01:10.082478 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9964 20:01:10.089295 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9965 20:01:10.092322 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9966 20:01:10.098815 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9967 20:01:10.102174 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9968 20:01:10.109080 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9969 20:01:10.112259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9970 20:01:10.119172 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9971 20:01:10.122132 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9972 20:01:10.125243 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9973 20:01:10.132377 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9974 20:01:10.134694 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9975 20:01:10.142049 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9976 20:01:10.144962 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9977 20:01:10.151621 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9978 20:01:10.154972 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9979 20:01:10.161450 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9980 20:01:10.165187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9981 20:01:10.167876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9982 20:01:10.174598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9983 20:01:10.177709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9984 20:01:10.184666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9985 20:01:10.187804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9986 20:01:10.195184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9987 20:01:10.198015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9988 20:01:10.203948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9989 20:01:10.208000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9990 20:01:10.214427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9991 20:01:10.217045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9992 20:01:10.223803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9993 20:01:10.227287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9994 20:01:10.234552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9995 20:01:10.236866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9996 20:01:10.243595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9997 20:01:10.246860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9998 20:01:10.253733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9999 20:01:10.256842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10000 20:01:10.264036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10001 20:01:10.267350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10002 20:01:10.273315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10003 20:01:10.276962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10004 20:01:10.283896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10005 20:01:10.287184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10006 20:01:10.293768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10007 20:01:10.296876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10008 20:01:10.303061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10009 20:01:10.306310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10010 20:01:10.313057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10011 20:01:10.316196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10012 20:01:10.319438 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10013 20:01:10.322890 INFO: [APUAPC] vio 0
10014 20:01:10.329907 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10015 20:01:10.332724 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10016 20:01:10.335865 INFO: [APUAPC] D0_APC_0: 0x400510
10017 20:01:10.339443 INFO: [APUAPC] D0_APC_1: 0x0
10018 20:01:10.342947 INFO: [APUAPC] D0_APC_2: 0x1540
10019 20:01:10.346504 INFO: [APUAPC] D0_APC_3: 0x0
10020 20:01:10.349262 INFO: [APUAPC] D1_APC_0: 0xffffffff
10021 20:01:10.352855 INFO: [APUAPC] D1_APC_1: 0xffffffff
10022 20:01:10.355901 INFO: [APUAPC] D1_APC_2: 0x3fffff
10023 20:01:10.359123 INFO: [APUAPC] D1_APC_3: 0x0
10024 20:01:10.362471 INFO: [APUAPC] D2_APC_0: 0xffffffff
10025 20:01:10.366320 INFO: [APUAPC] D2_APC_1: 0xffffffff
10026 20:01:10.369386 INFO: [APUAPC] D2_APC_2: 0x3fffff
10027 20:01:10.372666 INFO: [APUAPC] D2_APC_3: 0x0
10028 20:01:10.375711 INFO: [APUAPC] D3_APC_0: 0xffffffff
10029 20:01:10.379006 INFO: [APUAPC] D3_APC_1: 0xffffffff
10030 20:01:10.382401 INFO: [APUAPC] D3_APC_2: 0x3fffff
10031 20:01:10.385695 INFO: [APUAPC] D3_APC_3: 0x0
10032 20:01:10.388762 INFO: [APUAPC] D4_APC_0: 0xffffffff
10033 20:01:10.392682 INFO: [APUAPC] D4_APC_1: 0xffffffff
10034 20:01:10.395345 INFO: [APUAPC] D4_APC_2: 0x3fffff
10035 20:01:10.399038 INFO: [APUAPC] D4_APC_3: 0x0
10036 20:01:10.401745 INFO: [APUAPC] D5_APC_0: 0xffffffff
10037 20:01:10.405686 INFO: [APUAPC] D5_APC_1: 0xffffffff
10038 20:01:10.409096 INFO: [APUAPC] D5_APC_2: 0x3fffff
10039 20:01:10.409652 INFO: [APUAPC] D5_APC_3: 0x0
10040 20:01:10.415601 INFO: [APUAPC] D6_APC_0: 0xffffffff
10041 20:01:10.418639 INFO: [APUAPC] D6_APC_1: 0xffffffff
10042 20:01:10.421795 INFO: [APUAPC] D6_APC_2: 0x3fffff
10043 20:01:10.422349 INFO: [APUAPC] D6_APC_3: 0x0
10044 20:01:10.425682 INFO: [APUAPC] D7_APC_0: 0xffffffff
10045 20:01:10.431684 INFO: [APUAPC] D7_APC_1: 0xffffffff
10046 20:01:10.434847 INFO: [APUAPC] D7_APC_2: 0x3fffff
10047 20:01:10.435303 INFO: [APUAPC] D7_APC_3: 0x0
10048 20:01:10.438267 INFO: [APUAPC] D8_APC_0: 0xffffffff
10049 20:01:10.444981 INFO: [APUAPC] D8_APC_1: 0xffffffff
10050 20:01:10.448092 INFO: [APUAPC] D8_APC_2: 0x3fffff
10051 20:01:10.448563 INFO: [APUAPC] D8_APC_3: 0x0
10052 20:01:10.451434 INFO: [APUAPC] D9_APC_0: 0xffffffff
10053 20:01:10.455518 INFO: [APUAPC] D9_APC_1: 0xffffffff
10054 20:01:10.458259 INFO: [APUAPC] D9_APC_2: 0x3fffff
10055 20:01:10.461270 INFO: [APUAPC] D9_APC_3: 0x0
10056 20:01:10.464392 INFO: [APUAPC] D10_APC_0: 0xffffffff
10057 20:01:10.468179 INFO: [APUAPC] D10_APC_1: 0xffffffff
10058 20:01:10.471104 INFO: [APUAPC] D10_APC_2: 0x3fffff
10059 20:01:10.474571 INFO: [APUAPC] D10_APC_3: 0x0
10060 20:01:10.478073 INFO: [APUAPC] D11_APC_0: 0xffffffff
10061 20:01:10.484394 INFO: [APUAPC] D11_APC_1: 0xffffffff
10062 20:01:10.487232 INFO: [APUAPC] D11_APC_2: 0x3fffff
10063 20:01:10.487688 INFO: [APUAPC] D11_APC_3: 0x0
10064 20:01:10.491194 INFO: [APUAPC] D12_APC_0: 0xffffffff
10065 20:01:10.499102 INFO: [APUAPC] D12_APC_1: 0xffffffff
10066 20:01:10.500543 INFO: [APUAPC] D12_APC_2: 0x3fffff
10067 20:01:10.501002 INFO: [APUAPC] D12_APC_3: 0x0
10068 20:01:10.507688 INFO: [APUAPC] D13_APC_0: 0xffffffff
10069 20:01:10.510723 INFO: [APUAPC] D13_APC_1: 0xffffffff
10070 20:01:10.513702 INFO: [APUAPC] D13_APC_2: 0x3fffff
10071 20:01:10.517007 INFO: [APUAPC] D13_APC_3: 0x0
10072 20:01:10.520983 INFO: [APUAPC] D14_APC_0: 0xffffffff
10073 20:01:10.524026 INFO: [APUAPC] D14_APC_1: 0xffffffff
10074 20:01:10.527972 INFO: [APUAPC] D14_APC_2: 0x3fffff
10075 20:01:10.530395 INFO: [APUAPC] D14_APC_3: 0x0
10076 20:01:10.534254 INFO: [APUAPC] D15_APC_0: 0xffffffff
10077 20:01:10.537003 INFO: [APUAPC] D15_APC_1: 0xffffffff
10078 20:01:10.540195 INFO: [APUAPC] D15_APC_2: 0x3fffff
10079 20:01:10.543787 INFO: [APUAPC] D15_APC_3: 0x0
10080 20:01:10.544298 INFO: [APUAPC] APC_CON: 0x4
10081 20:01:10.547268 INFO: [NOCDAPC] D0_APC_0: 0x0
10082 20:01:10.550670 INFO: [NOCDAPC] D0_APC_1: 0x0
10083 20:01:10.553841 INFO: [NOCDAPC] D1_APC_0: 0x0
10084 20:01:10.557173 INFO: [NOCDAPC] D1_APC_1: 0xfff
10085 20:01:10.559813 INFO: [NOCDAPC] D2_APC_0: 0x0
10086 20:01:10.563484 INFO: [NOCDAPC] D2_APC_1: 0xfff
10087 20:01:10.567106 INFO: [NOCDAPC] D3_APC_0: 0x0
10088 20:01:10.570206 INFO: [NOCDAPC] D3_APC_1: 0xfff
10089 20:01:10.573640 INFO: [NOCDAPC] D4_APC_0: 0x0
10090 20:01:10.576709 INFO: [NOCDAPC] D4_APC_1: 0xfff
10091 20:01:10.577127 INFO: [NOCDAPC] D5_APC_0: 0x0
10092 20:01:10.580502 INFO: [NOCDAPC] D5_APC_1: 0xfff
10093 20:01:10.583464 INFO: [NOCDAPC] D6_APC_0: 0x0
10094 20:01:10.586641 INFO: [NOCDAPC] D6_APC_1: 0xfff
10095 20:01:10.589863 INFO: [NOCDAPC] D7_APC_0: 0x0
10096 20:01:10.593586 INFO: [NOCDAPC] D7_APC_1: 0xfff
10097 20:01:10.596656 INFO: [NOCDAPC] D8_APC_0: 0x0
10098 20:01:10.600069 INFO: [NOCDAPC] D8_APC_1: 0xfff
10099 20:01:10.603153 INFO: [NOCDAPC] D9_APC_0: 0x0
10100 20:01:10.606533 INFO: [NOCDAPC] D9_APC_1: 0xfff
10101 20:01:10.609799 INFO: [NOCDAPC] D10_APC_0: 0x0
10102 20:01:10.613067 INFO: [NOCDAPC] D10_APC_1: 0xfff
10103 20:01:10.613579 INFO: [NOCDAPC] D11_APC_0: 0x0
10104 20:01:10.616555 INFO: [NOCDAPC] D11_APC_1: 0xfff
10105 20:01:10.619763 INFO: [NOCDAPC] D12_APC_0: 0x0
10106 20:01:10.623376 INFO: [NOCDAPC] D12_APC_1: 0xfff
10107 20:01:10.626445 INFO: [NOCDAPC] D13_APC_0: 0x0
10108 20:01:10.629550 INFO: [NOCDAPC] D13_APC_1: 0xfff
10109 20:01:10.633058 INFO: [NOCDAPC] D14_APC_0: 0x0
10110 20:01:10.636123 INFO: [NOCDAPC] D14_APC_1: 0xfff
10111 20:01:10.639273 INFO: [NOCDAPC] D15_APC_0: 0x0
10112 20:01:10.642452 INFO: [NOCDAPC] D15_APC_1: 0xfff
10113 20:01:10.646207 INFO: [NOCDAPC] APC_CON: 0x4
10114 20:01:10.649587 INFO: [APUAPC] set_apusys_apc done
10115 20:01:10.653048 INFO: [DEVAPC] devapc_init done
10116 20:01:10.655847 INFO: GICv3 without legacy support detected.
10117 20:01:10.658849 INFO: ARM GICv3 driver initialized in EL3
10118 20:01:10.662636 INFO: Maximum SPI INTID supported: 639
10119 20:01:10.669072 INFO: BL31: Initializing runtime services
10120 20:01:10.672067 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10121 20:01:10.675601 INFO: SPM: enable CPC mode
10122 20:01:10.681734 INFO: mcdi ready for mcusys-off-idle and system suspend
10123 20:01:10.685308 INFO: BL31: Preparing for EL3 exit to normal world
10124 20:01:10.688309 INFO: Entry point address = 0x80000000
10125 20:01:10.691983 INFO: SPSR = 0x8
10126 20:01:10.698072
10127 20:01:10.698582
10128 20:01:10.698916
10129 20:01:10.700491 Starting depthcharge on Spherion...
10130 20:01:10.700902
10131 20:01:10.701229 Wipe memory regions:
10132 20:01:10.701537
10133 20:01:10.704198 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10134 20:01:10.704791 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10135 20:01:10.705186 Setting prompt string to ['asurada:']
10136 20:01:10.705585 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10137 20:01:10.706224 [0x00000040000000, 0x00000054600000)
10138 20:01:10.826384
10139 20:01:10.826936 [0x00000054660000, 0x00000080000000)
10140 20:01:11.087239
10141 20:01:11.087829 [0x000000821a7280, 0x000000ffe64000)
10142 20:01:11.832062
10143 20:01:11.832613 [0x00000100000000, 0x00000240000000)
10144 20:01:13.723062
10145 20:01:13.725910 Initializing XHCI USB controller at 0x11200000.
10146 20:01:14.706736
10147 20:01:14.706980 R8152: Initializing
10148 20:01:14.707112
10149 20:01:14.709854 Version 9 (ocp_data = 6010)
10150 20:01:14.710041
10151 20:01:14.713169 R8152: Done initializing
10152 20:01:14.713406
10153 20:01:14.713583 Adding net device
10154 20:01:15.236090
10155 20:01:15.239293 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10156 20:01:15.239902
10157 20:01:15.240276
10158 20:01:15.240616
10159 20:01:15.241431 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10161 20:01:15.342721 asurada: tftpboot 192.168.201.1 11899622/tftp-deploy-rghlf70a/kernel/image.itb 11899622/tftp-deploy-rghlf70a/kernel/cmdline
10162 20:01:15.343403 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10163 20:01:15.343923 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10164 20:01:15.349102 tftpboot 192.168.201.1 11899622/tftp-deploy-rghlf70a/kernel/image.ittp-deploy-rghlf70a/kernel/cmdline
10165 20:01:15.349670
10166 20:01:15.350036 Waiting for link
10167 20:01:15.550734
10168 20:01:15.551296 done.
10169 20:01:15.551852
10170 20:01:15.552219 MAC: f4:f5:e8:50:de:0a
10171 20:01:15.552556
10172 20:01:15.553779 Sending DHCP discover... done.
10173 20:01:15.554238
10174 20:01:15.557184 Waiting for reply... done.
10175 20:01:15.557646
10176 20:01:15.560619 Sending DHCP request... done.
10177 20:01:15.561082
10178 20:01:15.561448 Waiting for reply... done.
10179 20:01:15.563837
10180 20:01:15.564295 My ip is 192.168.201.14
10181 20:01:15.564784
10182 20:01:15.567340 The DHCP server ip is 192.168.201.1
10183 20:01:15.567989
10184 20:01:15.570632 TFTP server IP predefined by user: 192.168.201.1
10185 20:01:15.571205
10186 20:01:15.577120 Bootfile predefined by user: 11899622/tftp-deploy-rghlf70a/kernel/image.itb
10187 20:01:15.577761
10188 20:01:15.580705 Sending tftp read request... done.
10189 20:01:15.581267
10190 20:01:15.589587 Waiting for the transfer...
10191 20:01:15.590052
10192 20:01:15.870095 00000000 ################################################################
10193 20:01:15.870276
10194 20:01:16.119319 00080000 ################################################################
10195 20:01:16.119466
10196 20:01:16.354810 00100000 ################################################################
10197 20:01:16.354972
10198 20:01:16.591564 00180000 ################################################################
10199 20:01:16.591702
10200 20:01:16.843358 00200000 ################################################################
10201 20:01:16.843524
10202 20:01:17.103890 00280000 ################################################################
10203 20:01:17.104032
10204 20:01:17.333999 00300000 ################################################################
10205 20:01:17.334162
10206 20:01:17.561930 00380000 ################################################################
10207 20:01:17.562064
10208 20:01:17.794616 00400000 ################################################################
10209 20:01:17.794751
10210 20:01:18.028920 00480000 ################################################################
10211 20:01:18.029085
10212 20:01:18.268223 00500000 ################################################################
10213 20:01:18.268367
10214 20:01:18.498430 00580000 ################################################################
10215 20:01:18.498593
10216 20:01:18.736028 00600000 ################################################################
10217 20:01:18.736183
10218 20:01:18.988899 00680000 ################################################################
10219 20:01:18.989046
10220 20:01:19.224372 00700000 ################################################################
10221 20:01:19.224517
10222 20:01:19.471207 00780000 ################################################################
10223 20:01:19.471352
10224 20:01:19.718750 00800000 ################################################################
10225 20:01:19.718886
10226 20:01:19.965148 00880000 ################################################################
10227 20:01:19.965285
10228 20:01:20.196442 00900000 ################################################################
10229 20:01:20.196606
10230 20:01:20.436683 00980000 ################################################################
10231 20:01:20.436827
10232 20:01:20.687854 00a00000 ################################################################
10233 20:01:20.687994
10234 20:01:20.920764 00a80000 ################################################################
10235 20:01:20.920903
10236 20:01:21.187805 00b00000 ################################################################
10237 20:01:21.187948
10238 20:01:21.449203 00b80000 ################################################################
10239 20:01:21.449342
10240 20:01:21.716211 00c00000 ################################################################
10241 20:01:21.716353
10242 20:01:21.949600 00c80000 ################################################################
10243 20:01:21.949735
10244 20:01:22.215316 00d00000 ################################################################
10245 20:01:22.215457
10246 20:01:22.487169 00d80000 ################################################################
10247 20:01:22.487309
10248 20:01:22.730588 00e00000 ################################################################
10249 20:01:22.730731
10250 20:01:22.994405 00e80000 ################################################################
10251 20:01:22.994546
10252 20:01:23.258824 00f00000 ################################################################
10253 20:01:23.258970
10254 20:01:23.527345 00f80000 ################################################################
10255 20:01:23.527485
10256 20:01:23.793757 01000000 ################################################################
10257 20:01:23.793902
10258 20:01:24.066190 01080000 ################################################################
10259 20:01:24.066329
10260 20:01:24.333010 01100000 ################################################################
10261 20:01:24.333156
10262 20:01:24.582869 01180000 ################################################################
10263 20:01:24.583004
10264 20:01:24.849228 01200000 ################################################################
10265 20:01:24.849372
10266 20:01:25.116622 01280000 ################################################################
10267 20:01:25.116759
10268 20:01:25.390059 01300000 ################################################################
10269 20:01:25.390194
10270 20:01:25.660059 01380000 ################################################################
10271 20:01:25.660204
10272 20:01:25.926011 01400000 ################################################################
10273 20:01:25.926162
10274 20:01:26.167243 01480000 ################################################################
10275 20:01:26.167387
10276 20:01:26.418497 01500000 ################################################################
10277 20:01:26.418639
10278 20:01:26.673944 01580000 ################################################################
10279 20:01:26.674087
10280 20:01:26.908158 01600000 ################################################################
10281 20:01:26.908300
10282 20:01:27.140699 01680000 ################################################################
10283 20:01:27.140839
10284 20:01:27.368852 01700000 ################################################################
10285 20:01:27.368988
10286 20:01:27.616364 01780000 ################################################################
10287 20:01:27.616502
10288 20:01:27.848937 01800000 ################################################################
10289 20:01:27.849069
10290 20:01:28.078282 01880000 ################################################################
10291 20:01:28.078424
10292 20:01:28.308797 01900000 ################################################################
10293 20:01:28.308942
10294 20:01:28.548488 01980000 ################################################################
10295 20:01:28.548625
10296 20:01:28.810734 01a00000 ################################################################
10297 20:01:28.810872
10298 20:01:29.039114 01a80000 ################################################################
10299 20:01:29.039285
10300 20:01:29.277194 01b00000 ################################################################
10301 20:01:29.277339
10302 20:01:29.507559 01b80000 ################################################################
10303 20:01:29.507719
10304 20:01:29.729671 01c00000 ############################################################# done.
10305 20:01:29.729806
10306 20:01:29.733306 The bootfile was 29858082 bytes long.
10307 20:01:29.733397
10308 20:01:29.733467 Sending tftp read request... done.
10309 20:01:29.736340
10310 20:01:29.736427 Waiting for the transfer...
10311 20:01:29.736497
10312 20:01:29.739621 00000000 # done.
10313 20:01:29.739716
10314 20:01:29.746369 Command line loaded dynamically from TFTP file: 11899622/tftp-deploy-rghlf70a/kernel/cmdline
10315 20:01:29.746548
10316 20:01:29.770716 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11899622/extract-nfsrootfs-dl4xqeyi,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10317 20:01:29.770978
10318 20:01:29.771128 Loading FIT.
10319 20:01:29.771309
10320 20:01:29.772908 Image ramdisk-1 has 18761246 bytes.
10321 20:01:29.773083
10322 20:01:29.776090 Image fdt-1 has 47278 bytes.
10323 20:01:29.776377
10324 20:01:29.779599 Image kernel-1 has 11047522 bytes.
10325 20:01:29.779976
10326 20:01:29.789939 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10327 20:01:29.790422
10328 20:01:29.806147 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10329 20:01:29.806732
10330 20:01:29.812361 Choosing best match conf-1 for compat google,spherion-rev2.
10331 20:01:29.812825
10332 20:01:29.819955 Connected to device vid:did:rid of 1ae0:0028:00
10333 20:01:29.826616
10334 20:01:29.829969 tpm_get_response: command 0x17b, return code 0x0
10335 20:01:29.830552
10336 20:01:29.836612 ec_init: CrosEC protocol v3 supported (256, 248)
10337 20:01:29.837175
10338 20:01:29.840106 tpm_cleanup: add release locality here.
10339 20:01:29.840666
10340 20:01:29.843189 Shutting down all USB controllers.
10341 20:01:29.843772
10342 20:01:29.846647 Removing current net device
10343 20:01:29.847198
10344 20:01:29.850164 Exiting depthcharge with code 4 at timestamp: 48563582
10345 20:01:29.850719
10346 20:01:29.852868 LZMA decompressing kernel-1 to 0x821a6718
10347 20:01:29.856545
10348 20:01:29.860007 LZMA decompressing kernel-1 to 0x40000000
10349 20:01:31.247872
10350 20:01:31.248440 jumping to kernel
10351 20:01:31.250130 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10352 20:01:31.250666 start: 2.2.5 auto-login-action (timeout 00:04:05) [common]
10353 20:01:31.251076 Setting prompt string to ['Linux version [0-9]']
10354 20:01:31.251462 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10355 20:01:31.251912 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10356 20:01:31.329061
10357 20:01:31.332182 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10358 20:01:31.336076 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10359 20:01:31.336586 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10360 20:01:31.336985 Setting prompt string to []
10361 20:01:31.337406 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10362 20:01:31.337801 Using line separator: #'\n'#
10363 20:01:31.338189 No login prompt set.
10364 20:01:31.338611 Parsing kernel messages
10365 20:01:31.338956 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10366 20:01:31.339540 [login-action] Waiting for messages, (timeout 00:04:04)
10367 20:01:31.355423 [ 0.000000] Linux version 6.1.59-cip8-rt4 (KernelCI@build-j84202-arm64-gcc-10-defconfig-arm64-chromebook-st8dj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023
10368 20:01:31.358335 [ 0.000000] random: crng init done
10369 20:01:31.364898 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10370 20:01:31.368191 [ 0.000000] efi: UEFI not found.
10371 20:01:31.374950 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10372 20:01:31.385182 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10373 20:01:31.395134 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10374 20:01:31.401646 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10375 20:01:31.408272 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10376 20:01:31.414750 [ 0.000000] printk: bootconsole [mtk8250] enabled
10377 20:01:31.421690 [ 0.000000] NUMA: No NUMA configuration found
10378 20:01:31.427908 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10379 20:01:31.435134 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10380 20:01:31.435694 [ 0.000000] Zone ranges:
10381 20:01:31.441120 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10382 20:01:31.444527 [ 0.000000] DMA32 empty
10383 20:01:31.451478 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10384 20:01:31.454167 [ 0.000000] Movable zone start for each node
10385 20:01:31.457756 [ 0.000000] Early memory node ranges
10386 20:01:31.464678 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10387 20:01:31.471228 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10388 20:01:31.477205 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10389 20:01:31.484512 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10390 20:01:31.490968 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10391 20:01:31.497386 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10392 20:01:31.553765 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10393 20:01:31.560368 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10394 20:01:31.566796 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10395 20:01:31.570247 [ 0.000000] psci: probing for conduit method from DT.
10396 20:01:31.577367 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10397 20:01:31.580180 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10398 20:01:31.586497 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10399 20:01:31.589847 [ 0.000000] psci: SMC Calling Convention v1.2
10400 20:01:31.596529 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10401 20:01:31.599888 [ 0.000000] Detected VIPT I-cache on CPU0
10402 20:01:31.606312 [ 0.000000] CPU features: detected: GIC system register CPU interface
10403 20:01:31.612991 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10404 20:01:31.619890 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10405 20:01:31.626169 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10406 20:01:31.636825 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10407 20:01:31.642981 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10408 20:01:31.646181 [ 0.000000] alternatives: applying boot alternatives
10409 20:01:31.652712 [ 0.000000] Fallback order for Node 0: 0
10410 20:01:31.659460 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10411 20:01:31.663539 [ 0.000000] Policy zone: Normal
10412 20:01:31.686082 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11899622/extract-nfsrootfs-dl4xqeyi,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10413 20:01:31.695355 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10414 20:01:31.707400 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10415 20:01:31.716809 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10416 20:01:31.722992 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10417 20:01:31.726863 <6>[ 0.000000] software IO TLB: area num 8.
10418 20:01:31.782902 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10419 20:01:31.932259 <6>[ 0.000000] Memory: 7951104K/8385536K available (17984K kernel code, 4116K rwdata, 17476K rodata, 8448K init, 615K bss, 401664K reserved, 32768K cma-reserved)
10420 20:01:31.938982 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10421 20:01:31.945404 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10422 20:01:31.948661 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10423 20:01:31.955211 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10424 20:01:31.961944 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10425 20:01:31.965536 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10426 20:01:31.975075 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10427 20:01:31.982171 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10428 20:01:31.988127 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10429 20:01:31.995157 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10430 20:01:31.998503 <6>[ 0.000000] GICv3: 608 SPIs implemented
10431 20:01:32.001713 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10432 20:01:32.008382 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10433 20:01:32.012135 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10434 20:01:32.018043 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10435 20:01:32.031632 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10436 20:01:32.044225 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10437 20:01:32.051282 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10438 20:01:32.058721 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10439 20:01:32.072288 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10440 20:01:32.079482 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10441 20:01:32.085681 <6>[ 0.009234] Console: colour dummy device 80x25
10442 20:01:32.095190 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10443 20:01:32.101781 <6>[ 0.024402] pid_max: default: 32768 minimum: 301
10444 20:01:32.105229 <6>[ 0.029274] LSM: Security Framework initializing
10445 20:01:32.112442 <6>[ 0.034214] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10446 20:01:32.121948 <6>[ 0.042076] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10447 20:01:32.132222 <6>[ 0.051497] cblist_init_generic: Setting adjustable number of callback queues.
10448 20:01:32.134595 <6>[ 0.058941] cblist_init_generic: Setting shift to 3 and lim to 1.
10449 20:01:32.145151 <6>[ 0.065318] cblist_init_generic: Setting adjustable number of callback queues.
10450 20:01:32.151557 <6>[ 0.072745] cblist_init_generic: Setting shift to 3 and lim to 1.
10451 20:01:32.154938 <6>[ 0.079223] rcu: Hierarchical SRCU implementation.
10452 20:01:32.161101 <6>[ 0.079225] rcu: Max phase no-delay instances is 1000.
10453 20:01:32.167718 <6>[ 0.079250] printk: bootconsole [mtk8250] printing thread started
10454 20:01:32.174518 <6>[ 0.097536] EFI services will not be available.
10455 20:01:32.177866 <6>[ 0.097738] smp: Bringing up secondary CPUs ...
10456 20:01:32.184287 <6>[ 0.098046] Detected VIPT I-cache on CPU1
10457 20:01:32.191580 <6>[ 0.098115] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10458 20:01:32.198005 <6>[ 0.098145] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10459 20:01:32.207298 <6>[ 0.126023] Detected VIPT I-cache on CPU2
10460 20:01:32.214126 <6>[ 0.126075] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10461 20:01:32.224607 <6>[ 0.126091] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10462 20:01:32.227068 <6>[ 0.126351] Detected VIPT I-cache on CPU3
10463 20:01:32.232984 <6>[ 0.126397] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10464 20:01:32.239812 <6>[ 0.126411] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10465 20:01:32.243635 <6>[ 0.126719] CPU features: detected: Spectre-v4
10466 20:01:32.250029 <6>[ 0.126726] CPU features: detected: Spectre-BHB
10467 20:01:32.253258 <6>[ 0.126730] Detected PIPT I-cache on CPU4
10468 20:01:32.259853 <6>[ 0.126788] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10469 20:01:32.266107 <6>[ 0.126806] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10470 20:01:32.273168 <6>[ 0.127102] Detected PIPT I-cache on CPU5
10471 20:01:32.279807 <6>[ 0.127163] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10472 20:01:32.286245 <6>[ 0.127180] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10473 20:01:32.289279 <6>[ 0.127455] Detected PIPT I-cache on CPU6
10474 20:01:32.299902 <6>[ 0.127518] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10475 20:01:32.306134 <6>[ 0.127534] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10476 20:01:32.309368 <6>[ 0.127826] Detected PIPT I-cache on CPU7
10477 20:01:32.316135 <6>[ 0.127890] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10478 20:01:32.322449 <6>[ 0.127906] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10479 20:01:32.328712 <6>[ 0.127952] smp: Brought up 1 node, 8 CPUs
10480 20:01:32.332235 <6>[ 0.127957] SMP: Total of 8 processors activated.
10481 20:01:32.338825 <6>[ 0.127959] CPU features: detected: 32-bit EL0 Support
10482 20:01:32.345043 <6>[ 0.127961] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10483 20:01:32.351875 <6>[ 0.127964] CPU features: detected: Common not Private translations
10484 20:01:32.358772 <6>[ 0.127965] CPU features: detected: CRC32 instructions
10485 20:01:32.365286 <6>[ 0.127968] CPU features: detected: RCpc load-acquire (LDAPR)
10486 20:01:32.368510 <6>[ 0.127970] CPU features: detected: LSE atomic instructions
10487 20:01:32.375005 <6>[ 0.127971] CPU features: detected: Privileged Access Never
10488 20:01:32.381804 <6>[ 0.127973] CPU features: detected: RAS Extension Support
10489 20:01:32.387824 <6>[ 0.127976] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10490 20:01:32.391081 <6>[ 0.128043] CPU: All CPU(s) started at EL2
10491 20:01:32.397850 <6>[ 0.128045] alternatives: applying system-wide alternatives
10492 20:01:32.420474 �n.6.0
10493 20:01:32.426669 <6>[ 0.34<8457] printk: console [ttyS0] printing thread started
10494 20:01:32.433667 6>[ 0.225532] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10495 20:01:32.441218 <6>[ 0.348466] printk: console [ttyS0] enabled
10496 20:01:32.444786 <6>[ 0.348469] printk: bootconsole [mtk8250] disabled
10497 20:01:32.451541 <6>[ 0.361439] printk: bootconsole [mtk8250] printing thread stopped
10498 20:01:32.457754 <6>[ 0.362726] SuperH (H)SCI(F) driver initialized
10499 20:01:32.461560 <6>[ 0.363217] msm_serial: driver initialized
10500 20:01:32.470803 <6>[ 0.367919] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10501 20:01:32.477448 <6>[ 0.367947] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10502 20:01:32.485783 <6>[ 0.367977] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10503 20:01:32.497030 <6>[ 0.368006] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10504 20:01:32.509499 <6>[ 0.368027] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10505 20:01:32.529949 <6>[ 0.368054] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10506 20:01:32.531318 <6>[ 0.368082] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10507 20:01:32.531775 <6>[ 0.368200] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10508 20:01:32.545159 <6>[ 0.368230] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10509 20:01:32.551252 <6>[ 0.378646] loop: module loaded
10510 20:01:32.552605 <6>[ 0.381263] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10511 20:01:32.555276 <4>[ 0.398248] mtk-pmic-keys: Failed to locate of_node [id: -1]
10512 20:01:32.558462 <6>[ 0.399169] megasas: 07.719.03.00-rc1
10513 20:01:32.564605 <6>[ 0.408792] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10514 20:01:32.571293 <6>[ 0.412804] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10515 20:01:32.578156 <6>[ 0.424812] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10516 20:01:32.587905 <6>[ 0.482683] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10517 20:01:33.097240 <6>[ 1.018418] Freeing initrd memory: 18320K
10518 20:01:33.105454 <6>[ 1.025682] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10519 20:01:33.111901 <6>[ 1.030185] tun: Universal TUN/TAP device driver, 1.6
10520 20:01:33.115465 <6>[ 1.030940] thunder_xcv, ver 1.0
10521 20:01:33.118545 <6>[ 1.030957] thunder_bgx, ver 1.0
10522 20:01:33.121972 <6>[ 1.030971] nicpf, ver 1.0
10523 20:01:33.128206 <6>[ 1.032021] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10524 20:01:33.134900 <6>[ 1.032024] hns3: Copyright (c) 2017 Huawei Corporation.
10525 20:01:33.137972 <6>[ 1.032049] hclge is initializing
10526 20:01:33.142244 <6>[ 1.032063] e1000: Intel(R) PRO/1000 Network Driver
10527 20:01:33.149949 <6>[ 1.032065] e1000: Copyright (c) 1999-2006 Intel Corporation.
10528 20:01:33.156414 <6>[ 1.032082] e1000e: Intel(R) PRO/1000 Network Driver
10529 20:01:33.159681 <6>[ 1.032083] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10530 20:01:33.166395 <6>[ 1.032101] igb: Intel(R) Gigabit Ethernet Network Driver
10531 20:01:33.172962 <6>[ 1.032103] igb: Copyright (c) 2007-2014 Intel Corporation.
10532 20:01:33.180419 <6>[ 1.032117] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10533 20:01:33.183807 <6>[ 1.032119] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10534 20:01:33.190449 <6>[ 1.032412] sky2: driver version 1.30
10535 20:01:33.194182 <6>[ 1.033486] VFIO - User Level meta-driver version: 0.3
10536 20:01:33.200321 <6>[ 1.036335] usbcore: registered new interface driver usb-storage
10537 20:01:33.207236 <6>[ 1.036513] usbcore: registered new device driver onboard-usb-hub
10538 20:01:33.213715 <6>[ 1.039280] mt6397-rtc mt6359-rtc: registered as rtc0
10539 20:01:33.220162 <6>[ 1.039433] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-28T20:01:33 UTC (1698523293)
10540 20:01:33.226857 <6>[ 1.040046] i2c_dev: i2c /dev entries driver
10541 20:01:33.233439 <6>[ 1.047147] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10542 20:01:33.240420 <6>[ 1.062136] cpu cpu0: EM: created perf domain
10543 20:01:33.243072 <6>[ 1.062440] cpu cpu4: EM: created perf domain
10544 20:01:33.249908 <6>[ 1.064090] sdhci: Secure Digital Host Controller Interface driver
10545 20:01:33.253521 <6>[ 1.064091] sdhci: Copyright(c) Pierre Ossman
10546 20:01:33.259829 <6>[ 1.064448] Synopsys Designware Multimedia Card Interface Driver
10547 20:01:33.266335 <6>[ 1.064814] sdhci-pltfm: SDHCI platform and OF driver helper
10548 20:01:33.273125 <6>[ 1.067498] ledtrig-cpu: registered to indicate activity on CPUs
10549 20:01:33.275899 <6>[ 1.068096] mmc0: CQHCI version 5.10
10550 20:01:33.283033 <6>[ 1.068146] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10551 20:01:33.289479 <6>[ 1.068414] usbcore: registered new interface driver usbhid
10552 20:01:33.292736 <6>[ 1.068415] usbhid: USB HID core driver
10553 20:01:33.299296 <6>[ 1.068538] spi_master spi0: will run message pump with realtime priority
10554 20:01:33.312561 <6>[ 1.103488] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10555 20:01:33.325674 <6>[ 1.105711] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10556 20:01:33.332295 <6>[ 1.106724] cros-ec-spi spi0.0: Chrome EC device registered
10557 20:01:33.343003 <6>[ 1.128024] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10558 20:01:33.345776 <6>[ 1.130943] NET: Registered PF_PACKET protocol family
10559 20:01:33.352738 <6>[ 1.131055] 9pnet: Installing 9P2000 support
10560 20:01:33.355976 <5>[ 1.131101] Key type dns_resolver registered
10561 20:01:33.359178 <6>[ 1.131522] registered taskstats version 1
10562 20:01:33.365428 <5>[ 1.131540] Loading compiled-in X.509 certificates
10563 20:01:33.375475 <4>[ 1.147823] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10564 20:01:33.385481 <4>[ 1.148092] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 20:01:33.392180 <3>[ 1.148112] debugfs: File 'uA_load' in directory '/' already present!
10566 20:01:33.398601 <3>[ 1.148124] debugfs: File 'min_uV' in directory '/' already present!
10567 20:01:33.405439 <3>[ 1.148131] debugfs: File 'max_uV' in directory '/' already present!
10568 20:01:33.412373 <3>[ 1.148137] debugfs: File 'constraint_flags' in directory '/' already present!
10569 20:01:33.422561 <3>[ 1.151603] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10570 20:01:33.428553 <6>[ 1.161734] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10571 20:01:33.431820 <6>[ 1.162363] xhci-mtk 11200000.usb: xHCI Host Controller
10572 20:01:33.441809 <6>[ 1.162376] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10573 20:01:33.451710 <6>[ 1.162578] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10574 20:01:33.454678 <6>[ 1.162614] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10575 20:01:33.461727 <6>[ 1.162687] xhci-mtk 11200000.usb: xHCI Host Controller
10576 20:01:33.468121 <6>[ 1.162690] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10577 20:01:33.478034 <6>[ 1.162695] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10578 20:01:33.481540 <6>[ 1.162873] mmc0: Command Queue Engine enabled
10579 20:01:33.488190 <6>[ 1.162888] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10580 20:01:33.491147 <6>[ 1.163115] hub 1-0:1.0: USB hub found
10581 20:01:33.494909 <6>[ 1.163147] hub 1-0:1.0: 1 port detected
10582 20:01:33.501275 <6>[ 1.163479] mmcblk0: mmc0:0001 DA4128 116 GiB
10583 20:01:33.507963 <6>[ 1.163669] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10584 20:01:33.515156 <6>[ 1.163910] hub 2-0:1.0: USB hub found
10585 20:01:33.517899 <6>[ 1.163930] hub 2-0:1.0: 1 port detected
10586 20:01:33.521278 <6>[ 1.167781] mtk-msdc 11f70000.mmc: Got CD GPIO
10587 20:01:33.528128 <6>[ 1.168840] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10588 20:01:33.534280 <6>[ 1.169835] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10589 20:01:33.537441 <6>[ 1.170617] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10590 20:01:33.544049 <6>[ 1.171315] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10591 20:01:33.553832 <6>[ 1.183450] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10592 20:01:33.561096 <6>[ 1.183459] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10593 20:01:33.570355 <4>[ 1.183625] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10594 20:01:33.577468 <6>[ 1.184257] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10595 20:01:33.587375 <6>[ 1.184260] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10596 20:01:33.593524 <6>[ 1.184390] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10597 20:01:33.600115 <6>[ 1.184401] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10598 20:01:33.610507 <6>[ 1.184405] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10599 20:01:33.617070 <6>[ 1.184414] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10600 20:01:33.626557 <6>[ 1.186163] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10601 20:01:33.637183 <6>[ 1.186181] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10602 20:01:33.643279 <6>[ 1.186187] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10603 20:01:33.653645 <6>[ 1.186194] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10604 20:01:33.659816 <6>[ 1.186200] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10605 20:01:33.669611 <6>[ 1.186206] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10606 20:01:33.676093 <6>[ 1.186212] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10607 20:01:33.686491 <6>[ 1.186218] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10608 20:01:33.692348 <6>[ 1.186224] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10609 20:01:33.702465 <6>[ 1.186230] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10610 20:01:33.709129 <6>[ 1.186237] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10611 20:01:33.719561 <6>[ 1.186243] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10612 20:01:33.725566 <6>[ 1.186249] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10613 20:01:33.735838 <6>[ 1.186255] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10614 20:01:33.742954 <6>[ 1.186260] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10615 20:01:33.749861 <6>[ 1.186765] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10616 20:01:33.755393 <6>[ 1.187641] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10617 20:01:33.762734 <6>[ 1.188212] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10618 20:01:33.768422 <6>[ 1.188857] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10619 20:01:33.775068 <6>[ 1.189531] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10620 20:01:33.784917 <6>[ 1.189773] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10621 20:01:33.795399 <6>[ 1.189786] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10622 20:01:33.804708 <6>[ 1.189791] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10623 20:01:33.814715 <6>[ 1.189797] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10624 20:01:33.821475 <6>[ 1.189802] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10625 20:01:33.830982 <6>[ 1.189812] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10626 20:01:33.841354 <6>[ 1.189819] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10627 20:01:33.851053 <6>[ 1.189824] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10628 20:01:33.861153 <6>[ 1.189828] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10629 20:01:33.870532 <6>[ 1.189835] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10630 20:01:33.881385 <6>[ 1.189841] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10631 20:01:33.887474 <6>[ 1.190871] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10632 20:01:33.893820 <6>[ 1.202039] Trying to probe devices needed for running init ...
10633 20:01:33.900675 <6>[ 1.581521] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10634 20:01:33.904068 <6>[ 1.734391] hub 1-1:1.0: USB hub found
10635 20:01:33.910049 <6>[ 1.734767] hub 1-1:1.0: 4 ports detected
10636 20:01:33.944555 <6>[ 1.861788] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10637 20:01:33.965300 <6>[ 1.887574] hub 2-1:1.0: USB hub found
10638 20:01:33.968663 <6>[ 1.888056] hub 2-1:1.0: 3 ports detected
10639 20:01:34.132865 <6>[ 2.049705] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10640 20:01:34.253870 <6>[ 2.175000] hub 1-1.1:1.0: USB hub found
10641 20:01:34.256834 <6>[ 2.175059] hub 1-1.1:1.0: 4 ports detected
10642 20:01:34.364701 <6>[ 2.281528] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10643 20:01:34.485596 <6>[ 2.408458] hub 1-1.4:1.0: USB hub found
10644 20:01:34.488749 <6>[ 2.408768] hub 1-1.4:1.0: 2 ports detected
10645 20:01:34.568778 <6>[ 2.485716] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10646 20:01:34.749080 <6>[ 2.665650] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10647 20:01:34.825316 <3>[ 2.745890] usb 1-1.1.4: device descriptor read/64, error -32
10648 20:01:35.013547 <3>[ 2.933792] usb 1-1.1.4: device descriptor read/64, error -32
10649 20:01:35.204612 <6>[ 3.121710] usb 1-1.1.4: new full-speed USB device number 7 using xhci-mtk
10650 20:01:35.281268 <3>[ 3.201898] usb 1-1.1.4: device descriptor read/64, error -32
10651 20:01:35.469100 <3>[ 3.389893] usb 1-1.1.4: device descriptor read/64, error -32
10652 20:01:35.577190 <6>[ 3.498224] usb 1-1.1-port4: attempt power cycle
10653 20:01:35.660543 <6>[ 3.577712] usb 1-1.4.1: new high-speed USB device number 8 using xhci-mtk
10654 20:01:35.844595 <6>[ 3.761649] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10655 20:01:36.232219 <6>[ 4.149771] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10656 20:01:36.238837 <4>[ 4.150021] usb 1-1.1.4: Device not responding to setup address.
10657 20:01:36.437201 <4>[ 4.357793] usb 1-1.1.4: Device not responding to setup address.
10658 20:01:36.644942 <3>[ 4.565723] usb 1-1.1.4: device not accepting address 10, error -71
10659 20:01:36.728587 <6>[ 4.645702] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10660 20:01:36.735400 <4>[ 4.645942] usb 1-1.1.4: Device not responding to setup address.
10661 20:01:36.934277 <4>[ 4.853979] usb 1-1.1.4: Device not responding to setup address.
10662 20:01:37.141248 <3>[ 5.061713] usb 1-1.1.4: device not accepting address 11, error -71
10663 20:01:37.148273 <3>[ 5.062256] usb 1-1.1-port4: unable to enumerate USB device
10664 20:01:45.549020 <6>[ 13.474676] ALSA device list:
10665 20:01:45.555409 <6>[ 13.474698] No soundcards found.
10666 20:01:45.558670 <6>[ 13.479071] Freeing unused kernel memory: 8448K
10667 20:01:45.565469 Loading, please <6>[ 13.479237] Run /init as init process
10668 20:01:45.566006 wait...
10669 20:01:45.589526 Starting systemd-udevd version 252.6-1
10670 20:01:45.822229 <6>[ 13.740227] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10671 20:01:45.826045 <6>[ 13.745125] remoteproc remoteproc0: scp is available
10672 20:01:45.834202 <6>[ 13.745243] remoteproc remoteproc0: powering up scp
10673 20:01:45.844020 <6>[ 13.745251] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10674 20:01:45.847436 <6>[ 13.745285] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10675 20:01:45.866994 <6>[ 13.786342] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10676 20:01:45.874111 <6>[ 13.786387] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10677 20:01:45.883644 <6>[ 13.786392] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10678 20:01:45.890868 <6>[ 13.799307] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10679 20:01:45.900928 <3>[ 13.800635] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 20:01:45.907460 <3>[ 13.800655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 20:01:45.917138 <3>[ 13.800661] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 20:01:45.924298 <3>[ 13.800858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 20:01:45.930435 <3>[ 13.800866] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 20:01:45.941081 <3>[ 13.800871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 20:01:45.948353 <3>[ 13.800877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 20:01:45.958288 <3>[ 13.800881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 20:01:45.964371 <3>[ 13.800923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 20:01:45.974434 <3>[ 13.801000] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 20:01:45.980868 <3>[ 13.801009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 20:01:45.991246 <3>[ 13.801013] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 20:01:45.996926 <3>[ 13.801036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 20:01:46.004289 <3>[ 13.801039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 20:01:46.013924 <3>[ 13.801041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 20:01:46.020447 <3>[ 13.801044] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 20:01:46.030419 <3>[ 13.801047] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 20:01:46.037013 <3>[ 13.801057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 20:01:46.043816 <6>[ 13.816569] mc: Linux media interface: v0.10
10698 20:01:46.046723 <6>[ 13.825304] usbcore: registered new interface driver r8152
10699 20:01:46.056703 <4>[ 13.828649] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10700 20:01:46.064065 <4>[ 13.828649] Fallback method does not support PEC.
10701 20:01:46.069896 <4>[ 13.829228] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10702 20:01:46.076650 <4>[ 13.829344] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10703 20:01:46.082938 <6>[ 13.842734] videodev: Linux video capture interface: v2.00
10704 20:01:46.089899 <3>[ 13.849983] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10705 20:01:46.096142 <6>[ 13.872537] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10706 20:01:46.106411 <3>[ 13.874727] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10707 20:01:46.116125 <6>[ 13.879138] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10708 20:01:46.122805 <6>[ 13.879177] remoteproc remoteproc0: remote processor scp is now up
10709 20:01:46.129274 <6>[ 13.888289] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10710 20:01:46.139291 <6>[ 13.890755] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10711 20:01:46.146486 <6>[ 13.906698] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10712 20:01:46.149354 <6>[ 13.906703] pci_bus 0000:00: root bus resource [bus 00-ff]
10713 20:01:46.159115 <6>[ 13.906707] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10714 20:01:46.168994 <6>[ 13.906710] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10715 20:01:46.175105 <6>[ 13.906738] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10716 20:01:46.182201 <6>[ 13.906751] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10717 20:01:46.185365 <6>[ 13.906819] pci 0000:00:00.0: supports D1 D2
10718 20:01:46.192014 <6>[ 13.906820] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10719 20:01:46.202186 <6>[ 13.907826] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10720 20:01:46.208300 <6>[ 13.907904] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10721 20:01:46.215375 <6>[ 13.907930] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10722 20:01:46.221732 <6>[ 13.907948] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10723 20:01:46.228555 <6>[ 13.907962] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10724 20:01:46.235089 <6>[ 13.908076] pci 0000:01:00.0: supports D1 D2
10725 20:01:46.241646 <6>[ 13.908078] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10726 20:01:46.248220 <6>[ 13.909790] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10727 20:01:46.254866 <6>[ 13.921557] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10728 20:01:46.264806 <6>[ 13.921603] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10729 20:01:46.271374 <6>[ 13.921607] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10730 20:01:46.278041 <6>[ 13.921616] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10731 20:01:46.287675 <6>[ 13.921630] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10732 20:01:46.294824 <6>[ 13.921642] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10733 20:01:46.300879 <6>[ 13.921655] pci 0000:00:00.0: PCI bridge to [bus 01]
10734 20:01:46.307540 <6>[ 13.921660] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10735 20:01:46.314581 <6>[ 13.921799] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10736 20:01:46.321086 <6>[ 13.922313] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10737 20:01:46.327427 <6>[ 13.922963] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10738 20:01:46.336992 <6>[ 13.930852] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10739 20:01:46.347416 <6>[ 13.931161] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10740 20:01:46.353607 <6>[ 13.936267] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10741 20:01:46.363491 <5>[ 13.954694] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10742 20:01:46.370495 <5>[ 13.967349] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10743 20:01:46.380532 <4>[ 13.967408] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10744 20:01:46.383549 <6>[ 13.967413] cfg80211: failed to load regulatory.db
10745 20:01:46.390221 <6>[ 13.968610] usbcore: registered new interface driver cdc_ether
10746 20:01:46.396667 <6>[ 13.973698] usbcore: registered new interface driver r8153_ecm
10747 20:01:46.399783 <6>[ 14.000242] Bluetooth: Core ver 2.22
10748 20:01:46.406975 <6>[ 14.000316] NET: Registered PF_BLUETOOTH protocol family
10749 20:01:46.413172 <6>[ 14.000319] Bluetooth: HCI device and connection manager initialized
10750 20:01:46.416842 <6>[ 14.000334] Bluetooth: HCI socket layer initialized
10751 20:01:46.422936 <6>[ 14.000339] Bluetooth: L2CAP socket layer initialized
10752 20:01:46.426204 <6>[ 14.000350] Bluetooth: SCO socket layer initialized
10753 20:01:46.433004 <6>[ 14.008749] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10754 20:01:46.446038 <6>[ 14.009757] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10755 20:01:46.452656 <6>[ 14.009853] usbcore: registered new interface driver uvcvideo
10756 20:01:46.462766 <4>[ 14.016533] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10757 20:01:46.469525 <4>[ 14.016544] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10758 20:01:46.476145 <6>[ 14.046126] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10759 20:01:46.483196 <6>[ 14.065945] r8152 1-1.1.1:1.0 eth0: v1.12.13
10760 20:01:46.485831 <6>[ 14.069822] usbcore: registered new interface driver btusb
10761 20:01:46.499195 <4>[ 14.071262] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10762 20:01:46.502930 <3>[ 14.071280] Bluetooth: hci0: Failed to load firmware file (-2)
10763 20:01:46.508999 <3>[ 14.071282] Bluetooth: hci0: Failed to set up firmware (-2)
10764 20:01:46.518952 <4>[ 14.071286] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10765 20:01:46.525570 <6>[ 14.077089] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10766 20:01:46.532047 <6>[ 14.088399] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10767 20:01:46.538607 <6>[ 14.088510] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10768 20:01:46.545158 <6>[ 14.105518] mt7921e 0000:01:00.0: ASIC revision: 79610010
10769 20:01:46.555892 <4>[ 14.200479] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10770 20:01:46.568320 <4>[ 14.311241] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 20:01:46.578031 <4>[ 14.415017] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 20:01:46.585699 Begin: Loading essential drivers ... done.
10773 20:01:46.588366 Begin: Running /scripts/init-premount ... done.
10774 20:01:46.594743 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10775 20:01:46.607938 Begin: Running /scr<4>[ 14.524701] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 20:01:46.614665 ipts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10777 20:01:46.617677 Device /sys/class/net/enxf4f5e850de0a found
10778 20:01:46.621255 done.
10779 20:01:46.627688 Begin: Waiting up to 180 secs for any network device to become available ... done.
10780 20:01:46.679405 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10781 20:01:46.714603 <4>[ 14.632108] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 20:01:46.823330 <4>[ 14.738722] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 20:01:46.926430 <4>[ 14.842472] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 20:01:47.030433 <4>[ 14.946430] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 20:01:47.134460 <4>[ 15.050387] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 20:01:47.239104 <4>[ 15.154309] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 20:01:47.332203 <3>[ 15.256263] mt7921e 0000:01:00.0: hardware init failed
10788 20:01:47.803794 <6>[ 15.728691] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10789 20:01:48.613875 IP-Config: no response after 2 secs - giving up
10790 20:01:48.663396 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10791 20:01:48.666509 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10792 20:01:48.676228 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10793 20:01:48.683483 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10794 20:01:48.689412 host : mt8192-asurada-spherion-r0-cbg-9
10795 20:01:48.695823 domain : lava-rack
10796 20:01:48.699950 rootserver: 192.168.201.1 rootpath:
10797 20:01:48.700413 filename :
10798 20:01:48.790800 done.
10799 20:01:48.797356 Begin: Running /scripts/nfs-bottom ... done.
10800 20:01:48.818743 Begin: Running /scripts/init-bottom ... done.
10801 20:01:50.087301 <6>[ 18.011054] NET: Registered PF_INET6 protocol family
10802 20:01:50.090521 <6>[ 18.012766] Segment Routing with IPv6
10803 20:01:50.097635 <6>[ 18.012816] In-situ OAM (IOAM) with IPv6
10804 20:01:50.269564 <30>[ 18.165624] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10805 20:01:50.276462 <30>[ 18.165663] systemd[1]: Detected architecture arm64.
10806 20:01:50.276748
10807 20:01:50.279692 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10808 20:01:50.280066
10809 20:01:50.307272 <30>[ 18.230908] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10810 20:01:51.338837 <30>[ 19.257634] systemd[1]: Queued start job for default target graphical.target.
10811 20:01:51.371286 [[0;32m OK [0m] Created slic<30>[ 19.290739] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10812 20:01:51.374572 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10813 20:01:51.399950 [[0;32m OK [0m] Created slic<30>[ 19.319508] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10814 20:01:51.403607 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10815 20:01:51.428272 [[0;32m OK [0m] Created slic<30>[ 19.347390] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10816 20:01:51.434709 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10817 20:01:51.455806 [[0;32m OK [0m] Created slic<30>[ 19.374965] systemd[1]: Created slice user.slice - User and Session Slice.
10818 20:01:51.459472 e [0;1;39muser.slice[0m - User and Session Slice.
10819 20:01:51.486747 [[0;32m OK [0m] Started [0;<30>[ 19.402552] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10820 20:01:51.489891 1;39msystemd-ask-passwo…quests to Console Directory Watch.
10821 20:01:51.514084 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 19.429930] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10822 20:01:51.517352 -passwo… Requests to Wall Directory Watch.
10823 20:01:51.549072 [[0;32m OK [0m] Reached targ<30>[ 19.458334] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10824 20:01:51.558885 et [0;1;39mcryp<30>[ 19.458622] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10825 20:01:51.562292 tsetup.…get[0m - Local Encrypted Volumes.
10826 20:01:51.590785 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 19.506169] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10827 20:01:51.593689 grityse…Local Integrity Protected Volumes.
10828 20:01:51.614410 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 19.533781] systemd[1]: Reached target paths.target - Path Units.
10829 20:01:51.614976 s.target[0m - Path Units.
10830 20:01:51.637980 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 19.557717] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10831 20:01:51.641899 te-fs.target[0m - Remote File Systems.
10832 20:01:51.662790 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 19.581664] systemd[1]: Reached target slices.target - Slice Units.
10833 20:01:51.666042 es.target[0m - Slice Units.
10834 20:01:51.687334 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 19.606162] systemd[1]: Reached target swap.target - Swaps.
10835 20:01:51.687943 .target[0m - Swaps.
10836 20:01:51.711040 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 19.630098] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10837 20:01:51.717110 tysetup… - Local Verity Protected Volumes.
10838 20:01:51.739648 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 19.658156] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10839 20:01:51.745719 d-initc… initctl Compatibility Named Pipe.
10840 20:01:51.768447 [[0;32m OK [0m] Listening on<30>[ 19.687706] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10841 20:01:51.774704 [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10842 20:01:51.795902 [[0;32m OK [0m] Listening on<30>[ 19.715218] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10843 20:01:51.803031 [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10844 20:01:51.823336 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 19.742322] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10845 20:01:51.826434 d-journald.socket[0m - Journal Socket.
10846 20:01:51.849007 [[0;32m OK [<30>[ 19.768149] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10847 20:01:51.855530 0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10848 20:01:51.874551 [[0;32m OK [<30>[ 19.796966] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10849 20:01:51.884235 0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10850 20:01:51.902819 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 19.822177] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10851 20:01:51.906056 d-udevd…l.socket[0m - udev Kernel Socket.
10852 20:01:51.970694 Mounting [0;1;39mdev-hugepages.mount[<30>[ 19.889941] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10853 20:01:51.974132 0m - Huge Pages File System...
10854 20:01:51.998609 Mounting [0;1;39mdev-mqueue.mount…P<30>[ 19.918156] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10855 20:01:52.002072 OSIX Message Queue File System...
10856 20:01:52.030976 Mounting [0;1;39msys-kernel-debug.…<30>[ 19.950337] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10857 20:01:52.034160 [0m - Kernel Debug File System...
10858 20:01:52.064950 <30>[ 19.978049] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10859 20:01:52.110324 Starting [0;1;39mkmod-static-nodes…a<30>[ 20.026285] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10860 20:01:52.113326 te List of Static Device Nodes...
10861 20:01:52.140295 Starting [0;1;39mmodpr<30>[ 20.059613] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10862 20:01:52.143687 obe@configfs…m - Load Kernel Module configfs...
10863 20:01:52.216064 Starting [0;1;39mmodprobe@dm_mod.s…[<30>[ 20.134390] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10864 20:01:52.218498 0m - Load Kernel Module dm_mod...
10865 20:01:52.248269 Starting [0;1;39mmodpr<30>[ 20.167643] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10866 20:01:52.252207 obe@drm.service[0m - Load Kernel Module drm...
10867 20:01:52.266693 <30>[ 20.189255] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10868 20:01:52.276128 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10869 20:01:52.286213 <6>[ 20.206883] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10870 20:01:52.301131 Startin<30>[ 20.224109] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10871 20:01:52.307977 g [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10872 20:01:52.355133 <6>[ 20.277381] fuse: init (API version 7.37)
10873 20:01:52.361465 <30>[ 20.282495] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10874 20:01:52.371326 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10875 20:01:52.399818 Starting [0;1;39msyste<30>[ 20.319365] systemd[1]: Starting systemd-journald.service - Journal Service...
10876 20:01:52.403307 md-journald.service[0m - Journal Service...
10877 20:01:52.426218 <30>[ 20.349362] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10878 20:01:52.433145 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10879 20:01:52.463405 Starting [0;1;39msyste<30>[ 20.379097] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10880 20:01:52.466285 md-network-g… units from Kernel command line...
10881 20:01:52.501831 Starting [0;1;39msystemd-remount-f…n<30>[ 20.418049] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10882 20:01:52.504945 t Root and Kernel File Systems...
10883 20:01:52.533151 Starting [0;1;39msyste<30>[ 20.451702] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10884 20:01:52.535540 md-udev-trig…[0m - Coldplug All udev Devices...
10885 20:01:52.567279 [[0;32m OK [0m] Mounted [0;<30>[ 20.487070] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10886 20:01:52.570616 1;39mdev-hugepages.mount[0m - Huge Pages File System.
10887 20:01:52.596377 [[0;32m OK [0m] Mounted [0;<30>[ 20.515034] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10888 20:01:52.606399 1;39mdev-mqueue.<3>[ 20.522029] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 20:01:52.609397 mount[…- POSIX Message Queue File System.
10890 20:01:52.626309 <3>[ 20.547555] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 20:01:52.636112 <30>[ 20.549910] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10892 20:01:52.642942 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10893 20:01:52.667428 [[0;32m OK [0m] Finished [0<30>[ 20.586640] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10894 20:01:52.674478 ;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10895 20:01:52.684530 <3>[ 20.603543] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 20:01:52.694100 [[0;32m OK [0m] Finished [0<30>[ 20.615522] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10897 20:01:52.704186 ;1;39mmodprobe@c<30>[ 20.615958] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10898 20:01:52.707467 onfigfs…[0m - Load Kernel Module configfs.
10899 20:01:52.731785 [[0;32m OK [0m] Finished [0<30>[ 20.650478] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10900 20:01:52.738111 ;1;39mmodprobe@d<30>[ 20.650971] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10901 20:01:52.744144 m_mod.s…e[0m - Load Kernel Module dm_mod.
10902 20:01:52.759923 [[0;32m OK [0m] Finished [0<30>[ 20.682326] systemd[1]: modprobe@drm.service: Deactivated successfully.
10903 20:01:52.770103 ;1;39mmodprobe@d<30>[ 20.682734] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10904 20:01:52.780125 rm.service[0m -<3>[ 20.685362] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 20:01:52.790564 Load Kernel Mod<3>[ 20.705676] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 20:01:52.791123 ule drm.
10907 20:01:52.810496 <3>[ 20.730643] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 20:01:52.821882 [[0;32m OK [<30>[ 20.743948] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10909 20:01:52.832148 0m] Finished [0<30>[ 20.744397] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10910 20:01:52.845656 ;1;39mmodprobe@efi_psto…m - Lo<3>[ 20.765295] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 20:01:52.846242 ad Kernel Module efi_pstore.
10912 20:01:52.862891 <3>[ 20.784618] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 20:01:52.873871 [[0;32m OK [<30>[ 20.795840] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10914 20:01:52.884454 0m] Finished [0<30>[ 20.796697] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10915 20:01:52.887188 ;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10916 20:01:52.898833 <3>[ 20.821055] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 20:01:52.913435 [[0;32m OK [0m] Finished [0<30>[ 20.834860] systemd[1]: modprobe@loop.service: Deactivated successfully.
10918 20:01:52.923784 ;1;39mmodprobe@l<30>[ 20.835334] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10919 20:01:52.926449 oop.service[0m - Load Kernel Module loop.
10920 20:01:52.936328 <3>[ 20.855841] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 20:01:52.952145 [[0;32m OK [0m] Finished [0<30>[ 20.870847] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10922 20:01:52.955483 ;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10923 20:01:52.987854 [[0;32m OK [0m] Finished [0<30>[ 20.903377] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10924 20:01:52.991116 ;1;39msystemd-network-g…rk units from Kernel command line.
10925 20:01:53.017145 <4>[ 20.930336] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10926 20:01:53.027398 [[0;32m OK [<3>[ 20.930349] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10927 20:01:53.037695 0m] Started [0;<30>[ 20.934172] systemd[1]: Started systemd-journald.service - Journal Service.
10928 20:01:53.040196 1;39msystemd-journald.service[0m - Journal Service.
10929 20:01:53.063156 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10930 20:01:53.084090 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10931 20:01:53.106099 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10932 20:01:53.143674 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10933 20:01:53.168016 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10934 20:01:53.192776 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10935 20:01:53.216226 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10936 20:01:53.246677 Starting [0;1;39msyste<46>[ 21.167488] systemd-journald[313]: Received client request to flush runtime journal.
10937 20:01:53.249975 md-sysctl.se…ce[0m - Apply Kernel Variables...
10938 20:01:53.278207 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10939 20:01:53.482313 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10940 20:01:53.499086 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10941 20:01:53.519859 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10942 20:01:54.025172 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10943 20:01:54.653763 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10944 20:01:54.675265 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10945 20:01:54.720025 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10946 20:01:54.810813 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10947 20:01:54.831984 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10948 20:01:54.850478 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10949 20:01:54.905185 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10950 20:01:54.927470 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10951 20:01:54.955055 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10952 20:01:54.981388 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10953 20:01:54.995023 See 'systemctl status systemd-binfmt.service' for details.
10954 20:01:55.158034 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10955 20:01:55.198565 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10956 20:01:55.285125 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10957 20:01:55.445835 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10958 20:01:55.520590 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10959 20:01:55.543871 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10960 20:01:55.631809 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10961 20:01:55.676351 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10962 20:01:55.755631 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10963 20:01:55.795493 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10964 20:01:55.855148 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10965 20:01:55.879204 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10966 20:01:55.904276 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10967 20:01:55.921102 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10968 20:01:55.938943 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10969 20:01:55.954617 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10970 20:01:55.974998 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10971 20:01:55.999485 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10972 20:01:56.023111 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10973 20:01:56.039033 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10974 20:01:56.063090 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10975 20:01:56.083027 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10976 20:01:56.099428 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10977 20:01:56.124021 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10978 20:01:56.142172 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10979 20:01:56.158379 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10980 20:01:56.174739 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10981 20:01:56.213717 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10982 20:01:56.277270 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10983 20:01:56.390763 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10984 20:01:56.415535 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10985 20:01:56.444230 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10986 20:01:56.549133 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10987 20:01:56.599005 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10988 20:01:56.620393 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10989 20:01:56.647117 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10990 20:01:56.663832 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10991 20:01:56.682701 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10992 20:01:56.714556 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10993 20:01:56.737848 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10994 20:01:56.781264 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10995 20:01:56.800165 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10996 20:01:56.869390 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10997 20:01:56.893443 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10998 20:01:56.938439 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10999 20:01:56.983146 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11000 20:01:57.063216
11001 20:01:57.063766
11002 20:01:57.066797 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11003 20:01:57.067212
11004 20:01:57.069983 debian-bookworm-arm64 login: root (automatic login)
11005 20:01:57.070400
11006 20:01:57.070814
11007 20:01:57.354214 Linux debian-bookworm-arm64 6.1.59-cip8-rt4 #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023 aarch64
11008 20:01:57.354356
11009 20:01:57.360369 The programs included with the Debian GNU/Linux system are free software;
11010 20:01:57.367518 the exact distribution terms for each program are described in the
11011 20:01:57.370027 individual files in /usr/share/doc/*/copyright.
11012 20:01:57.370108
11013 20:01:57.376739 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11014 20:01:57.380068 permitted by applicable law.
11015 20:01:58.386075 Matched prompt #10: / #
11017 20:01:58.387192 Setting prompt string to ['/ #']
11018 20:01:58.387629 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11020 20:01:58.388723 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11021 20:01:58.389171 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
11022 20:01:58.389527 Setting prompt string to ['/ #']
11023 20:01:58.389841 Forcing a shell prompt, looking for ['/ #']
11025 20:01:58.440656 / #
11026 20:01:58.441334 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11027 20:01:58.441907 Waiting using forced prompt support (timeout 00:02:30)
11028 20:01:58.447659
11029 20:01:58.448702 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11030 20:01:58.449395 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
11032 20:01:58.550765 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11899622/extract-nfsrootfs-dl4xqeyi'
11033 20:01:58.557838 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11899622/extract-nfsrootfs-dl4xqeyi'
11035 20:01:58.659599 / # export NFS_SERVER_IP='192.168.201.1'
11036 20:01:58.666390 export NFS_SERVER_IP='192.168.201.1'
11037 20:01:58.667391 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11038 20:01:58.668029 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11039 20:01:58.668804 end: 2 depthcharge-action (duration 00:01:23) [common]
11040 20:01:58.669342 start: 3 lava-test-retry (timeout 00:07:58) [common]
11041 20:01:58.669829 start: 3.1 lava-test-shell (timeout 00:07:58) [common]
11042 20:01:58.670247 Using namespace: common
11044 20:01:58.771543 / # #
11045 20:01:58.772259 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11046 20:01:58.778094 #
11047 20:01:58.778990 Using /lava-11899622
11049 20:01:58.880354 / # export SHELL=/bin/bash
11050 20:01:58.886891 export SHELL=/bin/bash
11052 20:01:58.988746 / # . /lava-11899622/environment
11053 20:01:58.995497 . /lava-11899622/environment
11055 20:01:59.102737 / # /lava-11899622/bin/lava-test-runner /lava-11899622/0
11056 20:01:59.103386 Test shell timeout: 10s (minimum of the action and connection timeout)
11057 20:01:59.109229 /lava-11899622/bin/lava-test-runner /lava-11899622/0
11058 20:01:59.361052 + export TESTRUN_ID=0_timesync-off
11059 20:01:59.364003 + TESTRUN_ID=0_timesync-off
11060 20:01:59.367287 + cd /lava-11899622/0/tests/0_timesync-off
11061 20:01:59.370466 ++ cat uuid
11062 20:01:59.374308 + UUID=11899622_1.6.2.3.1
11063 20:01:59.374729 + set +x
11064 20:01:59.380740 <LAVA_SIGNAL_STARTRUN 0_timesync-off 11899622_1.6.2.3.1>
11065 20:01:59.381437 Received signal: <STARTRUN> 0_timesync-off 11899622_1.6.2.3.1
11066 20:01:59.381819 Starting test lava.0_timesync-off (11899622_1.6.2.3.1)
11067 20:01:59.382232 Skipping test definition patterns.
11068 20:01:59.383844 + systemctl stop systemd-timesyncd
11069 20:01:59.447960 + set +x
11070 20:01:59.451094 <LAVA_SIGNAL_ENDRUN 0_timesync-off 11899622_1.6.2.3.1>
11071 20:01:59.451907 Received signal: <ENDRUN> 0_timesync-off 11899622_1.6.2.3.1
11072 20:01:59.452350 Ending use of test pattern.
11073 20:01:59.452700 Ending test lava.0_timesync-off (11899622_1.6.2.3.1), duration 0.07
11075 20:01:59.517221 + export TESTRUN_ID=1_kselftest-alsa
11076 20:01:59.520637 + TESTRUN_ID=1_kselftest-alsa
11077 20:01:59.526842 + cd /lava-11899622/0/tests/1_kselftest-alsa
11078 20:01:59.527379 ++ cat uuid
11079 20:01:59.530613 + UUID=11899622_1.6.2.3.5
11080 20:01:59.531040 + set +x
11081 20:01:59.537633 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 11899622_1.6.2.3.5>
11082 20:01:59.538336 Received signal: <STARTRUN> 1_kselftest-alsa 11899622_1.6.2.3.5
11083 20:01:59.538699 Starting test lava.1_kselftest-alsa (11899622_1.6.2.3.5)
11084 20:01:59.539089 Skipping test definition patterns.
11085 20:01:59.540565 + cd ./automated/linux/kselftest/
11086 20:01:59.566647 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11087 20:01:59.600987 INFO: install_deps skipped
11088 20:02:00.092425 --2023-10-28 20:02:00-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11089 20:02:00.099615 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11090 20:02:00.221326 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11091 20:02:00.351183 HTTP request sent, awaiting response... 200 OK
11092 20:02:00.354536 Length: 2959220 (2.8M) [application/octet-stream]
11093 20:02:00.357936 Saving to: 'kselftest.tar.xz'
11094 20:02:00.358504
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11097 20:02:00.868348 kselftest.tar.xz 1%[ ] 47.81K 186KB/s
11098 20:02:01.302337 kselftest.tar.xz 7%[> ] 218.91K 425KB/s
11099 20:02:01.566449 kselftest.tar.xz 27%[====> ] 798.67K 841KB/s
11100 20:02:01.661501 kselftest.tar.xz 76%[==============> ] 2.17M 1.79MB/s
11101 20:02:01.667666 kselftest.tar.xz 100%[===================>] 2.82M 2.16MB/s in 1.3s
11102 20:02:01.667770
11103 20:02:01.924554 2023-10-28 20:02:02 (2.16 MB/s) - 'kselftest.tar.xz' saved [2959220/2959220]
11104 20:02:01.924705
11105 20:02:07.537625 skiplist:
11106 20:02:07.540312 ========================================
11107 20:02:07.544326 ========================================
11108 20:02:07.592982 alsa:mixer-test
11109 20:02:07.613238 ============== Tests to run ===============
11110 20:02:07.613674 alsa:mixer-test
11111 20:02:07.619326 ===========End Tests to run ===============
11112 20:02:07.622972 shardfile-alsa pass
11113 20:02:07.728821 <12>[ 35.656581] kselftest: Running tests in alsa
11114 20:02:07.737529 TAP version 13
11115 20:02:07.752217 1..1
11116 20:02:07.768555 # selftests: alsa: mixer-test
11117 20:02:08.268851 # TAP version 13
11118 20:02:08.269422 # 1..0
11119 20:02:08.275247 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11120 20:02:08.278479 ok 1 selftests: alsa: mixer-test
11121 20:02:08.998966 alsa_mixer-test pass
11122 20:02:09.041683 + ../../utils/send-to-lava.sh ./output/result.txt
11123 20:02:09.105943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11124 20:02:09.106784 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11126 20:02:09.152391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11127 20:02:09.152481 + set +x
11128 20:02:09.152718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11130 20:02:09.158954 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 11899622_1.6.2.3.5>
11131 20:02:09.159210 Received signal: <ENDRUN> 1_kselftest-alsa 11899622_1.6.2.3.5
11132 20:02:09.159287 Ending use of test pattern.
11133 20:02:09.159351 Ending test lava.1_kselftest-alsa (11899622_1.6.2.3.5), duration 9.62
11135 20:02:09.162002 <LAVA_TEST_RUNNER EXIT>
11136 20:02:09.162264 ok: lava_test_shell seems to have completed
11137 20:02:09.162375 alsa_mixer-test: pass
shardfile-alsa: pass
11138 20:02:09.162471 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11139 20:02:09.162567 end: 3 lava-test-retry (duration 00:00:10) [common]
11140 20:02:09.162660 start: 4 finalize (timeout 00:07:48) [common]
11141 20:02:09.162759 start: 4.1 power-off (timeout 00:00:30) [common]
11142 20:02:09.162931 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11143 20:02:09.250271 >> Command sent successfully.
11144 20:02:09.262308 Returned 0 in 0 seconds
11145 20:02:09.363663 end: 4.1 power-off (duration 00:00:00) [common]
11147 20:02:09.365499 start: 4.2 read-feedback (timeout 00:07:48) [common]
11148 20:02:09.366772 Listened to connection for namespace 'common' for up to 1s
11149 20:02:10.367418 Finalising connection for namespace 'common'
11150 20:02:10.368101 Disconnecting from shell: Finalise
11151 20:02:10.368482 / #
11152 20:02:10.469482 end: 4.2 read-feedback (duration 00:00:01) [common]
11153 20:02:10.470249 end: 4 finalize (duration 00:00:01) [common]
11154 20:02:10.470865 Cleaning after the job
11155 20:02:10.471388 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/ramdisk
11156 20:02:10.486467 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/kernel
11157 20:02:10.521074 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/dtb
11158 20:02:10.521406 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/nfsrootfs
11159 20:02:10.624587 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899622/tftp-deploy-rghlf70a/modules
11160 20:02:10.631861 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11899622
11161 20:02:11.292718 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11899622
11162 20:02:11.292904 Job finished correctly