Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Kernel Errors: 32
- Errors: 0
- Boot result: PASS
1 19:59:13.750955 lava-dispatcher, installed at version: 2023.08
2 19:59:13.751158 start: 0 validate
3 19:59:13.751285 Start time: 2023-10-28 19:59:13.751277+00:00 (UTC)
4 19:59:13.751396 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:59:13.751520 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 19:59:14.026794 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:59:14.027522 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:59:14.299124 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:59:14.299938 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:59:14.562346 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:59:14.563074 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:59:14.836783 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:59:14.837559 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:59:15.113147 validate duration: 1.36
16 19:59:15.113396 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:59:15.113489 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:59:15.113577 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:59:15.113698 Not decompressing ramdisk as can be used compressed.
20 19:59:15.113782 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 19:59:15.113844 saving as /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/ramdisk/initrd.cpio.gz
22 19:59:15.113906 total size: 4665395 (4 MB)
23 19:59:15.114949 progress 0 % (0 MB)
24 19:59:15.116466 progress 5 % (0 MB)
25 19:59:15.117730 progress 10 % (0 MB)
26 19:59:15.118953 progress 15 % (0 MB)
27 19:59:15.120157 progress 20 % (0 MB)
28 19:59:15.121422 progress 25 % (1 MB)
29 19:59:15.122628 progress 30 % (1 MB)
30 19:59:15.123856 progress 35 % (1 MB)
31 19:59:15.125148 progress 40 % (1 MB)
32 19:59:15.126517 progress 45 % (2 MB)
33 19:59:15.127712 progress 50 % (2 MB)
34 19:59:15.129045 progress 55 % (2 MB)
35 19:59:15.130235 progress 60 % (2 MB)
36 19:59:15.131463 progress 65 % (2 MB)
37 19:59:15.132717 progress 70 % (3 MB)
38 19:59:15.133906 progress 75 % (3 MB)
39 19:59:15.135095 progress 80 % (3 MB)
40 19:59:15.136517 progress 85 % (3 MB)
41 19:59:15.137793 progress 90 % (4 MB)
42 19:59:15.138987 progress 95 % (4 MB)
43 19:59:15.140198 progress 100 % (4 MB)
44 19:59:15.140385 4 MB downloaded in 0.03 s (168.03 MB/s)
45 19:59:15.140522 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:59:15.140746 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:59:15.140829 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:59:15.140909 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:59:15.141035 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:59:15.141103 saving as /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/kernel/Image
52 19:59:15.141162 total size: 49304064 (47 MB)
53 19:59:15.141220 No compression specified
54 19:59:15.142229 progress 0 % (0 MB)
55 19:59:15.154726 progress 5 % (2 MB)
56 19:59:15.167070 progress 10 % (4 MB)
57 19:59:15.179605 progress 15 % (7 MB)
58 19:59:15.192056 progress 20 % (9 MB)
59 19:59:15.204988 progress 25 % (11 MB)
60 19:59:15.217524 progress 30 % (14 MB)
61 19:59:15.230070 progress 35 % (16 MB)
62 19:59:15.242745 progress 40 % (18 MB)
63 19:59:15.255270 progress 45 % (21 MB)
64 19:59:15.267613 progress 50 % (23 MB)
65 19:59:15.279913 progress 55 % (25 MB)
66 19:59:15.292365 progress 60 % (28 MB)
67 19:59:15.305202 progress 65 % (30 MB)
68 19:59:15.317815 progress 70 % (32 MB)
69 19:59:15.330353 progress 75 % (35 MB)
70 19:59:15.342878 progress 80 % (37 MB)
71 19:59:15.355361 progress 85 % (39 MB)
72 19:59:15.367913 progress 90 % (42 MB)
73 19:59:15.380049 progress 95 % (44 MB)
74 19:59:15.392313 progress 100 % (47 MB)
75 19:59:15.392512 47 MB downloaded in 0.25 s (187.07 MB/s)
76 19:59:15.392658 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:59:15.392884 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:59:15.392967 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:59:15.393048 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:59:15.393190 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:59:15.393257 saving as /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/dtb/mt8192-asurada-spherion-r0.dtb
83 19:59:15.393315 total size: 47278 (0 MB)
84 19:59:15.393374 No compression specified
85 19:59:15.394493 progress 69 % (0 MB)
86 19:59:15.394758 progress 100 % (0 MB)
87 19:59:15.394911 0 MB downloaded in 0.00 s (28.29 MB/s)
88 19:59:15.395029 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:59:15.395243 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:59:15.395325 start: 1.4 download-retry (timeout 00:10:00) [common]
92 19:59:15.395404 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 19:59:15.395512 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 19:59:15.395580 saving as /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/nfsrootfs/full.rootfs.tar
95 19:59:15.395638 total size: 200813988 (191 MB)
96 19:59:15.395696 Using unxz to decompress xz
97 19:59:15.399760 progress 0 % (0 MB)
98 19:59:15.927027 progress 5 % (9 MB)
99 19:59:16.440148 progress 10 % (19 MB)
100 19:59:17.028879 progress 15 % (28 MB)
101 19:59:17.411129 progress 20 % (38 MB)
102 19:59:17.746019 progress 25 % (47 MB)
103 19:59:18.355309 progress 30 % (57 MB)
104 19:59:18.907623 progress 35 % (67 MB)
105 19:59:19.492378 progress 40 % (76 MB)
106 19:59:20.048957 progress 45 % (86 MB)
107 19:59:20.641331 progress 50 % (95 MB)
108 19:59:21.275905 progress 55 % (105 MB)
109 19:59:21.947327 progress 60 % (114 MB)
110 19:59:22.072773 progress 65 % (124 MB)
111 19:59:22.220082 progress 70 % (134 MB)
112 19:59:22.323459 progress 75 % (143 MB)
113 19:59:22.401083 progress 80 % (153 MB)
114 19:59:22.476285 progress 85 % (162 MB)
115 19:59:22.585876 progress 90 % (172 MB)
116 19:59:22.859044 progress 95 % (181 MB)
117 19:59:23.422009 progress 100 % (191 MB)
118 19:59:23.427183 191 MB downloaded in 8.03 s (23.84 MB/s)
119 19:59:23.427434 end: 1.4.1 http-download (duration 00:00:08) [common]
121 19:59:23.427689 end: 1.4 download-retry (duration 00:00:08) [common]
122 19:59:23.427777 start: 1.5 download-retry (timeout 00:09:52) [common]
123 19:59:23.427861 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 19:59:23.428012 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 19:59:23.428081 saving as /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/modules/modules.tar
126 19:59:23.428141 total size: 8635496 (8 MB)
127 19:59:23.428260 Using unxz to decompress xz
128 19:59:23.432458 progress 0 % (0 MB)
129 19:59:23.453604 progress 5 % (0 MB)
130 19:59:23.475172 progress 10 % (0 MB)
131 19:59:23.500767 progress 15 % (1 MB)
132 19:59:23.526166 progress 20 % (1 MB)
133 19:59:23.551584 progress 25 % (2 MB)
134 19:59:23.580747 progress 30 % (2 MB)
135 19:59:23.605390 progress 35 % (2 MB)
136 19:59:23.630413 progress 40 % (3 MB)
137 19:59:23.655065 progress 45 % (3 MB)
138 19:59:23.681066 progress 50 % (4 MB)
139 19:59:23.705841 progress 55 % (4 MB)
140 19:59:23.732289 progress 60 % (4 MB)
141 19:59:23.755138 progress 65 % (5 MB)
142 19:59:23.779605 progress 70 % (5 MB)
143 19:59:23.803212 progress 75 % (6 MB)
144 19:59:23.829143 progress 80 % (6 MB)
145 19:59:23.861505 progress 85 % (7 MB)
146 19:59:23.886956 progress 90 % (7 MB)
147 19:59:23.910745 progress 95 % (7 MB)
148 19:59:23.933646 progress 100 % (8 MB)
149 19:59:23.939207 8 MB downloaded in 0.51 s (16.11 MB/s)
150 19:59:23.939445 end: 1.5.1 http-download (duration 00:00:01) [common]
152 19:59:23.939707 end: 1.5 download-retry (duration 00:00:01) [common]
153 19:59:23.939800 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 19:59:23.939894 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 19:59:27.495336 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11899595/extract-nfsrootfs-idlrs87b
156 19:59:27.495536 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 19:59:27.495646 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 19:59:27.495810 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj
159 19:59:27.495942 makedir: /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin
160 19:59:27.496044 makedir: /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/tests
161 19:59:27.496143 makedir: /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/results
162 19:59:27.496541 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-add-keys
163 19:59:27.496689 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-add-sources
164 19:59:27.496820 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-background-process-start
165 19:59:27.496949 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-background-process-stop
166 19:59:27.497076 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-common-functions
167 19:59:27.497200 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-echo-ipv4
168 19:59:27.497324 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-install-packages
169 19:59:27.497448 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-installed-packages
170 19:59:27.497570 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-os-build
171 19:59:27.497695 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-probe-channel
172 19:59:27.497819 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-probe-ip
173 19:59:27.497942 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-target-ip
174 19:59:27.498066 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-target-mac
175 19:59:27.498188 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-target-storage
176 19:59:27.498314 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-test-case
177 19:59:27.498441 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-test-event
178 19:59:27.498564 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-test-feedback
179 19:59:27.498689 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-test-raise
180 19:59:27.498813 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-test-reference
181 19:59:27.498980 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-test-runner
182 19:59:27.499106 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-test-set
183 19:59:27.499231 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-test-shell
184 19:59:27.499357 Updating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-add-keys (debian)
185 19:59:27.499508 Updating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-add-sources (debian)
186 19:59:27.499649 Updating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-install-packages (debian)
187 19:59:27.499788 Updating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-installed-packages (debian)
188 19:59:27.499924 Updating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/bin/lava-os-build (debian)
189 19:59:27.500044 Creating /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/environment
190 19:59:27.500140 LAVA metadata
191 19:59:27.500215 - LAVA_JOB_ID=11899595
192 19:59:27.500278 - LAVA_DISPATCHER_IP=192.168.201.1
193 19:59:27.500378 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 19:59:27.500444 skipped lava-vland-overlay
195 19:59:27.500519 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 19:59:27.500598 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 19:59:27.500659 skipped lava-multinode-overlay
198 19:59:27.500731 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 19:59:27.500809 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 19:59:27.500883 Loading test definitions
201 19:59:27.500973 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 19:59:27.501044 Using /lava-11899595 at stage 0
203 19:59:27.501322 uuid=11899595_1.6.2.3.1 testdef=None
204 19:59:27.501410 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 19:59:27.501494 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 19:59:27.501940 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 19:59:27.502196 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 19:59:27.502736 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 19:59:27.502962 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 19:59:27.503698 runner path: /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/0/tests/0_timesync-off test_uuid 11899595_1.6.2.3.1
213 19:59:27.503855 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 19:59:27.504077 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 19:59:27.504229 Using /lava-11899595 at stage 0
217 19:59:27.504359 Fetching tests from https://github.com/kernelci/test-definitions.git
218 19:59:27.504441 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/0/tests/1_kselftest-arm64'
219 19:59:31.010404 Running '/usr/bin/git checkout kernelci.org
220 19:59:31.021710 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 19:59:31.022416 uuid=11899595_1.6.2.3.5 testdef=None
222 19:59:31.022574 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 19:59:31.022821 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 19:59:31.023558 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 19:59:31.023783 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 19:59:31.024794 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 19:59:31.025021 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 19:59:31.025934 runner path: /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/0/tests/1_kselftest-arm64 test_uuid 11899595_1.6.2.3.5
232 19:59:31.026027 BOARD='mt8192-asurada-spherion-r0'
233 19:59:31.026091 BRANCH='cip-gitlab'
234 19:59:31.026150 SKIPFILE='/dev/null'
235 19:59:31.026207 SKIP_INSTALL='True'
236 19:59:31.026262 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 19:59:31.026318 TST_CASENAME=''
238 19:59:31.026372 TST_CMDFILES='arm64'
239 19:59:31.026516 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 19:59:31.026714 Creating lava-test-runner.conf files
242 19:59:31.026777 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899595/lava-overlay-9gfx5jvj/lava-11899595/0 for stage 0
243 19:59:31.026872 - 0_timesync-off
244 19:59:31.026940 - 1_kselftest-arm64
245 19:59:31.027037 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 19:59:31.027125 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 19:59:38.363660 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 19:59:38.363814 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 19:59:38.363942 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 19:59:38.364040 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 19:59:38.364132 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 19:59:38.483141 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 19:59:38.483522 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 19:59:38.483648 extracting modules file /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899595/extract-nfsrootfs-idlrs87b
255 19:59:38.703699 extracting modules file /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899595/extract-overlay-ramdisk-y9k4ybwc/ramdisk
256 19:59:38.931003 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 19:59:38.931168 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 19:59:38.931264 [common] Applying overlay to NFS
259 19:59:38.931334 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899595/compress-overlay-22o_gxw6/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11899595/extract-nfsrootfs-idlrs87b
260 19:59:39.841665 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 19:59:39.841833 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 19:59:39.841936 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 19:59:39.842030 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 19:59:39.842113 Building ramdisk /var/lib/lava/dispatcher/tmp/11899595/extract-overlay-ramdisk-y9k4ybwc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11899595/extract-overlay-ramdisk-y9k4ybwc/ramdisk
265 19:59:40.181423 >> 119376 blocks
266 19:59:42.063968 rename /var/lib/lava/dispatcher/tmp/11899595/extract-overlay-ramdisk-y9k4ybwc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/ramdisk/ramdisk.cpio.gz
267 19:59:42.064464 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 19:59:42.064623 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 19:59:42.064721 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 19:59:42.064829 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/kernel/Image'
271 19:59:53.917259 Returned 0 in 11 seconds
272 19:59:54.018356 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/kernel/image.itb
273 19:59:54.389132 output: FIT description: Kernel Image image with one or more FDT blobs
274 19:59:54.389509 output: Created: Sat Oct 28 20:59:54 2023
275 19:59:54.389588 output: Image 0 (kernel-1)
276 19:59:54.389653 output: Description:
277 19:59:54.389720 output: Created: Sat Oct 28 20:59:54 2023
278 19:59:54.389786 output: Type: Kernel Image
279 19:59:54.389848 output: Compression: lzma compressed
280 19:59:54.389906 output: Data Size: 11047522 Bytes = 10788.60 KiB = 10.54 MiB
281 19:59:54.389965 output: Architecture: AArch64
282 19:59:54.390025 output: OS: Linux
283 19:59:54.390082 output: Load Address: 0x00000000
284 19:59:54.390139 output: Entry Point: 0x00000000
285 19:59:54.390195 output: Hash algo: crc32
286 19:59:54.390251 output: Hash value: da40eda2
287 19:59:54.390306 output: Image 1 (fdt-1)
288 19:59:54.390361 output: Description: mt8192-asurada-spherion-r0
289 19:59:54.390414 output: Created: Sat Oct 28 20:59:54 2023
290 19:59:54.390467 output: Type: Flat Device Tree
291 19:59:54.390519 output: Compression: uncompressed
292 19:59:54.390571 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 19:59:54.390624 output: Architecture: AArch64
294 19:59:54.390676 output: Hash algo: crc32
295 19:59:54.390728 output: Hash value: cc4352de
296 19:59:54.390781 output: Image 2 (ramdisk-1)
297 19:59:54.390833 output: Description: unavailable
298 19:59:54.390885 output: Created: Sat Oct 28 20:59:54 2023
299 19:59:54.390938 output: Type: RAMDisk Image
300 19:59:54.390990 output: Compression: Unknown Compression
301 19:59:54.391043 output: Data Size: 17794233 Bytes = 17377.18 KiB = 16.97 MiB
302 19:59:54.391095 output: Architecture: AArch64
303 19:59:54.391148 output: OS: Linux
304 19:59:54.391200 output: Load Address: unavailable
305 19:59:54.391252 output: Entry Point: unavailable
306 19:59:54.391305 output: Hash algo: crc32
307 19:59:54.391357 output: Hash value: cd1a74a7
308 19:59:54.391409 output: Default Configuration: 'conf-1'
309 19:59:54.391461 output: Configuration 0 (conf-1)
310 19:59:54.391512 output: Description: mt8192-asurada-spherion-r0
311 19:59:54.391564 output: Kernel: kernel-1
312 19:59:54.391617 output: Init Ramdisk: ramdisk-1
313 19:59:54.391669 output: FDT: fdt-1
314 19:59:54.391721 output: Loadables: kernel-1
315 19:59:54.391773 output:
316 19:59:54.391979 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 19:59:54.392075 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 19:59:54.392183 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 19:59:54.392330 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 19:59:54.392408 No LXC device requested
321 19:59:54.392487 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 19:59:54.392574 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 19:59:54.392649 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 19:59:54.392722 Checking files for TFTP limit of 4294967296 bytes.
325 19:59:54.393224 end: 1 tftp-deploy (duration 00:00:39) [common]
326 19:59:54.393333 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 19:59:54.393426 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 19:59:54.393553 substitutions:
329 19:59:54.393618 - {DTB}: 11899595/tftp-deploy-c1ag_fai/dtb/mt8192-asurada-spherion-r0.dtb
330 19:59:54.393683 - {INITRD}: 11899595/tftp-deploy-c1ag_fai/ramdisk/ramdisk.cpio.gz
331 19:59:54.393741 - {KERNEL}: 11899595/tftp-deploy-c1ag_fai/kernel/Image
332 19:59:54.393798 - {LAVA_MAC}: None
333 19:59:54.393853 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11899595/extract-nfsrootfs-idlrs87b
334 19:59:54.393908 - {NFS_SERVER_IP}: 192.168.201.1
335 19:59:54.393963 - {PRESEED_CONFIG}: None
336 19:59:54.394017 - {PRESEED_LOCAL}: None
337 19:59:54.394071 - {RAMDISK}: 11899595/tftp-deploy-c1ag_fai/ramdisk/ramdisk.cpio.gz
338 19:59:54.394125 - {ROOT_PART}: None
339 19:59:54.394179 - {ROOT}: None
340 19:59:54.394233 - {SERVER_IP}: 192.168.201.1
341 19:59:54.394286 - {TEE}: None
342 19:59:54.394340 Parsed boot commands:
343 19:59:54.394392 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 19:59:54.394573 Parsed boot commands: tftpboot 192.168.201.1 11899595/tftp-deploy-c1ag_fai/kernel/image.itb 11899595/tftp-deploy-c1ag_fai/kernel/cmdline
345 19:59:54.394659 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 19:59:54.394746 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 19:59:54.394838 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 19:59:54.394924 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 19:59:54.395000 Not connected, no need to disconnect.
350 19:59:54.395074 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 19:59:54.395154 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 19:59:54.395220 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 19:59:54.399419 Setting prompt string to ['lava-test: # ']
354 19:59:54.399892 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 19:59:54.400006 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 19:59:54.400109 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 19:59:54.400264 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 19:59:54.400486 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 19:59:59.547842 >> Command sent successfully.
360 19:59:59.558866 Returned 0 in 5 seconds
361 19:59:59.660300 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 19:59:59.661901 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 19:59:59.662569 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 19:59:59.663237 Setting prompt string to 'Starting depthcharge on Spherion...'
366 19:59:59.663657 Changing prompt to 'Starting depthcharge on Spherion...'
367 19:59:59.664054 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 19:59:59.665556 [Enter `^Ec?' for help]
369 19:59:59.829017
370 19:59:59.829636
371 19:59:59.830041 F0: 102B 0000
372 19:59:59.830428
373 19:59:59.830778 F3: 1001 0000 [0200]
374 19:59:59.831110
375 19:59:59.832796 F3: 1001 0000
376 19:59:59.833256
377 19:59:59.833609 F7: 102D 0000
378 19:59:59.833932
379 19:59:59.834238 F1: 0000 0000
380 19:59:59.836119
381 19:59:59.836577 V0: 0000 0000 [0001]
382 19:59:59.836921
383 19:59:59.837241 00: 0007 8000
384 19:59:59.837577
385 19:59:59.839758 01: 0000 0000
386 19:59:59.840228
387 19:59:59.840724 BP: 0C00 0209 [0000]
388 19:59:59.841057
389 19:59:59.842868 G0: 1182 0000
390 19:59:59.843292
391 19:59:59.843629 EC: 0000 0021 [4000]
392 19:59:59.843946
393 19:59:59.846808 S7: 0000 0000 [0000]
394 19:59:59.847479
395 19:59:59.848080 CC: 0000 0000 [0001]
396 19:59:59.848721
397 19:59:59.850117 T0: 0000 0040 [010F]
398 19:59:59.850789
399 19:59:59.851412 Jump to BL
400 19:59:59.852043
401 19:59:59.875612
402 19:59:59.875950
403 19:59:59.876246
404 19:59:59.883208 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 19:59:59.886452 ARM64: Exception handlers installed.
406 19:59:59.890380 ARM64: Testing exception
407 19:59:59.894205 ARM64: Done test exception
408 19:59:59.901548 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 19:59:59.908399 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 19:59:59.915406 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 19:59:59.926113 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 19:59:59.933011 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 19:59:59.943070 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 19:59:59.953314 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 19:59:59.959904 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 19:59:59.978288 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 19:59:59.981537 WDT: Last reset was cold boot
418 19:59:59.984865 SPI1(PAD0) initialized at 2873684 Hz
419 19:59:59.988374 SPI5(PAD0) initialized at 992727 Hz
420 19:59:59.991549 VBOOT: Loading verstage.
421 19:59:59.998486 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 20:00:00.001435 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 20:00:00.004879 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 20:00:00.008235 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 20:00:00.015747 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 20:00:00.022210 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 20:00:00.033170 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 20:00:00.033282
429 20:00:00.033350
430 20:00:00.043396 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 20:00:00.046411 ARM64: Exception handlers installed.
432 20:00:00.050392 ARM64: Testing exception
433 20:00:00.050994 ARM64: Done test exception
434 20:00:00.057017 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 20:00:00.060052 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 20:00:00.074587 Probing TPM: . done!
437 20:00:00.075075 TPM ready after 0 ms
438 20:00:00.081734 Connected to device vid:did:rid of 1ae0:0028:00
439 20:00:00.088718 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 20:00:00.135795 Initialized TPM device CR50 revision 0
441 20:00:00.151219 tlcl_send_startup: Startup return code is 0
442 20:00:00.151863 TPM: setup succeeded
443 20:00:00.161850 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 20:00:00.170938 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 20:00:00.180560 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 20:00:00.188939 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 20:00:00.192198 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 20:00:00.195757 in-header: 03 07 00 00 08 00 00 00
449 20:00:00.199131 in-data: aa e4 47 04 13 02 00 00
450 20:00:00.202455 Chrome EC: UHEPI supported
451 20:00:00.209052 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 20:00:00.212688 in-header: 03 95 00 00 08 00 00 00
453 20:00:00.216934 in-data: 18 20 20 08 00 00 00 00
454 20:00:00.217074 Phase 1
455 20:00:00.219989 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 20:00:00.227139 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 20:00:00.230933 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 20:00:00.234474 Recovery requested (1009000e)
459 20:00:00.243985 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 20:00:00.249322 tlcl_extend: response is 0
461 20:00:00.258857 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 20:00:00.264948 tlcl_extend: response is 0
463 20:00:00.272041 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 20:00:00.291672 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 20:00:00.298963 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 20:00:00.299078
467 20:00:00.299155
468 20:00:00.309216 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 20:00:00.312890 ARM64: Exception handlers installed.
470 20:00:00.313009 ARM64: Testing exception
471 20:00:00.315845 ARM64: Done test exception
472 20:00:00.336628 pmic_efuse_setting: Set efuses in 11 msecs
473 20:00:00.340155 pmwrap_interface_init: Select PMIF_VLD_RDY
474 20:00:00.346757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 20:00:00.350214 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 20:00:00.356891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 20:00:00.360411 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 20:00:00.366807 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 20:00:00.370309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 20:00:00.373470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 20:00:00.380412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 20:00:00.383665 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 20:00:00.390605 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 20:00:00.393894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 20:00:00.397417 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 20:00:00.404393 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 20:00:00.410593 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 20:00:00.414861 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 20:00:00.421680 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 20:00:00.425673 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 20:00:00.432523 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 20:00:00.436434 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 20:00:00.443706 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 20:00:00.447643 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 20:00:00.454895 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 20:00:00.458661 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 20:00:00.465863 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 20:00:00.469748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 20:00:00.476975 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 20:00:00.480623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 20:00:00.487964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 20:00:00.491501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 20:00:00.494972 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 20:00:00.502535 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 20:00:00.506297 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 20:00:00.509947 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 20:00:00.517337 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 20:00:00.521349 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 20:00:00.524871 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 20:00:00.532128 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 20:00:00.535651 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 20:00:00.539208 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 20:00:00.546461 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 20:00:00.550001 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 20:00:00.553210 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 20:00:00.557004 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 20:00:00.561054 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 20:00:00.567881 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 20:00:00.571647 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 20:00:00.575127 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 20:00:00.578818 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 20:00:00.582514 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 20:00:00.589581 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 20:00:00.593431 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 20:00:00.600808 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 20:00:00.608048 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 20:00:00.614904 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 20:00:00.621990 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 20:00:00.629194 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 20:00:00.633201 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 20:00:00.639923 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 20:00:00.643466 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 20:00:00.650882 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x38
534 20:00:00.654258 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 20:00:00.662252 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 20:00:00.665313 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 20:00:00.674723 [RTC]rtc_get_frequency_meter,154: input=15, output=764
538 20:00:00.684510 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 20:00:00.693603 [RTC]rtc_get_frequency_meter,154: input=19, output=856
540 20:00:00.703594 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 20:00:00.712706 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 20:00:00.722189 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 20:00:00.732488 [RTC]rtc_get_frequency_meter,154: input=17, output=811
544 20:00:00.735460 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 20:00:00.742785 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 20:00:00.746316 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 20:00:00.750265 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 20:00:00.753733 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 20:00:00.757336 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 20:00:00.760982 ADC[4]: Raw value=670432 ID=5
551 20:00:00.764931 ADC[3]: Raw value=212917 ID=1
552 20:00:00.765423 RAM Code: 0x51
553 20:00:00.768445 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 20:00:00.776269 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 20:00:00.783221 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 20:00:00.786786 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 20:00:00.790256 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 20:00:00.795340 in-header: 03 07 00 00 08 00 00 00
559 20:00:00.799111 in-data: aa e4 47 04 13 02 00 00
560 20:00:00.803004 Chrome EC: UHEPI supported
561 20:00:00.809960 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 20:00:00.813632 in-header: 03 95 00 00 08 00 00 00
563 20:00:00.817326 in-data: 18 20 20 08 00 00 00 00
564 20:00:00.817818 MRC: failed to locate region type 0.
565 20:00:00.824405 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 20:00:00.828167 DRAM-K: Running full calibration
567 20:00:00.835480 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 20:00:00.835971 header.status = 0x0
569 20:00:00.839691 header.version = 0x6 (expected: 0x6)
570 20:00:00.843354 header.size = 0xd00 (expected: 0xd00)
571 20:00:00.843959 header.flags = 0x0
572 20:00:00.850217 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 20:00:00.868912 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 20:00:00.876649 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 20:00:00.877445 dram_init: ddr_geometry: 0
576 20:00:00.880131 [EMI] MDL number = 0
577 20:00:00.883742 [EMI] Get MDL freq = 0
578 20:00:00.884244 dram_init: ddr_type: 0
579 20:00:00.887414 is_discrete_lpddr4: 1
580 20:00:00.891199 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 20:00:00.891795
582 20:00:00.892220
583 20:00:00.892575 [Bian_co] ETT version 0.0.0.1
584 20:00:00.898357 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 20:00:00.898830
586 20:00:00.902131 dramc_set_vcore_voltage set vcore to 650000
587 20:00:00.902725 Read voltage for 800, 4
588 20:00:00.905857 Vio18 = 0
589 20:00:00.906455 Vcore = 650000
590 20:00:00.906841 Vdram = 0
591 20:00:00.907192 Vddq = 0
592 20:00:00.909270 Vmddr = 0
593 20:00:00.909744 dram_init: config_dvfs: 1
594 20:00:00.917004 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 20:00:00.920995 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 20:00:00.924309 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 20:00:00.927931 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 20:00:00.931455 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 20:00:00.935293 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 20:00:00.939188 MEM_TYPE=3, freq_sel=18
601 20:00:00.942419 sv_algorithm_assistance_LP4_1600
602 20:00:00.945990 ============ PULL DRAM RESETB DOWN ============
603 20:00:00.950027 ========== PULL DRAM RESETB DOWN end =========
604 20:00:00.953809 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 20:00:00.957303 ===================================
606 20:00:00.961173 LPDDR4 DRAM CONFIGURATION
607 20:00:00.964630 ===================================
608 20:00:00.965061 EX_ROW_EN[0] = 0x0
609 20:00:00.968854 EX_ROW_EN[1] = 0x0
610 20:00:00.969384 LP4Y_EN = 0x0
611 20:00:00.972335 WORK_FSP = 0x0
612 20:00:00.972759 WL = 0x2
613 20:00:00.973096 RL = 0x2
614 20:00:00.975627 BL = 0x2
615 20:00:00.976046 RPST = 0x0
616 20:00:00.979267 RD_PRE = 0x0
617 20:00:00.979689 WR_PRE = 0x1
618 20:00:00.983051 WR_PST = 0x0
619 20:00:00.983471 DBI_WR = 0x0
620 20:00:00.986566 DBI_RD = 0x0
621 20:00:00.986990 OTF = 0x1
622 20:00:00.990331 ===================================
623 20:00:00.994043 ===================================
624 20:00:00.994469 ANA top config
625 20:00:00.997905 ===================================
626 20:00:01.001230 DLL_ASYNC_EN = 0
627 20:00:01.004764 ALL_SLAVE_EN = 1
628 20:00:01.008141 NEW_RANK_MODE = 1
629 20:00:01.008681 DLL_IDLE_MODE = 1
630 20:00:01.011340 LP45_APHY_COMB_EN = 1
631 20:00:01.015290 TX_ODT_DIS = 1
632 20:00:01.018066 NEW_8X_MODE = 1
633 20:00:01.021491 ===================================
634 20:00:01.024681 ===================================
635 20:00:01.028566 data_rate = 1600
636 20:00:01.029216 CKR = 1
637 20:00:01.031723 DQ_P2S_RATIO = 8
638 20:00:01.035218 ===================================
639 20:00:01.038998 CA_P2S_RATIO = 8
640 20:00:01.042555 DQ_CA_OPEN = 0
641 20:00:01.043028 DQ_SEMI_OPEN = 0
642 20:00:01.046240 CA_SEMI_OPEN = 0
643 20:00:01.049932 CA_FULL_RATE = 0
644 20:00:01.053017 DQ_CKDIV4_EN = 1
645 20:00:01.053465 CA_CKDIV4_EN = 1
646 20:00:01.056356 CA_PREDIV_EN = 0
647 20:00:01.060108 PH8_DLY = 0
648 20:00:01.063038 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 20:00:01.066817 DQ_AAMCK_DIV = 4
650 20:00:01.070407 CA_AAMCK_DIV = 4
651 20:00:01.071018 CA_ADMCK_DIV = 4
652 20:00:01.074250 DQ_TRACK_CA_EN = 0
653 20:00:01.077725 CA_PICK = 800
654 20:00:01.081775 CA_MCKIO = 800
655 20:00:01.082344 MCKIO_SEMI = 0
656 20:00:01.084868 PLL_FREQ = 3068
657 20:00:01.088511 DQ_UI_PI_RATIO = 32
658 20:00:01.091799 CA_UI_PI_RATIO = 0
659 20:00:01.095196 ===================================
660 20:00:01.099149 ===================================
661 20:00:01.099792 memory_type:LPDDR4
662 20:00:01.102770 GP_NUM : 10
663 20:00:01.106303 SRAM_EN : 1
664 20:00:01.106964 MD32_EN : 0
665 20:00:01.109651 ===================================
666 20:00:01.113322 [ANA_INIT] >>>>>>>>>>>>>>
667 20:00:01.113795 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 20:00:01.117057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 20:00:01.120817 ===================================
670 20:00:01.124336 data_rate = 1600,PCW = 0X7600
671 20:00:01.127927 ===================================
672 20:00:01.131529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 20:00:01.135463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 20:00:01.142264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 20:00:01.145580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 20:00:01.148863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 20:00:01.152281 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 20:00:01.155490 [ANA_INIT] flow start
679 20:00:01.159209 [ANA_INIT] PLL >>>>>>>>
680 20:00:01.159733 [ANA_INIT] PLL <<<<<<<<
681 20:00:01.162322 [ANA_INIT] MIDPI >>>>>>>>
682 20:00:01.165877 [ANA_INIT] MIDPI <<<<<<<<
683 20:00:01.169077 [ANA_INIT] DLL >>>>>>>>
684 20:00:01.169603 [ANA_INIT] flow end
685 20:00:01.172125 ============ LP4 DIFF to SE enter ============
686 20:00:01.179059 ============ LP4 DIFF to SE exit ============
687 20:00:01.179585 [ANA_INIT] <<<<<<<<<<<<<
688 20:00:01.182024 [Flow] Enable top DCM control >>>>>
689 20:00:01.185606 [Flow] Enable top DCM control <<<<<
690 20:00:01.188775 Enable DLL master slave shuffle
691 20:00:01.195588 ==============================================================
692 20:00:01.196123 Gating Mode config
693 20:00:01.202388 ==============================================================
694 20:00:01.205411 Config description:
695 20:00:01.211841 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 20:00:01.218754 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 20:00:01.225044 SELPH_MODE 0: By rank 1: By Phase
698 20:00:01.232544 ==============================================================
699 20:00:01.233070 GAT_TRACK_EN = 1
700 20:00:01.235334 RX_GATING_MODE = 2
701 20:00:01.238517 RX_GATING_TRACK_MODE = 2
702 20:00:01.242055 SELPH_MODE = 1
703 20:00:01.245041 PICG_EARLY_EN = 1
704 20:00:01.248414 VALID_LAT_VALUE = 1
705 20:00:01.255315 ==============================================================
706 20:00:01.258729 Enter into Gating configuration >>>>
707 20:00:01.261880 Exit from Gating configuration <<<<
708 20:00:01.265118 Enter into DVFS_PRE_config >>>>>
709 20:00:01.275339 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 20:00:01.278683 Exit from DVFS_PRE_config <<<<<
711 20:00:01.281891 Enter into PICG configuration >>>>
712 20:00:01.285190 Exit from PICG configuration <<<<
713 20:00:01.288661 [RX_INPUT] configuration >>>>>
714 20:00:01.289229 [RX_INPUT] configuration <<<<<
715 20:00:01.295265 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 20:00:01.301970 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 20:00:01.305383 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 20:00:01.312055 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 20:00:01.318801 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 20:00:01.325430 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 20:00:01.328745 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 20:00:01.332226 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 20:00:01.338421 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 20:00:01.341934 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 20:00:01.345220 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 20:00:01.348567 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 20:00:01.352126 ===================================
728 20:00:01.355003 LPDDR4 DRAM CONFIGURATION
729 20:00:01.358761 ===================================
730 20:00:01.362278 EX_ROW_EN[0] = 0x0
731 20:00:01.362872 EX_ROW_EN[1] = 0x0
732 20:00:01.365059 LP4Y_EN = 0x0
733 20:00:01.365527 WORK_FSP = 0x0
734 20:00:01.368672 WL = 0x2
735 20:00:01.369246 RL = 0x2
736 20:00:01.372017 BL = 0x2
737 20:00:01.372641 RPST = 0x0
738 20:00:01.375503 RD_PRE = 0x0
739 20:00:01.376076 WR_PRE = 0x1
740 20:00:01.378510 WR_PST = 0x0
741 20:00:01.381903 DBI_WR = 0x0
742 20:00:01.382481 DBI_RD = 0x0
743 20:00:01.385310 OTF = 0x1
744 20:00:01.388559 ===================================
745 20:00:01.391913 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 20:00:01.395276 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 20:00:01.398342 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 20:00:01.402067 ===================================
749 20:00:01.405284 LPDDR4 DRAM CONFIGURATION
750 20:00:01.408355 ===================================
751 20:00:01.411670 EX_ROW_EN[0] = 0x10
752 20:00:01.412449 EX_ROW_EN[1] = 0x0
753 20:00:01.415094 LP4Y_EN = 0x0
754 20:00:01.415832 WORK_FSP = 0x0
755 20:00:01.418351 WL = 0x2
756 20:00:01.419068 RL = 0x2
757 20:00:01.421651 BL = 0x2
758 20:00:01.422118 RPST = 0x0
759 20:00:01.425121 RD_PRE = 0x0
760 20:00:01.425590 WR_PRE = 0x1
761 20:00:01.428351 WR_PST = 0x0
762 20:00:01.428821 DBI_WR = 0x0
763 20:00:01.431670 DBI_RD = 0x0
764 20:00:01.432137 OTF = 0x1
765 20:00:01.434995 ===================================
766 20:00:01.441757 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 20:00:01.446657 nWR fixed to 40
768 20:00:01.450008 [ModeRegInit_LP4] CH0 RK0
769 20:00:01.450540 [ModeRegInit_LP4] CH0 RK1
770 20:00:01.453222 [ModeRegInit_LP4] CH1 RK0
771 20:00:01.456773 [ModeRegInit_LP4] CH1 RK1
772 20:00:01.457307 match AC timing 12
773 20:00:01.463846 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 20:00:01.466742 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 20:00:01.470479 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 20:00:01.476387 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 20:00:01.479889 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 20:00:01.480419 [EMI DOE] emi_dcm 0
779 20:00:01.486690 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 20:00:01.487263 ==
781 20:00:01.490154 Dram Type= 6, Freq= 0, CH_0, rank 0
782 20:00:01.493328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 20:00:01.493965 ==
784 20:00:01.499955 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 20:00:01.506195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 20:00:01.513857 [CA 0] Center 37 (7~68) winsize 62
787 20:00:01.517154 [CA 1] Center 37 (7~68) winsize 62
788 20:00:01.520445 [CA 2] Center 35 (4~66) winsize 63
789 20:00:01.524273 [CA 3] Center 35 (4~66) winsize 63
790 20:00:01.527074 [CA 4] Center 34 (4~65) winsize 62
791 20:00:01.530548 [CA 5] Center 33 (3~64) winsize 62
792 20:00:01.531130
793 20:00:01.534120 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 20:00:01.534697
795 20:00:01.537054 [CATrainingPosCal] consider 1 rank data
796 20:00:01.540290 u2DelayCellTimex100 = 270/100 ps
797 20:00:01.543884 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 20:00:01.550428 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 20:00:01.553801 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
800 20:00:01.556980 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 20:00:01.560342 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
802 20:00:01.563863 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 20:00:01.564522
804 20:00:01.567200 CA PerBit enable=1, Macro0, CA PI delay=33
805 20:00:01.567774
806 20:00:01.570503 [CBTSetCACLKResult] CA Dly = 33
807 20:00:01.570976 CS Dly: 6 (0~37)
808 20:00:01.573533 ==
809 20:00:01.577150 Dram Type= 6, Freq= 0, CH_0, rank 1
810 20:00:01.580731 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 20:00:01.581310 ==
812 20:00:01.584051 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 20:00:01.590745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 20:00:01.599968 [CA 0] Center 37 (6~68) winsize 63
815 20:00:01.603112 [CA 1] Center 37 (6~68) winsize 63
816 20:00:01.606594 [CA 2] Center 35 (4~66) winsize 63
817 20:00:01.609901 [CA 3] Center 34 (4~65) winsize 62
818 20:00:01.612890 [CA 4] Center 33 (3~64) winsize 62
819 20:00:01.616365 [CA 5] Center 33 (3~64) winsize 62
820 20:00:01.616855
821 20:00:01.619669 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 20:00:01.620132
823 20:00:01.622941 [CATrainingPosCal] consider 2 rank data
824 20:00:01.626258 u2DelayCellTimex100 = 270/100 ps
825 20:00:01.629879 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 20:00:01.633014 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 20:00:01.639785 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
828 20:00:01.643227 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 20:00:01.646599 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
830 20:00:01.650005 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 20:00:01.650573
832 20:00:01.653057 CA PerBit enable=1, Macro0, CA PI delay=33
833 20:00:01.653550
834 20:00:01.656395 [CBTSetCACLKResult] CA Dly = 33
835 20:00:01.656957 CS Dly: 6 (0~38)
836 20:00:01.657326
837 20:00:01.659967 ----->DramcWriteLeveling(PI) begin...
838 20:00:01.663387 ==
839 20:00:01.666751 Dram Type= 6, Freq= 0, CH_0, rank 0
840 20:00:01.669923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 20:00:01.670496 ==
842 20:00:01.673474 Write leveling (Byte 0): 29 => 29
843 20:00:01.676664 Write leveling (Byte 1): 28 => 28
844 20:00:01.680367 DramcWriteLeveling(PI) end<-----
845 20:00:01.680924
846 20:00:01.681293 ==
847 20:00:01.683405 Dram Type= 6, Freq= 0, CH_0, rank 0
848 20:00:01.687170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 20:00:01.687794 ==
850 20:00:01.690730 [Gating] SW mode calibration
851 20:00:01.697429 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 20:00:01.700757 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 20:00:01.704739 0 6 0 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
854 20:00:01.711462 0 6 4 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
855 20:00:01.714556 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 20:00:01.718085 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 20:00:01.724785 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 20:00:01.728064 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 20:00:01.731501 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 20:00:01.735306 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 20:00:01.741802 0 7 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
862 20:00:01.745066 0 7 4 | B1->B0 | 3535 4242 | 0 0 | (0 0) (0 0)
863 20:00:01.748346 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 20:00:01.755081 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 20:00:01.758065 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 20:00:01.761982 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 20:00:01.768634 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 20:00:01.771977 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 20:00:01.775229 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
870 20:00:01.782031 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
871 20:00:01.784940 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 20:00:01.788358 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 20:00:01.795110 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 20:00:01.797962 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 20:00:01.801844 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 20:00:01.808233 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 20:00:01.811220 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 20:00:01.814538 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 20:00:01.821375 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 20:00:01.824949 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 20:00:01.827928 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 20:00:01.835147 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 20:00:01.837931 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 20:00:01.841561 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 20:00:01.845083 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 20:00:01.848126 Total UI for P1: 0, mck2ui 16
887 20:00:01.851482 best dqsien dly found for B0: ( 0, 9, 30)
888 20:00:01.854855 Total UI for P1: 0, mck2ui 16
889 20:00:01.858627 best dqsien dly found for B1: ( 0, 9, 30)
890 20:00:01.861501 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
891 20:00:01.864967 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
892 20:00:01.868107
893 20:00:01.871901 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
894 20:00:01.874855 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
895 20:00:01.878194 [Gating] SW calibration Done
896 20:00:01.878767 ==
897 20:00:01.881374 Dram Type= 6, Freq= 0, CH_0, rank 0
898 20:00:01.884838 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 20:00:01.885409 ==
900 20:00:01.885788 RX Vref Scan: 0
901 20:00:01.888279
902 20:00:01.888847 RX Vref 0 -> 0, step: 1
903 20:00:01.889224
904 20:00:01.891333 RX Delay -130 -> 252, step: 16
905 20:00:01.894797 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
906 20:00:01.897924 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
907 20:00:01.904596 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
908 20:00:01.908204 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
909 20:00:01.911565 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
910 20:00:01.914574 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
911 20:00:01.917808 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
912 20:00:01.925044 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
913 20:00:01.927873 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
914 20:00:01.931214 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
915 20:00:01.934469 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
916 20:00:01.937737 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
917 20:00:01.944428 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
918 20:00:01.948043 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
919 20:00:01.951330 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
920 20:00:01.954877 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
921 20:00:01.955454 ==
922 20:00:01.958396 Dram Type= 6, Freq= 0, CH_0, rank 0
923 20:00:01.964810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
924 20:00:01.965380 ==
925 20:00:01.965745 DQS Delay:
926 20:00:01.968242 DQS0 = 0, DQS1 = 0
927 20:00:01.968809 DQM Delay:
928 20:00:01.969179 DQM0 = 82, DQM1 = 75
929 20:00:01.971678 DQ Delay:
930 20:00:01.974753 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
931 20:00:01.978146 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
932 20:00:01.981300 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
933 20:00:01.984505 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
934 20:00:01.985068
935 20:00:01.985434
936 20:00:01.985773 ==
937 20:00:01.988054 Dram Type= 6, Freq= 0, CH_0, rank 0
938 20:00:01.991704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
939 20:00:01.992314 ==
940 20:00:01.992690
941 20:00:01.993030
942 20:00:01.995089 TX Vref Scan disable
943 20:00:01.995648 == TX Byte 0 ==
944 20:00:02.001309 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
945 20:00:02.004746 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
946 20:00:02.005315 == TX Byte 1 ==
947 20:00:02.011463 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
948 20:00:02.014676 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
949 20:00:02.015289 ==
950 20:00:02.018197 Dram Type= 6, Freq= 0, CH_0, rank 0
951 20:00:02.021023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
952 20:00:02.021490 ==
953 20:00:02.035008 TX Vref=22, minBit 2, minWin=27, winSum=442
954 20:00:02.038145 TX Vref=24, minBit 0, minWin=27, winSum=445
955 20:00:02.041744 TX Vref=26, minBit 4, minWin=27, winSum=452
956 20:00:02.044941 TX Vref=28, minBit 1, minWin=28, winSum=453
957 20:00:02.048375 TX Vref=30, minBit 0, minWin=28, winSum=453
958 20:00:02.054983 TX Vref=32, minBit 1, minWin=27, winSum=448
959 20:00:02.058130 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 28
960 20:00:02.058801
961 20:00:02.061766 Final TX Range 1 Vref 28
962 20:00:02.062361
963 20:00:02.062738 ==
964 20:00:02.064776 Dram Type= 6, Freq= 0, CH_0, rank 0
965 20:00:02.068054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
966 20:00:02.068546 ==
967 20:00:02.068916
968 20:00:02.071251
969 20:00:02.071713 TX Vref Scan disable
970 20:00:02.075189 == TX Byte 0 ==
971 20:00:02.078641 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
972 20:00:02.081903 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
973 20:00:02.085317 == TX Byte 1 ==
974 20:00:02.088843 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
975 20:00:02.092532 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
976 20:00:02.093105
977 20:00:02.095751 [DATLAT]
978 20:00:02.096349 Freq=800, CH0 RK0
979 20:00:02.096727
980 20:00:02.098598 DATLAT Default: 0xa
981 20:00:02.099068 0, 0xFFFF, sum = 0
982 20:00:02.102219 1, 0xFFFF, sum = 0
983 20:00:02.102803 2, 0xFFFF, sum = 0
984 20:00:02.105718 3, 0xFFFF, sum = 0
985 20:00:02.106292 4, 0xFFFF, sum = 0
986 20:00:02.108675 5, 0xFFFF, sum = 0
987 20:00:02.109147 6, 0xFFFF, sum = 0
988 20:00:02.112334 7, 0xFFFF, sum = 0
989 20:00:02.112904 8, 0x0, sum = 1
990 20:00:02.115243 9, 0x0, sum = 2
991 20:00:02.115717 10, 0x0, sum = 3
992 20:00:02.118804 11, 0x0, sum = 4
993 20:00:02.119374 best_step = 9
994 20:00:02.119751
995 20:00:02.120102 ==
996 20:00:02.122111 Dram Type= 6, Freq= 0, CH_0, rank 0
997 20:00:02.125500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
998 20:00:02.128483 ==
999 20:00:02.128965 RX Vref Scan: 1
1000 20:00:02.129337
1001 20:00:02.132219 Set Vref Range= 32 -> 127
1002 20:00:02.132881
1003 20:00:02.133276 RX Vref 32 -> 127, step: 1
1004 20:00:02.135440
1005 20:00:02.135901 RX Delay -111 -> 252, step: 8
1006 20:00:02.136325
1007 20:00:02.138801 Set Vref, RX VrefLevel [Byte0]: 32
1008 20:00:02.142152 [Byte1]: 32
1009 20:00:02.146037
1010 20:00:02.146606 Set Vref, RX VrefLevel [Byte0]: 33
1011 20:00:02.148942 [Byte1]: 33
1012 20:00:02.153551
1013 20:00:02.154118 Set Vref, RX VrefLevel [Byte0]: 34
1014 20:00:02.156609 [Byte1]: 34
1015 20:00:02.161117
1016 20:00:02.161893 Set Vref, RX VrefLevel [Byte0]: 35
1017 20:00:02.164660 [Byte1]: 35
1018 20:00:02.168876
1019 20:00:02.169455 Set Vref, RX VrefLevel [Byte0]: 36
1020 20:00:02.171977 [Byte1]: 36
1021 20:00:02.176374
1022 20:00:02.176973 Set Vref, RX VrefLevel [Byte0]: 37
1023 20:00:02.179958 [Byte1]: 37
1024 20:00:02.183936
1025 20:00:02.184479 Set Vref, RX VrefLevel [Byte0]: 38
1026 20:00:02.187620 [Byte1]: 38
1027 20:00:02.191947
1028 20:00:02.192569 Set Vref, RX VrefLevel [Byte0]: 39
1029 20:00:02.195379 [Byte1]: 39
1030 20:00:02.199444
1031 20:00:02.199996 Set Vref, RX VrefLevel [Byte0]: 40
1032 20:00:02.202839 [Byte1]: 40
1033 20:00:02.207069
1034 20:00:02.207623 Set Vref, RX VrefLevel [Byte0]: 41
1035 20:00:02.210416 [Byte1]: 41
1036 20:00:02.214787
1037 20:00:02.215434 Set Vref, RX VrefLevel [Byte0]: 42
1038 20:00:02.218254 [Byte1]: 42
1039 20:00:02.222411
1040 20:00:02.222977 Set Vref, RX VrefLevel [Byte0]: 43
1041 20:00:02.225535 [Byte1]: 43
1042 20:00:02.229689
1043 20:00:02.230142 Set Vref, RX VrefLevel [Byte0]: 44
1044 20:00:02.232904 [Byte1]: 44
1045 20:00:02.237533
1046 20:00:02.238161 Set Vref, RX VrefLevel [Byte0]: 45
1047 20:00:02.240701 [Byte1]: 45
1048 20:00:02.245234
1049 20:00:02.245796 Set Vref, RX VrefLevel [Byte0]: 46
1050 20:00:02.248272 [Byte1]: 46
1051 20:00:02.252948
1052 20:00:02.253505 Set Vref, RX VrefLevel [Byte0]: 47
1053 20:00:02.256437 [Byte1]: 47
1054 20:00:02.260918
1055 20:00:02.261374 Set Vref, RX VrefLevel [Byte0]: 48
1056 20:00:02.263634 [Byte1]: 48
1057 20:00:02.268572
1058 20:00:02.269135 Set Vref, RX VrefLevel [Byte0]: 49
1059 20:00:02.271295 [Byte1]: 49
1060 20:00:02.276016
1061 20:00:02.276621 Set Vref, RX VrefLevel [Byte0]: 50
1062 20:00:02.278925 [Byte1]: 50
1063 20:00:02.283197
1064 20:00:02.283694 Set Vref, RX VrefLevel [Byte0]: 51
1065 20:00:02.287049 [Byte1]: 51
1066 20:00:02.291121
1067 20:00:02.291681 Set Vref, RX VrefLevel [Byte0]: 52
1068 20:00:02.294649 [Byte1]: 52
1069 20:00:02.298454
1070 20:00:02.298965 Set Vref, RX VrefLevel [Byte0]: 53
1071 20:00:02.302055 [Byte1]: 53
1072 20:00:02.306979
1073 20:00:02.307538 Set Vref, RX VrefLevel [Byte0]: 54
1074 20:00:02.309778 [Byte1]: 54
1075 20:00:02.313881
1076 20:00:02.314440 Set Vref, RX VrefLevel [Byte0]: 55
1077 20:00:02.317466 [Byte1]: 55
1078 20:00:02.321659
1079 20:00:02.322220 Set Vref, RX VrefLevel [Byte0]: 56
1080 20:00:02.325128 [Byte1]: 56
1081 20:00:02.329221
1082 20:00:02.329683 Set Vref, RX VrefLevel [Byte0]: 57
1083 20:00:02.332713 [Byte1]: 57
1084 20:00:02.336897
1085 20:00:02.337357 Set Vref, RX VrefLevel [Byte0]: 58
1086 20:00:02.340167 [Byte1]: 58
1087 20:00:02.344844
1088 20:00:02.345402 Set Vref, RX VrefLevel [Byte0]: 59
1089 20:00:02.348160 [Byte1]: 59
1090 20:00:02.352623
1091 20:00:02.353172 Set Vref, RX VrefLevel [Byte0]: 60
1092 20:00:02.355733 [Byte1]: 60
1093 20:00:02.359875
1094 20:00:02.360378 Set Vref, RX VrefLevel [Byte0]: 61
1095 20:00:02.363167 [Byte1]: 61
1096 20:00:02.368055
1097 20:00:02.368658 Set Vref, RX VrefLevel [Byte0]: 62
1098 20:00:02.371008 [Byte1]: 62
1099 20:00:02.375554
1100 20:00:02.376110 Set Vref, RX VrefLevel [Byte0]: 63
1101 20:00:02.378982 [Byte1]: 63
1102 20:00:02.383198
1103 20:00:02.383771 Set Vref, RX VrefLevel [Byte0]: 64
1104 20:00:02.385999 [Byte1]: 64
1105 20:00:02.390289
1106 20:00:02.390742 Set Vref, RX VrefLevel [Byte0]: 65
1107 20:00:02.393652 [Byte1]: 65
1108 20:00:02.398301
1109 20:00:02.398855 Set Vref, RX VrefLevel [Byte0]: 66
1110 20:00:02.401341 [Byte1]: 66
1111 20:00:02.405862
1112 20:00:02.406434 Set Vref, RX VrefLevel [Byte0]: 67
1113 20:00:02.409036 [Byte1]: 67
1114 20:00:02.413109
1115 20:00:02.413564 Set Vref, RX VrefLevel [Byte0]: 68
1116 20:00:02.416428 [Byte1]: 68
1117 20:00:02.421143
1118 20:00:02.421707 Set Vref, RX VrefLevel [Byte0]: 69
1119 20:00:02.424438 [Byte1]: 69
1120 20:00:02.428551
1121 20:00:02.429010 Set Vref, RX VrefLevel [Byte0]: 70
1122 20:00:02.432027 [Byte1]: 70
1123 20:00:02.436364
1124 20:00:02.436912 Set Vref, RX VrefLevel [Byte0]: 71
1125 20:00:02.439667 [Byte1]: 71
1126 20:00:02.444330
1127 20:00:02.444886 Set Vref, RX VrefLevel [Byte0]: 72
1128 20:00:02.447347 [Byte1]: 72
1129 20:00:02.451670
1130 20:00:02.452284 Set Vref, RX VrefLevel [Byte0]: 73
1131 20:00:02.454705 [Byte1]: 73
1132 20:00:02.459087
1133 20:00:02.459544 Set Vref, RX VrefLevel [Byte0]: 74
1134 20:00:02.462445 [Byte1]: 74
1135 20:00:02.467044
1136 20:00:02.467605 Set Vref, RX VrefLevel [Byte0]: 75
1137 20:00:02.470354 [Byte1]: 75
1138 20:00:02.474802
1139 20:00:02.475364 Final RX Vref Byte 0 = 53 to rank0
1140 20:00:02.477723 Final RX Vref Byte 1 = 54 to rank0
1141 20:00:02.481166 Final RX Vref Byte 0 = 53 to rank1
1142 20:00:02.484582 Final RX Vref Byte 1 = 54 to rank1==
1143 20:00:02.487734 Dram Type= 6, Freq= 0, CH_0, rank 0
1144 20:00:02.494369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1145 20:00:02.494831 ==
1146 20:00:02.495197 DQS Delay:
1147 20:00:02.495536 DQS0 = 0, DQS1 = 0
1148 20:00:02.497892 DQM Delay:
1149 20:00:02.498350 DQM0 = 83, DQM1 = 73
1150 20:00:02.501027 DQ Delay:
1151 20:00:02.504767 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1152 20:00:02.505281 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1153 20:00:02.507972 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1154 20:00:02.511367 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1155 20:00:02.514749
1156 20:00:02.515303
1157 20:00:02.521100 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1158 20:00:02.524943 CH0 RK0: MR19=606, MR18=3A3A
1159 20:00:02.531088 CH0_RK0: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1160 20:00:02.531610
1161 20:00:02.534845 ----->DramcWriteLeveling(PI) begin...
1162 20:00:02.535478 ==
1163 20:00:02.538129 Dram Type= 6, Freq= 0, CH_0, rank 1
1164 20:00:02.541420 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1165 20:00:02.541901 ==
1166 20:00:02.544373 Write leveling (Byte 0): 28 => 28
1167 20:00:02.548245 Write leveling (Byte 1): 27 => 27
1168 20:00:02.551394 DramcWriteLeveling(PI) end<-----
1169 20:00:02.551964
1170 20:00:02.552565 ==
1171 20:00:02.554836 Dram Type= 6, Freq= 0, CH_0, rank 1
1172 20:00:02.558382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1173 20:00:02.558961 ==
1174 20:00:02.561725 [Gating] SW mode calibration
1175 20:00:02.568410 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1176 20:00:02.574989 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1177 20:00:02.578317 0 6 0 | B1->B0 | 3232 3333 | 0 1 | (0 1) (1 0)
1178 20:00:02.581626 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1179 20:00:02.588406 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 20:00:02.591681 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 20:00:02.595205 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 20:00:02.601747 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 20:00:02.604925 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 20:00:02.608243 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 20:00:02.611445 0 7 0 | B1->B0 | 2c2c 2f2f | 0 0 | (0 0) (0 0)
1186 20:00:02.617924 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1187 20:00:02.621456 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 20:00:02.625094 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 20:00:02.631121 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 20:00:02.634774 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 20:00:02.638134 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 20:00:02.644863 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 20:00:02.648286 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1194 20:00:02.651540 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1195 20:00:02.658349 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 20:00:02.661322 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 20:00:02.664805 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 20:00:02.671302 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 20:00:02.674828 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 20:00:02.678280 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 20:00:02.684664 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 20:00:02.687971 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 20:00:02.691335 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 20:00:02.697973 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 20:00:02.701120 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 20:00:02.704411 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 20:00:02.711412 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 20:00:02.714641 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 20:00:02.717826 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1210 20:00:02.724848 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 20:00:02.725405 Total UI for P1: 0, mck2ui 16
1212 20:00:02.728325 best dqsien dly found for B0: ( 0, 10, 0)
1213 20:00:02.731332 Total UI for P1: 0, mck2ui 16
1214 20:00:02.734413 best dqsien dly found for B1: ( 0, 10, 0)
1215 20:00:02.737749 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1216 20:00:02.741095 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1217 20:00:02.744570
1218 20:00:02.748120 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1219 20:00:02.751393 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1220 20:00:02.754822 [Gating] SW calibration Done
1221 20:00:02.755378 ==
1222 20:00:02.798959 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 20:00:02.799672 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1224 20:00:02.800342 ==
1225 20:00:02.800715 RX Vref Scan: 0
1226 20:00:02.801055
1227 20:00:02.801379 RX Vref 0 -> 0, step: 1
1228 20:00:02.801695
1229 20:00:02.802004 RX Delay -130 -> 252, step: 16
1230 20:00:02.802383 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1231 20:00:02.803150 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1232 20:00:02.803515 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1233 20:00:02.803837 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1234 20:00:02.804149 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1235 20:00:02.804508 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1236 20:00:02.804814 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1237 20:00:02.805121 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1238 20:00:02.816296 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1239 20:00:02.817098 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1240 20:00:02.817694 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1241 20:00:02.818066 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1242 20:00:02.819428 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1243 20:00:02.823094 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1244 20:00:02.829640 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1245 20:00:02.833223 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1246 20:00:02.833686 ==
1247 20:00:02.836072 Dram Type= 6, Freq= 0, CH_0, rank 1
1248 20:00:02.839315 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1249 20:00:02.839776 ==
1250 20:00:02.840136 DQS Delay:
1251 20:00:02.842728 DQS0 = 0, DQS1 = 0
1252 20:00:02.843201 DQM Delay:
1253 20:00:02.846724 DQM0 = 83, DQM1 = 74
1254 20:00:02.847280 DQ Delay:
1255 20:00:02.849609 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
1256 20:00:02.853018 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1257 20:00:02.856521 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1258 20:00:02.859782 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1259 20:00:02.860388
1260 20:00:02.860761
1261 20:00:02.861099 ==
1262 20:00:02.862944 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 20:00:02.866563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1264 20:00:02.867129 ==
1265 20:00:02.867498
1266 20:00:02.869832
1267 20:00:02.870400 TX Vref Scan disable
1268 20:00:02.872994 == TX Byte 0 ==
1269 20:00:02.876875 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1270 20:00:02.879829 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1271 20:00:02.883317 == TX Byte 1 ==
1272 20:00:02.886520 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1273 20:00:02.889850 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1274 20:00:02.890406 ==
1275 20:00:02.893284 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 20:00:02.899738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1277 20:00:02.900390 ==
1278 20:00:02.911443 TX Vref=22, minBit 0, minWin=27, winSum=440
1279 20:00:02.914706 TX Vref=24, minBit 14, minWin=27, winSum=449
1280 20:00:02.917944 TX Vref=26, minBit 14, minWin=27, winSum=450
1281 20:00:02.921639 TX Vref=28, minBit 2, minWin=28, winSum=454
1282 20:00:02.925288 TX Vref=30, minBit 2, minWin=28, winSum=458
1283 20:00:02.928874 TX Vref=32, minBit 0, minWin=28, winSum=455
1284 20:00:02.936247 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 30
1285 20:00:02.936795
1286 20:00:02.939351 Final TX Range 1 Vref 30
1287 20:00:02.939837
1288 20:00:02.940244 ==
1289 20:00:02.942508 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 20:00:02.946099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1291 20:00:02.946791 ==
1292 20:00:02.947245
1293 20:00:02.947598
1294 20:00:02.949572 TX Vref Scan disable
1295 20:00:02.950051 == TX Byte 0 ==
1296 20:00:02.956792 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1297 20:00:02.960216 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1298 20:00:02.960782 == TX Byte 1 ==
1299 20:00:02.966979 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1300 20:00:02.970255 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1301 20:00:02.970816
1302 20:00:02.971183 [DATLAT]
1303 20:00:02.973342 Freq=800, CH0 RK1
1304 20:00:02.973916
1305 20:00:02.974288 DATLAT Default: 0x9
1306 20:00:02.976878 0, 0xFFFF, sum = 0
1307 20:00:02.977451 1, 0xFFFF, sum = 0
1308 20:00:02.980006 2, 0xFFFF, sum = 0
1309 20:00:02.980612 3, 0xFFFF, sum = 0
1310 20:00:02.983584 4, 0xFFFF, sum = 0
1311 20:00:02.984148 5, 0xFFFF, sum = 0
1312 20:00:02.987065 6, 0xFFFF, sum = 0
1313 20:00:02.987645 7, 0xFFFF, sum = 0
1314 20:00:02.989948 8, 0x0, sum = 1
1315 20:00:02.990417 9, 0x0, sum = 2
1316 20:00:02.993664 10, 0x0, sum = 3
1317 20:00:02.994229 11, 0x0, sum = 4
1318 20:00:02.996696 best_step = 9
1319 20:00:02.997155
1320 20:00:02.997519 ==
1321 20:00:03.000026 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 20:00:03.003526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1323 20:00:03.004083 ==
1324 20:00:03.006892 RX Vref Scan: 0
1325 20:00:03.007448
1326 20:00:03.007813 RX Vref 0 -> 0, step: 1
1327 20:00:03.008160
1328 20:00:03.010286 RX Delay -111 -> 252, step: 8
1329 20:00:03.016937 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1330 20:00:03.020734 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1331 20:00:03.023703 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1332 20:00:03.026631 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1333 20:00:03.030211 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1334 20:00:03.033364 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1335 20:00:03.040002 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1336 20:00:03.043588 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1337 20:00:03.046765 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1338 20:00:03.049930 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1339 20:00:03.056834 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1340 20:00:03.060279 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1341 20:00:03.063547 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1342 20:00:03.066668 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1343 20:00:03.069955 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1344 20:00:03.076552 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1345 20:00:03.077109 ==
1346 20:00:03.079930 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 20:00:03.083427 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1348 20:00:03.083986 ==
1349 20:00:03.084428 DQS Delay:
1350 20:00:03.086694 DQS0 = 0, DQS1 = 0
1351 20:00:03.087267 DQM Delay:
1352 20:00:03.089736 DQM0 = 86, DQM1 = 74
1353 20:00:03.090197 DQ Delay:
1354 20:00:03.093430 DQ0 =80, DQ1 =92, DQ2 =84, DQ3 =84
1355 20:00:03.096609 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1356 20:00:03.100040 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1357 20:00:03.103367 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1358 20:00:03.103915
1359 20:00:03.104333
1360 20:00:03.109799 [DQSOSCAuto] RK1, (LSB)MR18= 0x4848, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1361 20:00:03.113068 CH0 RK1: MR19=606, MR18=4848
1362 20:00:03.119866 CH0_RK1: MR19=0x606, MR18=0x4848, DQSOSC=391, MR23=63, INC=96, DEC=64
1363 20:00:03.123281 [RxdqsGatingPostProcess] freq 800
1364 20:00:03.129922 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1365 20:00:03.130340 Pre-setting of DQS Precalculation
1366 20:00:03.136468 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1367 20:00:03.136770 ==
1368 20:00:03.139960 Dram Type= 6, Freq= 0, CH_1, rank 0
1369 20:00:03.143067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1370 20:00:03.143375 ==
1371 20:00:03.150052 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1372 20:00:03.156260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1373 20:00:03.164206 [CA 0] Center 37 (6~68) winsize 63
1374 20:00:03.167288 [CA 1] Center 37 (6~68) winsize 63
1375 20:00:03.170666 [CA 2] Center 34 (4~65) winsize 62
1376 20:00:03.174740 [CA 3] Center 34 (4~65) winsize 62
1377 20:00:03.177554 [CA 4] Center 33 (3~64) winsize 62
1378 20:00:03.181112 [CA 5] Center 33 (3~64) winsize 62
1379 20:00:03.181662
1380 20:00:03.184096 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1381 20:00:03.184590
1382 20:00:03.187597 [CATrainingPosCal] consider 1 rank data
1383 20:00:03.190873 u2DelayCellTimex100 = 270/100 ps
1384 20:00:03.194519 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1385 20:00:03.197315 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1386 20:00:03.204111 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1387 20:00:03.207600 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1388 20:00:03.210968 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1389 20:00:03.214246 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1390 20:00:03.214825
1391 20:00:03.217462 CA PerBit enable=1, Macro0, CA PI delay=33
1392 20:00:03.217954
1393 20:00:03.220581 [CBTSetCACLKResult] CA Dly = 33
1394 20:00:03.221040 CS Dly: 5 (0~36)
1395 20:00:03.224342 ==
1396 20:00:03.224894 Dram Type= 6, Freq= 0, CH_1, rank 1
1397 20:00:03.230892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1398 20:00:03.231453 ==
1399 20:00:03.233981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1400 20:00:03.240511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1401 20:00:03.250268 [CA 0] Center 36 (6~67) winsize 62
1402 20:00:03.253191 [CA 1] Center 37 (6~68) winsize 63
1403 20:00:03.256950 [CA 2] Center 34 (4~65) winsize 62
1404 20:00:03.260042 [CA 3] Center 34 (4~65) winsize 62
1405 20:00:03.263680 [CA 4] Center 33 (3~64) winsize 62
1406 20:00:03.266654 [CA 5] Center 33 (3~64) winsize 62
1407 20:00:03.267110
1408 20:00:03.270307 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1409 20:00:03.270857
1410 20:00:03.273593 [CATrainingPosCal] consider 2 rank data
1411 20:00:03.277067 u2DelayCellTimex100 = 270/100 ps
1412 20:00:03.280153 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1413 20:00:03.283412 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1414 20:00:03.290257 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1415 20:00:03.293515 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1416 20:00:03.296900 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1417 20:00:03.300278 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1418 20:00:03.300854
1419 20:00:03.303230 CA PerBit enable=1, Macro0, CA PI delay=33
1420 20:00:03.303693
1421 20:00:03.306899 [CBTSetCACLKResult] CA Dly = 33
1422 20:00:03.307472 CS Dly: 5 (0~36)
1423 20:00:03.307842
1424 20:00:03.310443 ----->DramcWriteLeveling(PI) begin...
1425 20:00:03.311002 ==
1426 20:00:03.313322 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 20:00:03.320347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1428 20:00:03.320903 ==
1429 20:00:03.323570 Write leveling (Byte 0): 28 => 28
1430 20:00:03.326567 Write leveling (Byte 1): 24 => 24
1431 20:00:03.326981 DramcWriteLeveling(PI) end<-----
1432 20:00:03.330229
1433 20:00:03.330776 ==
1434 20:00:03.333286 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 20:00:03.336927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1436 20:00:03.337410 ==
1437 20:00:03.339887 [Gating] SW mode calibration
1438 20:00:03.347292 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1439 20:00:03.350315 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1440 20:00:03.357125 0 6 0 | B1->B0 | 2f2f 2a2a | 0 0 | (1 1) (1 1)
1441 20:00:03.360696 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 20:00:03.363672 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 20:00:03.370301 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 20:00:03.373668 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 20:00:03.376995 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 20:00:03.383961 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 20:00:03.387173 0 6 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1448 20:00:03.390559 0 7 0 | B1->B0 | 2e2e 3e3e | 1 0 | (0 0) (0 0)
1449 20:00:03.397104 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1450 20:00:03.400607 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 20:00:03.403787 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 20:00:03.407044 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1453 20:00:03.413782 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1454 20:00:03.416791 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1455 20:00:03.420353 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1456 20:00:03.427022 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1457 20:00:03.430635 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 20:00:03.433526 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 20:00:03.440243 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 20:00:03.443372 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 20:00:03.446905 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 20:00:03.454008 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 20:00:03.457148 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 20:00:03.460458 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 20:00:03.467132 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 20:00:03.470455 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 20:00:03.473613 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 20:00:03.480387 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 20:00:03.483866 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 20:00:03.487280 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1471 20:00:03.493657 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1472 20:00:03.497433 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1473 20:00:03.500281 Total UI for P1: 0, mck2ui 16
1474 20:00:03.503519 best dqsien dly found for B0: ( 0, 9, 28)
1475 20:00:03.506758 Total UI for P1: 0, mck2ui 16
1476 20:00:03.510180 best dqsien dly found for B1: ( 0, 9, 28)
1477 20:00:03.513434 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1478 20:00:03.516639 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1479 20:00:03.517128
1480 20:00:03.519927 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1481 20:00:03.523610 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1482 20:00:03.527073 [Gating] SW calibration Done
1483 20:00:03.527952 ==
1484 20:00:03.530340 Dram Type= 6, Freq= 0, CH_1, rank 0
1485 20:00:03.533349 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1486 20:00:03.533817 ==
1487 20:00:03.536639 RX Vref Scan: 0
1488 20:00:03.537292
1489 20:00:03.540090 RX Vref 0 -> 0, step: 1
1490 20:00:03.540608
1491 20:00:03.540974 RX Delay -130 -> 252, step: 16
1492 20:00:03.546975 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1493 20:00:03.549896 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1494 20:00:03.553734 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1495 20:00:03.556778 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1496 20:00:03.560278 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1497 20:00:03.566714 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1498 20:00:03.570116 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1499 20:00:03.573420 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1500 20:00:03.576942 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1501 20:00:03.580086 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1502 20:00:03.587034 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1503 20:00:03.590407 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1504 20:00:03.593531 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1505 20:00:03.597486 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1506 20:00:03.600736 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1507 20:00:03.604591 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1508 20:00:03.605139 ==
1509 20:00:03.608153 Dram Type= 6, Freq= 0, CH_1, rank 0
1510 20:00:03.611836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1511 20:00:03.615657 ==
1512 20:00:03.616119 DQS Delay:
1513 20:00:03.616542 DQS0 = 0, DQS1 = 0
1514 20:00:03.619031 DQM Delay:
1515 20:00:03.619539 DQM0 = 81, DQM1 = 73
1516 20:00:03.619919 DQ Delay:
1517 20:00:03.623292 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1518 20:00:03.626301 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1519 20:00:03.629400 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1520 20:00:03.632778 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1521 20:00:03.633240
1522 20:00:03.633607
1523 20:00:03.633945 ==
1524 20:00:03.636023 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 20:00:03.642980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1526 20:00:03.643589 ==
1527 20:00:03.644072
1528 20:00:03.644576
1529 20:00:03.645021 TX Vref Scan disable
1530 20:00:03.646080 == TX Byte 0 ==
1531 20:00:03.649389 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1532 20:00:03.652994 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1533 20:00:03.656083 == TX Byte 1 ==
1534 20:00:03.659713 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1535 20:00:03.662995 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1536 20:00:03.666533 ==
1537 20:00:03.669623 Dram Type= 6, Freq= 0, CH_1, rank 0
1538 20:00:03.673191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1539 20:00:03.673722 ==
1540 20:00:03.685678 TX Vref=22, minBit 3, minWin=27, winSum=447
1541 20:00:03.688972 TX Vref=24, minBit 3, minWin=27, winSum=451
1542 20:00:03.692569 TX Vref=26, minBit 0, minWin=28, winSum=452
1543 20:00:03.695854 TX Vref=28, minBit 0, minWin=28, winSum=456
1544 20:00:03.699044 TX Vref=30, minBit 0, minWin=28, winSum=460
1545 20:00:03.702043 TX Vref=32, minBit 0, minWin=28, winSum=459
1546 20:00:03.708940 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1547 20:00:03.709502
1548 20:00:03.712539 Final TX Range 1 Vref 30
1549 20:00:03.713095
1550 20:00:03.713462 ==
1551 20:00:03.715559 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 20:00:03.718598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1553 20:00:03.719140 ==
1554 20:00:03.719513
1555 20:00:03.722248
1556 20:00:03.722832 TX Vref Scan disable
1557 20:00:03.725372 == TX Byte 0 ==
1558 20:00:03.728833 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1559 20:00:03.732464 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1560 20:00:03.735352 == TX Byte 1 ==
1561 20:00:03.739135 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1562 20:00:03.742623 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1563 20:00:03.745410
1564 20:00:03.745872 [DATLAT]
1565 20:00:03.746238 Freq=800, CH1 RK0
1566 20:00:03.746577
1567 20:00:03.748631 DATLAT Default: 0xa
1568 20:00:03.749147 0, 0xFFFF, sum = 0
1569 20:00:03.752403 1, 0xFFFF, sum = 0
1570 20:00:03.752870 2, 0xFFFF, sum = 0
1571 20:00:03.755394 3, 0xFFFF, sum = 0
1572 20:00:03.755861 4, 0xFFFF, sum = 0
1573 20:00:03.759175 5, 0xFFFF, sum = 0
1574 20:00:03.762433 6, 0xFFFF, sum = 0
1575 20:00:03.763011 7, 0xFFFF, sum = 0
1576 20:00:03.763390 8, 0x0, sum = 1
1577 20:00:03.765786 9, 0x0, sum = 2
1578 20:00:03.766346 10, 0x0, sum = 3
1579 20:00:03.768581 11, 0x0, sum = 4
1580 20:00:03.769321 best_step = 9
1581 20:00:03.769832
1582 20:00:03.770187 ==
1583 20:00:03.772169 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 20:00:03.779176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1585 20:00:03.779734 ==
1586 20:00:03.780104 RX Vref Scan: 1
1587 20:00:03.780512
1588 20:00:03.782357 Set Vref Range= 32 -> 127
1589 20:00:03.782907
1590 20:00:03.785748 RX Vref 32 -> 127, step: 1
1591 20:00:03.786302
1592 20:00:03.786672 RX Delay -111 -> 252, step: 8
1593 20:00:03.788713
1594 20:00:03.789169 Set Vref, RX VrefLevel [Byte0]: 32
1595 20:00:03.792008 [Byte1]: 32
1596 20:00:03.796537
1597 20:00:03.797093 Set Vref, RX VrefLevel [Byte0]: 33
1598 20:00:03.799935 [Byte1]: 33
1599 20:00:03.804445
1600 20:00:03.805005 Set Vref, RX VrefLevel [Byte0]: 34
1601 20:00:03.807748 [Byte1]: 34
1602 20:00:03.811920
1603 20:00:03.812522 Set Vref, RX VrefLevel [Byte0]: 35
1604 20:00:03.815225 [Byte1]: 35
1605 20:00:03.819194
1606 20:00:03.819658 Set Vref, RX VrefLevel [Byte0]: 36
1607 20:00:03.822487 [Byte1]: 36
1608 20:00:03.827406
1609 20:00:03.827958 Set Vref, RX VrefLevel [Byte0]: 37
1610 20:00:03.830599 [Byte1]: 37
1611 20:00:03.834919
1612 20:00:03.835556 Set Vref, RX VrefLevel [Byte0]: 38
1613 20:00:03.837946 [Byte1]: 38
1614 20:00:03.842682
1615 20:00:03.843234 Set Vref, RX VrefLevel [Byte0]: 39
1616 20:00:03.845623 [Byte1]: 39
1617 20:00:03.850316
1618 20:00:03.850874 Set Vref, RX VrefLevel [Byte0]: 40
1619 20:00:03.853692 [Byte1]: 40
1620 20:00:03.857639
1621 20:00:03.858196 Set Vref, RX VrefLevel [Byte0]: 41
1622 20:00:03.860938 [Byte1]: 41
1623 20:00:03.865619
1624 20:00:03.866174 Set Vref, RX VrefLevel [Byte0]: 42
1625 20:00:03.868760 [Byte1]: 42
1626 20:00:03.873223
1627 20:00:03.873757 Set Vref, RX VrefLevel [Byte0]: 43
1628 20:00:03.876343 [Byte1]: 43
1629 20:00:03.880884
1630 20:00:03.881438 Set Vref, RX VrefLevel [Byte0]: 44
1631 20:00:03.884090 [Byte1]: 44
1632 20:00:03.888418
1633 20:00:03.888968 Set Vref, RX VrefLevel [Byte0]: 45
1634 20:00:03.892022 [Byte1]: 45
1635 20:00:03.895952
1636 20:00:03.896568 Set Vref, RX VrefLevel [Byte0]: 46
1637 20:00:03.899401 [Byte1]: 46
1638 20:00:03.903522
1639 20:00:03.903981 Set Vref, RX VrefLevel [Byte0]: 47
1640 20:00:03.907261 [Byte1]: 47
1641 20:00:03.911272
1642 20:00:03.911824 Set Vref, RX VrefLevel [Byte0]: 48
1643 20:00:03.914603 [Byte1]: 48
1644 20:00:03.918974
1645 20:00:03.919542 Set Vref, RX VrefLevel [Byte0]: 49
1646 20:00:03.922190 [Byte1]: 49
1647 20:00:03.926722
1648 20:00:03.927284 Set Vref, RX VrefLevel [Byte0]: 50
1649 20:00:03.929856 [Byte1]: 50
1650 20:00:03.934389
1651 20:00:03.934945 Set Vref, RX VrefLevel [Byte0]: 51
1652 20:00:03.937381 [Byte1]: 51
1653 20:00:03.941651
1654 20:00:03.942111 Set Vref, RX VrefLevel [Byte0]: 52
1655 20:00:03.944937 [Byte1]: 52
1656 20:00:03.949689
1657 20:00:03.950311 Set Vref, RX VrefLevel [Byte0]: 53
1658 20:00:03.952921 [Byte1]: 53
1659 20:00:03.957193
1660 20:00:03.957746 Set Vref, RX VrefLevel [Byte0]: 54
1661 20:00:03.960458 [Byte1]: 54
1662 20:00:03.965136
1663 20:00:03.965751 Set Vref, RX VrefLevel [Byte0]: 55
1664 20:00:03.968333 [Byte1]: 55
1665 20:00:03.972328
1666 20:00:03.972858 Set Vref, RX VrefLevel [Byte0]: 56
1667 20:00:03.976019 [Byte1]: 56
1668 20:00:03.979862
1669 20:00:03.980483 Set Vref, RX VrefLevel [Byte0]: 57
1670 20:00:03.983281 [Byte1]: 57
1671 20:00:03.987794
1672 20:00:03.988407 Set Vref, RX VrefLevel [Byte0]: 58
1673 20:00:03.991272 [Byte1]: 58
1674 20:00:03.995214
1675 20:00:03.995779 Set Vref, RX VrefLevel [Byte0]: 59
1676 20:00:03.998632 [Byte1]: 59
1677 20:00:04.002753
1678 20:00:04.003211 Set Vref, RX VrefLevel [Byte0]: 60
1679 20:00:04.006475 [Byte1]: 60
1680 20:00:04.010801
1681 20:00:04.011353 Set Vref, RX VrefLevel [Byte0]: 61
1682 20:00:04.013990 [Byte1]: 61
1683 20:00:04.018291
1684 20:00:04.018915 Set Vref, RX VrefLevel [Byte0]: 62
1685 20:00:04.021892 [Byte1]: 62
1686 20:00:04.026181
1687 20:00:04.026734 Set Vref, RX VrefLevel [Byte0]: 63
1688 20:00:04.029038 [Byte1]: 63
1689 20:00:04.033648
1690 20:00:04.034199 Set Vref, RX VrefLevel [Byte0]: 64
1691 20:00:04.037430 [Byte1]: 64
1692 20:00:04.041152
1693 20:00:04.041630 Set Vref, RX VrefLevel [Byte0]: 65
1694 20:00:04.044347 [Byte1]: 65
1695 20:00:04.048631
1696 20:00:04.049189 Set Vref, RX VrefLevel [Byte0]: 66
1697 20:00:04.052344 [Byte1]: 66
1698 20:00:04.056576
1699 20:00:04.057125 Set Vref, RX VrefLevel [Byte0]: 67
1700 20:00:04.059866 [Byte1]: 67
1701 20:00:04.064022
1702 20:00:04.064787 Set Vref, RX VrefLevel [Byte0]: 68
1703 20:00:04.067286 [Byte1]: 68
1704 20:00:04.071833
1705 20:00:04.072538 Set Vref, RX VrefLevel [Byte0]: 69
1706 20:00:04.075220 [Byte1]: 69
1707 20:00:04.079537
1708 20:00:04.080116 Set Vref, RX VrefLevel [Byte0]: 70
1709 20:00:04.082967 [Byte1]: 70
1710 20:00:04.087013
1711 20:00:04.087565 Set Vref, RX VrefLevel [Byte0]: 71
1712 20:00:04.090495 [Byte1]: 71
1713 20:00:04.095019
1714 20:00:04.095571 Set Vref, RX VrefLevel [Byte0]: 72
1715 20:00:04.098252 [Byte1]: 72
1716 20:00:04.102537
1717 20:00:04.103139 Set Vref, RX VrefLevel [Byte0]: 73
1718 20:00:04.105753 [Byte1]: 73
1719 20:00:04.110243
1720 20:00:04.110835 Set Vref, RX VrefLevel [Byte0]: 74
1721 20:00:04.113294 [Byte1]: 74
1722 20:00:04.117592
1723 20:00:04.118147 Set Vref, RX VrefLevel [Byte0]: 75
1724 20:00:04.120982 [Byte1]: 75
1725 20:00:04.125399
1726 20:00:04.125948 Set Vref, RX VrefLevel [Byte0]: 76
1727 20:00:04.128718 [Byte1]: 76
1728 20:00:04.133244
1729 20:00:04.133799 Set Vref, RX VrefLevel [Byte0]: 77
1730 20:00:04.136245 [Byte1]: 77
1731 20:00:04.140514
1732 20:00:04.140973 Set Vref, RX VrefLevel [Byte0]: 78
1733 20:00:04.143787 [Byte1]: 78
1734 20:00:04.148309
1735 20:00:04.148860 Final RX Vref Byte 0 = 59 to rank0
1736 20:00:04.151980 Final RX Vref Byte 1 = 58 to rank0
1737 20:00:04.155078 Final RX Vref Byte 0 = 59 to rank1
1738 20:00:04.158396 Final RX Vref Byte 1 = 58 to rank1==
1739 20:00:04.161407 Dram Type= 6, Freq= 0, CH_1, rank 0
1740 20:00:04.168722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1741 20:00:04.169316 ==
1742 20:00:04.169782 DQS Delay:
1743 20:00:04.170242 DQS0 = 0, DQS1 = 0
1744 20:00:04.172386 DQM Delay:
1745 20:00:04.172886 DQM0 = 81, DQM1 = 75
1746 20:00:04.173256 DQ Delay:
1747 20:00:04.176342 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1748 20:00:04.179202 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1749 20:00:04.182600 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1750 20:00:04.185599 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1751 20:00:04.186064
1752 20:00:04.186432
1753 20:00:04.195659 [DQSOSCAuto] RK0, (LSB)MR18= 0x5252, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1754 20:00:04.199187 CH1 RK0: MR19=606, MR18=5252
1755 20:00:04.202068 CH1_RK0: MR19=0x606, MR18=0x5252, DQSOSC=389, MR23=63, INC=97, DEC=65
1756 20:00:04.202677
1757 20:00:04.205836 ----->DramcWriteLeveling(PI) begin...
1758 20:00:04.209152 ==
1759 20:00:04.209705 Dram Type= 6, Freq= 0, CH_1, rank 1
1760 20:00:04.215661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1761 20:00:04.216252 ==
1762 20:00:04.218837 Write leveling (Byte 0): 26 => 26
1763 20:00:04.222447 Write leveling (Byte 1): 24 => 24
1764 20:00:04.225961 DramcWriteLeveling(PI) end<-----
1765 20:00:04.226525
1766 20:00:04.226894 ==
1767 20:00:04.228903 Dram Type= 6, Freq= 0, CH_1, rank 1
1768 20:00:04.232560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1769 20:00:04.233111 ==
1770 20:00:04.235734 [Gating] SW mode calibration
1771 20:00:04.242515 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1772 20:00:04.245834 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1773 20:00:04.252649 0 6 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
1774 20:00:04.255988 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1775 20:00:04.259168 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1776 20:00:04.265868 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1777 20:00:04.269050 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1778 20:00:04.272736 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1779 20:00:04.278973 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1780 20:00:04.282291 0 6 28 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
1781 20:00:04.285863 0 7 0 | B1->B0 | 3232 4545 | 1 0 | (0 0) (0 0)
1782 20:00:04.292401 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1783 20:00:04.295586 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1784 20:00:04.299268 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1785 20:00:04.305823 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1786 20:00:04.309137 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1787 20:00:04.312645 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1788 20:00:04.319016 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1789 20:00:04.322470 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1790 20:00:04.325870 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 20:00:04.329049 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 20:00:04.336079 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 20:00:04.338905 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 20:00:04.342303 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 20:00:04.349163 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 20:00:04.352379 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 20:00:04.356149 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1798 20:00:04.362826 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1799 20:00:04.365737 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1800 20:00:04.369186 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1801 20:00:04.375836 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1802 20:00:04.379321 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1803 20:00:04.382684 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1804 20:00:04.389157 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1805 20:00:04.389715 Total UI for P1: 0, mck2ui 16
1806 20:00:04.395678 best dqsien dly found for B0: ( 0, 9, 26)
1807 20:00:04.399010 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1808 20:00:04.402502 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1809 20:00:04.406150 Total UI for P1: 0, mck2ui 16
1810 20:00:04.408956 best dqsien dly found for B1: ( 0, 9, 30)
1811 20:00:04.412542 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1812 20:00:04.415718 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1813 20:00:04.416211
1814 20:00:04.419033 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1815 20:00:04.426103 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1816 20:00:04.426801 [Gating] SW calibration Done
1817 20:00:04.427250 ==
1818 20:00:04.429244 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 20:00:04.436228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1820 20:00:04.436823 ==
1821 20:00:04.437384 RX Vref Scan: 0
1822 20:00:04.437754
1823 20:00:04.438904 RX Vref 0 -> 0, step: 1
1824 20:00:04.439362
1825 20:00:04.442182 RX Delay -130 -> 252, step: 16
1826 20:00:04.445556 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1827 20:00:04.448969 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1828 20:00:04.452509 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1829 20:00:04.459210 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1830 20:00:04.462432 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1831 20:00:04.465485 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1832 20:00:04.468857 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1833 20:00:04.472440 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1834 20:00:04.478915 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1835 20:00:04.482583 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1836 20:00:04.485685 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1837 20:00:04.488868 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1838 20:00:04.492705 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1839 20:00:04.499379 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1840 20:00:04.502228 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1841 20:00:04.505932 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1842 20:00:04.506495 ==
1843 20:00:04.509065 Dram Type= 6, Freq= 0, CH_1, rank 1
1844 20:00:04.512573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1845 20:00:04.513055 ==
1846 20:00:04.515672 DQS Delay:
1847 20:00:04.516136 DQS0 = 0, DQS1 = 0
1848 20:00:04.519289 DQM Delay:
1849 20:00:04.519861 DQM0 = 86, DQM1 = 74
1850 20:00:04.520289 DQ Delay:
1851 20:00:04.522217 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1852 20:00:04.525743 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1853 20:00:04.529230 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1854 20:00:04.532548 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1855 20:00:04.533015
1856 20:00:04.533383
1857 20:00:04.535872 ==
1858 20:00:04.538942 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 20:00:04.542275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1860 20:00:04.542748 ==
1861 20:00:04.543118
1862 20:00:04.543459
1863 20:00:04.545513 TX Vref Scan disable
1864 20:00:04.545979 == TX Byte 0 ==
1865 20:00:04.552438 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1866 20:00:04.555467 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1867 20:00:04.555930 == TX Byte 1 ==
1868 20:00:04.562790 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1869 20:00:04.565679 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1870 20:00:04.566236 ==
1871 20:00:04.568710 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 20:00:04.571649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1873 20:00:04.572259 ==
1874 20:00:04.585605 TX Vref=22, minBit 1, minWin=27, winSum=448
1875 20:00:04.589033 TX Vref=24, minBit 0, minWin=27, winSum=450
1876 20:00:04.592294 TX Vref=26, minBit 1, minWin=28, winSum=456
1877 20:00:04.596051 TX Vref=28, minBit 0, minWin=28, winSum=455
1878 20:00:04.599474 TX Vref=30, minBit 0, minWin=28, winSum=458
1879 20:00:04.602618 TX Vref=32, minBit 9, minWin=27, winSum=455
1880 20:00:04.608912 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1881 20:00:04.609379
1882 20:00:04.612009 Final TX Range 1 Vref 30
1883 20:00:04.612505
1884 20:00:04.612872 ==
1885 20:00:04.615608 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 20:00:04.618760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1887 20:00:04.619226 ==
1888 20:00:04.619591
1889 20:00:04.622215
1890 20:00:04.622676 TX Vref Scan disable
1891 20:00:04.625564 == TX Byte 0 ==
1892 20:00:04.628653 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1893 20:00:04.632250 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1894 20:00:04.635669 == TX Byte 1 ==
1895 20:00:04.638672 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1896 20:00:04.642206 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1897 20:00:04.645514
1898 20:00:04.645973 [DATLAT]
1899 20:00:04.646338 Freq=800, CH1 RK1
1900 20:00:04.646679
1901 20:00:04.649152 DATLAT Default: 0x9
1902 20:00:04.649667 0, 0xFFFF, sum = 0
1903 20:00:04.652370 1, 0xFFFF, sum = 0
1904 20:00:04.652844 2, 0xFFFF, sum = 0
1905 20:00:04.655461 3, 0xFFFF, sum = 0
1906 20:00:04.655932 4, 0xFFFF, sum = 0
1907 20:00:04.659166 5, 0xFFFF, sum = 0
1908 20:00:04.659633 6, 0xFFFF, sum = 0
1909 20:00:04.662342 7, 0xFFFF, sum = 0
1910 20:00:04.662903 8, 0x0, sum = 1
1911 20:00:04.665447 9, 0x0, sum = 2
1912 20:00:04.665920 10, 0x0, sum = 3
1913 20:00:04.668651 11, 0x0, sum = 4
1914 20:00:04.669118 best_step = 9
1915 20:00:04.669485
1916 20:00:04.669827 ==
1917 20:00:04.672158 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 20:00:04.679019 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1919 20:00:04.679575 ==
1920 20:00:04.679948 RX Vref Scan: 0
1921 20:00:04.680345
1922 20:00:04.682281 RX Vref 0 -> 0, step: 1
1923 20:00:04.682853
1924 20:00:04.685371 RX Delay -111 -> 252, step: 8
1925 20:00:04.689111 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1926 20:00:04.692221 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1927 20:00:04.695719 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1928 20:00:04.702381 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1929 20:00:04.705635 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1930 20:00:04.709461 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1931 20:00:04.712287 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1932 20:00:04.715891 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1933 20:00:04.722586 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1934 20:00:04.725794 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1935 20:00:04.728874 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1936 20:00:04.732520 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1937 20:00:04.735763 iDelay=217, Bit 12, Center 88 (-31 ~ 208) 240
1938 20:00:04.742163 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1939 20:00:04.745492 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1940 20:00:04.748685 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1941 20:00:04.749147 ==
1942 20:00:04.752275 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 20:00:04.755941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1944 20:00:04.758787 ==
1945 20:00:04.759342 DQS Delay:
1946 20:00:04.759716 DQS0 = 0, DQS1 = 0
1947 20:00:04.762422 DQM Delay:
1948 20:00:04.762984 DQM0 = 84, DQM1 = 75
1949 20:00:04.765389 DQ Delay:
1950 20:00:04.765849 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =80
1951 20:00:04.768679 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1952 20:00:04.772438 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1953 20:00:04.775547 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1954 20:00:04.776013
1955 20:00:04.778939
1956 20:00:04.785782 [DQSOSCAuto] RK1, (LSB)MR18= 0x4242, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1957 20:00:04.788857 CH1 RK1: MR19=606, MR18=4242
1958 20:00:04.795633 CH1_RK1: MR19=0x606, MR18=0x4242, DQSOSC=393, MR23=63, INC=95, DEC=63
1959 20:00:04.796249 [RxdqsGatingPostProcess] freq 800
1960 20:00:04.802215 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1961 20:00:04.805470 Pre-setting of DQS Precalculation
1962 20:00:04.808906 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1963 20:00:04.819134 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1964 20:00:04.825806 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1965 20:00:04.826363
1966 20:00:04.826736
1967 20:00:04.828942 [Calibration Summary] 1600 Mbps
1968 20:00:04.829408 CH 0, Rank 0
1969 20:00:04.832613 SW Impedance : PASS
1970 20:00:04.833192 DUTY Scan : NO K
1971 20:00:04.835486 ZQ Calibration : PASS
1972 20:00:04.839352 Jitter Meter : NO K
1973 20:00:04.839924 CBT Training : PASS
1974 20:00:04.842463 Write leveling : PASS
1975 20:00:04.845618 RX DQS gating : PASS
1976 20:00:04.846091 RX DQ/DQS(RDDQC) : PASS
1977 20:00:04.848905 TX DQ/DQS : PASS
1978 20:00:04.852230 RX DATLAT : PASS
1979 20:00:04.852695 RX DQ/DQS(Engine): PASS
1980 20:00:04.855759 TX OE : NO K
1981 20:00:04.856372 All Pass.
1982 20:00:04.856756
1983 20:00:04.858935 CH 0, Rank 1
1984 20:00:04.859395 SW Impedance : PASS
1985 20:00:04.862347 DUTY Scan : NO K
1986 20:00:04.862901 ZQ Calibration : PASS
1987 20:00:04.865959 Jitter Meter : NO K
1988 20:00:04.869118 CBT Training : PASS
1989 20:00:04.869674 Write leveling : PASS
1990 20:00:04.872141 RX DQS gating : PASS
1991 20:00:04.875636 RX DQ/DQS(RDDQC) : PASS
1992 20:00:04.876237 TX DQ/DQS : PASS
1993 20:00:04.878982 RX DATLAT : PASS
1994 20:00:04.883025 RX DQ/DQS(Engine): PASS
1995 20:00:04.883584 TX OE : NO K
1996 20:00:04.885680 All Pass.
1997 20:00:04.886229
1998 20:00:04.886595 CH 1, Rank 0
1999 20:00:04.888884 SW Impedance : PASS
2000 20:00:04.889445 DUTY Scan : NO K
2001 20:00:04.892341 ZQ Calibration : PASS
2002 20:00:04.895879 Jitter Meter : NO K
2003 20:00:04.896498 CBT Training : PASS
2004 20:00:04.898968 Write leveling : PASS
2005 20:00:04.899519 RX DQS gating : PASS
2006 20:00:04.901941 RX DQ/DQS(RDDQC) : PASS
2007 20:00:04.905290 TX DQ/DQS : PASS
2008 20:00:04.905757 RX DATLAT : PASS
2009 20:00:04.909061 RX DQ/DQS(Engine): PASS
2010 20:00:04.912271 TX OE : NO K
2011 20:00:04.913014 All Pass.
2012 20:00:04.913466
2013 20:00:04.913815 CH 1, Rank 1
2014 20:00:04.915479 SW Impedance : PASS
2015 20:00:04.918777 DUTY Scan : NO K
2016 20:00:04.919241 ZQ Calibration : PASS
2017 20:00:04.922104 Jitter Meter : NO K
2018 20:00:04.925686 CBT Training : PASS
2019 20:00:04.926293 Write leveling : PASS
2020 20:00:04.929041 RX DQS gating : PASS
2021 20:00:04.932579 RX DQ/DQS(RDDQC) : PASS
2022 20:00:04.933138 TX DQ/DQS : PASS
2023 20:00:04.936102 RX DATLAT : PASS
2024 20:00:04.936700 RX DQ/DQS(Engine): PASS
2025 20:00:04.939108 TX OE : NO K
2026 20:00:04.939665 All Pass.
2027 20:00:04.940039
2028 20:00:04.942415 DramC Write-DBI off
2029 20:00:04.946016 PER_BANK_REFRESH: Hybrid Mode
2030 20:00:04.946479 TX_TRACKING: ON
2031 20:00:04.948950 [GetDramInforAfterCalByMRR] Vendor 6.
2032 20:00:04.952446 [GetDramInforAfterCalByMRR] Revision 606.
2033 20:00:04.955852 [GetDramInforAfterCalByMRR] Revision 2 0.
2034 20:00:04.959197 MR0 0x3939
2035 20:00:04.959751 MR8 0x1111
2036 20:00:04.962790 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2037 20:00:04.963349
2038 20:00:04.965924 MR0 0x3939
2039 20:00:04.966480 MR8 0x1111
2040 20:00:04.969103 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2041 20:00:04.969588
2042 20:00:04.979288 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2043 20:00:04.982571 [FAST_K] Save calibration result to emmc
2044 20:00:04.985759 [FAST_K] Save calibration result to emmc
2045 20:00:04.989023 dram_init: config_dvfs: 1
2046 20:00:04.992651 dramc_set_vcore_voltage set vcore to 662500
2047 20:00:04.993205 Read voltage for 1200, 2
2048 20:00:04.995746 Vio18 = 0
2049 20:00:04.996349 Vcore = 662500
2050 20:00:04.996730 Vdram = 0
2051 20:00:04.999147 Vddq = 0
2052 20:00:04.999701 Vmddr = 0
2053 20:00:05.002343 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2054 20:00:05.009056 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2055 20:00:05.012261 MEM_TYPE=3, freq_sel=15
2056 20:00:05.015737 sv_algorithm_assistance_LP4_1600
2057 20:00:05.018744 ============ PULL DRAM RESETB DOWN ============
2058 20:00:05.022224 ========== PULL DRAM RESETB DOWN end =========
2059 20:00:05.029065 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2060 20:00:05.032343 ===================================
2061 20:00:05.032919 LPDDR4 DRAM CONFIGURATION
2062 20:00:05.035434 ===================================
2063 20:00:05.039196 EX_ROW_EN[0] = 0x0
2064 20:00:05.039761 EX_ROW_EN[1] = 0x0
2065 20:00:05.042182 LP4Y_EN = 0x0
2066 20:00:05.042645 WORK_FSP = 0x0
2067 20:00:05.045490 WL = 0x4
2068 20:00:05.048836 RL = 0x4
2069 20:00:05.049298 BL = 0x2
2070 20:00:05.052337 RPST = 0x0
2071 20:00:05.052887 RD_PRE = 0x0
2072 20:00:05.055715 WR_PRE = 0x1
2073 20:00:05.056215 WR_PST = 0x0
2074 20:00:05.059150 DBI_WR = 0x0
2075 20:00:05.059702 DBI_RD = 0x0
2076 20:00:05.062379 OTF = 0x1
2077 20:00:05.065649 ===================================
2078 20:00:05.068941 ===================================
2079 20:00:05.069501 ANA top config
2080 20:00:05.072328 ===================================
2081 20:00:05.075659 DLL_ASYNC_EN = 0
2082 20:00:05.078983 ALL_SLAVE_EN = 0
2083 20:00:05.079537 NEW_RANK_MODE = 1
2084 20:00:05.082329 DLL_IDLE_MODE = 1
2085 20:00:05.085596 LP45_APHY_COMB_EN = 1
2086 20:00:05.088986 TX_ODT_DIS = 1
2087 20:00:05.089548 NEW_8X_MODE = 1
2088 20:00:05.092020 ===================================
2089 20:00:05.095430 ===================================
2090 20:00:05.098864 data_rate = 2400
2091 20:00:05.102213 CKR = 1
2092 20:00:05.105262 DQ_P2S_RATIO = 8
2093 20:00:05.108889 ===================================
2094 20:00:05.112089 CA_P2S_RATIO = 8
2095 20:00:05.115669 DQ_CA_OPEN = 0
2096 20:00:05.116478 DQ_SEMI_OPEN = 0
2097 20:00:05.119175 CA_SEMI_OPEN = 0
2098 20:00:05.122083 CA_FULL_RATE = 0
2099 20:00:05.125949 DQ_CKDIV4_EN = 0
2100 20:00:05.128984 CA_CKDIV4_EN = 0
2101 20:00:05.132350 CA_PREDIV_EN = 0
2102 20:00:05.132906 PH8_DLY = 17
2103 20:00:05.135634 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2104 20:00:05.139018 DQ_AAMCK_DIV = 4
2105 20:00:05.141959 CA_AAMCK_DIV = 4
2106 20:00:05.145746 CA_ADMCK_DIV = 4
2107 20:00:05.148913 DQ_TRACK_CA_EN = 0
2108 20:00:05.149480 CA_PICK = 1200
2109 20:00:05.151929 CA_MCKIO = 1200
2110 20:00:05.155548 MCKIO_SEMI = 0
2111 20:00:05.158830 PLL_FREQ = 2366
2112 20:00:05.162371 DQ_UI_PI_RATIO = 32
2113 20:00:05.165535 CA_UI_PI_RATIO = 0
2114 20:00:05.168857 ===================================
2115 20:00:05.172255 ===================================
2116 20:00:05.172724 memory_type:LPDDR4
2117 20:00:05.175484 GP_NUM : 10
2118 20:00:05.178820 SRAM_EN : 1
2119 20:00:05.179375 MD32_EN : 0
2120 20:00:05.182137 ===================================
2121 20:00:05.185268 [ANA_INIT] >>>>>>>>>>>>>>
2122 20:00:05.188615 <<<<<< [CONFIGURE PHASE]: ANA_TX
2123 20:00:05.192271 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2124 20:00:05.195802 ===================================
2125 20:00:05.198794 data_rate = 2400,PCW = 0X5b00
2126 20:00:05.202357 ===================================
2127 20:00:05.205213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2128 20:00:05.208927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2129 20:00:05.215536 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2130 20:00:05.218944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2131 20:00:05.221971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2132 20:00:05.225336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2133 20:00:05.228575 [ANA_INIT] flow start
2134 20:00:05.232563 [ANA_INIT] PLL >>>>>>>>
2135 20:00:05.233132 [ANA_INIT] PLL <<<<<<<<
2136 20:00:05.235403 [ANA_INIT] MIDPI >>>>>>>>
2137 20:00:05.239001 [ANA_INIT] MIDPI <<<<<<<<
2138 20:00:05.242308 [ANA_INIT] DLL >>>>>>>>
2139 20:00:05.242867 [ANA_INIT] DLL <<<<<<<<
2140 20:00:05.245196 [ANA_INIT] flow end
2141 20:00:05.248754 ============ LP4 DIFF to SE enter ============
2142 20:00:05.252146 ============ LP4 DIFF to SE exit ============
2143 20:00:05.255545 [ANA_INIT] <<<<<<<<<<<<<
2144 20:00:05.258924 [Flow] Enable top DCM control >>>>>
2145 20:00:05.262242 [Flow] Enable top DCM control <<<<<
2146 20:00:05.265275 Enable DLL master slave shuffle
2147 20:00:05.272051 ==============================================================
2148 20:00:05.272668 Gating Mode config
2149 20:00:05.278903 ==============================================================
2150 20:00:05.279459 Config description:
2151 20:00:05.289256 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2152 20:00:05.295627 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2153 20:00:05.302449 SELPH_MODE 0: By rank 1: By Phase
2154 20:00:05.305519 ==============================================================
2155 20:00:05.308764 GAT_TRACK_EN = 1
2156 20:00:05.312515 RX_GATING_MODE = 2
2157 20:00:05.315652 RX_GATING_TRACK_MODE = 2
2158 20:00:05.318927 SELPH_MODE = 1
2159 20:00:05.322005 PICG_EARLY_EN = 1
2160 20:00:05.325678 VALID_LAT_VALUE = 1
2161 20:00:05.328790 ==============================================================
2162 20:00:05.331901 Enter into Gating configuration >>>>
2163 20:00:05.335363 Exit from Gating configuration <<<<
2164 20:00:05.338751 Enter into DVFS_PRE_config >>>>>
2165 20:00:05.352051 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2166 20:00:05.352632 Exit from DVFS_PRE_config <<<<<
2167 20:00:05.355778 Enter into PICG configuration >>>>
2168 20:00:05.359203 Exit from PICG configuration <<<<
2169 20:00:05.362514 [RX_INPUT] configuration >>>>>
2170 20:00:05.365338 [RX_INPUT] configuration <<<<<
2171 20:00:05.372482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2172 20:00:05.375650 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2173 20:00:05.382295 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2174 20:00:05.389074 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2175 20:00:05.395533 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2176 20:00:05.402131 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2177 20:00:05.405321 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2178 20:00:05.408831 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2179 20:00:05.412340 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2180 20:00:05.419238 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2181 20:00:05.421883 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2182 20:00:05.424999 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2183 20:00:05.428907 ===================================
2184 20:00:05.432062 LPDDR4 DRAM CONFIGURATION
2185 20:00:05.435379 ===================================
2186 20:00:05.435937 EX_ROW_EN[0] = 0x0
2187 20:00:05.438722 EX_ROW_EN[1] = 0x0
2188 20:00:05.442255 LP4Y_EN = 0x0
2189 20:00:05.442826 WORK_FSP = 0x0
2190 20:00:05.445231 WL = 0x4
2191 20:00:05.445691 RL = 0x4
2192 20:00:05.448300 BL = 0x2
2193 20:00:05.448764 RPST = 0x0
2194 20:00:05.451718 RD_PRE = 0x0
2195 20:00:05.452214 WR_PRE = 0x1
2196 20:00:05.455631 WR_PST = 0x0
2197 20:00:05.456233 DBI_WR = 0x0
2198 20:00:05.458978 DBI_RD = 0x0
2199 20:00:05.459531 OTF = 0x1
2200 20:00:05.461656 ===================================
2201 20:00:05.465214 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2202 20:00:05.472107 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2203 20:00:05.475272 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2204 20:00:05.478416 ===================================
2205 20:00:05.481796 LPDDR4 DRAM CONFIGURATION
2206 20:00:05.485240 ===================================
2207 20:00:05.485703 EX_ROW_EN[0] = 0x10
2208 20:00:05.489143 EX_ROW_EN[1] = 0x0
2209 20:00:05.489604 LP4Y_EN = 0x0
2210 20:00:05.491871 WORK_FSP = 0x0
2211 20:00:05.492540 WL = 0x4
2212 20:00:05.495628 RL = 0x4
2213 20:00:05.496091 BL = 0x2
2214 20:00:05.498651 RPST = 0x0
2215 20:00:05.499111 RD_PRE = 0x0
2216 20:00:05.501923 WR_PRE = 0x1
2217 20:00:05.505061 WR_PST = 0x0
2218 20:00:05.505470 DBI_WR = 0x0
2219 20:00:05.508260 DBI_RD = 0x0
2220 20:00:05.508503 OTF = 0x1
2221 20:00:05.511662 ===================================
2222 20:00:05.518356 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2223 20:00:05.518515 ==
2224 20:00:05.521411 Dram Type= 6, Freq= 0, CH_0, rank 0
2225 20:00:05.524775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2226 20:00:05.524937 ==
2227 20:00:05.528083 [Duty_Offset_Calibration]
2228 20:00:05.528228 B0:0 B1:2 CA:1
2229 20:00:05.528336
2230 20:00:05.531945 [DutyScan_Calibration_Flow] k_type=0
2231 20:00:05.542354
2232 20:00:05.542490 ==CLK 0==
2233 20:00:05.545879 Final CLK duty delay cell = 0
2234 20:00:05.549333 [0] MAX Duty = 5093%(X100), DQS PI = 12
2235 20:00:05.552557 [0] MIN Duty = 4938%(X100), DQS PI = 54
2236 20:00:05.552693 [0] AVG Duty = 5015%(X100)
2237 20:00:05.555900
2238 20:00:05.559561 CH0 CLK Duty spec in!! Max-Min= 155%
2239 20:00:05.562714 [DutyScan_Calibration_Flow] ====Done====
2240 20:00:05.563179
2241 20:00:05.565870 [DutyScan_Calibration_Flow] k_type=1
2242 20:00:05.582289
2243 20:00:05.582799 ==DQS 0 ==
2244 20:00:05.585644 Final DQS duty delay cell = 0
2245 20:00:05.588980 [0] MAX Duty = 5125%(X100), DQS PI = 32
2246 20:00:05.592516 [0] MIN Duty = 5031%(X100), DQS PI = 4
2247 20:00:05.593031 [0] AVG Duty = 5078%(X100)
2248 20:00:05.595642
2249 20:00:05.596229 ==DQS 1 ==
2250 20:00:05.599091 Final DQS duty delay cell = 0
2251 20:00:05.602376 [0] MAX Duty = 5062%(X100), DQS PI = 58
2252 20:00:05.605518 [0] MIN Duty = 4906%(X100), DQS PI = 16
2253 20:00:05.606007 [0] AVG Duty = 4984%(X100)
2254 20:00:05.608795
2255 20:00:05.612645 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2256 20:00:05.613205
2257 20:00:05.615627 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2258 20:00:05.619465 [DutyScan_Calibration_Flow] ====Done====
2259 20:00:05.620024
2260 20:00:05.622066 [DutyScan_Calibration_Flow] k_type=3
2261 20:00:05.639407
2262 20:00:05.639965 ==DQM 0 ==
2263 20:00:05.642670 Final DQM duty delay cell = 0
2264 20:00:05.646120 [0] MAX Duty = 5187%(X100), DQS PI = 20
2265 20:00:05.649305 [0] MIN Duty = 4969%(X100), DQS PI = 54
2266 20:00:05.652513 [0] AVG Duty = 5078%(X100)
2267 20:00:05.652977
2268 20:00:05.653341 ==DQM 1 ==
2269 20:00:05.656053 Final DQM duty delay cell = 4
2270 20:00:05.659187 [4] MAX Duty = 5187%(X100), DQS PI = 54
2271 20:00:05.662846 [4] MIN Duty = 5000%(X100), DQS PI = 18
2272 20:00:05.663422 [4] AVG Duty = 5093%(X100)
2273 20:00:05.666244
2274 20:00:05.669543 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2275 20:00:05.670100
2276 20:00:05.672999 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2277 20:00:05.675847 [DutyScan_Calibration_Flow] ====Done====
2278 20:00:05.676344
2279 20:00:05.679183 [DutyScan_Calibration_Flow] k_type=2
2280 20:00:05.694593
2281 20:00:05.695198 ==DQ 0 ==
2282 20:00:05.697761 Final DQ duty delay cell = -4
2283 20:00:05.700906 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2284 20:00:05.704486 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2285 20:00:05.707566 [-4] AVG Duty = 4937%(X100)
2286 20:00:05.708030
2287 20:00:05.708458 ==DQ 1 ==
2288 20:00:05.711282 Final DQ duty delay cell = -4
2289 20:00:05.714559 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2290 20:00:05.717684 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2291 20:00:05.721361 [-4] AVG Duty = 4969%(X100)
2292 20:00:05.722270
2293 20:00:05.724356 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2294 20:00:05.724824
2295 20:00:05.727816 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2296 20:00:05.731226 [DutyScan_Calibration_Flow] ====Done====
2297 20:00:05.731781 ==
2298 20:00:05.734422 Dram Type= 6, Freq= 0, CH_1, rank 0
2299 20:00:05.737745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2300 20:00:05.738307 ==
2301 20:00:05.741067 [Duty_Offset_Calibration]
2302 20:00:05.741533 B0:0 B1:4 CA:-5
2303 20:00:05.741899
2304 20:00:05.744307 [DutyScan_Calibration_Flow] k_type=0
2305 20:00:05.755216
2306 20:00:05.755771 ==CLK 0==
2307 20:00:05.758543 Final CLK duty delay cell = 0
2308 20:00:05.761586 [0] MAX Duty = 5125%(X100), DQS PI = 10
2309 20:00:05.765441 [0] MIN Duty = 4907%(X100), DQS PI = 2
2310 20:00:05.766011 [0] AVG Duty = 5016%(X100)
2311 20:00:05.766387
2312 20:00:05.768091 CH1 CLK Duty spec in!! Max-Min= 218%
2313 20:00:05.775251 [DutyScan_Calibration_Flow] ====Done====
2314 20:00:05.775807
2315 20:00:05.778446 [DutyScan_Calibration_Flow] k_type=1
2316 20:00:05.793438
2317 20:00:05.793991 ==DQS 0 ==
2318 20:00:05.796793 Final DQS duty delay cell = 0
2319 20:00:05.800042 [0] MAX Duty = 5125%(X100), DQS PI = 16
2320 20:00:05.803540 [0] MIN Duty = 4875%(X100), DQS PI = 40
2321 20:00:05.804128 [0] AVG Duty = 5000%(X100)
2322 20:00:05.806824
2323 20:00:05.807283 ==DQS 1 ==
2324 20:00:05.810075 Final DQS duty delay cell = -4
2325 20:00:05.813516 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2326 20:00:05.817057 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2327 20:00:05.819992 [-4] AVG Duty = 4953%(X100)
2328 20:00:05.820493
2329 20:00:05.823093 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2330 20:00:05.823634
2331 20:00:05.826740 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2332 20:00:05.829748 [DutyScan_Calibration_Flow] ====Done====
2333 20:00:05.830211
2334 20:00:05.833236 [DutyScan_Calibration_Flow] k_type=3
2335 20:00:05.848312
2336 20:00:05.848884 ==DQM 0 ==
2337 20:00:05.851836 Final DQM duty delay cell = -4
2338 20:00:05.855438 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2339 20:00:05.858236 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2340 20:00:05.861820 [-4] AVG Duty = 4969%(X100)
2341 20:00:05.862372
2342 20:00:05.862741 ==DQM 1 ==
2343 20:00:05.865061 Final DQM duty delay cell = -4
2344 20:00:05.868512 [-4] MAX Duty = 5093%(X100), DQS PI = 20
2345 20:00:05.871623 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2346 20:00:05.874976 [-4] AVG Duty = 4984%(X100)
2347 20:00:05.875533
2348 20:00:05.878412 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2349 20:00:05.878987
2350 20:00:05.881575 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2351 20:00:05.885148 [DutyScan_Calibration_Flow] ====Done====
2352 20:00:05.885706
2353 20:00:05.888341 [DutyScan_Calibration_Flow] k_type=2
2354 20:00:05.905979
2355 20:00:05.906597 ==DQ 0 ==
2356 20:00:05.908985 Final DQ duty delay cell = 0
2357 20:00:05.912266 [0] MAX Duty = 5093%(X100), DQS PI = 32
2358 20:00:05.915384 [0] MIN Duty = 4969%(X100), DQS PI = 44
2359 20:00:05.915849 [0] AVG Duty = 5031%(X100)
2360 20:00:05.918733
2361 20:00:05.919188 ==DQ 1 ==
2362 20:00:05.921991 Final DQ duty delay cell = 0
2363 20:00:05.925636 [0] MAX Duty = 5000%(X100), DQS PI = 8
2364 20:00:05.928875 [0] MIN Duty = 4875%(X100), DQS PI = 30
2365 20:00:05.929340 [0] AVG Duty = 4937%(X100)
2366 20:00:05.929705
2367 20:00:05.932105 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2368 20:00:05.935865
2369 20:00:05.938808 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2370 20:00:05.941934 [DutyScan_Calibration_Flow] ====Done====
2371 20:00:05.945652 nWR fixed to 30
2372 20:00:05.946211 [ModeRegInit_LP4] CH0 RK0
2373 20:00:05.948905 [ModeRegInit_LP4] CH0 RK1
2374 20:00:05.952046 [ModeRegInit_LP4] CH1 RK0
2375 20:00:05.952537 [ModeRegInit_LP4] CH1 RK1
2376 20:00:05.955539 match AC timing 6
2377 20:00:05.958800 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2378 20:00:05.962784 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2379 20:00:05.968674 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2380 20:00:05.971976 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2381 20:00:05.978848 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2382 20:00:05.979311 ==
2383 20:00:05.982086 Dram Type= 6, Freq= 0, CH_0, rank 0
2384 20:00:05.985456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2385 20:00:05.985916 ==
2386 20:00:05.992378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2387 20:00:05.995663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2388 20:00:06.005411 [CA 0] Center 39 (9~70) winsize 62
2389 20:00:06.008453 [CA 1] Center 39 (8~70) winsize 63
2390 20:00:06.012123 [CA 2] Center 36 (5~67) winsize 63
2391 20:00:06.015345 [CA 3] Center 35 (4~66) winsize 63
2392 20:00:06.018810 [CA 4] Center 34 (3~65) winsize 63
2393 20:00:06.022013 [CA 5] Center 33 (3~64) winsize 62
2394 20:00:06.022576
2395 20:00:06.025243 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2396 20:00:06.025868
2397 20:00:06.028979 [CATrainingPosCal] consider 1 rank data
2398 20:00:06.032150 u2DelayCellTimex100 = 270/100 ps
2399 20:00:06.035623 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2400 20:00:06.039114 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2401 20:00:06.045447 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2402 20:00:06.048761 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2403 20:00:06.052030 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2404 20:00:06.055112 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2405 20:00:06.055572
2406 20:00:06.058590 CA PerBit enable=1, Macro0, CA PI delay=33
2407 20:00:06.059046
2408 20:00:06.061995 [CBTSetCACLKResult] CA Dly = 33
2409 20:00:06.062567 CS Dly: 7 (0~38)
2410 20:00:06.065084 ==
2411 20:00:06.065538 Dram Type= 6, Freq= 0, CH_0, rank 1
2412 20:00:06.072577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2413 20:00:06.073133 ==
2414 20:00:06.075510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2415 20:00:06.081968 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2416 20:00:06.090841 [CA 0] Center 39 (8~70) winsize 63
2417 20:00:06.093911 [CA 1] Center 39 (8~70) winsize 63
2418 20:00:06.097507 [CA 2] Center 36 (5~67) winsize 63
2419 20:00:06.100629 [CA 3] Center 35 (4~66) winsize 63
2420 20:00:06.104391 [CA 4] Center 33 (3~64) winsize 62
2421 20:00:06.107771 [CA 5] Center 34 (3~65) winsize 63
2422 20:00:06.108369
2423 20:00:06.110753 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2424 20:00:06.111302
2425 20:00:06.113956 [CATrainingPosCal] consider 2 rank data
2426 20:00:06.117518 u2DelayCellTimex100 = 270/100 ps
2427 20:00:06.120852 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2428 20:00:06.124015 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2429 20:00:06.130719 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2430 20:00:06.134244 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2431 20:00:06.137430 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2432 20:00:06.140888 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2433 20:00:06.141437
2434 20:00:06.144022 CA PerBit enable=1, Macro0, CA PI delay=33
2435 20:00:06.144614
2436 20:00:06.147086 [CBTSetCACLKResult] CA Dly = 33
2437 20:00:06.147543 CS Dly: 7 (0~39)
2438 20:00:06.147904
2439 20:00:06.150508 ----->DramcWriteLeveling(PI) begin...
2440 20:00:06.153752 ==
2441 20:00:06.157150 Dram Type= 6, Freq= 0, CH_0, rank 0
2442 20:00:06.160487 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2443 20:00:06.160950 ==
2444 20:00:06.164628 Write leveling (Byte 0): 28 => 28
2445 20:00:06.167095 Write leveling (Byte 1): 25 => 25
2446 20:00:06.170711 DramcWriteLeveling(PI) end<-----
2447 20:00:06.171281
2448 20:00:06.171657 ==
2449 20:00:06.173568 Dram Type= 6, Freq= 0, CH_0, rank 0
2450 20:00:06.177270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2451 20:00:06.177733 ==
2452 20:00:06.180542 [Gating] SW mode calibration
2453 20:00:06.187748 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2454 20:00:06.194106 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2455 20:00:06.197167 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2456 20:00:06.200636 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2457 20:00:06.203991 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2458 20:00:06.210818 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2459 20:00:06.214052 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2460 20:00:06.217141 0 11 20 | B1->B0 | 2d2d 2d2d | 1 0 | (1 0) (0 1)
2461 20:00:06.223814 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2462 20:00:06.227280 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2463 20:00:06.230340 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2464 20:00:06.237204 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2465 20:00:06.240644 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2466 20:00:06.243752 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2467 20:00:06.250284 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2468 20:00:06.253630 0 12 20 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)
2469 20:00:06.257024 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2470 20:00:06.263960 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2471 20:00:06.267190 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2472 20:00:06.270594 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2473 20:00:06.276893 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2474 20:00:06.280885 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2475 20:00:06.283639 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2476 20:00:06.290306 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2477 20:00:06.293774 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2478 20:00:06.297006 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 20:00:06.303669 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 20:00:06.306837 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 20:00:06.310433 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 20:00:06.314270 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 20:00:06.320653 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2484 20:00:06.323779 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2485 20:00:06.327166 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 20:00:06.333745 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 20:00:06.337025 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2488 20:00:06.340423 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2489 20:00:06.347246 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2490 20:00:06.350455 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2491 20:00:06.353838 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2492 20:00:06.360628 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2493 20:00:06.363640 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2494 20:00:06.366900 Total UI for P1: 0, mck2ui 16
2495 20:00:06.370454 best dqsien dly found for B0: ( 0, 15, 18)
2496 20:00:06.373709 Total UI for P1: 0, mck2ui 16
2497 20:00:06.377153 best dqsien dly found for B1: ( 0, 15, 20)
2498 20:00:06.380295 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2499 20:00:06.383657 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2500 20:00:06.384259
2501 20:00:06.387116 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2502 20:00:06.390565 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2503 20:00:06.393692 [Gating] SW calibration Done
2504 20:00:06.394159 ==
2505 20:00:06.397427 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 20:00:06.400813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2507 20:00:06.403627 ==
2508 20:00:06.404090 RX Vref Scan: 0
2509 20:00:06.404506
2510 20:00:06.407337 RX Vref 0 -> 0, step: 1
2511 20:00:06.407801
2512 20:00:06.409954 RX Delay -40 -> 252, step: 8
2513 20:00:06.413632 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2514 20:00:06.417161 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2515 20:00:06.420722 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2516 20:00:06.423303 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2517 20:00:06.430302 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2518 20:00:06.433731 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2519 20:00:06.437101 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2520 20:00:06.440423 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2521 20:00:06.443778 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2522 20:00:06.447075 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2523 20:00:06.453418 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2524 20:00:06.457167 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2525 20:00:06.461091 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2526 20:00:06.464045 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2527 20:00:06.467526 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2528 20:00:06.473941 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2529 20:00:06.474503 ==
2530 20:00:06.477531 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 20:00:06.480678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2532 20:00:06.481407 ==
2533 20:00:06.481796 DQS Delay:
2534 20:00:06.484288 DQS0 = 0, DQS1 = 0
2535 20:00:06.484752 DQM Delay:
2536 20:00:06.487529 DQM0 = 115, DQM1 = 106
2537 20:00:06.488087 DQ Delay:
2538 20:00:06.490772 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2539 20:00:06.494225 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2540 20:00:06.497495 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2541 20:00:06.500408 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2542 20:00:06.500964
2543 20:00:06.501336
2544 20:00:06.501682 ==
2545 20:00:06.503590 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 20:00:06.510356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2547 20:00:06.510825 ==
2548 20:00:06.511195
2549 20:00:06.511540
2550 20:00:06.511867 TX Vref Scan disable
2551 20:00:06.514448 == TX Byte 0 ==
2552 20:00:06.517922 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2553 20:00:06.520909 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2554 20:00:06.524331 == TX Byte 1 ==
2555 20:00:06.527618 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2556 20:00:06.530859 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2557 20:00:06.534446 ==
2558 20:00:06.537503 Dram Type= 6, Freq= 0, CH_0, rank 0
2559 20:00:06.541168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2560 20:00:06.541740 ==
2561 20:00:06.552548 TX Vref=22, minBit 9, minWin=25, winSum=415
2562 20:00:06.555666 TX Vref=24, minBit 8, minWin=25, winSum=417
2563 20:00:06.559134 TX Vref=26, minBit 9, minWin=25, winSum=429
2564 20:00:06.562390 TX Vref=28, minBit 9, minWin=25, winSum=436
2565 20:00:06.565861 TX Vref=30, minBit 8, minWin=26, winSum=438
2566 20:00:06.568870 TX Vref=32, minBit 8, minWin=26, winSum=436
2567 20:00:06.575758 [TxChooseVref] Worse bit 8, Min win 26, Win sum 438, Final Vref 30
2568 20:00:06.576366
2569 20:00:06.579082 Final TX Range 1 Vref 30
2570 20:00:06.579638
2571 20:00:06.580005 ==
2572 20:00:06.582089 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 20:00:06.585634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2574 20:00:06.586193 ==
2575 20:00:06.586560
2576 20:00:06.588699
2577 20:00:06.589160 TX Vref Scan disable
2578 20:00:06.592262 == TX Byte 0 ==
2579 20:00:06.595625 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2580 20:00:06.599347 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2581 20:00:06.602106 == TX Byte 1 ==
2582 20:00:06.605749 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2583 20:00:06.608616 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2584 20:00:06.609080
2585 20:00:06.612157 [DATLAT]
2586 20:00:06.612750 Freq=1200, CH0 RK0
2587 20:00:06.613119
2588 20:00:06.615419 DATLAT Default: 0xd
2589 20:00:06.615876 0, 0xFFFF, sum = 0
2590 20:00:06.619379 1, 0xFFFF, sum = 0
2591 20:00:06.619951 2, 0xFFFF, sum = 0
2592 20:00:06.621984 3, 0xFFFF, sum = 0
2593 20:00:06.622449 4, 0xFFFF, sum = 0
2594 20:00:06.625406 5, 0xFFFF, sum = 0
2595 20:00:06.625922 6, 0xFFFF, sum = 0
2596 20:00:06.629085 7, 0xFFFF, sum = 0
2597 20:00:06.632053 8, 0xFFFF, sum = 0
2598 20:00:06.632709 9, 0xFFFF, sum = 0
2599 20:00:06.635560 10, 0xFFFF, sum = 0
2600 20:00:06.636131 11, 0x0, sum = 1
2601 20:00:06.638744 12, 0x0, sum = 2
2602 20:00:06.639211 13, 0x0, sum = 3
2603 20:00:06.639583 14, 0x0, sum = 4
2604 20:00:06.642025 best_step = 12
2605 20:00:06.642482
2606 20:00:06.642847 ==
2607 20:00:06.645327 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 20:00:06.648743 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2609 20:00:06.649246 ==
2610 20:00:06.651957 RX Vref Scan: 1
2611 20:00:06.652597
2612 20:00:06.655859 Set Vref Range= 32 -> 127
2613 20:00:06.656464
2614 20:00:06.656841 RX Vref 32 -> 127, step: 1
2615 20:00:06.657187
2616 20:00:06.658725 RX Delay -21 -> 252, step: 4
2617 20:00:06.659183
2618 20:00:06.661952 Set Vref, RX VrefLevel [Byte0]: 32
2619 20:00:06.665487 [Byte1]: 32
2620 20:00:06.668898
2621 20:00:06.669449 Set Vref, RX VrefLevel [Byte0]: 33
2622 20:00:06.671906 [Byte1]: 33
2623 20:00:06.677012
2624 20:00:06.677574 Set Vref, RX VrefLevel [Byte0]: 34
2625 20:00:06.680097 [Byte1]: 34
2626 20:00:06.684799
2627 20:00:06.685363 Set Vref, RX VrefLevel [Byte0]: 35
2628 20:00:06.687801 [Byte1]: 35
2629 20:00:06.692552
2630 20:00:06.693120 Set Vref, RX VrefLevel [Byte0]: 36
2631 20:00:06.695841 [Byte1]: 36
2632 20:00:06.700619
2633 20:00:06.701191 Set Vref, RX VrefLevel [Byte0]: 37
2634 20:00:06.703668 [Byte1]: 37
2635 20:00:06.708407
2636 20:00:06.708963 Set Vref, RX VrefLevel [Byte0]: 38
2637 20:00:06.711317 [Byte1]: 38
2638 20:00:06.716644
2639 20:00:06.717212 Set Vref, RX VrefLevel [Byte0]: 39
2640 20:00:06.719641 [Byte1]: 39
2641 20:00:06.724128
2642 20:00:06.724728 Set Vref, RX VrefLevel [Byte0]: 40
2643 20:00:06.727561 [Byte1]: 40
2644 20:00:06.732345
2645 20:00:06.732889 Set Vref, RX VrefLevel [Byte0]: 41
2646 20:00:06.735438 [Byte1]: 41
2647 20:00:06.740263
2648 20:00:06.740818 Set Vref, RX VrefLevel [Byte0]: 42
2649 20:00:06.743462 [Byte1]: 42
2650 20:00:06.748026
2651 20:00:06.748630 Set Vref, RX VrefLevel [Byte0]: 43
2652 20:00:06.751158 [Byte1]: 43
2653 20:00:06.755581
2654 20:00:06.756038 Set Vref, RX VrefLevel [Byte0]: 44
2655 20:00:06.759107 [Byte1]: 44
2656 20:00:06.764052
2657 20:00:06.764662 Set Vref, RX VrefLevel [Byte0]: 45
2658 20:00:06.767272 [Byte1]: 45
2659 20:00:06.771797
2660 20:00:06.772405 Set Vref, RX VrefLevel [Byte0]: 46
2661 20:00:06.775113 [Byte1]: 46
2662 20:00:06.779598
2663 20:00:06.780153 Set Vref, RX VrefLevel [Byte0]: 47
2664 20:00:06.783044 [Byte1]: 47
2665 20:00:06.787611
2666 20:00:06.788162 Set Vref, RX VrefLevel [Byte0]: 48
2667 20:00:06.790819 [Byte1]: 48
2668 20:00:06.795711
2669 20:00:06.796336 Set Vref, RX VrefLevel [Byte0]: 49
2670 20:00:06.798981 [Byte1]: 49
2671 20:00:06.803437
2672 20:00:06.803982 Set Vref, RX VrefLevel [Byte0]: 50
2673 20:00:06.807299 [Byte1]: 50
2674 20:00:06.811170
2675 20:00:06.811627 Set Vref, RX VrefLevel [Byte0]: 51
2676 20:00:06.814614 [Byte1]: 51
2677 20:00:06.819401
2678 20:00:06.819954 Set Vref, RX VrefLevel [Byte0]: 52
2679 20:00:06.822591 [Byte1]: 52
2680 20:00:06.827031
2681 20:00:06.827570 Set Vref, RX VrefLevel [Byte0]: 53
2682 20:00:06.830728 [Byte1]: 53
2683 20:00:06.835394
2684 20:00:06.835945 Set Vref, RX VrefLevel [Byte0]: 54
2685 20:00:06.838438 [Byte1]: 54
2686 20:00:06.842917
2687 20:00:06.843377 Set Vref, RX VrefLevel [Byte0]: 55
2688 20:00:06.845977 [Byte1]: 55
2689 20:00:06.850986
2690 20:00:06.851444 Set Vref, RX VrefLevel [Byte0]: 56
2691 20:00:06.854053 [Byte1]: 56
2692 20:00:06.858972
2693 20:00:06.859563 Set Vref, RX VrefLevel [Byte0]: 57
2694 20:00:06.862772 [Byte1]: 57
2695 20:00:06.866896
2696 20:00:06.867456 Set Vref, RX VrefLevel [Byte0]: 58
2697 20:00:06.869881 [Byte1]: 58
2698 20:00:06.874651
2699 20:00:06.875216 Set Vref, RX VrefLevel [Byte0]: 59
2700 20:00:06.880988 [Byte1]: 59
2701 20:00:06.881542
2702 20:00:06.884663 Set Vref, RX VrefLevel [Byte0]: 60
2703 20:00:06.887857 [Byte1]: 60
2704 20:00:06.888475
2705 20:00:06.891383 Set Vref, RX VrefLevel [Byte0]: 61
2706 20:00:06.894587 [Byte1]: 61
2707 20:00:06.898353
2708 20:00:06.898915 Set Vref, RX VrefLevel [Byte0]: 62
2709 20:00:06.901831 [Byte1]: 62
2710 20:00:06.906684
2711 20:00:06.907253 Set Vref, RX VrefLevel [Byte0]: 63
2712 20:00:06.909657 [Byte1]: 63
2713 20:00:06.914015
2714 20:00:06.914476 Set Vref, RX VrefLevel [Byte0]: 64
2715 20:00:06.917657 [Byte1]: 64
2716 20:00:06.922411
2717 20:00:06.922963 Set Vref, RX VrefLevel [Byte0]: 65
2718 20:00:06.925391 [Byte1]: 65
2719 20:00:06.930157
2720 20:00:06.930704 Set Vref, RX VrefLevel [Byte0]: 66
2721 20:00:06.933463 [Byte1]: 66
2722 20:00:06.938393
2723 20:00:06.938941 Final RX Vref Byte 0 = 51 to rank0
2724 20:00:06.941243 Final RX Vref Byte 1 = 50 to rank0
2725 20:00:06.944642 Final RX Vref Byte 0 = 51 to rank1
2726 20:00:06.947923 Final RX Vref Byte 1 = 50 to rank1==
2727 20:00:06.951154 Dram Type= 6, Freq= 0, CH_0, rank 0
2728 20:00:06.957984 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2729 20:00:06.958463 ==
2730 20:00:06.958934 DQS Delay:
2731 20:00:06.959288 DQS0 = 0, DQS1 = 0
2732 20:00:06.961418 DQM Delay:
2733 20:00:06.961968 DQM0 = 114, DQM1 = 106
2734 20:00:06.964555 DQ Delay:
2735 20:00:06.967972 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2736 20:00:06.971500 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2737 20:00:06.974829 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =100
2738 20:00:06.978187 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2739 20:00:06.978743
2740 20:00:06.979110
2741 20:00:06.984836 [DQSOSCAuto] RK0, (LSB)MR18= 0x404, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2742 20:00:06.988214 CH0 RK0: MR19=404, MR18=404
2743 20:00:06.995016 CH0_RK0: MR19=0x404, MR18=0x404, DQSOSC=408, MR23=63, INC=39, DEC=26
2744 20:00:06.995587
2745 20:00:06.998328 ----->DramcWriteLeveling(PI) begin...
2746 20:00:06.998894 ==
2747 20:00:07.001570 Dram Type= 6, Freq= 0, CH_0, rank 1
2748 20:00:07.004591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2749 20:00:07.005054 ==
2750 20:00:07.007850 Write leveling (Byte 0): 27 => 27
2751 20:00:07.011225 Write leveling (Byte 1): 25 => 25
2752 20:00:07.014870 DramcWriteLeveling(PI) end<-----
2753 20:00:07.015433
2754 20:00:07.015807 ==
2755 20:00:07.018111 Dram Type= 6, Freq= 0, CH_0, rank 1
2756 20:00:07.021257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2757 20:00:07.024348 ==
2758 20:00:07.024899 [Gating] SW mode calibration
2759 20:00:07.034681 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2760 20:00:07.037765 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2761 20:00:07.041613 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2762 20:00:07.048040 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2763 20:00:07.051436 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2764 20:00:07.054745 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2765 20:00:07.061565 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2766 20:00:07.064378 0 11 20 | B1->B0 | 3030 2828 | 1 0 | (1 0) (0 0)
2767 20:00:07.067855 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2768 20:00:07.074631 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2769 20:00:07.078038 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2770 20:00:07.080952 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2771 20:00:07.088094 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2772 20:00:07.091110 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2773 20:00:07.094534 0 12 16 | B1->B0 | 2a2a 3939 | 1 1 | (0 0) (0 0)
2774 20:00:07.101239 0 12 20 | B1->B0 | 3737 4545 | 1 0 | (0 0) (0 0)
2775 20:00:07.104877 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2776 20:00:07.108203 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2777 20:00:07.111491 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2778 20:00:07.118193 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2779 20:00:07.121319 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2780 20:00:07.124734 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2781 20:00:07.131342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2782 20:00:07.134586 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2783 20:00:07.137697 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2784 20:00:07.144612 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 20:00:07.147775 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 20:00:07.151222 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 20:00:07.157680 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 20:00:07.160999 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2789 20:00:07.164374 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2790 20:00:07.171117 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2791 20:00:07.174620 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2792 20:00:07.177594 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2793 20:00:07.184667 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2794 20:00:07.187791 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2795 20:00:07.191381 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2796 20:00:07.197868 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2797 20:00:07.201022 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2798 20:00:07.205151 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2799 20:00:07.208363 Total UI for P1: 0, mck2ui 16
2800 20:00:07.211433 best dqsien dly found for B0: ( 0, 15, 16)
2801 20:00:07.214800 Total UI for P1: 0, mck2ui 16
2802 20:00:07.217994 best dqsien dly found for B1: ( 0, 15, 16)
2803 20:00:07.221020 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2804 20:00:07.224701 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
2805 20:00:07.225302
2806 20:00:07.227974 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2807 20:00:07.234309 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
2808 20:00:07.234856 [Gating] SW calibration Done
2809 20:00:07.235227 ==
2810 20:00:07.238084 Dram Type= 6, Freq= 0, CH_0, rank 1
2811 20:00:07.244779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2812 20:00:07.245343 ==
2813 20:00:07.245710 RX Vref Scan: 0
2814 20:00:07.246050
2815 20:00:07.248211 RX Vref 0 -> 0, step: 1
2816 20:00:07.248799
2817 20:00:07.251726 RX Delay -40 -> 252, step: 8
2818 20:00:07.255254 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2819 20:00:07.258275 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2820 20:00:07.261436 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2821 20:00:07.264788 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2822 20:00:07.271387 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2823 20:00:07.274757 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2824 20:00:07.278012 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2825 20:00:07.281383 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2826 20:00:07.284828 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2827 20:00:07.291439 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2828 20:00:07.294807 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2829 20:00:07.297891 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2830 20:00:07.301306 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2831 20:00:07.304776 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2832 20:00:07.311038 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2833 20:00:07.314288 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2834 20:00:07.314753 ==
2835 20:00:07.318278 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 20:00:07.321124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2837 20:00:07.321693 ==
2838 20:00:07.324606 DQS Delay:
2839 20:00:07.325238 DQS0 = 0, DQS1 = 0
2840 20:00:07.325624 DQM Delay:
2841 20:00:07.327553 DQM0 = 115, DQM1 = 106
2842 20:00:07.328012 DQ Delay:
2843 20:00:07.331166 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =107
2844 20:00:07.334300 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2845 20:00:07.337754 DQ8 =91, DQ9 =95, DQ10 =103, DQ11 =99
2846 20:00:07.344468 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =115
2847 20:00:07.345033
2848 20:00:07.345397
2849 20:00:07.345735 ==
2850 20:00:07.347485 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 20:00:07.351107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2852 20:00:07.351678 ==
2853 20:00:07.352049
2854 20:00:07.352443
2855 20:00:07.354142 TX Vref Scan disable
2856 20:00:07.354599 == TX Byte 0 ==
2857 20:00:07.361392 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2858 20:00:07.364366 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2859 20:00:07.364925 == TX Byte 1 ==
2860 20:00:07.370935 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2861 20:00:07.374423 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2862 20:00:07.374985 ==
2863 20:00:07.377530 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 20:00:07.380808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2865 20:00:07.381385 ==
2866 20:00:07.393718 TX Vref=22, minBit 8, minWin=25, winSum=416
2867 20:00:07.396906 TX Vref=24, minBit 1, minWin=26, winSum=425
2868 20:00:07.400534 TX Vref=26, minBit 11, minWin=25, winSum=429
2869 20:00:07.403858 TX Vref=28, minBit 9, minWin=26, winSum=430
2870 20:00:07.407234 TX Vref=30, minBit 10, minWin=26, winSum=434
2871 20:00:07.413871 TX Vref=32, minBit 9, minWin=26, winSum=431
2872 20:00:07.416857 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 30
2873 20:00:07.417417
2874 20:00:07.420711 Final TX Range 1 Vref 30
2875 20:00:07.421269
2876 20:00:07.421642 ==
2877 20:00:07.423416 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 20:00:07.427025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2879 20:00:07.430606 ==
2880 20:00:07.431165
2881 20:00:07.431534
2882 20:00:07.431877 TX Vref Scan disable
2883 20:00:07.433622 == TX Byte 0 ==
2884 20:00:07.437139 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2885 20:00:07.443589 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2886 20:00:07.444152 == TX Byte 1 ==
2887 20:00:07.447145 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2888 20:00:07.453681 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2889 20:00:07.454239
2890 20:00:07.454610 [DATLAT]
2891 20:00:07.454965 Freq=1200, CH0 RK1
2892 20:00:07.455336
2893 20:00:07.456920 DATLAT Default: 0xc
2894 20:00:07.457679 0, 0xFFFF, sum = 0
2895 20:00:07.460065 1, 0xFFFF, sum = 0
2896 20:00:07.463768 2, 0xFFFF, sum = 0
2897 20:00:07.464401 3, 0xFFFF, sum = 0
2898 20:00:07.466947 4, 0xFFFF, sum = 0
2899 20:00:07.467510 5, 0xFFFF, sum = 0
2900 20:00:07.471025 6, 0xFFFF, sum = 0
2901 20:00:07.471591 7, 0xFFFF, sum = 0
2902 20:00:07.473500 8, 0xFFFF, sum = 0
2903 20:00:07.473970 9, 0xFFFF, sum = 0
2904 20:00:07.476955 10, 0xFFFF, sum = 0
2905 20:00:07.477517 11, 0x0, sum = 1
2906 20:00:07.480577 12, 0x0, sum = 2
2907 20:00:07.481157 13, 0x0, sum = 3
2908 20:00:07.483502 14, 0x0, sum = 4
2909 20:00:07.483973 best_step = 12
2910 20:00:07.484378
2911 20:00:07.484725 ==
2912 20:00:07.486934 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 20:00:07.490849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2914 20:00:07.491418 ==
2915 20:00:07.494208 RX Vref Scan: 0
2916 20:00:07.494766
2917 20:00:07.496926 RX Vref 0 -> 0, step: 1
2918 20:00:07.497395
2919 20:00:07.497762 RX Delay -21 -> 252, step: 4
2920 20:00:07.503998 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2921 20:00:07.507545 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2922 20:00:07.511001 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2923 20:00:07.514433 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2924 20:00:07.517607 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2925 20:00:07.524780 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2926 20:00:07.527355 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2927 20:00:07.530935 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2928 20:00:07.534174 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2929 20:00:07.537547 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2930 20:00:07.544109 iDelay=199, Bit 10, Center 110 (47 ~ 174) 128
2931 20:00:07.547576 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2932 20:00:07.550676 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2933 20:00:07.554263 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
2934 20:00:07.557551 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2935 20:00:07.564429 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2936 20:00:07.564993 ==
2937 20:00:07.567656 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 20:00:07.570863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2939 20:00:07.571363 ==
2940 20:00:07.571741 DQS Delay:
2941 20:00:07.573937 DQS0 = 0, DQS1 = 0
2942 20:00:07.574397 DQM Delay:
2943 20:00:07.577415 DQM0 = 115, DQM1 = 106
2944 20:00:07.577984 DQ Delay:
2945 20:00:07.580562 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2946 20:00:07.583845 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =124
2947 20:00:07.587545 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2948 20:00:07.590763 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =114
2949 20:00:07.591332
2950 20:00:07.591698
2951 20:00:07.600841 [DQSOSCAuto] RK1, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
2952 20:00:07.604231 CH0 RK1: MR19=404, MR18=1414
2953 20:00:07.607324 CH0_RK1: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
2954 20:00:07.610483 [RxdqsGatingPostProcess] freq 1200
2955 20:00:07.617197 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2956 20:00:07.620815 Pre-setting of DQS Precalculation
2957 20:00:07.624297 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2958 20:00:07.627005 ==
2959 20:00:07.630977 Dram Type= 6, Freq= 0, CH_1, rank 0
2960 20:00:07.633643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2961 20:00:07.634111 ==
2962 20:00:07.637127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2963 20:00:07.643822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2964 20:00:07.653228 [CA 0] Center 37 (7~68) winsize 62
2965 20:00:07.656165 [CA 1] Center 37 (7~68) winsize 62
2966 20:00:07.659207 [CA 2] Center 34 (4~65) winsize 62
2967 20:00:07.662629 [CA 3] Center 33 (3~64) winsize 62
2968 20:00:07.665927 [CA 4] Center 32 (2~63) winsize 62
2969 20:00:07.669118 [CA 5] Center 32 (1~63) winsize 63
2970 20:00:07.669584
2971 20:00:07.672473 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2972 20:00:07.672938
2973 20:00:07.675820 [CATrainingPosCal] consider 1 rank data
2974 20:00:07.679609 u2DelayCellTimex100 = 270/100 ps
2975 20:00:07.682801 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2976 20:00:07.686062 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2977 20:00:07.692742 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2978 20:00:07.695991 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2979 20:00:07.699631 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2980 20:00:07.702889 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2981 20:00:07.703448
2982 20:00:07.706235 CA PerBit enable=1, Macro0, CA PI delay=32
2983 20:00:07.706798
2984 20:00:07.709265 [CBTSetCACLKResult] CA Dly = 32
2985 20:00:07.709730 CS Dly: 6 (0~37)
2986 20:00:07.710244 ==
2987 20:00:07.712794 Dram Type= 6, Freq= 0, CH_1, rank 1
2988 20:00:07.719650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2989 20:00:07.720268 ==
2990 20:00:07.722574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2991 20:00:07.729280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2992 20:00:07.738533 [CA 0] Center 37 (7~68) winsize 62
2993 20:00:07.740968 [CA 1] Center 37 (7~68) winsize 62
2994 20:00:07.744572 [CA 2] Center 34 (4~64) winsize 61
2995 20:00:07.748272 [CA 3] Center 34 (4~64) winsize 61
2996 20:00:07.751341 [CA 4] Center 32 (2~63) winsize 62
2997 20:00:07.754663 [CA 5] Center 32 (2~62) winsize 61
2998 20:00:07.755219
2999 20:00:07.757866 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3000 20:00:07.758330
3001 20:00:07.761393 [CATrainingPosCal] consider 2 rank data
3002 20:00:07.764558 u2DelayCellTimex100 = 270/100 ps
3003 20:00:07.767963 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
3004 20:00:07.771168 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
3005 20:00:07.778061 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
3006 20:00:07.781257 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
3007 20:00:07.784855 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3008 20:00:07.788228 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
3009 20:00:07.788808
3010 20:00:07.791478 CA PerBit enable=1, Macro0, CA PI delay=32
3011 20:00:07.792036
3012 20:00:07.794758 [CBTSetCACLKResult] CA Dly = 32
3013 20:00:07.795332 CS Dly: 6 (0~38)
3014 20:00:07.795708
3015 20:00:07.798057 ----->DramcWriteLeveling(PI) begin...
3016 20:00:07.801344 ==
3017 20:00:07.801919 Dram Type= 6, Freq= 0, CH_1, rank 0
3018 20:00:07.807856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3019 20:00:07.808467 ==
3020 20:00:07.811223 Write leveling (Byte 0): 20 => 20
3021 20:00:07.814290 Write leveling (Byte 1): 23 => 23
3022 20:00:07.818245 DramcWriteLeveling(PI) end<-----
3023 20:00:07.818814
3024 20:00:07.819189 ==
3025 20:00:07.821526 Dram Type= 6, Freq= 0, CH_1, rank 0
3026 20:00:07.824690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3027 20:00:07.825260 ==
3028 20:00:07.827833 [Gating] SW mode calibration
3029 20:00:07.834920 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3030 20:00:07.837985 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3031 20:00:07.844874 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3032 20:00:07.848074 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3033 20:00:07.850945 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3034 20:00:07.857818 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3035 20:00:07.861256 0 11 16 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (1 0)
3036 20:00:07.864695 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3037 20:00:07.871384 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3038 20:00:07.874432 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3039 20:00:07.877612 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3040 20:00:07.884273 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3041 20:00:07.887966 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3042 20:00:07.891174 0 12 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
3043 20:00:07.897677 0 12 16 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
3044 20:00:07.900904 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3045 20:00:07.904069 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3046 20:00:07.910987 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3047 20:00:07.914412 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3048 20:00:07.917742 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3049 20:00:07.924256 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3050 20:00:07.927701 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3051 20:00:07.930939 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3052 20:00:07.934623 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3053 20:00:07.941164 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3054 20:00:07.944713 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 20:00:07.948035 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 20:00:07.954317 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 20:00:07.958053 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 20:00:07.960927 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3059 20:00:07.967973 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3060 20:00:07.971462 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3061 20:00:07.974728 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3062 20:00:07.981022 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3063 20:00:07.984432 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3064 20:00:07.987742 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3065 20:00:07.994642 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3066 20:00:07.997718 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3067 20:00:08.001241 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3068 20:00:08.007988 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3069 20:00:08.008614 Total UI for P1: 0, mck2ui 16
3070 20:00:08.011018 best dqsien dly found for B0: ( 0, 15, 16)
3071 20:00:08.018079 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3072 20:00:08.021357 Total UI for P1: 0, mck2ui 16
3073 20:00:08.024621 best dqsien dly found for B1: ( 0, 15, 18)
3074 20:00:08.027810 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3075 20:00:08.031262 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3076 20:00:08.031728
3077 20:00:08.034437 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3078 20:00:08.037869 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3079 20:00:08.041346 [Gating] SW calibration Done
3080 20:00:08.041917 ==
3081 20:00:08.045059 Dram Type= 6, Freq= 0, CH_1, rank 0
3082 20:00:08.048078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3083 20:00:08.048684 ==
3084 20:00:08.051307 RX Vref Scan: 0
3085 20:00:08.051871
3086 20:00:08.054372 RX Vref 0 -> 0, step: 1
3087 20:00:08.054837
3088 20:00:08.055220 RX Delay -40 -> 252, step: 8
3089 20:00:08.060857 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3090 20:00:08.064608 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3091 20:00:08.067794 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3092 20:00:08.071432 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3093 20:00:08.074726 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3094 20:00:08.081031 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3095 20:00:08.084559 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3096 20:00:08.087757 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3097 20:00:08.091207 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3098 20:00:08.094163 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3099 20:00:08.101139 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3100 20:00:08.104398 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3101 20:00:08.107865 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3102 20:00:08.110888 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3103 20:00:08.114480 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3104 20:00:08.121610 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3105 20:00:08.122180 ==
3106 20:00:08.124723 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 20:00:08.127605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3108 20:00:08.128074 ==
3109 20:00:08.128636 DQS Delay:
3110 20:00:08.130938 DQS0 = 0, DQS1 = 0
3111 20:00:08.131397 DQM Delay:
3112 20:00:08.134538 DQM0 = 117, DQM1 = 109
3113 20:00:08.135099 DQ Delay:
3114 20:00:08.137394 DQ0 =119, DQ1 =111, DQ2 =111, DQ3 =115
3115 20:00:08.141153 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3116 20:00:08.144299 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3117 20:00:08.147658 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3118 20:00:08.148249
3119 20:00:08.148617
3120 20:00:08.150725 ==
3121 20:00:08.151182 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 20:00:08.157393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3123 20:00:08.157966 ==
3124 20:00:08.158337
3125 20:00:08.158677
3126 20:00:08.160709 TX Vref Scan disable
3127 20:00:08.161189 == TX Byte 0 ==
3128 20:00:08.163990 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3129 20:00:08.170632 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3130 20:00:08.171193 == TX Byte 1 ==
3131 20:00:08.174188 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3132 20:00:08.181214 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3133 20:00:08.181786 ==
3134 20:00:08.184132 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 20:00:08.187369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3136 20:00:08.187940 ==
3137 20:00:08.199726 TX Vref=22, minBit 0, minWin=25, winSum=409
3138 20:00:08.202840 TX Vref=24, minBit 1, minWin=25, winSum=417
3139 20:00:08.205644 TX Vref=26, minBit 1, minWin=25, winSum=420
3140 20:00:08.209401 TX Vref=28, minBit 3, minWin=26, winSum=426
3141 20:00:08.212298 TX Vref=30, minBit 8, minWin=26, winSum=430
3142 20:00:08.215941 TX Vref=32, minBit 1, minWin=26, winSum=426
3143 20:00:08.222459 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 30
3144 20:00:08.223036
3145 20:00:08.225884 Final TX Range 1 Vref 30
3146 20:00:08.226453
3147 20:00:08.226823 ==
3148 20:00:08.228898 Dram Type= 6, Freq= 0, CH_1, rank 0
3149 20:00:08.232906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3150 20:00:08.233374 ==
3151 20:00:08.233743
3152 20:00:08.236101
3153 20:00:08.236712 TX Vref Scan disable
3154 20:00:08.239574 == TX Byte 0 ==
3155 20:00:08.242994 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3156 20:00:08.246002 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3157 20:00:08.249481 == TX Byte 1 ==
3158 20:00:08.253030 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3159 20:00:08.255959 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3160 20:00:08.256463
3161 20:00:08.259720 [DATLAT]
3162 20:00:08.260343 Freq=1200, CH1 RK0
3163 20:00:08.260725
3164 20:00:08.262826 DATLAT Default: 0xd
3165 20:00:08.263292 0, 0xFFFF, sum = 0
3166 20:00:08.266261 1, 0xFFFF, sum = 0
3167 20:00:08.266839 2, 0xFFFF, sum = 0
3168 20:00:08.269276 3, 0xFFFF, sum = 0
3169 20:00:08.269744 4, 0xFFFF, sum = 0
3170 20:00:08.272702 5, 0xFFFF, sum = 0
3171 20:00:08.273171 6, 0xFFFF, sum = 0
3172 20:00:08.276014 7, 0xFFFF, sum = 0
3173 20:00:08.276613 8, 0xFFFF, sum = 0
3174 20:00:08.279428 9, 0xFFFF, sum = 0
3175 20:00:08.279986 10, 0xFFFF, sum = 0
3176 20:00:08.282986 11, 0x0, sum = 1
3177 20:00:08.283547 12, 0x0, sum = 2
3178 20:00:08.286149 13, 0x0, sum = 3
3179 20:00:08.286715 14, 0x0, sum = 4
3180 20:00:08.289601 best_step = 12
3181 20:00:08.290150
3182 20:00:08.290521 ==
3183 20:00:08.292658 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 20:00:08.296331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3185 20:00:08.296884 ==
3186 20:00:08.299672 RX Vref Scan: 1
3187 20:00:08.300293
3188 20:00:08.300672 Set Vref Range= 32 -> 127
3189 20:00:08.301017
3190 20:00:08.302470 RX Vref 32 -> 127, step: 1
3191 20:00:08.302933
3192 20:00:08.306166 RX Delay -21 -> 252, step: 4
3193 20:00:08.306727
3194 20:00:08.309457 Set Vref, RX VrefLevel [Byte0]: 32
3195 20:00:08.312727 [Byte1]: 32
3196 20:00:08.313194
3197 20:00:08.316087 Set Vref, RX VrefLevel [Byte0]: 33
3198 20:00:08.319353 [Byte1]: 33
3199 20:00:08.323788
3200 20:00:08.324410 Set Vref, RX VrefLevel [Byte0]: 34
3201 20:00:08.326776 [Byte1]: 34
3202 20:00:08.331625
3203 20:00:08.332233 Set Vref, RX VrefLevel [Byte0]: 35
3204 20:00:08.334975 [Byte1]: 35
3205 20:00:08.339706
3206 20:00:08.340296 Set Vref, RX VrefLevel [Byte0]: 36
3207 20:00:08.342780 [Byte1]: 36
3208 20:00:08.347606
3209 20:00:08.348160 Set Vref, RX VrefLevel [Byte0]: 37
3210 20:00:08.350513 [Byte1]: 37
3211 20:00:08.355243
3212 20:00:08.355797 Set Vref, RX VrefLevel [Byte0]: 38
3213 20:00:08.358531 [Byte1]: 38
3214 20:00:08.363298
3215 20:00:08.363920 Set Vref, RX VrefLevel [Byte0]: 39
3216 20:00:08.366207 [Byte1]: 39
3217 20:00:08.371171
3218 20:00:08.371737 Set Vref, RX VrefLevel [Byte0]: 40
3219 20:00:08.374418 [Byte1]: 40
3220 20:00:08.379128
3221 20:00:08.379695 Set Vref, RX VrefLevel [Byte0]: 41
3222 20:00:08.382791 [Byte1]: 41
3223 20:00:08.386639
3224 20:00:08.387106 Set Vref, RX VrefLevel [Byte0]: 42
3225 20:00:08.390234 [Byte1]: 42
3226 20:00:08.395038
3227 20:00:08.395600 Set Vref, RX VrefLevel [Byte0]: 43
3228 20:00:08.401486 [Byte1]: 43
3229 20:00:08.402054
3230 20:00:08.404766 Set Vref, RX VrefLevel [Byte0]: 44
3231 20:00:08.407929 [Byte1]: 44
3232 20:00:08.408435
3233 20:00:08.411396 Set Vref, RX VrefLevel [Byte0]: 45
3234 20:00:08.414747 [Byte1]: 45
3235 20:00:08.418829
3236 20:00:08.419393 Set Vref, RX VrefLevel [Byte0]: 46
3237 20:00:08.422056 [Byte1]: 46
3238 20:00:08.426694
3239 20:00:08.427272 Set Vref, RX VrefLevel [Byte0]: 47
3240 20:00:08.429809 [Byte1]: 47
3241 20:00:08.434663
3242 20:00:08.435228 Set Vref, RX VrefLevel [Byte0]: 48
3243 20:00:08.437570 [Byte1]: 48
3244 20:00:08.442473
3245 20:00:08.443034 Set Vref, RX VrefLevel [Byte0]: 49
3246 20:00:08.445811 [Byte1]: 49
3247 20:00:08.450543
3248 20:00:08.451109 Set Vref, RX VrefLevel [Byte0]: 50
3249 20:00:08.453789 [Byte1]: 50
3250 20:00:08.458612
3251 20:00:08.459173 Set Vref, RX VrefLevel [Byte0]: 51
3252 20:00:08.461522 [Byte1]: 51
3253 20:00:08.466274
3254 20:00:08.466836 Set Vref, RX VrefLevel [Byte0]: 52
3255 20:00:08.469466 [Byte1]: 52
3256 20:00:08.474288
3257 20:00:08.474850 Set Vref, RX VrefLevel [Byte0]: 53
3258 20:00:08.477404 [Byte1]: 53
3259 20:00:08.482033
3260 20:00:08.482588 Set Vref, RX VrefLevel [Byte0]: 54
3261 20:00:08.485127 [Byte1]: 54
3262 20:00:08.489966
3263 20:00:08.490525 Set Vref, RX VrefLevel [Byte0]: 55
3264 20:00:08.492832 [Byte1]: 55
3265 20:00:08.497828
3266 20:00:08.498456 Set Vref, RX VrefLevel [Byte0]: 56
3267 20:00:08.500940 [Byte1]: 56
3268 20:00:08.505818
3269 20:00:08.506372 Set Vref, RX VrefLevel [Byte0]: 57
3270 20:00:08.509064 [Byte1]: 57
3271 20:00:08.513939
3272 20:00:08.514490 Set Vref, RX VrefLevel [Byte0]: 58
3273 20:00:08.516720 [Byte1]: 58
3274 20:00:08.521478
3275 20:00:08.522059 Set Vref, RX VrefLevel [Byte0]: 59
3276 20:00:08.524587 [Byte1]: 59
3277 20:00:08.529305
3278 20:00:08.529780 Set Vref, RX VrefLevel [Byte0]: 60
3279 20:00:08.532676 [Byte1]: 60
3280 20:00:08.537317
3281 20:00:08.537875 Set Vref, RX VrefLevel [Byte0]: 61
3282 20:00:08.541135 [Byte1]: 61
3283 20:00:08.545178
3284 20:00:08.545738 Set Vref, RX VrefLevel [Byte0]: 62
3285 20:00:08.548762 [Byte1]: 62
3286 20:00:08.553094
3287 20:00:08.553649 Set Vref, RX VrefLevel [Byte0]: 63
3288 20:00:08.556503 [Byte1]: 63
3289 20:00:08.561169
3290 20:00:08.561725 Set Vref, RX VrefLevel [Byte0]: 64
3291 20:00:08.564475 [Byte1]: 64
3292 20:00:08.568859
3293 20:00:08.569423 Set Vref, RX VrefLevel [Byte0]: 65
3294 20:00:08.572593 [Byte1]: 65
3295 20:00:08.577040
3296 20:00:08.577606 Final RX Vref Byte 0 = 57 to rank0
3297 20:00:08.580405 Final RX Vref Byte 1 = 48 to rank0
3298 20:00:08.583620 Final RX Vref Byte 0 = 57 to rank1
3299 20:00:08.586950 Final RX Vref Byte 1 = 48 to rank1==
3300 20:00:08.590482 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 20:00:08.597464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3302 20:00:08.597933 ==
3303 20:00:08.598305 DQS Delay:
3304 20:00:08.598649 DQS0 = 0, DQS1 = 0
3305 20:00:08.600225 DQM Delay:
3306 20:00:08.600690 DQM0 = 114, DQM1 = 105
3307 20:00:08.603570 DQ Delay:
3308 20:00:08.607366 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3309 20:00:08.610512 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3310 20:00:08.613839 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3311 20:00:08.616883 DQ12 =114, DQ13 =116, DQ14 =112, DQ15 =114
3312 20:00:08.617351
3313 20:00:08.617715
3314 20:00:08.623792 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
3315 20:00:08.626924 CH1 RK0: MR19=404, MR18=1313
3316 20:00:08.634172 CH1_RK0: MR19=0x404, MR18=0x1313, DQSOSC=402, MR23=63, INC=40, DEC=27
3317 20:00:08.634758
3318 20:00:08.637029 ----->DramcWriteLeveling(PI) begin...
3319 20:00:08.637502 ==
3320 20:00:08.640563 Dram Type= 6, Freq= 0, CH_1, rank 1
3321 20:00:08.643805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3322 20:00:08.644411 ==
3323 20:00:08.647794 Write leveling (Byte 0): 21 => 21
3324 20:00:08.650472 Write leveling (Byte 1): 21 => 21
3325 20:00:08.653635 DramcWriteLeveling(PI) end<-----
3326 20:00:08.654101
3327 20:00:08.654468 ==
3328 20:00:08.656989 Dram Type= 6, Freq= 0, CH_1, rank 1
3329 20:00:08.660699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3330 20:00:08.663675 ==
3331 20:00:08.664137 [Gating] SW mode calibration
3332 20:00:08.673696 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3333 20:00:08.677097 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3334 20:00:08.680723 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3335 20:00:08.687348 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3336 20:00:08.690440 0 11 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3337 20:00:08.693677 0 11 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3338 20:00:08.700455 0 11 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
3339 20:00:08.703715 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3340 20:00:08.707420 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3341 20:00:08.713842 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3342 20:00:08.717146 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3343 20:00:08.720337 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3344 20:00:08.727258 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3345 20:00:08.730246 0 12 12 | B1->B0 | 2525 3f3f | 0 0 | (0 0) (0 0)
3346 20:00:08.733742 0 12 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3347 20:00:08.740422 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3348 20:00:08.743653 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3349 20:00:08.747146 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3350 20:00:08.753559 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3351 20:00:08.756980 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3352 20:00:08.760352 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3353 20:00:08.763705 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3354 20:00:08.770447 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3355 20:00:08.773552 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3356 20:00:08.776735 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 20:00:08.783619 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 20:00:08.787066 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 20:00:08.790144 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 20:00:08.797028 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 20:00:08.800246 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 20:00:08.803476 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 20:00:08.809990 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 20:00:08.813528 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3365 20:00:08.817208 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3366 20:00:08.823743 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3367 20:00:08.826872 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3368 20:00:08.830026 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3369 20:00:08.836811 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3370 20:00:08.840422 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3371 20:00:08.843636 Total UI for P1: 0, mck2ui 16
3372 20:00:08.847136 best dqsien dly found for B0: ( 0, 15, 12)
3373 20:00:08.850240 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3374 20:00:08.853447 Total UI for P1: 0, mck2ui 16
3375 20:00:08.856750 best dqsien dly found for B1: ( 0, 15, 16)
3376 20:00:08.859952 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3377 20:00:08.863326 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3378 20:00:08.863779
3379 20:00:08.866728 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3380 20:00:08.873285 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3381 20:00:08.873824 [Gating] SW calibration Done
3382 20:00:08.874184 ==
3383 20:00:08.876778 Dram Type= 6, Freq= 0, CH_1, rank 1
3384 20:00:08.883552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3385 20:00:08.884158 ==
3386 20:00:08.884610 RX Vref Scan: 0
3387 20:00:08.884948
3388 20:00:08.886884 RX Vref 0 -> 0, step: 1
3389 20:00:08.887436
3390 20:00:08.890322 RX Delay -40 -> 252, step: 8
3391 20:00:08.893272 iDelay=208, Bit 0, Center 115 (40 ~ 191) 152
3392 20:00:08.896989 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3393 20:00:08.900748 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3394 20:00:08.907220 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3395 20:00:08.910522 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3396 20:00:08.913238 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3397 20:00:08.916842 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3398 20:00:08.920028 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3399 20:00:08.923750 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3400 20:00:08.930225 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3401 20:00:08.934107 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3402 20:00:08.936832 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3403 20:00:08.940135 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3404 20:00:08.946914 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3405 20:00:08.949946 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3406 20:00:08.953124 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3407 20:00:08.953574 ==
3408 20:00:08.956552 Dram Type= 6, Freq= 0, CH_1, rank 1
3409 20:00:08.960355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3410 20:00:08.960915 ==
3411 20:00:08.963371 DQS Delay:
3412 20:00:08.963920 DQS0 = 0, DQS1 = 0
3413 20:00:08.966484 DQM Delay:
3414 20:00:08.967051 DQM0 = 116, DQM1 = 106
3415 20:00:08.967418 DQ Delay:
3416 20:00:08.970183 DQ0 =115, DQ1 =115, DQ2 =107, DQ3 =115
3417 20:00:08.976476 DQ4 =115, DQ5 =131, DQ6 =119, DQ7 =115
3418 20:00:08.980273 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =103
3419 20:00:08.983532 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3420 20:00:08.984085
3421 20:00:08.984507
3422 20:00:08.984848 ==
3423 20:00:08.986642 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 20:00:08.989911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3425 20:00:08.990473 ==
3426 20:00:08.990835
3427 20:00:08.991167
3428 20:00:08.993325 TX Vref Scan disable
3429 20:00:08.993879 == TX Byte 0 ==
3430 20:00:08.999818 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3431 20:00:09.003223 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3432 20:00:09.003695 == TX Byte 1 ==
3433 20:00:09.010115 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3434 20:00:09.013278 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3435 20:00:09.013876 ==
3436 20:00:09.016599 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 20:00:09.019700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3438 20:00:09.020159 ==
3439 20:00:09.032678 TX Vref=22, minBit 0, minWin=25, winSum=421
3440 20:00:09.035898 TX Vref=24, minBit 9, minWin=25, winSum=425
3441 20:00:09.039583 TX Vref=26, minBit 11, minWin=25, winSum=426
3442 20:00:09.043013 TX Vref=28, minBit 8, minWin=26, winSum=429
3443 20:00:09.046163 TX Vref=30, minBit 8, minWin=26, winSum=433
3444 20:00:09.049522 TX Vref=32, minBit 9, minWin=26, winSum=434
3445 20:00:09.055825 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3446 20:00:09.056455
3447 20:00:09.059568 Final TX Range 1 Vref 32
3448 20:00:09.060060
3449 20:00:09.060484 ==
3450 20:00:09.062405 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 20:00:09.065869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3452 20:00:09.066332 ==
3453 20:00:09.066694
3454 20:00:09.069219
3455 20:00:09.069673 TX Vref Scan disable
3456 20:00:09.072870 == TX Byte 0 ==
3457 20:00:09.075860 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3458 20:00:09.079345 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3459 20:00:09.082326 == TX Byte 1 ==
3460 20:00:09.086166 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3461 20:00:09.089348 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3462 20:00:09.089911
3463 20:00:09.092304 [DATLAT]
3464 20:00:09.092765 Freq=1200, CH1 RK1
3465 20:00:09.093130
3466 20:00:09.095909 DATLAT Default: 0xc
3467 20:00:09.096507 0, 0xFFFF, sum = 0
3468 20:00:09.099344 1, 0xFFFF, sum = 0
3469 20:00:09.100099 2, 0xFFFF, sum = 0
3470 20:00:09.102569 3, 0xFFFF, sum = 0
3471 20:00:09.103132 4, 0xFFFF, sum = 0
3472 20:00:09.105817 5, 0xFFFF, sum = 0
3473 20:00:09.106279 6, 0xFFFF, sum = 0
3474 20:00:09.109467 7, 0xFFFF, sum = 0
3475 20:00:09.112572 8, 0xFFFF, sum = 0
3476 20:00:09.113223 9, 0xFFFF, sum = 0
3477 20:00:09.116068 10, 0xFFFF, sum = 0
3478 20:00:09.116680 11, 0x0, sum = 1
3479 20:00:09.119255 12, 0x0, sum = 2
3480 20:00:09.119878 13, 0x0, sum = 3
3481 20:00:09.120322 14, 0x0, sum = 4
3482 20:00:09.122405 best_step = 12
3483 20:00:09.122955
3484 20:00:09.123318 ==
3485 20:00:09.125606 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 20:00:09.128852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3487 20:00:09.129348 ==
3488 20:00:09.132218 RX Vref Scan: 0
3489 20:00:09.132675
3490 20:00:09.133040 RX Vref 0 -> 0, step: 1
3491 20:00:09.135483
3492 20:00:09.135951 RX Delay -29 -> 252, step: 4
3493 20:00:09.142985 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3494 20:00:09.146415 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3495 20:00:09.149574 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3496 20:00:09.152631 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3497 20:00:09.156350 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3498 20:00:09.162576 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3499 20:00:09.166009 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3500 20:00:09.169653 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3501 20:00:09.172764 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3502 20:00:09.176663 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3503 20:00:09.183073 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3504 20:00:09.186342 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3505 20:00:09.189772 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3506 20:00:09.192882 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3507 20:00:09.196051 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144
3508 20:00:09.202755 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3509 20:00:09.203301 ==
3510 20:00:09.206587 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 20:00:09.209808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3512 20:00:09.210377 ==
3513 20:00:09.210742 DQS Delay:
3514 20:00:09.212772 DQS0 = 0, DQS1 = 0
3515 20:00:09.213277 DQM Delay:
3516 20:00:09.216908 DQM0 = 115, DQM1 = 103
3517 20:00:09.217464 DQ Delay:
3518 20:00:09.219589 DQ0 =114, DQ1 =112, DQ2 =108, DQ3 =112
3519 20:00:09.223062 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3520 20:00:09.226500 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3521 20:00:09.229559 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3522 20:00:09.230019
3523 20:00:09.230379
3524 20:00:09.239712 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
3525 20:00:09.240306 CH1 RK1: MR19=404, MR18=E0E
3526 20:00:09.246462 CH1_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
3527 20:00:09.249744 [RxdqsGatingPostProcess] freq 1200
3528 20:00:09.256437 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3529 20:00:09.259614 Pre-setting of DQS Precalculation
3530 20:00:09.262963 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3531 20:00:09.273028 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3532 20:00:09.279671 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3533 20:00:09.280276
3534 20:00:09.280653
3535 20:00:09.282712 [Calibration Summary] 2400 Mbps
3536 20:00:09.283250 CH 0, Rank 0
3537 20:00:09.286088 SW Impedance : PASS
3538 20:00:09.286644 DUTY Scan : NO K
3539 20:00:09.289750 ZQ Calibration : PASS
3540 20:00:09.292836 Jitter Meter : NO K
3541 20:00:09.293293 CBT Training : PASS
3542 20:00:09.295949 Write leveling : PASS
3543 20:00:09.299568 RX DQS gating : PASS
3544 20:00:09.300120 RX DQ/DQS(RDDQC) : PASS
3545 20:00:09.302747 TX DQ/DQS : PASS
3546 20:00:09.303302 RX DATLAT : PASS
3547 20:00:09.305985 RX DQ/DQS(Engine): PASS
3548 20:00:09.309646 TX OE : NO K
3549 20:00:09.310207 All Pass.
3550 20:00:09.310573
3551 20:00:09.310910 CH 0, Rank 1
3552 20:00:09.312838 SW Impedance : PASS
3553 20:00:09.316537 DUTY Scan : NO K
3554 20:00:09.317105 ZQ Calibration : PASS
3555 20:00:09.320022 Jitter Meter : NO K
3556 20:00:09.323068 CBT Training : PASS
3557 20:00:09.323626 Write leveling : PASS
3558 20:00:09.326493 RX DQS gating : PASS
3559 20:00:09.329439 RX DQ/DQS(RDDQC) : PASS
3560 20:00:09.329896 TX DQ/DQS : PASS
3561 20:00:09.332589 RX DATLAT : PASS
3562 20:00:09.336104 RX DQ/DQS(Engine): PASS
3563 20:00:09.336704 TX OE : NO K
3564 20:00:09.337222 All Pass.
3565 20:00:09.339545
3566 20:00:09.340024 CH 1, Rank 0
3567 20:00:09.343162 SW Impedance : PASS
3568 20:00:09.343742 DUTY Scan : NO K
3569 20:00:09.346084 ZQ Calibration : PASS
3570 20:00:09.346541 Jitter Meter : NO K
3571 20:00:09.349704 CBT Training : PASS
3572 20:00:09.352976 Write leveling : PASS
3573 20:00:09.353435 RX DQS gating : PASS
3574 20:00:09.356380 RX DQ/DQS(RDDQC) : PASS
3575 20:00:09.359620 TX DQ/DQS : PASS
3576 20:00:09.360216 RX DATLAT : PASS
3577 20:00:09.363011 RX DQ/DQS(Engine): PASS
3578 20:00:09.366068 TX OE : NO K
3579 20:00:09.366527 All Pass.
3580 20:00:09.366892
3581 20:00:09.367230 CH 1, Rank 1
3582 20:00:09.369911 SW Impedance : PASS
3583 20:00:09.373122 DUTY Scan : NO K
3584 20:00:09.373581 ZQ Calibration : PASS
3585 20:00:09.375860 Jitter Meter : NO K
3586 20:00:09.379761 CBT Training : PASS
3587 20:00:09.380366 Write leveling : PASS
3588 20:00:09.383071 RX DQS gating : PASS
3589 20:00:09.386587 RX DQ/DQS(RDDQC) : PASS
3590 20:00:09.387141 TX DQ/DQS : PASS
3591 20:00:09.389545 RX DATLAT : PASS
3592 20:00:09.390100 RX DQ/DQS(Engine): PASS
3593 20:00:09.392876 TX OE : NO K
3594 20:00:09.393335 All Pass.
3595 20:00:09.393699
3596 20:00:09.396022 DramC Write-DBI off
3597 20:00:09.399660 PER_BANK_REFRESH: Hybrid Mode
3598 20:00:09.400355 TX_TRACKING: ON
3599 20:00:09.409630 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3600 20:00:09.412686 [FAST_K] Save calibration result to emmc
3601 20:00:09.416257 dramc_set_vcore_voltage set vcore to 650000
3602 20:00:09.419809 Read voltage for 600, 5
3603 20:00:09.420424 Vio18 = 0
3604 20:00:09.420800 Vcore = 650000
3605 20:00:09.422942 Vdram = 0
3606 20:00:09.423513 Vddq = 0
3607 20:00:09.423880 Vmddr = 0
3608 20:00:09.429232 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3609 20:00:09.432742 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3610 20:00:09.436319 MEM_TYPE=3, freq_sel=19
3611 20:00:09.439368 sv_algorithm_assistance_LP4_1600
3612 20:00:09.442748 ============ PULL DRAM RESETB DOWN ============
3613 20:00:09.449595 ========== PULL DRAM RESETB DOWN end =========
3614 20:00:09.452841 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3615 20:00:09.456346 ===================================
3616 20:00:09.459405 LPDDR4 DRAM CONFIGURATION
3617 20:00:09.462806 ===================================
3618 20:00:09.463366 EX_ROW_EN[0] = 0x0
3619 20:00:09.465921 EX_ROW_EN[1] = 0x0
3620 20:00:09.466479 LP4Y_EN = 0x0
3621 20:00:09.469039 WORK_FSP = 0x0
3622 20:00:09.469495 WL = 0x2
3623 20:00:09.472837 RL = 0x2
3624 20:00:09.473394 BL = 0x2
3625 20:00:09.475952 RPST = 0x0
3626 20:00:09.476574 RD_PRE = 0x0
3627 20:00:09.479332 WR_PRE = 0x1
3628 20:00:09.479936 WR_PST = 0x0
3629 20:00:09.482478 DBI_WR = 0x0
3630 20:00:09.483032 DBI_RD = 0x0
3631 20:00:09.485822 OTF = 0x1
3632 20:00:09.489144 ===================================
3633 20:00:09.492366 ===================================
3634 20:00:09.492825 ANA top config
3635 20:00:09.495966 ===================================
3636 20:00:09.499264 DLL_ASYNC_EN = 0
3637 20:00:09.502602 ALL_SLAVE_EN = 1
3638 20:00:09.505831 NEW_RANK_MODE = 1
3639 20:00:09.509130 DLL_IDLE_MODE = 1
3640 20:00:09.509689 LP45_APHY_COMB_EN = 1
3641 20:00:09.512486 TX_ODT_DIS = 1
3642 20:00:09.515435 NEW_8X_MODE = 1
3643 20:00:09.518868 ===================================
3644 20:00:09.522804 ===================================
3645 20:00:09.525787 data_rate = 1200
3646 20:00:09.528782 CKR = 1
3647 20:00:09.529238 DQ_P2S_RATIO = 8
3648 20:00:09.532139 ===================================
3649 20:00:09.535521 CA_P2S_RATIO = 8
3650 20:00:09.539027 DQ_CA_OPEN = 0
3651 20:00:09.542190 DQ_SEMI_OPEN = 0
3652 20:00:09.545555 CA_SEMI_OPEN = 0
3653 20:00:09.548893 CA_FULL_RATE = 0
3654 20:00:09.549454 DQ_CKDIV4_EN = 1
3655 20:00:09.552410 CA_CKDIV4_EN = 1
3656 20:00:09.555031 CA_PREDIV_EN = 0
3657 20:00:09.558547 PH8_DLY = 0
3658 20:00:09.562033 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3659 20:00:09.565583 DQ_AAMCK_DIV = 4
3660 20:00:09.566145 CA_AAMCK_DIV = 4
3661 20:00:09.568691 CA_ADMCK_DIV = 4
3662 20:00:09.571958 DQ_TRACK_CA_EN = 0
3663 20:00:09.575711 CA_PICK = 600
3664 20:00:09.578963 CA_MCKIO = 600
3665 20:00:09.582391 MCKIO_SEMI = 0
3666 20:00:09.585833 PLL_FREQ = 2288
3667 20:00:09.586431 DQ_UI_PI_RATIO = 32
3668 20:00:09.588960 CA_UI_PI_RATIO = 0
3669 20:00:09.592239 ===================================
3670 20:00:09.595381 ===================================
3671 20:00:09.598984 memory_type:LPDDR4
3672 20:00:09.602245 GP_NUM : 10
3673 20:00:09.602800 SRAM_EN : 1
3674 20:00:09.605164 MD32_EN : 0
3675 20:00:09.608815 ===================================
3676 20:00:09.609377 [ANA_INIT] >>>>>>>>>>>>>>
3677 20:00:09.612065 <<<<<< [CONFIGURE PHASE]: ANA_TX
3678 20:00:09.615463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3679 20:00:09.618649 ===================================
3680 20:00:09.622334 data_rate = 1200,PCW = 0X5800
3681 20:00:09.625331 ===================================
3682 20:00:09.628679 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3683 20:00:09.635015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3684 20:00:09.641906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3685 20:00:09.645363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3686 20:00:09.648361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3687 20:00:09.651886 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3688 20:00:09.655222 [ANA_INIT] flow start
3689 20:00:09.655708 [ANA_INIT] PLL >>>>>>>>
3690 20:00:09.658393 [ANA_INIT] PLL <<<<<<<<
3691 20:00:09.661927 [ANA_INIT] MIDPI >>>>>>>>
3692 20:00:09.662489 [ANA_INIT] MIDPI <<<<<<<<
3693 20:00:09.664963 [ANA_INIT] DLL >>>>>>>>
3694 20:00:09.668276 [ANA_INIT] flow end
3695 20:00:09.671345 ============ LP4 DIFF to SE enter ============
3696 20:00:09.674839 ============ LP4 DIFF to SE exit ============
3697 20:00:09.678467 [ANA_INIT] <<<<<<<<<<<<<
3698 20:00:09.681634 [Flow] Enable top DCM control >>>>>
3699 20:00:09.684896 [Flow] Enable top DCM control <<<<<
3700 20:00:09.688211 Enable DLL master slave shuffle
3701 20:00:09.691742 ==============================================================
3702 20:00:09.695369 Gating Mode config
3703 20:00:09.701789 ==============================================================
3704 20:00:09.702349 Config description:
3705 20:00:09.711653 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3706 20:00:09.717934 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3707 20:00:09.724634 SELPH_MODE 0: By rank 1: By Phase
3708 20:00:09.728049 ==============================================================
3709 20:00:09.731361 GAT_TRACK_EN = 1
3710 20:00:09.734912 RX_GATING_MODE = 2
3711 20:00:09.738070 RX_GATING_TRACK_MODE = 2
3712 20:00:09.741397 SELPH_MODE = 1
3713 20:00:09.744695 PICG_EARLY_EN = 1
3714 20:00:09.748027 VALID_LAT_VALUE = 1
3715 20:00:09.751208 ==============================================================
3716 20:00:09.754590 Enter into Gating configuration >>>>
3717 20:00:09.757561 Exit from Gating configuration <<<<
3718 20:00:09.760912 Enter into DVFS_PRE_config >>>>>
3719 20:00:09.774386 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3720 20:00:09.777880 Exit from DVFS_PRE_config <<<<<
3721 20:00:09.778443 Enter into PICG configuration >>>>
3722 20:00:09.780895 Exit from PICG configuration <<<<
3723 20:00:09.784379 [RX_INPUT] configuration >>>>>
3724 20:00:09.787633 [RX_INPUT] configuration <<<<<
3725 20:00:09.794493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3726 20:00:09.798023 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3727 20:00:09.804445 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3728 20:00:09.811102 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3729 20:00:09.817547 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3730 20:00:09.824355 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3731 20:00:09.827532 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3732 20:00:09.830727 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3733 20:00:09.833996 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3734 20:00:09.840950 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3735 20:00:09.844162 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3736 20:00:09.847480 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3737 20:00:09.850976 ===================================
3738 20:00:09.853952 LPDDR4 DRAM CONFIGURATION
3739 20:00:09.857624 ===================================
3740 20:00:09.861068 EX_ROW_EN[0] = 0x0
3741 20:00:09.861648 EX_ROW_EN[1] = 0x0
3742 20:00:09.864212 LP4Y_EN = 0x0
3743 20:00:09.864855 WORK_FSP = 0x0
3744 20:00:09.867059 WL = 0x2
3745 20:00:09.867515 RL = 0x2
3746 20:00:09.870596 BL = 0x2
3747 20:00:09.871072 RPST = 0x0
3748 20:00:09.873925 RD_PRE = 0x0
3749 20:00:09.874491 WR_PRE = 0x1
3750 20:00:09.877575 WR_PST = 0x0
3751 20:00:09.878137 DBI_WR = 0x0
3752 20:00:09.880491 DBI_RD = 0x0
3753 20:00:09.880950 OTF = 0x1
3754 20:00:09.883657 ===================================
3755 20:00:09.890799 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3756 20:00:09.893891 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3757 20:00:09.896967 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3758 20:00:09.900485 ===================================
3759 20:00:09.903924 LPDDR4 DRAM CONFIGURATION
3760 20:00:09.907366 ===================================
3761 20:00:09.907936 EX_ROW_EN[0] = 0x10
3762 20:00:09.910312 EX_ROW_EN[1] = 0x0
3763 20:00:09.913735 LP4Y_EN = 0x0
3764 20:00:09.914299 WORK_FSP = 0x0
3765 20:00:09.917026 WL = 0x2
3766 20:00:09.917487 RL = 0x2
3767 20:00:09.920155 BL = 0x2
3768 20:00:09.920681 RPST = 0x0
3769 20:00:09.923436 RD_PRE = 0x0
3770 20:00:09.924023 WR_PRE = 0x1
3771 20:00:09.926711 WR_PST = 0x0
3772 20:00:09.927277 DBI_WR = 0x0
3773 20:00:09.929901 DBI_RD = 0x0
3774 20:00:09.930407 OTF = 0x1
3775 20:00:09.933406 ===================================
3776 20:00:09.940423 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3777 20:00:09.944792 nWR fixed to 30
3778 20:00:09.947678 [ModeRegInit_LP4] CH0 RK0
3779 20:00:09.948142 [ModeRegInit_LP4] CH0 RK1
3780 20:00:09.951303 [ModeRegInit_LP4] CH1 RK0
3781 20:00:09.954432 [ModeRegInit_LP4] CH1 RK1
3782 20:00:09.954899 match AC timing 16
3783 20:00:09.961221 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3784 20:00:09.964689 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3785 20:00:09.967556 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3786 20:00:09.974143 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3787 20:00:09.977916 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3788 20:00:09.978383 ==
3789 20:00:09.980958 Dram Type= 6, Freq= 0, CH_0, rank 0
3790 20:00:09.984113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3791 20:00:09.984631 ==
3792 20:00:09.990815 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3793 20:00:09.997550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3794 20:00:10.000779 [CA 0] Center 35 (5~66) winsize 62
3795 20:00:10.004304 [CA 1] Center 35 (5~66) winsize 62
3796 20:00:10.007723 [CA 2] Center 34 (4~65) winsize 62
3797 20:00:10.010896 [CA 3] Center 34 (3~65) winsize 63
3798 20:00:10.013799 [CA 4] Center 33 (3~64) winsize 62
3799 20:00:10.017523 [CA 5] Center 33 (3~64) winsize 62
3800 20:00:10.018096
3801 20:00:10.020581 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3802 20:00:10.021050
3803 20:00:10.024019 [CATrainingPosCal] consider 1 rank data
3804 20:00:10.027236 u2DelayCellTimex100 = 270/100 ps
3805 20:00:10.031080 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3806 20:00:10.033884 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3807 20:00:10.036960 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3808 20:00:10.040566 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3809 20:00:10.047399 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3810 20:00:10.050516 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3811 20:00:10.051084
3812 20:00:10.053626 CA PerBit enable=1, Macro0, CA PI delay=33
3813 20:00:10.054093
3814 20:00:10.056866 [CBTSetCACLKResult] CA Dly = 33
3815 20:00:10.057330 CS Dly: 4 (0~35)
3816 20:00:10.057718 ==
3817 20:00:10.060353 Dram Type= 6, Freq= 0, CH_0, rank 1
3818 20:00:10.067049 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3819 20:00:10.067606 ==
3820 20:00:10.070532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3821 20:00:10.077034 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3822 20:00:10.080094 [CA 0] Center 35 (5~66) winsize 62
3823 20:00:10.083920 [CA 1] Center 35 (5~66) winsize 62
3824 20:00:10.087082 [CA 2] Center 34 (4~65) winsize 62
3825 20:00:10.090480 [CA 3] Center 34 (4~65) winsize 62
3826 20:00:10.093592 [CA 4] Center 33 (3~64) winsize 62
3827 20:00:10.096975 [CA 5] Center 33 (3~64) winsize 62
3828 20:00:10.097532
3829 20:00:10.100290 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3830 20:00:10.100849
3831 20:00:10.103301 [CATrainingPosCal] consider 2 rank data
3832 20:00:10.106624 u2DelayCellTimex100 = 270/100 ps
3833 20:00:10.110152 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3834 20:00:10.113616 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3835 20:00:10.119960 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3836 20:00:10.123467 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3837 20:00:10.126882 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3838 20:00:10.130111 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3839 20:00:10.130667
3840 20:00:10.133212 CA PerBit enable=1, Macro0, CA PI delay=33
3841 20:00:10.133705
3842 20:00:10.136733 [CBTSetCACLKResult] CA Dly = 33
3843 20:00:10.137301 CS Dly: 4 (0~36)
3844 20:00:10.137673
3845 20:00:10.139923 ----->DramcWriteLeveling(PI) begin...
3846 20:00:10.143635 ==
3847 20:00:10.146443 Dram Type= 6, Freq= 0, CH_0, rank 0
3848 20:00:10.149667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3849 20:00:10.150158 ==
3850 20:00:10.152938 Write leveling (Byte 0): 31 => 31
3851 20:00:10.156555 Write leveling (Byte 1): 28 => 28
3852 20:00:10.159548 DramcWriteLeveling(PI) end<-----
3853 20:00:10.160011
3854 20:00:10.160505 ==
3855 20:00:10.162741 Dram Type= 6, Freq= 0, CH_0, rank 0
3856 20:00:10.166197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3857 20:00:10.166659 ==
3858 20:00:10.169555 [Gating] SW mode calibration
3859 20:00:10.176305 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3860 20:00:10.183191 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3861 20:00:10.186242 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3862 20:00:10.189595 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3863 20:00:10.193034 0 5 8 | B1->B0 | 3333 3131 | 1 0 | (1 0) (0 1)
3864 20:00:10.199626 0 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3865 20:00:10.202998 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3866 20:00:10.206358 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3867 20:00:10.212890 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3868 20:00:10.216059 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3869 20:00:10.219261 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3870 20:00:10.226161 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3871 20:00:10.229478 0 6 8 | B1->B0 | 2e2e 3131 | 1 1 | (1 1) (0 0)
3872 20:00:10.232656 0 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3873 20:00:10.239321 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3874 20:00:10.242845 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3875 20:00:10.245947 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3876 20:00:10.252436 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3877 20:00:10.255893 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3878 20:00:10.258899 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3879 20:00:10.265741 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3880 20:00:10.268791 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3881 20:00:10.272583 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 20:00:10.279226 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 20:00:10.282577 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 20:00:10.285478 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 20:00:10.292226 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 20:00:10.295535 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 20:00:10.298715 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 20:00:10.305676 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 20:00:10.308860 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 20:00:10.312152 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 20:00:10.318928 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3892 20:00:10.322295 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3893 20:00:10.325367 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3894 20:00:10.332108 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3895 20:00:10.335523 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3896 20:00:10.339233 Total UI for P1: 0, mck2ui 16
3897 20:00:10.342278 best dqsien dly found for B0: ( 0, 9, 6)
3898 20:00:10.345355 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3899 20:00:10.349228 Total UI for P1: 0, mck2ui 16
3900 20:00:10.352214 best dqsien dly found for B1: ( 0, 9, 8)
3901 20:00:10.355124 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3902 20:00:10.358718 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3903 20:00:10.359281
3904 20:00:10.362104 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3905 20:00:10.368737 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3906 20:00:10.369298 [Gating] SW calibration Done
3907 20:00:10.369664 ==
3908 20:00:10.372051 Dram Type= 6, Freq= 0, CH_0, rank 0
3909 20:00:10.378453 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3910 20:00:10.378989 ==
3911 20:00:10.379363 RX Vref Scan: 0
3912 20:00:10.379707
3913 20:00:10.382212 RX Vref 0 -> 0, step: 1
3914 20:00:10.382783
3915 20:00:10.385002 RX Delay -230 -> 252, step: 16
3916 20:00:10.388647 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3917 20:00:10.391908 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3918 20:00:10.395209 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3919 20:00:10.401441 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3920 20:00:10.405148 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3921 20:00:10.408457 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3922 20:00:10.412209 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3923 20:00:10.418455 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3924 20:00:10.421877 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3925 20:00:10.424776 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3926 20:00:10.428606 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3927 20:00:10.431593 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3928 20:00:10.438588 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3929 20:00:10.441641 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3930 20:00:10.444759 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3931 20:00:10.451565 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3932 20:00:10.452122 ==
3933 20:00:10.454820 Dram Type= 6, Freq= 0, CH_0, rank 0
3934 20:00:10.457824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3935 20:00:10.458286 ==
3936 20:00:10.458649 DQS Delay:
3937 20:00:10.461726 DQS0 = 0, DQS1 = 0
3938 20:00:10.462287 DQM Delay:
3939 20:00:10.464728 DQM0 = 38, DQM1 = 33
3940 20:00:10.465288 DQ Delay:
3941 20:00:10.468458 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3942 20:00:10.471305 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3943 20:00:10.474864 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3944 20:00:10.478126 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3945 20:00:10.478592
3946 20:00:10.478957
3947 20:00:10.479290 ==
3948 20:00:10.481086 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 20:00:10.484668 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 20:00:10.485128 ==
3951 20:00:10.485493
3952 20:00:10.485850
3953 20:00:10.487874 TX Vref Scan disable
3954 20:00:10.491286 == TX Byte 0 ==
3955 20:00:10.494554 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3956 20:00:10.497863 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3957 20:00:10.501614 == TX Byte 1 ==
3958 20:00:10.504288 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
3959 20:00:10.507793 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
3960 20:00:10.508396 ==
3961 20:00:10.511360 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 20:00:10.517918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3963 20:00:10.518497 ==
3964 20:00:10.518869
3965 20:00:10.519207
3966 20:00:10.519534 TX Vref Scan disable
3967 20:00:10.522270 == TX Byte 0 ==
3968 20:00:10.525210 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3969 20:00:10.531734 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3970 20:00:10.532260 == TX Byte 1 ==
3971 20:00:10.535017 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3972 20:00:10.542045 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3973 20:00:10.542615
3974 20:00:10.542989 [DATLAT]
3975 20:00:10.543336 Freq=600, CH0 RK0
3976 20:00:10.543669
3977 20:00:10.544889 DATLAT Default: 0x9
3978 20:00:10.548644 0, 0xFFFF, sum = 0
3979 20:00:10.549217 1, 0xFFFF, sum = 0
3980 20:00:10.551646 2, 0xFFFF, sum = 0
3981 20:00:10.552236 3, 0xFFFF, sum = 0
3982 20:00:10.554858 4, 0xFFFF, sum = 0
3983 20:00:10.555327 5, 0xFFFF, sum = 0
3984 20:00:10.558280 6, 0xFFFF, sum = 0
3985 20:00:10.558749 7, 0x0, sum = 1
3986 20:00:10.561300 8, 0x0, sum = 2
3987 20:00:10.561771 9, 0x0, sum = 3
3988 20:00:10.562149 10, 0x0, sum = 4
3989 20:00:10.565113 best_step = 8
3990 20:00:10.565683
3991 20:00:10.566057 ==
3992 20:00:10.568329 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 20:00:10.571551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3994 20:00:10.572141 ==
3995 20:00:10.574655 RX Vref Scan: 1
3996 20:00:10.575118
3997 20:00:10.575487 RX Vref 0 -> 0, step: 1
3998 20:00:10.577996
3999 20:00:10.578455 RX Delay -195 -> 252, step: 8
4000 20:00:10.578826
4001 20:00:10.581119 Set Vref, RX VrefLevel [Byte0]: 51
4002 20:00:10.584655 [Byte1]: 50
4003 20:00:10.589391
4004 20:00:10.589956 Final RX Vref Byte 0 = 51 to rank0
4005 20:00:10.592321 Final RX Vref Byte 1 = 50 to rank0
4006 20:00:10.595761 Final RX Vref Byte 0 = 51 to rank1
4007 20:00:10.598983 Final RX Vref Byte 1 = 50 to rank1==
4008 20:00:10.602298 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 20:00:10.608720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4010 20:00:10.609190 ==
4011 20:00:10.609558 DQS Delay:
4012 20:00:10.609906 DQS0 = 0, DQS1 = 0
4013 20:00:10.612150 DQM Delay:
4014 20:00:10.612652 DQM0 = 40, DQM1 = 30
4015 20:00:10.615443 DQ Delay:
4016 20:00:10.618800 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =40
4017 20:00:10.622205 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =52
4018 20:00:10.625555 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
4019 20:00:10.628573 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4020 20:00:10.628900
4021 20:00:10.629138
4022 20:00:10.635123 [DQSOSCAuto] RK0, (LSB)MR18= 0x5656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4023 20:00:10.638433 CH0 RK0: MR19=808, MR18=5656
4024 20:00:10.645261 CH0_RK0: MR19=0x808, MR18=0x5656, DQSOSC=393, MR23=63, INC=169, DEC=113
4025 20:00:10.645563
4026 20:00:10.648396 ----->DramcWriteLeveling(PI) begin...
4027 20:00:10.648699 ==
4028 20:00:10.651747 Dram Type= 6, Freq= 0, CH_0, rank 1
4029 20:00:10.655109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4030 20:00:10.655411 ==
4031 20:00:10.658159 Write leveling (Byte 0): 30 => 30
4032 20:00:10.661338 Write leveling (Byte 1): 30 => 30
4033 20:00:10.664813 DramcWriteLeveling(PI) end<-----
4034 20:00:10.664996
4035 20:00:10.665138 ==
4036 20:00:10.667943 Dram Type= 6, Freq= 0, CH_0, rank 1
4037 20:00:10.671313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4038 20:00:10.671466 ==
4039 20:00:10.674788 [Gating] SW mode calibration
4040 20:00:10.681249 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4041 20:00:10.687788 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4042 20:00:10.691138 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 20:00:10.697700 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 20:00:10.701033 0 5 8 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 1)
4045 20:00:10.704444 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4046 20:00:10.711030 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 20:00:10.714556 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 20:00:10.717967 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 20:00:10.724836 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 20:00:10.727928 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 20:00:10.731144 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 20:00:10.738040 0 6 8 | B1->B0 | 2727 3636 | 0 1 | (0 0) (0 0)
4053 20:00:10.741337 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4054 20:00:10.744433 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 20:00:10.750896 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 20:00:10.754074 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 20:00:10.758008 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 20:00:10.764400 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 20:00:10.767491 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 20:00:10.770725 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4061 20:00:10.774069 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 20:00:10.780650 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 20:00:10.783857 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 20:00:10.787129 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 20:00:10.794219 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 20:00:10.797570 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 20:00:10.800943 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 20:00:10.807604 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 20:00:10.811341 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 20:00:10.814311 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 20:00:10.821071 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 20:00:10.824433 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 20:00:10.827892 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 20:00:10.834153 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 20:00:10.837542 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 20:00:10.840891 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4077 20:00:10.847795 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4078 20:00:10.848483 Total UI for P1: 0, mck2ui 16
4079 20:00:10.854168 best dqsien dly found for B0: ( 0, 9, 8)
4080 20:00:10.857586 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 20:00:10.861048 Total UI for P1: 0, mck2ui 16
4082 20:00:10.864224 best dqsien dly found for B1: ( 0, 9, 10)
4083 20:00:10.867429 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4084 20:00:10.870946 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4085 20:00:10.871517
4086 20:00:10.874278 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4087 20:00:10.877242 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4088 20:00:10.880575 [Gating] SW calibration Done
4089 20:00:10.881038 ==
4090 20:00:10.884027 Dram Type= 6, Freq= 0, CH_0, rank 1
4091 20:00:10.887302 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4092 20:00:10.890725 ==
4093 20:00:10.891295 RX Vref Scan: 0
4094 20:00:10.891669
4095 20:00:10.894007 RX Vref 0 -> 0, step: 1
4096 20:00:10.894636
4097 20:00:10.897399 RX Delay -230 -> 252, step: 16
4098 20:00:10.900755 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4099 20:00:10.903758 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4100 20:00:10.907275 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4101 20:00:10.913847 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4102 20:00:10.916961 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4103 20:00:10.920512 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4104 20:00:10.923820 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4105 20:00:10.927002 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4106 20:00:10.933644 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4107 20:00:10.936887 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4108 20:00:10.940279 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4109 20:00:10.943705 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4110 20:00:10.950109 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4111 20:00:10.953532 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4112 20:00:10.956898 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4113 20:00:10.960155 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4114 20:00:10.960756 ==
4115 20:00:10.963333 Dram Type= 6, Freq= 0, CH_0, rank 1
4116 20:00:10.970032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4117 20:00:10.970501 ==
4118 20:00:10.970872 DQS Delay:
4119 20:00:10.973375 DQS0 = 0, DQS1 = 0
4120 20:00:10.973935 DQM Delay:
4121 20:00:10.976593 DQM0 = 40, DQM1 = 33
4122 20:00:10.977296 DQ Delay:
4123 20:00:10.979997 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4124 20:00:10.983342 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4125 20:00:10.987097 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4126 20:00:10.990109 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4127 20:00:10.990666
4128 20:00:10.991039
4129 20:00:10.991382 ==
4130 20:00:10.993297 Dram Type= 6, Freq= 0, CH_0, rank 1
4131 20:00:10.996384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4132 20:00:10.996868 ==
4133 20:00:10.997236
4134 20:00:10.997582
4135 20:00:11.000002 TX Vref Scan disable
4136 20:00:11.003361 == TX Byte 0 ==
4137 20:00:11.006700 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4138 20:00:11.009876 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4139 20:00:11.012883 == TX Byte 1 ==
4140 20:00:11.016520 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4141 20:00:11.019880 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4142 20:00:11.020504 ==
4143 20:00:11.023024 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 20:00:11.026280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4145 20:00:11.030071 ==
4146 20:00:11.030632
4147 20:00:11.030999
4148 20:00:11.031424 TX Vref Scan disable
4149 20:00:11.033405 == TX Byte 0 ==
4150 20:00:11.036973 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4151 20:00:11.040757 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4152 20:00:11.043591 == TX Byte 1 ==
4153 20:00:11.047490 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4154 20:00:11.050233 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4155 20:00:11.053503
4156 20:00:11.054058 [DATLAT]
4157 20:00:11.054429 Freq=600, CH0 RK1
4158 20:00:11.054773
4159 20:00:11.056722 DATLAT Default: 0x8
4160 20:00:11.057188 0, 0xFFFF, sum = 0
4161 20:00:11.060329 1, 0xFFFF, sum = 0
4162 20:00:11.060891 2, 0xFFFF, sum = 0
4163 20:00:11.063535 3, 0xFFFF, sum = 0
4164 20:00:11.064005 4, 0xFFFF, sum = 0
4165 20:00:11.067179 5, 0xFFFF, sum = 0
4166 20:00:11.070201 6, 0xFFFF, sum = 0
4167 20:00:11.070759 7, 0x0, sum = 1
4168 20:00:11.071136 8, 0x0, sum = 2
4169 20:00:11.073618 9, 0x0, sum = 3
4170 20:00:11.074181 10, 0x0, sum = 4
4171 20:00:11.076691 best_step = 8
4172 20:00:11.077241
4173 20:00:11.077875 ==
4174 20:00:11.079912 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 20:00:11.083341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4176 20:00:11.083910 ==
4177 20:00:11.086551 RX Vref Scan: 0
4178 20:00:11.087111
4179 20:00:11.087480 RX Vref 0 -> 0, step: 1
4180 20:00:11.087826
4181 20:00:11.089953 RX Delay -195 -> 252, step: 8
4182 20:00:11.096995 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4183 20:00:11.100538 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4184 20:00:11.104340 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4185 20:00:11.107141 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4186 20:00:11.114006 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4187 20:00:11.117035 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4188 20:00:11.120683 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4189 20:00:11.123878 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4190 20:00:11.127027 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4191 20:00:11.133597 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4192 20:00:11.136901 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4193 20:00:11.140281 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4194 20:00:11.143611 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4195 20:00:11.150083 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4196 20:00:11.153403 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4197 20:00:11.157018 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4198 20:00:11.157484 ==
4199 20:00:11.160008 Dram Type= 6, Freq= 0, CH_0, rank 1
4200 20:00:11.163678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4201 20:00:11.166891 ==
4202 20:00:11.167495 DQS Delay:
4203 20:00:11.167867 DQS0 = 0, DQS1 = 0
4204 20:00:11.170427 DQM Delay:
4205 20:00:11.170985 DQM0 = 41, DQM1 = 32
4206 20:00:11.173417 DQ Delay:
4207 20:00:11.176772 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4208 20:00:11.177236 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4209 20:00:11.180284 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4210 20:00:11.183370 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4211 20:00:11.186564
4212 20:00:11.187026
4213 20:00:11.193176 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d6d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4214 20:00:11.196533 CH0 RK1: MR19=808, MR18=6D6D
4215 20:00:11.203288 CH0_RK1: MR19=0x808, MR18=0x6D6D, DQSOSC=389, MR23=63, INC=173, DEC=115
4216 20:00:11.206502 [RxdqsGatingPostProcess] freq 600
4217 20:00:11.209682 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4218 20:00:11.213390 Pre-setting of DQS Precalculation
4219 20:00:11.220044 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4220 20:00:11.220653 ==
4221 20:00:11.223367 Dram Type= 6, Freq= 0, CH_1, rank 0
4222 20:00:11.226821 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4223 20:00:11.227393 ==
4224 20:00:11.233040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4225 20:00:11.235974 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4226 20:00:11.240791 [CA 0] Center 35 (5~66) winsize 62
4227 20:00:11.244268 [CA 1] Center 35 (5~66) winsize 62
4228 20:00:11.247840 [CA 2] Center 33 (3~64) winsize 62
4229 20:00:11.250495 [CA 3] Center 33 (3~64) winsize 62
4230 20:00:11.253784 [CA 4] Center 33 (2~64) winsize 63
4231 20:00:11.257268 [CA 5] Center 33 (2~64) winsize 63
4232 20:00:11.257821
4233 20:00:11.260566 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4234 20:00:11.261032
4235 20:00:11.263785 [CATrainingPosCal] consider 1 rank data
4236 20:00:11.267145 u2DelayCellTimex100 = 270/100 ps
4237 20:00:11.270765 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4238 20:00:11.276972 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4239 20:00:11.280208 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4240 20:00:11.283586 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4241 20:00:11.286927 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4242 20:00:11.290302 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4243 20:00:11.290876
4244 20:00:11.293411 CA PerBit enable=1, Macro0, CA PI delay=33
4245 20:00:11.293874
4246 20:00:11.296660 [CBTSetCACLKResult] CA Dly = 33
4247 20:00:11.300100 CS Dly: 3 (0~34)
4248 20:00:11.300599 ==
4249 20:00:11.303549 Dram Type= 6, Freq= 0, CH_1, rank 1
4250 20:00:11.306615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4251 20:00:11.307084 ==
4252 20:00:11.313445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4253 20:00:11.316784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4254 20:00:11.320706 [CA 0] Center 35 (5~66) winsize 62
4255 20:00:11.324158 [CA 1] Center 34 (4~65) winsize 62
4256 20:00:11.327576 [CA 2] Center 33 (3~64) winsize 62
4257 20:00:11.330760 [CA 3] Center 33 (3~64) winsize 62
4258 20:00:11.333903 [CA 4] Center 32 (2~63) winsize 62
4259 20:00:11.337142 [CA 5] Center 32 (2~63) winsize 62
4260 20:00:11.337606
4261 20:00:11.340916 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4262 20:00:11.341479
4263 20:00:11.343873 [CATrainingPosCal] consider 2 rank data
4264 20:00:11.347444 u2DelayCellTimex100 = 270/100 ps
4265 20:00:11.350391 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4266 20:00:11.357254 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4267 20:00:11.360618 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4268 20:00:11.363733 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4269 20:00:11.367282 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4270 20:00:11.370496 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4271 20:00:11.371056
4272 20:00:11.373523 CA PerBit enable=1, Macro0, CA PI delay=32
4273 20:00:11.373985
4274 20:00:11.377107 [CBTSetCACLKResult] CA Dly = 32
4275 20:00:11.377680 CS Dly: 4 (0~36)
4276 20:00:11.380289
4277 20:00:11.383821 ----->DramcWriteLeveling(PI) begin...
4278 20:00:11.384345 ==
4279 20:00:11.387163 Dram Type= 6, Freq= 0, CH_1, rank 0
4280 20:00:11.390314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4281 20:00:11.390876 ==
4282 20:00:11.393895 Write leveling (Byte 0): 27 => 27
4283 20:00:11.396832 Write leveling (Byte 1): 27 => 27
4284 20:00:11.400324 DramcWriteLeveling(PI) end<-----
4285 20:00:11.400881
4286 20:00:11.401250 ==
4287 20:00:11.403712 Dram Type= 6, Freq= 0, CH_1, rank 0
4288 20:00:11.407135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4289 20:00:11.407694 ==
4290 20:00:11.410258 [Gating] SW mode calibration
4291 20:00:11.416688 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4292 20:00:11.424118 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4293 20:00:11.427235 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4294 20:00:11.430055 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4295 20:00:11.436827 0 5 8 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (1 0)
4296 20:00:11.439926 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4297 20:00:11.443508 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4298 20:00:11.450029 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4299 20:00:11.453430 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4300 20:00:11.456851 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4301 20:00:11.463166 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4302 20:00:11.466498 0 6 4 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
4303 20:00:11.470113 0 6 8 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
4304 20:00:11.473223 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 20:00:11.480059 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4306 20:00:11.483167 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4307 20:00:11.486500 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4308 20:00:11.493120 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4309 20:00:11.496722 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4310 20:00:11.499851 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4311 20:00:11.506432 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4312 20:00:11.509428 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 20:00:11.512684 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 20:00:11.519434 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 20:00:11.522572 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 20:00:11.526528 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 20:00:11.532834 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 20:00:11.536051 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 20:00:11.539235 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 20:00:11.545806 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 20:00:11.548907 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 20:00:11.552785 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 20:00:11.559528 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4324 20:00:11.562265 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4325 20:00:11.565832 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4326 20:00:11.572746 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4327 20:00:11.576010 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4328 20:00:11.579091 Total UI for P1: 0, mck2ui 16
4329 20:00:11.582237 best dqsien dly found for B0: ( 0, 9, 4)
4330 20:00:11.585641 Total UI for P1: 0, mck2ui 16
4331 20:00:11.589163 best dqsien dly found for B1: ( 0, 9, 6)
4332 20:00:11.592447 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4333 20:00:11.595924 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4334 20:00:11.596572
4335 20:00:11.598932 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4336 20:00:11.602363 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4337 20:00:11.605641 [Gating] SW calibration Done
4338 20:00:11.606198 ==
4339 20:00:11.608805 Dram Type= 6, Freq= 0, CH_1, rank 0
4340 20:00:11.612238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4341 20:00:11.615357 ==
4342 20:00:11.615914 RX Vref Scan: 0
4343 20:00:11.616348
4344 20:00:11.618734 RX Vref 0 -> 0, step: 1
4345 20:00:11.619225
4346 20:00:11.622225 RX Delay -230 -> 252, step: 16
4347 20:00:11.625656 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4348 20:00:11.628742 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4349 20:00:11.632036 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4350 20:00:11.638682 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4351 20:00:11.641954 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4352 20:00:11.645272 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4353 20:00:11.648473 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4354 20:00:11.651769 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4355 20:00:11.658601 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4356 20:00:11.661623 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4357 20:00:11.665055 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4358 20:00:11.668628 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4359 20:00:11.674659 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4360 20:00:11.677990 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4361 20:00:11.681392 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4362 20:00:11.684762 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4363 20:00:11.688063 ==
4364 20:00:11.691189 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 20:00:11.694637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4366 20:00:11.695108 ==
4367 20:00:11.695468 DQS Delay:
4368 20:00:11.698304 DQS0 = 0, DQS1 = 0
4369 20:00:11.698853 DQM Delay:
4370 20:00:11.701561 DQM0 = 39, DQM1 = 32
4371 20:00:11.702107 DQ Delay:
4372 20:00:11.704732 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4373 20:00:11.707992 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4374 20:00:11.711101 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4375 20:00:11.714551 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4376 20:00:11.715104
4377 20:00:11.715465
4378 20:00:11.715796 ==
4379 20:00:11.717903 Dram Type= 6, Freq= 0, CH_1, rank 0
4380 20:00:11.721186 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4381 20:00:11.721683 ==
4382 20:00:11.722054
4383 20:00:11.722389
4384 20:00:11.724741 TX Vref Scan disable
4385 20:00:11.728041 == TX Byte 0 ==
4386 20:00:11.731090 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4387 20:00:11.734293 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4388 20:00:11.737730 == TX Byte 1 ==
4389 20:00:11.741171 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4390 20:00:11.744381 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4391 20:00:11.744924 ==
4392 20:00:11.748092 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 20:00:11.754324 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4394 20:00:11.754876 ==
4395 20:00:11.755237
4396 20:00:11.755572
4397 20:00:11.755893 TX Vref Scan disable
4398 20:00:11.758314 == TX Byte 0 ==
4399 20:00:11.761725 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4400 20:00:11.764851 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4401 20:00:11.768784 == TX Byte 1 ==
4402 20:00:11.772143 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4403 20:00:11.778365 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4404 20:00:11.778914
4405 20:00:11.779275 [DATLAT]
4406 20:00:11.779729 Freq=600, CH1 RK0
4407 20:00:11.780321
4408 20:00:11.781659 DATLAT Default: 0x9
4409 20:00:11.782343 0, 0xFFFF, sum = 0
4410 20:00:11.784749 1, 0xFFFF, sum = 0
4411 20:00:11.785212 2, 0xFFFF, sum = 0
4412 20:00:11.788450 3, 0xFFFF, sum = 0
4413 20:00:11.791756 4, 0xFFFF, sum = 0
4414 20:00:11.792368 5, 0xFFFF, sum = 0
4415 20:00:11.795211 6, 0xFFFF, sum = 0
4416 20:00:11.795769 7, 0x0, sum = 1
4417 20:00:11.796138 8, 0x0, sum = 2
4418 20:00:11.798516 9, 0x0, sum = 3
4419 20:00:11.799075 10, 0x0, sum = 4
4420 20:00:11.801889 best_step = 8
4421 20:00:11.802439
4422 20:00:11.802800 ==
4423 20:00:11.804883 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 20:00:11.808319 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4425 20:00:11.808881 ==
4426 20:00:11.811690 RX Vref Scan: 1
4427 20:00:11.812282
4428 20:00:11.812650 RX Vref 0 -> 0, step: 1
4429 20:00:11.812988
4430 20:00:11.814873 RX Delay -195 -> 252, step: 8
4431 20:00:11.815422
4432 20:00:11.818091 Set Vref, RX VrefLevel [Byte0]: 57
4433 20:00:11.821213 [Byte1]: 48
4434 20:00:11.825396
4435 20:00:11.825946 Final RX Vref Byte 0 = 57 to rank0
4436 20:00:11.829122 Final RX Vref Byte 1 = 48 to rank0
4437 20:00:11.832328 Final RX Vref Byte 0 = 57 to rank1
4438 20:00:11.835614 Final RX Vref Byte 1 = 48 to rank1==
4439 20:00:11.838743 Dram Type= 6, Freq= 0, CH_1, rank 0
4440 20:00:11.842268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4441 20:00:11.845417 ==
4442 20:00:11.845964 DQS Delay:
4443 20:00:11.846327 DQS0 = 0, DQS1 = 0
4444 20:00:11.848899 DQM Delay:
4445 20:00:11.849448 DQM0 = 38, DQM1 = 31
4446 20:00:11.852331 DQ Delay:
4447 20:00:11.855902 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4448 20:00:11.856517 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4449 20:00:11.859068 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4450 20:00:11.865469 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4451 20:00:11.866025
4452 20:00:11.866386
4453 20:00:11.872069 [DQSOSCAuto] RK0, (LSB)MR18= 0x7a7a, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4454 20:00:11.875318 CH1 RK0: MR19=808, MR18=7A7A
4455 20:00:11.881956 CH1_RK0: MR19=0x808, MR18=0x7A7A, DQSOSC=387, MR23=63, INC=175, DEC=116
4456 20:00:11.882567
4457 20:00:11.885393 ----->DramcWriteLeveling(PI) begin...
4458 20:00:11.885864 ==
4459 20:00:11.888818 Dram Type= 6, Freq= 0, CH_1, rank 1
4460 20:00:11.892320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4461 20:00:11.892901 ==
4462 20:00:11.895652 Write leveling (Byte 0): 29 => 29
4463 20:00:11.898697 Write leveling (Byte 1): 29 => 29
4464 20:00:11.901888 DramcWriteLeveling(PI) end<-----
4465 20:00:11.902346
4466 20:00:11.902706 ==
4467 20:00:11.905725 Dram Type= 6, Freq= 0, CH_1, rank 1
4468 20:00:11.908960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4469 20:00:11.909515 ==
4470 20:00:11.911808 [Gating] SW mode calibration
4471 20:00:11.918749 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4472 20:00:11.925027 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4473 20:00:11.928448 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 20:00:11.934797 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4475 20:00:11.938175 0 5 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4476 20:00:11.941658 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 20:00:11.944891 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 20:00:11.951707 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 20:00:11.955330 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 20:00:11.958008 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 20:00:11.964694 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 20:00:11.968318 0 6 4 | B1->B0 | 2424 3333 | 1 0 | (0 0) (0 0)
4483 20:00:11.971379 0 6 8 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
4484 20:00:11.978337 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 20:00:11.981239 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 20:00:11.984676 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 20:00:11.991436 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 20:00:11.994625 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 20:00:11.997845 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 20:00:12.004738 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4491 20:00:12.007771 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 20:00:12.011421 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 20:00:12.018260 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 20:00:12.021008 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 20:00:12.024557 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 20:00:12.031209 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 20:00:12.034624 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 20:00:12.037495 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 20:00:12.044953 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 20:00:12.047673 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 20:00:12.051216 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 20:00:12.057556 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 20:00:12.061026 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 20:00:12.064527 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 20:00:12.070953 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 20:00:12.074199 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 20:00:12.077645 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 20:00:12.081118 Total UI for P1: 0, mck2ui 16
4509 20:00:12.084149 best dqsien dly found for B0: ( 0, 9, 6)
4510 20:00:12.087891 Total UI for P1: 0, mck2ui 16
4511 20:00:12.090912 best dqsien dly found for B1: ( 0, 9, 6)
4512 20:00:12.094292 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4513 20:00:12.097492 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4514 20:00:12.097953
4515 20:00:12.101071 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4516 20:00:12.107609 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4517 20:00:12.108168 [Gating] SW calibration Done
4518 20:00:12.108598 ==
4519 20:00:12.110790 Dram Type= 6, Freq= 0, CH_1, rank 1
4520 20:00:12.117497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4521 20:00:12.118074 ==
4522 20:00:12.118446 RX Vref Scan: 0
4523 20:00:12.118789
4524 20:00:12.120909 RX Vref 0 -> 0, step: 1
4525 20:00:12.121370
4526 20:00:12.124279 RX Delay -230 -> 252, step: 16
4527 20:00:12.127449 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4528 20:00:12.130482 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4529 20:00:12.134513 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4530 20:00:12.140556 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4531 20:00:12.143951 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4532 20:00:12.147397 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4533 20:00:12.150576 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4534 20:00:12.157060 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4535 20:00:12.160405 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4536 20:00:12.163638 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4537 20:00:12.167778 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4538 20:00:12.173376 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4539 20:00:12.176838 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4540 20:00:12.180151 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4541 20:00:12.183561 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4542 20:00:12.190148 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4543 20:00:12.190706 ==
4544 20:00:12.193812 Dram Type= 6, Freq= 0, CH_1, rank 1
4545 20:00:12.196677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4546 20:00:12.197144 ==
4547 20:00:12.197512 DQS Delay:
4548 20:00:12.200005 DQS0 = 0, DQS1 = 0
4549 20:00:12.200649 DQM Delay:
4550 20:00:12.203468 DQM0 = 40, DQM1 = 33
4551 20:00:12.204022 DQ Delay:
4552 20:00:12.206721 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4553 20:00:12.210192 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4554 20:00:12.213099 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4555 20:00:12.216695 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4556 20:00:12.217256
4557 20:00:12.217623
4558 20:00:12.217967 ==
4559 20:00:12.219994 Dram Type= 6, Freq= 0, CH_1, rank 1
4560 20:00:12.223292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4561 20:00:12.223852 ==
4562 20:00:12.224296
4563 20:00:12.226582
4564 20:00:12.227135 TX Vref Scan disable
4565 20:00:12.229589 == TX Byte 0 ==
4566 20:00:12.232902 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4567 20:00:12.236196 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4568 20:00:12.239465 == TX Byte 1 ==
4569 20:00:12.242968 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4570 20:00:12.246370 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4571 20:00:12.249893 ==
4572 20:00:12.250492 Dram Type= 6, Freq= 0, CH_1, rank 1
4573 20:00:12.256264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4574 20:00:12.256828 ==
4575 20:00:12.257204
4576 20:00:12.257551
4577 20:00:12.259595 TX Vref Scan disable
4578 20:00:12.260061 == TX Byte 0 ==
4579 20:00:12.266014 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4580 20:00:12.269396 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4581 20:00:12.269954 == TX Byte 1 ==
4582 20:00:12.275922 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4583 20:00:12.279261 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4584 20:00:12.279839
4585 20:00:12.280265 [DATLAT]
4586 20:00:12.282371 Freq=600, CH1 RK1
4587 20:00:12.282833
4588 20:00:12.283203 DATLAT Default: 0x8
4589 20:00:12.285948 0, 0xFFFF, sum = 0
4590 20:00:12.286418 1, 0xFFFF, sum = 0
4591 20:00:12.289432 2, 0xFFFF, sum = 0
4592 20:00:12.289994 3, 0xFFFF, sum = 0
4593 20:00:12.292240 4, 0xFFFF, sum = 0
4594 20:00:12.295916 5, 0xFFFF, sum = 0
4595 20:00:12.296529 6, 0xFFFF, sum = 0
4596 20:00:12.296911 7, 0x0, sum = 1
4597 20:00:12.298935 8, 0x0, sum = 2
4598 20:00:12.299406 9, 0x0, sum = 3
4599 20:00:12.302430 10, 0x0, sum = 4
4600 20:00:12.303000 best_step = 8
4601 20:00:12.303371
4602 20:00:12.303714 ==
4603 20:00:12.306053 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 20:00:12.312488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4605 20:00:12.313049 ==
4606 20:00:12.313425 RX Vref Scan: 0
4607 20:00:12.313770
4608 20:00:12.315508 RX Vref 0 -> 0, step: 1
4609 20:00:12.315969
4610 20:00:12.319192 RX Delay -195 -> 252, step: 8
4611 20:00:12.322595 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4612 20:00:12.328970 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4613 20:00:12.332675 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4614 20:00:12.335389 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4615 20:00:12.338805 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4616 20:00:12.342685 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4617 20:00:12.348856 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4618 20:00:12.352375 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4619 20:00:12.355688 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4620 20:00:12.358659 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4621 20:00:12.365288 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4622 20:00:12.368668 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4623 20:00:12.371987 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4624 20:00:12.375150 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4625 20:00:12.382038 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4626 20:00:12.385320 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4627 20:00:12.386010 ==
4628 20:00:12.388896 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 20:00:12.391815 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4630 20:00:12.392319 ==
4631 20:00:12.395269 DQS Delay:
4632 20:00:12.395731 DQS0 = 0, DQS1 = 0
4633 20:00:12.396094 DQM Delay:
4634 20:00:12.398679 DQM0 = 36, DQM1 = 29
4635 20:00:12.399140 DQ Delay:
4636 20:00:12.401865 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4637 20:00:12.405017 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4638 20:00:12.408614 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4639 20:00:12.411936 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4640 20:00:12.412548
4641 20:00:12.412923
4642 20:00:12.422057 [DQSOSCAuto] RK1, (LSB)MR18= 0x5858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4643 20:00:12.425123 CH1 RK1: MR19=808, MR18=5858
4644 20:00:12.428311 CH1_RK1: MR19=0x808, MR18=0x5858, DQSOSC=393, MR23=63, INC=169, DEC=113
4645 20:00:12.431979 [RxdqsGatingPostProcess] freq 600
4646 20:00:12.438341 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4647 20:00:12.441628 Pre-setting of DQS Precalculation
4648 20:00:12.445007 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4649 20:00:12.455289 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4650 20:00:12.461314 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4651 20:00:12.461889
4652 20:00:12.462260
4653 20:00:12.464298 [Calibration Summary] 1200 Mbps
4654 20:00:12.464791 CH 0, Rank 0
4655 20:00:12.467815 SW Impedance : PASS
4656 20:00:12.468426 DUTY Scan : NO K
4657 20:00:12.471534 ZQ Calibration : PASS
4658 20:00:12.474784 Jitter Meter : NO K
4659 20:00:12.475353 CBT Training : PASS
4660 20:00:12.477934 Write leveling : PASS
4661 20:00:12.481191 RX DQS gating : PASS
4662 20:00:12.481763 RX DQ/DQS(RDDQC) : PASS
4663 20:00:12.484324 TX DQ/DQS : PASS
4664 20:00:12.487769 RX DATLAT : PASS
4665 20:00:12.488278 RX DQ/DQS(Engine): PASS
4666 20:00:12.491289 TX OE : NO K
4667 20:00:12.491855 All Pass.
4668 20:00:12.492293
4669 20:00:12.494390 CH 0, Rank 1
4670 20:00:12.494958 SW Impedance : PASS
4671 20:00:12.497515 DUTY Scan : NO K
4672 20:00:12.500677 ZQ Calibration : PASS
4673 20:00:12.501142 Jitter Meter : NO K
4674 20:00:12.504343 CBT Training : PASS
4675 20:00:12.507725 Write leveling : PASS
4676 20:00:12.508358 RX DQS gating : PASS
4677 20:00:12.510678 RX DQ/DQS(RDDQC) : PASS
4678 20:00:12.511241 TX DQ/DQS : PASS
4679 20:00:12.514294 RX DATLAT : PASS
4680 20:00:12.517197 RX DQ/DQS(Engine): PASS
4681 20:00:12.517669 TX OE : NO K
4682 20:00:12.520797 All Pass.
4683 20:00:12.521255
4684 20:00:12.521623 CH 1, Rank 0
4685 20:00:12.523827 SW Impedance : PASS
4686 20:00:12.524328 DUTY Scan : NO K
4687 20:00:12.527338 ZQ Calibration : PASS
4688 20:00:12.530414 Jitter Meter : NO K
4689 20:00:12.530980 CBT Training : PASS
4690 20:00:12.533853 Write leveling : PASS
4691 20:00:12.536786 RX DQS gating : PASS
4692 20:00:12.537250 RX DQ/DQS(RDDQC) : PASS
4693 20:00:12.540353 TX DQ/DQS : PASS
4694 20:00:12.543817 RX DATLAT : PASS
4695 20:00:12.544433 RX DQ/DQS(Engine): PASS
4696 20:00:12.547060 TX OE : NO K
4697 20:00:12.547631 All Pass.
4698 20:00:12.548003
4699 20:00:12.550293 CH 1, Rank 1
4700 20:00:12.550855 SW Impedance : PASS
4701 20:00:12.553524 DUTY Scan : NO K
4702 20:00:12.556698 ZQ Calibration : PASS
4703 20:00:12.557160 Jitter Meter : NO K
4704 20:00:12.559823 CBT Training : PASS
4705 20:00:12.563258 Write leveling : PASS
4706 20:00:12.563822 RX DQS gating : PASS
4707 20:00:12.566619 RX DQ/DQS(RDDQC) : PASS
4708 20:00:12.570339 TX DQ/DQS : PASS
4709 20:00:12.570909 RX DATLAT : PASS
4710 20:00:12.573357 RX DQ/DQS(Engine): PASS
4711 20:00:12.576832 TX OE : NO K
4712 20:00:12.577300 All Pass.
4713 20:00:12.577668
4714 20:00:12.578006 DramC Write-DBI off
4715 20:00:12.580078 PER_BANK_REFRESH: Hybrid Mode
4716 20:00:12.583499 TX_TRACKING: ON
4717 20:00:12.590110 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4718 20:00:12.593352 [FAST_K] Save calibration result to emmc
4719 20:00:12.599854 dramc_set_vcore_voltage set vcore to 662500
4720 20:00:12.600467 Read voltage for 933, 3
4721 20:00:12.603007 Vio18 = 0
4722 20:00:12.603576 Vcore = 662500
4723 20:00:12.603947 Vdram = 0
4724 20:00:12.604342 Vddq = 0
4725 20:00:12.606376 Vmddr = 0
4726 20:00:12.609550 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4727 20:00:12.616626 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4728 20:00:12.619663 MEM_TYPE=3, freq_sel=17
4729 20:00:12.623143 sv_algorithm_assistance_LP4_1600
4730 20:00:12.626246 ============ PULL DRAM RESETB DOWN ============
4731 20:00:12.629566 ========== PULL DRAM RESETB DOWN end =========
4732 20:00:12.632684 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4733 20:00:12.636328 ===================================
4734 20:00:12.639401 LPDDR4 DRAM CONFIGURATION
4735 20:00:12.642565 ===================================
4736 20:00:12.646157 EX_ROW_EN[0] = 0x0
4737 20:00:12.646712 EX_ROW_EN[1] = 0x0
4738 20:00:12.649480 LP4Y_EN = 0x0
4739 20:00:12.650033 WORK_FSP = 0x0
4740 20:00:12.652896 WL = 0x3
4741 20:00:12.653449 RL = 0x3
4742 20:00:12.656101 BL = 0x2
4743 20:00:12.656697 RPST = 0x0
4744 20:00:12.658979 RD_PRE = 0x0
4745 20:00:12.662706 WR_PRE = 0x1
4746 20:00:12.663259 WR_PST = 0x0
4747 20:00:12.665750 DBI_WR = 0x0
4748 20:00:12.666211 DBI_RD = 0x0
4749 20:00:12.668965 OTF = 0x1
4750 20:00:12.672545 ===================================
4751 20:00:12.675844 ===================================
4752 20:00:12.676451 ANA top config
4753 20:00:12.679458 ===================================
4754 20:00:12.682435 DLL_ASYNC_EN = 0
4755 20:00:12.685431 ALL_SLAVE_EN = 1
4756 20:00:12.685896 NEW_RANK_MODE = 1
4757 20:00:12.688847 DLL_IDLE_MODE = 1
4758 20:00:12.692162 LP45_APHY_COMB_EN = 1
4759 20:00:12.695496 TX_ODT_DIS = 1
4760 20:00:12.695960 NEW_8X_MODE = 1
4761 20:00:12.699137 ===================================
4762 20:00:12.702424 ===================================
4763 20:00:12.705681 data_rate = 1866
4764 20:00:12.708854 CKR = 1
4765 20:00:12.711961 DQ_P2S_RATIO = 8
4766 20:00:12.715697 ===================================
4767 20:00:12.719230 CA_P2S_RATIO = 8
4768 20:00:12.722417 DQ_CA_OPEN = 0
4769 20:00:12.725411 DQ_SEMI_OPEN = 0
4770 20:00:12.725965 CA_SEMI_OPEN = 0
4771 20:00:12.728741 CA_FULL_RATE = 0
4772 20:00:12.732105 DQ_CKDIV4_EN = 1
4773 20:00:12.735348 CA_CKDIV4_EN = 1
4774 20:00:12.738458 CA_PREDIV_EN = 0
4775 20:00:12.741578 PH8_DLY = 0
4776 20:00:12.742042 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4777 20:00:12.745195 DQ_AAMCK_DIV = 4
4778 20:00:12.748292 CA_AAMCK_DIV = 4
4779 20:00:12.751793 CA_ADMCK_DIV = 4
4780 20:00:12.755232 DQ_TRACK_CA_EN = 0
4781 20:00:12.758266 CA_PICK = 933
4782 20:00:12.761452 CA_MCKIO = 933
4783 20:00:12.761913 MCKIO_SEMI = 0
4784 20:00:12.764797 PLL_FREQ = 3732
4785 20:00:12.768539 DQ_UI_PI_RATIO = 32
4786 20:00:12.771531 CA_UI_PI_RATIO = 0
4787 20:00:12.775085 ===================================
4788 20:00:12.778162 ===================================
4789 20:00:12.781598 memory_type:LPDDR4
4790 20:00:12.782153 GP_NUM : 10
4791 20:00:12.784970 SRAM_EN : 1
4792 20:00:12.788259 MD32_EN : 0
4793 20:00:12.791360 ===================================
4794 20:00:12.791916 [ANA_INIT] >>>>>>>>>>>>>>
4795 20:00:12.794873 <<<<<< [CONFIGURE PHASE]: ANA_TX
4796 20:00:12.797950 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4797 20:00:12.801016 ===================================
4798 20:00:12.804625 data_rate = 1866,PCW = 0X8f00
4799 20:00:12.808060 ===================================
4800 20:00:12.811486 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4801 20:00:12.818224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4802 20:00:12.821105 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4803 20:00:12.828054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4804 20:00:12.831135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4805 20:00:12.834094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4806 20:00:12.834562 [ANA_INIT] flow start
4807 20:00:12.837608 [ANA_INIT] PLL >>>>>>>>
4808 20:00:12.840926 [ANA_INIT] PLL <<<<<<<<
4809 20:00:12.844170 [ANA_INIT] MIDPI >>>>>>>>
4810 20:00:12.844791 [ANA_INIT] MIDPI <<<<<<<<
4811 20:00:12.847836 [ANA_INIT] DLL >>>>>>>>
4812 20:00:12.850780 [ANA_INIT] flow end
4813 20:00:12.854314 ============ LP4 DIFF to SE enter ============
4814 20:00:12.857448 ============ LP4 DIFF to SE exit ============
4815 20:00:12.860672 [ANA_INIT] <<<<<<<<<<<<<
4816 20:00:12.864148 [Flow] Enable top DCM control >>>>>
4817 20:00:12.867330 [Flow] Enable top DCM control <<<<<
4818 20:00:12.870770 Enable DLL master slave shuffle
4819 20:00:12.874401 ==============================================================
4820 20:00:12.877197 Gating Mode config
4821 20:00:12.880513 ==============================================================
4822 20:00:12.883954 Config description:
4823 20:00:12.893746 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4824 20:00:12.900533 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4825 20:00:12.903991 SELPH_MODE 0: By rank 1: By Phase
4826 20:00:12.910187 ==============================================================
4827 20:00:12.913778 GAT_TRACK_EN = 1
4828 20:00:12.916979 RX_GATING_MODE = 2
4829 20:00:12.920419 RX_GATING_TRACK_MODE = 2
4830 20:00:12.923824 SELPH_MODE = 1
4831 20:00:12.927195 PICG_EARLY_EN = 1
4832 20:00:12.930204 VALID_LAT_VALUE = 1
4833 20:00:12.934180 ==============================================================
4834 20:00:12.936866 Enter into Gating configuration >>>>
4835 20:00:12.940165 Exit from Gating configuration <<<<
4836 20:00:12.943504 Enter into DVFS_PRE_config >>>>>
4837 20:00:12.953363 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4838 20:00:12.956922 Exit from DVFS_PRE_config <<<<<
4839 20:00:12.960117 Enter into PICG configuration >>>>
4840 20:00:12.963311 Exit from PICG configuration <<<<
4841 20:00:12.966776 [RX_INPUT] configuration >>>>>
4842 20:00:12.969913 [RX_INPUT] configuration <<<<<
4843 20:00:12.976828 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4844 20:00:12.979802 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4845 20:00:12.986940 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4846 20:00:12.993267 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4847 20:00:12.999669 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4848 20:00:13.006399 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4849 20:00:13.009780 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4850 20:00:13.012829 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4851 20:00:13.016126 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4852 20:00:13.022658 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4853 20:00:13.026157 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4854 20:00:13.029138 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 20:00:13.032553 ===================================
4856 20:00:13.036148 LPDDR4 DRAM CONFIGURATION
4857 20:00:13.039122 ===================================
4858 20:00:13.042259 EX_ROW_EN[0] = 0x0
4859 20:00:13.042900 EX_ROW_EN[1] = 0x0
4860 20:00:13.045703 LP4Y_EN = 0x0
4861 20:00:13.046294 WORK_FSP = 0x0
4862 20:00:13.048945 WL = 0x3
4863 20:00:13.049400 RL = 0x3
4864 20:00:13.052587 BL = 0x2
4865 20:00:13.053191 RPST = 0x0
4866 20:00:13.055883 RD_PRE = 0x0
4867 20:00:13.056521 WR_PRE = 0x1
4868 20:00:13.058894 WR_PST = 0x0
4869 20:00:13.059351 DBI_WR = 0x0
4870 20:00:13.062458 DBI_RD = 0x0
4871 20:00:13.063046 OTF = 0x1
4872 20:00:13.065692 ===================================
4873 20:00:13.072248 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4874 20:00:13.075964 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4875 20:00:13.078979 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4876 20:00:13.082297 ===================================
4877 20:00:13.085262 LPDDR4 DRAM CONFIGURATION
4878 20:00:13.088385 ===================================
4879 20:00:13.091839 EX_ROW_EN[0] = 0x10
4880 20:00:13.092471 EX_ROW_EN[1] = 0x0
4881 20:00:13.095532 LP4Y_EN = 0x0
4882 20:00:13.096091 WORK_FSP = 0x0
4883 20:00:13.098575 WL = 0x3
4884 20:00:13.099141 RL = 0x3
4885 20:00:13.101744 BL = 0x2
4886 20:00:13.102203 RPST = 0x0
4887 20:00:13.104870 RD_PRE = 0x0
4888 20:00:13.105327 WR_PRE = 0x1
4889 20:00:13.108303 WR_PST = 0x0
4890 20:00:13.108764 DBI_WR = 0x0
4891 20:00:13.111696 DBI_RD = 0x0
4892 20:00:13.112309 OTF = 0x1
4893 20:00:13.114812 ===================================
4894 20:00:13.121408 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4895 20:00:13.126493 nWR fixed to 30
4896 20:00:13.129804 [ModeRegInit_LP4] CH0 RK0
4897 20:00:13.130360 [ModeRegInit_LP4] CH0 RK1
4898 20:00:13.133158 [ModeRegInit_LP4] CH1 RK0
4899 20:00:13.136117 [ModeRegInit_LP4] CH1 RK1
4900 20:00:13.136644 match AC timing 8
4901 20:00:13.142938 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4902 20:00:13.146822 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4903 20:00:13.149624 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4904 20:00:13.156330 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4905 20:00:13.159466 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4906 20:00:13.159967 ==
4907 20:00:13.162861 Dram Type= 6, Freq= 0, CH_0, rank 0
4908 20:00:13.166148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4909 20:00:13.166706 ==
4910 20:00:13.172755 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4911 20:00:13.179541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4912 20:00:13.183178 [CA 0] Center 38 (8~69) winsize 62
4913 20:00:13.186040 [CA 1] Center 38 (8~69) winsize 62
4914 20:00:13.189240 [CA 2] Center 36 (6~67) winsize 62
4915 20:00:13.192469 [CA 3] Center 35 (5~66) winsize 62
4916 20:00:13.196033 [CA 4] Center 34 (4~65) winsize 62
4917 20:00:13.199265 [CA 5] Center 34 (4~65) winsize 62
4918 20:00:13.199729
4919 20:00:13.202720 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4920 20:00:13.203283
4921 20:00:13.205857 [CATrainingPosCal] consider 1 rank data
4922 20:00:13.209536 u2DelayCellTimex100 = 270/100 ps
4923 20:00:13.212642 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4924 20:00:13.215936 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4925 20:00:13.219669 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4926 20:00:13.222699 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4927 20:00:13.226110 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4928 20:00:13.232703 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4929 20:00:13.233262
4930 20:00:13.236087 CA PerBit enable=1, Macro0, CA PI delay=34
4931 20:00:13.236741
4932 20:00:13.239193 [CBTSetCACLKResult] CA Dly = 34
4933 20:00:13.239651 CS Dly: 7 (0~38)
4934 20:00:13.240023 ==
4935 20:00:13.242401 Dram Type= 6, Freq= 0, CH_0, rank 1
4936 20:00:13.245979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4937 20:00:13.249165 ==
4938 20:00:13.252509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4939 20:00:13.259252 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4940 20:00:13.262744 [CA 0] Center 38 (8~69) winsize 62
4941 20:00:13.265450 [CA 1] Center 38 (8~69) winsize 62
4942 20:00:13.269261 [CA 2] Center 36 (6~67) winsize 62
4943 20:00:13.272333 [CA 3] Center 35 (5~66) winsize 62
4944 20:00:13.275587 [CA 4] Center 34 (3~65) winsize 63
4945 20:00:13.278978 [CA 5] Center 34 (4~65) winsize 62
4946 20:00:13.279534
4947 20:00:13.282392 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4948 20:00:13.282959
4949 20:00:13.285442 [CATrainingPosCal] consider 2 rank data
4950 20:00:13.288681 u2DelayCellTimex100 = 270/100 ps
4951 20:00:13.291935 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4952 20:00:13.295582 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4953 20:00:13.299013 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4954 20:00:13.304975 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4955 20:00:13.308424 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4956 20:00:13.312233 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4957 20:00:13.312794
4958 20:00:13.315283 CA PerBit enable=1, Macro0, CA PI delay=34
4959 20:00:13.315840
4960 20:00:13.318588 [CBTSetCACLKResult] CA Dly = 34
4961 20:00:13.319139 CS Dly: 7 (0~39)
4962 20:00:13.319509
4963 20:00:13.321838 ----->DramcWriteLeveling(PI) begin...
4964 20:00:13.322305 ==
4965 20:00:13.325158 Dram Type= 6, Freq= 0, CH_0, rank 0
4966 20:00:13.331712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4967 20:00:13.332288 ==
4968 20:00:13.335275 Write leveling (Byte 0): 28 => 28
4969 20:00:13.338340 Write leveling (Byte 1): 27 => 27
4970 20:00:13.341638 DramcWriteLeveling(PI) end<-----
4971 20:00:13.342094
4972 20:00:13.342462 ==
4973 20:00:13.344909 Dram Type= 6, Freq= 0, CH_0, rank 0
4974 20:00:13.348480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4975 20:00:13.349038 ==
4976 20:00:13.351788 [Gating] SW mode calibration
4977 20:00:13.358460 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4978 20:00:13.361777 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4979 20:00:13.368289 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4980 20:00:13.371711 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4981 20:00:13.374865 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4982 20:00:13.382301 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4983 20:00:13.384945 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4984 20:00:13.388104 0 10 20 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (0 1)
4985 20:00:13.394860 0 10 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
4986 20:00:13.397829 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4987 20:00:13.401358 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4988 20:00:13.408253 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4989 20:00:13.411252 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4990 20:00:13.414790 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4991 20:00:13.421009 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4992 20:00:13.424355 0 11 20 | B1->B0 | 2929 3232 | 0 0 | (0 0) (0 0)
4993 20:00:13.427962 0 11 24 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
4994 20:00:13.434657 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4995 20:00:13.437943 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4996 20:00:13.440827 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4997 20:00:13.447505 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4998 20:00:13.451055 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4999 20:00:13.454657 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5000 20:00:13.460772 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5001 20:00:13.464503 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 20:00:13.467806 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 20:00:13.474095 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 20:00:13.477561 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 20:00:13.481089 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 20:00:13.487713 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 20:00:13.490963 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 20:00:13.494089 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 20:00:13.500768 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 20:00:13.504008 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 20:00:13.507545 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 20:00:13.514079 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 20:00:13.517705 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 20:00:13.520406 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5015 20:00:13.527044 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5016 20:00:13.530930 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5017 20:00:13.534358 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5018 20:00:13.537190 Total UI for P1: 0, mck2ui 16
5019 20:00:13.540429 best dqsien dly found for B0: ( 0, 14, 20)
5020 20:00:13.544332 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5021 20:00:13.547181 Total UI for P1: 0, mck2ui 16
5022 20:00:13.550887 best dqsien dly found for B1: ( 0, 14, 22)
5023 20:00:13.553875 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5024 20:00:13.560372 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5025 20:00:13.560986
5026 20:00:13.563400 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5027 20:00:13.567094 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5028 20:00:13.570018 [Gating] SW calibration Done
5029 20:00:13.570476 ==
5030 20:00:13.573512 Dram Type= 6, Freq= 0, CH_0, rank 0
5031 20:00:13.577096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5032 20:00:13.577655 ==
5033 20:00:13.580451 RX Vref Scan: 0
5034 20:00:13.581001
5035 20:00:13.581366 RX Vref 0 -> 0, step: 1
5036 20:00:13.581707
5037 20:00:13.583625 RX Delay -80 -> 252, step: 8
5038 20:00:13.587353 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5039 20:00:13.593542 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5040 20:00:13.596732 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5041 20:00:13.600085 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5042 20:00:13.603490 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5043 20:00:13.606734 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5044 20:00:13.609985 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5045 20:00:13.616758 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5046 20:00:13.620424 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5047 20:00:13.623532 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5048 20:00:13.626846 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5049 20:00:13.630384 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5050 20:00:13.633356 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5051 20:00:13.640236 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5052 20:00:13.643464 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5053 20:00:13.646841 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5054 20:00:13.647403 ==
5055 20:00:13.650010 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 20:00:13.653072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5057 20:00:13.656666 ==
5058 20:00:13.657227 DQS Delay:
5059 20:00:13.657596 DQS0 = 0, DQS1 = 0
5060 20:00:13.659886 DQM Delay:
5061 20:00:13.660499 DQM0 = 94, DQM1 = 84
5062 20:00:13.662924 DQ Delay:
5063 20:00:13.663399 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5064 20:00:13.666237 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =103
5065 20:00:13.669713 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5066 20:00:13.673073 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5067 20:00:13.676542
5068 20:00:13.677097
5069 20:00:13.677464 ==
5070 20:00:13.679659 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 20:00:13.683117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5072 20:00:13.683674 ==
5073 20:00:13.684041
5074 20:00:13.684650
5075 20:00:13.686418 TX Vref Scan disable
5076 20:00:13.686971 == TX Byte 0 ==
5077 20:00:13.692946 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5078 20:00:13.696543 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5079 20:00:13.697103 == TX Byte 1 ==
5080 20:00:13.703038 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5081 20:00:13.706501 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5082 20:00:13.707061 ==
5083 20:00:13.709252 Dram Type= 6, Freq= 0, CH_0, rank 0
5084 20:00:13.712683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5085 20:00:13.713151 ==
5086 20:00:13.713521
5087 20:00:13.713881
5088 20:00:13.716021 TX Vref Scan disable
5089 20:00:13.719436 == TX Byte 0 ==
5090 20:00:13.722542 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5091 20:00:13.726160 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5092 20:00:13.729165 == TX Byte 1 ==
5093 20:00:13.732446 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5094 20:00:13.736045 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5095 20:00:13.736651
5096 20:00:13.739156 [DATLAT]
5097 20:00:13.739619 Freq=933, CH0 RK0
5098 20:00:13.739998
5099 20:00:13.742242 DATLAT Default: 0xd
5100 20:00:13.742705 0, 0xFFFF, sum = 0
5101 20:00:13.746038 1, 0xFFFF, sum = 0
5102 20:00:13.746667 2, 0xFFFF, sum = 0
5103 20:00:13.749110 3, 0xFFFF, sum = 0
5104 20:00:13.749581 4, 0xFFFF, sum = 0
5105 20:00:13.752262 5, 0xFFFF, sum = 0
5106 20:00:13.752731 6, 0xFFFF, sum = 0
5107 20:00:13.755572 7, 0xFFFF, sum = 0
5108 20:00:13.756037 8, 0xFFFF, sum = 0
5109 20:00:13.759372 9, 0xFFFF, sum = 0
5110 20:00:13.759933 10, 0x0, sum = 1
5111 20:00:13.762125 11, 0x0, sum = 2
5112 20:00:13.762589 12, 0x0, sum = 3
5113 20:00:13.765580 13, 0x0, sum = 4
5114 20:00:13.766147 best_step = 11
5115 20:00:13.766519
5116 20:00:13.766863 ==
5117 20:00:13.768964 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 20:00:13.775892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5119 20:00:13.776559 ==
5120 20:00:13.776938 RX Vref Scan: 1
5121 20:00:13.777286
5122 20:00:13.779171 RX Vref 0 -> 0, step: 1
5123 20:00:13.779728
5124 20:00:13.782380 RX Delay -69 -> 252, step: 4
5125 20:00:13.782938
5126 20:00:13.785840 Set Vref, RX VrefLevel [Byte0]: 51
5127 20:00:13.788825 [Byte1]: 50
5128 20:00:13.789462
5129 20:00:13.792431 Final RX Vref Byte 0 = 51 to rank0
5130 20:00:13.795521 Final RX Vref Byte 1 = 50 to rank0
5131 20:00:13.799044 Final RX Vref Byte 0 = 51 to rank1
5132 20:00:13.802394 Final RX Vref Byte 1 = 50 to rank1==
5133 20:00:13.805687 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 20:00:13.808687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5135 20:00:13.809154 ==
5136 20:00:13.812329 DQS Delay:
5137 20:00:13.812879 DQS0 = 0, DQS1 = 0
5138 20:00:13.815548 DQM Delay:
5139 20:00:13.816109 DQM0 = 96, DQM1 = 86
5140 20:00:13.816591 DQ Delay:
5141 20:00:13.818759 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5142 20:00:13.821887 DQ4 =102, DQ5 =86, DQ6 =104, DQ7 =102
5143 20:00:13.825175 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5144 20:00:13.828816 DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =98
5145 20:00:13.829370
5146 20:00:13.832273
5147 20:00:13.838432 [DQSOSCAuto] RK0, (LSB)MR18= 0x2121, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5148 20:00:13.841857 CH0 RK0: MR19=505, MR18=2121
5149 20:00:13.848639 CH0_RK0: MR19=0x505, MR18=0x2121, DQSOSC=411, MR23=63, INC=64, DEC=42
5150 20:00:13.849197
5151 20:00:13.851770 ----->DramcWriteLeveling(PI) begin...
5152 20:00:13.852374 ==
5153 20:00:13.855233 Dram Type= 6, Freq= 0, CH_0, rank 1
5154 20:00:13.858500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5155 20:00:13.859145 ==
5156 20:00:13.861590 Write leveling (Byte 0): 28 => 28
5157 20:00:13.864932 Write leveling (Byte 1): 27 => 27
5158 20:00:13.868401 DramcWriteLeveling(PI) end<-----
5159 20:00:13.868869
5160 20:00:13.869242 ==
5161 20:00:13.871938 Dram Type= 6, Freq= 0, CH_0, rank 1
5162 20:00:13.874926 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5163 20:00:13.875393 ==
5164 20:00:13.878179 [Gating] SW mode calibration
5165 20:00:13.884952 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5166 20:00:13.891639 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5167 20:00:13.894707 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 20:00:13.897979 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 20:00:13.904903 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 20:00:13.908148 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 20:00:13.911396 0 10 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5172 20:00:13.917850 0 10 20 | B1->B0 | 3232 2f2f | 0 0 | (1 0) (0 1)
5173 20:00:13.921453 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
5174 20:00:13.924346 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 20:00:13.931054 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 20:00:13.934846 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 20:00:13.937831 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 20:00:13.944734 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 20:00:13.947707 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5180 20:00:13.950823 0 11 20 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 0)
5181 20:00:13.957712 0 11 24 | B1->B0 | 4140 4646 | 1 0 | (0 0) (0 0)
5182 20:00:13.960785 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 20:00:13.964214 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 20:00:13.971241 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 20:00:13.974092 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 20:00:13.977910 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 20:00:13.984262 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 20:00:13.987783 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5189 20:00:13.990803 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5190 20:00:13.997866 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 20:00:14.000594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 20:00:14.004271 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 20:00:14.010859 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 20:00:14.014454 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 20:00:14.017213 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 20:00:14.023934 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 20:00:14.027509 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 20:00:14.030639 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 20:00:14.037427 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 20:00:14.040500 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 20:00:14.044072 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 20:00:14.047604 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 20:00:14.054328 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 20:00:14.057082 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5205 20:00:14.060693 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 20:00:14.064296 Total UI for P1: 0, mck2ui 16
5207 20:00:14.067432 best dqsien dly found for B0: ( 0, 14, 20)
5208 20:00:14.070547 Total UI for P1: 0, mck2ui 16
5209 20:00:14.073896 best dqsien dly found for B1: ( 0, 14, 20)
5210 20:00:14.077462 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5211 20:00:14.084020 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5212 20:00:14.084827
5213 20:00:14.087372 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5214 20:00:14.090593 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5215 20:00:14.093778 [Gating] SW calibration Done
5216 20:00:14.094261 ==
5217 20:00:14.096953 Dram Type= 6, Freq= 0, CH_0, rank 1
5218 20:00:14.100408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5219 20:00:14.100866 ==
5220 20:00:14.101229 RX Vref Scan: 0
5221 20:00:14.103704
5222 20:00:14.104245 RX Vref 0 -> 0, step: 1
5223 20:00:14.104628
5224 20:00:14.106925 RX Delay -80 -> 252, step: 8
5225 20:00:14.110265 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5226 20:00:14.113721 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5227 20:00:14.120543 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5228 20:00:14.123581 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5229 20:00:14.127032 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5230 20:00:14.129982 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5231 20:00:14.133563 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5232 20:00:14.137103 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5233 20:00:14.143105 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5234 20:00:14.146992 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5235 20:00:14.150375 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5236 20:00:14.153578 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5237 20:00:14.156858 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5238 20:00:14.163400 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5239 20:00:14.166814 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5240 20:00:14.170362 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5241 20:00:14.170920 ==
5242 20:00:14.173592 Dram Type= 6, Freq= 0, CH_0, rank 1
5243 20:00:14.176807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5244 20:00:14.177369 ==
5245 20:00:14.179882 DQS Delay:
5246 20:00:14.180495 DQS0 = 0, DQS1 = 0
5247 20:00:14.180916 DQM Delay:
5248 20:00:14.183243 DQM0 = 96, DQM1 = 84
5249 20:00:14.183798 DQ Delay:
5250 20:00:14.186583 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87
5251 20:00:14.190084 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5252 20:00:14.193188 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5253 20:00:14.196244 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =95
5254 20:00:14.196774
5255 20:00:14.197221
5256 20:00:14.199819 ==
5257 20:00:14.202960 Dram Type= 6, Freq= 0, CH_0, rank 1
5258 20:00:14.206593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5259 20:00:14.207211 ==
5260 20:00:14.207591
5261 20:00:14.207929
5262 20:00:14.209926 TX Vref Scan disable
5263 20:00:14.210484 == TX Byte 0 ==
5264 20:00:14.213060 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5265 20:00:14.219817 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5266 20:00:14.220570 == TX Byte 1 ==
5267 20:00:14.222972 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5268 20:00:14.229395 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5269 20:00:14.229972 ==
5270 20:00:14.232686 Dram Type= 6, Freq= 0, CH_0, rank 1
5271 20:00:14.236025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5272 20:00:14.236644 ==
5273 20:00:14.237019
5274 20:00:14.237364
5275 20:00:14.239144 TX Vref Scan disable
5276 20:00:14.242668 == TX Byte 0 ==
5277 20:00:14.246126 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5278 20:00:14.249188 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5279 20:00:14.252838 == TX Byte 1 ==
5280 20:00:14.256119 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5281 20:00:14.259290 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5282 20:00:14.259846
5283 20:00:14.262485 [DATLAT]
5284 20:00:14.262947 Freq=933, CH0 RK1
5285 20:00:14.263316
5286 20:00:14.265857 DATLAT Default: 0xb
5287 20:00:14.266335 0, 0xFFFF, sum = 0
5288 20:00:14.269222 1, 0xFFFF, sum = 0
5289 20:00:14.269690 2, 0xFFFF, sum = 0
5290 20:00:14.272796 3, 0xFFFF, sum = 0
5291 20:00:14.273353 4, 0xFFFF, sum = 0
5292 20:00:14.275955 5, 0xFFFF, sum = 0
5293 20:00:14.276523 6, 0xFFFF, sum = 0
5294 20:00:14.279561 7, 0xFFFF, sum = 0
5295 20:00:14.280121 8, 0xFFFF, sum = 0
5296 20:00:14.282406 9, 0xFFFF, sum = 0
5297 20:00:14.282961 10, 0x0, sum = 1
5298 20:00:14.286108 11, 0x0, sum = 2
5299 20:00:14.286670 12, 0x0, sum = 3
5300 20:00:14.289282 13, 0x0, sum = 4
5301 20:00:14.289846 best_step = 11
5302 20:00:14.290216
5303 20:00:14.290557 ==
5304 20:00:14.292756 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 20:00:14.295861 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5306 20:00:14.299356 ==
5307 20:00:14.299907 RX Vref Scan: 0
5308 20:00:14.300338
5309 20:00:14.302697 RX Vref 0 -> 0, step: 1
5310 20:00:14.303159
5311 20:00:14.306363 RX Delay -77 -> 252, step: 4
5312 20:00:14.309327 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5313 20:00:14.312554 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5314 20:00:14.315982 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5315 20:00:14.322512 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5316 20:00:14.325968 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5317 20:00:14.329068 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5318 20:00:14.332566 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5319 20:00:14.335855 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5320 20:00:14.342447 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5321 20:00:14.345856 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5322 20:00:14.349024 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5323 20:00:14.352293 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5324 20:00:14.355487 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5325 20:00:14.358665 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5326 20:00:14.365425 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5327 20:00:14.369161 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5328 20:00:14.369720 ==
5329 20:00:14.372381 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 20:00:14.375742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5331 20:00:14.376369 ==
5332 20:00:14.379203 DQS Delay:
5333 20:00:14.379755 DQS0 = 0, DQS1 = 0
5334 20:00:14.380127 DQM Delay:
5335 20:00:14.381898 DQM0 = 97, DQM1 = 86
5336 20:00:14.382360 DQ Delay:
5337 20:00:14.385519 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5338 20:00:14.388884 DQ4 =100, DQ5 =88, DQ6 =106, DQ7 =108
5339 20:00:14.392122 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5340 20:00:14.395426 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =96
5341 20:00:14.395890
5342 20:00:14.396431
5343 20:00:14.405018 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5344 20:00:14.408809 CH0 RK1: MR19=505, MR18=2A2A
5345 20:00:14.412090 CH0_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5346 20:00:14.415284 [RxdqsGatingPostProcess] freq 933
5347 20:00:14.422014 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5348 20:00:14.425063 Pre-setting of DQS Precalculation
5349 20:00:14.428658 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5350 20:00:14.429211 ==
5351 20:00:14.432058 Dram Type= 6, Freq= 0, CH_1, rank 0
5352 20:00:14.438492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5353 20:00:14.439080 ==
5354 20:00:14.441859 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5355 20:00:14.448371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5356 20:00:14.451808 [CA 0] Center 37 (6~68) winsize 63
5357 20:00:14.455103 [CA 1] Center 37 (6~68) winsize 63
5358 20:00:14.458421 [CA 2] Center 34 (4~65) winsize 62
5359 20:00:14.461623 [CA 3] Center 34 (4~65) winsize 62
5360 20:00:14.464880 [CA 4] Center 33 (2~64) winsize 63
5361 20:00:14.468110 [CA 5] Center 33 (2~64) winsize 63
5362 20:00:14.468598
5363 20:00:14.471511 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5364 20:00:14.471962
5365 20:00:14.474703 [CATrainingPosCal] consider 1 rank data
5366 20:00:14.478101 u2DelayCellTimex100 = 270/100 ps
5367 20:00:14.481610 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5368 20:00:14.488134 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5369 20:00:14.491258 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5370 20:00:14.494825 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5371 20:00:14.497825 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5372 20:00:14.501236 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5373 20:00:14.501690
5374 20:00:14.504595 CA PerBit enable=1, Macro0, CA PI delay=33
5375 20:00:14.505398
5376 20:00:14.507751 [CBTSetCACLKResult] CA Dly = 33
5377 20:00:14.511158 CS Dly: 5 (0~36)
5378 20:00:14.511611 ==
5379 20:00:14.514700 Dram Type= 6, Freq= 0, CH_1, rank 1
5380 20:00:14.517732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5381 20:00:14.518185 ==
5382 20:00:14.524590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5383 20:00:14.527875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5384 20:00:14.531797 [CA 0] Center 37 (6~68) winsize 63
5385 20:00:14.534667 [CA 1] Center 37 (6~68) winsize 63
5386 20:00:14.537865 [CA 2] Center 34 (4~65) winsize 62
5387 20:00:14.541328 [CA 3] Center 34 (4~64) winsize 61
5388 20:00:14.544527 [CA 4] Center 33 (3~63) winsize 61
5389 20:00:14.547922 [CA 5] Center 33 (3~63) winsize 61
5390 20:00:14.548429
5391 20:00:14.552040 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5392 20:00:14.552724
5393 20:00:14.555110 [CATrainingPosCal] consider 2 rank data
5394 20:00:14.558036 u2DelayCellTimex100 = 270/100 ps
5395 20:00:14.561470 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5396 20:00:14.564700 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5397 20:00:14.571450 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5398 20:00:14.574718 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5399 20:00:14.578271 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5400 20:00:14.581446 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5401 20:00:14.582001
5402 20:00:14.585090 CA PerBit enable=1, Macro0, CA PI delay=33
5403 20:00:14.585645
5404 20:00:14.588209 [CBTSetCACLKResult] CA Dly = 33
5405 20:00:14.588782 CS Dly: 5 (0~37)
5406 20:00:14.589146
5407 20:00:14.591816 ----->DramcWriteLeveling(PI) begin...
5408 20:00:14.594611 ==
5409 20:00:14.598186 Dram Type= 6, Freq= 0, CH_1, rank 0
5410 20:00:14.601426 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5411 20:00:14.601981 ==
5412 20:00:14.604590 Write leveling (Byte 0): 22 => 22
5413 20:00:14.607888 Write leveling (Byte 1): 22 => 22
5414 20:00:14.611420 DramcWriteLeveling(PI) end<-----
5415 20:00:14.611975
5416 20:00:14.612421 ==
5417 20:00:14.614633 Dram Type= 6, Freq= 0, CH_1, rank 0
5418 20:00:14.618166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5419 20:00:14.618724 ==
5420 20:00:14.621736 [Gating] SW mode calibration
5421 20:00:14.627789 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5422 20:00:14.634505 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5423 20:00:14.637741 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5424 20:00:14.640899 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5425 20:00:14.647780 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5426 20:00:14.650791 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5427 20:00:14.653931 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5428 20:00:14.660987 0 10 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
5429 20:00:14.664241 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5430 20:00:14.667594 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5431 20:00:14.673966 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5432 20:00:14.677610 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 20:00:14.681034 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5434 20:00:14.687469 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 20:00:14.690682 0 11 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5436 20:00:14.694143 0 11 20 | B1->B0 | 2727 4444 | 0 0 | (0 0) (0 0)
5437 20:00:14.697020 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5438 20:00:14.704131 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 20:00:14.707356 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 20:00:14.713677 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 20:00:14.717223 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5442 20:00:14.720164 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 20:00:14.724221 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5444 20:00:14.730591 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5445 20:00:14.733777 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 20:00:14.737285 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 20:00:14.743576 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 20:00:14.747051 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 20:00:14.750092 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 20:00:14.757091 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 20:00:14.760538 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 20:00:14.763365 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 20:00:14.770146 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 20:00:14.773176 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 20:00:14.776318 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 20:00:14.783476 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 20:00:14.786600 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 20:00:14.789835 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5459 20:00:14.796681 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5460 20:00:14.800008 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5461 20:00:14.803405 Total UI for P1: 0, mck2ui 16
5462 20:00:14.806410 best dqsien dly found for B0: ( 0, 14, 14)
5463 20:00:14.809951 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5464 20:00:14.812841 Total UI for P1: 0, mck2ui 16
5465 20:00:14.816340 best dqsien dly found for B1: ( 0, 14, 18)
5466 20:00:14.819995 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5467 20:00:14.823063 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5468 20:00:14.826523
5469 20:00:14.829795 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5470 20:00:14.833063 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5471 20:00:14.836511 [Gating] SW calibration Done
5472 20:00:14.837140 ==
5473 20:00:14.839578 Dram Type= 6, Freq= 0, CH_1, rank 0
5474 20:00:14.842884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5475 20:00:14.843349 ==
5476 20:00:14.843708 RX Vref Scan: 0
5477 20:00:14.844049
5478 20:00:14.846151 RX Vref 0 -> 0, step: 1
5479 20:00:14.846607
5480 20:00:14.849604 RX Delay -80 -> 252, step: 8
5481 20:00:14.853108 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5482 20:00:14.856306 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5483 20:00:14.863151 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5484 20:00:14.865966 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5485 20:00:14.869457 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5486 20:00:14.872507 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5487 20:00:14.876335 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5488 20:00:14.879509 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5489 20:00:14.886150 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5490 20:00:14.889938 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5491 20:00:14.892737 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5492 20:00:14.896136 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5493 20:00:14.899190 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5494 20:00:14.905778 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5495 20:00:14.909239 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5496 20:00:14.912853 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5497 20:00:14.913410 ==
5498 20:00:14.916114 Dram Type= 6, Freq= 0, CH_1, rank 0
5499 20:00:14.919311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5500 20:00:14.919872 ==
5501 20:00:14.922463 DQS Delay:
5502 20:00:14.923017 DQS0 = 0, DQS1 = 0
5503 20:00:14.925561 DQM Delay:
5504 20:00:14.926016 DQM0 = 94, DQM1 = 87
5505 20:00:14.926399 DQ Delay:
5506 20:00:14.929142 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5507 20:00:14.932617 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5508 20:00:14.936153 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =79
5509 20:00:14.939154 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5510 20:00:14.939709
5511 20:00:14.940068
5512 20:00:14.942711 ==
5513 20:00:14.943268 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 20:00:14.948938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5515 20:00:14.949474 ==
5516 20:00:14.949849
5517 20:00:14.950188
5518 20:00:14.952143 TX Vref Scan disable
5519 20:00:14.952701 == TX Byte 0 ==
5520 20:00:14.955386 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5521 20:00:14.962319 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5522 20:00:14.962873 == TX Byte 1 ==
5523 20:00:14.965550 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5524 20:00:14.972046 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5525 20:00:14.972692 ==
5526 20:00:14.975229 Dram Type= 6, Freq= 0, CH_1, rank 0
5527 20:00:14.978844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5528 20:00:14.979401 ==
5529 20:00:14.979768
5530 20:00:14.980304
5531 20:00:14.982225 TX Vref Scan disable
5532 20:00:14.985431 == TX Byte 0 ==
5533 20:00:14.988872 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5534 20:00:14.992154 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5535 20:00:14.995533 == TX Byte 1 ==
5536 20:00:14.998458 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5537 20:00:15.001939 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5538 20:00:15.002398
5539 20:00:15.005459 [DATLAT]
5540 20:00:15.006052 Freq=933, CH1 RK0
5541 20:00:15.006448
5542 20:00:15.008593 DATLAT Default: 0xd
5543 20:00:15.009049 0, 0xFFFF, sum = 0
5544 20:00:15.012052 1, 0xFFFF, sum = 0
5545 20:00:15.012674 2, 0xFFFF, sum = 0
5546 20:00:15.015292 3, 0xFFFF, sum = 0
5547 20:00:15.015856 4, 0xFFFF, sum = 0
5548 20:00:15.018657 5, 0xFFFF, sum = 0
5549 20:00:15.019218 6, 0xFFFF, sum = 0
5550 20:00:15.022349 7, 0xFFFF, sum = 0
5551 20:00:15.022921 8, 0xFFFF, sum = 0
5552 20:00:15.024994 9, 0xFFFF, sum = 0
5553 20:00:15.025522 10, 0x0, sum = 1
5554 20:00:15.028316 11, 0x0, sum = 2
5555 20:00:15.028787 12, 0x0, sum = 3
5556 20:00:15.031506 13, 0x0, sum = 4
5557 20:00:15.031976 best_step = 11
5558 20:00:15.032406
5559 20:00:15.032760 ==
5560 20:00:15.035216 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 20:00:15.038883 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5562 20:00:15.041664 ==
5563 20:00:15.042181 RX Vref Scan: 1
5564 20:00:15.042556
5565 20:00:15.044850 RX Vref 0 -> 0, step: 1
5566 20:00:15.045316
5567 20:00:15.048757 RX Delay -69 -> 252, step: 4
5568 20:00:15.049314
5569 20:00:15.051758 Set Vref, RX VrefLevel [Byte0]: 57
5570 20:00:15.054973 [Byte1]: 48
5571 20:00:15.055532
5572 20:00:15.058437 Final RX Vref Byte 0 = 57 to rank0
5573 20:00:15.061544 Final RX Vref Byte 1 = 48 to rank0
5574 20:00:15.064867 Final RX Vref Byte 0 = 57 to rank1
5575 20:00:15.068314 Final RX Vref Byte 1 = 48 to rank1==
5576 20:00:15.071957 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 20:00:15.074895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5578 20:00:15.075457 ==
5579 20:00:15.078147 DQS Delay:
5580 20:00:15.078719 DQS0 = 0, DQS1 = 0
5581 20:00:15.079089 DQM Delay:
5582 20:00:15.081340 DQM0 = 93, DQM1 = 88
5583 20:00:15.081895 DQ Delay:
5584 20:00:15.084562 DQ0 =96, DQ1 =90, DQ2 =84, DQ3 =92
5585 20:00:15.088041 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =90
5586 20:00:15.091435 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5587 20:00:15.094968 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
5588 20:00:15.095542
5589 20:00:15.095906
5590 20:00:15.104739 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5591 20:00:15.108078 CH1 RK0: MR19=505, MR18=3232
5592 20:00:15.111533 CH1_RK0: MR19=0x505, MR18=0x3232, DQSOSC=406, MR23=63, INC=65, DEC=43
5593 20:00:15.112088
5594 20:00:15.114920 ----->DramcWriteLeveling(PI) begin...
5595 20:00:15.117860 ==
5596 20:00:15.121075 Dram Type= 6, Freq= 0, CH_1, rank 1
5597 20:00:15.124405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5598 20:00:15.124995 ==
5599 20:00:15.127996 Write leveling (Byte 0): 24 => 24
5600 20:00:15.131309 Write leveling (Byte 1): 26 => 26
5601 20:00:15.134603 DramcWriteLeveling(PI) end<-----
5602 20:00:15.135165
5603 20:00:15.135525 ==
5604 20:00:15.137821 Dram Type= 6, Freq= 0, CH_1, rank 1
5605 20:00:15.141105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5606 20:00:15.141577 ==
5607 20:00:15.144308 [Gating] SW mode calibration
5608 20:00:15.151210 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5609 20:00:15.157949 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5610 20:00:15.160987 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 20:00:15.164508 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 20:00:15.171255 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 20:00:15.174364 0 10 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5614 20:00:15.177491 0 10 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
5615 20:00:15.184096 0 10 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
5616 20:00:15.187849 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 20:00:15.190890 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 20:00:15.194212 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 20:00:15.200521 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 20:00:15.203961 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 20:00:15.207452 0 11 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5622 20:00:15.214068 0 11 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
5623 20:00:15.217151 0 11 20 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
5624 20:00:15.220397 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 20:00:15.227315 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 20:00:15.230446 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 20:00:15.233891 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 20:00:15.240571 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 20:00:15.244020 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 20:00:15.247041 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5631 20:00:15.253769 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5632 20:00:15.256850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 20:00:15.259900 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 20:00:15.267049 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 20:00:15.270059 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 20:00:15.273436 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 20:00:15.280063 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 20:00:15.283864 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 20:00:15.286824 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 20:00:15.293188 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 20:00:15.296799 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 20:00:15.299750 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 20:00:15.306749 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 20:00:15.310000 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 20:00:15.313169 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 20:00:15.320068 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5647 20:00:15.323268 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5648 20:00:15.326580 Total UI for P1: 0, mck2ui 16
5649 20:00:15.329698 best dqsien dly found for B0: ( 0, 14, 16)
5650 20:00:15.332891 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 20:00:15.336679 Total UI for P1: 0, mck2ui 16
5652 20:00:15.340526 best dqsien dly found for B1: ( 0, 14, 20)
5653 20:00:15.343376 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5654 20:00:15.346322 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5655 20:00:15.346781
5656 20:00:15.353250 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5657 20:00:15.356424 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5658 20:00:15.356983 [Gating] SW calibration Done
5659 20:00:15.360325 ==
5660 20:00:15.363239 Dram Type= 6, Freq= 0, CH_1, rank 1
5661 20:00:15.366698 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5662 20:00:15.367264 ==
5663 20:00:15.367628 RX Vref Scan: 0
5664 20:00:15.367971
5665 20:00:15.369416 RX Vref 0 -> 0, step: 1
5666 20:00:15.369869
5667 20:00:15.373112 RX Delay -80 -> 252, step: 8
5668 20:00:15.376167 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5669 20:00:15.379428 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5670 20:00:15.383233 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5671 20:00:15.389472 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5672 20:00:15.392854 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5673 20:00:15.396079 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5674 20:00:15.399636 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5675 20:00:15.402996 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5676 20:00:15.406265 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5677 20:00:15.412738 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5678 20:00:15.416258 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5679 20:00:15.419495 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5680 20:00:15.422723 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5681 20:00:15.425853 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5682 20:00:15.429472 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5683 20:00:15.435874 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5684 20:00:15.436479 ==
5685 20:00:15.439594 Dram Type= 6, Freq= 0, CH_1, rank 1
5686 20:00:15.442404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5687 20:00:15.442871 ==
5688 20:00:15.443244 DQS Delay:
5689 20:00:15.445891 DQS0 = 0, DQS1 = 0
5690 20:00:15.446356 DQM Delay:
5691 20:00:15.449358 DQM0 = 99, DQM1 = 90
5692 20:00:15.449924 DQ Delay:
5693 20:00:15.452701 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5694 20:00:15.455799 DQ4 =99, DQ5 =107, DQ6 =103, DQ7 =95
5695 20:00:15.459451 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5696 20:00:15.462820 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5697 20:00:15.463396
5698 20:00:15.463770
5699 20:00:15.464115 ==
5700 20:00:15.465608 Dram Type= 6, Freq= 0, CH_1, rank 1
5701 20:00:15.469059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5702 20:00:15.472602 ==
5703 20:00:15.473162
5704 20:00:15.473611
5705 20:00:15.473990 TX Vref Scan disable
5706 20:00:15.475524 == TX Byte 0 ==
5707 20:00:15.479266 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5708 20:00:15.482089 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5709 20:00:15.485690 == TX Byte 1 ==
5710 20:00:15.489109 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5711 20:00:15.492556 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5712 20:00:15.495715 ==
5713 20:00:15.496334 Dram Type= 6, Freq= 0, CH_1, rank 1
5714 20:00:15.502283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5715 20:00:15.502891 ==
5716 20:00:15.503285
5717 20:00:15.503624
5718 20:00:15.505726 TX Vref Scan disable
5719 20:00:15.506279 == TX Byte 0 ==
5720 20:00:15.512098 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5721 20:00:15.515601 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5722 20:00:15.516157 == TX Byte 1 ==
5723 20:00:15.522330 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5724 20:00:15.525324 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5725 20:00:15.525828
5726 20:00:15.526289 [DATLAT]
5727 20:00:15.528968 Freq=933, CH1 RK1
5728 20:00:15.529524
5729 20:00:15.529916 DATLAT Default: 0xb
5730 20:00:15.532204 0, 0xFFFF, sum = 0
5731 20:00:15.532778 1, 0xFFFF, sum = 0
5732 20:00:15.535547 2, 0xFFFF, sum = 0
5733 20:00:15.536102 3, 0xFFFF, sum = 0
5734 20:00:15.538646 4, 0xFFFF, sum = 0
5735 20:00:15.539203 5, 0xFFFF, sum = 0
5736 20:00:15.542468 6, 0xFFFF, sum = 0
5737 20:00:15.545093 7, 0xFFFF, sum = 0
5738 20:00:15.545556 8, 0xFFFF, sum = 0
5739 20:00:15.548629 9, 0xFFFF, sum = 0
5740 20:00:15.549192 10, 0x0, sum = 1
5741 20:00:15.552061 11, 0x0, sum = 2
5742 20:00:15.552668 12, 0x0, sum = 3
5743 20:00:15.553039 13, 0x0, sum = 4
5744 20:00:15.555109 best_step = 11
5745 20:00:15.555564
5746 20:00:15.555928 ==
5747 20:00:15.558175 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 20:00:15.562180 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5749 20:00:15.562754 ==
5750 20:00:15.565258 RX Vref Scan: 0
5751 20:00:15.565711
5752 20:00:15.566073 RX Vref 0 -> 0, step: 1
5753 20:00:15.566408
5754 20:00:15.568228 RX Delay -61 -> 252, step: 4
5755 20:00:15.576278 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5756 20:00:15.579370 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5757 20:00:15.582819 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5758 20:00:15.585863 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5759 20:00:15.589101 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5760 20:00:15.595831 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5761 20:00:15.598772 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5762 20:00:15.602113 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5763 20:00:15.605404 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5764 20:00:15.608864 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5765 20:00:15.612320 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5766 20:00:15.618920 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5767 20:00:15.622373 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5768 20:00:15.625318 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5769 20:00:15.629039 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5770 20:00:15.631847 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5771 20:00:15.632318 ==
5772 20:00:15.635494 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 20:00:15.641905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5774 20:00:15.642382 ==
5775 20:00:15.642746 DQS Delay:
5776 20:00:15.645252 DQS0 = 0, DQS1 = 0
5777 20:00:15.645705 DQM Delay:
5778 20:00:15.648639 DQM0 = 96, DQM1 = 87
5779 20:00:15.649092 DQ Delay:
5780 20:00:15.651847 DQ0 =98, DQ1 =92, DQ2 =88, DQ3 =92
5781 20:00:15.655584 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =94
5782 20:00:15.658856 DQ8 =74, DQ9 =74, DQ10 =86, DQ11 =80
5783 20:00:15.662086 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5784 20:00:15.662600
5785 20:00:15.662961
5786 20:00:15.668502 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5787 20:00:15.671774 CH1 RK1: MR19=505, MR18=2A2A
5788 20:00:15.678736 CH1_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5789 20:00:15.681760 [RxdqsGatingPostProcess] freq 933
5790 20:00:15.685323 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5791 20:00:15.688391 Pre-setting of DQS Precalculation
5792 20:00:15.694898 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5793 20:00:15.701485 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5794 20:00:15.708414 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5795 20:00:15.708873
5796 20:00:15.709232
5797 20:00:15.711374 [Calibration Summary] 1866 Mbps
5798 20:00:15.715103 CH 0, Rank 0
5799 20:00:15.715659 SW Impedance : PASS
5800 20:00:15.718228 DUTY Scan : NO K
5801 20:00:15.721174 ZQ Calibration : PASS
5802 20:00:15.721630 Jitter Meter : NO K
5803 20:00:15.724512 CBT Training : PASS
5804 20:00:15.727805 Write leveling : PASS
5805 20:00:15.728325 RX DQS gating : PASS
5806 20:00:15.731511 RX DQ/DQS(RDDQC) : PASS
5807 20:00:15.734730 TX DQ/DQS : PASS
5808 20:00:15.735292 RX DATLAT : PASS
5809 20:00:15.738238 RX DQ/DQS(Engine): PASS
5810 20:00:15.738798 TX OE : NO K
5811 20:00:15.741499 All Pass.
5812 20:00:15.742050
5813 20:00:15.742507 CH 0, Rank 1
5814 20:00:15.744644 SW Impedance : PASS
5815 20:00:15.745196 DUTY Scan : NO K
5816 20:00:15.747675 ZQ Calibration : PASS
5817 20:00:15.751798 Jitter Meter : NO K
5818 20:00:15.752459 CBT Training : PASS
5819 20:00:15.754417 Write leveling : PASS
5820 20:00:15.758099 RX DQS gating : PASS
5821 20:00:15.758660 RX DQ/DQS(RDDQC) : PASS
5822 20:00:15.761154 TX DQ/DQS : PASS
5823 20:00:15.764526 RX DATLAT : PASS
5824 20:00:15.765085 RX DQ/DQS(Engine): PASS
5825 20:00:15.767678 TX OE : NO K
5826 20:00:15.768278 All Pass.
5827 20:00:15.768647
5828 20:00:15.770910 CH 1, Rank 0
5829 20:00:15.771502 SW Impedance : PASS
5830 20:00:15.773970 DUTY Scan : NO K
5831 20:00:15.777600 ZQ Calibration : PASS
5832 20:00:15.778157 Jitter Meter : NO K
5833 20:00:15.781111 CBT Training : PASS
5834 20:00:15.784322 Write leveling : PASS
5835 20:00:15.784878 RX DQS gating : PASS
5836 20:00:15.787364 RX DQ/DQS(RDDQC) : PASS
5837 20:00:15.790751 TX DQ/DQS : PASS
5838 20:00:15.791211 RX DATLAT : PASS
5839 20:00:15.794050 RX DQ/DQS(Engine): PASS
5840 20:00:15.797260 TX OE : NO K
5841 20:00:15.797718 All Pass.
5842 20:00:15.798104
5843 20:00:15.798479 CH 1, Rank 1
5844 20:00:15.800466 SW Impedance : PASS
5845 20:00:15.804004 DUTY Scan : NO K
5846 20:00:15.804657 ZQ Calibration : PASS
5847 20:00:15.807182 Jitter Meter : NO K
5848 20:00:15.807638 CBT Training : PASS
5849 20:00:15.810638 Write leveling : PASS
5850 20:00:15.814173 RX DQS gating : PASS
5851 20:00:15.814728 RX DQ/DQS(RDDQC) : PASS
5852 20:00:15.817315 TX DQ/DQS : PASS
5853 20:00:15.820383 RX DATLAT : PASS
5854 20:00:15.820839 RX DQ/DQS(Engine): PASS
5855 20:00:15.824154 TX OE : NO K
5856 20:00:15.824768 All Pass.
5857 20:00:15.825132
5858 20:00:15.827083 DramC Write-DBI off
5859 20:00:15.830644 PER_BANK_REFRESH: Hybrid Mode
5860 20:00:15.831204 TX_TRACKING: ON
5861 20:00:15.840647 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5862 20:00:15.843568 [FAST_K] Save calibration result to emmc
5863 20:00:15.847210 dramc_set_vcore_voltage set vcore to 650000
5864 20:00:15.850830 Read voltage for 400, 6
5865 20:00:15.851410 Vio18 = 0
5866 20:00:15.851778 Vcore = 650000
5867 20:00:15.853470 Vdram = 0
5868 20:00:15.853924 Vddq = 0
5869 20:00:15.854285 Vmddr = 0
5870 20:00:15.860522 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5871 20:00:15.863883 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5872 20:00:15.866820 MEM_TYPE=3, freq_sel=20
5873 20:00:15.870058 sv_algorithm_assistance_LP4_800
5874 20:00:15.873395 ============ PULL DRAM RESETB DOWN ============
5875 20:00:15.880291 ========== PULL DRAM RESETB DOWN end =========
5876 20:00:15.883249 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5877 20:00:15.886632 ===================================
5878 20:00:15.890169 LPDDR4 DRAM CONFIGURATION
5879 20:00:15.893478 ===================================
5880 20:00:15.894033 EX_ROW_EN[0] = 0x0
5881 20:00:15.896415 EX_ROW_EN[1] = 0x0
5882 20:00:15.896869 LP4Y_EN = 0x0
5883 20:00:15.900025 WORK_FSP = 0x0
5884 20:00:15.900648 WL = 0x2
5885 20:00:15.902906 RL = 0x2
5886 20:00:15.903366 BL = 0x2
5887 20:00:15.906078 RPST = 0x0
5888 20:00:15.909793 RD_PRE = 0x0
5889 20:00:15.910247 WR_PRE = 0x1
5890 20:00:15.912728 WR_PST = 0x0
5891 20:00:15.913188 DBI_WR = 0x0
5892 20:00:15.916351 DBI_RD = 0x0
5893 20:00:15.917019 OTF = 0x1
5894 20:00:15.919785 ===================================
5895 20:00:15.923151 ===================================
5896 20:00:15.923710 ANA top config
5897 20:00:15.926860 ===================================
5898 20:00:15.929852 DLL_ASYNC_EN = 0
5899 20:00:15.933130 ALL_SLAVE_EN = 1
5900 20:00:15.936421 NEW_RANK_MODE = 1
5901 20:00:15.940589 DLL_IDLE_MODE = 1
5902 20:00:15.941147 LP45_APHY_COMB_EN = 1
5903 20:00:15.942639 TX_ODT_DIS = 1
5904 20:00:15.946213 NEW_8X_MODE = 1
5905 20:00:15.949508 ===================================
5906 20:00:15.953020 ===================================
5907 20:00:15.956334 data_rate = 800
5908 20:00:15.959366 CKR = 1
5909 20:00:15.962541 DQ_P2S_RATIO = 4
5910 20:00:15.965805 ===================================
5911 20:00:15.966264 CA_P2S_RATIO = 4
5912 20:00:15.968951 DQ_CA_OPEN = 0
5913 20:00:15.972424 DQ_SEMI_OPEN = 1
5914 20:00:15.975637 CA_SEMI_OPEN = 1
5915 20:00:15.979661 CA_FULL_RATE = 0
5916 20:00:15.982428 DQ_CKDIV4_EN = 0
5917 20:00:15.982896 CA_CKDIV4_EN = 1
5918 20:00:15.985791 CA_PREDIV_EN = 0
5919 20:00:15.989206 PH8_DLY = 0
5920 20:00:15.992288 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5921 20:00:15.995810 DQ_AAMCK_DIV = 0
5922 20:00:15.999094 CA_AAMCK_DIV = 0
5923 20:00:15.999648 CA_ADMCK_DIV = 4
5924 20:00:16.002562 DQ_TRACK_CA_EN = 0
5925 20:00:16.005588 CA_PICK = 800
5926 20:00:16.008678 CA_MCKIO = 400
5927 20:00:16.012137 MCKIO_SEMI = 400
5928 20:00:16.015857 PLL_FREQ = 3016
5929 20:00:16.019087 DQ_UI_PI_RATIO = 32
5930 20:00:16.019719 CA_UI_PI_RATIO = 32
5931 20:00:16.022163 ===================================
5932 20:00:16.025897 ===================================
5933 20:00:16.028872 memory_type:LPDDR4
5934 20:00:16.032283 GP_NUM : 10
5935 20:00:16.032841 SRAM_EN : 1
5936 20:00:16.035667 MD32_EN : 0
5937 20:00:16.039039 ===================================
5938 20:00:16.042205 [ANA_INIT] >>>>>>>>>>>>>>
5939 20:00:16.045430 <<<<<< [CONFIGURE PHASE]: ANA_TX
5940 20:00:16.048669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5941 20:00:16.052146 ===================================
5942 20:00:16.052771 data_rate = 800,PCW = 0X7400
5943 20:00:16.055505 ===================================
5944 20:00:16.058857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5945 20:00:16.064896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5946 20:00:16.078551 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5947 20:00:16.081314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5948 20:00:16.084762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5949 20:00:16.088334 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5950 20:00:16.091579 [ANA_INIT] flow start
5951 20:00:16.092152 [ANA_INIT] PLL >>>>>>>>
5952 20:00:16.095013 [ANA_INIT] PLL <<<<<<<<
5953 20:00:16.097976 [ANA_INIT] MIDPI >>>>>>>>
5954 20:00:16.101349 [ANA_INIT] MIDPI <<<<<<<<
5955 20:00:16.101897 [ANA_INIT] DLL >>>>>>>>
5956 20:00:16.104397 [ANA_INIT] flow end
5957 20:00:16.107743 ============ LP4 DIFF to SE enter ============
5958 20:00:16.111510 ============ LP4 DIFF to SE exit ============
5959 20:00:16.114702 [ANA_INIT] <<<<<<<<<<<<<
5960 20:00:16.118348 [Flow] Enable top DCM control >>>>>
5961 20:00:16.121033 [Flow] Enable top DCM control <<<<<
5962 20:00:16.124647 Enable DLL master slave shuffle
5963 20:00:16.130930 ==============================================================
5964 20:00:16.131486 Gating Mode config
5965 20:00:16.137536 ==============================================================
5966 20:00:16.138078 Config description:
5967 20:00:16.147738 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5968 20:00:16.154205 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5969 20:00:16.160599 SELPH_MODE 0: By rank 1: By Phase
5970 20:00:16.163974 ==============================================================
5971 20:00:16.167285 GAT_TRACK_EN = 0
5972 20:00:16.170802 RX_GATING_MODE = 2
5973 20:00:16.173851 RX_GATING_TRACK_MODE = 2
5974 20:00:16.177272 SELPH_MODE = 1
5975 20:00:16.180446 PICG_EARLY_EN = 1
5976 20:00:16.184077 VALID_LAT_VALUE = 1
5977 20:00:16.190560 ==============================================================
5978 20:00:16.194193 Enter into Gating configuration >>>>
5979 20:00:16.197193 Exit from Gating configuration <<<<
5980 20:00:16.200693 Enter into DVFS_PRE_config >>>>>
5981 20:00:16.210458 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5982 20:00:16.213821 Exit from DVFS_PRE_config <<<<<
5983 20:00:16.217012 Enter into PICG configuration >>>>
5984 20:00:16.220102 Exit from PICG configuration <<<<
5985 20:00:16.223589 [RX_INPUT] configuration >>>>>
5986 20:00:16.224143 [RX_INPUT] configuration <<<<<
5987 20:00:16.230413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5988 20:00:16.236916 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5989 20:00:16.240564 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5990 20:00:16.246853 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5991 20:00:16.253612 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5992 20:00:16.260280 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5993 20:00:16.263556 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5994 20:00:16.266583 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5995 20:00:16.273547 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5996 20:00:16.276633 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5997 20:00:16.280010 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5998 20:00:16.286920 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5999 20:00:16.289711 ===================================
6000 20:00:16.290269 LPDDR4 DRAM CONFIGURATION
6001 20:00:16.293029 ===================================
6002 20:00:16.296388 EX_ROW_EN[0] = 0x0
6003 20:00:16.296942 EX_ROW_EN[1] = 0x0
6004 20:00:16.299959 LP4Y_EN = 0x0
6005 20:00:16.303108 WORK_FSP = 0x0
6006 20:00:16.303702 WL = 0x2
6007 20:00:16.306268 RL = 0x2
6008 20:00:16.306740 BL = 0x2
6009 20:00:16.309477 RPST = 0x0
6010 20:00:16.309962 RD_PRE = 0x0
6011 20:00:16.313124 WR_PRE = 0x1
6012 20:00:16.313675 WR_PST = 0x0
6013 20:00:16.316069 DBI_WR = 0x0
6014 20:00:16.316729 DBI_RD = 0x0
6015 20:00:16.319608 OTF = 0x1
6016 20:00:16.323000 ===================================
6017 20:00:16.325747 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6018 20:00:16.329235 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6019 20:00:16.335676 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6020 20:00:16.339334 ===================================
6021 20:00:16.339891 LPDDR4 DRAM CONFIGURATION
6022 20:00:16.342586 ===================================
6023 20:00:16.345681 EX_ROW_EN[0] = 0x10
6024 20:00:16.349340 EX_ROW_EN[1] = 0x0
6025 20:00:16.349994 LP4Y_EN = 0x0
6026 20:00:16.352817 WORK_FSP = 0x0
6027 20:00:16.353366 WL = 0x2
6028 20:00:16.355466 RL = 0x2
6029 20:00:16.355920 BL = 0x2
6030 20:00:16.359231 RPST = 0x0
6031 20:00:16.359780 RD_PRE = 0x0
6032 20:00:16.362341 WR_PRE = 0x1
6033 20:00:16.362899 WR_PST = 0x0
6034 20:00:16.365886 DBI_WR = 0x0
6035 20:00:16.366439 DBI_RD = 0x0
6036 20:00:16.368966 OTF = 0x1
6037 20:00:16.372261 ===================================
6038 20:00:16.379049 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6039 20:00:16.382474 nWR fixed to 30
6040 20:00:16.383031 [ModeRegInit_LP4] CH0 RK0
6041 20:00:16.385174 [ModeRegInit_LP4] CH0 RK1
6042 20:00:16.388846 [ModeRegInit_LP4] CH1 RK0
6043 20:00:16.392119 [ModeRegInit_LP4] CH1 RK1
6044 20:00:16.392725 match AC timing 18
6045 20:00:16.398793 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6046 20:00:16.401975 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6047 20:00:16.405439 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6048 20:00:16.411764 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6049 20:00:16.415235 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6050 20:00:16.415797 ==
6051 20:00:16.418625 Dram Type= 6, Freq= 0, CH_0, rank 0
6052 20:00:16.421908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6053 20:00:16.422472 ==
6054 20:00:16.428267 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6055 20:00:16.434997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6056 20:00:16.438832 [CA 0] Center 36 (8~64) winsize 57
6057 20:00:16.439388 [CA 1] Center 36 (8~64) winsize 57
6058 20:00:16.442289 [CA 2] Center 36 (8~64) winsize 57
6059 20:00:16.445058 [CA 3] Center 36 (8~64) winsize 57
6060 20:00:16.448222 [CA 4] Center 36 (8~64) winsize 57
6061 20:00:16.451643 [CA 5] Center 36 (8~64) winsize 57
6062 20:00:16.452246
6063 20:00:16.454664 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6064 20:00:16.455122
6065 20:00:16.461560 [CATrainingPosCal] consider 1 rank data
6066 20:00:16.462121 u2DelayCellTimex100 = 270/100 ps
6067 20:00:16.468092 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6068 20:00:16.471405 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6069 20:00:16.474846 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6070 20:00:16.478139 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6071 20:00:16.481187 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6072 20:00:16.484714 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6073 20:00:16.485269
6074 20:00:16.487785 CA PerBit enable=1, Macro0, CA PI delay=36
6075 20:00:16.488386
6076 20:00:16.491245 [CBTSetCACLKResult] CA Dly = 36
6077 20:00:16.494447 CS Dly: 1 (0~32)
6078 20:00:16.495002 ==
6079 20:00:16.498052 Dram Type= 6, Freq= 0, CH_0, rank 1
6080 20:00:16.501047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6081 20:00:16.501607 ==
6082 20:00:16.507815 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6083 20:00:16.511222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6084 20:00:16.514402 [CA 0] Center 36 (8~64) winsize 57
6085 20:00:16.517753 [CA 1] Center 36 (8~64) winsize 57
6086 20:00:16.521026 [CA 2] Center 36 (8~64) winsize 57
6087 20:00:16.524309 [CA 3] Center 36 (8~64) winsize 57
6088 20:00:16.527800 [CA 4] Center 36 (8~64) winsize 57
6089 20:00:16.531125 [CA 5] Center 36 (8~64) winsize 57
6090 20:00:16.531839
6091 20:00:16.534361 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6092 20:00:16.534916
6093 20:00:16.537367 [CATrainingPosCal] consider 2 rank data
6094 20:00:16.540632 u2DelayCellTimex100 = 270/100 ps
6095 20:00:16.544040 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6096 20:00:16.547616 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6097 20:00:16.554331 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6098 20:00:16.557615 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6099 20:00:16.561035 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6100 20:00:16.564080 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6101 20:00:16.564674
6102 20:00:16.567454 CA PerBit enable=1, Macro0, CA PI delay=36
6103 20:00:16.567910
6104 20:00:16.570686 [CBTSetCACLKResult] CA Dly = 36
6105 20:00:16.571142 CS Dly: 1 (0~32)
6106 20:00:16.571530
6107 20:00:16.574161 ----->DramcWriteLeveling(PI) begin...
6108 20:00:16.577355 ==
6109 20:00:16.577928 Dram Type= 6, Freq= 0, CH_0, rank 0
6110 20:00:16.584264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6111 20:00:16.584837 ==
6112 20:00:16.587316 Write leveling (Byte 0): 32 => 0
6113 20:00:16.590543 Write leveling (Byte 1): 32 => 0
6114 20:00:16.591109 DramcWriteLeveling(PI) end<-----
6115 20:00:16.593963
6116 20:00:16.594528 ==
6117 20:00:16.597109 Dram Type= 6, Freq= 0, CH_0, rank 0
6118 20:00:16.600836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6119 20:00:16.601404 ==
6120 20:00:16.604291 [Gating] SW mode calibration
6121 20:00:16.610384 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6122 20:00:16.613873 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6123 20:00:16.620609 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6124 20:00:16.624002 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6125 20:00:16.627299 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6126 20:00:16.633715 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6127 20:00:16.636994 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6128 20:00:16.640534 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6129 20:00:16.646910 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6130 20:00:16.650776 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6131 20:00:16.653443 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6132 20:00:16.656912 Total UI for P1: 0, mck2ui 16
6133 20:00:16.660287 best dqsien dly found for B0: ( 0, 10, 16)
6134 20:00:16.663468 Total UI for P1: 0, mck2ui 16
6135 20:00:16.666993 best dqsien dly found for B1: ( 0, 10, 16)
6136 20:00:16.670138 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6137 20:00:16.673473 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6138 20:00:16.673948
6139 20:00:16.680603 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6140 20:00:16.683429 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6141 20:00:16.686765 [Gating] SW calibration Done
6142 20:00:16.687341 ==
6143 20:00:16.690192 Dram Type= 6, Freq= 0, CH_0, rank 0
6144 20:00:16.693395 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6145 20:00:16.693971 ==
6146 20:00:16.694461 RX Vref Scan: 0
6147 20:00:16.696707
6148 20:00:16.697287 RX Vref 0 -> 0, step: 1
6149 20:00:16.697775
6150 20:00:16.699794 RX Delay -410 -> 252, step: 16
6151 20:00:16.703427 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6152 20:00:16.709872 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6153 20:00:16.713364 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6154 20:00:16.716505 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6155 20:00:16.719886 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6156 20:00:16.726545 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6157 20:00:16.729634 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6158 20:00:16.732913 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6159 20:00:16.736214 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6160 20:00:16.743072 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6161 20:00:16.746451 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6162 20:00:16.749434 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6163 20:00:16.753042 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6164 20:00:16.759614 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6165 20:00:16.762748 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6166 20:00:16.766122 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6167 20:00:16.766686 ==
6168 20:00:16.769615 Dram Type= 6, Freq= 0, CH_0, rank 0
6169 20:00:16.775775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6170 20:00:16.776337 ==
6171 20:00:16.776715 DQS Delay:
6172 20:00:16.779381 DQS0 = 51, DQS1 = 59
6173 20:00:16.779840 DQM Delay:
6174 20:00:16.780252 DQM0 = 12, DQM1 = 16
6175 20:00:16.782636 DQ Delay:
6176 20:00:16.786099 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6177 20:00:16.789141 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6178 20:00:16.789721 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6179 20:00:16.792679 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6180 20:00:16.795657
6181 20:00:16.796109
6182 20:00:16.796532 ==
6183 20:00:16.799572 Dram Type= 6, Freq= 0, CH_0, rank 0
6184 20:00:16.802991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6185 20:00:16.803559 ==
6186 20:00:16.803931
6187 20:00:16.804335
6188 20:00:16.805553 TX Vref Scan disable
6189 20:00:16.806012 == TX Byte 0 ==
6190 20:00:16.808876 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6191 20:00:16.815950 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6192 20:00:16.816579 == TX Byte 1 ==
6193 20:00:16.822584 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6194 20:00:16.825585 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6195 20:00:16.826050 ==
6196 20:00:16.828753 Dram Type= 6, Freq= 0, CH_0, rank 0
6197 20:00:16.832495 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6198 20:00:16.833075 ==
6199 20:00:16.833444
6200 20:00:16.833780
6201 20:00:16.835583 TX Vref Scan disable
6202 20:00:16.836042 == TX Byte 0 ==
6203 20:00:16.842254 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6204 20:00:16.845912 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6205 20:00:16.846473 == TX Byte 1 ==
6206 20:00:16.852371 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6207 20:00:16.855523 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6208 20:00:16.856084
6209 20:00:16.856515 [DATLAT]
6210 20:00:16.858870 Freq=400, CH0 RK0
6211 20:00:16.859332
6212 20:00:16.859699 DATLAT Default: 0xf
6213 20:00:16.862320 0, 0xFFFF, sum = 0
6214 20:00:16.862888 1, 0xFFFF, sum = 0
6215 20:00:16.865379 2, 0xFFFF, sum = 0
6216 20:00:16.865893 3, 0xFFFF, sum = 0
6217 20:00:16.868675 4, 0xFFFF, sum = 0
6218 20:00:16.869138 5, 0xFFFF, sum = 0
6219 20:00:16.872332 6, 0xFFFF, sum = 0
6220 20:00:16.872899 7, 0xFFFF, sum = 0
6221 20:00:16.875429 8, 0xFFFF, sum = 0
6222 20:00:16.878993 9, 0xFFFF, sum = 0
6223 20:00:16.879558 10, 0xFFFF, sum = 0
6224 20:00:16.881866 11, 0xFFFF, sum = 0
6225 20:00:16.882330 12, 0x0, sum = 1
6226 20:00:16.885401 13, 0x0, sum = 2
6227 20:00:16.885866 14, 0x0, sum = 3
6228 20:00:16.886387 15, 0x0, sum = 4
6229 20:00:16.888799 best_step = 13
6230 20:00:16.889357
6231 20:00:16.889729 ==
6232 20:00:16.892249 Dram Type= 6, Freq= 0, CH_0, rank 0
6233 20:00:16.895157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6234 20:00:16.895645 ==
6235 20:00:16.898410 RX Vref Scan: 1
6236 20:00:16.898869
6237 20:00:16.902119 RX Vref 0 -> 0, step: 1
6238 20:00:16.902871
6239 20:00:16.903272 RX Delay -359 -> 252, step: 8
6240 20:00:16.903622
6241 20:00:16.905127 Set Vref, RX VrefLevel [Byte0]: 51
6242 20:00:16.908652 [Byte1]: 50
6243 20:00:16.914091
6244 20:00:16.914550 Final RX Vref Byte 0 = 51 to rank0
6245 20:00:16.917122 Final RX Vref Byte 1 = 50 to rank0
6246 20:00:16.920788 Final RX Vref Byte 0 = 51 to rank1
6247 20:00:16.924303 Final RX Vref Byte 1 = 50 to rank1==
6248 20:00:16.927150 Dram Type= 6, Freq= 0, CH_0, rank 0
6249 20:00:16.934016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6250 20:00:16.934596 ==
6251 20:00:16.935082 DQS Delay:
6252 20:00:16.936856 DQS0 = 52, DQS1 = 68
6253 20:00:16.937324 DQM Delay:
6254 20:00:16.937799 DQM0 = 8, DQM1 = 17
6255 20:00:16.940593 DQ Delay:
6256 20:00:16.944023 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6257 20:00:16.944647 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6258 20:00:16.947136 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6259 20:00:16.950135 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6260 20:00:16.950608
6261 20:00:16.951084
6262 20:00:16.960347 [DQSOSCAuto] RK0, (LSB)MR18= 0x9f9f, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6263 20:00:16.963672 CH0 RK0: MR19=C0C, MR18=9F9F
6264 20:00:16.970396 CH0_RK0: MR19=0xC0C, MR18=0x9F9F, DQSOSC=389, MR23=63, INC=390, DEC=260
6265 20:00:16.970956 ==
6266 20:00:16.973360 Dram Type= 6, Freq= 0, CH_0, rank 1
6267 20:00:16.976851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6268 20:00:16.977347 ==
6269 20:00:16.980140 [Gating] SW mode calibration
6270 20:00:16.987123 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6271 20:00:16.993461 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6272 20:00:16.996676 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 20:00:17.000121 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 20:00:17.006905 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 20:00:17.009706 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6276 20:00:17.013060 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 20:00:17.016639 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 20:00:17.023220 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 20:00:17.026452 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6280 20:00:17.029740 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 20:00:17.033142 Total UI for P1: 0, mck2ui 16
6282 20:00:17.036270 best dqsien dly found for B0: ( 0, 10, 16)
6283 20:00:17.039752 Total UI for P1: 0, mck2ui 16
6284 20:00:17.043057 best dqsien dly found for B1: ( 0, 10, 16)
6285 20:00:17.046465 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6286 20:00:17.053114 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6287 20:00:17.053674
6288 20:00:17.056222 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6289 20:00:17.059402 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6290 20:00:17.062927 [Gating] SW calibration Done
6291 20:00:17.063481 ==
6292 20:00:17.065820 Dram Type= 6, Freq= 0, CH_0, rank 1
6293 20:00:17.069445 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6294 20:00:17.070143 ==
6295 20:00:17.072537 RX Vref Scan: 0
6296 20:00:17.073099
6297 20:00:17.073465 RX Vref 0 -> 0, step: 1
6298 20:00:17.073805
6299 20:00:17.075863 RX Delay -410 -> 252, step: 16
6300 20:00:17.082467 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6301 20:00:17.085829 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6302 20:00:17.089362 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6303 20:00:17.092294 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6304 20:00:17.099316 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6305 20:00:17.102768 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6306 20:00:17.105876 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6307 20:00:17.109227 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6308 20:00:17.115809 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6309 20:00:17.119136 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6310 20:00:17.122329 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6311 20:00:17.125695 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6312 20:00:17.132728 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6313 20:00:17.135887 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6314 20:00:17.139246 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6315 20:00:17.142346 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6316 20:00:17.145791 ==
6317 20:00:17.146371 Dram Type= 6, Freq= 0, CH_0, rank 1
6318 20:00:17.152565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6319 20:00:17.153151 ==
6320 20:00:17.153646 DQS Delay:
6321 20:00:17.155465 DQS0 = 43, DQS1 = 59
6322 20:00:17.156038 DQM Delay:
6323 20:00:17.158921 DQM0 = 7, DQM1 = 15
6324 20:00:17.159496 DQ Delay:
6325 20:00:17.162230 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6326 20:00:17.165340 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6327 20:00:17.169010 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6328 20:00:17.172164 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6329 20:00:17.172692
6330 20:00:17.173173
6331 20:00:17.173625 ==
6332 20:00:17.175153 Dram Type= 6, Freq= 0, CH_0, rank 1
6333 20:00:17.178559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6334 20:00:17.179113 ==
6335 20:00:17.179597
6336 20:00:17.180053
6337 20:00:17.181797 TX Vref Scan disable
6338 20:00:17.182341 == TX Byte 0 ==
6339 20:00:17.188752 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6340 20:00:17.192351 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6341 20:00:17.192943 == TX Byte 1 ==
6342 20:00:17.195213 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6343 20:00:17.201855 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6344 20:00:17.202436 ==
6345 20:00:17.205598 Dram Type= 6, Freq= 0, CH_0, rank 1
6346 20:00:17.208760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6347 20:00:17.209237 ==
6348 20:00:17.209720
6349 20:00:17.210175
6350 20:00:17.211865 TX Vref Scan disable
6351 20:00:17.212358 == TX Byte 0 ==
6352 20:00:17.218777 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6353 20:00:17.221982 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6354 20:00:17.222770 == TX Byte 1 ==
6355 20:00:17.228710 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6356 20:00:17.232051 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6357 20:00:17.232691
6358 20:00:17.233068 [DATLAT]
6359 20:00:17.235518 Freq=400, CH0 RK1
6360 20:00:17.235980
6361 20:00:17.236384 DATLAT Default: 0xd
6362 20:00:17.238396 0, 0xFFFF, sum = 0
6363 20:00:17.238867 1, 0xFFFF, sum = 0
6364 20:00:17.241655 2, 0xFFFF, sum = 0
6365 20:00:17.242117 3, 0xFFFF, sum = 0
6366 20:00:17.244982 4, 0xFFFF, sum = 0
6367 20:00:17.245463 5, 0xFFFF, sum = 0
6368 20:00:17.248100 6, 0xFFFF, sum = 0
6369 20:00:17.248602 7, 0xFFFF, sum = 0
6370 20:00:17.251482 8, 0xFFFF, sum = 0
6371 20:00:17.251945 9, 0xFFFF, sum = 0
6372 20:00:17.254726 10, 0xFFFF, sum = 0
6373 20:00:17.255052 11, 0xFFFF, sum = 0
6374 20:00:17.258446 12, 0x0, sum = 1
6375 20:00:17.258778 13, 0x0, sum = 2
6376 20:00:17.261729 14, 0x0, sum = 3
6377 20:00:17.262064 15, 0x0, sum = 4
6378 20:00:17.264829 best_step = 13
6379 20:00:17.265159
6380 20:00:17.265357 ==
6381 20:00:17.268106 Dram Type= 6, Freq= 0, CH_0, rank 1
6382 20:00:17.271587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6383 20:00:17.271923 ==
6384 20:00:17.274819 RX Vref Scan: 0
6385 20:00:17.275150
6386 20:00:17.275348 RX Vref 0 -> 0, step: 1
6387 20:00:17.275529
6388 20:00:17.277923 RX Delay -359 -> 252, step: 8
6389 20:00:17.286188 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6390 20:00:17.289710 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6391 20:00:17.292888 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6392 20:00:17.296293 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6393 20:00:17.302945 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6394 20:00:17.306525 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6395 20:00:17.309070 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6396 20:00:17.315978 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6397 20:00:17.319419 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6398 20:00:17.322881 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6399 20:00:17.325730 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6400 20:00:17.332569 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6401 20:00:17.335981 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6402 20:00:17.338933 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6403 20:00:17.342738 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6404 20:00:17.349076 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6405 20:00:17.349533 ==
6406 20:00:17.352371 Dram Type= 6, Freq= 0, CH_0, rank 1
6407 20:00:17.355937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6408 20:00:17.356548 ==
6409 20:00:17.356915 DQS Delay:
6410 20:00:17.358947 DQS0 = 52, DQS1 = 64
6411 20:00:17.359397 DQM Delay:
6412 20:00:17.362776 DQM0 = 10, DQM1 = 14
6413 20:00:17.363334 DQ Delay:
6414 20:00:17.366052 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6415 20:00:17.369011 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6416 20:00:17.372568 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6417 20:00:17.375841 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6418 20:00:17.376449
6419 20:00:17.376814
6420 20:00:17.382561 [DQSOSCAuto] RK1, (LSB)MR18= 0xbebe, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6421 20:00:17.386094 CH0 RK1: MR19=C0C, MR18=BEBE
6422 20:00:17.392336 CH0_RK1: MR19=0xC0C, MR18=0xBEBE, DQSOSC=386, MR23=63, INC=396, DEC=264
6423 20:00:17.395552 [RxdqsGatingPostProcess] freq 400
6424 20:00:17.402520 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6425 20:00:17.403081 Pre-setting of DQS Precalculation
6426 20:00:17.409468 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6427 20:00:17.410027 ==
6428 20:00:17.412212 Dram Type= 6, Freq= 0, CH_1, rank 0
6429 20:00:17.415724 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6430 20:00:17.416335 ==
6431 20:00:17.422383 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6432 20:00:17.428945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6433 20:00:17.432080 [CA 0] Center 36 (8~64) winsize 57
6434 20:00:17.435667 [CA 1] Center 36 (8~64) winsize 57
6435 20:00:17.438918 [CA 2] Center 36 (8~64) winsize 57
6436 20:00:17.442280 [CA 3] Center 36 (8~64) winsize 57
6437 20:00:17.442848 [CA 4] Center 36 (8~64) winsize 57
6438 20:00:17.445354 [CA 5] Center 36 (8~64) winsize 57
6439 20:00:17.445832
6440 20:00:17.452392 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6441 20:00:17.452946
6442 20:00:17.455247 [CATrainingPosCal] consider 1 rank data
6443 20:00:17.458611 u2DelayCellTimex100 = 270/100 ps
6444 20:00:17.462219 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6445 20:00:17.465353 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6446 20:00:17.468841 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6447 20:00:17.472139 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6448 20:00:17.475285 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6449 20:00:17.478751 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6450 20:00:17.479353
6451 20:00:17.482128 CA PerBit enable=1, Macro0, CA PI delay=36
6452 20:00:17.482690
6453 20:00:17.485476 [CBTSetCACLKResult] CA Dly = 36
6454 20:00:17.488454 CS Dly: 1 (0~32)
6455 20:00:17.488916 ==
6456 20:00:17.492092 Dram Type= 6, Freq= 0, CH_1, rank 1
6457 20:00:17.495534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6458 20:00:17.496097 ==
6459 20:00:17.501790 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6460 20:00:17.505357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6461 20:00:17.508634 [CA 0] Center 36 (8~64) winsize 57
6462 20:00:17.511909 [CA 1] Center 36 (8~64) winsize 57
6463 20:00:17.514900 [CA 2] Center 36 (8~64) winsize 57
6464 20:00:17.518286 [CA 3] Center 36 (8~64) winsize 57
6465 20:00:17.521771 [CA 4] Center 32 (8~56) winsize 49
6466 20:00:17.525288 [CA 5] Center 36 (8~64) winsize 57
6467 20:00:17.525850
6468 20:00:17.528496 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6469 20:00:17.529060
6470 20:00:17.531858 [CATrainingPosCal] consider 2 rank data
6471 20:00:17.535221 u2DelayCellTimex100 = 270/100 ps
6472 20:00:17.538424 CA0 delay=36 (8~64),Diff = 4 PI (57 cell)
6473 20:00:17.545132 CA1 delay=36 (8~64),Diff = 4 PI (57 cell)
6474 20:00:17.548337 CA2 delay=36 (8~64),Diff = 4 PI (57 cell)
6475 20:00:17.551484 CA3 delay=36 (8~64),Diff = 4 PI (57 cell)
6476 20:00:17.554895 CA4 delay=32 (8~56),Diff = 0 PI (0 cell)
6477 20:00:17.558040 CA5 delay=36 (8~64),Diff = 4 PI (57 cell)
6478 20:00:17.558689
6479 20:00:17.561350 CA PerBit enable=1, Macro0, CA PI delay=32
6480 20:00:17.561922
6481 20:00:17.565150 [CBTSetCACLKResult] CA Dly = 32
6482 20:00:17.568040 CS Dly: 1 (0~32)
6483 20:00:17.568654
6484 20:00:17.571475 ----->DramcWriteLeveling(PI) begin...
6485 20:00:17.572043 ==
6486 20:00:17.575057 Dram Type= 6, Freq= 0, CH_1, rank 0
6487 20:00:17.578079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6488 20:00:17.578545 ==
6489 20:00:17.581628 Write leveling (Byte 0): 32 => 0
6490 20:00:17.584756 Write leveling (Byte 1): 32 => 0
6491 20:00:17.588104 DramcWriteLeveling(PI) end<-----
6492 20:00:17.588712
6493 20:00:17.589080 ==
6494 20:00:17.591679 Dram Type= 6, Freq= 0, CH_1, rank 0
6495 20:00:17.595077 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6496 20:00:17.595644 ==
6497 20:00:17.598185 [Gating] SW mode calibration
6498 20:00:17.604627 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6499 20:00:17.611662 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6500 20:00:17.614273 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6501 20:00:17.617863 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6502 20:00:17.624370 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 20:00:17.627589 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6504 20:00:17.630935 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 20:00:17.637503 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 20:00:17.640917 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 20:00:17.644342 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6508 20:00:17.650582 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 20:00:17.653961 Total UI for P1: 0, mck2ui 16
6510 20:00:17.657417 best dqsien dly found for B0: ( 0, 10, 16)
6511 20:00:17.657973 Total UI for P1: 0, mck2ui 16
6512 20:00:17.663850 best dqsien dly found for B1: ( 0, 10, 16)
6513 20:00:17.667067 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6514 20:00:17.670373 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6515 20:00:17.670832
6516 20:00:17.673785 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6517 20:00:17.677279 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6518 20:00:17.680821 [Gating] SW calibration Done
6519 20:00:17.681383 ==
6520 20:00:17.683794 Dram Type= 6, Freq= 0, CH_1, rank 0
6521 20:00:17.686726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6522 20:00:17.687338 ==
6523 20:00:17.690154 RX Vref Scan: 0
6524 20:00:17.690613
6525 20:00:17.693380 RX Vref 0 -> 0, step: 1
6526 20:00:17.693842
6527 20:00:17.694200 RX Delay -410 -> 252, step: 16
6528 20:00:17.700296 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6529 20:00:17.703376 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6530 20:00:17.706749 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6531 20:00:17.710587 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6532 20:00:17.717090 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6533 20:00:17.720283 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6534 20:00:17.723192 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6535 20:00:17.726465 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6536 20:00:17.733498 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6537 20:00:17.736767 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6538 20:00:17.740003 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6539 20:00:17.746372 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6540 20:00:17.749817 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6541 20:00:17.753061 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6542 20:00:17.756448 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6543 20:00:17.763115 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6544 20:00:17.763674 ==
6545 20:00:17.766361 Dram Type= 6, Freq= 0, CH_1, rank 0
6546 20:00:17.769656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6547 20:00:17.770140 ==
6548 20:00:17.770508 DQS Delay:
6549 20:00:17.772996 DQS0 = 43, DQS1 = 59
6550 20:00:17.773459 DQM Delay:
6551 20:00:17.776576 DQM0 = 6, DQM1 = 15
6552 20:00:17.777134 DQ Delay:
6553 20:00:17.779687 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6554 20:00:17.782851 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6555 20:00:17.786583 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6556 20:00:17.789561 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6557 20:00:17.790021
6558 20:00:17.790387
6559 20:00:17.790725 ==
6560 20:00:17.792914 Dram Type= 6, Freq= 0, CH_1, rank 0
6561 20:00:17.796244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6562 20:00:17.796805 ==
6563 20:00:17.797178
6564 20:00:17.797524
6565 20:00:17.799357 TX Vref Scan disable
6566 20:00:17.802654 == TX Byte 0 ==
6567 20:00:17.806144 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6568 20:00:17.809268 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6569 20:00:17.812562 == TX Byte 1 ==
6570 20:00:17.815781 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6571 20:00:17.819399 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6572 20:00:17.819959 ==
6573 20:00:17.822570 Dram Type= 6, Freq= 0, CH_1, rank 0
6574 20:00:17.825889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6575 20:00:17.829394 ==
6576 20:00:17.829951
6577 20:00:17.830318
6578 20:00:17.830750 TX Vref Scan disable
6579 20:00:17.832312 == TX Byte 0 ==
6580 20:00:17.835846 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6581 20:00:17.839242 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6582 20:00:17.842380 == TX Byte 1 ==
6583 20:00:17.845512 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6584 20:00:17.848793 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6585 20:00:17.849257
6586 20:00:17.852265 [DATLAT]
6587 20:00:17.852727 Freq=400, CH1 RK0
6588 20:00:17.853100
6589 20:00:17.855888 DATLAT Default: 0xf
6590 20:00:17.856509 0, 0xFFFF, sum = 0
6591 20:00:17.859693 1, 0xFFFF, sum = 0
6592 20:00:17.860436 2, 0xFFFF, sum = 0
6593 20:00:17.862133 3, 0xFFFF, sum = 0
6594 20:00:17.862600 4, 0xFFFF, sum = 0
6595 20:00:17.865615 5, 0xFFFF, sum = 0
6596 20:00:17.866083 6, 0xFFFF, sum = 0
6597 20:00:17.868922 7, 0xFFFF, sum = 0
6598 20:00:17.869392 8, 0xFFFF, sum = 0
6599 20:00:17.872299 9, 0xFFFF, sum = 0
6600 20:00:17.872774 10, 0xFFFF, sum = 0
6601 20:00:17.875784 11, 0xFFFF, sum = 0
6602 20:00:17.876408 12, 0x0, sum = 1
6603 20:00:17.878844 13, 0x0, sum = 2
6604 20:00:17.879315 14, 0x0, sum = 3
6605 20:00:17.882246 15, 0x0, sum = 4
6606 20:00:17.882934 best_step = 13
6607 20:00:17.883316
6608 20:00:17.883664 ==
6609 20:00:17.885782 Dram Type= 6, Freq= 0, CH_1, rank 0
6610 20:00:17.892031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6611 20:00:17.892628 ==
6612 20:00:17.893001 RX Vref Scan: 1
6613 20:00:17.893340
6614 20:00:17.895663 RX Vref 0 -> 0, step: 1
6615 20:00:17.896435
6616 20:00:17.898998 RX Delay -359 -> 252, step: 8
6617 20:00:17.899554
6618 20:00:17.902472 Set Vref, RX VrefLevel [Byte0]: 57
6619 20:00:17.905858 [Byte1]: 48
6620 20:00:17.906435
6621 20:00:17.908951 Final RX Vref Byte 0 = 57 to rank0
6622 20:00:17.912286 Final RX Vref Byte 1 = 48 to rank0
6623 20:00:17.915398 Final RX Vref Byte 0 = 57 to rank1
6624 20:00:17.919260 Final RX Vref Byte 1 = 48 to rank1==
6625 20:00:17.922472 Dram Type= 6, Freq= 0, CH_1, rank 0
6626 20:00:17.925491 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6627 20:00:17.928995 ==
6628 20:00:17.929458 DQS Delay:
6629 20:00:17.929825 DQS0 = 52, DQS1 = 64
6630 20:00:17.932099 DQM Delay:
6631 20:00:17.932612 DQM0 = 11, DQM1 = 16
6632 20:00:17.935811 DQ Delay:
6633 20:00:17.936439 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6634 20:00:17.939145 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6635 20:00:17.942382 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6636 20:00:17.945454 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6637 20:00:17.945918
6638 20:00:17.946284
6639 20:00:17.955688 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdcd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6640 20:00:17.958835 CH1 RK0: MR19=C0C, MR18=CDCD
6641 20:00:17.965316 CH1_RK0: MR19=0xC0C, MR18=0xCDCD, DQSOSC=384, MR23=63, INC=400, DEC=267
6642 20:00:17.965913 ==
6643 20:00:17.968968 Dram Type= 6, Freq= 0, CH_1, rank 1
6644 20:00:17.972345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6645 20:00:17.972902 ==
6646 20:00:17.975367 [Gating] SW mode calibration
6647 20:00:17.982601 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6648 20:00:17.985488 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6649 20:00:17.992108 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6650 20:00:17.995483 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6651 20:00:17.998918 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6652 20:00:18.005374 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6653 20:00:18.008761 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 20:00:18.011786 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 20:00:18.018531 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 20:00:18.021834 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6657 20:00:18.025054 Total UI for P1: 0, mck2ui 16
6658 20:00:18.028150 best dqsien dly found for B0: ( 0, 10, 8)
6659 20:00:18.031722 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 20:00:18.035063 Total UI for P1: 0, mck2ui 16
6661 20:00:18.038183 best dqsien dly found for B1: ( 0, 10, 16)
6662 20:00:18.041462 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6663 20:00:18.044975 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6664 20:00:18.045438
6665 20:00:18.051504 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6666 20:00:18.055123 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6667 20:00:18.058351 [Gating] SW calibration Done
6668 20:00:18.058905 ==
6669 20:00:18.061536 Dram Type= 6, Freq= 0, CH_1, rank 1
6670 20:00:18.064794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6671 20:00:18.065351 ==
6672 20:00:18.065724 RX Vref Scan: 0
6673 20:00:18.068442
6674 20:00:18.068904 RX Vref 0 -> 0, step: 1
6675 20:00:18.069273
6676 20:00:18.071612 RX Delay -410 -> 252, step: 16
6677 20:00:18.074771 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6678 20:00:18.081305 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6679 20:00:18.084474 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6680 20:00:18.088036 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6681 20:00:18.091468 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6682 20:00:18.098116 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6683 20:00:18.101173 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6684 20:00:18.104633 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6685 20:00:18.108162 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6686 20:00:18.114399 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6687 20:00:18.117685 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6688 20:00:18.121268 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6689 20:00:18.124511 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6690 20:00:18.131217 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6691 20:00:18.134708 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6692 20:00:18.138176 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6693 20:00:18.138731 ==
6694 20:00:18.140834 Dram Type= 6, Freq= 0, CH_1, rank 1
6695 20:00:18.147685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6696 20:00:18.148318 ==
6697 20:00:18.148695 DQS Delay:
6698 20:00:18.151103 DQS0 = 43, DQS1 = 59
6699 20:00:18.151670 DQM Delay:
6700 20:00:18.152040 DQM0 = 10, DQM1 = 16
6701 20:00:18.154184 DQ Delay:
6702 20:00:18.157643 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6703 20:00:18.158223 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6704 20:00:18.160884 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6705 20:00:18.164397 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =24
6706 20:00:18.164960
6707 20:00:18.165325
6708 20:00:18.167543 ==
6709 20:00:18.171085 Dram Type= 6, Freq= 0, CH_1, rank 1
6710 20:00:18.173999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6711 20:00:18.174461 ==
6712 20:00:18.174827
6713 20:00:18.175162
6714 20:00:18.177739 TX Vref Scan disable
6715 20:00:18.178302 == TX Byte 0 ==
6716 20:00:18.181009 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6717 20:00:18.187448 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6718 20:00:18.188011 == TX Byte 1 ==
6719 20:00:18.190881 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6720 20:00:18.197310 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6721 20:00:18.197876 ==
6722 20:00:18.200525 Dram Type= 6, Freq= 0, CH_1, rank 1
6723 20:00:18.204071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6724 20:00:18.204691 ==
6725 20:00:18.205059
6726 20:00:18.205399
6727 20:00:18.206959 TX Vref Scan disable
6728 20:00:18.207417 == TX Byte 0 ==
6729 20:00:18.210616 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6730 20:00:18.216838 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6731 20:00:18.217327 == TX Byte 1 ==
6732 20:00:18.220315 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6733 20:00:18.226959 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6734 20:00:18.227517
6735 20:00:18.227887 [DATLAT]
6736 20:00:18.228296 Freq=400, CH1 RK1
6737 20:00:18.230344
6738 20:00:18.230902 DATLAT Default: 0xd
6739 20:00:18.233738 0, 0xFFFF, sum = 0
6740 20:00:18.234302 1, 0xFFFF, sum = 0
6741 20:00:18.236777 2, 0xFFFF, sum = 0
6742 20:00:18.237247 3, 0xFFFF, sum = 0
6743 20:00:18.240484 4, 0xFFFF, sum = 0
6744 20:00:18.241047 5, 0xFFFF, sum = 0
6745 20:00:18.243518 6, 0xFFFF, sum = 0
6746 20:00:18.244079 7, 0xFFFF, sum = 0
6747 20:00:18.247248 8, 0xFFFF, sum = 0
6748 20:00:18.247863 9, 0xFFFF, sum = 0
6749 20:00:18.250259 10, 0xFFFF, sum = 0
6750 20:00:18.250821 11, 0xFFFF, sum = 0
6751 20:00:18.253174 12, 0x0, sum = 1
6752 20:00:18.253642 13, 0x0, sum = 2
6753 20:00:18.256515 14, 0x0, sum = 3
6754 20:00:18.256983 15, 0x0, sum = 4
6755 20:00:18.260016 best_step = 13
6756 20:00:18.260652
6757 20:00:18.261024 ==
6758 20:00:18.263422 Dram Type= 6, Freq= 0, CH_1, rank 1
6759 20:00:18.266888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6760 20:00:18.267456 ==
6761 20:00:18.270053 RX Vref Scan: 0
6762 20:00:18.270662
6763 20:00:18.271125 RX Vref 0 -> 0, step: 1
6764 20:00:18.271473
6765 20:00:18.272959 RX Delay -359 -> 252, step: 8
6766 20:00:18.281149 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6767 20:00:18.284352 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6768 20:00:18.287725 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6769 20:00:18.294301 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6770 20:00:18.297508 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6771 20:00:18.301157 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6772 20:00:18.304663 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6773 20:00:18.310890 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6774 20:00:18.314439 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6775 20:00:18.317554 iDelay=225, Bit 9, Center -60 (-303 ~ 184) 488
6776 20:00:18.320635 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6777 20:00:18.327387 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6778 20:00:18.330479 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6779 20:00:18.333821 iDelay=225, Bit 13, Center -36 (-279 ~ 208) 488
6780 20:00:18.337041 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6781 20:00:18.343764 iDelay=225, Bit 15, Center -44 (-287 ~ 200) 488
6782 20:00:18.344376 ==
6783 20:00:18.346766 Dram Type= 6, Freq= 0, CH_1, rank 1
6784 20:00:18.350402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6785 20:00:18.350970 ==
6786 20:00:18.351341 DQS Delay:
6787 20:00:18.353589 DQS0 = 48, DQS1 = 64
6788 20:00:18.354051 DQM Delay:
6789 20:00:18.357134 DQM0 = 9, DQM1 = 15
6790 20:00:18.357696 DQ Delay:
6791 20:00:18.360365 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6792 20:00:18.363395 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6793 20:00:18.367201 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6794 20:00:18.370507 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =20
6795 20:00:18.371212
6796 20:00:18.371594
6797 20:00:18.377126 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6798 20:00:18.380299 CH1 RK1: MR19=C0C, MR18=B0B0
6799 20:00:18.386836 CH1_RK1: MR19=0xC0C, MR18=0xB0B0, DQSOSC=387, MR23=63, INC=394, DEC=262
6800 20:00:18.390237 [RxdqsGatingPostProcess] freq 400
6801 20:00:18.396821 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6802 20:00:18.400157 Pre-setting of DQS Precalculation
6803 20:00:18.403563 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6804 20:00:18.409961 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6805 20:00:18.416721 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6806 20:00:18.419784
6807 20:00:18.420290
6808 20:00:18.420669 [Calibration Summary] 800 Mbps
6809 20:00:18.423250 CH 0, Rank 0
6810 20:00:18.423811 SW Impedance : PASS
6811 20:00:18.426465 DUTY Scan : NO K
6812 20:00:18.429735 ZQ Calibration : PASS
6813 20:00:18.430202 Jitter Meter : NO K
6814 20:00:18.433403 CBT Training : PASS
6815 20:00:18.436436 Write leveling : PASS
6816 20:00:18.436996 RX DQS gating : PASS
6817 20:00:18.439569 RX DQ/DQS(RDDQC) : PASS
6818 20:00:18.443019 TX DQ/DQS : PASS
6819 20:00:18.443592 RX DATLAT : PASS
6820 20:00:18.446313 RX DQ/DQS(Engine): PASS
6821 20:00:18.449758 TX OE : NO K
6822 20:00:18.450324 All Pass.
6823 20:00:18.450696
6824 20:00:18.451039 CH 0, Rank 1
6825 20:00:18.453298 SW Impedance : PASS
6826 20:00:18.456341 DUTY Scan : NO K
6827 20:00:18.456900 ZQ Calibration : PASS
6828 20:00:18.459492 Jitter Meter : NO K
6829 20:00:18.462872 CBT Training : PASS
6830 20:00:18.463647 Write leveling : NO K
6831 20:00:18.466263 RX DQS gating : PASS
6832 20:00:18.466717 RX DQ/DQS(RDDQC) : PASS
6833 20:00:18.469229 TX DQ/DQS : PASS
6834 20:00:18.472875 RX DATLAT : PASS
6835 20:00:18.473429 RX DQ/DQS(Engine): PASS
6836 20:00:18.475876 TX OE : NO K
6837 20:00:18.476376 All Pass.
6838 20:00:18.476740
6839 20:00:18.479414 CH 1, Rank 0
6840 20:00:18.479981 SW Impedance : PASS
6841 20:00:18.482749 DUTY Scan : NO K
6842 20:00:18.485934 ZQ Calibration : PASS
6843 20:00:18.486488 Jitter Meter : NO K
6844 20:00:18.489091 CBT Training : PASS
6845 20:00:18.492883 Write leveling : PASS
6846 20:00:18.493444 RX DQS gating : PASS
6847 20:00:18.495790 RX DQ/DQS(RDDQC) : PASS
6848 20:00:18.499183 TX DQ/DQS : PASS
6849 20:00:18.499639 RX DATLAT : PASS
6850 20:00:18.502490 RX DQ/DQS(Engine): PASS
6851 20:00:18.505904 TX OE : NO K
6852 20:00:18.506464 All Pass.
6853 20:00:18.506830
6854 20:00:18.507165 CH 1, Rank 1
6855 20:00:18.508796 SW Impedance : PASS
6856 20:00:18.512336 DUTY Scan : NO K
6857 20:00:18.512896 ZQ Calibration : PASS
6858 20:00:18.515743 Jitter Meter : NO K
6859 20:00:18.518659 CBT Training : PASS
6860 20:00:18.519316 Write leveling : NO K
6861 20:00:18.522425 RX DQS gating : PASS
6862 20:00:18.525516 RX DQ/DQS(RDDQC) : PASS
6863 20:00:18.525972 TX DQ/DQS : PASS
6864 20:00:18.528586 RX DATLAT : PASS
6865 20:00:18.532494 RX DQ/DQS(Engine): PASS
6866 20:00:18.533052 TX OE : NO K
6867 20:00:18.533419 All Pass.
6868 20:00:18.535582
6869 20:00:18.536133 DramC Write-DBI off
6870 20:00:18.538881 PER_BANK_REFRESH: Hybrid Mode
6871 20:00:18.539443 TX_TRACKING: ON
6872 20:00:18.548414 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6873 20:00:18.551853 [FAST_K] Save calibration result to emmc
6874 20:00:18.555081 dramc_set_vcore_voltage set vcore to 725000
6875 20:00:18.558194 Read voltage for 1600, 0
6876 20:00:18.558654 Vio18 = 0
6877 20:00:18.561983 Vcore = 725000
6878 20:00:18.562541 Vdram = 0
6879 20:00:18.562907 Vddq = 0
6880 20:00:18.563247 Vmddr = 0
6881 20:00:18.568433 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6882 20:00:18.575193 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6883 20:00:18.575833 MEM_TYPE=3, freq_sel=13
6884 20:00:18.578230 sv_algorithm_assistance_LP4_3733
6885 20:00:18.581506 ============ PULL DRAM RESETB DOWN ============
6886 20:00:18.588273 ========== PULL DRAM RESETB DOWN end =========
6887 20:00:18.591682 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6888 20:00:18.595115 ===================================
6889 20:00:18.598017 LPDDR4 DRAM CONFIGURATION
6890 20:00:18.601522 ===================================
6891 20:00:18.602101 EX_ROW_EN[0] = 0x0
6892 20:00:18.604964 EX_ROW_EN[1] = 0x0
6893 20:00:18.608047 LP4Y_EN = 0x0
6894 20:00:18.608537 WORK_FSP = 0x1
6895 20:00:18.611615 WL = 0x5
6896 20:00:18.612171 RL = 0x5
6897 20:00:18.614970 BL = 0x2
6898 20:00:18.615528 RPST = 0x0
6899 20:00:18.618331 RD_PRE = 0x0
6900 20:00:18.618785 WR_PRE = 0x1
6901 20:00:18.621152 WR_PST = 0x1
6902 20:00:18.621604 DBI_WR = 0x0
6903 20:00:18.624438 DBI_RD = 0x0
6904 20:00:18.624890 OTF = 0x1
6905 20:00:18.628065 ===================================
6906 20:00:18.631624 ===================================
6907 20:00:18.634651 ANA top config
6908 20:00:18.638111 ===================================
6909 20:00:18.638668 DLL_ASYNC_EN = 0
6910 20:00:18.641278 ALL_SLAVE_EN = 0
6911 20:00:18.644455 NEW_RANK_MODE = 1
6912 20:00:18.648076 DLL_IDLE_MODE = 1
6913 20:00:18.651671 LP45_APHY_COMB_EN = 1
6914 20:00:18.652290 TX_ODT_DIS = 0
6915 20:00:18.654398 NEW_8X_MODE = 1
6916 20:00:18.657837 ===================================
6917 20:00:18.661265 ===================================
6918 20:00:18.664760 data_rate = 3200
6919 20:00:18.668074 CKR = 1
6920 20:00:18.671053 DQ_P2S_RATIO = 8
6921 20:00:18.674422 ===================================
6922 20:00:18.677502 CA_P2S_RATIO = 8
6923 20:00:18.678069 DQ_CA_OPEN = 0
6924 20:00:18.681070 DQ_SEMI_OPEN = 0
6925 20:00:18.684355 CA_SEMI_OPEN = 0
6926 20:00:18.687763 CA_FULL_RATE = 0
6927 20:00:18.691035 DQ_CKDIV4_EN = 0
6928 20:00:18.694232 CA_CKDIV4_EN = 0
6929 20:00:18.694799 CA_PREDIV_EN = 0
6930 20:00:18.697369 PH8_DLY = 12
6931 20:00:18.700780 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6932 20:00:18.704098 DQ_AAMCK_DIV = 4
6933 20:00:18.707308 CA_AAMCK_DIV = 4
6934 20:00:18.710735 CA_ADMCK_DIV = 4
6935 20:00:18.711306 DQ_TRACK_CA_EN = 0
6936 20:00:18.713941 CA_PICK = 1600
6937 20:00:18.717182 CA_MCKIO = 1600
6938 20:00:18.720679 MCKIO_SEMI = 0
6939 20:00:18.724088 PLL_FREQ = 3068
6940 20:00:18.727335 DQ_UI_PI_RATIO = 32
6941 20:00:18.730506 CA_UI_PI_RATIO = 0
6942 20:00:18.733930 ===================================
6943 20:00:18.736910 ===================================
6944 20:00:18.737377 memory_type:LPDDR4
6945 20:00:18.740651 GP_NUM : 10
6946 20:00:18.743813 SRAM_EN : 1
6947 20:00:18.744423 MD32_EN : 0
6948 20:00:18.747328 ===================================
6949 20:00:18.750761 [ANA_INIT] >>>>>>>>>>>>>>
6950 20:00:18.753532 <<<<<< [CONFIGURE PHASE]: ANA_TX
6951 20:00:18.757040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6952 20:00:18.760422 ===================================
6953 20:00:18.763684 data_rate = 3200,PCW = 0X7600
6954 20:00:18.767018 ===================================
6955 20:00:18.770314 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6956 20:00:18.773460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6957 20:00:18.780226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6958 20:00:18.783663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6959 20:00:18.786760 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6960 20:00:18.789878 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6961 20:00:18.793301 [ANA_INIT] flow start
6962 20:00:18.796842 [ANA_INIT] PLL >>>>>>>>
6963 20:00:18.797426 [ANA_INIT] PLL <<<<<<<<
6964 20:00:18.800047 [ANA_INIT] MIDPI >>>>>>>>
6965 20:00:18.803113 [ANA_INIT] MIDPI <<<<<<<<
6966 20:00:18.806919 [ANA_INIT] DLL >>>>>>>>
6967 20:00:18.807488 [ANA_INIT] DLL <<<<<<<<
6968 20:00:18.809666 [ANA_INIT] flow end
6969 20:00:18.813082 ============ LP4 DIFF to SE enter ============
6970 20:00:18.816368 ============ LP4 DIFF to SE exit ============
6971 20:00:18.819647 [ANA_INIT] <<<<<<<<<<<<<
6972 20:00:18.823156 [Flow] Enable top DCM control >>>>>
6973 20:00:18.826659 [Flow] Enable top DCM control <<<<<
6974 20:00:18.829769 Enable DLL master slave shuffle
6975 20:00:18.836520 ==============================================================
6976 20:00:18.837093 Gating Mode config
6977 20:00:18.843136 ==============================================================
6978 20:00:18.843706 Config description:
6979 20:00:18.853162 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6980 20:00:18.859594 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6981 20:00:18.866316 SELPH_MODE 0: By rank 1: By Phase
6982 20:00:18.869393 ==============================================================
6983 20:00:18.872585 GAT_TRACK_EN = 1
6984 20:00:18.875866 RX_GATING_MODE = 2
6985 20:00:18.879474 RX_GATING_TRACK_MODE = 2
6986 20:00:18.882673 SELPH_MODE = 1
6987 20:00:18.885862 PICG_EARLY_EN = 1
6988 20:00:18.889352 VALID_LAT_VALUE = 1
6989 20:00:18.896136 ==============================================================
6990 20:00:18.899030 Enter into Gating configuration >>>>
6991 20:00:18.902631 Exit from Gating configuration <<<<
6992 20:00:18.903127 Enter into DVFS_PRE_config >>>>>
6993 20:00:18.916066 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6994 20:00:18.919075 Exit from DVFS_PRE_config <<<<<
6995 20:00:18.922299 Enter into PICG configuration >>>>
6996 20:00:18.925871 Exit from PICG configuration <<<<
6997 20:00:18.926431 [RX_INPUT] configuration >>>>>
6998 20:00:18.928997 [RX_INPUT] configuration <<<<<
6999 20:00:18.935914 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7000 20:00:18.942481 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7001 20:00:18.945673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7002 20:00:18.952447 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7003 20:00:18.959271 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7004 20:00:18.965375 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7005 20:00:18.968777 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7006 20:00:18.972103 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7007 20:00:18.978802 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7008 20:00:18.981964 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7009 20:00:18.985336 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7010 20:00:18.991981 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7011 20:00:18.995824 ===================================
7012 20:00:18.996502 LPDDR4 DRAM CONFIGURATION
7013 20:00:18.998537 ===================================
7014 20:00:19.002031 EX_ROW_EN[0] = 0x0
7015 20:00:19.002609 EX_ROW_EN[1] = 0x0
7016 20:00:19.005353 LP4Y_EN = 0x0
7017 20:00:19.005916 WORK_FSP = 0x1
7018 20:00:19.008757 WL = 0x5
7019 20:00:19.009319 RL = 0x5
7020 20:00:19.011999 BL = 0x2
7021 20:00:19.015458 RPST = 0x0
7022 20:00:19.016029 RD_PRE = 0x0
7023 20:00:19.018584 WR_PRE = 0x1
7024 20:00:19.019149 WR_PST = 0x1
7025 20:00:19.021697 DBI_WR = 0x0
7026 20:00:19.022161 DBI_RD = 0x0
7027 20:00:19.024984 OTF = 0x1
7028 20:00:19.028783 ===================================
7029 20:00:19.031895 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7030 20:00:19.035550 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7031 20:00:19.038184 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7032 20:00:19.041881 ===================================
7033 20:00:19.045063 LPDDR4 DRAM CONFIGURATION
7034 20:00:19.048253 ===================================
7035 20:00:19.051452 EX_ROW_EN[0] = 0x10
7036 20:00:19.052008 EX_ROW_EN[1] = 0x0
7037 20:00:19.054771 LP4Y_EN = 0x0
7038 20:00:19.055291 WORK_FSP = 0x1
7039 20:00:19.058314 WL = 0x5
7040 20:00:19.058872 RL = 0x5
7041 20:00:19.061647 BL = 0x2
7042 20:00:19.062206 RPST = 0x0
7043 20:00:19.065065 RD_PRE = 0x0
7044 20:00:19.068404 WR_PRE = 0x1
7045 20:00:19.068958 WR_PST = 0x1
7046 20:00:19.071436 DBI_WR = 0x0
7047 20:00:19.071991 DBI_RD = 0x0
7048 20:00:19.074749 OTF = 0x1
7049 20:00:19.077681 ===================================
7050 20:00:19.081257 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7051 20:00:19.084819 ==
7052 20:00:19.087859 Dram Type= 6, Freq= 0, CH_0, rank 0
7053 20:00:19.091372 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7054 20:00:19.091949 ==
7055 20:00:19.094471 [Duty_Offset_Calibration]
7056 20:00:19.095047 B0:0 B1:2 CA:1
7057 20:00:19.095536
7058 20:00:19.097974 [DutyScan_Calibration_Flow] k_type=0
7059 20:00:19.107881
7060 20:00:19.108504 ==CLK 0==
7061 20:00:19.111365 Final CLK duty delay cell = 0
7062 20:00:19.114633 [0] MAX Duty = 5156%(X100), DQS PI = 22
7063 20:00:19.117905 [0] MIN Duty = 4938%(X100), DQS PI = 38
7064 20:00:19.118480 [0] AVG Duty = 5047%(X100)
7065 20:00:19.121059
7066 20:00:19.124497 CH0 CLK Duty spec in!! Max-Min= 218%
7067 20:00:19.127818 [DutyScan_Calibration_Flow] ====Done====
7068 20:00:19.128438
7069 20:00:19.131001 [DutyScan_Calibration_Flow] k_type=1
7070 20:00:19.148006
7071 20:00:19.148622 ==DQS 0 ==
7072 20:00:19.151374 Final DQS duty delay cell = 0
7073 20:00:19.154393 [0] MAX Duty = 5125%(X100), DQS PI = 2
7074 20:00:19.157868 [0] MIN Duty = 5031%(X100), DQS PI = 6
7075 20:00:19.158432 [0] AVG Duty = 5078%(X100)
7076 20:00:19.161354
7077 20:00:19.161913 ==DQS 1 ==
7078 20:00:19.164500 Final DQS duty delay cell = 0
7079 20:00:19.167897 [0] MAX Duty = 5062%(X100), DQS PI = 6
7080 20:00:19.171157 [0] MIN Duty = 4907%(X100), DQS PI = 14
7081 20:00:19.171721 [0] AVG Duty = 4984%(X100)
7082 20:00:19.174601
7083 20:00:19.177918 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7084 20:00:19.178486
7085 20:00:19.180871 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7086 20:00:19.184198 [DutyScan_Calibration_Flow] ====Done====
7087 20:00:19.184658
7088 20:00:19.187920 [DutyScan_Calibration_Flow] k_type=3
7089 20:00:19.204749
7090 20:00:19.205492 ==DQM 0 ==
7091 20:00:19.208356 Final DQM duty delay cell = 0
7092 20:00:19.211578 [0] MAX Duty = 5187%(X100), DQS PI = 22
7093 20:00:19.214919 [0] MIN Duty = 4907%(X100), DQS PI = 56
7094 20:00:19.218346 [0] AVG Duty = 5047%(X100)
7095 20:00:19.218913
7096 20:00:19.219283 ==DQM 1 ==
7097 20:00:19.221234 Final DQM duty delay cell = 0
7098 20:00:19.224568 [0] MAX Duty = 5031%(X100), DQS PI = 50
7099 20:00:19.228219 [0] MIN Duty = 4782%(X100), DQS PI = 16
7100 20:00:19.231138 [0] AVG Duty = 4906%(X100)
7101 20:00:19.231711
7102 20:00:19.234266 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7103 20:00:19.234744
7104 20:00:19.238371 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7105 20:00:19.241128 [DutyScan_Calibration_Flow] ====Done====
7106 20:00:19.241676
7107 20:00:19.244277 [DutyScan_Calibration_Flow] k_type=2
7108 20:00:19.261428
7109 20:00:19.261995 ==DQ 0 ==
7110 20:00:19.264633 Final DQ duty delay cell = 0
7111 20:00:19.267920 [0] MAX Duty = 5218%(X100), DQS PI = 18
7112 20:00:19.271529 [0] MIN Duty = 4938%(X100), DQS PI = 56
7113 20:00:19.272108 [0] AVG Duty = 5078%(X100)
7114 20:00:19.274697
7115 20:00:19.275264 ==DQ 1 ==
7116 20:00:19.277950 Final DQ duty delay cell = -4
7117 20:00:19.280899 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7118 20:00:19.284301 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7119 20:00:19.288113 [-4] AVG Duty = 4953%(X100)
7120 20:00:19.288748
7121 20:00:19.291293 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7122 20:00:19.291871
7123 20:00:19.294209 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7124 20:00:19.297825 [DutyScan_Calibration_Flow] ====Done====
7125 20:00:19.298400 ==
7126 20:00:19.301042 Dram Type= 6, Freq= 0, CH_1, rank 0
7127 20:00:19.304263 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7128 20:00:19.304836 ==
7129 20:00:19.307620 [Duty_Offset_Calibration]
7130 20:00:19.308234 B0:0 B1:4 CA:-5
7131 20:00:19.308717
7132 20:00:19.310677 [DutyScan_Calibration_Flow] k_type=0
7133 20:00:19.321852
7134 20:00:19.322483 ==CLK 0==
7135 20:00:19.325055 Final CLK duty delay cell = 0
7136 20:00:19.328597 [0] MAX Duty = 5156%(X100), DQS PI = 20
7137 20:00:19.331661 [0] MIN Duty = 4906%(X100), DQS PI = 52
7138 20:00:19.335109 [0] AVG Duty = 5031%(X100)
7139 20:00:19.335664
7140 20:00:19.338373 CH1 CLK Duty spec in!! Max-Min= 250%
7141 20:00:19.341667 [DutyScan_Calibration_Flow] ====Done====
7142 20:00:19.342224
7143 20:00:19.345001 [DutyScan_Calibration_Flow] k_type=1
7144 20:00:19.360721
7145 20:00:19.361278 ==DQS 0 ==
7146 20:00:19.364082 Final DQS duty delay cell = 0
7147 20:00:19.367638 [0] MAX Duty = 5156%(X100), DQS PI = 18
7148 20:00:19.370920 [0] MIN Duty = 4844%(X100), DQS PI = 44
7149 20:00:19.373624 [0] AVG Duty = 5000%(X100)
7150 20:00:19.374080
7151 20:00:19.374437 ==DQS 1 ==
7152 20:00:19.377058 Final DQS duty delay cell = -4
7153 20:00:19.380575 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7154 20:00:19.383862 [-4] MIN Duty = 4875%(X100), DQS PI = 8
7155 20:00:19.387130 [-4] AVG Duty = 4937%(X100)
7156 20:00:19.387684
7157 20:00:19.390440 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7158 20:00:19.391011
7159 20:00:19.393567 CH1 DQS 1 Duty spec in!! Max-Min= 125%
7160 20:00:19.397097 [DutyScan_Calibration_Flow] ====Done====
7161 20:00:19.397652
7162 20:00:19.400435 [DutyScan_Calibration_Flow] k_type=3
7163 20:00:19.416294
7164 20:00:19.416845 ==DQM 0 ==
7165 20:00:19.419719 Final DQM duty delay cell = -4
7166 20:00:19.422843 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7167 20:00:19.426004 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7168 20:00:19.429612 [-4] AVG Duty = 4922%(X100)
7169 20:00:19.430170
7170 20:00:19.430534 ==DQM 1 ==
7171 20:00:19.432766 Final DQM duty delay cell = -4
7172 20:00:19.436138 [-4] MAX Duty = 5093%(X100), DQS PI = 18
7173 20:00:19.439641 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7174 20:00:19.442904 [-4] AVG Duty = 5000%(X100)
7175 20:00:19.443461
7176 20:00:19.446141 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7177 20:00:19.446697
7178 20:00:19.449163 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7179 20:00:19.452749 [DutyScan_Calibration_Flow] ====Done====
7180 20:00:19.453308
7181 20:00:19.455890 [DutyScan_Calibration_Flow] k_type=2
7182 20:00:19.474388
7183 20:00:19.474941 ==DQ 0 ==
7184 20:00:19.476971 Final DQ duty delay cell = 0
7185 20:00:19.480541 [0] MAX Duty = 5093%(X100), DQS PI = 18
7186 20:00:19.483990 [0] MIN Duty = 4938%(X100), DQS PI = 48
7187 20:00:19.484619 [0] AVG Duty = 5015%(X100)
7188 20:00:19.486985
7189 20:00:19.487440 ==DQ 1 ==
7190 20:00:19.490495 Final DQ duty delay cell = 0
7191 20:00:19.493778 [0] MAX Duty = 5031%(X100), DQS PI = 4
7192 20:00:19.497049 [0] MIN Duty = 4907%(X100), DQS PI = 22
7193 20:00:19.497608 [0] AVG Duty = 4969%(X100)
7194 20:00:19.497979
7195 20:00:19.500145 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7196 20:00:19.504066
7197 20:00:19.507244 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7198 20:00:19.510391 [DutyScan_Calibration_Flow] ====Done====
7199 20:00:19.513989 nWR fixed to 30
7200 20:00:19.514548 [ModeRegInit_LP4] CH0 RK0
7201 20:00:19.516767 [ModeRegInit_LP4] CH0 RK1
7202 20:00:19.520323 [ModeRegInit_LP4] CH1 RK0
7203 20:00:19.523424 [ModeRegInit_LP4] CH1 RK1
7204 20:00:19.524282 match AC timing 4
7205 20:00:19.530176 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7206 20:00:19.533264 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7207 20:00:19.536810 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7208 20:00:19.543590 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7209 20:00:19.546657 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7210 20:00:19.547213 [MiockJmeterHQA]
7211 20:00:19.547580
7212 20:00:19.549825 [DramcMiockJmeter] u1RxGatingPI = 0
7213 20:00:19.553123 0 : 4255, 4027
7214 20:00:19.553693 4 : 4363, 4137
7215 20:00:19.556441 8 : 4253, 4026
7216 20:00:19.556909 12 : 4252, 4026
7217 20:00:19.557278 16 : 4252, 4027
7218 20:00:19.559713 20 : 4253, 4027
7219 20:00:19.560200 24 : 4255, 4029
7220 20:00:19.563195 28 : 4252, 4027
7221 20:00:19.563754 32 : 4252, 4027
7222 20:00:19.566790 36 : 4363, 4138
7223 20:00:19.567347 40 : 4253, 4026
7224 20:00:19.569839 44 : 4252, 4027
7225 20:00:19.570307 48 : 4252, 4027
7226 20:00:19.570683 52 : 4363, 4137
7227 20:00:19.573200 56 : 4252, 4027
7228 20:00:19.573765 60 : 4361, 4137
7229 20:00:19.576690 64 : 4250, 4026
7230 20:00:19.577257 68 : 4250, 4027
7231 20:00:19.580070 72 : 4250, 4026
7232 20:00:19.580688 76 : 4250, 4027
7233 20:00:19.581064 80 : 4360, 4137
7234 20:00:19.583351 84 : 4250, 4027
7235 20:00:19.583911 88 : 4360, 4138
7236 20:00:19.586632 92 : 4250, 4026
7237 20:00:19.587196 96 : 4250, 4027
7238 20:00:19.590095 100 : 4250, 2311
7239 20:00:19.590659 104 : 4250, 0
7240 20:00:19.593086 108 : 4250, 0
7241 20:00:19.593554 112 : 4253, 0
7242 20:00:19.593936 116 : 4252, 0
7243 20:00:19.596638 120 : 4250, 0
7244 20:00:19.597212 124 : 4252, 0
7245 20:00:19.597590 128 : 4252, 0
7246 20:00:19.599843 132 : 4363, 0
7247 20:00:19.600475 136 : 4250, 0
7248 20:00:19.603228 140 : 4363, 0
7249 20:00:19.603791 144 : 4361, 0
7250 20:00:19.604171 148 : 4361, 0
7251 20:00:19.606324 152 : 4255, 0
7252 20:00:19.606791 156 : 4250, 0
7253 20:00:19.609598 160 : 4250, 0
7254 20:00:19.610164 164 : 4249, 0
7255 20:00:19.610542 168 : 4250, 0
7256 20:00:19.612894 172 : 4249, 0
7257 20:00:19.613363 176 : 4252, 0
7258 20:00:19.616249 180 : 4250, 0
7259 20:00:19.616714 184 : 4250, 0
7260 20:00:19.617092 188 : 4252, 0
7261 20:00:19.619908 192 : 4250, 0
7262 20:00:19.620535 196 : 4360, 0
7263 20:00:19.620917 200 : 4360, 0
7264 20:00:19.623055 204 : 4250, 0
7265 20:00:19.623584 208 : 4250, 0
7266 20:00:19.626247 212 : 4250, 0
7267 20:00:19.626717 216 : 4252, 0
7268 20:00:19.627092 220 : 4250, 612
7269 20:00:19.629845 224 : 4250, 3994
7270 20:00:19.630409 228 : 4250, 4027
7271 20:00:19.632772 232 : 4361, 4138
7272 20:00:19.633241 236 : 4360, 4137
7273 20:00:19.636104 240 : 4247, 4024
7274 20:00:19.636558 244 : 4360, 4138
7275 20:00:19.639330 248 : 4360, 4137
7276 20:00:19.639710 252 : 4250, 4027
7277 20:00:19.642968 256 : 4250, 4027
7278 20:00:19.643531 260 : 4250, 4027
7279 20:00:19.646041 264 : 4249, 4027
7280 20:00:19.646510 268 : 4250, 4027
7281 20:00:19.649558 272 : 4250, 4027
7282 20:00:19.650144 276 : 4250, 4027
7283 20:00:19.650578 280 : 4249, 4027
7284 20:00:19.652729 284 : 4360, 4137
7285 20:00:19.653196 288 : 4363, 4140
7286 20:00:19.656503 292 : 4250, 4027
7287 20:00:19.657087 296 : 4360, 4138
7288 20:00:19.659547 300 : 4361, 4137
7289 20:00:19.660116 304 : 4250, 4026
7290 20:00:19.662654 308 : 4253, 4029
7291 20:00:19.663226 312 : 4250, 4027
7292 20:00:19.666169 316 : 4251, 4027
7293 20:00:19.666743 320 : 4250, 4027
7294 20:00:19.669118 324 : 4250, 4027
7295 20:00:19.669587 328 : 4253, 4029
7296 20:00:19.672558 332 : 4251, 4027
7297 20:00:19.673134 336 : 4360, 4094
7298 20:00:19.676233 340 : 4361, 2167
7299 20:00:19.676815
7300 20:00:19.677187 MIOCK jitter meter ch=0
7301 20:00:19.677527
7302 20:00:19.679018 1T = (340-104) = 236 dly cells
7303 20:00:19.685953 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7304 20:00:19.686521 ==
7305 20:00:19.689471 Dram Type= 6, Freq= 0, CH_0, rank 0
7306 20:00:19.692660 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7307 20:00:19.693234 ==
7308 20:00:19.699296 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7309 20:00:19.702336 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7310 20:00:19.706207 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7311 20:00:19.712205 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7312 20:00:19.721205 [CA 0] Center 42 (12~73) winsize 62
7313 20:00:19.724373 [CA 1] Center 42 (12~73) winsize 62
7314 20:00:19.727644 [CA 2] Center 39 (9~69) winsize 61
7315 20:00:19.731879 [CA 3] Center 38 (9~68) winsize 60
7316 20:00:19.734275 [CA 4] Center 37 (7~67) winsize 61
7317 20:00:19.737750 [CA 5] Center 36 (6~66) winsize 61
7318 20:00:19.738216
7319 20:00:19.740972 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7320 20:00:19.741506
7321 20:00:19.744452 [CATrainingPosCal] consider 1 rank data
7322 20:00:19.747752 u2DelayCellTimex100 = 275/100 ps
7323 20:00:19.750954 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7324 20:00:19.757434 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7325 20:00:19.760769 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7326 20:00:19.764325 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7327 20:00:19.767517 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7328 20:00:19.771077 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7329 20:00:19.771635
7330 20:00:19.774259 CA PerBit enable=1, Macro0, CA PI delay=36
7331 20:00:19.774722
7332 20:00:19.777268 [CBTSetCACLKResult] CA Dly = 36
7333 20:00:19.780856 CS Dly: 10 (0~41)
7334 20:00:19.784363 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7335 20:00:19.787613 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7336 20:00:19.788222 ==
7337 20:00:19.790983 Dram Type= 6, Freq= 0, CH_0, rank 1
7338 20:00:19.794393 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7339 20:00:19.797495 ==
7340 20:00:19.801020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7341 20:00:19.804048 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7342 20:00:19.810938 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7343 20:00:19.817463 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7344 20:00:19.824007 [CA 0] Center 42 (12~73) winsize 62
7345 20:00:19.827116 [CA 1] Center 42 (12~73) winsize 62
7346 20:00:19.830534 [CA 2] Center 38 (9~68) winsize 60
7347 20:00:19.833783 [CA 3] Center 37 (8~67) winsize 60
7348 20:00:19.837094 [CA 4] Center 36 (6~66) winsize 61
7349 20:00:19.840410 [CA 5] Center 36 (6~66) winsize 61
7350 20:00:19.840962
7351 20:00:19.843910 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7352 20:00:19.844567
7353 20:00:19.847102 [CATrainingPosCal] consider 2 rank data
7354 20:00:19.850485 u2DelayCellTimex100 = 275/100 ps
7355 20:00:19.853922 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7356 20:00:19.860506 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7357 20:00:19.863730 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7358 20:00:19.867037 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7359 20:00:19.870253 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7360 20:00:19.873408 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7361 20:00:19.873868
7362 20:00:19.876674 CA PerBit enable=1, Macro0, CA PI delay=36
7363 20:00:19.877136
7364 20:00:19.879958 [CBTSetCACLKResult] CA Dly = 36
7365 20:00:19.883358 CS Dly: 10 (0~42)
7366 20:00:19.886637 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7367 20:00:19.890062 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7368 20:00:19.890524
7369 20:00:19.893643 ----->DramcWriteLeveling(PI) begin...
7370 20:00:19.894214 ==
7371 20:00:19.896929 Dram Type= 6, Freq= 0, CH_0, rank 0
7372 20:00:19.903396 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7373 20:00:19.903963 ==
7374 20:00:19.906838 Write leveling (Byte 0): 30 => 30
7375 20:00:19.907401 Write leveling (Byte 1): 26 => 26
7376 20:00:19.909825 DramcWriteLeveling(PI) end<-----
7377 20:00:19.910282
7378 20:00:19.913141 ==
7379 20:00:19.913710 Dram Type= 6, Freq= 0, CH_0, rank 0
7380 20:00:19.919874 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7381 20:00:19.920480 ==
7382 20:00:19.923186 [Gating] SW mode calibration
7383 20:00:19.929579 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7384 20:00:19.933015 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7385 20:00:19.939735 0 12 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7386 20:00:19.943223 0 12 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7387 20:00:19.946615 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7388 20:00:19.952897 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7389 20:00:19.956422 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7390 20:00:19.959639 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7391 20:00:19.966446 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7392 20:00:19.969507 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7393 20:00:19.972924 0 13 0 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 1)
7394 20:00:19.979367 0 13 4 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
7395 20:00:19.982393 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7396 20:00:19.985795 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7397 20:00:19.992782 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7398 20:00:19.996044 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7399 20:00:19.999131 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7400 20:00:20.006255 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7401 20:00:20.009524 0 14 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7402 20:00:20.012315 0 14 4 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
7403 20:00:20.019054 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7404 20:00:20.022408 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7405 20:00:20.025405 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7406 20:00:20.032561 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7407 20:00:20.035553 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7408 20:00:20.039043 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7409 20:00:20.045450 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7410 20:00:20.049170 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7411 20:00:20.052107 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 20:00:20.059084 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 20:00:20.062164 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 20:00:20.065588 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 20:00:20.072170 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 20:00:20.075296 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 20:00:20.078896 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 20:00:20.082245 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 20:00:20.088495 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 20:00:20.092461 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 20:00:20.095279 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 20:00:20.101681 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7423 20:00:20.105216 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7424 20:00:20.108574 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7425 20:00:20.115133 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7426 20:00:20.118415 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7427 20:00:20.121731 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7428 20:00:20.125183 Total UI for P1: 0, mck2ui 16
7429 20:00:20.128080 best dqsien dly found for B0: ( 1, 1, 0)
7430 20:00:20.134712 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7431 20:00:20.138373 Total UI for P1: 0, mck2ui 16
7432 20:00:20.141572 best dqsien dly found for B1: ( 1, 1, 6)
7433 20:00:20.144778 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7434 20:00:20.148328 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7435 20:00:20.148830
7436 20:00:20.151585 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7437 20:00:20.155016 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7438 20:00:20.158096 [Gating] SW calibration Done
7439 20:00:20.158555 ==
7440 20:00:20.161723 Dram Type= 6, Freq= 0, CH_0, rank 0
7441 20:00:20.164918 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7442 20:00:20.165382 ==
7443 20:00:20.168032 RX Vref Scan: 0
7444 20:00:20.168670
7445 20:00:20.169072 RX Vref 0 -> 0, step: 1
7446 20:00:20.169417
7447 20:00:20.171595 RX Delay 0 -> 252, step: 8
7448 20:00:20.174687 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7449 20:00:20.181336 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7450 20:00:20.184711 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7451 20:00:20.188324 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7452 20:00:20.191396 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7453 20:00:20.194671 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7454 20:00:20.201322 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7455 20:00:20.204777 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7456 20:00:20.208042 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7457 20:00:20.211224 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7458 20:00:20.214705 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7459 20:00:20.221009 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7460 20:00:20.224630 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7461 20:00:20.227631 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7462 20:00:20.230874 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7463 20:00:20.237283 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7464 20:00:20.237743 ==
7465 20:00:20.240992 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 20:00:20.244436 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7467 20:00:20.244992 ==
7468 20:00:20.245359 DQS Delay:
7469 20:00:20.247547 DQS0 = 0, DQS1 = 0
7470 20:00:20.248100 DQM Delay:
7471 20:00:20.250979 DQM0 = 130, DQM1 = 124
7472 20:00:20.251580 DQ Delay:
7473 20:00:20.254298 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7474 20:00:20.257603 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7475 20:00:20.261086 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7476 20:00:20.264362 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7477 20:00:20.264916
7478 20:00:20.265285
7479 20:00:20.267313 ==
7480 20:00:20.267864 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 20:00:20.273794 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7482 20:00:20.274336 ==
7483 20:00:20.274702
7484 20:00:20.275044
7485 20:00:20.277177 TX Vref Scan disable
7486 20:00:20.277670 == TX Byte 0 ==
7487 20:00:20.280543 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7488 20:00:20.287437 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7489 20:00:20.287992 == TX Byte 1 ==
7490 20:00:20.290667 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7491 20:00:20.297165 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7492 20:00:20.297726 ==
7493 20:00:20.300547 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 20:00:20.303662 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7495 20:00:20.304280 ==
7496 20:00:20.317021
7497 20:00:20.320345 TX Vref early break, caculate TX vref
7498 20:00:20.323533 TX Vref=16, minBit 8, minWin=22, winSum=371
7499 20:00:20.326888 TX Vref=18, minBit 8, minWin=22, winSum=380
7500 20:00:20.330102 TX Vref=20, minBit 8, minWin=22, winSum=388
7501 20:00:20.333605 TX Vref=22, minBit 8, minWin=22, winSum=394
7502 20:00:20.336556 TX Vref=24, minBit 8, minWin=24, winSum=402
7503 20:00:20.343616 TX Vref=26, minBit 0, minWin=25, winSum=412
7504 20:00:20.347001 TX Vref=28, minBit 0, minWin=25, winSum=415
7505 20:00:20.350338 TX Vref=30, minBit 8, minWin=24, winSum=410
7506 20:00:20.353430 TX Vref=32, minBit 1, minWin=24, winSum=399
7507 20:00:20.357034 TX Vref=34, minBit 6, minWin=23, winSum=393
7508 20:00:20.363629 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
7509 20:00:20.364225
7510 20:00:20.366868 Final TX Range 0 Vref 28
7511 20:00:20.367424
7512 20:00:20.367791 ==
7513 20:00:20.370123 Dram Type= 6, Freq= 0, CH_0, rank 0
7514 20:00:20.373245 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7515 20:00:20.373805 ==
7516 20:00:20.374175
7517 20:00:20.374514
7518 20:00:20.376758 TX Vref Scan disable
7519 20:00:20.383361 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7520 20:00:20.383920 == TX Byte 0 ==
7521 20:00:20.386497 u2DelayCellOfst[0]=10 cells (3 PI)
7522 20:00:20.390077 u2DelayCellOfst[1]=17 cells (5 PI)
7523 20:00:20.393339 u2DelayCellOfst[2]=14 cells (4 PI)
7524 20:00:20.396631 u2DelayCellOfst[3]=14 cells (4 PI)
7525 20:00:20.399884 u2DelayCellOfst[4]=10 cells (3 PI)
7526 20:00:20.403120 u2DelayCellOfst[5]=0 cells (0 PI)
7527 20:00:20.406365 u2DelayCellOfst[6]=17 cells (5 PI)
7528 20:00:20.409914 u2DelayCellOfst[7]=17 cells (5 PI)
7529 20:00:20.413339 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7530 20:00:20.416402 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7531 20:00:20.419865 == TX Byte 1 ==
7532 20:00:20.423023 u2DelayCellOfst[8]=3 cells (1 PI)
7533 20:00:20.423576 u2DelayCellOfst[9]=0 cells (0 PI)
7534 20:00:20.426424 u2DelayCellOfst[10]=10 cells (3 PI)
7535 20:00:20.429478 u2DelayCellOfst[11]=3 cells (1 PI)
7536 20:00:20.433226 u2DelayCellOfst[12]=14 cells (4 PI)
7537 20:00:20.436140 u2DelayCellOfst[13]=14 cells (4 PI)
7538 20:00:20.439603 u2DelayCellOfst[14]=17 cells (5 PI)
7539 20:00:20.442906 u2DelayCellOfst[15]=14 cells (4 PI)
7540 20:00:20.446287 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7541 20:00:20.452529 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7542 20:00:20.453078 DramC Write-DBI on
7543 20:00:20.453446 ==
7544 20:00:20.455922 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 20:00:20.462715 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7546 20:00:20.463183 ==
7547 20:00:20.463554
7548 20:00:20.463965
7549 20:00:20.464348 TX Vref Scan disable
7550 20:00:20.466455 == TX Byte 0 ==
7551 20:00:20.469670 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7552 20:00:20.473259 == TX Byte 1 ==
7553 20:00:20.476629 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7554 20:00:20.479416 DramC Write-DBI off
7555 20:00:20.479876
7556 20:00:20.480295 [DATLAT]
7557 20:00:20.480648 Freq=1600, CH0 RK0
7558 20:00:20.480982
7559 20:00:20.482886 DATLAT Default: 0xf
7560 20:00:20.483348 0, 0xFFFF, sum = 0
7561 20:00:20.486515 1, 0xFFFF, sum = 0
7562 20:00:20.489634 2, 0xFFFF, sum = 0
7563 20:00:20.490103 3, 0xFFFF, sum = 0
7564 20:00:20.492949 4, 0xFFFF, sum = 0
7565 20:00:20.493507 5, 0xFFFF, sum = 0
7566 20:00:20.496254 6, 0xFFFF, sum = 0
7567 20:00:20.496747 7, 0xFFFF, sum = 0
7568 20:00:20.499639 8, 0xFFFF, sum = 0
7569 20:00:20.500228 9, 0xFFFF, sum = 0
7570 20:00:20.502906 10, 0xFFFF, sum = 0
7571 20:00:20.503473 11, 0xFFFF, sum = 0
7572 20:00:20.506110 12, 0xFFF, sum = 0
7573 20:00:20.506579 13, 0x0, sum = 1
7574 20:00:20.509830 14, 0x0, sum = 2
7575 20:00:20.510402 15, 0x0, sum = 3
7576 20:00:20.512881 16, 0x0, sum = 4
7577 20:00:20.513347 best_step = 14
7578 20:00:20.513716
7579 20:00:20.514057 ==
7580 20:00:20.516458 Dram Type= 6, Freq= 0, CH_0, rank 0
7581 20:00:20.519584 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7582 20:00:20.522766 ==
7583 20:00:20.523323 RX Vref Scan: 1
7584 20:00:20.523694
7585 20:00:20.526276 Set Vref Range= 24 -> 127
7586 20:00:20.526832
7587 20:00:20.529176 RX Vref 24 -> 127, step: 1
7588 20:00:20.529643
7589 20:00:20.530014 RX Delay 11 -> 252, step: 4
7590 20:00:20.530362
7591 20:00:20.532748 Set Vref, RX VrefLevel [Byte0]: 24
7592 20:00:20.535861 [Byte1]: 24
7593 20:00:20.539897
7594 20:00:20.540509 Set Vref, RX VrefLevel [Byte0]: 25
7595 20:00:20.543136 [Byte1]: 25
7596 20:00:20.547329
7597 20:00:20.547883 Set Vref, RX VrefLevel [Byte0]: 26
7598 20:00:20.550699 [Byte1]: 26
7599 20:00:20.554963
7600 20:00:20.555519 Set Vref, RX VrefLevel [Byte0]: 27
7601 20:00:20.558036 [Byte1]: 27
7602 20:00:20.562529
7603 20:00:20.563106 Set Vref, RX VrefLevel [Byte0]: 28
7604 20:00:20.565881 [Byte1]: 28
7605 20:00:20.570397
7606 20:00:20.570954 Set Vref, RX VrefLevel [Byte0]: 29
7607 20:00:20.573474 [Byte1]: 29
7608 20:00:20.577926
7609 20:00:20.578485 Set Vref, RX VrefLevel [Byte0]: 30
7610 20:00:20.581329 [Byte1]: 30
7611 20:00:20.585293
7612 20:00:20.585851 Set Vref, RX VrefLevel [Byte0]: 31
7613 20:00:20.588886 [Byte1]: 31
7614 20:00:20.593087
7615 20:00:20.593667 Set Vref, RX VrefLevel [Byte0]: 32
7616 20:00:20.596539 [Byte1]: 32
7617 20:00:20.600538
7618 20:00:20.601154 Set Vref, RX VrefLevel [Byte0]: 33
7619 20:00:20.603987 [Byte1]: 33
7620 20:00:20.608604
7621 20:00:20.609168 Set Vref, RX VrefLevel [Byte0]: 34
7622 20:00:20.611638 [Byte1]: 34
7623 20:00:20.615913
7624 20:00:20.616519 Set Vref, RX VrefLevel [Byte0]: 35
7625 20:00:20.619913 [Byte1]: 35
7626 20:00:20.623616
7627 20:00:20.624213 Set Vref, RX VrefLevel [Byte0]: 36
7628 20:00:20.626642 [Byte1]: 36
7629 20:00:20.631028
7630 20:00:20.631492 Set Vref, RX VrefLevel [Byte0]: 37
7631 20:00:20.634211 [Byte1]: 37
7632 20:00:20.639138
7633 20:00:20.639700 Set Vref, RX VrefLevel [Byte0]: 38
7634 20:00:20.641856 [Byte1]: 38
7635 20:00:20.646387
7636 20:00:20.646949 Set Vref, RX VrefLevel [Byte0]: 39
7637 20:00:20.649591 [Byte1]: 39
7638 20:00:20.654109
7639 20:00:20.654670 Set Vref, RX VrefLevel [Byte0]: 40
7640 20:00:20.657702 [Byte1]: 40
7641 20:00:20.661495
7642 20:00:20.661953 Set Vref, RX VrefLevel [Byte0]: 41
7643 20:00:20.664758 [Byte1]: 41
7644 20:00:20.669165
7645 20:00:20.669720 Set Vref, RX VrefLevel [Byte0]: 42
7646 20:00:20.672397 [Byte1]: 42
7647 20:00:20.676943
7648 20:00:20.677495 Set Vref, RX VrefLevel [Byte0]: 43
7649 20:00:20.680138 [Byte1]: 43
7650 20:00:20.684567
7651 20:00:20.685158 Set Vref, RX VrefLevel [Byte0]: 44
7652 20:00:20.687491 [Byte1]: 44
7653 20:00:20.692008
7654 20:00:20.692676 Set Vref, RX VrefLevel [Byte0]: 45
7655 20:00:20.695608 [Byte1]: 45
7656 20:00:20.699561
7657 20:00:20.700107 Set Vref, RX VrefLevel [Byte0]: 46
7658 20:00:20.703144 [Byte1]: 46
7659 20:00:20.707546
7660 20:00:20.708100 Set Vref, RX VrefLevel [Byte0]: 47
7661 20:00:20.710530 [Byte1]: 47
7662 20:00:20.714939
7663 20:00:20.715488 Set Vref, RX VrefLevel [Byte0]: 48
7664 20:00:20.718672 [Byte1]: 48
7665 20:00:20.722409
7666 20:00:20.722968 Set Vref, RX VrefLevel [Byte0]: 49
7667 20:00:20.725436 [Byte1]: 49
7668 20:00:20.730013
7669 20:00:20.730806 Set Vref, RX VrefLevel [Byte0]: 50
7670 20:00:20.733456 [Byte1]: 50
7671 20:00:20.737892
7672 20:00:20.738449 Set Vref, RX VrefLevel [Byte0]: 51
7673 20:00:20.740778 [Byte1]: 51
7674 20:00:20.745167
7675 20:00:20.745731 Set Vref, RX VrefLevel [Byte0]: 52
7676 20:00:20.748398 [Byte1]: 52
7677 20:00:20.752840
7678 20:00:20.753369 Set Vref, RX VrefLevel [Byte0]: 53
7679 20:00:20.756119 [Byte1]: 53
7680 20:00:20.760387
7681 20:00:20.760859 Set Vref, RX VrefLevel [Byte0]: 54
7682 20:00:20.763652 [Byte1]: 54
7683 20:00:20.768251
7684 20:00:20.768824 Set Vref, RX VrefLevel [Byte0]: 55
7685 20:00:20.771607 [Byte1]: 55
7686 20:00:20.775776
7687 20:00:20.776288 Set Vref, RX VrefLevel [Byte0]: 56
7688 20:00:20.779166 [Byte1]: 56
7689 20:00:20.783887
7690 20:00:20.784503 Set Vref, RX VrefLevel [Byte0]: 57
7691 20:00:20.787574 [Byte1]: 57
7692 20:00:20.790867
7693 20:00:20.791336 Set Vref, RX VrefLevel [Byte0]: 58
7694 20:00:20.794317 [Byte1]: 58
7695 20:00:20.798544
7696 20:00:20.799117 Set Vref, RX VrefLevel [Byte0]: 59
7697 20:00:20.801992 [Byte1]: 59
7698 20:00:20.806189
7699 20:00:20.806652 Set Vref, RX VrefLevel [Byte0]: 60
7700 20:00:20.809574 [Byte1]: 60
7701 20:00:20.813895
7702 20:00:20.814457 Set Vref, RX VrefLevel [Byte0]: 61
7703 20:00:20.817440 [Byte1]: 61
7704 20:00:20.821563
7705 20:00:20.822124 Set Vref, RX VrefLevel [Byte0]: 62
7706 20:00:20.824867 [Byte1]: 62
7707 20:00:20.829137
7708 20:00:20.829698 Set Vref, RX VrefLevel [Byte0]: 63
7709 20:00:20.832437 [Byte1]: 63
7710 20:00:20.836565
7711 20:00:20.837178 Set Vref, RX VrefLevel [Byte0]: 64
7712 20:00:20.839773 [Byte1]: 64
7713 20:00:20.844362
7714 20:00:20.844919 Set Vref, RX VrefLevel [Byte0]: 65
7715 20:00:20.847659 [Byte1]: 65
7716 20:00:20.852335
7717 20:00:20.852945 Set Vref, RX VrefLevel [Byte0]: 66
7718 20:00:20.855149 [Byte1]: 66
7719 20:00:20.859522
7720 20:00:20.860121 Set Vref, RX VrefLevel [Byte0]: 67
7721 20:00:20.862708 [Byte1]: 67
7722 20:00:20.867050
7723 20:00:20.867606 Set Vref, RX VrefLevel [Byte0]: 68
7724 20:00:20.870299 [Byte1]: 68
7725 20:00:20.875021
7726 20:00:20.875581 Set Vref, RX VrefLevel [Byte0]: 69
7727 20:00:20.877987 [Byte1]: 69
7728 20:00:20.882571
7729 20:00:20.883166 Set Vref, RX VrefLevel [Byte0]: 70
7730 20:00:20.885452 [Byte1]: 70
7731 20:00:20.889713
7732 20:00:20.890188 Set Vref, RX VrefLevel [Byte0]: 71
7733 20:00:20.893251 [Byte1]: 71
7734 20:00:20.897487
7735 20:00:20.898059 Final RX Vref Byte 0 = 52 to rank0
7736 20:00:20.901071 Final RX Vref Byte 1 = 55 to rank0
7737 20:00:20.904126 Final RX Vref Byte 0 = 52 to rank1
7738 20:00:20.907286 Final RX Vref Byte 1 = 55 to rank1==
7739 20:00:20.910742 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 20:00:20.917317 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7741 20:00:20.917872 ==
7742 20:00:20.918240 DQS Delay:
7743 20:00:20.920520 DQS0 = 0, DQS1 = 0
7744 20:00:20.920980 DQM Delay:
7745 20:00:20.921341 DQM0 = 126, DQM1 = 121
7746 20:00:20.924268 DQ Delay:
7747 20:00:20.927340 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7748 20:00:20.930891 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7749 20:00:20.933650 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7750 20:00:20.936914 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7751 20:00:20.937414
7752 20:00:20.937782
7753 20:00:20.938122
7754 20:00:20.940736 [DramC_TX_OE_Calibration] TA2
7755 20:00:20.943748 Original DQ_B0 (3 6) =30, OEN = 27
7756 20:00:20.947427 Original DQ_B1 (3 6) =30, OEN = 27
7757 20:00:20.950722 24, 0x0, End_B0=24 End_B1=24
7758 20:00:20.951285 25, 0x0, End_B0=25 End_B1=25
7759 20:00:20.953611 26, 0x0, End_B0=26 End_B1=26
7760 20:00:20.957116 27, 0x0, End_B0=27 End_B1=27
7761 20:00:20.960634 28, 0x0, End_B0=28 End_B1=28
7762 20:00:20.963812 29, 0x0, End_B0=29 End_B1=29
7763 20:00:20.964415 30, 0x0, End_B0=30 End_B1=30
7764 20:00:20.967391 31, 0x4141, End_B0=30 End_B1=30
7765 20:00:20.970373 Byte0 end_step=30 best_step=27
7766 20:00:20.973580 Byte1 end_step=30 best_step=27
7767 20:00:20.977062 Byte0 TX OE(2T, 0.5T) = (3, 3)
7768 20:00:20.980154 Byte1 TX OE(2T, 0.5T) = (3, 3)
7769 20:00:20.980742
7770 20:00:20.981109
7771 20:00:20.986865 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7772 20:00:20.990422 CH0 RK0: MR19=303, MR18=1E1E
7773 20:00:20.996834 CH0_RK0: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
7774 20:00:20.997416
7775 20:00:21.000113 ----->DramcWriteLeveling(PI) begin...
7776 20:00:21.000745 ==
7777 20:00:21.003079 Dram Type= 6, Freq= 0, CH_0, rank 1
7778 20:00:21.006859 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7779 20:00:21.007461 ==
7780 20:00:21.009820 Write leveling (Byte 0): 30 => 30
7781 20:00:21.013413 Write leveling (Byte 1): 24 => 24
7782 20:00:21.016859 DramcWriteLeveling(PI) end<-----
7783 20:00:21.017428
7784 20:00:21.017918 ==
7785 20:00:21.020029 Dram Type= 6, Freq= 0, CH_0, rank 1
7786 20:00:21.023515 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7787 20:00:21.024094 ==
7788 20:00:21.026724 [Gating] SW mode calibration
7789 20:00:21.033052 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7790 20:00:21.039624 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7791 20:00:21.043295 0 12 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
7792 20:00:21.049841 0 12 4 | B1->B0 | 2625 3434 | 1 1 | (0 0) (1 1)
7793 20:00:21.052805 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7794 20:00:21.056339 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7795 20:00:21.063011 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7796 20:00:21.066627 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7797 20:00:21.069814 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7798 20:00:21.076248 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7799 20:00:21.079522 0 13 0 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
7800 20:00:21.083346 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
7801 20:00:21.086545 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7802 20:00:21.093091 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7803 20:00:21.096120 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7804 20:00:21.099637 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7805 20:00:21.106144 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7806 20:00:21.109826 0 13 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7807 20:00:21.113150 0 14 0 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7808 20:00:21.119633 0 14 4 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7809 20:00:21.122972 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7810 20:00:21.126435 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7811 20:00:21.132799 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7812 20:00:21.136170 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7813 20:00:21.139561 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7814 20:00:21.146259 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7815 20:00:21.149752 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7816 20:00:21.152875 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7817 20:00:21.159557 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 20:00:21.163065 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 20:00:21.166058 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 20:00:21.173084 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 20:00:21.176007 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 20:00:21.179148 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 20:00:21.185971 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 20:00:21.188969 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 20:00:21.192655 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 20:00:21.199348 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7827 20:00:21.202484 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7828 20:00:21.205524 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7829 20:00:21.212602 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7830 20:00:21.215895 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7831 20:00:21.219184 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7832 20:00:21.225768 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7833 20:00:21.229147 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7834 20:00:21.232264 Total UI for P1: 0, mck2ui 16
7835 20:00:21.235429 best dqsien dly found for B0: ( 1, 1, 0)
7836 20:00:21.239183 Total UI for P1: 0, mck2ui 16
7837 20:00:21.242246 best dqsien dly found for B1: ( 1, 1, 4)
7838 20:00:21.245533 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7839 20:00:21.248796 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7840 20:00:21.249255
7841 20:00:21.252257 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7842 20:00:21.255439 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7843 20:00:21.258847 [Gating] SW calibration Done
7844 20:00:21.259460 ==
7845 20:00:21.262368 Dram Type= 6, Freq= 0, CH_0, rank 1
7846 20:00:21.265325 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7847 20:00:21.265789 ==
7848 20:00:21.268703 RX Vref Scan: 0
7849 20:00:21.269160
7850 20:00:21.269528 RX Vref 0 -> 0, step: 1
7851 20:00:21.272071
7852 20:00:21.272567 RX Delay 0 -> 252, step: 8
7853 20:00:21.275322 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7854 20:00:21.281964 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7855 20:00:21.285711 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7856 20:00:21.288613 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7857 20:00:21.292015 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7858 20:00:21.295476 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7859 20:00:21.302026 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7860 20:00:21.305122 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7861 20:00:21.308722 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7862 20:00:21.312138 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7863 20:00:21.315548 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7864 20:00:21.322083 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7865 20:00:21.325035 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7866 20:00:21.328647 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7867 20:00:21.331957 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7868 20:00:21.338449 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7869 20:00:21.338917 ==
7870 20:00:21.341768 Dram Type= 6, Freq= 0, CH_0, rank 1
7871 20:00:21.344908 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7872 20:00:21.345373 ==
7873 20:00:21.345735 DQS Delay:
7874 20:00:21.348107 DQS0 = 0, DQS1 = 0
7875 20:00:21.348606 DQM Delay:
7876 20:00:21.351807 DQM0 = 131, DQM1 = 123
7877 20:00:21.352408 DQ Delay:
7878 20:00:21.354903 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7879 20:00:21.358597 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7880 20:00:21.361612 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7881 20:00:21.364735 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7882 20:00:21.365192
7883 20:00:21.365580
7884 20:00:21.368448 ==
7885 20:00:21.371640 Dram Type= 6, Freq= 0, CH_0, rank 1
7886 20:00:21.374995 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7887 20:00:21.375556 ==
7888 20:00:21.375925
7889 20:00:21.376302
7890 20:00:21.378472 TX Vref Scan disable
7891 20:00:21.379021 == TX Byte 0 ==
7892 20:00:21.381447 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7893 20:00:21.388396 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7894 20:00:21.388958 == TX Byte 1 ==
7895 20:00:21.391559 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7896 20:00:21.398243 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7897 20:00:21.398800 ==
7898 20:00:21.401876 Dram Type= 6, Freq= 0, CH_0, rank 1
7899 20:00:21.405079 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7900 20:00:21.405655 ==
7901 20:00:21.418469
7902 20:00:21.421736 TX Vref early break, caculate TX vref
7903 20:00:21.424893 TX Vref=16, minBit 7, minWin=22, winSum=372
7904 20:00:21.428546 TX Vref=18, minBit 0, minWin=23, winSum=381
7905 20:00:21.431631 TX Vref=20, minBit 1, minWin=22, winSum=387
7906 20:00:21.434729 TX Vref=22, minBit 1, minWin=24, winSum=399
7907 20:00:21.438137 TX Vref=24, minBit 1, minWin=24, winSum=408
7908 20:00:21.444610 TX Vref=26, minBit 1, minWin=25, winSum=414
7909 20:00:21.448062 TX Vref=28, minBit 1, minWin=25, winSum=416
7910 20:00:21.451598 TX Vref=30, minBit 0, minWin=25, winSum=411
7911 20:00:21.454463 TX Vref=32, minBit 0, minWin=25, winSum=406
7912 20:00:21.458202 TX Vref=34, minBit 8, minWin=23, winSum=392
7913 20:00:21.464751 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 28
7914 20:00:21.465317
7915 20:00:21.467795 Final TX Range 0 Vref 28
7916 20:00:21.468416
7917 20:00:21.468795 ==
7918 20:00:21.471283 Dram Type= 6, Freq= 0, CH_0, rank 1
7919 20:00:21.474131 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7920 20:00:21.474598 ==
7921 20:00:21.474966
7922 20:00:21.475306
7923 20:00:21.477640 TX Vref Scan disable
7924 20:00:21.484819 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7925 20:00:21.485387 == TX Byte 0 ==
7926 20:00:21.487907 u2DelayCellOfst[0]=10 cells (3 PI)
7927 20:00:21.491157 u2DelayCellOfst[1]=14 cells (4 PI)
7928 20:00:21.494424 u2DelayCellOfst[2]=10 cells (3 PI)
7929 20:00:21.497745 u2DelayCellOfst[3]=10 cells (3 PI)
7930 20:00:21.500889 u2DelayCellOfst[4]=7 cells (2 PI)
7931 20:00:21.504446 u2DelayCellOfst[5]=0 cells (0 PI)
7932 20:00:21.508003 u2DelayCellOfst[6]=14 cells (4 PI)
7933 20:00:21.511023 u2DelayCellOfst[7]=14 cells (4 PI)
7934 20:00:21.514507 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7935 20:00:21.517595 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7936 20:00:21.521019 == TX Byte 1 ==
7937 20:00:21.523912 u2DelayCellOfst[8]=3 cells (1 PI)
7938 20:00:21.524410 u2DelayCellOfst[9]=0 cells (0 PI)
7939 20:00:21.527585 u2DelayCellOfst[10]=10 cells (3 PI)
7940 20:00:21.530999 u2DelayCellOfst[11]=3 cells (1 PI)
7941 20:00:21.533895 u2DelayCellOfst[12]=14 cells (4 PI)
7942 20:00:21.537754 u2DelayCellOfst[13]=17 cells (5 PI)
7943 20:00:21.540695 u2DelayCellOfst[14]=21 cells (6 PI)
7944 20:00:21.544031 u2DelayCellOfst[15]=14 cells (4 PI)
7945 20:00:21.547548 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
7946 20:00:21.553966 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7947 20:00:21.554526 DramC Write-DBI on
7948 20:00:21.555013 ==
7949 20:00:21.557485 Dram Type= 6, Freq= 0, CH_0, rank 1
7950 20:00:21.564249 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7951 20:00:21.564826 ==
7952 20:00:21.565309
7953 20:00:21.565762
7954 20:00:21.566204 TX Vref Scan disable
7955 20:00:21.567580 == TX Byte 0 ==
7956 20:00:21.571028 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7957 20:00:21.575001 == TX Byte 1 ==
7958 20:00:21.577672 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7959 20:00:21.580964 DramC Write-DBI off
7960 20:00:21.581443
7961 20:00:21.581918 [DATLAT]
7962 20:00:21.582372 Freq=1600, CH0 RK1
7963 20:00:21.582830
7964 20:00:21.584461 DATLAT Default: 0xe
7965 20:00:21.584933 0, 0xFFFF, sum = 0
7966 20:00:21.587696 1, 0xFFFF, sum = 0
7967 20:00:21.591208 2, 0xFFFF, sum = 0
7968 20:00:21.591791 3, 0xFFFF, sum = 0
7969 20:00:21.594463 4, 0xFFFF, sum = 0
7970 20:00:21.595044 5, 0xFFFF, sum = 0
7971 20:00:21.597807 6, 0xFFFF, sum = 0
7972 20:00:21.598401 7, 0xFFFF, sum = 0
7973 20:00:21.601002 8, 0xFFFF, sum = 0
7974 20:00:21.601582 9, 0xFFFF, sum = 0
7975 20:00:21.604350 10, 0xFFFF, sum = 0
7976 20:00:21.604922 11, 0xFFFF, sum = 0
7977 20:00:21.607656 12, 0x8FFF, sum = 0
7978 20:00:21.608292 13, 0x0, sum = 1
7979 20:00:21.611179 14, 0x0, sum = 2
7980 20:00:21.611756 15, 0x0, sum = 3
7981 20:00:21.614269 16, 0x0, sum = 4
7982 20:00:21.614751 best_step = 14
7983 20:00:21.615230
7984 20:00:21.615684 ==
7985 20:00:21.617366 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 20:00:21.620744 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7987 20:00:21.624142 ==
7988 20:00:21.624766 RX Vref Scan: 0
7989 20:00:21.625253
7990 20:00:21.627078 RX Vref 0 -> 0, step: 1
7991 20:00:21.627554
7992 20:00:21.630510 RX Delay 11 -> 252, step: 4
7993 20:00:21.633920 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7994 20:00:21.637215 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7995 20:00:21.640490 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7996 20:00:21.647043 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7997 20:00:21.650513 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7998 20:00:21.653597 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7999 20:00:21.656951 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8000 20:00:21.660323 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
8001 20:00:21.667239 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
8002 20:00:21.670369 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
8003 20:00:21.673601 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8004 20:00:21.677064 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8005 20:00:21.680571 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8006 20:00:21.687092 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8007 20:00:21.690194 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8008 20:00:21.693616 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8009 20:00:21.694193 ==
8010 20:00:21.696828 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 20:00:21.700328 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8012 20:00:21.703621 ==
8013 20:00:21.704228 DQS Delay:
8014 20:00:21.704717 DQS0 = 0, DQS1 = 0
8015 20:00:21.706863 DQM Delay:
8016 20:00:21.707336 DQM0 = 128, DQM1 = 120
8017 20:00:21.709928 DQ Delay:
8018 20:00:21.713341 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
8019 20:00:21.716716 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
8020 20:00:21.720143 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8021 20:00:21.723570 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
8022 20:00:21.724141
8023 20:00:21.724677
8024 20:00:21.725130
8025 20:00:21.726421 [DramC_TX_OE_Calibration] TA2
8026 20:00:21.729751 Original DQ_B0 (3 6) =30, OEN = 27
8027 20:00:21.733346 Original DQ_B1 (3 6) =30, OEN = 27
8028 20:00:21.733925 24, 0x0, End_B0=24 End_B1=24
8029 20:00:21.736671 25, 0x0, End_B0=25 End_B1=25
8030 20:00:21.739705 26, 0x0, End_B0=26 End_B1=26
8031 20:00:21.743161 27, 0x0, End_B0=27 End_B1=27
8032 20:00:21.747025 28, 0x0, End_B0=28 End_B1=28
8033 20:00:21.747607 29, 0x0, End_B0=29 End_B1=29
8034 20:00:21.750373 30, 0x0, End_B0=30 End_B1=30
8035 20:00:21.753087 31, 0x4141, End_B0=30 End_B1=30
8036 20:00:21.756476 Byte0 end_step=30 best_step=27
8037 20:00:21.760155 Byte1 end_step=30 best_step=27
8038 20:00:21.763607 Byte0 TX OE(2T, 0.5T) = (3, 3)
8039 20:00:21.764227 Byte1 TX OE(2T, 0.5T) = (3, 3)
8040 20:00:21.764729
8041 20:00:21.765188
8042 20:00:21.773267 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8043 20:00:21.776790 CH0 RK1: MR19=303, MR18=1F1F
8044 20:00:21.783277 CH0_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8045 20:00:21.783851 [RxdqsGatingPostProcess] freq 1600
8046 20:00:21.789756 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8047 20:00:21.792943 Pre-setting of DQS Precalculation
8048 20:00:21.800324 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8049 20:00:21.800899 ==
8050 20:00:21.803085 Dram Type= 6, Freq= 0, CH_1, rank 0
8051 20:00:21.806246 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8052 20:00:21.806725 ==
8053 20:00:21.812964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8054 20:00:21.816286 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8055 20:00:21.819984 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8056 20:00:21.826267 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8057 20:00:21.833982 [CA 0] Center 41 (11~71) winsize 61
8058 20:00:21.837052 [CA 1] Center 41 (10~72) winsize 63
8059 20:00:21.840525 [CA 2] Center 37 (8~67) winsize 60
8060 20:00:21.843819 [CA 3] Center 36 (7~66) winsize 60
8061 20:00:21.847385 [CA 4] Center 34 (4~64) winsize 61
8062 20:00:21.850603 [CA 5] Center 34 (5~64) winsize 60
8063 20:00:21.851171
8064 20:00:21.853995 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8065 20:00:21.854571
8066 20:00:21.857167 [CATrainingPosCal] consider 1 rank data
8067 20:00:21.860564 u2DelayCellTimex100 = 275/100 ps
8068 20:00:21.863836 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8069 20:00:21.870835 CA1 delay=41 (10~72),Diff = 7 PI (24 cell)
8070 20:00:21.874059 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8071 20:00:21.877128 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8072 20:00:21.880439 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8073 20:00:21.883770 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8074 20:00:21.884395
8075 20:00:21.887210 CA PerBit enable=1, Macro0, CA PI delay=34
8076 20:00:21.887787
8077 20:00:21.890506 [CBTSetCACLKResult] CA Dly = 34
8078 20:00:21.893832 CS Dly: 8 (0~39)
8079 20:00:21.897006 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8080 20:00:21.900570 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8081 20:00:21.901145 ==
8082 20:00:21.903669 Dram Type= 6, Freq= 0, CH_1, rank 1
8083 20:00:21.906746 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8084 20:00:21.909941 ==
8085 20:00:21.913574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8086 20:00:21.916725 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8087 20:00:21.923421 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8088 20:00:21.930000 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8089 20:00:21.936355 [CA 0] Center 40 (10~70) winsize 61
8090 20:00:21.939692 [CA 1] Center 39 (9~70) winsize 62
8091 20:00:21.943484 [CA 2] Center 35 (6~65) winsize 60
8092 20:00:21.946107 [CA 3] Center 35 (6~64) winsize 59
8093 20:00:21.949488 [CA 4] Center 33 (3~63) winsize 61
8094 20:00:21.952948 [CA 5] Center 33 (3~63) winsize 61
8095 20:00:21.953503
8096 20:00:21.956144 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8097 20:00:21.956635
8098 20:00:21.959966 [CATrainingPosCal] consider 2 rank data
8099 20:00:21.962791 u2DelayCellTimex100 = 275/100 ps
8100 20:00:21.966247 CA0 delay=40 (11~70),Diff = 7 PI (24 cell)
8101 20:00:21.972765 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8102 20:00:21.976258 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8103 20:00:21.979069 CA3 delay=35 (7~64),Diff = 2 PI (7 cell)
8104 20:00:21.982832 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8105 20:00:21.986299 CA5 delay=34 (5~63),Diff = 1 PI (3 cell)
8106 20:00:21.986858
8107 20:00:21.989378 CA PerBit enable=1, Macro0, CA PI delay=33
8108 20:00:21.989934
8109 20:00:21.992550 [CBTSetCACLKResult] CA Dly = 33
8110 20:00:21.995637 CS Dly: 9 (0~41)
8111 20:00:21.999269 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8112 20:00:22.002594 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8113 20:00:22.003151
8114 20:00:22.005987 ----->DramcWriteLeveling(PI) begin...
8115 20:00:22.006548 ==
8116 20:00:22.009097 Dram Type= 6, Freq= 0, CH_1, rank 0
8117 20:00:22.015940 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8118 20:00:22.016536 ==
8119 20:00:22.018910 Write leveling (Byte 0): 23 => 23
8120 20:00:22.019365 Write leveling (Byte 1): 22 => 22
8121 20:00:22.022170 DramcWriteLeveling(PI) end<-----
8122 20:00:22.022625
8123 20:00:22.022986 ==
8124 20:00:22.025795 Dram Type= 6, Freq= 0, CH_1, rank 0
8125 20:00:22.032131 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8126 20:00:22.032644 ==
8127 20:00:22.035573 [Gating] SW mode calibration
8128 20:00:22.042475 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8129 20:00:22.045364 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8130 20:00:22.052437 0 12 0 | B1->B0 | 2b2b 3434 | 0 1 | (1 1) (1 1)
8131 20:00:22.055387 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8132 20:00:22.058899 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8133 20:00:22.065324 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8134 20:00:22.068592 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8135 20:00:22.072042 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8136 20:00:22.078721 0 12 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8137 20:00:22.081636 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8138 20:00:22.085156 0 13 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (1 0)
8139 20:00:22.091711 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8140 20:00:22.095200 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8141 20:00:22.098570 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8142 20:00:22.105090 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8143 20:00:22.108138 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8144 20:00:22.111339 0 13 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8145 20:00:22.118274 0 13 28 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
8146 20:00:22.121571 0 14 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
8147 20:00:22.124861 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8148 20:00:22.131622 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8149 20:00:22.134977 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8150 20:00:22.138331 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8151 20:00:22.144666 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8152 20:00:22.148341 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8153 20:00:22.151446 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8154 20:00:22.154892 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8155 20:00:22.161454 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8156 20:00:22.164579 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 20:00:22.167874 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 20:00:22.174590 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 20:00:22.177848 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 20:00:22.181197 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 20:00:22.187942 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 20:00:22.190931 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 20:00:22.194466 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 20:00:22.200934 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 20:00:22.204033 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 20:00:22.207485 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8167 20:00:22.214113 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8168 20:00:22.217240 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8169 20:00:22.220882 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8170 20:00:22.227362 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8171 20:00:22.231006 Total UI for P1: 0, mck2ui 16
8172 20:00:22.234025 best dqsien dly found for B0: ( 1, 0, 26)
8173 20:00:22.237218 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8174 20:00:22.240445 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8175 20:00:22.243930 Total UI for P1: 0, mck2ui 16
8176 20:00:22.247340 best dqsien dly found for B1: ( 1, 1, 0)
8177 20:00:22.250565 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8178 20:00:22.253990 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8179 20:00:22.254576
8180 20:00:22.260837 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8181 20:00:22.263860 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8182 20:00:22.267278 [Gating] SW calibration Done
8183 20:00:22.267887 ==
8184 20:00:22.270446 Dram Type= 6, Freq= 0, CH_1, rank 0
8185 20:00:22.273747 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8186 20:00:22.274310 ==
8187 20:00:22.274672 RX Vref Scan: 0
8188 20:00:22.275012
8189 20:00:22.276914 RX Vref 0 -> 0, step: 1
8190 20:00:22.277369
8191 20:00:22.280403 RX Delay 0 -> 252, step: 8
8192 20:00:22.283975 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8193 20:00:22.286913 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8194 20:00:22.293657 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8195 20:00:22.296803 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8196 20:00:22.300317 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8197 20:00:22.303213 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8198 20:00:22.307074 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8199 20:00:22.313423 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8200 20:00:22.316339 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8201 20:00:22.319824 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8202 20:00:22.323328 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8203 20:00:22.326756 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8204 20:00:22.333088 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8205 20:00:22.336471 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8206 20:00:22.339653 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8207 20:00:22.343067 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8208 20:00:22.343633 ==
8209 20:00:22.346035 Dram Type= 6, Freq= 0, CH_1, rank 0
8210 20:00:22.352836 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8211 20:00:22.353383 ==
8212 20:00:22.353755 DQS Delay:
8213 20:00:22.356009 DQS0 = 0, DQS1 = 0
8214 20:00:22.356530 DQM Delay:
8215 20:00:22.356899 DQM0 = 129, DQM1 = 125
8216 20:00:22.359509 DQ Delay:
8217 20:00:22.362739 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8218 20:00:22.366181 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8219 20:00:22.369487 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8220 20:00:22.372954 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8221 20:00:22.373416
8222 20:00:22.373782
8223 20:00:22.374115 ==
8224 20:00:22.376202 Dram Type= 6, Freq= 0, CH_1, rank 0
8225 20:00:22.383029 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8226 20:00:22.383595 ==
8227 20:00:22.383969
8228 20:00:22.384356
8229 20:00:22.384687 TX Vref Scan disable
8230 20:00:22.385836 == TX Byte 0 ==
8231 20:00:22.389542 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8232 20:00:22.392605 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8233 20:00:22.396344 == TX Byte 1 ==
8234 20:00:22.399617 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8235 20:00:22.405848 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8236 20:00:22.406404 ==
8237 20:00:22.409620 Dram Type= 6, Freq= 0, CH_1, rank 0
8238 20:00:22.412393 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8239 20:00:22.412856 ==
8240 20:00:22.424312
8241 20:00:22.427778 TX Vref early break, caculate TX vref
8242 20:00:22.430883 TX Vref=16, minBit 1, minWin=21, winSum=369
8243 20:00:22.434491 TX Vref=18, minBit 0, minWin=22, winSum=375
8244 20:00:22.437638 TX Vref=20, minBit 0, minWin=23, winSum=386
8245 20:00:22.440569 TX Vref=22, minBit 3, minWin=23, winSum=393
8246 20:00:22.443943 TX Vref=24, minBit 0, minWin=24, winSum=401
8247 20:00:22.450696 TX Vref=26, minBit 0, minWin=25, winSum=411
8248 20:00:22.454073 TX Vref=28, minBit 0, minWin=25, winSum=411
8249 20:00:22.457682 TX Vref=30, minBit 3, minWin=24, winSum=407
8250 20:00:22.460758 TX Vref=32, minBit 3, minWin=23, winSum=396
8251 20:00:22.463912 TX Vref=34, minBit 1, minWin=23, winSum=389
8252 20:00:22.470496 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 26
8253 20:00:22.471038
8254 20:00:22.474052 Final TX Range 0 Vref 26
8255 20:00:22.474618
8256 20:00:22.474989 ==
8257 20:00:22.477570 Dram Type= 6, Freq= 0, CH_1, rank 0
8258 20:00:22.480585 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8259 20:00:22.481145 ==
8260 20:00:22.481513
8261 20:00:22.481851
8262 20:00:22.484124 TX Vref Scan disable
8263 20:00:22.490468 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8264 20:00:22.491031 == TX Byte 0 ==
8265 20:00:22.493676 u2DelayCellOfst[0]=14 cells (4 PI)
8266 20:00:22.497006 u2DelayCellOfst[1]=10 cells (3 PI)
8267 20:00:22.500540 u2DelayCellOfst[2]=0 cells (0 PI)
8268 20:00:22.503741 u2DelayCellOfst[3]=7 cells (2 PI)
8269 20:00:22.507288 u2DelayCellOfst[4]=7 cells (2 PI)
8270 20:00:22.510324 u2DelayCellOfst[5]=14 cells (4 PI)
8271 20:00:22.513811 u2DelayCellOfst[6]=14 cells (4 PI)
8272 20:00:22.516944 u2DelayCellOfst[7]=3 cells (1 PI)
8273 20:00:22.520075 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8274 20:00:22.523347 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8275 20:00:22.526688 == TX Byte 1 ==
8276 20:00:22.530095 u2DelayCellOfst[8]=0 cells (0 PI)
8277 20:00:22.530658 u2DelayCellOfst[9]=7 cells (2 PI)
8278 20:00:22.533415 u2DelayCellOfst[10]=10 cells (3 PI)
8279 20:00:22.536710 u2DelayCellOfst[11]=3 cells (1 PI)
8280 20:00:22.539933 u2DelayCellOfst[12]=17 cells (5 PI)
8281 20:00:22.543350 u2DelayCellOfst[13]=21 cells (6 PI)
8282 20:00:22.546909 u2DelayCellOfst[14]=21 cells (6 PI)
8283 20:00:22.550000 u2DelayCellOfst[15]=21 cells (6 PI)
8284 20:00:22.553019 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8285 20:00:22.560276 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8286 20:00:22.560837 DramC Write-DBI on
8287 20:00:22.561205 ==
8288 20:00:22.563107 Dram Type= 6, Freq= 0, CH_1, rank 0
8289 20:00:22.569868 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8290 20:00:22.570434 ==
8291 20:00:22.570800
8292 20:00:22.571138
8293 20:00:22.571461 TX Vref Scan disable
8294 20:00:22.573409 == TX Byte 0 ==
8295 20:00:22.576879 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8296 20:00:22.580042 == TX Byte 1 ==
8297 20:00:22.583472 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8298 20:00:22.586570 DramC Write-DBI off
8299 20:00:22.587029
8300 20:00:22.587395 [DATLAT]
8301 20:00:22.587733 Freq=1600, CH1 RK0
8302 20:00:22.588060
8303 20:00:22.590016 DATLAT Default: 0xf
8304 20:00:22.593510 0, 0xFFFF, sum = 0
8305 20:00:22.594083 1, 0xFFFF, sum = 0
8306 20:00:22.596547 2, 0xFFFF, sum = 0
8307 20:00:22.597111 3, 0xFFFF, sum = 0
8308 20:00:22.600343 4, 0xFFFF, sum = 0
8309 20:00:22.600926 5, 0xFFFF, sum = 0
8310 20:00:22.603533 6, 0xFFFF, sum = 0
8311 20:00:22.604106 7, 0xFFFF, sum = 0
8312 20:00:22.606885 8, 0xFFFF, sum = 0
8313 20:00:22.607505 9, 0xFFFF, sum = 0
8314 20:00:22.610097 10, 0xFFFF, sum = 0
8315 20:00:22.610668 11, 0xFFFF, sum = 0
8316 20:00:22.613230 12, 0xF7F, sum = 0
8317 20:00:22.613696 13, 0x0, sum = 1
8318 20:00:22.616949 14, 0x0, sum = 2
8319 20:00:22.617519 15, 0x0, sum = 3
8320 20:00:22.620115 16, 0x0, sum = 4
8321 20:00:22.620766 best_step = 14
8322 20:00:22.621165
8323 20:00:22.621510 ==
8324 20:00:22.623072 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 20:00:22.626426 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8326 20:00:22.626888 ==
8327 20:00:22.630073 RX Vref Scan: 1
8328 20:00:22.630632
8329 20:00:22.633004 Set Vref Range= 24 -> 127
8330 20:00:22.633463
8331 20:00:22.633827 RX Vref 24 -> 127, step: 1
8332 20:00:22.636813
8333 20:00:22.637373 RX Delay 3 -> 252, step: 4
8334 20:00:22.637746
8335 20:00:22.639799 Set Vref, RX VrefLevel [Byte0]: 24
8336 20:00:22.642877 [Byte1]: 24
8337 20:00:22.646744
8338 20:00:22.647345 Set Vref, RX VrefLevel [Byte0]: 25
8339 20:00:22.650109 [Byte1]: 25
8340 20:00:22.654331
8341 20:00:22.654893 Set Vref, RX VrefLevel [Byte0]: 26
8342 20:00:22.657711 [Byte1]: 26
8343 20:00:22.661985
8344 20:00:22.662545 Set Vref, RX VrefLevel [Byte0]: 27
8345 20:00:22.665448 [Byte1]: 27
8346 20:00:22.669874
8347 20:00:22.670436 Set Vref, RX VrefLevel [Byte0]: 28
8348 20:00:22.672766 [Byte1]: 28
8349 20:00:22.677394
8350 20:00:22.677963 Set Vref, RX VrefLevel [Byte0]: 29
8351 20:00:22.680261 [Byte1]: 29
8352 20:00:22.684920
8353 20:00:22.685482 Set Vref, RX VrefLevel [Byte0]: 30
8354 20:00:22.688349 [Byte1]: 30
8355 20:00:22.692814
8356 20:00:22.693375 Set Vref, RX VrefLevel [Byte0]: 31
8357 20:00:22.695742 [Byte1]: 31
8358 20:00:22.700568
8359 20:00:22.701130 Set Vref, RX VrefLevel [Byte0]: 32
8360 20:00:22.703680 [Byte1]: 32
8361 20:00:22.707702
8362 20:00:22.708156 Set Vref, RX VrefLevel [Byte0]: 33
8363 20:00:22.711150 [Byte1]: 33
8364 20:00:22.715461
8365 20:00:22.715913 Set Vref, RX VrefLevel [Byte0]: 34
8366 20:00:22.718684 [Byte1]: 34
8367 20:00:22.723016
8368 20:00:22.723468 Set Vref, RX VrefLevel [Byte0]: 35
8369 20:00:22.726541 [Byte1]: 35
8370 20:00:22.731106
8371 20:00:22.731661 Set Vref, RX VrefLevel [Byte0]: 36
8372 20:00:22.734266 [Byte1]: 36
8373 20:00:22.738570
8374 20:00:22.739099 Set Vref, RX VrefLevel [Byte0]: 37
8375 20:00:22.741769 [Byte1]: 37
8376 20:00:22.746124
8377 20:00:22.746685 Set Vref, RX VrefLevel [Byte0]: 38
8378 20:00:22.749486 [Byte1]: 38
8379 20:00:22.753798
8380 20:00:22.754363 Set Vref, RX VrefLevel [Byte0]: 39
8381 20:00:22.756812 [Byte1]: 39
8382 20:00:22.761191
8383 20:00:22.761645 Set Vref, RX VrefLevel [Byte0]: 40
8384 20:00:22.764603 [Byte1]: 40
8385 20:00:22.769210
8386 20:00:22.769774 Set Vref, RX VrefLevel [Byte0]: 41
8387 20:00:22.772257 [Byte1]: 41
8388 20:00:22.776813
8389 20:00:22.777370 Set Vref, RX VrefLevel [Byte0]: 42
8390 20:00:22.780031 [Byte1]: 42
8391 20:00:22.784638
8392 20:00:22.785196 Set Vref, RX VrefLevel [Byte0]: 43
8393 20:00:22.787781 [Byte1]: 43
8394 20:00:22.792140
8395 20:00:22.792739 Set Vref, RX VrefLevel [Byte0]: 44
8396 20:00:22.795626 [Byte1]: 44
8397 20:00:22.799834
8398 20:00:22.800433 Set Vref, RX VrefLevel [Byte0]: 45
8399 20:00:22.803308 [Byte1]: 45
8400 20:00:22.807650
8401 20:00:22.808258 Set Vref, RX VrefLevel [Byte0]: 46
8402 20:00:22.810600 [Byte1]: 46
8403 20:00:22.814945
8404 20:00:22.815503 Set Vref, RX VrefLevel [Byte0]: 47
8405 20:00:22.818316 [Byte1]: 47
8406 20:00:22.822793
8407 20:00:22.823359 Set Vref, RX VrefLevel [Byte0]: 48
8408 20:00:22.825838 [Byte1]: 48
8409 20:00:22.830472
8410 20:00:22.831025 Set Vref, RX VrefLevel [Byte0]: 49
8411 20:00:22.833439 [Byte1]: 49
8412 20:00:22.838121
8413 20:00:22.838724 Set Vref, RX VrefLevel [Byte0]: 50
8414 20:00:22.841199 [Byte1]: 50
8415 20:00:22.845386
8416 20:00:22.845848 Set Vref, RX VrefLevel [Byte0]: 51
8417 20:00:22.849010 [Byte1]: 51
8418 20:00:22.853180
8419 20:00:22.853738 Set Vref, RX VrefLevel [Byte0]: 52
8420 20:00:22.856475 [Byte1]: 52
8421 20:00:22.860928
8422 20:00:22.861480 Set Vref, RX VrefLevel [Byte0]: 53
8423 20:00:22.864241 [Byte1]: 53
8424 20:00:22.868875
8425 20:00:22.869432 Set Vref, RX VrefLevel [Byte0]: 54
8426 20:00:22.871909 [Byte1]: 54
8427 20:00:22.876344
8428 20:00:22.876897 Set Vref, RX VrefLevel [Byte0]: 55
8429 20:00:22.879662 [Byte1]: 55
8430 20:00:22.883934
8431 20:00:22.884534 Set Vref, RX VrefLevel [Byte0]: 56
8432 20:00:22.887465 [Byte1]: 56
8433 20:00:22.891760
8434 20:00:22.892366 Set Vref, RX VrefLevel [Byte0]: 57
8435 20:00:22.894861 [Byte1]: 57
8436 20:00:22.899427
8437 20:00:22.899979 Set Vref, RX VrefLevel [Byte0]: 58
8438 20:00:22.902528 [Byte1]: 58
8439 20:00:22.907002
8440 20:00:22.907538 Set Vref, RX VrefLevel [Byte0]: 59
8441 20:00:22.910210 [Byte1]: 59
8442 20:00:22.914585
8443 20:00:22.915145 Set Vref, RX VrefLevel [Byte0]: 60
8444 20:00:22.917826 [Byte1]: 60
8445 20:00:22.922106
8446 20:00:22.922691 Set Vref, RX VrefLevel [Byte0]: 61
8447 20:00:22.925434 [Byte1]: 61
8448 20:00:22.930060
8449 20:00:22.930622 Set Vref, RX VrefLevel [Byte0]: 62
8450 20:00:22.933094 [Byte1]: 62
8451 20:00:22.937500
8452 20:00:22.938063 Set Vref, RX VrefLevel [Byte0]: 63
8453 20:00:22.940639 [Byte1]: 63
8454 20:00:22.944990
8455 20:00:22.945449 Set Vref, RX VrefLevel [Byte0]: 64
8456 20:00:22.948095 [Byte1]: 64
8457 20:00:22.952951
8458 20:00:22.953710 Set Vref, RX VrefLevel [Byte0]: 65
8459 20:00:22.956038 [Byte1]: 65
8460 20:00:22.960580
8461 20:00:22.961140 Set Vref, RX VrefLevel [Byte0]: 66
8462 20:00:22.966886 [Byte1]: 66
8463 20:00:22.967345
8464 20:00:22.970398 Set Vref, RX VrefLevel [Byte0]: 67
8465 20:00:22.973808 [Byte1]: 67
8466 20:00:22.974373
8467 20:00:22.976956 Set Vref, RX VrefLevel [Byte0]: 68
8468 20:00:22.980165 [Byte1]: 68
8469 20:00:22.983351
8470 20:00:22.983921 Set Vref, RX VrefLevel [Byte0]: 69
8471 20:00:22.986848 [Byte1]: 69
8472 20:00:22.991183
8473 20:00:22.991741 Set Vref, RX VrefLevel [Byte0]: 70
8474 20:00:22.994320 [Byte1]: 70
8475 20:00:22.998673
8476 20:00:22.999234 Set Vref, RX VrefLevel [Byte0]: 71
8477 20:00:23.001706 [Byte1]: 71
8478 20:00:23.006427
8479 20:00:23.006988 Set Vref, RX VrefLevel [Byte0]: 72
8480 20:00:23.009719 [Byte1]: 72
8481 20:00:23.013748
8482 20:00:23.014218 Set Vref, RX VrefLevel [Byte0]: 73
8483 20:00:23.017308 [Byte1]: 73
8484 20:00:23.021553
8485 20:00:23.022111 Set Vref, RX VrefLevel [Byte0]: 74
8486 20:00:23.024927 [Byte1]: 74
8487 20:00:23.029297
8488 20:00:23.029855 Set Vref, RX VrefLevel [Byte0]: 75
8489 20:00:23.032333 [Byte1]: 75
8490 20:00:23.036779
8491 20:00:23.037236 Set Vref, RX VrefLevel [Byte0]: 76
8492 20:00:23.040411 [Byte1]: 76
8493 20:00:23.044482
8494 20:00:23.044943 Set Vref, RX VrefLevel [Byte0]: 77
8495 20:00:23.048040 [Byte1]: 77
8496 20:00:23.052400
8497 20:00:23.052965 Final RX Vref Byte 0 = 59 to rank0
8498 20:00:23.055522 Final RX Vref Byte 1 = 53 to rank0
8499 20:00:23.058710 Final RX Vref Byte 0 = 59 to rank1
8500 20:00:23.062440 Final RX Vref Byte 1 = 53 to rank1==
8501 20:00:23.065363 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 20:00:23.071946 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8503 20:00:23.072586 ==
8504 20:00:23.072971 DQS Delay:
8505 20:00:23.075624 DQS0 = 0, DQS1 = 0
8506 20:00:23.076236 DQM Delay:
8507 20:00:23.076615 DQM0 = 128, DQM1 = 123
8508 20:00:23.078730 DQ Delay:
8509 20:00:23.081834 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8510 20:00:23.085398 DQ4 =128, DQ5 =138, DQ6 =138, DQ7 =126
8511 20:00:23.088553 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114
8512 20:00:23.092026 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =134
8513 20:00:23.092659
8514 20:00:23.093035
8515 20:00:23.093377
8516 20:00:23.095572 [DramC_TX_OE_Calibration] TA2
8517 20:00:23.098818 Original DQ_B0 (3 6) =30, OEN = 27
8518 20:00:23.102105 Original DQ_B1 (3 6) =30, OEN = 27
8519 20:00:23.105537 24, 0x0, End_B0=24 End_B1=24
8520 20:00:23.106110 25, 0x0, End_B0=25 End_B1=25
8521 20:00:23.108891 26, 0x0, End_B0=26 End_B1=26
8522 20:00:23.112039 27, 0x0, End_B0=27 End_B1=27
8523 20:00:23.115314 28, 0x0, End_B0=28 End_B1=28
8524 20:00:23.118593 29, 0x0, End_B0=29 End_B1=29
8525 20:00:23.119209 30, 0x0, End_B0=30 End_B1=30
8526 20:00:23.121973 31, 0x4545, End_B0=30 End_B1=30
8527 20:00:23.125123 Byte0 end_step=30 best_step=27
8528 20:00:23.128879 Byte1 end_step=30 best_step=27
8529 20:00:23.131582 Byte0 TX OE(2T, 0.5T) = (3, 3)
8530 20:00:23.135096 Byte1 TX OE(2T, 0.5T) = (3, 3)
8531 20:00:23.135657
8532 20:00:23.136023
8533 20:00:23.141491 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8534 20:00:23.144849 CH1 RK0: MR19=303, MR18=2525
8535 20:00:23.152027 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8536 20:00:23.152646
8537 20:00:23.155489 ----->DramcWriteLeveling(PI) begin...
8538 20:00:23.156055 ==
8539 20:00:23.158543 Dram Type= 6, Freq= 0, CH_1, rank 1
8540 20:00:23.161652 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8541 20:00:23.162116 ==
8542 20:00:23.164827 Write leveling (Byte 0): 21 => 21
8543 20:00:23.168276 Write leveling (Byte 1): 21 => 21
8544 20:00:23.171750 DramcWriteLeveling(PI) end<-----
8545 20:00:23.172362
8546 20:00:23.172735 ==
8547 20:00:23.175335 Dram Type= 6, Freq= 0, CH_1, rank 1
8548 20:00:23.178160 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8549 20:00:23.178625 ==
8550 20:00:23.181551 [Gating] SW mode calibration
8551 20:00:23.188450 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8552 20:00:23.194793 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8553 20:00:23.198363 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8554 20:00:23.201710 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8555 20:00:23.208002 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8556 20:00:23.211604 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8557 20:00:23.215021 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8558 20:00:23.221643 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
8559 20:00:23.224932 0 12 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8560 20:00:23.228061 0 12 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8561 20:00:23.234669 0 13 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8562 20:00:23.238187 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8563 20:00:23.241080 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8564 20:00:23.247692 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8565 20:00:23.251198 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8566 20:00:23.254638 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8567 20:00:23.261122 0 13 24 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8568 20:00:23.264574 0 13 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8569 20:00:23.267802 0 14 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8570 20:00:23.274319 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8571 20:00:23.277378 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8572 20:00:23.281002 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8573 20:00:23.287615 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8574 20:00:23.291134 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8575 20:00:23.294153 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8576 20:00:23.300809 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8577 20:00:23.304105 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8578 20:00:23.307701 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8579 20:00:23.314353 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8580 20:00:23.317505 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 20:00:23.320968 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 20:00:23.327182 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 20:00:23.330638 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 20:00:23.333965 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8585 20:00:23.340803 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8586 20:00:23.344130 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8587 20:00:23.347035 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8588 20:00:23.353705 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8589 20:00:23.356745 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8590 20:00:23.360236 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8591 20:00:23.366970 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8592 20:00:23.370378 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8593 20:00:23.373453 Total UI for P1: 0, mck2ui 16
8594 20:00:23.376936 best dqsien dly found for B0: ( 1, 0, 26)
8595 20:00:23.380341 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8596 20:00:23.386863 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8597 20:00:23.387435 Total UI for P1: 0, mck2ui 16
8598 20:00:23.393345 best dqsien dly found for B1: ( 1, 0, 30)
8599 20:00:23.396524 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8600 20:00:23.399842 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8601 20:00:23.400353
8602 20:00:23.403231 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8603 20:00:23.406813 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8604 20:00:23.410162 [Gating] SW calibration Done
8605 20:00:23.410801 ==
8606 20:00:23.413575 Dram Type= 6, Freq= 0, CH_1, rank 1
8607 20:00:23.416842 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8608 20:00:23.417413 ==
8609 20:00:23.419966 RX Vref Scan: 0
8610 20:00:23.420572
8611 20:00:23.420947 RX Vref 0 -> 0, step: 1
8612 20:00:23.421292
8613 20:00:23.423337 RX Delay 0 -> 252, step: 8
8614 20:00:23.426513 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8615 20:00:23.433211 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8616 20:00:23.436316 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8617 20:00:23.440014 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8618 20:00:23.443278 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8619 20:00:23.446357 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8620 20:00:23.452890 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8621 20:00:23.456377 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8622 20:00:23.459663 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8623 20:00:23.462769 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8624 20:00:23.466336 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8625 20:00:23.472879 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8626 20:00:23.476533 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8627 20:00:23.479748 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8628 20:00:23.482718 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8629 20:00:23.485989 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8630 20:00:23.489590 ==
8631 20:00:23.493134 Dram Type= 6, Freq= 0, CH_1, rank 1
8632 20:00:23.496038 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8633 20:00:23.496667 ==
8634 20:00:23.497046 DQS Delay:
8635 20:00:23.499583 DQS0 = 0, DQS1 = 0
8636 20:00:23.500150 DQM Delay:
8637 20:00:23.502723 DQM0 = 131, DQM1 = 125
8638 20:00:23.503292 DQ Delay:
8639 20:00:23.505903 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =131
8640 20:00:23.509357 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8641 20:00:23.512642 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8642 20:00:23.516004 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8643 20:00:23.516615
8644 20:00:23.516986
8645 20:00:23.517329 ==
8646 20:00:23.519121 Dram Type= 6, Freq= 0, CH_1, rank 1
8647 20:00:23.525919 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8648 20:00:23.526488 ==
8649 20:00:23.526863
8650 20:00:23.527207
8651 20:00:23.527536 TX Vref Scan disable
8652 20:00:23.529664 == TX Byte 0 ==
8653 20:00:23.532925 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8654 20:00:23.539540 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8655 20:00:23.540119 == TX Byte 1 ==
8656 20:00:23.542918 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8657 20:00:23.549451 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8658 20:00:23.549919 ==
8659 20:00:23.552723 Dram Type= 6, Freq= 0, CH_1, rank 1
8660 20:00:23.556245 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8661 20:00:23.556829 ==
8662 20:00:23.569018
8663 20:00:23.572642 TX Vref early break, caculate TX vref
8664 20:00:23.575612 TX Vref=16, minBit 4, minWin=22, winSum=380
8665 20:00:23.579158 TX Vref=18, minBit 1, minWin=23, winSum=388
8666 20:00:23.582246 TX Vref=20, minBit 3, minWin=23, winSum=398
8667 20:00:23.585762 TX Vref=22, minBit 3, minWin=23, winSum=401
8668 20:00:23.589024 TX Vref=24, minBit 0, minWin=24, winSum=412
8669 20:00:23.595240 TX Vref=26, minBit 0, minWin=25, winSum=418
8670 20:00:23.598847 TX Vref=28, minBit 0, minWin=25, winSum=418
8671 20:00:23.602242 TX Vref=30, minBit 0, minWin=24, winSum=417
8672 20:00:23.605491 TX Vref=32, minBit 0, minWin=24, winSum=409
8673 20:00:23.608849 TX Vref=34, minBit 0, minWin=23, winSum=400
8674 20:00:23.612109 TX Vref=36, minBit 0, minWin=23, winSum=395
8675 20:00:23.618745 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8676 20:00:23.619307
8677 20:00:23.622159 Final TX Range 0 Vref 26
8678 20:00:23.622860
8679 20:00:23.623235 ==
8680 20:00:23.625495 Dram Type= 6, Freq= 0, CH_1, rank 1
8681 20:00:23.628634 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8682 20:00:23.629207 ==
8683 20:00:23.629572
8684 20:00:23.632043
8685 20:00:23.632634 TX Vref Scan disable
8686 20:00:23.638883 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8687 20:00:23.639466 == TX Byte 0 ==
8688 20:00:23.641759 u2DelayCellOfst[0]=14 cells (4 PI)
8689 20:00:23.645503 u2DelayCellOfst[1]=10 cells (3 PI)
8690 20:00:23.648411 u2DelayCellOfst[2]=0 cells (0 PI)
8691 20:00:23.652091 u2DelayCellOfst[3]=7 cells (2 PI)
8692 20:00:23.655198 u2DelayCellOfst[4]=7 cells (2 PI)
8693 20:00:23.658921 u2DelayCellOfst[5]=17 cells (5 PI)
8694 20:00:23.661793 u2DelayCellOfst[6]=17 cells (5 PI)
8695 20:00:23.665002 u2DelayCellOfst[7]=7 cells (2 PI)
8696 20:00:23.668296 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8697 20:00:23.671841 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8698 20:00:23.675193 == TX Byte 1 ==
8699 20:00:23.678491 u2DelayCellOfst[8]=0 cells (0 PI)
8700 20:00:23.678953 u2DelayCellOfst[9]=3 cells (1 PI)
8701 20:00:23.681565 u2DelayCellOfst[10]=10 cells (3 PI)
8702 20:00:23.684711 u2DelayCellOfst[11]=3 cells (1 PI)
8703 20:00:23.688319 u2DelayCellOfst[12]=14 cells (4 PI)
8704 20:00:23.692090 u2DelayCellOfst[13]=17 cells (5 PI)
8705 20:00:23.694817 u2DelayCellOfst[14]=17 cells (5 PI)
8706 20:00:23.698406 u2DelayCellOfst[15]=17 cells (5 PI)
8707 20:00:23.704820 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8708 20:00:23.708460 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8709 20:00:23.708920 DramC Write-DBI on
8710 20:00:23.709285 ==
8711 20:00:23.711794 Dram Type= 6, Freq= 0, CH_1, rank 1
8712 20:00:23.718040 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8713 20:00:23.718611 ==
8714 20:00:23.718986
8715 20:00:23.719326
8716 20:00:23.719652 TX Vref Scan disable
8717 20:00:23.722161 == TX Byte 0 ==
8718 20:00:23.725702 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8719 20:00:23.728680 == TX Byte 1 ==
8720 20:00:23.732567 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8721 20:00:23.735527 DramC Write-DBI off
8722 20:00:23.736096
8723 20:00:23.736534 [DATLAT]
8724 20:00:23.736882 Freq=1600, CH1 RK1
8725 20:00:23.737212
8726 20:00:23.738518 DATLAT Default: 0xe
8727 20:00:23.738974 0, 0xFFFF, sum = 0
8728 20:00:23.741679 1, 0xFFFF, sum = 0
8729 20:00:23.745271 2, 0xFFFF, sum = 0
8730 20:00:23.745849 3, 0xFFFF, sum = 0
8731 20:00:23.748284 4, 0xFFFF, sum = 0
8732 20:00:23.748759 5, 0xFFFF, sum = 0
8733 20:00:23.752006 6, 0xFFFF, sum = 0
8734 20:00:23.752633 7, 0xFFFF, sum = 0
8735 20:00:23.755234 8, 0xFFFF, sum = 0
8736 20:00:23.755805 9, 0xFFFF, sum = 0
8737 20:00:23.758619 10, 0xFFFF, sum = 0
8738 20:00:23.759194 11, 0xFFFF, sum = 0
8739 20:00:23.761943 12, 0xF7F, sum = 0
8740 20:00:23.762443 13, 0x0, sum = 1
8741 20:00:23.765203 14, 0x0, sum = 2
8742 20:00:23.765775 15, 0x0, sum = 3
8743 20:00:23.768576 16, 0x0, sum = 4
8744 20:00:23.769050 best_step = 14
8745 20:00:23.769510
8746 20:00:23.769865 ==
8747 20:00:23.772287 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 20:00:23.775635 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8749 20:00:23.776321 ==
8750 20:00:23.778308 RX Vref Scan: 0
8751 20:00:23.778771
8752 20:00:23.781811 RX Vref 0 -> 0, step: 1
8753 20:00:23.782431
8754 20:00:23.782806 RX Delay 3 -> 252, step: 4
8755 20:00:23.788785 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8756 20:00:23.792391 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8757 20:00:23.795780 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8758 20:00:23.799057 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8759 20:00:23.802259 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8760 20:00:23.809147 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8761 20:00:23.812282 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8762 20:00:23.815601 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8763 20:00:23.819160 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8764 20:00:23.822253 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8765 20:00:23.828877 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8766 20:00:23.832002 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8767 20:00:23.835315 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8768 20:00:23.839018 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8769 20:00:23.845946 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8770 20:00:23.848793 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8771 20:00:23.849262 ==
8772 20:00:23.851916 Dram Type= 6, Freq= 0, CH_1, rank 1
8773 20:00:23.855375 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8774 20:00:23.855933 ==
8775 20:00:23.858649 DQS Delay:
8776 20:00:23.859123 DQS0 = 0, DQS1 = 0
8777 20:00:23.859491 DQM Delay:
8778 20:00:23.862011 DQM0 = 127, DQM1 = 122
8779 20:00:23.862573 DQ Delay:
8780 20:00:23.865490 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8781 20:00:23.868356 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8782 20:00:23.872137 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8783 20:00:23.878364 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8784 20:00:23.878904
8785 20:00:23.879269
8786 20:00:23.879611
8787 20:00:23.881987 [DramC_TX_OE_Calibration] TA2
8788 20:00:23.882550 Original DQ_B0 (3 6) =30, OEN = 27
8789 20:00:23.885323 Original DQ_B1 (3 6) =30, OEN = 27
8790 20:00:23.888553 24, 0x0, End_B0=24 End_B1=24
8791 20:00:23.891952 25, 0x0, End_B0=25 End_B1=25
8792 20:00:23.894941 26, 0x0, End_B0=26 End_B1=26
8793 20:00:23.898777 27, 0x0, End_B0=27 End_B1=27
8794 20:00:23.899346 28, 0x0, End_B0=28 End_B1=28
8795 20:00:23.902133 29, 0x0, End_B0=29 End_B1=29
8796 20:00:23.905277 30, 0x0, End_B0=30 End_B1=30
8797 20:00:23.908338 31, 0x4141, End_B0=30 End_B1=30
8798 20:00:23.912027 Byte0 end_step=30 best_step=27
8799 20:00:23.912664 Byte1 end_step=30 best_step=27
8800 20:00:23.914851 Byte0 TX OE(2T, 0.5T) = (3, 3)
8801 20:00:23.918620 Byte1 TX OE(2T, 0.5T) = (3, 3)
8802 20:00:23.919174
8803 20:00:23.919544
8804 20:00:23.928142 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8805 20:00:23.928744 CH1 RK1: MR19=303, MR18=1F1F
8806 20:00:23.934811 CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8807 20:00:23.937985 [RxdqsGatingPostProcess] freq 1600
8808 20:00:23.945121 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8809 20:00:23.947720 Pre-setting of DQS Precalculation
8810 20:00:23.951565 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8811 20:00:23.961096 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8812 20:00:23.967665 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8813 20:00:23.968279
8814 20:00:23.968664
8815 20:00:23.971352 [Calibration Summary] 3200 Mbps
8816 20:00:23.971909 CH 0, Rank 0
8817 20:00:23.974357 SW Impedance : PASS
8818 20:00:23.974821 DUTY Scan : NO K
8819 20:00:23.978161 ZQ Calibration : PASS
8820 20:00:23.981109 Jitter Meter : NO K
8821 20:00:23.981670 CBT Training : PASS
8822 20:00:23.984477 Write leveling : PASS
8823 20:00:23.987688 RX DQS gating : PASS
8824 20:00:23.988281 RX DQ/DQS(RDDQC) : PASS
8825 20:00:23.991327 TX DQ/DQS : PASS
8826 20:00:23.994466 RX DATLAT : PASS
8827 20:00:23.995022 RX DQ/DQS(Engine): PASS
8828 20:00:23.997819 TX OE : PASS
8829 20:00:23.998378 All Pass.
8830 20:00:23.998874
8831 20:00:24.000877 CH 0, Rank 1
8832 20:00:24.001340 SW Impedance : PASS
8833 20:00:24.004547 DUTY Scan : NO K
8834 20:00:24.005109 ZQ Calibration : PASS
8835 20:00:24.007607 Jitter Meter : NO K
8836 20:00:24.011042 CBT Training : PASS
8837 20:00:24.011751 Write leveling : PASS
8838 20:00:24.014124 RX DQS gating : PASS
8839 20:00:24.017490 RX DQ/DQS(RDDQC) : PASS
8840 20:00:24.017949 TX DQ/DQS : PASS
8841 20:00:24.020900 RX DATLAT : PASS
8842 20:00:24.024328 RX DQ/DQS(Engine): PASS
8843 20:00:24.024883 TX OE : PASS
8844 20:00:24.027540 All Pass.
8845 20:00:24.028093
8846 20:00:24.028508 CH 1, Rank 0
8847 20:00:24.030754 SW Impedance : PASS
8848 20:00:24.031313 DUTY Scan : NO K
8849 20:00:24.034294 ZQ Calibration : PASS
8850 20:00:24.037459 Jitter Meter : NO K
8851 20:00:24.038031 CBT Training : PASS
8852 20:00:24.040976 Write leveling : PASS
8853 20:00:24.043801 RX DQS gating : PASS
8854 20:00:24.044293 RX DQ/DQS(RDDQC) : PASS
8855 20:00:24.047356 TX DQ/DQS : PASS
8856 20:00:24.050687 RX DATLAT : PASS
8857 20:00:24.051148 RX DQ/DQS(Engine): PASS
8858 20:00:24.054112 TX OE : PASS
8859 20:00:24.054673 All Pass.
8860 20:00:24.055045
8861 20:00:24.057418 CH 1, Rank 1
8862 20:00:24.057972 SW Impedance : PASS
8863 20:00:24.060489 DUTY Scan : NO K
8864 20:00:24.060951 ZQ Calibration : PASS
8865 20:00:24.063889 Jitter Meter : NO K
8866 20:00:24.067549 CBT Training : PASS
8867 20:00:24.068152 Write leveling : PASS
8868 20:00:24.070649 RX DQS gating : PASS
8869 20:00:24.073749 RX DQ/DQS(RDDQC) : PASS
8870 20:00:24.074231 TX DQ/DQS : PASS
8871 20:00:24.077478 RX DATLAT : PASS
8872 20:00:24.080892 RX DQ/DQS(Engine): PASS
8873 20:00:24.081449 TX OE : PASS
8874 20:00:24.083869 All Pass.
8875 20:00:24.084472
8876 20:00:24.084847 DramC Write-DBI on
8877 20:00:24.087313 PER_BANK_REFRESH: Hybrid Mode
8878 20:00:24.087869 TX_TRACKING: ON
8879 20:00:24.097123 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8880 20:00:24.107152 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8881 20:00:24.113575 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8882 20:00:24.116902 [FAST_K] Save calibration result to emmc
8883 20:00:24.120723 sync common calibartion params.
8884 20:00:24.121190 sync cbt_mode0:0, 1:0
8885 20:00:24.123514 dram_init: ddr_geometry: 0
8886 20:00:24.126868 dram_init: ddr_geometry: 0
8887 20:00:24.130423 dram_init: ddr_geometry: 0
8888 20:00:24.130975 0:dram_rank_size:80000000
8889 20:00:24.133362 1:dram_rank_size:80000000
8890 20:00:24.140148 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8891 20:00:24.140757 DFS_SHUFFLE_HW_MODE: ON
8892 20:00:24.143535 dramc_set_vcore_voltage set vcore to 725000
8893 20:00:24.146706 Read voltage for 1600, 0
8894 20:00:24.147259 Vio18 = 0
8895 20:00:24.149829 Vcore = 725000
8896 20:00:24.150291 Vdram = 0
8897 20:00:24.150663 Vddq = 0
8898 20:00:24.153174 Vmddr = 0
8899 20:00:24.153666 switch to 3200 Mbps bootup
8900 20:00:24.156702 [DramcRunTimeConfig]
8901 20:00:24.157164 PHYPLL
8902 20:00:24.159995 DPM_CONTROL_AFTERK: ON
8903 20:00:24.160501 PER_BANK_REFRESH: ON
8904 20:00:24.163246 REFRESH_OVERHEAD_REDUCTION: ON
8905 20:00:24.166366 CMD_PICG_NEW_MODE: OFF
8906 20:00:24.166831 XRTWTW_NEW_MODE: ON
8907 20:00:24.170130 XRTRTR_NEW_MODE: ON
8908 20:00:24.170687 TX_TRACKING: ON
8909 20:00:24.173128 RDSEL_TRACKING: OFF
8910 20:00:24.176555 DQS Precalculation for DVFS: ON
8911 20:00:24.177107 RX_TRACKING: OFF
8912 20:00:24.179754 HW_GATING DBG: ON
8913 20:00:24.180350 ZQCS_ENABLE_LP4: ON
8914 20:00:24.183269 RX_PICG_NEW_MODE: ON
8915 20:00:24.183830 TX_PICG_NEW_MODE: ON
8916 20:00:24.186308 ENABLE_RX_DCM_DPHY: ON
8917 20:00:24.189665 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8918 20:00:24.193257 DUMMY_READ_FOR_TRACKING: OFF
8919 20:00:24.193810 !!! SPM_CONTROL_AFTERK: OFF
8920 20:00:24.196365 !!! SPM could not control APHY
8921 20:00:24.199471 IMPEDANCE_TRACKING: ON
8922 20:00:24.199935 TEMP_SENSOR: ON
8923 20:00:24.202692 HW_SAVE_FOR_SR: OFF
8924 20:00:24.206234 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8925 20:00:24.209492 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8926 20:00:24.212915 Read ODT Tracking: ON
8927 20:00:24.213467 Refresh Rate DeBounce: ON
8928 20:00:24.216221 DFS_NO_QUEUE_FLUSH: ON
8929 20:00:24.219300 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8930 20:00:24.222624 ENABLE_DFS_RUNTIME_MRW: OFF
8931 20:00:24.223087 DDR_RESERVE_NEW_MODE: ON
8932 20:00:24.226126 MR_CBT_SWITCH_FREQ: ON
8933 20:00:24.229344 =========================
8934 20:00:24.246842 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8935 20:00:24.249803 dram_init: ddr_geometry: 0
8936 20:00:24.268060 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8937 20:00:24.271329 dram_init: dram init end (result: 0)
8938 20:00:24.278268 DRAM-K: Full calibration passed in 23438 msecs
8939 20:00:24.281326 MRC: failed to locate region type 0.
8940 20:00:24.281885 DRAM rank0 size:0x80000000,
8941 20:00:24.284496 DRAM rank1 size=0x80000000
8942 20:00:24.294553 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8943 20:00:24.301447 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8944 20:00:24.307749 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8945 20:00:24.314522 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8946 20:00:24.318015 DRAM rank0 size:0x80000000,
8947 20:00:24.321112 DRAM rank1 size=0x80000000
8948 20:00:24.321679 CBMEM:
8949 20:00:24.324341 IMD: root @ 0xfffff000 254 entries.
8950 20:00:24.327889 IMD: root @ 0xffffec00 62 entries.
8951 20:00:24.331112 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8952 20:00:24.334288 WARNING: RO_VPD is uninitialized or empty.
8953 20:00:24.340707 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8954 20:00:24.347703 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8955 20:00:24.360257 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8956 20:00:24.371854 BS: romstage times (exec / console): total (unknown) / 22972 ms
8957 20:00:24.372477
8958 20:00:24.372917
8959 20:00:24.381738 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8960 20:00:24.384804 ARM64: Exception handlers installed.
8961 20:00:24.388143 ARM64: Testing exception
8962 20:00:24.391590 ARM64: Done test exception
8963 20:00:24.392143 Enumerating buses...
8964 20:00:24.394715 Show all devs... Before device enumeration.
8965 20:00:24.398141 Root Device: enabled 1
8966 20:00:24.401672 CPU_CLUSTER: 0: enabled 1
8967 20:00:24.402233 CPU: 00: enabled 1
8968 20:00:24.404963 Compare with tree...
8969 20:00:24.405546 Root Device: enabled 1
8970 20:00:24.408338 CPU_CLUSTER: 0: enabled 1
8971 20:00:24.411391 CPU: 00: enabled 1
8972 20:00:24.412119 Root Device scanning...
8973 20:00:24.414864 scan_static_bus for Root Device
8974 20:00:24.417999 CPU_CLUSTER: 0 enabled
8975 20:00:24.421275 scan_static_bus for Root Device done
8976 20:00:24.424566 scan_bus: bus Root Device finished in 8 msecs
8977 20:00:24.425120 done
8978 20:00:24.431262 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8979 20:00:24.434918 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8980 20:00:24.441244 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8981 20:00:24.444221 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8982 20:00:24.448003 Allocating resources...
8983 20:00:24.450838 Reading resources...
8984 20:00:24.454337 Root Device read_resources bus 0 link: 0
8985 20:00:24.454898 DRAM rank0 size:0x80000000,
8986 20:00:24.458157 DRAM rank1 size=0x80000000
8987 20:00:24.460859 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8988 20:00:24.463994 CPU: 00 missing read_resources
8989 20:00:24.470905 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8990 20:00:24.473987 Root Device read_resources bus 0 link: 0 done
8991 20:00:24.474450 Done reading resources.
8992 20:00:24.480657 Show resources in subtree (Root Device)...After reading.
8993 20:00:24.483864 Root Device child on link 0 CPU_CLUSTER: 0
8994 20:00:24.487306 CPU_CLUSTER: 0 child on link 0 CPU: 00
8995 20:00:24.497323 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8996 20:00:24.497889 CPU: 00
8997 20:00:24.500641 Root Device assign_resources, bus 0 link: 0
8998 20:00:24.504097 CPU_CLUSTER: 0 missing set_resources
8999 20:00:24.510776 Root Device assign_resources, bus 0 link: 0 done
9000 20:00:24.511332 Done setting resources.
9001 20:00:24.517585 Show resources in subtree (Root Device)...After assigning values.
9002 20:00:24.520613 Root Device child on link 0 CPU_CLUSTER: 0
9003 20:00:24.524271 CPU_CLUSTER: 0 child on link 0 CPU: 00
9004 20:00:24.533843 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9005 20:00:24.534408 CPU: 00
9006 20:00:24.536894 Done allocating resources.
9007 20:00:24.540580 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9008 20:00:24.543923 Enabling resources...
9009 20:00:24.544460 done.
9010 20:00:24.550644 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9011 20:00:24.551188 Initializing devices...
9012 20:00:24.553588 Root Device init
9013 20:00:24.554047 init hardware done!
9014 20:00:24.556815 0x00000018: ctrlr->caps
9015 20:00:24.560394 52.000 MHz: ctrlr->f_max
9016 20:00:24.560962 0.400 MHz: ctrlr->f_min
9017 20:00:24.563831 0x40ff8080: ctrlr->voltages
9018 20:00:24.567229 sclk: 390625
9019 20:00:24.567781 Bus Width = 1
9020 20:00:24.568420 sclk: 390625
9021 20:00:24.570180 Bus Width = 1
9022 20:00:24.570641 Early init status = 3
9023 20:00:24.576707 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9024 20:00:24.580278 in-header: 03 fc 00 00 01 00 00 00
9025 20:00:24.580691 in-data: 00
9026 20:00:24.586605 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9027 20:00:24.590784 in-header: 03 fd 00 00 00 00 00 00
9028 20:00:24.594223 in-data:
9029 20:00:24.597374 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9030 20:00:24.602228 in-header: 03 fc 00 00 01 00 00 00
9031 20:00:24.605001 in-data: 00
9032 20:00:24.608280 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9033 20:00:24.613902 in-header: 03 fd 00 00 00 00 00 00
9034 20:00:24.617290 in-data:
9035 20:00:24.620449 [SSUSB] Setting up USB HOST controller...
9036 20:00:24.623947 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9037 20:00:24.626961 [SSUSB] phy power-on done.
9038 20:00:24.630865 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9039 20:00:24.637193 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9040 20:00:24.640577 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9041 20:00:24.647538 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9042 20:00:24.653930 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9043 20:00:24.660161 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9044 20:00:24.667451 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9045 20:00:24.673723 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9046 20:00:24.676826 SPM: binary array size = 0x9dc
9047 20:00:24.680115 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9048 20:00:24.687069 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9049 20:00:24.693606 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9050 20:00:24.699982 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9051 20:00:24.703613 configure_display: Starting display init
9052 20:00:24.737186 anx7625_power_on_init: Init interface.
9053 20:00:24.740519 anx7625_disable_pd_protocol: Disabled PD feature.
9054 20:00:24.743858 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9055 20:00:24.771659 anx7625_start_dp_work: Secure OCM version=00
9056 20:00:24.774989 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9057 20:00:24.789733 sp_tx_get_edid_block: EDID Block = 1
9058 20:00:24.892795 Extracted contents:
9059 20:00:24.895654 header: 00 ff ff ff ff ff ff 00
9060 20:00:24.899008 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9061 20:00:24.902396 version: 01 04
9062 20:00:24.905470 basic params: 95 1f 11 78 0a
9063 20:00:24.908689 chroma info: 76 90 94 55 54 90 27 21 50 54
9064 20:00:24.912037 established: 00 00 00
9065 20:00:24.918735 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9066 20:00:24.924947 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9067 20:00:24.928628 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9068 20:00:24.935294 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9069 20:00:24.941773 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9070 20:00:24.945021 extensions: 00
9071 20:00:24.945477 checksum: fb
9072 20:00:24.945846
9073 20:00:24.948570 Manufacturer: IVO Model 57d Serial Number 0
9074 20:00:24.951809 Made week 0 of 2020
9075 20:00:24.954836 EDID version: 1.4
9076 20:00:24.955296 Digital display
9077 20:00:24.958127 6 bits per primary color channel
9078 20:00:24.958592 DisplayPort interface
9079 20:00:24.961478 Maximum image size: 31 cm x 17 cm
9080 20:00:24.964973 Gamma: 220%
9081 20:00:24.965428 Check DPMS levels
9082 20:00:24.968111 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9083 20:00:24.974964 First detailed timing is preferred timing
9084 20:00:24.975525 Established timings supported:
9085 20:00:24.978151 Standard timings supported:
9086 20:00:24.981349 Detailed timings
9087 20:00:24.984676 Hex of detail: 383680a07038204018303c0035ae10000019
9088 20:00:24.991564 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9089 20:00:24.994854 0780 0798 07c8 0820 hborder 0
9090 20:00:24.997997 0438 043b 0447 0458 vborder 0
9091 20:00:25.001525 -hsync -vsync
9092 20:00:25.002086 Did detailed timing
9093 20:00:25.008120 Hex of detail: 000000000000000000000000000000000000
9094 20:00:25.011392 Manufacturer-specified data, tag 0
9095 20:00:25.014754 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9096 20:00:25.018230 ASCII string: InfoVision
9097 20:00:25.021020 Hex of detail: 000000fe00523134304e574635205248200a
9098 20:00:25.024710 ASCII string: R140NWF5 RH
9099 20:00:25.025272 Checksum
9100 20:00:25.027865 Checksum: 0xfb (valid)
9101 20:00:25.031055 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9102 20:00:25.034288 DSI data_rate: 832800000 bps
9103 20:00:25.040978 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9104 20:00:25.044140 anx7625_parse_edid: pixelclock(138800).
9105 20:00:25.047741 hactive(1920), hsync(48), hfp(24), hbp(88)
9106 20:00:25.051118 vactive(1080), vsync(12), vfp(3), vbp(17)
9107 20:00:25.054186 anx7625_dsi_config: config dsi.
9108 20:00:25.060795 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9109 20:00:25.074534 anx7625_dsi_config: success to config DSI
9110 20:00:25.078188 anx7625_dp_start: MIPI phy setup OK.
9111 20:00:25.080842 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9112 20:00:25.084039 mtk_ddp_mode_set invalid vrefresh 60
9113 20:00:25.087592 main_disp_path_setup
9114 20:00:25.088145 ovl_layer_smi_id_en
9115 20:00:25.090679 ovl_layer_smi_id_en
9116 20:00:25.091236 ccorr_config
9117 20:00:25.091652 aal_config
9118 20:00:25.094179 gamma_config
9119 20:00:25.094737 postmask_config
9120 20:00:25.097349 dither_config
9121 20:00:25.100733 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9122 20:00:25.107377 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9123 20:00:25.110916 Root Device init finished in 554 msecs
9124 20:00:25.113813 CPU_CLUSTER: 0 init
9125 20:00:25.120818 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9126 20:00:25.124152 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9127 20:00:25.127447 APU_MBOX 0x190000b0 = 0x10001
9128 20:00:25.130953 APU_MBOX 0x190001b0 = 0x10001
9129 20:00:25.134423 APU_MBOX 0x190005b0 = 0x10001
9130 20:00:25.137375 APU_MBOX 0x190006b0 = 0x10001
9131 20:00:25.140689 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9132 20:00:25.153055 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9133 20:00:25.165831 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9134 20:00:25.172166 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9135 20:00:25.183978 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9136 20:00:25.193034 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9137 20:00:25.196761 CPU_CLUSTER: 0 init finished in 81 msecs
9138 20:00:25.199497 Devices initialized
9139 20:00:25.203211 Show all devs... After init.
9140 20:00:25.203773 Root Device: enabled 1
9141 20:00:25.206359 CPU_CLUSTER: 0: enabled 1
9142 20:00:25.209411 CPU: 00: enabled 1
9143 20:00:25.213051 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9144 20:00:25.216070 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9145 20:00:25.219657 ELOG: NV offset 0x57f000 size 0x1000
9146 20:00:25.225909 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9147 20:00:25.232866 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9148 20:00:25.235969 ELOG: Event(17) added with size 13 at 2023-10-28 20:00:25 UTC
9149 20:00:25.242608 out: cmd=0x121: 03 db 21 01 00 00 00 00
9150 20:00:25.245702 in-header: 03 e1 00 00 2c 00 00 00
9151 20:00:25.259127 in-data: 82 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9152 20:00:25.262205 ELOG: Event(A1) added with size 10 at 2023-10-28 20:00:25 UTC
9153 20:00:25.269076 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9154 20:00:25.275897 ELOG: Event(A0) added with size 9 at 2023-10-28 20:00:25 UTC
9155 20:00:25.279262 elog_add_boot_reason: Logged dev mode boot
9156 20:00:25.285639 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9157 20:00:25.286197 Finalize devices...
9158 20:00:25.288840 Devices finalized
9159 20:00:25.292490 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9160 20:00:25.295489 Writing coreboot table at 0xffe64000
9161 20:00:25.302205 0. 000000000010a000-0000000000113fff: RAMSTAGE
9162 20:00:25.305686 1. 0000000040000000-00000000400fffff: RAM
9163 20:00:25.308905 2. 0000000040100000-000000004032afff: RAMSTAGE
9164 20:00:25.312225 3. 000000004032b000-00000000545fffff: RAM
9165 20:00:25.315434 4. 0000000054600000-000000005465ffff: BL31
9166 20:00:25.318731 5. 0000000054660000-00000000ffe63fff: RAM
9167 20:00:25.325438 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9168 20:00:25.328631 7. 0000000100000000-000000013fffffff: RAM
9169 20:00:25.331995 Passing 5 GPIOs to payload:
9170 20:00:25.335472 NAME | PORT | POLARITY | VALUE
9171 20:00:25.342192 EC in RW | 0x000000aa | low | undefined
9172 20:00:25.345027 EC interrupt | 0x00000005 | low | undefined
9173 20:00:25.352139 TPM interrupt | 0x000000ab | high | undefined
9174 20:00:25.355239 SD card detect | 0x00000011 | high | undefined
9175 20:00:25.358659 speaker enable | 0x00000093 | high | undefined
9176 20:00:25.361417 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9177 20:00:25.365082 in-header: 03 f8 00 00 02 00 00 00
9178 20:00:25.368485 in-data: 03 00
9179 20:00:25.372066 ADC[4]: Raw value=668222 ID=5
9180 20:00:25.375201 ADC[3]: Raw value=212917 ID=1
9181 20:00:25.375767 RAM Code: 0x51
9182 20:00:25.379280 ADC[6]: Raw value=74410 ID=0
9183 20:00:25.381790 ADC[5]: Raw value=211812 ID=1
9184 20:00:25.382258 SKU Code: 0x1
9185 20:00:25.388244 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3418
9186 20:00:25.388712 coreboot table: 964 bytes.
9187 20:00:25.392072 IMD ROOT 0. 0xfffff000 0x00001000
9188 20:00:25.395162 IMD SMALL 1. 0xffffe000 0x00001000
9189 20:00:25.398485 RO MCACHE 2. 0xffffc000 0x00001104
9190 20:00:25.401689 CONSOLE 3. 0xfff7c000 0x00080000
9191 20:00:25.405350 FMAP 4. 0xfff7b000 0x00000452
9192 20:00:25.408367 TIME STAMP 5. 0xfff7a000 0x00000910
9193 20:00:25.411869 VBOOT WORK 6. 0xfff66000 0x00014000
9194 20:00:25.415039 RAMOOPS 7. 0xffe66000 0x00100000
9195 20:00:25.418593 COREBOOT 8. 0xffe64000 0x00002000
9196 20:00:25.421980 IMD small region:
9197 20:00:25.425222 IMD ROOT 0. 0xffffec00 0x00000400
9198 20:00:25.428501 VPD 1. 0xffffeb80 0x0000006c
9199 20:00:25.431421 MMC STATUS 2. 0xffffeb60 0x00000004
9200 20:00:25.434986 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9201 20:00:25.437949 Probing TPM: done!
9202 20:00:25.441859 Connected to device vid:did:rid of 1ae0:0028:00
9203 20:00:25.452616 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9204 20:00:25.456071 Initialized TPM device CR50 revision 0
9205 20:00:25.459598 Checking cr50 for pending updates
9206 20:00:25.463202 Reading cr50 TPM mode
9207 20:00:25.471947 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9208 20:00:25.479184 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9209 20:00:25.518966 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9210 20:00:25.522408 Checking segment from ROM address 0x40100000
9211 20:00:25.525610 Checking segment from ROM address 0x4010001c
9212 20:00:25.532053 Loading segment from ROM address 0x40100000
9213 20:00:25.532670 code (compression=0)
9214 20:00:25.541977 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9215 20:00:25.548619 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9216 20:00:25.549188 it's not compressed!
9217 20:00:25.555350 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9218 20:00:25.561567 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9219 20:00:25.579244 Loading segment from ROM address 0x4010001c
9220 20:00:25.579802 Entry Point 0x80000000
9221 20:00:25.582760 Loaded segments
9222 20:00:25.585873 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9223 20:00:25.592441 Jumping to boot code at 0x80000000(0xffe64000)
9224 20:00:25.598923 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9225 20:00:25.605370 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9226 20:00:25.613321 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9227 20:00:25.616667 Checking segment from ROM address 0x40100000
9228 20:00:25.620159 Checking segment from ROM address 0x4010001c
9229 20:00:25.626859 Loading segment from ROM address 0x40100000
9230 20:00:25.627412 code (compression=1)
9231 20:00:25.633529 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9232 20:00:25.643588 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9233 20:00:25.644252 using LZMA
9234 20:00:25.652055 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9235 20:00:25.658481 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9236 20:00:25.662151 Loading segment from ROM address 0x4010001c
9237 20:00:25.662766 Entry Point 0x54601000
9238 20:00:25.665050 Loaded segments
9239 20:00:25.668169 NOTICE: MT8192 bl31_setup
9240 20:00:25.675592 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9241 20:00:25.678805 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9242 20:00:25.682302 WARNING: region 0:
9243 20:00:25.685202 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9244 20:00:25.685675 WARNING: region 1:
9245 20:00:25.692073 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9246 20:00:25.695522 WARNING: region 2:
9247 20:00:25.699137 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9248 20:00:25.701882 WARNING: region 3:
9249 20:00:25.705245 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9250 20:00:25.708708 WARNING: region 4:
9251 20:00:25.715374 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9252 20:00:25.715934 WARNING: region 5:
9253 20:00:25.718652 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9254 20:00:25.722175 WARNING: region 6:
9255 20:00:25.725539 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9256 20:00:25.729131 WARNING: region 7:
9257 20:00:25.732102 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9258 20:00:25.738950 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9259 20:00:25.742408 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9260 20:00:25.745492 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9261 20:00:25.752308 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9262 20:00:25.755462 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9263 20:00:25.759002 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9264 20:00:25.765543 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9265 20:00:25.768996 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9266 20:00:25.775300 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9267 20:00:25.778656 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9268 20:00:25.782225 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9269 20:00:25.788964 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9270 20:00:25.792292 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9271 20:00:25.795123 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9272 20:00:25.801906 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9273 20:00:25.805264 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9274 20:00:25.811819 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9275 20:00:25.815703 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9276 20:00:25.818798 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9277 20:00:25.825362 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9278 20:00:25.829125 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9279 20:00:25.831994 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9280 20:00:25.838661 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9281 20:00:25.841861 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9282 20:00:25.848542 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9283 20:00:25.851692 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9284 20:00:25.855286 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9285 20:00:25.861593 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9286 20:00:25.865460 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9287 20:00:25.871769 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9288 20:00:25.875397 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9289 20:00:25.878825 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9290 20:00:25.885150 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9291 20:00:25.888487 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9292 20:00:25.891977 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9293 20:00:25.895365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9294 20:00:25.902248 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9295 20:00:25.905374 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9296 20:00:25.908818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9297 20:00:25.912114 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9298 20:00:25.918360 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9299 20:00:25.922229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9300 20:00:25.925553 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9301 20:00:25.928703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9302 20:00:25.935094 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9303 20:00:25.938782 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9304 20:00:25.942159 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9305 20:00:25.945089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9306 20:00:25.951818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9307 20:00:25.954993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9308 20:00:25.961986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9309 20:00:25.965234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9310 20:00:25.972010 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9311 20:00:25.975402 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9312 20:00:25.978702 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9313 20:00:25.985221 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9314 20:00:25.988496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9315 20:00:25.995233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9316 20:00:25.998619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9317 20:00:26.002163 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9318 20:00:26.008805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9319 20:00:26.011959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9320 20:00:26.019027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9321 20:00:26.021819 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9322 20:00:26.028625 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9323 20:00:26.031698 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9324 20:00:26.038773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9325 20:00:26.041745 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9326 20:00:26.044817 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9327 20:00:26.051781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9328 20:00:26.054934 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9329 20:00:26.061777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9330 20:00:26.064856 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9331 20:00:26.071757 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9332 20:00:26.075059 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9333 20:00:26.077967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9334 20:00:26.084768 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9335 20:00:26.088634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9336 20:00:26.094980 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9337 20:00:26.098420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9338 20:00:26.105544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9339 20:00:26.108864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9340 20:00:26.112333 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9341 20:00:26.118520 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9342 20:00:26.121832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9343 20:00:26.128412 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9344 20:00:26.132090 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9345 20:00:26.138320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9346 20:00:26.141939 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9347 20:00:26.145107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9348 20:00:26.151805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9349 20:00:26.155204 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9350 20:00:26.161500 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9351 20:00:26.165103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9352 20:00:26.171553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9353 20:00:26.174835 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9354 20:00:26.178250 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9355 20:00:26.185088 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9356 20:00:26.188535 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9357 20:00:26.191749 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9358 20:00:26.195134 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9359 20:00:26.201952 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9360 20:00:26.205251 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9361 20:00:26.211875 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9362 20:00:26.215083 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9363 20:00:26.218429 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9364 20:00:26.225401 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9365 20:00:26.228298 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9366 20:00:26.235094 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9367 20:00:26.238616 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9368 20:00:26.242083 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9369 20:00:26.248344 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9370 20:00:26.252079 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9371 20:00:26.258451 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9372 20:00:26.261645 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9373 20:00:26.264976 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9374 20:00:26.268253 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9375 20:00:26.274797 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9376 20:00:26.278405 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9377 20:00:26.281802 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9378 20:00:26.288476 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9379 20:00:26.291971 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9380 20:00:26.295012 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9381 20:00:26.298270 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9382 20:00:26.305104 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9383 20:00:26.308574 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9384 20:00:26.315454 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9385 20:00:26.318554 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9386 20:00:26.321985 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9387 20:00:26.328509 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9388 20:00:26.332154 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9389 20:00:26.335239 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9390 20:00:26.341856 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9391 20:00:26.345094 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9392 20:00:26.351542 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9393 20:00:26.355094 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9394 20:00:26.358145 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9395 20:00:26.364765 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9396 20:00:26.368349 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9397 20:00:26.375156 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9398 20:00:26.378250 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9399 20:00:26.381845 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9400 20:00:26.388216 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9401 20:00:26.391454 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9402 20:00:26.398194 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9403 20:00:26.401257 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9404 20:00:26.405071 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9405 20:00:26.411572 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9406 20:00:26.414948 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9407 20:00:26.421949 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9408 20:00:26.424806 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9409 20:00:26.428288 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9410 20:00:26.434783 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9411 20:00:26.438273 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9412 20:00:26.441475 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9413 20:00:26.448218 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9414 20:00:26.451579 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9415 20:00:26.458452 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9416 20:00:26.461330 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9417 20:00:26.464639 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9418 20:00:26.471628 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9419 20:00:26.474696 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9420 20:00:26.481373 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9421 20:00:26.484709 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9422 20:00:26.488075 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9423 20:00:26.494695 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9424 20:00:26.497864 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9425 20:00:26.501372 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9426 20:00:26.507899 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9427 20:00:26.511197 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9428 20:00:26.518031 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9429 20:00:26.521231 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9430 20:00:26.524503 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9431 20:00:26.531195 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9432 20:00:26.534665 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9433 20:00:26.541135 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9434 20:00:26.544371 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9435 20:00:26.547405 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9436 20:00:26.554317 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9437 20:00:26.557657 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9438 20:00:26.564071 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9439 20:00:26.567731 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9440 20:00:26.571047 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9441 20:00:26.577456 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9442 20:00:26.580828 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9443 20:00:26.587484 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9444 20:00:26.590580 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9445 20:00:26.594004 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9446 20:00:26.600947 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9447 20:00:26.603726 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9448 20:00:26.610581 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9449 20:00:26.613651 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9450 20:00:26.620577 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9451 20:00:26.623583 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9452 20:00:26.627052 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9453 20:00:26.634105 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9454 20:00:26.636975 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9455 20:00:26.643546 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9456 20:00:26.646998 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9457 20:00:26.650230 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9458 20:00:26.656911 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9459 20:00:26.660349 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9460 20:00:26.666776 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9461 20:00:26.670022 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9462 20:00:26.676419 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9463 20:00:26.680074 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9464 20:00:26.683564 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9465 20:00:26.689947 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9466 20:00:26.693104 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9467 20:00:26.699881 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9468 20:00:26.702978 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9469 20:00:26.706808 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9470 20:00:26.713103 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9471 20:00:26.716482 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9472 20:00:26.723230 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9473 20:00:26.726602 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9474 20:00:26.732758 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9475 20:00:26.736021 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9476 20:00:26.739950 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9477 20:00:26.745976 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9478 20:00:26.749275 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9479 20:00:26.755948 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9480 20:00:26.759368 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9481 20:00:26.765880 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9482 20:00:26.769535 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9483 20:00:26.772522 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9484 20:00:26.779318 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9485 20:00:26.782842 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9486 20:00:26.789300 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9487 20:00:26.792502 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9488 20:00:26.796284 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9489 20:00:26.799449 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9490 20:00:26.802764 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9491 20:00:26.809122 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9492 20:00:26.812088 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9493 20:00:26.819176 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9494 20:00:26.822373 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9495 20:00:26.825634 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9496 20:00:26.832390 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9497 20:00:26.835394 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9498 20:00:26.838829 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9499 20:00:26.845564 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9500 20:00:26.848564 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9501 20:00:26.852285 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9502 20:00:26.858786 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9503 20:00:26.862294 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9504 20:00:26.868730 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9505 20:00:26.872211 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9506 20:00:26.875085 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9507 20:00:26.882091 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9508 20:00:26.884973 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9509 20:00:26.891537 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9510 20:00:26.895377 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9511 20:00:26.898419 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9512 20:00:26.904976 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9513 20:00:26.908051 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9514 20:00:26.911477 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9515 20:00:26.917988 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9516 20:00:26.921575 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9517 20:00:26.924762 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9518 20:00:26.931437 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9519 20:00:26.934710 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9520 20:00:26.941357 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9521 20:00:26.944380 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9522 20:00:26.947658 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9523 20:00:26.954447 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9524 20:00:26.958232 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9525 20:00:26.964411 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9526 20:00:26.967564 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9527 20:00:26.971095 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9528 20:00:26.974035 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9529 20:00:26.977685 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9530 20:00:26.984501 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9531 20:00:26.987668 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9532 20:00:26.990894 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9533 20:00:26.994091 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9534 20:00:27.000753 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9535 20:00:27.003808 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9536 20:00:27.007157 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9537 20:00:27.010685 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9538 20:00:27.016926 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9539 20:00:27.020413 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9540 20:00:27.023585 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9541 20:00:27.030136 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9542 20:00:27.033848 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9543 20:00:27.040520 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9544 20:00:27.043488 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9545 20:00:27.049942 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9546 20:00:27.053977 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9547 20:00:27.056525 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9548 20:00:27.063469 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9549 20:00:27.066840 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9550 20:00:27.073460 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9551 20:00:27.076613 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9552 20:00:27.083677 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9553 20:00:27.086983 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9554 20:00:27.090181 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9555 20:00:27.096935 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9556 20:00:27.099893 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9557 20:00:27.106739 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9558 20:00:27.109870 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9559 20:00:27.113108 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9560 20:00:27.119907 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9561 20:00:27.123279 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9562 20:00:27.129752 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9563 20:00:27.132910 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9564 20:00:27.136168 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9565 20:00:27.142895 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9566 20:00:27.146060 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9567 20:00:27.153104 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9568 20:00:27.156350 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9569 20:00:27.162839 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9570 20:00:27.165898 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9571 20:00:27.169508 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9572 20:00:27.175997 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9573 20:00:27.179564 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9574 20:00:27.185827 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9575 20:00:27.189468 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9576 20:00:27.192708 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9577 20:00:27.199174 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9578 20:00:27.202939 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9579 20:00:27.209124 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9580 20:00:27.212777 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9581 20:00:27.216270 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9582 20:00:27.222583 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9583 20:00:27.225863 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9584 20:00:27.232285 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9585 20:00:27.235592 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9586 20:00:27.242426 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9587 20:00:27.245266 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9588 20:00:27.249073 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9589 20:00:27.255706 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9590 20:00:27.258603 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9591 20:00:27.265270 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9592 20:00:27.268483 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9593 20:00:27.271956 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9594 20:00:27.278700 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9595 20:00:27.282111 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9596 20:00:27.288649 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9597 20:00:27.291862 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9598 20:00:27.294963 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9599 20:00:27.301897 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9600 20:00:27.305015 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9601 20:00:27.312045 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9602 20:00:27.315235 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9603 20:00:27.318457 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9604 20:00:27.325232 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9605 20:00:27.328389 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9606 20:00:27.334911 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9607 20:00:27.338375 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9608 20:00:27.344823 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9609 20:00:27.348384 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9610 20:00:27.351501 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9611 20:00:27.358476 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9612 20:00:27.361473 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9613 20:00:27.368080 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9614 20:00:27.371409 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9615 20:00:27.378061 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9616 20:00:27.381110 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9617 20:00:27.384553 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9618 20:00:27.391491 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9619 20:00:27.394181 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9620 20:00:27.401130 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9621 20:00:27.404848 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9622 20:00:27.411073 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9623 20:00:27.414569 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9624 20:00:27.421167 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9625 20:00:27.424234 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9626 20:00:27.427702 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9627 20:00:27.434400 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9628 20:00:27.437425 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9629 20:00:27.444007 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9630 20:00:27.447422 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9631 20:00:27.454264 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9632 20:00:27.457756 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9633 20:00:27.460917 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9634 20:00:27.467354 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9635 20:00:27.470479 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9636 20:00:27.477219 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9637 20:00:27.480317 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9638 20:00:27.487409 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9639 20:00:27.490452 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9640 20:00:27.497144 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9641 20:00:27.500603 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9642 20:00:27.503680 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9643 20:00:27.510433 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9644 20:00:27.513598 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9645 20:00:27.520149 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9646 20:00:27.523619 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9647 20:00:27.530360 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9648 20:00:27.533495 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9649 20:00:27.540229 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9650 20:00:27.543560 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9651 20:00:27.546656 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9652 20:00:27.553245 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9653 20:00:27.556566 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9654 20:00:27.563388 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9655 20:00:27.566572 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9656 20:00:27.573256 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9657 20:00:27.576534 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9658 20:00:27.583560 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9659 20:00:27.586224 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9660 20:00:27.589500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9661 20:00:27.596137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9662 20:00:27.599882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9663 20:00:27.606367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9664 20:00:27.609298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9665 20:00:27.616092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9666 20:00:27.619250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9667 20:00:27.622865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9668 20:00:27.629507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9669 20:00:27.632769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9670 20:00:27.639268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9671 20:00:27.642728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9672 20:00:27.648899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9673 20:00:27.652629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9674 20:00:27.659133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9675 20:00:27.662121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9676 20:00:27.668803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9677 20:00:27.672216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9678 20:00:27.679213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9679 20:00:27.682318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9680 20:00:27.688713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9681 20:00:27.692042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9682 20:00:27.699065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9683 20:00:27.702322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9684 20:00:27.708998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9685 20:00:27.711923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9686 20:00:27.718841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9687 20:00:27.722129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9688 20:00:27.728557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9689 20:00:27.732439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9690 20:00:27.738759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9691 20:00:27.741838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9692 20:00:27.748885 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9693 20:00:27.749458 INFO: [APUAPC] vio 0
9694 20:00:27.754953 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9695 20:00:27.759042 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9696 20:00:27.762216 INFO: [APUAPC] D0_APC_0: 0x400510
9697 20:00:27.765426 INFO: [APUAPC] D0_APC_1: 0x0
9698 20:00:27.768829 INFO: [APUAPC] D0_APC_2: 0x1540
9699 20:00:27.772264 INFO: [APUAPC] D0_APC_3: 0x0
9700 20:00:27.775485 INFO: [APUAPC] D1_APC_0: 0xffffffff
9701 20:00:27.778563 INFO: [APUAPC] D1_APC_1: 0xffffffff
9702 20:00:27.782178 INFO: [APUAPC] D1_APC_2: 0x3fffff
9703 20:00:27.785621 INFO: [APUAPC] D1_APC_3: 0x0
9704 20:00:27.788718 INFO: [APUAPC] D2_APC_0: 0xffffffff
9705 20:00:27.791909 INFO: [APUAPC] D2_APC_1: 0xffffffff
9706 20:00:27.795184 INFO: [APUAPC] D2_APC_2: 0x3fffff
9707 20:00:27.798665 INFO: [APUAPC] D2_APC_3: 0x0
9708 20:00:27.801479 INFO: [APUAPC] D3_APC_0: 0xffffffff
9709 20:00:27.804883 INFO: [APUAPC] D3_APC_1: 0xffffffff
9710 20:00:27.808508 INFO: [APUAPC] D3_APC_2: 0x3fffff
9711 20:00:27.812004 INFO: [APUAPC] D3_APC_3: 0x0
9712 20:00:27.814992 INFO: [APUAPC] D4_APC_0: 0xffffffff
9713 20:00:27.818752 INFO: [APUAPC] D4_APC_1: 0xffffffff
9714 20:00:27.821509 INFO: [APUAPC] D4_APC_2: 0x3fffff
9715 20:00:27.821972 INFO: [APUAPC] D4_APC_3: 0x0
9716 20:00:27.828143 INFO: [APUAPC] D5_APC_0: 0xffffffff
9717 20:00:27.831608 INFO: [APUAPC] D5_APC_1: 0xffffffff
9718 20:00:27.835002 INFO: [APUAPC] D5_APC_2: 0x3fffff
9719 20:00:27.835458 INFO: [APUAPC] D5_APC_3: 0x0
9720 20:00:27.837970 INFO: [APUAPC] D6_APC_0: 0xffffffff
9721 20:00:27.841297 INFO: [APUAPC] D6_APC_1: 0xffffffff
9722 20:00:27.844718 INFO: [APUAPC] D6_APC_2: 0x3fffff
9723 20:00:27.848097 INFO: [APUAPC] D6_APC_3: 0x0
9724 20:00:27.851413 INFO: [APUAPC] D7_APC_0: 0xffffffff
9725 20:00:27.854609 INFO: [APUAPC] D7_APC_1: 0xffffffff
9726 20:00:27.857760 INFO: [APUAPC] D7_APC_2: 0x3fffff
9727 20:00:27.860868 INFO: [APUAPC] D7_APC_3: 0x0
9728 20:00:27.864345 INFO: [APUAPC] D8_APC_0: 0xffffffff
9729 20:00:27.867551 INFO: [APUAPC] D8_APC_1: 0xffffffff
9730 20:00:27.870751 INFO: [APUAPC] D8_APC_2: 0x3fffff
9731 20:00:27.873968 INFO: [APUAPC] D8_APC_3: 0x0
9732 20:00:27.877521 INFO: [APUAPC] D9_APC_0: 0xffffffff
9733 20:00:27.880758 INFO: [APUAPC] D9_APC_1: 0xffffffff
9734 20:00:27.884369 INFO: [APUAPC] D9_APC_2: 0x3fffff
9735 20:00:27.887838 INFO: [APUAPC] D9_APC_3: 0x0
9736 20:00:27.891028 INFO: [APUAPC] D10_APC_0: 0xffffffff
9737 20:00:27.894081 INFO: [APUAPC] D10_APC_1: 0xffffffff
9738 20:00:27.897739 INFO: [APUAPC] D10_APC_2: 0x3fffff
9739 20:00:27.900579 INFO: [APUAPC] D10_APC_3: 0x0
9740 20:00:27.903940 INFO: [APUAPC] D11_APC_0: 0xffffffff
9741 20:00:27.907721 INFO: [APUAPC] D11_APC_1: 0xffffffff
9742 20:00:27.910976 INFO: [APUAPC] D11_APC_2: 0x3fffff
9743 20:00:27.913952 INFO: [APUAPC] D11_APC_3: 0x0
9744 20:00:27.917350 INFO: [APUAPC] D12_APC_0: 0xffffffff
9745 20:00:27.920831 INFO: [APUAPC] D12_APC_1: 0xffffffff
9746 20:00:27.924210 INFO: [APUAPC] D12_APC_2: 0x3fffff
9747 20:00:27.927877 INFO: [APUAPC] D12_APC_3: 0x0
9748 20:00:27.931104 INFO: [APUAPC] D13_APC_0: 0xffffffff
9749 20:00:27.934496 INFO: [APUAPC] D13_APC_1: 0xffffffff
9750 20:00:27.937536 INFO: [APUAPC] D13_APC_2: 0x3fffff
9751 20:00:27.940689 INFO: [APUAPC] D13_APC_3: 0x0
9752 20:00:27.944442 INFO: [APUAPC] D14_APC_0: 0xffffffff
9753 20:00:27.947876 INFO: [APUAPC] D14_APC_1: 0xffffffff
9754 20:00:27.950650 INFO: [APUAPC] D14_APC_2: 0x3fffff
9755 20:00:27.954322 INFO: [APUAPC] D14_APC_3: 0x0
9756 20:00:27.957302 INFO: [APUAPC] D15_APC_0: 0xffffffff
9757 20:00:27.960556 INFO: [APUAPC] D15_APC_1: 0xffffffff
9758 20:00:27.964219 INFO: [APUAPC] D15_APC_2: 0x3fffff
9759 20:00:27.967290 INFO: [APUAPC] D15_APC_3: 0x0
9760 20:00:27.970680 INFO: [APUAPC] APC_CON: 0x4
9761 20:00:27.974135 INFO: [NOCDAPC] D0_APC_0: 0x0
9762 20:00:27.977223 INFO: [NOCDAPC] D0_APC_1: 0x0
9763 20:00:27.980491 INFO: [NOCDAPC] D1_APC_0: 0x0
9764 20:00:27.984246 INFO: [NOCDAPC] D1_APC_1: 0xfff
9765 20:00:27.987569 INFO: [NOCDAPC] D2_APC_0: 0x0
9766 20:00:27.990640 INFO: [NOCDAPC] D2_APC_1: 0xfff
9767 20:00:27.991205 INFO: [NOCDAPC] D3_APC_0: 0x0
9768 20:00:27.993758 INFO: [NOCDAPC] D3_APC_1: 0xfff
9769 20:00:27.996962 INFO: [NOCDAPC] D4_APC_0: 0x0
9770 20:00:28.000433 INFO: [NOCDAPC] D4_APC_1: 0xfff
9771 20:00:28.003925 INFO: [NOCDAPC] D5_APC_0: 0x0
9772 20:00:28.006930 INFO: [NOCDAPC] D5_APC_1: 0xfff
9773 20:00:28.010648 INFO: [NOCDAPC] D6_APC_0: 0x0
9774 20:00:28.013439 INFO: [NOCDAPC] D6_APC_1: 0xfff
9775 20:00:28.016933 INFO: [NOCDAPC] D7_APC_0: 0x0
9776 20:00:28.020592 INFO: [NOCDAPC] D7_APC_1: 0xfff
9777 20:00:28.023479 INFO: [NOCDAPC] D8_APC_0: 0x0
9778 20:00:28.027202 INFO: [NOCDAPC] D8_APC_1: 0xfff
9779 20:00:28.027762 INFO: [NOCDAPC] D9_APC_0: 0x0
9780 20:00:28.030214 INFO: [NOCDAPC] D9_APC_1: 0xfff
9781 20:00:28.033719 INFO: [NOCDAPC] D10_APC_0: 0x0
9782 20:00:28.037112 INFO: [NOCDAPC] D10_APC_1: 0xfff
9783 20:00:28.040426 INFO: [NOCDAPC] D11_APC_0: 0x0
9784 20:00:28.043514 INFO: [NOCDAPC] D11_APC_1: 0xfff
9785 20:00:28.046935 INFO: [NOCDAPC] D12_APC_0: 0x0
9786 20:00:28.050045 INFO: [NOCDAPC] D12_APC_1: 0xfff
9787 20:00:28.053303 INFO: [NOCDAPC] D13_APC_0: 0x0
9788 20:00:28.056646 INFO: [NOCDAPC] D13_APC_1: 0xfff
9789 20:00:28.060169 INFO: [NOCDAPC] D14_APC_0: 0x0
9790 20:00:28.063262 INFO: [NOCDAPC] D14_APC_1: 0xfff
9791 20:00:28.066747 INFO: [NOCDAPC] D15_APC_0: 0x0
9792 20:00:28.069753 INFO: [NOCDAPC] D15_APC_1: 0xfff
9793 20:00:28.070426 INFO: [NOCDAPC] APC_CON: 0x4
9794 20:00:28.073059 INFO: [APUAPC] set_apusys_apc done
9795 20:00:28.076302 INFO: [DEVAPC] devapc_init done
9796 20:00:28.083008 INFO: GICv3 without legacy support detected.
9797 20:00:28.086614 INFO: ARM GICv3 driver initialized in EL3
9798 20:00:28.089502 INFO: Maximum SPI INTID supported: 639
9799 20:00:28.092834 INFO: BL31: Initializing runtime services
9800 20:00:28.099882 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9801 20:00:28.103465 INFO: SPM: enable CPC mode
9802 20:00:28.106375 INFO: mcdi ready for mcusys-off-idle and system suspend
9803 20:00:28.113098 INFO: BL31: Preparing for EL3 exit to normal world
9804 20:00:28.116120 INFO: Entry point address = 0x80000000
9805 20:00:28.116731 INFO: SPSR = 0x8
9806 20:00:28.123558
9807 20:00:28.124122
9808 20:00:28.124535
9809 20:00:28.126571 Starting depthcharge on Spherion...
9810 20:00:28.127134
9811 20:00:28.127505 Wipe memory regions:
9812 20:00:28.127848
9813 20:00:28.130590 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9814 20:00:28.131129 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9815 20:00:28.131602 Setting prompt string to ['asurada:']
9816 20:00:28.132044 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9817 20:00:28.132800 [0x00000040000000, 0x00000054600000)
9818 20:00:28.252431
9819 20:00:28.252976 [0x00000054660000, 0x00000080000000)
9820 20:00:28.512904
9821 20:00:28.513452 [0x000000821a7280, 0x000000ffe64000)
9822 20:00:29.257986
9823 20:00:29.258539 [0x00000100000000, 0x00000140000000)
9824 20:00:29.638822
9825 20:00:29.642127 Initializing XHCI USB controller at 0x11200000.
9826 20:00:30.680013
9827 20:00:30.683209 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9828 20:00:30.683760
9829 20:00:30.684122
9830 20:00:30.684508
9831 20:00:30.685356 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9833 20:00:30.787000 asurada: tftpboot 192.168.201.1 11899595/tftp-deploy-c1ag_fai/kernel/image.itb 11899595/tftp-deploy-c1ag_fai/kernel/cmdline
9834 20:00:30.787641 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9835 20:00:30.788085 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9836 20:00:30.792733 tftpboot 192.168.201.1 11899595/tftp-deploy-c1ag_fai/kernel/image.itp-deploy-c1ag_fai/kernel/cmdline
9837 20:00:30.793196
9838 20:00:30.793557 Waiting for link
9839 20:00:30.953456
9840 20:00:30.954011 R8152: Initializing
9841 20:00:30.954379
9842 20:00:30.956799 Version 9 (ocp_data = 6010)
9843 20:00:30.957350
9844 20:00:30.959990 R8152: Done initializing
9845 20:00:30.960593
9846 20:00:30.960957 Adding net device
9847 20:00:33.093159
9848 20:00:33.093720 done.
9849 20:00:33.094086
9850 20:00:33.094425 MAC: 00:e0:4c:68:03:bd
9851 20:00:33.094752
9852 20:00:33.096348 Sending DHCP discover... done.
9853 20:00:33.096818
9854 20:00:43.062346 Waiting for reply... R8152: Bulk read error 0xffffffbf
9855 20:00:43.062963
9856 20:00:43.065658 Receive failed.
9857 20:00:43.066231
9858 20:00:43.066772 done.
9859 20:00:43.067128
9860 20:00:43.068656 Sending DHCP request... done.
9861 20:00:43.069115
9862 20:00:43.076620 Waiting for reply... done.
9863 20:00:43.077080
9864 20:00:43.077443 My ip is 192.168.201.16
9865 20:00:43.077781
9866 20:00:43.079960 The DHCP server ip is 192.168.201.1
9867 20:00:43.080478
9868 20:00:43.086499 TFTP server IP predefined by user: 192.168.201.1
9869 20:00:43.087055
9870 20:00:43.093333 Bootfile predefined by user: 11899595/tftp-deploy-c1ag_fai/kernel/image.itb
9871 20:00:43.093897
9872 20:00:43.096294 Sending tftp read request... done.
9873 20:00:43.096770
9874 20:00:43.102735 Waiting for the transfer...
9875 20:00:43.103241
9876 20:00:43.493420 00000000 ################################################################
9877 20:00:43.493928
9878 20:00:43.899247 00080000 ################################################################
9879 20:00:43.899893
9880 20:00:44.297049 00100000 ################################################################
9881 20:00:44.297553
9882 20:00:44.698909 00180000 ################################################################
9883 20:00:44.699411
9884 20:00:45.101404 00200000 ################################################################
9885 20:00:45.101922
9886 20:00:45.501158 00280000 ################################################################
9887 20:00:45.501675
9888 20:00:45.883414 00300000 ################################################################
9889 20:00:45.883911
9890 20:00:46.304090 00380000 ################################################################
9891 20:00:46.304634
9892 20:00:46.741589 00400000 ################################################################
9893 20:00:46.742089
9894 20:00:47.148628 00480000 ################################################################
9895 20:00:47.149124
9896 20:00:47.538528 00500000 ################################################################
9897 20:00:47.539245
9898 20:00:47.859355 00580000 ################################################################
9899 20:00:47.859497
9900 20:00:48.251470 00600000 ################################################################
9901 20:00:48.252143
9902 20:00:48.643383 00680000 ################################################################
9903 20:00:48.643877
9904 20:00:49.046498 00700000 ################################################################
9905 20:00:49.047077
9906 20:00:49.437394 00780000 ################################################################
9907 20:00:49.438033
9908 20:00:49.829598 00800000 ################################################################
9909 20:00:49.830157
9910 20:00:50.231973 00880000 ################################################################
9911 20:00:50.232618
9912 20:00:50.631562 00900000 ################################################################
9913 20:00:50.632058
9914 20:00:51.037494 00980000 ################################################################
9915 20:00:51.038021
9916 20:00:51.449099 00a00000 ################################################################
9917 20:00:51.449668
9918 20:00:51.894085 00a80000 ################################################################
9919 20:00:51.894597
9920 20:00:52.303712 00b00000 ################################################################
9921 20:00:52.304252
9922 20:00:52.712079 00b80000 ################################################################
9923 20:00:52.712663
9924 20:00:53.099889 00c00000 ################################################################
9925 20:00:53.100497
9926 20:00:53.509627 00c80000 ################################################################
9927 20:00:53.510147
9928 20:00:53.924796 00d00000 ################################################################
9929 20:00:53.925386
9930 20:00:54.345590 00d80000 ################################################################
9931 20:00:54.346141
9932 20:00:54.690221 00e00000 ################################################################
9933 20:00:54.690371
9934 20:00:54.985904 00e80000 ################################################################
9935 20:00:54.986040
9936 20:00:55.289501 00f00000 ################################################################
9937 20:00:55.289633
9938 20:00:55.592027 00f80000 ################################################################
9939 20:00:55.592194
9940 20:00:55.881038 01000000 ################################################################
9941 20:00:55.881173
9942 20:00:56.161716 01080000 ################################################################
9943 20:00:56.161877
9944 20:00:56.463651 01100000 ################################################################
9945 20:00:56.463812
9946 20:00:56.756850 01180000 ################################################################
9947 20:00:56.756984
9948 20:00:57.055313 01200000 ################################################################
9949 20:00:57.055473
9950 20:00:57.359499 01280000 ################################################################
9951 20:00:57.359638
9952 20:00:57.746926 01300000 ################################################################
9953 20:00:57.747564
9954 20:00:58.141946 01380000 ################################################################
9955 20:00:58.142473
9956 20:00:58.525094 01400000 ################################################################
9957 20:00:58.525654
9958 20:00:58.907287 01480000 ################################################################
9959 20:00:58.907816
9960 20:00:59.312445 01500000 ################################################################
9961 20:00:59.313098
9962 20:00:59.735378 01580000 ################################################################
9963 20:00:59.736052
9964 20:01:00.173855 01600000 ################################################################
9965 20:01:00.174431
9966 20:01:00.591840 01680000 ################################################################
9967 20:01:00.592475
9968 20:01:00.975226 01700000 ################################################################
9969 20:01:00.975745
9970 20:01:01.383090 01780000 ################################################################
9971 20:01:01.383613
9972 20:01:01.806390 01800000 ################################################################
9973 20:01:01.806902
9974 20:01:02.245879 01880000 ################################################################
9975 20:01:02.246377
9976 20:01:02.645962 01900000 ################################################################
9977 20:01:02.646112
9978 20:01:02.957671 01980000 ################################################################
9979 20:01:02.957807
9980 20:01:03.311630 01a00000 ################################################################
9981 20:01:03.312167
9982 20:01:03.700353 01a80000 ################################################################
9983 20:01:03.700929
9984 20:01:04.113231 01b00000 ################################################################
9985 20:01:04.113739
9986 20:01:04.157211 01b80000 ####### done.
9987 20:01:04.157647
9988 20:01:04.160716 The bootfile was 28891070 bytes long.
9989 20:01:04.161191
9990 20:01:04.163793 Sending tftp read request... done.
9991 20:01:04.164322
9992 20:01:04.167617 Waiting for the transfer...
9993 20:01:04.168102
9994 20:01:04.168529 00000000 # done.
9995 20:01:04.168885
9996 20:01:04.174337 Command line loaded dynamically from TFTP file: 11899595/tftp-deploy-c1ag_fai/kernel/cmdline
9997 20:01:04.177663
9998 20:01:04.197891 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11899595/extract-nfsrootfs-idlrs87b,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9999 20:01:04.198450
10000 20:01:04.198790 Loading FIT.
10001 20:01:04.199104
10002 20:01:04.200814 Image ramdisk-1 has 17794233 bytes.
10003 20:01:04.201169
10004 20:01:04.204059 Image fdt-1 has 47278 bytes.
10005 20:01:04.204505
10006 20:01:04.207562 Image kernel-1 has 11047522 bytes.
10007 20:01:04.208078
10008 20:01:04.217586 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10009 20:01:04.218105
10010 20:01:04.234339 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10011 20:01:04.234881
10012 20:01:04.240313 Choosing best match conf-1 for compat google,spherion-rev3.
10013 20:01:04.243648
10014 20:01:04.248496 Connected to device vid:did:rid of 1ae0:0028:00
10015 20:01:04.255697
10016 20:01:04.258927 tpm_get_response: command 0x17b, return code 0x0
10017 20:01:04.259492
10018 20:01:04.261977 ec_init: CrosEC protocol v3 supported (256, 248)
10019 20:01:04.265914
10020 20:01:04.269545 tpm_cleanup: add release locality here.
10021 20:01:04.270114
10022 20:01:04.270482 Shutting down all USB controllers.
10023 20:01:04.272379
10024 20:01:04.272777 Removing current net device
10025 20:01:04.273120
10026 20:01:04.279395 Exiting depthcharge with code 4 at timestamp: 64399900
10027 20:01:04.279974
10028 20:01:04.282763 LZMA decompressing kernel-1 to 0x821a6718
10029 20:01:04.283222
10030 20:01:04.285843 LZMA decompressing kernel-1 to 0x40000000
10031 20:01:05.673399
10032 20:01:05.673960 jumping to kernel
10033 20:01:05.676141 end: 2.2.4 bootloader-commands (duration 00:00:38) [common]
10034 20:01:05.676763 start: 2.2.5 auto-login-action (timeout 00:03:49) [common]
10035 20:01:05.677168 Setting prompt string to ['Linux version [0-9]']
10036 20:01:05.677540 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10037 20:01:05.677908 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10038 20:01:05.723661
10039 20:01:05.726578 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10040 20:01:05.730303 start: 2.2.5.1 login-action (timeout 00:03:49) [common]
10041 20:01:05.730837 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10042 20:01:05.731233 Setting prompt string to []
10043 20:01:05.731635 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10044 20:01:05.732012 Using line separator: #'\n'#
10045 20:01:05.732370 No login prompt set.
10046 20:01:05.732711 Parsing kernel messages
10047 20:01:05.733019 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10048 20:01:05.733709 [login-action] Waiting for messages, (timeout 00:03:49)
10049 20:01:05.750173 [ 0.000000] Linux version 6.1.59-cip8-rt4 (KernelCI@build-j84202-arm64-gcc-10-defconfig-arm64-chromebook-st8dj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023
10050 20:01:05.753079 [ 0.000000] random: crng init done
10051 20:01:05.759547 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10052 20:01:05.763030 [ 0.000000] efi: UEFI not found.
10053 20:01:05.769584 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10054 20:01:05.779706 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10055 20:01:05.789583 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10056 20:01:05.796214 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10057 20:01:05.803491 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10058 20:01:05.809314 [ 0.000000] printk: bootconsole [mtk8250] enabled
10059 20:01:05.816289 [ 0.000000] NUMA: No NUMA configuration found
10060 20:01:05.822718 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10061 20:01:05.829007 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10062 20:01:05.829595 [ 0.000000] Zone ranges:
10063 20:01:05.835963 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10064 20:01:05.839135 [ 0.000000] DMA32 empty
10065 20:01:05.845725 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10066 20:01:05.849299 [ 0.000000] Movable zone start for each node
10067 20:01:05.852283 [ 0.000000] Early memory node ranges
10068 20:01:05.859038 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10069 20:01:05.865626 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10070 20:01:05.872114 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10071 20:01:05.878651 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10072 20:01:05.885342 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10073 20:01:05.891892 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10074 20:01:05.922672 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10075 20:01:05.929220 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10076 20:01:05.935618 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10077 20:01:05.939311 [ 0.000000] psci: probing for conduit method from DT.
10078 20:01:05.945687 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10079 20:01:05.949417 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10080 20:01:05.955439 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10081 20:01:05.958763 [ 0.000000] psci: SMC Calling Convention v1.2
10082 20:01:05.965830 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10083 20:01:05.968695 [ 0.000000] Detected VIPT I-cache on CPU0
10084 20:01:05.975773 [ 0.000000] CPU features: detected: GIC system register CPU interface
10085 20:01:05.982425 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10086 20:01:05.988656 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10087 20:01:05.995608 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10088 20:01:06.005488 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10089 20:01:06.012089 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10090 20:01:06.015169 [ 0.000000] alternatives: applying boot alternatives
10091 20:01:06.022231 [ 0.000000] Fallback order for Node 0: 0
10092 20:01:06.028489 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10093 20:01:06.031751 [ 0.000000] Policy zone: Normal
10094 20:01:06.054841 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11899595/extract-nfsrootfs-idlrs87b,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10095 20:01:06.065134 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10096 20:01:06.074835 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10097 20:01:06.081615 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10098 20:01:06.088108 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10099 20:01:06.094582 <6>[ 0.000000] software IO TLB: area num 8.
10100 20:01:06.149067 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10101 20:01:06.229488 <6>[ 0.000000] Memory: 3837636K/4191232K available (17984K kernel code, 4116K rwdata, 17476K rodata, 8448K init, 615K bss, 320828K reserved, 32768K cma-reserved)
10102 20:01:06.236277 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10103 20:01:06.242749 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10104 20:01:06.246280 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10105 20:01:06.252681 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10106 20:01:06.259231 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10107 20:01:06.262491 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10108 20:01:06.272423 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10109 20:01:06.279215 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10110 20:01:06.285646 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10111 20:01:06.292639 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10112 20:01:06.295661 <6>[ 0.000000] GICv3: 608 SPIs implemented
10113 20:01:06.298909 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10114 20:01:06.305536 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10115 20:01:06.308813 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10116 20:01:06.315490 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10117 20:01:06.328948 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10118 20:01:06.342024 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10119 20:01:06.348505 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10120 20:01:06.356315 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10121 20:01:06.369208 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10122 20:01:06.375997 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10123 20:01:06.382458 <6>[ 0.009176] Console: colour dummy device 80x25
10124 20:01:06.392219 <6>[ 0.013894] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10125 20:01:06.399088 <6>[ 0.024336] pid_max: default: 32768 minimum: 301
10126 20:01:06.402310 <6>[ 0.029237] LSM: Security Framework initializing
10127 20:01:06.408697 <6>[ 0.034149] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10128 20:01:06.418667 <6>[ 0.041802] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10129 20:01:06.425233 <6>[ 0.051017] cblist_init_generic: Setting adjustable number of callback queues.
10130 20:01:06.431997 <6>[ 0.058505] cblist_init_generic: Setting shift to 3 and lim to 1.
10131 20:01:06.442000 <6>[ 0.064843] cblist_init_generic: Setting adjustable number of callback queues.
10132 20:01:06.448347 <6>[ 0.072315] cblist_init_generic: Setting shift to 3 and lim to 1.
10133 20:01:06.451839 <6>[ 0.078753] rcu: Hierarchical SRCU implementation.
10134 20:01:06.458300 <6>[ 0.078755] rcu: Max phase no-delay instances is 1000.
10135 20:01:06.464834 <6>[ 0.078779] printk: bootconsole [mtk8250] printing thread started
10136 20:01:06.471328 <6>[ 0.097112] EFI services will not be available.
10137 20:01:06.474840 <6>[ 0.097310] smp: Bringing up secondary CPUs ...
10138 20:01:06.478502 <6>[ 0.097618] Detected VIPT I-cache on CPU1
10139 20:01:06.488144 <6>[ 0.097685] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10140 20:01:06.494676 <6>[ 0.097715] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10141 20:01:06.503791 <6>[ 0.125559] Detected VIPT I-cache on CPU2
10142 20:01:06.510517 <6>[ 0.125606] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10143 20:01:06.517004 <6>[ 0.125620] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10144 20:01:06.523548 <6>[ 0.125878] Detected VIPT I-cache on CPU3
10145 20:01:06.530422 <6>[ 0.125924] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10146 20:01:06.536892 <6>[ 0.125937] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10147 20:01:06.540019 <6>[ 0.126246] CPU features: detected: Spectre-v4
10148 20:01:06.546725 <6>[ 0.126253] CPU features: detected: Spectre-BHB
10149 20:01:06.549862 <6>[ 0.126257] Detected PIPT I-cache on CPU4
10150 20:01:06.557020 <6>[ 0.126315] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10151 20:01:06.563464 <6>[ 0.126331] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10152 20:01:06.566841 <6>[ 0.126620] Detected PIPT I-cache on CPU5
10153 20:01:06.576362 <6>[ 0.126680] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10154 20:01:06.583054 <6>[ 0.126697] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10155 20:01:06.586670 <6>[ 0.126970] Detected PIPT I-cache on CPU6
10156 20:01:06.592871 <6>[ 0.127030] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10157 20:01:06.599554 <6>[ 0.127046] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10158 20:01:06.606882 <6>[ 0.127342] Detected PIPT I-cache on CPU7
10159 20:01:06.612794 <6>[ 0.127407] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10160 20:01:06.619462 <6>[ 0.127423] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10161 20:01:06.622875 <6>[ 0.127470] smp: Brought up 1 node, 8 CPUs
10162 20:01:06.629560 <6>[ 0.127475] SMP: Total of 8 processors activated.
10163 20:01:06.632397 <6>[ 0.127478] CPU features: detected: 32-bit EL0 Support
10164 20:01:06.642634 <6>[ 0.127480] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10165 20:01:06.649243 <6>[ 0.127482] CPU features: detected: Common not Private translations
10166 20:01:06.655827 <6>[ 0.127484] CPU features: detected: CRC32 instructions
10167 20:01:06.659061 <6>[ 0.127487] CPU features: detected: RCpc load-acquire (LDAPR)
10168 20:01:06.665571 <6>[ 0.127488] CPU features: detected: LSE atomic instructions
10169 20:01:06.672101 <6>[ 0.127490] CPU features: detected: Privileged Access Never
10170 20:01:06.678929 <6>[ 0.127491] CPU features: detected: RAS Extension Support
10171 20:01:06.685353 <6>[ 0.127494] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10172 20:01:06.710088 ���<6>[ 0.336935] printk: console [tt<yS0] printing thread started
10173 20:01:06.716577 6>[ 0.220004] clocksource: Switched to clocksource arch_sys_counter
10174 20:01:06.725148 <6>[ 0.336943] printk: console [ttyS0] enabled
10175 20:01:06.728564 <6>[ 0.336946] printk: bootconsole [mtk8250] disabled
10176 20:01:06.735282 <6>[ 0.349132] printk: bootconsole [mtk8250] printing thread stopped
10177 20:01:06.741773 <6>[ 0.350068] SuperH (H)SCI(F) driver initialized
10178 20:01:06.745154 <6>[ 0.350547] msm_serial: driver initialized
10179 20:01:06.754709 <6>[ 0.355133] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10180 20:01:06.761634 <6>[ 0.355162] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10181 20:01:06.773588 <6>[ 0.355191] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10182 20:01:06.778152 <6>[ 0.355222] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10183 20:01:06.788576 <6>[ 0.355243] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10184 20:01:06.812377 <6>[ 0.355270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10185 20:01:06.813006 <6>[ 0.355298] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10186 20:01:06.816740 <6>[ 0.355413] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10187 20:01:06.821255 <6>[ 0.355441] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10188 20:01:06.825945 <6>[ 0.365577] loop: module loaded
10189 20:01:06.830799 <6>[ 0.368107] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10190 20:01:06.838019 <4>[ 0.385185] mtk-pmic-keys: Failed to locate of_node [id: -1]
10191 20:01:06.840966 <6>[ 0.386053] megasas: 07.719.03.00-rc1
10192 20:01:06.847741 <6>[ 0.395365] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10193 20:01:06.854680 <6>[ 0.402928] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10194 20:01:06.860754 <6>[ 0.414877] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10195 20:01:06.870655 <6>[ 0.467355] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10196 20:01:07.329204 <6>[ 0.952481] Freeing initrd memory: 17376K
10197 20:01:07.335706 <6>[ 0.958279] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10198 20:01:07.339383 <6>[ 0.963098] tun: Universal TUN/TAP device driver, 1.6
10199 20:01:07.342763 <6>[ 0.963844] thunder_xcv, ver 1.0
10200 20:01:07.345745 <6>[ 0.963860] thunder_bgx, ver 1.0
10201 20:01:07.349199 <6>[ 0.963874] nicpf, ver 1.0
10202 20:01:07.355921 <6>[ 0.964943] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10203 20:01:07.362247 <6>[ 0.964946] hns3: Copyright (c) 2017 Huawei Corporation.
10204 20:01:07.365682 <6>[ 0.964973] hclge is initializing
10205 20:01:07.372106 <6>[ 0.964990] e1000: Intel(R) PRO/1000 Network Driver
10206 20:01:07.378880 <6>[ 0.964992] e1000: Copyright (c) 1999-2006 Intel Corporation.
10207 20:01:07.382403 <6>[ 0.965009] e1000e: Intel(R) PRO/1000 Network Driver
10208 20:01:07.389909 <6>[ 0.965010] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10209 20:01:07.393659 <6>[ 0.965028] igb: Intel(R) Gigabit Ethernet Network Driver
10210 20:01:07.400628 <6>[ 0.965030] igb: Copyright (c) 2007-2014 Intel Corporation.
10211 20:01:07.407463 <6>[ 0.965043] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10212 20:01:07.414488 <6>[ 0.965045] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10213 20:01:07.417372 <6>[ 0.965338] sky2: driver version 1.30
10214 20:01:07.420889 <6>[ 0.966407] VFIO - User Level meta-driver version: 0.3
10215 20:01:07.427777 <6>[ 0.969277] usbcore: registered new interface driver usb-storage
10216 20:01:07.434102 <6>[ 0.969456] usbcore: registered new device driver onboard-usb-hub
10217 20:01:07.440897 <6>[ 0.972232] mt6397-rtc mt6359-rtc: registered as rtc0
10218 20:01:07.451143 <6>[ 0.972383] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-28T20:01:07 UTC (1698523267)
10219 20:01:07.454317 <6>[ 0.973003] i2c_dev: i2c /dev entries driver
10220 20:01:07.460772 <6>[ 0.980444] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10221 20:01:07.467480 <6>[ 0.996276] cpu cpu0: EM: created perf domain
10222 20:01:07.470618 <6>[ 0.996638] cpu cpu4: EM: created perf domain
10223 20:01:07.477247 <6>[ 0.998902] sdhci: Secure Digital Host Controller Interface driver
10224 20:01:07.480910 <6>[ 0.998905] sdhci: Copyright(c) Pierre Ossman
10225 20:01:07.487166 <6>[ 0.999949] Synopsys Designware Multimedia Card Interface Driver
10226 20:01:07.494148 <6>[ 1.001451] sdhci-pltfm: SDHCI platform and OF driver helper
10227 20:01:07.497000 <6>[ 1.003780] mmc0: CQHCI version 5.10
10228 20:01:07.504047 <6>[ 1.009661] ledtrig-cpu: registered to indicate activity on CPUs
10229 20:01:07.510390 <6>[ 1.010893] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10230 20:01:07.516820 <6>[ 1.011565] usbcore: registered new interface driver usbhid
10231 20:01:07.520507 <6>[ 1.011568] usbhid: USB HID core driver
10232 20:01:07.526787 <6>[ 1.011731] spi_master spi0: will run message pump with realtime priority
10233 20:01:07.540428 <6>[ 1.043107] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10234 20:01:07.553460 <6>[ 1.045110] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10235 20:01:07.560045 <6>[ 1.047069] cros-ec-spi spi0.0: Chrome EC device registered
10236 20:01:07.569970 <6>[ 1.063734] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10237 20:01:07.573133 <6>[ 1.065973] NET: Registered PF_PACKET protocol family
10238 20:01:07.580137 <6>[ 1.066066] 9pnet: Installing 9P2000 support
10239 20:01:07.583333 <5>[ 1.066123] Key type dns_resolver registered
10240 20:01:07.586419 <6>[ 1.066468] registered taskstats version 1
10241 20:01:07.593099 <5>[ 1.066487] Loading compiled-in X.509 certificates
10242 20:01:07.603666 <4>[ 1.087064] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10243 20:01:07.613030 <4>[ 1.087201] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10244 20:01:07.620020 <3>[ 1.087211] debugfs: File 'uA_load' in directory '/' already present!
10245 20:01:07.626245 <3>[ 1.087217] debugfs: File 'min_uV' in directory '/' already present!
10246 20:01:07.633000 <3>[ 1.087220] debugfs: File 'max_uV' in directory '/' already present!
10247 20:01:07.642912 <3>[ 1.087223] debugfs: File 'constraint_flags' in directory '/' already present!
10248 20:01:07.649153 <3>[ 1.089158] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10249 20:01:07.656017 <6>[ 1.095837] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10250 20:01:07.662602 <6>[ 1.096416] xhci-mtk 11200000.usb: xHCI Host Controller
10251 20:01:07.668989 <6>[ 1.096434] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10252 20:01:07.679270 <6>[ 1.096642] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10253 20:01:07.685534 <6>[ 1.096699] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10254 20:01:07.689368 <6>[ 1.096815] xhci-mtk 11200000.usb: xHCI Host Controller
10255 20:01:07.699874 <6>[ 1.096825] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10256 20:01:07.705500 <6>[ 1.096831] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10257 20:01:07.709066 <6>[ 1.097272] hub 1-0:1.0: USB hub found
10258 20:01:07.712168 <6>[ 1.097289] hub 1-0:1.0: 1 port detected
10259 20:01:07.722073 <6>[ 1.097480] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10260 20:01:07.725448 <6>[ 1.097689] hub 2-0:1.0: USB hub found
10261 20:01:07.728657 <6>[ 1.097701] hub 2-0:1.0: 1 port detected
10262 20:01:07.735298 <6>[ 1.098348] mmc0: Command Queue Engine enabled
10263 20:01:07.742061 <6>[ 1.098357] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10264 20:01:07.745621 <6>[ 1.098684] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10265 20:01:07.752157 <6>[ 1.101535] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10266 20:01:07.755279 <6>[ 1.102382] mtk-msdc 11f70000.mmc: Got CD GPIO
10267 20:01:07.762228 <6>[ 1.102501] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10268 20:01:07.765343 <6>[ 1.103325] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10269 20:01:07.771921 <6>[ 1.103932] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10270 20:01:07.782245 <6>[ 1.117237] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10271 20:01:07.788544 <6>[ 1.117243] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10272 20:01:07.798518 <4>[ 1.117312] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10273 20:01:07.805107 <6>[ 1.117797] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10274 20:01:07.815049 <6>[ 1.117798] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10275 20:01:07.821637 <6>[ 1.117926] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10276 20:01:07.828115 <6>[ 1.117932] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10277 20:01:07.838335 <6>[ 1.117933] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10278 20:01:07.848604 <6>[ 1.117935] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10279 20:01:07.854662 <6>[ 1.119030] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10280 20:01:07.864445 <6>[ 1.119044] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10281 20:01:07.871337 <6>[ 1.119047] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10282 20:01:07.881569 <6>[ 1.119050] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10283 20:01:07.887834 <6>[ 1.119053] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10284 20:01:07.897602 <6>[ 1.119055] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10285 20:01:07.904356 <6>[ 1.119058] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10286 20:01:07.914070 <6>[ 1.119062] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10287 20:01:07.920924 <6>[ 1.119064] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10288 20:01:07.930574 <6>[ 1.119067] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10289 20:01:07.936956 <6>[ 1.119070] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10290 20:01:07.946835 <6>[ 1.119073] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10291 20:01:07.953569 <6>[ 1.119077] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10292 20:01:07.963300 <6>[ 1.119080] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10293 20:01:07.969775 <6>[ 1.119082] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10294 20:01:07.976866 <6>[ 1.119369] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10295 20:01:07.983443 <6>[ 1.119903] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10296 20:01:07.990146 <6>[ 1.120132] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10297 20:01:07.996679 <6>[ 1.120408] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10298 20:01:08.003523 <6>[ 1.120657] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10299 20:01:08.013052 <6>[ 1.120813] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10300 20:01:08.023404 <6>[ 1.120820] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10301 20:01:08.032821 <6>[ 1.120822] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10302 20:01:08.042471 <6>[ 1.120825] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10303 20:01:08.049298 <6>[ 1.120827] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10304 20:01:08.059052 <6>[ 1.120835] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10305 20:01:08.068941 <6>[ 1.120839] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10306 20:01:08.078839 <6>[ 1.120841] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10307 20:01:08.088832 <6>[ 1.120843] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10308 20:01:08.099138 <6>[ 1.120847] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10309 20:01:08.108736 <6>[ 1.120849] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10310 20:01:08.115463 <6>[ 1.122001] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10311 20:01:08.121821 <6>[ 1.140650] Trying to probe devices needed for running init ...
10312 20:01:08.128881 <6>[ 1.480310] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10313 20:01:08.132086 <6>[ 1.507314] hub 2-1:1.0: USB hub found
10314 20:01:08.138491 <6>[ 1.507687] hub 2-1:1.0: 3 ports detected
10315 20:01:08.145152 <6>[ 1.632080] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10316 20:01:08.160871 <6>[ 1.784774] hub 1-1:1.0: USB hub found
10317 20:01:08.164552 <6>[ 1.785133] hub 1-1:1.0: 4 ports detected
10318 20:01:08.240665 <6>[ 1.860533] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10319 20:01:08.476523 <6>[ 2.096351] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10320 20:01:08.597030 <6>[ 2.223165] hub 1-1.4:1.0: USB hub found
10321 20:01:08.600476 <6>[ 2.223474] hub 1-1.4:1.0: 2 ports detected
10322 20:01:08.892572 <6>[ 2.512286] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10323 20:01:09.075971 <6>[ 2.696260] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10324 20:01:19.812470 <6>[ 13.441271] ALSA device list:
10325 20:01:19.819320 <6>[ 13.441292] No soundcards found.
10326 20:01:19.822676 <6>[ 13.445529] Freeing unused kernel memory: 8448K
10327 20:01:19.825933 <6>[ 13.445671] Run /init as init process
10328 20:01:19.828950 Loading, please wait...
10329 20:01:19.853705 Starting version 247.3-7+deb11u2
10330 20:01:20.027216 <6>[ 13.651854] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10331 20:01:20.030406 <6>[ 13.655848] remoteproc remoteproc0: scp is available
10332 20:01:20.036846 <6>[ 13.656026] remoteproc remoteproc0: powering up scp
10333 20:01:20.043647 <6>[ 13.656038] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10334 20:01:20.049981 <6>[ 13.656096] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10335 20:01:20.079032 <3>[ 13.702954] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10336 20:01:20.085516 <3>[ 13.703022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10337 20:01:20.095555 <3>[ 13.703033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10338 20:01:20.101894 <6>[ 13.703553] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10339 20:01:20.112125 <6>[ 13.703584] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10340 20:01:20.118896 <6>[ 13.703594] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10341 20:01:20.128748 <3>[ 13.737617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10342 20:01:20.135190 <3>[ 13.737645] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10343 20:01:20.145063 <3>[ 13.737654] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10344 20:01:20.151860 <3>[ 13.737666] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10345 20:01:20.162168 <3>[ 13.737673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10346 20:01:20.168483 <3>[ 13.737732] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10347 20:01:20.175038 <3>[ 13.737794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10348 20:01:20.184792 <3>[ 13.737801] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10349 20:01:20.191817 <3>[ 13.737808] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10350 20:01:20.201415 <3>[ 13.762096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10351 20:01:20.208466 <3>[ 13.762121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10352 20:01:20.218239 <3>[ 13.762126] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10353 20:01:20.225580 <3>[ 13.762132] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10354 20:01:20.231952 <3>[ 13.762135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10355 20:01:20.241952 <3>[ 13.762863] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10356 20:01:20.245006 <6>[ 13.776159] mc: Linux media interface: v0.10
10357 20:01:20.251922 <4>[ 13.778411] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10358 20:01:20.261882 <4>[ 13.780236] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10359 20:01:20.268459 <6>[ 13.783010] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10360 20:01:20.274981 <6>[ 13.783020] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10361 20:01:20.281425 <6>[ 13.783027] remoteproc remoteproc0: remote processor scp is now up
10362 20:01:20.291233 <6>[ 13.784740] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10363 20:01:20.294640 <6>[ 13.802735] videodev: Linux video capture interface: v2.00
10364 20:01:20.301168 <6>[ 13.803860] usbcore: registered new interface driver r8152
10365 20:01:20.311181 <4>[ 13.819298] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10366 20:01:20.314598 <4>[ 13.819298] Fallback method does not support PEC.
10367 20:01:20.321088 <6>[ 13.821703] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10368 20:01:20.327925 <6>[ 13.821717] pci_bus 0000:00: root bus resource [bus 00-ff]
10369 20:01:20.334772 <6>[ 13.821722] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10370 20:01:20.344310 <6>[ 13.821725] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10371 20:01:20.350920 <6>[ 13.821791] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10372 20:01:20.357496 <6>[ 13.821807] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10373 20:01:20.363973 <6>[ 13.821892] pci 0000:00:00.0: supports D1 D2
10374 20:01:20.371087 <6>[ 13.821897] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10375 20:01:20.377435 <6>[ 13.823640] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10376 20:01:20.384254 <6>[ 13.824266] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10377 20:01:20.390962 <6>[ 13.824307] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10378 20:01:20.400819 <6>[ 13.824328] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10379 20:01:20.406778 <6>[ 13.824343] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10380 20:01:20.410388 <6>[ 13.824481] pci 0000:01:00.0: supports D1 D2
10381 20:01:20.417051 <6>[ 13.824482] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10382 20:01:20.426882 <3>[ 13.836328] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10383 20:01:20.433567 <6>[ 13.840098] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10384 20:01:20.439955 <6>[ 13.840129] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10385 20:01:20.450312 <6>[ 13.840132] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10386 20:01:20.457139 <6>[ 13.840147] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10387 20:01:20.466708 <6>[ 13.840160] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10388 20:01:20.472893 <6>[ 13.840172] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10389 20:01:20.479743 <6>[ 13.840183] pci 0000:00:00.0: PCI bridge to [bus 01]
10390 20:01:20.486153 <6>[ 13.840189] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10391 20:01:20.493088 <6>[ 13.840348] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10392 20:01:20.499820 <6>[ 13.841045] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10393 20:01:20.506174 <6>[ 13.841509] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10394 20:01:20.512955 <6>[ 13.851090] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10395 20:01:20.523075 <6>[ 13.852205] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10396 20:01:20.529345 <3>[ 13.859063] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10397 20:01:20.539071 <6>[ 13.888471] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10398 20:01:20.545719 <6>[ 13.892412] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10399 20:01:20.556106 <6>[ 13.897372] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10400 20:01:20.565676 <6>[ 13.897735] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10401 20:01:20.575513 <5>[ 13.916841] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10402 20:01:20.581908 <4>[ 13.923397] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10403 20:01:20.591986 <4>[ 13.923411] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10404 20:01:20.598411 <6>[ 13.923841] usbcore: registered new interface driver cdc_ether
10405 20:01:20.605552 <5>[ 13.933935] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10406 20:01:20.611966 <4>[ 13.933994] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10407 20:01:20.618448 <6>[ 13.934001] cfg80211: failed to load regulatory.db
10408 20:01:20.624776 <6>[ 13.935127] usbcore: registered new interface driver r8153_ecm
10409 20:01:20.628584 <6>[ 13.949338] Bluetooth: Core ver 2.22
10410 20:01:20.632211 <6>[ 13.949480] NET: Registered PF_BLUETOOTH protocol family
10411 20:01:20.638102 <6>[ 13.949484] Bluetooth: HCI device and connection manager initialized
10412 20:01:20.644786 <6>[ 13.949513] Bluetooth: HCI socket layer initialized
10413 20:01:20.651499 <6>[ 13.949521] Bluetooth: L2CAP socket layer initialized
10414 20:01:20.654805 <6>[ 13.949557] Bluetooth: SCO socket layer initialized
10415 20:01:20.661375 <6>[ 13.951156] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10416 20:01:20.674753 <6>[ 13.952929] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10417 20:01:20.681295 <6>[ 13.953041] usbcore: registered new interface driver uvcvideo
10418 20:01:20.688017 <6>[ 13.993444] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10419 20:01:20.691113 <6>[ 14.003175] r8152 2-1.3:1.0 eth0: v1.12.13
10420 20:01:20.697948 <6>[ 14.011623] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10421 20:01:20.704405 <6>[ 14.018332] usbcore: registered new interface driver btusb
10422 20:01:20.714261 <4>[ 14.019955] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10423 20:01:20.721174 <3>[ 14.019974] Bluetooth: hci0: Failed to load firmware file (-2)
10424 20:01:20.727553 <3>[ 14.019978] Bluetooth: hci0: Failed to set up firmware (-2)
10425 20:01:20.737395 <4>[ 14.019980] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10426 20:01:20.744019 <6>[ 14.045373] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10427 20:01:20.750711 <6>[ 14.045497] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10428 20:01:20.757348 <6>[ 14.064248] mt7921e 0000:01:00.0: ASIC revision: 79610010
10429 20:01:20.767206 <4>[ 14.159233] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10430 20:01:20.776774 <4>[ 14.266193] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10431 20:01:20.790386 <4>[ 14.373398] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10432 20:01:20.793491 Begin: Loading essential drivers ... done.
10433 20:01:20.797110 Begin: Running /scripts/init-premount ... done.
10434 20:01:20.803436 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10435 20:01:20.813378 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10436 20:01:20.816928 Device /sys/class/net/enx00e04c6803bd found
10437 20:01:20.817503 done.
10438 20:01:20.858590 <4>[ 14.478391] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10439 20:01:20.882749 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10440 20:01:20.965912 <4>[ 14.585548] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10441 20:01:21.066201 <4>[ 14.685004] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10442 20:01:21.170435 <4>[ 14.788839] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10443 20:01:21.274343 <4>[ 14.892822] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10444 20:01:21.378349 <4>[ 14.996750] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10445 20:01:21.481833 <4>[ 15.100671] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10446 20:01:21.575641 <3>[ 15.202638] mt7921e 0000:01:00.0: hardware init failed
10447 20:01:21.939675 <6>[ 15.566566] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10448 20:01:22.843906 IP-Config: no response after 2 secs - giving up
10449 20:01:22.894932 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10450 20:01:22.901438 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10451 20:01:22.907915 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10452 20:01:22.914848 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10453 20:01:22.921305 host : mt8192-asurada-spherion-r0-cbg-4
10454 20:01:22.927982 domain : lava-rack
10455 20:01:22.931387 rootserver: 192.168.201.1 rootpath:
10456 20:01:22.934378 filename :
10457 20:01:23.013647 done.
10458 20:01:23.020629 Begin: Running /scripts/nfs-bottom ... done.
10459 20:01:23.037518 Begin: Running /scripts/init-bottom ... done.
10460 20:01:24.247253 <6>[ 17.874278] NET: Registered PF_INET6 protocol family
10461 20:01:24.250516 <6>[ 17.876160] Segment Routing with IPv6
10462 20:01:24.253917 <6>[ 17.876185] In-situ OAM (IOAM) with IPv6
10463 20:01:24.367178 <30>[ 17.975608] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10464 20:01:24.370646 <30>[ 17.976702] systemd[1]: Detected architecture arm64.
10465 20:01:24.371204
10466 20:01:24.376778 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10467 20:01:24.377337
10468 20:01:24.395011 <30>[ 18.022943] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10469 20:01:25.262316 <30>[ 18.886837] systemd[1]: Queued start job for default target Graphical Interface.
10470 20:01:25.289747 [[0;32m OK [<30>[ 18.914622] systemd[1]: Created slice system-getty.slice.
10471 20:01:25.292618 0m] Created slice [0;1;39msystem-getty.slice[0m.
10472 20:01:25.312013 [[0;32m OK [0m] Created slic<30>[ 18.937607] systemd[1]: Created slice system-modprobe.slice.
10473 20:01:25.315564 e [0;1;39msystem-modprobe.slice[0m.
10474 20:01:25.336105 [[0;32m OK [0m] Created slic<30>[ 18.961517] systemd[1]: Created slice system-serial\x2dgetty.slice.
10475 20:01:25.342255 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10476 20:01:25.360830 [[0;32m OK [0m] Created slic<30>[ 18.986116] systemd[1]: Created slice User and Session Slice.
10477 20:01:25.364054 e [0;1;39mUser and Session Slice[0m.
10478 20:01:25.387281 [[0;32m OK [0m] Started [0;<30>[ 19.009090] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10479 20:01:25.390465 1;39mDispatch Password …ts to Console Directory Watch[0m.
10480 20:01:25.414428 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.036500] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10481 20:01:25.417767 sword R…uests to Wall Directory Watch[0m.
10482 20:01:25.441873 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.060418] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10483 20:01:25.448390 <30>[ 19.060613] systemd[1]: Reached target Local Encrypted Volumes.
10484 20:01:25.451655 l Encrypted Volumes[0m.
10485 20:01:25.471036 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.096419] systemd[1]: Reached target Paths.
10486 20:01:25.471629 s[0m.
10487 20:01:25.494255 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.116315] systemd[1]: Reached target Remote File Systems.
10488 20:01:25.494862 te File Systems[0m.
10489 20:01:25.514568 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.140269] systemd[1]: Reached target Slices.
10490 20:01:25.515128 es[0m.
10491 20:01:25.534961 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.160310] systemd[1]: Reached target Swap.
10492 20:01:25.535535 [0m.
10493 20:01:25.558522 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.180692] systemd[1]: Listening on initctl Compatibility Named Pipe.
10494 20:01:25.561948 l Compatibility Named Pipe[0m.
10495 20:01:25.571961 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.196789] systemd[1]: Listening on Journal Audit Socket.
10496 20:01:25.574696 l Audit Socket[0m.
10497 20:01:25.596854 [[0;32m OK [0m] Listening on<30>[ 19.222430] systemd[1]: Listening on Journal Socket (/dev/log).
10498 20:01:25.599894 [0;1;39mJournal Socket (/dev/log)[0m.
10499 20:01:25.619930 [[0;32m OK [0m] Listening on<30>[ 19.245469] systemd[1]: Listening on Journal Socket.
10500 20:01:25.623370 [0;1;39mJournal Socket[0m.
10501 20:01:25.640289 [[0;32m OK [0m] Listening on<30>[ 19.265990] systemd[1]: Listening on Network Service Netlink Socket.
10502 20:01:25.647004 [0;1;39mNetwork Service Netlink Socket[0m.
10503 20:01:25.666582 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 19.292234] systemd[1]: Listening on udev Control Socket.
10504 20:01:25.669745 ontrol Socket[0m.
10505 20:01:25.687197 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 19.312817] systemd[1]: Listening on udev Kernel Socket.
10506 20:01:25.690549 ernel Socket[0m.
10507 20:01:25.746665 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.368721] systemd[1]: Mounting Huge Pages File System...
10508 20:01:25.747232 m[0m...
10509 20:01:25.767911 Mounting [0;1;39mPOSIX<30>[ 19.393265] systemd[1]: Mounting POSIX Message Queue File System...
10510 20:01:25.771742 Message Queue File System[0m...
10511 20:01:25.797864 Mounting [0;1;39mKernel Debug File Sys<30>[ 19.420101] systemd[1]: Mounting Kernel Debug File System...
10512 20:01:25.798338 tem[0m...
10513 20:01:25.818188 <30>[ 19.440620] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10514 20:01:25.828544 <30>[ 19.447067] systemd[1]: Starting Create list of static device nodes for the current kernel...
10515 20:01:25.834706 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10516 20:01:25.882576 Starting [0;1;39mLoad Kernel Module co<30>[ 19.505007] systemd[1]: Starting Load Kernel Module configfs...
10517 20:01:25.883134 nfigfs[0m...
10518 20:01:25.906665 Starting [0;1;39mLoad Kernel Module dr<30>[ 19.528940] systemd[1]: Starting Load Kernel Module drm...
10519 20:01:25.907221 m[0m...
10520 20:01:25.927680 Starting [0;1;39mLoad <30>[ 19.553230] systemd[1]: Starting Load Kernel Module fuse...
10521 20:01:25.931074 Kernel Module fuse[0m...
10522 20:01:25.967008 <6>[ 19.593193] fuse: init (API version 7.37)
10523 20:01:25.976741 <30>[ 19.593570] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10524 20:01:26.003643 Starting [0;1;39mJourn<30>[ 19.629055] systemd[1]: Starting Journal Service...
10525 20:01:26.004266 al Service[0m...
10526 20:01:26.033851 Startin<30>[ 19.659269] systemd[1]: Starting Load Kernel Modules...
10527 20:01:26.036963 g [0;1;39mLoad Kernel Modules[0m...
10528 20:01:26.061201 Startin<30>[ 19.686602] systemd[1]: Starting Remount Root and Kernel File Systems...
10529 20:01:26.064770 g [0;1;39mRemount Root and Kernel File Systems[0m...
10530 20:01:26.088355 Starting [0;1;39mColdp<30>[ 19.713912] systemd[1]: Starting Coldplug All udev Devices...
10531 20:01:26.091536 lug All udev Devices[0m...
10532 20:01:26.121289 [[0;32m OK [0m] Mounted [0;<30>[ 19.746101] systemd[1]: Mounted Huge Pages File System.
10533 20:01:26.131480 1;39mHuge Pages <3>[ 19.753142] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10534 20:01:26.132047 File System[0m.
10535 20:01:26.154949 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Messa<30>[ 19.777059] systemd[1]: Mounted POSIX Message Queue File System.
10536 20:01:26.164676 ge Queue File Sy<3>[ 19.779197] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10537 20:01:26.165146 stem[0m.
10538 20:01:26.183716 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 19.808812] systemd[1]: Mounted Kernel Debug File System.
10539 20:01:26.193445 g File System[0<3>[ 19.815081] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10540 20:01:26.196663 m.
10541 20:01:26.219712 [[0;32m OK [0m] Finished [0<3>[ 19.841016] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10542 20:01:26.230395 ;1;39mCreate lis<30>[ 19.841783] systemd[1]: Finished Create list of static device nodes for the current kernel.
10543 20:01:26.240344 t of st… nodes<3>[ 19.862637] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10544 20:01:26.243582 for the current kernel[0m.
10545 20:01:26.263191 [[0;32m OK [0m] Finished [0<3>[ 19.884559] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10546 20:01:26.270466 ;1;39mLoad Kerne<30>[ 19.885086] systemd[1]: modprobe@configfs.service: Succeeded.
10547 20:01:26.277011 <30>[ 19.885518] systemd[1]: Finished Load Kernel Module configfs.
10548 20:01:26.277531 l Module configfs[0m.
10549 20:01:26.290722 <3>[ 19.912638] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10550 20:01:26.299802 <30>[ 19.926713] systemd[1]: modprobe@drm.service: Succeeded.
10551 20:01:26.306364 <30>[ 19.928068] systemd[1]: Finished Load Kernel Module drm.
10552 20:01:26.316402 [[0;32m OK [<3>[ 19.933381] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10553 20:01:26.320025 0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10554 20:01:26.334334 <3>[ 19.957068] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10555 20:01:26.347114 [[0;32m OK [<30>[ 19.970621] systemd[1]: modprobe@fuse.service: Succeeded.
10556 20:01:26.353607 0m] Finished [0<30>[ 19.971689] systemd[1]: Finished Load Kernel Module fuse.
10557 20:01:26.360341 <3>[ 19.982265] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10558 20:01:26.363438 ;1;39mLoad Kernel Module fuse[0m.
10559 20:01:26.384329 [[0;32m OK [0m] Finished [0<30>[ 20.010032] systemd[1]: Finished Load Kernel Modules.
10560 20:01:26.387714 ;1;39mLoad Kernel Modules[0m.
10561 20:01:26.403204 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 20.028888] systemd[1]: Started Journal Service.
10562 20:01:26.406574 vice[0m.
10563 20:01:26.425710 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10564 20:01:26.485437 Mounting [0;1;39mFUSE Control File System[0m...
10565 20:01:26.503090 Mounting [0;1;39mKernel Configuration File System[0m...
10566 20:01:26.531794 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10567 20:01:26.554934 Starting [0;1;39mLoad/Save Random Seed[0m...
10568 20:01:26.577737 <46>[ 20.203093] systemd-journald[303]: Received client request to flush runtime journal.
10569 20:01:26.584448 Starting [0;1;39mApply Kernel Variables[0m...
10570 20:01:26.606472 Starting [0;1;39mCreate System Users[0m...
10571 20:01:26.622755 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10572 20:01:26.639628 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10573 20:01:26.656346 <4>[ 20.272715] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10574 20:01:26.666219 <3>[ 20.272724] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10575 20:01:26.672766 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10576 20:01:26.686640 See 'systemctl status systemd-udev-trigger.service' for details.
10577 20:01:26.705270 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10578 20:01:27.337714 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10579 20:01:28.008096 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10580 20:01:28.029290 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10581 20:01:28.084081 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10582 20:01:28.165981 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10583 20:01:28.183631 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10584 20:01:28.199234 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10585 20:01:28.255681 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10586 20:01:28.287243 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10587 20:01:28.448330 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10588 20:01:28.499979 Starting [0;1;39mNetwork Service[0m...
10589 20:01:28.548046 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10590 20:01:28.578463 Starting [0;1;39mNetwork Time Synchronization[0m...
10591 20:01:28.598644 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10592 20:01:28.840643 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10593 20:01:28.861620 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10594 20:01:28.880904 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10595 20:01:28.926769 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10596 20:01:29.140844 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10597 20:01:29.162160 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10598 20:01:29.191688 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10599 20:01:29.210905 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10600 20:01:29.227634 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10601 20:01:29.243628 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10602 20:01:29.267020 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10603 20:01:29.283292 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10604 20:01:29.306639 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10605 20:01:29.322950 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10606 20:01:29.343454 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10607 20:01:29.372571 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10608 20:01:29.393729 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10609 20:01:29.413703 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10610 20:01:29.434742 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10611 20:01:29.447063 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10612 20:01:29.468140 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10613 20:01:29.482748 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10614 20:01:29.498361 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10615 20:01:29.535278 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10616 20:01:29.614990 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10617 20:01:29.687669 Starting [0;1;39mUser Login Management[0m...
10618 20:01:29.788425 Starting [0;1;39mNetwork Name Resolution[0m...
10619 20:01:29.909561 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10620 20:01:29.953409 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10621 20:01:30.567193 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10622 20:01:30.587607 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10623 20:01:30.610535 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10624 20:01:30.656474 Starting [0;1;39mPermit User Sessions[0m...
10625 20:01:30.714233 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10626 20:01:30.772525 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10627 20:01:30.816326 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10628 20:01:30.832229 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10629 20:01:30.848700 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10630 20:01:30.864935 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10631 20:01:30.927145 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10632 20:01:30.981958 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10633 20:01:31.048910
10634 20:01:31.049478
10635 20:01:31.051910 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10636 20:01:31.052417
10637 20:01:31.055146 debian-bullseye-arm64 login: root (automatic login)
10638 20:01:31.055621
10639 20:01:31.056105
10640 20:01:31.427924 Linux debian-bullseye-arm64 6.1.59-cip8-rt4 #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023 aarch64
10641 20:01:31.428541
10642 20:01:31.434716 The programs included with the Debian GNU/Linux system are free software;
10643 20:01:31.441300 the exact distribution terms for each program are described in the
10644 20:01:31.445045 individual files in /usr/share/doc/*/copyright.
10645 20:01:31.445521
10646 20:01:31.451408 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10647 20:01:31.454397 permitted by applicable law.
10648 20:01:32.494815 Matched prompt #10: / #
10650 20:01:32.496235 Setting prompt string to ['/ #']
10651 20:01:32.496836 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10653 20:01:32.498108 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10654 20:01:32.498685 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
10655 20:01:32.498824 Setting prompt string to ['/ #']
10656 20:01:32.498899 Forcing a shell prompt, looking for ['/ #']
10658 20:01:32.549326 / #
10659 20:01:32.549772 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10660 20:01:32.550145 Waiting using forced prompt support (timeout 00:02:30)
10661 20:01:32.555259
10662 20:01:32.556129 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10663 20:01:32.556686 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
10665 20:01:32.657957 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11899595/extract-nfsrootfs-idlrs87b'
10666 20:01:32.663077 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11899595/extract-nfsrootfs-idlrs87b'
10668 20:01:32.764026 / # export NFS_SERVER_IP='192.168.201.1'
10669 20:01:32.770677 export NFS_SERVER_IP='192.168.201.1'
10670 20:01:32.771654 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10671 20:01:32.772329 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
10672 20:01:32.772931 end: 2 depthcharge-action (duration 00:01:38) [common]
10673 20:01:32.773519 start: 3 lava-test-retry (timeout 00:07:42) [common]
10674 20:01:32.774066 start: 3.1 lava-test-shell (timeout 00:07:42) [common]
10675 20:01:32.774543 Using namespace: common
10677 20:01:32.876031 / # #
10678 20:01:32.876795 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10679 20:01:32.882436 #
10680 20:01:32.883368 Using /lava-11899595
10682 20:01:32.984981 / # export SHELL=/bin/bash
10683 20:01:32.991955 export SHELL=/bin/bash
10685 20:01:33.093733 / # . /lava-11899595/environment
10686 20:01:33.100093 . /lava-11899595/environment
10688 20:01:33.207852 / # /lava-11899595/bin/lava-test-runner /lava-11899595/0
10689 20:01:33.208580 Test shell timeout: 10s (minimum of the action and connection timeout)
10690 20:01:33.214435 /lava-11899595/bin/lava-test-runner /lava-11899595/0
10691 20:01:33.516863 + export TESTRUN_ID=0_timesync-off
10692 20:01:33.520227 + TESTRUN_ID=0_timesync-off
10693 20:01:33.523199 + cd /lava-11899595/0/tests/0_timesync-off
10694 20:01:33.526477 ++ cat uuid
10695 20:01:33.530757 + UUID=11899595_1.6.2.3.1
10696 20:01:33.531291 + set +x
10697 20:01:33.537327 <LAVA_SIGNAL_STARTRUN 0_timesync-off 11899595_1.6.2.3.1>
10698 20:01:33.538117 Received signal: <STARTRUN> 0_timesync-off 11899595_1.6.2.3.1
10699 20:01:33.538518 Starting test lava.0_timesync-off (11899595_1.6.2.3.1)
10700 20:01:33.538997 Skipping test definition patterns.
10701 20:01:33.540567 + systemctl stop systemd-timesyncd
10702 20:01:33.610114 + set +x
10703 20:01:33.612958 <LAVA_SIGNAL_ENDRUN 0_timesync-off 11899595_1.6.2.3.1>
10704 20:01:33.613769 Received signal: <ENDRUN> 0_timesync-off 11899595_1.6.2.3.1
10705 20:01:33.614216 Ending use of test pattern.
10706 20:01:33.614622 Ending test lava.0_timesync-off (11899595_1.6.2.3.1), duration 0.08
10708 20:01:33.683673 + export TESTRUN_ID=1_kselftest-arm64
10709 20:01:33.683763 + TESTRUN_ID=1_kselftest-arm64
10710 20:01:33.690166 + cd /lava-11899595/0/tests/1_kselftest-arm64
10711 20:01:33.690253 ++ cat uuid
10712 20:01:33.693256 + UUID=11899595_1.6.2.3.5
10713 20:01:33.693338 + set +x
10714 20:01:33.699842 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 11899595_1.6.2.3.5>
10715 20:01:33.700097 Received signal: <STARTRUN> 1_kselftest-arm64 11899595_1.6.2.3.5
10716 20:01:33.700168 Starting test lava.1_kselftest-arm64 (11899595_1.6.2.3.5)
10717 20:01:33.700286 Skipping test definition patterns.
10718 20:01:33.703232 + cd ./automated/linux/kselftest/
10719 20:01:33.729800 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10720 20:01:33.762747 INFO: install_deps skipped
10721 20:01:33.884109 --2023-10-28 20:01:33-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10722 20:01:33.902746 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10723 20:01:34.037089 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10724 20:01:34.173206 HTTP request sent, awaiting response... 200 OK
10725 20:01:34.176765 Length: 2959220 (2.8M) [application/octet-stream]
10726 20:01:34.179807 Saving to: 'kselftest.tar.xz'
10727 20:01:34.180402
10728 20:01:34.180772
10729 20:01:34.439967 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10730 20:01:34.706373 kselftest.tar.xz 1%[ ] 46.39K 177KB/s
10731 20:01:35.154474 kselftest.tar.xz 7%[> ] 217.50K 414KB/s
10732 20:01:35.435315 kselftest.tar.xz 28%[====> ] 811.40K 838KB/s
10733 20:01:35.511682 kselftest.tar.xz 83%[===============> ] 2.37M 1.90MB/s
10734 20:01:35.518366 kselftest.tar.xz 100%[===================>] 2.82M 2.14MB/s in 1.3s
10735 20:01:35.518856
10736 20:01:35.774481 2023-10-28 20:01:35 (2.14 MB/s) - 'kselftest.tar.xz' saved [2959220/2959220]
10737 20:01:35.774642
10738 20:01:41.446564 skiplist:
10739 20:01:41.449530 ========================================
10740 20:01:41.452809 ========================================
10741 20:01:41.500629 arm64:tags_test
10742 20:01:41.504152 arm64:run_tags_test.sh
10743 20:01:41.504592 arm64:fake_sigreturn_bad_magic
10744 20:01:41.507128 arm64:fake_sigreturn_bad_size
10745 20:01:41.510523 arm64:fake_sigreturn_bad_size_for_magic0
10746 20:01:41.513746 arm64:fake_sigreturn_duplicated_fpsimd
10747 20:01:41.517084 arm64:fake_sigreturn_misaligned_sp
10748 20:01:41.520238 arm64:fake_sigreturn_missing_fpsimd
10749 20:01:41.523778 arm64:fake_sigreturn_sme_change_vl
10750 20:01:41.527122 arm64:fake_sigreturn_sve_change_vl
10751 20:01:41.530537 arm64:mangle_pstate_invalid_compat_toggle
10752 20:01:41.533490 arm64:mangle_pstate_invalid_daif_bits
10753 20:01:41.537163 arm64:mangle_pstate_invalid_mode_el1h
10754 20:01:41.540478 arm64:mangle_pstate_invalid_mode_el1t
10755 20:01:41.543631 arm64:mangle_pstate_invalid_mode_el2h
10756 20:01:41.547490 arm64:mangle_pstate_invalid_mode_el2t
10757 20:01:41.550349 arm64:mangle_pstate_invalid_mode_el3h
10758 20:01:41.553648 arm64:mangle_pstate_invalid_mode_el3t
10759 20:01:41.556940 arm64:sme_trap_no_sm
10760 20:01:41.560332 arm64:sme_trap_non_streaming
10761 20:01:41.560787 arm64:sme_trap_za
10762 20:01:41.563602 arm64:sme_vl
10763 20:01:41.564052 arm64:ssve_regs
10764 20:01:41.567268 arm64:sve_regs
10765 20:01:41.567720 arm64:sve_vl
10766 20:01:41.568075 arm64:za_no_regs
10767 20:01:41.570292 arm64:za_regs
10768 20:01:41.570744 arm64:pac
10769 20:01:41.573518 arm64:fp-stress
10770 20:01:41.574007 arm64:sve-ptrace
10771 20:01:41.576859 arm64:sve-probe-vls
10772 20:01:41.577313 arm64:vec-syscfg
10773 20:01:41.577669 arm64:za-fork
10774 20:01:41.580271 arm64:za-ptrace
10775 20:01:41.583387 arm64:check_buffer_fill
10776 20:01:41.583863 arm64:check_child_memory
10777 20:01:41.586492 arm64:check_gcr_el1_cswitch
10778 20:01:41.590065 arm64:check_ksm_options
10779 20:01:41.590521 arm64:check_mmap_options
10780 20:01:41.593327 arm64:check_prctl
10781 20:01:41.596703 arm64:check_tags_inclusion
10782 20:01:41.597159 arm64:check_user_mem
10783 20:01:41.599905 arm64:btitest
10784 20:01:41.600448 arm64:nobtitest
10785 20:01:41.600814 arm64:hwcap
10786 20:01:41.603340 arm64:ptrace
10787 20:01:41.603795 arm64:syscall-abi
10788 20:01:41.606690 arm64:tpidr2
10789 20:01:41.609713 ============== Tests to run ===============
10790 20:01:41.610177 arm64:tags_test
10791 20:01:41.613220 arm64:run_tags_test.sh
10792 20:01:41.616734 arm64:fake_sigreturn_bad_magic
10793 20:01:41.617211 arm64:fake_sigreturn_bad_size
10794 20:01:41.622945 arm64:fake_sigreturn_bad_size_for_magic0
10795 20:01:41.626673 arm64:fake_sigreturn_duplicated_fpsimd
10796 20:01:41.629967 arm64:fake_sigreturn_misaligned_sp
10797 20:01:41.632981 arm64:fake_sigreturn_missing_fpsimd
10798 20:01:41.633491 arm64:fake_sigreturn_sme_change_vl
10799 20:01:41.636321 arm64:fake_sigreturn_sve_change_vl
10800 20:01:41.642850 arm64:mangle_pstate_invalid_compat_toggle
10801 20:01:41.645986 arm64:mangle_pstate_invalid_daif_bits
10802 20:01:41.649493 arm64:mangle_pstate_invalid_mode_el1h
10803 20:01:41.652843 arm64:mangle_pstate_invalid_mode_el1t
10804 20:01:41.655972 arm64:mangle_pstate_invalid_mode_el2h
10805 20:01:41.659151 arm64:mangle_pstate_invalid_mode_el2t
10806 20:01:41.662727 arm64:mangle_pstate_invalid_mode_el3h
10807 20:01:41.666072 arm64:mangle_pstate_invalid_mode_el3t
10808 20:01:41.666543 arm64:sme_trap_no_sm
10809 20:01:41.669155 arm64:sme_trap_non_streaming
10810 20:01:41.672509 arm64:sme_trap_za
10811 20:01:41.673023 arm64:sme_vl
10812 20:01:41.673443 arm64:ssve_regs
10813 20:01:41.675644 arm64:sve_regs
10814 20:01:41.676110 arm64:sve_vl
10815 20:01:41.679330 arm64:za_no_regs
10816 20:01:41.679743 arm64:za_regs
10817 20:01:41.680136 arm64:pac
10818 20:01:41.682351 arm64:fp-stress
10819 20:01:41.682916 arm64:sve-ptrace
10820 20:01:41.686042 arm64:sve-probe-vls
10821 20:01:41.686555 arm64:vec-syscfg
10822 20:01:41.688974 arm64:za-fork
10823 20:01:41.689441 arm64:za-ptrace
10824 20:01:41.692279 arm64:check_buffer_fill
10825 20:01:41.692759 arm64:check_child_memory
10826 20:01:41.695887 arm64:check_gcr_el1_cswitch
10827 20:01:41.698884 arm64:check_ksm_options
10828 20:01:41.702242 arm64:check_mmap_options
10829 20:01:41.702710 arm64:check_prctl
10830 20:01:41.705627 arm64:check_tags_inclusion
10831 20:01:41.706040 arm64:check_user_mem
10832 20:01:41.709200 arm64:btitest
10833 20:01:41.709661 arm64:nobtitest
10834 20:01:41.712029 arm64:hwcap
10835 20:01:41.712477 arm64:ptrace
10836 20:01:41.712809 arm64:syscall-abi
10837 20:01:41.715396 arm64:tpidr2
10838 20:01:41.718784 ===========End Tests to run ===============
10839 20:01:41.721913 shardfile-arm64 pass
10840 20:01:41.978205 <12>[ 35.607077] kselftest: Running tests in arm64
10841 20:01:41.986623 TAP version 13
10842 20:01:41.999910 1..48
10843 20:01:42.017963 # selftests: arm64: tags_test
10844 20:01:42.472631 ok 1 selftests: arm64: tags_test
10845 20:01:42.492777 # selftests: arm64: run_tags_test.sh
10846 20:01:42.543748 # --------------------
10847 20:01:42.547170 # running tags test
10848 20:01:42.547632 # --------------------
10849 20:01:42.550309 # [PASS]
10850 20:01:42.553268 ok 2 selftests: arm64: run_tags_test.sh
10851 20:01:42.567816 # selftests: arm64: fake_sigreturn_bad_magic
10852 20:01:42.651082 # Registered handlers for all signals.
10853 20:01:42.651631 # Detected MINSTKSIGSZ:4720
10854 20:01:42.654327 # Testcase initialized.
10855 20:01:42.657801 # uc context validated.
10856 20:01:42.660903 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10857 20:01:42.664431 # Handled SIG_COPYCTX
10858 20:01:42.664889 # Available space:3568
10859 20:01:42.670996 # Using badly built context - ERR: BAD MAGIC !
10860 20:01:42.677876 # SIG_OK -- SP:0xFFFFF86DA100 si_addr@:0xfffff86da100 si_code:2 token@:0xfffff86d8ea0 offset:-4704
10861 20:01:42.680878 # ==>> completed. PASS(1)
10862 20:01:42.687461 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
10863 20:01:42.694151 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF86D8EA0
10864 20:01:42.697701 ok 3 selftests: arm64: fake_sigreturn_bad_magic
10865 20:01:42.704301 # selftests: arm64: fake_sigreturn_bad_size
10866 20:01:42.727273 # Registered handlers for all signals.
10867 20:01:42.727837 # Detected MINSTKSIGSZ:4720
10868 20:01:42.730983 # Testcase initialized.
10869 20:01:42.733878 # uc context validated.
10870 20:01:42.737191 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10871 20:01:42.740502 # Handled SIG_COPYCTX
10872 20:01:42.740960 # Available space:3568
10873 20:01:42.743620 # uc context validated.
10874 20:01:42.750437 # Using badly built context - ERR: Bad size for esr_context
10875 20:01:42.757472 # SIG_OK -- SP:0xFFFFFC647CD0 si_addr@:0xfffffc647cd0 si_code:2 token@:0xfffffc646a70 offset:-4704
10876 20:01:42.760355 # ==>> completed. PASS(1)
10877 20:01:42.766600 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
10878 20:01:42.773474 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFC646A70
10879 20:01:42.776827 ok 4 selftests: arm64: fake_sigreturn_bad_size
10880 20:01:42.783638 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
10881 20:01:42.813742 # Registered handlers for all signals.
10882 20:01:42.814320 # Detected MINSTKSIGSZ:4720
10883 20:01:42.816691 # Testcase initialized.
10884 20:01:42.820045 # uc context validated.
10885 20:01:42.823382 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10886 20:01:42.827014 # Handled SIG_COPYCTX
10887 20:01:42.827485 # Available space:3568
10888 20:01:42.833584 # Using badly built context - ERR: Bad size for terminator
10889 20:01:42.843840 # SIG_OK -- SP:0xFFFFD9FD7C40 si_addr@:0xffffd9fd7c40 si_code:2 token@:0xffffd9fd69e0 offset:-4704
10890 20:01:42.844356 # ==>> completed. PASS(1)
10891 20:01:42.853176 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
10892 20:01:42.860151 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD9FD69E0
10893 20:01:42.863472 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
10894 20:01:42.870453 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
10895 20:01:42.900499 # Registered handlers for all signals.
10896 20:01:42.901139 # Detected MINSTKSIGSZ:4720
10897 20:01:42.903579 # Testcase initialized.
10898 20:01:42.906710 # uc context validated.
10899 20:01:42.910327 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10900 20:01:42.913147 # Handled SIG_COPYCTX
10901 20:01:42.913605 # Available space:3568
10902 20:01:42.919994 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
10903 20:01:42.929709 # SIG_OK -- SP:0xFFFFFB872D30 si_addr@:0xfffffb872d30 si_code:2 token@:0xfffffb871ad0 offset:-4704
10904 20:01:42.930172 # ==>> completed. PASS(1)
10905 20:01:42.939493 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
10906 20:01:42.946323 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFB871AD0
10907 20:01:42.949443 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
10908 20:01:42.952981 # selftests: arm64: fake_sigreturn_misaligned_sp
10909 20:01:42.999463 # Registered handlers for all signals.
10910 20:01:43.000045 # Detected MINSTKSIGSZ:4720
10911 20:01:43.001217 # Testcase initialized.
10912 20:01:43.004048 # uc context validated.
10913 20:01:43.007331 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10914 20:01:43.010774 # Handled SIG_COPYCTX
10915 20:01:43.017261 # SIG_OK -- SP:0xFFFFCDFB2BE3 si_addr@:0xffffcdfb2be3 si_code:2 token@:0xffffcdfb2be3 offset:0
10916 20:01:43.020676 # ==>> completed. PASS(1)
10917 20:01:43.027226 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
10918 20:01:43.034024 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCDFB2BE3
10919 20:01:43.040863 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
10920 20:01:43.043505 # selftests: arm64: fake_sigreturn_missing_fpsimd
10921 20:01:43.084323 # Registered handlers for all signals.
10922 20:01:43.084908 # Detected MINSTKSIGSZ:4720
10923 20:01:43.087457 # Testcase initialized.
10924 20:01:43.091071 # uc context validated.
10925 20:01:43.094486 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10926 20:01:43.097494 # Handled SIG_COPYCTX
10927 20:01:43.100761 # Mangling template header. Spare space:4096
10928 20:01:43.104307 # Using badly built context - ERR: Missing FPSIMD
10929 20:01:43.113948 # SIG_OK -- SP:0xFFFFF4C729E0 si_addr@:0xfffff4c729e0 si_code:2 token@:0xfffff4c71780 offset:-4704
10930 20:01:43.117635 # ==>> completed. PASS(1)
10931 20:01:43.123903 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
10932 20:01:43.130567 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF4C71780
10933 20:01:43.133928 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
10934 20:01:43.140258 # selftests: arm64: fake_sigreturn_sme_change_vl
10935 20:01:43.166425 # Registered handlers for all signals.
10936 20:01:43.167005 # Detected MINSTKSIGSZ:4720
10937 20:01:43.169402 # ==>> completed. SKIP.
10938 20:01:43.176345 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
10939 20:01:43.179432 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
10940 20:01:43.186230 # selftests: arm64: fake_sigreturn_sve_change_vl
10941 20:01:43.244867 # Registered handlers for all signals.
10942 20:01:43.245442 # Detected MINSTKSIGSZ:4720
10943 20:01:43.247996 # ==>> completed. SKIP.
10944 20:01:43.254747 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
10945 20:01:43.258051 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
10946 20:01:43.264424 # selftests: arm64: mangle_pstate_invalid_compat_toggle
10947 20:01:43.335500 # Registered handlers for all signals.
10948 20:01:43.336101 # Detected MINSTKSIGSZ:4720
10949 20:01:43.338687 # Testcase initialized.
10950 20:01:43.342147 # uc context validated.
10951 20:01:43.342606 # Handled SIG_TRIG
10952 20:01:43.352118 # SIG_OK -- SP:0xFFFFE5AD75F0 si_addr@:0xffffe5ad75f0 si_code:2 token@:(nil) offset:-281474535093744
10953 20:01:43.355221 # ==>> completed. PASS(1)
10954 20:01:43.361707 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
10955 20:01:43.368543 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
10956 20:01:43.371607 # selftests: arm64: mangle_pstate_invalid_daif_bits
10957 20:01:43.419021 # Registered handlers for all signals.
10958 20:01:43.419590 # Detected MINSTKSIGSZ:4720
10959 20:01:43.421853 # Testcase initialized.
10960 20:01:43.425361 # uc context validated.
10961 20:01:43.425817 # Handled SIG_TRIG
10962 20:01:43.435373 # SIG_OK -- SP:0xFFFFEE82AEC0 si_addr@:0xffffee82aec0 si_code:2 token@:(nil) offset:-281474683285184
10963 20:01:43.438577 # ==>> completed. PASS(1)
10964 20:01:43.445081 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
10965 20:01:43.448402 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
10966 20:01:43.454915 # selftests: arm64: mangle_pstate_invalid_mode_el1h
10967 20:01:43.500589 # Registered handlers for all signals.
10968 20:01:43.501184 # Detected MINSTKSIGSZ:4720
10969 20:01:43.503779 # Testcase initialized.
10970 20:01:43.507103 # uc context validated.
10971 20:01:43.507559 # Handled SIG_TRIG
10972 20:01:43.516752 # SIG_OK -- SP:0xFFFFDE298A10 si_addr@:0xffffde298a10 si_code:2 token@:(nil) offset:-281474409007632
10973 20:01:43.520468 # ==>> completed. PASS(1)
10974 20:01:43.527113 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
10975 20:01:43.530330 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
10976 20:01:43.536662 # selftests: arm64: mangle_pstate_invalid_mode_el1t
10977 20:01:43.575739 # Registered handlers for all signals.
10978 20:01:43.576369 # Detected MINSTKSIGSZ:4720
10979 20:01:43.578829 # Testcase initialized.
10980 20:01:43.582230 # uc context validated.
10981 20:01:43.582874 # Handled SIG_TRIG
10982 20:01:43.591949 # SIG_OK -- SP:0xFFFFE1487580 si_addr@:0xffffe1487580 si_code:2 token@:(nil) offset:-281474461365632
10983 20:01:43.595137 # ==>> completed. PASS(1)
10984 20:01:43.601629 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
10985 20:01:43.604872 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
10986 20:01:43.611748 # selftests: arm64: mangle_pstate_invalid_mode_el2h
10987 20:01:43.651188 # Registered handlers for all signals.
10988 20:01:43.651810 # Detected MINSTKSIGSZ:4720
10989 20:01:43.653854 # Testcase initialized.
10990 20:01:43.657335 # uc context validated.
10991 20:01:43.657796 # Handled SIG_TRIG
10992 20:01:43.667072 # SIG_OK -- SP:0xFFFFFC4805C0 si_addr@:0xfffffc4805c0 si_code:2 token@:(nil) offset:-281474914321856
10993 20:01:43.670544 # ==>> completed. PASS(1)
10994 20:01:43.677269 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
10995 20:01:43.680511 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
10996 20:01:43.687128 # selftests: arm64: mangle_pstate_invalid_mode_el2t
10997 20:01:43.724027 # Registered handlers for all signals.
10998 20:01:43.724650 # Detected MINSTKSIGSZ:4720
10999 20:01:43.727355 # Testcase initialized.
11000 20:01:43.730146 # uc context validated.
11001 20:01:43.730607 # Handled SIG_TRIG
11002 20:01:43.739944 # SIG_OK -- SP:0xFFFFE1225D20 si_addr@:0xffffe1225d20 si_code:2 token@:(nil) offset:-281474458869024
11003 20:01:43.743396 # ==>> completed. PASS(1)
11004 20:01:43.749918 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11005 20:01:43.753327 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11006 20:01:43.759691 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11007 20:01:43.796140 # Registered handlers for all signals.
11008 20:01:43.796744 # Detected MINSTKSIGSZ:4720
11009 20:01:43.799042 # Testcase initialized.
11010 20:01:43.803037 # uc context validated.
11011 20:01:43.803598 # Handled SIG_TRIG
11012 20:01:43.812352 # SIG_OK -- SP:0xFFFFDEEEFDE0 si_addr@:0xffffdeeefde0 si_code:2 token@:(nil) offset:-281474421947872
11013 20:01:43.815582 # ==>> completed. PASS(1)
11014 20:01:43.822342 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11015 20:01:43.825557 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11016 20:01:43.831967 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11017 20:01:43.883043 # Registered handlers for all signals.
11018 20:01:43.883598 # Detected MINSTKSIGSZ:4720
11019 20:01:43.886797 # Testcase initialized.
11020 20:01:43.889658 # uc context validated.
11021 20:01:43.890134 # Handled SIG_TRIG
11022 20:01:43.899330 # SIG_OK -- SP:0xFFFFC33A7470 si_addr@:0xffffc33a7470 si_code:2 token@:(nil) offset:-281473957131376
11023 20:01:43.902896 # ==>> completed. PASS(1)
11024 20:01:43.909210 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11025 20:01:43.912662 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11026 20:01:43.915761 # selftests: arm64: sme_trap_no_sm
11027 20:01:43.971195 # Registered handlers for all signals.
11028 20:01:43.971766 # Detected MINSTKSIGSZ:4720
11029 20:01:43.974562 # ==>> completed. SKIP.
11030 20:01:43.984114 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11031 20:01:43.987373 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11032 20:01:43.990575 # selftests: arm64: sme_trap_non_streaming
11033 20:01:44.051326 # Registered handlers for all signals.
11034 20:01:44.051914 # Detected MINSTKSIGSZ:4720
11035 20:01:44.054509 # ==>> completed. SKIP.
11036 20:01:44.064272 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11037 20:01:44.070768 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11038 20:01:44.074131 # selftests: arm64: sme_trap_za
11039 20:01:44.126582 # Registered handlers for all signals.
11040 20:01:44.126869 # Detected MINSTKSIGSZ:4720
11041 20:01:44.129621 # Testcase initialized.
11042 20:01:44.139361 # SIG_OK -- SP:0xFFFFF89AC8B0 si_addr@:0xaaaac3ef2510 si_code:1 token@:(nil) offset:-187650408391952
11043 20:01:44.139516 # ==>> completed. PASS(1)
11044 20:01:44.149737 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11045 20:01:44.152779 ok 21 selftests: arm64: sme_trap_za
11046 20:01:44.152885 # selftests: arm64: sme_vl
11047 20:01:44.203655 # Registered handlers for all signals.
11048 20:01:44.204289 # Detected MINSTKSIGSZ:4720
11049 20:01:44.206951 # ==>> completed. SKIP.
11050 20:01:44.213613 # # SME VL :: Check that we get the right SME VL reported
11051 20:01:44.216546 ok 22 selftests: arm64: sme_vl # SKIP
11052 20:01:44.220300 # selftests: arm64: ssve_regs
11053 20:01:44.288038 # Registered handlers for all signals.
11054 20:01:44.288706 # Detected MINSTKSIGSZ:4720
11055 20:01:44.291575 # ==>> completed. SKIP.
11056 20:01:44.297944 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11057 20:01:44.304586 ok 23 selftests: arm64: ssve_regs # SKIP
11058 20:01:44.308161 # selftests: arm64: sve_regs
11059 20:01:44.380770 # Registered handlers for all signals.
11060 20:01:44.381330 # Detected MINSTKSIGSZ:4720
11061 20:01:44.383788 # ==>> completed. SKIP.
11062 20:01:44.390376 # # SVE registers :: Check that we get the right SVE registers reported
11063 20:01:44.393512 ok 24 selftests: arm64: sve_regs # SKIP
11064 20:01:44.398712 # selftests: arm64: sve_vl
11065 20:01:44.470989 # Registered handlers for all signals.
11066 20:01:44.471569 # Detected MINSTKSIGSZ:4720
11067 20:01:44.474321 # ==>> completed. SKIP.
11068 20:01:44.480616 # # SVE VL :: Check that we get the right SVE VL reported
11069 20:01:44.483795 ok 25 selftests: arm64: sve_vl # SKIP
11070 20:01:44.487090 # selftests: arm64: za_no_regs
11071 20:01:44.553348 # Registered handlers for all signals.
11072 20:01:44.553926 # Detected MINSTKSIGSZ:4720
11073 20:01:44.556279 # ==>> completed. SKIP.
11074 20:01:44.563106 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11075 20:01:44.566343 ok 26 selftests: arm64: za_no_regs # SKIP
11076 20:01:44.570828 # selftests: arm64: za_regs
11077 20:01:44.612583 # Registered handlers for all signals.
11078 20:01:44.613154 # Detected MINSTKSIGSZ:4720
11079 20:01:44.616040 # ==>> completed. SKIP.
11080 20:01:44.622392 # # ZA register :: Check that we get the right ZA registers reported
11081 20:01:44.625964 ok 27 selftests: arm64: za_regs # SKIP
11082 20:01:44.629198 # selftests: arm64: pac
11083 20:01:44.687650 # TAP version 13
11084 20:01:44.688257 # 1..7
11085 20:01:44.691197 # # Starting 7 tests from 1 test cases.
11086 20:01:44.694495 # # RUN global.corrupt_pac ...
11087 20:01:44.697807 # # SKIP PAUTH not enabled
11088 20:01:44.700720 # # OK global.corrupt_pac
11089 20:01:44.703934 # ok 1 # SKIP PAUTH not enabled
11090 20:01:44.710604 # # RUN global.pac_instructions_not_nop ...
11091 20:01:44.714303 # # SKIP PAUTH not enabled
11092 20:01:44.717242 # # OK global.pac_instructions_not_nop
11093 20:01:44.720770 # ok 2 # SKIP PAUTH not enabled
11094 20:01:44.727144 # # RUN global.pac_instructions_not_nop_generic ...
11095 20:01:44.730634 # # SKIP Generic PAUTH not enabled
11096 20:01:44.733991 # # OK global.pac_instructions_not_nop_generic
11097 20:01:44.740574 # ok 3 # SKIP Generic PAUTH not enabled
11098 20:01:44.743713 # # RUN global.single_thread_different_keys ...
11099 20:01:44.747014 # # SKIP PAUTH not enabled
11100 20:01:44.753518 # # OK global.single_thread_different_keys
11101 20:01:44.754032 # ok 4 # SKIP PAUTH not enabled
11102 20:01:44.760359 # # RUN global.exec_changed_keys ...
11103 20:01:44.763812 # # SKIP PAUTH not enabled
11104 20:01:44.767324 # # OK global.exec_changed_keys
11105 20:01:44.770210 # ok 5 # SKIP PAUTH not enabled
11106 20:01:44.773660 # # RUN global.context_switch_keep_keys ...
11107 20:01:44.776815 # # SKIP PAUTH not enabled
11108 20:01:44.783508 # # OK global.context_switch_keep_keys
11109 20:01:44.786727 # ok 6 # SKIP PAUTH not enabled
11110 20:01:44.789745 # # RUN global.context_switch_keep_keys_generic ...
11111 20:01:44.793371 # # SKIP Generic PAUTH not enabled
11112 20:01:44.800101 # # OK global.context_switch_keep_keys_generic
11113 20:01:44.803468 # ok 7 # SKIP Generic PAUTH not enabled
11114 20:01:44.806484 # # PASSED: 7 / 7 tests passed.
11115 20:01:44.809656 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11116 20:01:44.813186 ok 28 selftests: arm64: pac
11117 20:01:44.816326 # selftests: arm64: fp-stress
11118 20:01:50.556690 <6>[ 44.187937] vpu: disabling
11119 20:01:50.560103 <6>[ 44.188020] vproc2: disabling
11120 20:01:50.563469 <6>[ 44.188058] vproc1: disabling
11121 20:01:50.566901 <6>[ 44.188095] vaud18: disabling
11122 20:01:50.569978 <6>[ 44.188276] vsram_others: disabling
11123 20:01:50.573054 <6>[ 44.188402] va09: disabling
11124 20:01:50.576433 <6>[ 44.188458] vsram_md: disabling
11125 20:01:50.579746 <6>[ 44.188554] Vgpu: disabling
11126 20:01:54.780118 # TAP version 13
11127 20:01:54.780739 # 1..16
11128 20:01:54.783121 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11129 20:01:54.786669 # # Will run for 10s
11130 20:01:54.787125 # # Started FPSIMD-0-0
11131 20:01:54.790189 # # Started FPSIMD-0-1
11132 20:01:54.793203 # # Started FPSIMD-1-0
11133 20:01:54.793730 # # Started FPSIMD-1-1
11134 20:01:54.796664 # # Started FPSIMD-2-0
11135 20:01:54.797173 # # Started FPSIMD-2-1
11136 20:01:54.799736 # # Started FPSIMD-3-0
11137 20:01:54.803087 # # Started FPSIMD-3-1
11138 20:01:54.803607 # # Started FPSIMD-4-0
11139 20:01:54.806839 # # Started FPSIMD-4-1
11140 20:01:54.809528 # # Started FPSIMD-5-0
11141 20:01:54.810075 # # Started FPSIMD-5-1
11142 20:01:54.812890 # # Started FPSIMD-6-0
11143 20:01:54.816115 # # Started FPSIMD-6-1
11144 20:01:54.816638 # # Started FPSIMD-7-0
11145 20:01:54.819584 # # Started FPSIMD-7-1
11146 20:01:54.822734 # # FPSIMD-0-1: Vector length: 128 bits
11147 20:01:54.826061 # # FPSIMD-0-1: PID: 1160
11148 20:01:54.829451 # # FPSIMD-0-0: Vector length: 128 bits
11149 20:01:54.829995 # # FPSIMD-0-0: PID: 1159
11150 20:01:54.832524 # # FPSIMD-1-0: Vector length: 128 bits
11151 20:01:54.836139 # # FPSIMD-1-0: PID: 1161
11152 20:01:54.839270 # # FPSIMD-3-0: Vector length: 128 bits
11153 20:01:54.842745 # # FPSIMD-3-0: PID: 1165
11154 20:01:54.846081 # # FPSIMD-1-1: Vector length: 128 bits
11155 20:01:54.849382 # # FPSIMD-1-1: PID: 1162
11156 20:01:54.852520 # # FPSIMD-2-1: Vector length: 128 bits
11157 20:01:54.855783 # # FPSIMD-2-1: PID: 1164
11158 20:01:54.859206 # # FPSIMD-2-0: Vector length: 128 bits
11159 20:01:54.859661 # # FPSIMD-2-0: PID: 1163
11160 20:01:54.862709 # # FPSIMD-4-1: Vector length: 128 bits
11161 20:01:54.865674 # # FPSIMD-4-1: PID: 1168
11162 20:01:54.869160 # # FPSIMD-6-1: Vector length: 128 bits
11163 20:01:54.872293 # # FPSIMD-6-1: PID: 1172
11164 20:01:54.875544 # # FPSIMD-4-0: Vector length: 128 bits
11165 20:01:54.878912 # # FPSIMD-4-0: PID: 1167
11166 20:01:54.882119 # # FPSIMD-6-0: Vector length: 128 bits
11167 20:01:54.882658 # # FPSIMD-6-0: PID: 1171
11168 20:01:54.888856 # # FPSIMD-5-1: Vector length: 128 bits
11169 20:01:54.889382 # # FPSIMD-5-1: PID: 1170
11170 20:01:54.891888 # # FPSIMD-3-1: Vector length: 128 bits
11171 20:01:54.895553 # # FPSIMD-3-1: PID: 1166
11172 20:01:54.899061 # # FPSIMD-7-1: Vector length: 128 bits
11173 20:01:54.902055 # # FPSIMD-7-1: PID: 1174
11174 20:01:54.905284 # # FPSIMD-7-0: Vector length: 128 bits
11175 20:01:54.908723 # # FPSIMD-7-0: PID: 1173
11176 20:01:54.911936 # # FPSIMD-5-0: Vector length: 128 bits
11177 20:01:54.912453 # # FPSIMD-5-0: PID: 1169
11178 20:01:54.915390 # # Finishing up...
11179 20:01:54.921585 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1092939, signals=10
11180 20:01:54.928250 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1091895, signals=10
11181 20:01:54.938344 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=2254054, signals=10
11182 20:01:54.944759 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1131447, signals=10
11183 20:01:54.951507 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=2251169, signals=10
11184 20:01:54.958413 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=2259723, signals=10
11185 20:01:54.964916 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=2253447, signals=10
11186 20:01:54.967894 # ok 1 FPSIMD-0-0
11187 20:01:54.968341 # ok 2 FPSIMD-0-1
11188 20:01:54.971167 # ok 3 FPSIMD-1-0
11189 20:01:54.971754 # ok 4 FPSIMD-1-1
11190 20:01:54.974590 # ok 5 FPSIMD-2-0
11191 20:01:54.975099 # ok 6 FPSIMD-2-1
11192 20:01:54.977639 # ok 7 FPSIMD-3-0
11193 20:01:54.978060 # ok 8 FPSIMD-3-1
11194 20:01:54.981118 # ok 9 FPSIMD-4-0
11195 20:01:54.981553 # ok 10 FPSIMD-4-1
11196 20:01:54.984479 # ok 11 FPSIMD-5-0
11197 20:01:54.984889 # ok 12 FPSIMD-5-1
11198 20:01:54.987591 # ok 13 FPSIMD-6-0
11199 20:01:54.988132 # ok 14 FPSIMD-6-1
11200 20:01:54.990699 # ok 15 FPSIMD-7-0
11201 20:01:54.990804 # ok 16 FPSIMD-7-1
11202 20:01:55.000575 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1137066, signals=9
11203 20:01:55.007324 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1095698, signals=10
11204 20:01:55.013663 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1092430, signals=10
11205 20:01:55.020498 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1142519, signals=10
11206 20:01:55.027269 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1090895, signals=10
11207 20:01:55.033919 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1097884, signals=9
11208 20:01:55.043918 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1089840, signals=10
11209 20:01:55.050426 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1086873, signals=10
11210 20:01:55.056684 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1138486, signals=9
11211 20:01:55.063297 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11212 20:01:55.063379 ok 29 selftests: arm64: fp-stress
11213 20:01:55.066815 # selftests: arm64: sve-ptrace
11214 20:01:55.070018 # TAP version 13
11215 20:01:55.070184 # 1..4104
11216 20:01:55.073274 # ok 2 # SKIP SVE not available
11217 20:01:55.076664 # # Planned tests != run tests (4104 != 1)
11218 20:01:55.083294 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11219 20:01:55.086459 ok 30 selftests: arm64: sve-ptrace # SKIP
11220 20:01:55.089624 # selftests: arm64: sve-probe-vls
11221 20:01:55.089800 # TAP version 13
11222 20:01:55.089911 # 1..2
11223 20:01:55.093060 # ok 2 # SKIP SVE not available
11224 20:01:55.096323 # # Planned tests != run tests (2 != 1)
11225 20:01:55.103013 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11226 20:01:55.106256 ok 31 selftests: arm64: sve-probe-vls # SKIP
11227 20:01:55.109431 # selftests: arm64: vec-syscfg
11228 20:01:55.109628 # TAP version 13
11229 20:01:55.113028 # 1..20
11230 20:01:55.113262 # ok 1 # SKIP SVE not supported
11231 20:01:55.116258 # ok 2 # SKIP SVE not supported
11232 20:01:55.119666 # ok 3 # SKIP SVE not supported
11233 20:01:55.122704 # ok 4 # SKIP SVE not supported
11234 20:01:55.125894 # ok 5 # SKIP SVE not supported
11235 20:01:55.129135 # ok 6 # SKIP SVE not supported
11236 20:01:55.132627 # ok 7 # SKIP SVE not supported
11237 20:01:55.136146 # ok 8 # SKIP SVE not supported
11238 20:01:55.136261 # ok 9 # SKIP SVE not supported
11239 20:01:55.139362 # ok 10 # SKIP SVE not supported
11240 20:01:55.143022 # ok 11 # SKIP SME not supported
11241 20:01:55.145990 # ok 12 # SKIP SME not supported
11242 20:01:55.149254 # ok 13 # SKIP SME not supported
11243 20:01:55.152531 # ok 14 # SKIP SME not supported
11244 20:01:55.155947 # ok 15 # SKIP SME not supported
11245 20:01:55.159421 # ok 16 # SKIP SME not supported
11246 20:01:55.162875 # ok 17 # SKIP SME not supported
11247 20:01:55.163096 # ok 18 # SKIP SME not supported
11248 20:01:55.166235 # ok 19 # SKIP SME not supported
11249 20:01:55.169106 # ok 20 # SKIP SME not supported
11250 20:01:55.175811 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11251 20:01:55.179401 ok 32 selftests: arm64: vec-syscfg
11252 20:01:55.179679 # selftests: arm64: za-fork
11253 20:01:55.182468 # TAP version 13
11254 20:01:55.182718 # 1..1
11255 20:01:55.185688 # # PID: 1248
11256 20:01:55.185923 # # SME support not present
11257 20:01:55.188969 # ok 0 skipped
11258 20:01:55.192423 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11259 20:01:55.195667 ok 33 selftests: arm64: za-fork
11260 20:01:55.198929 # selftests: arm64: za-ptrace
11261 20:01:55.199387 # TAP version 13
11262 20:01:55.202522 # 1..1
11263 20:01:55.202980 # ok 2 # SKIP SME not available
11264 20:01:55.208800 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11265 20:01:55.212082 ok 34 selftests: arm64: za-ptrace # SKIP
11266 20:01:55.215508 # selftests: arm64: check_buffer_fill
11267 20:01:55.253017 # # SKIP: MTE features unavailable
11268 20:01:55.260812 ok 35 selftests: arm64: check_buffer_fill # SKIP
11269 20:01:55.276809 # selftests: arm64: check_child_memory
11270 20:01:55.346788 # # SKIP: MTE features unavailable
11271 20:01:55.353744 ok 36 selftests: arm64: check_child_memory # SKIP
11272 20:01:55.371331 # selftests: arm64: check_gcr_el1_cswitch
11273 20:01:55.428587 # # SKIP: MTE features unavailable
11274 20:01:55.435838 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11275 20:01:55.453455 # selftests: arm64: check_ksm_options
11276 20:01:55.509278 # # SKIP: MTE features unavailable
11277 20:01:55.516332 ok 38 selftests: arm64: check_ksm_options # SKIP
11278 20:01:55.532029 # selftests: arm64: check_mmap_options
11279 20:01:55.601185 # # SKIP: MTE features unavailable
11280 20:01:55.608470 ok 39 selftests: arm64: check_mmap_options # SKIP
11281 20:01:55.619180 # selftests: arm64: check_prctl
11282 20:01:55.685146 # TAP version 13
11283 20:01:55.685699 # 1..5
11284 20:01:55.688196 # ok 1 check_basic_read
11285 20:01:55.688657 # ok 2 NONE
11286 20:01:55.692121 # ok 3 # SKIP SYNC
11287 20:01:55.692726 # ok 4 # SKIP ASYNC
11288 20:01:55.695088 # ok 5 # SKIP SYNC+ASYNC
11289 20:01:55.698091 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11290 20:01:55.701244 ok 40 selftests: arm64: check_prctl
11291 20:01:55.709163 # selftests: arm64: check_tags_inclusion
11292 20:01:55.780761 # # SKIP: MTE features unavailable
11293 20:01:55.788482 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11294 20:01:55.802547 # selftests: arm64: check_user_mem
11295 20:01:55.872454 # # SKIP: MTE features unavailable
11296 20:01:55.879717 ok 42 selftests: arm64: check_user_mem # SKIP
11297 20:01:55.891438 # selftests: arm64: btitest
11298 20:01:55.948328 # TAP version 13
11299 20:01:55.948884 # 1..18
11300 20:01:55.951356 # # HWCAP_PACA not present
11301 20:01:55.954488 # # HWCAP2_BTI not present
11302 20:01:55.957929 # # Test binary built for BTI
11303 20:01:55.961314 # ok 1 nohint_func/call_using_br_x0 # SKIP
11304 20:01:55.964397 # ok 1 nohint_func/call_using_br_x16 # SKIP
11305 20:01:55.967754 # ok 1 nohint_func/call_using_blr # SKIP
11306 20:01:55.971223 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11307 20:01:55.974423 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11308 20:01:55.981080 # ok 1 bti_none_func/call_using_blr # SKIP
11309 20:01:55.984490 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11310 20:01:55.987556 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11311 20:01:55.990677 # ok 1 bti_c_func/call_using_blr # SKIP
11312 20:01:55.993984 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11313 20:01:55.997710 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11314 20:01:56.000946 # ok 1 bti_j_func/call_using_blr # SKIP
11315 20:01:56.004413 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11316 20:01:56.010616 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11317 20:01:56.014270 # ok 1 bti_jc_func/call_using_blr # SKIP
11318 20:01:56.017427 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11319 20:01:56.020552 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11320 20:01:56.024136 # ok 1 paciasp_func/call_using_blr # SKIP
11321 20:01:56.030650 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11322 20:01:56.034036 # # WARNING - EXPECTED TEST COUNT WRONG
11323 20:01:56.037290 ok 43 selftests: arm64: btitest
11324 20:01:56.040530 # selftests: arm64: nobtitest
11325 20:01:56.040943 # TAP version 13
11326 20:01:56.041272 # 1..18
11327 20:01:56.043681 # # HWCAP_PACA not present
11328 20:01:56.047026 # # HWCAP2_BTI not present
11329 20:01:56.050382 # # Test binary not built for BTI
11330 20:01:56.053929 # ok 1 nohint_func/call_using_br_x0 # SKIP
11331 20:01:56.056984 # ok 1 nohint_func/call_using_br_x16 # SKIP
11332 20:01:56.060238 # ok 1 nohint_func/call_using_blr # SKIP
11333 20:01:56.063759 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11334 20:01:56.067183 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11335 20:01:56.073639 # ok 1 bti_none_func/call_using_blr # SKIP
11336 20:01:56.076840 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11337 20:01:56.080655 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11338 20:01:56.083765 # ok 1 bti_c_func/call_using_blr # SKIP
11339 20:01:56.087127 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11340 20:01:56.090120 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11341 20:01:56.093794 # ok 1 bti_j_func/call_using_blr # SKIP
11342 20:01:56.100441 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11343 20:01:56.103422 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11344 20:01:56.106928 # ok 1 bti_jc_func/call_using_blr # SKIP
11345 20:01:56.110004 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11346 20:01:56.113810 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11347 20:01:56.116557 # ok 1 paciasp_func/call_using_blr # SKIP
11348 20:01:56.123135 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11349 20:01:56.126665 # # WARNING - EXPECTED TEST COUNT WRONG
11350 20:01:56.129949 ok 44 selftests: arm64: nobtitest
11351 20:01:56.132945 # selftests: arm64: hwcap
11352 20:01:56.133405 # TAP version 13
11353 20:01:56.133770 # 1..28
11354 20:01:56.136498 # ok 1 cpuinfo_match_RNG
11355 20:01:56.139805 # # SIGILL reported for RNG
11356 20:01:56.140307 # ok 2 # SKIP sigill_RNG
11357 20:01:56.143063 # ok 3 cpuinfo_match_SME
11358 20:01:56.146459 # ok 4 sigill_SME
11359 20:01:56.146880 # ok 5 cpuinfo_match_SVE
11360 20:01:56.150071 # ok 6 sigill_SVE
11361 20:01:56.150603 # ok 7 cpuinfo_match_SVE 2
11362 20:01:56.153144 # # SIGILL reported for SVE 2
11363 20:01:56.156209 # ok 8 # SKIP sigill_SVE 2
11364 20:01:56.159790 # ok 9 cpuinfo_match_SVE AES
11365 20:01:56.163380 # # SIGILL reported for SVE AES
11366 20:01:56.163950 # ok 10 # SKIP sigill_SVE AES
11367 20:01:56.166489 # ok 11 cpuinfo_match_SVE2 PMULL
11368 20:01:56.169714 # # SIGILL reported for SVE2 PMULL
11369 20:01:56.172975 # ok 12 # SKIP sigill_SVE2 PMULL
11370 20:01:56.176387 # ok 13 cpuinfo_match_SVE2 BITPERM
11371 20:01:56.179862 # # SIGILL reported for SVE2 BITPERM
11372 20:01:56.182882 # ok 14 # SKIP sigill_SVE2 BITPERM
11373 20:01:56.186245 # ok 15 cpuinfo_match_SVE2 SHA3
11374 20:01:56.189809 # # SIGILL reported for SVE2 SHA3
11375 20:01:56.193043 # ok 16 # SKIP sigill_SVE2 SHA3
11376 20:01:56.196054 # ok 17 cpuinfo_match_SVE2 SM4
11377 20:01:56.196506 # # SIGILL reported for SVE2 SM4
11378 20:01:56.199621 # ok 18 # SKIP sigill_SVE2 SM4
11379 20:01:56.202609 # ok 19 cpuinfo_match_SVE2 I8MM
11380 20:01:56.206465 # # SIGILL reported for SVE2 I8MM
11381 20:01:56.209392 # ok 20 # SKIP sigill_SVE2 I8MM
11382 20:01:56.212703 # ok 21 cpuinfo_match_SVE2 F32MM
11383 20:01:56.215978 # # SIGILL reported for SVE2 F32MM
11384 20:01:56.219502 # ok 22 # SKIP sigill_SVE2 F32MM
11385 20:01:56.222875 # ok 23 cpuinfo_match_SVE2 F64MM
11386 20:01:56.223419 # # SIGILL reported for SVE2 F64MM
11387 20:01:56.226010 # ok 24 # SKIP sigill_SVE2 F64MM
11388 20:01:56.229628 # ok 25 cpuinfo_match_SVE2 BF16
11389 20:01:56.232605 # # SIGILL reported for SVE2 BF16
11390 20:01:56.235910 # ok 26 # SKIP sigill_SVE2 BF16
11391 20:01:56.239003 # ok 27 cpuinfo_match_SVE2 EBF16
11392 20:01:56.242527 # ok 28 # SKIP sigill_SVE2 EBF16
11393 20:01:56.245757 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11394 20:01:56.249121 ok 45 selftests: arm64: hwcap
11395 20:01:56.252798 # selftests: arm64: ptrace
11396 20:01:56.253255 # TAP version 13
11397 20:01:56.255673 # 1..7
11398 20:01:56.258760 # # Parent is 1490, child is 1491
11399 20:01:56.259247 # ok 1 read_tpidr_one
11400 20:01:56.262211 # ok 2 write_tpidr_one
11401 20:01:56.262627 # ok 3 verify_tpidr_one
11402 20:01:56.265460 # ok 4 count_tpidrs
11403 20:01:56.268933 # ok 5 tpidr2_write
11404 20:01:56.269348 # ok 6 tpidr2_read
11405 20:01:56.271985 # ok 7 write_tpidr_only
11406 20:01:56.275444 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11407 20:01:56.278694 ok 46 selftests: arm64: ptrace
11408 20:01:56.282012 # selftests: arm64: syscall-abi
11409 20:01:56.282428 # TAP version 13
11410 20:01:56.285465 # 1..2
11411 20:01:56.285930 # ok 1 getpid() FPSIMD
11412 20:01:56.288851 # ok 2 sched_yield() FPSIMD
11413 20:01:56.295397 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11414 20:01:56.298501 ok 47 selftests: arm64: syscall-abi
11415 20:01:56.299028 # selftests: arm64: tpidr2
11416 20:01:56.318163 # TAP version 13
11417 20:01:56.318729 # 1..5
11418 20:01:56.321380 # # PID: 1527
11419 20:01:56.321841 # # SME support not present
11420 20:01:56.324617 # ok 0 skipped, TPIDR2 not supported
11421 20:01:56.327957 # ok 1 skipped, TPIDR2 not supported
11422 20:01:56.331131 # ok 2 skipped, TPIDR2 not supported
11423 20:01:56.334400 # ok 3 skipped, TPIDR2 not supported
11424 20:01:56.337677 # ok 4 skipped, TPIDR2 not supported
11425 20:01:56.344649 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11426 20:01:56.347305 ok 48 selftests: arm64: tpidr2
11427 20:01:56.974485 arm64_tags_test pass
11428 20:01:56.977667 arm64_run_tags_test_sh pass
11429 20:01:56.981255 arm64_fake_sigreturn_bad_magic pass
11430 20:01:56.984554 arm64_fake_sigreturn_bad_size pass
11431 20:01:56.987669 arm64_fake_sigreturn_bad_size_for_magic0 pass
11432 20:01:56.991230 arm64_fake_sigreturn_duplicated_fpsimd pass
11433 20:01:56.994237 arm64_fake_sigreturn_misaligned_sp pass
11434 20:01:56.997775 arm64_fake_sigreturn_missing_fpsimd pass
11435 20:01:57.000764 arm64_fake_sigreturn_sme_change_vl skip
11436 20:01:57.007478 arm64_fake_sigreturn_sve_change_vl skip
11437 20:01:57.010834 arm64_mangle_pstate_invalid_compat_toggle pass
11438 20:01:57.014036 arm64_mangle_pstate_invalid_daif_bits pass
11439 20:01:57.017214 arm64_mangle_pstate_invalid_mode_el1h pass
11440 20:01:57.020897 arm64_mangle_pstate_invalid_mode_el1t pass
11441 20:01:57.024589 arm64_mangle_pstate_invalid_mode_el2h pass
11442 20:01:57.031056 arm64_mangle_pstate_invalid_mode_el2t pass
11443 20:01:57.033985 arm64_mangle_pstate_invalid_mode_el3h pass
11444 20:01:57.037586 arm64_mangle_pstate_invalid_mode_el3t pass
11445 20:01:57.040571 arm64_sme_trap_no_sm skip
11446 20:01:57.041032 arm64_sme_trap_non_streaming skip
11447 20:01:57.044081 arm64_sme_trap_za pass
11448 20:01:57.047380 arm64_sme_vl skip
11449 20:01:57.047937 arm64_ssve_regs skip
11450 20:01:57.050531 arm64_sve_regs skip
11451 20:01:57.051095 arm64_sve_vl skip
11452 20:01:57.053696 arm64_za_no_regs skip
11453 20:01:57.054161 arm64_za_regs skip
11454 20:01:57.056961 arm64_pac_pauth_not_enabled skip
11455 20:01:57.060143 arm64_pac_pauth_not_enabled skip
11456 20:01:57.063887 arm64_pac_generic_pauth_not_enabled skip
11457 20:01:57.067097 arm64_pac_pauth_not_enabled skip
11458 20:01:57.070630 arm64_pac_pauth_not_enabled skip
11459 20:01:57.073869 arm64_pac_pauth_not_enabled skip
11460 20:01:57.077478 arm64_pac_generic_pauth_not_enabled skip
11461 20:01:57.078046 arm64_pac pass
11462 20:01:57.080570 arm64_fp-stress_FPSIMD-0-0 pass
11463 20:01:57.083850 arm64_fp-stress_FPSIMD-0-1 pass
11464 20:01:57.086810 arm64_fp-stress_FPSIMD-1-0 pass
11465 20:01:57.090225 arm64_fp-stress_FPSIMD-1-1 pass
11466 20:01:57.093510 arm64_fp-stress_FPSIMD-2-0 pass
11467 20:01:57.096673 arm64_fp-stress_FPSIMD-2-1 pass
11468 20:01:57.100003 arm64_fp-stress_FPSIMD-3-0 pass
11469 20:01:57.100756 arm64_fp-stress_FPSIMD-3-1 pass
11470 20:01:57.103406 arm64_fp-stress_FPSIMD-4-0 pass
11471 20:01:57.106911 arm64_fp-stress_FPSIMD-4-1 pass
11472 20:01:57.109922 arm64_fp-stress_FPSIMD-5-0 pass
11473 20:01:57.113655 arm64_fp-stress_FPSIMD-5-1 pass
11474 20:01:57.116637 arm64_fp-stress_FPSIMD-6-0 pass
11475 20:01:57.119759 arm64_fp-stress_FPSIMD-6-1 pass
11476 20:01:57.120250 arm64_fp-stress_FPSIMD-7-0 pass
11477 20:01:57.123446 arm64_fp-stress_FPSIMD-7-1 pass
11478 20:01:57.126749 arm64_fp-stress pass
11479 20:01:57.129950 arm64_sve-ptrace_sve_not_available skip
11480 20:01:57.133590 arm64_sve-ptrace skip
11481 20:01:57.136759 arm64_sve-probe-vls_sve_not_available skip
11482 20:01:57.137350 arm64_sve-probe-vls skip
11483 20:01:57.139805 arm64_vec-syscfg_sve_not_supported skip
11484 20:01:57.146412 arm64_vec-syscfg_sve_not_supported skip
11485 20:01:57.149568 arm64_vec-syscfg_sve_not_supported skip
11486 20:01:57.153107 arm64_vec-syscfg_sve_not_supported skip
11487 20:01:57.156348 arm64_vec-syscfg_sve_not_supported skip
11488 20:01:57.159462 arm64_vec-syscfg_sve_not_supported skip
11489 20:01:57.163085 arm64_vec-syscfg_sve_not_supported skip
11490 20:01:57.166298 arm64_vec-syscfg_sve_not_supported skip
11491 20:01:57.169859 arm64_vec-syscfg_sve_not_supported skip
11492 20:01:57.173077 arm64_vec-syscfg_sve_not_supported skip
11493 20:01:57.176459 arm64_vec-syscfg_sme_not_supported skip
11494 20:01:57.179786 arm64_vec-syscfg_sme_not_supported skip
11495 20:01:57.183007 arm64_vec-syscfg_sme_not_supported skip
11496 20:01:57.186210 arm64_vec-syscfg_sme_not_supported skip
11497 20:01:57.192786 arm64_vec-syscfg_sme_not_supported skip
11498 20:01:57.196089 arm64_vec-syscfg_sme_not_supported skip
11499 20:01:57.199608 arm64_vec-syscfg_sme_not_supported skip
11500 20:01:57.202663 arm64_vec-syscfg_sme_not_supported skip
11501 20:01:57.205674 arm64_vec-syscfg_sme_not_supported skip
11502 20:01:57.209089 arm64_vec-syscfg_sme_not_supported skip
11503 20:01:57.212585 arm64_vec-syscfg pass
11504 20:01:57.213155 arm64_za-fork_skipped pass
11505 20:01:57.215658 arm64_za-fork pass
11506 20:01:57.219401 arm64_za-ptrace_sme_not_available skip
11507 20:01:57.219969 arm64_za-ptrace skip
11508 20:01:57.222605 arm64_check_buffer_fill skip
11509 20:01:57.225631 arm64_check_child_memory skip
11510 20:01:57.228902 arm64_check_gcr_el1_cswitch skip
11511 20:01:57.232344 arm64_check_ksm_options skip
11512 20:01:57.235863 arm64_check_mmap_options skip
11513 20:01:57.238604 arm64_check_prctl_check_basic_read pass
11514 20:01:57.239068 arm64_check_prctl_NONE pass
11515 20:01:57.242077 arm64_check_prctl_sync skip
11516 20:01:57.245608 arm64_check_prctl_async skip
11517 20:01:57.248920 arm64_check_prctl_sync_async skip
11518 20:01:57.252466 arm64_check_prctl pass
11519 20:01:57.253028 arm64_check_tags_inclusion skip
11520 20:01:57.255387 arm64_check_user_mem skip
11521 20:01:57.258735 arm64_btitest_nohint_func_call_using_br_x0 skip
11522 20:01:57.265292 arm64_btitest_nohint_func_call_using_br_x16 skip
11523 20:01:57.268444 arm64_btitest_nohint_func_call_using_blr skip
11524 20:01:57.271842 arm64_btitest_bti_none_func_call_using_br_x0 skip
11525 20:01:57.278417 arm64_btitest_bti_none_func_call_using_br_x16 skip
11526 20:01:57.281798 arm64_btitest_bti_none_func_call_using_blr skip
11527 20:01:57.285122 arm64_btitest_bti_c_func_call_using_br_x0 skip
11528 20:01:57.291679 arm64_btitest_bti_c_func_call_using_br_x16 skip
11529 20:01:57.295078 arm64_btitest_bti_c_func_call_using_blr skip
11530 20:01:57.298376 arm64_btitest_bti_j_func_call_using_br_x0 skip
11531 20:01:57.301720 arm64_btitest_bti_j_func_call_using_br_x16 skip
11532 20:01:57.305053 arm64_btitest_bti_j_func_call_using_blr skip
11533 20:01:57.311351 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11534 20:01:57.314557 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11535 20:01:57.317853 arm64_btitest_bti_jc_func_call_using_blr skip
11536 20:01:57.324901 arm64_btitest_paciasp_func_call_using_br_x0 skip
11537 20:01:57.327744 arm64_btitest_paciasp_func_call_using_br_x16 skip
11538 20:01:57.330990 arm64_btitest_paciasp_func_call_using_blr skip
11539 20:01:57.334520 arm64_btitest pass
11540 20:01:57.338091 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11541 20:01:57.341015 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11542 20:01:57.347929 arm64_nobtitest_nohint_func_call_using_blr skip
11543 20:01:57.350933 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11544 20:01:57.357479 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11545 20:01:57.361164 arm64_nobtitest_bti_none_func_call_using_blr skip
11546 20:01:57.364170 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11547 20:01:57.370777 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11548 20:01:57.373908 arm64_nobtitest_bti_c_func_call_using_blr skip
11549 20:01:57.377324 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11550 20:01:57.380479 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11551 20:01:57.387430 arm64_nobtitest_bti_j_func_call_using_blr skip
11552 20:01:57.390447 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11553 20:01:57.393918 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11554 20:01:57.400698 arm64_nobtitest_bti_jc_func_call_using_blr skip
11555 20:01:57.403761 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11556 20:01:57.407068 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11557 20:01:57.413540 arm64_nobtitest_paciasp_func_call_using_blr skip
11558 20:01:57.413954 arm64_nobtitest pass
11559 20:01:57.417004 arm64_hwcap_cpuinfo_match_RNG pass
11560 20:01:57.421110 arm64_hwcap_sigill_rng skip
11561 20:01:57.423403 arm64_hwcap_cpuinfo_match_SME pass
11562 20:01:57.426763 arm64_hwcap_sigill_SME pass
11563 20:01:57.430472 arm64_hwcap_cpuinfo_match_SVE pass
11564 20:01:57.430892 arm64_hwcap_sigill_SVE pass
11565 20:01:57.433503 arm64_hwcap_cpuinfo_match_SVE_2 pass
11566 20:01:57.436867 arm64_hwcap_sigill_sve_2 skip
11567 20:01:57.440316 arm64_hwcap_cpuinfo_match_SVE_AES pass
11568 20:01:57.443425 arm64_hwcap_sigill_sve_aes skip
11569 20:01:57.446793 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11570 20:01:57.450045 arm64_hwcap_sigill_sve2_pmull skip
11571 20:01:57.453334 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11572 20:01:57.456484 arm64_hwcap_sigill_sve2_bitperm skip
11573 20:01:57.463195 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11574 20:01:57.463617 arm64_hwcap_sigill_sve2_sha3 skip
11575 20:01:57.470116 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11576 20:01:57.470535 arm64_hwcap_sigill_sve2_sm4 skip
11577 20:01:57.476578 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11578 20:01:57.476999 arm64_hwcap_sigill_sve2_i8mm skip
11579 20:01:57.483029 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11580 20:01:57.486159 arm64_hwcap_sigill_sve2_f32mm skip
11581 20:01:57.489722 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11582 20:01:57.492941 arm64_hwcap_sigill_sve2_f64mm skip
11583 20:01:57.496310 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11584 20:01:57.499616 arm64_hwcap_sigill_sve2_bf16 skip
11585 20:01:57.503124 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11586 20:01:57.506432 arm64_hwcap_sigill_sve2_ebf16 skip
11587 20:01:57.506850 arm64_hwcap pass
11588 20:01:57.509503 arm64_ptrace_read_tpidr_one pass
11589 20:01:57.512819 arm64_ptrace_write_tpidr_one pass
11590 20:01:57.516132 arm64_ptrace_verify_tpidr_one pass
11591 20:01:57.519352 arm64_ptrace_count_tpidrs pass
11592 20:01:57.522924 arm64_ptrace_tpidr2_write pass
11593 20:01:57.523449 arm64_ptrace_tpidr2_read pass
11594 20:01:57.526057 arm64_ptrace_write_tpidr_only pass
11595 20:01:57.529518 arm64_ptrace pass
11596 20:01:57.532761 arm64_syscall-abi_getpid_FPSIMD pass
11597 20:01:57.535907 arm64_syscall-abi_sched_yield_FPSIMD pass
11598 20:01:57.539347 arm64_syscall-abi pass
11599 20:01:57.542598 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11600 20:01:57.546144 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11601 20:01:57.549309 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11602 20:01:57.555946 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11603 20:01:57.558912 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11604 20:01:57.559335 arm64_tpidr2 pass
11605 20:01:57.565968 + ../../utils/send-to-lava.sh ./output/result.txt
11606 20:01:57.569086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11607 20:01:57.570067 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11609 20:01:57.575542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11610 20:01:57.576281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11612 20:01:57.582396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11613 20:01:57.583150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11615 20:01:57.588769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11616 20:01:57.589478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11618 20:01:57.624771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11619 20:01:57.625478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11621 20:01:57.679614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11622 20:01:57.680331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11624 20:01:57.736896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11625 20:01:57.737640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11627 20:01:57.794605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11628 20:01:57.795325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11630 20:01:57.850543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11631 20:01:57.851244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11633 20:01:57.901409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11634 20:01:57.901767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11636 20:01:57.954714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11637 20:01:57.955407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11639 20:01:58.009884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11640 20:01:58.010210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11642 20:01:58.057651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11643 20:01:58.058007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11645 20:01:58.104668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11646 20:01:58.105314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11648 20:01:58.161693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11649 20:01:58.162401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11651 20:01:58.212709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11652 20:01:58.213438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11654 20:01:58.261461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
11655 20:01:58.261738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
11657 20:01:58.308698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
11658 20:01:58.309229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
11660 20:01:58.363518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
11661 20:01:58.364249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
11663 20:01:58.408302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
11664 20:01:58.408559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
11666 20:01:58.453015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
11668 20:01:58.456053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
11669 20:01:58.501543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
11670 20:01:58.502238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
11672 20:01:58.548627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
11673 20:01:58.548888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
11675 20:01:58.588307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
11676 20:01:58.588572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
11678 20:01:58.633670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
11679 20:01:58.634404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
11681 20:01:58.687052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
11682 20:01:58.687751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
11684 20:01:58.740192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
11685 20:01:58.740465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
11687 20:01:58.784906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
11688 20:01:58.785159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
11690 20:01:58.829796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11692 20:01:58.832771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11693 20:01:58.877404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11695 20:01:58.880600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11696 20:01:58.926699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
11697 20:01:58.926958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
11699 20:01:58.962684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11701 20:01:58.965818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11702 20:01:59.002567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11704 20:01:59.005320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11705 20:01:59.045429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11707 20:01:59.048439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11708 20:01:59.088503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
11709 20:01:59.088821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
11711 20:01:59.123063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
11712 20:01:59.123841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
11714 20:01:59.162882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
11715 20:01:59.163143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
11717 20:01:59.207038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
11718 20:01:59.207363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
11720 20:01:59.261376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
11721 20:01:59.262129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
11723 20:01:59.317775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
11724 20:01:59.318524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
11726 20:01:59.370545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
11727 20:01:59.371237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
11729 20:01:59.421866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
11730 20:01:59.422738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
11732 20:01:59.477683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
11734 20:01:59.480811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
11735 20:01:59.513912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
11736 20:01:59.514167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
11738 20:01:59.550705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
11739 20:01:59.550990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
11741 20:01:59.588780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
11742 20:01:59.589034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
11744 20:01:59.626785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
11745 20:01:59.627043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
11747 20:01:59.667528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
11748 20:01:59.667785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
11750 20:01:59.708348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
11751 20:01:59.709188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
11753 20:01:59.764124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
11754 20:01:59.764903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
11756 20:01:59.820167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
11757 20:01:59.820931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
11759 20:01:59.877564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
11760 20:01:59.878268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
11762 20:01:59.929625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
11763 20:01:59.930009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
11765 20:01:59.983559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
11766 20:01:59.984310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
11768 20:02:00.035889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
11769 20:02:00.036746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
11771 20:02:00.101192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
11772 20:02:00.101873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
11774 20:02:00.156512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
11775 20:02:00.157260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
11777 20:02:00.217276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11778 20:02:00.217951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11780 20:02:00.278130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11781 20:02:00.278878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11783 20:02:00.334525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11784 20:02:00.335227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11786 20:02:00.394081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11787 20:02:00.394824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11789 20:02:00.447977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11790 20:02:00.448730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11792 20:02:00.504495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11793 20:02:00.505194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11795 20:02:00.555037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11796 20:02:00.555322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11798 20:02:00.601099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11799 20:02:00.601357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11801 20:02:00.646801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11802 20:02:00.647112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11804 20:02:00.693448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11805 20:02:00.694090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11807 20:02:00.750377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11808 20:02:00.750664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11810 20:02:00.800157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11811 20:02:00.800905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11813 20:02:00.856657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11814 20:02:00.857384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11816 20:02:00.902119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11817 20:02:00.902449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11819 20:02:00.954679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11820 20:02:00.954978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11822 20:02:01.002821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11823 20:02:01.003552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11825 20:02:01.043663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11826 20:02:01.043924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11828 20:02:01.082144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11829 20:02:01.082407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11831 20:02:01.126361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11832 20:02:01.127144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11834 20:02:01.180682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11835 20:02:01.181035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11837 20:02:01.226275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
11838 20:02:01.226544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
11840 20:02:01.274077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
11841 20:02:01.274435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
11843 20:02:01.328254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
11844 20:02:01.329042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
11846 20:02:01.377439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
11847 20:02:01.377720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
11849 20:02:01.420114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
11850 20:02:01.420389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
11852 20:02:01.470340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
11853 20:02:01.470597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
11855 20:02:01.518720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
11856 20:02:01.519051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
11858 20:02:01.573883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
11860 20:02:01.576918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
11861 20:02:01.625027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
11862 20:02:01.625289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
11864 20:02:01.677246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
11865 20:02:01.677657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
11867 20:02:01.736474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
11868 20:02:01.737220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
11870 20:02:01.786071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
11871 20:02:01.786797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
11873 20:02:01.838521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
11874 20:02:01.839368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
11876 20:02:01.889881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
11877 20:02:01.890586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
11879 20:02:01.947768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
11881 20:02:01.950573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
11882 20:02:02.000700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
11883 20:02:02.001405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
11885 20:02:02.054757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
11886 20:02:02.055537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
11888 20:02:02.106700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
11889 20:02:02.107367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
11891 20:02:02.165851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
11892 20:02:02.166528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
11894 20:02:02.225896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
11895 20:02:02.226624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
11897 20:02:02.277269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
11898 20:02:02.277593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
11900 20:02:02.321397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
11901 20:02:02.321651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
11903 20:02:02.366120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
11904 20:02:02.366376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
11906 20:02:02.418547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
11907 20:02:02.418818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
11909 20:02:02.465376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
11910 20:02:02.465645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
11912 20:02:02.505916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
11913 20:02:02.506224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
11915 20:02:02.554001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
11916 20:02:02.554378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
11918 20:02:02.605636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
11919 20:02:02.606457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
11921 20:02:02.652617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
11922 20:02:02.653415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
11924 20:02:02.708723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
11925 20:02:02.709441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
11927 20:02:02.768588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
11928 20:02:02.769314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
11930 20:02:02.826108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
11931 20:02:02.826956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
11933 20:02:02.876806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
11934 20:02:02.877076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
11936 20:02:02.923588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
11937 20:02:02.923943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
11939 20:02:02.966194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
11940 20:02:02.966524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
11942 20:02:03.012802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
11943 20:02:03.013660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
11945 20:02:03.063570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
11946 20:02:03.064404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
11948 20:02:03.125380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
11949 20:02:03.126123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
11951 20:02:03.187369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
11952 20:02:03.188122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
11954 20:02:03.246181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
11955 20:02:03.246953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
11957 20:02:03.302437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
11958 20:02:03.303261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
11960 20:02:03.360044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
11961 20:02:03.360874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
11963 20:02:03.421763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
11964 20:02:03.422467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
11966 20:02:03.474567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
11967 20:02:03.475269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
11969 20:02:03.531481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
11970 20:02:03.532306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
11972 20:02:03.583453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
11973 20:02:03.584276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
11975 20:02:03.640508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
11976 20:02:03.641214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
11978 20:02:03.696043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
11979 20:02:03.696794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
11981 20:02:03.750358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
11982 20:02:03.751145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
11984 20:02:03.805651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
11985 20:02:03.806369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
11987 20:02:03.857894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
11988 20:02:03.858711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
11990 20:02:03.912141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
11991 20:02:03.912879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
11993 20:02:03.963496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
11994 20:02:03.964309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
11996 20:02:04.016504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
11997 20:02:04.017207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
11999 20:02:04.066443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12000 20:02:04.067271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12002 20:02:04.114210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12003 20:02:04.114919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12005 20:02:04.170933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12006 20:02:04.171650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12008 20:02:04.221252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12009 20:02:04.221976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12011 20:02:04.277101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12012 20:02:04.277878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12014 20:02:04.327601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12015 20:02:04.328314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12017 20:02:04.385269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12018 20:02:04.386086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12020 20:02:04.432670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12021 20:02:04.433376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12023 20:02:04.490218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12024 20:02:04.490963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12026 20:02:04.544931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12027 20:02:04.545722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12029 20:02:04.602469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12030 20:02:04.603222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12032 20:02:04.654413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12033 20:02:04.655230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12035 20:02:04.714168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12036 20:02:04.714916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12038 20:02:04.766614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12039 20:02:04.767452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12041 20:02:04.821733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12042 20:02:04.822624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12044 20:02:04.877267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12045 20:02:04.878254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12047 20:02:04.936353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12048 20:02:04.937049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12050 20:02:04.991969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12052 20:02:04.995047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12053 20:02:05.049360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12054 20:02:05.050125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12056 20:02:05.096220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12058 20:02:05.099014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12059 20:02:05.147053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12060 20:02:05.147809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12062 20:02:05.197430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12064 20:02:05.200488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12065 20:02:05.257665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12066 20:02:05.258344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12068 20:02:05.308385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12069 20:02:05.309055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12071 20:02:05.357438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12072 20:02:05.358108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12074 20:02:05.411691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12075 20:02:05.412366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12077 20:02:05.461045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12078 20:02:05.461561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12080 20:02:05.504784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12082 20:02:05.507661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12083 20:02:05.558530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12084 20:02:05.559206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12086 20:02:05.606287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12087 20:02:05.606556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12089 20:02:05.657920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12090 20:02:05.658655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12092 20:02:05.709842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12094 20:02:05.712716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12095 20:02:05.748039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12097 20:02:05.750912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12098 20:02:05.797470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12099 20:02:05.798162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12101 20:02:05.846860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12102 20:02:05.847738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12104 20:02:05.899650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12105 20:02:05.899941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12107 20:02:05.946053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12108 20:02:05.946317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12110 20:02:05.993545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12111 20:02:05.994227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12113 20:02:06.034728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12114 20:02:06.035065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12116 20:02:06.092217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12117 20:02:06.092914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12119 20:02:06.143865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12120 20:02:06.144683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12122 20:02:06.190830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12123 20:02:06.191094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12125 20:02:06.241415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12126 20:02:06.241940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12128 20:02:06.290559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12129 20:02:06.290960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12131 20:02:06.338267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12132 20:02:06.338522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12134 20:02:06.381408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12135 20:02:06.381708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12137 20:02:06.424548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12138 20:02:06.425354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12140 20:02:06.475818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12141 20:02:06.476270 + set +x
12142 20:02:06.476860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12144 20:02:06.482658 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 11899595_1.6.2.3.5>
12145 20:02:06.483451 Received signal: <ENDRUN> 1_kselftest-arm64 11899595_1.6.2.3.5
12146 20:02:06.483858 Ending use of test pattern.
12147 20:02:06.484240 Ending test lava.1_kselftest-arm64 (11899595_1.6.2.3.5), duration 32.78
12149 20:02:06.485540 <LAVA_TEST_RUNNER EXIT>
12150 20:02:06.486182 ok: lava_test_shell seems to have completed
12151 20:02:06.491512 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12152 20:02:06.492374 end: 3.1 lava-test-shell (duration 00:00:34) [common]
12153 20:02:06.492861 end: 3 lava-test-retry (duration 00:00:34) [common]
12154 20:02:06.493344 start: 4 finalize (timeout 00:07:09) [common]
12155 20:02:06.493824 start: 4.1 power-off (timeout 00:00:30) [common]
12156 20:02:06.494664 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
12157 20:02:06.580309 >> Command sent successfully.
12158 20:02:06.585113 Returned 0 in 0 seconds
12159 20:02:06.686097 end: 4.1 power-off (duration 00:00:00) [common]
12161 20:02:06.687706 start: 4.2 read-feedback (timeout 00:07:08) [common]
12162 20:02:06.689058 Listened to connection for namespace 'common' for up to 1s
12163 20:02:07.689696 Finalising connection for namespace 'common'
12164 20:02:07.690479 Disconnecting from shell: Finalise
12165 20:02:07.690899 / #
12166 20:02:07.792022 end: 4.2 read-feedback (duration 00:00:01) [common]
12167 20:02:07.792857 end: 4 finalize (duration 00:00:01) [common]
12168 20:02:07.793510 Cleaning after the job
12169 20:02:07.794069 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/ramdisk
12170 20:02:07.807116 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/kernel
12171 20:02:07.843179 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/dtb
12172 20:02:07.843467 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/nfsrootfs
12173 20:02:07.937517 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899595/tftp-deploy-c1ag_fai/modules
12174 20:02:07.944898 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11899595
12175 20:02:08.584423 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11899595
12176 20:02:08.584604 Job finished correctly