Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Kernel Errors: 36
- Errors: 0
- Boot result: PASS
1 19:56:33.737482 lava-dispatcher, installed at version: 2023.08
2 19:56:33.737693 start: 0 validate
3 19:56:33.737826 Start time: 2023-10-28 19:56:33.737819+00:00 (UTC)
4 19:56:33.737944 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:56:33.738072 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 19:56:33.999688 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:56:34.000457 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:56:34.270679 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:56:34.271492 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:56:34.543077 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:56:34.543804 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:56:34.806907 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:56:34.807748 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:56:35.085404 validate duration: 1.35
16 19:56:35.086648 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:56:35.087185 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:56:35.087695 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:56:35.088325 Not decompressing ramdisk as can be used compressed.
20 19:56:35.088839 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 19:56:35.089199 saving as /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/ramdisk/initrd.cpio.gz
22 19:56:35.089573 total size: 4665395 (4 MB)
23 19:56:35.094737 progress 0 % (0 MB)
24 19:56:35.103228 progress 5 % (0 MB)
25 19:56:35.110028 progress 10 % (0 MB)
26 19:56:35.114526 progress 15 % (0 MB)
27 19:56:35.118116 progress 20 % (0 MB)
28 19:56:35.121040 progress 25 % (1 MB)
29 19:56:35.123842 progress 30 % (1 MB)
30 19:56:35.126215 progress 35 % (1 MB)
31 19:56:35.128554 progress 40 % (1 MB)
32 19:56:35.130892 progress 45 % (2 MB)
33 19:56:35.132942 progress 50 % (2 MB)
34 19:56:35.134778 progress 55 % (2 MB)
35 19:56:35.136543 progress 60 % (2 MB)
36 19:56:35.138301 progress 65 % (2 MB)
37 19:56:35.139857 progress 70 % (3 MB)
38 19:56:35.141421 progress 75 % (3 MB)
39 19:56:35.142993 progress 80 % (3 MB)
40 19:56:35.144653 progress 85 % (3 MB)
41 19:56:35.146054 progress 90 % (4 MB)
42 19:56:35.147456 progress 95 % (4 MB)
43 19:56:35.148848 progress 100 % (4 MB)
44 19:56:35.149024 4 MB downloaded in 0.06 s (74.82 MB/s)
45 19:56:35.149177 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:56:35.149419 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:56:35.149507 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:56:35.149593 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:56:35.149731 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:56:35.149805 saving as /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/kernel/Image
52 19:56:35.149869 total size: 49304064 (47 MB)
53 19:56:35.149932 No compression specified
54 19:56:35.151056 progress 0 % (0 MB)
55 19:56:35.164029 progress 5 % (2 MB)
56 19:56:35.176811 progress 10 % (4 MB)
57 19:56:35.189465 progress 15 % (7 MB)
58 19:56:35.202259 progress 20 % (9 MB)
59 19:56:35.215250 progress 25 % (11 MB)
60 19:56:35.228007 progress 30 % (14 MB)
61 19:56:35.240856 progress 35 % (16 MB)
62 19:56:35.253645 progress 40 % (18 MB)
63 19:56:35.266556 progress 45 % (21 MB)
64 19:56:35.279160 progress 50 % (23 MB)
65 19:56:35.291882 progress 55 % (25 MB)
66 19:56:35.304663 progress 60 % (28 MB)
67 19:56:35.317430 progress 65 % (30 MB)
68 19:56:35.330089 progress 70 % (32 MB)
69 19:56:35.342862 progress 75 % (35 MB)
70 19:56:35.355600 progress 80 % (37 MB)
71 19:56:35.368219 progress 85 % (39 MB)
72 19:56:35.380968 progress 90 % (42 MB)
73 19:56:35.393427 progress 95 % (44 MB)
74 19:56:35.405939 progress 100 % (47 MB)
75 19:56:35.406146 47 MB downloaded in 0.26 s (183.48 MB/s)
76 19:56:35.406297 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:56:35.406526 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:56:35.406612 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:56:35.406701 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:56:35.406838 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:56:35.406909 saving as /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/dtb/mt8192-asurada-spherion-r0.dtb
83 19:56:35.406969 total size: 47278 (0 MB)
84 19:56:35.407028 No compression specified
85 19:56:35.408160 progress 69 % (0 MB)
86 19:56:35.408439 progress 100 % (0 MB)
87 19:56:35.408595 0 MB downloaded in 0.00 s (27.77 MB/s)
88 19:56:35.408715 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:56:35.408932 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:56:35.409016 start: 1.4 download-retry (timeout 00:10:00) [common]
92 19:56:35.409098 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 19:56:35.409209 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 19:56:35.409279 saving as /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/nfsrootfs/full.rootfs.tar
95 19:56:35.409338 total size: 200813988 (191 MB)
96 19:56:35.409399 Using unxz to decompress xz
97 19:56:35.413422 progress 0 % (0 MB)
98 19:56:35.936349 progress 5 % (9 MB)
99 19:56:36.443375 progress 10 % (19 MB)
100 19:56:37.019627 progress 15 % (28 MB)
101 19:56:37.389134 progress 20 % (38 MB)
102 19:56:37.709246 progress 25 % (47 MB)
103 19:56:38.288739 progress 30 % (57 MB)
104 19:56:38.828016 progress 35 % (67 MB)
105 19:56:39.409828 progress 40 % (76 MB)
106 19:56:39.957877 progress 45 % (86 MB)
107 19:56:40.527423 progress 50 % (95 MB)
108 19:56:41.146948 progress 55 % (105 MB)
109 19:56:41.797150 progress 60 % (114 MB)
110 19:56:41.912843 progress 65 % (124 MB)
111 19:56:42.049595 progress 70 % (134 MB)
112 19:56:42.143798 progress 75 % (143 MB)
113 19:56:42.214044 progress 80 % (153 MB)
114 19:56:42.282034 progress 85 % (162 MB)
115 19:56:42.381769 progress 90 % (172 MB)
116 19:56:42.655206 progress 95 % (181 MB)
117 19:56:43.217964 progress 100 % (191 MB)
118 19:56:43.223057 191 MB downloaded in 7.81 s (24.51 MB/s)
119 19:56:43.223325 end: 1.4.1 http-download (duration 00:00:08) [common]
121 19:56:43.223607 end: 1.4 download-retry (duration 00:00:08) [common]
122 19:56:43.223713 start: 1.5 download-retry (timeout 00:09:52) [common]
123 19:56:43.223814 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 19:56:43.223984 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 19:56:43.224057 saving as /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/modules/modules.tar
126 19:56:43.224154 total size: 8635496 (8 MB)
127 19:56:43.224263 Using unxz to decompress xz
128 19:56:43.228950 progress 0 % (0 MB)
129 19:56:43.249997 progress 5 % (0 MB)
130 19:56:43.272002 progress 10 % (0 MB)
131 19:56:43.297663 progress 15 % (1 MB)
132 19:56:43.322208 progress 20 % (1 MB)
133 19:56:43.347879 progress 25 % (2 MB)
134 19:56:43.377295 progress 30 % (2 MB)
135 19:56:43.402880 progress 35 % (2 MB)
136 19:56:43.428381 progress 40 % (3 MB)
137 19:56:43.453487 progress 45 % (3 MB)
138 19:56:43.480531 progress 50 % (4 MB)
139 19:56:43.506642 progress 55 % (4 MB)
140 19:56:43.533815 progress 60 % (4 MB)
141 19:56:43.559524 progress 65 % (5 MB)
142 19:56:43.585456 progress 70 % (5 MB)
143 19:56:43.610556 progress 75 % (6 MB)
144 19:56:43.637516 progress 80 % (6 MB)
145 19:56:43.670998 progress 85 % (7 MB)
146 19:56:43.697689 progress 90 % (7 MB)
147 19:56:43.722697 progress 95 % (7 MB)
148 19:56:43.746879 progress 100 % (8 MB)
149 19:56:43.752577 8 MB downloaded in 0.53 s (15.59 MB/s)
150 19:56:43.752825 end: 1.5.1 http-download (duration 00:00:01) [common]
152 19:56:43.753081 end: 1.5 download-retry (duration 00:00:01) [common]
153 19:56:43.753175 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 19:56:43.753270 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 19:56:47.201842 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11899585/extract-nfsrootfs-4f9236_g
156 19:56:47.202039 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 19:56:47.202137 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 19:56:47.202304 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q
159 19:56:47.202434 makedir: /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin
160 19:56:47.202534 makedir: /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/tests
161 19:56:47.202632 makedir: /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/results
162 19:56:47.202732 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-add-keys
163 19:56:47.202877 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-add-sources
164 19:56:47.203053 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-background-process-start
165 19:56:47.203280 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-background-process-stop
166 19:56:47.203418 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-common-functions
167 19:56:47.203542 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-echo-ipv4
168 19:56:47.203667 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-install-packages
169 19:56:47.203791 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-installed-packages
170 19:56:47.203916 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-os-build
171 19:56:47.204040 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-probe-channel
172 19:56:47.204163 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-probe-ip
173 19:56:47.204335 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-target-ip
174 19:56:47.204460 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-target-mac
175 19:56:47.204583 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-target-storage
176 19:56:47.204709 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-test-case
177 19:56:47.204836 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-test-event
178 19:56:47.204958 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-test-feedback
179 19:56:47.205146 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-test-raise
180 19:56:47.205271 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-test-reference
181 19:56:47.205395 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-test-runner
182 19:56:47.205517 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-test-set
183 19:56:47.205642 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-test-shell
184 19:56:47.205766 Updating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-add-keys (debian)
185 19:56:47.205918 Updating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-add-sources (debian)
186 19:56:47.206058 Updating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-install-packages (debian)
187 19:56:47.206195 Updating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-installed-packages (debian)
188 19:56:47.206333 Updating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/bin/lava-os-build (debian)
189 19:56:47.206452 Creating /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/environment
190 19:56:47.206546 LAVA metadata
191 19:56:47.206615 - LAVA_JOB_ID=11899585
192 19:56:47.206677 - LAVA_DISPATCHER_IP=192.168.201.1
193 19:56:47.206775 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 19:56:47.206839 skipped lava-vland-overlay
195 19:56:47.206912 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 19:56:47.206989 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 19:56:47.207048 skipped lava-multinode-overlay
198 19:56:47.207119 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 19:56:47.207195 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 19:56:47.207265 Loading test definitions
201 19:56:47.207353 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 19:56:47.207421 Using /lava-11899585 at stage 0
203 19:56:47.207700 uuid=11899585_1.6.2.3.1 testdef=None
204 19:56:47.207787 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 19:56:47.207870 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 19:56:47.208493 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 19:56:47.208706 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 19:56:47.209247 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 19:56:47.209471 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 19:56:47.212802 runner path: /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/0/tests/0_timesync-off test_uuid 11899585_1.6.2.3.1
213 19:56:47.212956 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 19:56:47.213184 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 19:56:47.213254 Using /lava-11899585 at stage 0
217 19:56:47.213348 Fetching tests from https://github.com/kernelci/test-definitions.git
218 19:56:47.213442 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/0/tests/1_kselftest-tpm2'
219 19:56:50.578908 Running '/usr/bin/git checkout kernelci.org
220 19:56:50.930484 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 19:56:50.931229 uuid=11899585_1.6.2.3.5 testdef=None
222 19:56:50.931396 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 19:56:50.931674 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 19:56:50.932487 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 19:56:50.932752 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 19:56:50.933893 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 19:56:50.934172 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 19:56:50.935846 runner path: /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/0/tests/1_kselftest-tpm2 test_uuid 11899585_1.6.2.3.5
232 19:56:50.935978 BOARD='mt8192-asurada-spherion-r0'
233 19:56:50.936082 BRANCH='cip-gitlab'
234 19:56:50.936202 SKIPFILE='/dev/null'
235 19:56:50.936287 SKIP_INSTALL='True'
236 19:56:50.936368 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 19:56:50.936451 TST_CASENAME=''
238 19:56:50.936531 TST_CMDFILES='tpm2'
239 19:56:50.936742 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 19:56:50.937118 Creating lava-test-runner.conf files
242 19:56:50.937224 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899585/lava-overlay-3ahy7l_q/lava-11899585/0 for stage 0
243 19:56:50.937372 - 0_timesync-off
244 19:56:50.937477 - 1_kselftest-tpm2
245 19:56:50.937608 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 19:56:50.937715 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 19:56:58.378964 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 19:56:58.379135 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 19:56:58.379279 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 19:56:58.379397 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 19:56:58.379500 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 19:56:58.498553 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 19:56:58.498952 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 19:56:58.499089 extracting modules file /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899585/extract-nfsrootfs-4f9236_g
255 19:56:58.719672 extracting modules file /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899585/extract-overlay-ramdisk-yoowc7p2/ramdisk
256 19:56:58.948580 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 19:56:58.948757 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 19:56:58.948872 [common] Applying overlay to NFS
259 19:56:58.948954 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899585/compress-overlay-g93i1d3w/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11899585/extract-nfsrootfs-4f9236_g
260 19:56:59.860720 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 19:56:59.860900 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 19:56:59.861017 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 19:56:59.861127 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 19:56:59.861219 Building ramdisk /var/lib/lava/dispatcher/tmp/11899585/extract-overlay-ramdisk-yoowc7p2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11899585/extract-overlay-ramdisk-yoowc7p2/ramdisk
265 19:57:00.269826 >> 119376 blocks
266 19:57:02.229851 rename /var/lib/lava/dispatcher/tmp/11899585/extract-overlay-ramdisk-yoowc7p2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/ramdisk/ramdisk.cpio.gz
267 19:57:02.230307 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 19:57:02.230433 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 19:57:02.230534 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 19:57:02.230636 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/kernel/Image'
271 19:57:14.112748 Returned 0 in 11 seconds
272 19:57:14.213791 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/kernel/image.itb
273 19:57:14.660362 output: FIT description: Kernel Image image with one or more FDT blobs
274 19:57:14.660739 output: Created: Sat Oct 28 20:57:14 2023
275 19:57:14.660814 output: Image 0 (kernel-1)
276 19:57:14.660878 output: Description:
277 19:57:14.660940 output: Created: Sat Oct 28 20:57:14 2023
278 19:57:14.661002 output: Type: Kernel Image
279 19:57:14.661061 output: Compression: lzma compressed
280 19:57:14.661148 output: Data Size: 11047522 Bytes = 10788.60 KiB = 10.54 MiB
281 19:57:14.661208 output: Architecture: AArch64
282 19:57:14.661266 output: OS: Linux
283 19:57:14.661323 output: Load Address: 0x00000000
284 19:57:14.661380 output: Entry Point: 0x00000000
285 19:57:14.661434 output: Hash algo: crc32
286 19:57:14.661486 output: Hash value: da40eda2
287 19:57:14.661540 output: Image 1 (fdt-1)
288 19:57:14.661592 output: Description: mt8192-asurada-spherion-r0
289 19:57:14.661643 output: Created: Sat Oct 28 20:57:14 2023
290 19:57:14.661695 output: Type: Flat Device Tree
291 19:57:14.661747 output: Compression: uncompressed
292 19:57:14.661798 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 19:57:14.661850 output: Architecture: AArch64
294 19:57:14.661901 output: Hash algo: crc32
295 19:57:14.661952 output: Hash value: cc4352de
296 19:57:14.662003 output: Image 2 (ramdisk-1)
297 19:57:14.662054 output: Description: unavailable
298 19:57:14.662105 output: Created: Sat Oct 28 20:57:14 2023
299 19:57:14.662156 output: Type: RAMDisk Image
300 19:57:14.662207 output: Compression: Unknown Compression
301 19:57:14.662258 output: Data Size: 17793697 Bytes = 17376.66 KiB = 16.97 MiB
302 19:57:14.662310 output: Architecture: AArch64
303 19:57:14.662360 output: OS: Linux
304 19:57:14.662412 output: Load Address: unavailable
305 19:57:14.662463 output: Entry Point: unavailable
306 19:57:14.662515 output: Hash algo: crc32
307 19:57:14.662566 output: Hash value: 11cd7fa8
308 19:57:14.662617 output: Default Configuration: 'conf-1'
309 19:57:14.662669 output: Configuration 0 (conf-1)
310 19:57:14.662720 output: Description: mt8192-asurada-spherion-r0
311 19:57:14.662771 output: Kernel: kernel-1
312 19:57:14.662822 output: Init Ramdisk: ramdisk-1
313 19:57:14.662873 output: FDT: fdt-1
314 19:57:14.662925 output: Loadables: kernel-1
315 19:57:14.662975 output:
316 19:57:14.663176 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 19:57:14.663271 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 19:57:14.663370 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 19:57:14.663461 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 19:57:14.663536 No LXC device requested
321 19:57:14.663613 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 19:57:14.663696 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 19:57:14.663774 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 19:57:14.663847 Checking files for TFTP limit of 4294967296 bytes.
325 19:57:14.664398 end: 1 tftp-deploy (duration 00:00:40) [common]
326 19:57:14.664510 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 19:57:14.664601 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 19:57:14.664727 substitutions:
329 19:57:14.664793 - {DTB}: 11899585/tftp-deploy-6kfofeti/dtb/mt8192-asurada-spherion-r0.dtb
330 19:57:14.664856 - {INITRD}: 11899585/tftp-deploy-6kfofeti/ramdisk/ramdisk.cpio.gz
331 19:57:14.664913 - {KERNEL}: 11899585/tftp-deploy-6kfofeti/kernel/Image
332 19:57:14.664970 - {LAVA_MAC}: None
333 19:57:14.665025 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11899585/extract-nfsrootfs-4f9236_g
334 19:57:14.665079 - {NFS_SERVER_IP}: 192.168.201.1
335 19:57:14.665133 - {PRESEED_CONFIG}: None
336 19:57:14.665186 - {PRESEED_LOCAL}: None
337 19:57:14.665239 - {RAMDISK}: 11899585/tftp-deploy-6kfofeti/ramdisk/ramdisk.cpio.gz
338 19:57:14.665292 - {ROOT_PART}: None
339 19:57:14.665344 - {ROOT}: None
340 19:57:14.665396 - {SERVER_IP}: 192.168.201.1
341 19:57:14.665448 - {TEE}: None
342 19:57:14.665500 Parsed boot commands:
343 19:57:14.665552 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 19:57:14.665791 Parsed boot commands: tftpboot 192.168.201.1 11899585/tftp-deploy-6kfofeti/kernel/image.itb 11899585/tftp-deploy-6kfofeti/kernel/cmdline
345 19:57:14.665881 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 19:57:14.665970 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 19:57:14.666064 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 19:57:14.666148 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 19:57:14.666220 Not connected, no need to disconnect.
350 19:57:14.666295 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 19:57:14.666375 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 19:57:14.666441 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 19:57:14.670599 Setting prompt string to ['lava-test: # ']
354 19:57:14.670956 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 19:57:14.671062 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 19:57:14.671178 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 19:57:14.671293 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 19:57:14.671579 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 19:57:19.820623 >> Command sent successfully.
360 19:57:19.826603 Returned 0 in 5 seconds
361 19:57:19.926969 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 19:57:19.927349 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 19:57:19.927490 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 19:57:19.927582 Setting prompt string to 'Starting depthcharge on Spherion...'
366 19:57:19.927650 Changing prompt to 'Starting depthcharge on Spherion...'
367 19:57:19.927717 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 19:57:19.927981 [Enter `^Ec?' for help]
369 19:57:20.101693
370 19:57:20.102298
371 19:57:20.102684 F0: 102B 0000
372 19:57:20.103025
373 19:57:20.105005 F3: 1001 0000 [0200]
374 19:57:20.105463
375 19:57:20.105794 F3: 1001 0000
376 19:57:20.106100
377 19:57:20.106392 F7: 102D 0000
378 19:57:20.106680
379 19:57:20.108056 F1: 0000 0000
380 19:57:20.108521
381 19:57:20.108856 V0: 0000 0000 [0001]
382 19:57:20.109167
383 19:57:20.111330 00: 0007 8000
384 19:57:20.111793
385 19:57:20.112226 01: 0000 0000
386 19:57:20.112559
387 19:57:20.114626 BP: 0C00 0209 [0000]
388 19:57:20.115041
389 19:57:20.115370 G0: 1182 0000
390 19:57:20.115676
391 19:57:20.118174 EC: 0000 0021 [4000]
392 19:57:20.118592
393 19:57:20.118921 S7: 0000 0000 [0000]
394 19:57:20.119227
395 19:57:20.122110 CC: 0000 0000 [0001]
396 19:57:20.122526
397 19:57:20.122857 T0: 0000 0040 [010F]
398 19:57:20.123181
399 19:57:20.125177 Jump to BL
400 19:57:20.125616
401 19:57:20.148580
402 19:57:20.148748
403 19:57:20.148892
404 19:57:20.155244 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 19:57:20.158525 ARM64: Exception handlers installed.
406 19:57:20.162344 ARM64: Testing exception
407 19:57:20.165701 ARM64: Done test exception
408 19:57:20.172607 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 19:57:20.182274 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 19:57:20.189473 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 19:57:20.199523 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 19:57:20.206022 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 19:57:20.216106 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 19:57:20.226772 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 19:57:20.233444 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 19:57:20.251150 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 19:57:20.254804 WDT: Last reset was cold boot
418 19:57:20.258365 SPI1(PAD0) initialized at 2873684 Hz
419 19:57:20.261198 SPI5(PAD0) initialized at 992727 Hz
420 19:57:20.264952 VBOOT: Loading verstage.
421 19:57:20.271288 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 19:57:20.274928 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 19:57:20.278091 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 19:57:20.281300 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 19:57:20.289119 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 19:57:20.295871 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 19:57:20.306485 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 19:57:20.306806
429 19:57:20.307127
430 19:57:20.316401 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 19:57:20.319400 ARM64: Exception handlers installed.
432 19:57:20.322668 ARM64: Testing exception
433 19:57:20.322823 ARM64: Done test exception
434 19:57:20.329312 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 19:57:20.333118 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 19:57:20.347497 Probing TPM: . done!
437 19:57:20.347663 TPM ready after 0 ms
438 19:57:20.354551 Connected to device vid:did:rid of 1ae0:0028:00
439 19:57:20.361024 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 19:57:20.364557 Initialized TPM device CR50 revision 0
441 19:57:20.423555 tlcl_send_startup: Startup return code is 0
442 19:57:20.424297 TPM: setup succeeded
443 19:57:20.437109 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 19:57:20.446627 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 19:57:20.455449 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 19:57:20.464830 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 19:57:20.468152 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 19:57:20.471292 in-header: 03 07 00 00 08 00 00 00
449 19:57:20.474932 in-data: aa e4 47 04 13 02 00 00
450 19:57:20.478008 Chrome EC: UHEPI supported
451 19:57:20.484566 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 19:57:20.497444 in-header: 03 95 00 00 08 00 00 00
453 19:57:20.500907 in-data: 18 20 20 08 00 00 00 00
454 19:57:20.501498 Phase 1
455 19:57:20.504654 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 19:57:20.511500 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 19:57:20.519000 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 19:57:20.519595 Recovery requested (1009000e)
459 19:57:20.529576 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 19:57:20.534808 tlcl_extend: response is 0
461 19:57:20.544460 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 19:57:20.549725 tlcl_extend: response is 0
463 19:57:20.556570 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 19:57:20.577523 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 19:57:20.584903 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 19:57:20.585392
467 19:57:20.585883
468 19:57:20.592280 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 19:57:20.595928 ARM64: Exception handlers installed.
470 19:57:20.599441 ARM64: Testing exception
471 19:57:20.602528 ARM64: Done test exception
472 19:57:20.622372 pmic_efuse_setting: Set efuses in 11 msecs
473 19:57:20.625780 pmwrap_interface_init: Select PMIF_VLD_RDY
474 19:57:20.632427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 19:57:20.635721 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 19:57:20.642718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 19:57:20.645872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 19:57:20.652512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 19:57:20.655701 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 19:57:20.659184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 19:57:20.665850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 19:57:20.669011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 19:57:20.675915 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 19:57:20.679411 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 19:57:20.682850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 19:57:20.689901 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 19:57:20.693555 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 19:57:20.701083 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 19:57:20.708369 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 19:57:20.711578 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 19:57:20.719517 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 19:57:20.723061 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 19:57:20.730451 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 19:57:20.733828 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 19:57:20.741004 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 19:57:20.744491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 19:57:20.752696 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 19:57:20.755626 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 19:57:20.762866 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 19:57:20.766296 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 19:57:20.770006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 19:57:20.777542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 19:57:20.780910 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 19:57:20.788271 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 19:57:20.792002 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 19:57:20.795862 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 19:57:20.803352 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 19:57:20.806928 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 19:57:20.810516 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 19:57:20.818317 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 19:57:20.821564 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 19:57:20.824926 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 19:57:20.828910 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 19:57:20.835683 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 19:57:20.839565 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 19:57:20.843401 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 19:57:20.846799 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 19:57:20.850564 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 19:57:20.857806 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 19:57:20.861210 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 19:57:20.865180 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 19:57:20.868750 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 19:57:20.872752 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 19:57:20.876324 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 19:57:20.887328 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 19:57:20.894515 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 19:57:20.898510 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 19:57:20.905383 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 19:57:20.916844 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 19:57:20.920285 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 19:57:20.923845 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 19:57:20.926965 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 19:57:20.935039 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x38
534 19:57:20.942811 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 19:57:20.946095 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 19:57:20.949777 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 19:57:20.959475 [RTC]rtc_get_frequency_meter,154: input=15, output=765
538 19:57:20.969451 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 19:57:20.979276 [RTC]rtc_get_frequency_meter,154: input=19, output=858
540 19:57:20.988640 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 19:57:20.997515 [RTC]rtc_get_frequency_meter,154: input=16, output=788
542 19:57:21.007937 [RTC]rtc_get_frequency_meter,154: input=16, output=788
543 19:57:21.017452 [RTC]rtc_get_frequency_meter,154: input=17, output=810
544 19:57:21.020768 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 19:57:21.024717 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 19:57:21.032235 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 19:57:21.035393 [RTC]rtc_boot_common,220: irqsta=1, bbpu=81, con=486
548 19:57:21.039703 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 19:57:21.042804 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 19:57:21.046339 ADC[4]: Raw value=669695 ID=5
551 19:57:21.049925 ADC[3]: Raw value=212549 ID=1
552 19:57:21.050430 RAM Code: 0x51
553 19:57:21.053530 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 19:57:21.061166 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 19:57:21.068732 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 19:57:21.072166 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 19:57:21.075447 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 19:57:21.079540 in-header: 03 07 00 00 08 00 00 00
559 19:57:21.083370 in-data: aa e4 47 04 13 02 00 00
560 19:57:21.086539 Chrome EC: UHEPI supported
561 19:57:21.094225 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 19:57:21.097744 in-header: 03 95 00 00 08 00 00 00
563 19:57:21.101858 in-data: 18 20 20 08 00 00 00 00
564 19:57:21.105090 MRC: failed to locate region type 0.
565 19:57:21.109094 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 19:57:21.112575 DRAM-K: Running full calibration
567 19:57:21.120106 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 19:57:21.120710 header.status = 0x0
569 19:57:21.123398 header.version = 0x6 (expected: 0x6)
570 19:57:21.127362 header.size = 0xd00 (expected: 0xd00)
571 19:57:21.130751 header.flags = 0x0
572 19:57:21.134441 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 19:57:21.154409 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 19:57:21.161818 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 19:57:21.162409 dram_init: ddr_geometry: 0
576 19:57:21.165356 [EMI] MDL number = 0
577 19:57:21.165821 [EMI] Get MDL freq = 0
578 19:57:21.169205 dram_init: ddr_type: 0
579 19:57:21.172906 is_discrete_lpddr4: 1
580 19:57:21.173479 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 19:57:21.176479
582 19:57:21.176942
583 19:57:21.177313 [Bian_co] ETT version 0.0.0.1
584 19:57:21.183680 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 19:57:21.184328
586 19:57:21.187371 dramc_set_vcore_voltage set vcore to 650000
587 19:57:21.187951 Read voltage for 800, 4
588 19:57:21.190913 Vio18 = 0
589 19:57:21.191523 Vcore = 650000
590 19:57:21.191899 Vdram = 0
591 19:57:21.192296 Vddq = 0
592 19:57:21.194459 Vmddr = 0
593 19:57:21.195045 dram_init: config_dvfs: 1
594 19:57:21.202296 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 19:57:21.205659 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 19:57:21.209706 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 19:57:21.213221 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 19:57:21.216861 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 19:57:21.220733 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 19:57:21.224264 MEM_TYPE=3, freq_sel=18
601 19:57:21.228148 sv_algorithm_assistance_LP4_1600
602 19:57:21.231409 ============ PULL DRAM RESETB DOWN ============
603 19:57:21.235352 ========== PULL DRAM RESETB DOWN end =========
604 19:57:21.238867 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 19:57:21.242559 ===================================
606 19:57:21.246552 LPDDR4 DRAM CONFIGURATION
607 19:57:21.249844 ===================================
608 19:57:21.250326 EX_ROW_EN[0] = 0x0
609 19:57:21.253470 EX_ROW_EN[1] = 0x0
610 19:57:21.254128 LP4Y_EN = 0x0
611 19:57:21.257113 WORK_FSP = 0x0
612 19:57:21.257575 WL = 0x2
613 19:57:21.260588 RL = 0x2
614 19:57:21.261048 BL = 0x2
615 19:57:21.264481 RPST = 0x0
616 19:57:21.265013 RD_PRE = 0x0
617 19:57:21.265383 WR_PRE = 0x1
618 19:57:21.268000 WR_PST = 0x0
619 19:57:21.268495 DBI_WR = 0x0
620 19:57:21.271464 DBI_RD = 0x0
621 19:57:21.271927 OTF = 0x1
622 19:57:21.275279 ===================================
623 19:57:21.278894 ===================================
624 19:57:21.283203 ANA top config
625 19:57:21.283768 ===================================
626 19:57:21.286374 DLL_ASYNC_EN = 0
627 19:57:21.289585 ALL_SLAVE_EN = 1
628 19:57:21.293094 NEW_RANK_MODE = 1
629 19:57:21.293690 DLL_IDLE_MODE = 1
630 19:57:21.296407 LP45_APHY_COMB_EN = 1
631 19:57:21.299673 TX_ODT_DIS = 1
632 19:57:21.302950 NEW_8X_MODE = 1
633 19:57:21.306476 ===================================
634 19:57:21.309986 ===================================
635 19:57:21.312935 data_rate = 1600
636 19:57:21.313598 CKR = 1
637 19:57:21.316823 DQ_P2S_RATIO = 8
638 19:57:21.320268 ===================================
639 19:57:21.323752 CA_P2S_RATIO = 8
640 19:57:21.327601 DQ_CA_OPEN = 0
641 19:57:21.328256 DQ_SEMI_OPEN = 0
642 19:57:21.331585 CA_SEMI_OPEN = 0
643 19:57:21.334561 CA_FULL_RATE = 0
644 19:57:21.338178 DQ_CKDIV4_EN = 1
645 19:57:21.341606 CA_CKDIV4_EN = 1
646 19:57:21.342107 CA_PREDIV_EN = 0
647 19:57:21.344361 PH8_DLY = 0
648 19:57:21.347649 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 19:57:21.351270 DQ_AAMCK_DIV = 4
650 19:57:21.355099 CA_AAMCK_DIV = 4
651 19:57:21.355589 CA_ADMCK_DIV = 4
652 19:57:21.358372 DQ_TRACK_CA_EN = 0
653 19:57:21.361601 CA_PICK = 800
654 19:57:21.365356 CA_MCKIO = 800
655 19:57:21.368217 MCKIO_SEMI = 0
656 19:57:21.372097 PLL_FREQ = 3068
657 19:57:21.372622 DQ_UI_PI_RATIO = 32
658 19:57:21.376122 CA_UI_PI_RATIO = 0
659 19:57:21.379683 ===================================
660 19:57:21.383648 ===================================
661 19:57:21.387390 memory_type:LPDDR4
662 19:57:21.387951 GP_NUM : 10
663 19:57:21.390562 SRAM_EN : 1
664 19:57:21.391022 MD32_EN : 0
665 19:57:21.394715 ===================================
666 19:57:21.398006 [ANA_INIT] >>>>>>>>>>>>>>
667 19:57:21.401946 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 19:57:21.405222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 19:57:21.405754 ===================================
670 19:57:21.408783 data_rate = 1600,PCW = 0X7600
671 19:57:21.412114 ===================================
672 19:57:21.415629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 19:57:21.422133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 19:57:21.428932 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 19:57:21.432297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 19:57:21.435718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 19:57:21.439049 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 19:57:21.442065 [ANA_INIT] flow start
679 19:57:21.442532 [ANA_INIT] PLL >>>>>>>>
680 19:57:21.445644 [ANA_INIT] PLL <<<<<<<<
681 19:57:21.448780 [ANA_INIT] MIDPI >>>>>>>>
682 19:57:21.449249 [ANA_INIT] MIDPI <<<<<<<<
683 19:57:21.452400 [ANA_INIT] DLL >>>>>>>>
684 19:57:21.455328 [ANA_INIT] flow end
685 19:57:21.458854 ============ LP4 DIFF to SE enter ============
686 19:57:21.462530 ============ LP4 DIFF to SE exit ============
687 19:57:21.465460 [ANA_INIT] <<<<<<<<<<<<<
688 19:57:21.468766 [Flow] Enable top DCM control >>>>>
689 19:57:21.472057 [Flow] Enable top DCM control <<<<<
690 19:57:21.475789 Enable DLL master slave shuffle
691 19:57:21.479036 ==============================================================
692 19:57:21.482600 Gating Mode config
693 19:57:21.485387 ==============================================================
694 19:57:21.488856 Config description:
695 19:57:21.499396 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 19:57:21.505572 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 19:57:21.509162 SELPH_MODE 0: By rank 1: By Phase
698 19:57:21.515546 ==============================================================
699 19:57:21.519153 GAT_TRACK_EN = 1
700 19:57:21.522325 RX_GATING_MODE = 2
701 19:57:21.525835 RX_GATING_TRACK_MODE = 2
702 19:57:21.529039 SELPH_MODE = 1
703 19:57:21.532487 PICG_EARLY_EN = 1
704 19:57:21.533062 VALID_LAT_VALUE = 1
705 19:57:21.539083 ==============================================================
706 19:57:21.542686 Enter into Gating configuration >>>>
707 19:57:21.545626 Exit from Gating configuration <<<<
708 19:57:21.548934 Enter into DVFS_PRE_config >>>>>
709 19:57:21.558793 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 19:57:21.562468 Exit from DVFS_PRE_config <<<<<
711 19:57:21.565507 Enter into PICG configuration >>>>
712 19:57:21.568898 Exit from PICG configuration <<<<
713 19:57:21.572481 [RX_INPUT] configuration >>>>>
714 19:57:21.575494 [RX_INPUT] configuration <<<<<
715 19:57:21.579256 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 19:57:21.585746 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 19:57:21.592409 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 19:57:21.599013 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 19:57:21.605554 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 19:57:21.609144 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 19:57:21.615681 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 19:57:21.618883 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 19:57:21.622350 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 19:57:21.626097 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 19:57:21.632652 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 19:57:21.635819 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 19:57:21.639033 ===================================
728 19:57:21.642175 LPDDR4 DRAM CONFIGURATION
729 19:57:21.645520 ===================================
730 19:57:21.646097 EX_ROW_EN[0] = 0x0
731 19:57:21.649080 EX_ROW_EN[1] = 0x0
732 19:57:21.649729 LP4Y_EN = 0x0
733 19:57:21.652030 WORK_FSP = 0x0
734 19:57:21.652551 WL = 0x2
735 19:57:21.655446 RL = 0x2
736 19:57:21.655931 BL = 0x2
737 19:57:21.659024 RPST = 0x0
738 19:57:21.659491 RD_PRE = 0x0
739 19:57:21.662472 WR_PRE = 0x1
740 19:57:21.663051 WR_PST = 0x0
741 19:57:21.665382 DBI_WR = 0x0
742 19:57:21.665850 DBI_RD = 0x0
743 19:57:21.668755 OTF = 0x1
744 19:57:21.672071 ===================================
745 19:57:21.675535 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 19:57:21.678805 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 19:57:21.685673 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 19:57:21.689204 ===================================
749 19:57:21.689678 LPDDR4 DRAM CONFIGURATION
750 19:57:21.692311 ===================================
751 19:57:21.696004 EX_ROW_EN[0] = 0x10
752 19:57:21.699078 EX_ROW_EN[1] = 0x0
753 19:57:21.699550 LP4Y_EN = 0x0
754 19:57:21.702336 WORK_FSP = 0x0
755 19:57:21.702802 WL = 0x2
756 19:57:21.705648 RL = 0x2
757 19:57:21.706117 BL = 0x2
758 19:57:21.709108 RPST = 0x0
759 19:57:21.709676 RD_PRE = 0x0
760 19:57:21.712637 WR_PRE = 0x1
761 19:57:21.713196 WR_PST = 0x0
762 19:57:21.715622 DBI_WR = 0x0
763 19:57:21.716089 DBI_RD = 0x0
764 19:57:21.718811 OTF = 0x1
765 19:57:21.722517 ===================================
766 19:57:21.728912 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 19:57:21.732702 nWR fixed to 40
768 19:57:21.733269 [ModeRegInit_LP4] CH0 RK0
769 19:57:21.735987 [ModeRegInit_LP4] CH0 RK1
770 19:57:21.738963 [ModeRegInit_LP4] CH1 RK0
771 19:57:21.742552 [ModeRegInit_LP4] CH1 RK1
772 19:57:21.743116 match AC timing 12
773 19:57:21.745871 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 19:57:21.752465 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 19:57:21.755834 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 19:57:21.758916 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 19:57:21.765633 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 19:57:21.766186 [EMI DOE] emi_dcm 0
779 19:57:21.772414 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 19:57:21.772972 ==
781 19:57:21.776111 Dram Type= 6, Freq= 0, CH_0, rank 0
782 19:57:21.779798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 19:57:21.780420 ==
784 19:57:21.786132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 19:57:21.789008 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 19:57:21.799117 [CA 0] Center 37 (7~68) winsize 62
787 19:57:21.802498 [CA 1] Center 37 (7~68) winsize 62
788 19:57:21.805688 [CA 2] Center 35 (5~66) winsize 62
789 19:57:21.808911 [CA 3] Center 35 (5~66) winsize 62
790 19:57:21.811968 [CA 4] Center 34 (4~65) winsize 62
791 19:57:21.815728 [CA 5] Center 34 (4~64) winsize 61
792 19:57:21.816247
793 19:57:21.818997 [CmdBusTrainingLP45] Vref(ca) range 1: 30
794 19:57:21.819587
795 19:57:21.822419 [CATrainingPosCal] consider 1 rank data
796 19:57:21.825777 u2DelayCellTimex100 = 270/100 ps
797 19:57:21.829135 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
798 19:57:21.832420 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
799 19:57:21.838908 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
800 19:57:21.842189 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
801 19:57:21.845700 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
802 19:57:21.849128 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
803 19:57:21.849718
804 19:57:21.852156 CA PerBit enable=1, Macro0, CA PI delay=34
805 19:57:21.852671
806 19:57:21.855787 [CBTSetCACLKResult] CA Dly = 34
807 19:57:21.856437 CS Dly: 6 (0~37)
808 19:57:21.858730 ==
809 19:57:21.859346 Dram Type= 6, Freq= 0, CH_0, rank 1
810 19:57:21.865369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 19:57:21.865940 ==
812 19:57:21.868881 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 19:57:21.875426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 19:57:21.885413 [CA 0] Center 37 (7~68) winsize 62
815 19:57:21.887902 [CA 1] Center 37 (6~68) winsize 63
816 19:57:21.891626 [CA 2] Center 35 (4~66) winsize 63
817 19:57:21.894713 [CA 3] Center 34 (4~65) winsize 62
818 19:57:21.898300 [CA 4] Center 33 (3~64) winsize 62
819 19:57:21.901492 [CA 5] Center 33 (3~64) winsize 62
820 19:57:21.902054
821 19:57:21.904572 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 19:57:21.905134
823 19:57:21.908099 [CATrainingPosCal] consider 2 rank data
824 19:57:21.911119 u2DelayCellTimex100 = 270/100 ps
825 19:57:21.915337 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
826 19:57:21.918447 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
827 19:57:21.924619 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
828 19:57:21.927825 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
829 19:57:21.931361 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
830 19:57:21.934760 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
831 19:57:21.935337
832 19:57:21.937868 CA PerBit enable=1, Macro0, CA PI delay=34
833 19:57:21.938337
834 19:57:21.941471 [CBTSetCACLKResult] CA Dly = 34
835 19:57:21.942042 CS Dly: 6 (0~38)
836 19:57:21.942417
837 19:57:21.944603 ----->DramcWriteLeveling(PI) begin...
838 19:57:21.947875 ==
839 19:57:21.951643 Dram Type= 6, Freq= 0, CH_0, rank 0
840 19:57:21.955253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 19:57:21.955733 ==
842 19:57:21.958956 Write leveling (Byte 0): 28 => 28
843 19:57:21.959468 Write leveling (Byte 1): 28 => 28
844 19:57:21.962535 DramcWriteLeveling(PI) end<-----
845 19:57:21.963002
846 19:57:21.963375 ==
847 19:57:21.966513 Dram Type= 6, Freq= 0, CH_0, rank 0
848 19:57:21.969732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 19:57:21.973107 ==
850 19:57:21.973582 [Gating] SW mode calibration
851 19:57:21.980264 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 19:57:21.986915 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 19:57:21.990153 0 6 0 | B1->B0 | 3333 3232 | 1 0 | (0 0) (1 0)
854 19:57:21.993444 0 6 4 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
855 19:57:22.000240 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 19:57:22.003802 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 19:57:22.006912 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 19:57:22.013595 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 19:57:22.016780 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 19:57:22.020144 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 19:57:22.027081 0 7 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
862 19:57:22.030316 0 7 4 | B1->B0 | 4141 4343 | 1 1 | (0 0) (0 0)
863 19:57:22.033672 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 19:57:22.040295 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 19:57:22.043726 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 19:57:22.047022 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 19:57:22.053856 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 19:57:22.056942 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 19:57:22.060619 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 19:57:22.063565 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 19:57:22.070551 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 19:57:22.073539 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 19:57:22.076844 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 19:57:22.083897 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 19:57:22.086991 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 19:57:22.090386 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 19:57:22.097290 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 19:57:22.100733 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 19:57:22.103822 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 19:57:22.110433 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 19:57:22.113712 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 19:57:22.117023 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 19:57:22.123833 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 19:57:22.127269 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 19:57:22.130492 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
886 19:57:22.137013 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 19:57:22.137568 Total UI for P1: 0, mck2ui 16
888 19:57:22.140822 best dqsien dly found for B0: ( 0, 10, 0)
889 19:57:22.144264 Total UI for P1: 0, mck2ui 16
890 19:57:22.147506 best dqsien dly found for B1: ( 0, 10, 2)
891 19:57:22.150782 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
892 19:57:22.157208 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
893 19:57:22.157777
894 19:57:22.160749 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 19:57:22.163690 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
896 19:57:22.167418 [Gating] SW calibration Done
897 19:57:22.167993 ==
898 19:57:22.170359 Dram Type= 6, Freq= 0, CH_0, rank 0
899 19:57:22.173669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 19:57:22.174142 ==
901 19:57:22.174518 RX Vref Scan: 0
902 19:57:22.177200
903 19:57:22.177748 RX Vref 0 -> 0, step: 1
904 19:57:22.178137
905 19:57:22.180266 RX Delay -130 -> 252, step: 16
906 19:57:22.183865 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 19:57:22.186995 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
908 19:57:22.193855 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 19:57:22.197320 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 19:57:22.200577 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 19:57:22.204024 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 19:57:22.207171 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 19:57:22.214092 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 19:57:22.217281 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
915 19:57:22.220655 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 19:57:22.223776 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 19:57:22.227163 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 19:57:22.233595 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 19:57:22.237120 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 19:57:22.240792 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 19:57:22.244043 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 19:57:22.244702 ==
923 19:57:22.247277 Dram Type= 6, Freq= 0, CH_0, rank 0
924 19:57:22.253801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 19:57:22.254370 ==
926 19:57:22.254745 DQS Delay:
927 19:57:22.257070 DQS0 = 0, DQS1 = 0
928 19:57:22.257535 DQM Delay:
929 19:57:22.257905 DQM0 = 81, DQM1 = 75
930 19:57:22.260904 DQ Delay:
931 19:57:22.263823 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
932 19:57:22.267202 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 19:57:22.270304 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
934 19:57:22.273604 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 19:57:22.274068
936 19:57:22.274436
937 19:57:22.274776 ==
938 19:57:22.276911 Dram Type= 6, Freq= 0, CH_0, rank 0
939 19:57:22.280318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 19:57:22.280792 ==
941 19:57:22.281169
942 19:57:22.281514
943 19:57:22.283672 TX Vref Scan disable
944 19:57:22.284140 == TX Byte 0 ==
945 19:57:22.290376 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
946 19:57:22.293881 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
947 19:57:22.294448 == TX Byte 1 ==
948 19:57:22.300242 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
949 19:57:22.304015 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
950 19:57:22.304643 ==
951 19:57:22.306942 Dram Type= 6, Freq= 0, CH_0, rank 0
952 19:57:22.310464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 19:57:22.311029 ==
954 19:57:22.323985 TX Vref=22, minBit 2, minWin=27, winSum=445
955 19:57:22.327533 TX Vref=24, minBit 3, minWin=27, winSum=447
956 19:57:22.331307 TX Vref=26, minBit 3, minWin=27, winSum=446
957 19:57:22.333937 TX Vref=28, minBit 0, minWin=28, winSum=451
958 19:57:22.337110 TX Vref=30, minBit 0, minWin=28, winSum=454
959 19:57:22.340773 TX Vref=32, minBit 0, minWin=28, winSum=450
960 19:57:22.347978 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
961 19:57:22.348589
962 19:57:22.351392 Final TX Range 1 Vref 30
963 19:57:22.351955
964 19:57:22.352410 ==
965 19:57:22.354483 Dram Type= 6, Freq= 0, CH_0, rank 0
966 19:57:22.358255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 19:57:22.358820 ==
968 19:57:22.359194
969 19:57:22.359714
970 19:57:22.361096 TX Vref Scan disable
971 19:57:22.364709 == TX Byte 0 ==
972 19:57:22.368003 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
973 19:57:22.371341 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
974 19:57:22.374488 == TX Byte 1 ==
975 19:57:22.377671 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
976 19:57:22.381132 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
977 19:57:22.381750
978 19:57:22.384862 [DATLAT]
979 19:57:22.385445 Freq=800, CH0 RK0
980 19:57:22.385828
981 19:57:22.387754 DATLAT Default: 0xa
982 19:57:22.388296 0, 0xFFFF, sum = 0
983 19:57:22.391227 1, 0xFFFF, sum = 0
984 19:57:22.391813 2, 0xFFFF, sum = 0
985 19:57:22.394608 3, 0xFFFF, sum = 0
986 19:57:22.395180 4, 0xFFFF, sum = 0
987 19:57:22.397826 5, 0xFFFF, sum = 0
988 19:57:22.398396 6, 0xFFFF, sum = 0
989 19:57:22.401481 7, 0xFFFF, sum = 0
990 19:57:22.402077 8, 0x0, sum = 1
991 19:57:22.404614 9, 0x0, sum = 2
992 19:57:22.405092 10, 0x0, sum = 3
993 19:57:22.407685 11, 0x0, sum = 4
994 19:57:22.408157 best_step = 9
995 19:57:22.408568
996 19:57:22.408914 ==
997 19:57:22.411199 Dram Type= 6, Freq= 0, CH_0, rank 0
998 19:57:22.414605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 19:57:22.415169 ==
1000 19:57:22.417722 RX Vref Scan: 1
1001 19:57:22.418191
1002 19:57:22.421001 Set Vref Range= 32 -> 127
1003 19:57:22.421470
1004 19:57:22.421834 RX Vref 32 -> 127, step: 1
1005 19:57:22.422177
1006 19:57:22.424625 RX Delay -111 -> 252, step: 8
1007 19:57:22.425297
1008 19:57:22.427731 Set Vref, RX VrefLevel [Byte0]: 32
1009 19:57:22.431235 [Byte1]: 32
1010 19:57:22.434770
1011 19:57:22.435331 Set Vref, RX VrefLevel [Byte0]: 33
1012 19:57:22.438491 [Byte1]: 33
1013 19:57:22.442672
1014 19:57:22.443228 Set Vref, RX VrefLevel [Byte0]: 34
1015 19:57:22.445612 [Byte1]: 34
1016 19:57:22.450187
1017 19:57:22.450746 Set Vref, RX VrefLevel [Byte0]: 35
1018 19:57:22.453307 [Byte1]: 35
1019 19:57:22.457484
1020 19:57:22.458041 Set Vref, RX VrefLevel [Byte0]: 36
1021 19:57:22.460849 [Byte1]: 36
1022 19:57:22.465189
1023 19:57:22.465741 Set Vref, RX VrefLevel [Byte0]: 37
1024 19:57:22.468671 [Byte1]: 37
1025 19:57:22.472791
1026 19:57:22.473247 Set Vref, RX VrefLevel [Byte0]: 38
1027 19:57:22.475988 [Byte1]: 38
1028 19:57:22.480506
1029 19:57:22.480962 Set Vref, RX VrefLevel [Byte0]: 39
1030 19:57:22.483713 [Byte1]: 39
1031 19:57:22.487994
1032 19:57:22.488575 Set Vref, RX VrefLevel [Byte0]: 40
1033 19:57:22.491443 [Byte1]: 40
1034 19:57:22.496066
1035 19:57:22.496568 Set Vref, RX VrefLevel [Byte0]: 41
1036 19:57:22.499143 [Byte1]: 41
1037 19:57:22.503724
1038 19:57:22.504338 Set Vref, RX VrefLevel [Byte0]: 42
1039 19:57:22.506791 [Byte1]: 42
1040 19:57:22.511176
1041 19:57:22.511789 Set Vref, RX VrefLevel [Byte0]: 43
1042 19:57:22.514500 [Byte1]: 43
1043 19:57:22.518962
1044 19:57:22.519510 Set Vref, RX VrefLevel [Byte0]: 44
1045 19:57:22.522490 [Byte1]: 44
1046 19:57:22.526486
1047 19:57:22.527034 Set Vref, RX VrefLevel [Byte0]: 45
1048 19:57:22.529492 [Byte1]: 45
1049 19:57:22.534522
1050 19:57:22.535071 Set Vref, RX VrefLevel [Byte0]: 46
1051 19:57:22.537530 [Byte1]: 46
1052 19:57:22.542022
1053 19:57:22.542572 Set Vref, RX VrefLevel [Byte0]: 47
1054 19:57:22.545033 [Byte1]: 47
1055 19:57:22.549461
1056 19:57:22.550001 Set Vref, RX VrefLevel [Byte0]: 48
1057 19:57:22.552669 [Byte1]: 48
1058 19:57:22.556913
1059 19:57:22.557370 Set Vref, RX VrefLevel [Byte0]: 49
1060 19:57:22.560335 [Byte1]: 49
1061 19:57:22.564722
1062 19:57:22.565179 Set Vref, RX VrefLevel [Byte0]: 50
1063 19:57:22.567795 [Byte1]: 50
1064 19:57:22.572537
1065 19:57:22.573084 Set Vref, RX VrefLevel [Byte0]: 51
1066 19:57:22.575344 [Byte1]: 51
1067 19:57:22.579871
1068 19:57:22.580378 Set Vref, RX VrefLevel [Byte0]: 52
1069 19:57:22.583326 [Byte1]: 52
1070 19:57:22.587754
1071 19:57:22.588398 Set Vref, RX VrefLevel [Byte0]: 53
1072 19:57:22.590978 [Byte1]: 53
1073 19:57:22.595226
1074 19:57:22.595775 Set Vref, RX VrefLevel [Byte0]: 54
1075 19:57:22.599047 [Byte1]: 54
1076 19:57:22.603209
1077 19:57:22.603766 Set Vref, RX VrefLevel [Byte0]: 55
1078 19:57:22.606398 [Byte1]: 55
1079 19:57:22.610764
1080 19:57:22.611313 Set Vref, RX VrefLevel [Byte0]: 56
1081 19:57:22.614153 [Byte1]: 56
1082 19:57:22.619066
1083 19:57:22.619616 Set Vref, RX VrefLevel [Byte0]: 57
1084 19:57:22.621793 [Byte1]: 57
1085 19:57:22.626578
1086 19:57:22.627135 Set Vref, RX VrefLevel [Byte0]: 58
1087 19:57:22.629620 [Byte1]: 58
1088 19:57:22.633744
1089 19:57:22.634271 Set Vref, RX VrefLevel [Byte0]: 59
1090 19:57:22.637240 [Byte1]: 59
1091 19:57:22.641703
1092 19:57:22.642271 Set Vref, RX VrefLevel [Byte0]: 60
1093 19:57:22.644948 [Byte1]: 60
1094 19:57:22.649162
1095 19:57:22.649715 Set Vref, RX VrefLevel [Byte0]: 61
1096 19:57:22.652419 [Byte1]: 61
1097 19:57:22.656326
1098 19:57:22.656787 Set Vref, RX VrefLevel [Byte0]: 62
1099 19:57:22.659639 [Byte1]: 62
1100 19:57:22.663719
1101 19:57:22.664232 Set Vref, RX VrefLevel [Byte0]: 63
1102 19:57:22.667597 [Byte1]: 63
1103 19:57:22.671729
1104 19:57:22.672337 Set Vref, RX VrefLevel [Byte0]: 64
1105 19:57:22.674890 [Byte1]: 64
1106 19:57:22.679060
1107 19:57:22.679523 Set Vref, RX VrefLevel [Byte0]: 65
1108 19:57:22.682753 [Byte1]: 65
1109 19:57:22.687345
1110 19:57:22.687905 Set Vref, RX VrefLevel [Byte0]: 66
1111 19:57:22.690558 [Byte1]: 66
1112 19:57:22.694664
1113 19:57:22.695231 Set Vref, RX VrefLevel [Byte0]: 67
1114 19:57:22.698069 [Byte1]: 67
1115 19:57:22.702313
1116 19:57:22.702771 Set Vref, RX VrefLevel [Byte0]: 68
1117 19:57:22.705720 [Byte1]: 68
1118 19:57:22.710088
1119 19:57:22.710657 Set Vref, RX VrefLevel [Byte0]: 69
1120 19:57:22.713215 [Byte1]: 69
1121 19:57:22.717719
1122 19:57:22.718283 Set Vref, RX VrefLevel [Byte0]: 70
1123 19:57:22.720892 [Byte1]: 70
1124 19:57:22.725396
1125 19:57:22.725958 Set Vref, RX VrefLevel [Byte0]: 71
1126 19:57:22.728928 [Byte1]: 71
1127 19:57:22.732597
1128 19:57:22.733057 Set Vref, RX VrefLevel [Byte0]: 72
1129 19:57:22.736222 [Byte1]: 72
1130 19:57:22.740522
1131 19:57:22.741078 Set Vref, RX VrefLevel [Byte0]: 73
1132 19:57:22.743919 [Byte1]: 73
1133 19:57:22.748342
1134 19:57:22.748903 Final RX Vref Byte 0 = 51 to rank0
1135 19:57:22.751745 Final RX Vref Byte 1 = 56 to rank0
1136 19:57:22.754664 Final RX Vref Byte 0 = 51 to rank1
1137 19:57:22.758142 Final RX Vref Byte 1 = 56 to rank1==
1138 19:57:22.761355 Dram Type= 6, Freq= 0, CH_0, rank 0
1139 19:57:22.768647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1140 19:57:22.769218 ==
1141 19:57:22.769592 DQS Delay:
1142 19:57:22.769934 DQS0 = 0, DQS1 = 0
1143 19:57:22.771508 DQM Delay:
1144 19:57:22.771965 DQM0 = 83, DQM1 = 74
1145 19:57:22.775113 DQ Delay:
1146 19:57:22.778136 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1147 19:57:22.778600 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1148 19:57:22.781489 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1149 19:57:22.784904 DQ12 =84, DQ13 =76, DQ14 =84, DQ15 =84
1150 19:57:22.788119
1151 19:57:22.788749
1152 19:57:22.795126 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1153 19:57:22.798397 CH0 RK0: MR19=606, MR18=3B3B
1154 19:57:22.804676 CH0_RK0: MR19=0x606, MR18=0x3B3B, DQSOSC=394, MR23=63, INC=95, DEC=63
1155 19:57:22.805231
1156 19:57:22.808075 ----->DramcWriteLeveling(PI) begin...
1157 19:57:22.808601 ==
1158 19:57:22.811545 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 19:57:22.814878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1160 19:57:22.815455 ==
1161 19:57:22.817778 Write leveling (Byte 0): 30 => 30
1162 19:57:22.821633 Write leveling (Byte 1): 29 => 29
1163 19:57:22.824841 DramcWriteLeveling(PI) end<-----
1164 19:57:22.825472
1165 19:57:22.825846 ==
1166 19:57:22.828234 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 19:57:22.831223 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1168 19:57:22.831703 ==
1169 19:57:22.835101 [Gating] SW mode calibration
1170 19:57:22.841324 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1171 19:57:22.848278 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1172 19:57:22.851375 0 6 0 | B1->B0 | 3232 3131 | 0 0 | (0 1) (0 1)
1173 19:57:22.855050 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 19:57:22.861276 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 19:57:22.864498 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 19:57:22.868090 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 19:57:22.874542 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 19:57:22.877767 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 19:57:22.881681 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 19:57:22.888302 0 7 0 | B1->B0 | 2e2e 3131 | 1 1 | (0 0) (0 0)
1181 19:57:22.891295 0 7 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1182 19:57:22.894737 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 19:57:22.901060 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 19:57:22.904708 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 19:57:22.907554 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 19:57:22.914592 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 19:57:22.917615 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 19:57:22.921282 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1189 19:57:22.927636 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 19:57:22.931340 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 19:57:22.934689 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 19:57:22.937938 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 19:57:22.944529 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 19:57:22.947698 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 19:57:22.951312 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 19:57:22.957722 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 19:57:22.960884 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 19:57:22.964100 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 19:57:22.970869 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 19:57:22.974177 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 19:57:22.977984 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 19:57:22.984319 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 19:57:22.987768 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 19:57:22.991363 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1205 19:57:22.997961 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1206 19:57:22.998518 Total UI for P1: 0, mck2ui 16
1207 19:57:23.004302 best dqsien dly found for B0: ( 0, 10, 0)
1208 19:57:23.007738 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 19:57:23.011117 Total UI for P1: 0, mck2ui 16
1210 19:57:23.014263 best dqsien dly found for B1: ( 0, 10, 2)
1211 19:57:23.017756 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1212 19:57:23.021029 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1213 19:57:23.021585
1214 19:57:23.024347 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1215 19:57:23.027519 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1216 19:57:23.071788 [Gating] SW calibration Done
1217 19:57:23.072545 ==
1218 19:57:23.073427 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 19:57:23.073811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1220 19:57:23.074162 ==
1221 19:57:23.074493 RX Vref Scan: 0
1222 19:57:23.074811
1223 19:57:23.075123 RX Vref 0 -> 0, step: 1
1224 19:57:23.075435
1225 19:57:23.075743 RX Delay -130 -> 252, step: 16
1226 19:57:23.076166 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1227 19:57:23.076711 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1228 19:57:23.077042 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1229 19:57:23.077350 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1230 19:57:23.077658 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1231 19:57:23.078031 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1232 19:57:23.088591 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1233 19:57:23.089185 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1234 19:57:23.089912 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1235 19:57:23.090290 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1236 19:57:23.090635 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1237 19:57:23.095429 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1238 19:57:23.098984 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1239 19:57:23.102102 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1240 19:57:23.105446 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1241 19:57:23.108667 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1242 19:57:23.109221 ==
1243 19:57:23.112217 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 19:57:23.118643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1245 19:57:23.119188 ==
1246 19:57:23.119552 DQS Delay:
1247 19:57:23.122285 DQS0 = 0, DQS1 = 0
1248 19:57:23.122852 DQM Delay:
1249 19:57:23.125486 DQM0 = 82, DQM1 = 74
1250 19:57:23.125949 DQ Delay:
1251 19:57:23.128649 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1252 19:57:23.131721 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1253 19:57:23.135253 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1254 19:57:23.138486 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1255 19:57:23.138951
1256 19:57:23.139312
1257 19:57:23.139651 ==
1258 19:57:23.142213 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 19:57:23.145121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1260 19:57:23.145678 ==
1261 19:57:23.146047
1262 19:57:23.146386
1263 19:57:23.148558 TX Vref Scan disable
1264 19:57:23.152080 == TX Byte 0 ==
1265 19:57:23.155212 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1266 19:57:23.158560 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1267 19:57:23.161832 == TX Byte 1 ==
1268 19:57:23.165058 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1269 19:57:23.168479 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1270 19:57:23.168941 ==
1271 19:57:23.172097 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 19:57:23.175494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1273 19:57:23.176051 ==
1274 19:57:23.189591 TX Vref=22, minBit 0, minWin=27, winSum=443
1275 19:57:23.192851 TX Vref=24, minBit 2, minWin=27, winSum=453
1276 19:57:23.196253 TX Vref=26, minBit 0, minWin=28, winSum=455
1277 19:57:23.199743 TX Vref=28, minBit 2, minWin=28, winSum=459
1278 19:57:23.203666 TX Vref=30, minBit 4, minWin=28, winSum=461
1279 19:57:23.207487 TX Vref=32, minBit 0, minWin=28, winSum=455
1280 19:57:23.214426 [TxChooseVref] Worse bit 4, Min win 28, Win sum 461, Final Vref 30
1281 19:57:23.214993
1282 19:57:23.215355 Final TX Range 1 Vref 30
1283 19:57:23.218253
1284 19:57:23.218712 ==
1285 19:57:23.221056 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 19:57:23.224918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1287 19:57:23.225486 ==
1288 19:57:23.225856
1289 19:57:23.226193
1290 19:57:23.226516 TX Vref Scan disable
1291 19:57:23.229107 == TX Byte 0 ==
1292 19:57:23.232871 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1293 19:57:23.236105 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1294 19:57:23.239699 == TX Byte 1 ==
1295 19:57:23.242776 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1296 19:57:23.249415 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1297 19:57:23.249978
1298 19:57:23.250344 [DATLAT]
1299 19:57:23.250683 Freq=800, CH0 RK1
1300 19:57:23.251012
1301 19:57:23.252587 DATLAT Default: 0x9
1302 19:57:23.253048 0, 0xFFFF, sum = 0
1303 19:57:23.255843 1, 0xFFFF, sum = 0
1304 19:57:23.256490 2, 0xFFFF, sum = 0
1305 19:57:23.259632 3, 0xFFFF, sum = 0
1306 19:57:23.260237 4, 0xFFFF, sum = 0
1307 19:57:23.262495 5, 0xFFFF, sum = 0
1308 19:57:23.262960 6, 0xFFFF, sum = 0
1309 19:57:23.265974 7, 0xFFFF, sum = 0
1310 19:57:23.266567 8, 0x0, sum = 1
1311 19:57:23.269498 9, 0x0, sum = 2
1312 19:57:23.270057 10, 0x0, sum = 3
1313 19:57:23.272805 11, 0x0, sum = 4
1314 19:57:23.273273 best_step = 9
1315 19:57:23.273636
1316 19:57:23.273974 ==
1317 19:57:23.275942 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 19:57:23.282988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1319 19:57:23.283556 ==
1320 19:57:23.283928 RX Vref Scan: 0
1321 19:57:23.284311
1322 19:57:23.286358 RX Vref 0 -> 0, step: 1
1323 19:57:23.286909
1324 19:57:23.289323 RX Delay -111 -> 252, step: 8
1325 19:57:23.292921 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1326 19:57:23.296056 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1327 19:57:23.302874 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1328 19:57:23.306322 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1329 19:57:23.309374 iDelay=217, Bit 4, Center 92 (-23 ~ 208) 232
1330 19:57:23.312953 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1331 19:57:23.315973 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1332 19:57:23.319188 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1333 19:57:23.326155 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1334 19:57:23.329446 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1335 19:57:23.332791 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1336 19:57:23.335930 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1337 19:57:23.339690 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1338 19:57:23.346257 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1339 19:57:23.349551 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1340 19:57:23.352941 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1341 19:57:23.353494 ==
1342 19:57:23.356282 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 19:57:23.359632 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1344 19:57:23.362705 ==
1345 19:57:23.363166 DQS Delay:
1346 19:57:23.363530 DQS0 = 0, DQS1 = 0
1347 19:57:23.366160 DQM Delay:
1348 19:57:23.366645 DQM0 = 87, DQM1 = 75
1349 19:57:23.367005 DQ Delay:
1350 19:57:23.369426 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1351 19:57:23.372695 DQ4 =92, DQ5 =76, DQ6 =92, DQ7 =100
1352 19:57:23.376252 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1353 19:57:23.379616 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1354 19:57:23.380165
1355 19:57:23.383204
1356 19:57:23.389299 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1357 19:57:23.392658 CH0 RK1: MR19=606, MR18=4A4A
1358 19:57:23.399342 CH0_RK1: MR19=0x606, MR18=0x4A4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1359 19:57:23.402741 [RxdqsGatingPostProcess] freq 800
1360 19:57:23.405940 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1361 19:57:23.409229 Pre-setting of DQS Precalculation
1362 19:57:23.412486 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1363 19:57:23.415936 ==
1364 19:57:23.419248 Dram Type= 6, Freq= 0, CH_1, rank 0
1365 19:57:23.422518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1366 19:57:23.422973 ==
1367 19:57:23.425773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1368 19:57:23.432297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1369 19:57:23.442498 [CA 0] Center 37 (6~68) winsize 63
1370 19:57:23.445341 [CA 1] Center 37 (6~68) winsize 63
1371 19:57:23.448776 [CA 2] Center 34 (4~65) winsize 62
1372 19:57:23.451928 [CA 3] Center 34 (4~65) winsize 62
1373 19:57:23.455828 [CA 4] Center 33 (3~64) winsize 62
1374 19:57:23.458614 [CA 5] Center 33 (3~64) winsize 62
1375 19:57:23.458940
1376 19:57:23.462106 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1377 19:57:23.462524
1378 19:57:23.465301 [CATrainingPosCal] consider 1 rank data
1379 19:57:23.468860 u2DelayCellTimex100 = 270/100 ps
1380 19:57:23.472087 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1381 19:57:23.475333 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1382 19:57:23.482512 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1383 19:57:23.485676 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1384 19:57:23.488587 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1385 19:57:23.492124 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1386 19:57:23.492624
1387 19:57:23.495673 CA PerBit enable=1, Macro0, CA PI delay=33
1388 19:57:23.496273
1389 19:57:23.498826 [CBTSetCACLKResult] CA Dly = 33
1390 19:57:23.499273 CS Dly: 5 (0~36)
1391 19:57:23.502135 ==
1392 19:57:23.502684 Dram Type= 6, Freq= 0, CH_1, rank 1
1393 19:57:23.509309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1394 19:57:23.509850 ==
1395 19:57:23.512137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1396 19:57:23.518492 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1397 19:57:23.528077 [CA 0] Center 36 (6~67) winsize 62
1398 19:57:23.531406 [CA 1] Center 37 (6~68) winsize 63
1399 19:57:23.534864 [CA 2] Center 34 (4~65) winsize 62
1400 19:57:23.538174 [CA 3] Center 34 (4~65) winsize 62
1401 19:57:23.541403 [CA 4] Center 33 (3~64) winsize 62
1402 19:57:23.544785 [CA 5] Center 33 (2~64) winsize 63
1403 19:57:23.545233
1404 19:57:23.548328 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1405 19:57:23.548890
1406 19:57:23.550964 [CATrainingPosCal] consider 2 rank data
1407 19:57:23.554474 u2DelayCellTimex100 = 270/100 ps
1408 19:57:23.557967 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1409 19:57:23.564603 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1410 19:57:23.567737 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1411 19:57:23.571296 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1412 19:57:23.574489 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1413 19:57:23.577960 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1414 19:57:23.578513
1415 19:57:23.580910 CA PerBit enable=1, Macro0, CA PI delay=33
1416 19:57:23.581425
1417 19:57:23.584473 [CBTSetCACLKResult] CA Dly = 33
1418 19:57:23.585048 CS Dly: 5 (0~36)
1419 19:57:23.587655
1420 19:57:23.591061 ----->DramcWriteLeveling(PI) begin...
1421 19:57:23.591474 ==
1422 19:57:23.594704 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 19:57:23.597749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1424 19:57:23.598305 ==
1425 19:57:23.600828 Write leveling (Byte 0): 26 => 26
1426 19:57:23.604121 Write leveling (Byte 1): 23 => 23
1427 19:57:23.607891 DramcWriteLeveling(PI) end<-----
1428 19:57:23.608393
1429 19:57:23.608758 ==
1430 19:57:23.611213 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 19:57:23.614654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1432 19:57:23.615206 ==
1433 19:57:23.617640 [Gating] SW mode calibration
1434 19:57:23.624771 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1435 19:57:23.631300 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1436 19:57:23.634280 0 6 0 | B1->B0 | 3232 2727 | 0 0 | (0 0) (0 0)
1437 19:57:23.637710 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 19:57:23.640990 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 19:57:23.647875 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 19:57:23.651101 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 19:57:23.654502 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 19:57:23.660917 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 19:57:23.664626 0 6 28 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
1444 19:57:23.667683 0 7 0 | B1->B0 | 2f2f 4040 | 0 0 | (0 0) (0 0)
1445 19:57:23.674162 0 7 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1446 19:57:23.677359 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 19:57:23.680877 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 19:57:23.687665 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 19:57:23.690911 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 19:57:23.694376 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 19:57:23.701099 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1452 19:57:23.703987 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1453 19:57:23.707752 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 19:57:23.714262 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 19:57:23.717485 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 19:57:23.720522 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 19:57:23.727609 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 19:57:23.730720 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 19:57:23.733919 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 19:57:23.740945 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 19:57:23.744040 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 19:57:23.747540 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 19:57:23.754423 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 19:57:23.757580 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 19:57:23.760828 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 19:57:23.764694 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 19:57:23.771364 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1468 19:57:23.774276 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1469 19:57:23.777821 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1470 19:57:23.781044 Total UI for P1: 0, mck2ui 16
1471 19:57:23.784030 best dqsien dly found for B0: ( 0, 9, 30)
1472 19:57:23.787463 Total UI for P1: 0, mck2ui 16
1473 19:57:23.790849 best dqsien dly found for B1: ( 0, 9, 30)
1474 19:57:23.794289 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1475 19:57:23.797812 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1476 19:57:23.798366
1477 19:57:23.804452 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1478 19:57:23.807968 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1479 19:57:23.810792 [Gating] SW calibration Done
1480 19:57:23.811298 ==
1481 19:57:23.814280 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 19:57:23.817749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1483 19:57:23.818303 ==
1484 19:57:23.818664 RX Vref Scan: 0
1485 19:57:23.818994
1486 19:57:23.820760 RX Vref 0 -> 0, step: 1
1487 19:57:23.821212
1488 19:57:23.824291 RX Delay -130 -> 252, step: 16
1489 19:57:23.827565 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1490 19:57:23.831176 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1491 19:57:23.837447 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1492 19:57:23.840921 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1493 19:57:23.844139 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1494 19:57:23.847477 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1495 19:57:23.851073 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1496 19:57:23.857947 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1497 19:57:23.861150 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1498 19:57:23.865002 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1499 19:57:23.868689 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1500 19:57:23.872304 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1501 19:57:23.876068 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1502 19:57:23.879858 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1503 19:57:23.883584 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1504 19:57:23.887084 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1505 19:57:23.887638 ==
1506 19:57:23.890822 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 19:57:23.894841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1508 19:57:23.895569 ==
1509 19:57:23.897999 DQS Delay:
1510 19:57:23.898546 DQS0 = 0, DQS1 = 0
1511 19:57:23.901017 DQM Delay:
1512 19:57:23.901464 DQM0 = 84, DQM1 = 76
1513 19:57:23.901817 DQ Delay:
1514 19:57:23.904283 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1515 19:57:23.907868 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =85
1516 19:57:23.911042 DQ8 =53, DQ9 =69, DQ10 =77, DQ11 =69
1517 19:57:23.914662 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1518 19:57:23.915221
1519 19:57:23.915582
1520 19:57:23.917706 ==
1521 19:57:23.918163 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 19:57:23.924918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1523 19:57:23.925478 ==
1524 19:57:23.925844
1525 19:57:23.926181
1526 19:57:23.927905 TX Vref Scan disable
1527 19:57:23.928511 == TX Byte 0 ==
1528 19:57:23.931769 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1529 19:57:23.938097 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1530 19:57:23.938658 == TX Byte 1 ==
1531 19:57:23.940980 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1532 19:57:23.948112 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1533 19:57:23.948723 ==
1534 19:57:23.951422 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 19:57:23.954676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1536 19:57:23.955240 ==
1537 19:57:23.968112 TX Vref=22, minBit 0, minWin=27, winSum=446
1538 19:57:23.971403 TX Vref=24, minBit 3, minWin=27, winSum=448
1539 19:57:23.974794 TX Vref=26, minBit 0, minWin=28, winSum=454
1540 19:57:23.977578 TX Vref=28, minBit 9, minWin=27, winSum=456
1541 19:57:23.980920 TX Vref=30, minBit 0, minWin=28, winSum=460
1542 19:57:23.987587 TX Vref=32, minBit 9, minWin=27, winSum=457
1543 19:57:23.991069 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1544 19:57:23.991682
1545 19:57:23.994472 Final TX Range 1 Vref 30
1546 19:57:23.995025
1547 19:57:23.995430 ==
1548 19:57:23.997527 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 19:57:24.000898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1550 19:57:24.001354 ==
1551 19:57:24.001800
1552 19:57:24.004218
1553 19:57:24.004678 TX Vref Scan disable
1554 19:57:24.007582 == TX Byte 0 ==
1555 19:57:24.010978 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1556 19:57:24.017742 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1557 19:57:24.018291 == TX Byte 1 ==
1558 19:57:24.020704 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1559 19:57:24.027592 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1560 19:57:24.028147
1561 19:57:24.028547 [DATLAT]
1562 19:57:24.028883 Freq=800, CH1 RK0
1563 19:57:24.029205
1564 19:57:24.030770 DATLAT Default: 0xa
1565 19:57:24.031335 0, 0xFFFF, sum = 0
1566 19:57:24.034130 1, 0xFFFF, sum = 0
1567 19:57:24.034594 2, 0xFFFF, sum = 0
1568 19:57:24.037559 3, 0xFFFF, sum = 0
1569 19:57:24.040862 4, 0xFFFF, sum = 0
1570 19:57:24.041473 5, 0xFFFF, sum = 0
1571 19:57:24.044585 6, 0xFFFF, sum = 0
1572 19:57:24.045147 7, 0xFFFF, sum = 0
1573 19:57:24.045514 8, 0x0, sum = 1
1574 19:57:24.047776 9, 0x0, sum = 2
1575 19:57:24.048367 10, 0x0, sum = 3
1576 19:57:24.051114 11, 0x0, sum = 4
1577 19:57:24.051670 best_step = 9
1578 19:57:24.052030
1579 19:57:24.052402 ==
1580 19:57:24.054566 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 19:57:24.060890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1582 19:57:24.061445 ==
1583 19:57:24.061807 RX Vref Scan: 1
1584 19:57:24.062138
1585 19:57:24.064068 Set Vref Range= 32 -> 127
1586 19:57:24.064556
1587 19:57:24.067802 RX Vref 32 -> 127, step: 1
1588 19:57:24.068389
1589 19:57:24.070896 RX Delay -111 -> 252, step: 8
1590 19:57:24.071347
1591 19:57:24.074244 Set Vref, RX VrefLevel [Byte0]: 32
1592 19:57:24.077322 [Byte1]: 32
1593 19:57:24.077773
1594 19:57:24.080771 Set Vref, RX VrefLevel [Byte0]: 33
1595 19:57:24.084053 [Byte1]: 33
1596 19:57:24.084552
1597 19:57:24.087818 Set Vref, RX VrefLevel [Byte0]: 34
1598 19:57:24.091262 [Byte1]: 34
1599 19:57:24.091817
1600 19:57:24.094562 Set Vref, RX VrefLevel [Byte0]: 35
1601 19:57:24.097401 [Byte1]: 35
1602 19:57:24.101471
1603 19:57:24.101923 Set Vref, RX VrefLevel [Byte0]: 36
1604 19:57:24.104775 [Byte1]: 36
1605 19:57:24.109222
1606 19:57:24.109770 Set Vref, RX VrefLevel [Byte0]: 37
1607 19:57:24.112808 [Byte1]: 37
1608 19:57:24.117158
1609 19:57:24.117706 Set Vref, RX VrefLevel [Byte0]: 38
1610 19:57:24.120167 [Byte1]: 38
1611 19:57:24.124823
1612 19:57:24.125371 Set Vref, RX VrefLevel [Byte0]: 39
1613 19:57:24.127960 [Byte1]: 39
1614 19:57:24.132287
1615 19:57:24.132838 Set Vref, RX VrefLevel [Byte0]: 40
1616 19:57:24.135517 [Byte1]: 40
1617 19:57:24.140057
1618 19:57:24.140787 Set Vref, RX VrefLevel [Byte0]: 41
1619 19:57:24.143198 [Byte1]: 41
1620 19:57:24.147859
1621 19:57:24.148469 Set Vref, RX VrefLevel [Byte0]: 42
1622 19:57:24.151210 [Byte1]: 42
1623 19:57:24.155490
1624 19:57:24.156039 Set Vref, RX VrefLevel [Byte0]: 43
1625 19:57:24.158773 [Byte1]: 43
1626 19:57:24.162859
1627 19:57:24.163416 Set Vref, RX VrefLevel [Byte0]: 44
1628 19:57:24.166277 [Byte1]: 44
1629 19:57:24.170471
1630 19:57:24.171023 Set Vref, RX VrefLevel [Byte0]: 45
1631 19:57:24.173783 [Byte1]: 45
1632 19:57:24.178099
1633 19:57:24.178552 Set Vref, RX VrefLevel [Byte0]: 46
1634 19:57:24.181145 [Byte1]: 46
1635 19:57:24.185570
1636 19:57:24.186024 Set Vref, RX VrefLevel [Byte0]: 47
1637 19:57:24.189108 [Byte1]: 47
1638 19:57:24.193659
1639 19:57:24.194201 Set Vref, RX VrefLevel [Byte0]: 48
1640 19:57:24.196672 [Byte1]: 48
1641 19:57:24.201041
1642 19:57:24.201616 Set Vref, RX VrefLevel [Byte0]: 49
1643 19:57:24.204518 [Byte1]: 49
1644 19:57:24.208958
1645 19:57:24.209512 Set Vref, RX VrefLevel [Byte0]: 50
1646 19:57:24.211735 [Byte1]: 50
1647 19:57:24.216447
1648 19:57:24.217001 Set Vref, RX VrefLevel [Byte0]: 51
1649 19:57:24.219574 [Byte1]: 51
1650 19:57:24.224118
1651 19:57:24.224721 Set Vref, RX VrefLevel [Byte0]: 52
1652 19:57:24.227249 [Byte1]: 52
1653 19:57:24.231709
1654 19:57:24.232309 Set Vref, RX VrefLevel [Byte0]: 53
1655 19:57:24.234808 [Byte1]: 53
1656 19:57:24.239531
1657 19:57:24.240103 Set Vref, RX VrefLevel [Byte0]: 54
1658 19:57:24.242725 [Byte1]: 54
1659 19:57:24.247230
1660 19:57:24.247783 Set Vref, RX VrefLevel [Byte0]: 55
1661 19:57:24.250387 [Byte1]: 55
1662 19:57:24.254622
1663 19:57:24.255176 Set Vref, RX VrefLevel [Byte0]: 56
1664 19:57:24.257686 [Byte1]: 56
1665 19:57:24.262043
1666 19:57:24.262594 Set Vref, RX VrefLevel [Byte0]: 57
1667 19:57:24.265653 [Byte1]: 57
1668 19:57:24.269781
1669 19:57:24.270377 Set Vref, RX VrefLevel [Byte0]: 58
1670 19:57:24.272895 [Byte1]: 58
1671 19:57:24.277912
1672 19:57:24.278468 Set Vref, RX VrefLevel [Byte0]: 59
1673 19:57:24.280673 [Byte1]: 59
1674 19:57:24.285361
1675 19:57:24.285914 Set Vref, RX VrefLevel [Byte0]: 60
1676 19:57:24.288623 [Byte1]: 60
1677 19:57:24.292740
1678 19:57:24.293297 Set Vref, RX VrefLevel [Byte0]: 61
1679 19:57:24.296214 [Byte1]: 61
1680 19:57:24.300543
1681 19:57:24.301094 Set Vref, RX VrefLevel [Byte0]: 62
1682 19:57:24.303660 [Byte1]: 62
1683 19:57:24.308358
1684 19:57:24.308910 Set Vref, RX VrefLevel [Byte0]: 63
1685 19:57:24.314678 [Byte1]: 63
1686 19:57:24.315224
1687 19:57:24.317917 Set Vref, RX VrefLevel [Byte0]: 64
1688 19:57:24.321197 [Byte1]: 64
1689 19:57:24.321743
1690 19:57:24.324569 Set Vref, RX VrefLevel [Byte0]: 65
1691 19:57:24.327913 [Byte1]: 65
1692 19:57:24.328525
1693 19:57:24.331424 Set Vref, RX VrefLevel [Byte0]: 66
1694 19:57:24.334556 [Byte1]: 66
1695 19:57:24.338859
1696 19:57:24.339405 Set Vref, RX VrefLevel [Byte0]: 67
1697 19:57:24.341744 [Byte1]: 67
1698 19:57:24.346286
1699 19:57:24.346834 Set Vref, RX VrefLevel [Byte0]: 68
1700 19:57:24.349635 [Byte1]: 68
1701 19:57:24.353857
1702 19:57:24.354402 Set Vref, RX VrefLevel [Byte0]: 69
1703 19:57:24.357107 [Byte1]: 69
1704 19:57:24.361696
1705 19:57:24.362279 Set Vref, RX VrefLevel [Byte0]: 70
1706 19:57:24.364830 [Byte1]: 70
1707 19:57:24.369489
1708 19:57:24.370057 Set Vref, RX VrefLevel [Byte0]: 71
1709 19:57:24.372485 [Byte1]: 71
1710 19:57:24.377430
1711 19:57:24.377978 Set Vref, RX VrefLevel [Byte0]: 72
1712 19:57:24.380321 [Byte1]: 72
1713 19:57:24.384389
1714 19:57:24.384843 Set Vref, RX VrefLevel [Byte0]: 73
1715 19:57:24.387954 [Byte1]: 73
1716 19:57:24.392455
1717 19:57:24.393074 Set Vref, RX VrefLevel [Byte0]: 74
1718 19:57:24.395844 [Byte1]: 74
1719 19:57:24.400273
1720 19:57:24.400836 Final RX Vref Byte 0 = 59 to rank0
1721 19:57:24.403402 Final RX Vref Byte 1 = 52 to rank0
1722 19:57:24.406771 Final RX Vref Byte 0 = 59 to rank1
1723 19:57:24.409974 Final RX Vref Byte 1 = 52 to rank1==
1724 19:57:24.413430 Dram Type= 6, Freq= 0, CH_1, rank 0
1725 19:57:24.416626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1726 19:57:24.420304 ==
1727 19:57:24.420910 DQS Delay:
1728 19:57:24.421279 DQS0 = 0, DQS1 = 0
1729 19:57:24.423561 DQM Delay:
1730 19:57:24.424115 DQM0 = 81, DQM1 = 75
1731 19:57:24.426861 DQ Delay:
1732 19:57:24.429940 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1733 19:57:24.430394 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1734 19:57:24.433466 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1735 19:57:24.436532 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1736 19:57:24.436989
1737 19:57:24.440355
1738 19:57:24.447304 [DQSOSCAuto] RK0, (LSB)MR18= 0x5555, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1739 19:57:24.450928 CH1 RK0: MR19=606, MR18=5555
1740 19:57:24.454031 CH1_RK0: MR19=0x606, MR18=0x5555, DQSOSC=388, MR23=63, INC=98, DEC=65
1741 19:57:24.454579
1742 19:57:24.457169 ----->DramcWriteLeveling(PI) begin...
1743 19:57:24.460620 ==
1744 19:57:24.464246 Dram Type= 6, Freq= 0, CH_1, rank 1
1745 19:57:24.467494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1746 19:57:24.468041 ==
1747 19:57:24.470605 Write leveling (Byte 0): 25 => 25
1748 19:57:24.473960 Write leveling (Byte 1): 26 => 26
1749 19:57:24.477262 DramcWriteLeveling(PI) end<-----
1750 19:57:24.477715
1751 19:57:24.478069 ==
1752 19:57:24.480757 Dram Type= 6, Freq= 0, CH_1, rank 1
1753 19:57:24.483645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1754 19:57:24.484104 ==
1755 19:57:24.487575 [Gating] SW mode calibration
1756 19:57:24.494060 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1757 19:57:24.497610 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1758 19:57:24.504299 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
1759 19:57:24.507441 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1760 19:57:24.510492 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1761 19:57:24.517805 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1762 19:57:24.520480 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1763 19:57:24.524048 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1764 19:57:24.530443 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1765 19:57:24.533798 0 6 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1766 19:57:24.537436 0 7 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
1767 19:57:24.543893 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1768 19:57:24.547115 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1769 19:57:24.550617 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1770 19:57:24.557318 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1771 19:57:24.560682 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1772 19:57:24.564020 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1773 19:57:24.570982 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1774 19:57:24.574201 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1775 19:57:24.577791 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1776 19:57:24.580748 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1777 19:57:24.587801 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 19:57:24.590977 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1779 19:57:24.594073 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 19:57:24.600807 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 19:57:24.604240 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 19:57:24.607447 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 19:57:24.613774 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 19:57:24.617456 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 19:57:24.620608 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 19:57:24.627229 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 19:57:24.630759 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 19:57:24.634152 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 19:57:24.640586 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1790 19:57:24.643858 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1791 19:57:24.647339 Total UI for P1: 0, mck2ui 16
1792 19:57:24.650510 best dqsien dly found for B0: ( 0, 9, 28)
1793 19:57:24.654156 Total UI for P1: 0, mck2ui 16
1794 19:57:24.657357 best dqsien dly found for B1: ( 0, 9, 28)
1795 19:57:24.660674 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1796 19:57:24.664082 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1797 19:57:24.664682
1798 19:57:24.667390 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1799 19:57:24.670888 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1800 19:57:24.673630 [Gating] SW calibration Done
1801 19:57:24.674095 ==
1802 19:57:24.677195 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 19:57:24.680410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1804 19:57:24.684153 ==
1805 19:57:24.684992 RX Vref Scan: 0
1806 19:57:24.685365
1807 19:57:24.687345 RX Vref 0 -> 0, step: 1
1808 19:57:24.687794
1809 19:57:24.690734 RX Delay -130 -> 252, step: 16
1810 19:57:24.694077 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1811 19:57:24.697697 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1812 19:57:24.700560 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1813 19:57:24.703736 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1814 19:57:24.707130 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1815 19:57:24.713939 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1816 19:57:24.717080 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1817 19:57:24.720880 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1818 19:57:24.724198 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1819 19:57:24.727360 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1820 19:57:24.734042 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1821 19:57:24.737042 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1822 19:57:24.740813 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1823 19:57:24.743823 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1824 19:57:24.750772 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1825 19:57:24.753989 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1826 19:57:24.754546 ==
1827 19:57:24.759351 Dram Type= 6, Freq= 0, CH_1, rank 1
1828 19:57:24.760618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1829 19:57:24.761203 ==
1830 19:57:24.761715 DQS Delay:
1831 19:57:24.763617 DQS0 = 0, DQS1 = 0
1832 19:57:24.764071 DQM Delay:
1833 19:57:24.767234 DQM0 = 85, DQM1 = 73
1834 19:57:24.767686 DQ Delay:
1835 19:57:24.770664 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1836 19:57:24.773880 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1837 19:57:24.777303 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1838 19:57:24.780897 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1839 19:57:24.781352
1840 19:57:24.781709
1841 19:57:24.782043 ==
1842 19:57:24.783779 Dram Type= 6, Freq= 0, CH_1, rank 1
1843 19:57:24.787544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1844 19:57:24.790617 ==
1845 19:57:24.791177
1846 19:57:24.791535
1847 19:57:24.791869 TX Vref Scan disable
1848 19:57:24.794072 == TX Byte 0 ==
1849 19:57:24.797498 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1850 19:57:24.800539 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1851 19:57:24.804432 == TX Byte 1 ==
1852 19:57:24.807367 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1853 19:57:24.811136 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1854 19:57:24.811768 ==
1855 19:57:24.813885 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 19:57:24.821102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1857 19:57:24.821762 ==
1858 19:57:24.832699 TX Vref=22, minBit 0, minWin=27, winSum=447
1859 19:57:24.835810 TX Vref=24, minBit 8, minWin=27, winSum=455
1860 19:57:24.839787 TX Vref=26, minBit 8, minWin=27, winSum=451
1861 19:57:24.842578 TX Vref=28, minBit 8, minWin=27, winSum=458
1862 19:57:24.846269 TX Vref=30, minBit 0, minWin=28, winSum=455
1863 19:57:24.849468 TX Vref=32, minBit 9, minWin=27, winSum=454
1864 19:57:24.856598 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1865 19:57:24.857146
1866 19:57:24.859192 Final TX Range 1 Vref 30
1867 19:57:24.859645
1868 19:57:24.859997 ==
1869 19:57:24.862809 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 19:57:24.866303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1871 19:57:24.866848 ==
1872 19:57:24.867206
1873 19:57:24.869327
1874 19:57:24.869857 TX Vref Scan disable
1875 19:57:24.872491 == TX Byte 0 ==
1876 19:57:24.875678 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1877 19:57:24.882661 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1878 19:57:24.883225 == TX Byte 1 ==
1879 19:57:24.885870 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1880 19:57:24.889164 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1881 19:57:24.892545
1882 19:57:24.892997 [DATLAT]
1883 19:57:24.893354 Freq=800, CH1 RK1
1884 19:57:24.893691
1885 19:57:24.896058 DATLAT Default: 0x9
1886 19:57:24.896658 0, 0xFFFF, sum = 0
1887 19:57:24.899382 1, 0xFFFF, sum = 0
1888 19:57:24.899944 2, 0xFFFF, sum = 0
1889 19:57:24.903025 3, 0xFFFF, sum = 0
1890 19:57:24.903585 4, 0xFFFF, sum = 0
1891 19:57:24.905531 5, 0xFFFF, sum = 0
1892 19:57:24.909109 6, 0xFFFF, sum = 0
1893 19:57:24.909634 7, 0xFFFF, sum = 0
1894 19:57:24.912308 8, 0x0, sum = 1
1895 19:57:24.912772 9, 0x0, sum = 2
1896 19:57:24.913204 10, 0x0, sum = 3
1897 19:57:24.915730 11, 0x0, sum = 4
1898 19:57:24.916335 best_step = 9
1899 19:57:24.916705
1900 19:57:24.917040 ==
1901 19:57:24.919108 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 19:57:24.925782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1903 19:57:24.926338 ==
1904 19:57:24.926701 RX Vref Scan: 0
1905 19:57:24.927034
1906 19:57:24.928882 RX Vref 0 -> 0, step: 1
1907 19:57:24.929337
1908 19:57:24.932439 RX Delay -111 -> 252, step: 8
1909 19:57:24.935838 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1910 19:57:24.939033 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1911 19:57:24.945584 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1912 19:57:24.948937 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1913 19:57:24.952591 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1914 19:57:24.955940 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1915 19:57:24.958979 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1916 19:57:24.965750 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1917 19:57:24.968896 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1918 19:57:24.972164 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1919 19:57:24.975177 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1920 19:57:24.978799 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1921 19:57:24.985081 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1922 19:57:24.988329 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1923 19:57:24.991846 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1924 19:57:24.995368 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1925 19:57:24.995824 ==
1926 19:57:24.998771 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 19:57:25.005470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1928 19:57:25.006032 ==
1929 19:57:25.006395 DQS Delay:
1930 19:57:25.008684 DQS0 = 0, DQS1 = 0
1931 19:57:25.009141 DQM Delay:
1932 19:57:25.009504 DQM0 = 84, DQM1 = 74
1933 19:57:25.012025 DQ Delay:
1934 19:57:25.015497 DQ0 =84, DQ1 =80, DQ2 =76, DQ3 =84
1935 19:57:25.018828 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1936 19:57:25.022247 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1937 19:57:25.025692 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1938 19:57:25.026256
1939 19:57:25.026617
1940 19:57:25.032249 [DQSOSCAuto] RK1, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1941 19:57:25.035822 CH1 RK1: MR19=606, MR18=3737
1942 19:57:25.041725 CH1_RK1: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63
1943 19:57:25.045448 [RxdqsGatingPostProcess] freq 800
1944 19:57:25.048833 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1945 19:57:25.052475 Pre-setting of DQS Precalculation
1946 19:57:25.059005 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1947 19:57:25.065659 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1948 19:57:25.072273 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1949 19:57:25.072836
1950 19:57:25.073198
1951 19:57:25.075256 [Calibration Summary] 1600 Mbps
1952 19:57:25.075711 CH 0, Rank 0
1953 19:57:25.078818 SW Impedance : PASS
1954 19:57:25.082324 DUTY Scan : NO K
1955 19:57:25.082877 ZQ Calibration : PASS
1956 19:57:25.085335 Jitter Meter : NO K
1957 19:57:25.085790 CBT Training : PASS
1958 19:57:25.088675 Write leveling : PASS
1959 19:57:25.092096 RX DQS gating : PASS
1960 19:57:25.092602 RX DQ/DQS(RDDQC) : PASS
1961 19:57:25.095430 TX DQ/DQS : PASS
1962 19:57:25.098842 RX DATLAT : PASS
1963 19:57:25.099443 RX DQ/DQS(Engine): PASS
1964 19:57:25.101915 TX OE : NO K
1965 19:57:25.102469 All Pass.
1966 19:57:25.102825
1967 19:57:25.105545 CH 0, Rank 1
1968 19:57:25.106094 SW Impedance : PASS
1969 19:57:25.108557 DUTY Scan : NO K
1970 19:57:25.111742 ZQ Calibration : PASS
1971 19:57:25.112361 Jitter Meter : NO K
1972 19:57:25.115309 CBT Training : PASS
1973 19:57:25.118854 Write leveling : PASS
1974 19:57:25.119403 RX DQS gating : PASS
1975 19:57:25.121958 RX DQ/DQS(RDDQC) : PASS
1976 19:57:25.122426 TX DQ/DQS : PASS
1977 19:57:25.125541 RX DATLAT : PASS
1978 19:57:25.128949 RX DQ/DQS(Engine): PASS
1979 19:57:25.129400 TX OE : NO K
1980 19:57:25.132144 All Pass.
1981 19:57:25.132763
1982 19:57:25.133127 CH 1, Rank 0
1983 19:57:25.135312 SW Impedance : PASS
1984 19:57:25.135863 DUTY Scan : NO K
1985 19:57:25.138829 ZQ Calibration : PASS
1986 19:57:25.142164 Jitter Meter : NO K
1987 19:57:25.142616 CBT Training : PASS
1988 19:57:25.145643 Write leveling : PASS
1989 19:57:25.148901 RX DQS gating : PASS
1990 19:57:25.149449 RX DQ/DQS(RDDQC) : PASS
1991 19:57:25.152419 TX DQ/DQS : PASS
1992 19:57:25.155720 RX DATLAT : PASS
1993 19:57:25.156314 RX DQ/DQS(Engine): PASS
1994 19:57:25.158802 TX OE : NO K
1995 19:57:25.159358 All Pass.
1996 19:57:25.159718
1997 19:57:25.162110 CH 1, Rank 1
1998 19:57:25.162656 SW Impedance : PASS
1999 19:57:25.165557 DUTY Scan : NO K
2000 19:57:25.168959 ZQ Calibration : PASS
2001 19:57:25.169510 Jitter Meter : NO K
2002 19:57:25.172356 CBT Training : PASS
2003 19:57:25.172897 Write leveling : PASS
2004 19:57:25.175626 RX DQS gating : PASS
2005 19:57:25.178617 RX DQ/DQS(RDDQC) : PASS
2006 19:57:25.179158 TX DQ/DQS : PASS
2007 19:57:25.182072 RX DATLAT : PASS
2008 19:57:25.185325 RX DQ/DQS(Engine): PASS
2009 19:57:25.185780 TX OE : NO K
2010 19:57:25.188733 All Pass.
2011 19:57:25.189278
2012 19:57:25.189637 DramC Write-DBI off
2013 19:57:25.191920 PER_BANK_REFRESH: Hybrid Mode
2014 19:57:25.192427 TX_TRACKING: ON
2015 19:57:25.195388 [GetDramInforAfterCalByMRR] Vendor 6.
2016 19:57:25.202448 [GetDramInforAfterCalByMRR] Revision 606.
2017 19:57:25.205457 [GetDramInforAfterCalByMRR] Revision 2 0.
2018 19:57:25.205998 MR0 0x3939
2019 19:57:25.206356 MR8 0x1111
2020 19:57:25.208527 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2021 19:57:25.208981
2022 19:57:25.211831 MR0 0x3939
2023 19:57:25.212356 MR8 0x1111
2024 19:57:25.215727 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2025 19:57:25.216328
2026 19:57:25.225598 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2027 19:57:25.228903 [FAST_K] Save calibration result to emmc
2028 19:57:25.231967 [FAST_K] Save calibration result to emmc
2029 19:57:25.235560 dram_init: config_dvfs: 1
2030 19:57:25.239146 dramc_set_vcore_voltage set vcore to 662500
2031 19:57:25.242078 Read voltage for 1200, 2
2032 19:57:25.242533 Vio18 = 0
2033 19:57:25.242891 Vcore = 662500
2034 19:57:25.245524 Vdram = 0
2035 19:57:25.246073 Vddq = 0
2036 19:57:25.246429 Vmddr = 0
2037 19:57:25.252256 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2038 19:57:25.255680 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2039 19:57:25.259096 MEM_TYPE=3, freq_sel=15
2040 19:57:25.261796 sv_algorithm_assistance_LP4_1600
2041 19:57:25.265469 ============ PULL DRAM RESETB DOWN ============
2042 19:57:25.268653 ========== PULL DRAM RESETB DOWN end =========
2043 19:57:25.275453 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2044 19:57:25.278499 ===================================
2045 19:57:25.278956 LPDDR4 DRAM CONFIGURATION
2046 19:57:25.282285 ===================================
2047 19:57:25.284942 EX_ROW_EN[0] = 0x0
2048 19:57:25.288429 EX_ROW_EN[1] = 0x0
2049 19:57:25.288883 LP4Y_EN = 0x0
2050 19:57:25.292294 WORK_FSP = 0x0
2051 19:57:25.292844 WL = 0x4
2052 19:57:25.295092 RL = 0x4
2053 19:57:25.295583 BL = 0x2
2054 19:57:25.298796 RPST = 0x0
2055 19:57:25.299351 RD_PRE = 0x0
2056 19:57:25.301757 WR_PRE = 0x1
2057 19:57:25.302212 WR_PST = 0x0
2058 19:57:25.305272 DBI_WR = 0x0
2059 19:57:25.305722 DBI_RD = 0x0
2060 19:57:25.308450 OTF = 0x1
2061 19:57:25.312266 ===================================
2062 19:57:25.315535 ===================================
2063 19:57:25.316095 ANA top config
2064 19:57:25.318844 ===================================
2065 19:57:25.322017 DLL_ASYNC_EN = 0
2066 19:57:25.325452 ALL_SLAVE_EN = 0
2067 19:57:25.326006 NEW_RANK_MODE = 1
2068 19:57:25.329071 DLL_IDLE_MODE = 1
2069 19:57:25.331950 LP45_APHY_COMB_EN = 1
2070 19:57:25.335463 TX_ODT_DIS = 1
2071 19:57:25.338753 NEW_8X_MODE = 1
2072 19:57:25.341931 ===================================
2073 19:57:25.345602 ===================================
2074 19:57:25.346156 data_rate = 2400
2075 19:57:25.348816 CKR = 1
2076 19:57:25.351979 DQ_P2S_RATIO = 8
2077 19:57:25.355779 ===================================
2078 19:57:25.358626 CA_P2S_RATIO = 8
2079 19:57:25.362171 DQ_CA_OPEN = 0
2080 19:57:25.365508 DQ_SEMI_OPEN = 0
2081 19:57:25.366060 CA_SEMI_OPEN = 0
2082 19:57:25.368817 CA_FULL_RATE = 0
2083 19:57:25.372343 DQ_CKDIV4_EN = 0
2084 19:57:25.375570 CA_CKDIV4_EN = 0
2085 19:57:25.378692 CA_PREDIV_EN = 0
2086 19:57:25.381938 PH8_DLY = 17
2087 19:57:25.382392 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2088 19:57:25.385259 DQ_AAMCK_DIV = 4
2089 19:57:25.388780 CA_AAMCK_DIV = 4
2090 19:57:25.391896 CA_ADMCK_DIV = 4
2091 19:57:25.395557 DQ_TRACK_CA_EN = 0
2092 19:57:25.398824 CA_PICK = 1200
2093 19:57:25.399378 CA_MCKIO = 1200
2094 19:57:25.402100 MCKIO_SEMI = 0
2095 19:57:25.405023 PLL_FREQ = 2366
2096 19:57:25.408371 DQ_UI_PI_RATIO = 32
2097 19:57:25.411890 CA_UI_PI_RATIO = 0
2098 19:57:25.415055 ===================================
2099 19:57:25.418584 ===================================
2100 19:57:25.421988 memory_type:LPDDR4
2101 19:57:25.422539 GP_NUM : 10
2102 19:57:25.425264 SRAM_EN : 1
2103 19:57:25.429152 MD32_EN : 0
2104 19:57:25.429705 ===================================
2105 19:57:25.432012 [ANA_INIT] >>>>>>>>>>>>>>
2106 19:57:25.435144 <<<<<< [CONFIGURE PHASE]: ANA_TX
2107 19:57:25.438156 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2108 19:57:25.441981 ===================================
2109 19:57:25.445140 data_rate = 2400,PCW = 0X5b00
2110 19:57:25.448569 ===================================
2111 19:57:25.451821 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2112 19:57:25.458574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2113 19:57:25.461863 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2114 19:57:25.468345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2115 19:57:25.471893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2116 19:57:25.474817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2117 19:57:25.475275 [ANA_INIT] flow start
2118 19:57:25.478258 [ANA_INIT] PLL >>>>>>>>
2119 19:57:25.481824 [ANA_INIT] PLL <<<<<<<<
2120 19:57:25.482277 [ANA_INIT] MIDPI >>>>>>>>
2121 19:57:25.484758 [ANA_INIT] MIDPI <<<<<<<<
2122 19:57:25.488281 [ANA_INIT] DLL >>>>>>>>
2123 19:57:25.488737 [ANA_INIT] DLL <<<<<<<<
2124 19:57:25.491570 [ANA_INIT] flow end
2125 19:57:25.494858 ============ LP4 DIFF to SE enter ============
2126 19:57:25.498333 ============ LP4 DIFF to SE exit ============
2127 19:57:25.501870 [ANA_INIT] <<<<<<<<<<<<<
2128 19:57:25.505009 [Flow] Enable top DCM control >>>>>
2129 19:57:25.508085 [Flow] Enable top DCM control <<<<<
2130 19:57:25.511259 Enable DLL master slave shuffle
2131 19:57:25.518291 ==============================================================
2132 19:57:25.518451 Gating Mode config
2133 19:57:25.524474 ==============================================================
2134 19:57:25.524608 Config description:
2135 19:57:25.534506 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2136 19:57:25.541359 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2137 19:57:25.548336 SELPH_MODE 0: By rank 1: By Phase
2138 19:57:25.551650 ==============================================================
2139 19:57:25.554933 GAT_TRACK_EN = 1
2140 19:57:25.558252 RX_GATING_MODE = 2
2141 19:57:25.561331 RX_GATING_TRACK_MODE = 2
2142 19:57:25.564715 SELPH_MODE = 1
2143 19:57:25.567816 PICG_EARLY_EN = 1
2144 19:57:25.571339 VALID_LAT_VALUE = 1
2145 19:57:25.577926 ==============================================================
2146 19:57:25.581529 Enter into Gating configuration >>>>
2147 19:57:25.584659 Exit from Gating configuration <<<<
2148 19:57:25.584881 Enter into DVFS_PRE_config >>>>>
2149 19:57:25.598481 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2150 19:57:25.601615 Exit from DVFS_PRE_config <<<<<
2151 19:57:25.605072 Enter into PICG configuration >>>>
2152 19:57:25.608444 Exit from PICG configuration <<<<
2153 19:57:25.608993 [RX_INPUT] configuration >>>>>
2154 19:57:25.611623 [RX_INPUT] configuration <<<<<
2155 19:57:25.618485 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2156 19:57:25.621723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2157 19:57:25.628236 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2158 19:57:25.635310 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2159 19:57:25.641791 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2160 19:57:25.648545 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2161 19:57:25.651743 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2162 19:57:25.655423 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2163 19:57:25.661765 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2164 19:57:25.665065 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2165 19:57:25.668242 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2166 19:57:25.671729 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2167 19:57:25.675055 ===================================
2168 19:57:25.678079 LPDDR4 DRAM CONFIGURATION
2169 19:57:25.681500 ===================================
2170 19:57:25.685095 EX_ROW_EN[0] = 0x0
2171 19:57:25.685546 EX_ROW_EN[1] = 0x0
2172 19:57:25.688284 LP4Y_EN = 0x0
2173 19:57:25.688865 WORK_FSP = 0x0
2174 19:57:25.692030 WL = 0x4
2175 19:57:25.692529 RL = 0x4
2176 19:57:25.694937 BL = 0x2
2177 19:57:25.695491 RPST = 0x0
2178 19:57:25.698385 RD_PRE = 0x0
2179 19:57:25.698838 WR_PRE = 0x1
2180 19:57:25.701982 WR_PST = 0x0
2181 19:57:25.702582 DBI_WR = 0x0
2182 19:57:25.705172 DBI_RD = 0x0
2183 19:57:25.705720 OTF = 0x1
2184 19:57:25.708769 ===================================
2185 19:57:25.714828 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2186 19:57:25.718468 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2187 19:57:25.721945 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2188 19:57:25.724877 ===================================
2189 19:57:25.728465 LPDDR4 DRAM CONFIGURATION
2190 19:57:25.731598 ===================================
2191 19:57:25.732051 EX_ROW_EN[0] = 0x10
2192 19:57:25.735213 EX_ROW_EN[1] = 0x0
2193 19:57:25.738322 LP4Y_EN = 0x0
2194 19:57:25.738776 WORK_FSP = 0x0
2195 19:57:25.741577 WL = 0x4
2196 19:57:25.742026 RL = 0x4
2197 19:57:25.745049 BL = 0x2
2198 19:57:25.745501 RPST = 0x0
2199 19:57:25.748046 RD_PRE = 0x0
2200 19:57:25.748528 WR_PRE = 0x1
2201 19:57:25.751451 WR_PST = 0x0
2202 19:57:25.751901 DBI_WR = 0x0
2203 19:57:25.754973 DBI_RD = 0x0
2204 19:57:25.755522 OTF = 0x1
2205 19:57:25.758423 ===================================
2206 19:57:25.764996 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2207 19:57:25.765577 ==
2208 19:57:25.768616 Dram Type= 6, Freq= 0, CH_0, rank 0
2209 19:57:25.771497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2210 19:57:25.774689 ==
2211 19:57:25.775148 [Duty_Offset_Calibration]
2212 19:57:25.777930 B0:0 B1:2 CA:1
2213 19:57:25.778430
2214 19:57:25.781481 [DutyScan_Calibration_Flow] k_type=0
2215 19:57:25.789805
2216 19:57:25.790258 ==CLK 0==
2217 19:57:25.793279 Final CLK duty delay cell = 0
2218 19:57:25.796477 [0] MAX Duty = 5093%(X100), DQS PI = 12
2219 19:57:25.800086 [0] MIN Duty = 4938%(X100), DQS PI = 54
2220 19:57:25.800673 [0] AVG Duty = 5015%(X100)
2221 19:57:25.803006
2222 19:57:25.806414 CH0 CLK Duty spec in!! Max-Min= 155%
2223 19:57:25.809676 [DutyScan_Calibration_Flow] ====Done====
2224 19:57:25.810133
2225 19:57:25.813090 [DutyScan_Calibration_Flow] k_type=1
2226 19:57:25.829030
2227 19:57:25.829582 ==DQS 0 ==
2228 19:57:25.832651 Final DQS duty delay cell = 0
2229 19:57:25.835717 [0] MAX Duty = 5125%(X100), DQS PI = 30
2230 19:57:25.839013 [0] MIN Duty = 5031%(X100), DQS PI = 4
2231 19:57:25.842529 [0] AVG Duty = 5078%(X100)
2232 19:57:25.843080
2233 19:57:25.843439 ==DQS 1 ==
2234 19:57:25.846112 Final DQS duty delay cell = 0
2235 19:57:25.849126 [0] MAX Duty = 5062%(X100), DQS PI = 58
2236 19:57:25.852278 [0] MIN Duty = 4906%(X100), DQS PI = 16
2237 19:57:25.855865 [0] AVG Duty = 4984%(X100)
2238 19:57:25.856468
2239 19:57:25.859260 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2240 19:57:25.859813
2241 19:57:25.862633 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2242 19:57:25.865919 [DutyScan_Calibration_Flow] ====Done====
2243 19:57:25.866474
2244 19:57:25.869323 [DutyScan_Calibration_Flow] k_type=3
2245 19:57:25.885571
2246 19:57:25.886127 ==DQM 0 ==
2247 19:57:25.888686 Final DQM duty delay cell = 0
2248 19:57:25.892261 [0] MAX Duty = 5156%(X100), DQS PI = 20
2249 19:57:25.895789 [0] MIN Duty = 4969%(X100), DQS PI = 54
2250 19:57:25.899117 [0] AVG Duty = 5062%(X100)
2251 19:57:25.899707
2252 19:57:25.900082 ==DQM 1 ==
2253 19:57:25.902568 Final DQM duty delay cell = 0
2254 19:57:25.905528 [0] MAX Duty = 5000%(X100), DQS PI = 56
2255 19:57:25.908890 [0] MIN Duty = 4844%(X100), DQS PI = 0
2256 19:57:25.912323 [0] AVG Duty = 4922%(X100)
2257 19:57:25.912780
2258 19:57:25.915409 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2259 19:57:25.915860
2260 19:57:25.919051 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2261 19:57:25.922127 [DutyScan_Calibration_Flow] ====Done====
2262 19:57:25.922586
2263 19:57:25.925504 [DutyScan_Calibration_Flow] k_type=2
2264 19:57:25.940778
2265 19:57:25.941341 ==DQ 0 ==
2266 19:57:25.943812 Final DQ duty delay cell = -4
2267 19:57:25.947415 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2268 19:57:25.950499 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2269 19:57:25.953924 [-4] AVG Duty = 4937%(X100)
2270 19:57:25.954480
2271 19:57:25.954844 ==DQ 1 ==
2272 19:57:25.957029 Final DQ duty delay cell = -4
2273 19:57:25.960596 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2274 19:57:25.963545 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2275 19:57:25.967223 [-4] AVG Duty = 4969%(X100)
2276 19:57:25.967773
2277 19:57:25.970424 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2278 19:57:25.970975
2279 19:57:25.973578 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2280 19:57:25.977135 [DutyScan_Calibration_Flow] ====Done====
2281 19:57:25.977700 ==
2282 19:57:25.980214 Dram Type= 6, Freq= 0, CH_1, rank 0
2283 19:57:25.983739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2284 19:57:25.984229 ==
2285 19:57:25.987220 [Duty_Offset_Calibration]
2286 19:57:25.987772 B0:0 B1:4 CA:-5
2287 19:57:25.988130
2288 19:57:25.990628 [DutyScan_Calibration_Flow] k_type=0
2289 19:57:26.001385
2290 19:57:26.001944 ==CLK 0==
2291 19:57:26.004554 Final CLK duty delay cell = 0
2292 19:57:26.007751 [0] MAX Duty = 5094%(X100), DQS PI = 24
2293 19:57:26.010951 [0] MIN Duty = 4907%(X100), DQS PI = 44
2294 19:57:26.011404 [0] AVG Duty = 5000%(X100)
2295 19:57:26.014330
2296 19:57:26.017706 CH1 CLK Duty spec in!! Max-Min= 187%
2297 19:57:26.020914 [DutyScan_Calibration_Flow] ====Done====
2298 19:57:26.021366
2299 19:57:26.024620 [DutyScan_Calibration_Flow] k_type=1
2300 19:57:26.039433
2301 19:57:26.039983 ==DQS 0 ==
2302 19:57:26.043014 Final DQS duty delay cell = 0
2303 19:57:26.046121 [0] MAX Duty = 5125%(X100), DQS PI = 16
2304 19:57:26.049566 [0] MIN Duty = 4875%(X100), DQS PI = 40
2305 19:57:26.053143 [0] AVG Duty = 5000%(X100)
2306 19:57:26.053697
2307 19:57:26.054054 ==DQS 1 ==
2308 19:57:26.055921 Final DQS duty delay cell = -4
2309 19:57:26.059167 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2310 19:57:26.062885 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2311 19:57:26.066204 [-4] AVG Duty = 4953%(X100)
2312 19:57:26.066757
2313 19:57:26.069787 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2314 19:57:26.070341
2315 19:57:26.072999 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2316 19:57:26.076349 [DutyScan_Calibration_Flow] ====Done====
2317 19:57:26.076904
2318 19:57:26.079276 [DutyScan_Calibration_Flow] k_type=3
2319 19:57:26.095114
2320 19:57:26.095661 ==DQM 0 ==
2321 19:57:26.097818 Final DQM duty delay cell = -4
2322 19:57:26.101349 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2323 19:57:26.104945 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2324 19:57:26.108242 [-4] AVG Duty = 4969%(X100)
2325 19:57:26.108797
2326 19:57:26.109153 ==DQM 1 ==
2327 19:57:26.111210 Final DQM duty delay cell = -4
2328 19:57:26.114652 [-4] MAX Duty = 5093%(X100), DQS PI = 20
2329 19:57:26.118215 [-4] MIN Duty = 4907%(X100), DQS PI = 58
2330 19:57:26.121269 [-4] AVG Duty = 5000%(X100)
2331 19:57:26.121723
2332 19:57:26.124908 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2333 19:57:26.125465
2334 19:57:26.128237 CH1 DQM 1 Duty spec in!! Max-Min= 186%
2335 19:57:26.131601 [DutyScan_Calibration_Flow] ====Done====
2336 19:57:26.132152
2337 19:57:26.134862 [DutyScan_Calibration_Flow] k_type=2
2338 19:57:26.152202
2339 19:57:26.152762 ==DQ 0 ==
2340 19:57:26.155239 Final DQ duty delay cell = 0
2341 19:57:26.158673 [0] MAX Duty = 5093%(X100), DQS PI = 0
2342 19:57:26.162513 [0] MIN Duty = 4938%(X100), DQS PI = 44
2343 19:57:26.163065 [0] AVG Duty = 5015%(X100)
2344 19:57:26.163429
2345 19:57:26.165214 ==DQ 1 ==
2346 19:57:26.168851 Final DQ duty delay cell = 0
2347 19:57:26.172490 [0] MAX Duty = 5031%(X100), DQS PI = 8
2348 19:57:26.175185 [0] MIN Duty = 4907%(X100), DQS PI = 0
2349 19:57:26.175666 [0] AVG Duty = 4969%(X100)
2350 19:57:26.176022
2351 19:57:26.179092 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2352 19:57:26.179650
2353 19:57:26.182058 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2354 19:57:26.188312 [DutyScan_Calibration_Flow] ====Done====
2355 19:57:26.192053 nWR fixed to 30
2356 19:57:26.192657 [ModeRegInit_LP4] CH0 RK0
2357 19:57:26.195424 [ModeRegInit_LP4] CH0 RK1
2358 19:57:26.198835 [ModeRegInit_LP4] CH1 RK0
2359 19:57:26.199386 [ModeRegInit_LP4] CH1 RK1
2360 19:57:26.201836 match AC timing 6
2361 19:57:26.205065 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2362 19:57:26.208484 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2363 19:57:26.215169 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2364 19:57:26.218729 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2365 19:57:26.225556 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2366 19:57:26.226101 ==
2367 19:57:26.228940 Dram Type= 6, Freq= 0, CH_0, rank 0
2368 19:57:26.232123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2369 19:57:26.232703 ==
2370 19:57:26.238853 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2371 19:57:26.242051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2372 19:57:26.251617 [CA 0] Center 39 (9~70) winsize 62
2373 19:57:26.255041 [CA 1] Center 39 (9~70) winsize 62
2374 19:57:26.257865 [CA 2] Center 36 (5~67) winsize 63
2375 19:57:26.261880 [CA 3] Center 35 (5~66) winsize 62
2376 19:57:26.264858 [CA 4] Center 34 (3~65) winsize 63
2377 19:57:26.268354 [CA 5] Center 33 (3~64) winsize 62
2378 19:57:26.268896
2379 19:57:26.271811 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2380 19:57:26.272401
2381 19:57:26.274720 [CATrainingPosCal] consider 1 rank data
2382 19:57:26.278284 u2DelayCellTimex100 = 270/100 ps
2383 19:57:26.281547 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2384 19:57:26.284762 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2385 19:57:26.291587 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2386 19:57:26.294819 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2387 19:57:26.298174 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2388 19:57:26.301479 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2389 19:57:26.301927
2390 19:57:26.305019 CA PerBit enable=1, Macro0, CA PI delay=33
2391 19:57:26.305566
2392 19:57:26.308432 [CBTSetCACLKResult] CA Dly = 33
2393 19:57:26.308975 CS Dly: 7 (0~38)
2394 19:57:26.311650 ==
2395 19:57:26.312229 Dram Type= 6, Freq= 0, CH_0, rank 1
2396 19:57:26.318278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2397 19:57:26.318849 ==
2398 19:57:26.321769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2399 19:57:26.328003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2400 19:57:26.337061 [CA 0] Center 39 (8~70) winsize 63
2401 19:57:26.340628 [CA 1] Center 39 (8~70) winsize 63
2402 19:57:26.343992 [CA 2] Center 35 (5~66) winsize 62
2403 19:57:26.347063 [CA 3] Center 35 (4~66) winsize 63
2404 19:57:26.350381 [CA 4] Center 33 (3~64) winsize 62
2405 19:57:26.353526 [CA 5] Center 34 (3~65) winsize 63
2406 19:57:26.353976
2407 19:57:26.357391 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2408 19:57:26.357962
2409 19:57:26.360459 [CATrainingPosCal] consider 2 rank data
2410 19:57:26.363752 u2DelayCellTimex100 = 270/100 ps
2411 19:57:26.367525 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2412 19:57:26.370398 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2413 19:57:26.377138 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2414 19:57:26.380389 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2415 19:57:26.383974 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2416 19:57:26.387241 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2417 19:57:26.387854
2418 19:57:26.390420 CA PerBit enable=1, Macro0, CA PI delay=33
2419 19:57:26.390966
2420 19:57:26.393722 [CBTSetCACLKResult] CA Dly = 33
2421 19:57:26.394170 CS Dly: 7 (0~39)
2422 19:57:26.394524
2423 19:57:26.396928 ----->DramcWriteLeveling(PI) begin...
2424 19:57:26.400208 ==
2425 19:57:26.400666 Dram Type= 6, Freq= 0, CH_0, rank 0
2426 19:57:26.407046 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2427 19:57:26.407602 ==
2428 19:57:26.410552 Write leveling (Byte 0): 28 => 28
2429 19:57:26.413437 Write leveling (Byte 1): 25 => 25
2430 19:57:26.416880 DramcWriteLeveling(PI) end<-----
2431 19:57:26.417502
2432 19:57:26.417873 ==
2433 19:57:26.420796 Dram Type= 6, Freq= 0, CH_0, rank 0
2434 19:57:26.424081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2435 19:57:26.424673 ==
2436 19:57:26.427283 [Gating] SW mode calibration
2437 19:57:26.434069 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2438 19:57:26.437078 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2439 19:57:26.443977 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2440 19:57:26.447281 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2441 19:57:26.450690 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2442 19:57:26.457733 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2443 19:57:26.460567 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2444 19:57:26.464020 0 11 20 | B1->B0 | 3131 2b2b | 0 1 | (0 1) (1 0)
2445 19:57:26.470381 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2446 19:57:26.473713 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2447 19:57:26.477191 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2448 19:57:26.483698 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2449 19:57:26.487255 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2450 19:57:26.490571 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2451 19:57:26.497217 0 12 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2452 19:57:26.500526 0 12 20 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
2453 19:57:26.504024 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2454 19:57:26.507182 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2455 19:57:26.514191 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2456 19:57:26.517175 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2457 19:57:26.520720 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2458 19:57:26.527263 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2459 19:57:26.530555 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2460 19:57:26.534035 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2461 19:57:26.540398 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2462 19:57:26.543979 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2463 19:57:26.547357 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2464 19:57:26.553968 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 19:57:26.557445 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 19:57:26.560712 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 19:57:26.567683 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 19:57:26.570737 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 19:57:26.574147 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 19:57:26.580761 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 19:57:26.583931 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 19:57:26.587383 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 19:57:26.590817 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 19:57:26.597276 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 19:57:26.600551 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2476 19:57:26.604275 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2477 19:57:26.607608 Total UI for P1: 0, mck2ui 16
2478 19:57:26.611232 best dqsien dly found for B0: ( 0, 15, 16)
2479 19:57:26.614000 Total UI for P1: 0, mck2ui 16
2480 19:57:26.617110 best dqsien dly found for B1: ( 0, 15, 18)
2481 19:57:26.620559 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2482 19:57:26.627392 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2483 19:57:26.627936
2484 19:57:26.630401 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2485 19:57:26.633857 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2486 19:57:26.636942 [Gating] SW calibration Done
2487 19:57:26.637398 ==
2488 19:57:26.640227 Dram Type= 6, Freq= 0, CH_0, rank 0
2489 19:57:26.643759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2490 19:57:26.644436 ==
2491 19:57:26.646779 RX Vref Scan: 0
2492 19:57:26.647228
2493 19:57:26.647583 RX Vref 0 -> 0, step: 1
2494 19:57:26.647920
2495 19:57:26.650204 RX Delay -40 -> 252, step: 8
2496 19:57:26.653453 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2497 19:57:26.656901 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2498 19:57:26.664140 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2499 19:57:26.667106 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2500 19:57:26.670194 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2501 19:57:26.673615 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2502 19:57:26.676772 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2503 19:57:26.683646 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2504 19:57:26.686962 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2505 19:57:26.690489 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2506 19:57:26.693434 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2507 19:57:26.696944 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2508 19:57:26.703851 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2509 19:57:26.707677 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2510 19:57:26.710508 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2511 19:57:26.713944 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2512 19:57:26.714493 ==
2513 19:57:26.717036 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 19:57:26.723762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2515 19:57:26.724390 ==
2516 19:57:26.724762 DQS Delay:
2517 19:57:26.725095 DQS0 = 0, DQS1 = 0
2518 19:57:26.727449 DQM Delay:
2519 19:57:26.727993 DQM0 = 115, DQM1 = 106
2520 19:57:26.730400 DQ Delay:
2521 19:57:26.733630 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2522 19:57:26.737154 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2523 19:57:26.740282 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2524 19:57:26.743731 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2525 19:57:26.744321
2526 19:57:26.744687
2527 19:57:26.745018 ==
2528 19:57:26.746820 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 19:57:26.750466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2530 19:57:26.751015 ==
2531 19:57:26.753779
2532 19:57:26.754325
2533 19:57:26.754686 TX Vref Scan disable
2534 19:57:26.756885 == TX Byte 0 ==
2535 19:57:26.760254 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2536 19:57:26.763588 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2537 19:57:26.766856 == TX Byte 1 ==
2538 19:57:26.770149 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2539 19:57:26.773531 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2540 19:57:26.774084 ==
2541 19:57:26.776651 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 19:57:26.783187 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2543 19:57:26.783791 ==
2544 19:57:26.794161 TX Vref=22, minBit 8, minWin=25, winSum=416
2545 19:57:26.797299 TX Vref=24, minBit 10, minWin=25, winSum=426
2546 19:57:26.800453 TX Vref=26, minBit 14, minWin=25, winSum=432
2547 19:57:26.804060 TX Vref=28, minBit 9, minWin=25, winSum=429
2548 19:57:26.807396 TX Vref=30, minBit 8, minWin=26, winSum=433
2549 19:57:26.813688 TX Vref=32, minBit 8, minWin=26, winSum=435
2550 19:57:26.817420 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 32
2551 19:57:26.817993
2552 19:57:26.820664 Final TX Range 1 Vref 32
2553 19:57:26.821116
2554 19:57:26.821475 ==
2555 19:57:26.823673 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 19:57:26.827013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2557 19:57:26.830608 ==
2558 19:57:26.831381
2559 19:57:26.831763
2560 19:57:26.832099 TX Vref Scan disable
2561 19:57:26.834078 == TX Byte 0 ==
2562 19:57:26.837087 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2563 19:57:26.844135 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2564 19:57:26.844720 == TX Byte 1 ==
2565 19:57:26.847152 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2566 19:57:26.853846 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2567 19:57:26.854302
2568 19:57:26.854658 [DATLAT]
2569 19:57:26.854991 Freq=1200, CH0 RK0
2570 19:57:26.855310
2571 19:57:26.857356 DATLAT Default: 0xd
2572 19:57:26.857904 0, 0xFFFF, sum = 0
2573 19:57:26.860786 1, 0xFFFF, sum = 0
2574 19:57:26.861345 2, 0xFFFF, sum = 0
2575 19:57:26.864162 3, 0xFFFF, sum = 0
2576 19:57:26.867116 4, 0xFFFF, sum = 0
2577 19:57:26.867577 5, 0xFFFF, sum = 0
2578 19:57:26.870625 6, 0xFFFF, sum = 0
2579 19:57:26.871182 7, 0xFFFF, sum = 0
2580 19:57:26.874246 8, 0xFFFF, sum = 0
2581 19:57:26.874809 9, 0xFFFF, sum = 0
2582 19:57:26.877360 10, 0xFFFF, sum = 0
2583 19:57:26.877923 11, 0x0, sum = 1
2584 19:57:26.880564 12, 0x0, sum = 2
2585 19:57:26.881123 13, 0x0, sum = 3
2586 19:57:26.883720 14, 0x0, sum = 4
2587 19:57:26.884378 best_step = 12
2588 19:57:26.884751
2589 19:57:26.885081 ==
2590 19:57:26.887128 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 19:57:26.890362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2592 19:57:26.890818 ==
2593 19:57:26.893842 RX Vref Scan: 1
2594 19:57:26.894292
2595 19:57:26.897086 Set Vref Range= 32 -> 127
2596 19:57:26.897538
2597 19:57:26.897995 RX Vref 32 -> 127, step: 1
2598 19:57:26.898505
2599 19:57:26.900523 RX Delay -21 -> 252, step: 4
2600 19:57:26.900994
2601 19:57:26.903899 Set Vref, RX VrefLevel [Byte0]: 32
2602 19:57:26.907231 [Byte1]: 32
2603 19:57:26.910548
2604 19:57:26.910999 Set Vref, RX VrefLevel [Byte0]: 33
2605 19:57:26.914025 [Byte1]: 33
2606 19:57:26.918822
2607 19:57:26.919367 Set Vref, RX VrefLevel [Byte0]: 34
2608 19:57:26.922285 [Byte1]: 34
2609 19:57:26.926715
2610 19:57:26.927260 Set Vref, RX VrefLevel [Byte0]: 35
2611 19:57:26.930299 [Byte1]: 35
2612 19:57:26.934530
2613 19:57:26.934978 Set Vref, RX VrefLevel [Byte0]: 36
2614 19:57:26.938264 [Byte1]: 36
2615 19:57:26.942664
2616 19:57:26.943212 Set Vref, RX VrefLevel [Byte0]: 37
2617 19:57:26.945929 [Byte1]: 37
2618 19:57:26.950633
2619 19:57:26.951180 Set Vref, RX VrefLevel [Byte0]: 38
2620 19:57:26.953796 [Byte1]: 38
2621 19:57:26.959096
2622 19:57:26.959646 Set Vref, RX VrefLevel [Byte0]: 39
2623 19:57:26.961868 [Byte1]: 39
2624 19:57:26.966437
2625 19:57:26.966993 Set Vref, RX VrefLevel [Byte0]: 40
2626 19:57:26.969769 [Byte1]: 40
2627 19:57:26.974358
2628 19:57:26.974912 Set Vref, RX VrefLevel [Byte0]: 41
2629 19:57:26.977520 [Byte1]: 41
2630 19:57:26.982276
2631 19:57:26.982820 Set Vref, RX VrefLevel [Byte0]: 42
2632 19:57:26.985265 [Byte1]: 42
2633 19:57:26.989823
2634 19:57:26.990273 Set Vref, RX VrefLevel [Byte0]: 43
2635 19:57:26.993115 [Byte1]: 43
2636 19:57:26.997757
2637 19:57:26.998206 Set Vref, RX VrefLevel [Byte0]: 44
2638 19:57:27.001024 [Byte1]: 44
2639 19:57:27.005881
2640 19:57:27.006434 Set Vref, RX VrefLevel [Byte0]: 45
2641 19:57:27.009727 [Byte1]: 45
2642 19:57:27.013592
2643 19:57:27.014044 Set Vref, RX VrefLevel [Byte0]: 46
2644 19:57:27.016851 [Byte1]: 46
2645 19:57:27.021884
2646 19:57:27.022494 Set Vref, RX VrefLevel [Byte0]: 47
2647 19:57:27.025104 [Byte1]: 47
2648 19:57:27.029805
2649 19:57:27.030414 Set Vref, RX VrefLevel [Byte0]: 48
2650 19:57:27.032929 [Byte1]: 48
2651 19:57:27.037682
2652 19:57:27.038246 Set Vref, RX VrefLevel [Byte0]: 49
2653 19:57:27.040943 [Byte1]: 49
2654 19:57:27.045632
2655 19:57:27.046193 Set Vref, RX VrefLevel [Byte0]: 50
2656 19:57:27.048814 [Byte1]: 50
2657 19:57:27.053510
2658 19:57:27.054080 Set Vref, RX VrefLevel [Byte0]: 51
2659 19:57:27.056814 [Byte1]: 51
2660 19:57:27.061220
2661 19:57:27.061780 Set Vref, RX VrefLevel [Byte0]: 52
2662 19:57:27.064917 [Byte1]: 52
2663 19:57:27.069193
2664 19:57:27.069749 Set Vref, RX VrefLevel [Byte0]: 53
2665 19:57:27.072778 [Byte1]: 53
2666 19:57:27.077267
2667 19:57:27.077822 Set Vref, RX VrefLevel [Byte0]: 54
2668 19:57:27.080842 [Byte1]: 54
2669 19:57:27.084934
2670 19:57:27.085396 Set Vref, RX VrefLevel [Byte0]: 55
2671 19:57:27.088256 [Byte1]: 55
2672 19:57:27.092900
2673 19:57:27.093358 Set Vref, RX VrefLevel [Byte0]: 56
2674 19:57:27.096220 [Byte1]: 56
2675 19:57:27.100833
2676 19:57:27.101439 Set Vref, RX VrefLevel [Byte0]: 57
2677 19:57:27.104047 [Byte1]: 57
2678 19:57:27.109139
2679 19:57:27.109697 Set Vref, RX VrefLevel [Byte0]: 58
2680 19:57:27.112078 [Byte1]: 58
2681 19:57:27.116695
2682 19:57:27.117154 Set Vref, RX VrefLevel [Byte0]: 59
2683 19:57:27.120216 [Byte1]: 59
2684 19:57:27.124669
2685 19:57:27.125229 Set Vref, RX VrefLevel [Byte0]: 60
2686 19:57:27.128060 [Byte1]: 60
2687 19:57:27.132899
2688 19:57:27.133460 Set Vref, RX VrefLevel [Byte0]: 61
2689 19:57:27.136340 [Byte1]: 61
2690 19:57:27.140590
2691 19:57:27.141174 Set Vref, RX VrefLevel [Byte0]: 62
2692 19:57:27.143832 [Byte1]: 62
2693 19:57:27.148500
2694 19:57:27.149056 Set Vref, RX VrefLevel [Byte0]: 63
2695 19:57:27.151728 [Byte1]: 63
2696 19:57:27.156557
2697 19:57:27.157119 Set Vref, RX VrefLevel [Byte0]: 64
2698 19:57:27.159507 [Byte1]: 64
2699 19:57:27.164349
2700 19:57:27.164911 Set Vref, RX VrefLevel [Byte0]: 65
2701 19:57:27.167724 [Byte1]: 65
2702 19:57:27.172264
2703 19:57:27.172820 Set Vref, RX VrefLevel [Byte0]: 66
2704 19:57:27.175551 [Byte1]: 66
2705 19:57:27.180315
2706 19:57:27.180870 Set Vref, RX VrefLevel [Byte0]: 67
2707 19:57:27.183812 [Byte1]: 67
2708 19:57:27.188140
2709 19:57:27.188653 Final RX Vref Byte 0 = 51 to rank0
2710 19:57:27.191052 Final RX Vref Byte 1 = 51 to rank0
2711 19:57:27.194773 Final RX Vref Byte 0 = 51 to rank1
2712 19:57:27.198171 Final RX Vref Byte 1 = 51 to rank1==
2713 19:57:27.201319 Dram Type= 6, Freq= 0, CH_0, rank 0
2714 19:57:27.208093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2715 19:57:27.208723 ==
2716 19:57:27.209095 DQS Delay:
2717 19:57:27.209434 DQS0 = 0, DQS1 = 0
2718 19:57:27.211094 DQM Delay:
2719 19:57:27.211549 DQM0 = 114, DQM1 = 105
2720 19:57:27.214575 DQ Delay:
2721 19:57:27.218290 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =110
2722 19:57:27.221344 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2723 19:57:27.224652 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =98
2724 19:57:27.228227 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2725 19:57:27.228688
2726 19:57:27.229050
2727 19:57:27.234471 [DQSOSCAuto] RK0, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2728 19:57:27.238365 CH0 RK0: MR19=404, MR18=C0C
2729 19:57:27.244589 CH0_RK0: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
2730 19:57:27.245138
2731 19:57:27.247880 ----->DramcWriteLeveling(PI) begin...
2732 19:57:27.248384 ==
2733 19:57:27.251837 Dram Type= 6, Freq= 0, CH_0, rank 1
2734 19:57:27.254778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2735 19:57:27.255341 ==
2736 19:57:27.258309 Write leveling (Byte 0): 28 => 28
2737 19:57:27.261375 Write leveling (Byte 1): 25 => 25
2738 19:57:27.264694 DramcWriteLeveling(PI) end<-----
2739 19:57:27.265253
2740 19:57:27.265620 ==
2741 19:57:27.268042 Dram Type= 6, Freq= 0, CH_0, rank 1
2742 19:57:27.271669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2743 19:57:27.274484 ==
2744 19:57:27.274949 [Gating] SW mode calibration
2745 19:57:27.284797 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2746 19:57:27.287727 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2747 19:57:27.291410 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2748 19:57:27.298060 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2749 19:57:27.301218 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2750 19:57:27.304918 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2751 19:57:27.311583 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2752 19:57:27.314721 0 11 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2753 19:57:27.317896 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2754 19:57:27.324630 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2755 19:57:27.327662 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2756 19:57:27.331024 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2757 19:57:27.337724 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2758 19:57:27.341225 0 12 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2759 19:57:27.344662 0 12 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2760 19:57:27.351171 0 12 20 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2761 19:57:27.354585 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2762 19:57:27.357801 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2763 19:57:27.364450 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2764 19:57:27.367697 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2765 19:57:27.371336 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2766 19:57:27.374469 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2767 19:57:27.380891 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 19:57:27.384123 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2769 19:57:27.387643 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2770 19:57:27.394400 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2771 19:57:27.397984 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 19:57:27.401055 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 19:57:27.407745 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 19:57:27.411047 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 19:57:27.414171 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 19:57:27.421089 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 19:57:27.424345 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 19:57:27.427444 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 19:57:27.434006 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 19:57:27.437387 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 19:57:27.440890 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 19:57:27.447543 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 19:57:27.450774 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 19:57:27.454413 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2785 19:57:27.460857 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2786 19:57:27.461474 Total UI for P1: 0, mck2ui 16
2787 19:57:27.467446 best dqsien dly found for B0: ( 0, 15, 20)
2788 19:57:27.468018 Total UI for P1: 0, mck2ui 16
2789 19:57:27.473943 best dqsien dly found for B1: ( 0, 15, 20)
2790 19:57:27.477444 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2791 19:57:27.480911 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2792 19:57:27.481474
2793 19:57:27.483923 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2794 19:57:27.487347 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2795 19:57:27.490659 [Gating] SW calibration Done
2796 19:57:27.491126 ==
2797 19:57:27.493975 Dram Type= 6, Freq= 0, CH_0, rank 1
2798 19:57:27.497719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2799 19:57:27.498303 ==
2800 19:57:27.500598 RX Vref Scan: 0
2801 19:57:27.501127
2802 19:57:27.501499 RX Vref 0 -> 0, step: 1
2803 19:57:27.501839
2804 19:57:27.504039 RX Delay -40 -> 252, step: 8
2805 19:57:27.507560 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2806 19:57:27.513722 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2807 19:57:27.517493 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2808 19:57:27.520888 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2809 19:57:27.524112 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2810 19:57:27.527300 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2811 19:57:27.533955 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2812 19:57:27.537616 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2813 19:57:27.540777 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2814 19:57:27.543711 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2815 19:57:27.547341 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2816 19:57:27.550764 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2817 19:57:27.557349 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2818 19:57:27.560794 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2819 19:57:27.564146 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2820 19:57:27.567574 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2821 19:57:27.568236 ==
2822 19:57:27.570788 Dram Type= 6, Freq= 0, CH_0, rank 1
2823 19:57:27.577283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2824 19:57:27.577843 ==
2825 19:57:27.578212 DQS Delay:
2826 19:57:27.580854 DQS0 = 0, DQS1 = 0
2827 19:57:27.581413 DQM Delay:
2828 19:57:27.581780 DQM0 = 115, DQM1 = 107
2829 19:57:27.583863 DQ Delay:
2830 19:57:27.587269 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =107
2831 19:57:27.591176 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2832 19:57:27.593940 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2833 19:57:27.597455 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =115
2834 19:57:27.598015
2835 19:57:27.598379
2836 19:57:27.598717 ==
2837 19:57:27.600745 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 19:57:27.604128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2839 19:57:27.604750 ==
2840 19:57:27.605119
2841 19:57:27.607370
2842 19:57:27.607831 TX Vref Scan disable
2843 19:57:27.611001 == TX Byte 0 ==
2844 19:57:27.613987 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2845 19:57:27.617125 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2846 19:57:27.621134 == TX Byte 1 ==
2847 19:57:27.624348 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2848 19:57:27.627827 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2849 19:57:27.628421 ==
2850 19:57:27.631070 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 19:57:27.637454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2852 19:57:27.638012 ==
2853 19:57:27.648126 TX Vref=22, minBit 9, minWin=25, winSum=423
2854 19:57:27.651423 TX Vref=24, minBit 10, minWin=25, winSum=427
2855 19:57:27.654725 TX Vref=26, minBit 11, minWin=25, winSum=429
2856 19:57:27.658075 TX Vref=28, minBit 9, minWin=26, winSum=430
2857 19:57:27.661276 TX Vref=30, minBit 10, minWin=25, winSum=432
2858 19:57:27.668338 TX Vref=32, minBit 9, minWin=26, winSum=437
2859 19:57:27.671549 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 32
2860 19:57:27.672100
2861 19:57:27.674754 Final TX Range 1 Vref 32
2862 19:57:27.675306
2863 19:57:27.675664 ==
2864 19:57:27.678245 Dram Type= 6, Freq= 0, CH_0, rank 1
2865 19:57:27.681470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2866 19:57:27.684873 ==
2867 19:57:27.685436
2868 19:57:27.685805
2869 19:57:27.686143 TX Vref Scan disable
2870 19:57:27.687942 == TX Byte 0 ==
2871 19:57:27.691249 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2872 19:57:27.698143 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2873 19:57:27.698696 == TX Byte 1 ==
2874 19:57:27.701377 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2875 19:57:27.708131 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2876 19:57:27.708887
2877 19:57:27.709257 [DATLAT]
2878 19:57:27.709590 Freq=1200, CH0 RK1
2879 19:57:27.709911
2880 19:57:27.711240 DATLAT Default: 0xc
2881 19:57:27.711691 0, 0xFFFF, sum = 0
2882 19:57:27.714589 1, 0xFFFF, sum = 0
2883 19:57:27.715191 2, 0xFFFF, sum = 0
2884 19:57:27.717700 3, 0xFFFF, sum = 0
2885 19:57:27.721616 4, 0xFFFF, sum = 0
2886 19:57:27.722190 5, 0xFFFF, sum = 0
2887 19:57:27.724487 6, 0xFFFF, sum = 0
2888 19:57:27.724946 7, 0xFFFF, sum = 0
2889 19:57:27.727761 8, 0xFFFF, sum = 0
2890 19:57:27.728263 9, 0xFFFF, sum = 0
2891 19:57:27.731479 10, 0xFFFF, sum = 0
2892 19:57:27.732041 11, 0x0, sum = 1
2893 19:57:27.734937 12, 0x0, sum = 2
2894 19:57:27.735498 13, 0x0, sum = 3
2895 19:57:27.738189 14, 0x0, sum = 4
2896 19:57:27.738753 best_step = 12
2897 19:57:27.739114
2898 19:57:27.739444 ==
2899 19:57:27.741235 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 19:57:27.744824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2901 19:57:27.745386 ==
2902 19:57:27.748387 RX Vref Scan: 0
2903 19:57:27.749014
2904 19:57:27.749384 RX Vref 0 -> 0, step: 1
2905 19:57:27.751461
2906 19:57:27.752013 RX Delay -21 -> 252, step: 4
2907 19:57:27.758444 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2908 19:57:27.761871 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2909 19:57:27.765073 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2910 19:57:27.768278 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2911 19:57:27.772029 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2912 19:57:27.778831 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2913 19:57:27.782283 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2914 19:57:27.785203 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2915 19:57:27.788733 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2916 19:57:27.791786 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2917 19:57:27.798748 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
2918 19:57:27.801738 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2919 19:57:27.805152 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2920 19:57:27.808724 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
2921 19:57:27.811866 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2922 19:57:27.818618 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
2923 19:57:27.819178 ==
2924 19:57:27.821844 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 19:57:27.825496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2926 19:57:27.826051 ==
2927 19:57:27.826411 DQS Delay:
2928 19:57:27.828642 DQS0 = 0, DQS1 = 0
2929 19:57:27.829092 DQM Delay:
2930 19:57:27.831981 DQM0 = 114, DQM1 = 106
2931 19:57:27.832611 DQ Delay:
2932 19:57:27.835228 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2933 19:57:27.838730 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2934 19:57:27.841727 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =96
2935 19:57:27.845110 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
2936 19:57:27.845667
2937 19:57:27.846028
2938 19:57:27.855355 [DQSOSCAuto] RK1, (LSB)MR18= 0x1111, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2939 19:57:27.858431 CH0 RK1: MR19=404, MR18=1111
2940 19:57:27.862066 CH0_RK1: MR19=0x404, MR18=0x1111, DQSOSC=403, MR23=63, INC=40, DEC=26
2941 19:57:27.865331 [RxdqsGatingPostProcess] freq 1200
2942 19:57:27.871870 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2943 19:57:27.875195 Pre-setting of DQS Precalculation
2944 19:57:27.878582 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2945 19:57:27.879135 ==
2946 19:57:27.881509 Dram Type= 6, Freq= 0, CH_1, rank 0
2947 19:57:27.888513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2948 19:57:27.889295 ==
2949 19:57:27.891736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2950 19:57:27.898856 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2951 19:57:27.907152 [CA 0] Center 37 (7~68) winsize 62
2952 19:57:27.910959 [CA 1] Center 37 (7~68) winsize 62
2953 19:57:27.913712 [CA 2] Center 34 (4~65) winsize 62
2954 19:57:27.917397 [CA 3] Center 33 (3~64) winsize 62
2955 19:57:27.920599 [CA 4] Center 32 (1~63) winsize 63
2956 19:57:27.924027 [CA 5] Center 32 (1~63) winsize 63
2957 19:57:27.924767
2958 19:57:27.927430 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2959 19:57:27.928012
2960 19:57:27.930642 [CATrainingPosCal] consider 1 rank data
2961 19:57:27.934043 u2DelayCellTimex100 = 270/100 ps
2962 19:57:27.937503 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2963 19:57:27.940314 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2964 19:57:27.946878 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2965 19:57:27.950398 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2966 19:57:27.953737 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2967 19:57:27.956541 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2968 19:57:27.956623
2969 19:57:27.959941 CA PerBit enable=1, Macro0, CA PI delay=32
2970 19:57:27.960040
2971 19:57:27.963205 [CBTSetCACLKResult] CA Dly = 32
2972 19:57:27.963291 CS Dly: 5 (0~36)
2973 19:57:27.963354 ==
2974 19:57:27.966596 Dram Type= 6, Freq= 0, CH_1, rank 1
2975 19:57:27.973470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2976 19:57:27.973650 ==
2977 19:57:27.976830 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2978 19:57:27.983347 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2979 19:57:27.992131 [CA 0] Center 37 (6~68) winsize 63
2980 19:57:27.995499 [CA 1] Center 37 (7~68) winsize 62
2981 19:57:27.999049 [CA 2] Center 34 (3~65) winsize 63
2982 19:57:28.001995 [CA 3] Center 33 (3~64) winsize 62
2983 19:57:28.006055 [CA 4] Center 32 (2~63) winsize 62
2984 19:57:28.008867 [CA 5] Center 32 (1~63) winsize 63
2985 19:57:28.009117
2986 19:57:28.012037 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2987 19:57:28.012417
2988 19:57:28.015593 [CATrainingPosCal] consider 2 rank data
2989 19:57:28.018988 u2DelayCellTimex100 = 270/100 ps
2990 19:57:28.022483 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2991 19:57:28.025484 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2992 19:57:28.032577 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2993 19:57:28.035797 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2994 19:57:28.039044 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2995 19:57:28.042561 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2996 19:57:28.043130
2997 19:57:28.045811 CA PerBit enable=1, Macro0, CA PI delay=32
2998 19:57:28.046436
2999 19:57:28.049155 [CBTSetCACLKResult] CA Dly = 32
3000 19:57:28.049748 CS Dly: 6 (0~38)
3001 19:57:28.050117
3002 19:57:28.052781 ----->DramcWriteLeveling(PI) begin...
3003 19:57:28.055984 ==
3004 19:57:28.059036 Dram Type= 6, Freq= 0, CH_1, rank 0
3005 19:57:28.062446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3006 19:57:28.063013 ==
3007 19:57:28.065874 Write leveling (Byte 0): 22 => 22
3008 19:57:28.068945 Write leveling (Byte 1): 22 => 22
3009 19:57:28.072437 DramcWriteLeveling(PI) end<-----
3010 19:57:28.072994
3011 19:57:28.073357 ==
3012 19:57:28.075695 Dram Type= 6, Freq= 0, CH_1, rank 0
3013 19:57:28.079189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3014 19:57:28.079750 ==
3015 19:57:28.081933 [Gating] SW mode calibration
3016 19:57:28.088735 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3017 19:57:28.095540 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3018 19:57:28.098598 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3019 19:57:28.101972 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3020 19:57:28.105871 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3021 19:57:28.112387 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3022 19:57:28.115539 0 11 16 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (0 1)
3023 19:57:28.119069 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3024 19:57:28.125314 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3025 19:57:28.129121 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3026 19:57:28.132549 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3027 19:57:28.138755 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3028 19:57:28.142330 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3029 19:57:28.145128 0 12 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3030 19:57:28.152471 0 12 16 | B1->B0 | 3535 4545 | 1 0 | (0 0) (0 0)
3031 19:57:28.155141 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3032 19:57:28.158605 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3033 19:57:28.165317 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3034 19:57:28.168727 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 19:57:28.172036 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 19:57:28.178949 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 19:57:28.181990 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3038 19:57:28.185151 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3039 19:57:28.191678 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3040 19:57:28.195360 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3041 19:57:28.198516 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3042 19:57:28.205302 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 19:57:28.208810 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 19:57:28.212248 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 19:57:28.218404 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 19:57:28.221926 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 19:57:28.225038 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 19:57:28.228668 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 19:57:28.235177 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 19:57:28.238799 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 19:57:28.241889 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 19:57:28.248501 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 19:57:28.252104 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 19:57:28.255240 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3055 19:57:28.261671 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3056 19:57:28.265105 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3057 19:57:28.268338 Total UI for P1: 0, mck2ui 16
3058 19:57:28.271810 best dqsien dly found for B0: ( 0, 15, 18)
3059 19:57:28.275301 Total UI for P1: 0, mck2ui 16
3060 19:57:28.278519 best dqsien dly found for B1: ( 0, 15, 18)
3061 19:57:28.281829 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
3062 19:57:28.285125 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3063 19:57:28.285681
3064 19:57:28.288557 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
3065 19:57:28.291628 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3066 19:57:28.294881 [Gating] SW calibration Done
3067 19:57:28.295337 ==
3068 19:57:28.298682 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 19:57:28.304842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3070 19:57:28.305323 ==
3071 19:57:28.305690 RX Vref Scan: 0
3072 19:57:28.306024
3073 19:57:28.308490 RX Vref 0 -> 0, step: 1
3074 19:57:28.309046
3075 19:57:28.311561 RX Delay -40 -> 252, step: 8
3076 19:57:28.314816 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3077 19:57:28.318358 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3078 19:57:28.321692 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3079 19:57:28.325091 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3080 19:57:28.332011 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3081 19:57:28.335178 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3082 19:57:28.338302 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3083 19:57:28.342107 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3084 19:57:28.344915 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3085 19:57:28.351786 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3086 19:57:28.354989 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3087 19:57:28.358121 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3088 19:57:28.361648 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3089 19:57:28.364898 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3090 19:57:28.372243 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3091 19:57:28.374713 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3092 19:57:28.375170 ==
3093 19:57:28.378317 Dram Type= 6, Freq= 0, CH_1, rank 0
3094 19:57:28.381651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3095 19:57:28.382214 ==
3096 19:57:28.384946 DQS Delay:
3097 19:57:28.385500 DQS0 = 0, DQS1 = 0
3098 19:57:28.385862 DQM Delay:
3099 19:57:28.388304 DQM0 = 115, DQM1 = 107
3100 19:57:28.388864 DQ Delay:
3101 19:57:28.391523 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3102 19:57:28.395182 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3103 19:57:28.397970 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3104 19:57:28.401718 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3105 19:57:28.402277
3106 19:57:28.404950
3107 19:57:28.405404 ==
3108 19:57:28.408214 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 19:57:28.411797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3110 19:57:28.412405 ==
3111 19:57:28.412778
3112 19:57:28.413117
3113 19:57:28.414800 TX Vref Scan disable
3114 19:57:28.415255 == TX Byte 0 ==
3115 19:57:28.421558 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3116 19:57:28.425176 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3117 19:57:28.425778 == TX Byte 1 ==
3118 19:57:28.431749 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3119 19:57:28.434907 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3120 19:57:28.435461 ==
3121 19:57:28.438523 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 19:57:28.441454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3123 19:57:28.442017 ==
3124 19:57:28.453666 TX Vref=22, minBit 3, minWin=25, winSum=420
3125 19:57:28.456755 TX Vref=24, minBit 0, minWin=26, winSum=427
3126 19:57:28.460358 TX Vref=26, minBit 1, minWin=26, winSum=430
3127 19:57:28.463498 TX Vref=28, minBit 15, minWin=25, winSum=431
3128 19:57:28.466774 TX Vref=30, minBit 8, minWin=26, winSum=431
3129 19:57:28.473437 TX Vref=32, minBit 9, minWin=25, winSum=430
3130 19:57:28.476467 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 30
3131 19:57:28.476976
3132 19:57:28.480347 Final TX Range 1 Vref 30
3133 19:57:28.480906
3134 19:57:28.481268 ==
3135 19:57:28.483514 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 19:57:28.486679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3137 19:57:28.487237 ==
3138 19:57:28.490779
3139 19:57:28.491334
3140 19:57:28.491696 TX Vref Scan disable
3141 19:57:28.493195 == TX Byte 0 ==
3142 19:57:28.496612 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3143 19:57:28.499760 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3144 19:57:28.503398 == TX Byte 1 ==
3145 19:57:28.507074 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3146 19:57:28.510126 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3147 19:57:28.510686
3148 19:57:28.513230 [DATLAT]
3149 19:57:28.513684 Freq=1200, CH1 RK0
3150 19:57:28.514047
3151 19:57:28.516610 DATLAT Default: 0xd
3152 19:57:28.517065 0, 0xFFFF, sum = 0
3153 19:57:28.520212 1, 0xFFFF, sum = 0
3154 19:57:28.520789 2, 0xFFFF, sum = 0
3155 19:57:28.523901 3, 0xFFFF, sum = 0
3156 19:57:28.524507 4, 0xFFFF, sum = 0
3157 19:57:28.526783 5, 0xFFFF, sum = 0
3158 19:57:28.527348 6, 0xFFFF, sum = 0
3159 19:57:28.529883 7, 0xFFFF, sum = 0
3160 19:57:28.530344 8, 0xFFFF, sum = 0
3161 19:57:28.533679 9, 0xFFFF, sum = 0
3162 19:57:28.536974 10, 0xFFFF, sum = 0
3163 19:57:28.537541 11, 0x0, sum = 1
3164 19:57:28.537910 12, 0x0, sum = 2
3165 19:57:28.540340 13, 0x0, sum = 3
3166 19:57:28.540903 14, 0x0, sum = 4
3167 19:57:28.543392 best_step = 12
3168 19:57:28.543845
3169 19:57:28.544344 ==
3170 19:57:28.547061 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 19:57:28.550295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3172 19:57:28.550756 ==
3173 19:57:28.553707 RX Vref Scan: 1
3174 19:57:28.554265
3175 19:57:28.554625 Set Vref Range= 32 -> 127
3176 19:57:28.554959
3177 19:57:28.556714 RX Vref 32 -> 127, step: 1
3178 19:57:28.557167
3179 19:57:28.560437 RX Delay -21 -> 252, step: 4
3180 19:57:28.560993
3181 19:57:28.563701 Set Vref, RX VrefLevel [Byte0]: 32
3182 19:57:28.567384 [Byte1]: 32
3183 19:57:28.567841
3184 19:57:28.569871 Set Vref, RX VrefLevel [Byte0]: 33
3185 19:57:28.573437 [Byte1]: 33
3186 19:57:28.577637
3187 19:57:28.578094 Set Vref, RX VrefLevel [Byte0]: 34
3188 19:57:28.580894 [Byte1]: 34
3189 19:57:28.585897
3190 19:57:28.586468 Set Vref, RX VrefLevel [Byte0]: 35
3191 19:57:28.589181 [Byte1]: 35
3192 19:57:28.593600
3193 19:57:28.594056 Set Vref, RX VrefLevel [Byte0]: 36
3194 19:57:28.597186 [Byte1]: 36
3195 19:57:28.601786
3196 19:57:28.602343 Set Vref, RX VrefLevel [Byte0]: 37
3197 19:57:28.605006 [Byte1]: 37
3198 19:57:28.609610
3199 19:57:28.610172 Set Vref, RX VrefLevel [Byte0]: 38
3200 19:57:28.612869 [Byte1]: 38
3201 19:57:28.617640
3202 19:57:28.618197 Set Vref, RX VrefLevel [Byte0]: 39
3203 19:57:28.620523 [Byte1]: 39
3204 19:57:28.625700
3205 19:57:28.626257 Set Vref, RX VrefLevel [Byte0]: 40
3206 19:57:28.628650 [Byte1]: 40
3207 19:57:28.633551
3208 19:57:28.634109 Set Vref, RX VrefLevel [Byte0]: 41
3209 19:57:28.636621 [Byte1]: 41
3210 19:57:28.641150
3211 19:57:28.641708 Set Vref, RX VrefLevel [Byte0]: 42
3212 19:57:28.644428 [Byte1]: 42
3213 19:57:28.649348
3214 19:57:28.649900 Set Vref, RX VrefLevel [Byte0]: 43
3215 19:57:28.652607 [Byte1]: 43
3216 19:57:28.657180
3217 19:57:28.657925 Set Vref, RX VrefLevel [Byte0]: 44
3218 19:57:28.660292 [Byte1]: 44
3219 19:57:28.665166
3220 19:57:28.665721 Set Vref, RX VrefLevel [Byte0]: 45
3221 19:57:28.668403 [Byte1]: 45
3222 19:57:28.672914
3223 19:57:28.676208 Set Vref, RX VrefLevel [Byte0]: 46
3224 19:57:28.676825 [Byte1]: 46
3225 19:57:28.680897
3226 19:57:28.681452 Set Vref, RX VrefLevel [Byte0]: 47
3227 19:57:28.684261 [Byte1]: 47
3228 19:57:28.688857
3229 19:57:28.689418 Set Vref, RX VrefLevel [Byte0]: 48
3230 19:57:28.691900 [Byte1]: 48
3231 19:57:28.696727
3232 19:57:28.697180 Set Vref, RX VrefLevel [Byte0]: 49
3233 19:57:28.699778 [Byte1]: 49
3234 19:57:28.704304
3235 19:57:28.704762 Set Vref, RX VrefLevel [Byte0]: 50
3236 19:57:28.707651 [Byte1]: 50
3237 19:57:28.712667
3238 19:57:28.713223 Set Vref, RX VrefLevel [Byte0]: 51
3239 19:57:28.715636 [Byte1]: 51
3240 19:57:28.720371
3241 19:57:28.720927 Set Vref, RX VrefLevel [Byte0]: 52
3242 19:57:28.723317 [Byte1]: 52
3243 19:57:28.728396
3244 19:57:28.728945 Set Vref, RX VrefLevel [Byte0]: 53
3245 19:57:28.731657 [Byte1]: 53
3246 19:57:28.736338
3247 19:57:28.736892 Set Vref, RX VrefLevel [Byte0]: 54
3248 19:57:28.739505 [Byte1]: 54
3249 19:57:28.744338
3250 19:57:28.744902 Set Vref, RX VrefLevel [Byte0]: 55
3251 19:57:28.747405 [Byte1]: 55
3252 19:57:28.752258
3253 19:57:28.752820 Set Vref, RX VrefLevel [Byte0]: 56
3254 19:57:28.755373 [Byte1]: 56
3255 19:57:28.760144
3256 19:57:28.760745 Set Vref, RX VrefLevel [Byte0]: 57
3257 19:57:28.763416 [Byte1]: 57
3258 19:57:28.767928
3259 19:57:28.768548 Set Vref, RX VrefLevel [Byte0]: 58
3260 19:57:28.771187 [Byte1]: 58
3261 19:57:28.775942
3262 19:57:28.776542 Set Vref, RX VrefLevel [Byte0]: 59
3263 19:57:28.779224 [Byte1]: 59
3264 19:57:28.783755
3265 19:57:28.784359 Set Vref, RX VrefLevel [Byte0]: 60
3266 19:57:28.787107 [Byte1]: 60
3267 19:57:28.791527
3268 19:57:28.792081 Set Vref, RX VrefLevel [Byte0]: 61
3269 19:57:28.794720 [Byte1]: 61
3270 19:57:28.799305
3271 19:57:28.799761 Set Vref, RX VrefLevel [Byte0]: 62
3272 19:57:28.802971 [Byte1]: 62
3273 19:57:28.807377
3274 19:57:28.807926 Set Vref, RX VrefLevel [Byte0]: 63
3275 19:57:28.811005 [Byte1]: 63
3276 19:57:28.815392
3277 19:57:28.815941 Set Vref, RX VrefLevel [Byte0]: 64
3278 19:57:28.818996 [Byte1]: 64
3279 19:57:28.823141
3280 19:57:28.823692 Set Vref, RX VrefLevel [Byte0]: 65
3281 19:57:28.826561 [Byte1]: 65
3282 19:57:28.831251
3283 19:57:28.831801 Final RX Vref Byte 0 = 53 to rank0
3284 19:57:28.834567 Final RX Vref Byte 1 = 50 to rank0
3285 19:57:28.837472 Final RX Vref Byte 0 = 53 to rank1
3286 19:57:28.840733 Final RX Vref Byte 1 = 50 to rank1==
3287 19:57:28.844481 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 19:57:28.850726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3289 19:57:28.851289 ==
3290 19:57:28.851651 DQS Delay:
3291 19:57:28.854440 DQS0 = 0, DQS1 = 0
3292 19:57:28.854992 DQM Delay:
3293 19:57:28.855354 DQM0 = 115, DQM1 = 105
3294 19:57:28.857688 DQ Delay:
3295 19:57:28.861174 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3296 19:57:28.864615 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3297 19:57:28.867601 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3298 19:57:28.870819 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =116
3299 19:57:28.871290
3300 19:57:28.871647
3301 19:57:28.880859 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3302 19:57:28.881417 CH1 RK0: MR19=404, MR18=1515
3303 19:57:28.887571 CH1_RK0: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27
3304 19:57:28.888146
3305 19:57:28.890576 ----->DramcWriteLeveling(PI) begin...
3306 19:57:28.891039 ==
3307 19:57:28.894160 Dram Type= 6, Freq= 0, CH_1, rank 1
3308 19:57:28.897662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3309 19:57:28.900871 ==
3310 19:57:28.901331 Write leveling (Byte 0): 20 => 20
3311 19:57:28.903969 Write leveling (Byte 1): 20 => 20
3312 19:57:28.907786 DramcWriteLeveling(PI) end<-----
3313 19:57:28.908398
3314 19:57:28.908769 ==
3315 19:57:28.910999 Dram Type= 6, Freq= 0, CH_1, rank 1
3316 19:57:28.917392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3317 19:57:28.917855 ==
3318 19:57:28.918218 [Gating] SW mode calibration
3319 19:57:28.927728 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3320 19:57:28.930807 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3321 19:57:28.934441 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3322 19:57:28.940902 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3323 19:57:28.944389 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3324 19:57:28.947485 0 11 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
3325 19:57:28.954196 0 11 16 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
3326 19:57:28.957775 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3327 19:57:28.961096 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3328 19:57:28.967827 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3329 19:57:28.970809 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3330 19:57:28.974433 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3331 19:57:28.980998 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3332 19:57:28.984037 0 12 12 | B1->B0 | 2323 3b3b | 1 0 | (0 0) (0 0)
3333 19:57:28.987640 0 12 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
3334 19:57:28.994002 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3335 19:57:28.997249 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3336 19:57:29.000610 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3337 19:57:29.007660 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3338 19:57:29.010609 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3339 19:57:29.014156 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3340 19:57:29.020775 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3341 19:57:29.024159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3342 19:57:29.027390 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3343 19:57:29.030846 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3344 19:57:29.037461 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3345 19:57:29.040927 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3346 19:57:29.044147 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3347 19:57:29.051416 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 19:57:29.054151 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 19:57:29.057606 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 19:57:29.064699 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 19:57:29.067337 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 19:57:29.070700 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 19:57:29.077842 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 19:57:29.081045 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 19:57:29.083938 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 19:57:29.090916 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3357 19:57:29.094093 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3358 19:57:29.097376 Total UI for P1: 0, mck2ui 16
3359 19:57:29.100621 best dqsien dly found for B0: ( 0, 15, 12)
3360 19:57:29.103994 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3361 19:57:29.107325 Total UI for P1: 0, mck2ui 16
3362 19:57:29.110786 best dqsien dly found for B1: ( 0, 15, 16)
3363 19:57:29.114106 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3364 19:57:29.117294 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3365 19:57:29.117747
3366 19:57:29.124435 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3367 19:57:29.127462 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3368 19:57:29.128022 [Gating] SW calibration Done
3369 19:57:29.130813 ==
3370 19:57:29.131307 Dram Type= 6, Freq= 0, CH_1, rank 1
3371 19:57:29.137953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3372 19:57:29.138514 ==
3373 19:57:29.138874 RX Vref Scan: 0
3374 19:57:29.139206
3375 19:57:29.140792 RX Vref 0 -> 0, step: 1
3376 19:57:29.141243
3377 19:57:29.144250 RX Delay -40 -> 252, step: 8
3378 19:57:29.147484 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3379 19:57:29.151070 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3380 19:57:29.154507 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3381 19:57:29.160812 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3382 19:57:29.164167 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3383 19:57:29.167523 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3384 19:57:29.171086 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3385 19:57:29.173779 iDelay=200, Bit 7, Center 111 (32 ~ 191) 160
3386 19:57:29.180652 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3387 19:57:29.184603 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3388 19:57:29.187289 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3389 19:57:29.190484 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3390 19:57:29.193844 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3391 19:57:29.200868 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3392 19:57:29.204106 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3393 19:57:29.207162 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3394 19:57:29.207620 ==
3395 19:57:29.210672 Dram Type= 6, Freq= 0, CH_1, rank 1
3396 19:57:29.214528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3397 19:57:29.215098 ==
3398 19:57:29.217205 DQS Delay:
3399 19:57:29.217677 DQS0 = 0, DQS1 = 0
3400 19:57:29.220950 DQM Delay:
3401 19:57:29.221507 DQM0 = 115, DQM1 = 105
3402 19:57:29.221869 DQ Delay:
3403 19:57:29.224104 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3404 19:57:29.230918 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =111
3405 19:57:29.234081 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3406 19:57:29.237235 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3407 19:57:29.237815
3408 19:57:29.238184
3409 19:57:29.238510 ==
3410 19:57:29.240681 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 19:57:29.244249 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3412 19:57:29.244927 ==
3413 19:57:29.245294
3414 19:57:29.245689
3415 19:57:29.247138 TX Vref Scan disable
3416 19:57:29.247625 == TX Byte 0 ==
3417 19:57:29.253938 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3418 19:57:29.257445 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3419 19:57:29.257995 == TX Byte 1 ==
3420 19:57:29.263969 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3421 19:57:29.267316 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3422 19:57:29.267769 ==
3423 19:57:29.270503 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 19:57:29.273862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3425 19:57:29.274415 ==
3426 19:57:29.286775 TX Vref=22, minBit 9, minWin=25, winSum=424
3427 19:57:29.290182 TX Vref=24, minBit 0, minWin=26, winSum=426
3428 19:57:29.293482 TX Vref=26, minBit 4, minWin=26, winSum=430
3429 19:57:29.296552 TX Vref=28, minBit 9, minWin=26, winSum=434
3430 19:57:29.299836 TX Vref=30, minBit 9, minWin=26, winSum=436
3431 19:57:29.306309 TX Vref=32, minBit 9, minWin=26, winSum=432
3432 19:57:29.309776 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3433 19:57:29.310337
3434 19:57:29.313107 Final TX Range 1 Vref 30
3435 19:57:29.313662
3436 19:57:29.314020 ==
3437 19:57:29.316611 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 19:57:29.319579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3439 19:57:29.320037 ==
3440 19:57:29.322962
3441 19:57:29.323504
3442 19:57:29.323864 TX Vref Scan disable
3443 19:57:29.326491 == TX Byte 0 ==
3444 19:57:29.329792 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3445 19:57:29.332862 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3446 19:57:29.336746 == TX Byte 1 ==
3447 19:57:29.339754 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3448 19:57:29.343005 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3449 19:57:29.346461
3450 19:57:29.346913 [DATLAT]
3451 19:57:29.347270 Freq=1200, CH1 RK1
3452 19:57:29.347606
3453 19:57:29.349864 DATLAT Default: 0xc
3454 19:57:29.350316 0, 0xFFFF, sum = 0
3455 19:57:29.353126 1, 0xFFFF, sum = 0
3456 19:57:29.353585 2, 0xFFFF, sum = 0
3457 19:57:29.356571 3, 0xFFFF, sum = 0
3458 19:57:29.357145 4, 0xFFFF, sum = 0
3459 19:57:29.359567 5, 0xFFFF, sum = 0
3460 19:57:29.362942 6, 0xFFFF, sum = 0
3461 19:57:29.363402 7, 0xFFFF, sum = 0
3462 19:57:29.366723 8, 0xFFFF, sum = 0
3463 19:57:29.367284 9, 0xFFFF, sum = 0
3464 19:57:29.369778 10, 0xFFFF, sum = 0
3465 19:57:29.370352 11, 0x0, sum = 1
3466 19:57:29.373193 12, 0x0, sum = 2
3467 19:57:29.373750 13, 0x0, sum = 3
3468 19:57:29.374113 14, 0x0, sum = 4
3469 19:57:29.376344 best_step = 12
3470 19:57:29.376912
3471 19:57:29.377275 ==
3472 19:57:29.379598 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 19:57:29.382865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3474 19:57:29.383324 ==
3475 19:57:29.386368 RX Vref Scan: 0
3476 19:57:29.386939
3477 19:57:29.389642 RX Vref 0 -> 0, step: 1
3478 19:57:29.390199
3479 19:57:29.390557 RX Delay -29 -> 252, step: 4
3480 19:57:29.396982 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3481 19:57:29.400124 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3482 19:57:29.403405 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3483 19:57:29.406861 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3484 19:57:29.410221 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3485 19:57:29.416728 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3486 19:57:29.419920 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3487 19:57:29.423253 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3488 19:57:29.426832 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3489 19:57:29.429987 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3490 19:57:29.436888 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3491 19:57:29.440167 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3492 19:57:29.443626 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3493 19:57:29.446654 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3494 19:57:29.450262 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144
3495 19:57:29.456724 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3496 19:57:29.457179 ==
3497 19:57:29.460148 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 19:57:29.463650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3499 19:57:29.464246 ==
3500 19:57:29.464615 DQS Delay:
3501 19:57:29.466693 DQS0 = 0, DQS1 = 0
3502 19:57:29.467246 DQM Delay:
3503 19:57:29.470400 DQM0 = 114, DQM1 = 103
3504 19:57:29.470953 DQ Delay:
3505 19:57:29.473465 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3506 19:57:29.476739 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3507 19:57:29.480273 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3508 19:57:29.483434 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3509 19:57:29.483884
3510 19:57:29.484285
3511 19:57:29.493367 [DQSOSCAuto] RK1, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3512 19:57:29.497024 CH1 RK1: MR19=404, MR18=606
3513 19:57:29.500013 CH1_RK1: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
3514 19:57:29.503576 [RxdqsGatingPostProcess] freq 1200
3515 19:57:29.510044 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3516 19:57:29.513528 Pre-setting of DQS Precalculation
3517 19:57:29.516798 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3518 19:57:29.527202 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3519 19:57:29.533666 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3520 19:57:29.534212
3521 19:57:29.534573
3522 19:57:29.536754 [Calibration Summary] 2400 Mbps
3523 19:57:29.537217 CH 0, Rank 0
3524 19:57:29.540208 SW Impedance : PASS
3525 19:57:29.540678 DUTY Scan : NO K
3526 19:57:29.543378 ZQ Calibration : PASS
3527 19:57:29.546695 Jitter Meter : NO K
3528 19:57:29.547153 CBT Training : PASS
3529 19:57:29.550076 Write leveling : PASS
3530 19:57:29.550531 RX DQS gating : PASS
3531 19:57:29.553570 RX DQ/DQS(RDDQC) : PASS
3532 19:57:29.557012 TX DQ/DQS : PASS
3533 19:57:29.557572 RX DATLAT : PASS
3534 19:57:29.560303 RX DQ/DQS(Engine): PASS
3535 19:57:29.563953 TX OE : NO K
3536 19:57:29.564553 All Pass.
3537 19:57:29.564921
3538 19:57:29.565259 CH 0, Rank 1
3539 19:57:29.566731 SW Impedance : PASS
3540 19:57:29.570408 DUTY Scan : NO K
3541 19:57:29.570967 ZQ Calibration : PASS
3542 19:57:29.573539 Jitter Meter : NO K
3543 19:57:29.576839 CBT Training : PASS
3544 19:57:29.577296 Write leveling : PASS
3545 19:57:29.580252 RX DQS gating : PASS
3546 19:57:29.584059 RX DQ/DQS(RDDQC) : PASS
3547 19:57:29.584668 TX DQ/DQS : PASS
3548 19:57:29.587309 RX DATLAT : PASS
3549 19:57:29.587894 RX DQ/DQS(Engine): PASS
3550 19:57:29.590324 TX OE : NO K
3551 19:57:29.590883 All Pass.
3552 19:57:29.591247
3553 19:57:29.593549 CH 1, Rank 0
3554 19:57:29.594004 SW Impedance : PASS
3555 19:57:29.596939 DUTY Scan : NO K
3556 19:57:29.600213 ZQ Calibration : PASS
3557 19:57:29.600684 Jitter Meter : NO K
3558 19:57:29.603602 CBT Training : PASS
3559 19:57:29.607238 Write leveling : PASS
3560 19:57:29.607799 RX DQS gating : PASS
3561 19:57:29.610337 RX DQ/DQS(RDDQC) : PASS
3562 19:57:29.613794 TX DQ/DQS : PASS
3563 19:57:29.614353 RX DATLAT : PASS
3564 19:57:29.616980 RX DQ/DQS(Engine): PASS
3565 19:57:29.620169 TX OE : NO K
3566 19:57:29.620659 All Pass.
3567 19:57:29.621092
3568 19:57:29.621568 CH 1, Rank 1
3569 19:57:29.623513 SW Impedance : PASS
3570 19:57:29.627355 DUTY Scan : NO K
3571 19:57:29.627913 ZQ Calibration : PASS
3572 19:57:29.630620 Jitter Meter : NO K
3573 19:57:29.633693 CBT Training : PASS
3574 19:57:29.634251 Write leveling : PASS
3575 19:57:29.637010 RX DQS gating : PASS
3576 19:57:29.637568 RX DQ/DQS(RDDQC) : PASS
3577 19:57:29.640461 TX DQ/DQS : PASS
3578 19:57:29.643599 RX DATLAT : PASS
3579 19:57:29.644155 RX DQ/DQS(Engine): PASS
3580 19:57:29.647493 TX OE : NO K
3581 19:57:29.648048 All Pass.
3582 19:57:29.648600
3583 19:57:29.650420 DramC Write-DBI off
3584 19:57:29.653322 PER_BANK_REFRESH: Hybrid Mode
3585 19:57:29.653829 TX_TRACKING: ON
3586 19:57:29.663766 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3587 19:57:29.667126 [FAST_K] Save calibration result to emmc
3588 19:57:29.670425 dramc_set_vcore_voltage set vcore to 650000
3589 19:57:29.673975 Read voltage for 600, 5
3590 19:57:29.674528 Vio18 = 0
3591 19:57:29.674889 Vcore = 650000
3592 19:57:29.676807 Vdram = 0
3593 19:57:29.677327 Vddq = 0
3594 19:57:29.677841 Vmddr = 0
3595 19:57:29.683697 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3596 19:57:29.687325 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3597 19:57:29.690661 MEM_TYPE=3, freq_sel=19
3598 19:57:29.693964 sv_algorithm_assistance_LP4_1600
3599 19:57:29.697257 ============ PULL DRAM RESETB DOWN ============
3600 19:57:29.700303 ========== PULL DRAM RESETB DOWN end =========
3601 19:57:29.707012 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3602 19:57:29.710724 ===================================
3603 19:57:29.713842 LPDDR4 DRAM CONFIGURATION
3604 19:57:29.717179 ===================================
3605 19:57:29.717736 EX_ROW_EN[0] = 0x0
3606 19:57:29.720288 EX_ROW_EN[1] = 0x0
3607 19:57:29.720843 LP4Y_EN = 0x0
3608 19:57:29.724065 WORK_FSP = 0x0
3609 19:57:29.724688 WL = 0x2
3610 19:57:29.726925 RL = 0x2
3611 19:57:29.727489 BL = 0x2
3612 19:57:29.730483 RPST = 0x0
3613 19:57:29.731037 RD_PRE = 0x0
3614 19:57:29.733658 WR_PRE = 0x1
3615 19:57:29.734216 WR_PST = 0x0
3616 19:57:29.737064 DBI_WR = 0x0
3617 19:57:29.737624 DBI_RD = 0x0
3618 19:57:29.740384 OTF = 0x1
3619 19:57:29.743642 ===================================
3620 19:57:29.747457 ===================================
3621 19:57:29.748013 ANA top config
3622 19:57:29.750604 ===================================
3623 19:57:29.753666 DLL_ASYNC_EN = 0
3624 19:57:29.757164 ALL_SLAVE_EN = 1
3625 19:57:29.762524 NEW_RANK_MODE = 1
3626 19:57:29.763167 DLL_IDLE_MODE = 1
3627 19:57:29.763940 LP45_APHY_COMB_EN = 1
3628 19:57:29.766981 TX_ODT_DIS = 1
3629 19:57:29.770106 NEW_8X_MODE = 1
3630 19:57:29.773252 ===================================
3631 19:57:29.776840 ===================================
3632 19:57:29.780313 data_rate = 1200
3633 19:57:29.780776 CKR = 1
3634 19:57:29.783338 DQ_P2S_RATIO = 8
3635 19:57:29.786513 ===================================
3636 19:57:29.789759 CA_P2S_RATIO = 8
3637 19:57:29.793317 DQ_CA_OPEN = 0
3638 19:57:29.796501 DQ_SEMI_OPEN = 0
3639 19:57:29.799791 CA_SEMI_OPEN = 0
3640 19:57:29.800296 CA_FULL_RATE = 0
3641 19:57:29.803490 DQ_CKDIV4_EN = 1
3642 19:57:29.806347 CA_CKDIV4_EN = 1
3643 19:57:29.809815 CA_PREDIV_EN = 0
3644 19:57:29.813112 PH8_DLY = 0
3645 19:57:29.816573 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3646 19:57:29.817128 DQ_AAMCK_DIV = 4
3647 19:57:29.819608 CA_AAMCK_DIV = 4
3648 19:57:29.823293 CA_ADMCK_DIV = 4
3649 19:57:29.826542 DQ_TRACK_CA_EN = 0
3650 19:57:29.829955 CA_PICK = 600
3651 19:57:29.833003 CA_MCKIO = 600
3652 19:57:29.836820 MCKIO_SEMI = 0
3653 19:57:29.837383 PLL_FREQ = 2288
3654 19:57:29.839746 DQ_UI_PI_RATIO = 32
3655 19:57:29.843393 CA_UI_PI_RATIO = 0
3656 19:57:29.846879 ===================================
3657 19:57:29.849486 ===================================
3658 19:57:29.853513 memory_type:LPDDR4
3659 19:57:29.854226 GP_NUM : 10
3660 19:57:29.856681 SRAM_EN : 1
3661 19:57:29.859927 MD32_EN : 0
3662 19:57:29.863172 ===================================
3663 19:57:29.863638 [ANA_INIT] >>>>>>>>>>>>>>
3664 19:57:29.866361 <<<<<< [CONFIGURE PHASE]: ANA_TX
3665 19:57:29.869823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3666 19:57:29.873293 ===================================
3667 19:57:29.876473 data_rate = 1200,PCW = 0X5800
3668 19:57:29.879943 ===================================
3669 19:57:29.883267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3670 19:57:29.889490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3671 19:57:29.893008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3672 19:57:29.899703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3673 19:57:29.902893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3674 19:57:29.906038 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3675 19:57:29.906555 [ANA_INIT] flow start
3676 19:57:29.909183 [ANA_INIT] PLL >>>>>>>>
3677 19:57:29.912626 [ANA_INIT] PLL <<<<<<<<
3678 19:57:29.916166 [ANA_INIT] MIDPI >>>>>>>>
3679 19:57:29.916788 [ANA_INIT] MIDPI <<<<<<<<
3680 19:57:29.919316 [ANA_INIT] DLL >>>>>>>>
3681 19:57:29.922517 [ANA_INIT] flow end
3682 19:57:29.925997 ============ LP4 DIFF to SE enter ============
3683 19:57:29.928966 ============ LP4 DIFF to SE exit ============
3684 19:57:29.932654 [ANA_INIT] <<<<<<<<<<<<<
3685 19:57:29.935681 [Flow] Enable top DCM control >>>>>
3686 19:57:29.939091 [Flow] Enable top DCM control <<<<<
3687 19:57:29.942622 Enable DLL master slave shuffle
3688 19:57:29.945958 ==============================================================
3689 19:57:29.949112 Gating Mode config
3690 19:57:29.952486 ==============================================================
3691 19:57:29.956341 Config description:
3692 19:57:29.965865 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3693 19:57:29.972503 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3694 19:57:29.975521 SELPH_MODE 0: By rank 1: By Phase
3695 19:57:29.982385 ==============================================================
3696 19:57:29.985652 GAT_TRACK_EN = 1
3697 19:57:29.989148 RX_GATING_MODE = 2
3698 19:57:29.992239 RX_GATING_TRACK_MODE = 2
3699 19:57:29.995269 SELPH_MODE = 1
3700 19:57:29.999211 PICG_EARLY_EN = 1
3701 19:57:30.001961 VALID_LAT_VALUE = 1
3702 19:57:30.005273 ==============================================================
3703 19:57:30.008481 Enter into Gating configuration >>>>
3704 19:57:30.012201 Exit from Gating configuration <<<<
3705 19:57:30.015376 Enter into DVFS_PRE_config >>>>>
3706 19:57:30.028659 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3707 19:57:30.029235 Exit from DVFS_PRE_config <<<<<
3708 19:57:30.031769 Enter into PICG configuration >>>>
3709 19:57:30.035284 Exit from PICG configuration <<<<
3710 19:57:30.038509 [RX_INPUT] configuration >>>>>
3711 19:57:30.041869 [RX_INPUT] configuration <<<<<
3712 19:57:30.048429 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3713 19:57:30.052316 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3714 19:57:30.058499 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3715 19:57:30.065153 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3716 19:57:30.071678 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3717 19:57:30.078708 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3718 19:57:30.081528 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3719 19:57:30.085120 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3720 19:57:30.088355 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3721 19:57:30.095068 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3722 19:57:30.098571 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3723 19:57:30.101344 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3724 19:57:30.104907 ===================================
3725 19:57:30.108059 LPDDR4 DRAM CONFIGURATION
3726 19:57:30.111457 ===================================
3727 19:57:30.114678 EX_ROW_EN[0] = 0x0
3728 19:57:30.115237 EX_ROW_EN[1] = 0x0
3729 19:57:30.117841 LP4Y_EN = 0x0
3730 19:57:30.118301 WORK_FSP = 0x0
3731 19:57:30.121249 WL = 0x2
3732 19:57:30.121708 RL = 0x2
3733 19:57:30.124525 BL = 0x2
3734 19:57:30.124983 RPST = 0x0
3735 19:57:30.127806 RD_PRE = 0x0
3736 19:57:30.128312 WR_PRE = 0x1
3737 19:57:30.131134 WR_PST = 0x0
3738 19:57:30.131589 DBI_WR = 0x0
3739 19:57:30.134751 DBI_RD = 0x0
3740 19:57:30.135305 OTF = 0x1
3741 19:57:30.138380 ===================================
3742 19:57:30.141468 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3743 19:57:30.148013 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3744 19:57:30.151313 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3745 19:57:30.154762 ===================================
3746 19:57:30.157871 LPDDR4 DRAM CONFIGURATION
3747 19:57:30.161185 ===================================
3748 19:57:30.161744 EX_ROW_EN[0] = 0x10
3749 19:57:30.164776 EX_ROW_EN[1] = 0x0
3750 19:57:30.167937 LP4Y_EN = 0x0
3751 19:57:30.168555 WORK_FSP = 0x0
3752 19:57:30.171104 WL = 0x2
3753 19:57:30.171664 RL = 0x2
3754 19:57:30.174417 BL = 0x2
3755 19:57:30.174874 RPST = 0x0
3756 19:57:30.177950 RD_PRE = 0x0
3757 19:57:30.178506 WR_PRE = 0x1
3758 19:57:30.181290 WR_PST = 0x0
3759 19:57:30.181844 DBI_WR = 0x0
3760 19:57:30.184361 DBI_RD = 0x0
3761 19:57:30.184917 OTF = 0x1
3762 19:57:30.187952 ===================================
3763 19:57:30.194291 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3764 19:57:30.198858 nWR fixed to 30
3765 19:57:30.201633 [ModeRegInit_LP4] CH0 RK0
3766 19:57:30.202284 [ModeRegInit_LP4] CH0 RK1
3767 19:57:30.205255 [ModeRegInit_LP4] CH1 RK0
3768 19:57:30.208313 [ModeRegInit_LP4] CH1 RK1
3769 19:57:30.208772 match AC timing 16
3770 19:57:30.215203 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3771 19:57:30.218412 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3772 19:57:30.221672 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3773 19:57:30.228134 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3774 19:57:30.231561 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3775 19:57:30.232218 ==
3776 19:57:30.235165 Dram Type= 6, Freq= 0, CH_0, rank 0
3777 19:57:30.238293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3778 19:57:30.238950 ==
3779 19:57:30.244965 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3780 19:57:30.251514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3781 19:57:30.254914 [CA 0] Center 36 (6~66) winsize 61
3782 19:57:30.258363 [CA 1] Center 35 (5~66) winsize 62
3783 19:57:30.261698 [CA 2] Center 34 (4~65) winsize 62
3784 19:57:30.264688 [CA 3] Center 34 (4~65) winsize 62
3785 19:57:30.268320 [CA 4] Center 33 (3~64) winsize 62
3786 19:57:30.271342 [CA 5] Center 33 (3~64) winsize 62
3787 19:57:30.271798
3788 19:57:30.274494 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3789 19:57:30.274951
3790 19:57:30.278154 [CATrainingPosCal] consider 1 rank data
3791 19:57:30.281658 u2DelayCellTimex100 = 270/100 ps
3792 19:57:30.284943 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3793 19:57:30.288109 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3794 19:57:30.290989 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3795 19:57:30.294607 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3796 19:57:30.298366 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3797 19:57:30.304436 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3798 19:57:30.304980
3799 19:57:30.307956 CA PerBit enable=1, Macro0, CA PI delay=33
3800 19:57:30.308464
3801 19:57:30.311070 [CBTSetCACLKResult] CA Dly = 33
3802 19:57:30.311526 CS Dly: 4 (0~35)
3803 19:57:30.311883 ==
3804 19:57:30.314880 Dram Type= 6, Freq= 0, CH_0, rank 1
3805 19:57:30.317972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3806 19:57:30.321383 ==
3807 19:57:30.324306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3808 19:57:30.331230 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3809 19:57:30.334071 [CA 0] Center 35 (5~66) winsize 62
3810 19:57:30.337554 [CA 1] Center 35 (5~66) winsize 62
3811 19:57:30.340784 [CA 2] Center 34 (4~65) winsize 62
3812 19:57:30.344143 [CA 3] Center 34 (3~65) winsize 63
3813 19:57:30.347609 [CA 4] Center 33 (3~64) winsize 62
3814 19:57:30.351031 [CA 5] Center 33 (3~64) winsize 62
3815 19:57:30.351604
3816 19:57:30.354120 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3817 19:57:30.354578
3818 19:57:30.357778 [CATrainingPosCal] consider 2 rank data
3819 19:57:30.360957 u2DelayCellTimex100 = 270/100 ps
3820 19:57:30.364129 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3821 19:57:30.367696 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3822 19:57:30.370848 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3823 19:57:30.377700 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3824 19:57:30.380949 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3825 19:57:30.384239 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3826 19:57:30.384802
3827 19:57:30.387733 CA PerBit enable=1, Macro0, CA PI delay=33
3828 19:57:30.388334
3829 19:57:30.390848 [CBTSetCACLKResult] CA Dly = 33
3830 19:57:30.391399 CS Dly: 4 (0~35)
3831 19:57:30.391759
3832 19:57:30.394494 ----->DramcWriteLeveling(PI) begin...
3833 19:57:30.397681 ==
3834 19:57:30.398307 Dram Type= 6, Freq= 0, CH_0, rank 0
3835 19:57:30.403733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3836 19:57:30.404221 ==
3837 19:57:30.407232 Write leveling (Byte 0): 33 => 33
3838 19:57:30.410345 Write leveling (Byte 1): 30 => 30
3839 19:57:30.413814 DramcWriteLeveling(PI) end<-----
3840 19:57:30.414374
3841 19:57:30.414738 ==
3842 19:57:30.417286 Dram Type= 6, Freq= 0, CH_0, rank 0
3843 19:57:30.420509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3844 19:57:30.420972 ==
3845 19:57:30.423786 [Gating] SW mode calibration
3846 19:57:30.430786 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3847 19:57:30.433759 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3848 19:57:30.440371 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3849 19:57:30.443774 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3850 19:57:30.447125 0 5 8 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)
3851 19:57:30.453864 0 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
3852 19:57:30.456924 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3853 19:57:30.460345 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3854 19:57:30.467110 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3855 19:57:30.470164 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3856 19:57:30.473763 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3857 19:57:30.480263 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3858 19:57:30.483818 0 6 8 | B1->B0 | 2a2a 3535 | 0 0 | (0 0) (0 0)
3859 19:57:30.486724 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3860 19:57:30.493380 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3861 19:57:30.496937 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3862 19:57:30.500105 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3863 19:57:30.506351 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3864 19:57:30.509527 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3865 19:57:30.513282 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3866 19:57:30.520123 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3867 19:57:30.523106 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3868 19:57:30.526864 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3869 19:57:30.532967 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3870 19:57:30.536426 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3871 19:57:30.540038 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3872 19:57:30.545996 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 19:57:30.549535 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 19:57:30.552820 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 19:57:30.559537 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 19:57:30.562758 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 19:57:30.566211 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 19:57:30.572925 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 19:57:30.576299 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 19:57:30.579383 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 19:57:30.586125 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 19:57:30.589155 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3883 19:57:30.592596 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3884 19:57:30.596102 Total UI for P1: 0, mck2ui 16
3885 19:57:30.599111 best dqsien dly found for B0: ( 0, 9, 8)
3886 19:57:30.602416 Total UI for P1: 0, mck2ui 16
3887 19:57:30.605542 best dqsien dly found for B1: ( 0, 9, 10)
3888 19:57:30.609175 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3889 19:57:30.612468 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3890 19:57:30.612974
3891 19:57:30.615721 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3892 19:57:30.622450 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3893 19:57:30.622959 [Gating] SW calibration Done
3894 19:57:30.623315 ==
3895 19:57:30.625502 Dram Type= 6, Freq= 0, CH_0, rank 0
3896 19:57:30.632057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3897 19:57:30.632316 ==
3898 19:57:30.632507 RX Vref Scan: 0
3899 19:57:30.632684
3900 19:57:30.635369 RX Vref 0 -> 0, step: 1
3901 19:57:30.635558
3902 19:57:30.638585 RX Delay -230 -> 252, step: 16
3903 19:57:30.641901 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3904 19:57:30.645134 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3905 19:57:30.651772 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3906 19:57:30.655354 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3907 19:57:30.658511 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3908 19:57:30.661791 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3909 19:57:30.664976 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3910 19:57:30.671782 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3911 19:57:30.675036 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3912 19:57:30.678311 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3913 19:57:30.681519 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3914 19:57:30.688147 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3915 19:57:30.691401 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3916 19:57:30.694799 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3917 19:57:30.697974 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3918 19:57:30.704766 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3919 19:57:30.704861 ==
3920 19:57:30.708077 Dram Type= 6, Freq= 0, CH_0, rank 0
3921 19:57:30.711505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3922 19:57:30.711600 ==
3923 19:57:30.711673 DQS Delay:
3924 19:57:30.715088 DQS0 = 0, DQS1 = 0
3925 19:57:30.715504 DQM Delay:
3926 19:57:30.718444 DQM0 = 39, DQM1 = 33
3927 19:57:30.718862 DQ Delay:
3928 19:57:30.721768 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3929 19:57:30.725054 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3930 19:57:30.728873 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3931 19:57:30.731596 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3932 19:57:30.732080
3933 19:57:30.732448
3934 19:57:30.732758 ==
3935 19:57:30.734932 Dram Type= 6, Freq= 0, CH_0, rank 0
3936 19:57:30.738200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3937 19:57:30.738621 ==
3938 19:57:30.738952
3939 19:57:30.741581
3940 19:57:30.741993 TX Vref Scan disable
3941 19:57:30.744874 == TX Byte 0 ==
3942 19:57:30.748130 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
3943 19:57:30.751397 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
3944 19:57:30.754690 == TX Byte 1 ==
3945 19:57:30.757941 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3946 19:57:30.761098 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3947 19:57:30.761250 ==
3948 19:57:30.764698 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 19:57:30.771602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 19:57:30.772042 ==
3951 19:57:30.772351
3952 19:57:30.772595
3953 19:57:30.772825 TX Vref Scan disable
3954 19:57:30.776503 == TX Byte 0 ==
3955 19:57:30.779357 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
3956 19:57:30.785853 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
3957 19:57:30.786179 == TX Byte 1 ==
3958 19:57:30.789194 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3959 19:57:30.796058 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3960 19:57:30.796535
3961 19:57:30.796803 [DATLAT]
3962 19:57:30.797062 Freq=600, CH0 RK0
3963 19:57:30.797388
3964 19:57:30.799884 DATLAT Default: 0x9
3965 19:57:30.800245 0, 0xFFFF, sum = 0
3966 19:57:30.802515 1, 0xFFFF, sum = 0
3967 19:57:30.802853 2, 0xFFFF, sum = 0
3968 19:57:30.805827 3, 0xFFFF, sum = 0
3969 19:57:30.809103 4, 0xFFFF, sum = 0
3970 19:57:30.809448 5, 0xFFFF, sum = 0
3971 19:57:30.812449 6, 0xFFFF, sum = 0
3972 19:57:30.812787 7, 0x0, sum = 1
3973 19:57:30.813145 8, 0x0, sum = 2
3974 19:57:30.815773 9, 0x0, sum = 3
3975 19:57:30.816099 10, 0x0, sum = 4
3976 19:57:30.819231 best_step = 8
3977 19:57:30.819652
3978 19:57:30.819914 ==
3979 19:57:30.822729 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 19:57:30.826042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3981 19:57:30.826460 ==
3982 19:57:30.828957 RX Vref Scan: 1
3983 19:57:30.829318
3984 19:57:30.829584 RX Vref 0 -> 0, step: 1
3985 19:57:30.829900
3986 19:57:30.832155 RX Delay -195 -> 252, step: 8
3987 19:57:30.832515
3988 19:57:30.835530 Set Vref, RX VrefLevel [Byte0]: 51
3989 19:57:30.839350 [Byte1]: 51
3990 19:57:30.843256
3991 19:57:30.843820 Final RX Vref Byte 0 = 51 to rank0
3992 19:57:30.846855 Final RX Vref Byte 1 = 51 to rank0
3993 19:57:30.850026 Final RX Vref Byte 0 = 51 to rank1
3994 19:57:30.853440 Final RX Vref Byte 1 = 51 to rank1==
3995 19:57:30.856347 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 19:57:30.863103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3997 19:57:30.863672 ==
3998 19:57:30.864042 DQS Delay:
3999 19:57:30.866508 DQS0 = 0, DQS1 = 0
4000 19:57:30.867065 DQM Delay:
4001 19:57:30.867432 DQM0 = 39, DQM1 = 30
4002 19:57:30.869459 DQ Delay:
4003 19:57:30.873002 DQ0 =32, DQ1 =40, DQ2 =40, DQ3 =40
4004 19:57:30.876447 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4005 19:57:30.879695 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
4006 19:57:30.882996 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4007 19:57:30.883556
4008 19:57:30.883921
4009 19:57:30.889772 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4010 19:57:30.892981 CH0 RK0: MR19=808, MR18=5C5C
4011 19:57:30.899130 CH0_RK0: MR19=0x808, MR18=0x5C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4012 19:57:30.899675
4013 19:57:30.902858 ----->DramcWriteLeveling(PI) begin...
4014 19:57:30.903424 ==
4015 19:57:30.905887 Dram Type= 6, Freq= 0, CH_0, rank 1
4016 19:57:30.909412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4017 19:57:30.909985 ==
4018 19:57:30.912488 Write leveling (Byte 0): 30 => 30
4019 19:57:30.916163 Write leveling (Byte 1): 29 => 29
4020 19:57:30.919259 DramcWriteLeveling(PI) end<-----
4021 19:57:30.919821
4022 19:57:30.920237 ==
4023 19:57:30.922665 Dram Type= 6, Freq= 0, CH_0, rank 1
4024 19:57:30.925764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4025 19:57:30.929128 ==
4026 19:57:30.929685 [Gating] SW mode calibration
4027 19:57:30.935616 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4028 19:57:30.942543 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4029 19:57:30.945762 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 19:57:30.952457 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 19:57:30.955742 0 5 8 | B1->B0 | 3131 3333 | 0 0 | (0 0) (0 1)
4032 19:57:30.958967 0 5 12 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
4033 19:57:30.965518 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 19:57:30.968800 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 19:57:30.972125 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 19:57:30.978966 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 19:57:30.982250 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 19:57:30.985583 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 19:57:30.992361 0 6 8 | B1->B0 | 2525 3434 | 0 0 | (0 0) (1 1)
4040 19:57:30.995450 0 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
4041 19:57:30.998648 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 19:57:31.005458 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 19:57:31.008482 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 19:57:31.011940 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 19:57:31.018655 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 19:57:31.021682 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4047 19:57:31.024983 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4048 19:57:31.032069 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 19:57:31.035068 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 19:57:31.038399 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 19:57:31.044928 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 19:57:31.048295 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 19:57:31.051977 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 19:57:31.058228 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 19:57:31.061405 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 19:57:31.065047 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 19:57:31.068347 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 19:57:31.074902 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 19:57:31.078764 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 19:57:31.081573 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 19:57:31.088363 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 19:57:31.091648 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 19:57:31.094834 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 19:57:31.098791 Total UI for P1: 0, mck2ui 16
4065 19:57:31.101417 best dqsien dly found for B0: ( 0, 9, 6)
4066 19:57:31.104849 Total UI for P1: 0, mck2ui 16
4067 19:57:31.107920 best dqsien dly found for B1: ( 0, 9, 6)
4068 19:57:31.111143 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4069 19:57:31.114614 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4070 19:57:31.115186
4071 19:57:31.121184 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4072 19:57:31.124381 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4073 19:57:31.127985 [Gating] SW calibration Done
4074 19:57:31.128602 ==
4075 19:57:31.131305 Dram Type= 6, Freq= 0, CH_0, rank 1
4076 19:57:31.134904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4077 19:57:31.135470 ==
4078 19:57:31.135839 RX Vref Scan: 0
4079 19:57:31.136215
4080 19:57:31.137812 RX Vref 0 -> 0, step: 1
4081 19:57:31.138352
4082 19:57:31.140939 RX Delay -230 -> 252, step: 16
4083 19:57:31.144289 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4084 19:57:31.150930 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4085 19:57:31.154573 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4086 19:57:31.157629 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4087 19:57:31.160883 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4088 19:57:31.164277 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4089 19:57:31.170807 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4090 19:57:31.174020 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4091 19:57:31.177476 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4092 19:57:31.180801 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4093 19:57:31.187647 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4094 19:57:31.190669 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4095 19:57:31.194160 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4096 19:57:31.197251 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4097 19:57:31.204307 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4098 19:57:31.207105 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4099 19:57:31.207583 ==
4100 19:57:31.210597 Dram Type= 6, Freq= 0, CH_0, rank 1
4101 19:57:31.213926 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4102 19:57:31.214482 ==
4103 19:57:31.214847 DQS Delay:
4104 19:57:31.217650 DQS0 = 0, DQS1 = 0
4105 19:57:31.218200 DQM Delay:
4106 19:57:31.220477 DQM0 = 40, DQM1 = 33
4107 19:57:31.220940 DQ Delay:
4108 19:57:31.224360 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4109 19:57:31.227470 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4110 19:57:31.230603 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4111 19:57:31.234053 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4112 19:57:31.234604
4113 19:57:31.234970
4114 19:57:31.235380 ==
4115 19:57:31.237031 Dram Type= 6, Freq= 0, CH_0, rank 1
4116 19:57:31.243881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4117 19:57:31.244502 ==
4118 19:57:31.244878
4119 19:57:31.245220
4120 19:57:31.245545 TX Vref Scan disable
4121 19:57:31.247429 == TX Byte 0 ==
4122 19:57:31.250266 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4123 19:57:31.256974 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4124 19:57:31.257523 == TX Byte 1 ==
4125 19:57:31.260549 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4126 19:57:31.266900 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4127 19:57:31.267424 ==
4128 19:57:31.270222 Dram Type= 6, Freq= 0, CH_0, rank 1
4129 19:57:31.274059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4130 19:57:31.274658 ==
4131 19:57:31.275037
4132 19:57:31.275376
4133 19:57:31.276847 TX Vref Scan disable
4134 19:57:31.280840 == TX Byte 0 ==
4135 19:57:31.283530 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4136 19:57:31.287110 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4137 19:57:31.290471 == TX Byte 1 ==
4138 19:57:31.293690 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4139 19:57:31.296859 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4140 19:57:31.297415
4141 19:57:31.297783 [DATLAT]
4142 19:57:31.300143 Freq=600, CH0 RK1
4143 19:57:31.300786
4144 19:57:31.301263 DATLAT Default: 0x8
4145 19:57:31.303334 0, 0xFFFF, sum = 0
4146 19:57:31.306721 1, 0xFFFF, sum = 0
4147 19:57:31.307191 2, 0xFFFF, sum = 0
4148 19:57:31.309788 3, 0xFFFF, sum = 0
4149 19:57:31.310255 4, 0xFFFF, sum = 0
4150 19:57:31.313294 5, 0xFFFF, sum = 0
4151 19:57:31.313777 6, 0xFFFF, sum = 0
4152 19:57:31.316418 7, 0x0, sum = 1
4153 19:57:31.316903 8, 0x0, sum = 2
4154 19:57:31.317392 9, 0x0, sum = 3
4155 19:57:31.319714 10, 0x0, sum = 4
4156 19:57:31.320232 best_step = 8
4157 19:57:31.320723
4158 19:57:31.321176 ==
4159 19:57:31.323240 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 19:57:31.330104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4161 19:57:31.330688 ==
4162 19:57:31.331180 RX Vref Scan: 0
4163 19:57:31.331638
4164 19:57:31.333195 RX Vref 0 -> 0, step: 1
4165 19:57:31.333666
4166 19:57:31.336590 RX Delay -195 -> 252, step: 8
4167 19:57:31.339771 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4168 19:57:31.346655 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4169 19:57:31.349715 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4170 19:57:31.353127 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4171 19:57:31.356297 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4172 19:57:31.363138 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4173 19:57:31.366568 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4174 19:57:31.369655 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4175 19:57:31.373137 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4176 19:57:31.376572 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4177 19:57:31.383183 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4178 19:57:31.386579 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4179 19:57:31.390040 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4180 19:57:31.392887 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4181 19:57:31.399570 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4182 19:57:31.403060 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4183 19:57:31.403555 ==
4184 19:57:31.406473 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 19:57:31.409480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4186 19:57:31.410030 ==
4187 19:57:31.412772 DQS Delay:
4188 19:57:31.413373 DQS0 = 0, DQS1 = 0
4189 19:57:31.413888 DQM Delay:
4190 19:57:31.416159 DQM0 = 42, DQM1 = 32
4191 19:57:31.416654 DQ Delay:
4192 19:57:31.419892 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4193 19:57:31.423013 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =48
4194 19:57:31.425982 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4195 19:57:31.429857 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4196 19:57:31.430419
4197 19:57:31.430783
4198 19:57:31.439530 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d6d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4199 19:57:31.442894 CH0 RK1: MR19=808, MR18=6D6D
4200 19:57:31.446508 CH0_RK1: MR19=0x808, MR18=0x6D6D, DQSOSC=389, MR23=63, INC=173, DEC=115
4201 19:57:31.449374 [RxdqsGatingPostProcess] freq 600
4202 19:57:31.456134 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4203 19:57:31.459534 Pre-setting of DQS Precalculation
4204 19:57:31.462757 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4205 19:57:31.463315 ==
4206 19:57:31.466009 Dram Type= 6, Freq= 0, CH_1, rank 0
4207 19:57:31.472895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4208 19:57:31.473465 ==
4209 19:57:31.475805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4210 19:57:31.482642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4211 19:57:31.486074 [CA 0] Center 35 (5~66) winsize 62
4212 19:57:31.489235 [CA 1] Center 35 (5~66) winsize 62
4213 19:57:31.492823 [CA 2] Center 33 (3~64) winsize 62
4214 19:57:31.496137 [CA 3] Center 33 (3~64) winsize 62
4215 19:57:31.499278 [CA 4] Center 33 (2~64) winsize 63
4216 19:57:31.502755 [CA 5] Center 33 (2~64) winsize 63
4217 19:57:31.503319
4218 19:57:31.505998 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4219 19:57:31.506556
4220 19:57:31.509005 [CATrainingPosCal] consider 1 rank data
4221 19:57:31.512345 u2DelayCellTimex100 = 270/100 ps
4222 19:57:31.515610 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4223 19:57:31.519250 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4224 19:57:31.525643 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4225 19:57:31.529128 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4226 19:57:31.532546 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4227 19:57:31.535640 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4228 19:57:31.536121
4229 19:57:31.539310 CA PerBit enable=1, Macro0, CA PI delay=33
4230 19:57:31.539864
4231 19:57:31.542512 [CBTSetCACLKResult] CA Dly = 33
4232 19:57:31.543069 CS Dly: 3 (0~34)
4233 19:57:31.545813 ==
4234 19:57:31.548682 Dram Type= 6, Freq= 0, CH_1, rank 1
4235 19:57:31.552625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4236 19:57:31.553184 ==
4237 19:57:31.555518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4238 19:57:31.562312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4239 19:57:31.566197 [CA 0] Center 35 (5~66) winsize 62
4240 19:57:31.569653 [CA 1] Center 34 (4~65) winsize 62
4241 19:57:31.572721 [CA 2] Center 33 (3~64) winsize 62
4242 19:57:31.576221 [CA 3] Center 33 (3~64) winsize 62
4243 19:57:31.579354 [CA 4] Center 32 (2~63) winsize 62
4244 19:57:31.582455 [CA 5] Center 32 (2~63) winsize 62
4245 19:57:31.583012
4246 19:57:31.585815 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4247 19:57:31.586394
4248 19:57:31.589039 [CATrainingPosCal] consider 2 rank data
4249 19:57:31.592754 u2DelayCellTimex100 = 270/100 ps
4250 19:57:31.595761 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4251 19:57:31.602400 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4252 19:57:31.605918 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4253 19:57:31.608747 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4254 19:57:31.611947 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4255 19:57:31.615497 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4256 19:57:31.615954
4257 19:57:31.618711 CA PerBit enable=1, Macro0, CA PI delay=32
4258 19:57:31.619169
4259 19:57:31.621911 [CBTSetCACLKResult] CA Dly = 32
4260 19:57:31.625165 CS Dly: 4 (0~36)
4261 19:57:31.625762
4262 19:57:31.628557 ----->DramcWriteLeveling(PI) begin...
4263 19:57:31.629022 ==
4264 19:57:31.631941 Dram Type= 6, Freq= 0, CH_1, rank 0
4265 19:57:31.635230 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4266 19:57:31.635856 ==
4267 19:57:31.638520 Write leveling (Byte 0): 27 => 27
4268 19:57:31.642143 Write leveling (Byte 1): 27 => 27
4269 19:57:31.645110 DramcWriteLeveling(PI) end<-----
4270 19:57:31.645670
4271 19:57:31.646035 ==
4272 19:57:31.648620 Dram Type= 6, Freq= 0, CH_1, rank 0
4273 19:57:31.651911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4274 19:57:31.652544 ==
4275 19:57:31.655384 [Gating] SW mode calibration
4276 19:57:31.661871 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4277 19:57:31.669041 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4278 19:57:31.671665 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4279 19:57:31.675150 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4280 19:57:31.681731 0 5 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
4281 19:57:31.685026 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 19:57:31.688318 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 19:57:31.694847 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 19:57:31.698364 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 19:57:31.701185 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 19:57:31.707876 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 19:57:31.711130 0 6 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4288 19:57:31.714252 0 6 8 | B1->B0 | 3737 3d3d | 0 0 | (0 0) (1 1)
4289 19:57:31.720975 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 19:57:31.724432 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 19:57:31.727588 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 19:57:31.734582 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 19:57:31.737775 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 19:57:31.741023 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 19:57:31.747837 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4296 19:57:31.750770 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 19:57:31.754110 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 19:57:31.760722 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 19:57:31.764286 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 19:57:31.767879 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 19:57:31.774150 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 19:57:31.777672 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 19:57:31.780842 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 19:57:31.787535 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 19:57:31.790810 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 19:57:31.794065 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 19:57:31.800456 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 19:57:31.803999 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 19:57:31.807424 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 19:57:31.813761 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 19:57:31.816856 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 19:57:31.820454 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4313 19:57:31.823620 Total UI for P1: 0, mck2ui 16
4314 19:57:31.827114 best dqsien dly found for B0: ( 0, 9, 6)
4315 19:57:31.830463 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4316 19:57:31.834012 Total UI for P1: 0, mck2ui 16
4317 19:57:31.837031 best dqsien dly found for B1: ( 0, 9, 8)
4318 19:57:31.840243 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4319 19:57:31.844101 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4320 19:57:31.847406
4321 19:57:31.850399 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4322 19:57:31.853643 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4323 19:57:31.857020 [Gating] SW calibration Done
4324 19:57:31.857580 ==
4325 19:57:31.860287 Dram Type= 6, Freq= 0, CH_1, rank 0
4326 19:57:31.863696 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4327 19:57:31.864295 ==
4328 19:57:31.864667 RX Vref Scan: 0
4329 19:57:31.867321
4330 19:57:31.867991 RX Vref 0 -> 0, step: 1
4331 19:57:31.868440
4332 19:57:31.870115 RX Delay -230 -> 252, step: 16
4333 19:57:31.873651 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4334 19:57:31.880472 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4335 19:57:31.883524 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4336 19:57:31.886869 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4337 19:57:31.890148 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4338 19:57:31.893459 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4339 19:57:31.900023 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4340 19:57:31.903404 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4341 19:57:31.906844 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4342 19:57:31.910016 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4343 19:57:31.916743 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4344 19:57:31.919710 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4345 19:57:31.923595 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4346 19:57:31.926264 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4347 19:57:31.932933 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4348 19:57:31.936337 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4349 19:57:31.936808 ==
4350 19:57:31.939655 Dram Type= 6, Freq= 0, CH_1, rank 0
4351 19:57:31.942998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4352 19:57:31.943634 ==
4353 19:57:31.946569 DQS Delay:
4354 19:57:31.947132 DQS0 = 0, DQS1 = 0
4355 19:57:31.947603 DQM Delay:
4356 19:57:31.949477 DQM0 = 41, DQM1 = 33
4357 19:57:31.949932 DQ Delay:
4358 19:57:31.952698 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4359 19:57:31.956407 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4360 19:57:31.959469 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4361 19:57:31.962816 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4362 19:57:31.963273
4363 19:57:31.963628
4364 19:57:31.963962 ==
4365 19:57:31.966111 Dram Type= 6, Freq= 0, CH_1, rank 0
4366 19:57:31.972691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4367 19:57:31.973150 ==
4368 19:57:31.973509
4369 19:57:31.973835
4370 19:57:31.974154 TX Vref Scan disable
4371 19:57:31.976264 == TX Byte 0 ==
4372 19:57:31.979468 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4373 19:57:31.986547 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4374 19:57:31.987106 == TX Byte 1 ==
4375 19:57:31.989824 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4376 19:57:31.996777 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4377 19:57:31.997344 ==
4378 19:57:31.999708 Dram Type= 6, Freq= 0, CH_1, rank 0
4379 19:57:32.003069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4380 19:57:32.003630 ==
4381 19:57:32.003995
4382 19:57:32.004399
4383 19:57:32.006321 TX Vref Scan disable
4384 19:57:32.009452 == TX Byte 0 ==
4385 19:57:32.013219 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4386 19:57:32.016262 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4387 19:57:32.019608 == TX Byte 1 ==
4388 19:57:32.023203 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4389 19:57:32.026116 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4390 19:57:32.026577
4391 19:57:32.026936 [DATLAT]
4392 19:57:32.029604 Freq=600, CH1 RK0
4393 19:57:32.030059
4394 19:57:32.030421 DATLAT Default: 0x9
4395 19:57:32.032594 0, 0xFFFF, sum = 0
4396 19:57:32.036090 1, 0xFFFF, sum = 0
4397 19:57:32.036645 2, 0xFFFF, sum = 0
4398 19:57:32.039584 3, 0xFFFF, sum = 0
4399 19:57:32.039998 4, 0xFFFF, sum = 0
4400 19:57:32.042772 5, 0xFFFF, sum = 0
4401 19:57:32.043339 6, 0xFFFF, sum = 0
4402 19:57:32.046453 7, 0x0, sum = 1
4403 19:57:32.047023 8, 0x0, sum = 2
4404 19:57:32.047393 9, 0x0, sum = 3
4405 19:57:32.049401 10, 0x0, sum = 4
4406 19:57:32.050022 best_step = 8
4407 19:57:32.050579
4408 19:57:32.050942 ==
4409 19:57:32.052532 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 19:57:32.059367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4411 19:57:32.059934 ==
4412 19:57:32.060565 RX Vref Scan: 1
4413 19:57:32.060945
4414 19:57:32.062817 RX Vref 0 -> 0, step: 1
4415 19:57:32.063376
4416 19:57:32.066160 RX Delay -195 -> 252, step: 8
4417 19:57:32.066713
4418 19:57:32.069473 Set Vref, RX VrefLevel [Byte0]: 53
4419 19:57:32.072629 [Byte1]: 50
4420 19:57:32.073189
4421 19:57:32.075819 Final RX Vref Byte 0 = 53 to rank0
4422 19:57:32.079688 Final RX Vref Byte 1 = 50 to rank0
4423 19:57:32.082427 Final RX Vref Byte 0 = 53 to rank1
4424 19:57:32.086039 Final RX Vref Byte 1 = 50 to rank1==
4425 19:57:32.089003 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 19:57:32.092544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4427 19:57:32.093107 ==
4428 19:57:32.095742 DQS Delay:
4429 19:57:32.096357 DQS0 = 0, DQS1 = 0
4430 19:57:32.099243 DQM Delay:
4431 19:57:32.099839 DQM0 = 37, DQM1 = 31
4432 19:57:32.100412 DQ Delay:
4433 19:57:32.102641 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4434 19:57:32.105754 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4435 19:57:32.109139 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =24
4436 19:57:32.112328 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4437 19:57:32.113025
4438 19:57:32.113430
4439 19:57:32.122379 [DQSOSCAuto] RK0, (LSB)MR18= 0x7272, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4440 19:57:32.125673 CH1 RK0: MR19=808, MR18=7272
4441 19:57:32.132254 CH1_RK0: MR19=0x808, MR18=0x7272, DQSOSC=388, MR23=63, INC=174, DEC=116
4442 19:57:32.132804
4443 19:57:32.135635 ----->DramcWriteLeveling(PI) begin...
4444 19:57:32.136247 ==
4445 19:57:32.139005 Dram Type= 6, Freq= 0, CH_1, rank 1
4446 19:57:32.142544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4447 19:57:32.143102 ==
4448 19:57:32.145611 Write leveling (Byte 0): 28 => 28
4449 19:57:32.149386 Write leveling (Byte 1): 27 => 27
4450 19:57:32.152130 DramcWriteLeveling(PI) end<-----
4451 19:57:32.152616
4452 19:57:32.152979 ==
4453 19:57:32.155485 Dram Type= 6, Freq= 0, CH_1, rank 1
4454 19:57:32.158996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4455 19:57:32.159574 ==
4456 19:57:32.162264 [Gating] SW mode calibration
4457 19:57:32.169185 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4458 19:57:32.175873 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4459 19:57:32.178803 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 19:57:32.182507 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
4461 19:57:32.188816 0 5 8 | B1->B0 | 2f2f 2626 | 1 1 | (1 0) (1 0)
4462 19:57:32.192109 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 19:57:32.195467 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 19:57:32.201728 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 19:57:32.205152 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 19:57:32.208340 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 19:57:32.214965 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 19:57:32.218272 0 6 4 | B1->B0 | 2323 3434 | 1 0 | (0 0) (0 0)
4469 19:57:32.221666 0 6 8 | B1->B0 | 3737 4444 | 0 0 | (0 0) (0 0)
4470 19:57:32.228133 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 19:57:32.231438 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 19:57:32.234792 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 19:57:32.241709 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 19:57:32.244583 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 19:57:32.248433 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 19:57:32.254969 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4477 19:57:32.258040 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4478 19:57:32.261680 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 19:57:32.267902 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 19:57:32.271423 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 19:57:32.274470 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 19:57:32.281274 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 19:57:32.284543 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 19:57:32.287689 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 19:57:32.294296 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 19:57:32.297912 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 19:57:32.300928 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 19:57:32.304957 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 19:57:32.310758 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 19:57:32.314273 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 19:57:32.317503 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 19:57:32.324248 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4493 19:57:32.327368 Total UI for P1: 0, mck2ui 16
4494 19:57:32.331105 best dqsien dly found for B0: ( 0, 9, 2)
4495 19:57:32.334395 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 19:57:32.337744 Total UI for P1: 0, mck2ui 16
4497 19:57:32.340941 best dqsien dly found for B1: ( 0, 9, 4)
4498 19:57:32.344126 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4499 19:57:32.347617 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4500 19:57:32.348268
4501 19:57:32.350816 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4502 19:57:32.353979 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4503 19:57:32.357524 [Gating] SW calibration Done
4504 19:57:32.358232 ==
4505 19:57:32.360722 Dram Type= 6, Freq= 0, CH_1, rank 1
4506 19:57:32.367735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4507 19:57:32.368349 ==
4508 19:57:32.368723 RX Vref Scan: 0
4509 19:57:32.369066
4510 19:57:32.370335 RX Vref 0 -> 0, step: 1
4511 19:57:32.370794
4512 19:57:32.373986 RX Delay -230 -> 252, step: 16
4513 19:57:32.376972 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4514 19:57:32.380320 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4515 19:57:32.383577 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4516 19:57:32.390571 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4517 19:57:32.393801 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4518 19:57:32.396732 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4519 19:57:32.400283 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4520 19:57:32.407320 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4521 19:57:32.410438 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4522 19:57:32.413472 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4523 19:57:32.416548 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4524 19:57:32.423436 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4525 19:57:32.426482 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4526 19:57:32.430016 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4527 19:57:32.433084 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4528 19:57:32.439850 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4529 19:57:32.440429 ==
4530 19:57:32.443109 Dram Type= 6, Freq= 0, CH_1, rank 1
4531 19:57:32.446633 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4532 19:57:32.447204 ==
4533 19:57:32.447573 DQS Delay:
4534 19:57:32.450003 DQS0 = 0, DQS1 = 0
4535 19:57:32.450565 DQM Delay:
4536 19:57:32.453103 DQM0 = 40, DQM1 = 33
4537 19:57:32.453560 DQ Delay:
4538 19:57:32.456632 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4539 19:57:32.459933 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4540 19:57:32.463237 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4541 19:57:32.466581 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4542 19:57:32.467042
4543 19:57:32.467404
4544 19:57:32.467738 ==
4545 19:57:32.469880 Dram Type= 6, Freq= 0, CH_1, rank 1
4546 19:57:32.473016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4547 19:57:32.473483 ==
4548 19:57:32.473847
4549 19:57:32.474182
4550 19:57:32.476440 TX Vref Scan disable
4551 19:57:32.479838 == TX Byte 0 ==
4552 19:57:32.483236 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4553 19:57:32.486566 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4554 19:57:32.489822 == TX Byte 1 ==
4555 19:57:32.493136 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4556 19:57:32.496391 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4557 19:57:32.496952 ==
4558 19:57:32.500128 Dram Type= 6, Freq= 0, CH_1, rank 1
4559 19:57:32.506191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4560 19:57:32.506762 ==
4561 19:57:32.507133
4562 19:57:32.507476
4563 19:57:32.507801 TX Vref Scan disable
4564 19:57:32.510894 == TX Byte 0 ==
4565 19:57:32.513883 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4566 19:57:32.520363 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4567 19:57:32.520829 == TX Byte 1 ==
4568 19:57:32.524042 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4569 19:57:32.530600 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4570 19:57:32.531163
4571 19:57:32.531532 [DATLAT]
4572 19:57:32.531867 Freq=600, CH1 RK1
4573 19:57:32.532239
4574 19:57:32.533613 DATLAT Default: 0x8
4575 19:57:32.534070 0, 0xFFFF, sum = 0
4576 19:57:32.536954 1, 0xFFFF, sum = 0
4577 19:57:32.537480 2, 0xFFFF, sum = 0
4578 19:57:32.540131 3, 0xFFFF, sum = 0
4579 19:57:32.543745 4, 0xFFFF, sum = 0
4580 19:57:32.544357 5, 0xFFFF, sum = 0
4581 19:57:32.546951 6, 0xFFFF, sum = 0
4582 19:57:32.547575 7, 0x0, sum = 1
4583 19:57:32.548168 8, 0x0, sum = 2
4584 19:57:32.550071 9, 0x0, sum = 3
4585 19:57:32.550627 10, 0x0, sum = 4
4586 19:57:32.553749 best_step = 8
4587 19:57:32.554313
4588 19:57:32.554676 ==
4589 19:57:32.556686 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 19:57:32.559922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4591 19:57:32.560432 ==
4592 19:57:32.563460 RX Vref Scan: 0
4593 19:57:32.564006
4594 19:57:32.564444 RX Vref 0 -> 0, step: 1
4595 19:57:32.564790
4596 19:57:32.566602 RX Delay -195 -> 252, step: 8
4597 19:57:32.574052 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4598 19:57:32.577783 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4599 19:57:32.580827 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4600 19:57:32.584169 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4601 19:57:32.590897 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4602 19:57:32.593950 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4603 19:57:32.597411 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4604 19:57:32.600710 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4605 19:57:32.607749 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4606 19:57:32.610815 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4607 19:57:32.613746 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4608 19:57:32.617066 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4609 19:57:32.620522 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4610 19:57:32.626910 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4611 19:57:32.630885 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4612 19:57:32.633750 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4613 19:57:32.634313 ==
4614 19:57:32.637169 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 19:57:32.643967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4616 19:57:32.644585 ==
4617 19:57:32.644956 DQS Delay:
4618 19:57:32.645291 DQS0 = 0, DQS1 = 0
4619 19:57:32.647291 DQM Delay:
4620 19:57:32.647849 DQM0 = 37, DQM1 = 29
4621 19:57:32.650369 DQ Delay:
4622 19:57:32.653520 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4623 19:57:32.656790 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4624 19:57:32.660316 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4625 19:57:32.663704 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4626 19:57:32.664318
4627 19:57:32.664694
4628 19:57:32.669919 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4629 19:57:32.673707 CH1 RK1: MR19=808, MR18=6161
4630 19:57:32.680710 CH1_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4631 19:57:32.683594 [RxdqsGatingPostProcess] freq 600
4632 19:57:32.686861 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4633 19:57:32.690283 Pre-setting of DQS Precalculation
4634 19:57:32.696820 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4635 19:57:32.703166 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4636 19:57:32.710088 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4637 19:57:32.710654
4638 19:57:32.711015
4639 19:57:32.713130 [Calibration Summary] 1200 Mbps
4640 19:57:32.713590 CH 0, Rank 0
4641 19:57:32.716513 SW Impedance : PASS
4642 19:57:32.719986 DUTY Scan : NO K
4643 19:57:32.720494 ZQ Calibration : PASS
4644 19:57:32.723285 Jitter Meter : NO K
4645 19:57:32.726510 CBT Training : PASS
4646 19:57:32.727167 Write leveling : PASS
4647 19:57:32.729943 RX DQS gating : PASS
4648 19:57:32.733504 RX DQ/DQS(RDDQC) : PASS
4649 19:57:32.734069 TX DQ/DQS : PASS
4650 19:57:32.736589 RX DATLAT : PASS
4651 19:57:32.739762 RX DQ/DQS(Engine): PASS
4652 19:57:32.740365 TX OE : NO K
4653 19:57:32.740739 All Pass.
4654 19:57:32.741080
4655 19:57:32.743203 CH 0, Rank 1
4656 19:57:32.746607 SW Impedance : PASS
4657 19:57:32.747170 DUTY Scan : NO K
4658 19:57:32.749880 ZQ Calibration : PASS
4659 19:57:32.750440 Jitter Meter : NO K
4660 19:57:32.753167 CBT Training : PASS
4661 19:57:32.756519 Write leveling : PASS
4662 19:57:32.757083 RX DQS gating : PASS
4663 19:57:32.759506 RX DQ/DQS(RDDQC) : PASS
4664 19:57:32.763221 TX DQ/DQS : PASS
4665 19:57:32.763787 RX DATLAT : PASS
4666 19:57:32.766250 RX DQ/DQS(Engine): PASS
4667 19:57:32.769440 TX OE : NO K
4668 19:57:32.770005 All Pass.
4669 19:57:32.770371
4670 19:57:32.770708 CH 1, Rank 0
4671 19:57:32.772716 SW Impedance : PASS
4672 19:57:32.776252 DUTY Scan : NO K
4673 19:57:32.776886 ZQ Calibration : PASS
4674 19:57:32.779625 Jitter Meter : NO K
4675 19:57:32.782629 CBT Training : PASS
4676 19:57:32.783252 Write leveling : PASS
4677 19:57:32.786265 RX DQS gating : PASS
4678 19:57:32.789349 RX DQ/DQS(RDDQC) : PASS
4679 19:57:32.789910 TX DQ/DQS : PASS
4680 19:57:32.792794 RX DATLAT : PASS
4681 19:57:32.795946 RX DQ/DQS(Engine): PASS
4682 19:57:32.796565 TX OE : NO K
4683 19:57:32.796939 All Pass.
4684 19:57:32.799149
4685 19:57:32.799608 CH 1, Rank 1
4686 19:57:32.802270 SW Impedance : PASS
4687 19:57:32.802731 DUTY Scan : NO K
4688 19:57:32.805975 ZQ Calibration : PASS
4689 19:57:32.809209 Jitter Meter : NO K
4690 19:57:32.809765 CBT Training : PASS
4691 19:57:32.812462 Write leveling : PASS
4692 19:57:32.813035 RX DQS gating : PASS
4693 19:57:32.815923 RX DQ/DQS(RDDQC) : PASS
4694 19:57:32.819184 TX DQ/DQS : PASS
4695 19:57:32.819736 RX DATLAT : PASS
4696 19:57:32.822315 RX DQ/DQS(Engine): PASS
4697 19:57:32.825654 TX OE : NO K
4698 19:57:32.826122 All Pass.
4699 19:57:32.826484
4700 19:57:32.829005 DramC Write-DBI off
4701 19:57:32.829538 PER_BANK_REFRESH: Hybrid Mode
4702 19:57:32.832237 TX_TRACKING: ON
4703 19:57:32.842272 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4704 19:57:32.845420 [FAST_K] Save calibration result to emmc
4705 19:57:32.848886 dramc_set_vcore_voltage set vcore to 662500
4706 19:57:32.849448 Read voltage for 933, 3
4707 19:57:32.851964 Vio18 = 0
4708 19:57:32.852474 Vcore = 662500
4709 19:57:32.852912 Vdram = 0
4710 19:57:32.855218 Vddq = 0
4711 19:57:32.855786 Vmddr = 0
4712 19:57:32.861914 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4713 19:57:32.865418 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4714 19:57:32.869114 MEM_TYPE=3, freq_sel=17
4715 19:57:32.872321 sv_algorithm_assistance_LP4_1600
4716 19:57:32.875218 ============ PULL DRAM RESETB DOWN ============
4717 19:57:32.878326 ========== PULL DRAM RESETB DOWN end =========
4718 19:57:32.885159 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4719 19:57:32.888577 ===================================
4720 19:57:32.889039 LPDDR4 DRAM CONFIGURATION
4721 19:57:32.891613 ===================================
4722 19:57:32.894954 EX_ROW_EN[0] = 0x0
4723 19:57:32.895414 EX_ROW_EN[1] = 0x0
4724 19:57:32.898639 LP4Y_EN = 0x0
4725 19:57:32.901978 WORK_FSP = 0x0
4726 19:57:32.902534 WL = 0x3
4727 19:57:32.905485 RL = 0x3
4728 19:57:32.906076 BL = 0x2
4729 19:57:32.908496 RPST = 0x0
4730 19:57:32.908959 RD_PRE = 0x0
4731 19:57:32.911935 WR_PRE = 0x1
4732 19:57:32.912567 WR_PST = 0x0
4733 19:57:32.915348 DBI_WR = 0x0
4734 19:57:32.915911 DBI_RD = 0x0
4735 19:57:32.918177 OTF = 0x1
4736 19:57:32.921499 ===================================
4737 19:57:32.925341 ===================================
4738 19:57:32.925898 ANA top config
4739 19:57:32.928463 ===================================
4740 19:57:32.932008 DLL_ASYNC_EN = 0
4741 19:57:32.935167 ALL_SLAVE_EN = 1
4742 19:57:32.935721 NEW_RANK_MODE = 1
4743 19:57:32.938306 DLL_IDLE_MODE = 1
4744 19:57:32.941729 LP45_APHY_COMB_EN = 1
4745 19:57:32.945090 TX_ODT_DIS = 1
4746 19:57:32.948328 NEW_8X_MODE = 1
4747 19:57:32.951715 ===================================
4748 19:57:32.954932 ===================================
4749 19:57:32.955498 data_rate = 1866
4750 19:57:32.958320 CKR = 1
4751 19:57:32.961567 DQ_P2S_RATIO = 8
4752 19:57:32.965100 ===================================
4753 19:57:32.968631 CA_P2S_RATIO = 8
4754 19:57:32.971573 DQ_CA_OPEN = 0
4755 19:57:32.975135 DQ_SEMI_OPEN = 0
4756 19:57:32.975696 CA_SEMI_OPEN = 0
4757 19:57:32.978377 CA_FULL_RATE = 0
4758 19:57:32.981645 DQ_CKDIV4_EN = 1
4759 19:57:32.984734 CA_CKDIV4_EN = 1
4760 19:57:32.988345 CA_PREDIV_EN = 0
4761 19:57:32.991552 PH8_DLY = 0
4762 19:57:32.992011 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4763 19:57:32.994496 DQ_AAMCK_DIV = 4
4764 19:57:32.998032 CA_AAMCK_DIV = 4
4765 19:57:33.001238 CA_ADMCK_DIV = 4
4766 19:57:33.004548 DQ_TRACK_CA_EN = 0
4767 19:57:33.008113 CA_PICK = 933
4768 19:57:33.011279 CA_MCKIO = 933
4769 19:57:33.011741 MCKIO_SEMI = 0
4770 19:57:33.014481 PLL_FREQ = 3732
4771 19:57:33.017807 DQ_UI_PI_RATIO = 32
4772 19:57:33.021357 CA_UI_PI_RATIO = 0
4773 19:57:33.024467 ===================================
4774 19:57:33.027829 ===================================
4775 19:57:33.031304 memory_type:LPDDR4
4776 19:57:33.031867 GP_NUM : 10
4777 19:57:33.034641 SRAM_EN : 1
4778 19:57:33.037784 MD32_EN : 0
4779 19:57:33.041296 ===================================
4780 19:57:33.041867 [ANA_INIT] >>>>>>>>>>>>>>
4781 19:57:33.044485 <<<<<< [CONFIGURE PHASE]: ANA_TX
4782 19:57:33.047691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4783 19:57:33.050825 ===================================
4784 19:57:33.054423 data_rate = 1866,PCW = 0X8f00
4785 19:57:33.057424 ===================================
4786 19:57:33.060896 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4787 19:57:33.067664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4788 19:57:33.070897 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4789 19:57:33.077650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4790 19:57:33.080490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4791 19:57:33.084016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4792 19:57:33.084621 [ANA_INIT] flow start
4793 19:57:33.087030 [ANA_INIT] PLL >>>>>>>>
4794 19:57:33.090685 [ANA_INIT] PLL <<<<<<<<
4795 19:57:33.091249 [ANA_INIT] MIDPI >>>>>>>>
4796 19:57:33.094512 [ANA_INIT] MIDPI <<<<<<<<
4797 19:57:33.097337 [ANA_INIT] DLL >>>>>>>>
4798 19:57:33.097900 [ANA_INIT] flow end
4799 19:57:33.104217 ============ LP4 DIFF to SE enter ============
4800 19:57:33.107249 ============ LP4 DIFF to SE exit ============
4801 19:57:33.110753 [ANA_INIT] <<<<<<<<<<<<<
4802 19:57:33.113898 [Flow] Enable top DCM control >>>>>
4803 19:57:33.116980 [Flow] Enable top DCM control <<<<<
4804 19:57:33.120404 Enable DLL master slave shuffle
4805 19:57:33.123838 ==============================================================
4806 19:57:33.127285 Gating Mode config
4807 19:57:33.130421 ==============================================================
4808 19:57:33.133716 Config description:
4809 19:57:33.143802 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4810 19:57:33.150468 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4811 19:57:33.153338 SELPH_MODE 0: By rank 1: By Phase
4812 19:57:33.160046 ==============================================================
4813 19:57:33.163495 GAT_TRACK_EN = 1
4814 19:57:33.166648 RX_GATING_MODE = 2
4815 19:57:33.169878 RX_GATING_TRACK_MODE = 2
4816 19:57:33.173474 SELPH_MODE = 1
4817 19:57:33.176562 PICG_EARLY_EN = 1
4818 19:57:33.177027 VALID_LAT_VALUE = 1
4819 19:57:33.183319 ==============================================================
4820 19:57:33.186463 Enter into Gating configuration >>>>
4821 19:57:33.189953 Exit from Gating configuration <<<<
4822 19:57:33.193380 Enter into DVFS_PRE_config >>>>>
4823 19:57:33.203276 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4824 19:57:33.206775 Exit from DVFS_PRE_config <<<<<
4825 19:57:33.210301 Enter into PICG configuration >>>>
4826 19:57:33.213361 Exit from PICG configuration <<<<
4827 19:57:33.216671 [RX_INPUT] configuration >>>>>
4828 19:57:33.219768 [RX_INPUT] configuration <<<<<
4829 19:57:33.226293 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4830 19:57:33.229701 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4831 19:57:33.236387 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4832 19:57:33.243400 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4833 19:57:33.250378 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4834 19:57:33.256476 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4835 19:57:33.260160 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4836 19:57:33.263370 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4837 19:57:33.266618 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4838 19:57:33.272796 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4839 19:57:33.276535 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4840 19:57:33.279841 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4841 19:57:33.283390 ===================================
4842 19:57:33.286514 LPDDR4 DRAM CONFIGURATION
4843 19:57:33.289990 ===================================
4844 19:57:33.290454 EX_ROW_EN[0] = 0x0
4845 19:57:33.292921 EX_ROW_EN[1] = 0x0
4846 19:57:33.293382 LP4Y_EN = 0x0
4847 19:57:33.296347 WORK_FSP = 0x0
4848 19:57:33.296931 WL = 0x3
4849 19:57:33.299801 RL = 0x3
4850 19:57:33.302746 BL = 0x2
4851 19:57:33.303207 RPST = 0x0
4852 19:57:33.306265 RD_PRE = 0x0
4853 19:57:33.306826 WR_PRE = 0x1
4854 19:57:33.309381 WR_PST = 0x0
4855 19:57:33.309839 DBI_WR = 0x0
4856 19:57:33.312689 DBI_RD = 0x0
4857 19:57:33.313151 OTF = 0x1
4858 19:57:33.316252 ===================================
4859 19:57:33.319226 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4860 19:57:33.326031 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4861 19:57:33.329451 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 19:57:33.332637 ===================================
4863 19:57:33.335854 LPDDR4 DRAM CONFIGURATION
4864 19:57:33.339216 ===================================
4865 19:57:33.339684 EX_ROW_EN[0] = 0x10
4866 19:57:33.342747 EX_ROW_EN[1] = 0x0
4867 19:57:33.343306 LP4Y_EN = 0x0
4868 19:57:33.346140 WORK_FSP = 0x0
4869 19:57:33.346698 WL = 0x3
4870 19:57:33.349026 RL = 0x3
4871 19:57:33.352369 BL = 0x2
4872 19:57:33.352831 RPST = 0x0
4873 19:57:33.355842 RD_PRE = 0x0
4874 19:57:33.356488 WR_PRE = 0x1
4875 19:57:33.359286 WR_PST = 0x0
4876 19:57:33.359845 DBI_WR = 0x0
4877 19:57:33.362742 DBI_RD = 0x0
4878 19:57:33.363303 OTF = 0x1
4879 19:57:33.366022 ===================================
4880 19:57:33.372527 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4881 19:57:33.376859 nWR fixed to 30
4882 19:57:33.379666 [ModeRegInit_LP4] CH0 RK0
4883 19:57:33.380269 [ModeRegInit_LP4] CH0 RK1
4884 19:57:33.383037 [ModeRegInit_LP4] CH1 RK0
4885 19:57:33.386421 [ModeRegInit_LP4] CH1 RK1
4886 19:57:33.386983 match AC timing 8
4887 19:57:33.392882 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4888 19:57:33.396268 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4889 19:57:33.400315 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4890 19:57:33.405903 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4891 19:57:33.409176 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4892 19:57:33.409736 ==
4893 19:57:33.412917 Dram Type= 6, Freq= 0, CH_0, rank 0
4894 19:57:33.415911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4895 19:57:33.416517 ==
4896 19:57:33.422703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4897 19:57:33.429056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4898 19:57:33.432468 [CA 0] Center 38 (8~69) winsize 62
4899 19:57:33.435990 [CA 1] Center 38 (8~69) winsize 62
4900 19:57:33.439162 [CA 2] Center 36 (5~67) winsize 63
4901 19:57:33.442437 [CA 3] Center 35 (5~66) winsize 62
4902 19:57:33.445997 [CA 4] Center 34 (4~65) winsize 62
4903 19:57:33.448807 [CA 5] Center 34 (4~65) winsize 62
4904 19:57:33.449270
4905 19:57:33.452269 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4906 19:57:33.452731
4907 19:57:33.455738 [CATrainingPosCal] consider 1 rank data
4908 19:57:33.459347 u2DelayCellTimex100 = 270/100 ps
4909 19:57:33.462456 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4910 19:57:33.465275 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4911 19:57:33.469042 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4912 19:57:33.472365 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4913 19:57:33.475743 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4914 19:57:33.481861 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4915 19:57:33.482408
4916 19:57:33.485398 CA PerBit enable=1, Macro0, CA PI delay=34
4917 19:57:33.485959
4918 19:57:33.488611 [CBTSetCACLKResult] CA Dly = 34
4919 19:57:33.489071 CS Dly: 7 (0~38)
4920 19:57:33.489435 ==
4921 19:57:33.492325 Dram Type= 6, Freq= 0, CH_0, rank 1
4922 19:57:33.495027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4923 19:57:33.498609 ==
4924 19:57:33.501765 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4925 19:57:33.508560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4926 19:57:33.511803 [CA 0] Center 38 (8~69) winsize 62
4927 19:57:33.515033 [CA 1] Center 38 (8~69) winsize 62
4928 19:57:33.518372 [CA 2] Center 36 (5~67) winsize 63
4929 19:57:33.521617 [CA 3] Center 35 (5~66) winsize 62
4930 19:57:33.524935 [CA 4] Center 34 (4~65) winsize 62
4931 19:57:33.528348 [CA 5] Center 34 (4~65) winsize 62
4932 19:57:33.528985
4933 19:57:33.531625 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4934 19:57:33.532087
4935 19:57:33.534744 [CATrainingPosCal] consider 2 rank data
4936 19:57:33.538008 u2DelayCellTimex100 = 270/100 ps
4937 19:57:33.541616 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4938 19:57:33.544586 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4939 19:57:33.547958 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4940 19:57:33.554671 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4941 19:57:33.558199 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4942 19:57:33.561238 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4943 19:57:33.561701
4944 19:57:33.564293 CA PerBit enable=1, Macro0, CA PI delay=34
4945 19:57:33.564755
4946 19:57:33.567972 [CBTSetCACLKResult] CA Dly = 34
4947 19:57:33.568577 CS Dly: 7 (0~38)
4948 19:57:33.568943
4949 19:57:33.571119 ----->DramcWriteLeveling(PI) begin...
4950 19:57:33.574573 ==
4951 19:57:33.577718 Dram Type= 6, Freq= 0, CH_0, rank 0
4952 19:57:33.581050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4953 19:57:33.581643 ==
4954 19:57:33.584493 Write leveling (Byte 0): 27 => 27
4955 19:57:33.587741 Write leveling (Byte 1): 26 => 26
4956 19:57:33.590801 DramcWriteLeveling(PI) end<-----
4957 19:57:33.591355
4958 19:57:33.591717 ==
4959 19:57:33.594205 Dram Type= 6, Freq= 0, CH_0, rank 0
4960 19:57:33.597957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4961 19:57:33.598515 ==
4962 19:57:33.600823 [Gating] SW mode calibration
4963 19:57:33.607683 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4964 19:57:33.614147 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4965 19:57:33.617339 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4966 19:57:33.620807 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4967 19:57:33.627174 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4968 19:57:33.630295 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4969 19:57:33.634372 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4970 19:57:33.640440 0 10 20 | B1->B0 | 3131 2e2e | 1 0 | (0 0) (1 0)
4971 19:57:33.644002 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4972 19:57:33.647318 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4973 19:57:33.654086 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4974 19:57:33.657434 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4975 19:57:33.660472 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4976 19:57:33.666959 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4977 19:57:33.670526 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4978 19:57:33.673913 0 11 20 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4979 19:57:33.680401 0 11 24 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
4980 19:57:33.683602 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4981 19:57:33.686881 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4982 19:57:33.693606 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4983 19:57:33.696727 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4984 19:57:33.700496 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4985 19:57:33.703418 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4986 19:57:33.709903 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4987 19:57:33.713388 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4988 19:57:33.716559 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4989 19:57:33.723035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4990 19:57:33.726558 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4991 19:57:33.729694 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 19:57:33.736318 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4993 19:57:33.740226 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4994 19:57:33.743296 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 19:57:33.749613 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 19:57:33.753272 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 19:57:33.756266 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 19:57:33.763271 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 19:57:33.766671 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 19:57:33.769673 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 19:57:33.776333 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 19:57:33.779755 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5003 19:57:33.783145 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5004 19:57:33.786468 Total UI for P1: 0, mck2ui 16
5005 19:57:33.789646 best dqsien dly found for B0: ( 0, 14, 20)
5006 19:57:33.792901 Total UI for P1: 0, mck2ui 16
5007 19:57:33.796206 best dqsien dly found for B1: ( 0, 14, 20)
5008 19:57:33.799353 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5009 19:57:33.802794 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5010 19:57:33.803353
5011 19:57:33.809499 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5012 19:57:33.812917 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5013 19:57:33.816016 [Gating] SW calibration Done
5014 19:57:33.816621 ==
5015 19:57:33.819325 Dram Type= 6, Freq= 0, CH_0, rank 0
5016 19:57:33.822529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5017 19:57:33.822993 ==
5018 19:57:33.823361 RX Vref Scan: 0
5019 19:57:33.823698
5020 19:57:33.826130 RX Vref 0 -> 0, step: 1
5021 19:57:33.826690
5022 19:57:33.828940 RX Delay -80 -> 252, step: 8
5023 19:57:33.832579 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5024 19:57:33.835993 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5025 19:57:33.842535 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5026 19:57:33.845620 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5027 19:57:33.848857 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5028 19:57:33.852523 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5029 19:57:33.855673 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5030 19:57:33.858896 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5031 19:57:33.865826 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5032 19:57:33.869107 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5033 19:57:33.872793 iDelay=208, Bit 10, Center 83 (-8 ~ 175) 184
5034 19:57:33.875539 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5035 19:57:33.878622 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5036 19:57:33.885789 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5037 19:57:33.889043 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5038 19:57:33.892429 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5039 19:57:33.892995 ==
5040 19:57:33.895763 Dram Type= 6, Freq= 0, CH_0, rank 0
5041 19:57:33.898777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5042 19:57:33.899248 ==
5043 19:57:33.902189 DQS Delay:
5044 19:57:33.902780 DQS0 = 0, DQS1 = 0
5045 19:57:33.905574 DQM Delay:
5046 19:57:33.906031 DQM0 = 95, DQM1 = 84
5047 19:57:33.906449 DQ Delay:
5048 19:57:33.908674 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5049 19:57:33.911853 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5050 19:57:33.915878 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =83
5051 19:57:33.918791 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5052 19:57:33.919353
5053 19:57:33.919716
5054 19:57:33.921818 ==
5055 19:57:33.925412 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 19:57:33.928459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5057 19:57:33.928924 ==
5058 19:57:33.929510
5059 19:57:33.929904
5060 19:57:33.931545 TX Vref Scan disable
5061 19:57:33.931999 == TX Byte 0 ==
5062 19:57:33.934991 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5063 19:57:33.941625 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5064 19:57:33.942177 == TX Byte 1 ==
5065 19:57:33.944891 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5066 19:57:33.951725 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5067 19:57:33.952342 ==
5068 19:57:33.954979 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 19:57:33.958155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5070 19:57:33.958714 ==
5071 19:57:33.959084
5072 19:57:33.959599
5073 19:57:33.961753 TX Vref Scan disable
5074 19:57:33.964945 == TX Byte 0 ==
5075 19:57:33.968755 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5076 19:57:33.971475 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5077 19:57:33.974821 == TX Byte 1 ==
5078 19:57:33.978220 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5079 19:57:33.981706 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5080 19:57:33.982266
5081 19:57:33.984866 [DATLAT]
5082 19:57:33.985415 Freq=933, CH0 RK0
5083 19:57:33.985783
5084 19:57:33.988269 DATLAT Default: 0xd
5085 19:57:33.988945 0, 0xFFFF, sum = 0
5086 19:57:33.991278 1, 0xFFFF, sum = 0
5087 19:57:33.991747 2, 0xFFFF, sum = 0
5088 19:57:33.994792 3, 0xFFFF, sum = 0
5089 19:57:33.995355 4, 0xFFFF, sum = 0
5090 19:57:33.998097 5, 0xFFFF, sum = 0
5091 19:57:33.998660 6, 0xFFFF, sum = 0
5092 19:57:34.001131 7, 0xFFFF, sum = 0
5093 19:57:34.001597 8, 0xFFFF, sum = 0
5094 19:57:34.004680 9, 0xFFFF, sum = 0
5095 19:57:34.005247 10, 0x0, sum = 1
5096 19:57:34.007879 11, 0x0, sum = 2
5097 19:57:34.008378 12, 0x0, sum = 3
5098 19:57:34.011656 13, 0x0, sum = 4
5099 19:57:34.012251 best_step = 11
5100 19:57:34.012632
5101 19:57:34.012972 ==
5102 19:57:34.014237 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 19:57:34.021130 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5104 19:57:34.021696 ==
5105 19:57:34.022081 RX Vref Scan: 1
5106 19:57:34.022422
5107 19:57:34.024328 RX Vref 0 -> 0, step: 1
5108 19:57:34.024789
5109 19:57:34.027817 RX Delay -69 -> 252, step: 4
5110 19:57:34.028320
5111 19:57:34.030996 Set Vref, RX VrefLevel [Byte0]: 51
5112 19:57:34.034258 [Byte1]: 51
5113 19:57:34.034716
5114 19:57:34.038106 Final RX Vref Byte 0 = 51 to rank0
5115 19:57:34.040965 Final RX Vref Byte 1 = 51 to rank0
5116 19:57:34.044236 Final RX Vref Byte 0 = 51 to rank1
5117 19:57:34.047842 Final RX Vref Byte 1 = 51 to rank1==
5118 19:57:34.050948 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 19:57:34.054360 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5120 19:57:34.054921 ==
5121 19:57:34.057736 DQS Delay:
5122 19:57:34.058194 DQS0 = 0, DQS1 = 0
5123 19:57:34.058556 DQM Delay:
5124 19:57:34.060575 DQM0 = 96, DQM1 = 88
5125 19:57:34.061039 DQ Delay:
5126 19:57:34.064000 DQ0 =92, DQ1 =100, DQ2 =94, DQ3 =94
5127 19:57:34.067318 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =102
5128 19:57:34.070720 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =80
5129 19:57:34.074000 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =98
5130 19:57:34.074462
5131 19:57:34.074824
5132 19:57:34.084136 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5133 19:57:34.087057 CH0 RK0: MR19=505, MR18=1E1E
5134 19:57:34.094294 CH0_RK0: MR19=0x505, MR18=0x1E1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5135 19:57:34.094860
5136 19:57:34.097094 ----->DramcWriteLeveling(PI) begin...
5137 19:57:34.097606 ==
5138 19:57:34.100472 Dram Type= 6, Freq= 0, CH_0, rank 1
5139 19:57:34.103985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5140 19:57:34.104593 ==
5141 19:57:34.107020 Write leveling (Byte 0): 26 => 26
5142 19:57:34.110489 Write leveling (Byte 1): 25 => 25
5143 19:57:34.113693 DramcWriteLeveling(PI) end<-----
5144 19:57:34.114253
5145 19:57:34.114615 ==
5146 19:57:34.117047 Dram Type= 6, Freq= 0, CH_0, rank 1
5147 19:57:34.120140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5148 19:57:34.120631 ==
5149 19:57:34.123460 [Gating] SW mode calibration
5150 19:57:34.129953 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5151 19:57:34.136889 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5152 19:57:34.139896 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 19:57:34.143300 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 19:57:34.150230 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 19:57:34.153495 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 19:57:34.156645 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5157 19:57:34.163341 0 10 20 | B1->B0 | 2f2f 2e2e | 1 0 | (1 1) (0 0)
5158 19:57:34.166572 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5159 19:57:34.169963 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 19:57:34.177000 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 19:57:34.179743 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 19:57:34.183218 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 19:57:34.189478 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 19:57:34.193388 0 11 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5165 19:57:34.196391 0 11 20 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (1 1)
5166 19:57:34.203341 0 11 24 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
5167 19:57:34.206226 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 19:57:34.209854 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 19:57:34.216286 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 19:57:34.219546 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 19:57:34.222608 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 19:57:34.229374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 19:57:34.232488 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 19:57:34.235919 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 19:57:34.242213 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 19:57:34.245943 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 19:57:34.248965 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 19:57:34.255597 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 19:57:34.259003 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 19:57:34.262613 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 19:57:34.269150 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 19:57:34.272058 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 19:57:34.275899 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 19:57:34.282211 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 19:57:34.285664 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 19:57:34.288936 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 19:57:34.295505 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 19:57:34.298766 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 19:57:34.301963 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5190 19:57:34.308278 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5191 19:57:34.311986 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 19:57:34.314910 Total UI for P1: 0, mck2ui 16
5193 19:57:34.318257 best dqsien dly found for B0: ( 0, 14, 22)
5194 19:57:34.321614 Total UI for P1: 0, mck2ui 16
5195 19:57:34.324898 best dqsien dly found for B1: ( 0, 14, 22)
5196 19:57:34.328361 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5197 19:57:34.331386 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5198 19:57:34.331849
5199 19:57:34.334919 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5200 19:57:34.338266 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5201 19:57:34.341286 [Gating] SW calibration Done
5202 19:57:34.341749 ==
5203 19:57:34.345007 Dram Type= 6, Freq= 0, CH_0, rank 1
5204 19:57:34.351647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5205 19:57:34.352251 ==
5206 19:57:34.352633 RX Vref Scan: 0
5207 19:57:34.352974
5208 19:57:34.354419 RX Vref 0 -> 0, step: 1
5209 19:57:34.354919
5210 19:57:34.357755 RX Delay -80 -> 252, step: 8
5211 19:57:34.361306 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5212 19:57:34.364691 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5213 19:57:34.367898 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5214 19:57:34.370988 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5215 19:57:34.374676 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5216 19:57:34.381257 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5217 19:57:34.384885 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5218 19:57:34.387654 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5219 19:57:34.390945 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5220 19:57:34.394410 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5221 19:57:34.400884 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5222 19:57:34.404209 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5223 19:57:34.407282 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5224 19:57:34.410637 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5225 19:57:34.414241 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5226 19:57:34.417410 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5227 19:57:34.420428 ==
5228 19:57:34.423880 Dram Type= 6, Freq= 0, CH_0, rank 1
5229 19:57:34.427088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5230 19:57:34.427559 ==
5231 19:57:34.427924 DQS Delay:
5232 19:57:34.430355 DQS0 = 0, DQS1 = 0
5233 19:57:34.430819 DQM Delay:
5234 19:57:34.434005 DQM0 = 97, DQM1 = 87
5235 19:57:34.434562 DQ Delay:
5236 19:57:34.437495 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5237 19:57:34.440724 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =107
5238 19:57:34.443679 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =79
5239 19:57:34.447205 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5240 19:57:34.447767
5241 19:57:34.448136
5242 19:57:34.448511 ==
5243 19:57:34.450519 Dram Type= 6, Freq= 0, CH_0, rank 1
5244 19:57:34.453823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5245 19:57:34.454388 ==
5246 19:57:34.457254
5247 19:57:34.457710
5248 19:57:34.458073 TX Vref Scan disable
5249 19:57:34.460319 == TX Byte 0 ==
5250 19:57:34.464008 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5251 19:57:34.467496 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5252 19:57:34.470438 == TX Byte 1 ==
5253 19:57:34.473957 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5254 19:57:34.477060 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5255 19:57:34.477620 ==
5256 19:57:34.480566 Dram Type= 6, Freq= 0, CH_0, rank 1
5257 19:57:34.486999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5258 19:57:34.487566 ==
5259 19:57:34.487936
5260 19:57:34.488301
5261 19:57:34.488630 TX Vref Scan disable
5262 19:57:34.491113 == TX Byte 0 ==
5263 19:57:34.494645 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5264 19:57:34.501095 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5265 19:57:34.501662 == TX Byte 1 ==
5266 19:57:34.504264 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5267 19:57:34.511069 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5268 19:57:34.511629
5269 19:57:34.511991 [DATLAT]
5270 19:57:34.512448 Freq=933, CH0 RK1
5271 19:57:34.512800
5272 19:57:34.513994 DATLAT Default: 0xb
5273 19:57:34.514466 0, 0xFFFF, sum = 0
5274 19:57:34.517430 1, 0xFFFF, sum = 0
5275 19:57:34.520725 2, 0xFFFF, sum = 0
5276 19:57:34.521189 3, 0xFFFF, sum = 0
5277 19:57:34.523951 4, 0xFFFF, sum = 0
5278 19:57:34.524450 5, 0xFFFF, sum = 0
5279 19:57:34.527279 6, 0xFFFF, sum = 0
5280 19:57:34.527746 7, 0xFFFF, sum = 0
5281 19:57:34.530370 8, 0xFFFF, sum = 0
5282 19:57:34.530900 9, 0xFFFF, sum = 0
5283 19:57:34.533966 10, 0x0, sum = 1
5284 19:57:34.534588 11, 0x0, sum = 2
5285 19:57:34.536959 12, 0x0, sum = 3
5286 19:57:34.537520 13, 0x0, sum = 4
5287 19:57:34.537898 best_step = 11
5288 19:57:34.540653
5289 19:57:34.541327 ==
5290 19:57:34.543750 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 19:57:34.547429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5292 19:57:34.547997 ==
5293 19:57:34.548408 RX Vref Scan: 0
5294 19:57:34.548748
5295 19:57:34.550472 RX Vref 0 -> 0, step: 1
5296 19:57:34.551038
5297 19:57:34.553995 RX Delay -61 -> 252, step: 4
5298 19:57:34.560727 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5299 19:57:34.563677 iDelay=203, Bit 1, Center 100 (7 ~ 194) 188
5300 19:57:34.567042 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5301 19:57:34.570112 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184
5302 19:57:34.573290 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5303 19:57:34.576891 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5304 19:57:34.583385 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5305 19:57:34.586880 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5306 19:57:34.590071 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5307 19:57:34.593372 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5308 19:57:34.597088 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5309 19:57:34.603609 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5310 19:57:34.606561 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5311 19:57:34.610107 iDelay=203, Bit 13, Center 94 (3 ~ 186) 184
5312 19:57:34.613494 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5313 19:57:34.616474 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5314 19:57:34.616938 ==
5315 19:57:34.620002 Dram Type= 6, Freq= 0, CH_0, rank 1
5316 19:57:34.626671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5317 19:57:34.627223 ==
5318 19:57:34.627589 DQS Delay:
5319 19:57:34.629699 DQS0 = 0, DQS1 = 0
5320 19:57:34.630161 DQM Delay:
5321 19:57:34.630524 DQM0 = 97, DQM1 = 86
5322 19:57:34.632829 DQ Delay:
5323 19:57:34.636671 DQ0 =92, DQ1 =100, DQ2 =96, DQ3 =90
5324 19:57:34.639706 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =108
5325 19:57:34.643059 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5326 19:57:34.646244 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =94
5327 19:57:34.646788
5328 19:57:34.647154
5329 19:57:34.652776 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5330 19:57:34.656143 CH0 RK1: MR19=505, MR18=2929
5331 19:57:34.663019 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5332 19:57:34.666250 [RxdqsGatingPostProcess] freq 933
5333 19:57:34.673018 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5334 19:57:34.673568 Pre-setting of DQS Precalculation
5335 19:57:34.679368 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5336 19:57:34.679909 ==
5337 19:57:34.682899 Dram Type= 6, Freq= 0, CH_1, rank 0
5338 19:57:34.686073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5339 19:57:34.686633 ==
5340 19:57:34.693172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5341 19:57:34.699303 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5342 19:57:34.702837 [CA 0] Center 37 (6~68) winsize 63
5343 19:57:34.705803 [CA 1] Center 37 (6~68) winsize 63
5344 19:57:34.709333 [CA 2] Center 35 (5~65) winsize 61
5345 19:57:34.712882 [CA 3] Center 34 (4~65) winsize 62
5346 19:57:34.716338 [CA 4] Center 33 (2~64) winsize 63
5347 19:57:34.719228 [CA 5] Center 33 (3~64) winsize 62
5348 19:57:34.719779
5349 19:57:34.722758 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5350 19:57:34.723310
5351 19:57:34.725751 [CATrainingPosCal] consider 1 rank data
5352 19:57:34.728958 u2DelayCellTimex100 = 270/100 ps
5353 19:57:34.732211 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5354 19:57:34.735788 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5355 19:57:34.738794 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5356 19:57:34.742220 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5357 19:57:34.745939 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5358 19:57:34.749255 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5359 19:57:34.752302
5360 19:57:34.755292 CA PerBit enable=1, Macro0, CA PI delay=33
5361 19:57:34.755746
5362 19:57:34.758697 [CBTSetCACLKResult] CA Dly = 33
5363 19:57:34.759476 CS Dly: 5 (0~36)
5364 19:57:34.760146 ==
5365 19:57:34.764552 Dram Type= 6, Freq= 0, CH_1, rank 1
5366 19:57:34.765540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5367 19:57:34.768727 ==
5368 19:57:34.771845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5369 19:57:34.778716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5370 19:57:34.782106 [CA 0] Center 37 (6~68) winsize 63
5371 19:57:34.785339 [CA 1] Center 37 (6~68) winsize 63
5372 19:57:34.788734 [CA 2] Center 34 (4~65) winsize 62
5373 19:57:34.792135 [CA 3] Center 34 (4~64) winsize 61
5374 19:57:34.795631 [CA 4] Center 33 (2~64) winsize 63
5375 19:57:34.798662 [CA 5] Center 33 (2~64) winsize 63
5376 19:57:34.799080
5377 19:57:34.802326 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5378 19:57:34.802740
5379 19:57:34.804992 [CATrainingPosCal] consider 2 rank data
5380 19:57:34.808082 u2DelayCellTimex100 = 270/100 ps
5381 19:57:34.812038 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5382 19:57:34.815036 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5383 19:57:34.818309 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5384 19:57:34.821912 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5385 19:57:34.828513 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5386 19:57:34.831575 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5387 19:57:34.832029
5388 19:57:34.835276 CA PerBit enable=1, Macro0, CA PI delay=33
5389 19:57:34.835822
5390 19:57:34.838626 [CBTSetCACLKResult] CA Dly = 33
5391 19:57:34.839217 CS Dly: 6 (0~38)
5392 19:57:34.839586
5393 19:57:34.841730 ----->DramcWriteLeveling(PI) begin...
5394 19:57:34.842228 ==
5395 19:57:34.844796 Dram Type= 6, Freq= 0, CH_1, rank 0
5396 19:57:34.851974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5397 19:57:34.852565 ==
5398 19:57:34.855148 Write leveling (Byte 0): 23 => 23
5399 19:57:34.855697 Write leveling (Byte 1): 26 => 26
5400 19:57:34.858425 DramcWriteLeveling(PI) end<-----
5401 19:57:34.858984
5402 19:57:34.862009 ==
5403 19:57:34.862556 Dram Type= 6, Freq= 0, CH_1, rank 0
5404 19:57:34.868295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5405 19:57:34.868849 ==
5406 19:57:34.871857 [Gating] SW mode calibration
5407 19:57:34.878427 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5408 19:57:34.882027 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5409 19:57:34.888666 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 19:57:34.891730 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 19:57:34.895135 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 19:57:34.901759 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5413 19:57:34.905138 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5414 19:57:34.908347 0 10 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
5415 19:57:34.914979 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5416 19:57:34.918195 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 19:57:34.921515 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 19:57:34.928082 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 19:57:34.931334 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 19:57:34.934681 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5421 19:57:34.941410 0 11 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5422 19:57:34.944469 0 11 20 | B1->B0 | 2a2a 4545 | 0 0 | (0 0) (0 0)
5423 19:57:34.948123 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5424 19:57:34.954711 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 19:57:34.957654 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 19:57:34.961568 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 19:57:34.964433 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 19:57:34.971510 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 19:57:34.974705 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5430 19:57:34.977877 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5431 19:57:34.984751 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5432 19:57:34.987796 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 19:57:34.991496 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 19:57:34.997931 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 19:57:35.001287 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 19:57:35.004738 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 19:57:35.010830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 19:57:35.013993 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 19:57:35.017864 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 19:57:35.024349 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 19:57:35.027507 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 19:57:35.030748 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 19:57:35.037634 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 19:57:35.040552 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 19:57:35.044102 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5446 19:57:35.051286 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5447 19:57:35.051841 Total UI for P1: 0, mck2ui 16
5448 19:57:35.057675 best dqsien dly found for B0: ( 0, 14, 16)
5449 19:57:35.058234 Total UI for P1: 0, mck2ui 16
5450 19:57:35.064311 best dqsien dly found for B1: ( 0, 14, 16)
5451 19:57:35.067545 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5452 19:57:35.070875 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5453 19:57:35.071427
5454 19:57:35.074218 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5455 19:57:35.077760 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5456 19:57:35.080649 [Gating] SW calibration Done
5457 19:57:35.081201 ==
5458 19:57:35.084002 Dram Type= 6, Freq= 0, CH_1, rank 0
5459 19:57:35.087113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5460 19:57:35.087664 ==
5461 19:57:35.090762 RX Vref Scan: 0
5462 19:57:35.091312
5463 19:57:35.091679 RX Vref 0 -> 0, step: 1
5464 19:57:35.092020
5465 19:57:35.093892 RX Delay -80 -> 252, step: 8
5466 19:57:35.097330 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5467 19:57:35.103822 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5468 19:57:35.107242 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5469 19:57:35.110557 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5470 19:57:35.113607 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5471 19:57:35.117234 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5472 19:57:35.123857 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5473 19:57:35.126989 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5474 19:57:35.130272 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5475 19:57:35.133457 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5476 19:57:35.136845 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5477 19:57:35.144065 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5478 19:57:35.147215 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5479 19:57:35.150324 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5480 19:57:35.153468 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5481 19:57:35.156893 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5482 19:57:35.157445 ==
5483 19:57:35.160082 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 19:57:35.167041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5485 19:57:35.167589 ==
5486 19:57:35.167953 DQS Delay:
5487 19:57:35.170219 DQS0 = 0, DQS1 = 0
5488 19:57:35.170780 DQM Delay:
5489 19:57:35.171145 DQM0 = 95, DQM1 = 87
5490 19:57:35.173667 DQ Delay:
5491 19:57:35.177035 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5492 19:57:35.180355 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =95
5493 19:57:35.183506 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5494 19:57:35.186473 DQ12 =91, DQ13 =99, DQ14 =91, DQ15 =95
5495 19:57:35.186926
5496 19:57:35.187279
5497 19:57:35.187606 ==
5498 19:57:35.189933 Dram Type= 6, Freq= 0, CH_1, rank 0
5499 19:57:35.192984 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5500 19:57:35.193440 ==
5501 19:57:35.193801
5502 19:57:35.194132
5503 19:57:35.196892 TX Vref Scan disable
5504 19:57:35.200050 == TX Byte 0 ==
5505 19:57:35.203040 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5506 19:57:35.206472 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5507 19:57:35.209651 == TX Byte 1 ==
5508 19:57:35.213401 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5509 19:57:35.216887 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5510 19:57:35.217564 ==
5511 19:57:35.220000 Dram Type= 6, Freq= 0, CH_1, rank 0
5512 19:57:35.223439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5513 19:57:35.224003 ==
5514 19:57:35.224421
5515 19:57:35.226796
5516 19:57:35.227351 TX Vref Scan disable
5517 19:57:35.229638 == TX Byte 0 ==
5518 19:57:35.233060 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5519 19:57:35.236738 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5520 19:57:35.239616 == TX Byte 1 ==
5521 19:57:35.242966 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5522 19:57:35.250011 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5523 19:57:35.250574
5524 19:57:35.250937 [DATLAT]
5525 19:57:35.251276 Freq=933, CH1 RK0
5526 19:57:35.251602
5527 19:57:35.252945 DATLAT Default: 0xd
5528 19:57:35.253400 0, 0xFFFF, sum = 0
5529 19:57:35.256344 1, 0xFFFF, sum = 0
5530 19:57:35.256909 2, 0xFFFF, sum = 0
5531 19:57:35.259848 3, 0xFFFF, sum = 0
5532 19:57:35.260455 4, 0xFFFF, sum = 0
5533 19:57:35.262995 5, 0xFFFF, sum = 0
5534 19:57:35.266651 6, 0xFFFF, sum = 0
5535 19:57:35.267220 7, 0xFFFF, sum = 0
5536 19:57:35.269830 8, 0xFFFF, sum = 0
5537 19:57:35.270393 9, 0xFFFF, sum = 0
5538 19:57:35.273117 10, 0x0, sum = 1
5539 19:57:35.273700 11, 0x0, sum = 2
5540 19:57:35.276264 12, 0x0, sum = 3
5541 19:57:35.276733 13, 0x0, sum = 4
5542 19:57:35.277198 best_step = 11
5543 19:57:35.277542
5544 19:57:35.279613 ==
5545 19:57:35.282817 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 19:57:35.286350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5547 19:57:35.286913 ==
5548 19:57:35.287281 RX Vref Scan: 1
5549 19:57:35.287619
5550 19:57:35.289554 RX Vref 0 -> 0, step: 1
5551 19:57:35.290117
5552 19:57:35.292880 RX Delay -69 -> 252, step: 4
5553 19:57:35.293620
5554 19:57:35.295859 Set Vref, RX VrefLevel [Byte0]: 53
5555 19:57:35.299328 [Byte1]: 50
5556 19:57:35.299891
5557 19:57:35.302969 Final RX Vref Byte 0 = 53 to rank0
5558 19:57:35.306325 Final RX Vref Byte 1 = 50 to rank0
5559 19:57:35.309301 Final RX Vref Byte 0 = 53 to rank1
5560 19:57:35.312424 Final RX Vref Byte 1 = 50 to rank1==
5561 19:57:35.315908 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 19:57:35.319273 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5563 19:57:35.322466 ==
5564 19:57:35.322931 DQS Delay:
5565 19:57:35.323295 DQS0 = 0, DQS1 = 0
5566 19:57:35.325861 DQM Delay:
5567 19:57:35.326480 DQM0 = 94, DQM1 = 88
5568 19:57:35.329237 DQ Delay:
5569 19:57:35.332718 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5570 19:57:35.335961 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5571 19:57:35.336604 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5572 19:57:35.342341 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5573 19:57:35.342799
5574 19:57:35.343270
5575 19:57:35.349070 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5576 19:57:35.352259 CH1 RK0: MR19=505, MR18=3232
5577 19:57:35.358903 CH1_RK0: MR19=0x505, MR18=0x3232, DQSOSC=406, MR23=63, INC=65, DEC=43
5578 19:57:35.359463
5579 19:57:35.362197 ----->DramcWriteLeveling(PI) begin...
5580 19:57:35.362764 ==
5581 19:57:35.365170 Dram Type= 6, Freq= 0, CH_1, rank 1
5582 19:57:35.368863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5583 19:57:35.369428 ==
5584 19:57:35.372413 Write leveling (Byte 0): 25 => 25
5585 19:57:35.375673 Write leveling (Byte 1): 24 => 24
5586 19:57:35.378526 DramcWriteLeveling(PI) end<-----
5587 19:57:35.379083
5588 19:57:35.379445 ==
5589 19:57:35.381784 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 19:57:35.385435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5591 19:57:35.386002 ==
5592 19:57:35.388836 [Gating] SW mode calibration
5593 19:57:35.395205 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5594 19:57:35.401938 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5595 19:57:35.405074 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 19:57:35.411729 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 19:57:35.414892 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 19:57:35.418372 0 10 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5599 19:57:35.425048 0 10 16 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
5600 19:57:35.428447 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5601 19:57:35.431695 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 19:57:35.438246 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 19:57:35.441270 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 19:57:35.444783 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 19:57:35.451481 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 19:57:35.454608 0 11 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5607 19:57:35.458140 0 11 16 | B1->B0 | 2525 3e3e | 0 0 | (0 0) (1 1)
5608 19:57:35.465069 0 11 20 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
5609 19:57:35.468149 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 19:57:35.471424 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 19:57:35.477614 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 19:57:35.480901 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 19:57:35.484857 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 19:57:35.491243 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5615 19:57:35.494411 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5616 19:57:35.497859 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5617 19:57:35.504564 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 19:57:35.507579 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 19:57:35.510670 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 19:57:35.517558 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 19:57:35.520475 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 19:57:35.524337 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 19:57:35.530218 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 19:57:35.533717 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 19:57:35.536976 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 19:57:35.543628 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 19:57:35.547323 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 19:57:35.550135 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 19:57:35.553861 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 19:57:35.560313 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 19:57:35.563825 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5632 19:57:35.567317 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5633 19:57:35.570355 Total UI for P1: 0, mck2ui 16
5634 19:57:35.573724 best dqsien dly found for B0: ( 0, 14, 16)
5635 19:57:35.580218 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 19:57:35.583714 Total UI for P1: 0, mck2ui 16
5637 19:57:35.586874 best dqsien dly found for B1: ( 0, 14, 20)
5638 19:57:35.589997 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5639 19:57:35.593267 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5640 19:57:35.593859
5641 19:57:35.596923 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5642 19:57:35.600197 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5643 19:57:35.603280 [Gating] SW calibration Done
5644 19:57:35.603844 ==
5645 19:57:35.606875 Dram Type= 6, Freq= 0, CH_1, rank 1
5646 19:57:35.609862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5647 19:57:35.610324 ==
5648 19:57:35.613275 RX Vref Scan: 0
5649 19:57:35.613836
5650 19:57:35.616567 RX Vref 0 -> 0, step: 1
5651 19:57:35.617129
5652 19:57:35.617496 RX Delay -80 -> 252, step: 8
5653 19:57:35.623390 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5654 19:57:35.626811 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5655 19:57:35.630211 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5656 19:57:35.633013 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5657 19:57:35.636373 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5658 19:57:35.642766 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5659 19:57:35.646268 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5660 19:57:35.649397 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5661 19:57:35.652762 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5662 19:57:35.656278 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5663 19:57:35.659728 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5664 19:57:35.666041 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5665 19:57:35.669268 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5666 19:57:35.672880 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5667 19:57:35.676027 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5668 19:57:35.679103 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5669 19:57:35.682484 ==
5670 19:57:35.685874 Dram Type= 6, Freq= 0, CH_1, rank 1
5671 19:57:35.689182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5672 19:57:35.689645 ==
5673 19:57:35.690050 DQS Delay:
5674 19:57:35.692903 DQS0 = 0, DQS1 = 0
5675 19:57:35.693466 DQM Delay:
5676 19:57:35.695991 DQM0 = 97, DQM1 = 88
5677 19:57:35.696598 DQ Delay:
5678 19:57:35.698975 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5679 19:57:35.702905 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =91
5680 19:57:35.705919 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5681 19:57:35.709135 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =95
5682 19:57:35.709691
5683 19:57:35.710055
5684 19:57:35.710392 ==
5685 19:57:35.712132 Dram Type= 6, Freq= 0, CH_1, rank 1
5686 19:57:35.715874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5687 19:57:35.716399 ==
5688 19:57:35.716883
5689 19:57:35.718760
5690 19:57:35.719233 TX Vref Scan disable
5691 19:57:35.722119 == TX Byte 0 ==
5692 19:57:35.725489 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5693 19:57:35.728999 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5694 19:57:35.732143 == TX Byte 1 ==
5695 19:57:35.735555 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5696 19:57:35.738730 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5697 19:57:35.739210 ==
5698 19:57:35.742103 Dram Type= 6, Freq= 0, CH_1, rank 1
5699 19:57:35.748501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5700 19:57:35.748981 ==
5701 19:57:35.749466
5702 19:57:35.749920
5703 19:57:35.750363 TX Vref Scan disable
5704 19:57:35.752647 == TX Byte 0 ==
5705 19:57:35.755823 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5706 19:57:35.762838 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5707 19:57:35.763418 == TX Byte 1 ==
5708 19:57:35.765961 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5709 19:57:35.772590 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5710 19:57:35.773170
5711 19:57:35.773666 [DATLAT]
5712 19:57:35.774125 Freq=933, CH1 RK1
5713 19:57:35.774576
5714 19:57:35.776026 DATLAT Default: 0xb
5715 19:57:35.776548 0, 0xFFFF, sum = 0
5716 19:57:35.779421 1, 0xFFFF, sum = 0
5717 19:57:35.779898 2, 0xFFFF, sum = 0
5718 19:57:35.782739 3, 0xFFFF, sum = 0
5719 19:57:35.786037 4, 0xFFFF, sum = 0
5720 19:57:35.786619 5, 0xFFFF, sum = 0
5721 19:57:35.789273 6, 0xFFFF, sum = 0
5722 19:57:35.789757 7, 0xFFFF, sum = 0
5723 19:57:35.792660 8, 0xFFFF, sum = 0
5724 19:57:35.793144 9, 0xFFFF, sum = 0
5725 19:57:35.795879 10, 0x0, sum = 1
5726 19:57:35.796402 11, 0x0, sum = 2
5727 19:57:35.799183 12, 0x0, sum = 3
5728 19:57:35.799760 13, 0x0, sum = 4
5729 19:57:35.800367 best_step = 11
5730 19:57:35.800829
5731 19:57:35.802336 ==
5732 19:57:35.806265 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 19:57:35.809311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5734 19:57:35.809894 ==
5735 19:57:35.810391 RX Vref Scan: 0
5736 19:57:35.810857
5737 19:57:35.812571 RX Vref 0 -> 0, step: 1
5738 19:57:35.813045
5739 19:57:35.816143 RX Delay -77 -> 252, step: 4
5740 19:57:35.819503 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5741 19:57:35.825912 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5742 19:57:35.829056 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5743 19:57:35.832497 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5744 19:57:35.835455 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5745 19:57:35.839073 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5746 19:57:35.845830 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5747 19:57:35.848994 iDelay=203, Bit 7, Center 96 (3 ~ 190) 188
5748 19:57:35.852585 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5749 19:57:35.855756 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5750 19:57:35.859092 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5751 19:57:35.862294 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5752 19:57:35.868927 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5753 19:57:35.872258 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5754 19:57:35.875654 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5755 19:57:35.878479 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5756 19:57:35.878954 ==
5757 19:57:35.882095 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 19:57:35.885194 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5759 19:57:35.888752 ==
5760 19:57:35.889313 DQS Delay:
5761 19:57:35.889677 DQS0 = 0, DQS1 = 0
5762 19:57:35.891700 DQM Delay:
5763 19:57:35.892156 DQM0 = 96, DQM1 = 88
5764 19:57:35.895069 DQ Delay:
5765 19:57:35.898586 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5766 19:57:35.901737 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =96
5767 19:57:35.902201 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =82
5768 19:57:35.908550 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =94
5769 19:57:35.909112
5770 19:57:35.909706
5771 19:57:35.915670 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5772 19:57:35.918466 CH1 RK1: MR19=505, MR18=2323
5773 19:57:35.925297 CH1_RK1: MR19=0x505, MR18=0x2323, DQSOSC=410, MR23=63, INC=64, DEC=42
5774 19:57:35.928641 [RxdqsGatingPostProcess] freq 933
5775 19:57:35.931746 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5776 19:57:35.934801 Pre-setting of DQS Precalculation
5777 19:57:35.941328 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5778 19:57:35.948346 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5779 19:57:35.954750 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5780 19:57:35.955305
5781 19:57:35.955674
5782 19:57:35.958102 [Calibration Summary] 1866 Mbps
5783 19:57:35.958655 CH 0, Rank 0
5784 19:57:35.961190 SW Impedance : PASS
5785 19:57:35.964889 DUTY Scan : NO K
5786 19:57:35.965442 ZQ Calibration : PASS
5787 19:57:35.968143 Jitter Meter : NO K
5788 19:57:35.971303 CBT Training : PASS
5789 19:57:35.972027 Write leveling : PASS
5790 19:57:35.974651 RX DQS gating : PASS
5791 19:57:35.977630 RX DQ/DQS(RDDQC) : PASS
5792 19:57:35.978327 TX DQ/DQS : PASS
5793 19:57:35.981123 RX DATLAT : PASS
5794 19:57:35.984566 RX DQ/DQS(Engine): PASS
5795 19:57:35.985026 TX OE : NO K
5796 19:57:35.985390 All Pass.
5797 19:57:35.987975
5798 19:57:35.988578 CH 0, Rank 1
5799 19:57:35.991520 SW Impedance : PASS
5800 19:57:35.992081 DUTY Scan : NO K
5801 19:57:35.994489 ZQ Calibration : PASS
5802 19:57:35.997890 Jitter Meter : NO K
5803 19:57:35.998452 CBT Training : PASS
5804 19:57:36.000892 Write leveling : PASS
5805 19:57:36.001349 RX DQS gating : PASS
5806 19:57:36.004114 RX DQ/DQS(RDDQC) : PASS
5807 19:57:36.007707 TX DQ/DQS : PASS
5808 19:57:36.008335 RX DATLAT : PASS
5809 19:57:36.010866 RX DQ/DQS(Engine): PASS
5810 19:57:36.014294 TX OE : NO K
5811 19:57:36.014859 All Pass.
5812 19:57:36.015224
5813 19:57:36.015559 CH 1, Rank 0
5814 19:57:36.017492 SW Impedance : PASS
5815 19:57:36.021112 DUTY Scan : NO K
5816 19:57:36.021572 ZQ Calibration : PASS
5817 19:57:36.024123 Jitter Meter : NO K
5818 19:57:36.027735 CBT Training : PASS
5819 19:57:36.028361 Write leveling : PASS
5820 19:57:36.030991 RX DQS gating : PASS
5821 19:57:36.034061 RX DQ/DQS(RDDQC) : PASS
5822 19:57:36.034522 TX DQ/DQS : PASS
5823 19:57:36.037245 RX DATLAT : PASS
5824 19:57:36.041017 RX DQ/DQS(Engine): PASS
5825 19:57:36.041575 TX OE : NO K
5826 19:57:36.044161 All Pass.
5827 19:57:36.044709
5828 19:57:36.045075 CH 1, Rank 1
5829 19:57:36.047381 SW Impedance : PASS
5830 19:57:36.047837 DUTY Scan : NO K
5831 19:57:36.050562 ZQ Calibration : PASS
5832 19:57:36.054147 Jitter Meter : NO K
5833 19:57:36.054609 CBT Training : PASS
5834 19:57:36.057632 Write leveling : PASS
5835 19:57:36.058197 RX DQS gating : PASS
5836 19:57:36.060725 RX DQ/DQS(RDDQC) : PASS
5837 19:57:36.064424 TX DQ/DQS : PASS
5838 19:57:36.064988 RX DATLAT : PASS
5839 19:57:36.067168 RX DQ/DQS(Engine): PASS
5840 19:57:36.070765 TX OE : NO K
5841 19:57:36.071327 All Pass.
5842 19:57:36.071696
5843 19:57:36.074205 DramC Write-DBI off
5844 19:57:36.074766 PER_BANK_REFRESH: Hybrid Mode
5845 19:57:36.077327 TX_TRACKING: ON
5846 19:57:36.087453 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5847 19:57:36.090776 [FAST_K] Save calibration result to emmc
5848 19:57:36.094144 dramc_set_vcore_voltage set vcore to 650000
5849 19:57:36.094706 Read voltage for 400, 6
5850 19:57:36.097465 Vio18 = 0
5851 19:57:36.098030 Vcore = 650000
5852 19:57:36.098396 Vdram = 0
5853 19:57:36.100707 Vddq = 0
5854 19:57:36.101267 Vmddr = 0
5855 19:57:36.103516 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5856 19:57:36.110593 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5857 19:57:36.114046 MEM_TYPE=3, freq_sel=20
5858 19:57:36.116973 sv_algorithm_assistance_LP4_800
5859 19:57:36.120420 ============ PULL DRAM RESETB DOWN ============
5860 19:57:36.124218 ========== PULL DRAM RESETB DOWN end =========
5861 19:57:36.131039 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5862 19:57:36.131607 ===================================
5863 19:57:36.133675 LPDDR4 DRAM CONFIGURATION
5864 19:57:36.136927 ===================================
5865 19:57:36.140627 EX_ROW_EN[0] = 0x0
5866 19:57:36.141087 EX_ROW_EN[1] = 0x0
5867 19:57:36.143792 LP4Y_EN = 0x0
5868 19:57:36.144305 WORK_FSP = 0x0
5869 19:57:36.146876 WL = 0x2
5870 19:57:36.147334 RL = 0x2
5871 19:57:36.150585 BL = 0x2
5872 19:57:36.153664 RPST = 0x0
5873 19:57:36.154121 RD_PRE = 0x0
5874 19:57:36.157041 WR_PRE = 0x1
5875 19:57:36.157499 WR_PST = 0x0
5876 19:57:36.160274 DBI_WR = 0x0
5877 19:57:36.160733 DBI_RD = 0x0
5878 19:57:36.163888 OTF = 0x1
5879 19:57:36.166757 ===================================
5880 19:57:36.170568 ===================================
5881 19:57:36.171131 ANA top config
5882 19:57:36.173976 ===================================
5883 19:57:36.176921 DLL_ASYNC_EN = 0
5884 19:57:36.180385 ALL_SLAVE_EN = 1
5885 19:57:36.180938 NEW_RANK_MODE = 1
5886 19:57:36.183697 DLL_IDLE_MODE = 1
5887 19:57:36.186914 LP45_APHY_COMB_EN = 1
5888 19:57:36.190171 TX_ODT_DIS = 1
5889 19:57:36.190736 NEW_8X_MODE = 1
5890 19:57:36.193629 ===================================
5891 19:57:36.196779 ===================================
5892 19:57:36.200211 data_rate = 800
5893 19:57:36.203510 CKR = 1
5894 19:57:36.206771 DQ_P2S_RATIO = 4
5895 19:57:36.210221 ===================================
5896 19:57:36.213023 CA_P2S_RATIO = 4
5897 19:57:36.216964 DQ_CA_OPEN = 0
5898 19:57:36.219802 DQ_SEMI_OPEN = 1
5899 19:57:36.220392 CA_SEMI_OPEN = 1
5900 19:57:36.223130 CA_FULL_RATE = 0
5901 19:57:36.226275 DQ_CKDIV4_EN = 0
5902 19:57:36.229720 CA_CKDIV4_EN = 1
5903 19:57:36.233001 CA_PREDIV_EN = 0
5904 19:57:36.236521 PH8_DLY = 0
5905 19:57:36.236976 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5906 19:57:36.239877 DQ_AAMCK_DIV = 0
5907 19:57:36.243317 CA_AAMCK_DIV = 0
5908 19:57:36.246376 CA_ADMCK_DIV = 4
5909 19:57:36.250125 DQ_TRACK_CA_EN = 0
5910 19:57:36.253731 CA_PICK = 800
5911 19:57:36.254192 CA_MCKIO = 400
5912 19:57:36.256294 MCKIO_SEMI = 400
5913 19:57:36.259583 PLL_FREQ = 3016
5914 19:57:36.263052 DQ_UI_PI_RATIO = 32
5915 19:57:36.266180 CA_UI_PI_RATIO = 32
5916 19:57:36.269560 ===================================
5917 19:57:36.273112 ===================================
5918 19:57:36.275846 memory_type:LPDDR4
5919 19:57:36.276342 GP_NUM : 10
5920 19:57:36.279598 SRAM_EN : 1
5921 19:57:36.282971 MD32_EN : 0
5922 19:57:36.286369 ===================================
5923 19:57:36.286932 [ANA_INIT] >>>>>>>>>>>>>>
5924 19:57:36.289158 <<<<<< [CONFIGURE PHASE]: ANA_TX
5925 19:57:36.292786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5926 19:57:36.296048 ===================================
5927 19:57:36.299534 data_rate = 800,PCW = 0X7400
5928 19:57:36.302717 ===================================
5929 19:57:36.305953 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5930 19:57:36.312560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5931 19:57:36.322811 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5932 19:57:36.329760 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5933 19:57:36.332260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5934 19:57:36.335719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5935 19:57:36.336208 [ANA_INIT] flow start
5936 19:57:36.339119 [ANA_INIT] PLL >>>>>>>>
5937 19:57:36.342503 [ANA_INIT] PLL <<<<<<<<
5938 19:57:36.342964 [ANA_INIT] MIDPI >>>>>>>>
5939 19:57:36.345900 [ANA_INIT] MIDPI <<<<<<<<
5940 19:57:36.348923 [ANA_INIT] DLL >>>>>>>>
5941 19:57:36.349402 [ANA_INIT] flow end
5942 19:57:36.355519 ============ LP4 DIFF to SE enter ============
5943 19:57:36.358781 ============ LP4 DIFF to SE exit ============
5944 19:57:36.359245 [ANA_INIT] <<<<<<<<<<<<<
5945 19:57:36.362496 [Flow] Enable top DCM control >>>>>
5946 19:57:36.365566 [Flow] Enable top DCM control <<<<<
5947 19:57:36.368723 Enable DLL master slave shuffle
5948 19:57:36.375650 ==============================================================
5949 19:57:36.378749 Gating Mode config
5950 19:57:36.382378 ==============================================================
5951 19:57:36.385811 Config description:
5952 19:57:36.395286 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5953 19:57:36.402043 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5954 19:57:36.405724 SELPH_MODE 0: By rank 1: By Phase
5955 19:57:36.412101 ==============================================================
5956 19:57:36.415190 GAT_TRACK_EN = 0
5957 19:57:36.418526 RX_GATING_MODE = 2
5958 19:57:36.421739 RX_GATING_TRACK_MODE = 2
5959 19:57:36.422199 SELPH_MODE = 1
5960 19:57:36.425285 PICG_EARLY_EN = 1
5961 19:57:36.428478 VALID_LAT_VALUE = 1
5962 19:57:36.435282 ==============================================================
5963 19:57:36.438228 Enter into Gating configuration >>>>
5964 19:57:36.441703 Exit from Gating configuration <<<<
5965 19:57:36.444746 Enter into DVFS_PRE_config >>>>>
5966 19:57:36.455037 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5967 19:57:36.458428 Exit from DVFS_PRE_config <<<<<
5968 19:57:36.461733 Enter into PICG configuration >>>>
5969 19:57:36.464950 Exit from PICG configuration <<<<
5970 19:57:36.468098 [RX_INPUT] configuration >>>>>
5971 19:57:36.471572 [RX_INPUT] configuration <<<<<
5972 19:57:36.474830 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5973 19:57:36.481828 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5974 19:57:36.488570 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5975 19:57:36.495296 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5976 19:57:36.501576 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5977 19:57:36.505026 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5978 19:57:36.511557 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5979 19:57:36.514661 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5980 19:57:36.517778 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5981 19:57:36.521487 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5982 19:57:36.524738 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5983 19:57:36.531167 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5984 19:57:36.534486 ===================================
5985 19:57:36.538339 LPDDR4 DRAM CONFIGURATION
5986 19:57:36.541663 ===================================
5987 19:57:36.542234 EX_ROW_EN[0] = 0x0
5988 19:57:36.544710 EX_ROW_EN[1] = 0x0
5989 19:57:36.545403 LP4Y_EN = 0x0
5990 19:57:36.548087 WORK_FSP = 0x0
5991 19:57:36.548617 WL = 0x2
5992 19:57:36.551078 RL = 0x2
5993 19:57:36.551527 BL = 0x2
5994 19:57:36.554433 RPST = 0x0
5995 19:57:36.554887 RD_PRE = 0x0
5996 19:57:36.557727 WR_PRE = 0x1
5997 19:57:36.558182 WR_PST = 0x0
5998 19:57:36.561253 DBI_WR = 0x0
5999 19:57:36.561741 DBI_RD = 0x0
6000 19:57:36.564245 OTF = 0x1
6001 19:57:36.567721 ===================================
6002 19:57:36.571302 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6003 19:57:36.574781 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6004 19:57:36.581405 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6005 19:57:36.584560 ===================================
6006 19:57:36.585133 LPDDR4 DRAM CONFIGURATION
6007 19:57:36.587790 ===================================
6008 19:57:36.591251 EX_ROW_EN[0] = 0x10
6009 19:57:36.594669 EX_ROW_EN[1] = 0x0
6010 19:57:36.595278 LP4Y_EN = 0x0
6011 19:57:36.597990 WORK_FSP = 0x0
6012 19:57:36.598689 WL = 0x2
6013 19:57:36.601020 RL = 0x2
6014 19:57:36.601471 BL = 0x2
6015 19:57:36.604292 RPST = 0x0
6016 19:57:36.604744 RD_PRE = 0x0
6017 19:57:36.607978 WR_PRE = 0x1
6018 19:57:36.608579 WR_PST = 0x0
6019 19:57:36.611241 DBI_WR = 0x0
6020 19:57:36.611790 DBI_RD = 0x0
6021 19:57:36.614346 OTF = 0x1
6022 19:57:36.617876 ===================================
6023 19:57:36.624381 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6024 19:57:36.627646 nWR fixed to 30
6025 19:57:36.630934 [ModeRegInit_LP4] CH0 RK0
6026 19:57:36.631486 [ModeRegInit_LP4] CH0 RK1
6027 19:57:36.634070 [ModeRegInit_LP4] CH1 RK0
6028 19:57:36.637470 [ModeRegInit_LP4] CH1 RK1
6029 19:57:36.637936 match AC timing 18
6030 19:57:36.644009 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6031 19:57:36.647415 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6032 19:57:36.650892 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6033 19:57:36.657728 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6034 19:57:36.661080 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6035 19:57:36.661641 ==
6036 19:57:36.664034 Dram Type= 6, Freq= 0, CH_0, rank 0
6037 19:57:36.667351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6038 19:57:36.667830 ==
6039 19:57:36.674421 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6040 19:57:36.680828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6041 19:57:36.684118 [CA 0] Center 36 (8~64) winsize 57
6042 19:57:36.687452 [CA 1] Center 36 (8~64) winsize 57
6043 19:57:36.688015 [CA 2] Center 36 (8~64) winsize 57
6044 19:57:36.690819 [CA 3] Center 36 (8~64) winsize 57
6045 19:57:36.694105 [CA 4] Center 36 (8~64) winsize 57
6046 19:57:36.697352 [CA 5] Center 36 (8~64) winsize 57
6047 19:57:36.697973
6048 19:57:36.700659 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6049 19:57:36.701119
6050 19:57:36.707405 [CATrainingPosCal] consider 1 rank data
6051 19:57:36.707974 u2DelayCellTimex100 = 270/100 ps
6052 19:57:36.710909 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6053 19:57:36.717420 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6054 19:57:36.720765 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6055 19:57:36.723887 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6056 19:57:36.727428 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6057 19:57:36.730731 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6058 19:57:36.731298
6059 19:57:36.734108 CA PerBit enable=1, Macro0, CA PI delay=36
6060 19:57:36.734567
6061 19:57:36.737325 [CBTSetCACLKResult] CA Dly = 36
6062 19:57:36.737787 CS Dly: 1 (0~32)
6063 19:57:36.740760 ==
6064 19:57:36.743721 Dram Type= 6, Freq= 0, CH_0, rank 1
6065 19:57:36.747466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6066 19:57:36.747931 ==
6067 19:57:36.750822 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6068 19:57:36.757586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6069 19:57:36.760683 [CA 0] Center 36 (8~64) winsize 57
6070 19:57:36.764034 [CA 1] Center 36 (8~64) winsize 57
6071 19:57:36.767531 [CA 2] Center 36 (8~64) winsize 57
6072 19:57:36.770530 [CA 3] Center 36 (8~64) winsize 57
6073 19:57:36.773948 [CA 4] Center 36 (8~64) winsize 57
6074 19:57:36.776946 [CA 5] Center 36 (8~64) winsize 57
6075 19:57:36.777409
6076 19:57:36.780615 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6077 19:57:36.781192
6078 19:57:36.783914 [CATrainingPosCal] consider 2 rank data
6079 19:57:36.786975 u2DelayCellTimex100 = 270/100 ps
6080 19:57:36.790355 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6081 19:57:36.793790 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6082 19:57:36.797313 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6083 19:57:36.800332 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6084 19:57:36.806866 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6085 19:57:36.810192 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6086 19:57:36.810656
6087 19:57:36.813472 CA PerBit enable=1, Macro0, CA PI delay=36
6088 19:57:36.813966
6089 19:57:36.817056 [CBTSetCACLKResult] CA Dly = 36
6090 19:57:36.817620 CS Dly: 1 (0~32)
6091 19:57:36.817986
6092 19:57:36.820063 ----->DramcWriteLeveling(PI) begin...
6093 19:57:36.820560 ==
6094 19:57:36.823418 Dram Type= 6, Freq= 0, CH_0, rank 0
6095 19:57:36.830274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6096 19:57:36.830842 ==
6097 19:57:36.833227 Write leveling (Byte 0): 32 => 0
6098 19:57:36.833687 Write leveling (Byte 1): 32 => 0
6099 19:57:36.836892 DramcWriteLeveling(PI) end<-----
6100 19:57:36.837405
6101 19:57:36.840245 ==
6102 19:57:36.840706 Dram Type= 6, Freq= 0, CH_0, rank 0
6103 19:57:36.846812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6104 19:57:36.847366 ==
6105 19:57:36.850142 [Gating] SW mode calibration
6106 19:57:36.856971 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6107 19:57:36.859673 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6108 19:57:36.866584 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6109 19:57:36.869960 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6110 19:57:36.873552 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6111 19:57:36.879853 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6112 19:57:36.883235 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6113 19:57:36.886719 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6114 19:57:36.893279 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6115 19:57:36.896655 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6116 19:57:36.899858 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6117 19:57:36.903293 Total UI for P1: 0, mck2ui 16
6118 19:57:36.907181 best dqsien dly found for B0: ( 0, 10, 16)
6119 19:57:36.909870 Total UI for P1: 0, mck2ui 16
6120 19:57:36.913208 best dqsien dly found for B1: ( 0, 10, 16)
6121 19:57:36.916642 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6122 19:57:36.919649 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6123 19:57:36.920240
6124 19:57:36.926139 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6125 19:57:36.929705 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6126 19:57:36.930269 [Gating] SW calibration Done
6127 19:57:36.932874 ==
6128 19:57:36.936245 Dram Type= 6, Freq= 0, CH_0, rank 0
6129 19:57:36.939702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6130 19:57:36.940295 ==
6131 19:57:36.940666 RX Vref Scan: 0
6132 19:57:36.941007
6133 19:57:36.943440 RX Vref 0 -> 0, step: 1
6134 19:57:36.943995
6135 19:57:36.946039 RX Delay -410 -> 252, step: 16
6136 19:57:36.949291 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6137 19:57:36.952680 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6138 19:57:36.959415 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6139 19:57:36.962763 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6140 19:57:36.966510 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6141 19:57:36.969484 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6142 19:57:36.976384 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6143 19:57:36.979520 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6144 19:57:36.982683 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6145 19:57:36.986101 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6146 19:57:36.992891 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6147 19:57:36.996150 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6148 19:57:36.999077 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6149 19:57:37.006256 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6150 19:57:37.009043 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6151 19:57:37.012495 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6152 19:57:37.012960 ==
6153 19:57:37.015814 Dram Type= 6, Freq= 0, CH_0, rank 0
6154 19:57:37.019305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6155 19:57:37.022508 ==
6156 19:57:37.022975 DQS Delay:
6157 19:57:37.023339 DQS0 = 51, DQS1 = 59
6158 19:57:37.025854 DQM Delay:
6159 19:57:37.026312 DQM0 = 12, DQM1 = 16
6160 19:57:37.029046 DQ Delay:
6161 19:57:37.029617 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6162 19:57:37.032555 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6163 19:57:37.035916 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6164 19:57:37.038876 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6165 19:57:37.039353
6166 19:57:37.039716
6167 19:57:37.040100 ==
6168 19:57:37.042781 Dram Type= 6, Freq= 0, CH_0, rank 0
6169 19:57:37.048931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6170 19:57:37.049395 ==
6171 19:57:37.049761
6172 19:57:37.050096
6173 19:57:37.050418 TX Vref Scan disable
6174 19:57:37.052495 == TX Byte 0 ==
6175 19:57:37.056029 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6176 19:57:37.062803 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6177 19:57:37.063350 == TX Byte 1 ==
6178 19:57:37.065674 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6179 19:57:37.072494 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6180 19:57:37.073053 ==
6181 19:57:37.075593 Dram Type= 6, Freq= 0, CH_0, rank 0
6182 19:57:37.079094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6183 19:57:37.079649 ==
6184 19:57:37.080015
6185 19:57:37.080398
6186 19:57:37.082250 TX Vref Scan disable
6187 19:57:37.082800 == TX Byte 0 ==
6188 19:57:37.085648 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6189 19:57:37.092251 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6190 19:57:37.092822 == TX Byte 1 ==
6191 19:57:37.095740 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6192 19:57:37.102155 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6193 19:57:37.102711
6194 19:57:37.103077 [DATLAT]
6195 19:57:37.105315 Freq=400, CH0 RK0
6196 19:57:37.105782
6197 19:57:37.106146 DATLAT Default: 0xf
6198 19:57:37.108787 0, 0xFFFF, sum = 0
6199 19:57:37.109341 1, 0xFFFF, sum = 0
6200 19:57:37.111873 2, 0xFFFF, sum = 0
6201 19:57:37.112465 3, 0xFFFF, sum = 0
6202 19:57:37.115087 4, 0xFFFF, sum = 0
6203 19:57:37.115553 5, 0xFFFF, sum = 0
6204 19:57:37.118611 6, 0xFFFF, sum = 0
6205 19:57:37.119167 7, 0xFFFF, sum = 0
6206 19:57:37.122024 8, 0xFFFF, sum = 0
6207 19:57:37.122579 9, 0xFFFF, sum = 0
6208 19:57:37.125161 10, 0xFFFF, sum = 0
6209 19:57:37.125715 11, 0xFFFF, sum = 0
6210 19:57:37.128295 12, 0x0, sum = 1
6211 19:57:37.128764 13, 0x0, sum = 2
6212 19:57:37.131869 14, 0x0, sum = 3
6213 19:57:37.132471 15, 0x0, sum = 4
6214 19:57:37.135079 best_step = 13
6215 19:57:37.135535
6216 19:57:37.135965 ==
6217 19:57:37.138355 Dram Type= 6, Freq= 0, CH_0, rank 0
6218 19:57:37.141631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6219 19:57:37.142096 ==
6220 19:57:37.144876 RX Vref Scan: 1
6221 19:57:37.145336
6222 19:57:37.145712 RX Vref 0 -> 0, step: 1
6223 19:57:37.146051
6224 19:57:37.148315 RX Delay -359 -> 252, step: 8
6225 19:57:37.148791
6226 19:57:37.151510 Set Vref, RX VrefLevel [Byte0]: 51
6227 19:57:37.155152 [Byte1]: 51
6228 19:57:37.159836
6229 19:57:37.160437 Final RX Vref Byte 0 = 51 to rank0
6230 19:57:37.162847 Final RX Vref Byte 1 = 51 to rank0
6231 19:57:37.166446 Final RX Vref Byte 0 = 51 to rank1
6232 19:57:37.169553 Final RX Vref Byte 1 = 51 to rank1==
6233 19:57:37.172876 Dram Type= 6, Freq= 0, CH_0, rank 0
6234 19:57:37.179668 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6235 19:57:37.180312 ==
6236 19:57:37.180695 DQS Delay:
6237 19:57:37.183106 DQS0 = 52, DQS1 = 64
6238 19:57:37.183660 DQM Delay:
6239 19:57:37.184024 DQM0 = 8, DQM1 = 13
6240 19:57:37.186480 DQ Delay:
6241 19:57:37.189630 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6242 19:57:37.190183 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6243 19:57:37.192852 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6244 19:57:37.196094 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6245 19:57:37.196706
6246 19:57:37.197079
6247 19:57:37.206157 [DQSOSCAuto] RK0, (LSB)MR18= 0x9f9f, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6248 19:57:37.209526 CH0 RK0: MR19=C0C, MR18=9F9F
6249 19:57:37.216646 CH0_RK0: MR19=0xC0C, MR18=0x9F9F, DQSOSC=389, MR23=63, INC=390, DEC=260
6250 19:57:37.217258 ==
6251 19:57:37.219522 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 19:57:37.223060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6253 19:57:37.223620 ==
6254 19:57:37.226282 [Gating] SW mode calibration
6255 19:57:37.232896 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6256 19:57:37.236236 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6257 19:57:37.242435 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6258 19:57:37.245877 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 19:57:37.249348 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6260 19:57:37.256172 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6261 19:57:37.259264 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6262 19:57:37.262405 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 19:57:37.269064 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 19:57:37.272566 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6265 19:57:37.275904 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 19:57:37.279575 Total UI for P1: 0, mck2ui 16
6267 19:57:37.282642 best dqsien dly found for B0: ( 0, 10, 16)
6268 19:57:37.285624 Total UI for P1: 0, mck2ui 16
6269 19:57:37.289501 best dqsien dly found for B1: ( 0, 10, 16)
6270 19:57:37.292535 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6271 19:57:37.295700 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6272 19:57:37.298860
6273 19:57:37.302178 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6274 19:57:37.305732 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6275 19:57:37.308857 [Gating] SW calibration Done
6276 19:57:37.309410 ==
6277 19:57:37.312472 Dram Type= 6, Freq= 0, CH_0, rank 1
6278 19:57:37.315303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6279 19:57:37.315785 ==
6280 19:57:37.316152 RX Vref Scan: 0
6281 19:57:37.318929
6282 19:57:37.319498 RX Vref 0 -> 0, step: 1
6283 19:57:37.319870
6284 19:57:37.322170 RX Delay -410 -> 252, step: 16
6285 19:57:37.325595 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6286 19:57:37.332309 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6287 19:57:37.335599 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6288 19:57:37.338878 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6289 19:57:37.342112 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6290 19:57:37.348767 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6291 19:57:37.351825 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6292 19:57:37.355213 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6293 19:57:37.359163 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6294 19:57:37.365329 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6295 19:57:37.368911 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6296 19:57:37.372215 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6297 19:57:37.375374 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6298 19:57:37.381985 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6299 19:57:37.385057 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6300 19:57:37.388854 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6301 19:57:37.389407 ==
6302 19:57:37.391978 Dram Type= 6, Freq= 0, CH_0, rank 1
6303 19:57:37.398584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6304 19:57:37.399188 ==
6305 19:57:37.399560 DQS Delay:
6306 19:57:37.401853 DQS0 = 43, DQS1 = 59
6307 19:57:37.402309 DQM Delay:
6308 19:57:37.402667 DQM0 = 7, DQM1 = 15
6309 19:57:37.405176 DQ Delay:
6310 19:57:37.408423 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6311 19:57:37.408962 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6312 19:57:37.411937 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6313 19:57:37.415160 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6314 19:57:37.415618
6315 19:57:37.415979
6316 19:57:37.418829 ==
6317 19:57:37.421940 Dram Type= 6, Freq= 0, CH_0, rank 1
6318 19:57:37.425002 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6319 19:57:37.425567 ==
6320 19:57:37.425930
6321 19:57:37.426265
6322 19:57:37.428545 TX Vref Scan disable
6323 19:57:37.429090 == TX Byte 0 ==
6324 19:57:37.431861 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6325 19:57:37.438447 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6326 19:57:37.438984 == TX Byte 1 ==
6327 19:57:37.441562 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6328 19:57:37.448221 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6329 19:57:37.448705 ==
6330 19:57:37.451512 Dram Type= 6, Freq= 0, CH_0, rank 1
6331 19:57:37.455035 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6332 19:57:37.455598 ==
6333 19:57:37.455962
6334 19:57:37.456356
6335 19:57:37.458435 TX Vref Scan disable
6336 19:57:37.459009 == TX Byte 0 ==
6337 19:57:37.461416 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6338 19:57:37.468723 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6339 19:57:37.469281 == TX Byte 1 ==
6340 19:57:37.471512 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6341 19:57:37.478359 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6342 19:57:37.478911
6343 19:57:37.479272 [DATLAT]
6344 19:57:37.479607 Freq=400, CH0 RK1
6345 19:57:37.479931
6346 19:57:37.481392 DATLAT Default: 0xd
6347 19:57:37.481845 0, 0xFFFF, sum = 0
6348 19:57:37.484618 1, 0xFFFF, sum = 0
6349 19:57:37.488436 2, 0xFFFF, sum = 0
6350 19:57:37.488995 3, 0xFFFF, sum = 0
6351 19:57:37.491939 4, 0xFFFF, sum = 0
6352 19:57:37.492542 5, 0xFFFF, sum = 0
6353 19:57:37.494798 6, 0xFFFF, sum = 0
6354 19:57:37.495351 7, 0xFFFF, sum = 0
6355 19:57:37.498151 8, 0xFFFF, sum = 0
6356 19:57:37.498709 9, 0xFFFF, sum = 0
6357 19:57:37.501346 10, 0xFFFF, sum = 0
6358 19:57:37.501808 11, 0xFFFF, sum = 0
6359 19:57:37.504721 12, 0x0, sum = 1
6360 19:57:37.505181 13, 0x0, sum = 2
6361 19:57:37.507741 14, 0x0, sum = 3
6362 19:57:37.508222 15, 0x0, sum = 4
6363 19:57:37.511383 best_step = 13
6364 19:57:37.511833
6365 19:57:37.512216 ==
6366 19:57:37.514338 Dram Type= 6, Freq= 0, CH_0, rank 1
6367 19:57:37.517623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6368 19:57:37.518079 ==
6369 19:57:37.518430 RX Vref Scan: 0
6370 19:57:37.520964
6371 19:57:37.521412 RX Vref 0 -> 0, step: 1
6372 19:57:37.521773
6373 19:57:37.524374 RX Delay -359 -> 252, step: 8
6374 19:57:37.531907 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6375 19:57:37.535377 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6376 19:57:37.538398 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6377 19:57:37.541802 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6378 19:57:37.548575 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6379 19:57:37.551850 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6380 19:57:37.555651 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6381 19:57:37.558645 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6382 19:57:37.565052 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6383 19:57:37.568448 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6384 19:57:37.572052 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6385 19:57:37.575845 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6386 19:57:37.581926 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6387 19:57:37.585276 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6388 19:57:37.588752 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6389 19:57:37.595267 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6390 19:57:37.595834 ==
6391 19:57:37.598616 Dram Type= 6, Freq= 0, CH_0, rank 1
6392 19:57:37.601475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6393 19:57:37.601930 ==
6394 19:57:37.602290 DQS Delay:
6395 19:57:37.605327 DQS0 = 52, DQS1 = 64
6396 19:57:37.605867 DQM Delay:
6397 19:57:37.608523 DQM0 = 10, DQM1 = 13
6398 19:57:37.609066 DQ Delay:
6399 19:57:37.611831 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6400 19:57:37.615004 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6401 19:57:37.618493 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6402 19:57:37.621508 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6403 19:57:37.621964
6404 19:57:37.622320
6405 19:57:37.628147 [DQSOSCAuto] RK1, (LSB)MR18= 0xb9b9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6406 19:57:37.631411 CH0 RK1: MR19=C0C, MR18=B9B9
6407 19:57:37.638068 CH0_RK1: MR19=0xC0C, MR18=0xB9B9, DQSOSC=386, MR23=63, INC=396, DEC=264
6408 19:57:37.641468 [RxdqsGatingPostProcess] freq 400
6409 19:57:37.648156 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6410 19:57:37.648799 Pre-setting of DQS Precalculation
6411 19:57:37.655176 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6412 19:57:37.655730 ==
6413 19:57:37.658297 Dram Type= 6, Freq= 0, CH_1, rank 0
6414 19:57:37.661483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6415 19:57:37.661942 ==
6416 19:57:37.668338 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6417 19:57:37.675076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6418 19:57:37.678180 [CA 0] Center 36 (8~64) winsize 57
6419 19:57:37.681376 [CA 1] Center 36 (8~64) winsize 57
6420 19:57:37.684626 [CA 2] Center 36 (8~64) winsize 57
6421 19:57:37.685087 [CA 3] Center 36 (8~64) winsize 57
6422 19:57:37.688292 [CA 4] Center 36 (8~64) winsize 57
6423 19:57:37.691459 [CA 5] Center 36 (8~64) winsize 57
6424 19:57:37.692059
6425 19:57:37.697999 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6426 19:57:37.698548
6427 19:57:37.701173 [CATrainingPosCal] consider 1 rank data
6428 19:57:37.704751 u2DelayCellTimex100 = 270/100 ps
6429 19:57:37.708286 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6430 19:57:37.710869 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6431 19:57:37.714035 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6432 19:57:37.717848 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6433 19:57:37.721146 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6434 19:57:37.724271 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6435 19:57:37.724722
6436 19:57:37.727787 CA PerBit enable=1, Macro0, CA PI delay=36
6437 19:57:37.728386
6438 19:57:37.731016 [CBTSetCACLKResult] CA Dly = 36
6439 19:57:37.734363 CS Dly: 1 (0~32)
6440 19:57:37.734945 ==
6441 19:57:37.737516 Dram Type= 6, Freq= 0, CH_1, rank 1
6442 19:57:37.741139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6443 19:57:37.741685 ==
6444 19:57:37.747790 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6445 19:57:37.750935 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6446 19:57:37.753970 [CA 0] Center 36 (8~64) winsize 57
6447 19:57:37.757399 [CA 1] Center 36 (8~64) winsize 57
6448 19:57:37.760747 [CA 2] Center 36 (8~64) winsize 57
6449 19:57:37.763995 [CA 3] Center 36 (8~64) winsize 57
6450 19:57:37.767439 [CA 4] Center 36 (8~64) winsize 57
6451 19:57:37.770779 [CA 5] Center 36 (8~64) winsize 57
6452 19:57:37.771232
6453 19:57:37.774215 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6454 19:57:37.774770
6455 19:57:37.777545 [CATrainingPosCal] consider 2 rank data
6456 19:57:37.780823 u2DelayCellTimex100 = 270/100 ps
6457 19:57:37.784299 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6458 19:57:37.787660 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6459 19:57:37.794217 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6460 19:57:37.797235 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6461 19:57:37.800744 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6462 19:57:37.804003 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6463 19:57:37.804627
6464 19:57:37.807162 CA PerBit enable=1, Macro0, CA PI delay=36
6465 19:57:37.807724
6466 19:57:37.810613 [CBTSetCACLKResult] CA Dly = 36
6467 19:57:37.811165 CS Dly: 1 (0~32)
6468 19:57:37.811527
6469 19:57:37.817005 ----->DramcWriteLeveling(PI) begin...
6470 19:57:37.817552 ==
6471 19:57:37.820847 Dram Type= 6, Freq= 0, CH_1, rank 0
6472 19:57:37.823846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6473 19:57:37.824437 ==
6474 19:57:37.827315 Write leveling (Byte 0): 32 => 0
6475 19:57:37.830561 Write leveling (Byte 1): 32 => 0
6476 19:57:37.833719 DramcWriteLeveling(PI) end<-----
6477 19:57:37.834269
6478 19:57:37.834627 ==
6479 19:57:37.836863 Dram Type= 6, Freq= 0, CH_1, rank 0
6480 19:57:37.840736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6481 19:57:37.841294 ==
6482 19:57:37.843449 [Gating] SW mode calibration
6483 19:57:37.850231 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 19:57:37.856648 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6485 19:57:37.860261 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 19:57:37.863603 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 19:57:37.867013 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 19:57:37.873325 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6489 19:57:37.876640 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 19:57:37.879798 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 19:57:37.886533 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 19:57:37.889622 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6493 19:57:37.893285 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 19:57:37.896591 Total UI for P1: 0, mck2ui 16
6495 19:57:37.900027 best dqsien dly found for B0: ( 0, 10, 16)
6496 19:57:37.903271 Total UI for P1: 0, mck2ui 16
6497 19:57:37.906727 best dqsien dly found for B1: ( 0, 10, 16)
6498 19:57:37.909706 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6499 19:57:37.916795 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6500 19:57:37.917253
6501 19:57:37.919953 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6502 19:57:37.923236 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6503 19:57:37.926555 [Gating] SW calibration Done
6504 19:57:37.927013 ==
6505 19:57:37.929631 Dram Type= 6, Freq= 0, CH_1, rank 0
6506 19:57:37.933176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6507 19:57:37.933635 ==
6508 19:57:37.936770 RX Vref Scan: 0
6509 19:57:37.937301
6510 19:57:37.937677 RX Vref 0 -> 0, step: 1
6511 19:57:37.938014
6512 19:57:37.939636 RX Delay -410 -> 252, step: 16
6513 19:57:37.942956 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6514 19:57:37.949716 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6515 19:57:37.953041 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6516 19:57:37.956152 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6517 19:57:37.959923 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6518 19:57:37.966366 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6519 19:57:37.969349 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6520 19:57:37.972802 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6521 19:57:37.976302 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6522 19:57:37.983173 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6523 19:57:37.986406 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6524 19:57:37.989396 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6525 19:57:37.995997 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6526 19:57:37.999205 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6527 19:57:38.002703 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6528 19:57:38.006117 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6529 19:57:38.006678 ==
6530 19:57:38.009402 Dram Type= 6, Freq= 0, CH_1, rank 0
6531 19:57:38.016052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6532 19:57:38.016765 ==
6533 19:57:38.017145 DQS Delay:
6534 19:57:38.019805 DQS0 = 43, DQS1 = 59
6535 19:57:38.020414 DQM Delay:
6536 19:57:38.020779 DQM0 = 6, DQM1 = 15
6537 19:57:38.022476 DQ Delay:
6538 19:57:38.026108 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6539 19:57:38.026662 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6540 19:57:38.029177 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6541 19:57:38.032310 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6542 19:57:38.035814
6543 19:57:38.036310
6544 19:57:38.036676 ==
6545 19:57:38.039308 Dram Type= 6, Freq= 0, CH_1, rank 0
6546 19:57:38.042236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6547 19:57:38.042692 ==
6548 19:57:38.043051
6549 19:57:38.043381
6550 19:57:38.045712 TX Vref Scan disable
6551 19:57:38.046164 == TX Byte 0 ==
6552 19:57:38.049147 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6553 19:57:38.055703 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6554 19:57:38.056157 == TX Byte 1 ==
6555 19:57:38.059084 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6556 19:57:38.065375 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6557 19:57:38.065912 ==
6558 19:57:38.068843 Dram Type= 6, Freq= 0, CH_1, rank 0
6559 19:57:38.072050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6560 19:57:38.072564 ==
6561 19:57:38.072923
6562 19:57:38.073330
6563 19:57:38.075469 TX Vref Scan disable
6564 19:57:38.075923 == TX Byte 0 ==
6565 19:57:38.082238 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6566 19:57:38.085585 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6567 19:57:38.086153 == TX Byte 1 ==
6568 19:57:38.092217 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6569 19:57:38.095697 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6570 19:57:38.096304
6571 19:57:38.096674 [DATLAT]
6572 19:57:38.098904 Freq=400, CH1 RK0
6573 19:57:38.099457
6574 19:57:38.099816 DATLAT Default: 0xf
6575 19:57:38.101995 0, 0xFFFF, sum = 0
6576 19:57:38.102482 1, 0xFFFF, sum = 0
6577 19:57:38.105439 2, 0xFFFF, sum = 0
6578 19:57:38.106059 3, 0xFFFF, sum = 0
6579 19:57:38.108755 4, 0xFFFF, sum = 0
6580 19:57:38.111719 5, 0xFFFF, sum = 0
6581 19:57:38.112284 6, 0xFFFF, sum = 0
6582 19:57:38.115118 7, 0xFFFF, sum = 0
6583 19:57:38.115576 8, 0xFFFF, sum = 0
6584 19:57:38.118309 9, 0xFFFF, sum = 0
6585 19:57:38.118770 10, 0xFFFF, sum = 0
6586 19:57:38.121680 11, 0xFFFF, sum = 0
6587 19:57:38.122138 12, 0x0, sum = 1
6588 19:57:38.125180 13, 0x0, sum = 2
6589 19:57:38.125743 14, 0x0, sum = 3
6590 19:57:38.128457 15, 0x0, sum = 4
6591 19:57:38.128915 best_step = 13
6592 19:57:38.129271
6593 19:57:38.129599 ==
6594 19:57:38.131611 Dram Type= 6, Freq= 0, CH_1, rank 0
6595 19:57:38.135126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6596 19:57:38.135581 ==
6597 19:57:38.138328 RX Vref Scan: 1
6598 19:57:38.138779
6599 19:57:38.141675 RX Vref 0 -> 0, step: 1
6600 19:57:38.142427
6601 19:57:38.142907 RX Delay -359 -> 252, step: 8
6602 19:57:38.143256
6603 19:57:38.144990 Set Vref, RX VrefLevel [Byte0]: 53
6604 19:57:38.148415 [Byte1]: 50
6605 19:57:38.153910
6606 19:57:38.154458 Final RX Vref Byte 0 = 53 to rank0
6607 19:57:38.157126 Final RX Vref Byte 1 = 50 to rank0
6608 19:57:38.160248 Final RX Vref Byte 0 = 53 to rank1
6609 19:57:38.164039 Final RX Vref Byte 1 = 50 to rank1==
6610 19:57:38.166913 Dram Type= 6, Freq= 0, CH_1, rank 0
6611 19:57:38.173746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6612 19:57:38.174306 ==
6613 19:57:38.174671 DQS Delay:
6614 19:57:38.176944 DQS0 = 48, DQS1 = 64
6615 19:57:38.177395 DQM Delay:
6616 19:57:38.177753 DQM0 = 8, DQM1 = 16
6617 19:57:38.180497 DQ Delay:
6618 19:57:38.183652 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6619 19:57:38.184104 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6620 19:57:38.186976 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6621 19:57:38.190166 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6622 19:57:38.190617
6623 19:57:38.190970
6624 19:57:38.200346 [DQSOSCAuto] RK0, (LSB)MR18= 0xdfdf, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6625 19:57:38.203583 CH1 RK0: MR19=C0C, MR18=DFDF
6626 19:57:38.210267 CH1_RK0: MR19=0xC0C, MR18=0xDFDF, DQSOSC=382, MR23=63, INC=404, DEC=269
6627 19:57:38.210822 ==
6628 19:57:38.213891 Dram Type= 6, Freq= 0, CH_1, rank 1
6629 19:57:38.216755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6630 19:57:38.217359 ==
6631 19:57:38.220076 [Gating] SW mode calibration
6632 19:57:38.226750 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6633 19:57:38.230132 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6634 19:57:38.236903 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6635 19:57:38.239899 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6636 19:57:38.243363 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6637 19:57:38.250127 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6638 19:57:38.253480 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6639 19:57:38.256500 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6640 19:57:38.263216 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6641 19:57:38.266496 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6642 19:57:38.269914 Total UI for P1: 0, mck2ui 16
6643 19:57:38.273092 best dqsien dly found for B0: ( 0, 10, 8)
6644 19:57:38.276724 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6645 19:57:38.279859 Total UI for P1: 0, mck2ui 16
6646 19:57:38.283281 best dqsien dly found for B1: ( 0, 10, 16)
6647 19:57:38.286477 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6648 19:57:38.289748 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6649 19:57:38.293114
6650 19:57:38.296391 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6651 19:57:38.299587 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6652 19:57:38.303151 [Gating] SW calibration Done
6653 19:57:38.303708 ==
6654 19:57:38.306387 Dram Type= 6, Freq= 0, CH_1, rank 1
6655 19:57:38.309350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6656 19:57:38.309809 ==
6657 19:57:38.310165 RX Vref Scan: 0
6658 19:57:38.312893
6659 19:57:38.313441 RX Vref 0 -> 0, step: 1
6660 19:57:38.313805
6661 19:57:38.315976 RX Delay -410 -> 252, step: 16
6662 19:57:38.319528 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6663 19:57:38.325923 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6664 19:57:38.329610 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6665 19:57:38.332775 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6666 19:57:38.336090 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6667 19:57:38.342880 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6668 19:57:38.346079 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6669 19:57:38.349165 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6670 19:57:38.352625 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6671 19:57:38.359379 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6672 19:57:38.362790 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6673 19:57:38.365730 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6674 19:57:38.369660 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6675 19:57:38.375814 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6676 19:57:38.379302 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6677 19:57:38.382590 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6678 19:57:38.383143 ==
6679 19:57:38.385875 Dram Type= 6, Freq= 0, CH_1, rank 1
6680 19:57:38.392501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6681 19:57:38.393056 ==
6682 19:57:38.393419 DQS Delay:
6683 19:57:38.395674 DQS0 = 43, DQS1 = 59
6684 19:57:38.396124 DQM Delay:
6685 19:57:38.396516 DQM0 = 10, DQM1 = 17
6686 19:57:38.398727 DQ Delay:
6687 19:57:38.402447 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6688 19:57:38.403001 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6689 19:57:38.405855 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6690 19:57:38.408976 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6691 19:57:38.409526
6692 19:57:38.412524
6693 19:57:38.413071 ==
6694 19:57:38.415476 Dram Type= 6, Freq= 0, CH_1, rank 1
6695 19:57:38.418979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6696 19:57:38.419437 ==
6697 19:57:38.419792
6698 19:57:38.420123
6699 19:57:38.422136 TX Vref Scan disable
6700 19:57:38.422655 == TX Byte 0 ==
6701 19:57:38.425683 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6702 19:57:38.432101 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6703 19:57:38.432666 == TX Byte 1 ==
6704 19:57:38.435675 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6705 19:57:38.442363 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6706 19:57:38.442928 ==
6707 19:57:38.445507 Dram Type= 6, Freq= 0, CH_1, rank 1
6708 19:57:38.449060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6709 19:57:38.449608 ==
6710 19:57:38.449973
6711 19:57:38.450304
6712 19:57:38.452145 TX Vref Scan disable
6713 19:57:38.452641 == TX Byte 0 ==
6714 19:57:38.455390 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6715 19:57:38.462239 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6716 19:57:38.462858 == TX Byte 1 ==
6717 19:57:38.465183 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6718 19:57:38.471686 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6719 19:57:38.472138
6720 19:57:38.472566 [DATLAT]
6721 19:57:38.472967 Freq=400, CH1 RK1
6722 19:57:38.473298
6723 19:57:38.475302 DATLAT Default: 0xd
6724 19:57:38.478842 0, 0xFFFF, sum = 0
6725 19:57:38.479398 1, 0xFFFF, sum = 0
6726 19:57:38.481948 2, 0xFFFF, sum = 0
6727 19:57:38.482500 3, 0xFFFF, sum = 0
6728 19:57:38.485030 4, 0xFFFF, sum = 0
6729 19:57:38.485492 5, 0xFFFF, sum = 0
6730 19:57:38.488767 6, 0xFFFF, sum = 0
6731 19:57:38.489227 7, 0xFFFF, sum = 0
6732 19:57:38.491804 8, 0xFFFF, sum = 0
6733 19:57:38.492312 9, 0xFFFF, sum = 0
6734 19:57:38.495445 10, 0xFFFF, sum = 0
6735 19:57:38.496001 11, 0xFFFF, sum = 0
6736 19:57:38.498621 12, 0x0, sum = 1
6737 19:57:38.499176 13, 0x0, sum = 2
6738 19:57:38.502008 14, 0x0, sum = 3
6739 19:57:38.502569 15, 0x0, sum = 4
6740 19:57:38.505393 best_step = 13
6741 19:57:38.505939
6742 19:57:38.506294 ==
6743 19:57:38.508491 Dram Type= 6, Freq= 0, CH_1, rank 1
6744 19:57:38.511963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6745 19:57:38.512615 ==
6746 19:57:38.512980 RX Vref Scan: 0
6747 19:57:38.514932
6748 19:57:38.515379 RX Vref 0 -> 0, step: 1
6749 19:57:38.515737
6750 19:57:38.518091 RX Delay -359 -> 252, step: 8
6751 19:57:38.526228 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6752 19:57:38.529049 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6753 19:57:38.532857 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6754 19:57:38.536092 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6755 19:57:38.542652 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6756 19:57:38.545750 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6757 19:57:38.549176 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6758 19:57:38.552701 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
6759 19:57:38.559140 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6760 19:57:38.562669 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6761 19:57:38.566074 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6762 19:57:38.569052 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6763 19:57:38.575879 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6764 19:57:38.579070 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6765 19:57:38.582674 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6766 19:57:38.589031 iDelay=225, Bit 15, Center -36 (-279 ~ 208) 488
6767 19:57:38.589486 ==
6768 19:57:38.592886 Dram Type= 6, Freq= 0, CH_1, rank 1
6769 19:57:38.595687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6770 19:57:38.596144 ==
6771 19:57:38.596548 DQS Delay:
6772 19:57:38.599181 DQS0 = 48, DQS1 = 64
6773 19:57:38.599731 DQM Delay:
6774 19:57:38.602610 DQM0 = 10, DQM1 = 16
6775 19:57:38.603160 DQ Delay:
6776 19:57:38.606018 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6777 19:57:38.608828 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =12
6778 19:57:38.612561 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6779 19:57:38.615804 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =28
6780 19:57:38.616399
6781 19:57:38.616765
6782 19:57:38.622606 [DQSOSCAuto] RK1, (LSB)MR18= 0xa6a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6783 19:57:38.625742 CH1 RK1: MR19=C0C, MR18=A6A6
6784 19:57:38.632551 CH1_RK1: MR19=0xC0C, MR18=0xA6A6, DQSOSC=389, MR23=63, INC=390, DEC=260
6785 19:57:38.635795 [RxdqsGatingPostProcess] freq 400
6786 19:57:38.642681 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6787 19:57:38.643232 Pre-setting of DQS Precalculation
6788 19:57:38.648800 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6789 19:57:38.655250 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6790 19:57:38.662230 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6791 19:57:38.662786
6792 19:57:38.663147
6793 19:57:38.665352 [Calibration Summary] 800 Mbps
6794 19:57:38.668901 CH 0, Rank 0
6795 19:57:38.669445 SW Impedance : PASS
6796 19:57:38.672805 DUTY Scan : NO K
6797 19:57:38.675283 ZQ Calibration : PASS
6798 19:57:38.675832 Jitter Meter : NO K
6799 19:57:38.678801 CBT Training : PASS
6800 19:57:38.681988 Write leveling : PASS
6801 19:57:38.682537 RX DQS gating : PASS
6802 19:57:38.685270 RX DQ/DQS(RDDQC) : PASS
6803 19:57:38.685719 TX DQ/DQS : PASS
6804 19:57:38.688248 RX DATLAT : PASS
6805 19:57:38.691881 RX DQ/DQS(Engine): PASS
6806 19:57:38.692476 TX OE : NO K
6807 19:57:38.695171 All Pass.
6808 19:57:38.695722
6809 19:57:38.696080 CH 0, Rank 1
6810 19:57:38.698370 SW Impedance : PASS
6811 19:57:38.698872 DUTY Scan : NO K
6812 19:57:38.701776 ZQ Calibration : PASS
6813 19:57:38.704928 Jitter Meter : NO K
6814 19:57:38.705380 CBT Training : PASS
6815 19:57:38.708724 Write leveling : NO K
6816 19:57:38.711674 RX DQS gating : PASS
6817 19:57:38.712127 RX DQ/DQS(RDDQC) : PASS
6818 19:57:38.715152 TX DQ/DQS : PASS
6819 19:57:38.718147 RX DATLAT : PASS
6820 19:57:38.718625 RX DQ/DQS(Engine): PASS
6821 19:57:38.721916 TX OE : NO K
6822 19:57:38.722483 All Pass.
6823 19:57:38.722845
6824 19:57:38.725043 CH 1, Rank 0
6825 19:57:38.725498 SW Impedance : PASS
6826 19:57:38.728527 DUTY Scan : NO K
6827 19:57:38.731826 ZQ Calibration : PASS
6828 19:57:38.732423 Jitter Meter : NO K
6829 19:57:38.735425 CBT Training : PASS
6830 19:57:38.735983 Write leveling : PASS
6831 19:57:38.738539 RX DQS gating : PASS
6832 19:57:38.741528 RX DQ/DQS(RDDQC) : PASS
6833 19:57:38.741986 TX DQ/DQS : PASS
6834 19:57:38.744806 RX DATLAT : PASS
6835 19:57:38.748404 RX DQ/DQS(Engine): PASS
6836 19:57:38.748973 TX OE : NO K
6837 19:57:38.751531 All Pass.
6838 19:57:38.751987
6839 19:57:38.752389 CH 1, Rank 1
6840 19:57:38.754988 SW Impedance : PASS
6841 19:57:38.755552 DUTY Scan : NO K
6842 19:57:38.758106 ZQ Calibration : PASS
6843 19:57:38.761598 Jitter Meter : NO K
6844 19:57:38.762156 CBT Training : PASS
6845 19:57:38.764496 Write leveling : NO K
6846 19:57:38.767933 RX DQS gating : PASS
6847 19:57:38.768430 RX DQ/DQS(RDDQC) : PASS
6848 19:57:38.771346 TX DQ/DQS : PASS
6849 19:57:38.774846 RX DATLAT : PASS
6850 19:57:38.775409 RX DQ/DQS(Engine): PASS
6851 19:57:38.777956 TX OE : NO K
6852 19:57:38.778523 All Pass.
6853 19:57:38.778887
6854 19:57:38.780826 DramC Write-DBI off
6855 19:57:38.784412 PER_BANK_REFRESH: Hybrid Mode
6856 19:57:38.784874 TX_TRACKING: ON
6857 19:57:38.794636 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6858 19:57:38.797611 [FAST_K] Save calibration result to emmc
6859 19:57:38.801199 dramc_set_vcore_voltage set vcore to 725000
6860 19:57:38.804697 Read voltage for 1600, 0
6861 19:57:38.805276 Vio18 = 0
6862 19:57:38.805647 Vcore = 725000
6863 19:57:38.807865 Vdram = 0
6864 19:57:38.808359 Vddq = 0
6865 19:57:38.808729 Vmddr = 0
6866 19:57:38.814489 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6867 19:57:38.817801 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6868 19:57:38.821570 MEM_TYPE=3, freq_sel=13
6869 19:57:38.824459 sv_algorithm_assistance_LP4_3733
6870 19:57:38.827648 ============ PULL DRAM RESETB DOWN ============
6871 19:57:38.831133 ========== PULL DRAM RESETB DOWN end =========
6872 19:57:38.837774 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6873 19:57:38.840853 ===================================
6874 19:57:38.841318 LPDDR4 DRAM CONFIGURATION
6875 19:57:38.844545 ===================================
6876 19:57:38.847875 EX_ROW_EN[0] = 0x0
6877 19:57:38.851038 EX_ROW_EN[1] = 0x0
6878 19:57:38.851501 LP4Y_EN = 0x0
6879 19:57:38.854457 WORK_FSP = 0x1
6880 19:57:38.855018 WL = 0x5
6881 19:57:38.857475 RL = 0x5
6882 19:57:38.857934 BL = 0x2
6883 19:57:38.860946 RPST = 0x0
6884 19:57:38.861405 RD_PRE = 0x0
6885 19:57:38.863946 WR_PRE = 0x1
6886 19:57:38.864465 WR_PST = 0x1
6887 19:57:38.867502 DBI_WR = 0x0
6888 19:57:38.868052 DBI_RD = 0x0
6889 19:57:38.870845 OTF = 0x1
6890 19:57:38.874185 ===================================
6891 19:57:38.877368 ===================================
6892 19:57:38.877832 ANA top config
6893 19:57:38.880757 ===================================
6894 19:57:38.884136 DLL_ASYNC_EN = 0
6895 19:57:38.887543 ALL_SLAVE_EN = 0
6896 19:57:38.890814 NEW_RANK_MODE = 1
6897 19:57:38.891364 DLL_IDLE_MODE = 1
6898 19:57:38.894152 LP45_APHY_COMB_EN = 1
6899 19:57:38.897612 TX_ODT_DIS = 0
6900 19:57:38.900761 NEW_8X_MODE = 1
6901 19:57:38.904233 ===================================
6902 19:57:38.907428 ===================================
6903 19:57:38.910508 data_rate = 3200
6904 19:57:38.913937 CKR = 1
6905 19:57:38.914484 DQ_P2S_RATIO = 8
6906 19:57:38.917278 ===================================
6907 19:57:38.920386 CA_P2S_RATIO = 8
6908 19:57:38.923794 DQ_CA_OPEN = 0
6909 19:57:38.927037 DQ_SEMI_OPEN = 0
6910 19:57:38.930145 CA_SEMI_OPEN = 0
6911 19:57:38.930607 CA_FULL_RATE = 0
6912 19:57:38.933789 DQ_CKDIV4_EN = 0
6913 19:57:38.937120 CA_CKDIV4_EN = 0
6914 19:57:38.940335 CA_PREDIV_EN = 0
6915 19:57:38.943820 PH8_DLY = 12
6916 19:57:38.947031 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6917 19:57:38.947576 DQ_AAMCK_DIV = 4
6918 19:57:38.950449 CA_AAMCK_DIV = 4
6919 19:57:38.953659 CA_ADMCK_DIV = 4
6920 19:57:38.956832 DQ_TRACK_CA_EN = 0
6921 19:57:38.960234 CA_PICK = 1600
6922 19:57:38.963539 CA_MCKIO = 1600
6923 19:57:38.966725 MCKIO_SEMI = 0
6924 19:57:38.970165 PLL_FREQ = 3068
6925 19:57:38.970715 DQ_UI_PI_RATIO = 32
6926 19:57:38.973650 CA_UI_PI_RATIO = 0
6927 19:57:38.976912 ===================================
6928 19:57:38.980090 ===================================
6929 19:57:38.983472 memory_type:LPDDR4
6930 19:57:38.986873 GP_NUM : 10
6931 19:57:38.987425 SRAM_EN : 1
6932 19:57:38.990082 MD32_EN : 0
6933 19:57:38.993404 ===================================
6934 19:57:38.997060 [ANA_INIT] >>>>>>>>>>>>>>
6935 19:57:38.997787 <<<<<< [CONFIGURE PHASE]: ANA_TX
6936 19:57:38.999719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6937 19:57:39.003137 ===================================
6938 19:57:39.006585 data_rate = 3200,PCW = 0X7600
6939 19:57:39.010207 ===================================
6940 19:57:39.012983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6941 19:57:39.019931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6942 19:57:39.026405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6943 19:57:39.029581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6944 19:57:39.032956 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6945 19:57:39.036456 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6946 19:57:39.039642 [ANA_INIT] flow start
6947 19:57:39.040102 [ANA_INIT] PLL >>>>>>>>
6948 19:57:39.043043 [ANA_INIT] PLL <<<<<<<<
6949 19:57:39.046289 [ANA_INIT] MIDPI >>>>>>>>
6950 19:57:39.046750 [ANA_INIT] MIDPI <<<<<<<<
6951 19:57:39.049780 [ANA_INIT] DLL >>>>>>>>
6952 19:57:39.052837 [ANA_INIT] DLL <<<<<<<<
6953 19:57:39.053375 [ANA_INIT] flow end
6954 19:57:39.059637 ============ LP4 DIFF to SE enter ============
6955 19:57:39.063280 ============ LP4 DIFF to SE exit ============
6956 19:57:39.066213 [ANA_INIT] <<<<<<<<<<<<<
6957 19:57:39.069629 [Flow] Enable top DCM control >>>>>
6958 19:57:39.072806 [Flow] Enable top DCM control <<<<<
6959 19:57:39.073261 Enable DLL master slave shuffle
6960 19:57:39.079731 ==============================================================
6961 19:57:39.083035 Gating Mode config
6962 19:57:39.086276 ==============================================================
6963 19:57:39.089273 Config description:
6964 19:57:39.099634 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6965 19:57:39.105896 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6966 19:57:39.109577 SELPH_MODE 0: By rank 1: By Phase
6967 19:57:39.116589 ==============================================================
6968 19:57:39.119388 GAT_TRACK_EN = 1
6969 19:57:39.122998 RX_GATING_MODE = 2
6970 19:57:39.126072 RX_GATING_TRACK_MODE = 2
6971 19:57:39.129057 SELPH_MODE = 1
6972 19:57:39.129550 PICG_EARLY_EN = 1
6973 19:57:39.132657 VALID_LAT_VALUE = 1
6974 19:57:39.139160 ==============================================================
6975 19:57:39.142409 Enter into Gating configuration >>>>
6976 19:57:39.146000 Exit from Gating configuration <<<<
6977 19:57:39.149683 Enter into DVFS_PRE_config >>>>>
6978 19:57:39.158813 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6979 19:57:39.162454 Exit from DVFS_PRE_config <<<<<
6980 19:57:39.165587 Enter into PICG configuration >>>>
6981 19:57:39.168869 Exit from PICG configuration <<<<
6982 19:57:39.172319 [RX_INPUT] configuration >>>>>
6983 19:57:39.176017 [RX_INPUT] configuration <<<<<
6984 19:57:39.179208 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6985 19:57:39.185624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6986 19:57:39.192286 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6987 19:57:39.198960 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6988 19:57:39.205424 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6989 19:57:39.212151 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6990 19:57:39.215579 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6991 19:57:39.218854 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6992 19:57:39.221957 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6993 19:57:39.228781 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6994 19:57:39.231901 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6995 19:57:39.235251 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6996 19:57:39.238538 ===================================
6997 19:57:39.241634 LPDDR4 DRAM CONFIGURATION
6998 19:57:39.244923 ===================================
6999 19:57:39.245475 EX_ROW_EN[0] = 0x0
7000 19:57:39.248677 EX_ROW_EN[1] = 0x0
7001 19:57:39.251464 LP4Y_EN = 0x0
7002 19:57:39.252097 WORK_FSP = 0x1
7003 19:57:39.254674 WL = 0x5
7004 19:57:39.255134 RL = 0x5
7005 19:57:39.258254 BL = 0x2
7006 19:57:39.258885 RPST = 0x0
7007 19:57:39.261315 RD_PRE = 0x0
7008 19:57:39.261778 WR_PRE = 0x1
7009 19:57:39.264790 WR_PST = 0x1
7010 19:57:39.265247 DBI_WR = 0x0
7011 19:57:39.268066 DBI_RD = 0x0
7012 19:57:39.268608 OTF = 0x1
7013 19:57:39.271683 ===================================
7014 19:57:39.274928 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7015 19:57:39.281583 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7016 19:57:39.284914 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7017 19:57:39.288408 ===================================
7018 19:57:39.291571 LPDDR4 DRAM CONFIGURATION
7019 19:57:39.294993 ===================================
7020 19:57:39.295546 EX_ROW_EN[0] = 0x10
7021 19:57:39.298116 EX_ROW_EN[1] = 0x0
7022 19:57:39.298674 LP4Y_EN = 0x0
7023 19:57:39.301339 WORK_FSP = 0x1
7024 19:57:39.301797 WL = 0x5
7025 19:57:39.304693 RL = 0x5
7026 19:57:39.308123 BL = 0x2
7027 19:57:39.308751 RPST = 0x0
7028 19:57:39.311211 RD_PRE = 0x0
7029 19:57:39.311757 WR_PRE = 0x1
7030 19:57:39.314596 WR_PST = 0x1
7031 19:57:39.314987 DBI_WR = 0x0
7032 19:57:39.317692 DBI_RD = 0x0
7033 19:57:39.318149 OTF = 0x1
7034 19:57:39.321195 ===================================
7035 19:57:39.327525 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7036 19:57:39.328066 ==
7037 19:57:39.331181 Dram Type= 6, Freq= 0, CH_0, rank 0
7038 19:57:39.334436 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7039 19:57:39.334991 ==
7040 19:57:39.337647 [Duty_Offset_Calibration]
7041 19:57:39.340725 B0:0 B1:2 CA:1
7042 19:57:39.341183
7043 19:57:39.344316 [DutyScan_Calibration_Flow] k_type=0
7044 19:57:39.352811
7045 19:57:39.353352 ==CLK 0==
7046 19:57:39.356496 Final CLK duty delay cell = 0
7047 19:57:39.359394 [0] MAX Duty = 5156%(X100), DQS PI = 22
7048 19:57:39.362927 [0] MIN Duty = 4907%(X100), DQS PI = 54
7049 19:57:39.366413 [0] AVG Duty = 5031%(X100)
7050 19:57:39.367002
7051 19:57:39.369875 CH0 CLK Duty spec in!! Max-Min= 249%
7052 19:57:39.372781 [DutyScan_Calibration_Flow] ====Done====
7053 19:57:39.373232
7054 19:57:39.375822 [DutyScan_Calibration_Flow] k_type=1
7055 19:57:39.392952
7056 19:57:39.393500 ==DQS 0 ==
7057 19:57:39.396257 Final DQS duty delay cell = 0
7058 19:57:39.399689 [0] MAX Duty = 5125%(X100), DQS PI = 22
7059 19:57:39.402920 [0] MIN Duty = 5031%(X100), DQS PI = 8
7060 19:57:39.403471 [0] AVG Duty = 5078%(X100)
7061 19:57:39.406755
7062 19:57:39.407303 ==DQS 1 ==
7063 19:57:39.409448 Final DQS duty delay cell = 0
7064 19:57:39.412916 [0] MAX Duty = 5031%(X100), DQS PI = 4
7065 19:57:39.416123 [0] MIN Duty = 4876%(X100), DQS PI = 16
7066 19:57:39.416847 [0] AVG Duty = 4953%(X100)
7067 19:57:39.419274
7068 19:57:39.423045 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7069 19:57:39.423628
7070 19:57:39.426282 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7071 19:57:39.429702 [DutyScan_Calibration_Flow] ====Done====
7072 19:57:39.430255
7073 19:57:39.432700 [DutyScan_Calibration_Flow] k_type=3
7074 19:57:39.450013
7075 19:57:39.450569 ==DQM 0 ==
7076 19:57:39.453133 Final DQM duty delay cell = 0
7077 19:57:39.456384 [0] MAX Duty = 5187%(X100), DQS PI = 22
7078 19:57:39.459836 [0] MIN Duty = 4907%(X100), DQS PI = 56
7079 19:57:39.463387 [0] AVG Duty = 5047%(X100)
7080 19:57:39.463939
7081 19:57:39.464364 ==DQM 1 ==
7082 19:57:39.466485 Final DQM duty delay cell = 0
7083 19:57:39.470156 [0] MAX Duty = 5031%(X100), DQS PI = 4
7084 19:57:39.473209 [0] MIN Duty = 4782%(X100), DQS PI = 14
7085 19:57:39.476401 [0] AVG Duty = 4906%(X100)
7086 19:57:39.476952
7087 19:57:39.479556 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7088 19:57:39.480015
7089 19:57:39.483222 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7090 19:57:39.486924 [DutyScan_Calibration_Flow] ====Done====
7091 19:57:39.487475
7092 19:57:39.489583 [DutyScan_Calibration_Flow] k_type=2
7093 19:57:39.506347
7094 19:57:39.506917 ==DQ 0 ==
7095 19:57:39.509687 Final DQ duty delay cell = 0
7096 19:57:39.513116 [0] MAX Duty = 5218%(X100), DQS PI = 18
7097 19:57:39.516404 [0] MIN Duty = 4938%(X100), DQS PI = 56
7098 19:57:39.516954 [0] AVG Duty = 5078%(X100)
7099 19:57:39.519326
7100 19:57:39.519779 ==DQ 1 ==
7101 19:57:39.523037 Final DQ duty delay cell = -4
7102 19:57:39.526376 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7103 19:57:39.529523 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7104 19:57:39.532651 [-4] AVG Duty = 4953%(X100)
7105 19:57:39.533204
7106 19:57:39.536050 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7107 19:57:39.536646
7108 19:57:39.539401 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7109 19:57:39.542893 [DutyScan_Calibration_Flow] ====Done====
7110 19:57:39.543508 ==
7111 19:57:39.545951 Dram Type= 6, Freq= 0, CH_1, rank 0
7112 19:57:39.549403 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7113 19:57:39.549961 ==
7114 19:57:39.552562 [Duty_Offset_Calibration]
7115 19:57:39.553024 B0:0 B1:4 CA:-5
7116 19:57:39.553458
7117 19:57:39.556300 [DutyScan_Calibration_Flow] k_type=0
7118 19:57:39.566750
7119 19:57:39.567321 ==CLK 0==
7120 19:57:39.570226 Final CLK duty delay cell = 0
7121 19:57:39.573448 [0] MAX Duty = 5156%(X100), DQS PI = 22
7122 19:57:39.576948 [0] MIN Duty = 4906%(X100), DQS PI = 50
7123 19:57:39.577500 [0] AVG Duty = 5031%(X100)
7124 19:57:39.580697
7125 19:57:39.583453 CH1 CLK Duty spec in!! Max-Min= 250%
7126 19:57:39.586758 [DutyScan_Calibration_Flow] ====Done====
7127 19:57:39.587326
7128 19:57:39.589869 [DutyScan_Calibration_Flow] k_type=1
7129 19:57:39.605816
7130 19:57:39.606368 ==DQS 0 ==
7131 19:57:39.609342 Final DQS duty delay cell = 0
7132 19:57:39.612892 [0] MAX Duty = 5156%(X100), DQS PI = 18
7133 19:57:39.615744 [0] MIN Duty = 4875%(X100), DQS PI = 42
7134 19:57:39.619058 [0] AVG Duty = 5015%(X100)
7135 19:57:39.619625
7136 19:57:39.620014 ==DQS 1 ==
7137 19:57:39.622404 Final DQS duty delay cell = -4
7138 19:57:39.625607 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7139 19:57:39.629008 [-4] MIN Duty = 4844%(X100), DQS PI = 42
7140 19:57:39.632615 [-4] AVG Duty = 4922%(X100)
7141 19:57:39.633190
7142 19:57:39.635673 CH1 DQS 0 Duty spec in!! Max-Min= 281%
7143 19:57:39.636308
7144 19:57:39.639194 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7145 19:57:39.642087 [DutyScan_Calibration_Flow] ====Done====
7146 19:57:39.642542
7147 19:57:39.645520 [DutyScan_Calibration_Flow] k_type=3
7148 19:57:39.661371
7149 19:57:39.661922 ==DQM 0 ==
7150 19:57:39.664665 Final DQM duty delay cell = -4
7151 19:57:39.668241 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7152 19:57:39.671381 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7153 19:57:39.674613 [-4] AVG Duty = 4937%(X100)
7154 19:57:39.675069
7155 19:57:39.675430 ==DQM 1 ==
7156 19:57:39.678116 Final DQM duty delay cell = -4
7157 19:57:39.681272 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7158 19:57:39.684491 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7159 19:57:39.688131 [-4] AVG Duty = 4984%(X100)
7160 19:57:39.688738
7161 19:57:39.691425 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7162 19:57:39.691978
7163 19:57:39.694726 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7164 19:57:39.697883 [DutyScan_Calibration_Flow] ====Done====
7165 19:57:39.698434
7166 19:57:39.700866 [DutyScan_Calibration_Flow] k_type=2
7167 19:57:39.719044
7168 19:57:39.719594 ==DQ 0 ==
7169 19:57:39.722068 Final DQ duty delay cell = 0
7170 19:57:39.725827 [0] MAX Duty = 5093%(X100), DQS PI = 20
7171 19:57:39.729004 [0] MIN Duty = 4938%(X100), DQS PI = 48
7172 19:57:39.729565 [0] AVG Duty = 5015%(X100)
7173 19:57:39.732210
7174 19:57:39.732774 ==DQ 1 ==
7175 19:57:39.735750 Final DQ duty delay cell = 0
7176 19:57:39.739020 [0] MAX Duty = 5031%(X100), DQS PI = 4
7177 19:57:39.742333 [0] MIN Duty = 4876%(X100), DQS PI = 30
7178 19:57:39.742920 [0] AVG Duty = 4953%(X100)
7179 19:57:39.743298
7180 19:57:39.745746 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7181 19:57:39.748688
7182 19:57:39.752120 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7183 19:57:39.755210 [DutyScan_Calibration_Flow] ====Done====
7184 19:57:39.758853 nWR fixed to 30
7185 19:57:39.759406 [ModeRegInit_LP4] CH0 RK0
7186 19:57:39.762008 [ModeRegInit_LP4] CH0 RK1
7187 19:57:39.766191 [ModeRegInit_LP4] CH1 RK0
7188 19:57:39.768691 [ModeRegInit_LP4] CH1 RK1
7189 19:57:39.769152 match AC timing 4
7190 19:57:39.772354 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7191 19:57:39.779043 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7192 19:57:39.782452 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7193 19:57:39.788803 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7194 19:57:39.792032 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7195 19:57:39.792701 [MiockJmeterHQA]
7196 19:57:39.793074
7197 19:57:39.795403 [DramcMiockJmeter] u1RxGatingPI = 0
7198 19:57:39.798802 0 : 4363, 4137
7199 19:57:39.799365 4 : 4363, 4137
7200 19:57:39.799809 8 : 4363, 4138
7201 19:57:39.802086 12 : 4252, 4027
7202 19:57:39.802645 16 : 4252, 4027
7203 19:57:39.805359 20 : 4255, 4029
7204 19:57:39.805964 24 : 4363, 4138
7205 19:57:39.808754 28 : 4252, 4027
7206 19:57:39.809221 32 : 4252, 4027
7207 19:57:39.811615 36 : 4253, 4026
7208 19:57:39.812149 40 : 4252, 4027
7209 19:57:39.812722 44 : 4252, 4027
7210 19:57:39.815479 48 : 4363, 4137
7211 19:57:39.816041 52 : 4363, 4137
7212 19:57:39.818770 56 : 4250, 4026
7213 19:57:39.819336 60 : 4250, 4027
7214 19:57:39.821693 64 : 4250, 4027
7215 19:57:39.822161 68 : 4250, 4026
7216 19:57:39.824906 72 : 4250, 4026
7217 19:57:39.825373 76 : 4360, 4138
7218 19:57:39.825746 80 : 4250, 4027
7219 19:57:39.828624 84 : 4250, 4027
7220 19:57:39.829183 88 : 4250, 4026
7221 19:57:39.831712 92 : 4250, 4027
7222 19:57:39.832208 96 : 4250, 4027
7223 19:57:39.834953 100 : 4361, 2260
7224 19:57:39.835420 104 : 4250, 0
7225 19:57:39.835808 108 : 4250, 0
7226 19:57:39.838772 112 : 4250, 0
7227 19:57:39.839332 116 : 4249, 0
7228 19:57:39.841631 120 : 4363, 0
7229 19:57:39.842101 124 : 4250, 0
7230 19:57:39.842473 128 : 4250, 0
7231 19:57:39.844959 132 : 4253, 0
7232 19:57:39.845430 136 : 4252, 0
7233 19:57:39.848084 140 : 4250, 0
7234 19:57:39.848599 144 : 4252, 0
7235 19:57:39.848973 148 : 4250, 0
7236 19:57:39.851579 152 : 4250, 0
7237 19:57:39.852108 156 : 4252, 0
7238 19:57:39.854812 160 : 4250, 0
7239 19:57:39.855513 164 : 4250, 0
7240 19:57:39.855910 168 : 4250, 0
7241 19:57:39.857996 172 : 4361, 0
7242 19:57:39.858463 176 : 4360, 0
7243 19:57:39.858834 180 : 4361, 0
7244 19:57:39.861564 184 : 4250, 0
7245 19:57:39.862046 188 : 4250, 0
7246 19:57:39.864753 192 : 4250, 0
7247 19:57:39.865316 196 : 4250, 0
7248 19:57:39.865690 200 : 4250, 0
7249 19:57:39.867989 204 : 4250, 0
7250 19:57:39.868504 208 : 4250, 0
7251 19:57:39.871875 212 : 4250, 0
7252 19:57:39.872508 216 : 4250, 0
7253 19:57:39.872885 220 : 4250, 483
7254 19:57:39.874853 224 : 4360, 4121
7255 19:57:39.875334 228 : 4255, 4029
7256 19:57:39.878342 232 : 4250, 4027
7257 19:57:39.878901 236 : 4363, 4140
7258 19:57:39.881836 240 : 4249, 4027
7259 19:57:39.882429 244 : 4250, 4026
7260 19:57:39.884867 248 : 4250, 4026
7261 19:57:39.885424 252 : 4255, 4032
7262 19:57:39.888396 256 : 4250, 4027
7263 19:57:39.889118 260 : 4250, 4026
7264 19:57:39.891729 264 : 4361, 4137
7265 19:57:39.892336 268 : 4250, 4026
7266 19:57:39.892716 272 : 4250, 4027
7267 19:57:39.894940 276 : 4360, 4137
7268 19:57:39.895496 280 : 4250, 4026
7269 19:57:39.898474 284 : 4250, 4027
7270 19:57:39.899028 288 : 4361, 4138
7271 19:57:39.901582 292 : 4250, 4027
7272 19:57:39.902142 296 : 4250, 4026
7273 19:57:39.904845 300 : 4250, 4027
7274 19:57:39.905409 304 : 4250, 4027
7275 19:57:39.908288 308 : 4250, 4027
7276 19:57:39.908842 312 : 4250, 4026
7277 19:57:39.911600 316 : 4361, 4137
7278 19:57:39.912154 320 : 4250, 4027
7279 19:57:39.914781 324 : 4250, 4027
7280 19:57:39.915241 328 : 4360, 4138
7281 19:57:39.915607 332 : 4250, 4027
7282 19:57:39.917908 336 : 4250, 3915
7283 19:57:39.918383 340 : 4361, 2407
7284 19:57:39.921328 344 : 4250, 2
7285 19:57:39.921788
7286 19:57:39.925182 MIOCK jitter meter ch=0
7287 19:57:39.925749
7288 19:57:39.926118 1T = (344-104) = 240 dly cells
7289 19:57:39.931799 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7290 19:57:39.932400 ==
7291 19:57:39.934323 Dram Type= 6, Freq= 0, CH_0, rank 0
7292 19:57:39.938383 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7293 19:57:39.941091 ==
7294 19:57:39.944701 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7295 19:57:39.947804 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7296 19:57:39.954313 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7297 19:57:39.957607 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7298 19:57:39.967285 [CA 0] Center 41 (11~72) winsize 62
7299 19:57:39.970649 [CA 1] Center 41 (11~72) winsize 62
7300 19:57:39.974088 [CA 2] Center 37 (7~67) winsize 61
7301 19:57:39.976998 [CA 3] Center 37 (7~67) winsize 61
7302 19:57:39.980417 [CA 4] Center 35 (5~66) winsize 62
7303 19:57:39.983656 [CA 5] Center 35 (5~65) winsize 61
7304 19:57:39.984217
7305 19:57:39.986948 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7306 19:57:39.987402
7307 19:57:39.990685 [CATrainingPosCal] consider 1 rank data
7308 19:57:39.994151 u2DelayCellTimex100 = 271/100 ps
7309 19:57:39.996971 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7310 19:57:40.004014 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7311 19:57:40.007244 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7312 19:57:40.010486 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7313 19:57:40.013759 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7314 19:57:40.017066 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7315 19:57:40.017614
7316 19:57:40.020337 CA PerBit enable=1, Macro0, CA PI delay=35
7317 19:57:40.020895
7318 19:57:40.023870 [CBTSetCACLKResult] CA Dly = 35
7319 19:57:40.027081 CS Dly: 11 (0~42)
7320 19:57:40.030542 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7321 19:57:40.033677 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7322 19:57:40.034133 ==
7323 19:57:40.036837 Dram Type= 6, Freq= 0, CH_0, rank 1
7324 19:57:40.040106 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7325 19:57:40.043222 ==
7326 19:57:40.046814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7327 19:57:40.050411 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7328 19:57:40.056749 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7329 19:57:40.063459 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7330 19:57:40.070011 [CA 0] Center 42 (12~73) winsize 62
7331 19:57:40.073726 [CA 1] Center 41 (11~72) winsize 62
7332 19:57:40.076275 [CA 2] Center 38 (8~68) winsize 61
7333 19:57:40.079888 [CA 3] Center 37 (7~67) winsize 61
7334 19:57:40.083246 [CA 4] Center 35 (5~65) winsize 61
7335 19:57:40.086567 [CA 5] Center 35 (5~66) winsize 62
7336 19:57:40.087113
7337 19:57:40.089577 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7338 19:57:40.090127
7339 19:57:40.093312 [CATrainingPosCal] consider 2 rank data
7340 19:57:40.096618 u2DelayCellTimex100 = 271/100 ps
7341 19:57:40.103379 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7342 19:57:40.106729 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7343 19:57:40.109882 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7344 19:57:40.113132 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7345 19:57:40.116531 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7346 19:57:40.119823 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7347 19:57:40.120424
7348 19:57:40.123144 CA PerBit enable=1, Macro0, CA PI delay=35
7349 19:57:40.123696
7350 19:57:40.126301 [CBTSetCACLKResult] CA Dly = 35
7351 19:57:40.129960 CS Dly: 11 (0~43)
7352 19:57:40.132897 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7353 19:57:40.136387 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7354 19:57:40.136932
7355 19:57:40.139688 ----->DramcWriteLeveling(PI) begin...
7356 19:57:40.140424 ==
7357 19:57:40.142713 Dram Type= 6, Freq= 0, CH_0, rank 0
7358 19:57:40.149574 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7359 19:57:40.150205 ==
7360 19:57:40.152758 Write leveling (Byte 0): 27 => 27
7361 19:57:40.153212 Write leveling (Byte 1): 27 => 27
7362 19:57:40.156087 DramcWriteLeveling(PI) end<-----
7363 19:57:40.156692
7364 19:57:40.159279 ==
7365 19:57:40.159748 Dram Type= 6, Freq= 0, CH_0, rank 0
7366 19:57:40.165959 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7367 19:57:40.166412 ==
7368 19:57:40.169026 [Gating] SW mode calibration
7369 19:57:40.176029 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7370 19:57:40.179330 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7371 19:57:40.185975 0 12 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7372 19:57:40.189027 0 12 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (0 0)
7373 19:57:40.192377 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
7374 19:57:40.199291 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7375 19:57:40.202394 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7376 19:57:40.205591 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7377 19:57:40.212397 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7378 19:57:40.215664 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7379 19:57:40.218922 0 13 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7380 19:57:40.225538 0 13 4 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
7381 19:57:40.228956 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7382 19:57:40.232749 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7383 19:57:40.238960 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7384 19:57:40.242368 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7385 19:57:40.245807 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7386 19:57:40.252352 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7387 19:57:40.255527 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7388 19:57:40.258787 0 14 4 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
7389 19:57:40.265233 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7390 19:57:40.268842 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7391 19:57:40.272021 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7392 19:57:40.278890 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7393 19:57:40.282434 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7394 19:57:40.285167 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7395 19:57:40.288519 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7396 19:57:40.295069 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7397 19:57:40.298603 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7398 19:57:40.301700 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7399 19:57:40.308387 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7400 19:57:40.311734 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7401 19:57:40.315092 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7402 19:57:40.321777 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7403 19:57:40.325439 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7404 19:57:40.328229 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7405 19:57:40.335066 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 19:57:40.338574 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 19:57:40.341412 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 19:57:40.348487 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 19:57:40.351741 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 19:57:40.354608 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7411 19:57:40.361334 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7412 19:57:40.364558 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7413 19:57:40.368069 Total UI for P1: 0, mck2ui 16
7414 19:57:40.371345 best dqsien dly found for B0: ( 1, 0, 30)
7415 19:57:40.374771 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7416 19:57:40.381517 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7417 19:57:40.382068 Total UI for P1: 0, mck2ui 16
7418 19:57:40.387967 best dqsien dly found for B1: ( 1, 1, 4)
7419 19:57:40.391126 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7420 19:57:40.394673 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7421 19:57:40.395230
7422 19:57:40.398001 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7423 19:57:40.400920 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7424 19:57:40.404249 [Gating] SW calibration Done
7425 19:57:40.404817 ==
7426 19:57:40.407480 Dram Type= 6, Freq= 0, CH_0, rank 0
7427 19:57:40.411010 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7428 19:57:40.411598 ==
7429 19:57:40.414530 RX Vref Scan: 0
7430 19:57:40.415091
7431 19:57:40.415480 RX Vref 0 -> 0, step: 1
7432 19:57:40.415822
7433 19:57:40.417805 RX Delay 0 -> 252, step: 8
7434 19:57:40.421212 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
7435 19:57:40.427750 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7436 19:57:40.430872 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7437 19:57:40.434127 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7438 19:57:40.437643 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7439 19:57:40.440811 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7440 19:57:40.447502 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7441 19:57:40.451003 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7442 19:57:40.454016 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7443 19:57:40.457453 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7444 19:57:40.460666 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7445 19:57:40.467369 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7446 19:57:40.470926 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7447 19:57:40.474197 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7448 19:57:40.477230 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7449 19:57:40.480801 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7450 19:57:40.484456 ==
7451 19:57:40.487396 Dram Type= 6, Freq= 0, CH_0, rank 0
7452 19:57:40.490516 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7453 19:57:40.491078 ==
7454 19:57:40.491451 DQS Delay:
7455 19:57:40.494650 DQS0 = 0, DQS1 = 0
7456 19:57:40.495211 DQM Delay:
7457 19:57:40.497219 DQM0 = 129, DQM1 = 123
7458 19:57:40.497776 DQ Delay:
7459 19:57:40.500767 DQ0 =123, DQ1 =131, DQ2 =127, DQ3 =127
7460 19:57:40.504029 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7461 19:57:40.507138 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
7462 19:57:40.510438 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7463 19:57:40.511012
7464 19:57:40.511381
7465 19:57:40.511720 ==
7466 19:57:40.513889 Dram Type= 6, Freq= 0, CH_0, rank 0
7467 19:57:40.520688 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7468 19:57:40.521258 ==
7469 19:57:40.521628
7470 19:57:40.522099
7471 19:57:40.522497 TX Vref Scan disable
7472 19:57:40.524011 == TX Byte 0 ==
7473 19:57:40.527604 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7474 19:57:40.533999 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7475 19:57:40.534551 == TX Byte 1 ==
7476 19:57:40.537517 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7477 19:57:40.543989 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7478 19:57:40.544499 ==
7479 19:57:40.547799 Dram Type= 6, Freq= 0, CH_0, rank 0
7480 19:57:40.550867 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7481 19:57:40.551433 ==
7482 19:57:40.563754
7483 19:57:40.567009 TX Vref early break, caculate TX vref
7484 19:57:40.570413 TX Vref=16, minBit 11, minWin=21, winSum=373
7485 19:57:40.573672 TX Vref=18, minBit 9, minWin=22, winSum=386
7486 19:57:40.576824 TX Vref=20, minBit 8, minWin=23, winSum=392
7487 19:57:40.580643 TX Vref=22, minBit 8, minWin=24, winSum=404
7488 19:57:40.583899 TX Vref=24, minBit 8, minWin=24, winSum=409
7489 19:57:40.590312 TX Vref=26, minBit 8, minWin=24, winSum=417
7490 19:57:40.594012 TX Vref=28, minBit 0, minWin=25, winSum=418
7491 19:57:40.597090 TX Vref=30, minBit 0, minWin=25, winSum=412
7492 19:57:40.600351 TX Vref=32, minBit 1, minWin=24, winSum=403
7493 19:57:40.603810 TX Vref=34, minBit 1, minWin=24, winSum=398
7494 19:57:40.607098 TX Vref=36, minBit 1, minWin=23, winSum=383
7495 19:57:40.613447 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
7496 19:57:40.614011
7497 19:57:40.617102 Final TX Range 0 Vref 28
7498 19:57:40.617668
7499 19:57:40.618039 ==
7500 19:57:40.620381 Dram Type= 6, Freq= 0, CH_0, rank 0
7501 19:57:40.623264 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7502 19:57:40.623731 ==
7503 19:57:40.624099
7504 19:57:40.626920
7505 19:57:40.627490 TX Vref Scan disable
7506 19:57:40.633470 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7507 19:57:40.634068 == TX Byte 0 ==
7508 19:57:40.636763 u2DelayCellOfst[0]=10 cells (3 PI)
7509 19:57:40.640153 u2DelayCellOfst[1]=18 cells (5 PI)
7510 19:57:40.643145 u2DelayCellOfst[2]=14 cells (4 PI)
7511 19:57:40.646963 u2DelayCellOfst[3]=10 cells (3 PI)
7512 19:57:40.650394 u2DelayCellOfst[4]=7 cells (2 PI)
7513 19:57:40.653569 u2DelayCellOfst[5]=0 cells (0 PI)
7514 19:57:40.656929 u2DelayCellOfst[6]=18 cells (5 PI)
7515 19:57:40.660282 u2DelayCellOfst[7]=18 cells (5 PI)
7516 19:57:40.663729 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7517 19:57:40.666832 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7518 19:57:40.670174 == TX Byte 1 ==
7519 19:57:40.673831 u2DelayCellOfst[8]=3 cells (1 PI)
7520 19:57:40.674387 u2DelayCellOfst[9]=0 cells (0 PI)
7521 19:57:40.676589 u2DelayCellOfst[10]=10 cells (3 PI)
7522 19:57:40.680216 u2DelayCellOfst[11]=7 cells (2 PI)
7523 19:57:40.683459 u2DelayCellOfst[12]=18 cells (5 PI)
7524 19:57:40.686789 u2DelayCellOfst[13]=14 cells (4 PI)
7525 19:57:40.690215 u2DelayCellOfst[14]=18 cells (5 PI)
7526 19:57:40.693279 u2DelayCellOfst[15]=18 cells (5 PI)
7527 19:57:40.696691 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7528 19:57:40.703315 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7529 19:57:40.703866 DramC Write-DBI on
7530 19:57:40.704294 ==
7531 19:57:40.706592 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 19:57:40.713226 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7533 19:57:40.713783 ==
7534 19:57:40.714152
7535 19:57:40.714491
7536 19:57:40.714815 TX Vref Scan disable
7537 19:57:40.716876 == TX Byte 0 ==
7538 19:57:40.720626 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7539 19:57:40.723506 == TX Byte 1 ==
7540 19:57:40.727110 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7541 19:57:40.730192 DramC Write-DBI off
7542 19:57:40.730652
7543 19:57:40.731015 [DATLAT]
7544 19:57:40.731390 Freq=1600, CH0 RK0
7545 19:57:40.731921
7546 19:57:40.733466 DATLAT Default: 0xf
7547 19:57:40.733924 0, 0xFFFF, sum = 0
7548 19:57:40.737060 1, 0xFFFF, sum = 0
7549 19:57:40.740623 2, 0xFFFF, sum = 0
7550 19:57:40.741178 3, 0xFFFF, sum = 0
7551 19:57:40.743451 4, 0xFFFF, sum = 0
7552 19:57:40.743918 5, 0xFFFF, sum = 0
7553 19:57:40.747100 6, 0xFFFF, sum = 0
7554 19:57:40.747665 7, 0xFFFF, sum = 0
7555 19:57:40.750122 8, 0xFFFF, sum = 0
7556 19:57:40.750690 9, 0xFFFF, sum = 0
7557 19:57:40.753360 10, 0xFFFF, sum = 0
7558 19:57:40.753886 11, 0xFFFF, sum = 0
7559 19:57:40.756729 12, 0xBFF, sum = 0
7560 19:57:40.757238 13, 0x0, sum = 1
7561 19:57:40.759890 14, 0x0, sum = 2
7562 19:57:40.760437 15, 0x0, sum = 3
7563 19:57:40.763007 16, 0x0, sum = 4
7564 19:57:40.763547 best_step = 14
7565 19:57:40.763916
7566 19:57:40.764309 ==
7567 19:57:40.766270 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 19:57:40.769752 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7569 19:57:40.772980 ==
7570 19:57:40.773441 RX Vref Scan: 1
7571 19:57:40.773808
7572 19:57:40.776329 Set Vref Range= 24 -> 127
7573 19:57:40.776795
7574 19:57:40.780022 RX Vref 24 -> 127, step: 1
7575 19:57:40.780674
7576 19:57:40.781053 RX Delay 11 -> 252, step: 4
7577 19:57:40.781401
7578 19:57:40.783339 Set Vref, RX VrefLevel [Byte0]: 24
7579 19:57:40.786659 [Byte1]: 24
7580 19:57:40.790567
7581 19:57:40.791131 Set Vref, RX VrefLevel [Byte0]: 25
7582 19:57:40.793891 [Byte1]: 25
7583 19:57:40.798066
7584 19:57:40.798628 Set Vref, RX VrefLevel [Byte0]: 26
7585 19:57:40.801365 [Byte1]: 26
7586 19:57:40.805633
7587 19:57:40.806196 Set Vref, RX VrefLevel [Byte0]: 27
7588 19:57:40.808713 [Byte1]: 27
7589 19:57:40.813250
7590 19:57:40.813809 Set Vref, RX VrefLevel [Byte0]: 28
7591 19:57:40.816273 [Byte1]: 28
7592 19:57:40.820578
7593 19:57:40.821054 Set Vref, RX VrefLevel [Byte0]: 29
7594 19:57:40.823774 [Byte1]: 29
7595 19:57:40.828565
7596 19:57:40.829123 Set Vref, RX VrefLevel [Byte0]: 30
7597 19:57:40.831842 [Byte1]: 30
7598 19:57:40.835871
7599 19:57:40.836414 Set Vref, RX VrefLevel [Byte0]: 31
7600 19:57:40.839330 [Byte1]: 31
7601 19:57:40.843828
7602 19:57:40.844434 Set Vref, RX VrefLevel [Byte0]: 32
7603 19:57:40.846918 [Byte1]: 32
7604 19:57:40.851374
7605 19:57:40.851935 Set Vref, RX VrefLevel [Byte0]: 33
7606 19:57:40.854431 [Byte1]: 33
7607 19:57:40.858939
7608 19:57:40.859500 Set Vref, RX VrefLevel [Byte0]: 34
7609 19:57:40.861981 [Byte1]: 34
7610 19:57:40.866497
7611 19:57:40.867318 Set Vref, RX VrefLevel [Byte0]: 35
7612 19:57:40.869918 [Byte1]: 35
7613 19:57:40.874262
7614 19:57:40.874813 Set Vref, RX VrefLevel [Byte0]: 36
7615 19:57:40.877399 [Byte1]: 36
7616 19:57:40.881828
7617 19:57:40.882379 Set Vref, RX VrefLevel [Byte0]: 37
7618 19:57:40.884893 [Byte1]: 37
7619 19:57:40.889223
7620 19:57:40.889775 Set Vref, RX VrefLevel [Byte0]: 38
7621 19:57:40.892545 [Byte1]: 38
7622 19:57:40.896724
7623 19:57:40.897185 Set Vref, RX VrefLevel [Byte0]: 39
7624 19:57:40.900251 [Byte1]: 39
7625 19:57:40.904519
7626 19:57:40.905069 Set Vref, RX VrefLevel [Byte0]: 40
7627 19:57:40.907748 [Byte1]: 40
7628 19:57:40.912034
7629 19:57:40.912554 Set Vref, RX VrefLevel [Byte0]: 41
7630 19:57:40.915454 [Byte1]: 41
7631 19:57:40.919527
7632 19:57:40.919988 Set Vref, RX VrefLevel [Byte0]: 42
7633 19:57:40.922778 [Byte1]: 42
7634 19:57:40.927408
7635 19:57:40.927975 Set Vref, RX VrefLevel [Byte0]: 43
7636 19:57:40.930892 [Byte1]: 43
7637 19:57:40.934862
7638 19:57:40.935333 Set Vref, RX VrefLevel [Byte0]: 44
7639 19:57:40.938414 [Byte1]: 44
7640 19:57:40.942683
7641 19:57:40.943246 Set Vref, RX VrefLevel [Byte0]: 45
7642 19:57:40.945903 [Byte1]: 45
7643 19:57:40.950440
7644 19:57:40.951006 Set Vref, RX VrefLevel [Byte0]: 46
7645 19:57:40.953278 [Byte1]: 46
7646 19:57:40.957911
7647 19:57:40.958474 Set Vref, RX VrefLevel [Byte0]: 47
7648 19:57:40.960852 [Byte1]: 47
7649 19:57:40.965356
7650 19:57:40.965826 Set Vref, RX VrefLevel [Byte0]: 48
7651 19:57:40.968835 [Byte1]: 48
7652 19:57:40.973163
7653 19:57:40.973729 Set Vref, RX VrefLevel [Byte0]: 49
7654 19:57:40.976161 [Byte1]: 49
7655 19:57:40.980822
7656 19:57:40.981448 Set Vref, RX VrefLevel [Byte0]: 50
7657 19:57:40.984056 [Byte1]: 50
7658 19:57:40.988279
7659 19:57:40.988843 Set Vref, RX VrefLevel [Byte0]: 51
7660 19:57:40.991860 [Byte1]: 51
7661 19:57:40.995835
7662 19:57:40.996443 Set Vref, RX VrefLevel [Byte0]: 52
7663 19:57:40.999251 [Byte1]: 52
7664 19:57:41.003498
7665 19:57:41.004062 Set Vref, RX VrefLevel [Byte0]: 53
7666 19:57:41.006546 [Byte1]: 53
7667 19:57:41.011118
7668 19:57:41.011695 Set Vref, RX VrefLevel [Byte0]: 54
7669 19:57:41.014408 [Byte1]: 54
7670 19:57:41.018739
7671 19:57:41.019308 Set Vref, RX VrefLevel [Byte0]: 55
7672 19:57:41.021718 [Byte1]: 55
7673 19:57:41.026352
7674 19:57:41.026919 Set Vref, RX VrefLevel [Byte0]: 56
7675 19:57:41.029305 [Byte1]: 56
7676 19:57:41.033890
7677 19:57:41.034454 Set Vref, RX VrefLevel [Byte0]: 57
7678 19:57:41.037036 [Byte1]: 57
7679 19:57:41.041489
7680 19:57:41.042051 Set Vref, RX VrefLevel [Byte0]: 58
7681 19:57:41.044866 [Byte1]: 58
7682 19:57:41.049140
7683 19:57:41.049706 Set Vref, RX VrefLevel [Byte0]: 59
7684 19:57:41.052561 [Byte1]: 59
7685 19:57:41.057033
7686 19:57:41.057505 Set Vref, RX VrefLevel [Byte0]: 60
7687 19:57:41.060060 [Byte1]: 60
7688 19:57:41.064281
7689 19:57:41.064758 Set Vref, RX VrefLevel [Byte0]: 61
7690 19:57:41.067489 [Byte1]: 61
7691 19:57:41.072057
7692 19:57:41.072675 Set Vref, RX VrefLevel [Byte0]: 62
7693 19:57:41.075680 [Byte1]: 62
7694 19:57:41.079776
7695 19:57:41.080409 Set Vref, RX VrefLevel [Byte0]: 63
7696 19:57:41.083214 [Byte1]: 63
7697 19:57:41.087318
7698 19:57:41.087892 Set Vref, RX VrefLevel [Byte0]: 64
7699 19:57:41.090509 [Byte1]: 64
7700 19:57:41.094698
7701 19:57:41.095249 Set Vref, RX VrefLevel [Byte0]: 65
7702 19:57:41.098011 [Byte1]: 65
7703 19:57:41.102214
7704 19:57:41.102675 Set Vref, RX VrefLevel [Byte0]: 66
7705 19:57:41.105575 [Byte1]: 66
7706 19:57:41.110126
7707 19:57:41.110679 Set Vref, RX VrefLevel [Byte0]: 67
7708 19:57:41.113472 [Byte1]: 67
7709 19:57:41.117862
7710 19:57:41.118414 Set Vref, RX VrefLevel [Byte0]: 68
7711 19:57:41.121169 [Byte1]: 68
7712 19:57:41.125234
7713 19:57:41.125794 Set Vref, RX VrefLevel [Byte0]: 69
7714 19:57:41.128465 [Byte1]: 69
7715 19:57:41.132675
7716 19:57:41.133137 Set Vref, RX VrefLevel [Byte0]: 70
7717 19:57:41.136304 [Byte1]: 70
7718 19:57:41.140319
7719 19:57:41.140795 Set Vref, RX VrefLevel [Byte0]: 71
7720 19:57:41.143634 [Byte1]: 71
7721 19:57:41.147993
7722 19:57:41.148487 Final RX Vref Byte 0 = 54 to rank0
7723 19:57:41.151466 Final RX Vref Byte 1 = 55 to rank0
7724 19:57:41.154993 Final RX Vref Byte 0 = 54 to rank1
7725 19:57:41.158078 Final RX Vref Byte 1 = 55 to rank1==
7726 19:57:41.161096 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 19:57:41.168258 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7728 19:57:41.169035 ==
7729 19:57:41.169429 DQS Delay:
7730 19:57:41.169772 DQS0 = 0, DQS1 = 0
7731 19:57:41.171740 DQM Delay:
7732 19:57:41.172244 DQM0 = 126, DQM1 = 120
7733 19:57:41.174718 DQ Delay:
7734 19:57:41.177933 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7735 19:57:41.181472 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7736 19:57:41.184375 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7737 19:57:41.188127 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7738 19:57:41.188764
7739 19:57:41.189130
7740 19:57:41.189466
7741 19:57:41.191164 [DramC_TX_OE_Calibration] TA2
7742 19:57:41.194792 Original DQ_B0 (3 6) =30, OEN = 27
7743 19:57:41.198201 Original DQ_B1 (3 6) =30, OEN = 27
7744 19:57:41.201548 24, 0x0, End_B0=24 End_B1=24
7745 19:57:41.202112 25, 0x0, End_B0=25 End_B1=25
7746 19:57:41.204566 26, 0x0, End_B0=26 End_B1=26
7747 19:57:41.207908 27, 0x0, End_B0=27 End_B1=27
7748 19:57:41.211185 28, 0x0, End_B0=28 End_B1=28
7749 19:57:41.214636 29, 0x0, End_B0=29 End_B1=29
7750 19:57:41.215190 30, 0x0, End_B0=30 End_B1=30
7751 19:57:41.217964 31, 0x4141, End_B0=30 End_B1=30
7752 19:57:41.221053 Byte0 end_step=30 best_step=27
7753 19:57:41.224377 Byte1 end_step=30 best_step=27
7754 19:57:41.227983 Byte0 TX OE(2T, 0.5T) = (3, 3)
7755 19:57:41.230772 Byte1 TX OE(2T, 0.5T) = (3, 3)
7756 19:57:41.231336
7757 19:57:41.231821
7758 19:57:41.237376 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7759 19:57:41.240954 CH0 RK0: MR19=303, MR18=1A1A
7760 19:57:41.247737 CH0_RK0: MR19=0x303, MR18=0x1A1A, DQSOSC=396, MR23=63, INC=23, DEC=15
7761 19:57:41.248353
7762 19:57:41.250833 ----->DramcWriteLeveling(PI) begin...
7763 19:57:41.251405 ==
7764 19:57:41.253960 Dram Type= 6, Freq= 0, CH_0, rank 1
7765 19:57:41.257632 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7766 19:57:41.258202 ==
7767 19:57:41.260519 Write leveling (Byte 0): 29 => 29
7768 19:57:41.263922 Write leveling (Byte 1): 25 => 25
7769 19:57:41.267255 DramcWriteLeveling(PI) end<-----
7770 19:57:41.267811
7771 19:57:41.268235 ==
7772 19:57:41.270500 Dram Type= 6, Freq= 0, CH_0, rank 1
7773 19:57:41.274461 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7774 19:57:41.275013 ==
7775 19:57:41.277089 [Gating] SW mode calibration
7776 19:57:41.284093 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7777 19:57:41.290719 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7778 19:57:41.293832 0 12 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
7779 19:57:41.300635 0 12 4 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7780 19:57:41.304116 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7781 19:57:41.307695 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7782 19:57:41.313975 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7783 19:57:41.317498 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7784 19:57:41.320468 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7785 19:57:41.327209 0 12 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7786 19:57:41.330123 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 1)
7787 19:57:41.333620 0 13 4 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
7788 19:57:41.337540 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7789 19:57:41.343420 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7790 19:57:41.346981 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7791 19:57:41.350483 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7792 19:57:41.356809 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7793 19:57:41.360538 0 13 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7794 19:57:41.363841 0 14 0 | B1->B0 | 2323 4141 | 0 0 | (0 0) (1 1)
7795 19:57:41.370111 0 14 4 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7796 19:57:41.373920 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7797 19:57:41.376994 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7798 19:57:41.383785 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7799 19:57:41.386708 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7800 19:57:41.390063 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7801 19:57:41.396286 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7802 19:57:41.399569 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7803 19:57:41.403517 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7804 19:57:41.409898 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7805 19:57:41.413341 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7806 19:57:41.416660 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7807 19:57:41.422966 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7808 19:57:41.426597 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7809 19:57:41.429450 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 19:57:41.436666 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7811 19:57:41.439940 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7812 19:57:41.442862 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7813 19:57:41.449197 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 19:57:41.452979 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 19:57:41.455623 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 19:57:41.462569 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7817 19:57:41.465636 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7818 19:57:41.469152 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7819 19:57:41.475779 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7820 19:57:41.479180 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7821 19:57:41.482451 Total UI for P1: 0, mck2ui 16
7822 19:57:41.485502 best dqsien dly found for B0: ( 1, 0, 30)
7823 19:57:41.488941 Total UI for P1: 0, mck2ui 16
7824 19:57:41.492312 best dqsien dly found for B1: ( 1, 1, 2)
7825 19:57:41.495617 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7826 19:57:41.498569 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7827 19:57:41.499042
7828 19:57:41.502287 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7829 19:57:41.505652 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7830 19:57:41.508545 [Gating] SW calibration Done
7831 19:57:41.509007 ==
7832 19:57:41.512301 Dram Type= 6, Freq= 0, CH_0, rank 1
7833 19:57:41.515207 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7834 19:57:41.518670 ==
7835 19:57:41.519233 RX Vref Scan: 0
7836 19:57:41.519600
7837 19:57:41.522247 RX Vref 0 -> 0, step: 1
7838 19:57:41.522809
7839 19:57:41.525051 RX Delay 0 -> 252, step: 8
7840 19:57:41.529060 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7841 19:57:41.532054 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7842 19:57:41.535483 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7843 19:57:41.538889 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7844 19:57:41.542144 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7845 19:57:41.548650 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7846 19:57:41.552128 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7847 19:57:41.555012 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7848 19:57:41.558396 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7849 19:57:41.564958 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7850 19:57:41.568103 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7851 19:57:41.571756 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7852 19:57:41.575169 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7853 19:57:41.578071 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7854 19:57:41.585070 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7855 19:57:41.588369 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7856 19:57:41.588934 ==
7857 19:57:41.591418 Dram Type= 6, Freq= 0, CH_0, rank 1
7858 19:57:41.594828 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7859 19:57:41.595395 ==
7860 19:57:41.598097 DQS Delay:
7861 19:57:41.598607 DQS0 = 0, DQS1 = 0
7862 19:57:41.599086 DQM Delay:
7863 19:57:41.601201 DQM0 = 130, DQM1 = 124
7864 19:57:41.601675 DQ Delay:
7865 19:57:41.604560 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7866 19:57:41.608270 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7867 19:57:41.615063 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7868 19:57:41.618051 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7869 19:57:41.618610
7870 19:57:41.619168
7871 19:57:41.619590 ==
7872 19:57:41.621063 Dram Type= 6, Freq= 0, CH_0, rank 1
7873 19:57:41.624528 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7874 19:57:41.625081 ==
7875 19:57:41.625466
7876 19:57:41.625808
7877 19:57:41.627463 TX Vref Scan disable
7878 19:57:41.630876 == TX Byte 0 ==
7879 19:57:41.634587 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7880 19:57:41.637769 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7881 19:57:41.641145 == TX Byte 1 ==
7882 19:57:41.644512 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7883 19:57:41.647508 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7884 19:57:41.648083 ==
7885 19:57:41.651125 Dram Type= 6, Freq= 0, CH_0, rank 1
7886 19:57:41.654401 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7887 19:57:41.657043 ==
7888 19:57:41.669948
7889 19:57:41.672988 TX Vref early break, caculate TX vref
7890 19:57:41.676724 TX Vref=16, minBit 8, minWin=22, winSum=373
7891 19:57:41.679853 TX Vref=18, minBit 8, minWin=22, winSum=379
7892 19:57:41.683284 TX Vref=20, minBit 9, minWin=23, winSum=389
7893 19:57:41.686616 TX Vref=22, minBit 1, minWin=24, winSum=399
7894 19:57:41.689638 TX Vref=24, minBit 7, minWin=24, winSum=403
7895 19:57:41.696558 TX Vref=26, minBit 1, minWin=24, winSum=414
7896 19:57:41.699519 TX Vref=28, minBit 1, minWin=25, winSum=413
7897 19:57:41.702915 TX Vref=30, minBit 0, minWin=25, winSum=413
7898 19:57:41.706321 TX Vref=32, minBit 8, minWin=23, winSum=401
7899 19:57:41.709944 TX Vref=34, minBit 8, minWin=23, winSum=393
7900 19:57:41.712747 TX Vref=36, minBit 8, minWin=23, winSum=386
7901 19:57:41.719501 [TxChooseVref] Worse bit 1, Min win 25, Win sum 413, Final Vref 28
7902 19:57:41.720063
7903 19:57:41.722656 Final TX Range 0 Vref 28
7904 19:57:41.723218
7905 19:57:41.723680 ==
7906 19:57:41.726107 Dram Type= 6, Freq= 0, CH_0, rank 1
7907 19:57:41.729742 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7908 19:57:41.730361 ==
7909 19:57:41.732431
7910 19:57:41.732890
7911 19:57:41.733256 TX Vref Scan disable
7912 19:57:41.739485 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7913 19:57:41.740049 == TX Byte 0 ==
7914 19:57:41.742765 u2DelayCellOfst[0]=14 cells (4 PI)
7915 19:57:41.745659 u2DelayCellOfst[1]=18 cells (5 PI)
7916 19:57:41.749100 u2DelayCellOfst[2]=14 cells (4 PI)
7917 19:57:41.752780 u2DelayCellOfst[3]=14 cells (4 PI)
7918 19:57:41.756075 u2DelayCellOfst[4]=10 cells (3 PI)
7919 19:57:41.759336 u2DelayCellOfst[5]=0 cells (0 PI)
7920 19:57:41.763105 u2DelayCellOfst[6]=18 cells (5 PI)
7921 19:57:41.765935 u2DelayCellOfst[7]=18 cells (5 PI)
7922 19:57:41.768979 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7923 19:57:41.772432 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7924 19:57:41.775578 == TX Byte 1 ==
7925 19:57:41.779012 u2DelayCellOfst[8]=3 cells (1 PI)
7926 19:57:41.782544 u2DelayCellOfst[9]=0 cells (0 PI)
7927 19:57:41.785690 u2DelayCellOfst[10]=10 cells (3 PI)
7928 19:57:41.788998 u2DelayCellOfst[11]=3 cells (1 PI)
7929 19:57:41.789604 u2DelayCellOfst[12]=18 cells (5 PI)
7930 19:57:41.792381 u2DelayCellOfst[13]=18 cells (5 PI)
7931 19:57:41.795931 u2DelayCellOfst[14]=21 cells (6 PI)
7932 19:57:41.798832 u2DelayCellOfst[15]=18 cells (5 PI)
7933 19:57:41.805691 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7934 19:57:41.808974 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7935 19:57:41.809434 DramC Write-DBI on
7936 19:57:41.812552 ==
7937 19:57:41.813114 Dram Type= 6, Freq= 0, CH_0, rank 1
7938 19:57:41.818809 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7939 19:57:41.819368 ==
7940 19:57:41.819737
7941 19:57:41.820078
7942 19:57:41.822010 TX Vref Scan disable
7943 19:57:41.822466 == TX Byte 0 ==
7944 19:57:41.828895 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7945 19:57:41.829460 == TX Byte 1 ==
7946 19:57:41.832113 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7947 19:57:41.835455 DramC Write-DBI off
7948 19:57:41.836053
7949 19:57:41.836683 [DATLAT]
7950 19:57:41.838489 Freq=1600, CH0 RK1
7951 19:57:41.838951
7952 19:57:41.839313 DATLAT Default: 0xe
7953 19:57:41.842184 0, 0xFFFF, sum = 0
7954 19:57:41.842887 1, 0xFFFF, sum = 0
7955 19:57:41.845277 2, 0xFFFF, sum = 0
7956 19:57:41.845771 3, 0xFFFF, sum = 0
7957 19:57:41.848504 4, 0xFFFF, sum = 0
7958 19:57:41.849011 5, 0xFFFF, sum = 0
7959 19:57:41.851840 6, 0xFFFF, sum = 0
7960 19:57:41.852351 7, 0xFFFF, sum = 0
7961 19:57:41.855283 8, 0xFFFF, sum = 0
7962 19:57:41.858515 9, 0xFFFF, sum = 0
7963 19:57:41.858986 10, 0xFFFF, sum = 0
7964 19:57:41.862243 11, 0xFFFF, sum = 0
7965 19:57:41.862812 12, 0x8FFF, sum = 0
7966 19:57:41.865440 13, 0x0, sum = 1
7967 19:57:41.866010 14, 0x0, sum = 2
7968 19:57:41.868451 15, 0x0, sum = 3
7969 19:57:41.868920 16, 0x0, sum = 4
7970 19:57:41.869292 best_step = 14
7971 19:57:41.869629
7972 19:57:41.872073 ==
7973 19:57:41.875285 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 19:57:41.878504 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7975 19:57:41.879069 ==
7976 19:57:41.879441 RX Vref Scan: 0
7977 19:57:41.879780
7978 19:57:41.882019 RX Vref 0 -> 0, step: 1
7979 19:57:41.882581
7980 19:57:41.885125 RX Delay 11 -> 252, step: 4
7981 19:57:41.888544 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7982 19:57:41.891609 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7983 19:57:41.898337 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7984 19:57:41.901524 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7985 19:57:41.904958 iDelay=195, Bit 4, Center 132 (75 ~ 190) 116
7986 19:57:41.908279 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7987 19:57:41.911674 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7988 19:57:41.918457 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7989 19:57:41.921567 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
7990 19:57:41.924876 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7991 19:57:41.928385 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7992 19:57:41.931855 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7993 19:57:41.938132 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7994 19:57:41.941893 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7995 19:57:41.944841 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7996 19:57:41.947794 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7997 19:57:41.948304 ==
7998 19:57:41.951366 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 19:57:41.958363 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8000 19:57:41.958917 ==
8001 19:57:41.959292 DQS Delay:
8002 19:57:41.961701 DQS0 = 0, DQS1 = 0
8003 19:57:41.962277 DQM Delay:
8004 19:57:41.964970 DQM0 = 128, DQM1 = 120
8005 19:57:41.965554 DQ Delay:
8006 19:57:41.968057 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
8007 19:57:41.971606 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
8008 19:57:41.974712 DQ8 =106, DQ9 =106, DQ10 =122, DQ11 =112
8009 19:57:41.977984 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8010 19:57:41.978449
8011 19:57:41.978817
8012 19:57:41.979157
8013 19:57:41.981575 [DramC_TX_OE_Calibration] TA2
8014 19:57:41.985155 Original DQ_B0 (3 6) =30, OEN = 27
8015 19:57:41.988295 Original DQ_B1 (3 6) =30, OEN = 27
8016 19:57:41.991350 24, 0x0, End_B0=24 End_B1=24
8017 19:57:41.991918 25, 0x0, End_B0=25 End_B1=25
8018 19:57:41.994568 26, 0x0, End_B0=26 End_B1=26
8019 19:57:41.998049 27, 0x0, End_B0=27 End_B1=27
8020 19:57:42.001095 28, 0x0, End_B0=28 End_B1=28
8021 19:57:42.004764 29, 0x0, End_B0=29 End_B1=29
8022 19:57:42.005323 30, 0x0, End_B0=30 End_B1=30
8023 19:57:42.007598 31, 0x4141, End_B0=30 End_B1=30
8024 19:57:42.011081 Byte0 end_step=30 best_step=27
8025 19:57:42.014573 Byte1 end_step=30 best_step=27
8026 19:57:42.017875 Byte0 TX OE(2T, 0.5T) = (3, 3)
8027 19:57:42.020766 Byte1 TX OE(2T, 0.5T) = (3, 3)
8028 19:57:42.021228
8029 19:57:42.021591
8030 19:57:42.027533 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8031 19:57:42.031073 CH0 RK1: MR19=303, MR18=2020
8032 19:57:42.037852 CH0_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
8033 19:57:42.040892 [RxdqsGatingPostProcess] freq 1600
8034 19:57:42.044606 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8035 19:57:42.047956 Pre-setting of DQS Precalculation
8036 19:57:42.054419 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8037 19:57:42.054981 ==
8038 19:57:42.057681 Dram Type= 6, Freq= 0, CH_1, rank 0
8039 19:57:42.061082 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8040 19:57:42.061738 ==
8041 19:57:42.067500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8042 19:57:42.070711 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8043 19:57:42.074336 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8044 19:57:42.080782 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8045 19:57:42.089760 [CA 0] Center 41 (11~72) winsize 62
8046 19:57:42.092902 [CA 1] Center 41 (11~72) winsize 62
8047 19:57:42.096045 [CA 2] Center 37 (8~67) winsize 60
8048 19:57:42.099296 [CA 3] Center 36 (7~66) winsize 60
8049 19:57:42.102345 [CA 4] Center 34 (4~64) winsize 61
8050 19:57:42.105869 [CA 5] Center 34 (5~64) winsize 60
8051 19:57:42.106422
8052 19:57:42.109103 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8053 19:57:42.109655
8054 19:57:42.112762 [CATrainingPosCal] consider 1 rank data
8055 19:57:42.116227 u2DelayCellTimex100 = 271/100 ps
8056 19:57:42.119567 CA0 delay=41 (11~72),Diff = 7 PI (25 cell)
8057 19:57:42.125721 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8058 19:57:42.128933 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8059 19:57:42.132702 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8060 19:57:42.135872 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8061 19:57:42.139143 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8062 19:57:42.139699
8063 19:57:42.142523 CA PerBit enable=1, Macro0, CA PI delay=34
8064 19:57:42.143087
8065 19:57:42.145966 [CBTSetCACLKResult] CA Dly = 34
8066 19:57:42.148914 CS Dly: 8 (0~39)
8067 19:57:42.152436 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8068 19:57:42.155828 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8069 19:57:42.156415 ==
8070 19:57:42.159166 Dram Type= 6, Freq= 0, CH_1, rank 1
8071 19:57:42.162570 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8072 19:57:42.165805 ==
8073 19:57:42.168845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8074 19:57:42.172876 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8075 19:57:42.178698 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8076 19:57:42.182077 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8077 19:57:42.192090 [CA 0] Center 40 (10~70) winsize 61
8078 19:57:42.195279 [CA 1] Center 39 (9~70) winsize 62
8079 19:57:42.198159 [CA 2] Center 35 (6~65) winsize 60
8080 19:57:42.201824 [CA 3] Center 35 (6~65) winsize 60
8081 19:57:42.205066 [CA 4] Center 33 (4~62) winsize 59
8082 19:57:42.208487 [CA 5] Center 33 (3~63) winsize 61
8083 19:57:42.209053
8084 19:57:42.211998 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8085 19:57:42.212612
8086 19:57:42.215030 [CATrainingPosCal] consider 2 rank data
8087 19:57:42.218305 u2DelayCellTimex100 = 271/100 ps
8088 19:57:42.221663 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8089 19:57:42.228253 CA1 delay=40 (11~70),Diff = 7 PI (25 cell)
8090 19:57:42.231538 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8091 19:57:42.234722 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8092 19:57:42.238441 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8093 19:57:42.241333 CA5 delay=34 (5~63),Diff = 1 PI (3 cell)
8094 19:57:42.241800
8095 19:57:42.244599 CA PerBit enable=1, Macro0, CA PI delay=33
8096 19:57:42.245166
8097 19:57:42.248272 [CBTSetCACLKResult] CA Dly = 33
8098 19:57:42.251068 CS Dly: 9 (0~41)
8099 19:57:42.254896 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8100 19:57:42.257871 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8101 19:57:42.258333
8102 19:57:42.261421 ----->DramcWriteLeveling(PI) begin...
8103 19:57:42.261987 ==
8104 19:57:42.264477 Dram Type= 6, Freq= 0, CH_1, rank 0
8105 19:57:42.270977 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8106 19:57:42.271587 ==
8107 19:57:42.274390 Write leveling (Byte 0): 24 => 24
8108 19:57:42.274853 Write leveling (Byte 1): 25 => 25
8109 19:57:42.277983 DramcWriteLeveling(PI) end<-----
8110 19:57:42.278546
8111 19:57:42.281372 ==
8112 19:57:42.281837 Dram Type= 6, Freq= 0, CH_1, rank 0
8113 19:57:42.287962 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8114 19:57:42.288584 ==
8115 19:57:42.291202 [Gating] SW mode calibration
8116 19:57:42.297900 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8117 19:57:42.300985 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8118 19:57:42.308014 0 12 0 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
8119 19:57:42.311338 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8120 19:57:42.314520 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8121 19:57:42.320847 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8122 19:57:42.324408 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8123 19:57:42.327367 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8124 19:57:42.334331 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8125 19:57:42.337501 0 12 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8126 19:57:42.341044 0 13 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8127 19:57:42.347255 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8128 19:57:42.350739 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8129 19:57:42.354097 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8130 19:57:42.360796 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8131 19:57:42.364032 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8132 19:57:42.367135 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8133 19:57:42.373906 0 13 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8134 19:57:42.377227 0 14 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8135 19:57:42.380265 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8136 19:57:42.386849 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8137 19:57:42.390299 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8138 19:57:42.393429 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8139 19:57:42.400166 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 19:57:42.403626 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8141 19:57:42.406901 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8142 19:57:42.413641 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8143 19:57:42.416606 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8144 19:57:42.420148 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8145 19:57:42.426384 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 19:57:42.429798 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 19:57:42.433151 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 19:57:42.439659 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 19:57:42.443336 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 19:57:42.446177 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 19:57:42.452853 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 19:57:42.456737 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 19:57:42.459740 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 19:57:42.463178 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 19:57:42.469982 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 19:57:42.472859 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8157 19:57:42.476547 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8158 19:57:42.482935 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8159 19:57:42.486154 Total UI for P1: 0, mck2ui 16
8160 19:57:42.489550 best dqsien dly found for B0: ( 1, 0, 26)
8161 19:57:42.492815 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8162 19:57:42.496204 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8163 19:57:42.499339 Total UI for P1: 0, mck2ui 16
8164 19:57:42.502439 best dqsien dly found for B1: ( 1, 1, 2)
8165 19:57:42.505816 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8166 19:57:42.509387 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8167 19:57:42.512414
8168 19:57:42.515763 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8169 19:57:42.519493 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8170 19:57:42.522693 [Gating] SW calibration Done
8171 19:57:42.523250 ==
8172 19:57:42.525590 Dram Type= 6, Freq= 0, CH_1, rank 0
8173 19:57:42.529095 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8174 19:57:42.529559 ==
8175 19:57:42.529931 RX Vref Scan: 0
8176 19:57:42.532464
8177 19:57:42.532929 RX Vref 0 -> 0, step: 1
8178 19:57:42.533300
8179 19:57:42.535835 RX Delay 0 -> 252, step: 8
8180 19:57:42.539229 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8181 19:57:42.542219 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8182 19:57:42.548853 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8183 19:57:42.552719 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8184 19:57:42.555645 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8185 19:57:42.558707 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8186 19:57:42.562170 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8187 19:57:42.568805 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8188 19:57:42.571921 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8189 19:57:42.575089 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8190 19:57:42.578488 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8191 19:57:42.581771 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8192 19:57:42.588640 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8193 19:57:42.591930 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8194 19:57:42.595327 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8195 19:57:42.598610 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8196 19:57:42.599169 ==
8197 19:57:42.601981 Dram Type= 6, Freq= 0, CH_1, rank 0
8198 19:57:42.608477 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8199 19:57:42.609035 ==
8200 19:57:42.609404 DQS Delay:
8201 19:57:42.611555 DQS0 = 0, DQS1 = 0
8202 19:57:42.612103 DQM Delay:
8203 19:57:42.615120 DQM0 = 130, DQM1 = 125
8204 19:57:42.615711 DQ Delay:
8205 19:57:42.618344 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8206 19:57:42.621770 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8207 19:57:42.624928 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =115
8208 19:57:42.628331 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8209 19:57:42.628798
8210 19:57:42.629163
8211 19:57:42.629501 ==
8212 19:57:42.631317 Dram Type= 6, Freq= 0, CH_1, rank 0
8213 19:57:42.638360 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8214 19:57:42.638973 ==
8215 19:57:42.639360
8216 19:57:42.639700
8217 19:57:42.640022 TX Vref Scan disable
8218 19:57:42.641478 == TX Byte 0 ==
8219 19:57:42.644886 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8220 19:57:42.651458 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8221 19:57:42.652013 == TX Byte 1 ==
8222 19:57:42.654857 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8223 19:57:42.661283 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8224 19:57:42.661836 ==
8225 19:57:42.664790 Dram Type= 6, Freq= 0, CH_1, rank 0
8226 19:57:42.667970 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8227 19:57:42.668615 ==
8228 19:57:42.678927
8229 19:57:42.682498 TX Vref early break, caculate TX vref
8230 19:57:42.685599 TX Vref=16, minBit 0, minWin=22, winSum=367
8231 19:57:42.688814 TX Vref=18, minBit 3, minWin=22, winSum=375
8232 19:57:42.692137 TX Vref=20, minBit 3, minWin=23, winSum=383
8233 19:57:42.695548 TX Vref=22, minBit 8, minWin=23, winSum=395
8234 19:57:42.699157 TX Vref=24, minBit 0, minWin=24, winSum=404
8235 19:57:42.705283 TX Vref=26, minBit 3, minWin=25, winSum=416
8236 19:57:42.709084 TX Vref=28, minBit 3, minWin=24, winSum=410
8237 19:57:42.712312 TX Vref=30, minBit 9, minWin=23, winSum=406
8238 19:57:42.715562 TX Vref=32, minBit 9, minWin=23, winSum=393
8239 19:57:42.721991 [TxChooseVref] Worse bit 3, Min win 25, Win sum 416, Final Vref 26
8240 19:57:42.722552
8241 19:57:42.725299 Final TX Range 0 Vref 26
8242 19:57:42.725853
8243 19:57:42.726224 ==
8244 19:57:42.728439 Dram Type= 6, Freq= 0, CH_1, rank 0
8245 19:57:42.731992 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8246 19:57:42.732597 ==
8247 19:57:42.732973
8248 19:57:42.733311
8249 19:57:42.735478 TX Vref Scan disable
8250 19:57:42.741521 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8251 19:57:42.742062 == TX Byte 0 ==
8252 19:57:42.745031 u2DelayCellOfst[0]=18 cells (5 PI)
8253 19:57:42.748563 u2DelayCellOfst[1]=10 cells (3 PI)
8254 19:57:42.751625 u2DelayCellOfst[2]=0 cells (0 PI)
8255 19:57:42.755016 u2DelayCellOfst[3]=7 cells (2 PI)
8256 19:57:42.758449 u2DelayCellOfst[4]=7 cells (2 PI)
8257 19:57:42.761646 u2DelayCellOfst[5]=14 cells (4 PI)
8258 19:57:42.762111 u2DelayCellOfst[6]=14 cells (4 PI)
8259 19:57:42.764632 u2DelayCellOfst[7]=7 cells (2 PI)
8260 19:57:42.771853 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8261 19:57:42.774813 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8262 19:57:42.775275 == TX Byte 1 ==
8263 19:57:42.778093 u2DelayCellOfst[8]=0 cells (0 PI)
8264 19:57:42.781354 u2DelayCellOfst[9]=7 cells (2 PI)
8265 19:57:42.784558 u2DelayCellOfst[10]=10 cells (3 PI)
8266 19:57:42.788024 u2DelayCellOfst[11]=3 cells (1 PI)
8267 19:57:42.791732 u2DelayCellOfst[12]=18 cells (5 PI)
8268 19:57:42.794994 u2DelayCellOfst[13]=21 cells (6 PI)
8269 19:57:42.798280 u2DelayCellOfst[14]=21 cells (6 PI)
8270 19:57:42.801449 u2DelayCellOfst[15]=21 cells (6 PI)
8271 19:57:42.805152 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8272 19:57:42.808281 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8273 19:57:42.811628 DramC Write-DBI on
8274 19:57:42.812214 ==
8275 19:57:42.814915 Dram Type= 6, Freq= 0, CH_1, rank 0
8276 19:57:42.818204 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8277 19:57:42.818761 ==
8278 19:57:42.819132
8279 19:57:42.822291
8280 19:57:42.822847 TX Vref Scan disable
8281 19:57:42.824522 == TX Byte 0 ==
8282 19:57:42.827952 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8283 19:57:42.831305 == TX Byte 1 ==
8284 19:57:42.834849 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8285 19:57:42.835405 DramC Write-DBI off
8286 19:57:42.835776
8287 19:57:42.837915 [DATLAT]
8288 19:57:42.838470 Freq=1600, CH1 RK0
8289 19:57:42.838841
8290 19:57:42.840997 DATLAT Default: 0xf
8291 19:57:42.841457 0, 0xFFFF, sum = 0
8292 19:57:42.844535 1, 0xFFFF, sum = 0
8293 19:57:42.845091 2, 0xFFFF, sum = 0
8294 19:57:42.847665 3, 0xFFFF, sum = 0
8295 19:57:42.848146 4, 0xFFFF, sum = 0
8296 19:57:42.851326 5, 0xFFFF, sum = 0
8297 19:57:42.851902 6, 0xFFFF, sum = 0
8298 19:57:42.854536 7, 0xFFFF, sum = 0
8299 19:57:42.857788 8, 0xFFFF, sum = 0
8300 19:57:42.858375 9, 0xFFFF, sum = 0
8301 19:57:42.861176 10, 0xFFFF, sum = 0
8302 19:57:42.861702 11, 0xFFFF, sum = 0
8303 19:57:42.864719 12, 0xF7F, sum = 0
8304 19:57:42.865198 13, 0x0, sum = 1
8305 19:57:42.867579 14, 0x0, sum = 2
8306 19:57:42.868056 15, 0x0, sum = 3
8307 19:57:42.870988 16, 0x0, sum = 4
8308 19:57:42.871565 best_step = 14
8309 19:57:42.872051
8310 19:57:42.872546 ==
8311 19:57:42.873919 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 19:57:42.877426 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8313 19:57:42.877912 ==
8314 19:57:42.880823 RX Vref Scan: 1
8315 19:57:42.881287
8316 19:57:42.884139 Set Vref Range= 24 -> 127
8317 19:57:42.884670
8318 19:57:42.885201 RX Vref 24 -> 127, step: 1
8319 19:57:42.885659
8320 19:57:42.887727 RX Delay 11 -> 252, step: 4
8321 19:57:42.888351
8322 19:57:42.890884 Set Vref, RX VrefLevel [Byte0]: 24
8323 19:57:42.894077 [Byte1]: 24
8324 19:57:42.897228
8325 19:57:42.897682 Set Vref, RX VrefLevel [Byte0]: 25
8326 19:57:42.900803 [Byte1]: 25
8327 19:57:42.905147
8328 19:57:42.905698 Set Vref, RX VrefLevel [Byte0]: 26
8329 19:57:42.908547 [Byte1]: 26
8330 19:57:42.912435
8331 19:57:42.912897 Set Vref, RX VrefLevel [Byte0]: 27
8332 19:57:42.916054 [Byte1]: 27
8333 19:57:42.920504
8334 19:57:42.921054 Set Vref, RX VrefLevel [Byte0]: 28
8335 19:57:42.923532 [Byte1]: 28
8336 19:57:42.928139
8337 19:57:42.928791 Set Vref, RX VrefLevel [Byte0]: 29
8338 19:57:42.931515 [Byte1]: 29
8339 19:57:42.935507
8340 19:57:42.935965 Set Vref, RX VrefLevel [Byte0]: 30
8341 19:57:42.938886 [Byte1]: 30
8342 19:57:42.943139
8343 19:57:42.943689 Set Vref, RX VrefLevel [Byte0]: 31
8344 19:57:42.946834 [Byte1]: 31
8345 19:57:42.950839
8346 19:57:42.951300 Set Vref, RX VrefLevel [Byte0]: 32
8347 19:57:42.954039 [Byte1]: 32
8348 19:57:42.958336
8349 19:57:42.958915 Set Vref, RX VrefLevel [Byte0]: 33
8350 19:57:42.961789 [Byte1]: 33
8351 19:57:42.965978
8352 19:57:42.966533 Set Vref, RX VrefLevel [Byte0]: 34
8353 19:57:42.969353 [Byte1]: 34
8354 19:57:42.973590
8355 19:57:42.974149 Set Vref, RX VrefLevel [Byte0]: 35
8356 19:57:42.976806 [Byte1]: 35
8357 19:57:42.981239
8358 19:57:42.981697 Set Vref, RX VrefLevel [Byte0]: 36
8359 19:57:42.984462 [Byte1]: 36
8360 19:57:42.988510
8361 19:57:42.988967 Set Vref, RX VrefLevel [Byte0]: 37
8362 19:57:42.991882 [Byte1]: 37
8363 19:57:42.996165
8364 19:57:42.996670 Set Vref, RX VrefLevel [Byte0]: 38
8365 19:57:42.999469 [Byte1]: 38
8366 19:57:43.003937
8367 19:57:43.004449 Set Vref, RX VrefLevel [Byte0]: 39
8368 19:57:43.007252 [Byte1]: 39
8369 19:57:43.011773
8370 19:57:43.012369 Set Vref, RX VrefLevel [Byte0]: 40
8371 19:57:43.014807 [Byte1]: 40
8372 19:57:43.019289
8373 19:57:43.019843 Set Vref, RX VrefLevel [Byte0]: 41
8374 19:57:43.023296 [Byte1]: 41
8375 19:57:43.027317
8376 19:57:43.027869 Set Vref, RX VrefLevel [Byte0]: 42
8377 19:57:43.029943 [Byte1]: 42
8378 19:57:43.034683
8379 19:57:43.035240 Set Vref, RX VrefLevel [Byte0]: 43
8380 19:57:43.037712 [Byte1]: 43
8381 19:57:43.042414
8382 19:57:43.042969 Set Vref, RX VrefLevel [Byte0]: 44
8383 19:57:43.045506 [Byte1]: 44
8384 19:57:43.049919
8385 19:57:43.050471 Set Vref, RX VrefLevel [Byte0]: 45
8386 19:57:43.053049 [Byte1]: 45
8387 19:57:43.057142
8388 19:57:43.057600 Set Vref, RX VrefLevel [Byte0]: 46
8389 19:57:43.060438 [Byte1]: 46
8390 19:57:43.065073
8391 19:57:43.065623 Set Vref, RX VrefLevel [Byte0]: 47
8392 19:57:43.067957 [Byte1]: 47
8393 19:57:43.072763
8394 19:57:43.073525 Set Vref, RX VrefLevel [Byte0]: 48
8395 19:57:43.075779 [Byte1]: 48
8396 19:57:43.080079
8397 19:57:43.080578 Set Vref, RX VrefLevel [Byte0]: 49
8398 19:57:43.083415 [Byte1]: 49
8399 19:57:43.087911
8400 19:57:43.088521 Set Vref, RX VrefLevel [Byte0]: 50
8401 19:57:43.091127 [Byte1]: 50
8402 19:57:43.095236
8403 19:57:43.095785 Set Vref, RX VrefLevel [Byte0]: 51
8404 19:57:43.098897 [Byte1]: 51
8405 19:57:43.102985
8406 19:57:43.103545 Set Vref, RX VrefLevel [Byte0]: 52
8407 19:57:43.106381 [Byte1]: 52
8408 19:57:43.110418
8409 19:57:43.110874 Set Vref, RX VrefLevel [Byte0]: 53
8410 19:57:43.114335 [Byte1]: 53
8411 19:57:43.118384
8412 19:57:43.118932 Set Vref, RX VrefLevel [Byte0]: 54
8413 19:57:43.121655 [Byte1]: 54
8414 19:57:43.125874
8415 19:57:43.126421 Set Vref, RX VrefLevel [Byte0]: 55
8416 19:57:43.129013 [Byte1]: 55
8417 19:57:43.133887
8418 19:57:43.134440 Set Vref, RX VrefLevel [Byte0]: 56
8419 19:57:43.136647 [Byte1]: 56
8420 19:57:43.141038
8421 19:57:43.141586 Set Vref, RX VrefLevel [Byte0]: 57
8422 19:57:43.144221 [Byte1]: 57
8423 19:57:43.148843
8424 19:57:43.149398 Set Vref, RX VrefLevel [Byte0]: 58
8425 19:57:43.152210 [Byte1]: 58
8426 19:57:43.156546
8427 19:57:43.157109 Set Vref, RX VrefLevel [Byte0]: 59
8428 19:57:43.159494 [Byte1]: 59
8429 19:57:43.164011
8430 19:57:43.164617 Set Vref, RX VrefLevel [Byte0]: 60
8431 19:57:43.167548 [Byte1]: 60
8432 19:57:43.171307
8433 19:57:43.171765 Set Vref, RX VrefLevel [Byte0]: 61
8434 19:57:43.174768 [Byte1]: 61
8435 19:57:43.179212
8436 19:57:43.179688 Set Vref, RX VrefLevel [Byte0]: 62
8437 19:57:43.182578 [Byte1]: 62
8438 19:57:43.186829
8439 19:57:43.187392 Set Vref, RX VrefLevel [Byte0]: 63
8440 19:57:43.190093 [Byte1]: 63
8441 19:57:43.194659
8442 19:57:43.195210 Set Vref, RX VrefLevel [Byte0]: 64
8443 19:57:43.197651 [Byte1]: 64
8444 19:57:43.202116
8445 19:57:43.202670 Set Vref, RX VrefLevel [Byte0]: 65
8446 19:57:43.205263 [Byte1]: 65
8447 19:57:43.209726
8448 19:57:43.210281 Set Vref, RX VrefLevel [Byte0]: 66
8449 19:57:43.212691 [Byte1]: 66
8450 19:57:43.217011
8451 19:57:43.217548 Set Vref, RX VrefLevel [Byte0]: 67
8452 19:57:43.220774 [Byte1]: 67
8453 19:57:43.224942
8454 19:57:43.225496 Set Vref, RX VrefLevel [Byte0]: 68
8455 19:57:43.228236 [Byte1]: 68
8456 19:57:43.232564
8457 19:57:43.233029 Set Vref, RX VrefLevel [Byte0]: 69
8458 19:57:43.235493 [Byte1]: 69
8459 19:57:43.240327
8460 19:57:43.240928 Set Vref, RX VrefLevel [Byte0]: 70
8461 19:57:43.243517 [Byte1]: 70
8462 19:57:43.247946
8463 19:57:43.248591 Set Vref, RX VrefLevel [Byte0]: 71
8464 19:57:43.250686 [Byte1]: 71
8465 19:57:43.255344
8466 19:57:43.255896 Set Vref, RX VrefLevel [Byte0]: 72
8467 19:57:43.258450 [Byte1]: 72
8468 19:57:43.262882
8469 19:57:43.263431 Set Vref, RX VrefLevel [Byte0]: 73
8470 19:57:43.266166 [Byte1]: 73
8471 19:57:43.270527
8472 19:57:43.271082 Set Vref, RX VrefLevel [Byte0]: 74
8473 19:57:43.273548 [Byte1]: 74
8474 19:57:43.278252
8475 19:57:43.278829 Set Vref, RX VrefLevel [Byte0]: 75
8476 19:57:43.281222 [Byte1]: 75
8477 19:57:43.285606
8478 19:57:43.286157 Set Vref, RX VrefLevel [Byte0]: 76
8479 19:57:43.288992 [Byte1]: 76
8480 19:57:43.293447
8481 19:57:43.294010 Set Vref, RX VrefLevel [Byte0]: 77
8482 19:57:43.296664 [Byte1]: 77
8483 19:57:43.300781
8484 19:57:43.301245 Final RX Vref Byte 0 = 59 to rank0
8485 19:57:43.304371 Final RX Vref Byte 1 = 52 to rank0
8486 19:57:43.307905 Final RX Vref Byte 0 = 59 to rank1
8487 19:57:43.311274 Final RX Vref Byte 1 = 52 to rank1==
8488 19:57:43.314393 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 19:57:43.320671 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8490 19:57:43.321213 ==
8491 19:57:43.321582 DQS Delay:
8492 19:57:43.321924 DQS0 = 0, DQS1 = 0
8493 19:57:43.324236 DQM Delay:
8494 19:57:43.324696 DQM0 = 129, DQM1 = 123
8495 19:57:43.327517 DQ Delay:
8496 19:57:43.330787 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8497 19:57:43.334157 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8498 19:57:43.337612 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =112
8499 19:57:43.340874 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8500 19:57:43.341338
8501 19:57:43.341704
8502 19:57:43.342040
8503 19:57:43.344055 [DramC_TX_OE_Calibration] TA2
8504 19:57:43.347450 Original DQ_B0 (3 6) =30, OEN = 27
8505 19:57:43.350772 Original DQ_B1 (3 6) =30, OEN = 27
8506 19:57:43.354236 24, 0x0, End_B0=24 End_B1=24
8507 19:57:43.354798 25, 0x0, End_B0=25 End_B1=25
8508 19:57:43.357058 26, 0x0, End_B0=26 End_B1=26
8509 19:57:43.360644 27, 0x0, End_B0=27 End_B1=27
8510 19:57:43.363704 28, 0x0, End_B0=28 End_B1=28
8511 19:57:43.367264 29, 0x0, End_B0=29 End_B1=29
8512 19:57:43.367825 30, 0x0, End_B0=30 End_B1=30
8513 19:57:43.370202 31, 0x4545, End_B0=30 End_B1=30
8514 19:57:43.374512 Byte0 end_step=30 best_step=27
8515 19:57:43.376892 Byte1 end_step=30 best_step=27
8516 19:57:43.380421 Byte0 TX OE(2T, 0.5T) = (3, 3)
8517 19:57:43.383869 Byte1 TX OE(2T, 0.5T) = (3, 3)
8518 19:57:43.384469
8519 19:57:43.384845
8520 19:57:43.390599 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8521 19:57:43.393551 CH1 RK0: MR19=303, MR18=2525
8522 19:57:43.400095 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8523 19:57:43.400592
8524 19:57:43.403609 ----->DramcWriteLeveling(PI) begin...
8525 19:57:43.404169 ==
8526 19:57:43.406669 Dram Type= 6, Freq= 0, CH_1, rank 1
8527 19:57:43.409982 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8528 19:57:43.410445 ==
8529 19:57:43.413689 Write leveling (Byte 0): 23 => 23
8530 19:57:43.416663 Write leveling (Byte 1): 19 => 19
8531 19:57:43.420063 DramcWriteLeveling(PI) end<-----
8532 19:57:43.420664
8533 19:57:43.421034 ==
8534 19:57:43.423015 Dram Type= 6, Freq= 0, CH_1, rank 1
8535 19:57:43.426792 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8536 19:57:43.427351 ==
8537 19:57:43.429917 [Gating] SW mode calibration
8538 19:57:43.436288 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8539 19:57:43.443337 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8540 19:57:43.446619 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
8541 19:57:43.452814 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8542 19:57:43.456540 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8543 19:57:43.459645 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8544 19:57:43.466518 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8545 19:57:43.469852 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8546 19:57:43.473076 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8547 19:57:43.479706 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8548 19:57:43.482596 0 13 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8549 19:57:43.486224 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8550 19:57:43.492656 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8551 19:57:43.495840 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8552 19:57:43.499446 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8553 19:57:43.506015 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8554 19:57:43.509279 0 13 24 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8555 19:57:43.512646 0 13 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8556 19:57:43.519197 0 14 0 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
8557 19:57:43.522786 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8558 19:57:43.525771 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8559 19:57:43.532293 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8560 19:57:43.535672 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8561 19:57:43.539264 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8562 19:57:43.545664 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8563 19:57:43.548743 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8564 19:57:43.552008 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8565 19:57:43.558895 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 19:57:43.562249 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8567 19:57:43.565568 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8568 19:57:43.572140 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8569 19:57:43.575213 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8570 19:57:43.578557 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8571 19:57:43.585067 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 19:57:43.588651 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 19:57:43.591784 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 19:57:43.595391 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 19:57:43.601499 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 19:57:43.605246 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 19:57:43.608338 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8578 19:57:43.614609 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8579 19:57:43.618510 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8580 19:57:43.621399 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8581 19:57:43.624858 Total UI for P1: 0, mck2ui 16
8582 19:57:43.628240 best dqsien dly found for B0: ( 1, 0, 24)
8583 19:57:43.635020 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8584 19:57:43.638287 Total UI for P1: 0, mck2ui 16
8585 19:57:43.641264 best dqsien dly found for B1: ( 1, 1, 0)
8586 19:57:43.645067 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8587 19:57:43.647801 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8588 19:57:43.648300
8589 19:57:43.651349 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8590 19:57:43.654625 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8591 19:57:43.657961 [Gating] SW calibration Done
8592 19:57:43.658510 ==
8593 19:57:43.661044 Dram Type= 6, Freq= 0, CH_1, rank 1
8594 19:57:43.664382 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8595 19:57:43.664854 ==
8596 19:57:43.667622 RX Vref Scan: 0
8597 19:57:43.668081
8598 19:57:43.671281 RX Vref 0 -> 0, step: 1
8599 19:57:43.671834
8600 19:57:43.672248 RX Delay 0 -> 252, step: 8
8601 19:57:43.677620 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8602 19:57:43.680981 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8603 19:57:43.684381 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8604 19:57:43.687748 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8605 19:57:43.691182 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8606 19:57:43.697775 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8607 19:57:43.700886 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8608 19:57:43.704041 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8609 19:57:43.707434 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8610 19:57:43.710572 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8611 19:57:43.717335 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8612 19:57:43.720710 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8613 19:57:43.723885 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8614 19:57:43.727242 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8615 19:57:43.733981 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8616 19:57:43.737031 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8617 19:57:43.737585 ==
8618 19:57:43.740470 Dram Type= 6, Freq= 0, CH_1, rank 1
8619 19:57:43.744163 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8620 19:57:43.744768 ==
8621 19:57:43.745139 DQS Delay:
8622 19:57:43.747015 DQS0 = 0, DQS1 = 0
8623 19:57:43.747475 DQM Delay:
8624 19:57:43.750622 DQM0 = 130, DQM1 = 124
8625 19:57:43.751177 DQ Delay:
8626 19:57:43.753800 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8627 19:57:43.757444 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8628 19:57:43.760565 DQ8 =107, DQ9 =111, DQ10 =127, DQ11 =115
8629 19:57:43.764215 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8630 19:57:43.767026
8631 19:57:43.767573
8632 19:57:43.767945 ==
8633 19:57:43.770099 Dram Type= 6, Freq= 0, CH_1, rank 1
8634 19:57:43.773595 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8635 19:57:43.774148 ==
8636 19:57:43.774518
8637 19:57:43.774855
8638 19:57:43.777239 TX Vref Scan disable
8639 19:57:43.777732 == TX Byte 0 ==
8640 19:57:43.783892 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8641 19:57:43.786944 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8642 19:57:43.787409 == TX Byte 1 ==
8643 19:57:43.794115 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8644 19:57:43.796694 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8645 19:57:43.797159 ==
8646 19:57:43.799987 Dram Type= 6, Freq= 0, CH_1, rank 1
8647 19:57:43.803570 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8648 19:57:43.804125 ==
8649 19:57:43.818378
8650 19:57:43.821485 TX Vref early break, caculate TX vref
8651 19:57:43.824818 TX Vref=16, minBit 0, minWin=22, winSum=379
8652 19:57:43.828123 TX Vref=18, minBit 0, minWin=23, winSum=394
8653 19:57:43.831482 TX Vref=20, minBit 0, minWin=22, winSum=397
8654 19:57:43.834845 TX Vref=22, minBit 6, minWin=23, winSum=402
8655 19:57:43.838255 TX Vref=24, minBit 0, minWin=24, winSum=406
8656 19:57:43.844364 TX Vref=26, minBit 0, minWin=24, winSum=420
8657 19:57:43.847790 TX Vref=28, minBit 0, minWin=24, winSum=421
8658 19:57:43.851223 TX Vref=30, minBit 0, minWin=24, winSum=415
8659 19:57:43.854632 TX Vref=32, minBit 0, minWin=23, winSum=411
8660 19:57:43.857937 TX Vref=34, minBit 0, minWin=22, winSum=401
8661 19:57:43.861191 TX Vref=36, minBit 0, minWin=21, winSum=388
8662 19:57:43.867972 [TxChooseVref] Worse bit 0, Min win 24, Win sum 421, Final Vref 28
8663 19:57:43.868569
8664 19:57:43.870848 Final TX Range 0 Vref 28
8665 19:57:43.871315
8666 19:57:43.871680 ==
8667 19:57:43.874430 Dram Type= 6, Freq= 0, CH_1, rank 1
8668 19:57:43.877828 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8669 19:57:43.878321 ==
8670 19:57:43.878691
8671 19:57:43.880731
8672 19:57:43.881190 TX Vref Scan disable
8673 19:57:43.887421 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8674 19:57:43.887887 == TX Byte 0 ==
8675 19:57:43.891045 u2DelayCellOfst[0]=18 cells (5 PI)
8676 19:57:43.894395 u2DelayCellOfst[1]=7 cells (2 PI)
8677 19:57:43.897815 u2DelayCellOfst[2]=0 cells (0 PI)
8678 19:57:43.900881 u2DelayCellOfst[3]=7 cells (2 PI)
8679 19:57:43.904060 u2DelayCellOfst[4]=7 cells (2 PI)
8680 19:57:43.907429 u2DelayCellOfst[5]=14 cells (4 PI)
8681 19:57:43.910750 u2DelayCellOfst[6]=14 cells (4 PI)
8682 19:57:43.914495 u2DelayCellOfst[7]=3 cells (1 PI)
8683 19:57:43.917227 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8684 19:57:43.920748 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8685 19:57:43.924121 == TX Byte 1 ==
8686 19:57:43.927836 u2DelayCellOfst[8]=0 cells (0 PI)
8687 19:57:43.930519 u2DelayCellOfst[9]=7 cells (2 PI)
8688 19:57:43.931029 u2DelayCellOfst[10]=7 cells (2 PI)
8689 19:57:43.933895 u2DelayCellOfst[11]=3 cells (1 PI)
8690 19:57:43.937129 u2DelayCellOfst[12]=14 cells (4 PI)
8691 19:57:43.940570 u2DelayCellOfst[13]=18 cells (5 PI)
8692 19:57:43.944119 u2DelayCellOfst[14]=18 cells (5 PI)
8693 19:57:43.947073 u2DelayCellOfst[15]=18 cells (5 PI)
8694 19:57:43.953891 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8695 19:57:43.957141 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8696 19:57:43.957700 DramC Write-DBI on
8697 19:57:43.958072 ==
8698 19:57:43.960351 Dram Type= 6, Freq= 0, CH_1, rank 1
8699 19:57:43.967150 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8700 19:57:43.967709 ==
8701 19:57:43.968083
8702 19:57:43.968467
8703 19:57:43.968793 TX Vref Scan disable
8704 19:57:43.971121 == TX Byte 0 ==
8705 19:57:43.974300 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8706 19:57:43.977656 == TX Byte 1 ==
8707 19:57:43.980918 Update DQM dly =714 (2 ,6, 10) DQM OEN =(3 ,3)
8708 19:57:43.984071 DramC Write-DBI off
8709 19:57:43.984582
8710 19:57:43.984950 [DATLAT]
8711 19:57:43.985291 Freq=1600, CH1 RK1
8712 19:57:43.985627
8713 19:57:43.987463 DATLAT Default: 0xe
8714 19:57:43.987924 0, 0xFFFF, sum = 0
8715 19:57:43.990776 1, 0xFFFF, sum = 0
8716 19:57:43.994343 2, 0xFFFF, sum = 0
8717 19:57:43.994924 3, 0xFFFF, sum = 0
8718 19:57:43.997681 4, 0xFFFF, sum = 0
8719 19:57:43.998149 5, 0xFFFF, sum = 0
8720 19:57:44.000688 6, 0xFFFF, sum = 0
8721 19:57:44.001159 7, 0xFFFF, sum = 0
8722 19:57:44.004010 8, 0xFFFF, sum = 0
8723 19:57:44.004535 9, 0xFFFF, sum = 0
8724 19:57:44.007473 10, 0xFFFF, sum = 0
8725 19:57:44.008031 11, 0xFFFF, sum = 0
8726 19:57:44.011173 12, 0xF7F, sum = 0
8727 19:57:44.011751 13, 0x0, sum = 1
8728 19:57:44.014205 14, 0x0, sum = 2
8729 19:57:44.014764 15, 0x0, sum = 3
8730 19:57:44.017271 16, 0x0, sum = 4
8731 19:57:44.017743 best_step = 14
8732 19:57:44.018109
8733 19:57:44.018452 ==
8734 19:57:44.021056 Dram Type= 6, Freq= 0, CH_1, rank 1
8735 19:57:44.024092 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8736 19:57:44.027333 ==
8737 19:57:44.027798 RX Vref Scan: 0
8738 19:57:44.028162
8739 19:57:44.030735 RX Vref 0 -> 0, step: 1
8740 19:57:44.031239
8741 19:57:44.031594 RX Delay 3 -> 252, step: 4
8742 19:57:44.038005 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8743 19:57:44.041295 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8744 19:57:44.044993 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8745 19:57:44.047987 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8746 19:57:44.051103 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8747 19:57:44.057891 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8748 19:57:44.060980 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8749 19:57:44.064275 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8750 19:57:44.067726 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8751 19:57:44.074514 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8752 19:57:44.077356 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8753 19:57:44.080518 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8754 19:57:44.084027 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8755 19:57:44.087166 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8756 19:57:44.094034 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8757 19:57:44.097062 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8758 19:57:44.097552 ==
8759 19:57:44.100527 Dram Type= 6, Freq= 0, CH_1, rank 1
8760 19:57:44.104228 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8761 19:57:44.104785 ==
8762 19:57:44.107061 DQS Delay:
8763 19:57:44.107517 DQS0 = 0, DQS1 = 0
8764 19:57:44.110400 DQM Delay:
8765 19:57:44.110861 DQM0 = 127, DQM1 = 122
8766 19:57:44.111225 DQ Delay:
8767 19:57:44.113864 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8768 19:57:44.120358 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8769 19:57:44.123836 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8770 19:57:44.126900 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8771 19:57:44.127458
8772 19:57:44.127826
8773 19:57:44.128164
8774 19:57:44.130128 [DramC_TX_OE_Calibration] TA2
8775 19:57:44.133737 Original DQ_B0 (3 6) =30, OEN = 27
8776 19:57:44.136794 Original DQ_B1 (3 6) =30, OEN = 27
8777 19:57:44.137361 24, 0x0, End_B0=24 End_B1=24
8778 19:57:44.140141 25, 0x0, End_B0=25 End_B1=25
8779 19:57:44.143417 26, 0x0, End_B0=26 End_B1=26
8780 19:57:44.146421 27, 0x0, End_B0=27 End_B1=27
8781 19:57:44.149870 28, 0x0, End_B0=28 End_B1=28
8782 19:57:44.150423 29, 0x0, End_B0=29 End_B1=29
8783 19:57:44.153130 30, 0x0, End_B0=30 End_B1=30
8784 19:57:44.156721 31, 0x4141, End_B0=30 End_B1=30
8785 19:57:44.159998 Byte0 end_step=30 best_step=27
8786 19:57:44.162894 Byte1 end_step=30 best_step=27
8787 19:57:44.166420 Byte0 TX OE(2T, 0.5T) = (3, 3)
8788 19:57:44.166980 Byte1 TX OE(2T, 0.5T) = (3, 3)
8789 19:57:44.167350
8790 19:57:44.167691
8791 19:57:44.176465 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8792 19:57:44.179405 CH1 RK1: MR19=303, MR18=1B1B
8793 19:57:44.185943 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8794 19:57:44.189286 [RxdqsGatingPostProcess] freq 1600
8795 19:57:44.192849 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8796 19:57:44.196229 Pre-setting of DQS Precalculation
8797 19:57:44.202791 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8798 19:57:44.209489 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8799 19:57:44.216128 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8800 19:57:44.216748
8801 19:57:44.217123
8802 19:57:44.219317 [Calibration Summary] 3200 Mbps
8803 19:57:44.219781 CH 0, Rank 0
8804 19:57:44.223005 SW Impedance : PASS
8805 19:57:44.226113 DUTY Scan : NO K
8806 19:57:44.226663 ZQ Calibration : PASS
8807 19:57:44.229161 Jitter Meter : NO K
8808 19:57:44.232464 CBT Training : PASS
8809 19:57:44.232924 Write leveling : PASS
8810 19:57:44.235831 RX DQS gating : PASS
8811 19:57:44.239097 RX DQ/DQS(RDDQC) : PASS
8812 19:57:44.239649 TX DQ/DQS : PASS
8813 19:57:44.242427 RX DATLAT : PASS
8814 19:57:44.243046 RX DQ/DQS(Engine): PASS
8815 19:57:44.245949 TX OE : PASS
8816 19:57:44.246416 All Pass.
8817 19:57:44.246785
8818 19:57:44.248901 CH 0, Rank 1
8819 19:57:44.249363 SW Impedance : PASS
8820 19:57:44.252318 DUTY Scan : NO K
8821 19:57:44.255648 ZQ Calibration : PASS
8822 19:57:44.256225 Jitter Meter : NO K
8823 19:57:44.258738 CBT Training : PASS
8824 19:57:44.262289 Write leveling : PASS
8825 19:57:44.262846 RX DQS gating : PASS
8826 19:57:44.265876 RX DQ/DQS(RDDQC) : PASS
8827 19:57:44.268720 TX DQ/DQS : PASS
8828 19:57:44.269187 RX DATLAT : PASS
8829 19:57:44.272055 RX DQ/DQS(Engine): PASS
8830 19:57:44.275339 TX OE : PASS
8831 19:57:44.275804 All Pass.
8832 19:57:44.276169
8833 19:57:44.276569 CH 1, Rank 0
8834 19:57:44.278515 SW Impedance : PASS
8835 19:57:44.281893 DUTY Scan : NO K
8836 19:57:44.282358 ZQ Calibration : PASS
8837 19:57:44.285224 Jitter Meter : NO K
8838 19:57:44.288469 CBT Training : PASS
8839 19:57:44.288929 Write leveling : PASS
8840 19:57:44.291759 RX DQS gating : PASS
8841 19:57:44.295555 RX DQ/DQS(RDDQC) : PASS
8842 19:57:44.296106 TX DQ/DQS : PASS
8843 19:57:44.298586 RX DATLAT : PASS
8844 19:57:44.301977 RX DQ/DQS(Engine): PASS
8845 19:57:44.302533 TX OE : PASS
8846 19:57:44.302905 All Pass.
8847 19:57:44.305070
8848 19:57:44.305537 CH 1, Rank 1
8849 19:57:44.308469 SW Impedance : PASS
8850 19:57:44.308930 DUTY Scan : NO K
8851 19:57:44.311825 ZQ Calibration : PASS
8852 19:57:44.312333 Jitter Meter : NO K
8853 19:57:44.315222 CBT Training : PASS
8854 19:57:44.318540 Write leveling : PASS
8855 19:57:44.319096 RX DQS gating : PASS
8856 19:57:44.321565 RX DQ/DQS(RDDQC) : PASS
8857 19:57:44.325157 TX DQ/DQS : PASS
8858 19:57:44.325712 RX DATLAT : PASS
8859 19:57:44.328340 RX DQ/DQS(Engine): PASS
8860 19:57:44.331674 TX OE : PASS
8861 19:57:44.332160 All Pass.
8862 19:57:44.332587
8863 19:57:44.334939 DramC Write-DBI on
8864 19:57:44.335489 PER_BANK_REFRESH: Hybrid Mode
8865 19:57:44.338058 TX_TRACKING: ON
8866 19:57:44.348210 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8867 19:57:44.354698 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8868 19:57:44.361377 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8869 19:57:44.364963 [FAST_K] Save calibration result to emmc
8870 19:57:44.368170 sync common calibartion params.
8871 19:57:44.371577 sync cbt_mode0:0, 1:0
8872 19:57:44.372030 dram_init: ddr_geometry: 0
8873 19:57:44.374687 dram_init: ddr_geometry: 0
8874 19:57:44.377549 dram_init: ddr_geometry: 0
8875 19:57:44.381247 0:dram_rank_size:80000000
8876 19:57:44.381957 1:dram_rank_size:80000000
8877 19:57:44.387833 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8878 19:57:44.391298 DFS_SHUFFLE_HW_MODE: ON
8879 19:57:44.394392 dramc_set_vcore_voltage set vcore to 725000
8880 19:57:44.394994 Read voltage for 1600, 0
8881 19:57:44.397735 Vio18 = 0
8882 19:57:44.398282 Vcore = 725000
8883 19:57:44.398641 Vdram = 0
8884 19:57:44.400910 Vddq = 0
8885 19:57:44.401423 Vmddr = 0
8886 19:57:44.404042 switch to 3200 Mbps bootup
8887 19:57:44.404555 [DramcRunTimeConfig]
8888 19:57:44.404920 PHYPLL
8889 19:57:44.407576 DPM_CONTROL_AFTERK: ON
8890 19:57:44.411233 PER_BANK_REFRESH: ON
8891 19:57:44.411789 REFRESH_OVERHEAD_REDUCTION: ON
8892 19:57:44.414355 CMD_PICG_NEW_MODE: OFF
8893 19:57:44.417881 XRTWTW_NEW_MODE: ON
8894 19:57:44.418435 XRTRTR_NEW_MODE: ON
8895 19:57:44.421132 TX_TRACKING: ON
8896 19:57:44.421719 RDSEL_TRACKING: OFF
8897 19:57:44.424445 DQS Precalculation for DVFS: ON
8898 19:57:44.427646 RX_TRACKING: OFF
8899 19:57:44.428253 HW_GATING DBG: ON
8900 19:57:44.430885 ZQCS_ENABLE_LP4: ON
8901 19:57:44.431439 RX_PICG_NEW_MODE: ON
8902 19:57:44.434105 TX_PICG_NEW_MODE: ON
8903 19:57:44.434659 ENABLE_RX_DCM_DPHY: ON
8904 19:57:44.437296 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8905 19:57:44.440743 DUMMY_READ_FOR_TRACKING: OFF
8906 19:57:44.444298 !!! SPM_CONTROL_AFTERK: OFF
8907 19:57:44.447174 !!! SPM could not control APHY
8908 19:57:44.447636 IMPEDANCE_TRACKING: ON
8909 19:57:44.450637 TEMP_SENSOR: ON
8910 19:57:44.451198 HW_SAVE_FOR_SR: OFF
8911 19:57:44.454041 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8912 19:57:44.457446 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8913 19:57:44.460783 Read ODT Tracking: ON
8914 19:57:44.463935 Refresh Rate DeBounce: ON
8915 19:57:44.464541 DFS_NO_QUEUE_FLUSH: ON
8916 19:57:44.467330 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8917 19:57:44.470119 ENABLE_DFS_RUNTIME_MRW: OFF
8918 19:57:44.473761 DDR_RESERVE_NEW_MODE: ON
8919 19:57:44.474328 MR_CBT_SWITCH_FREQ: ON
8920 19:57:44.476895 =========================
8921 19:57:44.495574 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8922 19:57:44.498758 dram_init: ddr_geometry: 0
8923 19:57:44.517014 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8924 19:57:44.520424 dram_init: dram init end (result: 0)
8925 19:57:44.526734 DRAM-K: Full calibration passed in 23401 msecs
8926 19:57:44.530265 MRC: failed to locate region type 0.
8927 19:57:44.530887 DRAM rank0 size:0x80000000,
8928 19:57:44.533674 DRAM rank1 size=0x80000000
8929 19:57:44.543839 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8930 19:57:44.550372 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8931 19:57:44.556666 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8932 19:57:44.563252 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8933 19:57:44.566442 DRAM rank0 size:0x80000000,
8934 19:57:44.569678 DRAM rank1 size=0x80000000
8935 19:57:44.570244 CBMEM:
8936 19:57:44.573126 IMD: root @ 0xfffff000 254 entries.
8937 19:57:44.576568 IMD: root @ 0xffffec00 62 entries.
8938 19:57:44.579687 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8939 19:57:44.582871 WARNING: RO_VPD is uninitialized or empty.
8940 19:57:44.589464 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8941 19:57:44.596551 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8942 19:57:44.609048 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8943 19:57:44.620663 BS: romstage times (exec / console): total (unknown) / 22944 ms
8944 19:57:44.621202
8945 19:57:44.621563
8946 19:57:44.630387 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8947 19:57:44.633908 ARM64: Exception handlers installed.
8948 19:57:44.636985 ARM64: Testing exception
8949 19:57:44.640425 ARM64: Done test exception
8950 19:57:44.640889 Enumerating buses...
8951 19:57:44.644010 Show all devs... Before device enumeration.
8952 19:57:44.646881 Root Device: enabled 1
8953 19:57:44.650189 CPU_CLUSTER: 0: enabled 1
8954 19:57:44.650652 CPU: 00: enabled 1
8955 19:57:44.653586 Compare with tree...
8956 19:57:44.654046 Root Device: enabled 1
8957 19:57:44.657579 CPU_CLUSTER: 0: enabled 1
8958 19:57:44.660375 CPU: 00: enabled 1
8959 19:57:44.660840 Root Device scanning...
8960 19:57:44.663732 scan_static_bus for Root Device
8961 19:57:44.667088 CPU_CLUSTER: 0 enabled
8962 19:57:44.670293 scan_static_bus for Root Device done
8963 19:57:44.673517 scan_bus: bus Root Device finished in 8 msecs
8964 19:57:44.673982 done
8965 19:57:44.680518 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8966 19:57:44.683277 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8967 19:57:44.689877 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8968 19:57:44.693595 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8969 19:57:44.696477 Allocating resources...
8970 19:57:44.699988 Reading resources...
8971 19:57:44.703393 Root Device read_resources bus 0 link: 0
8972 19:57:44.703955 DRAM rank0 size:0x80000000,
8973 19:57:44.706869 DRAM rank1 size=0x80000000
8974 19:57:44.709902 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8975 19:57:44.713509 CPU: 00 missing read_resources
8976 19:57:44.719820 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8977 19:57:44.723187 Root Device read_resources bus 0 link: 0 done
8978 19:57:44.723654 Done reading resources.
8979 19:57:44.729562 Show resources in subtree (Root Device)...After reading.
8980 19:57:44.733030 Root Device child on link 0 CPU_CLUSTER: 0
8981 19:57:44.736558 CPU_CLUSTER: 0 child on link 0 CPU: 00
8982 19:57:44.746664 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8983 19:57:44.747231 CPU: 00
8984 19:57:44.750119 Root Device assign_resources, bus 0 link: 0
8985 19:57:44.753089 CPU_CLUSTER: 0 missing set_resources
8986 19:57:44.759863 Root Device assign_resources, bus 0 link: 0 done
8987 19:57:44.760470 Done setting resources.
8988 19:57:44.766394 Show resources in subtree (Root Device)...After assigning values.
8989 19:57:44.771128 Root Device child on link 0 CPU_CLUSTER: 0
8990 19:57:44.772946 CPU_CLUSTER: 0 child on link 0 CPU: 00
8991 19:57:44.783028 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8992 19:57:44.783575 CPU: 00
8993 19:57:44.786596 Done allocating resources.
8994 19:57:44.789996 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8995 19:57:44.793295 Enabling resources...
8996 19:57:44.793846 done.
8997 19:57:44.800050 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8998 19:57:44.800636 Initializing devices...
8999 19:57:44.803230 Root Device init
9000 19:57:44.803785 init hardware done!
9001 19:57:44.806573 0x00000018: ctrlr->caps
9002 19:57:44.809971 52.000 MHz: ctrlr->f_max
9003 19:57:44.810537 0.400 MHz: ctrlr->f_min
9004 19:57:44.813122 0x40ff8080: ctrlr->voltages
9005 19:57:44.813688 sclk: 390625
9006 19:57:44.816498 Bus Width = 1
9007 19:57:44.817057 sclk: 390625
9008 19:57:44.819519 Bus Width = 1
9009 19:57:44.820070 Early init status = 3
9010 19:57:44.826153 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9011 19:57:44.829287 in-header: 03 fc 00 00 01 00 00 00
9012 19:57:44.832579 in-data: 00
9013 19:57:44.835835 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9014 19:57:44.841031 in-header: 03 fd 00 00 00 00 00 00
9015 19:57:44.844327 in-data:
9016 19:57:44.847460 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9017 19:57:44.852246 in-header: 03 fc 00 00 01 00 00 00
9018 19:57:44.855934 in-data: 00
9019 19:57:44.859014 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9020 19:57:44.864815 in-header: 03 fd 00 00 00 00 00 00
9021 19:57:44.867957 in-data:
9022 19:57:44.871315 [SSUSB] Setting up USB HOST controller...
9023 19:57:44.874527 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9024 19:57:44.877856 [SSUSB] phy power-on done.
9025 19:57:44.881106 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9026 19:57:44.887485 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9027 19:57:44.891216 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9028 19:57:44.897660 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9029 19:57:44.904013 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9030 19:57:44.911207 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9031 19:57:44.917522 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9032 19:57:44.924303 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9033 19:57:44.927284 SPM: binary array size = 0x9dc
9034 19:57:44.931273 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9035 19:57:44.937382 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9036 19:57:44.944024 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9037 19:57:44.947127 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9038 19:57:44.953923 configure_display: Starting display init
9039 19:57:44.987961 anx7625_power_on_init: Init interface.
9040 19:57:44.991210 anx7625_disable_pd_protocol: Disabled PD feature.
9041 19:57:44.994684 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9042 19:57:45.022382 anx7625_start_dp_work: Secure OCM version=00
9043 19:57:45.025134 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9044 19:57:45.040165 sp_tx_get_edid_block: EDID Block = 1
9045 19:57:45.142859 Extracted contents:
9046 19:57:45.145935 header: 00 ff ff ff ff ff ff 00
9047 19:57:45.149378 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9048 19:57:45.152880 version: 01 04
9049 19:57:45.155931 basic params: 95 1f 11 78 0a
9050 19:57:45.159390 chroma info: 76 90 94 55 54 90 27 21 50 54
9051 19:57:45.162432 established: 00 00 00
9052 19:57:45.169534 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9053 19:57:45.172565 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9054 19:57:45.179051 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9055 19:57:45.185691 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9056 19:57:45.192354 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9057 19:57:45.195614 extensions: 00
9058 19:57:45.196234 checksum: fb
9059 19:57:45.196629
9060 19:57:45.202105 Manufacturer: IVO Model 57d Serial Number 0
9061 19:57:45.202646 Made week 0 of 2020
9062 19:57:45.205048 EDID version: 1.4
9063 19:57:45.205509 Digital display
9064 19:57:45.208545 6 bits per primary color channel
9065 19:57:45.209015 DisplayPort interface
9066 19:57:45.211757 Maximum image size: 31 cm x 17 cm
9067 19:57:45.215251 Gamma: 220%
9068 19:57:45.215800 Check DPMS levels
9069 19:57:45.222055 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9070 19:57:45.225230 First detailed timing is preferred timing
9071 19:57:45.225789 Established timings supported:
9072 19:57:45.228451 Standard timings supported:
9073 19:57:45.232023 Detailed timings
9074 19:57:45.235082 Hex of detail: 383680a07038204018303c0035ae10000019
9075 19:57:45.241930 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9076 19:57:45.245003 0780 0798 07c8 0820 hborder 0
9077 19:57:45.248568 0438 043b 0447 0458 vborder 0
9078 19:57:45.251983 -hsync -vsync
9079 19:57:45.252620 Did detailed timing
9080 19:57:45.258600 Hex of detail: 000000000000000000000000000000000000
9081 19:57:45.261879 Manufacturer-specified data, tag 0
9082 19:57:45.265456 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9083 19:57:45.268309 ASCII string: InfoVision
9084 19:57:45.272097 Hex of detail: 000000fe00523134304e574635205248200a
9085 19:57:45.274973 ASCII string: R140NWF5 RH
9086 19:57:45.275520 Checksum
9087 19:57:45.278186 Checksum: 0xfb (valid)
9088 19:57:45.281479 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9089 19:57:45.284838 DSI data_rate: 832800000 bps
9090 19:57:45.291215 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9091 19:57:45.294768 anx7625_parse_edid: pixelclock(138800).
9092 19:57:45.298346 hactive(1920), hsync(48), hfp(24), hbp(88)
9093 19:57:45.301573 vactive(1080), vsync(12), vfp(3), vbp(17)
9094 19:57:45.304559 anx7625_dsi_config: config dsi.
9095 19:57:45.311504 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9096 19:57:45.325035 anx7625_dsi_config: success to config DSI
9097 19:57:45.328382 anx7625_dp_start: MIPI phy setup OK.
9098 19:57:45.331510 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9099 19:57:45.334488 mtk_ddp_mode_set invalid vrefresh 60
9100 19:57:45.338669 main_disp_path_setup
9101 19:57:45.339225 ovl_layer_smi_id_en
9102 19:57:45.341677 ovl_layer_smi_id_en
9103 19:57:45.342232 ccorr_config
9104 19:57:45.342600 aal_config
9105 19:57:45.344820 gamma_config
9106 19:57:45.345373 postmask_config
9107 19:57:45.348168 dither_config
9108 19:57:45.351471 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9109 19:57:45.357907 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9110 19:57:45.361457 Root Device init finished in 555 msecs
9111 19:57:45.364551 CPU_CLUSTER: 0 init
9112 19:57:45.371406 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9113 19:57:45.374830 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9114 19:57:45.377784 APU_MBOX 0x190000b0 = 0x10001
9115 19:57:45.380942 APU_MBOX 0x190001b0 = 0x10001
9116 19:57:45.384541 APU_MBOX 0x190005b0 = 0x10001
9117 19:57:45.387804 APU_MBOX 0x190006b0 = 0x10001
9118 19:57:45.390885 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9119 19:57:45.403658 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9120 19:57:45.416335 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9121 19:57:45.422732 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9122 19:57:45.434110 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9123 19:57:45.443842 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9124 19:57:45.446873 CPU_CLUSTER: 0 init finished in 81 msecs
9125 19:57:45.450088 Devices initialized
9126 19:57:45.453478 Show all devs... After init.
9127 19:57:45.453940 Root Device: enabled 1
9128 19:57:45.456958 CPU_CLUSTER: 0: enabled 1
9129 19:57:45.460279 CPU: 00: enabled 1
9130 19:57:45.463694 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9131 19:57:45.466440 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9132 19:57:45.470171 ELOG: NV offset 0x57f000 size 0x1000
9133 19:57:45.476709 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9134 19:57:45.483385 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9135 19:57:45.486535 ELOG: Event(17) added with size 13 at 2023-10-28 19:57:46 UTC
9136 19:57:45.492957 out: cmd=0x121: 03 db 21 01 00 00 00 00
9137 19:57:45.496365 in-header: 03 f8 00 00 2c 00 00 00
9138 19:57:45.509659 in-data: 6b 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9139 19:57:45.512744 ELOG: Event(A1) added with size 10 at 2023-10-28 19:57:46 UTC
9140 19:57:45.519597 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9141 19:57:45.526282 ELOG: Event(A0) added with size 9 at 2023-10-28 19:57:46 UTC
9142 19:57:45.529606 elog_add_boot_reason: Logged dev mode boot
9143 19:57:45.536272 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9144 19:57:45.536828 Finalize devices...
9145 19:57:45.539747 Devices finalized
9146 19:57:45.542981 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9147 19:57:45.545939 Writing coreboot table at 0xffe64000
9148 19:57:45.552787 0. 000000000010a000-0000000000113fff: RAMSTAGE
9149 19:57:45.555900 1. 0000000040000000-00000000400fffff: RAM
9150 19:57:45.559527 2. 0000000040100000-000000004032afff: RAMSTAGE
9151 19:57:45.562764 3. 000000004032b000-00000000545fffff: RAM
9152 19:57:45.565814 4. 0000000054600000-000000005465ffff: BL31
9153 19:57:45.569263 5. 0000000054660000-00000000ffe63fff: RAM
9154 19:57:45.576263 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9155 19:57:45.579383 7. 0000000100000000-000000013fffffff: RAM
9156 19:57:45.582822 Passing 5 GPIOs to payload:
9157 19:57:45.586410 NAME | PORT | POLARITY | VALUE
9158 19:57:45.592877 EC in RW | 0x000000aa | low | undefined
9159 19:57:45.595862 EC interrupt | 0x00000005 | low | undefined
9160 19:57:45.602523 TPM interrupt | 0x000000ab | high | undefined
9161 19:57:45.605786 SD card detect | 0x00000011 | high | undefined
9162 19:57:45.609408 speaker enable | 0x00000093 | high | undefined
9163 19:57:45.612411 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9164 19:57:45.616320 in-header: 03 f8 00 00 02 00 00 00
9165 19:57:45.619210 in-data: 03 00
9166 19:57:45.622550 ADC[4]: Raw value=668222 ID=5
9167 19:57:45.625833 ADC[3]: Raw value=212917 ID=1
9168 19:57:45.626376 RAM Code: 0x51
9169 19:57:45.629147 ADC[6]: Raw value=74410 ID=0
9170 19:57:45.632314 ADC[5]: Raw value=211444 ID=1
9171 19:57:45.632891 SKU Code: 0x1
9172 19:57:45.639441 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3418
9173 19:57:45.639993 coreboot table: 964 bytes.
9174 19:57:45.642558 IMD ROOT 0. 0xfffff000 0x00001000
9175 19:57:45.645738 IMD SMALL 1. 0xffffe000 0x00001000
9176 19:57:45.648960 RO MCACHE 2. 0xffffc000 0x00001104
9177 19:57:45.652451 CONSOLE 3. 0xfff7c000 0x00080000
9178 19:57:45.655671 FMAP 4. 0xfff7b000 0x00000452
9179 19:57:45.658650 TIME STAMP 5. 0xfff7a000 0x00000910
9180 19:57:45.662415 VBOOT WORK 6. 0xfff66000 0x00014000
9181 19:57:45.665229 RAMOOPS 7. 0xffe66000 0x00100000
9182 19:57:45.669061 COREBOOT 8. 0xffe64000 0x00002000
9183 19:57:45.672150 IMD small region:
9184 19:57:45.675576 IMD ROOT 0. 0xffffec00 0x00000400
9185 19:57:45.678593 VPD 1. 0xffffeb80 0x0000006c
9186 19:57:45.682447 MMC STATUS 2. 0xffffeb60 0x00000004
9187 19:57:45.688515 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9188 19:57:45.689313 Probing TPM: done!
9189 19:57:45.695441 Connected to device vid:did:rid of 1ae0:0028:00
9190 19:57:45.702285 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9191 19:57:45.705193 Initialized TPM device CR50 revision 0
9192 19:57:45.708934 Checking cr50 for pending updates
9193 19:57:45.714006 Reading cr50 TPM mode
9194 19:57:45.722980 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9195 19:57:45.729111 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9196 19:57:45.769223 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9197 19:57:45.772828 Checking segment from ROM address 0x40100000
9198 19:57:45.776095 Checking segment from ROM address 0x4010001c
9199 19:57:45.782556 Loading segment from ROM address 0x40100000
9200 19:57:45.783116 code (compression=0)
9201 19:57:45.792726 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9202 19:57:45.799367 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9203 19:57:45.799912 it's not compressed!
9204 19:57:45.806093 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9205 19:57:45.809408 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9206 19:57:45.830237 Loading segment from ROM address 0x4010001c
9207 19:57:45.830791 Entry Point 0x80000000
9208 19:57:45.833303 Loaded segments
9209 19:57:45.835858 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9210 19:57:45.843252 Jumping to boot code at 0x80000000(0xffe64000)
9211 19:57:45.849773 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9212 19:57:45.856450 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9213 19:57:45.864444 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9214 19:57:45.867467 Checking segment from ROM address 0x40100000
9215 19:57:45.870980 Checking segment from ROM address 0x4010001c
9216 19:57:45.877585 Loading segment from ROM address 0x40100000
9217 19:57:45.878140 code (compression=1)
9218 19:57:45.884499 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9219 19:57:45.893791 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9220 19:57:45.894343 using LZMA
9221 19:57:45.903178 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9222 19:57:45.909099 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9223 19:57:45.912702 Loading segment from ROM address 0x4010001c
9224 19:57:45.913261 Entry Point 0x54601000
9225 19:57:45.915670 Loaded segments
9226 19:57:45.919144 NOTICE: MT8192 bl31_setup
9227 19:57:45.926255 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9228 19:57:45.929813 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9229 19:57:45.932995 WARNING: region 0:
9230 19:57:45.936032 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9231 19:57:45.936557 WARNING: region 1:
9232 19:57:45.942529 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9233 19:57:45.946174 WARNING: region 2:
9234 19:57:45.949075 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9235 19:57:45.953061 WARNING: region 3:
9236 19:57:45.956160 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9237 19:57:45.959807 WARNING: region 4:
9238 19:57:45.966064 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9239 19:57:45.966609 WARNING: region 5:
9240 19:57:45.969517 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9241 19:57:45.973065 WARNING: region 6:
9242 19:57:45.976230 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9243 19:57:45.979441 WARNING: region 7:
9244 19:57:45.982718 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9245 19:57:45.989593 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9246 19:57:45.992817 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9247 19:57:45.996054 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9248 19:57:46.003057 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9249 19:57:46.005961 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9250 19:57:46.009741 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9251 19:57:46.016339 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9252 19:57:46.019750 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9253 19:57:46.026305 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9254 19:57:46.029706 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9255 19:57:46.032798 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9256 19:57:46.039340 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9257 19:57:46.042903 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9258 19:57:46.046238 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9259 19:57:46.052977 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9260 19:57:46.055888 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9261 19:57:46.062814 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9262 19:57:46.065990 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9263 19:57:46.069003 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9264 19:57:46.075921 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9265 19:57:46.079175 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9266 19:57:46.082738 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9267 19:57:46.089103 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9268 19:57:46.092553 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9269 19:57:46.099178 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9270 19:57:46.102946 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9271 19:57:46.105920 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9272 19:57:46.112742 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9273 19:57:46.115532 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9274 19:57:46.122554 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9275 19:57:46.125673 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9276 19:57:46.129252 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9277 19:57:46.135480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9278 19:57:46.139240 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9279 19:57:46.142533 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9280 19:57:46.145959 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9281 19:57:46.152786 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9282 19:57:46.155787 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9283 19:57:46.159524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9284 19:57:46.162628 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9285 19:57:46.169254 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9286 19:57:46.172811 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9287 19:57:46.175884 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9288 19:57:46.179228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9289 19:57:46.185909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9290 19:57:46.189311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9291 19:57:46.192577 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9292 19:57:46.195920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9293 19:57:46.202932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9294 19:57:46.205870 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9295 19:57:46.212359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9296 19:57:46.215975 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9297 19:57:46.219015 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9298 19:57:46.226087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9299 19:57:46.229282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9300 19:57:46.235818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9301 19:57:46.239293 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9302 19:57:46.246046 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9303 19:57:46.249121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9304 19:57:46.252649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9305 19:57:46.259412 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9306 19:57:46.262669 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9307 19:57:46.269328 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9308 19:57:46.272420 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9309 19:57:46.279406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9310 19:57:46.282756 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9311 19:57:46.288853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9312 19:57:46.292324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9313 19:57:46.295659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9314 19:57:46.303064 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9315 19:57:46.305773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9316 19:57:46.312557 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9317 19:57:46.315869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9318 19:57:46.322550 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9319 19:57:46.325618 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9320 19:57:46.329852 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9321 19:57:46.335984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9322 19:57:46.339198 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9323 19:57:46.345926 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9324 19:57:46.349170 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9325 19:57:46.355342 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9326 19:57:46.359232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9327 19:57:46.362439 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9328 19:57:46.369148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9329 19:57:46.372717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9330 19:57:46.379246 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9331 19:57:46.382253 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9332 19:57:46.389135 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9333 19:57:46.392287 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9334 19:57:46.395824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9335 19:57:46.402499 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9336 19:57:46.405850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9337 19:57:46.412627 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9338 19:57:46.415671 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9339 19:57:46.422613 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9340 19:57:46.426105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9341 19:57:46.429110 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9342 19:57:46.435545 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9343 19:57:46.438956 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9344 19:57:46.442408 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9345 19:57:46.445709 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9346 19:57:46.452152 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9347 19:57:46.455465 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9348 19:57:46.462514 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9349 19:57:46.465467 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9350 19:57:46.469184 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9351 19:57:46.475837 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9352 19:57:46.479029 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9353 19:57:46.485602 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9354 19:57:46.489024 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9355 19:57:46.492146 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9356 19:57:46.499486 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9357 19:57:46.502670 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9358 19:57:46.508958 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9359 19:57:46.512237 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9360 19:57:46.515510 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9361 19:57:46.518790 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9362 19:57:46.525442 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9363 19:57:46.528978 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9364 19:57:46.532445 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9365 19:57:46.539152 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9366 19:57:46.542664 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9367 19:57:46.545824 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9368 19:57:46.548774 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9369 19:57:46.555622 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9370 19:57:46.559190 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9371 19:57:46.565510 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9372 19:57:46.569115 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9373 19:57:46.572387 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9374 19:57:46.579229 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9375 19:57:46.582387 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9376 19:57:46.585468 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9377 19:57:46.592552 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9378 19:57:46.595601 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9379 19:57:46.602629 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9380 19:57:46.605828 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9381 19:57:46.608903 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9382 19:57:46.616298 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9383 19:57:46.618913 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9384 19:57:46.625666 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9385 19:57:46.629138 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9386 19:57:46.632642 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9387 19:57:46.639047 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9388 19:57:46.642659 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9389 19:57:46.645756 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9390 19:57:46.652651 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9391 19:57:46.655961 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9392 19:57:46.662561 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9393 19:57:46.666020 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9394 19:57:46.669123 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9395 19:57:46.675860 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9396 19:57:46.679469 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9397 19:57:46.685873 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9398 19:57:46.689123 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9399 19:57:46.692690 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9400 19:57:46.698842 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9401 19:57:46.702531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9402 19:57:46.708910 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9403 19:57:46.712539 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9404 19:57:46.716348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9405 19:57:46.722619 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9406 19:57:46.725965 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9407 19:57:46.729367 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9408 19:57:46.735498 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9409 19:57:46.739158 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9410 19:57:46.745708 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9411 19:57:46.748953 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9412 19:57:46.752105 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9413 19:57:46.759171 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9414 19:57:46.762316 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9415 19:57:46.768831 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9416 19:57:46.771960 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9417 19:57:46.775368 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9418 19:57:46.782527 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9419 19:57:46.785739 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9420 19:57:46.791960 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9421 19:57:46.795149 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9422 19:57:46.798657 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9423 19:57:46.805003 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9424 19:57:46.808204 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9425 19:57:46.811518 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9426 19:57:46.818482 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9427 19:57:46.821642 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9428 19:57:46.828641 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9429 19:57:46.831740 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9430 19:57:46.838149 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9431 19:57:46.841520 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9432 19:57:46.845048 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9433 19:57:46.851551 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9434 19:57:46.854534 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9435 19:57:46.861401 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9436 19:57:46.864542 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9437 19:57:46.867790 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9438 19:57:46.874841 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9439 19:57:46.877919 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9440 19:57:46.884743 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9441 19:57:46.887883 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9442 19:57:46.891218 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9443 19:57:46.897757 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9444 19:57:46.901252 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9445 19:57:46.907784 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9446 19:57:46.911288 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9447 19:57:46.917886 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9448 19:57:46.920924 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9449 19:57:46.924151 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9450 19:57:46.930978 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9451 19:57:46.934523 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9452 19:57:46.940788 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9453 19:57:46.944055 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9454 19:57:46.950496 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9455 19:57:46.954170 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9456 19:57:46.957379 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9457 19:57:46.964298 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9458 19:57:46.967496 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9459 19:57:46.974090 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9460 19:57:46.977223 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9461 19:57:46.984096 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9462 19:57:46.987199 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9463 19:57:46.990560 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9464 19:57:46.997216 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9465 19:57:47.000449 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9466 19:57:47.007191 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9467 19:57:47.010366 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9468 19:57:47.013724 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9469 19:57:47.020607 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9470 19:57:47.023886 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9471 19:57:47.030484 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9472 19:57:47.033598 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9473 19:57:47.037077 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9474 19:57:47.043599 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9475 19:57:47.047205 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9476 19:57:47.050303 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9477 19:57:47.053780 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9478 19:57:47.060474 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9479 19:57:47.063785 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9480 19:57:47.066885 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9481 19:57:47.073404 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9482 19:57:47.076871 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9483 19:57:47.080530 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9484 19:57:47.086975 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9485 19:57:47.089786 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9486 19:57:47.096637 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9487 19:57:47.099752 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9488 19:57:47.103111 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9489 19:57:47.109752 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9490 19:57:47.112768 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9491 19:57:47.119708 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9492 19:57:47.122987 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9493 19:57:47.126387 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9494 19:57:47.132832 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9495 19:57:47.136390 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9496 19:57:47.139454 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9497 19:57:47.146240 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9498 19:57:47.149586 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9499 19:57:47.152770 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9500 19:57:47.159473 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9501 19:57:47.162711 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9502 19:57:47.169267 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9503 19:57:47.172666 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9504 19:57:47.175833 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9505 19:57:47.182503 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9506 19:57:47.186081 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9507 19:57:47.189097 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9508 19:57:47.195875 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9509 19:57:47.199264 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9510 19:57:47.205485 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9511 19:57:47.209011 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9512 19:57:47.212037 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9513 19:57:47.218993 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9514 19:57:47.222454 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9515 19:57:47.225872 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9516 19:57:47.228754 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9517 19:57:47.232337 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9518 19:57:47.238726 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9519 19:57:47.242036 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9520 19:57:47.245312 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9521 19:57:47.249024 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9522 19:57:47.255345 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9523 19:57:47.258645 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9524 19:57:47.261984 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9525 19:57:47.268515 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9526 19:57:47.271989 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9527 19:57:47.275426 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9528 19:57:47.281847 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9529 19:57:47.285043 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9530 19:57:47.292087 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9531 19:57:47.295188 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9532 19:57:47.298680 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9533 19:57:47.305354 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9534 19:57:47.308399 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9535 19:57:47.318126 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9536 19:57:47.319077 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9537 19:57:47.321256 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9538 19:57:47.327826 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9539 19:57:47.331156 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9540 19:57:47.337942 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9541 19:57:47.341239 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9542 19:57:47.345099 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9543 19:57:47.351511 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9544 19:57:47.354416 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9545 19:57:47.361609 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9546 19:57:47.364901 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9547 19:57:47.371345 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9548 19:57:47.374660 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9549 19:57:47.377893 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9550 19:57:47.384640 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9551 19:57:47.388089 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9552 19:57:47.394733 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9553 19:57:47.398087 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9554 19:57:47.401076 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9555 19:57:47.408227 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9556 19:57:47.411350 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9557 19:57:47.417871 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9558 19:57:47.421132 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9559 19:57:47.424370 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9560 19:57:47.431161 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9561 19:57:47.434321 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9562 19:57:47.441104 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9563 19:57:47.444238 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9564 19:57:47.450917 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9565 19:57:47.454135 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9566 19:57:47.457547 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9567 19:57:47.464154 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9568 19:57:47.467504 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9569 19:57:47.474200 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9570 19:57:47.477307 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9571 19:57:47.480556 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9572 19:57:47.487375 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9573 19:57:47.490601 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9574 19:57:47.493726 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9575 19:57:47.500494 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9576 19:57:47.503613 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9577 19:57:47.510562 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9578 19:57:47.513958 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9579 19:57:47.520631 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9580 19:57:47.523896 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9581 19:57:47.530368 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9582 19:57:47.533648 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9583 19:57:47.536959 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9584 19:57:47.543772 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9585 19:57:47.546946 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9586 19:57:47.553912 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9587 19:57:47.557039 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9588 19:57:47.560488 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9589 19:57:47.566815 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9590 19:57:47.570626 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9591 19:57:47.576878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9592 19:57:47.580023 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9593 19:57:47.583631 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9594 19:57:47.590427 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9595 19:57:47.593172 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9596 19:57:47.599744 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9597 19:57:47.602954 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9598 19:57:47.606546 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9599 19:57:47.613274 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9600 19:57:47.616640 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9601 19:57:47.623243 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9602 19:57:47.626792 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9603 19:57:47.633159 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9604 19:57:47.636833 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9605 19:57:47.643342 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9606 19:57:47.646419 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9607 19:57:47.650178 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9608 19:57:47.656320 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9609 19:57:47.659584 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9610 19:57:47.666415 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9611 19:57:47.670013 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9612 19:57:47.676401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9613 19:57:47.679394 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9614 19:57:47.682656 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9615 19:57:47.689379 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9616 19:57:47.692666 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9617 19:57:47.699485 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9618 19:57:47.702790 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9619 19:57:47.709135 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9620 19:57:47.712405 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9621 19:57:47.719418 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9622 19:57:47.722826 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9623 19:57:47.726203 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9624 19:57:47.732558 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9625 19:57:47.735992 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9626 19:57:47.742737 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9627 19:57:47.745954 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9628 19:57:47.752514 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9629 19:57:47.756063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9630 19:57:47.759219 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9631 19:57:47.766034 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9632 19:57:47.768793 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9633 19:57:47.775658 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9634 19:57:47.778969 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9635 19:57:47.785801 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9636 19:57:47.789063 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9637 19:57:47.795675 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9638 19:57:47.798830 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9639 19:57:47.802140 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9640 19:57:47.808553 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9641 19:57:47.812278 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9642 19:57:47.818761 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9643 19:57:47.822071 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9644 19:57:47.825247 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9645 19:57:47.832227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9646 19:57:47.835573 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9647 19:57:47.841875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9648 19:57:47.845555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9649 19:57:47.849142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9650 19:57:47.855401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9651 19:57:47.858446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9652 19:57:47.865423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9653 19:57:47.868804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9654 19:57:47.875407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9655 19:57:47.878362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9656 19:57:47.884942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9657 19:57:47.888523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9658 19:57:47.895270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9659 19:57:47.898253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9660 19:57:47.904769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9661 19:57:47.908151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9662 19:57:47.914956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9663 19:57:47.918398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9664 19:57:47.924776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9665 19:57:47.928561 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9666 19:57:47.934689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9667 19:57:47.938123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9668 19:57:47.944893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9669 19:57:47.948198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9670 19:57:47.954877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9671 19:57:47.958049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9672 19:57:47.964783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9673 19:57:47.967512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9674 19:57:47.974437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9675 19:57:47.977936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9676 19:57:47.984478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9677 19:57:47.987782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9678 19:57:47.994413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9679 19:57:47.997936 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9680 19:57:48.000777 INFO: [APUAPC] vio 0
9681 19:57:48.004018 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9682 19:57:48.010984 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9683 19:57:48.014142 INFO: [APUAPC] D0_APC_0: 0x400510
9684 19:57:48.017548 INFO: [APUAPC] D0_APC_1: 0x0
9685 19:57:48.018102 INFO: [APUAPC] D0_APC_2: 0x1540
9686 19:57:48.020595 INFO: [APUAPC] D0_APC_3: 0x0
9687 19:57:48.024009 INFO: [APUAPC] D1_APC_0: 0xffffffff
9688 19:57:48.027320 INFO: [APUAPC] D1_APC_1: 0xffffffff
9689 19:57:48.030905 INFO: [APUAPC] D1_APC_2: 0x3fffff
9690 19:57:48.034068 INFO: [APUAPC] D1_APC_3: 0x0
9691 19:57:48.037093 INFO: [APUAPC] D2_APC_0: 0xffffffff
9692 19:57:48.040850 INFO: [APUAPC] D2_APC_1: 0xffffffff
9693 19:57:48.044051 INFO: [APUAPC] D2_APC_2: 0x3fffff
9694 19:57:48.047257 INFO: [APUAPC] D2_APC_3: 0x0
9695 19:57:48.050691 INFO: [APUAPC] D3_APC_0: 0xffffffff
9696 19:57:48.053605 INFO: [APUAPC] D3_APC_1: 0xffffffff
9697 19:57:48.057069 INFO: [APUAPC] D3_APC_2: 0x3fffff
9698 19:57:48.059903 INFO: [APUAPC] D3_APC_3: 0x0
9699 19:57:48.063894 INFO: [APUAPC] D4_APC_0: 0xffffffff
9700 19:57:48.067070 INFO: [APUAPC] D4_APC_1: 0xffffffff
9701 19:57:48.070448 INFO: [APUAPC] D4_APC_2: 0x3fffff
9702 19:57:48.073662 INFO: [APUAPC] D4_APC_3: 0x0
9703 19:57:48.077002 INFO: [APUAPC] D5_APC_0: 0xffffffff
9704 19:57:48.080532 INFO: [APUAPC] D5_APC_1: 0xffffffff
9705 19:57:48.083488 INFO: [APUAPC] D5_APC_2: 0x3fffff
9706 19:57:48.086786 INFO: [APUAPC] D5_APC_3: 0x0
9707 19:57:48.089895 INFO: [APUAPC] D6_APC_0: 0xffffffff
9708 19:57:48.093020 INFO: [APUAPC] D6_APC_1: 0xffffffff
9709 19:57:48.096558 INFO: [APUAPC] D6_APC_2: 0x3fffff
9710 19:57:48.100002 INFO: [APUAPC] D6_APC_3: 0x0
9711 19:57:48.102919 INFO: [APUAPC] D7_APC_0: 0xffffffff
9712 19:57:48.106603 INFO: [APUAPC] D7_APC_1: 0xffffffff
9713 19:57:48.110030 INFO: [APUAPC] D7_APC_2: 0x3fffff
9714 19:57:48.112849 INFO: [APUAPC] D7_APC_3: 0x0
9715 19:57:48.116648 INFO: [APUAPC] D8_APC_0: 0xffffffff
9716 19:57:48.119696 INFO: [APUAPC] D8_APC_1: 0xffffffff
9717 19:57:48.123187 INFO: [APUAPC] D8_APC_2: 0x3fffff
9718 19:57:48.126313 INFO: [APUAPC] D8_APC_3: 0x0
9719 19:57:48.129606 INFO: [APUAPC] D9_APC_0: 0xffffffff
9720 19:57:48.132864 INFO: [APUAPC] D9_APC_1: 0xffffffff
9721 19:57:48.136545 INFO: [APUAPC] D9_APC_2: 0x3fffff
9722 19:57:48.139736 INFO: [APUAPC] D9_APC_3: 0x0
9723 19:57:48.142990 INFO: [APUAPC] D10_APC_0: 0xffffffff
9724 19:57:48.146664 INFO: [APUAPC] D10_APC_1: 0xffffffff
9725 19:57:48.149707 INFO: [APUAPC] D10_APC_2: 0x3fffff
9726 19:57:48.152993 INFO: [APUAPC] D10_APC_3: 0x0
9727 19:57:48.156435 INFO: [APUAPC] D11_APC_0: 0xffffffff
9728 19:57:48.159429 INFO: [APUAPC] D11_APC_1: 0xffffffff
9729 19:57:48.162722 INFO: [APUAPC] D11_APC_2: 0x3fffff
9730 19:57:48.166290 INFO: [APUAPC] D11_APC_3: 0x0
9731 19:57:48.169458 INFO: [APUAPC] D12_APC_0: 0xffffffff
9732 19:57:48.172645 INFO: [APUAPC] D12_APC_1: 0xffffffff
9733 19:57:48.175800 INFO: [APUAPC] D12_APC_2: 0x3fffff
9734 19:57:48.179464 INFO: [APUAPC] D12_APC_3: 0x0
9735 19:57:48.182718 INFO: [APUAPC] D13_APC_0: 0xffffffff
9736 19:57:48.185706 INFO: [APUAPC] D13_APC_1: 0xffffffff
9737 19:57:48.189184 INFO: [APUAPC] D13_APC_2: 0x3fffff
9738 19:57:48.192445 INFO: [APUAPC] D13_APC_3: 0x0
9739 19:57:48.195884 INFO: [APUAPC] D14_APC_0: 0xffffffff
9740 19:57:48.199579 INFO: [APUAPC] D14_APC_1: 0xffffffff
9741 19:57:48.202316 INFO: [APUAPC] D14_APC_2: 0x3fffff
9742 19:57:48.205714 INFO: [APUAPC] D14_APC_3: 0x0
9743 19:57:48.208889 INFO: [APUAPC] D15_APC_0: 0xffffffff
9744 19:57:48.212322 INFO: [APUAPC] D15_APC_1: 0xffffffff
9745 19:57:48.216024 INFO: [APUAPC] D15_APC_2: 0x3fffff
9746 19:57:48.219069 INFO: [APUAPC] D15_APC_3: 0x0
9747 19:57:48.222283 INFO: [APUAPC] APC_CON: 0x4
9748 19:57:48.225461 INFO: [NOCDAPC] D0_APC_0: 0x0
9749 19:57:48.229030 INFO: [NOCDAPC] D0_APC_1: 0x0
9750 19:57:48.229494 INFO: [NOCDAPC] D1_APC_0: 0x0
9751 19:57:48.232251 INFO: [NOCDAPC] D1_APC_1: 0xfff
9752 19:57:48.235503 INFO: [NOCDAPC] D2_APC_0: 0x0
9753 19:57:48.238989 INFO: [NOCDAPC] D2_APC_1: 0xfff
9754 19:57:48.242367 INFO: [NOCDAPC] D3_APC_0: 0x0
9755 19:57:48.245436 INFO: [NOCDAPC] D3_APC_1: 0xfff
9756 19:57:48.249029 INFO: [NOCDAPC] D4_APC_0: 0x0
9757 19:57:48.252229 INFO: [NOCDAPC] D4_APC_1: 0xfff
9758 19:57:48.255611 INFO: [NOCDAPC] D5_APC_0: 0x0
9759 19:57:48.258526 INFO: [NOCDAPC] D5_APC_1: 0xfff
9760 19:57:48.261876 INFO: [NOCDAPC] D6_APC_0: 0x0
9761 19:57:48.265127 INFO: [NOCDAPC] D6_APC_1: 0xfff
9762 19:57:48.265677 INFO: [NOCDAPC] D7_APC_0: 0x0
9763 19:57:48.268645 INFO: [NOCDAPC] D7_APC_1: 0xfff
9764 19:57:48.271961 INFO: [NOCDAPC] D8_APC_0: 0x0
9765 19:57:48.275387 INFO: [NOCDAPC] D8_APC_1: 0xfff
9766 19:57:48.278434 INFO: [NOCDAPC] D9_APC_0: 0x0
9767 19:57:48.281616 INFO: [NOCDAPC] D9_APC_1: 0xfff
9768 19:57:48.285088 INFO: [NOCDAPC] D10_APC_0: 0x0
9769 19:57:48.288273 INFO: [NOCDAPC] D10_APC_1: 0xfff
9770 19:57:48.291519 INFO: [NOCDAPC] D11_APC_0: 0x0
9771 19:57:48.294943 INFO: [NOCDAPC] D11_APC_1: 0xfff
9772 19:57:48.298168 INFO: [NOCDAPC] D12_APC_0: 0x0
9773 19:57:48.301340 INFO: [NOCDAPC] D12_APC_1: 0xfff
9774 19:57:48.304727 INFO: [NOCDAPC] D13_APC_0: 0x0
9775 19:57:48.307840 INFO: [NOCDAPC] D13_APC_1: 0xfff
9776 19:57:48.308351 INFO: [NOCDAPC] D14_APC_0: 0x0
9777 19:57:48.311683 INFO: [NOCDAPC] D14_APC_1: 0xfff
9778 19:57:48.314618 INFO: [NOCDAPC] D15_APC_0: 0x0
9779 19:57:48.318229 INFO: [NOCDAPC] D15_APC_1: 0xfff
9780 19:57:48.321441 INFO: [NOCDAPC] APC_CON: 0x4
9781 19:57:48.324896 INFO: [APUAPC] set_apusys_apc done
9782 19:57:48.328171 INFO: [DEVAPC] devapc_init done
9783 19:57:48.331520 INFO: GICv3 without legacy support detected.
9784 19:57:48.337992 INFO: ARM GICv3 driver initialized in EL3
9785 19:57:48.340955 INFO: Maximum SPI INTID supported: 639
9786 19:57:48.344355 INFO: BL31: Initializing runtime services
9787 19:57:48.351296 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9788 19:57:48.351857 INFO: SPM: enable CPC mode
9789 19:57:48.357783 INFO: mcdi ready for mcusys-off-idle and system suspend
9790 19:57:48.360974 INFO: BL31: Preparing for EL3 exit to normal world
9791 19:57:48.367798 INFO: Entry point address = 0x80000000
9792 19:57:48.368409 INFO: SPSR = 0x8
9793 19:57:48.374003
9794 19:57:48.374554
9795 19:57:48.374923
9796 19:57:48.377024 Starting depthcharge on Spherion...
9797 19:57:48.377490
9798 19:57:48.377855 Wipe memory regions:
9799 19:57:48.378197
9800 19:57:48.380892 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9801 19:57:48.381442 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9802 19:57:48.381893 Setting prompt string to ['asurada:']
9803 19:57:48.382329 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9804 19:57:48.383055 [0x00000040000000, 0x00000054600000)
9805 19:57:48.502968
9806 19:57:48.503661 [0x00000054660000, 0x00000080000000)
9807 19:57:48.763350
9808 19:57:48.763900 [0x000000821a7280, 0x000000ffe64000)
9809 19:57:49.508336
9810 19:57:49.508889 [0x00000100000000, 0x00000140000000)
9811 19:57:49.888790
9812 19:57:49.892811 Initializing XHCI USB controller at 0x11200000.
9813 19:57:50.929948
9814 19:57:50.932913 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9815 19:57:50.933383
9816 19:57:50.933863
9817 19:57:50.934316
9818 19:57:50.935257 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9820 19:57:51.036765 asurada: tftpboot 192.168.201.1 11899585/tftp-deploy-6kfofeti/kernel/image.itb 11899585/tftp-deploy-6kfofeti/kernel/cmdline
9821 19:57:51.037444 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9822 19:57:51.037985 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9823 19:57:51.042245 tftpboot 192.168.201.1 11899585/tftp-deploy-6kfofeti/kernel/image.itbtp-deploy-6kfofeti/kernel/cmdline
9824 19:57:51.042725
9825 19:57:51.043203 Waiting for link
9826 19:57:51.203213
9827 19:57:51.203780 R8152: Initializing
9828 19:57:51.204375
9829 19:57:51.206193 Version 9 (ocp_data = 6010)
9830 19:57:51.206760
9831 19:57:51.209729 R8152: Done initializing
9832 19:57:51.210298
9833 19:57:51.210781 Adding net device
9834 19:57:53.207052
9835 19:57:53.207656 done.
9836 19:57:53.208267
9837 19:57:53.208828 MAC: 00:e0:4c:68:03:bd
9838 19:57:53.209381
9839 19:57:53.210300 Sending DHCP discover... done.
9840 19:57:53.210828
9841 19:57:53.212788 Waiting for reply... done.
9842 19:57:53.212882
9843 19:57:53.216157 Sending DHCP request... done.
9844 19:57:53.216286
9845 19:57:53.221870 Waiting for reply... done.
9846 19:57:53.222038
9847 19:57:53.222114 My ip is 192.168.201.16
9848 19:57:53.222181
9849 19:57:53.225342 The DHCP server ip is 192.168.201.1
9850 19:57:53.225505
9851 19:57:53.231637 TFTP server IP predefined by user: 192.168.201.1
9852 19:57:53.231812
9853 19:57:53.238106 Bootfile predefined by user: 11899585/tftp-deploy-6kfofeti/kernel/image.itb
9854 19:57:53.238222
9855 19:57:53.241685 Sending tftp read request... done.
9856 19:57:53.241811
9857 19:57:53.245663 Waiting for the transfer...
9858 19:57:53.245832
9859 19:57:53.539362 00000000 ################################################################
9860 19:57:53.539533
9861 19:57:53.816695 00080000 ################################################################
9862 19:57:53.816848
9863 19:57:54.112137 00100000 ################################################################
9864 19:57:54.112289
9865 19:57:54.402793 00180000 ################################################################
9866 19:57:54.402924
9867 19:57:54.681256 00200000 ################################################################
9868 19:57:54.681409
9869 19:57:54.979518 00280000 ################################################################
9870 19:57:54.979653
9871 19:57:55.277668 00300000 ################################################################
9872 19:57:55.277804
9873 19:57:55.571794 00380000 ################################################################
9874 19:57:55.571947
9875 19:57:55.851855 00400000 ################################################################
9876 19:57:55.851992
9877 19:57:56.148881 00480000 ################################################################
9878 19:57:56.149023
9879 19:57:56.443566 00500000 ################################################################
9880 19:57:56.443696
9881 19:57:56.716103 00580000 ################################################################
9882 19:57:56.716296
9883 19:57:57.012019 00600000 ################################################################
9884 19:57:57.012184
9885 19:57:57.309230 00680000 ################################################################
9886 19:57:57.309357
9887 19:57:57.592536 00700000 ################################################################
9888 19:57:57.592669
9889 19:57:57.883685 00780000 ################################################################
9890 19:57:57.883818
9891 19:57:58.179689 00800000 ################################################################
9892 19:57:58.179869
9893 19:57:58.472380 00880000 ################################################################
9894 19:57:58.472519
9895 19:57:58.757834 00900000 ################################################################
9896 19:57:58.757975
9897 19:57:59.045251 00980000 ################################################################
9898 19:57:59.045378
9899 19:57:59.325442 00a00000 ################################################################
9900 19:57:59.325577
9901 19:57:59.617125 00a80000 ################################################################
9902 19:57:59.617251
9903 19:57:59.902106 00b00000 ################################################################
9904 19:57:59.902244
9905 19:58:00.193188 00b80000 ################################################################
9906 19:58:00.193331
9907 19:58:00.476642 00c00000 ################################################################
9908 19:58:00.476781
9909 19:58:00.763893 00c80000 ################################################################
9910 19:58:00.764024
9911 19:58:01.038132 00d00000 ################################################################
9912 19:58:01.038262
9913 19:58:01.318032 00d80000 ################################################################
9914 19:58:01.318164
9915 19:58:01.589774 00e00000 ################################################################
9916 19:58:01.589909
9917 19:58:01.888611 00e80000 ################################################################
9918 19:58:01.888744
9919 19:58:02.188872 00f00000 ################################################################
9920 19:58:02.189004
9921 19:58:02.475584 00f80000 ################################################################
9922 19:58:02.475722
9923 19:58:02.764128 01000000 ################################################################
9924 19:58:02.764304
9925 19:58:03.048657 01080000 ################################################################
9926 19:58:03.048784
9927 19:58:03.334664 01100000 ################################################################
9928 19:58:03.334795
9929 19:58:03.615317 01180000 ################################################################
9930 19:58:03.615451
9931 19:58:03.911403 01200000 ################################################################
9932 19:58:03.911541
9933 19:58:04.195724 01280000 ################################################################
9934 19:58:04.195855
9935 19:58:04.495412 01300000 ################################################################
9936 19:58:04.495550
9937 19:58:04.766173 01380000 ################################################################
9938 19:58:04.766310
9939 19:58:05.049934 01400000 ################################################################
9940 19:58:05.050065
9941 19:58:05.332336 01480000 ################################################################
9942 19:58:05.332468
9943 19:58:05.621358 01500000 ################################################################
9944 19:58:05.621526
9945 19:58:05.907077 01580000 ################################################################
9946 19:58:05.907209
9947 19:58:06.206322 01600000 ################################################################
9948 19:58:06.206454
9949 19:58:06.505569 01680000 ################################################################
9950 19:58:06.505702
9951 19:58:06.805225 01700000 ################################################################
9952 19:58:06.805363
9953 19:58:07.079033 01780000 ################################################################
9954 19:58:07.079171
9955 19:58:07.365287 01800000 ################################################################
9956 19:58:07.365420
9957 19:58:07.636081 01880000 ################################################################
9958 19:58:07.636243
9959 19:58:07.888950 01900000 ################################################################
9960 19:58:07.889108
9961 19:58:08.172537 01980000 ################################################################
9962 19:58:08.172673
9963 19:58:08.469662 01a00000 ################################################################
9964 19:58:08.469795
9965 19:58:08.767376 01a80000 ################################################################
9966 19:58:08.767508
9967 19:58:09.064045 01b00000 ################################################################
9968 19:58:09.064190
9969 19:58:09.088591 01b80000 ####### done.
9970 19:58:09.088679
9971 19:58:09.091865 The bootfile was 28890534 bytes long.
9972 19:58:09.091954
9973 19:58:09.095066 Sending tftp read request... done.
9974 19:58:09.095225
9975 19:58:09.098418 Waiting for the transfer...
9976 19:58:09.098594
9977 19:58:09.101792 00000000 # done.
9978 19:58:09.101936
9979 19:58:09.108590 Command line loaded dynamically from TFTP file: 11899585/tftp-deploy-6kfofeti/kernel/cmdline
9980 19:58:09.108777
9981 19:58:09.131614 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11899585/extract-nfsrootfs-4f9236_g,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9982 19:58:09.131872
9983 19:58:09.132023 Loading FIT.
9984 19:58:09.132158
9985 19:58:09.135290 Image ramdisk-1 has 17793697 bytes.
9986 19:58:09.135577
9987 19:58:09.138873 Image fdt-1 has 47278 bytes.
9988 19:58:09.139200
9989 19:58:09.141902 Image kernel-1 has 11047522 bytes.
9990 19:58:09.142228
9991 19:58:09.148619 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9992 19:58:09.149108
9993 19:58:09.168222 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9994 19:58:09.168803
9995 19:58:09.171545 Choosing best match conf-1 for compat google,spherion-rev3.
9996 19:58:09.177088
9997 19:58:09.181789 Connected to device vid:did:rid of 1ae0:0028:00
9998 19:58:09.188881
9999 19:58:09.191819 tpm_get_response: command 0x17b, return code 0x0
10000 19:58:09.192410
10001 19:58:09.195205 ec_init: CrosEC protocol v3 supported (256, 248)
10002 19:58:09.199152
10003 19:58:09.202276 tpm_cleanup: add release locality here.
10004 19:58:09.202742
10005 19:58:09.203108 Shutting down all USB controllers.
10006 19:58:09.205956
10007 19:58:09.206564 Removing current net device
10008 19:58:09.206943
10009 19:58:09.212417 Exiting depthcharge with code 4 at timestamp: 49060046
10010 19:58:09.212972
10011 19:58:09.215693 LZMA decompressing kernel-1 to 0x821a6718
10012 19:58:09.216157
10013 19:58:09.218916 LZMA decompressing kernel-1 to 0x40000000
10014 19:58:10.606845
10015 19:58:10.607443 jumping to kernel
10016 19:58:10.609184 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10017 19:58:10.609709 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10018 19:58:10.610118 Setting prompt string to ['Linux version [0-9]']
10019 19:58:10.610494 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10020 19:58:10.610865 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10021 19:58:10.657984
10022 19:58:10.661389 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10023 19:58:10.665068 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10024 19:58:10.665646 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10025 19:58:10.666047 Setting prompt string to []
10026 19:58:10.666459 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10027 19:58:10.666840 Using line separator: #'\n'#
10028 19:58:10.667175 No login prompt set.
10029 19:58:10.667521 Parsing kernel messages
10030 19:58:10.667827 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10031 19:58:10.668432 [login-action] Waiting for messages, (timeout 00:04:04)
10032 19:58:10.683899 [ 0.000000] Linux version 6.1.59-cip8-rt4 (KernelCI@build-j84202-arm64-gcc-10-defconfig-arm64-chromebook-st8dj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023
10033 19:58:10.687331 [ 0.000000] random: crng init done
10034 19:58:10.693793 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10035 19:58:10.697427 [ 0.000000] efi: UEFI not found.
10036 19:58:10.704039 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10037 19:58:10.713958 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10038 19:58:10.720279 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10039 19:58:10.730375 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10040 19:58:10.737531 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10041 19:58:10.743827 [ 0.000000] printk: bootconsole [mtk8250] enabled
10042 19:58:10.750690 [ 0.000000] NUMA: No NUMA configuration found
10043 19:58:10.757025 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10044 19:58:10.763417 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10045 19:58:10.763958 [ 0.000000] Zone ranges:
10046 19:58:10.769994 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10047 19:58:10.773335 [ 0.000000] DMA32 empty
10048 19:58:10.780045 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10049 19:58:10.783179 [ 0.000000] Movable zone start for each node
10050 19:58:10.787024 [ 0.000000] Early memory node ranges
10051 19:58:10.793246 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10052 19:58:10.799857 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10053 19:58:10.806804 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10054 19:58:10.813320 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10055 19:58:10.819676 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10056 19:58:10.825719 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10057 19:58:10.857353 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10058 19:58:10.863496 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10059 19:58:10.870195 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10060 19:58:10.873592 [ 0.000000] psci: probing for conduit method from DT.
10061 19:58:10.880371 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10062 19:58:10.883891 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10063 19:58:10.890168 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10064 19:58:10.893584 [ 0.000000] psci: SMC Calling Convention v1.2
10065 19:58:10.900336 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10066 19:58:10.903755 [ 0.000000] Detected VIPT I-cache on CPU0
10067 19:58:10.910188 [ 0.000000] CPU features: detected: GIC system register CPU interface
10068 19:58:10.917102 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10069 19:58:10.923407 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10070 19:58:10.930057 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10071 19:58:10.936725 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10072 19:58:10.946694 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10073 19:58:10.949680 [ 0.000000] alternatives: applying boot alternatives
10074 19:58:10.956465 [ 0.000000] Fallback order for Node 0: 0
10075 19:58:10.963012 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10076 19:58:10.966157 [ 0.000000] Policy zone: Normal
10077 19:58:10.989416 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11899585/extract-nfsrootfs-4f9236_g,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10078 19:58:10.999447 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10079 19:58:11.009154 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10080 19:58:11.015972 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10081 19:58:11.022501 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10082 19:58:11.029355 <6>[ 0.000000] software IO TLB: area num 8.
10083 19:58:11.083793 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10084 19:58:11.163768 <6>[ 0.000000] Memory: 3837636K/4191232K available (17984K kernel code, 4116K rwdata, 17476K rodata, 8448K init, 615K bss, 320828K reserved, 32768K cma-reserved)
10085 19:58:11.170548 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10086 19:58:11.177183 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10087 19:58:11.180286 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10088 19:58:11.187454 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10089 19:58:11.193542 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10090 19:58:11.197460 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10091 19:58:11.207032 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10092 19:58:11.213516 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10093 19:58:11.220140 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10094 19:58:11.226607 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10095 19:58:11.230107 <6>[ 0.000000] GICv3: 608 SPIs implemented
10096 19:58:11.233031 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10097 19:58:11.239869 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10098 19:58:11.243456 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10099 19:58:11.249809 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10100 19:58:11.262639 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10101 19:58:11.276218 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10102 19:58:11.282465 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10103 19:58:11.290920 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10104 19:58:11.304687 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10105 19:58:11.310392 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10106 19:58:11.316934 <6>[ 0.009174] Console: colour dummy device 80x25
10107 19:58:11.326871 <6>[ 0.013897] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10108 19:58:11.333373 <6>[ 0.024340] pid_max: default: 32768 minimum: 301
10109 19:58:11.336880 <6>[ 0.029240] LSM: Security Framework initializing
10110 19:58:11.343382 <6>[ 0.034152] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10111 19:58:11.353499 <6>[ 0.041757] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10112 19:58:11.360200 <6>[ 0.050978] cblist_init_generic: Setting adjustable number of callback queues.
10113 19:58:11.366395 <6>[ 0.058419] cblist_init_generic: Setting shift to 3 and lim to 1.
10114 19:58:11.376298 <6>[ 0.064756] cblist_init_generic: Setting adjustable number of callback queues.
10115 19:58:11.379689 <6>[ 0.072228] cblist_init_generic: Setting shift to 3 and lim to 1.
10116 19:58:11.386684 <6>[ 0.078666] rcu: Hierarchical SRCU implementation.
10117 19:58:11.393315 <6>[ 0.078668] rcu: Max phase no-delay instances is 1000.
10118 19:58:11.399782 <6>[ 0.078692] printk: bootconsole [mtk8250] printing thread started
10119 19:58:11.406136 <6>[ 0.096984] EFI services will not be available.
10120 19:58:11.409413 <6>[ 0.097182] smp: Bringing up secondary CPUs ...
10121 19:58:11.413102 <6>[ 0.097489] Detected VIPT I-cache on CPU1
10122 19:58:11.423139 <6>[ 0.097556] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10123 19:58:11.429278 <6>[ 0.097588] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10124 19:58:11.438381 <6>[ 0.125432] Detected VIPT I-cache on CPU2
10125 19:58:11.444668 <6>[ 0.125477] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10126 19:58:11.451495 <6>[ 0.125491] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10127 19:58:11.458304 <6>[ 0.125746] Detected VIPT I-cache on CPU3
10128 19:58:11.464302 <6>[ 0.125792] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10129 19:58:11.471226 <6>[ 0.125805] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10130 19:58:11.474766 <6>[ 0.126116] CPU features: detected: Spectre-v4
10131 19:58:11.480931 <6>[ 0.126122] CPU features: detected: Spectre-BHB
10132 19:58:11.484517 <6>[ 0.126127] Detected PIPT I-cache on CPU4
10133 19:58:11.490946 <6>[ 0.126184] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10134 19:58:11.497307 <6>[ 0.126201] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10135 19:58:11.504388 <6>[ 0.126495] Detected PIPT I-cache on CPU5
10136 19:58:11.510653 <6>[ 0.126557] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10137 19:58:11.517471 <6>[ 0.126575] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10138 19:58:11.520502 <6>[ 0.126851] Detected PIPT I-cache on CPU6
10139 19:58:11.530558 <6>[ 0.126913] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10140 19:58:11.537008 <6>[ 0.126929] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10141 19:58:11.540496 <6>[ 0.127224] Detected PIPT I-cache on CPU7
10142 19:58:11.547174 <6>[ 0.127289] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10143 19:58:11.553483 <6>[ 0.127306] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10144 19:58:11.560552 <6>[ 0.127352] smp: Brought up 1 node, 8 CPUs
10145 19:58:11.563314 <6>[ 0.127356] SMP: Total of 8 processors activated.
10146 19:58:11.570275 <6>[ 0.127359] CPU features: detected: 32-bit EL0 Support
10147 19:58:11.576813 <6>[ 0.127361] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10148 19:58:11.583418 <6>[ 0.127364] CPU features: detected: Common not Private translations
10149 19:58:11.589689 <6>[ 0.127366] CPU features: detected: CRC32 instructions
10150 19:58:11.596234 <6>[ 0.127368] CPU features: detected: RCpc load-acquire (LDAPR)
10151 19:58:11.603031 <6>[ 0.127370] CPU features: detected: LSE atomic instructions
10152 19:58:11.606276 <6>[ 0.127372] CPU features: detected: Privileged Access Never
10153 19:58:11.613211 <6>[ 0.127373] CPU features: detected: RAS Extension Support
10154 19:58:11.619599 <6>[ 0.127376] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10155 19:58:11.622657 <6>[ 0.127440] CPU: All CPU(s) started at EL2
10156 19:58:11.646316 ���ɍ��
10157 19:58:11.652624 ɍ�}���}��չѕ�5R�<6<>[ 0.343916] printk: console [ttyS0] printing thread started
10158 19:58:11.656562 5>[ <6>[ 0.343950] printk: console [ttyS0] enabled
10159 19:58:11.662676 0.224061] VFS: Disk quotas dquot_6.6.0
10160 19:58:11.669387 <6>[ 0.343954] printk: bootconsole [mtk8250] disabled
10161 19:58:11.672499 <6>[ 0.358368] printk: bootconsole [mtk8250] printing thread stopped
10162 19:58:11.679319 <6>[ 0.359411] SuperH (H)SCI(F) driver initialized
10163 19:58:11.682423 <6>[ 0.359893] msm_serial: driver initialized
10164 19:58:11.692755 <6>[ 0.364481] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10165 19:58:11.698914 <6>[ 0.364516] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10166 19:58:11.712346 <6>[ 0.364546] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10167 19:58:11.717095 <6>[ 0.364576] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10168 19:58:11.735118 <6>[ 0.364598] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10169 19:58:11.735683 <6>[ 0.364625] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10170 19:58:11.753385 <6>[ 0.364653] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10171 19:58:11.758261 <6>[ 0.364765] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10172 19:58:11.764111 <6>[ 0.364795] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10173 19:58:11.770459 <6>[ 0.375035] loop: module loaded
10174 19:58:11.773760 <6>[ 0.377496] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10175 19:58:11.777223 <4>[ 0.394370] mtk-pmic-keys: Failed to locate of_node [id: -1]
10176 19:58:11.780242 <6>[ 0.395203] megasas: 07.719.03.00-rc1
10177 19:58:11.786911 <6>[ 0.407367] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10178 19:58:11.790366 <6>[ 0.407466] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10179 19:58:11.796916 <6>[ 0.419125] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10180 19:58:11.810131 <6>[ 0.470447] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10181 19:58:12.267726 <6>[ 0.959786] Freeing initrd memory: 17376K
10182 19:58:12.275693 <6>[ 0.965485] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10183 19:58:12.282408 <6>[ 0.970325] tun: Universal TUN/TAP device driver, 1.6
10184 19:58:12.285373 <6>[ 0.971088] thunder_xcv, ver 1.0
10185 19:58:12.288864 <6>[ 0.971106] thunder_bgx, ver 1.0
10186 19:58:12.292103 <6>[ 0.971120] nicpf, ver 1.0
10187 19:58:12.298495 <6>[ 0.972206] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10188 19:58:12.305105 <6>[ 0.972209] hns3: Copyright (c) 2017 Huawei Corporation.
10189 19:58:12.308439 <6>[ 0.972235] hclge is initializing
10190 19:58:12.315623 <6>[ 0.972248] e1000: Intel(R) PRO/1000 Network Driver
10191 19:58:12.318790 <6>[ 0.972250] e1000: Copyright (c) 1999-2006 Intel Corporation.
10192 19:58:12.325781 <6>[ 0.972271] e1000e: Intel(R) PRO/1000 Network Driver
10193 19:58:12.333106 <6>[ 0.972273] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10194 19:58:12.336669 <6>[ 0.972289] igb: Intel(R) Gigabit Ethernet Network Driver
10195 19:58:12.342742 <6>[ 0.972291] igb: Copyright (c) 2007-2014 Intel Corporation.
10196 19:58:12.349988 <6>[ 0.972305] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10197 19:58:12.356490 <6>[ 0.972307] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10198 19:58:12.360075 <6>[ 0.972603] sky2: driver version 1.30
10199 19:58:12.363454 <6>[ 0.973679] VFIO - User Level meta-driver version: 0.3
10200 19:58:12.370215 <6>[ 0.976528] usbcore: registered new interface driver usb-storage
10201 19:58:12.376764 <6>[ 0.976711] usbcore: registered new device driver onboard-usb-hub
10202 19:58:12.383226 <6>[ 0.979462] mt6397-rtc mt6359-rtc: registered as rtc0
10203 19:58:12.389782 <6>[ 0.979615] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-28T19:58:13 UTC (1698523093)
10204 19:58:12.396391 <6>[ 0.980242] i2c_dev: i2c /dev entries driver
10205 19:58:12.403431 <6>[ 0.987489] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10206 19:58:12.409678 <6>[ 1.003474] cpu cpu0: EM: created perf domain
10207 19:58:12.413096 <6>[ 1.003773] cpu cpu4: EM: created perf domain
10208 19:58:12.419979 <6>[ 1.006189] sdhci: Secure Digital Host Controller Interface driver
10209 19:58:12.423120 <6>[ 1.006190] sdhci: Copyright(c) Pierre Ossman
10210 19:58:12.429661 <6>[ 1.006508] Synopsys Designware Multimedia Card Interface Driver
10211 19:58:12.436149 <6>[ 1.006842] sdhci-pltfm: SDHCI platform and OF driver helper
10212 19:58:12.442640 <6>[ 1.011183] ledtrig-cpu: registered to indicate activity on CPUs
10213 19:58:12.446314 <6>[ 1.011533] mmc0: CQHCI version 5.10
10214 19:58:12.453021 <6>[ 1.011624] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10215 19:58:12.459478 <6>[ 1.011883] usbcore: registered new interface driver usbhid
10216 19:58:12.462774 <6>[ 1.011885] usbhid: USB HID core driver
10217 19:58:12.469387 <6>[ 1.011989] spi_master spi0: will run message pump with realtime priority
10218 19:58:12.482649 <6>[ 1.043600] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10219 19:58:12.495831 <6>[ 1.045536] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10220 19:58:12.502414 <6>[ 1.047350] cros-ec-spi spi0.0: Chrome EC device registered
10221 19:58:12.512334 <6>[ 1.059078] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10222 19:58:12.515768 <6>[ 1.059930] NET: Registered PF_PACKET protocol family
10223 19:58:12.522198 <6>[ 1.060020] 9pnet: Installing 9P2000 support
10224 19:58:12.525394 <5>[ 1.060054] Key type dns_resolver registered
10225 19:58:12.528903 <6>[ 1.060409] registered taskstats version 1
10226 19:58:12.535704 <5>[ 1.060427] Loading compiled-in X.509 certificates
10227 19:58:12.545580 <4>[ 1.078779] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10228 19:58:12.555331 <4>[ 1.078967] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10229 19:58:12.562043 <3>[ 1.078980] debugfs: File 'uA_load' in directory '/' already present!
10230 19:58:12.568909 <3>[ 1.078990] debugfs: File 'min_uV' in directory '/' already present!
10231 19:58:12.575302 <3>[ 1.078994] debugfs: File 'max_uV' in directory '/' already present!
10232 19:58:12.582193 <3>[ 1.078998] debugfs: File 'constraint_flags' in directory '/' already present!
10233 19:58:12.592013 <3>[ 1.082324] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10234 19:58:12.598400 <6>[ 1.094557] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10235 19:58:12.605161 <6>[ 1.095183] xhci-mtk 11200000.usb: xHCI Host Controller
10236 19:58:12.611655 <6>[ 1.095236] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10237 19:58:12.622051 <6>[ 1.095433] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10238 19:58:12.628638 <6>[ 1.095473] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10239 19:58:12.631607 <6>[ 1.095564] xhci-mtk 11200000.usb: xHCI Host Controller
10240 19:58:12.638544 <6>[ 1.095571] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10241 19:58:12.648325 <6>[ 1.095578] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10242 19:58:12.651508 <6>[ 1.096243] hub 1-0:1.0: USB hub found
10243 19:58:12.654714 <6>[ 1.096336] hub 1-0:1.0: 1 port detected
10244 19:58:12.664777 <6>[ 1.096649] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10245 19:58:12.667980 <6>[ 1.097160] hub 2-0:1.0: USB hub found
10246 19:58:12.670864 <6>[ 1.097255] hub 2-0:1.0: 1 port detected
10247 19:58:12.677721 <6>[ 1.100350] mtk-msdc 11f70000.mmc: Got CD GPIO
10248 19:58:12.680951 <6>[ 1.106000] mmc0: Command Queue Engine enabled
10249 19:58:12.687596 <6>[ 1.106013] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10250 19:58:12.690974 <6>[ 1.106412] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10251 19:58:12.697575 <6>[ 1.109681] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10252 19:58:12.704385 <6>[ 1.110730] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10253 19:58:12.707833 <6>[ 1.111425] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10254 19:58:12.714026 <6>[ 1.111981] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10255 19:58:12.723913 <6>[ 1.118232] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10256 19:58:12.730824 <6>[ 1.118239] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10257 19:58:12.740962 <4>[ 1.118388] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10258 19:58:12.747723 <6>[ 1.119021] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10259 19:58:12.757312 <6>[ 1.119024] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10260 19:58:12.764243 <6>[ 1.119144] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10261 19:58:12.770629 <6>[ 1.119158] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10262 19:58:12.780349 <6>[ 1.119162] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10263 19:58:12.787116 <6>[ 1.119167] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10264 19:58:12.797243 <6>[ 1.120908] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10265 19:58:12.807113 <6>[ 1.120942] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10266 19:58:12.813520 <6>[ 1.120948] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10267 19:58:12.823654 <6>[ 1.120955] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10268 19:58:12.829827 <6>[ 1.120962] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10269 19:58:12.840085 <6>[ 1.120969] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10270 19:58:12.846723 <6>[ 1.120975] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10271 19:58:12.856783 <6>[ 1.120981] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10272 19:58:12.863099 <6>[ 1.120987] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10273 19:58:12.872989 <6>[ 1.120993] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10274 19:58:12.879595 <6>[ 1.120999] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10275 19:58:12.889289 <6>[ 1.121005] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10276 19:58:12.896215 <6>[ 1.121011] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10277 19:58:12.906108 <6>[ 1.121017] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10278 19:58:12.912901 <6>[ 1.121023] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10279 19:58:12.919657 <6>[ 1.121547] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10280 19:58:12.926141 <6>[ 1.122429] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10281 19:58:12.932849 <6>[ 1.122972] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10282 19:58:12.939414 <6>[ 1.123583] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10283 19:58:12.946087 <6>[ 1.124243] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10284 19:58:12.956051 <6>[ 1.124466] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10285 19:58:12.965658 <6>[ 1.124477] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10286 19:58:12.975401 <6>[ 1.124482] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10287 19:58:12.985273 <6>[ 1.124488] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10288 19:58:12.992105 <6>[ 1.124493] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10289 19:58:13.001915 <6>[ 1.124503] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10290 19:58:13.011912 <6>[ 1.124511] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10291 19:58:13.021689 <6>[ 1.124515] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10292 19:58:13.031332 <6>[ 1.124520] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10293 19:58:13.041382 <6>[ 1.124527] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10294 19:58:13.051491 <6>[ 1.124531] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10295 19:58:13.057899 <6>[ 1.125137] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10296 19:58:13.064437 <6>[ 1.135201] Trying to probe devices needed for running init ...
10297 19:58:13.071199 <6>[ 1.480329] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10298 19:58:13.074280 <6>[ 1.506727] hub 2-1:1.0: USB hub found
10299 19:58:13.080780 <6>[ 1.507014] hub 2-1:1.0: 3 ports detected
10300 19:58:13.087518 <6>[ 1.628092] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10301 19:58:13.090942 <6>[ 1.781023] hub 1-1:1.0: USB hub found
10302 19:58:13.093872 <6>[ 1.781415] hub 1-1:1.0: 4 ports detected
10303 19:58:13.171193 <6>[ 1.856486] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10304 19:58:13.406941 <6>[ 2.092278] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10305 19:58:13.532162 <6>[ 2.220012] hub 1-1.4:1.0: USB hub found
10306 19:58:13.535287 <6>[ 2.220464] hub 1-1.4:1.0: 2 ports detected
10307 19:58:13.822770 <6>[ 2.508247] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10308 19:58:14.006834 <6>[ 2.692248] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10309 19:58:24.715303 <6>[ 13.409241] ALSA device list:
10310 19:58:24.721591 <6>[ 13.409262] No soundcards found.
10311 19:58:24.724803 <6>[ 13.413450] Freeing unused kernel memory: 8448K
10312 19:58:24.728448 <6>[ 13.413591] Run /init as init process
10313 19:58:24.731486 Loading, please wait...
10314 19:58:24.750449 Starting version 247.3-7+deb11u2
10315 19:58:24.937746 <6>[ 13.624810] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10316 19:58:24.944171 <3>[ 13.626651] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10317 19:58:24.954055 <3>[ 13.626684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10318 19:58:24.960560 <3>[ 13.626699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10319 19:58:24.970267 <3>[ 13.626903] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10320 19:58:24.977059 <3>[ 13.626915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10321 19:58:24.987088 <3>[ 13.626922] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10322 19:58:24.993494 <3>[ 13.626933] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10323 19:58:25.003524 <3>[ 13.626942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10324 19:58:25.010155 <3>[ 13.627010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10325 19:58:25.016701 <3>[ 13.627066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10326 19:58:25.027227 <3>[ 13.627075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10327 19:58:25.034054 <3>[ 13.627083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10328 19:58:25.044121 <3>[ 13.627151] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10329 19:58:25.051425 <3>[ 13.627161] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10330 19:58:25.057883 <3>[ 13.627169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10331 19:58:25.067850 <3>[ 13.627178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10332 19:58:25.074654 <3>[ 13.627187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10333 19:58:25.084713 <3>[ 13.627238] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10334 19:58:25.087917 <6>[ 13.636918] remoteproc remoteproc0: scp is available
10335 19:58:25.094466 <6>[ 13.637294] remoteproc remoteproc0: powering up scp
10336 19:58:25.100899 <6>[ 13.637312] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10337 19:58:25.108028 <6>[ 13.637370] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10338 19:58:25.114033 <6>[ 13.678366] usbcore: registered new interface driver r8152
10339 19:58:25.120887 <6>[ 13.685619] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10340 19:58:25.130582 <6>[ 13.685652] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10341 19:58:25.137208 <6>[ 13.685658] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10342 19:58:25.144025 <6>[ 13.685950] mc: Linux media interface: v0.10
10343 19:58:25.150426 <6>[ 13.690247] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10344 19:58:25.156862 <6>[ 13.693389] videodev: Linux video capture interface: v2.00
10345 19:58:25.160487 <6>[ 13.702192] usbcore: registered new interface driver cdc_ether
10346 19:58:25.170396 <4>[ 13.712526] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10347 19:58:25.176757 <4>[ 13.712526] Fallback method does not support PEC.
10348 19:58:25.183547 <3>[ 13.729231] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10349 19:58:25.190105 <4>[ 13.730731] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10350 19:58:25.200411 <4>[ 13.730903] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10351 19:58:25.206913 <6>[ 13.739116] usbcore: registered new interface driver r8153_ecm
10352 19:58:25.213350 <3>[ 13.749334] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10353 19:58:25.216428 <6>[ 13.752466] Bluetooth: Core ver 2.22
10354 19:58:25.223750 <6>[ 13.752861] NET: Registered PF_BLUETOOTH protocol family
10355 19:58:25.230005 <6>[ 13.752866] Bluetooth: HCI device and connection manager initialized
10356 19:58:25.236473 <6>[ 13.752927] Bluetooth: HCI socket layer initialized
10357 19:58:25.239722 <6>[ 13.752947] Bluetooth: L2CAP socket layer initialized
10358 19:58:25.246639 <6>[ 13.752983] Bluetooth: SCO socket layer initialized
10359 19:58:25.252728 <6>[ 13.763096] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10360 19:58:25.259298 <6>[ 13.763096] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10361 19:58:25.266111 <6>[ 13.763140] remoteproc remoteproc0: remote processor scp is now up
10362 19:58:25.276335 <6>[ 13.764408] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10363 19:58:25.282555 <6>[ 13.788142] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10364 19:58:25.292646 <6>[ 13.789646] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10365 19:58:25.299447 <4>[ 13.791137] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10366 19:58:25.309061 <4>[ 13.791142] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10367 19:58:25.315663 <6>[ 13.809232] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10368 19:58:25.322303 <6>[ 13.809241] pci_bus 0000:00: root bus resource [bus 00-ff]
10369 19:58:25.328849 <6>[ 13.809246] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10370 19:58:25.338791 <6>[ 13.809249] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10371 19:58:25.345202 <6>[ 13.809288] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10372 19:58:25.351897 <6>[ 13.809304] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10373 19:58:25.355261 <6>[ 13.809375] pci 0000:00:00.0: supports D1 D2
10374 19:58:25.361927 <6>[ 13.809377] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10375 19:58:25.371464 <6>[ 13.810243] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10376 19:58:25.378148 <6>[ 13.810313] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10377 19:58:25.385031 <6>[ 13.810336] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10378 19:58:25.391790 <6>[ 13.810351] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10379 19:58:25.398189 <6>[ 13.810366] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10380 19:58:25.405073 <6>[ 13.810467] pci 0000:01:00.0: supports D1 D2
10381 19:58:25.411609 <6>[ 13.810468] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10382 19:58:25.418051 <6>[ 13.824140] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10383 19:58:25.424797 <6>[ 13.824165] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10384 19:58:25.434580 <6>[ 13.824167] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10385 19:58:25.440830 <6>[ 13.824174] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10386 19:58:25.450749 <6>[ 13.824187] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10387 19:58:25.457317 <6>[ 13.824199] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10388 19:58:25.464026 <6>[ 13.824210] pci 0000:00:00.0: PCI bridge to [bus 01]
10389 19:58:25.470605 <6>[ 13.824215] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10390 19:58:25.477497 <6>[ 13.824346] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10391 19:58:25.484011 <6>[ 13.824843] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10392 19:58:25.490683 <6>[ 13.825580] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10393 19:58:25.497067 <6>[ 13.839306] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10394 19:58:25.503824 <6>[ 13.844234] r8152 2-1.3:1.0 eth0: v1.12.13
10395 19:58:25.513573 <6>[ 13.853049] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10396 19:58:25.523271 <6>[ 13.853413] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10397 19:58:25.529865 <5>[ 13.877515] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10398 19:58:25.536621 <6>[ 13.883950] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10399 19:58:25.543246 <5>[ 13.888609] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10400 19:58:25.549978 <6>[ 13.891643] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10401 19:58:25.563449 <6>[ 13.892774] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10402 19:58:25.569752 <6>[ 13.892852] usbcore: registered new interface driver uvcvideo
10403 19:58:25.576269 <6>[ 13.922515] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10404 19:58:25.579433 <6>[ 13.929023] usbcore: registered new interface driver btusb
10405 19:58:25.589559 <4>[ 13.929905] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10406 19:58:25.596373 <3>[ 13.929917] Bluetooth: hci0: Failed to load firmware file (-2)
10407 19:58:25.602775 <3>[ 13.929921] Bluetooth: hci0: Failed to set up firmware (-2)
10408 19:58:25.612715 <4>[ 13.929927] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10409 19:58:25.622310 <4>[ 14.152632] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10410 19:58:25.625709 <6>[ 14.152645] cfg80211: failed to load regulatory.db
10411 19:58:25.635472 <6>[ 14.228896] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10412 19:58:25.642105 <6>[ 14.228989] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10413 19:58:25.645428 <6>[ 14.248178] mt7921e 0000:01:00.0: ASIC revision: 79610010
10414 19:58:25.658745 <4>[ 14.343280] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10415 19:58:25.667739 Begin: Loading essential drivers ... done.
10416 19:58:25.671256 Begin: Running /scripts/init-premount ... done.
10417 19:58:25.677509 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10418 19:58:25.687868 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10419 19:58:25.690747 Device /sys/class/net/enx00e04c6803bd found
10420 19:58:25.691352 done.
10421 19:58:25.733709 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10422 19:58:25.764800 <4>[ 14.450133] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10423 19:58:25.868887 <4>[ 14.553179] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10424 19:58:25.972932 <4>[ 14.656961] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10425 19:58:26.076869 <4>[ 14.760883] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10426 19:58:26.180796 <4>[ 14.864800] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10427 19:58:26.284888 <4>[ 14.968750] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10428 19:58:26.389166 <4>[ 15.072736] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10429 19:58:26.493125 <4>[ 15.176671] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10430 19:58:26.596985 <4>[ 15.280650] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10431 19:58:26.690209 <3>[ 15.382564] mt7921e 0000:01:00.0: hardware init failed
10432 19:58:26.785800 IP-Config: no response after 2 secs - giving up
10433 19:58:26.817668 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10434 19:58:26.826197 <6>[ 15.516701] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10435 19:58:27.922901 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10436 19:58:27.929489 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10437 19:58:27.936168 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10438 19:58:27.942965 host : mt8192-asurada-spherion-r0-cbg-4
10439 19:58:27.949573 domain : lava-rack
10440 19:58:27.952632 rootserver: 192.168.201.1 rootpath:
10441 19:58:27.955933 filename :
10442 19:58:28.029204 done.
10443 19:58:28.036880 Begin: Running /scripts/nfs-bottom ... done.
10444 19:58:28.054033 Begin: Running /scripts/init-bottom ... done.
10445 19:58:29.265526 <6>[ 17.956430] NET: Registered PF_INET6 protocol family
10446 19:58:29.268899 <6>[ 17.958201] Segment Routing with IPv6
10447 19:58:29.275899 <6>[ 17.958228] In-situ OAM (IOAM) with IPv6
10448 19:58:29.393673 <30>[ 18.066697] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10449 19:58:29.396836 <30>[ 18.067714] systemd[1]: Detected architecture arm64.
10450 19:58:29.397429
10451 19:58:29.403788 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10452 19:58:29.404404
10453 19:58:29.425887 <30>[ 18.118908] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10454 19:58:30.280880 <30>[ 18.969309] systemd[1]: Queued start job for default target Graphical Interface.
10455 19:58:30.303751 [[0;32m OK [<30>[ 18.994620] systemd[1]: Created slice system-getty.slice.
10456 19:58:30.307010 0m] Created slice [0;1;39msystem-getty.slice[0m.
10457 19:58:30.326566 [[0;32m OK [0m] Created slic<30>[ 19.017604] systemd[1]: Created slice system-modprobe.slice.
10458 19:58:30.330091 e [0;1;39msystem-modprobe.slice[0m.
10459 19:58:30.350488 [[0;32m OK [0m] Created slic<30>[ 19.041491] systemd[1]: Created slice system-serial\x2dgetty.slice.
10460 19:58:30.357057 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10461 19:58:30.375328 [[0;32m OK [0m] Created slic<30>[ 19.066073] systemd[1]: Created slice User and Session Slice.
10462 19:58:30.378558 e [0;1;39mUser and Session Slice[0m.
10463 19:58:30.401415 [[0;32m OK [0m] Started [0;<30>[ 19.089078] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10464 19:58:30.405041 1;39mDispatch Password …ts to Console Directory Watch[0m.
10465 19:58:30.429621 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.116992] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10466 19:58:30.432959 sword R…uests to Wall Directory Watch[0m.
10467 19:58:30.460998 [[0;32m OK [0m] Reached targ<30>[ 19.144801] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10468 19:58:30.467524 <30>[ 19.145051] systemd[1]: Reached target Local Encrypted Volumes.
10469 19:58:30.470614 et [0;1;39mLocal Encrypted Volumes[0m.
10470 19:58:30.489718 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.180373] systemd[1]: Reached target Paths.
10471 19:58:30.490263 s[0m.
10472 19:58:30.512776 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.200253] systemd[1]: Reached target Remote File Systems.
10473 19:58:30.513334 te File Systems[0m.
10474 19:58:30.533288 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.224212] systemd[1]: Reached target Slices.
10475 19:58:30.533876 es[0m.
10476 19:58:30.553239 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.244258] systemd[1]: Reached target Swap.
10477 19:58:30.553785 [0m.
10478 19:58:30.577128 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.264698] systemd[1]: Listening on initctl Compatibility Named Pipe.
10479 19:58:30.580113 l Compatibility Named Pipe[0m.
10480 19:58:30.590721 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.280829] systemd[1]: Listening on Journal Audit Socket.
10481 19:58:30.593667 l Audit Socket[0m.
10482 19:58:30.614992 [[0;32m OK [0m] Listening on<30>[ 19.305657] systemd[1]: Listening on Journal Socket (/dev/log).
10483 19:58:30.618101 [0;1;39mJournal Socket (/dev/log)[0m.
10484 19:58:30.638668 [[0;32m OK [0m] Listening on<30>[ 19.329517] systemd[1]: Listening on Journal Socket.
10485 19:58:30.642045 [0;1;39mJournal Socket[0m.
10486 19:58:30.659177 [[0;32m OK [0m] Listening on<30>[ 19.350101] systemd[1]: Listening on Network Service Netlink Socket.
10487 19:58:30.665773 [0;1;39mNetwork Service Netlink Socket[0m.
10488 19:58:30.685440 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 19.376251] systemd[1]: Listening on udev Control Socket.
10489 19:58:30.688413 ontrol Socket[0m.
10490 19:58:30.705649 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 19.396720] systemd[1]: Listening on udev Kernel Socket.
10491 19:58:30.708794 ernel Socket[0m.
10492 19:58:30.761938 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.452684] systemd[1]: Mounting Huge Pages File System...
10493 19:58:30.764818 m[0m...
10494 19:58:30.788662 Mounting [0;1;39mPOSIX Message Queue F<30>[ 19.476703] systemd[1]: Mounting POSIX Message Queue File System...
10495 19:58:30.789212 ile System[0m...
10496 19:58:30.811899 Mountin<30>[ 19.503039] systemd[1]: Mounting Kernel Debug File System...
10497 19:58:30.815300 g [0;1;39mKernel Debug File System[0m...
10498 19:58:30.836777 <30>[ 19.524599] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10499 19:58:30.846804 <30>[ 19.529303] systemd[1]: Starting Create list of static device nodes for the current kernel...
10500 19:58:30.853457 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10501 19:58:30.921297 Starting [0;1;39mLoad Kernel Module co<30>[ 19.609040] systemd[1]: Starting Load Kernel Module configfs...
10502 19:58:30.921847 nfigfs[0m...
10503 19:58:30.943068 Starting [0;1;39mLoad <30>[ 19.634004] systemd[1]: Starting Load Kernel Module drm...
10504 19:58:30.946547 Kernel Module drm[0m...
10505 19:58:30.974486 Starting [0;1;39mLoad <30>[ 19.665367] systemd[1]: Starting Load Kernel Module fuse...
10506 19:58:30.977692 Kernel Module fuse[0m...
10507 19:58:31.009491 <6>[ 19.703439] fuse: init (API version 7.37)
10508 19:58:31.019362 <30>[ 19.703779] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10509 19:58:31.045966 Starting [0;1;39mJournal Service[0m..<30>[ 19.736872] systemd[1]: Starting Journal Service...
10510 19:58:31.046516 .
10511 19:58:31.076476 Startin<30>[ 19.767380] systemd[1]: Starting Load Kernel Modules...
10512 19:58:31.079376 g [0;1;39mLoad Kernel Modules[0m...
10513 19:58:31.107715 Startin<30>[ 19.798817] systemd[1]: Starting Remount Root and Kernel File Systems...
10514 19:58:31.111193 g [0;1;39mRemount Root and Kernel File Systems[0m...
10515 19:58:31.133300 <30>[ 19.827804] systemd[1]: Starting Coldplug All udev Devices...
10516 19:58:31.140009 Starting [0;1;39mColdplug All udev Devices[0m...
10517 19:58:31.163338 [[0;32m OK [0m] Mounted [0;<30>[ 19.854316] systemd[1]: Mounted Huge Pages File System.
10518 19:58:31.166679 1;39mHuge Pages File System[0m.
10519 19:58:31.188749 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Messa<30>[ 19.876764] systemd[1]: Mounted POSIX Message Queue File System.
10520 19:58:31.189219 ge Queue File System[0m.
10521 19:58:31.210746 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 19.900959] systemd[1]: Mounted Kernel Debug File System.
10522 19:58:31.220777 g File System[0<3>[ 19.909182] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10523 19:58:31.221255 m.
10524 19:58:31.241044 <3>[ 19.931797] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10525 19:58:31.254350 [[0;32m OK [0m] Finished [0<30>[ 19.942230] systemd[1]: Finished Create list of static device nodes for the current kernel.
10526 19:58:31.260982 ;1;39mCreate list of st… nodes for the current kernel[0m.
10527 19:58:31.278149 <30>[ 19.969131] systemd[1]: modprobe@configfs.service: Succeeded.
10528 19:58:31.288246 [[0;32m OK [0m] Finished [0<30>[ 19.976008] systemd[1]: Finished Load Kernel Module configfs.
10529 19:58:31.298085 ;1;39mLoad Kerne<3>[ 19.982965] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10530 19:58:31.298624 l Module configfs[0m.
10531 19:58:31.312546 <3>[ 20.002617] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10532 19:58:31.327603 [[0;32m OK [0m] Finished [0<30>[ 20.016469] systemd[1]: modprobe@drm.service: Succeeded.
10533 19:58:31.334659 ;1;39mLoad Kerne<30>[ 20.017980] systemd[1]: Finished Load Kernel Module drm.
10534 19:58:31.344342 <3>[ 20.029157] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10535 19:58:31.344903 l Module drm[0m.
10536 19:58:31.365128 <3>[ 20.054583] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10537 19:58:31.375753 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<30>[ 20.058907] systemd[1]: modprobe@fuse.service: Succeeded.
10538 19:58:31.382231 <30>[ 20.060187] systemd[1]: Finished Load Kernel Module fuse.
10539 19:58:31.389102 <3>[ 20.077964] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10540 19:58:31.392624 l Module fuse[0m.
10541 19:58:31.411542 [[0;32m OK [0m] Finished [0<30>[ 20.102308] systemd[1]: Finished Load Kernel Modules.
10542 19:58:31.422336 ;1;39mLoad Kerne<3>[ 20.103505] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10543 19:58:31.422920 l Modules[0m.
10544 19:58:31.436889 <3>[ 20.127396] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10545 19:58:31.448564 [[0;32m OK [<30>[ 20.138693] systemd[1]: Finished Remount Root and Kernel File Systems.
10546 19:58:31.451593 0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10547 19:58:31.461922 <3>[ 20.148944] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10548 19:58:31.462482
10549 19:58:31.507690 Mountin<30>[ 20.198824] systemd[1]: Mounting FUSE Control File System...
10550 19:58:31.510966 g [0;1;39mFUSE Control File System[0m...
10551 19:58:31.537326 Mounting [0;1;39mKernel Configuration <30>[ 20.224848] systemd[1]: Mounting Kernel Configuration File System...
10552 19:58:31.538093 File System[0m...
10553 19:58:31.569214 <30>[ 20.258841] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10554 19:58:31.579081 <30>[ 20.259158] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10555 19:58:31.585736 <30>[ 20.263660] systemd[1]: Starting Load/Save Random Seed...
10556 19:58:31.588927 Starting [0;1;39mLoad/Save Random Seed[0m...
10557 19:58:31.615112 Starting [0;1;39mApply<30>[ 20.305148] systemd[1]: Starting Apply Kernel Variables...
10558 19:58:31.617987 Kernel Variables[0m...
10559 19:58:31.631779 <4>[ 20.315107] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10560 19:58:31.638398 <3>[ 20.315120] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10561 19:58:31.648522 Startin<30>[ 20.338448] systemd[1]: Starting Create System Users...
10562 19:58:31.651545 g [0;1;39mCreate System Users[0m...
10563 19:58:31.670734 [[0;32m OK [0m] Started [0;<30>[ 20.362261] systemd[1]: Started Journal Service.
10564 19:58:31.674131 1;39mJournal Service[0m.
10565 19:58:31.692526 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10566 19:58:31.705017 See 'systemctl status systemd-udev-trigger.service' for details.
10567 19:58:31.721427 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10568 19:58:31.737341 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10569 19:58:31.759213 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10570 19:58:31.779168 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10571 19:58:31.799689 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10572 19:58:31.834600 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10573 19:58:31.853349 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10574 19:58:31.908314 <46>[ 20.596656] systemd-journald[303]: Received client request to flush runtime journal.
10575 19:58:31.932555 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10576 19:58:31.946676 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10577 19:58:31.961569 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10578 19:58:32.014035 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10579 19:58:33.335702 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10580 19:58:33.373878 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10581 19:58:33.403711 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10582 19:58:33.448161 Starting [0;1;39mNetwork Service[0m...
10583 19:58:33.733403 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10584 19:58:33.793483 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10585 19:58:33.814715 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10586 19:58:34.118821 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10587 19:58:34.136701 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10588 19:58:34.190171 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10589 19:58:34.206602 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10590 19:58:34.227815 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10591 19:58:34.245754 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10592 19:58:34.270675 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10593 19:58:34.346166 Starting [0;1;39mNetwork Name Resolution[0m...
10594 19:58:34.376931 Starting [0;1;39mNetwork Time Synchronization[0m...
10595 19:58:34.396139 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10596 19:58:34.440559 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10597 19:58:34.549047 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10598 19:58:34.565796 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10599 19:58:34.584509 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10600 19:58:34.601001 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10601 19:58:34.620891 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10602 19:58:34.653235 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10603 19:58:34.719515 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10604 19:58:34.775229 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10605 19:58:34.810497 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10606 19:58:34.825103 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10607 19:58:34.872154 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10608 19:58:34.885174 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10609 19:58:34.901022 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10610 19:58:34.945937 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10611 19:58:35.645376 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10612 19:58:36.037777 Starting [0;1;39mUser Login Management[0m...
10613 19:58:36.147030 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10614 19:58:36.161752 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10615 19:58:36.180383 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10616 19:58:36.231029 Starting [0;1;39mPermit User Sessions[0m...
10617 19:58:36.300348 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10618 19:58:36.380964 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10619 19:58:36.426620 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10620 19:58:36.447929 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10621 19:58:36.469752 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10622 19:58:36.486536 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10623 19:58:36.495637 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10624 19:58:36.514355 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10625 19:58:36.567306 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10626 19:58:36.619620 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10627 19:58:36.690962
10628 19:58:36.691509
10629 19:58:36.694177 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10630 19:58:36.694635
10631 19:58:36.697536 debian-bullseye-arm64 login: root (automatic login)
10632 19:58:36.697999
10633 19:58:36.698362
10634 19:58:37.074505 Linux debian-bullseye-arm64 6.1.59-cip8-rt4 #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023 aarch64
10635 19:58:37.075004
10636 19:58:37.081166 The programs included with the Debian GNU/Linux system are free software;
10637 19:58:37.087712 the exact distribution terms for each program are described in the
10638 19:58:37.091018 individual files in /usr/share/doc/*/copyright.
10639 19:58:37.091535
10640 19:58:37.097622 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10641 19:58:37.100712 permitted by applicable law.
10642 19:58:38.046273 Matched prompt #10: / #
10644 19:58:38.047515 Setting prompt string to ['/ #']
10645 19:58:38.048012 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10647 19:58:38.049333 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10648 19:58:38.049835 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
10649 19:58:38.050289 Setting prompt string to ['/ #']
10650 19:58:38.050643 Forcing a shell prompt, looking for ['/ #']
10652 19:58:38.101622 / #
10653 19:58:38.102274 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10654 19:58:38.102722 Waiting using forced prompt support (timeout 00:02:30)
10655 19:58:38.108069
10656 19:58:38.109058 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10657 19:58:38.109580 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
10659 19:58:38.210910 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11899585/extract-nfsrootfs-4f9236_g'
10660 19:58:38.217478 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11899585/extract-nfsrootfs-4f9236_g'
10662 19:58:38.319291 / # export NFS_SERVER_IP='192.168.201.1'
10663 19:58:38.325939 export NFS_SERVER_IP='192.168.201.1'
10664 19:58:38.326886 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10665 19:58:38.327425 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
10666 19:58:38.327950 end: 2 depthcharge-action (duration 00:01:24) [common]
10667 19:58:38.328628 start: 3 lava-test-retry (timeout 00:07:57) [common]
10668 19:58:38.329123 start: 3.1 lava-test-shell (timeout 00:07:57) [common]
10669 19:58:38.329545 Using namespace: common
10671 19:58:38.430724 / # #
10672 19:58:38.431375 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10673 19:58:38.437025 #
10674 19:58:38.437911 Using /lava-11899585
10676 19:58:38.539114 / # export SHELL=/bin/bash
10677 19:58:38.545622 export SHELL=/bin/bash
10679 19:58:38.647501 / # . /lava-11899585/environment
10680 19:58:38.654152 . /lava-11899585/environment
10682 19:58:38.761678 / # /lava-11899585/bin/lava-test-runner /lava-11899585/0
10683 19:58:38.762316 Test shell timeout: 10s (minimum of the action and connection timeout)
10684 19:58:38.767996 /lava-11899585/bin/lava-test-runner /lava-11899585/0
10685 19:58:39.049388 + export TESTRUN_ID=0_timesync-off
10686 19:58:39.052464 + TESTRUN_ID=0_timesync-off
10687 19:58:39.055659 + cd /lava-11899585/0/tests/0_timesync-off
10688 19:58:39.058911 ++ cat uuid
10689 19:58:39.062335 + UUID=11899585_1.6.2.3.1
10690 19:58:39.062799 + set +x
10691 19:58:39.069109 <LAVA_SIGNAL_STARTRUN 0_timesync-off 11899585_1.6.2.3.1>
10692 19:58:39.069847 Received signal: <STARTRUN> 0_timesync-off 11899585_1.6.2.3.1
10693 19:58:39.070259 Starting test lava.0_timesync-off (11899585_1.6.2.3.1)
10694 19:58:39.070718 Skipping test definition patterns.
10695 19:58:39.072156 + systemctl stop systemd-timesyncd
10696 19:58:39.108820 + set +x
10697 19:58:39.112058 <LAVA_SIGNAL_ENDRUN 0_timesync-off 11899585_1.6.2.3.1>
10698 19:58:39.112756 Received signal: <ENDRUN> 0_timesync-off 11899585_1.6.2.3.1
10699 19:58:39.113168 Ending use of test pattern.
10700 19:58:39.113489 Ending test lava.0_timesync-off (11899585_1.6.2.3.1), duration 0.04
10702 19:58:39.183331 + export TESTRUN_ID=1_kselftest-tpm2
10703 19:58:39.186588 + TESTRUN_ID=1_kselftest-tpm2
10704 19:58:39.193106 + cd /lava-11899585/0/tests/1_kselftest-tpm2
10705 19:58:39.193581 ++ cat uuid
10706 19:58:39.198176 + UUID=11899585_1.6.2.3.5
10707 19:58:39.198664 + set +x
10708 19:58:39.204923 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 11899585_1.6.2.3.5>
10709 19:58:39.205751 Received signal: <STARTRUN> 1_kselftest-tpm2 11899585_1.6.2.3.5
10710 19:58:39.206194 Starting test lava.1_kselftest-tpm2 (11899585_1.6.2.3.5)
10711 19:58:39.206637 Skipping test definition patterns.
10712 19:58:39.208024 + cd ./automated/linux/kselftest/
10713 19:58:39.234239 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10714 19:58:39.274409 INFO: install_deps skipped
10715 19:58:39.396497 --2023-10-28 19:58:39-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10716 19:58:39.403026 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10717 19:58:39.536984 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10718 19:58:39.671330 HTTP request sent, awaiting response... 200 OK
10719 19:58:39.674155 Length: 2959220 (2.8M) [application/octet-stream]
10720 19:58:39.677183 Saving to: 'kselftest.tar.xz'
10721 19:58:39.677743
10722 19:58:39.678108
10723 19:58:39.937737 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10724 19:58:40.204620 kselftest.tar.xz 1%[ ] 46.39K 175KB/s
10725 19:58:40.653292 kselftest.tar.xz 7%[> ] 213.25K 401KB/s
10726 19:58:40.925749 kselftest.tar.xz 28%[====> ] 811.40K 827KB/s
10727 19:58:41.017584 kselftest.tar.xz 80%[===============> ] 2.28M 1.82MB/s
10728 19:58:41.024043 kselftest.tar.xz 100%[===================>] 2.82M 2.10MB/s in 1.3s
10729 19:58:41.024191
10730 19:58:41.281182 2023-10-28 19:58:41 (2.10 MB/s) - 'kselftest.tar.xz' saved [2959220/2959220]
10731 19:58:41.281358
10732 19:58:46.672405 skiplist:
10733 19:58:46.675734 ========================================
10734 19:58:46.678860 ========================================
10735 19:58:46.718954 tpm2:test_smoke.sh
10736 19:58:46.722081 tpm2:test_space.sh
10737 19:58:46.736972 ============== Tests to run ===============
10738 19:58:46.737390 tpm2:test_smoke.sh
10739 19:58:46.740354 tpm2:test_space.sh
10740 19:58:46.743690 ===========End Tests to run ===============
10741 19:58:46.744149 shardfile-tpm2 pass
10742 19:58:46.859405 <12>[ 35.552708] kselftest: Running tests in tpm2
10743 19:58:46.862767 TAP version 13
10744 19:58:46.876646 1..2
10745 19:58:46.911493 # selftests: tpm2: test_smoke.sh
10746 19:58:48.421035 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
10747 19:58:48.424534 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
10748 19:58:48.431136 # Exception ignored in: <function Client.__del__ at 0xffffbbc79d30>
10749 19:58:48.434356 # Traceback (most recent call last):
10750 19:58:48.444439 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10751 19:58:48.448457 # if self.tpm:
10752 19:58:48.450896 # AttributeError: 'Client' object has no attribute 'tpm'
10753 19:58:48.457556 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
10754 19:58:48.460877 # Exception ignored in: <function Client.__del__ at 0xffffbbc79d30>
10755 19:58:48.463940 # Traceback (most recent call last):
10756 19:58:48.474277 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10757 19:58:48.477308 # if self.tpm:
10758 19:58:48.480886 # AttributeError: 'Client' object has no attribute 'tpm'
10759 19:58:48.487758 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
10760 19:58:48.494263 # Exception ignored in: <function Client.__del__ at 0xffffbbc79d30>
10761 19:58:48.497380 # Traceback (most recent call last):
10762 19:58:48.507666 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10763 19:58:48.508274 # if self.tpm:
10764 19:58:48.513780 # AttributeError: 'Client' object has no attribute 'tpm'
10765 19:58:48.517109 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
10766 19:58:48.523714 # Exception ignored in: <function Client.__del__ at 0xffffbbc79d30>
10767 19:58:48.527153 # Traceback (most recent call last):
10768 19:58:48.536823 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10769 19:58:48.540211 # if self.tpm:
10770 19:58:48.543913 # AttributeError: 'Client' object has no attribute 'tpm'
10771 19:58:48.550434 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
10772 19:58:48.553746 # Exception ignored in: <function Client.__del__ at 0xffffbbc79d30>
10773 19:58:48.557323 # Traceback (most recent call last):
10774 19:58:48.566830 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10775 19:58:48.570469 # if self.tpm:
10776 19:58:48.573589 # AttributeError: 'Client' object has no attribute 'tpm'
10777 19:58:48.580307 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
10778 19:58:48.586720 # Exception ignored in: <function Client.__del__ at 0xffffbbc79d30>
10779 19:58:48.590828 # Traceback (most recent call last):
10780 19:58:48.599991 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10781 19:58:48.600622 # if self.tpm:
10782 19:58:48.607209 # AttributeError: 'Client' object has no attribute 'tpm'
10783 19:58:48.610281 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
10784 19:58:48.616714 # Exception ignored in: <function Client.__del__ at 0xffffbbc79d30>
10785 19:58:48.620101 # Traceback (most recent call last):
10786 19:58:48.630225 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10787 19:58:48.633065 # if self.tpm:
10788 19:58:48.636386 # AttributeError: 'Client' object has no attribute 'tpm'
10789 19:58:48.643088 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
10790 19:58:48.649877 # Exception ignored in: <function Client.__del__ at 0xffffbbc79d30>
10791 19:58:48.653187 # Traceback (most recent call last):
10792 19:58:48.663007 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10793 19:58:48.663617 # if self.tpm:
10794 19:58:48.669490 # AttributeError: 'Client' object has no attribute 'tpm'
10795 19:58:48.669964 #
10796 19:58:48.676199 # ======================================================================
10797 19:58:48.679450 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
10798 19:58:48.686449 # ----------------------------------------------------------------------
10799 19:58:48.689478 # Traceback (most recent call last):
10800 19:58:48.699181 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
10801 19:58:48.705909 # self.root_key = self.client.create_root_key()
10802 19:58:48.715707 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10803 19:58:48.722528 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10804 19:58:48.732614 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10805 19:58:48.735719 # raise ProtocolError(cc, rc)
10806 19:58:48.739238 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10807 19:58:48.739799 #
10808 19:58:48.745782 # ======================================================================
10809 19:58:48.752170 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
10810 19:58:48.759596 # ----------------------------------------------------------------------
10811 19:58:48.762182 # Traceback (most recent call last):
10812 19:58:48.772299 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10813 19:58:48.775504 # self.client = tpm2.Client()
10814 19:58:48.785692 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10815 19:58:48.788756 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10816 19:58:48.795398 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10817 19:58:48.795855 #
10818 19:58:48.801922 # ======================================================================
10819 19:58:48.805234 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
10820 19:58:48.812009 # ----------------------------------------------------------------------
10821 19:58:48.815220 # Traceback (most recent call last):
10822 19:58:48.825122 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10823 19:58:48.828504 # self.client = tpm2.Client()
10824 19:58:48.838456 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10825 19:58:48.845236 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10826 19:58:48.848566 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10827 19:58:48.849024 #
10828 19:58:48.855187 # ======================================================================
10829 19:58:48.862136 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
10830 19:58:48.865446 # ----------------------------------------------------------------------
10831 19:58:48.868728 # Traceback (most recent call last):
10832 19:58:48.878290 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10833 19:58:48.881701 # self.client = tpm2.Client()
10834 19:58:48.891739 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10835 19:58:48.898432 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10836 19:58:48.901780 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10837 19:58:48.905079 #
10838 19:58:48.908475 # ======================================================================
10839 19:58:48.914857 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
10840 19:58:48.921679 # ----------------------------------------------------------------------
10841 19:58:48.925321 # Traceback (most recent call last):
10842 19:58:48.935141 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10843 19:58:48.938596 # self.client = tpm2.Client()
10844 19:58:48.948313 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10845 19:58:48.951477 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10846 19:58:48.958076 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10847 19:58:48.958635 #
10848 19:58:48.964772 # ======================================================================
10849 19:58:48.967811 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
10850 19:58:48.975142 # ----------------------------------------------------------------------
10851 19:58:48.978251 # Traceback (most recent call last):
10852 19:58:48.987929 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10853 19:58:48.991254 # self.client = tpm2.Client()
10854 19:58:49.001335 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10855 19:58:49.007874 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10856 19:58:49.011156 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10857 19:58:49.011615 #
10858 19:58:49.018174 # ======================================================================
10859 19:58:49.024696 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
10860 19:58:49.031151 # ----------------------------------------------------------------------
10861 19:58:49.034505 # Traceback (most recent call last):
10862 19:58:49.044254 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10863 19:58:49.047741 # self.client = tpm2.Client()
10864 19:58:49.054734 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10865 19:58:49.062584 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10866 19:58:49.065768 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10867 19:58:49.066241 #
10868 19:58:49.073519 # ======================================================================
10869 19:58:49.080900 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
10870 19:58:49.083904 # ----------------------------------------------------------------------
10871 19:58:49.087629 # Traceback (most recent call last):
10872 19:58:49.100623 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10873 19:58:49.101110 # self.client = tpm2.Client()
10874 19:58:49.111370 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10875 19:58:49.115227 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10876 19:58:49.124592 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10877 19:58:49.125156 #
10878 19:58:49.127683 # ======================================================================
10879 19:58:49.134460 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
10880 19:58:49.141024 # ----------------------------------------------------------------------
10881 19:58:49.144639 # Traceback (most recent call last):
10882 19:58:49.154363 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10883 19:58:49.157629 # self.client = tpm2.Client()
10884 19:58:49.167749 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10885 19:58:49.170917 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10886 19:58:49.177801 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10887 19:58:49.178365 #
10888 19:58:49.184418 # ----------------------------------------------------------------------
10889 19:58:49.184992 # Ran 9 tests in 0.051s
10890 19:58:49.185365 #
10891 19:58:49.187868 # FAILED (errors=9)
10892 19:58:49.191021 # test_async (tpm2_tests.AsyncTest) ... ok
10893 19:58:49.197490 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
10894 19:58:49.198052 #
10895 19:58:49.204085 # ----------------------------------------------------------------------
10896 19:58:49.204679 # Ran 2 tests in 0.030s
10897 19:58:49.205050 #
10898 19:58:49.207181 # OK
10899 19:58:49.210707 ok 1 selftests: tpm2: test_smoke.sh
10900 19:58:49.211170 # selftests: tpm2: test_space.sh
10901 19:58:49.217377 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
10902 19:58:49.220461 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
10903 19:58:49.227279 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
10904 19:58:49.230496 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
10905 19:58:49.230915 #
10906 19:58:49.237727 # ======================================================================
10907 19:58:49.243961 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
10908 19:58:49.247030 # ----------------------------------------------------------------------
10909 19:58:49.250530 # Traceback (most recent call last):
10910 19:58:49.263504 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
10911 19:58:49.266911 # root1 = space1.create_root_key()
10912 19:58:49.276992 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10913 19:58:49.283666 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10914 19:58:49.293491 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10915 19:58:49.296842 # raise ProtocolError(cc, rc)
10916 19:58:49.303258 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10917 19:58:49.303721 #
10918 19:58:49.309852 # ======================================================================
10919 19:58:49.313043 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
10920 19:58:49.319685 # ----------------------------------------------------------------------
10921 19:58:49.323200 # Traceback (most recent call last):
10922 19:58:49.333431 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
10923 19:58:49.336425 # space1.create_root_key()
10924 19:58:49.346365 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10925 19:58:49.352953 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10926 19:58:49.362682 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10927 19:58:49.365963 # raise ProtocolError(cc, rc)
10928 19:58:49.372676 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10929 19:58:49.373171 #
10930 19:58:49.379234 # ======================================================================
10931 19:58:49.382776 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
10932 19:58:49.389257 # ----------------------------------------------------------------------
10933 19:58:49.392615 # Traceback (most recent call last):
10934 19:58:49.402866 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
10935 19:58:49.406557 # root1 = space1.create_root_key()
10936 19:58:49.415902 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10937 19:58:49.422638 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10938 19:58:49.432394 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10939 19:58:49.435684 # raise ProtocolError(cc, rc)
10940 19:58:49.442283 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10941 19:58:49.442739 #
10942 19:58:49.448892 # ======================================================================
10943 19:58:49.452232 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
10944 19:58:49.458897 # ----------------------------------------------------------------------
10945 19:58:49.462337 # Traceback (most recent call last):
10946 19:58:49.475702 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
10947 19:58:49.478747 # root1 = space1.create_root_key()
10948 19:58:49.488743 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10949 19:58:49.492324 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10950 19:58:49.502137 # File "/lava-11899585/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10951 19:58:49.505334 # raise ProtocolError(cc, rc)
10952 19:58:49.511972 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10953 19:58:49.512463 #
10954 19:58:49.518680 # ----------------------------------------------------------------------
10955 19:58:49.521914 # Ran 4 tests in 0.094s
10956 19:58:49.522368 #
10957 19:58:49.525595 # FAILED (errors=4)
10958 19:58:49.528762 not ok 2 selftests: tpm2: test_space.sh # exit=1
10959 19:58:49.532719 tpm2_test_smoke_sh pass
10960 19:58:49.533277 tpm2_test_space_sh fail
10961 19:58:49.535524 + ../../utils/send-to-lava.sh ./output/result.txt
10962 19:58:49.542124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
10963 19:58:49.543119 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
10965 19:58:49.548776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
10966 19:58:49.549613 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
10968 19:58:49.555518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
10969 19:58:49.556114 + set +x
10970 19:58:49.556822 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
10972 19:58:49.558544 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 11899585_1.6.2.3.5>
10973 19:58:49.559268 Received signal: <ENDRUN> 1_kselftest-tpm2 11899585_1.6.2.3.5
10974 19:58:49.559669 Ending use of test pattern.
10975 19:58:49.560013 Ending test lava.1_kselftest-tpm2 (11899585_1.6.2.3.5), duration 10.35
10977 19:58:49.561938 <LAVA_TEST_RUNNER EXIT>
10978 19:58:49.562660 ok: lava_test_shell seems to have completed
10979 19:58:49.563265 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
10980 19:58:49.563717 end: 3.1 lava-test-shell (duration 00:00:11) [common]
10981 19:58:49.564168 end: 3 lava-test-retry (duration 00:00:11) [common]
10982 19:58:49.564688 start: 4 finalize (timeout 00:07:46) [common]
10983 19:58:49.565180 start: 4.1 power-off (timeout 00:00:30) [common]
10984 19:58:49.565981 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10985 19:58:49.687991 >> Command sent successfully.
10986 19:58:49.692262 Returned 0 in 0 seconds
10987 19:58:49.793257 end: 4.1 power-off (duration 00:00:00) [common]
10989 19:58:49.794921 start: 4.2 read-feedback (timeout 00:07:45) [common]
10990 19:58:49.796346 Listened to connection for namespace 'common' for up to 1s
10991 19:58:50.796473 Finalising connection for namespace 'common'
10992 19:58:50.797169 Disconnecting from shell: Finalise
10993 19:58:50.797607 / #
10994 19:58:50.898666 end: 4.2 read-feedback (duration 00:00:01) [common]
10995 19:58:50.899367 end: 4 finalize (duration 00:00:01) [common]
10996 19:58:50.899978 Cleaning after the job
10997 19:58:50.900576 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/ramdisk
10998 19:58:50.914774 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/kernel
10999 19:58:50.948924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/dtb
11000 19:58:50.949217 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/nfsrootfs
11001 19:58:51.043241 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899585/tftp-deploy-6kfofeti/modules
11002 19:58:51.050508 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11899585
11003 19:58:51.676945 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11899585
11004 19:58:51.677127 Job finished correctly