Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 18
- Kernel Errors: 131
- Errors: 5
- Boot result: PASS
1 19:51:33.404531 lava-dispatcher, installed at version: 2023.08
2 19:51:33.404753 start: 0 validate
3 19:51:33.404887 Start time: 2023-10-28 19:51:33.404878+00:00 (UTC)
4 19:51:33.405010 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:51:33.405145 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 19:51:33.675860 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:51:33.676542 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:51:33.946984 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:51:33.947784 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:52:03.435590 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:52:03.436407 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:52:03.973401 validate duration: 30.57
14 19:52:03.974769 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:52:03.975303 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:52:03.975794 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:52:03.976461 Not decompressing ramdisk as can be used compressed.
18 19:52:03.976948 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 19:52:03.977310 saving as /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/ramdisk/rootfs.cpio.gz
20 19:52:03.977665 total size: 84918747 (80 MB)
21 19:52:07.606015 progress 0 % (0 MB)
22 19:52:07.631073 progress 5 % (4 MB)
23 19:52:07.652444 progress 10 % (8 MB)
24 19:52:07.673679 progress 15 % (12 MB)
25 19:52:07.695229 progress 20 % (16 MB)
26 19:52:07.716625 progress 25 % (20 MB)
27 19:52:07.738716 progress 30 % (24 MB)
28 19:52:07.760394 progress 35 % (28 MB)
29 19:52:07.781854 progress 40 % (32 MB)
30 19:52:07.803846 progress 45 % (36 MB)
31 19:52:07.825525 progress 50 % (40 MB)
32 19:52:07.847336 progress 55 % (44 MB)
33 19:52:07.868940 progress 60 % (48 MB)
34 19:52:07.890695 progress 65 % (52 MB)
35 19:52:07.912605 progress 70 % (56 MB)
36 19:52:07.934564 progress 75 % (60 MB)
37 19:52:07.956337 progress 80 % (64 MB)
38 19:52:07.977993 progress 85 % (68 MB)
39 19:52:07.999589 progress 90 % (72 MB)
40 19:52:08.021377 progress 95 % (76 MB)
41 19:52:08.043004 progress 100 % (80 MB)
42 19:52:08.043237 80 MB downloaded in 4.07 s (19.92 MB/s)
43 19:52:08.043403 end: 1.1.1 http-download (duration 00:00:04) [common]
45 19:52:08.043643 end: 1.1 download-retry (duration 00:00:04) [common]
46 19:52:08.043729 start: 1.2 download-retry (timeout 00:09:56) [common]
47 19:52:08.043811 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 19:52:08.043948 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:52:08.044020 saving as /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/kernel/Image
50 19:52:08.044080 total size: 49304064 (47 MB)
51 19:52:08.044140 No compression specified
52 19:52:08.045285 progress 0 % (0 MB)
53 19:52:08.058078 progress 5 % (2 MB)
54 19:52:08.070724 progress 10 % (4 MB)
55 19:52:08.083464 progress 15 % (7 MB)
56 19:52:08.096007 progress 20 % (9 MB)
57 19:52:08.108691 progress 25 % (11 MB)
58 19:52:08.121717 progress 30 % (14 MB)
59 19:52:08.134423 progress 35 % (16 MB)
60 19:52:08.147105 progress 40 % (18 MB)
61 19:52:08.159902 progress 45 % (21 MB)
62 19:52:08.172633 progress 50 % (23 MB)
63 19:52:08.185253 progress 55 % (25 MB)
64 19:52:08.197969 progress 60 % (28 MB)
65 19:52:08.210714 progress 65 % (30 MB)
66 19:52:08.223498 progress 70 % (32 MB)
67 19:52:08.236186 progress 75 % (35 MB)
68 19:52:08.248870 progress 80 % (37 MB)
69 19:52:08.261376 progress 85 % (39 MB)
70 19:52:08.274180 progress 90 % (42 MB)
71 19:52:08.286653 progress 95 % (44 MB)
72 19:52:08.299087 progress 100 % (47 MB)
73 19:52:08.299301 47 MB downloaded in 0.26 s (184.24 MB/s)
74 19:52:08.299449 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:52:08.299723 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:52:08.299819 start: 1.3 download-retry (timeout 00:09:56) [common]
78 19:52:08.299905 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 19:52:08.300049 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:52:08.300117 saving as /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/dtb/mt8192-asurada-spherion-r0.dtb
81 19:52:08.300186 total size: 47278 (0 MB)
82 19:52:08.300284 No compression specified
83 19:52:08.301421 progress 69 % (0 MB)
84 19:52:08.301694 progress 100 % (0 MB)
85 19:52:08.301849 0 MB downloaded in 0.00 s (27.16 MB/s)
86 19:52:08.301969 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:52:08.302188 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:52:08.302272 start: 1.4 download-retry (timeout 00:09:56) [common]
90 19:52:08.302352 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 19:52:08.302464 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:52:08.302530 saving as /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/modules/modules.tar
93 19:52:08.302589 total size: 8635496 (8 MB)
94 19:52:08.302650 Using unxz to decompress xz
95 19:52:08.306767 progress 0 % (0 MB)
96 19:52:08.328345 progress 5 % (0 MB)
97 19:52:08.350356 progress 10 % (0 MB)
98 19:52:08.376077 progress 15 % (1 MB)
99 19:52:08.401216 progress 20 % (1 MB)
100 19:52:08.426723 progress 25 % (2 MB)
101 19:52:08.454465 progress 30 % (2 MB)
102 19:52:08.479158 progress 35 % (2 MB)
103 19:52:08.503587 progress 40 % (3 MB)
104 19:52:08.528141 progress 45 % (3 MB)
105 19:52:08.554181 progress 50 % (4 MB)
106 19:52:08.579168 progress 55 % (4 MB)
107 19:52:08.605114 progress 60 % (4 MB)
108 19:52:08.628064 progress 65 % (5 MB)
109 19:52:08.652763 progress 70 % (5 MB)
110 19:52:08.676405 progress 75 % (6 MB)
111 19:52:08.702513 progress 80 % (6 MB)
112 19:52:08.734842 progress 85 % (7 MB)
113 19:52:08.760532 progress 90 % (7 MB)
114 19:52:08.784382 progress 95 % (7 MB)
115 19:52:08.807385 progress 100 % (8 MB)
116 19:52:08.812969 8 MB downloaded in 0.51 s (16.14 MB/s)
117 19:52:08.813234 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:52:08.813497 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:52:08.813592 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 19:52:08.813686 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 19:52:08.813769 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:52:08.813857 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 19:52:08.814087 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab
125 19:52:08.814269 makedir: /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin
126 19:52:08.814389 makedir: /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/tests
127 19:52:08.814491 makedir: /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/results
128 19:52:08.814612 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-add-keys
129 19:52:08.814761 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-add-sources
130 19:52:08.814893 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-background-process-start
131 19:52:08.815022 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-background-process-stop
132 19:52:08.815149 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-common-functions
133 19:52:08.815287 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-echo-ipv4
134 19:52:08.815417 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-install-packages
135 19:52:08.815543 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-installed-packages
136 19:52:08.815668 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-os-build
137 19:52:08.815794 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-probe-channel
138 19:52:08.815919 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-probe-ip
139 19:52:08.816044 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-target-ip
140 19:52:08.816171 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-target-mac
141 19:52:08.816409 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-target-storage
142 19:52:08.816600 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-test-case
143 19:52:08.816823 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-test-event
144 19:52:08.816970 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-test-feedback
145 19:52:08.817099 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-test-raise
146 19:52:08.817229 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-test-reference
147 19:52:08.817354 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-test-runner
148 19:52:08.817481 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-test-set
149 19:52:08.817611 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-test-shell
150 19:52:08.817741 Updating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-install-packages (oe)
151 19:52:08.817895 Updating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/bin/lava-installed-packages (oe)
152 19:52:08.818017 Creating /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/environment
153 19:52:08.818119 LAVA metadata
154 19:52:08.818218 - LAVA_JOB_ID=11899575
155 19:52:08.818306 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:52:08.818411 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 19:52:08.818477 skipped lava-vland-overlay
158 19:52:08.818551 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:52:08.818636 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 19:52:08.818699 skipped lava-multinode-overlay
161 19:52:08.818782 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:52:08.818866 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 19:52:08.818940 Loading test definitions
164 19:52:08.819032 start: 1.5.2.3.1 git-repo-action (timeout 00:09:55) [common]
165 19:52:08.819107 Using /lava-11899575 at stage 0
166 19:52:08.819203 Fetching tests from https://github.com/kernelci/kernelci-core
167 19:52:08.819287 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/0/tests/0_sleep'
168 19:52:09.477919 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/0/tests/0_sleep
169 19:52:09.479272 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 19:52:09.479679 uuid=11899575_1.5.2.3.1 testdef=None
171 19:52:09.479821 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 19:52:09.480077 start: 1.5.2.3.2 test-overlay (timeout 00:09:54) [common]
174 19:52:09.480686 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 19:52:09.480921 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:54) [common]
177 19:52:09.481633 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 19:52:09.481867 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
180 19:52:09.482515 runner path: /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/0/tests/0_sleep test_uuid 11899575_1.5.2.3.1
181 19:52:09.482599 sleep_params='mem freeze'
182 19:52:09.482740 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 19:52:09.482952 Creating lava-test-runner.conf files
185 19:52:09.483015 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899575/lava-overlay-ilitmeab/lava-11899575/0 for stage 0
186 19:52:09.483108 - 0_sleep
187 19:52:09.483211 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 19:52:09.483299 start: 1.5.2.4 compress-overlay (timeout 00:09:54) [common]
189 19:52:09.611074 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 19:52:09.611234 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
191 19:52:09.611326 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 19:52:09.611424 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 19:52:09.611512 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
194 19:52:12.092316 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 19:52:12.092700 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
196 19:52:12.092820 extracting modules file /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899575/extract-overlay-ramdisk-a3812fg1/ramdisk
197 19:52:12.319474 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 19:52:12.319660 start: 1.5.5 apply-overlay-tftp (timeout 00:09:52) [common]
199 19:52:12.319786 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899575/compress-overlay-hesjqmya/overlay-1.5.2.4.tar.gz to ramdisk
200 19:52:12.319869 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899575/compress-overlay-hesjqmya/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11899575/extract-overlay-ramdisk-a3812fg1/ramdisk
201 19:52:12.415271 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 19:52:12.415453 start: 1.5.6 configure-preseed-file (timeout 00:09:52) [common]
203 19:52:12.415569 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 19:52:12.415683 start: 1.5.7 compress-ramdisk (timeout 00:09:52) [common]
205 19:52:12.415780 Building ramdisk /var/lib/lava/dispatcher/tmp/11899575/extract-overlay-ramdisk-a3812fg1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11899575/extract-overlay-ramdisk-a3812fg1/ramdisk
206 19:52:13.993366 >> 563490 blocks
207 19:52:23.827485 rename /var/lib/lava/dispatcher/tmp/11899575/extract-overlay-ramdisk-a3812fg1/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/ramdisk/ramdisk.cpio.gz
208 19:52:23.827946 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 19:52:23.828074 start: 1.5.8 prepare-kernel (timeout 00:09:40) [common]
210 19:52:23.828181 start: 1.5.8.1 prepare-fit (timeout 00:09:40) [common]
211 19:52:23.828334 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/kernel/Image'
212 19:52:35.999474 Returned 0 in 12 seconds
213 19:52:36.100142 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/kernel/image.itb
214 19:52:37.464627 output: FIT description: Kernel Image image with one or more FDT blobs
215 19:52:37.465017 output: Created: Sat Oct 28 20:52:37 2023
216 19:52:37.465095 output: Image 0 (kernel-1)
217 19:52:37.465162 output: Description:
218 19:52:37.465227 output: Created: Sat Oct 28 20:52:37 2023
219 19:52:37.465289 output: Type: Kernel Image
220 19:52:37.465352 output: Compression: lzma compressed
221 19:52:37.465412 output: Data Size: 11047522 Bytes = 10788.60 KiB = 10.54 MiB
222 19:52:37.465469 output: Architecture: AArch64
223 19:52:37.465525 output: OS: Linux
224 19:52:37.465579 output: Load Address: 0x00000000
225 19:52:37.465635 output: Entry Point: 0x00000000
226 19:52:37.465692 output: Hash algo: crc32
227 19:52:37.465750 output: Hash value: da40eda2
228 19:52:37.465806 output: Image 1 (fdt-1)
229 19:52:37.465863 output: Description: mt8192-asurada-spherion-r0
230 19:52:37.465916 output: Created: Sat Oct 28 20:52:37 2023
231 19:52:37.465970 output: Type: Flat Device Tree
232 19:52:37.466022 output: Compression: uncompressed
233 19:52:37.466075 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 19:52:37.466128 output: Architecture: AArch64
235 19:52:37.466180 output: Hash algo: crc32
236 19:52:37.466233 output: Hash value: cc4352de
237 19:52:37.466285 output: Image 2 (ramdisk-1)
238 19:52:37.466338 output: Description: unavailable
239 19:52:37.466389 output: Created: Sat Oct 28 20:52:37 2023
240 19:52:37.466442 output: Type: RAMDisk Image
241 19:52:37.466494 output: Compression: Unknown Compression
242 19:52:37.466546 output: Data Size: 98318988 Bytes = 96014.64 KiB = 93.76 MiB
243 19:52:37.466599 output: Architecture: AArch64
244 19:52:37.466651 output: OS: Linux
245 19:52:37.466703 output: Load Address: unavailable
246 19:52:37.466754 output: Entry Point: unavailable
247 19:52:37.466806 output: Hash algo: crc32
248 19:52:37.466858 output: Hash value: 00383872
249 19:52:37.466910 output: Default Configuration: 'conf-1'
250 19:52:37.466962 output: Configuration 0 (conf-1)
251 19:52:37.467014 output: Description: mt8192-asurada-spherion-r0
252 19:52:37.467067 output: Kernel: kernel-1
253 19:52:37.467119 output: Init Ramdisk: ramdisk-1
254 19:52:37.467170 output: FDT: fdt-1
255 19:52:37.467222 output: Loadables: kernel-1
256 19:52:37.467275 output:
257 19:52:37.467478 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 19:52:37.467578 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 19:52:37.467688 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
260 19:52:37.467786 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:27) [common]
261 19:52:37.467861 No LXC device requested
262 19:52:37.467938 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 19:52:37.468027 start: 1.7 deploy-device-env (timeout 00:09:27) [common]
264 19:52:37.468105 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 19:52:37.468172 Checking files for TFTP limit of 4294967296 bytes.
266 19:52:37.468692 end: 1 tftp-deploy (duration 00:00:33) [common]
267 19:52:37.468803 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 19:52:37.468897 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 19:52:37.469018 substitutions:
270 19:52:37.469085 - {DTB}: 11899575/tftp-deploy-vq85ut5t/dtb/mt8192-asurada-spherion-r0.dtb
271 19:52:37.469150 - {INITRD}: 11899575/tftp-deploy-vq85ut5t/ramdisk/ramdisk.cpio.gz
272 19:52:37.469209 - {KERNEL}: 11899575/tftp-deploy-vq85ut5t/kernel/Image
273 19:52:37.469266 - {LAVA_MAC}: None
274 19:52:37.469322 - {PRESEED_CONFIG}: None
275 19:52:37.469377 - {PRESEED_LOCAL}: None
276 19:52:37.469431 - {RAMDISK}: 11899575/tftp-deploy-vq85ut5t/ramdisk/ramdisk.cpio.gz
277 19:52:37.469486 - {ROOT_PART}: None
278 19:52:37.469539 - {ROOT}: None
279 19:52:37.469592 - {SERVER_IP}: 192.168.201.1
280 19:52:37.469645 - {TEE}: None
281 19:52:37.469698 Parsed boot commands:
282 19:52:37.469750 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 19:52:37.469994 Parsed boot commands: tftpboot 192.168.201.1 11899575/tftp-deploy-vq85ut5t/kernel/image.itb 11899575/tftp-deploy-vq85ut5t/kernel/cmdline
284 19:52:37.470086 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 19:52:37.470173 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 19:52:37.470266 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 19:52:37.470353 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 19:52:37.470423 Not connected, no need to disconnect.
289 19:52:37.470497 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 19:52:37.470579 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 19:52:37.470645 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
292 19:52:37.474801 Setting prompt string to ['lava-test: # ']
293 19:52:37.475197 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 19:52:37.475307 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 19:52:37.475411 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 19:52:37.475504 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 19:52:37.475746 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
298 19:52:42.610696 >> Command sent successfully.
299 19:52:42.613165 Returned 0 in 5 seconds
300 19:52:42.713570 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 19:52:42.713898 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 19:52:42.713995 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 19:52:42.714081 Setting prompt string to 'Starting depthcharge on Spherion...'
305 19:52:42.714149 Changing prompt to 'Starting depthcharge on Spherion...'
306 19:52:42.714217 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 19:52:42.714446 [Enter `^Ec?' for help]
308 19:52:42.893879
309 19:52:42.894041
310 19:52:42.894112 F0: 102B 0000
311 19:52:42.894177
312 19:52:42.894239 F3: 1001 0000 [0200]
313 19:52:42.894297
314 19:52:42.897591 F3: 1001 0000
315 19:52:42.897675
316 19:52:42.897740 F7: 102D 0000
317 19:52:42.897800
318 19:52:42.897859 F1: 0000 0000
319 19:52:42.897917
320 19:52:42.900838 V0: 0000 0000 [0001]
321 19:52:42.900921
322 19:52:42.900986 00: 0007 8000
323 19:52:42.901048
324 19:52:42.904729 01: 0000 0000
325 19:52:42.904813
326 19:52:42.904877 BP: 0C00 0209 [0000]
327 19:52:42.904937
328 19:52:42.908109 G0: 1182 0000
329 19:52:42.908202
330 19:52:42.908268 EC: 0000 0021 [4000]
331 19:52:42.908329
332 19:52:42.911413 S7: 0000 0000 [0000]
333 19:52:42.911494
334 19:52:42.911560 CC: 0000 0000 [0001]
335 19:52:42.911620
336 19:52:42.914576 T0: 0000 0040 [010F]
337 19:52:42.914660
338 19:52:42.914725 Jump to BL
339 19:52:42.914785
340 19:52:42.940903
341 19:52:42.941052
342 19:52:42.941118
343 19:52:42.948257 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 19:52:42.951757 ARM64: Exception handlers installed.
345 19:52:42.955182 ARM64: Testing exception
346 19:52:42.958804 ARM64: Done test exception
347 19:52:42.966275 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 19:52:42.973300 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 19:52:42.980357 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 19:52:42.990978 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 19:52:42.997853 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 19:52:43.008186 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 19:52:43.018859 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 19:52:43.025221 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 19:52:43.043249 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 19:52:43.046587 WDT: Last reset was cold boot
357 19:52:43.050074 SPI1(PAD0) initialized at 2873684 Hz
358 19:52:43.053321 SPI5(PAD0) initialized at 992727 Hz
359 19:52:43.056505 VBOOT: Loading verstage.
360 19:52:43.062976 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 19:52:43.066289 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 19:52:43.069541 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 19:52:43.073004 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 19:52:43.080693 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 19:52:43.087276 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 19:52:43.098210 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 19:52:43.098335
368 19:52:43.098403
369 19:52:43.108465 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 19:52:43.112638 ARM64: Exception handlers installed.
371 19:52:43.112732 ARM64: Testing exception
372 19:52:43.116026 ARM64: Done test exception
373 19:52:43.119347 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 19:52:43.125901 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 19:52:43.139303 Probing TPM: . done!
376 19:52:43.139431 TPM ready after 0 ms
377 19:52:43.147281 Connected to device vid:did:rid of 1ae0:0028:00
378 19:52:43.154125 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
379 19:52:43.203770 Initialized TPM device CR50 revision 0
380 19:52:43.207447 tlcl_send_startup: Startup return code is 0
381 19:52:43.216459 TPM: setup succeeded
382 19:52:43.227015 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 19:52:43.235917 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 19:52:43.245635 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 19:52:43.254706 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 19:52:43.257976 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 19:52:43.261793 in-header: 03 07 00 00 08 00 00 00
388 19:52:43.265267 in-data: aa e4 47 04 13 02 00 00
389 19:52:43.268578 Chrome EC: UHEPI supported
390 19:52:43.275146 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 19:52:43.288571 in-header: 03 95 00 00 08 00 00 00
392 19:52:43.291974 in-data: 18 20 20 08 00 00 00 00
393 19:52:43.292092 Phase 1
394 19:52:43.295436 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 19:52:43.303197 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 19:52:43.310774 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 19:52:43.310868 Recovery requested (1009000e)
398 19:52:43.320479 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 19:52:43.326055 tlcl_extend: response is 0
400 19:52:43.335224 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 19:52:43.340638 tlcl_extend: response is 0
402 19:52:43.347829 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 19:52:43.368246 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 19:52:43.375506 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 19:52:43.375615
406 19:52:43.375680
407 19:52:43.382872 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 19:52:43.386639 ARM64: Exception handlers installed.
409 19:52:43.389812 ARM64: Testing exception
410 19:52:43.393065 ARM64: Done test exception
411 19:52:43.413254 pmic_efuse_setting: Set efuses in 11 msecs
412 19:52:43.416590 pmwrap_interface_init: Select PMIF_VLD_RDY
413 19:52:43.423246 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 19:52:43.426704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 19:52:43.433595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 19:52:43.437049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 19:52:43.443436 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 19:52:43.446902 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 19:52:43.450036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 19:52:43.456895 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 19:52:43.460305 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 19:52:43.466931 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 19:52:43.470223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 19:52:43.473903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 19:52:43.480867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 19:52:43.484631 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 19:52:43.491962 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 19:52:43.495691 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 19:52:43.502973 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 19:52:43.510265 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 19:52:43.513912 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 19:52:43.521234 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 19:52:43.524930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 19:52:43.532196 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 19:52:43.535990 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 19:52:43.543126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 19:52:43.546786 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 19:52:43.554061 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 19:52:43.557909 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 19:52:43.561617 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 19:52:43.568812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 19:52:43.572715 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 19:52:43.576290 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 19:52:43.583819 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 19:52:43.587436 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 19:52:43.591172 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 19:52:43.598393 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 19:52:43.601998 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 19:52:43.605946 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 19:52:43.613192 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 19:52:43.616902 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 19:52:43.620137 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 19:52:43.623994 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 19:52:43.631388 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 19:52:43.635312 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 19:52:43.638622 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 19:52:43.642430 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 19:52:43.646284 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 19:52:43.653293 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 19:52:43.656985 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 19:52:43.660382 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 19:52:43.664220 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 19:52:43.667651 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 19:52:43.675336 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 19:52:43.686150 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 19:52:43.689663 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 19:52:43.697332 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 19:52:43.704291 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 19:52:43.711409 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 19:52:43.715151 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 19:52:43.718511 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 19:52:43.726918 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
473 19:52:43.733429 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 19:52:43.737338 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 19:52:43.740706 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 19:52:43.750951 [RTC]rtc_get_frequency_meter,154: input=15, output=765
477 19:52:43.760642 [RTC]rtc_get_frequency_meter,154: input=23, output=949
478 19:52:43.769994 [RTC]rtc_get_frequency_meter,154: input=19, output=857
479 19:52:43.779160 [RTC]rtc_get_frequency_meter,154: input=17, output=810
480 19:52:43.788957 [RTC]rtc_get_frequency_meter,154: input=16, output=788
481 19:52:43.798638 [RTC]rtc_get_frequency_meter,154: input=16, output=788
482 19:52:43.807875 [RTC]rtc_get_frequency_meter,154: input=17, output=810
483 19:52:43.811365 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 19:52:43.818396 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 19:52:43.822237 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 19:52:43.826019 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 19:52:43.829530 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 19:52:43.833291 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 19:52:43.836972 ADC[4]: Raw value=671168 ID=5
490 19:52:43.840763 ADC[3]: Raw value=212549 ID=1
491 19:52:43.840845 RAM Code: 0x51
492 19:52:43.844720 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 19:52:43.851885 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 19:52:43.859561 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
495 19:52:43.862802 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
496 19:52:43.866101 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 19:52:43.870572 in-header: 03 07 00 00 08 00 00 00
498 19:52:43.874021 in-data: aa e4 47 04 13 02 00 00
499 19:52:43.877882 Chrome EC: UHEPI supported
500 19:52:43.885115 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 19:52:43.888935 in-header: 03 95 00 00 08 00 00 00
502 19:52:43.892155 in-data: 18 20 20 08 00 00 00 00
503 19:52:43.896330 MRC: failed to locate region type 0.
504 19:52:43.899775 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 19:52:43.903859 DRAM-K: Running full calibration
506 19:52:43.910818 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
507 19:52:43.910905 header.status = 0x0
508 19:52:43.914373 header.version = 0x6 (expected: 0x6)
509 19:52:43.917887 header.size = 0xd00 (expected: 0xd00)
510 19:52:43.921803 header.flags = 0x0
511 19:52:43.925378 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 19:52:43.944710 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
513 19:52:43.951962 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 19:52:43.955575 dram_init: ddr_geometry: 0
515 19:52:43.955660 [EMI] MDL number = 0
516 19:52:43.959721 [EMI] Get MDL freq = 0
517 19:52:43.959805 dram_init: ddr_type: 0
518 19:52:43.963438 is_discrete_lpddr4: 1
519 19:52:43.966919 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 19:52:43.967002
521 19:52:43.967066
522 19:52:43.967126 [Bian_co] ETT version 0.0.0.1
523 19:52:43.974208 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
524 19:52:43.974293
525 19:52:43.977688 dramc_set_vcore_voltage set vcore to 650000
526 19:52:43.977770 Read voltage for 800, 4
527 19:52:43.981423 Vio18 = 0
528 19:52:43.981504 Vcore = 650000
529 19:52:43.981569 Vdram = 0
530 19:52:43.985054 Vddq = 0
531 19:52:43.985135 Vmddr = 0
532 19:52:43.985200 dram_init: config_dvfs: 1
533 19:52:43.992817 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 19:52:43.996031 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 19:52:43.999892 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
536 19:52:44.003531 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
537 19:52:44.007122 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
538 19:52:44.010678 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
539 19:52:44.014278 MEM_TYPE=3, freq_sel=18
540 19:52:44.018211 sv_algorithm_assistance_LP4_1600
541 19:52:44.021880 ============ PULL DRAM RESETB DOWN ============
542 19:52:44.025381 ========== PULL DRAM RESETB DOWN end =========
543 19:52:44.029281 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 19:52:44.033043 ===================================
545 19:52:44.037134 LPDDR4 DRAM CONFIGURATION
546 19:52:44.040374 ===================================
547 19:52:44.040457 EX_ROW_EN[0] = 0x0
548 19:52:44.043975 EX_ROW_EN[1] = 0x0
549 19:52:44.044057 LP4Y_EN = 0x0
550 19:52:44.047670 WORK_FSP = 0x0
551 19:52:44.047751 WL = 0x2
552 19:52:44.051188 RL = 0x2
553 19:52:44.051278 BL = 0x2
554 19:52:44.055361 RPST = 0x0
555 19:52:44.055446 RD_PRE = 0x0
556 19:52:44.058806 WR_PRE = 0x1
557 19:52:44.058890 WR_PST = 0x0
558 19:52:44.062348 DBI_WR = 0x0
559 19:52:44.062433 DBI_RD = 0x0
560 19:52:44.062518 OTF = 0x1
561 19:52:44.066046 ===================================
562 19:52:44.069273 ===================================
563 19:52:44.072679 ANA top config
564 19:52:44.075828 ===================================
565 19:52:44.079115 DLL_ASYNC_EN = 0
566 19:52:44.079199 ALL_SLAVE_EN = 1
567 19:52:44.082580 NEW_RANK_MODE = 1
568 19:52:44.085894 DLL_IDLE_MODE = 1
569 19:52:44.089493 LP45_APHY_COMB_EN = 1
570 19:52:44.089577 TX_ODT_DIS = 1
571 19:52:44.092893 NEW_8X_MODE = 1
572 19:52:44.096535 ===================================
573 19:52:44.100042 ===================================
574 19:52:44.103343 data_rate = 1600
575 19:52:44.107112 CKR = 1
576 19:52:44.107197 DQ_P2S_RATIO = 8
577 19:52:44.110647 ===================================
578 19:52:44.114470 CA_P2S_RATIO = 8
579 19:52:44.117464 DQ_CA_OPEN = 0
580 19:52:44.120802 DQ_SEMI_OPEN = 0
581 19:52:44.124063 CA_SEMI_OPEN = 0
582 19:52:44.124148 CA_FULL_RATE = 0
583 19:52:44.127553 DQ_CKDIV4_EN = 1
584 19:52:44.131210 CA_CKDIV4_EN = 1
585 19:52:44.134436 CA_PREDIV_EN = 0
586 19:52:44.138268 PH8_DLY = 0
587 19:52:44.138350 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 19:52:44.141171 DQ_AAMCK_DIV = 4
589 19:52:44.144780 CA_AAMCK_DIV = 4
590 19:52:44.148365 CA_ADMCK_DIV = 4
591 19:52:44.151497 DQ_TRACK_CA_EN = 0
592 19:52:44.151579 CA_PICK = 800
593 19:52:44.154697 CA_MCKIO = 800
594 19:52:44.158012 MCKIO_SEMI = 0
595 19:52:44.161764 PLL_FREQ = 3068
596 19:52:44.165410 DQ_UI_PI_RATIO = 32
597 19:52:44.168992 CA_UI_PI_RATIO = 0
598 19:52:44.169074 ===================================
599 19:52:44.173060 ===================================
600 19:52:44.176565 memory_type:LPDDR4
601 19:52:44.180388 GP_NUM : 10
602 19:52:44.180470 SRAM_EN : 1
603 19:52:44.183752 MD32_EN : 0
604 19:52:44.187498 ===================================
605 19:52:44.187584 [ANA_INIT] >>>>>>>>>>>>>>
606 19:52:44.191226 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 19:52:44.195238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 19:52:44.198731 ===================================
609 19:52:44.198821 data_rate = 1600,PCW = 0X7600
610 19:52:44.201939 ===================================
611 19:52:44.208704 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 19:52:44.212006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 19:52:44.218851 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 19:52:44.222071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 19:52:44.225437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 19:52:44.228961 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 19:52:44.232043 [ANA_INIT] flow start
618 19:52:44.235681 [ANA_INIT] PLL >>>>>>>>
619 19:52:44.235763 [ANA_INIT] PLL <<<<<<<<
620 19:52:44.239262 [ANA_INIT] MIDPI >>>>>>>>
621 19:52:44.242171 [ANA_INIT] MIDPI <<<<<<<<
622 19:52:44.242252 [ANA_INIT] DLL >>>>>>>>
623 19:52:44.245716 [ANA_INIT] flow end
624 19:52:44.249133 ============ LP4 DIFF to SE enter ============
625 19:52:44.252445 ============ LP4 DIFF to SE exit ============
626 19:52:44.255633 [ANA_INIT] <<<<<<<<<<<<<
627 19:52:44.259078 [Flow] Enable top DCM control >>>>>
628 19:52:44.262316 [Flow] Enable top DCM control <<<<<
629 19:52:44.265719 Enable DLL master slave shuffle
630 19:52:44.272056 ==============================================================
631 19:52:44.272140 Gating Mode config
632 19:52:44.278741 ==============================================================
633 19:52:44.278822 Config description:
634 19:52:44.288702 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 19:52:44.295205 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 19:52:44.301756 SELPH_MODE 0: By rank 1: By Phase
637 19:52:44.305276 ==============================================================
638 19:52:44.308470 GAT_TRACK_EN = 1
639 19:52:44.311955 RX_GATING_MODE = 2
640 19:52:44.315337 RX_GATING_TRACK_MODE = 2
641 19:52:44.318459 SELPH_MODE = 1
642 19:52:44.321996 PICG_EARLY_EN = 1
643 19:52:44.325315 VALID_LAT_VALUE = 1
644 19:52:44.332071 ==============================================================
645 19:52:44.335059 Enter into Gating configuration >>>>
646 19:52:44.338401 Exit from Gating configuration <<<<
647 19:52:44.338485 Enter into DVFS_PRE_config >>>>>
648 19:52:44.351786 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 19:52:44.355264 Exit from DVFS_PRE_config <<<<<
650 19:52:44.358616 Enter into PICG configuration >>>>
651 19:52:44.361986 Exit from PICG configuration <<<<
652 19:52:44.362068 [RX_INPUT] configuration >>>>>
653 19:52:44.365365 [RX_INPUT] configuration <<<<<
654 19:52:44.371800 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 19:52:44.375090 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 19:52:44.381854 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 19:52:44.388455 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 19:52:44.395700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 19:52:44.401767 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 19:52:44.405155 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 19:52:44.408430 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 19:52:44.411836 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 19:52:44.418539 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 19:52:44.422021 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 19:52:44.425310 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 19:52:44.428939 ===================================
667 19:52:44.431833 LPDDR4 DRAM CONFIGURATION
668 19:52:44.435229 ===================================
669 19:52:44.438409 EX_ROW_EN[0] = 0x0
670 19:52:44.438494 EX_ROW_EN[1] = 0x0
671 19:52:44.441825 LP4Y_EN = 0x0
672 19:52:44.441909 WORK_FSP = 0x0
673 19:52:44.445216 WL = 0x2
674 19:52:44.445300 RL = 0x2
675 19:52:44.448463 BL = 0x2
676 19:52:44.448547 RPST = 0x0
677 19:52:44.451904 RD_PRE = 0x0
678 19:52:44.451988 WR_PRE = 0x1
679 19:52:44.455317 WR_PST = 0x0
680 19:52:44.455401 DBI_WR = 0x0
681 19:52:44.458425 DBI_RD = 0x0
682 19:52:44.458534 OTF = 0x1
683 19:52:44.462160 ===================================
684 19:52:44.465171 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 19:52:44.471866 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 19:52:44.475155 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 19:52:44.478555 ===================================
688 19:52:44.481875 LPDDR4 DRAM CONFIGURATION
689 19:52:44.485629 ===================================
690 19:52:44.485711 EX_ROW_EN[0] = 0x10
691 19:52:44.488812 EX_ROW_EN[1] = 0x0
692 19:52:44.488893 LP4Y_EN = 0x0
693 19:52:44.492145 WORK_FSP = 0x0
694 19:52:44.495456 WL = 0x2
695 19:52:44.495540 RL = 0x2
696 19:52:44.498813 BL = 0x2
697 19:52:44.498895 RPST = 0x0
698 19:52:44.502079 RD_PRE = 0x0
699 19:52:44.502161 WR_PRE = 0x1
700 19:52:44.505803 WR_PST = 0x0
701 19:52:44.505884 DBI_WR = 0x0
702 19:52:44.508551 DBI_RD = 0x0
703 19:52:44.508632 OTF = 0x1
704 19:52:44.512328 ===================================
705 19:52:44.518685 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 19:52:44.522555 nWR fixed to 40
707 19:52:44.526332 [ModeRegInit_LP4] CH0 RK0
708 19:52:44.526415 [ModeRegInit_LP4] CH0 RK1
709 19:52:44.529405 [ModeRegInit_LP4] CH1 RK0
710 19:52:44.532562 [ModeRegInit_LP4] CH1 RK1
711 19:52:44.532644 match AC timing 12
712 19:52:44.539200 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
713 19:52:44.542651 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 19:52:44.545688 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 19:52:44.552567 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 19:52:44.555790 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 19:52:44.555874 [EMI DOE] emi_dcm 0
718 19:52:44.562442 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 19:52:44.562528 ==
720 19:52:44.565689 Dram Type= 6, Freq= 0, CH_0, rank 0
721 19:52:44.569129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
722 19:52:44.569211 ==
723 19:52:44.575689 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 19:52:44.582434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 19:52:44.590081 [CA 0] Center 37 (7~68) winsize 62
726 19:52:44.593104 [CA 1] Center 37 (7~68) winsize 62
727 19:52:44.596328 [CA 2] Center 35 (5~66) winsize 62
728 19:52:44.599719 [CA 3] Center 35 (5~66) winsize 62
729 19:52:44.603241 [CA 4] Center 34 (4~65) winsize 62
730 19:52:44.606406 [CA 5] Center 33 (3~64) winsize 62
731 19:52:44.606490
732 19:52:44.610110 [CmdBusTrainingLP45] Vref(ca) range 1: 32
733 19:52:44.610192
734 19:52:44.613063 [CATrainingPosCal] consider 1 rank data
735 19:52:44.616681 u2DelayCellTimex100 = 270/100 ps
736 19:52:44.620000 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 19:52:44.623302 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
738 19:52:44.630021 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
739 19:52:44.633378 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
740 19:52:44.636472 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
741 19:52:44.639791 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 19:52:44.639873
743 19:52:44.643335 CA PerBit enable=1, Macro0, CA PI delay=33
744 19:52:44.643426
745 19:52:44.646428 [CBTSetCACLKResult] CA Dly = 33
746 19:52:44.646512 CS Dly: 6 (0~37)
747 19:52:44.649780 ==
748 19:52:44.649865 Dram Type= 6, Freq= 0, CH_0, rank 1
749 19:52:44.656450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
750 19:52:44.656551 ==
751 19:52:44.659869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 19:52:44.666219 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 19:52:44.675802 [CA 0] Center 37 (7~68) winsize 62
754 19:52:44.679421 [CA 1] Center 37 (7~68) winsize 62
755 19:52:44.682694 [CA 2] Center 35 (4~66) winsize 63
756 19:52:44.686238 [CA 3] Center 35 (4~66) winsize 63
757 19:52:44.689069 [CA 4] Center 33 (3~64) winsize 62
758 19:52:44.692662 [CA 5] Center 34 (3~65) winsize 63
759 19:52:44.692769
760 19:52:44.695871 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 19:52:44.695954
762 19:52:44.699297 [CATrainingPosCal] consider 2 rank data
763 19:52:44.702802 u2DelayCellTimex100 = 270/100 ps
764 19:52:44.705940 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 19:52:44.709128 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 19:52:44.715695 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 19:52:44.719029 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
768 19:52:44.722815 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
769 19:52:44.725888 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 19:52:44.725976
771 19:52:44.729210 CA PerBit enable=1, Macro0, CA PI delay=33
772 19:52:44.729291
773 19:52:44.732846 [CBTSetCACLKResult] CA Dly = 33
774 19:52:44.732929 CS Dly: 6 (0~37)
775 19:52:44.732996
776 19:52:44.736244 ----->DramcWriteLeveling(PI) begin...
777 19:52:44.739282 ==
778 19:52:44.743163 Dram Type= 6, Freq= 0, CH_0, rank 0
779 19:52:44.746669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
780 19:52:44.746756 ==
781 19:52:44.750314 Write leveling (Byte 0): 30 => 30
782 19:52:44.750397 Write leveling (Byte 1): 28 => 28
783 19:52:44.753856 DramcWriteLeveling(PI) end<-----
784 19:52:44.753940
785 19:52:44.754006 ==
786 19:52:44.757681 Dram Type= 6, Freq= 0, CH_0, rank 0
787 19:52:44.760784 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
788 19:52:44.760871 ==
789 19:52:44.764465 [Gating] SW mode calibration
790 19:52:44.771684 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 19:52:44.778517 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 19:52:44.782408 0 6 0 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 1)
793 19:52:44.785136 0 6 4 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
794 19:52:44.791819 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:52:44.795292 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:52:44.798561 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 19:52:44.805462 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 19:52:44.808537 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 19:52:44.811808 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 19:52:44.818459 0 7 0 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
801 19:52:44.821638 0 7 4 | B1->B0 | 3939 4141 | 1 0 | (0 0) (0 0)
802 19:52:44.825286 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
803 19:52:44.828504 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
804 19:52:44.835031 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
805 19:52:44.838477 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
806 19:52:44.841728 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
807 19:52:44.848526 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
808 19:52:44.851773 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
809 19:52:44.855164 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 19:52:44.861755 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 19:52:44.865495 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 19:52:44.868367 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 19:52:44.875293 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 19:52:44.878503 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 19:52:44.881805 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 19:52:44.888531 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 19:52:44.891858 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 19:52:44.895144 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
819 19:52:44.901956 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
820 19:52:44.905021 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
821 19:52:44.908380 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
822 19:52:44.915358 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
823 19:52:44.918299 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
824 19:52:44.921793 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
825 19:52:44.925094 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 19:52:44.928496 Total UI for P1: 0, mck2ui 16
827 19:52:44.931838 best dqsien dly found for B0: ( 0, 10, 0)
828 19:52:44.935177 Total UI for P1: 0, mck2ui 16
829 19:52:44.938400 best dqsien dly found for B1: ( 0, 10, 2)
830 19:52:44.941605 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
831 19:52:44.948334 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
832 19:52:44.948420
833 19:52:44.951675 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
834 19:52:44.955006 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
835 19:52:44.958447 [Gating] SW calibration Done
836 19:52:44.958531 ==
837 19:52:44.961775 Dram Type= 6, Freq= 0, CH_0, rank 0
838 19:52:44.965104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
839 19:52:44.965189 ==
840 19:52:44.965254 RX Vref Scan: 0
841 19:52:44.965314
842 19:52:44.968563 RX Vref 0 -> 0, step: 1
843 19:52:44.968644
844 19:52:44.971705 RX Delay -130 -> 252, step: 16
845 19:52:44.975213 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
846 19:52:44.978657 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
847 19:52:44.985404 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
848 19:52:44.988523 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
849 19:52:44.991997 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
850 19:52:44.995125 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
851 19:52:44.998499 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
852 19:52:45.005225 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
853 19:52:45.008406 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
854 19:52:45.011754 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
855 19:52:45.015172 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
856 19:52:45.018454 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
857 19:52:45.025639 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
858 19:52:45.028847 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
859 19:52:45.031861 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
860 19:52:45.035428 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
861 19:52:45.035510 ==
862 19:52:45.038636 Dram Type= 6, Freq= 0, CH_0, rank 0
863 19:52:45.042103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
864 19:52:45.045045 ==
865 19:52:45.045128 DQS Delay:
866 19:52:45.045193 DQS0 = 0, DQS1 = 0
867 19:52:45.048521 DQM Delay:
868 19:52:45.048603 DQM0 = 81, DQM1 = 74
869 19:52:45.051839 DQ Delay:
870 19:52:45.055204 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
871 19:52:45.055285 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
872 19:52:45.058527 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
873 19:52:45.061868 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
874 19:52:45.061950
875 19:52:45.065661
876 19:52:45.065742 ==
877 19:52:45.068668 Dram Type= 6, Freq= 0, CH_0, rank 0
878 19:52:45.071854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
879 19:52:45.071937 ==
880 19:52:45.072002
881 19:52:45.072063
882 19:52:45.075493 TX Vref Scan disable
883 19:52:45.075576 == TX Byte 0 ==
884 19:52:45.081899 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
885 19:52:45.085337 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
886 19:52:45.085420 == TX Byte 1 ==
887 19:52:45.092022 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
888 19:52:45.095363 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
889 19:52:45.095447 ==
890 19:52:45.098777 Dram Type= 6, Freq= 0, CH_0, rank 0
891 19:52:45.101887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
892 19:52:45.101970 ==
893 19:52:45.115496 TX Vref=22, minBit 0, minWin=27, winSum=443
894 19:52:45.119034 TX Vref=24, minBit 2, minWin=27, winSum=445
895 19:52:45.122100 TX Vref=26, minBit 4, minWin=27, winSum=450
896 19:52:45.125404 TX Vref=28, minBit 4, minWin=27, winSum=455
897 19:52:45.128905 TX Vref=30, minBit 2, minWin=28, winSum=458
898 19:52:45.132134 TX Vref=32, minBit 0, minWin=28, winSum=452
899 19:52:45.139018 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 30
900 19:52:45.139102
901 19:52:45.142873 Final TX Range 1 Vref 30
902 19:52:45.142956
903 19:52:45.143021 ==
904 19:52:45.146143 Dram Type= 6, Freq= 0, CH_0, rank 0
905 19:52:45.149827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
906 19:52:45.149910 ==
907 19:52:45.149975
908 19:52:45.150036
909 19:52:45.153093 TX Vref Scan disable
910 19:52:45.156384 == TX Byte 0 ==
911 19:52:45.159406 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
912 19:52:45.162798 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
913 19:52:45.166140 == TX Byte 1 ==
914 19:52:45.169445 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
915 19:52:45.173011 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
916 19:52:45.173093
917 19:52:45.176112 [DATLAT]
918 19:52:45.176200 Freq=800, CH0 RK0
919 19:52:45.176266
920 19:52:45.179434 DATLAT Default: 0xa
921 19:52:45.179516 0, 0xFFFF, sum = 0
922 19:52:45.182780 1, 0xFFFF, sum = 0
923 19:52:45.182862 2, 0xFFFF, sum = 0
924 19:52:45.186397 3, 0xFFFF, sum = 0
925 19:52:45.186481 4, 0xFFFF, sum = 0
926 19:52:45.189437 5, 0xFFFF, sum = 0
927 19:52:45.189521 6, 0xFFFF, sum = 0
928 19:52:45.193016 7, 0xFFFF, sum = 0
929 19:52:45.193099 8, 0x0, sum = 1
930 19:52:45.196290 9, 0x0, sum = 2
931 19:52:45.196376 10, 0x0, sum = 3
932 19:52:45.199484 11, 0x0, sum = 4
933 19:52:45.199567 best_step = 9
934 19:52:45.199633
935 19:52:45.199695 ==
936 19:52:45.202627 Dram Type= 6, Freq= 0, CH_0, rank 0
937 19:52:45.206068 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
938 19:52:45.206151 ==
939 19:52:45.209442 RX Vref Scan: 1
940 19:52:45.209523
941 19:52:45.212828 Set Vref Range= 32 -> 127
942 19:52:45.212909
943 19:52:45.212974 RX Vref 32 -> 127, step: 1
944 19:52:45.213035
945 19:52:45.216085 RX Delay -111 -> 252, step: 8
946 19:52:45.216197
947 19:52:45.219396 Set Vref, RX VrefLevel [Byte0]: 32
948 19:52:45.222804 [Byte1]: 32
949 19:52:45.226341
950 19:52:45.226421 Set Vref, RX VrefLevel [Byte0]: 33
951 19:52:45.229735 [Byte1]: 33
952 19:52:45.233925
953 19:52:45.234005 Set Vref, RX VrefLevel [Byte0]: 34
954 19:52:45.237205 [Byte1]: 34
955 19:52:45.241750
956 19:52:45.241830 Set Vref, RX VrefLevel [Byte0]: 35
957 19:52:45.244816 [Byte1]: 35
958 19:52:45.249812
959 19:52:45.249893 Set Vref, RX VrefLevel [Byte0]: 36
960 19:52:45.252660 [Byte1]: 36
961 19:52:45.256877
962 19:52:45.256958 Set Vref, RX VrefLevel [Byte0]: 37
963 19:52:45.260128 [Byte1]: 37
964 19:52:45.264498
965 19:52:45.264579 Set Vref, RX VrefLevel [Byte0]: 38
966 19:52:45.268064 [Byte1]: 38
967 19:52:45.272231
968 19:52:45.272312 Set Vref, RX VrefLevel [Byte0]: 39
969 19:52:45.275571 [Byte1]: 39
970 19:52:45.279800
971 19:52:45.279880 Set Vref, RX VrefLevel [Byte0]: 40
972 19:52:45.283226 [Byte1]: 40
973 19:52:45.287417
974 19:52:45.287498 Set Vref, RX VrefLevel [Byte0]: 41
975 19:52:45.290735 [Byte1]: 41
976 19:52:45.295334
977 19:52:45.295417 Set Vref, RX VrefLevel [Byte0]: 42
978 19:52:45.298495 [Byte1]: 42
979 19:52:45.302872
980 19:52:45.302953 Set Vref, RX VrefLevel [Byte0]: 43
981 19:52:45.306066 [Byte1]: 43
982 19:52:45.310269
983 19:52:45.310350 Set Vref, RX VrefLevel [Byte0]: 44
984 19:52:45.313767 [Byte1]: 44
985 19:52:45.318062
986 19:52:45.318143 Set Vref, RX VrefLevel [Byte0]: 45
987 19:52:45.321426 [Byte1]: 45
988 19:52:45.325685
989 19:52:45.325766 Set Vref, RX VrefLevel [Byte0]: 46
990 19:52:45.329071 [Byte1]: 46
991 19:52:45.333308
992 19:52:45.333389 Set Vref, RX VrefLevel [Byte0]: 47
993 19:52:45.336612 [Byte1]: 47
994 19:52:45.341011
995 19:52:45.341093 Set Vref, RX VrefLevel [Byte0]: 48
996 19:52:45.344496 [Byte1]: 48
997 19:52:45.348771
998 19:52:45.348851 Set Vref, RX VrefLevel [Byte0]: 49
999 19:52:45.351921 [Byte1]: 49
1000 19:52:45.356396
1001 19:52:45.356478 Set Vref, RX VrefLevel [Byte0]: 50
1002 19:52:45.359693 [Byte1]: 50
1003 19:52:45.363891
1004 19:52:45.363974 Set Vref, RX VrefLevel [Byte0]: 51
1005 19:52:45.367176 [Byte1]: 51
1006 19:52:45.371523
1007 19:52:45.371604 Set Vref, RX VrefLevel [Byte0]: 52
1008 19:52:45.375065 [Byte1]: 52
1009 19:52:45.379208
1010 19:52:45.379289 Set Vref, RX VrefLevel [Byte0]: 53
1011 19:52:45.382626 [Byte1]: 53
1012 19:52:45.386809
1013 19:52:45.386890 Set Vref, RX VrefLevel [Byte0]: 54
1014 19:52:45.390091 [Byte1]: 54
1015 19:52:45.394555
1016 19:52:45.394638 Set Vref, RX VrefLevel [Byte0]: 55
1017 19:52:45.397620 [Byte1]: 55
1018 19:52:45.402146
1019 19:52:45.402228 Set Vref, RX VrefLevel [Byte0]: 56
1020 19:52:45.405444 [Byte1]: 56
1021 19:52:45.410503
1022 19:52:45.410585 Set Vref, RX VrefLevel [Byte0]: 57
1023 19:52:45.413134 [Byte1]: 57
1024 19:52:45.418565
1025 19:52:45.418651 Set Vref, RX VrefLevel [Byte0]: 58
1026 19:52:45.421489 [Byte1]: 58
1027 19:52:45.425672
1028 19:52:45.425753 Set Vref, RX VrefLevel [Byte0]: 59
1029 19:52:45.429116 [Byte1]: 59
1030 19:52:45.433141
1031 19:52:45.433221 Set Vref, RX VrefLevel [Byte0]: 60
1032 19:52:45.436483 [Byte1]: 60
1033 19:52:45.440748
1034 19:52:45.440830 Set Vref, RX VrefLevel [Byte0]: 61
1035 19:52:45.444472 [Byte1]: 61
1036 19:52:45.448020
1037 19:52:45.448100 Set Vref, RX VrefLevel [Byte0]: 62
1038 19:52:45.451399 [Byte1]: 62
1039 19:52:45.455574
1040 19:52:45.455654 Set Vref, RX VrefLevel [Byte0]: 63
1041 19:52:45.462283 [Byte1]: 63
1042 19:52:45.462370
1043 19:52:45.465474 Set Vref, RX VrefLevel [Byte0]: 64
1044 19:52:45.468666 [Byte1]: 64
1045 19:52:45.468748
1046 19:52:45.472287 Set Vref, RX VrefLevel [Byte0]: 65
1047 19:52:45.475752 [Byte1]: 65
1048 19:52:45.475833
1049 19:52:45.478648 Set Vref, RX VrefLevel [Byte0]: 66
1050 19:52:45.482081 [Byte1]: 66
1051 19:52:45.486307
1052 19:52:45.486388 Set Vref, RX VrefLevel [Byte0]: 67
1053 19:52:45.489452 [Byte1]: 67
1054 19:52:45.494113
1055 19:52:45.494232 Set Vref, RX VrefLevel [Byte0]: 68
1056 19:52:45.497298 [Byte1]: 68
1057 19:52:45.501580
1058 19:52:45.501661 Set Vref, RX VrefLevel [Byte0]: 69
1059 19:52:45.504766 [Byte1]: 69
1060 19:52:45.509180
1061 19:52:45.509261 Set Vref, RX VrefLevel [Byte0]: 70
1062 19:52:45.512427 [Byte1]: 70
1063 19:52:45.516725
1064 19:52:45.516805 Set Vref, RX VrefLevel [Byte0]: 71
1065 19:52:45.520029 [Byte1]: 71
1066 19:52:45.524523
1067 19:52:45.524605 Set Vref, RX VrefLevel [Byte0]: 72
1068 19:52:45.528030 [Byte1]: 72
1069 19:52:45.532290
1070 19:52:45.532371 Final RX Vref Byte 0 = 52 to rank0
1071 19:52:45.535464 Final RX Vref Byte 1 = 56 to rank0
1072 19:52:45.538817 Final RX Vref Byte 0 = 52 to rank1
1073 19:52:45.542095 Final RX Vref Byte 1 = 56 to rank1==
1074 19:52:45.545353 Dram Type= 6, Freq= 0, CH_0, rank 0
1075 19:52:45.551923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1076 19:52:45.552008 ==
1077 19:52:45.552073 DQS Delay:
1078 19:52:45.552132 DQS0 = 0, DQS1 = 0
1079 19:52:45.555473 DQM Delay:
1080 19:52:45.555554 DQM0 = 83, DQM1 = 74
1081 19:52:45.559036 DQ Delay:
1082 19:52:45.562554 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1083 19:52:45.562649 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1084 19:52:45.565414 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1085 19:52:45.568789 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1086 19:52:45.572259
1087 19:52:45.572339
1088 19:52:45.578824 [DQSOSCAuto] RK0, (LSB)MR18= 0x3535, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1089 19:52:45.582074 CH0 RK0: MR19=606, MR18=3535
1090 19:52:45.588807 CH0_RK0: MR19=0x606, MR18=0x3535, DQSOSC=396, MR23=63, INC=94, DEC=62
1091 19:52:45.588893
1092 19:52:45.592206 ----->DramcWriteLeveling(PI) begin...
1093 19:52:45.592301 ==
1094 19:52:45.595482 Dram Type= 6, Freq= 0, CH_0, rank 1
1095 19:52:45.599062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1096 19:52:45.599144 ==
1097 19:52:45.602381 Write leveling (Byte 0): 29 => 29
1098 19:52:45.605523 Write leveling (Byte 1): 28 => 28
1099 19:52:45.609033 DramcWriteLeveling(PI) end<-----
1100 19:52:45.609113
1101 19:52:45.609178 ==
1102 19:52:45.612557 Dram Type= 6, Freq= 0, CH_0, rank 1
1103 19:52:45.615530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1104 19:52:45.615611 ==
1105 19:52:45.618951 [Gating] SW mode calibration
1106 19:52:45.625625 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1107 19:52:45.632426 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1108 19:52:45.635653 0 6 0 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
1109 19:52:45.638772 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 19:52:45.645590 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 19:52:45.648897 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 19:52:45.652342 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 19:52:45.659259 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 19:52:45.662372 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 19:52:45.665883 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 19:52:45.669273 0 7 0 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
1117 19:52:45.675833 0 7 4 | B1->B0 | 4242 4444 | 0 0 | (0 0) (0 0)
1118 19:52:45.679388 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 19:52:45.682397 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 19:52:45.689014 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 19:52:45.692463 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 19:52:45.695648 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 19:52:45.702499 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 19:52:45.705934 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1125 19:52:45.709308 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 19:52:45.716030 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 19:52:45.719484 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 19:52:45.722701 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 19:52:45.729294 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 19:52:45.732584 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 19:52:45.735996 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 19:52:45.742640 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 19:52:45.745878 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 19:52:45.749313 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 19:52:45.752533 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 19:52:45.759187 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 19:52:45.762486 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 19:52:45.765907 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 19:52:45.772381 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 19:52:45.775546 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 19:52:45.779237 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1142 19:52:45.785706 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1143 19:52:45.789011 Total UI for P1: 0, mck2ui 16
1144 19:52:45.792208 best dqsien dly found for B0: ( 0, 10, 4)
1145 19:52:45.792303 Total UI for P1: 0, mck2ui 16
1146 19:52:45.799119 best dqsien dly found for B1: ( 0, 10, 4)
1147 19:52:45.802289 best DQS0 dly(MCK, UI, PI) = (0, 10, 4)
1148 19:52:45.805752 best DQS1 dly(MCK, UI, PI) = (0, 10, 4)
1149 19:52:45.805832
1150 19:52:45.809057 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 4)
1151 19:52:45.812166 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 4)
1152 19:52:45.815896 [Gating] SW calibration Done
1153 19:52:45.815976 ==
1154 19:52:45.819020 Dram Type= 6, Freq= 0, CH_0, rank 1
1155 19:52:45.863306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1156 19:52:45.863404 ==
1157 19:52:45.863468 RX Vref Scan: 0
1158 19:52:45.863528
1159 19:52:45.863810 RX Vref 0 -> 0, step: 1
1160 19:52:45.863873
1161 19:52:45.863930 RX Delay -130 -> 252, step: 16
1162 19:52:45.863985 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1163 19:52:45.864121 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1164 19:52:45.864223 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1165 19:52:45.864300 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1166 19:52:45.864549 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1167 19:52:45.864632 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1168 19:52:45.864714 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1169 19:52:45.865082 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1170 19:52:45.879945 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1171 19:52:45.880050 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1172 19:52:45.880363 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1173 19:52:45.880614 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1174 19:52:45.883580 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1175 19:52:45.886811 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1176 19:52:45.890099 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1177 19:52:45.893644 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1178 19:52:45.893724 ==
1179 19:52:45.896669 Dram Type= 6, Freq= 0, CH_0, rank 1
1180 19:52:45.900349 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1181 19:52:45.903441 ==
1182 19:52:45.903533 DQS Delay:
1183 19:52:45.903618 DQS0 = 0, DQS1 = 0
1184 19:52:45.906947 DQM Delay:
1185 19:52:45.907026 DQM0 = 83, DQM1 = 73
1186 19:52:45.910363 DQ Delay:
1187 19:52:45.910443 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =69
1188 19:52:45.913549 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1189 19:52:45.916979 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
1190 19:52:45.920120 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1191 19:52:45.920206
1192 19:52:45.923270
1193 19:52:45.923350 ==
1194 19:52:45.926825 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 19:52:45.930170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1196 19:52:45.930250 ==
1197 19:52:45.930314
1198 19:52:45.930373
1199 19:52:45.934061 TX Vref Scan disable
1200 19:52:45.934141 == TX Byte 0 ==
1201 19:52:45.939995 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1202 19:52:45.943550 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1203 19:52:45.943630 == TX Byte 1 ==
1204 19:52:45.950607 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1205 19:52:45.953396 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1206 19:52:45.953476 ==
1207 19:52:45.956585 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 19:52:45.960064 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1209 19:52:45.960145 ==
1210 19:52:45.973396 TX Vref=22, minBit 0, minWin=27, winSum=443
1211 19:52:45.976652 TX Vref=24, minBit 13, minWin=27, winSum=452
1212 19:52:45.980135 TX Vref=26, minBit 14, minWin=27, winSum=453
1213 19:52:45.983274 TX Vref=28, minBit 2, minWin=28, winSum=458
1214 19:52:45.986790 TX Vref=30, minBit 2, minWin=28, winSum=458
1215 19:52:45.990342 TX Vref=32, minBit 2, minWin=28, winSum=460
1216 19:52:45.997378 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 32
1217 19:52:45.997465
1218 19:52:46.000861 Final TX Range 1 Vref 32
1219 19:52:46.000943
1220 19:52:46.001006 ==
1221 19:52:46.004807 Dram Type= 6, Freq= 0, CH_0, rank 1
1222 19:52:46.008030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1223 19:52:46.008110 ==
1224 19:52:46.008181
1225 19:52:46.008274
1226 19:52:46.011462 TX Vref Scan disable
1227 19:52:46.015042 == TX Byte 0 ==
1228 19:52:46.018630 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1229 19:52:46.021777 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1230 19:52:46.021858 == TX Byte 1 ==
1231 19:52:46.028589 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1232 19:52:46.032081 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1233 19:52:46.032162
1234 19:52:46.032232 [DATLAT]
1235 19:52:46.035425 Freq=800, CH0 RK1
1236 19:52:46.035505
1237 19:52:46.035569 DATLAT Default: 0x9
1238 19:52:46.038515 0, 0xFFFF, sum = 0
1239 19:52:46.038596 1, 0xFFFF, sum = 0
1240 19:52:46.041681 2, 0xFFFF, sum = 0
1241 19:52:46.041762 3, 0xFFFF, sum = 0
1242 19:52:46.045092 4, 0xFFFF, sum = 0
1243 19:52:46.048223 5, 0xFFFF, sum = 0
1244 19:52:46.048304 6, 0xFFFF, sum = 0
1245 19:52:46.051804 7, 0xFFFF, sum = 0
1246 19:52:46.051885 8, 0x0, sum = 1
1247 19:52:46.051950 9, 0x0, sum = 2
1248 19:52:46.054924 10, 0x0, sum = 3
1249 19:52:46.055005 11, 0x0, sum = 4
1250 19:52:46.058284 best_step = 9
1251 19:52:46.058363
1252 19:52:46.058427 ==
1253 19:52:46.061802 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 19:52:46.064860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1255 19:52:46.064941 ==
1256 19:52:46.068345 RX Vref Scan: 0
1257 19:52:46.068425
1258 19:52:46.068489 RX Vref 0 -> 0, step: 1
1259 19:52:46.068549
1260 19:52:46.071489 RX Delay -111 -> 252, step: 8
1261 19:52:46.078405 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1262 19:52:46.081629 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1263 19:52:46.084811 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1264 19:52:46.088271 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1265 19:52:46.091713 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1266 19:52:46.098331 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1267 19:52:46.101788 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1268 19:52:46.105121 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1269 19:52:46.108462 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1270 19:52:46.111919 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1271 19:52:46.118426 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1272 19:52:46.121634 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1273 19:52:46.125072 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1274 19:52:46.128393 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1275 19:52:46.131823 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1276 19:52:46.138677 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1277 19:52:46.138833 ==
1278 19:52:46.141844 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 19:52:46.145289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1280 19:52:46.145453 ==
1281 19:52:46.145533 DQS Delay:
1282 19:52:46.148619 DQS0 = 0, DQS1 = 0
1283 19:52:46.148785 DQM Delay:
1284 19:52:46.151904 DQM0 = 86, DQM1 = 74
1285 19:52:46.152072 DQ Delay:
1286 19:52:46.155223 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =80
1287 19:52:46.158653 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1288 19:52:46.162014 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64
1289 19:52:46.165114 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1290 19:52:46.165296
1291 19:52:46.165402
1292 19:52:46.175240 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1293 19:52:46.175477 CH0 RK1: MR19=606, MR18=4D4D
1294 19:52:46.182073 CH0_RK1: MR19=0x606, MR18=0x4D4D, DQSOSC=390, MR23=63, INC=97, DEC=64
1295 19:52:46.185145 [RxdqsGatingPostProcess] freq 800
1296 19:52:46.191939 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1297 19:52:46.195450 Pre-setting of DQS Precalculation
1298 19:52:46.198723 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1299 19:52:46.199126 ==
1300 19:52:46.201679 Dram Type= 6, Freq= 0, CH_1, rank 0
1301 19:52:46.204955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1302 19:52:46.205037 ==
1303 19:52:46.211716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1304 19:52:46.218112 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1305 19:52:46.226134 [CA 0] Center 36 (6~67) winsize 62
1306 19:52:46.229559 [CA 1] Center 37 (6~68) winsize 63
1307 19:52:46.232873 [CA 2] Center 34 (4~65) winsize 62
1308 19:52:46.236076 [CA 3] Center 34 (4~65) winsize 62
1309 19:52:46.239499 [CA 4] Center 33 (3~64) winsize 62
1310 19:52:46.242654 [CA 5] Center 33 (3~64) winsize 62
1311 19:52:46.242734
1312 19:52:46.246091 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1313 19:52:46.246174
1314 19:52:46.249404 [CATrainingPosCal] consider 1 rank data
1315 19:52:46.252825 u2DelayCellTimex100 = 270/100 ps
1316 19:52:46.256074 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1317 19:52:46.259611 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1318 19:52:46.266253 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1319 19:52:46.269532 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1320 19:52:46.272681 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1321 19:52:46.276370 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1322 19:52:46.276450
1323 19:52:46.279310 CA PerBit enable=1, Macro0, CA PI delay=33
1324 19:52:46.279389
1325 19:52:46.282859 [CBTSetCACLKResult] CA Dly = 33
1326 19:52:46.282939 CS Dly: 4 (0~35)
1327 19:52:46.286086 ==
1328 19:52:46.286166 Dram Type= 6, Freq= 0, CH_1, rank 1
1329 19:52:46.292650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1330 19:52:46.292730 ==
1331 19:52:46.296250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1332 19:52:46.302820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1333 19:52:46.312018 [CA 0] Center 37 (6~68) winsize 63
1334 19:52:46.315252 [CA 1] Center 37 (6~68) winsize 63
1335 19:52:46.318597 [CA 2] Center 34 (4~65) winsize 62
1336 19:52:46.322475 [CA 3] Center 34 (4~65) winsize 62
1337 19:52:46.325561 [CA 4] Center 33 (3~64) winsize 62
1338 19:52:46.328782 [CA 5] Center 33 (3~64) winsize 62
1339 19:52:46.328861
1340 19:52:46.331869 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1341 19:52:46.331948
1342 19:52:46.335196 [CATrainingPosCal] consider 2 rank data
1343 19:52:46.338573 u2DelayCellTimex100 = 270/100 ps
1344 19:52:46.341970 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1345 19:52:46.345519 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1346 19:52:46.351967 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1347 19:52:46.355375 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1348 19:52:46.358886 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1349 19:52:46.362048 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1350 19:52:46.362169
1351 19:52:46.365380 CA PerBit enable=1, Macro0, CA PI delay=33
1352 19:52:46.365459
1353 19:52:46.368710 [CBTSetCACLKResult] CA Dly = 33
1354 19:52:46.368789 CS Dly: 5 (0~37)
1355 19:52:46.368852
1356 19:52:46.372017 ----->DramcWriteLeveling(PI) begin...
1357 19:52:46.375234 ==
1358 19:52:46.378548 Dram Type= 6, Freq= 0, CH_1, rank 0
1359 19:52:46.381944 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1360 19:52:46.382024 ==
1361 19:52:46.385040 Write leveling (Byte 0): 28 => 28
1362 19:52:46.388372 Write leveling (Byte 1): 27 => 27
1363 19:52:46.391771 DramcWriteLeveling(PI) end<-----
1364 19:52:46.391849
1365 19:52:46.391911 ==
1366 19:52:46.395210 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 19:52:46.398498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1368 19:52:46.398577 ==
1369 19:52:46.401745 [Gating] SW mode calibration
1370 19:52:46.408607 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1371 19:52:46.414973 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1372 19:52:46.418565 0 6 0 | B1->B0 | 3030 2828 | 0 0 | (1 1) (0 0)
1373 19:52:46.421923 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 19:52:46.424952 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 19:52:46.431752 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 19:52:46.435245 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 19:52:46.438321 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 19:52:46.445051 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 19:52:46.448446 0 6 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1380 19:52:46.451695 0 7 0 | B1->B0 | 2d2d 3a3a | 0 1 | (0 0) (0 0)
1381 19:52:46.458441 0 7 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1382 19:52:46.461715 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 19:52:46.465059 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 19:52:46.471614 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 19:52:46.475021 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 19:52:46.478365 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 19:52:46.485029 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1388 19:52:46.488349 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1389 19:52:46.491781 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 19:52:46.498308 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 19:52:46.501670 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 19:52:46.504969 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 19:52:46.511730 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 19:52:46.514856 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 19:52:46.518315 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 19:52:46.521670 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 19:52:46.528438 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 19:52:46.531855 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 19:52:46.535045 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 19:52:46.541799 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 19:52:46.545215 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 19:52:46.548162 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 19:52:46.554822 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 19:52:46.558176 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1405 19:52:46.561488 Total UI for P1: 0, mck2ui 16
1406 19:52:46.564802 best dqsien dly found for B0: ( 0, 9, 30)
1407 19:52:46.568059 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1408 19:52:46.571765 Total UI for P1: 0, mck2ui 16
1409 19:52:46.574636 best dqsien dly found for B1: ( 0, 10, 0)
1410 19:52:46.578236 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1411 19:52:46.581644 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1412 19:52:46.581738
1413 19:52:46.588257 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1414 19:52:46.591488 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1415 19:52:46.595105 [Gating] SW calibration Done
1416 19:52:46.595257 ==
1417 19:52:46.598454 Dram Type= 6, Freq= 0, CH_1, rank 0
1418 19:52:46.601603 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1419 19:52:46.601766 ==
1420 19:52:46.601845 RX Vref Scan: 0
1421 19:52:46.601914
1422 19:52:46.604783 RX Vref 0 -> 0, step: 1
1423 19:52:46.604936
1424 19:52:46.608011 RX Delay -130 -> 252, step: 16
1425 19:52:46.611324 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1426 19:52:46.615533 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1427 19:52:46.621825 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1428 19:52:46.625398 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1429 19:52:46.628379 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1430 19:52:46.631635 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1431 19:52:46.635057 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1432 19:52:46.638598 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1433 19:52:46.645188 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1434 19:52:46.648855 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1435 19:52:46.652405 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1436 19:52:46.656051 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1437 19:52:46.659837 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1438 19:52:46.663548 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1439 19:52:46.667065 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1440 19:52:46.674402 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1441 19:52:46.674785 ==
1442 19:52:46.677820 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 19:52:46.681988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1444 19:52:46.682588 ==
1445 19:52:46.682928 DQS Delay:
1446 19:52:46.683279 DQS0 = 0, DQS1 = 0
1447 19:52:46.685376 DQM Delay:
1448 19:52:46.686001 DQM0 = 83, DQM1 = 74
1449 19:52:46.689148 DQ Delay:
1450 19:52:46.689738 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1451 19:52:46.692170 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =85
1452 19:52:46.695795 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1453 19:52:46.698816 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1454 19:52:46.699235
1455 19:52:46.699566
1456 19:52:46.702558 ==
1457 19:52:46.705769 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 19:52:46.708928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1459 19:52:46.709351 ==
1460 19:52:46.709687
1461 19:52:46.709994
1462 19:52:46.711993 TX Vref Scan disable
1463 19:52:46.712443 == TX Byte 0 ==
1464 19:52:46.715809 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1465 19:52:46.722577 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1466 19:52:46.723103 == TX Byte 1 ==
1467 19:52:46.725878 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1468 19:52:46.732238 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1469 19:52:46.732768 ==
1470 19:52:46.735806 Dram Type= 6, Freq= 0, CH_1, rank 0
1471 19:52:46.739412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1472 19:52:46.739932 ==
1473 19:52:46.751828 TX Vref=22, minBit 3, minWin=27, winSum=446
1474 19:52:46.755360 TX Vref=24, minBit 9, minWin=27, winSum=450
1475 19:52:46.758452 TX Vref=26, minBit 3, minWin=28, winSum=453
1476 19:52:46.761880 TX Vref=28, minBit 3, minWin=27, winSum=454
1477 19:52:46.765060 TX Vref=30, minBit 0, minWin=28, winSum=460
1478 19:52:46.768766 TX Vref=32, minBit 0, minWin=28, winSum=456
1479 19:52:46.775677 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1480 19:52:46.776246
1481 19:52:46.779074 Final TX Range 1 Vref 30
1482 19:52:46.779592
1483 19:52:46.779927 ==
1484 19:52:46.782471 Dram Type= 6, Freq= 0, CH_1, rank 0
1485 19:52:46.785532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1486 19:52:46.786053 ==
1487 19:52:46.786392
1488 19:52:46.786699
1489 19:52:46.788780 TX Vref Scan disable
1490 19:52:46.791892 == TX Byte 0 ==
1491 19:52:46.795823 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1492 19:52:46.798917 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1493 19:52:46.802483 == TX Byte 1 ==
1494 19:52:46.805055 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1495 19:52:46.808293 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1496 19:52:46.811872
1497 19:52:46.812625 [DATLAT]
1498 19:52:46.812985 Freq=800, CH1 RK0
1499 19:52:46.813301
1500 19:52:46.815022 DATLAT Default: 0xa
1501 19:52:46.815435 0, 0xFFFF, sum = 0
1502 19:52:46.818439 1, 0xFFFF, sum = 0
1503 19:52:46.818962 2, 0xFFFF, sum = 0
1504 19:52:46.822038 3, 0xFFFF, sum = 0
1505 19:52:46.822494 4, 0xFFFF, sum = 0
1506 19:52:46.825242 5, 0xFFFF, sum = 0
1507 19:52:46.825670 6, 0xFFFF, sum = 0
1508 19:52:46.828857 7, 0xFFFF, sum = 0
1509 19:52:46.829280 8, 0x0, sum = 1
1510 19:52:46.831950 9, 0x0, sum = 2
1511 19:52:46.832510 10, 0x0, sum = 3
1512 19:52:46.835364 11, 0x0, sum = 4
1513 19:52:46.835894 best_step = 9
1514 19:52:46.836288
1515 19:52:46.836609 ==
1516 19:52:46.838499 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 19:52:46.845422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1518 19:52:46.845933 ==
1519 19:52:46.846269 RX Vref Scan: 1
1520 19:52:46.846581
1521 19:52:46.848652 Set Vref Range= 32 -> 127
1522 19:52:46.849159
1523 19:52:46.851864 RX Vref 32 -> 127, step: 1
1524 19:52:46.852436
1525 19:52:46.852781 RX Delay -111 -> 252, step: 8
1526 19:52:46.855268
1527 19:52:46.855682 Set Vref, RX VrefLevel [Byte0]: 32
1528 19:52:46.858332 [Byte1]: 32
1529 19:52:46.863037
1530 19:52:46.863470 Set Vref, RX VrefLevel [Byte0]: 33
1531 19:52:46.865986 [Byte1]: 33
1532 19:52:46.870298
1533 19:52:46.870717 Set Vref, RX VrefLevel [Byte0]: 34
1534 19:52:46.873969 [Byte1]: 34
1535 19:52:46.878186
1536 19:52:46.878692 Set Vref, RX VrefLevel [Byte0]: 35
1537 19:52:46.881384 [Byte1]: 35
1538 19:52:46.885813
1539 19:52:46.886323 Set Vref, RX VrefLevel [Byte0]: 36
1540 19:52:46.889151 [Byte1]: 36
1541 19:52:46.893788
1542 19:52:46.894340 Set Vref, RX VrefLevel [Byte0]: 37
1543 19:52:46.896640 [Byte1]: 37
1544 19:52:46.900766
1545 19:52:46.901173 Set Vref, RX VrefLevel [Byte0]: 38
1546 19:52:46.904285 [Byte1]: 38
1547 19:52:46.908793
1548 19:52:46.909305 Set Vref, RX VrefLevel [Byte0]: 39
1549 19:52:46.911982 [Byte1]: 39
1550 19:52:46.916401
1551 19:52:46.916943 Set Vref, RX VrefLevel [Byte0]: 40
1552 19:52:46.920506 [Byte1]: 40
1553 19:52:46.923895
1554 19:52:46.924329 Set Vref, RX VrefLevel [Byte0]: 41
1555 19:52:46.927350 [Byte1]: 41
1556 19:52:46.931519
1557 19:52:46.932027 Set Vref, RX VrefLevel [Byte0]: 42
1558 19:52:46.934964 [Byte1]: 42
1559 19:52:46.939239
1560 19:52:46.939781 Set Vref, RX VrefLevel [Byte0]: 43
1561 19:52:46.942597 [Byte1]: 43
1562 19:52:46.947164
1563 19:52:46.947676 Set Vref, RX VrefLevel [Byte0]: 44
1564 19:52:46.950306 [Byte1]: 44
1565 19:52:46.954863
1566 19:52:46.955400 Set Vref, RX VrefLevel [Byte0]: 45
1567 19:52:46.957902 [Byte1]: 45
1568 19:52:46.962769
1569 19:52:46.963488 Set Vref, RX VrefLevel [Byte0]: 46
1570 19:52:46.965728 [Byte1]: 46
1571 19:52:46.969878
1572 19:52:46.970390 Set Vref, RX VrefLevel [Byte0]: 47
1573 19:52:46.973194 [Byte1]: 47
1574 19:52:46.977681
1575 19:52:46.978192 Set Vref, RX VrefLevel [Byte0]: 48
1576 19:52:46.980768 [Byte1]: 48
1577 19:52:46.985180
1578 19:52:46.985687 Set Vref, RX VrefLevel [Byte0]: 49
1579 19:52:46.988867 [Byte1]: 49
1580 19:52:46.992647
1581 19:52:46.993054 Set Vref, RX VrefLevel [Byte0]: 50
1582 19:52:46.996250 [Byte1]: 50
1583 19:52:47.000372
1584 19:52:47.000780 Set Vref, RX VrefLevel [Byte0]: 51
1585 19:52:47.003747 [Byte1]: 51
1586 19:52:47.008317
1587 19:52:47.008831 Set Vref, RX VrefLevel [Byte0]: 52
1588 19:52:47.011672 [Byte1]: 52
1589 19:52:47.015533
1590 19:52:47.015940 Set Vref, RX VrefLevel [Byte0]: 53
1591 19:52:47.018883 [Byte1]: 53
1592 19:52:47.023365
1593 19:52:47.023872 Set Vref, RX VrefLevel [Byte0]: 54
1594 19:52:47.026742 [Byte1]: 54
1595 19:52:47.031002
1596 19:52:47.031513 Set Vref, RX VrefLevel [Byte0]: 55
1597 19:52:47.034278 [Byte1]: 55
1598 19:52:47.038815
1599 19:52:47.039333 Set Vref, RX VrefLevel [Byte0]: 56
1600 19:52:47.042157 [Byte1]: 56
1601 19:52:47.046581
1602 19:52:47.047131 Set Vref, RX VrefLevel [Byte0]: 57
1603 19:52:47.049801 [Byte1]: 57
1604 19:52:47.053823
1605 19:52:47.054363 Set Vref, RX VrefLevel [Byte0]: 58
1606 19:52:47.057456 [Byte1]: 58
1607 19:52:47.061677
1608 19:52:47.062183 Set Vref, RX VrefLevel [Byte0]: 59
1609 19:52:47.064704 [Byte1]: 59
1610 19:52:47.069516
1611 19:52:47.070023 Set Vref, RX VrefLevel [Byte0]: 60
1612 19:52:47.073125 [Byte1]: 60
1613 19:52:47.076984
1614 19:52:47.077493 Set Vref, RX VrefLevel [Byte0]: 61
1615 19:52:47.080294 [Byte1]: 61
1616 19:52:47.084514
1617 19:52:47.085022 Set Vref, RX VrefLevel [Byte0]: 62
1618 19:52:47.088115 [Byte1]: 62
1619 19:52:47.092767
1620 19:52:47.093271 Set Vref, RX VrefLevel [Byte0]: 63
1621 19:52:47.095561 [Byte1]: 63
1622 19:52:47.099609
1623 19:52:47.100017 Set Vref, RX VrefLevel [Byte0]: 64
1624 19:52:47.103154 [Byte1]: 64
1625 19:52:47.107630
1626 19:52:47.108136 Set Vref, RX VrefLevel [Byte0]: 65
1627 19:52:47.111100 [Byte1]: 65
1628 19:52:47.115023
1629 19:52:47.115431 Set Vref, RX VrefLevel [Byte0]: 66
1630 19:52:47.118969 [Byte1]: 66
1631 19:52:47.123125
1632 19:52:47.123632 Set Vref, RX VrefLevel [Byte0]: 67
1633 19:52:47.126135 [Byte1]: 67
1634 19:52:47.130558
1635 19:52:47.131067 Set Vref, RX VrefLevel [Byte0]: 68
1636 19:52:47.133760 [Byte1]: 68
1637 19:52:47.138263
1638 19:52:47.138768 Set Vref, RX VrefLevel [Byte0]: 69
1639 19:52:47.141374 [Byte1]: 69
1640 19:52:47.146165
1641 19:52:47.146674 Set Vref, RX VrefLevel [Byte0]: 70
1642 19:52:47.149019 [Byte1]: 70
1643 19:52:47.153281
1644 19:52:47.153792 Set Vref, RX VrefLevel [Byte0]: 71
1645 19:52:47.156641 [Byte1]: 71
1646 19:52:47.160880
1647 19:52:47.161286 Set Vref, RX VrefLevel [Byte0]: 72
1648 19:52:47.164408 [Byte1]: 72
1649 19:52:47.168798
1650 19:52:47.169202 Set Vref, RX VrefLevel [Byte0]: 73
1651 19:52:47.171695 [Byte1]: 73
1652 19:52:47.176505
1653 19:52:47.177048 Set Vref, RX VrefLevel [Byte0]: 74
1654 19:52:47.179465 [Byte1]: 74
1655 19:52:47.183995
1656 19:52:47.184575 Final RX Vref Byte 0 = 60 to rank0
1657 19:52:47.187788 Final RX Vref Byte 1 = 54 to rank0
1658 19:52:47.190675 Final RX Vref Byte 0 = 60 to rank1
1659 19:52:47.194023 Final RX Vref Byte 1 = 54 to rank1==
1660 19:52:47.197522 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 19:52:47.204246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1662 19:52:47.204780 ==
1663 19:52:47.205117 DQS Delay:
1664 19:52:47.205422 DQS0 = 0, DQS1 = 0
1665 19:52:47.207123 DQM Delay:
1666 19:52:47.207529 DQM0 = 81, DQM1 = 75
1667 19:52:47.210665 DQ Delay:
1668 19:52:47.213836 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1669 19:52:47.214244 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1670 19:52:47.217885 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1671 19:52:47.220557 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1672 19:52:47.224113
1673 19:52:47.224673
1674 19:52:47.230914 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1675 19:52:47.234636 CH1 RK0: MR19=606, MR18=4D4D
1676 19:52:47.238221 CH1_RK0: MR19=0x606, MR18=0x4D4D, DQSOSC=390, MR23=63, INC=97, DEC=64
1677 19:52:47.238726
1678 19:52:47.241639 ----->DramcWriteLeveling(PI) begin...
1679 19:52:47.244785 ==
1680 19:52:47.248033 Dram Type= 6, Freq= 0, CH_1, rank 1
1681 19:52:47.251817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1682 19:52:47.252375 ==
1683 19:52:47.254589 Write leveling (Byte 0): 24 => 24
1684 19:52:47.258265 Write leveling (Byte 1): 24 => 24
1685 19:52:47.261402 DramcWriteLeveling(PI) end<-----
1686 19:52:47.261902
1687 19:52:47.262231 ==
1688 19:52:47.264427 Dram Type= 6, Freq= 0, CH_1, rank 1
1689 19:52:47.268286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1690 19:52:47.268801 ==
1691 19:52:47.271553 [Gating] SW mode calibration
1692 19:52:47.278281 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1693 19:52:47.281677 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1694 19:52:47.288561 0 6 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1695 19:52:47.291548 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1696 19:52:47.294976 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1697 19:52:47.301084 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1698 19:52:47.304671 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1699 19:52:47.308027 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1700 19:52:47.314907 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1701 19:52:47.318257 0 6 28 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
1702 19:52:47.321578 0 7 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
1703 19:52:47.328147 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1704 19:52:47.331582 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1705 19:52:47.335018 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1706 19:52:47.341606 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1707 19:52:47.344893 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1708 19:52:47.347829 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1709 19:52:47.354552 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1710 19:52:47.358100 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1711 19:52:47.361391 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1712 19:52:47.367948 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1713 19:52:47.371411 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 19:52:47.374884 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 19:52:47.378083 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 19:52:47.384609 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 19:52:47.388109 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 19:52:47.391414 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 19:52:47.397957 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 19:52:47.401201 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 19:52:47.404491 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 19:52:47.411162 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 19:52:47.414626 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 19:52:47.417679 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1725 19:52:47.425061 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1726 19:52:47.428070 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1727 19:52:47.431160 Total UI for P1: 0, mck2ui 16
1728 19:52:47.434871 best dqsien dly found for B0: ( 0, 9, 26)
1729 19:52:47.437827 Total UI for P1: 0, mck2ui 16
1730 19:52:47.441152 best dqsien dly found for B1: ( 0, 9, 30)
1731 19:52:47.444668 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1732 19:52:47.448088 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1733 19:52:47.448643
1734 19:52:47.451546 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1735 19:52:47.454503 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1736 19:52:47.457708 [Gating] SW calibration Done
1737 19:52:47.458261 ==
1738 19:52:47.460942 Dram Type= 6, Freq= 0, CH_1, rank 1
1739 19:52:47.464284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1740 19:52:47.468060 ==
1741 19:52:47.468626 RX Vref Scan: 0
1742 19:52:47.468959
1743 19:52:47.471548 RX Vref 0 -> 0, step: 1
1744 19:52:47.472157
1745 19:52:47.474527 RX Delay -130 -> 252, step: 16
1746 19:52:47.478030 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1747 19:52:47.481000 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1748 19:52:47.484727 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1749 19:52:47.488000 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1750 19:52:47.494546 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1751 19:52:47.498004 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1752 19:52:47.500981 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1753 19:52:47.504702 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1754 19:52:47.508071 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1755 19:52:47.514523 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1756 19:52:47.517973 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1757 19:52:47.520779 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1758 19:52:47.524519 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1759 19:52:47.527864 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1760 19:52:47.534684 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1761 19:52:47.538022 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1762 19:52:47.538602 ==
1763 19:52:47.541154 Dram Type= 6, Freq= 0, CH_1, rank 1
1764 19:52:47.544598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1765 19:52:47.545132 ==
1766 19:52:47.548066 DQS Delay:
1767 19:52:47.548619 DQS0 = 0, DQS1 = 0
1768 19:52:47.549011 DQM Delay:
1769 19:52:47.551463 DQM0 = 85, DQM1 = 73
1770 19:52:47.551980 DQ Delay:
1771 19:52:47.554450 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1772 19:52:47.557626 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1773 19:52:47.561248 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1774 19:52:47.564558 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1775 19:52:47.565068
1776 19:52:47.565400
1777 19:52:47.565704 ==
1778 19:52:47.567855 Dram Type= 6, Freq= 0, CH_1, rank 1
1779 19:52:47.574575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1780 19:52:47.575094 ==
1781 19:52:47.575426
1782 19:52:47.575729
1783 19:52:47.576019 TX Vref Scan disable
1784 19:52:47.577762 == TX Byte 0 ==
1785 19:52:47.581649 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1786 19:52:47.584516 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1787 19:52:47.588003 == TX Byte 1 ==
1788 19:52:47.591575 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1789 19:52:47.594920 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1790 19:52:47.598009 ==
1791 19:52:47.601328 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 19:52:47.604089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1793 19:52:47.604561 ==
1794 19:52:47.617081 TX Vref=22, minBit 8, minWin=27, winSum=450
1795 19:52:47.619944 TX Vref=24, minBit 8, minWin=27, winSum=453
1796 19:52:47.623381 TX Vref=26, minBit 3, minWin=28, winSum=455
1797 19:52:47.626803 TX Vref=28, minBit 5, minWin=28, winSum=455
1798 19:52:47.630263 TX Vref=30, minBit 0, minWin=28, winSum=457
1799 19:52:47.633268 TX Vref=32, minBit 0, minWin=28, winSum=455
1800 19:52:47.640017 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1801 19:52:47.640575
1802 19:52:47.643089 Final TX Range 1 Vref 30
1803 19:52:47.643503
1804 19:52:47.643832 ==
1805 19:52:47.646684 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 19:52:47.650361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1807 19:52:47.650899 ==
1808 19:52:47.651240
1809 19:52:47.651546
1810 19:52:47.653298 TX Vref Scan disable
1811 19:52:47.656476 == TX Byte 0 ==
1812 19:52:47.659878 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1813 19:52:47.663415 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1814 19:52:47.666570 == TX Byte 1 ==
1815 19:52:47.669987 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1816 19:52:47.673254 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1817 19:52:47.673746
1818 19:52:47.676667 [DATLAT]
1819 19:52:47.677174 Freq=800, CH1 RK1
1820 19:52:47.677511
1821 19:52:47.679866 DATLAT Default: 0x9
1822 19:52:47.680374 0, 0xFFFF, sum = 0
1823 19:52:47.683789 1, 0xFFFF, sum = 0
1824 19:52:47.684349 2, 0xFFFF, sum = 0
1825 19:52:47.686580 3, 0xFFFF, sum = 0
1826 19:52:47.686995 4, 0xFFFF, sum = 0
1827 19:52:47.690078 5, 0xFFFF, sum = 0
1828 19:52:47.690591 6, 0xFFFF, sum = 0
1829 19:52:47.693206 7, 0xFFFF, sum = 0
1830 19:52:47.693734 8, 0x0, sum = 1
1831 19:52:47.696494 9, 0x0, sum = 2
1832 19:52:47.696914 10, 0x0, sum = 3
1833 19:52:47.699841 11, 0x0, sum = 4
1834 19:52:47.700294 best_step = 9
1835 19:52:47.700628
1836 19:52:47.700931 ==
1837 19:52:47.703328 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 19:52:47.710096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1839 19:52:47.710607 ==
1840 19:52:47.710942 RX Vref Scan: 0
1841 19:52:47.711248
1842 19:52:47.713124 RX Vref 0 -> 0, step: 1
1843 19:52:47.713534
1844 19:52:47.716569 RX Delay -111 -> 252, step: 8
1845 19:52:47.720021 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1846 19:52:47.723598 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1847 19:52:47.726587 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1848 19:52:47.733535 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1849 19:52:47.736674 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1850 19:52:47.739976 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1851 19:52:47.743171 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1852 19:52:47.746683 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1853 19:52:47.752974 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1854 19:52:47.756575 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1855 19:52:47.760348 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1856 19:52:47.763319 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1857 19:52:47.766671 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1858 19:52:47.773225 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1859 19:52:47.776457 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1860 19:52:47.779872 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1861 19:52:47.780413 ==
1862 19:52:47.783410 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 19:52:47.786979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1864 19:52:47.787496 ==
1865 19:52:47.790136 DQS Delay:
1866 19:52:47.790651 DQS0 = 0, DQS1 = 0
1867 19:52:47.793174 DQM Delay:
1868 19:52:47.793584 DQM0 = 83, DQM1 = 74
1869 19:52:47.793913 DQ Delay:
1870 19:52:47.797185 DQ0 =84, DQ1 =80, DQ2 =72, DQ3 =84
1871 19:52:47.800295 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1872 19:52:47.803405 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1873 19:52:47.807202 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1874 19:52:47.807708
1875 19:52:47.808040
1876 19:52:47.816904 [DQSOSCAuto] RK1, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1877 19:52:47.820238 CH1 RK1: MR19=606, MR18=3838
1878 19:52:47.823898 CH1_RK1: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1879 19:52:47.826925 [RxdqsGatingPostProcess] freq 800
1880 19:52:47.833586 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1881 19:52:47.836793 Pre-setting of DQS Precalculation
1882 19:52:47.840290 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1883 19:52:47.847143 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1884 19:52:47.856768 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1885 19:52:47.857313
1886 19:52:47.857653
1887 19:52:47.860474 [Calibration Summary] 1600 Mbps
1888 19:52:47.860980 CH 0, Rank 0
1889 19:52:47.863823 SW Impedance : PASS
1890 19:52:47.864408 DUTY Scan : NO K
1891 19:52:47.866681 ZQ Calibration : PASS
1892 19:52:47.870053 Jitter Meter : NO K
1893 19:52:47.870459 CBT Training : PASS
1894 19:52:47.873325 Write leveling : PASS
1895 19:52:47.873732 RX DQS gating : PASS
1896 19:52:47.877124 RX DQ/DQS(RDDQC) : PASS
1897 19:52:47.880080 TX DQ/DQS : PASS
1898 19:52:47.880513 RX DATLAT : PASS
1899 19:52:47.883508 RX DQ/DQS(Engine): PASS
1900 19:52:47.886640 TX OE : NO K
1901 19:52:47.887047 All Pass.
1902 19:52:47.887373
1903 19:52:47.887675 CH 0, Rank 1
1904 19:52:47.889830 SW Impedance : PASS
1905 19:52:47.893288 DUTY Scan : NO K
1906 19:52:47.893695 ZQ Calibration : PASS
1907 19:52:47.896563 Jitter Meter : NO K
1908 19:52:47.900215 CBT Training : PASS
1909 19:52:47.900727 Write leveling : PASS
1910 19:52:47.903473 RX DQS gating : PASS
1911 19:52:47.907029 RX DQ/DQS(RDDQC) : PASS
1912 19:52:47.907531 TX DQ/DQS : PASS
1913 19:52:47.910073 RX DATLAT : PASS
1914 19:52:47.913553 RX DQ/DQS(Engine): PASS
1915 19:52:47.914055 TX OE : NO K
1916 19:52:47.914389 All Pass.
1917 19:52:47.916883
1918 19:52:47.917289 CH 1, Rank 0
1919 19:52:47.920489 SW Impedance : PASS
1920 19:52:47.920992 DUTY Scan : NO K
1921 19:52:47.923538 ZQ Calibration : PASS
1922 19:52:47.924036 Jitter Meter : NO K
1923 19:52:47.926920 CBT Training : PASS
1924 19:52:47.930016 Write leveling : PASS
1925 19:52:47.930424 RX DQS gating : PASS
1926 19:52:47.933414 RX DQ/DQS(RDDQC) : PASS
1927 19:52:47.936702 TX DQ/DQS : PASS
1928 19:52:47.937113 RX DATLAT : PASS
1929 19:52:47.940320 RX DQ/DQS(Engine): PASS
1930 19:52:47.943367 TX OE : NO K
1931 19:52:47.943876 All Pass.
1932 19:52:47.944244
1933 19:52:47.944557 CH 1, Rank 1
1934 19:52:47.947174 SW Impedance : PASS
1935 19:52:47.950175 DUTY Scan : NO K
1936 19:52:47.950689 ZQ Calibration : PASS
1937 19:52:47.953338 Jitter Meter : NO K
1938 19:52:47.956930 CBT Training : PASS
1939 19:52:47.957452 Write leveling : PASS
1940 19:52:47.960079 RX DQS gating : PASS
1941 19:52:47.963735 RX DQ/DQS(RDDQC) : PASS
1942 19:52:47.964310 TX DQ/DQS : PASS
1943 19:52:47.966800 RX DATLAT : PASS
1944 19:52:47.967250 RX DQ/DQS(Engine): PASS
1945 19:52:47.970045 TX OE : NO K
1946 19:52:47.970451 All Pass.
1947 19:52:47.970777
1948 19:52:47.973351 DramC Write-DBI off
1949 19:52:47.976643 PER_BANK_REFRESH: Hybrid Mode
1950 19:52:47.977151 TX_TRACKING: ON
1951 19:52:47.980325 [GetDramInforAfterCalByMRR] Vendor 6.
1952 19:52:47.983477 [GetDramInforAfterCalByMRR] Revision 606.
1953 19:52:47.990205 [GetDramInforAfterCalByMRR] Revision 2 0.
1954 19:52:47.990715 MR0 0x3939
1955 19:52:47.991044 MR8 0x1111
1956 19:52:47.993023 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1957 19:52:47.993429
1958 19:52:47.996632 MR0 0x3939
1959 19:52:47.997138 MR8 0x1111
1960 19:52:47.999908 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1961 19:52:48.000581
1962 19:52:48.010121 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1963 19:52:48.013586 [FAST_K] Save calibration result to emmc
1964 19:52:48.016500 [FAST_K] Save calibration result to emmc
1965 19:52:48.020396 dram_init: config_dvfs: 1
1966 19:52:48.023399 dramc_set_vcore_voltage set vcore to 662500
1967 19:52:48.023913 Read voltage for 1200, 2
1968 19:52:48.026759 Vio18 = 0
1969 19:52:48.027271 Vcore = 662500
1970 19:52:48.027601 Vdram = 0
1971 19:52:48.029987 Vddq = 0
1972 19:52:48.030394 Vmddr = 0
1973 19:52:48.033531 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1974 19:52:48.040267 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1975 19:52:48.043491 MEM_TYPE=3, freq_sel=15
1976 19:52:48.046908 sv_algorithm_assistance_LP4_1600
1977 19:52:48.050233 ============ PULL DRAM RESETB DOWN ============
1978 19:52:48.053515 ========== PULL DRAM RESETB DOWN end =========
1979 19:52:48.057146 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1980 19:52:48.059933 ===================================
1981 19:52:48.063657 LPDDR4 DRAM CONFIGURATION
1982 19:52:48.066839 ===================================
1983 19:52:48.070032 EX_ROW_EN[0] = 0x0
1984 19:52:48.070441 EX_ROW_EN[1] = 0x0
1985 19:52:48.073674 LP4Y_EN = 0x0
1986 19:52:48.074083 WORK_FSP = 0x0
1987 19:52:48.076524 WL = 0x4
1988 19:52:48.076933 RL = 0x4
1989 19:52:48.080020 BL = 0x2
1990 19:52:48.080628 RPST = 0x0
1991 19:52:48.083418 RD_PRE = 0x0
1992 19:52:48.083919 WR_PRE = 0x1
1993 19:52:48.086734 WR_PST = 0x0
1994 19:52:48.090144 DBI_WR = 0x0
1995 19:52:48.090655 DBI_RD = 0x0
1996 19:52:48.093661 OTF = 0x1
1997 19:52:48.096908 ===================================
1998 19:52:48.100275 ===================================
1999 19:52:48.100801 ANA top config
2000 19:52:48.103213 ===================================
2001 19:52:48.107035 DLL_ASYNC_EN = 0
2002 19:52:48.107545 ALL_SLAVE_EN = 0
2003 19:52:48.110144 NEW_RANK_MODE = 1
2004 19:52:48.113390 DLL_IDLE_MODE = 1
2005 19:52:48.116506 LP45_APHY_COMB_EN = 1
2006 19:52:48.119920 TX_ODT_DIS = 1
2007 19:52:48.120369 NEW_8X_MODE = 1
2008 19:52:48.123208 ===================================
2009 19:52:48.126715 ===================================
2010 19:52:48.129893 data_rate = 2400
2011 19:52:48.133241 CKR = 1
2012 19:52:48.136839 DQ_P2S_RATIO = 8
2013 19:52:48.140428 ===================================
2014 19:52:48.143684 CA_P2S_RATIO = 8
2015 19:52:48.144246 DQ_CA_OPEN = 0
2016 19:52:48.147021 DQ_SEMI_OPEN = 0
2017 19:52:48.150433 CA_SEMI_OPEN = 0
2018 19:52:48.153760 CA_FULL_RATE = 0
2019 19:52:48.156872 DQ_CKDIV4_EN = 0
2020 19:52:48.160414 CA_CKDIV4_EN = 0
2021 19:52:48.160937 CA_PREDIV_EN = 0
2022 19:52:48.163579 PH8_DLY = 17
2023 19:52:48.166979 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2024 19:52:48.170030 DQ_AAMCK_DIV = 4
2025 19:52:48.173480 CA_AAMCK_DIV = 4
2026 19:52:48.176904 CA_ADMCK_DIV = 4
2027 19:52:48.177420 DQ_TRACK_CA_EN = 0
2028 19:52:48.179863 CA_PICK = 1200
2029 19:52:48.183520 CA_MCKIO = 1200
2030 19:52:48.186693 MCKIO_SEMI = 0
2031 19:52:48.190002 PLL_FREQ = 2366
2032 19:52:48.193540 DQ_UI_PI_RATIO = 32
2033 19:52:48.196950 CA_UI_PI_RATIO = 0
2034 19:52:48.200545 ===================================
2035 19:52:48.203654 ===================================
2036 19:52:48.204170 memory_type:LPDDR4
2037 19:52:48.207090 GP_NUM : 10
2038 19:52:48.210163 SRAM_EN : 1
2039 19:52:48.210676 MD32_EN : 0
2040 19:52:48.213455 ===================================
2041 19:52:48.216689 [ANA_INIT] >>>>>>>>>>>>>>
2042 19:52:48.220378 <<<<<< [CONFIGURE PHASE]: ANA_TX
2043 19:52:48.223593 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2044 19:52:48.226783 ===================================
2045 19:52:48.230202 data_rate = 2400,PCW = 0X5b00
2046 19:52:48.233708 ===================================
2047 19:52:48.236803 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2048 19:52:48.240279 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2049 19:52:48.247464 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2050 19:52:48.250717 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2051 19:52:48.253553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2052 19:52:48.257077 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2053 19:52:48.260537 [ANA_INIT] flow start
2054 19:52:48.263568 [ANA_INIT] PLL >>>>>>>>
2055 19:52:48.264077 [ANA_INIT] PLL <<<<<<<<
2056 19:52:48.266991 [ANA_INIT] MIDPI >>>>>>>>
2057 19:52:48.269949 [ANA_INIT] MIDPI <<<<<<<<
2058 19:52:48.270327 [ANA_INIT] DLL >>>>>>>>
2059 19:52:48.273364 [ANA_INIT] DLL <<<<<<<<
2060 19:52:48.277162 [ANA_INIT] flow end
2061 19:52:48.280260 ============ LP4 DIFF to SE enter ============
2062 19:52:48.283632 ============ LP4 DIFF to SE exit ============
2063 19:52:48.287034 [ANA_INIT] <<<<<<<<<<<<<
2064 19:52:48.290357 [Flow] Enable top DCM control >>>>>
2065 19:52:48.293341 [Flow] Enable top DCM control <<<<<
2066 19:52:48.296460 Enable DLL master slave shuffle
2067 19:52:48.300092 ==============================================================
2068 19:52:48.303855 Gating Mode config
2069 19:52:48.309714 ==============================================================
2070 19:52:48.310184 Config description:
2071 19:52:48.320120 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2072 19:52:48.326723 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2073 19:52:48.329952 SELPH_MODE 0: By rank 1: By Phase
2074 19:52:48.337138 ==============================================================
2075 19:52:48.339870 GAT_TRACK_EN = 1
2076 19:52:48.343620 RX_GATING_MODE = 2
2077 19:52:48.346794 RX_GATING_TRACK_MODE = 2
2078 19:52:48.350054 SELPH_MODE = 1
2079 19:52:48.353155 PICG_EARLY_EN = 1
2080 19:52:48.356823 VALID_LAT_VALUE = 1
2081 19:52:48.359869 ==============================================================
2082 19:52:48.363611 Enter into Gating configuration >>>>
2083 19:52:48.366904 Exit from Gating configuration <<<<
2084 19:52:48.369828 Enter into DVFS_PRE_config >>>>>
2085 19:52:48.380345 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2086 19:52:48.383680 Exit from DVFS_PRE_config <<<<<
2087 19:52:48.386970 Enter into PICG configuration >>>>
2088 19:52:48.390429 Exit from PICG configuration <<<<
2089 19:52:48.393684 [RX_INPUT] configuration >>>>>
2090 19:52:48.396576 [RX_INPUT] configuration <<<<<
2091 19:52:48.403443 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2092 19:52:48.406702 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2093 19:52:48.412938 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2094 19:52:48.419713 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2095 19:52:48.426774 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2096 19:52:48.433370 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2097 19:52:48.436860 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2098 19:52:48.439965 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2099 19:52:48.443341 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2100 19:52:48.449983 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2101 19:52:48.452987 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2102 19:52:48.456674 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2103 19:52:48.460723 ===================================
2104 19:52:48.463223 LPDDR4 DRAM CONFIGURATION
2105 19:52:48.466448 ===================================
2106 19:52:48.466983 EX_ROW_EN[0] = 0x0
2107 19:52:48.469698 EX_ROW_EN[1] = 0x0
2108 19:52:48.470151 LP4Y_EN = 0x0
2109 19:52:48.473043 WORK_FSP = 0x0
2110 19:52:48.473567 WL = 0x4
2111 19:52:48.476484 RL = 0x4
2112 19:52:48.480247 BL = 0x2
2113 19:52:48.480822 RPST = 0x0
2114 19:52:48.483469 RD_PRE = 0x0
2115 19:52:48.484021 WR_PRE = 0x1
2116 19:52:48.486495 WR_PST = 0x0
2117 19:52:48.486951 DBI_WR = 0x0
2118 19:52:48.489786 DBI_RD = 0x0
2119 19:52:48.490194 OTF = 0x1
2120 19:52:48.493355 ===================================
2121 19:52:48.496239 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2122 19:52:48.502797 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2123 19:52:48.506895 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 19:52:48.510195 ===================================
2125 19:52:48.513333 LPDDR4 DRAM CONFIGURATION
2126 19:52:48.516864 ===================================
2127 19:52:48.517384 EX_ROW_EN[0] = 0x10
2128 19:52:48.520626 EX_ROW_EN[1] = 0x0
2129 19:52:48.521133 LP4Y_EN = 0x0
2130 19:52:48.523411 WORK_FSP = 0x0
2131 19:52:48.523971 WL = 0x4
2132 19:52:48.526836 RL = 0x4
2133 19:52:48.527351 BL = 0x2
2134 19:52:48.530201 RPST = 0x0
2135 19:52:48.530715 RD_PRE = 0x0
2136 19:52:48.533015 WR_PRE = 0x1
2137 19:52:48.533425 WR_PST = 0x0
2138 19:52:48.536556 DBI_WR = 0x0
2139 19:52:48.537041 DBI_RD = 0x0
2140 19:52:48.540075 OTF = 0x1
2141 19:52:48.543499 ===================================
2142 19:52:48.550211 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2143 19:52:48.550730 ==
2144 19:52:48.553297 Dram Type= 6, Freq= 0, CH_0, rank 0
2145 19:52:48.556954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2146 19:52:48.557473 ==
2147 19:52:48.560093 [Duty_Offset_Calibration]
2148 19:52:48.560526 B0:0 B1:2 CA:1
2149 19:52:48.560858
2150 19:52:48.570859 [DutyScan_Calibration_Flow] k_type=0
2151 19:52:48.573494
2152 19:52:48.573581 ==CLK 0==
2153 19:52:48.576604 Final CLK duty delay cell = 0
2154 19:52:48.580279 [0] MAX Duty = 5093%(X100), DQS PI = 12
2155 19:52:48.583189 [0] MIN Duty = 4938%(X100), DQS PI = 54
2156 19:52:48.583382 [0] AVG Duty = 5015%(X100)
2157 19:52:48.586749
2158 19:52:48.590430 CH0 CLK Duty spec in!! Max-Min= 155%
2159 19:52:48.593948 [DutyScan_Calibration_Flow] ====Done====
2160 19:52:48.594126
2161 19:52:48.596816 [DutyScan_Calibration_Flow] k_type=1
2162 19:52:48.612826
2163 19:52:48.613076 ==DQS 0 ==
2164 19:52:48.616616 Final DQS duty delay cell = 0
2165 19:52:48.619812 [0] MAX Duty = 5125%(X100), DQS PI = 30
2166 19:52:48.622952 [0] MIN Duty = 5031%(X100), DQS PI = 6
2167 19:52:48.623280 [0] AVG Duty = 5078%(X100)
2168 19:52:48.626175
2169 19:52:48.626502 ==DQS 1 ==
2170 19:52:48.630046 Final DQS duty delay cell = 0
2171 19:52:48.633345 [0] MAX Duty = 5062%(X100), DQS PI = 58
2172 19:52:48.636781 [0] MIN Duty = 4906%(X100), DQS PI = 16
2173 19:52:48.637266 [0] AVG Duty = 4984%(X100)
2174 19:52:48.640134
2175 19:52:48.643018 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2176 19:52:48.643642
2177 19:52:48.646662 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2178 19:52:48.649666 [DutyScan_Calibration_Flow] ====Done====
2179 19:52:48.650125
2180 19:52:48.652872 [DutyScan_Calibration_Flow] k_type=3
2181 19:52:48.670275
2182 19:52:48.670827 ==DQM 0 ==
2183 19:52:48.673555 Final DQM duty delay cell = 0
2184 19:52:48.677145 [0] MAX Duty = 5156%(X100), DQS PI = 20
2185 19:52:48.680288 [0] MIN Duty = 4969%(X100), DQS PI = 54
2186 19:52:48.683762 [0] AVG Duty = 5062%(X100)
2187 19:52:48.684363
2188 19:52:48.684733 ==DQM 1 ==
2189 19:52:48.686833 Final DQM duty delay cell = 4
2190 19:52:48.690082 [4] MAX Duty = 5187%(X100), DQS PI = 52
2191 19:52:48.694039 [4] MIN Duty = 5000%(X100), DQS PI = 16
2192 19:52:48.696965 [4] AVG Duty = 5093%(X100)
2193 19:52:48.697527
2194 19:52:48.700053 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2195 19:52:48.700533
2196 19:52:48.703954 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2197 19:52:48.706650 [DutyScan_Calibration_Flow] ====Done====
2198 19:52:48.707202
2199 19:52:48.710094 [DutyScan_Calibration_Flow] k_type=2
2200 19:52:48.725138
2201 19:52:48.725709 ==DQ 0 ==
2202 19:52:48.728677 Final DQ duty delay cell = -4
2203 19:52:48.731817 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2204 19:52:48.735103 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2205 19:52:48.738709 [-4] AVG Duty = 4937%(X100)
2206 19:52:48.739264
2207 19:52:48.739628 ==DQ 1 ==
2208 19:52:48.742237 Final DQ duty delay cell = -4
2209 19:52:48.745090 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2210 19:52:48.748922 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2211 19:52:48.751943 [-4] AVG Duty = 4984%(X100)
2212 19:52:48.752550
2213 19:52:48.755335 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2214 19:52:48.755907
2215 19:52:48.758815 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2216 19:52:48.762064 [DutyScan_Calibration_Flow] ====Done====
2217 19:52:48.762621 ==
2218 19:52:48.765283 Dram Type= 6, Freq= 0, CH_1, rank 0
2219 19:52:48.768583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2220 19:52:48.769065 ==
2221 19:52:48.771883 [Duty_Offset_Calibration]
2222 19:52:48.772462 B0:0 B1:4 CA:-5
2223 19:52:48.772828
2224 19:52:48.775372 [DutyScan_Calibration_Flow] k_type=0
2225 19:52:48.785785
2226 19:52:48.786323 ==CLK 0==
2227 19:52:48.788751 Final CLK duty delay cell = 0
2228 19:52:48.792599 [0] MAX Duty = 5094%(X100), DQS PI = 24
2229 19:52:48.796291 [0] MIN Duty = 4907%(X100), DQS PI = 44
2230 19:52:48.798917 [0] AVG Duty = 5000%(X100)
2231 19:52:48.799370
2232 19:52:48.802694 CH1 CLK Duty spec in!! Max-Min= 187%
2233 19:52:48.805793 [DutyScan_Calibration_Flow] ====Done====
2234 19:52:48.806396
2235 19:52:48.809292 [DutyScan_Calibration_Flow] k_type=1
2236 19:52:48.824368
2237 19:52:48.824909 ==DQS 0 ==
2238 19:52:48.827855 Final DQS duty delay cell = 0
2239 19:52:48.830856 [0] MAX Duty = 5125%(X100), DQS PI = 16
2240 19:52:48.834147 [0] MIN Duty = 4875%(X100), DQS PI = 40
2241 19:52:48.834560 [0] AVG Duty = 5000%(X100)
2242 19:52:48.837566
2243 19:52:48.837971 ==DQS 1 ==
2244 19:52:48.840915 Final DQS duty delay cell = -4
2245 19:52:48.844598 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2246 19:52:48.847618 [-4] MIN Duty = 4907%(X100), DQS PI = 42
2247 19:52:48.850928 [-4] AVG Duty = 4953%(X100)
2248 19:52:48.851438
2249 19:52:48.854352 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2250 19:52:48.854869
2251 19:52:48.857594 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2252 19:52:48.860565 [DutyScan_Calibration_Flow] ====Done====
2253 19:52:48.861002
2254 19:52:48.864150 [DutyScan_Calibration_Flow] k_type=3
2255 19:52:48.879387
2256 19:52:48.879953 ==DQM 0 ==
2257 19:52:48.882769 Final DQM duty delay cell = -4
2258 19:52:48.886300 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2259 19:52:48.889210 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2260 19:52:48.892894 [-4] AVG Duty = 4969%(X100)
2261 19:52:48.893400
2262 19:52:48.893730 ==DQM 1 ==
2263 19:52:48.896091 Final DQM duty delay cell = -4
2264 19:52:48.899809 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2265 19:52:48.902870 [-4] MIN Duty = 4907%(X100), DQS PI = 60
2266 19:52:48.905971 [-4] AVG Duty = 4984%(X100)
2267 19:52:48.906478
2268 19:52:48.909116 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2269 19:52:48.909641
2270 19:52:48.912794 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2271 19:52:48.916013 [DutyScan_Calibration_Flow] ====Done====
2272 19:52:48.916449
2273 19:52:48.919044 [DutyScan_Calibration_Flow] k_type=2
2274 19:52:48.936561
2275 19:52:48.937083 ==DQ 0 ==
2276 19:52:48.939658 Final DQ duty delay cell = 0
2277 19:52:48.943331 [0] MAX Duty = 5062%(X100), DQS PI = 0
2278 19:52:48.946450 [0] MIN Duty = 4969%(X100), DQS PI = 42
2279 19:52:48.947007 [0] AVG Duty = 5015%(X100)
2280 19:52:48.947379
2281 19:52:48.949541 ==DQ 1 ==
2282 19:52:48.953320 Final DQ duty delay cell = 0
2283 19:52:48.956376 [0] MAX Duty = 5000%(X100), DQS PI = 6
2284 19:52:48.959448 [0] MIN Duty = 4907%(X100), DQS PI = 0
2285 19:52:48.959856 [0] AVG Duty = 4953%(X100)
2286 19:52:48.960208
2287 19:52:48.963133 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2288 19:52:48.963642
2289 19:52:48.966130 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2290 19:52:48.969590 [DutyScan_Calibration_Flow] ====Done====
2291 19:52:48.974999 nWR fixed to 30
2292 19:52:48.978911 [ModeRegInit_LP4] CH0 RK0
2293 19:52:48.979422 [ModeRegInit_LP4] CH0 RK1
2294 19:52:48.981971 [ModeRegInit_LP4] CH1 RK0
2295 19:52:48.985455 [ModeRegInit_LP4] CH1 RK1
2296 19:52:48.985963 match AC timing 6
2297 19:52:48.992321 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2298 19:52:48.994840 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2299 19:52:48.998138 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2300 19:52:49.004956 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2301 19:52:49.008602 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2302 19:52:49.009007 ==
2303 19:52:49.011603 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 19:52:49.015047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2305 19:52:49.015518 ==
2306 19:52:49.021714 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2307 19:52:49.028598 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2308 19:52:49.035730 [CA 0] Center 39 (9~70) winsize 62
2309 19:52:49.039317 [CA 1] Center 39 (9~70) winsize 62
2310 19:52:49.042520 [CA 2] Center 36 (5~67) winsize 63
2311 19:52:49.046093 [CA 3] Center 35 (4~66) winsize 63
2312 19:52:49.048888 [CA 4] Center 34 (3~65) winsize 63
2313 19:52:49.052544 [CA 5] Center 33 (3~64) winsize 62
2314 19:52:49.053057
2315 19:52:49.055881 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2316 19:52:49.056437
2317 19:52:49.059262 [CATrainingPosCal] consider 1 rank data
2318 19:52:49.062494 u2DelayCellTimex100 = 270/100 ps
2319 19:52:49.066232 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2320 19:52:49.068764 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2321 19:52:49.075468 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2322 19:52:49.078864 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2323 19:52:49.082414 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2324 19:52:49.086181 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2325 19:52:49.086752
2326 19:52:49.088874 CA PerBit enable=1, Macro0, CA PI delay=33
2327 19:52:49.089282
2328 19:52:49.092702 [CBTSetCACLKResult] CA Dly = 33
2329 19:52:49.093212 CS Dly: 7 (0~38)
2330 19:52:49.096419 ==
2331 19:52:49.096922 Dram Type= 6, Freq= 0, CH_0, rank 1
2332 19:52:49.102371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2333 19:52:49.102876 ==
2334 19:52:49.105953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2335 19:52:49.112138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2336 19:52:49.121543 [CA 0] Center 39 (8~70) winsize 63
2337 19:52:49.124587 [CA 1] Center 39 (8~70) winsize 63
2338 19:52:49.128206 [CA 2] Center 35 (5~66) winsize 62
2339 19:52:49.131391 [CA 3] Center 35 (4~66) winsize 63
2340 19:52:49.134763 [CA 4] Center 33 (3~64) winsize 62
2341 19:52:49.138316 [CA 5] Center 34 (3~65) winsize 63
2342 19:52:49.138822
2343 19:52:49.141047 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2344 19:52:49.141451
2345 19:52:49.144867 [CATrainingPosCal] consider 2 rank data
2346 19:52:49.148053 u2DelayCellTimex100 = 270/100 ps
2347 19:52:49.151098 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2348 19:52:49.155018 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2349 19:52:49.161253 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2350 19:52:49.164775 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2351 19:52:49.167658 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2352 19:52:49.170799 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2353 19:52:49.171204
2354 19:52:49.174467 CA PerBit enable=1, Macro0, CA PI delay=33
2355 19:52:49.174976
2356 19:52:49.177614 [CBTSetCACLKResult] CA Dly = 33
2357 19:52:49.178018 CS Dly: 7 (0~39)
2358 19:52:49.178359
2359 19:52:49.181253 ----->DramcWriteLeveling(PI) begin...
2360 19:52:49.184497 ==
2361 19:52:49.185008 Dram Type= 6, Freq= 0, CH_0, rank 0
2362 19:52:49.191317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2363 19:52:49.191833 ==
2364 19:52:49.194721 Write leveling (Byte 0): 26 => 26
2365 19:52:49.197742 Write leveling (Byte 1): 27 => 27
2366 19:52:49.201364 DramcWriteLeveling(PI) end<-----
2367 19:52:49.201875
2368 19:52:49.202206 ==
2369 19:52:49.204569 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 19:52:49.207726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2371 19:52:49.208137 ==
2372 19:52:49.211264 [Gating] SW mode calibration
2373 19:52:49.218170 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2374 19:52:49.221110 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2375 19:52:49.228113 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2376 19:52:49.231775 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2377 19:52:49.234815 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2378 19:52:49.241287 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2379 19:52:49.244838 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2380 19:52:49.248052 0 11 20 | B1->B0 | 2e2e 2a2a | 0 0 | (1 0) (1 0)
2381 19:52:49.255073 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2382 19:52:49.257707 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2383 19:52:49.260998 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2384 19:52:49.268413 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2385 19:52:49.272028 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2386 19:52:49.274577 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2387 19:52:49.281526 0 12 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2388 19:52:49.284727 0 12 20 | B1->B0 | 3636 4040 | 0 0 | (0 0) (0 0)
2389 19:52:49.287800 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2390 19:52:49.294655 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2391 19:52:49.297653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2392 19:52:49.301468 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2393 19:52:49.308095 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 19:52:49.311139 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 19:52:49.314320 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2396 19:52:49.317829 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2397 19:52:49.324216 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2398 19:52:49.327800 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2399 19:52:49.331050 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2400 19:52:49.337966 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 19:52:49.341085 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 19:52:49.344409 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 19:52:49.351186 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 19:52:49.354497 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 19:52:49.357789 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 19:52:49.364705 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 19:52:49.368082 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 19:52:49.371057 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 19:52:49.378458 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 19:52:49.381139 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 19:52:49.384856 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 19:52:49.391339 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2413 19:52:49.394983 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2414 19:52:49.398200 Total UI for P1: 0, mck2ui 16
2415 19:52:49.401724 best dqsien dly found for B0: ( 0, 15, 20)
2416 19:52:49.404614 Total UI for P1: 0, mck2ui 16
2417 19:52:49.408216 best dqsien dly found for B1: ( 0, 15, 20)
2418 19:52:49.411026 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2419 19:52:49.414461 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2420 19:52:49.414923
2421 19:52:49.417757 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2422 19:52:49.421681 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2423 19:52:49.424484 [Gating] SW calibration Done
2424 19:52:49.424892 ==
2425 19:52:49.427721 Dram Type= 6, Freq= 0, CH_0, rank 0
2426 19:52:49.431360 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2427 19:52:49.431885 ==
2428 19:52:49.434621 RX Vref Scan: 0
2429 19:52:49.435153
2430 19:52:49.437865 RX Vref 0 -> 0, step: 1
2431 19:52:49.438399
2432 19:52:49.438739 RX Delay -40 -> 252, step: 8
2433 19:52:49.444322 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2434 19:52:49.448121 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2435 19:52:49.451243 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2436 19:52:49.454446 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2437 19:52:49.457608 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2438 19:52:49.464549 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2439 19:52:49.468256 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2440 19:52:49.471177 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2441 19:52:49.474801 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2442 19:52:49.478109 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2443 19:52:49.484790 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2444 19:52:49.487974 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2445 19:52:49.491581 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2446 19:52:49.495037 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2447 19:52:49.498162 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2448 19:52:49.504657 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2449 19:52:49.505260 ==
2450 19:52:49.508040 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 19:52:49.511348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2452 19:52:49.511910 ==
2453 19:52:49.512346 DQS Delay:
2454 19:52:49.514385 DQS0 = 0, DQS1 = 0
2455 19:52:49.514845 DQM Delay:
2456 19:52:49.518018 DQM0 = 115, DQM1 = 105
2457 19:52:49.518578 DQ Delay:
2458 19:52:49.521388 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2459 19:52:49.524718 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2460 19:52:49.527759 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2461 19:52:49.531560 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2462 19:52:49.532144
2463 19:52:49.532580
2464 19:52:49.533001 ==
2465 19:52:49.535408 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 19:52:49.541027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2467 19:52:49.541493 ==
2468 19:52:49.541849
2469 19:52:49.542157
2470 19:52:49.542453 TX Vref Scan disable
2471 19:52:49.544890 == TX Byte 0 ==
2472 19:52:49.548446 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2473 19:52:49.551417 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2474 19:52:49.554969 == TX Byte 1 ==
2475 19:52:49.557849 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2476 19:52:49.561574 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2477 19:52:49.564955 ==
2478 19:52:49.568107 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 19:52:49.571090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2480 19:52:49.571530 ==
2481 19:52:49.582342 TX Vref=22, minBit 5, minWin=25, winSum=411
2482 19:52:49.585979 TX Vref=24, minBit 10, minWin=25, winSum=417
2483 19:52:49.589366 TX Vref=26, minBit 1, minWin=26, winSum=423
2484 19:52:49.592786 TX Vref=28, minBit 3, minWin=26, winSum=428
2485 19:52:49.595779 TX Vref=30, minBit 5, minWin=26, winSum=432
2486 19:52:49.599557 TX Vref=32, minBit 3, minWin=26, winSum=430
2487 19:52:49.605935 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 30
2488 19:52:49.606498
2489 19:52:49.609211 Final TX Range 1 Vref 30
2490 19:52:49.609770
2491 19:52:49.610141 ==
2492 19:52:49.613026 Dram Type= 6, Freq= 0, CH_0, rank 0
2493 19:52:49.615862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2494 19:52:49.616375 ==
2495 19:52:49.616749
2496 19:52:49.619220
2497 19:52:49.619767 TX Vref Scan disable
2498 19:52:49.622531 == TX Byte 0 ==
2499 19:52:49.626103 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2500 19:52:49.629036 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2501 19:52:49.632466 == TX Byte 1 ==
2502 19:52:49.635849 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2503 19:52:49.638944 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2504 19:52:49.639376
2505 19:52:49.642651 [DATLAT]
2506 19:52:49.643160 Freq=1200, CH0 RK0
2507 19:52:49.643500
2508 19:52:49.645421 DATLAT Default: 0xd
2509 19:52:49.645838 0, 0xFFFF, sum = 0
2510 19:52:49.649175 1, 0xFFFF, sum = 0
2511 19:52:49.649690 2, 0xFFFF, sum = 0
2512 19:52:49.652287 3, 0xFFFF, sum = 0
2513 19:52:49.652728 4, 0xFFFF, sum = 0
2514 19:52:49.655922 5, 0xFFFF, sum = 0
2515 19:52:49.656507 6, 0xFFFF, sum = 0
2516 19:52:49.659246 7, 0xFFFF, sum = 0
2517 19:52:49.659775 8, 0xFFFF, sum = 0
2518 19:52:49.662532 9, 0xFFFF, sum = 0
2519 19:52:49.662967 10, 0xFFFF, sum = 0
2520 19:52:49.665637 11, 0x0, sum = 1
2521 19:52:49.666074 12, 0x0, sum = 2
2522 19:52:49.669055 13, 0x0, sum = 3
2523 19:52:49.669492 14, 0x0, sum = 4
2524 19:52:49.672444 best_step = 12
2525 19:52:49.672874
2526 19:52:49.673328 ==
2527 19:52:49.675937 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 19:52:49.679246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2529 19:52:49.679774 ==
2530 19:52:49.682789 RX Vref Scan: 1
2531 19:52:49.683312
2532 19:52:49.683760 Set Vref Range= 32 -> 127
2533 19:52:49.684213
2534 19:52:49.685784 RX Vref 32 -> 127, step: 1
2535 19:52:49.686214
2536 19:52:49.688983 RX Delay -21 -> 252, step: 4
2537 19:52:49.689415
2538 19:52:49.692835 Set Vref, RX VrefLevel [Byte0]: 32
2539 19:52:49.696127 [Byte1]: 32
2540 19:52:49.696699
2541 19:52:49.699485 Set Vref, RX VrefLevel [Byte0]: 33
2542 19:52:49.702825 [Byte1]: 33
2543 19:52:49.706862
2544 19:52:49.707381 Set Vref, RX VrefLevel [Byte0]: 34
2545 19:52:49.710142 [Byte1]: 34
2546 19:52:49.714889
2547 19:52:49.715409 Set Vref, RX VrefLevel [Byte0]: 35
2548 19:52:49.718019 [Byte1]: 35
2549 19:52:49.722616
2550 19:52:49.723139 Set Vref, RX VrefLevel [Byte0]: 36
2551 19:52:49.726244 [Byte1]: 36
2552 19:52:49.730232
2553 19:52:49.730724 Set Vref, RX VrefLevel [Byte0]: 37
2554 19:52:49.733743 [Byte1]: 37
2555 19:52:49.738614
2556 19:52:49.739130 Set Vref, RX VrefLevel [Byte0]: 38
2557 19:52:49.741960 [Byte1]: 38
2558 19:52:49.746531
2559 19:52:49.747091 Set Vref, RX VrefLevel [Byte0]: 39
2560 19:52:49.749635 [Byte1]: 39
2561 19:52:49.754109
2562 19:52:49.754525 Set Vref, RX VrefLevel [Byte0]: 40
2563 19:52:49.757744 [Byte1]: 40
2564 19:52:49.762320
2565 19:52:49.762836 Set Vref, RX VrefLevel [Byte0]: 41
2566 19:52:49.765666 [Byte1]: 41
2567 19:52:49.770073
2568 19:52:49.770548 Set Vref, RX VrefLevel [Byte0]: 42
2569 19:52:49.773247 [Byte1]: 42
2570 19:52:49.777877
2571 19:52:49.778307 Set Vref, RX VrefLevel [Byte0]: 43
2572 19:52:49.781685 [Byte1]: 43
2573 19:52:49.785852
2574 19:52:49.786378 Set Vref, RX VrefLevel [Byte0]: 44
2575 19:52:49.789115 [Byte1]: 44
2576 19:52:49.793861
2577 19:52:49.794379 Set Vref, RX VrefLevel [Byte0]: 45
2578 19:52:49.797303 [Byte1]: 45
2579 19:52:49.801676
2580 19:52:49.802181 Set Vref, RX VrefLevel [Byte0]: 46
2581 19:52:49.805113 [Byte1]: 46
2582 19:52:49.809688
2583 19:52:49.810207 Set Vref, RX VrefLevel [Byte0]: 47
2584 19:52:49.812907 [Byte1]: 47
2585 19:52:49.817652
2586 19:52:49.818211 Set Vref, RX VrefLevel [Byte0]: 48
2587 19:52:49.820685 [Byte1]: 48
2588 19:52:49.825821
2589 19:52:49.826341 Set Vref, RX VrefLevel [Byte0]: 49
2590 19:52:49.828875 [Byte1]: 49
2591 19:52:49.833727
2592 19:52:49.834247 Set Vref, RX VrefLevel [Byte0]: 50
2593 19:52:49.836420 [Byte1]: 50
2594 19:52:49.841600
2595 19:52:49.842122 Set Vref, RX VrefLevel [Byte0]: 51
2596 19:52:49.844745 [Byte1]: 51
2597 19:52:49.849484
2598 19:52:49.850009 Set Vref, RX VrefLevel [Byte0]: 52
2599 19:52:49.852534 [Byte1]: 52
2600 19:52:49.857155
2601 19:52:49.857676 Set Vref, RX VrefLevel [Byte0]: 53
2602 19:52:49.860509 [Byte1]: 53
2603 19:52:49.865165
2604 19:52:49.865594 Set Vref, RX VrefLevel [Byte0]: 54
2605 19:52:49.868165 [Byte1]: 54
2606 19:52:49.872830
2607 19:52:49.873255 Set Vref, RX VrefLevel [Byte0]: 55
2608 19:52:49.876932 [Byte1]: 55
2609 19:52:49.881126
2610 19:52:49.881644 Set Vref, RX VrefLevel [Byte0]: 56
2611 19:52:49.884645 [Byte1]: 56
2612 19:52:49.889014
2613 19:52:49.889537 Set Vref, RX VrefLevel [Byte0]: 57
2614 19:52:49.892143 [Byte1]: 57
2615 19:52:49.897134
2616 19:52:49.897661 Set Vref, RX VrefLevel [Byte0]: 58
2617 19:52:49.900020 [Byte1]: 58
2618 19:52:49.904791
2619 19:52:49.905217 Set Vref, RX VrefLevel [Byte0]: 59
2620 19:52:49.908151 [Byte1]: 59
2621 19:52:49.913140
2622 19:52:49.913660 Set Vref, RX VrefLevel [Byte0]: 60
2623 19:52:49.916009 [Byte1]: 60
2624 19:52:49.920214
2625 19:52:49.920635 Set Vref, RX VrefLevel [Byte0]: 61
2626 19:52:49.924153 [Byte1]: 61
2627 19:52:49.928352
2628 19:52:49.928863 Set Vref, RX VrefLevel [Byte0]: 62
2629 19:52:49.931506 [Byte1]: 62
2630 19:52:49.936692
2631 19:52:49.937209 Set Vref, RX VrefLevel [Byte0]: 63
2632 19:52:49.939634 [Byte1]: 63
2633 19:52:49.944127
2634 19:52:49.944575 Set Vref, RX VrefLevel [Byte0]: 64
2635 19:52:49.947265 [Byte1]: 64
2636 19:52:49.952441
2637 19:52:49.952964 Final RX Vref Byte 0 = 51 to rank0
2638 19:52:49.955587 Final RX Vref Byte 1 = 48 to rank0
2639 19:52:49.958939 Final RX Vref Byte 0 = 51 to rank1
2640 19:52:49.962513 Final RX Vref Byte 1 = 48 to rank1==
2641 19:52:49.965593 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 19:52:49.968882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2643 19:52:49.972116 ==
2644 19:52:49.972578 DQS Delay:
2645 19:52:49.973020 DQS0 = 0, DQS1 = 0
2646 19:52:49.976140 DQM Delay:
2647 19:52:49.976710 DQM0 = 114, DQM1 = 105
2648 19:52:49.979213 DQ Delay:
2649 19:52:49.982671 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2650 19:52:49.985425 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2651 19:52:49.989471 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2652 19:52:49.992719 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2653 19:52:49.993239
2654 19:52:49.993578
2655 19:52:49.998974 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2656 19:52:50.002588 CH0 RK0: MR19=404, MR18=606
2657 19:52:50.009270 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
2658 19:52:50.009790
2659 19:52:50.012874 ----->DramcWriteLeveling(PI) begin...
2660 19:52:50.013398 ==
2661 19:52:50.015505 Dram Type= 6, Freq= 0, CH_0, rank 1
2662 19:52:50.019155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2663 19:52:50.019680 ==
2664 19:52:50.022416 Write leveling (Byte 0): 28 => 28
2665 19:52:50.025684 Write leveling (Byte 1): 24 => 24
2666 19:52:50.029242 DramcWriteLeveling(PI) end<-----
2667 19:52:50.029760
2668 19:52:50.030167 ==
2669 19:52:50.032249 Dram Type= 6, Freq= 0, CH_0, rank 1
2670 19:52:50.035541 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2671 19:52:50.039016 ==
2672 19:52:50.039538 [Gating] SW mode calibration
2673 19:52:50.048762 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2674 19:52:50.052283 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2675 19:52:50.055580 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2676 19:52:50.061977 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2677 19:52:50.065794 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2678 19:52:50.069155 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2679 19:52:50.075937 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2680 19:52:50.078794 0 11 20 | B1->B0 | 2e2e 2323 | 1 1 | (1 0) (1 0)
2681 19:52:50.082212 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2682 19:52:50.089344 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2683 19:52:50.092335 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2684 19:52:50.095983 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2685 19:52:50.102527 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2686 19:52:50.105797 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2687 19:52:50.108704 0 12 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2688 19:52:50.115204 0 12 20 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
2689 19:52:50.118819 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2690 19:52:50.122154 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2691 19:52:50.125696 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2692 19:52:50.132348 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2693 19:52:50.135668 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2694 19:52:50.138956 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2695 19:52:50.145369 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2696 19:52:50.148866 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2697 19:52:50.151957 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2698 19:52:50.158964 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2699 19:52:50.161892 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2700 19:52:50.165597 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2701 19:52:50.171980 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2702 19:52:50.175618 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2703 19:52:50.178671 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2704 19:52:50.185730 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2705 19:52:50.189390 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 19:52:50.192278 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 19:52:50.199619 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 19:52:50.202128 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 19:52:50.205717 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 19:52:50.208966 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 19:52:50.215679 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2712 19:52:50.219362 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2713 19:52:50.223125 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2714 19:52:50.225933 Total UI for P1: 0, mck2ui 16
2715 19:52:50.228943 best dqsien dly found for B0: ( 0, 15, 18)
2716 19:52:50.232667 Total UI for P1: 0, mck2ui 16
2717 19:52:50.235690 best dqsien dly found for B1: ( 0, 15, 20)
2718 19:52:50.239119 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2719 19:52:50.242651 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2720 19:52:50.246090
2721 19:52:50.249161 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2722 19:52:50.252320 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2723 19:52:50.255918 [Gating] SW calibration Done
2724 19:52:50.256490 ==
2725 19:52:50.259092 Dram Type= 6, Freq= 0, CH_0, rank 1
2726 19:52:50.262120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2727 19:52:50.262663 ==
2728 19:52:50.263107 RX Vref Scan: 0
2729 19:52:50.263525
2730 19:52:50.265687 RX Vref 0 -> 0, step: 1
2731 19:52:50.266215
2732 19:52:50.268946 RX Delay -40 -> 252, step: 8
2733 19:52:50.272314 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2734 19:52:50.275485 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2735 19:52:50.282429 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2736 19:52:50.285607 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2737 19:52:50.288641 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2738 19:52:50.292101 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2739 19:52:50.295358 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2740 19:52:50.302005 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2741 19:52:50.305355 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2742 19:52:50.308634 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2743 19:52:50.311960 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2744 19:52:50.315194 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2745 19:52:50.318731 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2746 19:52:50.325264 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2747 19:52:50.328325 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2748 19:52:50.331483 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2749 19:52:50.331614 ==
2750 19:52:50.334972 Dram Type= 6, Freq= 0, CH_0, rank 1
2751 19:52:50.338292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2752 19:52:50.341525 ==
2753 19:52:50.341627 DQS Delay:
2754 19:52:50.341708 DQS0 = 0, DQS1 = 0
2755 19:52:50.345033 DQM Delay:
2756 19:52:50.345123 DQM0 = 115, DQM1 = 107
2757 19:52:50.348558 DQ Delay:
2758 19:52:50.351443 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =107
2759 19:52:50.355290 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2760 19:52:50.358344 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2761 19:52:50.361241 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2762 19:52:50.361326
2763 19:52:50.361392
2764 19:52:50.361452 ==
2765 19:52:50.364734 Dram Type= 6, Freq= 0, CH_0, rank 1
2766 19:52:50.367878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2767 19:52:50.367968 ==
2768 19:52:50.368034
2769 19:52:50.368111
2770 19:52:50.371233 TX Vref Scan disable
2771 19:52:50.374703 == TX Byte 0 ==
2772 19:52:50.378034 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2773 19:52:50.381280 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2774 19:52:50.384543 == TX Byte 1 ==
2775 19:52:50.387801 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2776 19:52:50.391202 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2777 19:52:50.391292 ==
2778 19:52:50.394663 Dram Type= 6, Freq= 0, CH_0, rank 1
2779 19:52:50.401334 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2780 19:52:50.401443 ==
2781 19:52:50.411768 TX Vref=22, minBit 8, minWin=24, winSum=419
2782 19:52:50.415099 TX Vref=24, minBit 8, minWin=25, winSum=426
2783 19:52:50.418417 TX Vref=26, minBit 1, minWin=26, winSum=428
2784 19:52:50.421756 TX Vref=28, minBit 8, minWin=26, winSum=434
2785 19:52:50.425185 TX Vref=30, minBit 8, minWin=26, winSum=432
2786 19:52:50.428557 TX Vref=32, minBit 8, minWin=25, winSum=432
2787 19:52:50.435035 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
2788 19:52:50.435118
2789 19:52:50.438449 Final TX Range 1 Vref 28
2790 19:52:50.438531
2791 19:52:50.438597 ==
2792 19:52:50.442591 Dram Type= 6, Freq= 0, CH_0, rank 1
2793 19:52:50.445001 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2794 19:52:50.445083 ==
2795 19:52:50.445148
2796 19:52:50.448546
2797 19:52:50.448627 TX Vref Scan disable
2798 19:52:50.451742 == TX Byte 0 ==
2799 19:52:50.454981 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2800 19:52:50.458577 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2801 19:52:50.461833 == TX Byte 1 ==
2802 19:52:50.465005 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2803 19:52:50.468450 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2804 19:52:50.468531
2805 19:52:50.472067 [DATLAT]
2806 19:52:50.472151 Freq=1200, CH0 RK1
2807 19:52:50.472247
2808 19:52:50.475237 DATLAT Default: 0xc
2809 19:52:50.475318 0, 0xFFFF, sum = 0
2810 19:52:50.478460 1, 0xFFFF, sum = 0
2811 19:52:50.478543 2, 0xFFFF, sum = 0
2812 19:52:50.481769 3, 0xFFFF, sum = 0
2813 19:52:50.481853 4, 0xFFFF, sum = 0
2814 19:52:50.485439 5, 0xFFFF, sum = 0
2815 19:52:50.485525 6, 0xFFFF, sum = 0
2816 19:52:50.488355 7, 0xFFFF, sum = 0
2817 19:52:50.488438 8, 0xFFFF, sum = 0
2818 19:52:50.492092 9, 0xFFFF, sum = 0
2819 19:52:50.495260 10, 0xFFFF, sum = 0
2820 19:52:50.495344 11, 0x0, sum = 1
2821 19:52:50.495411 12, 0x0, sum = 2
2822 19:52:50.498587 13, 0x0, sum = 3
2823 19:52:50.498673 14, 0x0, sum = 4
2824 19:52:50.501907 best_step = 12
2825 19:52:50.501988
2826 19:52:50.502053 ==
2827 19:52:50.505209 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 19:52:50.508491 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2829 19:52:50.508574 ==
2830 19:52:50.511737 RX Vref Scan: 0
2831 19:52:50.511818
2832 19:52:50.511883 RX Vref 0 -> 0, step: 1
2833 19:52:50.511944
2834 19:52:50.515143 RX Delay -21 -> 252, step: 4
2835 19:52:50.522266 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2836 19:52:50.525307 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2837 19:52:50.528990 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2838 19:52:50.531904 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2839 19:52:50.535210 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2840 19:52:50.542028 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2841 19:52:50.545351 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2842 19:52:50.548737 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2843 19:52:50.552094 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2844 19:52:50.556168 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2845 19:52:50.562540 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
2846 19:52:50.565682 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2847 19:52:50.569304 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2848 19:52:50.572329 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2849 19:52:50.575827 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2850 19:52:50.582569 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2851 19:52:50.583031 ==
2852 19:52:50.585721 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 19:52:50.589224 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2854 19:52:50.589641 ==
2855 19:52:50.589973 DQS Delay:
2856 19:52:50.592541 DQS0 = 0, DQS1 = 0
2857 19:52:50.592965 DQM Delay:
2858 19:52:50.595757 DQM0 = 115, DQM1 = 106
2859 19:52:50.596226 DQ Delay:
2860 19:52:50.599031 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2861 19:52:50.602615 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =124
2862 19:52:50.605500 DQ8 =94, DQ9 =90, DQ10 =112, DQ11 =96
2863 19:52:50.608867 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2864 19:52:50.609183
2865 19:52:50.609427
2866 19:52:50.618652 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2867 19:52:50.622209 CH0 RK1: MR19=404, MR18=F0F
2868 19:52:50.625452 CH0_RK1: MR19=0x404, MR18=0xF0F, DQSOSC=404, MR23=63, INC=40, DEC=26
2869 19:52:50.628539 [RxdqsGatingPostProcess] freq 1200
2870 19:52:50.635267 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2871 19:52:50.638537 Pre-setting of DQS Precalculation
2872 19:52:50.641840 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2873 19:52:50.641932 ==
2874 19:52:50.645279 Dram Type= 6, Freq= 0, CH_1, rank 0
2875 19:52:50.651875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2876 19:52:50.651998 ==
2877 19:52:50.655216 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2878 19:52:50.662047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2879 19:52:50.670362 [CA 0] Center 37 (7~68) winsize 62
2880 19:52:50.673748 [CA 1] Center 37 (7~68) winsize 62
2881 19:52:50.677221 [CA 2] Center 34 (4~65) winsize 62
2882 19:52:50.680704 [CA 3] Center 33 (3~64) winsize 62
2883 19:52:50.683847 [CA 4] Center 32 (2~63) winsize 62
2884 19:52:50.687108 [CA 5] Center 32 (2~63) winsize 62
2885 19:52:50.687191
2886 19:52:50.690740 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2887 19:52:50.690824
2888 19:52:50.693692 [CATrainingPosCal] consider 1 rank data
2889 19:52:50.697038 u2DelayCellTimex100 = 270/100 ps
2890 19:52:50.700947 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2891 19:52:50.704100 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2892 19:52:50.710714 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2893 19:52:50.714263 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2894 19:52:50.717596 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2895 19:52:50.720743 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2896 19:52:50.721164
2897 19:52:50.723994 CA PerBit enable=1, Macro0, CA PI delay=32
2898 19:52:50.724509
2899 19:52:50.727770 [CBTSetCACLKResult] CA Dly = 32
2900 19:52:50.728223 CS Dly: 6 (0~37)
2901 19:52:50.728572 ==
2902 19:52:50.731034 Dram Type= 6, Freq= 0, CH_1, rank 1
2903 19:52:50.737655 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2904 19:52:50.738073 ==
2905 19:52:50.741470 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2906 19:52:50.747676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2907 19:52:50.755766 [CA 0] Center 37 (7~68) winsize 62
2908 19:52:50.759506 [CA 1] Center 37 (7~68) winsize 62
2909 19:52:50.762515 [CA 2] Center 34 (3~65) winsize 63
2910 19:52:50.765883 [CA 3] Center 33 (3~64) winsize 62
2911 19:52:50.769619 [CA 4] Center 32 (2~63) winsize 62
2912 19:52:50.772764 [CA 5] Center 32 (1~63) winsize 63
2913 19:52:50.773182
2914 19:52:50.776220 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2915 19:52:50.776641
2916 19:52:50.779308 [CATrainingPosCal] consider 2 rank data
2917 19:52:50.783056 u2DelayCellTimex100 = 270/100 ps
2918 19:52:50.785935 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2919 19:52:50.789318 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2920 19:52:50.795689 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2921 19:52:50.799277 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2922 19:52:50.802580 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2923 19:52:50.805663 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2924 19:52:50.805814
2925 19:52:50.808987 CA PerBit enable=1, Macro0, CA PI delay=32
2926 19:52:50.809139
2927 19:52:50.812388 [CBTSetCACLKResult] CA Dly = 32
2928 19:52:50.812518 CS Dly: 6 (0~38)
2929 19:52:50.812621
2930 19:52:50.815709 ----->DramcWriteLeveling(PI) begin...
2931 19:52:50.818917 ==
2932 19:52:50.822582 Dram Type= 6, Freq= 0, CH_1, rank 0
2933 19:52:50.826048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2934 19:52:50.826377 ==
2935 19:52:50.829102 Write leveling (Byte 0): 20 => 20
2936 19:52:50.832513 Write leveling (Byte 1): 20 => 20
2937 19:52:50.836014 DramcWriteLeveling(PI) end<-----
2938 19:52:50.836269
2939 19:52:50.836399 ==
2940 19:52:50.839071 Dram Type= 6, Freq= 0, CH_1, rank 0
2941 19:52:50.842396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2942 19:52:50.842554 ==
2943 19:52:50.845668 [Gating] SW mode calibration
2944 19:52:50.852356 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2945 19:52:50.856005 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2946 19:52:50.862398 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2947 19:52:50.865971 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 19:52:50.869203 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2949 19:52:50.875990 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2950 19:52:50.879355 0 11 16 | B1->B0 | 3333 2929 | 0 0 | (0 1) (0 1)
2951 19:52:50.882833 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2952 19:52:50.889631 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2953 19:52:50.892773 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 19:52:50.896638 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 19:52:50.903313 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 19:52:50.906557 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 19:52:50.909613 0 12 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2958 19:52:50.916631 0 12 16 | B1->B0 | 3434 4141 | 0 0 | (1 1) (0 0)
2959 19:52:50.919967 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 19:52:50.922726 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 19:52:50.929471 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 19:52:50.932869 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 19:52:50.935713 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 19:52:50.943109 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 19:52:50.945669 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 19:52:50.949678 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2967 19:52:50.955926 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2968 19:52:50.959109 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 19:52:50.962654 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 19:52:50.966194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 19:52:50.972261 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 19:52:50.976060 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 19:52:50.979040 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 19:52:50.986039 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 19:52:50.988800 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 19:52:50.992169 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 19:52:50.999238 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 19:52:51.002481 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 19:52:51.005887 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 19:52:51.012686 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 19:52:51.015703 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 19:52:51.019290 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2983 19:52:51.025645 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2984 19:52:51.028789 Total UI for P1: 0, mck2ui 16
2985 19:52:51.032160 best dqsien dly found for B0: ( 0, 15, 16)
2986 19:52:51.035854 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 19:52:51.039103 Total UI for P1: 0, mck2ui 16
2988 19:52:51.042359 best dqsien dly found for B1: ( 0, 15, 18)
2989 19:52:51.045778 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2990 19:52:51.048858 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2991 19:52:51.049278
2992 19:52:51.052272 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2993 19:52:51.055555 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2994 19:52:51.059077 [Gating] SW calibration Done
2995 19:52:51.059597 ==
2996 19:52:51.062368 Dram Type= 6, Freq= 0, CH_1, rank 0
2997 19:52:51.065867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2998 19:52:51.069263 ==
2999 19:52:51.069782 RX Vref Scan: 0
3000 19:52:51.070121
3001 19:52:51.072895 RX Vref 0 -> 0, step: 1
3002 19:52:51.073314
3003 19:52:51.076073 RX Delay -40 -> 252, step: 8
3004 19:52:51.079212 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3005 19:52:51.082668 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3006 19:52:51.085858 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3007 19:52:51.089187 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3008 19:52:51.092825 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3009 19:52:51.099390 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3010 19:52:51.102283 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3011 19:52:51.105936 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3012 19:52:51.109517 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3013 19:52:51.112696 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3014 19:52:51.119483 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3015 19:52:51.122691 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3016 19:52:51.125971 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3017 19:52:51.129351 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3018 19:52:51.132514 iDelay=208, Bit 14, Center 115 (48 ~ 183) 136
3019 19:52:51.139827 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3020 19:52:51.140439 ==
3021 19:52:51.142579 Dram Type= 6, Freq= 0, CH_1, rank 0
3022 19:52:51.145995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3023 19:52:51.146459 ==
3024 19:52:51.146826 DQS Delay:
3025 19:52:51.149656 DQS0 = 0, DQS1 = 0
3026 19:52:51.150214 DQM Delay:
3027 19:52:51.152379 DQM0 = 115, DQM1 = 107
3028 19:52:51.152841 DQ Delay:
3029 19:52:51.156038 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3030 19:52:51.159371 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3031 19:52:51.162504 DQ8 =87, DQ9 =95, DQ10 =107, DQ11 =99
3032 19:52:51.166620 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3033 19:52:51.167185
3034 19:52:51.167553
3035 19:52:51.167893 ==
3036 19:52:51.169027 Dram Type= 6, Freq= 0, CH_1, rank 0
3037 19:52:51.176138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3038 19:52:51.176750 ==
3039 19:52:51.177120
3040 19:52:51.177462
3041 19:52:51.179159 TX Vref Scan disable
3042 19:52:51.179728 == TX Byte 0 ==
3043 19:52:51.182524 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3044 19:52:51.189162 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3045 19:52:51.189724 == TX Byte 1 ==
3046 19:52:51.192492 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3047 19:52:51.199494 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3048 19:52:51.200057 ==
3049 19:52:51.202713 Dram Type= 6, Freq= 0, CH_1, rank 0
3050 19:52:51.206154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3051 19:52:51.206716 ==
3052 19:52:51.217364 TX Vref=22, minBit 3, minWin=24, winSum=410
3053 19:52:51.220927 TX Vref=24, minBit 3, minWin=25, winSum=417
3054 19:52:51.223913 TX Vref=26, minBit 9, minWin=25, winSum=423
3055 19:52:51.227283 TX Vref=28, minBit 3, minWin=26, winSum=427
3056 19:52:51.230571 TX Vref=30, minBit 9, minWin=25, winSum=429
3057 19:52:51.234083 TX Vref=32, minBit 3, minWin=26, winSum=426
3058 19:52:51.240813 [TxChooseVref] Worse bit 3, Min win 26, Win sum 427, Final Vref 28
3059 19:52:51.241371
3060 19:52:51.244235 Final TX Range 1 Vref 28
3061 19:52:51.244801
3062 19:52:51.245169 ==
3063 19:52:51.247570 Dram Type= 6, Freq= 0, CH_1, rank 0
3064 19:52:51.250837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3065 19:52:51.251402 ==
3066 19:52:51.251774
3067 19:52:51.252117
3068 19:52:51.254001 TX Vref Scan disable
3069 19:52:51.257180 == TX Byte 0 ==
3070 19:52:51.260477 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3071 19:52:51.264104 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3072 19:52:51.267296 == TX Byte 1 ==
3073 19:52:51.270495 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3074 19:52:51.273797 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3075 19:52:51.274255
3076 19:52:51.277082 [DATLAT]
3077 19:52:51.277537 Freq=1200, CH1 RK0
3078 19:52:51.277907
3079 19:52:51.280739 DATLAT Default: 0xd
3080 19:52:51.281198 0, 0xFFFF, sum = 0
3081 19:52:51.283972 1, 0xFFFF, sum = 0
3082 19:52:51.284585 2, 0xFFFF, sum = 0
3083 19:52:51.287501 3, 0xFFFF, sum = 0
3084 19:52:51.287967 4, 0xFFFF, sum = 0
3085 19:52:51.290954 5, 0xFFFF, sum = 0
3086 19:52:51.291517 6, 0xFFFF, sum = 0
3087 19:52:51.293697 7, 0xFFFF, sum = 0
3088 19:52:51.294164 8, 0xFFFF, sum = 0
3089 19:52:51.297146 9, 0xFFFF, sum = 0
3090 19:52:51.300852 10, 0xFFFF, sum = 0
3091 19:52:51.301425 11, 0x0, sum = 1
3092 19:52:51.301805 12, 0x0, sum = 2
3093 19:52:51.303813 13, 0x0, sum = 3
3094 19:52:51.304316 14, 0x0, sum = 4
3095 19:52:51.307654 best_step = 12
3096 19:52:51.308249
3097 19:52:51.308625 ==
3098 19:52:51.311053 Dram Type= 6, Freq= 0, CH_1, rank 0
3099 19:52:51.313896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3100 19:52:51.314460 ==
3101 19:52:51.317344 RX Vref Scan: 1
3102 19:52:51.317923
3103 19:52:51.318297 Set Vref Range= 32 -> 127
3104 19:52:51.318643
3105 19:52:51.320786 RX Vref 32 -> 127, step: 1
3106 19:52:51.321354
3107 19:52:51.324151 RX Delay -29 -> 252, step: 4
3108 19:52:51.324659
3109 19:52:51.327042 Set Vref, RX VrefLevel [Byte0]: 32
3110 19:52:51.330557 [Byte1]: 32
3111 19:52:51.331015
3112 19:52:51.334005 Set Vref, RX VrefLevel [Byte0]: 33
3113 19:52:51.337180 [Byte1]: 33
3114 19:52:51.341566
3115 19:52:51.342082 Set Vref, RX VrefLevel [Byte0]: 34
3116 19:52:51.344613 [Byte1]: 34
3117 19:52:51.349576
3118 19:52:51.350093 Set Vref, RX VrefLevel [Byte0]: 35
3119 19:52:51.352733 [Byte1]: 35
3120 19:52:51.357607
3121 19:52:51.358121 Set Vref, RX VrefLevel [Byte0]: 36
3122 19:52:51.360637 [Byte1]: 36
3123 19:52:51.365639
3124 19:52:51.366156 Set Vref, RX VrefLevel [Byte0]: 37
3125 19:52:51.369217 [Byte1]: 37
3126 19:52:51.373450
3127 19:52:51.373891 Set Vref, RX VrefLevel [Byte0]: 38
3128 19:52:51.376994 [Byte1]: 38
3129 19:52:51.381299
3130 19:52:51.381814 Set Vref, RX VrefLevel [Byte0]: 39
3131 19:52:51.385030 [Byte1]: 39
3132 19:52:51.389503
3133 19:52:51.390023 Set Vref, RX VrefLevel [Byte0]: 40
3134 19:52:51.392780 [Byte1]: 40
3135 19:52:51.397445
3136 19:52:51.398152 Set Vref, RX VrefLevel [Byte0]: 41
3137 19:52:51.400653 [Byte1]: 41
3138 19:52:51.405287
3139 19:52:51.405808 Set Vref, RX VrefLevel [Byte0]: 42
3140 19:52:51.408589 [Byte1]: 42
3141 19:52:51.413144
3142 19:52:51.413663 Set Vref, RX VrefLevel [Byte0]: 43
3143 19:52:51.416556 [Byte1]: 43
3144 19:52:51.421611
3145 19:52:51.422129 Set Vref, RX VrefLevel [Byte0]: 44
3146 19:52:51.424929 [Byte1]: 44
3147 19:52:51.428979
3148 19:52:51.429392 Set Vref, RX VrefLevel [Byte0]: 45
3149 19:52:51.432159 [Byte1]: 45
3150 19:52:51.437296
3151 19:52:51.437812 Set Vref, RX VrefLevel [Byte0]: 46
3152 19:52:51.440308 [Byte1]: 46
3153 19:52:51.445427
3154 19:52:51.445942 Set Vref, RX VrefLevel [Byte0]: 47
3155 19:52:51.448116 [Byte1]: 47
3156 19:52:51.453095
3157 19:52:51.453615 Set Vref, RX VrefLevel [Byte0]: 48
3158 19:52:51.456360 [Byte1]: 48
3159 19:52:51.460854
3160 19:52:51.461416 Set Vref, RX VrefLevel [Byte0]: 49
3161 19:52:51.464275 [Byte1]: 49
3162 19:52:51.469159
3163 19:52:51.469718 Set Vref, RX VrefLevel [Byte0]: 50
3164 19:52:51.472235 [Byte1]: 50
3165 19:52:51.476920
3166 19:52:51.477466 Set Vref, RX VrefLevel [Byte0]: 51
3167 19:52:51.480664 [Byte1]: 51
3168 19:52:51.484978
3169 19:52:51.485545 Set Vref, RX VrefLevel [Byte0]: 52
3170 19:52:51.488503 [Byte1]: 52
3171 19:52:51.493105
3172 19:52:51.493671 Set Vref, RX VrefLevel [Byte0]: 53
3173 19:52:51.496551 [Byte1]: 53
3174 19:52:51.501092
3175 19:52:51.501658 Set Vref, RX VrefLevel [Byte0]: 54
3176 19:52:51.504119 [Byte1]: 54
3177 19:52:51.508763
3178 19:52:51.509330 Set Vref, RX VrefLevel [Byte0]: 55
3179 19:52:51.512032 [Byte1]: 55
3180 19:52:51.516858
3181 19:52:51.517424 Set Vref, RX VrefLevel [Byte0]: 56
3182 19:52:51.520086 [Byte1]: 56
3183 19:52:51.524572
3184 19:52:51.525274 Set Vref, RX VrefLevel [Byte0]: 57
3185 19:52:51.528137 [Byte1]: 57
3186 19:52:51.532836
3187 19:52:51.533401 Set Vref, RX VrefLevel [Byte0]: 58
3188 19:52:51.536148 [Byte1]: 58
3189 19:52:51.540680
3190 19:52:51.541245 Set Vref, RX VrefLevel [Byte0]: 59
3191 19:52:51.543881 [Byte1]: 59
3192 19:52:51.548639
3193 19:52:51.549203 Set Vref, RX VrefLevel [Byte0]: 60
3194 19:52:51.551922 [Byte1]: 60
3195 19:52:51.556717
3196 19:52:51.557281 Set Vref, RX VrefLevel [Byte0]: 61
3197 19:52:51.559825 [Byte1]: 61
3198 19:52:51.564215
3199 19:52:51.564693 Set Vref, RX VrefLevel [Byte0]: 62
3200 19:52:51.567535 [Byte1]: 62
3201 19:52:51.572157
3202 19:52:51.572420 Set Vref, RX VrefLevel [Byte0]: 63
3203 19:52:51.575081 [Byte1]: 63
3204 19:52:51.580207
3205 19:52:51.580428 Set Vref, RX VrefLevel [Byte0]: 64
3206 19:52:51.583215 [Byte1]: 64
3207 19:52:51.587760
3208 19:52:51.587881 Set Vref, RX VrefLevel [Byte0]: 65
3209 19:52:51.591364 [Byte1]: 65
3210 19:52:51.595977
3211 19:52:51.596195 Set Vref, RX VrefLevel [Byte0]: 66
3212 19:52:51.599529 [Byte1]: 66
3213 19:52:51.604242
3214 19:52:51.604456 Final RX Vref Byte 0 = 53 to rank0
3215 19:52:51.607583 Final RX Vref Byte 1 = 49 to rank0
3216 19:52:51.610886 Final RX Vref Byte 0 = 53 to rank1
3217 19:52:51.614307 Final RX Vref Byte 1 = 49 to rank1==
3218 19:52:51.617036 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 19:52:51.623714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3220 19:52:51.624042 ==
3221 19:52:51.624277 DQS Delay:
3222 19:52:51.624457 DQS0 = 0, DQS1 = 0
3223 19:52:51.627435 DQM Delay:
3224 19:52:51.627819 DQM0 = 115, DQM1 = 105
3225 19:52:51.630920 DQ Delay:
3226 19:52:51.634320 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3227 19:52:51.637387 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3228 19:52:51.640721 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =96
3229 19:52:51.643914 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =116
3230 19:52:51.644391
3231 19:52:51.644753
3232 19:52:51.650984 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3233 19:52:51.654238 CH1 RK0: MR19=404, MR18=1A1A
3234 19:52:51.660862 CH1_RK0: MR19=0x404, MR18=0x1A1A, DQSOSC=400, MR23=63, INC=40, DEC=27
3235 19:52:51.661697
3236 19:52:51.664082 ----->DramcWriteLeveling(PI) begin...
3237 19:52:51.664587 ==
3238 19:52:51.667415 Dram Type= 6, Freq= 0, CH_1, rank 1
3239 19:52:51.670930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3240 19:52:51.671386 ==
3241 19:52:51.674093 Write leveling (Byte 0): 21 => 21
3242 19:52:51.677680 Write leveling (Byte 1): 22 => 22
3243 19:52:51.680967 DramcWriteLeveling(PI) end<-----
3244 19:52:51.681496
3245 19:52:51.681864 ==
3246 19:52:51.684343 Dram Type= 6, Freq= 0, CH_1, rank 1
3247 19:52:51.690801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3248 19:52:51.691629 ==
3249 19:52:51.692320 [Gating] SW mode calibration
3250 19:52:51.700877 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3251 19:52:51.704050 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3252 19:52:51.707741 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3253 19:52:51.713884 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3254 19:52:51.717308 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3255 19:52:51.720846 0 11 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
3256 19:52:51.727474 0 11 16 | B1->B0 | 3030 2323 | 1 0 | (0 1) (0 0)
3257 19:52:51.730709 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3258 19:52:51.734131 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3259 19:52:51.740725 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3260 19:52:51.744096 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3261 19:52:51.747612 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3262 19:52:51.754036 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3263 19:52:51.757313 0 12 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
3264 19:52:51.760764 0 12 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3265 19:52:51.767388 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3266 19:52:51.770890 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3267 19:52:51.773742 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3268 19:52:51.780850 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3269 19:52:51.784097 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3270 19:52:51.787305 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3271 19:52:51.793906 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3272 19:52:51.797336 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3273 19:52:51.800738 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 19:52:51.804038 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 19:52:51.810725 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 19:52:51.813955 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 19:52:51.817289 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 19:52:51.823870 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 19:52:51.827502 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 19:52:51.830663 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 19:52:51.837499 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 19:52:51.840801 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 19:52:51.843953 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 19:52:51.850829 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 19:52:51.854460 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 19:52:51.858014 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3287 19:52:51.864552 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3288 19:52:51.867612 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3289 19:52:51.871248 Total UI for P1: 0, mck2ui 16
3290 19:52:51.874083 best dqsien dly found for B0: ( 0, 15, 10)
3291 19:52:51.877567 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3292 19:52:51.880757 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3293 19:52:51.883934 Total UI for P1: 0, mck2ui 16
3294 19:52:51.887530 best dqsien dly found for B1: ( 0, 15, 18)
3295 19:52:51.890792 best DQS0 dly(MCK, UI, PI) = (0, 15, 10)
3296 19:52:51.897675 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3297 19:52:51.898302
3298 19:52:51.900621 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 10)
3299 19:52:51.903976 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3300 19:52:51.907376 [Gating] SW calibration Done
3301 19:52:51.907787 ==
3302 19:52:51.910998 Dram Type= 6, Freq= 0, CH_1, rank 1
3303 19:52:51.914487 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3304 19:52:51.914904 ==
3305 19:52:51.915237 RX Vref Scan: 0
3306 19:52:51.915548
3307 19:52:51.917469 RX Vref 0 -> 0, step: 1
3308 19:52:51.917897
3309 19:52:51.920919 RX Delay -40 -> 252, step: 8
3310 19:52:51.924656 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3311 19:52:51.927800 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3312 19:52:51.934084 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3313 19:52:51.938144 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3314 19:52:51.941030 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3315 19:52:51.944313 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3316 19:52:51.947671 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3317 19:52:51.950989 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3318 19:52:51.957919 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3319 19:52:51.960988 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3320 19:52:51.964884 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3321 19:52:51.967994 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3322 19:52:51.971348 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3323 19:52:51.978343 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3324 19:52:51.981498 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3325 19:52:51.984768 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3326 19:52:51.985224 ==
3327 19:52:51.988033 Dram Type= 6, Freq= 0, CH_1, rank 1
3328 19:52:51.991701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3329 19:52:51.992308 ==
3330 19:52:51.994827 DQS Delay:
3331 19:52:51.995398 DQS0 = 0, DQS1 = 0
3332 19:52:51.998294 DQM Delay:
3333 19:52:51.998847 DQM0 = 115, DQM1 = 106
3334 19:52:51.999208 DQ Delay:
3335 19:52:52.004931 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3336 19:52:52.008404 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3337 19:52:52.011678 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3338 19:52:52.014970 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =111
3339 19:52:52.015522
3340 19:52:52.015886
3341 19:52:52.016282 ==
3342 19:52:52.018197 Dram Type= 6, Freq= 0, CH_1, rank 1
3343 19:52:52.021745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3344 19:52:52.022301 ==
3345 19:52:52.022670
3346 19:52:52.023005
3347 19:52:52.024510 TX Vref Scan disable
3348 19:52:52.024961 == TX Byte 0 ==
3349 19:52:52.031283 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3350 19:52:52.034740 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3351 19:52:52.035301 == TX Byte 1 ==
3352 19:52:52.041394 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3353 19:52:52.045062 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3354 19:52:52.045517 ==
3355 19:52:52.047980 Dram Type= 6, Freq= 0, CH_1, rank 1
3356 19:52:52.051292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3357 19:52:52.051848 ==
3358 19:52:52.063895 TX Vref=22, minBit 8, minWin=25, winSum=422
3359 19:52:52.067509 TX Vref=24, minBit 3, minWin=26, winSum=428
3360 19:52:52.070920 TX Vref=26, minBit 3, minWin=26, winSum=429
3361 19:52:52.073866 TX Vref=28, minBit 8, minWin=26, winSum=432
3362 19:52:52.077318 TX Vref=30, minBit 0, minWin=26, winSum=430
3363 19:52:52.080660 TX Vref=32, minBit 9, minWin=26, winSum=432
3364 19:52:52.087595 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 28
3365 19:52:52.088056
3366 19:52:52.090913 Final TX Range 1 Vref 28
3367 19:52:52.091370
3368 19:52:52.091738 ==
3369 19:52:52.094175 Dram Type= 6, Freq= 0, CH_1, rank 1
3370 19:52:52.097444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3371 19:52:52.097864 ==
3372 19:52:52.098199
3373 19:52:52.098506
3374 19:52:52.100774 TX Vref Scan disable
3375 19:52:52.104109 == TX Byte 0 ==
3376 19:52:52.107413 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3377 19:52:52.110790 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3378 19:52:52.114581 == TX Byte 1 ==
3379 19:52:52.117645 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3380 19:52:52.120788 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3381 19:52:52.121194
3382 19:52:52.124287 [DATLAT]
3383 19:52:52.124820 Freq=1200, CH1 RK1
3384 19:52:52.125158
3385 19:52:52.127479 DATLAT Default: 0xc
3386 19:52:52.127982 0, 0xFFFF, sum = 0
3387 19:52:52.131147 1, 0xFFFF, sum = 0
3388 19:52:52.131659 2, 0xFFFF, sum = 0
3389 19:52:52.134301 3, 0xFFFF, sum = 0
3390 19:52:52.134787 4, 0xFFFF, sum = 0
3391 19:52:52.137800 5, 0xFFFF, sum = 0
3392 19:52:52.138310 6, 0xFFFF, sum = 0
3393 19:52:52.140655 7, 0xFFFF, sum = 0
3394 19:52:52.141071 8, 0xFFFF, sum = 0
3395 19:52:52.144313 9, 0xFFFF, sum = 0
3396 19:52:52.147236 10, 0xFFFF, sum = 0
3397 19:52:52.147665 11, 0x0, sum = 1
3398 19:52:52.147992 12, 0x0, sum = 2
3399 19:52:52.150795 13, 0x0, sum = 3
3400 19:52:52.151324 14, 0x0, sum = 4
3401 19:52:52.154288 best_step = 12
3402 19:52:52.154931
3403 19:52:52.155339 ==
3404 19:52:52.157512 Dram Type= 6, Freq= 0, CH_1, rank 1
3405 19:52:52.160571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3406 19:52:52.161037 ==
3407 19:52:52.163969 RX Vref Scan: 0
3408 19:52:52.164494
3409 19:52:52.164839 RX Vref 0 -> 0, step: 1
3410 19:52:52.165185
3411 19:52:52.166952 RX Delay -29 -> 252, step: 4
3412 19:52:52.174314 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3413 19:52:52.177401 iDelay=199, Bit 1, Center 108 (39 ~ 178) 140
3414 19:52:52.181186 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3415 19:52:52.184454 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3416 19:52:52.187575 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3417 19:52:52.194454 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3418 19:52:52.197885 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3419 19:52:52.201406 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3420 19:52:52.204254 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3421 19:52:52.208022 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3422 19:52:52.214577 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3423 19:52:52.217860 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3424 19:52:52.221278 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3425 19:52:52.224757 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3426 19:52:52.228327 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144
3427 19:52:52.236539 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3428 19:52:52.237400 ==
3429 19:52:52.238501 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 19:52:52.241244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3431 19:52:52.241955 ==
3432 19:52:52.242609 DQS Delay:
3433 19:52:52.244286 DQS0 = 0, DQS1 = 0
3434 19:52:52.245002 DQM Delay:
3435 19:52:52.247660 DQM0 = 114, DQM1 = 103
3436 19:52:52.248325 DQ Delay:
3437 19:52:52.250915 DQ0 =116, DQ1 =108, DQ2 =108, DQ3 =112
3438 19:52:52.254816 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3439 19:52:52.257670 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3440 19:52:52.261162 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3441 19:52:52.261618
3442 19:52:52.261979
3443 19:52:52.271059 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3444 19:52:52.271581 CH1 RK1: MR19=404, MR18=D0D
3445 19:52:52.277672 CH1_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3446 19:52:52.281076 [RxdqsGatingPostProcess] freq 1200
3447 19:52:52.287804 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3448 19:52:52.291094 Pre-setting of DQS Precalculation
3449 19:52:52.294566 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3450 19:52:52.301109 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3451 19:52:52.310991 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3452 19:52:52.311542
3453 19:52:52.311906
3454 19:52:52.314429 [Calibration Summary] 2400 Mbps
3455 19:52:52.314954 CH 0, Rank 0
3456 19:52:52.317619 SW Impedance : PASS
3457 19:52:52.318078 DUTY Scan : NO K
3458 19:52:52.321127 ZQ Calibration : PASS
3459 19:52:52.324888 Jitter Meter : NO K
3460 19:52:52.325444 CBT Training : PASS
3461 19:52:52.327946 Write leveling : PASS
3462 19:52:52.328560 RX DQS gating : PASS
3463 19:52:52.331342 RX DQ/DQS(RDDQC) : PASS
3464 19:52:52.334303 TX DQ/DQS : PASS
3465 19:52:52.334755 RX DATLAT : PASS
3466 19:52:52.337518 RX DQ/DQS(Engine): PASS
3467 19:52:52.340824 TX OE : NO K
3468 19:52:52.341286 All Pass.
3469 19:52:52.341648
3470 19:52:52.342011 CH 0, Rank 1
3471 19:52:52.344073 SW Impedance : PASS
3472 19:52:52.347958 DUTY Scan : NO K
3473 19:52:52.348625 ZQ Calibration : PASS
3474 19:52:52.351153 Jitter Meter : NO K
3475 19:52:52.354608 CBT Training : PASS
3476 19:52:52.355202 Write leveling : PASS
3477 19:52:52.357652 RX DQS gating : PASS
3478 19:52:52.360744 RX DQ/DQS(RDDQC) : PASS
3479 19:52:52.361202 TX DQ/DQS : PASS
3480 19:52:52.364359 RX DATLAT : PASS
3481 19:52:52.367698 RX DQ/DQS(Engine): PASS
3482 19:52:52.368300 TX OE : NO K
3483 19:52:52.368750 All Pass.
3484 19:52:52.370810
3485 19:52:52.371507 CH 1, Rank 0
3486 19:52:52.374053 SW Impedance : PASS
3487 19:52:52.374599 DUTY Scan : NO K
3488 19:52:52.377331 ZQ Calibration : PASS
3489 19:52:52.377795 Jitter Meter : NO K
3490 19:52:52.380674 CBT Training : PASS
3491 19:52:52.384760 Write leveling : PASS
3492 19:52:52.385333 RX DQS gating : PASS
3493 19:52:52.387696 RX DQ/DQS(RDDQC) : PASS
3494 19:52:52.391158 TX DQ/DQS : PASS
3495 19:52:52.391721 RX DATLAT : PASS
3496 19:52:52.394738 RX DQ/DQS(Engine): PASS
3497 19:52:52.397455 TX OE : NO K
3498 19:52:52.397919 All Pass.
3499 19:52:52.398289
3500 19:52:52.398645 CH 1, Rank 1
3501 19:52:52.400927 SW Impedance : PASS
3502 19:52:52.404410 DUTY Scan : NO K
3503 19:52:52.404976 ZQ Calibration : PASS
3504 19:52:52.407425 Jitter Meter : NO K
3505 19:52:52.411020 CBT Training : PASS
3506 19:52:52.411580 Write leveling : PASS
3507 19:52:52.414125 RX DQS gating : PASS
3508 19:52:52.417716 RX DQ/DQS(RDDQC) : PASS
3509 19:52:52.418278 TX DQ/DQS : PASS
3510 19:52:52.420855 RX DATLAT : PASS
3511 19:52:52.421416 RX DQ/DQS(Engine): PASS
3512 19:52:52.424034 TX OE : NO K
3513 19:52:52.424536 All Pass.
3514 19:52:52.424906
3515 19:52:52.427784 DramC Write-DBI off
3516 19:52:52.431381 PER_BANK_REFRESH: Hybrid Mode
3517 19:52:52.431843 TX_TRACKING: ON
3518 19:52:52.440987 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3519 19:52:52.443968 [FAST_K] Save calibration result to emmc
3520 19:52:52.447435 dramc_set_vcore_voltage set vcore to 650000
3521 19:52:52.451086 Read voltage for 600, 5
3522 19:52:52.451644 Vio18 = 0
3523 19:52:52.454116 Vcore = 650000
3524 19:52:52.454677 Vdram = 0
3525 19:52:52.455049 Vddq = 0
3526 19:52:52.455389 Vmddr = 0
3527 19:52:52.460830 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3528 19:52:52.467035 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3529 19:52:52.467587 MEM_TYPE=3, freq_sel=19
3530 19:52:52.470491 sv_algorithm_assistance_LP4_1600
3531 19:52:52.473972 ============ PULL DRAM RESETB DOWN ============
3532 19:52:52.480953 ========== PULL DRAM RESETB DOWN end =========
3533 19:52:52.484163 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3534 19:52:52.487475 ===================================
3535 19:52:52.490658 LPDDR4 DRAM CONFIGURATION
3536 19:52:52.493974 ===================================
3537 19:52:52.494558 EX_ROW_EN[0] = 0x0
3538 19:52:52.497037 EX_ROW_EN[1] = 0x0
3539 19:52:52.497526 LP4Y_EN = 0x0
3540 19:52:52.500491 WORK_FSP = 0x0
3541 19:52:52.500948 WL = 0x2
3542 19:52:52.504116 RL = 0x2
3543 19:52:52.504730 BL = 0x2
3544 19:52:52.507661 RPST = 0x0
3545 19:52:52.508261 RD_PRE = 0x0
3546 19:52:52.510864 WR_PRE = 0x1
3547 19:52:52.511320 WR_PST = 0x0
3548 19:52:52.514161 DBI_WR = 0x0
3549 19:52:52.517618 DBI_RD = 0x0
3550 19:52:52.518174 OTF = 0x1
3551 19:52:52.520818 ===================================
3552 19:52:52.524305 ===================================
3553 19:52:52.524861 ANA top config
3554 19:52:52.527318 ===================================
3555 19:52:52.531038 DLL_ASYNC_EN = 0
3556 19:52:52.534063 ALL_SLAVE_EN = 1
3557 19:52:52.537370 NEW_RANK_MODE = 1
3558 19:52:52.540575 DLL_IDLE_MODE = 1
3559 19:52:52.541132 LP45_APHY_COMB_EN = 1
3560 19:52:52.543799 TX_ODT_DIS = 1
3561 19:52:52.547509 NEW_8X_MODE = 1
3562 19:52:52.550424 ===================================
3563 19:52:52.553748 ===================================
3564 19:52:52.557535 data_rate = 1200
3565 19:52:52.560312 CKR = 1
3566 19:52:52.560770 DQ_P2S_RATIO = 8
3567 19:52:52.563973 ===================================
3568 19:52:52.566829 CA_P2S_RATIO = 8
3569 19:52:52.570756 DQ_CA_OPEN = 0
3570 19:52:52.573632 DQ_SEMI_OPEN = 0
3571 19:52:52.576756 CA_SEMI_OPEN = 0
3572 19:52:52.580982 CA_FULL_RATE = 0
3573 19:52:52.581545 DQ_CKDIV4_EN = 1
3574 19:52:52.583791 CA_CKDIV4_EN = 1
3575 19:52:52.586799 CA_PREDIV_EN = 0
3576 19:52:52.590643 PH8_DLY = 0
3577 19:52:52.593740 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3578 19:52:52.596829 DQ_AAMCK_DIV = 4
3579 19:52:52.597285 CA_AAMCK_DIV = 4
3580 19:52:52.600350 CA_ADMCK_DIV = 4
3581 19:52:52.603309 DQ_TRACK_CA_EN = 0
3582 19:52:52.607026 CA_PICK = 600
3583 19:52:52.609966 CA_MCKIO = 600
3584 19:52:52.613361 MCKIO_SEMI = 0
3585 19:52:52.617025 PLL_FREQ = 2288
3586 19:52:52.617480 DQ_UI_PI_RATIO = 32
3587 19:52:52.620057 CA_UI_PI_RATIO = 0
3588 19:52:52.623332 ===================================
3589 19:52:52.626824 ===================================
3590 19:52:52.630249 memory_type:LPDDR4
3591 19:52:52.633469 GP_NUM : 10
3592 19:52:52.633928 SRAM_EN : 1
3593 19:52:52.636516 MD32_EN : 0
3594 19:52:52.639891 ===================================
3595 19:52:52.640394 [ANA_INIT] >>>>>>>>>>>>>>
3596 19:52:52.643336 <<<<<< [CONFIGURE PHASE]: ANA_TX
3597 19:52:52.646864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3598 19:52:52.649840 ===================================
3599 19:52:52.653630 data_rate = 1200,PCW = 0X5800
3600 19:52:52.656584 ===================================
3601 19:52:52.659845 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3602 19:52:52.666454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3603 19:52:52.673403 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3604 19:52:52.676286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3605 19:52:52.679717 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3606 19:52:52.683125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3607 19:52:52.686905 [ANA_INIT] flow start
3608 19:52:52.687460 [ANA_INIT] PLL >>>>>>>>
3609 19:52:52.689666 [ANA_INIT] PLL <<<<<<<<
3610 19:52:52.693408 [ANA_INIT] MIDPI >>>>>>>>
3611 19:52:52.693939 [ANA_INIT] MIDPI <<<<<<<<
3612 19:52:52.696511 [ANA_INIT] DLL >>>>>>>>
3613 19:52:52.700093 [ANA_INIT] flow end
3614 19:52:52.703338 ============ LP4 DIFF to SE enter ============
3615 19:52:52.706284 ============ LP4 DIFF to SE exit ============
3616 19:52:52.709677 [ANA_INIT] <<<<<<<<<<<<<
3617 19:52:52.713038 [Flow] Enable top DCM control >>>>>
3618 19:52:52.716229 [Flow] Enable top DCM control <<<<<
3619 19:52:52.719988 Enable DLL master slave shuffle
3620 19:52:52.723299 ==============================================================
3621 19:52:52.726197 Gating Mode config
3622 19:52:52.732528 ==============================================================
3623 19:52:52.733634 Config description:
3624 19:52:52.742557 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3625 19:52:52.749408 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3626 19:52:52.756045 SELPH_MODE 0: By rank 1: By Phase
3627 19:52:52.759186 ==============================================================
3628 19:52:52.762792 GAT_TRACK_EN = 1
3629 19:52:52.765806 RX_GATING_MODE = 2
3630 19:52:52.769240 RX_GATING_TRACK_MODE = 2
3631 19:52:52.772296 SELPH_MODE = 1
3632 19:52:52.775906 PICG_EARLY_EN = 1
3633 19:52:52.778985 VALID_LAT_VALUE = 1
3634 19:52:52.782719 ==============================================================
3635 19:52:52.785874 Enter into Gating configuration >>>>
3636 19:52:52.789254 Exit from Gating configuration <<<<
3637 19:52:52.792557 Enter into DVFS_PRE_config >>>>>
3638 19:52:52.805746 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3639 19:52:52.809118 Exit from DVFS_PRE_config <<<<<
3640 19:52:52.812273 Enter into PICG configuration >>>>
3641 19:52:52.812830 Exit from PICG configuration <<<<
3642 19:52:52.815649 [RX_INPUT] configuration >>>>>
3643 19:52:52.819219 [RX_INPUT] configuration <<<<<
3644 19:52:52.825775 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3645 19:52:52.828857 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3646 19:52:52.835753 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3647 19:52:52.842641 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3648 19:52:52.849153 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3649 19:52:52.855643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3650 19:52:52.858999 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3651 19:52:52.862349 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3652 19:52:52.865635 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3653 19:52:52.872072 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3654 19:52:52.875312 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3655 19:52:52.878896 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3656 19:52:52.882261 ===================================
3657 19:52:52.885579 LPDDR4 DRAM CONFIGURATION
3658 19:52:52.889292 ===================================
3659 19:52:52.892341 EX_ROW_EN[0] = 0x0
3660 19:52:52.892909 EX_ROW_EN[1] = 0x0
3661 19:52:52.896039 LP4Y_EN = 0x0
3662 19:52:52.896638 WORK_FSP = 0x0
3663 19:52:52.898789 WL = 0x2
3664 19:52:52.899344 RL = 0x2
3665 19:52:52.901897 BL = 0x2
3666 19:52:52.902353 RPST = 0x0
3667 19:52:52.905861 RD_PRE = 0x0
3668 19:52:52.906464 WR_PRE = 0x1
3669 19:52:52.908712 WR_PST = 0x0
3670 19:52:52.909265 DBI_WR = 0x0
3671 19:52:52.911905 DBI_RD = 0x0
3672 19:52:52.912385 OTF = 0x1
3673 19:52:52.915500 ===================================
3674 19:52:52.918974 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3675 19:52:52.925416 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3676 19:52:52.928877 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3677 19:52:52.932330 ===================================
3678 19:52:52.935407 LPDDR4 DRAM CONFIGURATION
3679 19:52:52.938904 ===================================
3680 19:52:52.939471 EX_ROW_EN[0] = 0x10
3681 19:52:52.942115 EX_ROW_EN[1] = 0x0
3682 19:52:52.945654 LP4Y_EN = 0x0
3683 19:52:52.946215 WORK_FSP = 0x0
3684 19:52:52.948639 WL = 0x2
3685 19:52:52.949093 RL = 0x2
3686 19:52:52.951909 BL = 0x2
3687 19:52:52.952486 RPST = 0x0
3688 19:52:52.955504 RD_PRE = 0x0
3689 19:52:52.956059 WR_PRE = 0x1
3690 19:52:52.958560 WR_PST = 0x0
3691 19:52:52.959115 DBI_WR = 0x0
3692 19:52:52.962004 DBI_RD = 0x0
3693 19:52:52.962560 OTF = 0x1
3694 19:52:52.966139 ===================================
3695 19:52:52.971676 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3696 19:52:52.975971 nWR fixed to 30
3697 19:52:52.979236 [ModeRegInit_LP4] CH0 RK0
3698 19:52:52.979691 [ModeRegInit_LP4] CH0 RK1
3699 19:52:52.982416 [ModeRegInit_LP4] CH1 RK0
3700 19:52:52.985800 [ModeRegInit_LP4] CH1 RK1
3701 19:52:52.986255 match AC timing 16
3702 19:52:52.992519 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3703 19:52:52.996127 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3704 19:52:52.999115 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3705 19:52:53.005775 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3706 19:52:53.008813 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3707 19:52:53.009270 ==
3708 19:52:53.012657 Dram Type= 6, Freq= 0, CH_0, rank 0
3709 19:52:53.015624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3710 19:52:53.016082 ==
3711 19:52:53.022232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3712 19:52:53.028853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3713 19:52:53.032334 [CA 0] Center 35 (5~66) winsize 62
3714 19:52:53.035603 [CA 1] Center 35 (5~66) winsize 62
3715 19:52:53.038897 [CA 2] Center 34 (4~65) winsize 62
3716 19:52:53.042656 [CA 3] Center 34 (4~65) winsize 62
3717 19:52:53.045850 [CA 4] Center 33 (3~64) winsize 62
3718 19:52:53.048877 [CA 5] Center 33 (3~64) winsize 62
3719 19:52:53.049293
3720 19:52:53.052583 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3721 19:52:53.053097
3722 19:52:53.055747 [CATrainingPosCal] consider 1 rank data
3723 19:52:53.059275 u2DelayCellTimex100 = 270/100 ps
3724 19:52:53.062102 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3725 19:52:53.065424 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3726 19:52:53.068821 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3727 19:52:53.072131 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3728 19:52:53.075559 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3729 19:52:53.078716 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3730 19:52:53.082458
3731 19:52:53.085642 CA PerBit enable=1, Macro0, CA PI delay=33
3732 19:52:53.086100
3733 19:52:53.088759 [CBTSetCACLKResult] CA Dly = 33
3734 19:52:53.089219 CS Dly: 6 (0~37)
3735 19:52:53.089585 ==
3736 19:52:53.092303 Dram Type= 6, Freq= 0, CH_0, rank 1
3737 19:52:53.095538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3738 19:52:53.095993 ==
3739 19:52:53.102091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3740 19:52:53.109114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3741 19:52:53.112113 [CA 0] Center 35 (5~66) winsize 62
3742 19:52:53.115429 [CA 1] Center 35 (5~66) winsize 62
3743 19:52:53.118528 [CA 2] Center 34 (4~65) winsize 62
3744 19:52:53.122034 [CA 3] Center 34 (3~65) winsize 63
3745 19:52:53.125371 [CA 4] Center 33 (3~64) winsize 62
3746 19:52:53.128740 [CA 5] Center 33 (3~64) winsize 62
3747 19:52:53.129225
3748 19:52:53.131861 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3749 19:52:53.132377
3750 19:52:53.135131 [CATrainingPosCal] consider 2 rank data
3751 19:52:53.138745 u2DelayCellTimex100 = 270/100 ps
3752 19:52:53.141795 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3753 19:52:53.145107 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3754 19:52:53.148367 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3755 19:52:53.151746 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3756 19:52:53.158556 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3757 19:52:53.161827 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3758 19:52:53.162243
3759 19:52:53.165625 CA PerBit enable=1, Macro0, CA PI delay=33
3760 19:52:53.166039
3761 19:52:53.168789 [CBTSetCACLKResult] CA Dly = 33
3762 19:52:53.169204 CS Dly: 5 (0~36)
3763 19:52:53.169533
3764 19:52:53.171931 ----->DramcWriteLeveling(PI) begin...
3765 19:52:53.172467 ==
3766 19:52:53.174845 Dram Type= 6, Freq= 0, CH_0, rank 0
3767 19:52:53.181589 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3768 19:52:53.182065 ==
3769 19:52:53.184793 Write leveling (Byte 0): 30 => 30
3770 19:52:53.188476 Write leveling (Byte 1): 30 => 30
3771 19:52:53.189141 DramcWriteLeveling(PI) end<-----
3772 19:52:53.189653
3773 19:52:53.191715 ==
3774 19:52:53.195039 Dram Type= 6, Freq= 0, CH_0, rank 0
3775 19:52:53.198347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3776 19:52:53.199010 ==
3777 19:52:53.201494 [Gating] SW mode calibration
3778 19:52:53.208758 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3779 19:52:53.211475 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3780 19:52:53.218434 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3781 19:52:53.221513 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3782 19:52:53.224646 0 5 8 | B1->B0 | 3131 3131 | 0 0 | (0 1) (0 1)
3783 19:52:53.231407 0 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3784 19:52:53.234945 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3785 19:52:53.238136 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3786 19:52:53.244523 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3787 19:52:53.247831 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3788 19:52:53.251043 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3789 19:52:53.258148 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3790 19:52:53.261316 0 6 8 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
3791 19:52:53.264528 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3792 19:52:53.271466 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3793 19:52:53.274366 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3794 19:52:53.277650 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3795 19:52:53.284483 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3796 19:52:53.287955 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3797 19:52:53.291085 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3798 19:52:53.297562 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3799 19:52:53.301240 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3800 19:52:53.304216 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3801 19:52:53.311276 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3802 19:52:53.314129 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3803 19:52:53.317540 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3804 19:52:53.321125 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3805 19:52:53.327691 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3806 19:52:53.331039 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3807 19:52:53.334481 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3808 19:52:53.340821 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3809 19:52:53.344070 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 19:52:53.347518 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 19:52:53.354322 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 19:52:53.357985 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 19:52:53.360681 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 19:52:53.367390 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 19:52:53.370811 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3816 19:52:53.374251 Total UI for P1: 0, mck2ui 16
3817 19:52:53.377246 best dqsien dly found for B0: ( 0, 9, 10)
3818 19:52:53.380729 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3819 19:52:53.384319 Total UI for P1: 0, mck2ui 16
3820 19:52:53.387427 best dqsien dly found for B1: ( 0, 9, 12)
3821 19:52:53.390799 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3822 19:52:53.394391 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
3823 19:52:53.394942
3824 19:52:53.401120 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3825 19:52:53.404149 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
3826 19:52:53.407376 [Gating] SW calibration Done
3827 19:52:53.407836 ==
3828 19:52:53.410765 Dram Type= 6, Freq= 0, CH_0, rank 0
3829 19:52:53.414318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3830 19:52:53.414889 ==
3831 19:52:53.415263 RX Vref Scan: 0
3832 19:52:53.415607
3833 19:52:53.417407 RX Vref 0 -> 0, step: 1
3834 19:52:53.417972
3835 19:52:53.420710 RX Delay -230 -> 252, step: 16
3836 19:52:53.424014 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3837 19:52:53.427201 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3838 19:52:53.434104 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3839 19:52:53.437168 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3840 19:52:53.440806 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3841 19:52:53.444122 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3842 19:52:53.450751 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3843 19:52:53.454036 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3844 19:52:53.457358 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
3845 19:52:53.460544 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3846 19:52:53.464024 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3847 19:52:53.470449 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
3848 19:52:53.473468 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3849 19:52:53.476920 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3850 19:52:53.480428 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3851 19:52:53.487355 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3852 19:52:53.487918 ==
3853 19:52:53.490854 Dram Type= 6, Freq= 0, CH_0, rank 0
3854 19:52:53.493832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3855 19:52:53.494401 ==
3856 19:52:53.494773 DQS Delay:
3857 19:52:53.497072 DQS0 = 0, DQS1 = 0
3858 19:52:53.497636 DQM Delay:
3859 19:52:53.500857 DQM0 = 39, DQM1 = 31
3860 19:52:53.501436 DQ Delay:
3861 19:52:53.503993 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3862 19:52:53.507092 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3863 19:52:53.510342 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
3864 19:52:53.513452 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3865 19:52:53.513919
3866 19:52:53.514288
3867 19:52:53.514628 ==
3868 19:52:53.517002 Dram Type= 6, Freq= 0, CH_0, rank 0
3869 19:52:53.520599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3870 19:52:53.521063 ==
3871 19:52:53.523849
3872 19:52:53.524465
3873 19:52:53.524849 TX Vref Scan disable
3874 19:52:53.527611 == TX Byte 0 ==
3875 19:52:53.530431 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3876 19:52:53.533660 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3877 19:52:53.536939 == TX Byte 1 ==
3878 19:52:53.539913 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3879 19:52:53.543491 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3880 19:52:53.547185 ==
3881 19:52:53.547750 Dram Type= 6, Freq= 0, CH_0, rank 0
3882 19:52:53.553386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3883 19:52:53.553917 ==
3884 19:52:53.554285
3885 19:52:53.554630
3886 19:52:53.556617 TX Vref Scan disable
3887 19:52:53.557075 == TX Byte 0 ==
3888 19:52:53.563451 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3889 19:52:53.566626 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3890 19:52:53.567120 == TX Byte 1 ==
3891 19:52:53.573584 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3892 19:52:53.577334 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3893 19:52:53.577818
3894 19:52:53.578154 [DATLAT]
3895 19:52:53.579907 Freq=600, CH0 RK0
3896 19:52:53.580367
3897 19:52:53.580707 DATLAT Default: 0x9
3898 19:52:53.583224 0, 0xFFFF, sum = 0
3899 19:52:53.583649 1, 0xFFFF, sum = 0
3900 19:52:53.586822 2, 0xFFFF, sum = 0
3901 19:52:53.587244 3, 0xFFFF, sum = 0
3902 19:52:53.590088 4, 0xFFFF, sum = 0
3903 19:52:53.590509 5, 0xFFFF, sum = 0
3904 19:52:53.593093 6, 0xFFFF, sum = 0
3905 19:52:53.593588 7, 0x0, sum = 1
3906 19:52:53.596436 8, 0x0, sum = 2
3907 19:52:53.596964 9, 0x0, sum = 3
3908 19:52:53.599684 10, 0x0, sum = 4
3909 19:52:53.600223 best_step = 8
3910 19:52:53.600629
3911 19:52:53.600954 ==
3912 19:52:53.602994 Dram Type= 6, Freq= 0, CH_0, rank 0
3913 19:52:53.609960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3914 19:52:53.610443 ==
3915 19:52:53.610782 RX Vref Scan: 1
3916 19:52:53.611095
3917 19:52:53.612679 RX Vref 0 -> 0, step: 1
3918 19:52:53.613097
3919 19:52:53.616427 RX Delay -195 -> 252, step: 8
3920 19:52:53.616844
3921 19:52:53.619429 Set Vref, RX VrefLevel [Byte0]: 51
3922 19:52:53.623115 [Byte1]: 48
3923 19:52:53.623632
3924 19:52:53.626426 Final RX Vref Byte 0 = 51 to rank0
3925 19:52:53.629483 Final RX Vref Byte 1 = 48 to rank0
3926 19:52:53.632772 Final RX Vref Byte 0 = 51 to rank1
3927 19:52:53.636579 Final RX Vref Byte 1 = 48 to rank1==
3928 19:52:53.639948 Dram Type= 6, Freq= 0, CH_0, rank 0
3929 19:52:53.642738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3930 19:52:53.643202 ==
3931 19:52:53.646296 DQS Delay:
3932 19:52:53.646857 DQS0 = 0, DQS1 = 0
3933 19:52:53.647230 DQM Delay:
3934 19:52:53.649719 DQM0 = 40, DQM1 = 31
3935 19:52:53.650281 DQ Delay:
3936 19:52:53.652912 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =40
3937 19:52:53.656068 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
3938 19:52:53.659437 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
3939 19:52:53.662794 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
3940 19:52:53.663208
3941 19:52:53.663538
3942 19:52:53.672834 [DQSOSCAuto] RK0, (LSB)MR18= 0x5959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3943 19:52:53.675926 CH0 RK0: MR19=808, MR18=5959
3944 19:52:53.679330 CH0_RK0: MR19=0x808, MR18=0x5959, DQSOSC=393, MR23=63, INC=169, DEC=113
3945 19:52:53.682675
3946 19:52:53.685641 ----->DramcWriteLeveling(PI) begin...
3947 19:52:53.686099 ==
3948 19:52:53.689065 Dram Type= 6, Freq= 0, CH_0, rank 1
3949 19:52:53.692332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 19:52:53.692824 ==
3951 19:52:53.695707 Write leveling (Byte 0): 32 => 32
3952 19:52:53.699323 Write leveling (Byte 1): 31 => 31
3953 19:52:53.702581 DramcWriteLeveling(PI) end<-----
3954 19:52:53.703041
3955 19:52:53.703480 ==
3956 19:52:53.706244 Dram Type= 6, Freq= 0, CH_0, rank 1
3957 19:52:53.709289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3958 19:52:53.709726 ==
3959 19:52:53.712165 [Gating] SW mode calibration
3960 19:52:53.719076 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3961 19:52:53.725969 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3962 19:52:53.729255 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3963 19:52:53.732292 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3964 19:52:53.739112 0 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
3965 19:52:53.742069 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3966 19:52:53.745681 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 19:52:53.753039 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 19:52:53.756263 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 19:52:53.758559 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 19:52:53.761888 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 19:52:53.768665 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 19:52:53.772376 0 6 8 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 0)
3973 19:52:53.775364 0 6 12 | B1->B0 | 4140 4646 | 1 0 | (0 0) (0 0)
3974 19:52:53.782061 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 19:52:53.785399 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 19:52:53.788461 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 19:52:53.795332 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 19:52:53.798661 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 19:52:53.801771 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 19:52:53.808755 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3981 19:52:53.811986 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3982 19:52:53.815183 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 19:52:53.821820 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 19:52:53.824963 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 19:52:53.828708 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 19:52:53.835095 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 19:52:53.838390 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 19:52:53.841589 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 19:52:53.848245 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 19:52:53.851637 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 19:52:53.854791 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 19:52:53.861673 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 19:52:53.864968 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 19:52:53.868300 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 19:52:53.874937 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 19:52:53.877838 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 19:52:53.881262 Total UI for P1: 0, mck2ui 16
3998 19:52:53.884798 best dqsien dly found for B0: ( 0, 9, 6)
3999 19:52:53.888227 Total UI for P1: 0, mck2ui 16
4000 19:52:53.891720 best dqsien dly found for B1: ( 0, 9, 6)
4001 19:52:53.894455 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4002 19:52:53.897922 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4003 19:52:53.898533
4004 19:52:53.901220 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4005 19:52:53.905029 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4006 19:52:53.907506 [Gating] SW calibration Done
4007 19:52:53.907956 ==
4008 19:52:53.911076 Dram Type= 6, Freq= 0, CH_0, rank 1
4009 19:52:53.914555 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4010 19:52:53.917726 ==
4011 19:52:53.918180 RX Vref Scan: 0
4012 19:52:53.918542
4013 19:52:53.920995 RX Vref 0 -> 0, step: 1
4014 19:52:53.921446
4015 19:52:53.924715 RX Delay -230 -> 252, step: 16
4016 19:52:53.927352 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4017 19:52:53.930639 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4018 19:52:53.933983 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4019 19:52:53.940836 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4020 19:52:53.944118 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4021 19:52:53.947483 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4022 19:52:53.950763 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4023 19:52:53.954136 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4024 19:52:53.960747 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4025 19:52:53.963734 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4026 19:52:53.967098 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4027 19:52:53.970926 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4028 19:52:53.977274 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4029 19:52:53.980552 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4030 19:52:53.983899 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4031 19:52:53.987199 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4032 19:52:53.987614 ==
4033 19:52:53.990653 Dram Type= 6, Freq= 0, CH_0, rank 1
4034 19:52:53.997134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4035 19:52:53.997649 ==
4036 19:52:53.997985 DQS Delay:
4037 19:52:54.000775 DQS0 = 0, DQS1 = 0
4038 19:52:54.001191 DQM Delay:
4039 19:52:54.001527 DQM0 = 40, DQM1 = 33
4040 19:52:54.003691 DQ Delay:
4041 19:52:54.007389 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4042 19:52:54.010472 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4043 19:52:54.013888 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4044 19:52:54.017188 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4045 19:52:54.017677
4046 19:52:54.018012
4047 19:52:54.018319 ==
4048 19:52:54.020545 Dram Type= 6, Freq= 0, CH_0, rank 1
4049 19:52:54.023975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4050 19:52:54.024446 ==
4051 19:52:54.024787
4052 19:52:54.025096
4053 19:52:54.027028 TX Vref Scan disable
4054 19:52:54.030381 == TX Byte 0 ==
4055 19:52:54.033925 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4056 19:52:54.037039 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4057 19:52:54.040699 == TX Byte 1 ==
4058 19:52:54.043849 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4059 19:52:54.047501 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4060 19:52:54.047986 ==
4061 19:52:54.050402 Dram Type= 6, Freq= 0, CH_0, rank 1
4062 19:52:54.053687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4063 19:52:54.054109 ==
4064 19:52:54.056975
4065 19:52:54.057392
4066 19:52:54.057724 TX Vref Scan disable
4067 19:52:54.060468 == TX Byte 0 ==
4068 19:52:54.063807 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4069 19:52:54.070666 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4070 19:52:54.071083 == TX Byte 1 ==
4071 19:52:54.073843 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4072 19:52:54.080133 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4073 19:52:54.080596
4074 19:52:54.080930 [DATLAT]
4075 19:52:54.081243 Freq=600, CH0 RK1
4076 19:52:54.081544
4077 19:52:54.083696 DATLAT Default: 0x8
4078 19:52:54.084111 0, 0xFFFF, sum = 0
4079 19:52:54.087201 1, 0xFFFF, sum = 0
4080 19:52:54.087623 2, 0xFFFF, sum = 0
4081 19:52:54.091179 3, 0xFFFF, sum = 0
4082 19:52:54.091704 4, 0xFFFF, sum = 0
4083 19:52:54.093968 5, 0xFFFF, sum = 0
4084 19:52:54.097536 6, 0xFFFF, sum = 0
4085 19:52:54.098074 7, 0x0, sum = 1
4086 19:52:54.098420 8, 0x0, sum = 2
4087 19:52:54.100597 9, 0x0, sum = 3
4088 19:52:54.101016 10, 0x0, sum = 4
4089 19:52:54.103989 best_step = 8
4090 19:52:54.104443
4091 19:52:54.104775 ==
4092 19:52:54.107152 Dram Type= 6, Freq= 0, CH_0, rank 1
4093 19:52:54.111080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4094 19:52:54.111589 ==
4095 19:52:54.114521 RX Vref Scan: 0
4096 19:52:54.115028
4097 19:52:54.115361 RX Vref 0 -> 0, step: 1
4098 19:52:54.115669
4099 19:52:54.117265 RX Delay -195 -> 252, step: 8
4100 19:52:54.124522 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4101 19:52:54.127808 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4102 19:52:54.130981 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4103 19:52:54.134656 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4104 19:52:54.140842 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4105 19:52:54.144308 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4106 19:52:54.147514 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4107 19:52:54.151081 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4108 19:52:54.154667 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4109 19:52:54.161072 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4110 19:52:54.164214 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4111 19:52:54.167995 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4112 19:52:54.170601 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4113 19:52:54.177255 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4114 19:52:54.180772 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4115 19:52:54.184043 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4116 19:52:54.184548 ==
4117 19:52:54.186944 Dram Type= 6, Freq= 0, CH_0, rank 1
4118 19:52:54.194214 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4119 19:52:54.194778 ==
4120 19:52:54.195147 DQS Delay:
4121 19:52:54.195484 DQS0 = 0, DQS1 = 0
4122 19:52:54.196784 DQM Delay:
4123 19:52:54.197238 DQM0 = 41, DQM1 = 32
4124 19:52:54.200638 DQ Delay:
4125 19:52:54.203723 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =36
4126 19:52:54.206852 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =48
4127 19:52:54.210276 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4128 19:52:54.213756 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4129 19:52:54.214280
4130 19:52:54.214641
4131 19:52:54.220163 [DQSOSCAuto] RK1, (LSB)MR18= 0x6464, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4132 19:52:54.223811 CH0 RK1: MR19=808, MR18=6464
4133 19:52:54.230169 CH0_RK1: MR19=0x808, MR18=0x6464, DQSOSC=391, MR23=63, INC=171, DEC=114
4134 19:52:54.233506 [RxdqsGatingPostProcess] freq 600
4135 19:52:54.236879 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4136 19:52:54.240340 Pre-setting of DQS Precalculation
4137 19:52:54.246824 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4138 19:52:54.247368 ==
4139 19:52:54.250235 Dram Type= 6, Freq= 0, CH_1, rank 0
4140 19:52:54.253482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4141 19:52:54.254133 ==
4142 19:52:54.260412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4143 19:52:54.263371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4144 19:52:54.267665 [CA 0] Center 35 (5~66) winsize 62
4145 19:52:54.271134 [CA 1] Center 35 (4~66) winsize 63
4146 19:52:54.274890 [CA 2] Center 33 (3~64) winsize 62
4147 19:52:54.277630 [CA 3] Center 33 (3~64) winsize 62
4148 19:52:54.281002 [CA 4] Center 33 (2~64) winsize 63
4149 19:52:54.284534 [CA 5] Center 33 (2~64) winsize 63
4150 19:52:54.285041
4151 19:52:54.287596 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4152 19:52:54.288050
4153 19:52:54.291371 [CATrainingPosCal] consider 1 rank data
4154 19:52:54.294267 u2DelayCellTimex100 = 270/100 ps
4155 19:52:54.297638 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4156 19:52:54.304439 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4157 19:52:54.307642 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4158 19:52:54.310844 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4159 19:52:54.314220 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4160 19:52:54.317532 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4161 19:52:54.317944
4162 19:52:54.321057 CA PerBit enable=1, Macro0, CA PI delay=33
4163 19:52:54.321469
4164 19:52:54.324261 [CBTSetCACLKResult] CA Dly = 33
4165 19:52:54.324674 CS Dly: 4 (0~35)
4166 19:52:54.327504 ==
4167 19:52:54.327915 Dram Type= 6, Freq= 0, CH_1, rank 1
4168 19:52:54.334317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4169 19:52:54.334839 ==
4170 19:52:54.337851 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4171 19:52:54.343883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4172 19:52:54.347852 [CA 0] Center 35 (4~66) winsize 63
4173 19:52:54.351589 [CA 1] Center 34 (4~65) winsize 62
4174 19:52:54.354621 [CA 2] Center 33 (3~64) winsize 62
4175 19:52:54.357887 [CA 3] Center 33 (2~64) winsize 63
4176 19:52:54.360938 [CA 4] Center 32 (2~63) winsize 62
4177 19:52:54.364266 [CA 5] Center 32 (2~63) winsize 62
4178 19:52:54.364680
4179 19:52:54.367843 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4180 19:52:54.368302
4181 19:52:54.371312 [CATrainingPosCal] consider 2 rank data
4182 19:52:54.374650 u2DelayCellTimex100 = 270/100 ps
4183 19:52:54.377389 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4184 19:52:54.384313 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4185 19:52:54.387597 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4186 19:52:54.391256 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4187 19:52:54.394460 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4188 19:52:54.398058 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4189 19:52:54.398576
4190 19:52:54.400913 CA PerBit enable=1, Macro0, CA PI delay=32
4191 19:52:54.401325
4192 19:52:54.404849 [CBTSetCACLKResult] CA Dly = 32
4193 19:52:54.405495 CS Dly: 4 (0~36)
4194 19:52:54.405991
4195 19:52:54.408050 ----->DramcWriteLeveling(PI) begin...
4196 19:52:54.411774 ==
4197 19:52:54.414371 Dram Type= 6, Freq= 0, CH_1, rank 0
4198 19:52:54.417472 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4199 19:52:54.417891 ==
4200 19:52:54.420890 Write leveling (Byte 0): 28 => 28
4201 19:52:54.424498 Write leveling (Byte 1): 29 => 29
4202 19:52:54.427373 DramcWriteLeveling(PI) end<-----
4203 19:52:54.427783
4204 19:52:54.428111 ==
4205 19:52:54.430909 Dram Type= 6, Freq= 0, CH_1, rank 0
4206 19:52:54.434197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4207 19:52:54.434614 ==
4208 19:52:54.437705 [Gating] SW mode calibration
4209 19:52:54.444580 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4210 19:52:54.450727 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4211 19:52:54.454230 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4212 19:52:54.457375 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 1)
4213 19:52:54.460602 0 5 8 | B1->B0 | 2f2f 2929 | 1 0 | (1 0) (0 0)
4214 19:52:54.467267 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 19:52:54.470608 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 19:52:54.474599 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 19:52:54.480781 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 19:52:54.484121 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 19:52:54.487188 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 19:52:54.493833 0 6 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
4221 19:52:54.497463 0 6 8 | B1->B0 | 3434 3f3f | 0 0 | (0 0) (0 0)
4222 19:52:54.500459 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 19:52:54.507365 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 19:52:54.510347 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 19:52:54.513585 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 19:52:54.520404 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 19:52:54.523905 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 19:52:54.527105 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4229 19:52:54.533606 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4230 19:52:54.537207 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4231 19:52:54.540170 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 19:52:54.546778 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 19:52:54.550107 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 19:52:54.553577 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 19:52:54.560336 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 19:52:54.563630 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 19:52:54.566667 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 19:52:54.573657 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 19:52:54.576732 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 19:52:54.579852 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 19:52:54.586484 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 19:52:54.589983 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 19:52:54.593188 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 19:52:54.600149 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4245 19:52:54.603263 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4246 19:52:54.606785 Total UI for P1: 0, mck2ui 16
4247 19:52:54.610186 best dqsien dly found for B0: ( 0, 9, 4)
4248 19:52:54.613339 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 19:52:54.617063 Total UI for P1: 0, mck2ui 16
4250 19:52:54.620299 best dqsien dly found for B1: ( 0, 9, 8)
4251 19:52:54.623402 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4252 19:52:54.626300 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4253 19:52:54.626711
4254 19:52:54.630114 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4255 19:52:54.636718 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4256 19:52:54.637234 [Gating] SW calibration Done
4257 19:52:54.637572 ==
4258 19:52:54.639895 Dram Type= 6, Freq= 0, CH_1, rank 0
4259 19:52:54.646219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4260 19:52:54.646630 ==
4261 19:52:54.646959 RX Vref Scan: 0
4262 19:52:54.647263
4263 19:52:54.649917 RX Vref 0 -> 0, step: 1
4264 19:52:54.650433
4265 19:52:54.652975 RX Delay -230 -> 252, step: 16
4266 19:52:54.656538 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4267 19:52:54.659538 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4268 19:52:54.666238 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4269 19:52:54.669502 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4270 19:52:54.672856 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4271 19:52:54.676702 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4272 19:52:54.679224 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4273 19:52:54.686622 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4274 19:52:54.689388 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4275 19:52:54.692782 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4276 19:52:54.695801 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4277 19:52:54.702539 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4278 19:52:54.706060 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4279 19:52:54.709468 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4280 19:52:54.713028 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4281 19:52:54.719618 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4282 19:52:54.720139 ==
4283 19:52:54.722395 Dram Type= 6, Freq= 0, CH_1, rank 0
4284 19:52:54.725682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4285 19:52:54.726097 ==
4286 19:52:54.726426 DQS Delay:
4287 19:52:54.729461 DQS0 = 0, DQS1 = 0
4288 19:52:54.729975 DQM Delay:
4289 19:52:54.732690 DQM0 = 41, DQM1 = 33
4290 19:52:54.733205 DQ Delay:
4291 19:52:54.736166 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4292 19:52:54.739518 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4293 19:52:54.742628 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4294 19:52:54.746085 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4295 19:52:54.746500
4296 19:52:54.746829
4297 19:52:54.747133 ==
4298 19:52:54.748974 Dram Type= 6, Freq= 0, CH_1, rank 0
4299 19:52:54.752332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4300 19:52:54.752742 ==
4301 19:52:54.753066
4302 19:52:54.755568
4303 19:52:54.755968 TX Vref Scan disable
4304 19:52:54.758799 == TX Byte 0 ==
4305 19:52:54.762160 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4306 19:52:54.765416 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4307 19:52:54.768842 == TX Byte 1 ==
4308 19:52:54.772042 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4309 19:52:54.775511 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4310 19:52:54.776015 ==
4311 19:52:54.778818 Dram Type= 6, Freq= 0, CH_1, rank 0
4312 19:52:54.785585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4313 19:52:54.786092 ==
4314 19:52:54.786417
4315 19:52:54.786714
4316 19:52:54.787070 TX Vref Scan disable
4317 19:52:54.789786 == TX Byte 0 ==
4318 19:52:54.793318 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4319 19:52:54.800034 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4320 19:52:54.800594 == TX Byte 1 ==
4321 19:52:54.803107 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4322 19:52:54.810133 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4323 19:52:54.810542
4324 19:52:54.810865 [DATLAT]
4325 19:52:54.811163 Freq=600, CH1 RK0
4326 19:52:54.811551
4327 19:52:54.813602 DATLAT Default: 0x9
4328 19:52:54.814118 0, 0xFFFF, sum = 0
4329 19:52:54.816684 1, 0xFFFF, sum = 0
4330 19:52:54.817193 2, 0xFFFF, sum = 0
4331 19:52:54.820160 3, 0xFFFF, sum = 0
4332 19:52:54.823172 4, 0xFFFF, sum = 0
4333 19:52:54.823589 5, 0xFFFF, sum = 0
4334 19:52:54.826259 6, 0xFFFF, sum = 0
4335 19:52:54.826669 7, 0x0, sum = 1
4336 19:52:54.826997 8, 0x0, sum = 2
4337 19:52:54.830166 9, 0x0, sum = 3
4338 19:52:54.830676 10, 0x0, sum = 4
4339 19:52:54.833116 best_step = 8
4340 19:52:54.833607
4341 19:52:54.833932 ==
4342 19:52:54.836509 Dram Type= 6, Freq= 0, CH_1, rank 0
4343 19:52:54.839907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4344 19:52:54.840476 ==
4345 19:52:54.843259 RX Vref Scan: 1
4346 19:52:54.843753
4347 19:52:54.844079 RX Vref 0 -> 0, step: 1
4348 19:52:54.844445
4349 19:52:54.846472 RX Delay -195 -> 252, step: 8
4350 19:52:54.846957
4351 19:52:54.849989 Set Vref, RX VrefLevel [Byte0]: 53
4352 19:52:54.853139 [Byte1]: 49
4353 19:52:54.857251
4354 19:52:54.857748 Final RX Vref Byte 0 = 53 to rank0
4355 19:52:54.860512 Final RX Vref Byte 1 = 49 to rank0
4356 19:52:54.863692 Final RX Vref Byte 0 = 53 to rank1
4357 19:52:54.867509 Final RX Vref Byte 1 = 49 to rank1==
4358 19:52:54.870544 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 19:52:54.877354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4360 19:52:54.877900 ==
4361 19:52:54.878260 DQS Delay:
4362 19:52:54.878594 DQS0 = 0, DQS1 = 0
4363 19:52:54.880125 DQM Delay:
4364 19:52:54.880631 DQM0 = 38, DQM1 = 31
4365 19:52:54.883922 DQ Delay:
4366 19:52:54.887227 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4367 19:52:54.887775 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4368 19:52:54.890721 DQ8 =12, DQ9 =20, DQ10 =36, DQ11 =24
4369 19:52:54.897494 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4370 19:52:54.898050
4371 19:52:54.898412
4372 19:52:54.903396 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e7e, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4373 19:52:54.906835 CH1 RK0: MR19=808, MR18=7E7E
4374 19:52:54.913461 CH1_RK0: MR19=0x808, MR18=0x7E7E, DQSOSC=386, MR23=63, INC=176, DEC=117
4375 19:52:54.913916
4376 19:52:54.916630 ----->DramcWriteLeveling(PI) begin...
4377 19:52:54.917089 ==
4378 19:52:54.920407 Dram Type= 6, Freq= 0, CH_1, rank 1
4379 19:52:54.923457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4380 19:52:54.923913 ==
4381 19:52:54.926702 Write leveling (Byte 0): 27 => 27
4382 19:52:54.930246 Write leveling (Byte 1): 27 => 27
4383 19:52:54.933448 DramcWriteLeveling(PI) end<-----
4384 19:52:54.934027
4385 19:52:54.934405 ==
4386 19:52:54.936484 Dram Type= 6, Freq= 0, CH_1, rank 1
4387 19:52:54.940404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4388 19:52:54.940955 ==
4389 19:52:54.943343 [Gating] SW mode calibration
4390 19:52:54.950431 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4391 19:52:54.956781 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4392 19:52:54.960150 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4393 19:52:54.967082 0 5 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
4394 19:52:54.970429 0 5 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4395 19:52:54.973768 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4396 19:52:54.977021 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4397 19:52:54.983190 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 19:52:54.986719 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 19:52:54.989669 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 19:52:54.996612 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 19:52:55.000289 0 6 4 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 0)
4402 19:52:55.003582 0 6 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4403 19:52:55.010297 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4404 19:52:55.013136 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 19:52:55.016579 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 19:52:55.023328 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 19:52:55.026232 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 19:52:55.030022 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4409 19:52:55.036234 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4410 19:52:55.039381 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4411 19:52:55.043071 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 19:52:55.049586 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 19:52:55.052661 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 19:52:55.056128 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 19:52:55.062783 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 19:52:55.066096 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 19:52:55.069520 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 19:52:55.076131 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 19:52:55.079669 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 19:52:55.082346 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 19:52:55.089324 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 19:52:55.092651 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 19:52:55.096089 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 19:52:55.102670 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 19:52:55.105581 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4426 19:52:55.109388 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 19:52:55.112141 Total UI for P1: 0, mck2ui 16
4428 19:52:55.115662 best dqsien dly found for B0: ( 0, 9, 4)
4429 19:52:55.118923 Total UI for P1: 0, mck2ui 16
4430 19:52:55.122380 best dqsien dly found for B1: ( 0, 9, 6)
4431 19:52:55.125438 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4432 19:52:55.129075 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4433 19:52:55.129620
4434 19:52:55.135376 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4435 19:52:55.138856 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4436 19:52:55.139405 [Gating] SW calibration Done
4437 19:52:55.142068 ==
4438 19:52:55.145178 Dram Type= 6, Freq= 0, CH_1, rank 1
4439 19:52:55.148853 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4440 19:52:55.149415 ==
4441 19:52:55.149791 RX Vref Scan: 0
4442 19:52:55.150136
4443 19:52:55.151618 RX Vref 0 -> 0, step: 1
4444 19:52:55.152075
4445 19:52:55.155257 RX Delay -230 -> 252, step: 16
4446 19:52:55.158674 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4447 19:52:55.161670 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4448 19:52:55.168402 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4449 19:52:55.171613 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4450 19:52:55.175268 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4451 19:52:55.178245 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4452 19:52:55.184891 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4453 19:52:55.188367 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4454 19:52:55.191431 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4455 19:52:55.195047 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4456 19:52:55.198535 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4457 19:52:55.204828 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4458 19:52:55.208354 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4459 19:52:55.211652 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4460 19:52:55.214680 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4461 19:52:55.221467 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4462 19:52:55.221942 ==
4463 19:52:55.224924 Dram Type= 6, Freq= 0, CH_1, rank 1
4464 19:52:55.228387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4465 19:52:55.228960 ==
4466 19:52:55.229447 DQS Delay:
4467 19:52:55.231582 DQS0 = 0, DQS1 = 0
4468 19:52:55.232143 DQM Delay:
4469 19:52:55.235077 DQM0 = 39, DQM1 = 33
4470 19:52:55.235646 DQ Delay:
4471 19:52:55.238102 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4472 19:52:55.241317 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4473 19:52:55.244741 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4474 19:52:55.248130 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4475 19:52:55.248779
4476 19:52:55.249423
4477 19:52:55.249890 ==
4478 19:52:55.251244 Dram Type= 6, Freq= 0, CH_1, rank 1
4479 19:52:55.254716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4480 19:52:55.258026 ==
4481 19:52:55.258575
4482 19:52:55.258940
4483 19:52:55.259279 TX Vref Scan disable
4484 19:52:55.261429 == TX Byte 0 ==
4485 19:52:55.264997 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4486 19:52:55.267950 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4487 19:52:55.270920 == TX Byte 1 ==
4488 19:52:55.274591 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4489 19:52:55.277630 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4490 19:52:55.280829 ==
4491 19:52:55.284304 Dram Type= 6, Freq= 0, CH_1, rank 1
4492 19:52:55.287542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4493 19:52:55.288103 ==
4494 19:52:55.288530
4495 19:52:55.288874
4496 19:52:55.290879 TX Vref Scan disable
4497 19:52:55.291451 == TX Byte 0 ==
4498 19:52:55.297411 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4499 19:52:55.300773 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4500 19:52:55.304287 == TX Byte 1 ==
4501 19:52:55.308151 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4502 19:52:55.310676 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4503 19:52:55.311226
4504 19:52:55.311586 [DATLAT]
4505 19:52:55.313950 Freq=600, CH1 RK1
4506 19:52:55.314403
4507 19:52:55.314762 DATLAT Default: 0x8
4508 19:52:55.317235 0, 0xFFFF, sum = 0
4509 19:52:55.321141 1, 0xFFFF, sum = 0
4510 19:52:55.321719 2, 0xFFFF, sum = 0
4511 19:52:55.323641 3, 0xFFFF, sum = 0
4512 19:52:55.324096 4, 0xFFFF, sum = 0
4513 19:52:55.327166 5, 0xFFFF, sum = 0
4514 19:52:55.327625 6, 0xFFFF, sum = 0
4515 19:52:55.330703 7, 0x0, sum = 1
4516 19:52:55.331159 8, 0x0, sum = 2
4517 19:52:55.331527 9, 0x0, sum = 3
4518 19:52:55.333898 10, 0x0, sum = 4
4519 19:52:55.334478 best_step = 8
4520 19:52:55.334866
4521 19:52:55.335204 ==
4522 19:52:55.336950 Dram Type= 6, Freq= 0, CH_1, rank 1
4523 19:52:55.343624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4524 19:52:55.344158 ==
4525 19:52:55.344632 RX Vref Scan: 0
4526 19:52:55.344979
4527 19:52:55.347423 RX Vref 0 -> 0, step: 1
4528 19:52:55.348005
4529 19:52:55.350296 RX Delay -195 -> 252, step: 8
4530 19:52:55.353463 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4531 19:52:55.360337 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4532 19:52:55.363598 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4533 19:52:55.366930 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4534 19:52:55.370302 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4535 19:52:55.376869 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4536 19:52:55.380266 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4537 19:52:55.383727 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4538 19:52:55.386629 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4539 19:52:55.389952 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4540 19:52:55.396738 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4541 19:52:55.399934 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4542 19:52:55.403362 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4543 19:52:55.406808 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4544 19:52:55.413054 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4545 19:52:55.416726 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4546 19:52:55.417277 ==
4547 19:52:55.419901 Dram Type= 6, Freq= 0, CH_1, rank 1
4548 19:52:55.423099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4549 19:52:55.423650 ==
4550 19:52:55.426137 DQS Delay:
4551 19:52:55.426587 DQS0 = 0, DQS1 = 0
4552 19:52:55.429652 DQM Delay:
4553 19:52:55.430208 DQM0 = 36, DQM1 = 28
4554 19:52:55.430573 DQ Delay:
4555 19:52:55.432880 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4556 19:52:55.436151 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4557 19:52:55.439749 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4558 19:52:55.443059 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4559 19:52:55.443607
4560 19:52:55.443969
4561 19:52:55.452890 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4562 19:52:55.456291 CH1 RK1: MR19=808, MR18=5E5E
4563 19:52:55.462965 CH1_RK1: MR19=0x808, MR18=0x5E5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4564 19:52:55.463535 [RxdqsGatingPostProcess] freq 600
4565 19:52:55.469654 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4566 19:52:55.472667 Pre-setting of DQS Precalculation
4567 19:52:55.476422 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4568 19:52:55.486396 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4569 19:52:55.492916 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4570 19:52:55.493495
4571 19:52:55.493984
4572 19:52:55.495880 [Calibration Summary] 1200 Mbps
4573 19:52:55.496423 CH 0, Rank 0
4574 19:52:55.499407 SW Impedance : PASS
4575 19:52:55.499971 DUTY Scan : NO K
4576 19:52:55.502524 ZQ Calibration : PASS
4577 19:52:55.505997 Jitter Meter : NO K
4578 19:52:55.506630 CBT Training : PASS
4579 19:52:55.508811 Write leveling : PASS
4580 19:52:55.512646 RX DQS gating : PASS
4581 19:52:55.513210 RX DQ/DQS(RDDQC) : PASS
4582 19:52:55.515638 TX DQ/DQS : PASS
4583 19:52:55.519025 RX DATLAT : PASS
4584 19:52:55.519577 RX DQ/DQS(Engine): PASS
4585 19:52:55.522154 TX OE : NO K
4586 19:52:55.522607 All Pass.
4587 19:52:55.523002
4588 19:52:55.525630 CH 0, Rank 1
4589 19:52:55.526180 SW Impedance : PASS
4590 19:52:55.529053 DUTY Scan : NO K
4591 19:52:55.532068 ZQ Calibration : PASS
4592 19:52:55.532600 Jitter Meter : NO K
4593 19:52:55.535741 CBT Training : PASS
4594 19:52:55.538865 Write leveling : PASS
4595 19:52:55.539412 RX DQS gating : PASS
4596 19:52:55.542373 RX DQ/DQS(RDDQC) : PASS
4597 19:52:55.545820 TX DQ/DQS : PASS
4598 19:52:55.546374 RX DATLAT : PASS
4599 19:52:55.548557 RX DQ/DQS(Engine): PASS
4600 19:52:55.549006 TX OE : NO K
4601 19:52:55.552137 All Pass.
4602 19:52:55.552633
4603 19:52:55.552996 CH 1, Rank 0
4604 19:52:55.555756 SW Impedance : PASS
4605 19:52:55.556360 DUTY Scan : NO K
4606 19:52:55.559196 ZQ Calibration : PASS
4607 19:52:55.562105 Jitter Meter : NO K
4608 19:52:55.562663 CBT Training : PASS
4609 19:52:55.565593 Write leveling : PASS
4610 19:52:55.568403 RX DQS gating : PASS
4611 19:52:55.568860 RX DQ/DQS(RDDQC) : PASS
4612 19:52:55.572490 TX DQ/DQS : PASS
4613 19:52:55.575306 RX DATLAT : PASS
4614 19:52:55.575849 RX DQ/DQS(Engine): PASS
4615 19:52:55.578906 TX OE : NO K
4616 19:52:55.579448 All Pass.
4617 19:52:55.579810
4618 19:52:55.581779 CH 1, Rank 1
4619 19:52:55.582244 SW Impedance : PASS
4620 19:52:55.585020 DUTY Scan : NO K
4621 19:52:55.588851 ZQ Calibration : PASS
4622 19:52:55.589408 Jitter Meter : NO K
4623 19:52:55.592143 CBT Training : PASS
4624 19:52:55.595345 Write leveling : PASS
4625 19:52:55.595895 RX DQS gating : PASS
4626 19:52:55.598490 RX DQ/DQS(RDDQC) : PASS
4627 19:52:55.601817 TX DQ/DQS : PASS
4628 19:52:55.602369 RX DATLAT : PASS
4629 19:52:55.605211 RX DQ/DQS(Engine): PASS
4630 19:52:55.608534 TX OE : NO K
4631 19:52:55.609090 All Pass.
4632 19:52:55.609451
4633 19:52:55.609788 DramC Write-DBI off
4634 19:52:55.611925 PER_BANK_REFRESH: Hybrid Mode
4635 19:52:55.614892 TX_TRACKING: ON
4636 19:52:55.621710 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4637 19:52:55.624974 [FAST_K] Save calibration result to emmc
4638 19:52:55.631592 dramc_set_vcore_voltage set vcore to 662500
4639 19:52:55.632155 Read voltage for 933, 3
4640 19:52:55.634777 Vio18 = 0
4641 19:52:55.635310 Vcore = 662500
4642 19:52:55.635736 Vdram = 0
4643 19:52:55.636075 Vddq = 0
4644 19:52:55.638023 Vmddr = 0
4645 19:52:55.641417 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4646 19:52:55.648110 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4647 19:52:55.651298 MEM_TYPE=3, freq_sel=17
4648 19:52:55.652292 sv_algorithm_assistance_LP4_1600
4649 19:52:55.658096 ============ PULL DRAM RESETB DOWN ============
4650 19:52:55.661035 ========== PULL DRAM RESETB DOWN end =========
4651 19:52:55.664614 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4652 19:52:55.667892 ===================================
4653 19:52:55.670869 LPDDR4 DRAM CONFIGURATION
4654 19:52:55.674547 ===================================
4655 19:52:55.677517 EX_ROW_EN[0] = 0x0
4656 19:52:55.677972 EX_ROW_EN[1] = 0x0
4657 19:52:55.680850 LP4Y_EN = 0x0
4658 19:52:55.681332 WORK_FSP = 0x0
4659 19:52:55.684438 WL = 0x3
4660 19:52:55.685066 RL = 0x3
4661 19:52:55.687756 BL = 0x2
4662 19:52:55.688246 RPST = 0x0
4663 19:52:55.691299 RD_PRE = 0x0
4664 19:52:55.691849 WR_PRE = 0x1
4665 19:52:55.694306 WR_PST = 0x0
4666 19:52:55.694754 DBI_WR = 0x0
4667 19:52:55.697755 DBI_RD = 0x0
4668 19:52:55.701257 OTF = 0x1
4669 19:52:55.701814 ===================================
4670 19:52:55.704408 ===================================
4671 19:52:55.707780 ANA top config
4672 19:52:55.711177 ===================================
4673 19:52:55.714404 DLL_ASYNC_EN = 0
4674 19:52:55.714955 ALL_SLAVE_EN = 1
4675 19:52:55.717926 NEW_RANK_MODE = 1
4676 19:52:55.721153 DLL_IDLE_MODE = 1
4677 19:52:55.724441 LP45_APHY_COMB_EN = 1
4678 19:52:55.727794 TX_ODT_DIS = 1
4679 19:52:55.728392 NEW_8X_MODE = 1
4680 19:52:55.730908 ===================================
4681 19:52:55.734174 ===================================
4682 19:52:55.738121 data_rate = 1866
4683 19:52:55.740903 CKR = 1
4684 19:52:55.744351 DQ_P2S_RATIO = 8
4685 19:52:55.747547 ===================================
4686 19:52:55.750972 CA_P2S_RATIO = 8
4687 19:52:55.754434 DQ_CA_OPEN = 0
4688 19:52:55.754889 DQ_SEMI_OPEN = 0
4689 19:52:55.757476 CA_SEMI_OPEN = 0
4690 19:52:55.761043 CA_FULL_RATE = 0
4691 19:52:55.764043 DQ_CKDIV4_EN = 1
4692 19:52:55.767412 CA_CKDIV4_EN = 1
4693 19:52:55.770654 CA_PREDIV_EN = 0
4694 19:52:55.771106 PH8_DLY = 0
4695 19:52:55.774353 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4696 19:52:55.777187 DQ_AAMCK_DIV = 4
4697 19:52:55.780464 CA_AAMCK_DIV = 4
4698 19:52:55.783931 CA_ADMCK_DIV = 4
4699 19:52:55.787444 DQ_TRACK_CA_EN = 0
4700 19:52:55.787996 CA_PICK = 933
4701 19:52:55.790490 CA_MCKIO = 933
4702 19:52:55.793892 MCKIO_SEMI = 0
4703 19:52:55.797358 PLL_FREQ = 3732
4704 19:52:55.800636 DQ_UI_PI_RATIO = 32
4705 19:52:55.804018 CA_UI_PI_RATIO = 0
4706 19:52:55.807526 ===================================
4707 19:52:55.810864 ===================================
4708 19:52:55.811417 memory_type:LPDDR4
4709 19:52:55.814119 GP_NUM : 10
4710 19:52:55.817300 SRAM_EN : 1
4711 19:52:55.817758 MD32_EN : 0
4712 19:52:55.820927 ===================================
4713 19:52:55.823799 [ANA_INIT] >>>>>>>>>>>>>>
4714 19:52:55.827343 <<<<<< [CONFIGURE PHASE]: ANA_TX
4715 19:52:55.830703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4716 19:52:55.833620 ===================================
4717 19:52:55.837073 data_rate = 1866,PCW = 0X8f00
4718 19:52:55.840780 ===================================
4719 19:52:55.843786 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4720 19:52:55.847447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4721 19:52:55.854032 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4722 19:52:55.856819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4723 19:52:55.860453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4724 19:52:55.863686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4725 19:52:55.866951 [ANA_INIT] flow start
4726 19:52:55.870461 [ANA_INIT] PLL >>>>>>>>
4727 19:52:55.871030 [ANA_INIT] PLL <<<<<<<<
4728 19:52:55.873651 [ANA_INIT] MIDPI >>>>>>>>
4729 19:52:55.876724 [ANA_INIT] MIDPI <<<<<<<<
4730 19:52:55.879981 [ANA_INIT] DLL >>>>>>>>
4731 19:52:55.880497 [ANA_INIT] flow end
4732 19:52:55.883317 ============ LP4 DIFF to SE enter ============
4733 19:52:55.890078 ============ LP4 DIFF to SE exit ============
4734 19:52:55.890619 [ANA_INIT] <<<<<<<<<<<<<
4735 19:52:55.893950 [Flow] Enable top DCM control >>>>>
4736 19:52:55.897134 [Flow] Enable top DCM control <<<<<
4737 19:52:55.900397 Enable DLL master slave shuffle
4738 19:52:55.906797 ==============================================================
4739 19:52:55.907350 Gating Mode config
4740 19:52:55.913359 ==============================================================
4741 19:52:55.916357 Config description:
4742 19:52:55.926972 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4743 19:52:55.933249 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4744 19:52:55.936271 SELPH_MODE 0: By rank 1: By Phase
4745 19:52:55.943048 ==============================================================
4746 19:52:55.946016 GAT_TRACK_EN = 1
4747 19:52:55.946201 RX_GATING_MODE = 2
4748 19:52:55.949649 RX_GATING_TRACK_MODE = 2
4749 19:52:55.952773 SELPH_MODE = 1
4750 19:52:55.956028 PICG_EARLY_EN = 1
4751 19:52:55.959409 VALID_LAT_VALUE = 1
4752 19:52:55.965919 ==============================================================
4753 19:52:55.969296 Enter into Gating configuration >>>>
4754 19:52:55.972678 Exit from Gating configuration <<<<
4755 19:52:55.976180 Enter into DVFS_PRE_config >>>>>
4756 19:52:55.986155 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4757 19:52:55.989419 Exit from DVFS_PRE_config <<<<<
4758 19:52:55.992990 Enter into PICG configuration >>>>
4759 19:52:55.996597 Exit from PICG configuration <<<<
4760 19:52:55.999652 [RX_INPUT] configuration >>>>>
4761 19:52:56.003296 [RX_INPUT] configuration <<<<<
4762 19:52:56.006181 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4763 19:52:56.012728 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4764 19:52:56.019347 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4765 19:52:56.022455 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4766 19:52:56.029196 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4767 19:52:56.035796 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4768 19:52:56.039212 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4769 19:52:56.042431 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4770 19:52:56.049432 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4771 19:52:56.052527 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4772 19:52:56.055859 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4773 19:52:56.062582 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4774 19:52:56.066179 ===================================
4775 19:52:56.066426 LPDDR4 DRAM CONFIGURATION
4776 19:52:56.069354 ===================================
4777 19:52:56.072387 EX_ROW_EN[0] = 0x0
4778 19:52:56.075636 EX_ROW_EN[1] = 0x0
4779 19:52:56.075870 LP4Y_EN = 0x0
4780 19:52:56.079153 WORK_FSP = 0x0
4781 19:52:56.079470 WL = 0x3
4782 19:52:56.082266 RL = 0x3
4783 19:52:56.082572 BL = 0x2
4784 19:52:56.085926 RPST = 0x0
4785 19:52:56.086572 RD_PRE = 0x0
4786 19:52:56.089291 WR_PRE = 0x1
4787 19:52:56.089667 WR_PST = 0x0
4788 19:52:56.092542 DBI_WR = 0x0
4789 19:52:56.092995 DBI_RD = 0x0
4790 19:52:56.096104 OTF = 0x1
4791 19:52:56.099456 ===================================
4792 19:52:56.102886 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4793 19:52:56.105693 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4794 19:52:56.112459 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4795 19:52:56.116138 ===================================
4796 19:52:56.116735 LPDDR4 DRAM CONFIGURATION
4797 19:52:56.118998 ===================================
4798 19:52:56.122657 EX_ROW_EN[0] = 0x10
4799 19:52:56.125504 EX_ROW_EN[1] = 0x0
4800 19:52:56.125958 LP4Y_EN = 0x0
4801 19:52:56.129570 WORK_FSP = 0x0
4802 19:52:56.130126 WL = 0x3
4803 19:52:56.132342 RL = 0x3
4804 19:52:56.132891 BL = 0x2
4805 19:52:56.135859 RPST = 0x0
4806 19:52:56.136473 RD_PRE = 0x0
4807 19:52:56.138838 WR_PRE = 0x1
4808 19:52:56.139302 WR_PST = 0x0
4809 19:52:56.142234 DBI_WR = 0x0
4810 19:52:56.142782 DBI_RD = 0x0
4811 19:52:56.145773 OTF = 0x1
4812 19:52:56.148965 ===================================
4813 19:52:56.155183 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4814 19:52:56.159059 nWR fixed to 30
4815 19:52:56.159611 [ModeRegInit_LP4] CH0 RK0
4816 19:52:56.162236 [ModeRegInit_LP4] CH0 RK1
4817 19:52:56.165840 [ModeRegInit_LP4] CH1 RK0
4818 19:52:56.168572 [ModeRegInit_LP4] CH1 RK1
4819 19:52:56.169022 match AC timing 8
4820 19:52:56.172534 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4821 19:52:56.178894 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4822 19:52:56.181956 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4823 19:52:56.188564 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4824 19:52:56.191844 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4825 19:52:56.192461 ==
4826 19:52:56.195353 Dram Type= 6, Freq= 0, CH_0, rank 0
4827 19:52:56.198770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4828 19:52:56.199331 ==
4829 19:52:56.205136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4830 19:52:56.211780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4831 19:52:56.215111 [CA 0] Center 39 (8~70) winsize 63
4832 19:52:56.219029 [CA 1] Center 39 (8~70) winsize 63
4833 19:52:56.221871 [CA 2] Center 36 (6~67) winsize 62
4834 19:52:56.224868 [CA 3] Center 35 (5~66) winsize 62
4835 19:52:56.228252 [CA 4] Center 35 (5~65) winsize 61
4836 19:52:56.231732 [CA 5] Center 34 (4~65) winsize 62
4837 19:52:56.232313
4838 19:52:56.235142 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4839 19:52:56.235690
4840 19:52:56.238111 [CATrainingPosCal] consider 1 rank data
4841 19:52:56.241713 u2DelayCellTimex100 = 270/100 ps
4842 19:52:56.244732 CA0 delay=39 (8~70),Diff = 5 PI (31 cell)
4843 19:52:56.248315 CA1 delay=39 (8~70),Diff = 5 PI (31 cell)
4844 19:52:56.251446 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4845 19:52:56.254650 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4846 19:52:56.258151 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4847 19:52:56.261538 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4848 19:52:56.262148
4849 19:52:56.268475 CA PerBit enable=1, Macro0, CA PI delay=34
4850 19:52:56.269025
4851 19:52:56.269388 [CBTSetCACLKResult] CA Dly = 34
4852 19:52:56.271352 CS Dly: 7 (0~38)
4853 19:52:56.271805 ==
4854 19:52:56.274580 Dram Type= 6, Freq= 0, CH_0, rank 1
4855 19:52:56.278121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4856 19:52:56.278674 ==
4857 19:52:56.284570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4858 19:52:56.291178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4859 19:52:56.294562 [CA 0] Center 38 (8~69) winsize 62
4860 19:52:56.298038 [CA 1] Center 38 (7~69) winsize 63
4861 19:52:56.300998 [CA 2] Center 35 (5~66) winsize 62
4862 19:52:56.304459 [CA 3] Center 35 (5~66) winsize 62
4863 19:52:56.308074 [CA 4] Center 34 (3~65) winsize 63
4864 19:52:56.311477 [CA 5] Center 34 (4~65) winsize 62
4865 19:52:56.312027
4866 19:52:56.314825 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4867 19:52:56.315374
4868 19:52:56.317904 [CATrainingPosCal] consider 2 rank data
4869 19:52:56.321389 u2DelayCellTimex100 = 270/100 ps
4870 19:52:56.324670 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4871 19:52:56.328122 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4872 19:52:56.331187 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
4873 19:52:56.334467 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4874 19:52:56.338247 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4875 19:52:56.341459 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4876 19:52:56.344320
4877 19:52:56.347901 CA PerBit enable=1, Macro0, CA PI delay=34
4878 19:52:56.348498
4879 19:52:56.350712 [CBTSetCACLKResult] CA Dly = 34
4880 19:52:56.351164 CS Dly: 7 (0~39)
4881 19:52:56.351596
4882 19:52:56.354146 ----->DramcWriteLeveling(PI) begin...
4883 19:52:56.354703 ==
4884 19:52:56.357686 Dram Type= 6, Freq= 0, CH_0, rank 0
4885 19:52:56.360587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4886 19:52:56.363808 ==
4887 19:52:56.364295 Write leveling (Byte 0): 31 => 31
4888 19:52:56.367089 Write leveling (Byte 1): 25 => 25
4889 19:52:56.371325 DramcWriteLeveling(PI) end<-----
4890 19:52:56.371872
4891 19:52:56.372309 ==
4892 19:52:56.373912 Dram Type= 6, Freq= 0, CH_0, rank 0
4893 19:52:56.380579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4894 19:52:56.381127 ==
4895 19:52:56.383715 [Gating] SW mode calibration
4896 19:52:56.391043 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4897 19:52:56.394168 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4898 19:52:56.400715 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4899 19:52:56.404446 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4900 19:52:56.407407 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4901 19:52:56.413816 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4902 19:52:56.417318 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4903 19:52:56.420611 0 10 20 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
4904 19:52:56.426903 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4905 19:52:56.430559 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4906 19:52:56.433820 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4907 19:52:56.440483 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4908 19:52:56.443976 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4909 19:52:56.446926 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4910 19:52:56.450231 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4911 19:52:56.457138 0 11 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4912 19:52:56.460271 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4913 19:52:56.465447 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4914 19:52:56.470354 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4915 19:52:56.473611 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4916 19:52:56.477155 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4917 19:52:56.483305 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4918 19:52:56.486713 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4919 19:52:56.490075 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4920 19:52:56.496549 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4921 19:52:56.499857 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4922 19:52:56.503417 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4923 19:52:56.510000 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4924 19:52:56.513145 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4925 19:52:56.516625 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4926 19:52:56.522906 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4927 19:52:56.526438 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4928 19:52:56.529476 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4929 19:52:56.535849 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 19:52:56.539292 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 19:52:56.542467 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 19:52:56.549382 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 19:52:56.552827 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 19:52:56.556201 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 19:52:56.562343 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 19:52:56.565881 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4937 19:52:56.569185 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4938 19:52:56.572153 Total UI for P1: 0, mck2ui 16
4939 19:52:56.575558 best dqsien dly found for B0: ( 0, 14, 24)
4940 19:52:56.578836 Total UI for P1: 0, mck2ui 16
4941 19:52:56.582350 best dqsien dly found for B1: ( 0, 14, 24)
4942 19:52:56.585551 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
4943 19:52:56.588736 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
4944 19:52:56.588815
4945 19:52:56.595439 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 24)
4946 19:52:56.598742 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
4947 19:52:56.601958 [Gating] SW calibration Done
4948 19:52:56.602036 ==
4949 19:52:56.605216 Dram Type= 6, Freq= 0, CH_0, rank 0
4950 19:52:56.608572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4951 19:52:56.608651 ==
4952 19:52:56.608715 RX Vref Scan: 0
4953 19:52:56.608774
4954 19:52:56.611816 RX Vref 0 -> 0, step: 1
4955 19:52:56.611895
4956 19:52:56.615415 RX Delay -80 -> 252, step: 8
4957 19:52:56.618429 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4958 19:52:56.621988 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4959 19:52:56.625227 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4960 19:52:56.631650 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4961 19:52:56.635143 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4962 19:52:56.638303 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4963 19:52:56.641625 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4964 19:52:56.645076 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4965 19:52:56.651666 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4966 19:52:56.655097 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4967 19:52:56.658099 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4968 19:52:56.661558 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4969 19:52:56.664982 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4970 19:52:56.671448 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4971 19:52:56.674731 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
4972 19:52:56.677993 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4973 19:52:56.678064 ==
4974 19:52:56.681451 Dram Type= 6, Freq= 0, CH_0, rank 0
4975 19:52:56.684674 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4976 19:52:56.684747 ==
4977 19:52:56.687845 DQS Delay:
4978 19:52:56.687916 DQS0 = 0, DQS1 = 0
4979 19:52:56.691330 DQM Delay:
4980 19:52:56.691431 DQM0 = 95, DQM1 = 84
4981 19:52:56.691519 DQ Delay:
4982 19:52:56.694678 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
4983 19:52:56.698229 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
4984 19:52:56.701254 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
4985 19:52:56.704621 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
4986 19:52:56.704716
4987 19:52:56.704812
4988 19:52:56.708148 ==
4989 19:52:56.708236 Dram Type= 6, Freq= 0, CH_0, rank 0
4990 19:52:56.714665 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4991 19:52:56.714738 ==
4992 19:52:56.714805
4993 19:52:56.714870
4994 19:52:56.717742 TX Vref Scan disable
4995 19:52:56.717811 == TX Byte 0 ==
4996 19:52:56.724323 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
4997 19:52:56.727529 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
4998 19:52:56.727614 == TX Byte 1 ==
4999 19:52:56.734356 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5000 19:52:56.737480 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5001 19:52:56.737556 ==
5002 19:52:56.740883 Dram Type= 6, Freq= 0, CH_0, rank 0
5003 19:52:56.744091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5004 19:52:56.744199 ==
5005 19:52:56.744291
5006 19:52:56.744378
5007 19:52:56.747427 TX Vref Scan disable
5008 19:52:56.750656 == TX Byte 0 ==
5009 19:52:56.754157 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5010 19:52:56.757469 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5011 19:52:56.760723 == TX Byte 1 ==
5012 19:52:56.763787 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5013 19:52:56.767756 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5014 19:52:56.767835
5015 19:52:56.770444 [DATLAT]
5016 19:52:56.770522 Freq=933, CH0 RK0
5017 19:52:56.770586
5018 19:52:56.773729 DATLAT Default: 0xd
5019 19:52:56.773808 0, 0xFFFF, sum = 0
5020 19:52:56.777499 1, 0xFFFF, sum = 0
5021 19:52:56.777579 2, 0xFFFF, sum = 0
5022 19:52:56.780443 3, 0xFFFF, sum = 0
5023 19:52:56.780523 4, 0xFFFF, sum = 0
5024 19:52:56.783891 5, 0xFFFF, sum = 0
5025 19:52:56.783972 6, 0xFFFF, sum = 0
5026 19:52:56.787313 7, 0xFFFF, sum = 0
5027 19:52:56.787398 8, 0xFFFF, sum = 0
5028 19:52:56.790375 9, 0xFFFF, sum = 0
5029 19:52:56.790452 10, 0x0, sum = 1
5030 19:52:56.793677 11, 0x0, sum = 2
5031 19:52:56.793755 12, 0x0, sum = 3
5032 19:52:56.796931 13, 0x0, sum = 4
5033 19:52:56.797009 best_step = 11
5034 19:52:56.797074
5035 19:52:56.797134 ==
5036 19:52:56.800665 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 19:52:56.806750 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5038 19:52:56.806839 ==
5039 19:52:56.806923 RX Vref Scan: 1
5040 19:52:56.807002
5041 19:52:56.810344 RX Vref 0 -> 0, step: 1
5042 19:52:56.810426
5043 19:52:56.813438 RX Delay -69 -> 252, step: 4
5044 19:52:56.813520
5045 19:52:56.816591 Set Vref, RX VrefLevel [Byte0]: 51
5046 19:52:56.820223 [Byte1]: 48
5047 19:52:56.820319
5048 19:52:56.823454 Final RX Vref Byte 0 = 51 to rank0
5049 19:52:56.826855 Final RX Vref Byte 1 = 48 to rank0
5050 19:52:56.830176 Final RX Vref Byte 0 = 51 to rank1
5051 19:52:56.833977 Final RX Vref Byte 1 = 48 to rank1==
5052 19:52:56.836936 Dram Type= 6, Freq= 0, CH_0, rank 0
5053 19:52:56.839964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5054 19:52:56.840046 ==
5055 19:52:56.843611 DQS Delay:
5056 19:52:56.843693 DQS0 = 0, DQS1 = 0
5057 19:52:56.847061 DQM Delay:
5058 19:52:56.847143 DQM0 = 97, DQM1 = 86
5059 19:52:56.847226 DQ Delay:
5060 19:52:56.849839 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =94
5061 19:52:56.853326 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5062 19:52:56.856569 DQ8 =76, DQ9 =70, DQ10 =84, DQ11 =80
5063 19:52:56.859747 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =96
5064 19:52:56.862903
5065 19:52:56.862983
5066 19:52:56.869660 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5067 19:52:56.873062 CH0 RK0: MR19=505, MR18=2525
5068 19:52:56.879852 CH0_RK0: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5069 19:52:56.879933
5070 19:52:56.882889 ----->DramcWriteLeveling(PI) begin...
5071 19:52:56.882971 ==
5072 19:52:56.886311 Dram Type= 6, Freq= 0, CH_0, rank 1
5073 19:52:56.889846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5074 19:52:56.889927 ==
5075 19:52:56.892988 Write leveling (Byte 0): 27 => 27
5076 19:52:56.896143 Write leveling (Byte 1): 30 => 30
5077 19:52:56.899336 DramcWriteLeveling(PI) end<-----
5078 19:52:56.899416
5079 19:52:56.899481 ==
5080 19:52:56.902884 Dram Type= 6, Freq= 0, CH_0, rank 1
5081 19:52:56.906162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5082 19:52:56.906243 ==
5083 19:52:56.909753 [Gating] SW mode calibration
5084 19:52:56.915833 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5085 19:52:56.923115 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5086 19:52:56.925781 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5087 19:52:56.929330 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 19:52:56.935745 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5089 19:52:56.939174 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5090 19:52:56.942513 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 19:52:56.949233 0 10 20 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
5092 19:52:56.952504 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5093 19:52:56.955839 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5094 19:52:56.962178 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 19:52:56.965651 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 19:52:56.968934 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 19:52:56.975469 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 19:52:56.979014 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 19:52:56.982107 0 11 20 | B1->B0 | 2a2a 3131 | 0 0 | (0 0) (0 0)
5100 19:52:56.989135 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5101 19:52:56.992012 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 19:52:56.995585 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 19:52:57.001915 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 19:52:57.005483 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 19:52:57.008829 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 19:52:57.015173 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 19:52:57.018733 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5108 19:52:57.021856 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 19:52:57.028412 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 19:52:57.031718 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 19:52:57.035093 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 19:52:57.041668 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 19:52:57.045072 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 19:52:57.048230 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 19:52:57.054820 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 19:52:57.058281 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 19:52:57.062324 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 19:52:57.068154 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 19:52:57.071748 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 19:52:57.075063 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 19:52:57.081343 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 19:52:57.084734 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 19:52:57.087901 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5124 19:52:57.094624 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 19:52:57.094708 Total UI for P1: 0, mck2ui 16
5126 19:52:57.101278 best dqsien dly found for B0: ( 0, 14, 20)
5127 19:52:57.101359 Total UI for P1: 0, mck2ui 16
5128 19:52:57.107726 best dqsien dly found for B1: ( 0, 14, 20)
5129 19:52:57.111415 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5130 19:52:57.114755 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5131 19:52:57.114836
5132 19:52:57.117633 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5133 19:52:57.120885 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5134 19:52:57.124984 [Gating] SW calibration Done
5135 19:52:57.125077 ==
5136 19:52:57.127601 Dram Type= 6, Freq= 0, CH_0, rank 1
5137 19:52:57.130893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5138 19:52:57.130975 ==
5139 19:52:57.134354 RX Vref Scan: 0
5140 19:52:57.134435
5141 19:52:57.134499 RX Vref 0 -> 0, step: 1
5142 19:52:57.134560
5143 19:52:57.137522 RX Delay -80 -> 252, step: 8
5144 19:52:57.144294 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5145 19:52:57.147294 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5146 19:52:57.150584 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5147 19:52:57.153726 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5148 19:52:57.157159 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5149 19:52:57.160689 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5150 19:52:57.167129 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5151 19:52:57.170556 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5152 19:52:57.173654 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5153 19:52:57.177375 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5154 19:52:57.180463 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5155 19:52:57.187171 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5156 19:52:57.190277 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5157 19:52:57.193533 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5158 19:52:57.196841 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5159 19:52:57.200148 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5160 19:52:57.200243 ==
5161 19:52:57.203331 Dram Type= 6, Freq= 0, CH_0, rank 1
5162 19:52:57.210123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5163 19:52:57.210204 ==
5164 19:52:57.210268 DQS Delay:
5165 19:52:57.213234 DQS0 = 0, DQS1 = 0
5166 19:52:57.213315 DQM Delay:
5167 19:52:57.213380 DQM0 = 96, DQM1 = 86
5168 19:52:57.216564 DQ Delay:
5169 19:52:57.220128 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5170 19:52:57.223197 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5171 19:52:57.226651 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =79
5172 19:52:57.230070 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5173 19:52:57.230151
5174 19:52:57.230215
5175 19:52:57.230275 ==
5176 19:52:57.233096 Dram Type= 6, Freq= 0, CH_0, rank 1
5177 19:52:57.236450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5178 19:52:57.236532 ==
5179 19:52:57.236596
5180 19:52:57.236656
5181 19:52:57.239924 TX Vref Scan disable
5182 19:52:57.240004 == TX Byte 0 ==
5183 19:52:57.246584 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5184 19:52:57.249765 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5185 19:52:57.249846 == TX Byte 1 ==
5186 19:52:57.256682 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5187 19:52:57.259814 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5188 19:52:57.259899 ==
5189 19:52:57.263282 Dram Type= 6, Freq= 0, CH_0, rank 1
5190 19:52:57.266292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5191 19:52:57.266374 ==
5192 19:52:57.266439
5193 19:52:57.269759
5194 19:52:57.269839 TX Vref Scan disable
5195 19:52:57.272928 == TX Byte 0 ==
5196 19:52:57.276367 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5197 19:52:57.282937 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5198 19:52:57.283040 == TX Byte 1 ==
5199 19:52:57.285979 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5200 19:52:57.292753 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5201 19:52:57.292834
5202 19:52:57.292898 [DATLAT]
5203 19:52:57.292959 Freq=933, CH0 RK1
5204 19:52:57.293017
5205 19:52:57.296378 DATLAT Default: 0xb
5206 19:52:57.296458 0, 0xFFFF, sum = 0
5207 19:52:57.299510 1, 0xFFFF, sum = 0
5208 19:52:57.299592 2, 0xFFFF, sum = 0
5209 19:52:57.302893 3, 0xFFFF, sum = 0
5210 19:52:57.306021 4, 0xFFFF, sum = 0
5211 19:52:57.306103 5, 0xFFFF, sum = 0
5212 19:52:57.309604 6, 0xFFFF, sum = 0
5213 19:52:57.309686 7, 0xFFFF, sum = 0
5214 19:52:57.312957 8, 0xFFFF, sum = 0
5215 19:52:57.313038 9, 0xFFFF, sum = 0
5216 19:52:57.315894 10, 0x0, sum = 1
5217 19:52:57.315975 11, 0x0, sum = 2
5218 19:52:57.319264 12, 0x0, sum = 3
5219 19:52:57.319345 13, 0x0, sum = 4
5220 19:52:57.319411 best_step = 11
5221 19:52:57.319470
5222 19:52:57.322658 ==
5223 19:52:57.325947 Dram Type= 6, Freq= 0, CH_0, rank 1
5224 19:52:57.329568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5225 19:52:57.329649 ==
5226 19:52:57.329713 RX Vref Scan: 0
5227 19:52:57.329773
5228 19:52:57.332343 RX Vref 0 -> 0, step: 1
5229 19:52:57.332424
5230 19:52:57.335869 RX Delay -77 -> 252, step: 4
5231 19:52:57.342455 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5232 19:52:57.345653 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5233 19:52:57.348889 iDelay=203, Bit 2, Center 94 (-1 ~ 190) 192
5234 19:52:57.352312 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5235 19:52:57.355399 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5236 19:52:57.358733 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5237 19:52:57.365441 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5238 19:52:57.368682 iDelay=203, Bit 7, Center 106 (11 ~ 202) 192
5239 19:52:57.371905 iDelay=203, Bit 8, Center 76 (-9 ~ 162) 172
5240 19:52:57.375377 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5241 19:52:57.378526 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5242 19:52:57.385129 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5243 19:52:57.388926 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5244 19:52:57.391709 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5245 19:52:57.395027 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5246 19:52:57.398370 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5247 19:52:57.398451 ==
5248 19:52:57.401599 Dram Type= 6, Freq= 0, CH_0, rank 1
5249 19:52:57.408628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5250 19:52:57.408709 ==
5251 19:52:57.408774 DQS Delay:
5252 19:52:57.411508 DQS0 = 0, DQS1 = 0
5253 19:52:57.411588 DQM Delay:
5254 19:52:57.411651 DQM0 = 97, DQM1 = 86
5255 19:52:57.414841 DQ Delay:
5256 19:52:57.418280 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5257 19:52:57.421623 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =106
5258 19:52:57.425228 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =78
5259 19:52:57.428741 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =94
5260 19:52:57.428822
5261 19:52:57.428888
5262 19:52:57.434882 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5263 19:52:57.438175 CH0 RK1: MR19=505, MR18=2E2E
5264 19:52:57.444833 CH0_RK1: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5265 19:52:57.448234 [RxdqsGatingPostProcess] freq 933
5266 19:52:57.451747 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5267 19:52:57.454832 Pre-setting of DQS Precalculation
5268 19:52:57.461513 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5269 19:52:57.461593 ==
5270 19:52:57.465266 Dram Type= 6, Freq= 0, CH_1, rank 0
5271 19:52:57.467948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5272 19:52:57.468029 ==
5273 19:52:57.475070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5274 19:52:57.481342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5275 19:52:57.484467 [CA 0] Center 37 (6~68) winsize 63
5276 19:52:57.488438 [CA 1] Center 37 (6~68) winsize 63
5277 19:52:57.491361 [CA 2] Center 34 (4~65) winsize 62
5278 19:52:57.494689 [CA 3] Center 34 (4~65) winsize 62
5279 19:52:57.498000 [CA 4] Center 33 (2~64) winsize 63
5280 19:52:57.501272 [CA 5] Center 33 (2~64) winsize 63
5281 19:52:57.501353
5282 19:52:57.504615 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5283 19:52:57.504696
5284 19:52:57.508036 [CATrainingPosCal] consider 1 rank data
5285 19:52:57.511212 u2DelayCellTimex100 = 270/100 ps
5286 19:52:57.514591 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5287 19:52:57.517703 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5288 19:52:57.521175 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5289 19:52:57.524741 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5290 19:52:57.527812 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5291 19:52:57.531161 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5292 19:52:57.531242
5293 19:52:57.537839 CA PerBit enable=1, Macro0, CA PI delay=33
5294 19:52:57.537921
5295 19:52:57.537986 [CBTSetCACLKResult] CA Dly = 33
5296 19:52:57.541009 CS Dly: 5 (0~36)
5297 19:52:57.541090 ==
5298 19:52:57.544866 Dram Type= 6, Freq= 0, CH_1, rank 1
5299 19:52:57.547582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5300 19:52:57.547671 ==
5301 19:52:57.554152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5302 19:52:57.560796 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5303 19:52:57.564110 [CA 0] Center 37 (6~68) winsize 63
5304 19:52:57.567403 [CA 1] Center 37 (6~68) winsize 63
5305 19:52:57.570934 [CA 2] Center 34 (4~65) winsize 62
5306 19:52:57.574363 [CA 3] Center 33 (3~64) winsize 62
5307 19:52:57.577757 [CA 4] Center 33 (2~64) winsize 63
5308 19:52:57.580808 [CA 5] Center 33 (2~64) winsize 63
5309 19:52:57.580889
5310 19:52:57.584651 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5311 19:52:57.584731
5312 19:52:57.587685 [CATrainingPosCal] consider 2 rank data
5313 19:52:57.591015 u2DelayCellTimex100 = 270/100 ps
5314 19:52:57.594269 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5315 19:52:57.597337 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5316 19:52:57.600864 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5317 19:52:57.604102 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5318 19:52:57.607569 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5319 19:52:57.610740 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5320 19:52:57.610820
5321 19:52:57.617399 CA PerBit enable=1, Macro0, CA PI delay=33
5322 19:52:57.617480
5323 19:52:57.617544 [CBTSetCACLKResult] CA Dly = 33
5324 19:52:57.620849 CS Dly: 5 (0~37)
5325 19:52:57.620929
5326 19:52:57.624074 ----->DramcWriteLeveling(PI) begin...
5327 19:52:57.624155 ==
5328 19:52:57.627398 Dram Type= 6, Freq= 0, CH_1, rank 0
5329 19:52:57.630776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5330 19:52:57.630856 ==
5331 19:52:57.634391 Write leveling (Byte 0): 26 => 26
5332 19:52:57.637271 Write leveling (Byte 1): 23 => 23
5333 19:52:57.640715 DramcWriteLeveling(PI) end<-----
5334 19:52:57.640795
5335 19:52:57.640858 ==
5336 19:52:57.643852 Dram Type= 6, Freq= 0, CH_1, rank 0
5337 19:52:57.647402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5338 19:52:57.650928 ==
5339 19:52:57.651010 [Gating] SW mode calibration
5340 19:52:57.661235 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5341 19:52:57.663876 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5342 19:52:57.667258 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 19:52:57.674155 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 19:52:57.677624 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 19:52:57.680827 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 19:52:57.687302 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5347 19:52:57.690635 0 10 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
5348 19:52:57.693836 0 10 24 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
5349 19:52:57.700316 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 19:52:57.703882 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 19:52:57.707163 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 19:52:57.713856 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 19:52:57.717482 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 19:52:57.720342 0 11 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5355 19:52:57.727067 0 11 20 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
5356 19:52:57.730463 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5357 19:52:57.733605 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 19:52:57.740168 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 19:52:57.743516 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 19:52:57.746932 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 19:52:57.753516 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5362 19:52:57.756649 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5363 19:52:57.760059 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5364 19:52:57.767413 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 19:52:57.769992 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 19:52:57.773482 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 19:52:57.779972 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 19:52:57.783454 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 19:52:57.786540 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 19:52:57.793460 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 19:52:57.796538 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 19:52:57.799840 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 19:52:57.803129 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 19:52:57.810018 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 19:52:57.813379 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 19:52:57.816514 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 19:52:57.823245 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 19:52:57.826680 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 19:52:57.829997 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5380 19:52:57.833074 Total UI for P1: 0, mck2ui 16
5381 19:52:57.836556 best dqsien dly found for B0: ( 0, 14, 18)
5382 19:52:57.843197 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 19:52:57.846304 Total UI for P1: 0, mck2ui 16
5384 19:52:57.849908 best dqsien dly found for B1: ( 0, 14, 20)
5385 19:52:57.852939 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5386 19:52:57.856316 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5387 19:52:57.856396
5388 19:52:57.859702 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5389 19:52:57.863188 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5390 19:52:57.866303 [Gating] SW calibration Done
5391 19:52:57.866383 ==
5392 19:52:57.869468 Dram Type= 6, Freq= 0, CH_1, rank 0
5393 19:52:57.873238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5394 19:52:57.873322 ==
5395 19:52:57.876137 RX Vref Scan: 0
5396 19:52:57.876256
5397 19:52:57.876321 RX Vref 0 -> 0, step: 1
5398 19:52:57.879412
5399 19:52:57.879492 RX Delay -80 -> 252, step: 8
5400 19:52:57.886041 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5401 19:52:57.889994 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5402 19:52:57.892849 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5403 19:52:57.895954 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5404 19:52:57.899353 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5405 19:52:57.902725 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5406 19:52:57.909456 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5407 19:52:57.912740 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5408 19:52:57.915876 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5409 19:52:57.919334 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5410 19:52:57.922752 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5411 19:52:57.929309 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5412 19:52:57.932589 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5413 19:52:57.935908 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5414 19:52:57.939210 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5415 19:52:57.942398 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5416 19:52:57.942497 ==
5417 19:52:57.945677 Dram Type= 6, Freq= 0, CH_1, rank 0
5418 19:52:57.952643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5419 19:52:57.952719 ==
5420 19:52:57.952787 DQS Delay:
5421 19:52:57.955690 DQS0 = 0, DQS1 = 0
5422 19:52:57.955792 DQM Delay:
5423 19:52:57.955884 DQM0 = 94, DQM1 = 88
5424 19:52:57.959092 DQ Delay:
5425 19:52:57.962536 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5426 19:52:57.965923 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5427 19:52:57.969209 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =79
5428 19:52:57.972352 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5429 19:52:57.972449
5430 19:52:57.972543
5431 19:52:57.972629 ==
5432 19:52:57.975545 Dram Type= 6, Freq= 0, CH_1, rank 0
5433 19:52:57.979071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5434 19:52:57.979171 ==
5435 19:52:57.979261
5436 19:52:57.979346
5437 19:52:57.982373 TX Vref Scan disable
5438 19:52:57.982475 == TX Byte 0 ==
5439 19:52:57.989092 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5440 19:52:57.992183 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5441 19:52:57.992258 == TX Byte 1 ==
5442 19:52:57.999072 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5443 19:52:58.002117 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5444 19:52:58.002216 ==
5445 19:52:58.005781 Dram Type= 6, Freq= 0, CH_1, rank 0
5446 19:52:58.009230 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5447 19:52:58.009307 ==
5448 19:52:58.009368
5449 19:52:58.012370
5450 19:52:58.012438 TX Vref Scan disable
5451 19:52:58.015822 == TX Byte 0 ==
5452 19:52:58.019252 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5453 19:52:58.022111 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5454 19:52:58.025454 == TX Byte 1 ==
5455 19:52:58.028698 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5456 19:52:58.032060 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5457 19:52:58.035436
5458 19:52:58.035534 [DATLAT]
5459 19:52:58.035623 Freq=933, CH1 RK0
5460 19:52:58.035715
5461 19:52:58.038866 DATLAT Default: 0xd
5462 19:52:58.038967 0, 0xFFFF, sum = 0
5463 19:52:58.042244 1, 0xFFFF, sum = 0
5464 19:52:58.042343 2, 0xFFFF, sum = 0
5465 19:52:58.045262 3, 0xFFFF, sum = 0
5466 19:52:58.045333 4, 0xFFFF, sum = 0
5467 19:52:58.048594 5, 0xFFFF, sum = 0
5468 19:52:58.051731 6, 0xFFFF, sum = 0
5469 19:52:58.051830 7, 0xFFFF, sum = 0
5470 19:52:58.055169 8, 0xFFFF, sum = 0
5471 19:52:58.055270 9, 0xFFFF, sum = 0
5472 19:52:58.058533 10, 0x0, sum = 1
5473 19:52:58.058636 11, 0x0, sum = 2
5474 19:52:58.061718 12, 0x0, sum = 3
5475 19:52:58.061801 13, 0x0, sum = 4
5476 19:52:58.061906 best_step = 11
5477 19:52:58.061998
5478 19:52:58.065277 ==
5479 19:52:58.068418 Dram Type= 6, Freq= 0, CH_1, rank 0
5480 19:52:58.071747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5481 19:52:58.071828 ==
5482 19:52:58.071893 RX Vref Scan: 1
5483 19:52:58.071953
5484 19:52:58.075284 RX Vref 0 -> 0, step: 1
5485 19:52:58.075365
5486 19:52:58.078345 RX Delay -69 -> 252, step: 4
5487 19:52:58.078426
5488 19:52:58.081442 Set Vref, RX VrefLevel [Byte0]: 53
5489 19:52:58.084863 [Byte1]: 49
5490 19:52:58.084944
5491 19:52:58.088333 Final RX Vref Byte 0 = 53 to rank0
5492 19:52:58.091639 Final RX Vref Byte 1 = 49 to rank0
5493 19:52:58.094973 Final RX Vref Byte 0 = 53 to rank1
5494 19:52:58.098490 Final RX Vref Byte 1 = 49 to rank1==
5495 19:52:58.101598 Dram Type= 6, Freq= 0, CH_1, rank 0
5496 19:52:58.104653 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5497 19:52:58.108157 ==
5498 19:52:58.108244 DQS Delay:
5499 19:52:58.108309 DQS0 = 0, DQS1 = 0
5500 19:52:58.111442 DQM Delay:
5501 19:52:58.111522 DQM0 = 94, DQM1 = 88
5502 19:52:58.114672 DQ Delay:
5503 19:52:58.114753 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =90
5504 19:52:58.118454 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5505 19:52:58.121583 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5506 19:52:58.128338 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5507 19:52:58.128419
5508 19:52:58.128483
5509 19:52:58.134782 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x505, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
5510 19:52:58.137904 CH1 RK0: MR19=505, MR18=3B3B
5511 19:52:58.144673 CH1_RK0: MR19=0x505, MR18=0x3B3B, DQSOSC=403, MR23=63, INC=66, DEC=44
5512 19:52:58.144754
5513 19:52:58.148048 ----->DramcWriteLeveling(PI) begin...
5514 19:52:58.148130 ==
5515 19:52:58.151166 Dram Type= 6, Freq= 0, CH_1, rank 1
5516 19:52:58.154460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5517 19:52:58.154541 ==
5518 19:52:58.157786 Write leveling (Byte 0): 26 => 26
5519 19:52:58.161167 Write leveling (Byte 1): 26 => 26
5520 19:52:58.164630 DramcWriteLeveling(PI) end<-----
5521 19:52:58.164710
5522 19:52:58.164775 ==
5523 19:52:58.167786 Dram Type= 6, Freq= 0, CH_1, rank 1
5524 19:52:58.171396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5525 19:52:58.171504 ==
5526 19:52:58.174457 [Gating] SW mode calibration
5527 19:52:58.181025 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5528 19:52:58.187765 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5529 19:52:58.191132 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5530 19:52:58.194394 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5531 19:52:58.200865 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5532 19:52:58.204183 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
5533 19:52:58.207630 0 10 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
5534 19:52:58.214198 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5535 19:52:58.217446 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5536 19:52:58.220964 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5537 19:52:58.227313 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5538 19:52:58.231130 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5539 19:52:58.234176 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5540 19:52:58.240642 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5541 19:52:58.244091 0 11 16 | B1->B0 | 2525 3e3e | 0 0 | (0 0) (0 0)
5542 19:52:58.247174 0 11 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5543 19:52:58.254088 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5544 19:52:58.257370 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5545 19:52:58.260664 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5546 19:52:58.267226 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5547 19:52:58.270705 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5548 19:52:58.273774 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5549 19:52:58.280308 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5550 19:52:58.284155 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5551 19:52:58.287131 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5552 19:52:58.293568 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5553 19:52:58.296950 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5554 19:52:58.300504 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5555 19:52:58.306817 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5556 19:52:58.310064 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5557 19:52:58.313343 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 19:52:58.320236 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 19:52:58.323590 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 19:52:58.326653 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 19:52:58.333540 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 19:52:58.336592 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 19:52:58.340188 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 19:52:58.347255 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 19:52:58.350141 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5566 19:52:58.353104 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 19:52:58.356597 Total UI for P1: 0, mck2ui 16
5568 19:52:58.359979 best dqsien dly found for B0: ( 0, 14, 16)
5569 19:52:58.363404 Total UI for P1: 0, mck2ui 16
5570 19:52:58.366856 best dqsien dly found for B1: ( 0, 14, 18)
5571 19:52:58.369773 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5572 19:52:58.372885 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5573 19:52:58.372965
5574 19:52:58.379569 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5575 19:52:58.383230 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5576 19:52:58.383332 [Gating] SW calibration Done
5577 19:52:58.386492 ==
5578 19:52:58.389897 Dram Type= 6, Freq= 0, CH_1, rank 1
5579 19:52:58.392854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5580 19:52:58.392956 ==
5581 19:52:58.393050 RX Vref Scan: 0
5582 19:52:58.393137
5583 19:52:58.396283 RX Vref 0 -> 0, step: 1
5584 19:52:58.396357
5585 19:52:58.399666 RX Delay -80 -> 252, step: 8
5586 19:52:58.402783 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5587 19:52:58.406206 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5588 19:52:58.409460 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5589 19:52:58.416150 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5590 19:52:58.419325 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5591 19:52:58.422773 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5592 19:52:58.426244 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5593 19:52:58.429350 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5594 19:52:58.432856 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5595 19:52:58.439233 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5596 19:52:58.442789 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5597 19:52:58.445950 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5598 19:52:58.449744 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5599 19:52:58.452650 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5600 19:52:58.459305 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5601 19:52:58.462636 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5602 19:52:58.462723 ==
5603 19:52:58.466047 Dram Type= 6, Freq= 0, CH_1, rank 1
5604 19:52:58.469108 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5605 19:52:58.469189 ==
5606 19:52:58.469254 DQS Delay:
5607 19:52:58.472559 DQS0 = 0, DQS1 = 0
5608 19:52:58.472639 DQM Delay:
5609 19:52:58.475654 DQM0 = 96, DQM1 = 88
5610 19:52:58.475734 DQ Delay:
5611 19:52:58.478953 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5612 19:52:58.482165 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5613 19:52:58.485793 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =79
5614 19:52:58.489007 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5615 19:52:58.489090
5616 19:52:58.489155
5617 19:52:58.489215 ==
5618 19:52:58.492401 Dram Type= 6, Freq= 0, CH_1, rank 1
5619 19:52:58.498762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5620 19:52:58.498844 ==
5621 19:52:58.498907
5622 19:52:58.498967
5623 19:52:58.499024 TX Vref Scan disable
5624 19:52:58.502359 == TX Byte 0 ==
5625 19:52:58.505404 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5626 19:52:58.512536 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5627 19:52:58.512617 == TX Byte 1 ==
5628 19:52:58.515605 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5629 19:52:58.521974 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5630 19:52:58.522055 ==
5631 19:52:58.525522 Dram Type= 6, Freq= 0, CH_1, rank 1
5632 19:52:58.528740 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5633 19:52:58.528820 ==
5634 19:52:58.528885
5635 19:52:58.528944
5636 19:52:58.531781 TX Vref Scan disable
5637 19:52:58.531861 == TX Byte 0 ==
5638 19:52:58.538607 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5639 19:52:58.541759 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5640 19:52:58.545056 == TX Byte 1 ==
5641 19:52:58.548517 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5642 19:52:58.551506 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5643 19:52:58.551587
5644 19:52:58.551652 [DATLAT]
5645 19:52:58.554869 Freq=933, CH1 RK1
5646 19:52:58.554949
5647 19:52:58.558238 DATLAT Default: 0xb
5648 19:52:58.558318 0, 0xFFFF, sum = 0
5649 19:52:58.561516 1, 0xFFFF, sum = 0
5650 19:52:58.561597 2, 0xFFFF, sum = 0
5651 19:52:58.564940 3, 0xFFFF, sum = 0
5652 19:52:58.565023 4, 0xFFFF, sum = 0
5653 19:52:58.568148 5, 0xFFFF, sum = 0
5654 19:52:58.568271 6, 0xFFFF, sum = 0
5655 19:52:58.571393 7, 0xFFFF, sum = 0
5656 19:52:58.571475 8, 0xFFFF, sum = 0
5657 19:52:58.574797 9, 0xFFFF, sum = 0
5658 19:52:58.574879 10, 0x0, sum = 1
5659 19:52:58.578333 11, 0x0, sum = 2
5660 19:52:58.578415 12, 0x0, sum = 3
5661 19:52:58.581362 13, 0x0, sum = 4
5662 19:52:58.581444 best_step = 11
5663 19:52:58.581509
5664 19:52:58.581569 ==
5665 19:52:58.584675 Dram Type= 6, Freq= 0, CH_1, rank 1
5666 19:52:58.588208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5667 19:52:58.588303 ==
5668 19:52:58.591484 RX Vref Scan: 0
5669 19:52:58.591565
5670 19:52:58.594519 RX Vref 0 -> 0, step: 1
5671 19:52:58.594599
5672 19:52:58.594664 RX Delay -69 -> 252, step: 4
5673 19:52:58.602786 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5674 19:52:58.605908 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5675 19:52:58.609318 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5676 19:52:58.612663 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5677 19:52:58.616050 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5678 19:52:58.619271 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5679 19:52:58.625994 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5680 19:52:58.629235 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5681 19:52:58.632518 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5682 19:52:58.635681 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5683 19:52:58.639578 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5684 19:52:58.645746 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5685 19:52:58.648870 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5686 19:52:58.652236 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5687 19:52:58.655407 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5688 19:52:58.659128 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5689 19:52:58.659209 ==
5690 19:52:58.662089 Dram Type= 6, Freq= 0, CH_1, rank 1
5691 19:52:58.668967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5692 19:52:58.669049 ==
5693 19:52:58.669113 DQS Delay:
5694 19:52:58.672359 DQS0 = 0, DQS1 = 0
5695 19:52:58.672439 DQM Delay:
5696 19:52:58.675598 DQM0 = 96, DQM1 = 88
5697 19:52:58.675678 DQ Delay:
5698 19:52:58.678709 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5699 19:52:58.681943 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5700 19:52:58.685467 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5701 19:52:58.688588 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5702 19:52:58.688669
5703 19:52:58.688734
5704 19:52:58.695313 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5705 19:52:58.698481 CH1 RK1: MR19=505, MR18=2525
5706 19:52:58.705101 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5707 19:52:58.708556 [RxdqsGatingPostProcess] freq 933
5708 19:52:58.715133 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5709 19:52:58.715213 Pre-setting of DQS Precalculation
5710 19:52:58.721604 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5711 19:52:58.728216 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5712 19:52:58.735407 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5713 19:52:58.735487
5714 19:52:58.735551
5715 19:52:58.738231 [Calibration Summary] 1866 Mbps
5716 19:52:58.742063 CH 0, Rank 0
5717 19:52:58.742143 SW Impedance : PASS
5718 19:52:58.745023 DUTY Scan : NO K
5719 19:52:58.748364 ZQ Calibration : PASS
5720 19:52:58.748445 Jitter Meter : NO K
5721 19:52:58.751812 CBT Training : PASS
5722 19:52:58.751893 Write leveling : PASS
5723 19:52:58.754928 RX DQS gating : PASS
5724 19:52:58.758204 RX DQ/DQS(RDDQC) : PASS
5725 19:52:58.758284 TX DQ/DQS : PASS
5726 19:52:58.761505 RX DATLAT : PASS
5727 19:52:58.765083 RX DQ/DQS(Engine): PASS
5728 19:52:58.765165 TX OE : NO K
5729 19:52:58.768118 All Pass.
5730 19:52:58.768234
5731 19:52:58.768300 CH 0, Rank 1
5732 19:52:58.771620 SW Impedance : PASS
5733 19:52:58.771701 DUTY Scan : NO K
5734 19:52:58.775212 ZQ Calibration : PASS
5735 19:52:58.778233 Jitter Meter : NO K
5736 19:52:58.778313 CBT Training : PASS
5737 19:52:58.781647 Write leveling : PASS
5738 19:52:58.784863 RX DQS gating : PASS
5739 19:52:58.784943 RX DQ/DQS(RDDQC) : PASS
5740 19:52:58.788200 TX DQ/DQS : PASS
5741 19:52:58.791451 RX DATLAT : PASS
5742 19:52:58.791531 RX DQ/DQS(Engine): PASS
5743 19:52:58.795026 TX OE : NO K
5744 19:52:58.795107 All Pass.
5745 19:52:58.795172
5746 19:52:58.798165 CH 1, Rank 0
5747 19:52:58.798246 SW Impedance : PASS
5748 19:52:58.801362 DUTY Scan : NO K
5749 19:52:58.804354 ZQ Calibration : PASS
5750 19:52:58.804434 Jitter Meter : NO K
5751 19:52:58.807658 CBT Training : PASS
5752 19:52:58.811394 Write leveling : PASS
5753 19:52:58.811475 RX DQS gating : PASS
5754 19:52:58.814547 RX DQ/DQS(RDDQC) : PASS
5755 19:52:58.814628 TX DQ/DQS : PASS
5756 19:52:58.817940 RX DATLAT : PASS
5757 19:52:58.821044 RX DQ/DQS(Engine): PASS
5758 19:52:58.821122 TX OE : NO K
5759 19:52:58.824401 All Pass.
5760 19:52:58.824474
5761 19:52:58.824559 CH 1, Rank 1
5762 19:52:58.827662 SW Impedance : PASS
5763 19:52:58.827770 DUTY Scan : NO K
5764 19:52:58.831153 ZQ Calibration : PASS
5765 19:52:58.834231 Jitter Meter : NO K
5766 19:52:58.834330 CBT Training : PASS
5767 19:52:58.837549 Write leveling : PASS
5768 19:52:58.840936 RX DQS gating : PASS
5769 19:52:58.841009 RX DQ/DQS(RDDQC) : PASS
5770 19:52:58.844260 TX DQ/DQS : PASS
5771 19:52:58.847454 RX DATLAT : PASS
5772 19:52:58.847551 RX DQ/DQS(Engine): PASS
5773 19:52:58.850829 TX OE : NO K
5774 19:52:58.850904 All Pass.
5775 19:52:58.850965
5776 19:52:58.854209 DramC Write-DBI off
5777 19:52:58.857311 PER_BANK_REFRESH: Hybrid Mode
5778 19:52:58.857409 TX_TRACKING: ON
5779 19:52:58.867177 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5780 19:52:58.871100 [FAST_K] Save calibration result to emmc
5781 19:52:58.873946 dramc_set_vcore_voltage set vcore to 650000
5782 19:52:58.877619 Read voltage for 400, 6
5783 19:52:58.877717 Vio18 = 0
5784 19:52:58.877812 Vcore = 650000
5785 19:52:58.880780 Vdram = 0
5786 19:52:58.880867 Vddq = 0
5787 19:52:58.880932 Vmddr = 0
5788 19:52:58.887022 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5789 19:52:58.890650 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5790 19:52:58.893837 MEM_TYPE=3, freq_sel=20
5791 19:52:58.897453 sv_algorithm_assistance_LP4_800
5792 19:52:58.900398 ============ PULL DRAM RESETB DOWN ============
5793 19:52:58.903877 ========== PULL DRAM RESETB DOWN end =========
5794 19:52:58.910495 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5795 19:52:58.914027 ===================================
5796 19:52:58.917113 LPDDR4 DRAM CONFIGURATION
5797 19:52:58.920425 ===================================
5798 19:52:58.920506 EX_ROW_EN[0] = 0x0
5799 19:52:58.923610 EX_ROW_EN[1] = 0x0
5800 19:52:58.923691 LP4Y_EN = 0x0
5801 19:52:58.927319 WORK_FSP = 0x0
5802 19:52:58.927399 WL = 0x2
5803 19:52:58.930199 RL = 0x2
5804 19:52:58.930279 BL = 0x2
5805 19:52:58.933861 RPST = 0x0
5806 19:52:58.933942 RD_PRE = 0x0
5807 19:52:58.936893 WR_PRE = 0x1
5808 19:52:58.936973 WR_PST = 0x0
5809 19:52:58.940435 DBI_WR = 0x0
5810 19:52:58.940516 DBI_RD = 0x0
5811 19:52:58.944022 OTF = 0x1
5812 19:52:58.946880 ===================================
5813 19:52:58.950234 ===================================
5814 19:52:58.950314 ANA top config
5815 19:52:58.953694 ===================================
5816 19:52:58.956929 DLL_ASYNC_EN = 0
5817 19:52:58.960568 ALL_SLAVE_EN = 1
5818 19:52:58.963540 NEW_RANK_MODE = 1
5819 19:52:58.963622 DLL_IDLE_MODE = 1
5820 19:52:58.967174 LP45_APHY_COMB_EN = 1
5821 19:52:58.970322 TX_ODT_DIS = 1
5822 19:52:58.973547 NEW_8X_MODE = 1
5823 19:52:58.977223 ===================================
5824 19:52:58.980340 ===================================
5825 19:52:58.983835 data_rate = 800
5826 19:52:58.983919 CKR = 1
5827 19:52:58.987273 DQ_P2S_RATIO = 4
5828 19:52:58.990335 ===================================
5829 19:52:58.993576 CA_P2S_RATIO = 4
5830 19:52:58.996794 DQ_CA_OPEN = 0
5831 19:52:59.000163 DQ_SEMI_OPEN = 1
5832 19:52:59.003589 CA_SEMI_OPEN = 1
5833 19:52:59.003670 CA_FULL_RATE = 0
5834 19:52:59.006874 DQ_CKDIV4_EN = 0
5835 19:52:59.009998 CA_CKDIV4_EN = 1
5836 19:52:59.013635 CA_PREDIV_EN = 0
5837 19:52:59.016855 PH8_DLY = 0
5838 19:52:59.020435 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5839 19:52:59.020516 DQ_AAMCK_DIV = 0
5840 19:52:59.023767 CA_AAMCK_DIV = 0
5841 19:52:59.027020 CA_ADMCK_DIV = 4
5842 19:52:59.030049 DQ_TRACK_CA_EN = 0
5843 19:52:59.033857 CA_PICK = 800
5844 19:52:59.037137 CA_MCKIO = 400
5845 19:52:59.037217 MCKIO_SEMI = 400
5846 19:52:59.040137 PLL_FREQ = 3016
5847 19:52:59.043683 DQ_UI_PI_RATIO = 32
5848 19:52:59.046837 CA_UI_PI_RATIO = 32
5849 19:52:59.050050 ===================================
5850 19:52:59.053457 ===================================
5851 19:52:59.056834 memory_type:LPDDR4
5852 19:52:59.056915 GP_NUM : 10
5853 19:52:59.059861 SRAM_EN : 1
5854 19:52:59.063224 MD32_EN : 0
5855 19:52:59.066756 ===================================
5856 19:52:59.066836 [ANA_INIT] >>>>>>>>>>>>>>
5857 19:52:59.070606 <<<<<< [CONFIGURE PHASE]: ANA_TX
5858 19:52:59.073135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5859 19:52:59.076392 ===================================
5860 19:52:59.079772 data_rate = 800,PCW = 0X7400
5861 19:52:59.083341 ===================================
5862 19:52:59.086694 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5863 19:52:59.093233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5864 19:52:59.102735 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5865 19:52:59.109636 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5866 19:52:59.112953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5867 19:52:59.116086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5868 19:52:59.116194 [ANA_INIT] flow start
5869 19:52:59.119481 [ANA_INIT] PLL >>>>>>>>
5870 19:52:59.122810 [ANA_INIT] PLL <<<<<<<<
5871 19:52:59.122912 [ANA_INIT] MIDPI >>>>>>>>
5872 19:52:59.126499 [ANA_INIT] MIDPI <<<<<<<<
5873 19:52:59.129545 [ANA_INIT] DLL >>>>>>>>
5874 19:52:59.129647 [ANA_INIT] flow end
5875 19:52:59.136164 ============ LP4 DIFF to SE enter ============
5876 19:52:59.139377 ============ LP4 DIFF to SE exit ============
5877 19:52:59.142584 [ANA_INIT] <<<<<<<<<<<<<
5878 19:52:59.146045 [Flow] Enable top DCM control >>>>>
5879 19:52:59.149422 [Flow] Enable top DCM control <<<<<
5880 19:52:59.149526 Enable DLL master slave shuffle
5881 19:52:59.155858 ==============================================================
5882 19:52:59.159170 Gating Mode config
5883 19:52:59.162646 ==============================================================
5884 19:52:59.165719 Config description:
5885 19:52:59.175628 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5886 19:52:59.182507 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5887 19:52:59.185624 SELPH_MODE 0: By rank 1: By Phase
5888 19:52:59.192307 ==============================================================
5889 19:52:59.195473 GAT_TRACK_EN = 0
5890 19:52:59.198897 RX_GATING_MODE = 2
5891 19:52:59.202067 RX_GATING_TRACK_MODE = 2
5892 19:52:59.205419 SELPH_MODE = 1
5893 19:52:59.208757 PICG_EARLY_EN = 1
5894 19:52:59.208838 VALID_LAT_VALUE = 1
5895 19:52:59.215437 ==============================================================
5896 19:52:59.218926 Enter into Gating configuration >>>>
5897 19:52:59.222054 Exit from Gating configuration <<<<
5898 19:52:59.225339 Enter into DVFS_PRE_config >>>>>
5899 19:52:59.235390 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5900 19:52:59.238534 Exit from DVFS_PRE_config <<<<<
5901 19:52:59.241970 Enter into PICG configuration >>>>
5902 19:52:59.245296 Exit from PICG configuration <<<<
5903 19:52:59.248372 [RX_INPUT] configuration >>>>>
5904 19:52:59.251742 [RX_INPUT] configuration <<<<<
5905 19:52:59.258232 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5906 19:52:59.261771 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5907 19:52:59.268154 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5908 19:52:59.274930 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5909 19:52:59.281420 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5910 19:52:59.288630 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5911 19:52:59.291556 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5912 19:52:59.294922 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5913 19:52:59.298561 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5914 19:52:59.304962 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5915 19:52:59.308217 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5916 19:52:59.311453 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5917 19:52:59.314745 ===================================
5918 19:52:59.318225 LPDDR4 DRAM CONFIGURATION
5919 19:52:59.321293 ===================================
5920 19:52:59.321374 EX_ROW_EN[0] = 0x0
5921 19:52:59.324812 EX_ROW_EN[1] = 0x0
5922 19:52:59.328129 LP4Y_EN = 0x0
5923 19:52:59.328224 WORK_FSP = 0x0
5924 19:52:59.331403 WL = 0x2
5925 19:52:59.331484 RL = 0x2
5926 19:52:59.334627 BL = 0x2
5927 19:52:59.334707 RPST = 0x0
5928 19:52:59.337928 RD_PRE = 0x0
5929 19:52:59.338009 WR_PRE = 0x1
5930 19:52:59.341463 WR_PST = 0x0
5931 19:52:59.341570 DBI_WR = 0x0
5932 19:52:59.344592 DBI_RD = 0x0
5933 19:52:59.344672 OTF = 0x1
5934 19:52:59.348143 ===================================
5935 19:52:59.351162 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5936 19:52:59.358022 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5937 19:52:59.361215 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5938 19:52:59.364490 ===================================
5939 19:52:59.368045 LPDDR4 DRAM CONFIGURATION
5940 19:52:59.370952 ===================================
5941 19:52:59.371033 EX_ROW_EN[0] = 0x10
5942 19:52:59.374384 EX_ROW_EN[1] = 0x0
5943 19:52:59.377531 LP4Y_EN = 0x0
5944 19:52:59.377612 WORK_FSP = 0x0
5945 19:52:59.381068 WL = 0x2
5946 19:52:59.381149 RL = 0x2
5947 19:52:59.384454 BL = 0x2
5948 19:52:59.384535 RPST = 0x0
5949 19:52:59.387533 RD_PRE = 0x0
5950 19:52:59.387613 WR_PRE = 0x1
5951 19:52:59.390684 WR_PST = 0x0
5952 19:52:59.390764 DBI_WR = 0x0
5953 19:52:59.394144 DBI_RD = 0x0
5954 19:52:59.394225 OTF = 0x1
5955 19:52:59.397480 ===================================
5956 19:52:59.404069 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5957 19:52:59.408453 nWR fixed to 30
5958 19:52:59.411584 [ModeRegInit_LP4] CH0 RK0
5959 19:52:59.411665 [ModeRegInit_LP4] CH0 RK1
5960 19:52:59.414876 [ModeRegInit_LP4] CH1 RK0
5961 19:52:59.418110 [ModeRegInit_LP4] CH1 RK1
5962 19:52:59.418190 match AC timing 18
5963 19:52:59.424689 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5964 19:52:59.428087 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5965 19:52:59.431168 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5966 19:52:59.438200 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5967 19:52:59.441366 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5968 19:52:59.441447 ==
5969 19:52:59.444655 Dram Type= 6, Freq= 0, CH_0, rank 0
5970 19:52:59.448089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5971 19:52:59.448170 ==
5972 19:52:59.454532 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5973 19:52:59.461147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5974 19:52:59.464748 [CA 0] Center 36 (8~64) winsize 57
5975 19:52:59.467860 [CA 1] Center 36 (8~64) winsize 57
5976 19:52:59.471065 [CA 2] Center 36 (8~64) winsize 57
5977 19:52:59.474495 [CA 3] Center 36 (8~64) winsize 57
5978 19:52:59.474575 [CA 4] Center 36 (8~64) winsize 57
5979 19:52:59.477871 [CA 5] Center 36 (8~64) winsize 57
5980 19:52:59.477951
5981 19:52:59.484733 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5982 19:52:59.484814
5983 19:52:59.487971 [CATrainingPosCal] consider 1 rank data
5984 19:52:59.491034 u2DelayCellTimex100 = 270/100 ps
5985 19:52:59.494463 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5986 19:52:59.497716 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5987 19:52:59.501029 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5988 19:52:59.504527 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5989 19:52:59.507578 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5990 19:52:59.511182 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
5991 19:52:59.511262
5992 19:52:59.514311 CA PerBit enable=1, Macro0, CA PI delay=36
5993 19:52:59.514393
5994 19:52:59.517718 [CBTSetCACLKResult] CA Dly = 36
5995 19:52:59.520739 CS Dly: 1 (0~32)
5996 19:52:59.520819 ==
5997 19:52:59.524297 Dram Type= 6, Freq= 0, CH_0, rank 1
5998 19:52:59.527719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5999 19:52:59.527800 ==
6000 19:52:59.534428 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6001 19:52:59.537651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6002 19:52:59.540905 [CA 0] Center 36 (8~64) winsize 57
6003 19:52:59.544046 [CA 1] Center 36 (8~64) winsize 57
6004 19:52:59.547468 [CA 2] Center 36 (8~64) winsize 57
6005 19:52:59.550597 [CA 3] Center 36 (8~64) winsize 57
6006 19:52:59.554228 [CA 4] Center 36 (8~64) winsize 57
6007 19:52:59.557450 [CA 5] Center 36 (8~64) winsize 57
6008 19:52:59.557531
6009 19:52:59.560716 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6010 19:52:59.560797
6011 19:52:59.564081 [CATrainingPosCal] consider 2 rank data
6012 19:52:59.567803 u2DelayCellTimex100 = 270/100 ps
6013 19:52:59.570767 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6014 19:52:59.574049 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6015 19:52:59.580758 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6016 19:52:59.583862 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6017 19:52:59.587425 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6018 19:52:59.590655 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6019 19:52:59.590739
6020 19:52:59.593878 CA PerBit enable=1, Macro0, CA PI delay=36
6021 19:52:59.593959
6022 19:52:59.597276 [CBTSetCACLKResult] CA Dly = 36
6023 19:52:59.597356 CS Dly: 1 (0~32)
6024 19:52:59.597421
6025 19:52:59.600511 ----->DramcWriteLeveling(PI) begin...
6026 19:52:59.603633 ==
6027 19:52:59.607090 Dram Type= 6, Freq= 0, CH_0, rank 0
6028 19:52:59.610769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6029 19:52:59.610851 ==
6030 19:52:59.613757 Write leveling (Byte 0): 32 => 0
6031 19:52:59.616940 Write leveling (Byte 1): 32 => 0
6032 19:52:59.620448 DramcWriteLeveling(PI) end<-----
6033 19:52:59.620529
6034 19:52:59.620593 ==
6035 19:52:59.623541 Dram Type= 6, Freq= 0, CH_0, rank 0
6036 19:52:59.627174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6037 19:52:59.627254 ==
6038 19:52:59.630315 [Gating] SW mode calibration
6039 19:52:59.636823 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6040 19:52:59.643507 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6041 19:52:59.646727 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6042 19:52:59.650145 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6043 19:52:59.653478 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6044 19:52:59.660059 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6045 19:52:59.663588 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6046 19:52:59.666695 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6047 19:52:59.673296 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6048 19:52:59.676511 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6049 19:52:59.679916 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6050 19:52:59.683435 Total UI for P1: 0, mck2ui 16
6051 19:52:59.686973 best dqsien dly found for B0: ( 0, 10, 16)
6052 19:52:59.689861 Total UI for P1: 0, mck2ui 16
6053 19:52:59.693096 best dqsien dly found for B1: ( 0, 10, 24)
6054 19:52:59.697250 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6055 19:52:59.703265 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6056 19:52:59.703347
6057 19:52:59.706422 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6058 19:52:59.709773 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6059 19:52:59.712850 [Gating] SW calibration Done
6060 19:52:59.712930 ==
6061 19:52:59.716249 Dram Type= 6, Freq= 0, CH_0, rank 0
6062 19:52:59.719744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6063 19:52:59.719826 ==
6064 19:52:59.722837 RX Vref Scan: 0
6065 19:52:59.722917
6066 19:52:59.722981 RX Vref 0 -> 0, step: 1
6067 19:52:59.723041
6068 19:52:59.726317 RX Delay -410 -> 252, step: 16
6069 19:52:59.732880 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6070 19:52:59.736250 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6071 19:52:59.739578 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6072 19:52:59.742655 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6073 19:52:59.749771 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6074 19:52:59.752616 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6075 19:52:59.756002 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6076 19:52:59.759322 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6077 19:52:59.762759 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6078 19:52:59.769268 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6079 19:52:59.772717 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6080 19:52:59.776118 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6081 19:52:59.782623 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6082 19:52:59.786187 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6083 19:52:59.789183 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6084 19:52:59.792643 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6085 19:52:59.792724 ==
6086 19:52:59.795716 Dram Type= 6, Freq= 0, CH_0, rank 0
6087 19:52:59.802528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6088 19:52:59.802609 ==
6089 19:52:59.802672 DQS Delay:
6090 19:52:59.806123 DQS0 = 51, DQS1 = 59
6091 19:52:59.806204 DQM Delay:
6092 19:52:59.809221 DQM0 = 12, DQM1 = 15
6093 19:52:59.809302 DQ Delay:
6094 19:52:59.812746 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6095 19:52:59.815860 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6096 19:52:59.819300 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6097 19:52:59.822306 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6098 19:52:59.822387
6099 19:52:59.822451
6100 19:52:59.822511 ==
6101 19:52:59.825716 Dram Type= 6, Freq= 0, CH_0, rank 0
6102 19:52:59.829109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6103 19:52:59.829190 ==
6104 19:52:59.829254
6105 19:52:59.829314
6106 19:52:59.832065 TX Vref Scan disable
6107 19:52:59.832145 == TX Byte 0 ==
6108 19:52:59.838818 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6109 19:52:59.842212 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6110 19:52:59.842293 == TX Byte 1 ==
6111 19:52:59.848772 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6112 19:52:59.851919 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6113 19:52:59.852000 ==
6114 19:52:59.855300 Dram Type= 6, Freq= 0, CH_0, rank 0
6115 19:52:59.858654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6116 19:52:59.858735 ==
6117 19:52:59.858800
6118 19:52:59.858860
6119 19:52:59.862047 TX Vref Scan disable
6120 19:52:59.865264 == TX Byte 0 ==
6121 19:52:59.868492 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6122 19:52:59.871889 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6123 19:52:59.875825 == TX Byte 1 ==
6124 19:52:59.878401 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6125 19:52:59.881660 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6126 19:52:59.881762
6127 19:52:59.881861 [DATLAT]
6128 19:52:59.885108 Freq=400, CH0 RK0
6129 19:52:59.885186
6130 19:52:59.888341 DATLAT Default: 0xf
6131 19:52:59.888443 0, 0xFFFF, sum = 0
6132 19:52:59.891653 1, 0xFFFF, sum = 0
6133 19:52:59.891759 2, 0xFFFF, sum = 0
6134 19:52:59.895184 3, 0xFFFF, sum = 0
6135 19:52:59.895262 4, 0xFFFF, sum = 0
6136 19:52:59.898200 5, 0xFFFF, sum = 0
6137 19:52:59.898301 6, 0xFFFF, sum = 0
6138 19:52:59.901950 7, 0xFFFF, sum = 0
6139 19:52:59.902050 8, 0xFFFF, sum = 0
6140 19:52:59.905351 9, 0xFFFF, sum = 0
6141 19:52:59.905451 10, 0xFFFF, sum = 0
6142 19:52:59.908325 11, 0xFFFF, sum = 0
6143 19:52:59.908401 12, 0x0, sum = 1
6144 19:52:59.911633 13, 0x0, sum = 2
6145 19:52:59.911732 14, 0x0, sum = 3
6146 19:52:59.914901 15, 0x0, sum = 4
6147 19:52:59.915001 best_step = 13
6148 19:52:59.915099
6149 19:52:59.915194 ==
6150 19:52:59.918337 Dram Type= 6, Freq= 0, CH_0, rank 0
6151 19:52:59.921468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6152 19:52:59.924688 ==
6153 19:52:59.924763 RX Vref Scan: 1
6154 19:52:59.924847
6155 19:52:59.928188 RX Vref 0 -> 0, step: 1
6156 19:52:59.928286
6157 19:52:59.931710 RX Delay -359 -> 252, step: 8
6158 19:52:59.931812
6159 19:52:59.934840 Set Vref, RX VrefLevel [Byte0]: 51
6160 19:52:59.937960 [Byte1]: 48
6161 19:52:59.938058
6162 19:52:59.941141 Final RX Vref Byte 0 = 51 to rank0
6163 19:52:59.944488 Final RX Vref Byte 1 = 48 to rank0
6164 19:52:59.947833 Final RX Vref Byte 0 = 51 to rank1
6165 19:52:59.951164 Final RX Vref Byte 1 = 48 to rank1==
6166 19:52:59.954461 Dram Type= 6, Freq= 0, CH_0, rank 0
6167 19:52:59.958274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6168 19:52:59.958376 ==
6169 19:52:59.961207 DQS Delay:
6170 19:52:59.961307 DQS0 = 52, DQS1 = 68
6171 19:52:59.964681 DQM Delay:
6172 19:52:59.964783 DQM0 = 8, DQM1 = 16
6173 19:52:59.964883 DQ Delay:
6174 19:52:59.967705 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6175 19:52:59.971668 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6176 19:52:59.974178 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6177 19:52:59.977756 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6178 19:52:59.977858
6179 19:52:59.977958
6180 19:52:59.987511 [DQSOSCAuto] RK0, (LSB)MR18= 0xb1b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6181 19:52:59.987616 CH0 RK0: MR19=C0C, MR18=B1B1
6182 19:52:59.994406 CH0_RK0: MR19=0xC0C, MR18=0xB1B1, DQSOSC=387, MR23=63, INC=394, DEC=262
6183 19:52:59.994512 ==
6184 19:52:59.997850 Dram Type= 6, Freq= 0, CH_0, rank 1
6185 19:53:00.004285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6186 19:53:00.004367 ==
6187 19:53:00.007466 [Gating] SW mode calibration
6188 19:53:00.014068 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6189 19:53:00.017475 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6190 19:53:00.024151 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6191 19:53:00.027505 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6192 19:53:00.030817 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6193 19:53:00.037278 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6194 19:53:00.040694 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6195 19:53:00.044060 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6196 19:53:00.050659 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6197 19:53:00.054131 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6198 19:53:00.057444 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6199 19:53:00.060434 Total UI for P1: 0, mck2ui 16
6200 19:53:00.063696 best dqsien dly found for B0: ( 0, 10, 16)
6201 19:53:00.067474 Total UI for P1: 0, mck2ui 16
6202 19:53:00.070776 best dqsien dly found for B1: ( 0, 10, 24)
6203 19:53:00.073777 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6204 19:53:00.077021 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6205 19:53:00.077100
6206 19:53:00.083596 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6207 19:53:00.086910 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6208 19:53:00.087011 [Gating] SW calibration Done
6209 19:53:00.090402 ==
6210 19:53:00.093651 Dram Type= 6, Freq= 0, CH_0, rank 1
6211 19:53:00.097034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6212 19:53:00.097134 ==
6213 19:53:00.097237 RX Vref Scan: 0
6214 19:53:00.097336
6215 19:53:00.100350 RX Vref 0 -> 0, step: 1
6216 19:53:00.100448
6217 19:53:00.103637 RX Delay -410 -> 252, step: 16
6218 19:53:00.107019 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6219 19:53:00.110290 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6220 19:53:00.116873 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6221 19:53:00.120505 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6222 19:53:00.123747 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6223 19:53:00.127206 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6224 19:53:00.133831 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6225 19:53:00.136812 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6226 19:53:00.140271 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6227 19:53:00.143648 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6228 19:53:00.150366 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6229 19:53:00.153755 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6230 19:53:00.156660 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6231 19:53:00.163354 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6232 19:53:00.166802 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6233 19:53:00.169990 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6234 19:53:00.170088 ==
6235 19:53:00.173382 Dram Type= 6, Freq= 0, CH_0, rank 1
6236 19:53:00.176663 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6237 19:53:00.176770 ==
6238 19:53:00.180035 DQS Delay:
6239 19:53:00.180131 DQS0 = 43, DQS1 = 59
6240 19:53:00.183279 DQM Delay:
6241 19:53:00.183355 DQM0 = 6, DQM1 = 14
6242 19:53:00.187138 DQ Delay:
6243 19:53:00.187242 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6244 19:53:00.189958 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6245 19:53:00.193397 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6246 19:53:00.196620 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6247 19:53:00.196722
6248 19:53:00.196814
6249 19:53:00.196911 ==
6250 19:53:00.200193 Dram Type= 6, Freq= 0, CH_0, rank 1
6251 19:53:00.206723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6252 19:53:00.206843 ==
6253 19:53:00.206943
6254 19:53:00.207041
6255 19:53:00.207139 TX Vref Scan disable
6256 19:53:00.210060 == TX Byte 0 ==
6257 19:53:00.213222 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6258 19:53:00.216667 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6259 19:53:00.220021 == TX Byte 1 ==
6260 19:53:00.223305 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6261 19:53:00.226648 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6262 19:53:00.226730 ==
6263 19:53:00.229668 Dram Type= 6, Freq= 0, CH_0, rank 1
6264 19:53:00.236732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6265 19:53:00.236814 ==
6266 19:53:00.236879
6267 19:53:00.236939
6268 19:53:00.236997 TX Vref Scan disable
6269 19:53:00.240018 == TX Byte 0 ==
6270 19:53:00.243485 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6271 19:53:00.246849 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6272 19:53:00.249707 == TX Byte 1 ==
6273 19:53:00.253034 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6274 19:53:00.256542 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6275 19:53:00.256623
6276 19:53:00.259993 [DATLAT]
6277 19:53:00.260073 Freq=400, CH0 RK1
6278 19:53:00.260139
6279 19:53:00.263041 DATLAT Default: 0xd
6280 19:53:00.263122 0, 0xFFFF, sum = 0
6281 19:53:00.266578 1, 0xFFFF, sum = 0
6282 19:53:00.266660 2, 0xFFFF, sum = 0
6283 19:53:00.269643 3, 0xFFFF, sum = 0
6284 19:53:00.269726 4, 0xFFFF, sum = 0
6285 19:53:00.273041 5, 0xFFFF, sum = 0
6286 19:53:00.273124 6, 0xFFFF, sum = 0
6287 19:53:00.276339 7, 0xFFFF, sum = 0
6288 19:53:00.276422 8, 0xFFFF, sum = 0
6289 19:53:00.279737 9, 0xFFFF, sum = 0
6290 19:53:00.279820 10, 0xFFFF, sum = 0
6291 19:53:00.283198 11, 0xFFFF, sum = 0
6292 19:53:00.283280 12, 0x0, sum = 1
6293 19:53:00.286310 13, 0x0, sum = 2
6294 19:53:00.286460 14, 0x0, sum = 3
6295 19:53:00.289300 15, 0x0, sum = 4
6296 19:53:00.289375 best_step = 13
6297 19:53:00.289438
6298 19:53:00.289498 ==
6299 19:53:00.293027 Dram Type= 6, Freq= 0, CH_0, rank 1
6300 19:53:00.299394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6301 19:53:00.299479 ==
6302 19:53:00.299546 RX Vref Scan: 0
6303 19:53:00.299610
6304 19:53:00.302999 RX Vref 0 -> 0, step: 1
6305 19:53:00.303096
6306 19:53:00.306148 RX Delay -359 -> 252, step: 8
6307 19:53:00.312674 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6308 19:53:00.316154 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6309 19:53:00.319706 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6310 19:53:00.325907 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6311 19:53:00.329231 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6312 19:53:00.332701 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6313 19:53:00.335826 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6314 19:53:00.339150 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6315 19:53:00.345780 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6316 19:53:00.349239 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6317 19:53:00.352663 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6318 19:53:00.358829 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6319 19:53:00.362325 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6320 19:53:00.365834 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6321 19:53:00.369355 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6322 19:53:00.375808 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6323 19:53:00.375908 ==
6324 19:53:00.379050 Dram Type= 6, Freq= 0, CH_0, rank 1
6325 19:53:00.382239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6326 19:53:00.382349 ==
6327 19:53:00.382437 DQS Delay:
6328 19:53:00.385692 DQS0 = 52, DQS1 = 60
6329 19:53:00.385811 DQM Delay:
6330 19:53:00.389234 DQM0 = 10, DQM1 = 11
6331 19:53:00.389353 DQ Delay:
6332 19:53:00.392420 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6333 19:53:00.395717 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6334 19:53:00.398827 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6335 19:53:00.402220 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =16
6336 19:53:00.402301
6337 19:53:00.402365
6338 19:53:00.408772 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1c1, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6339 19:53:00.412430 CH0 RK1: MR19=C0C, MR18=C1C1
6340 19:53:00.418658 CH0_RK1: MR19=0xC0C, MR18=0xC1C1, DQSOSC=385, MR23=63, INC=398, DEC=265
6341 19:53:00.422284 [RxdqsGatingPostProcess] freq 400
6342 19:53:00.428555 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6343 19:53:00.432090 Pre-setting of DQS Precalculation
6344 19:53:00.435421 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6345 19:53:00.435501 ==
6346 19:53:00.438524 Dram Type= 6, Freq= 0, CH_1, rank 0
6347 19:53:00.441902 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6348 19:53:00.441983 ==
6349 19:53:00.448171 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6350 19:53:00.455036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6351 19:53:00.458611 [CA 0] Center 36 (8~64) winsize 57
6352 19:53:00.461772 [CA 1] Center 36 (8~64) winsize 57
6353 19:53:00.464988 [CA 2] Center 36 (8~64) winsize 57
6354 19:53:00.468109 [CA 3] Center 36 (8~64) winsize 57
6355 19:53:00.471477 [CA 4] Center 36 (8~64) winsize 57
6356 19:53:00.475025 [CA 5] Center 36 (8~64) winsize 57
6357 19:53:00.475105
6358 19:53:00.478040 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6359 19:53:00.478120
6360 19:53:00.481523 [CATrainingPosCal] consider 1 rank data
6361 19:53:00.484734 u2DelayCellTimex100 = 270/100 ps
6362 19:53:00.488368 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6363 19:53:00.491519 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6364 19:53:00.494629 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6365 19:53:00.497938 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6366 19:53:00.501278 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 19:53:00.504658 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 19:53:00.504738
6369 19:53:00.508147 CA PerBit enable=1, Macro0, CA PI delay=36
6370 19:53:00.511339
6371 19:53:00.511418 [CBTSetCACLKResult] CA Dly = 36
6372 19:53:00.514714 CS Dly: 1 (0~32)
6373 19:53:00.514794 ==
6374 19:53:00.517841 Dram Type= 6, Freq= 0, CH_1, rank 1
6375 19:53:00.521186 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6376 19:53:00.521267 ==
6377 19:53:00.527673 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6378 19:53:00.534367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6379 19:53:00.537593 [CA 0] Center 36 (8~64) winsize 57
6380 19:53:00.540865 [CA 1] Center 36 (8~64) winsize 57
6381 19:53:00.544191 [CA 2] Center 36 (8~64) winsize 57
6382 19:53:00.544273 [CA 3] Center 36 (8~64) winsize 57
6383 19:53:00.547692 [CA 4] Center 36 (8~64) winsize 57
6384 19:53:00.550996 [CA 5] Center 36 (8~64) winsize 57
6385 19:53:00.551077
6386 19:53:00.557391 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6387 19:53:00.557472
6388 19:53:00.560739 [CATrainingPosCal] consider 2 rank data
6389 19:53:00.564019 u2DelayCellTimex100 = 270/100 ps
6390 19:53:00.567509 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6391 19:53:00.571108 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6392 19:53:00.574002 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6393 19:53:00.577212 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6394 19:53:00.580879 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6395 19:53:00.583831 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6396 19:53:00.583944
6397 19:53:00.587095 CA PerBit enable=1, Macro0, CA PI delay=36
6398 19:53:00.587176
6399 19:53:00.590402 [CBTSetCACLKResult] CA Dly = 36
6400 19:53:00.594152 CS Dly: 1 (0~32)
6401 19:53:00.594233
6402 19:53:00.597017 ----->DramcWriteLeveling(PI) begin...
6403 19:53:00.597100 ==
6404 19:53:00.600372 Dram Type= 6, Freq= 0, CH_1, rank 0
6405 19:53:00.603695 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6406 19:53:00.603777 ==
6407 19:53:00.607006 Write leveling (Byte 0): 32 => 0
6408 19:53:00.610142 Write leveling (Byte 1): 32 => 0
6409 19:53:00.613382 DramcWriteLeveling(PI) end<-----
6410 19:53:00.613464
6411 19:53:00.613529 ==
6412 19:53:00.616972 Dram Type= 6, Freq= 0, CH_1, rank 0
6413 19:53:00.619989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6414 19:53:00.620070 ==
6415 19:53:00.623453 [Gating] SW mode calibration
6416 19:53:00.630078 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6417 19:53:00.637151 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6418 19:53:00.640086 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 19:53:00.646624 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 19:53:00.649923 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 19:53:00.653140 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6422 19:53:00.659709 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 19:53:00.663206 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 19:53:00.666238 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 19:53:00.669784 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6426 19:53:00.676586 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 19:53:00.679470 Total UI for P1: 0, mck2ui 16
6428 19:53:00.683296 best dqsien dly found for B0: ( 0, 10, 16)
6429 19:53:00.686164 Total UI for P1: 0, mck2ui 16
6430 19:53:00.689748 best dqsien dly found for B1: ( 0, 10, 16)
6431 19:53:00.693034 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6432 19:53:00.696317 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6433 19:53:00.696423
6434 19:53:00.699773 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6435 19:53:00.702855 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6436 19:53:00.706323 [Gating] SW calibration Done
6437 19:53:00.706407 ==
6438 19:53:00.709520 Dram Type= 6, Freq= 0, CH_1, rank 0
6439 19:53:00.712751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6440 19:53:00.712831 ==
6441 19:53:00.716393 RX Vref Scan: 0
6442 19:53:00.716489
6443 19:53:00.719667 RX Vref 0 -> 0, step: 1
6444 19:53:00.719773
6445 19:53:00.719867 RX Delay -410 -> 252, step: 16
6446 19:53:00.726443 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6447 19:53:00.729412 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6448 19:53:00.732908 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6449 19:53:00.736504 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6450 19:53:00.743015 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6451 19:53:00.746110 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6452 19:53:00.749532 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6453 19:53:00.752668 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6454 19:53:00.759694 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6455 19:53:00.762622 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6456 19:53:00.766029 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6457 19:53:00.772587 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6458 19:53:00.776124 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6459 19:53:00.779760 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6460 19:53:00.782583 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6461 19:53:00.789228 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6462 19:53:00.789330 ==
6463 19:53:00.792510 Dram Type= 6, Freq= 0, CH_1, rank 0
6464 19:53:00.795944 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6465 19:53:00.796059 ==
6466 19:53:00.796150 DQS Delay:
6467 19:53:00.799008 DQS0 = 43, DQS1 = 59
6468 19:53:00.799099 DQM Delay:
6469 19:53:00.802425 DQM0 = 6, DQM1 = 15
6470 19:53:00.802521 DQ Delay:
6471 19:53:00.805703 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6472 19:53:00.809667 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6473 19:53:00.812289 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6474 19:53:00.815757 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6475 19:53:00.815851
6476 19:53:00.815940
6477 19:53:00.816026 ==
6478 19:53:00.818924 Dram Type= 6, Freq= 0, CH_1, rank 0
6479 19:53:00.822403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6480 19:53:00.822504 ==
6481 19:53:00.822592
6482 19:53:00.822679
6483 19:53:00.825940 TX Vref Scan disable
6484 19:53:00.826035 == TX Byte 0 ==
6485 19:53:00.832631 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6486 19:53:00.836150 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6487 19:53:00.838761 == TX Byte 1 ==
6488 19:53:00.842212 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6489 19:53:00.845668 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6490 19:53:00.845760 ==
6491 19:53:00.848750 Dram Type= 6, Freq= 0, CH_1, rank 0
6492 19:53:00.852159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6493 19:53:00.852268 ==
6494 19:53:00.855315
6495 19:53:00.855410
6496 19:53:00.855503 TX Vref Scan disable
6497 19:53:00.858779 == TX Byte 0 ==
6498 19:53:00.861984 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6499 19:53:00.865445 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6500 19:53:00.868885 == TX Byte 1 ==
6501 19:53:00.871896 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6502 19:53:00.875402 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6503 19:53:00.875505
6504 19:53:00.878495 [DATLAT]
6505 19:53:00.878594 Freq=400, CH1 RK0
6506 19:53:00.878683
6507 19:53:00.881901 DATLAT Default: 0xf
6508 19:53:00.882002 0, 0xFFFF, sum = 0
6509 19:53:00.885436 1, 0xFFFF, sum = 0
6510 19:53:00.885534 2, 0xFFFF, sum = 0
6511 19:53:00.888659 3, 0xFFFF, sum = 0
6512 19:53:00.888762 4, 0xFFFF, sum = 0
6513 19:53:00.891941 5, 0xFFFF, sum = 0
6514 19:53:00.892042 6, 0xFFFF, sum = 0
6515 19:53:00.895342 7, 0xFFFF, sum = 0
6516 19:53:00.895428 8, 0xFFFF, sum = 0
6517 19:53:00.898632 9, 0xFFFF, sum = 0
6518 19:53:00.898729 10, 0xFFFF, sum = 0
6519 19:53:00.901798 11, 0xFFFF, sum = 0
6520 19:53:00.901895 12, 0x0, sum = 1
6521 19:53:00.905008 13, 0x0, sum = 2
6522 19:53:00.905106 14, 0x0, sum = 3
6523 19:53:00.908696 15, 0x0, sum = 4
6524 19:53:00.908768 best_step = 13
6525 19:53:00.908831
6526 19:53:00.908888 ==
6527 19:53:00.911813 Dram Type= 6, Freq= 0, CH_1, rank 0
6528 19:53:00.918318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6529 19:53:00.918421 ==
6530 19:53:00.918513 RX Vref Scan: 1
6531 19:53:00.918600
6532 19:53:00.921695 RX Vref 0 -> 0, step: 1
6533 19:53:00.921787
6534 19:53:00.924924 RX Delay -359 -> 252, step: 8
6535 19:53:00.924994
6536 19:53:00.928359 Set Vref, RX VrefLevel [Byte0]: 53
6537 19:53:00.931641 [Byte1]: 49
6538 19:53:00.931736
6539 19:53:00.934951 Final RX Vref Byte 0 = 53 to rank0
6540 19:53:00.938140 Final RX Vref Byte 1 = 49 to rank0
6541 19:53:00.941446 Final RX Vref Byte 0 = 53 to rank1
6542 19:53:00.945136 Final RX Vref Byte 1 = 49 to rank1==
6543 19:53:00.948294 Dram Type= 6, Freq= 0, CH_1, rank 0
6544 19:53:00.951514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6545 19:53:00.954864 ==
6546 19:53:00.954960 DQS Delay:
6547 19:53:00.955051 DQS0 = 48, DQS1 = 64
6548 19:53:00.958298 DQM Delay:
6549 19:53:00.958393 DQM0 = 8, DQM1 = 15
6550 19:53:00.961666 DQ Delay:
6551 19:53:00.961761 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6552 19:53:00.964768 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6553 19:53:00.968150 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6554 19:53:00.971452 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6555 19:53:00.971548
6556 19:53:00.971640
6557 19:53:00.981471 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1d1, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6558 19:53:00.984754 CH1 RK0: MR19=C0C, MR18=D1D1
6559 19:53:00.988143 CH1_RK0: MR19=0xC0C, MR18=0xD1D1, DQSOSC=384, MR23=63, INC=400, DEC=267
6560 19:53:00.991406 ==
6561 19:53:00.994675 Dram Type= 6, Freq= 0, CH_1, rank 1
6562 19:53:00.997920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6563 19:53:00.998017 ==
6564 19:53:01.001346 [Gating] SW mode calibration
6565 19:53:01.007929 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6566 19:53:01.011388 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6567 19:53:01.017994 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6568 19:53:01.021373 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6569 19:53:01.024611 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6570 19:53:01.031583 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6571 19:53:01.034645 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6572 19:53:01.037714 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6573 19:53:01.044557 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6574 19:53:01.047668 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6575 19:53:01.051106 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6576 19:53:01.054353 Total UI for P1: 0, mck2ui 16
6577 19:53:01.057627 best dqsien dly found for B0: ( 0, 10, 16)
6578 19:53:01.060920 Total UI for P1: 0, mck2ui 16
6579 19:53:01.064534 best dqsien dly found for B1: ( 0, 10, 16)
6580 19:53:01.067588 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6581 19:53:01.070986 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6582 19:53:01.071082
6583 19:53:01.077849 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6584 19:53:01.081033 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6585 19:53:01.084468 [Gating] SW calibration Done
6586 19:53:01.084567 ==
6587 19:53:01.087518 Dram Type= 6, Freq= 0, CH_1, rank 1
6588 19:53:01.090905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6589 19:53:01.090977 ==
6590 19:53:01.091060 RX Vref Scan: 0
6591 19:53:01.091148
6592 19:53:01.094284 RX Vref 0 -> 0, step: 1
6593 19:53:01.094383
6594 19:53:01.097636 RX Delay -410 -> 252, step: 16
6595 19:53:01.100916 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6596 19:53:01.107951 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6597 19:53:01.111322 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6598 19:53:01.114189 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6599 19:53:01.117541 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6600 19:53:01.123975 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6601 19:53:01.127549 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6602 19:53:01.130660 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6603 19:53:01.133939 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6604 19:53:01.140818 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6605 19:53:01.144126 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6606 19:53:01.147585 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6607 19:53:01.150866 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6608 19:53:01.157312 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6609 19:53:01.160809 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6610 19:53:01.163877 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6611 19:53:01.163984 ==
6612 19:53:01.167123 Dram Type= 6, Freq= 0, CH_1, rank 1
6613 19:53:01.170570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6614 19:53:01.173726 ==
6615 19:53:01.173823 DQS Delay:
6616 19:53:01.173921 DQS0 = 43, DQS1 = 59
6617 19:53:01.177485 DQM Delay:
6618 19:53:01.177557 DQM0 = 9, DQM1 = 18
6619 19:53:01.180572 DQ Delay:
6620 19:53:01.180677 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6621 19:53:01.183755 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6622 19:53:01.187046 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6623 19:53:01.190357 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6624 19:53:01.190455
6625 19:53:01.190556
6626 19:53:01.190644 ==
6627 19:53:01.193761 Dram Type= 6, Freq= 0, CH_1, rank 1
6628 19:53:01.200137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6629 19:53:01.200231 ==
6630 19:53:01.200299
6631 19:53:01.200359
6632 19:53:01.203567 TX Vref Scan disable
6633 19:53:01.203664 == TX Byte 0 ==
6634 19:53:01.206990 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6635 19:53:01.210385 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6636 19:53:01.213800 == TX Byte 1 ==
6637 19:53:01.217085 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6638 19:53:01.220250 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6639 19:53:01.223730 ==
6640 19:53:01.223829 Dram Type= 6, Freq= 0, CH_1, rank 1
6641 19:53:01.230066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6642 19:53:01.230168 ==
6643 19:53:01.230261
6644 19:53:01.230348
6645 19:53:01.233632 TX Vref Scan disable
6646 19:53:01.233730 == TX Byte 0 ==
6647 19:53:01.237169 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6648 19:53:01.243554 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6649 19:53:01.243658 == TX Byte 1 ==
6650 19:53:01.246780 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6651 19:53:01.250046 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6652 19:53:01.253380
6653 19:53:01.253451 [DATLAT]
6654 19:53:01.253517 Freq=400, CH1 RK1
6655 19:53:01.253579
6656 19:53:01.256776 DATLAT Default: 0xd
6657 19:53:01.256852 0, 0xFFFF, sum = 0
6658 19:53:01.260160 1, 0xFFFF, sum = 0
6659 19:53:01.260295 2, 0xFFFF, sum = 0
6660 19:53:01.263610 3, 0xFFFF, sum = 0
6661 19:53:01.263713 4, 0xFFFF, sum = 0
6662 19:53:01.266507 5, 0xFFFF, sum = 0
6663 19:53:01.270088 6, 0xFFFF, sum = 0
6664 19:53:01.270185 7, 0xFFFF, sum = 0
6665 19:53:01.273200 8, 0xFFFF, sum = 0
6666 19:53:01.273297 9, 0xFFFF, sum = 0
6667 19:53:01.276613 10, 0xFFFF, sum = 0
6668 19:53:01.276687 11, 0xFFFF, sum = 0
6669 19:53:01.279823 12, 0x0, sum = 1
6670 19:53:01.279920 13, 0x0, sum = 2
6671 19:53:01.283079 14, 0x0, sum = 3
6672 19:53:01.283177 15, 0x0, sum = 4
6673 19:53:01.283241 best_step = 13
6674 19:53:01.286777
6675 19:53:01.286867 ==
6676 19:53:01.289715 Dram Type= 6, Freq= 0, CH_1, rank 1
6677 19:53:01.293259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6678 19:53:01.293334 ==
6679 19:53:01.293396 RX Vref Scan: 0
6680 19:53:01.293455
6681 19:53:01.296532 RX Vref 0 -> 0, step: 1
6682 19:53:01.296601
6683 19:53:01.299764 RX Delay -359 -> 252, step: 8
6684 19:53:01.306812 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6685 19:53:01.310197 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6686 19:53:01.313201 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6687 19:53:01.319869 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6688 19:53:01.323413 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6689 19:53:01.326521 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6690 19:53:01.329884 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6691 19:53:01.336844 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6692 19:53:01.339852 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6693 19:53:01.343167 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6694 19:53:01.346364 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6695 19:53:01.352956 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6696 19:53:01.356453 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6697 19:53:01.359676 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6698 19:53:01.362917 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6699 19:53:01.369705 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6700 19:53:01.369810 ==
6701 19:53:01.372986 Dram Type= 6, Freq= 0, CH_1, rank 1
6702 19:53:01.376024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6703 19:53:01.376149 ==
6704 19:53:01.376301 DQS Delay:
6705 19:53:01.380184 DQS0 = 44, DQS1 = 64
6706 19:53:01.380298 DQM Delay:
6707 19:53:01.383005 DQM0 = 5, DQM1 = 15
6708 19:53:01.383091 DQ Delay:
6709 19:53:01.386241 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6710 19:53:01.389837 DQ4 =4, DQ5 =16, DQ6 =12, DQ7 =4
6711 19:53:01.393014 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6712 19:53:01.396086 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6713 19:53:01.396168
6714 19:53:01.396272
6715 19:53:01.402733 [DQSOSCAuto] RK1, (LSB)MR18= 0xb8b8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6716 19:53:01.406119 CH1 RK1: MR19=C0C, MR18=B8B8
6717 19:53:01.412744 CH1_RK1: MR19=0xC0C, MR18=0xB8B8, DQSOSC=386, MR23=63, INC=396, DEC=264
6718 19:53:01.416164 [RxdqsGatingPostProcess] freq 400
6719 19:53:01.422784 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6720 19:53:01.422866 Pre-setting of DQS Precalculation
6721 19:53:01.429482 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6722 19:53:01.436194 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6723 19:53:01.442794 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6724 19:53:01.442875
6725 19:53:01.442939
6726 19:53:01.445981 [Calibration Summary] 800 Mbps
6727 19:53:01.449222 CH 0, Rank 0
6728 19:53:01.449303 SW Impedance : PASS
6729 19:53:01.452489 DUTY Scan : NO K
6730 19:53:01.455932 ZQ Calibration : PASS
6731 19:53:01.456013 Jitter Meter : NO K
6732 19:53:01.459257 CBT Training : PASS
6733 19:53:01.462957 Write leveling : PASS
6734 19:53:01.463038 RX DQS gating : PASS
6735 19:53:01.465708 RX DQ/DQS(RDDQC) : PASS
6736 19:53:01.465790 TX DQ/DQS : PASS
6737 19:53:01.469173 RX DATLAT : PASS
6738 19:53:01.472519 RX DQ/DQS(Engine): PASS
6739 19:53:01.472600 TX OE : NO K
6740 19:53:01.475611 All Pass.
6741 19:53:01.475692
6742 19:53:01.475757 CH 0, Rank 1
6743 19:53:01.479215 SW Impedance : PASS
6744 19:53:01.479297 DUTY Scan : NO K
6745 19:53:01.482343 ZQ Calibration : PASS
6746 19:53:01.485925 Jitter Meter : NO K
6747 19:53:01.486006 CBT Training : PASS
6748 19:53:01.489032 Write leveling : NO K
6749 19:53:01.492151 RX DQS gating : PASS
6750 19:53:01.492314 RX DQ/DQS(RDDQC) : PASS
6751 19:53:01.495701 TX DQ/DQS : PASS
6752 19:53:01.499164 RX DATLAT : PASS
6753 19:53:01.499246 RX DQ/DQS(Engine): PASS
6754 19:53:01.502329 TX OE : NO K
6755 19:53:01.502411 All Pass.
6756 19:53:01.502476
6757 19:53:01.505718 CH 1, Rank 0
6758 19:53:01.505799 SW Impedance : PASS
6759 19:53:01.508930 DUTY Scan : NO K
6760 19:53:01.512223 ZQ Calibration : PASS
6761 19:53:01.512304 Jitter Meter : NO K
6762 19:53:01.515464 CBT Training : PASS
6763 19:53:01.518569 Write leveling : PASS
6764 19:53:01.518650 RX DQS gating : PASS
6765 19:53:01.521824 RX DQ/DQS(RDDQC) : PASS
6766 19:53:01.525243 TX DQ/DQS : PASS
6767 19:53:01.525324 RX DATLAT : PASS
6768 19:53:01.528584 RX DQ/DQS(Engine): PASS
6769 19:53:01.528665 TX OE : NO K
6770 19:53:01.531828 All Pass.
6771 19:53:01.531908
6772 19:53:01.531973 CH 1, Rank 1
6773 19:53:01.535564 SW Impedance : PASS
6774 19:53:01.535645 DUTY Scan : NO K
6775 19:53:01.538528 ZQ Calibration : PASS
6776 19:53:01.541973 Jitter Meter : NO K
6777 19:53:01.542054 CBT Training : PASS
6778 19:53:01.545291 Write leveling : NO K
6779 19:53:01.548472 RX DQS gating : PASS
6780 19:53:01.548553 RX DQ/DQS(RDDQC) : PASS
6781 19:53:01.551866 TX DQ/DQS : PASS
6782 19:53:01.555223 RX DATLAT : PASS
6783 19:53:01.555304 RX DQ/DQS(Engine): PASS
6784 19:53:01.558857 TX OE : NO K
6785 19:53:01.558938 All Pass.
6786 19:53:01.559003
6787 19:53:01.562115 DramC Write-DBI off
6788 19:53:01.564861 PER_BANK_REFRESH: Hybrid Mode
6789 19:53:01.564942 TX_TRACKING: ON
6790 19:53:01.574808 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6791 19:53:01.578052 [FAST_K] Save calibration result to emmc
6792 19:53:01.581406 dramc_set_vcore_voltage set vcore to 725000
6793 19:53:01.585154 Read voltage for 1600, 0
6794 19:53:01.585236 Vio18 = 0
6795 19:53:01.585300 Vcore = 725000
6796 19:53:01.588060 Vdram = 0
6797 19:53:01.588141 Vddq = 0
6798 19:53:01.588259 Vmddr = 0
6799 19:53:01.594721 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6800 19:53:01.597995 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6801 19:53:01.601387 MEM_TYPE=3, freq_sel=13
6802 19:53:01.604742 sv_algorithm_assistance_LP4_3733
6803 19:53:01.607846 ============ PULL DRAM RESETB DOWN ============
6804 19:53:01.614799 ========== PULL DRAM RESETB DOWN end =========
6805 19:53:01.617835 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6806 19:53:01.621084 ===================================
6807 19:53:01.624502 LPDDR4 DRAM CONFIGURATION
6808 19:53:01.627754 ===================================
6809 19:53:01.627854 EX_ROW_EN[0] = 0x0
6810 19:53:01.631117 EX_ROW_EN[1] = 0x0
6811 19:53:01.631187 LP4Y_EN = 0x0
6812 19:53:01.634498 WORK_FSP = 0x1
6813 19:53:01.634579 WL = 0x5
6814 19:53:01.637825 RL = 0x5
6815 19:53:01.637906 BL = 0x2
6816 19:53:01.641284 RPST = 0x0
6817 19:53:01.644456 RD_PRE = 0x0
6818 19:53:01.644536 WR_PRE = 0x1
6819 19:53:01.647597 WR_PST = 0x1
6820 19:53:01.647678 DBI_WR = 0x0
6821 19:53:01.651050 DBI_RD = 0x0
6822 19:53:01.651131 OTF = 0x1
6823 19:53:01.654309 ===================================
6824 19:53:01.657616 ===================================
6825 19:53:01.660684 ANA top config
6826 19:53:01.664092 ===================================
6827 19:53:01.664195 DLL_ASYNC_EN = 0
6828 19:53:01.667411 ALL_SLAVE_EN = 0
6829 19:53:01.670640 NEW_RANK_MODE = 1
6830 19:53:01.674071 DLL_IDLE_MODE = 1
6831 19:53:01.674152 LP45_APHY_COMB_EN = 1
6832 19:53:01.677367 TX_ODT_DIS = 0
6833 19:53:01.680718 NEW_8X_MODE = 1
6834 19:53:01.683885 ===================================
6835 19:53:01.687364 ===================================
6836 19:53:01.690660 data_rate = 3200
6837 19:53:01.693766 CKR = 1
6838 19:53:01.697387 DQ_P2S_RATIO = 8
6839 19:53:01.700591 ===================================
6840 19:53:01.700672 CA_P2S_RATIO = 8
6841 19:53:01.703916 DQ_CA_OPEN = 0
6842 19:53:01.706817 DQ_SEMI_OPEN = 0
6843 19:53:01.710242 CA_SEMI_OPEN = 0
6844 19:53:01.713839 CA_FULL_RATE = 0
6845 19:53:01.717044 DQ_CKDIV4_EN = 0
6846 19:53:01.717126 CA_CKDIV4_EN = 0
6847 19:53:01.720126 CA_PREDIV_EN = 0
6848 19:53:01.723416 PH8_DLY = 12
6849 19:53:01.726937 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6850 19:53:01.730190 DQ_AAMCK_DIV = 4
6851 19:53:01.733440 CA_AAMCK_DIV = 4
6852 19:53:01.733521 CA_ADMCK_DIV = 4
6853 19:53:01.736916 DQ_TRACK_CA_EN = 0
6854 19:53:01.740365 CA_PICK = 1600
6855 19:53:01.743419 CA_MCKIO = 1600
6856 19:53:01.746944 MCKIO_SEMI = 0
6857 19:53:01.750392 PLL_FREQ = 3068
6858 19:53:01.753234 DQ_UI_PI_RATIO = 32
6859 19:53:01.753315 CA_UI_PI_RATIO = 0
6860 19:53:01.756742 ===================================
6861 19:53:01.760067 ===================================
6862 19:53:01.763114 memory_type:LPDDR4
6863 19:53:01.766609 GP_NUM : 10
6864 19:53:01.766690 SRAM_EN : 1
6865 19:53:01.770128 MD32_EN : 0
6866 19:53:01.773195 ===================================
6867 19:53:01.776695 [ANA_INIT] >>>>>>>>>>>>>>
6868 19:53:01.779953 <<<<<< [CONFIGURE PHASE]: ANA_TX
6869 19:53:01.783191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6870 19:53:01.786455 ===================================
6871 19:53:01.786537 data_rate = 3200,PCW = 0X7600
6872 19:53:01.789654 ===================================
6873 19:53:01.796346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6874 19:53:01.799619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6875 19:53:01.806261 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6876 19:53:01.809572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6877 19:53:01.813137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6878 19:53:01.816170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6879 19:53:01.819650 [ANA_INIT] flow start
6880 19:53:01.822779 [ANA_INIT] PLL >>>>>>>>
6881 19:53:01.822860 [ANA_INIT] PLL <<<<<<<<
6882 19:53:01.826181 [ANA_INIT] MIDPI >>>>>>>>
6883 19:53:01.829598 [ANA_INIT] MIDPI <<<<<<<<
6884 19:53:01.829679 [ANA_INIT] DLL >>>>>>>>
6885 19:53:01.833020 [ANA_INIT] DLL <<<<<<<<
6886 19:53:01.836324 [ANA_INIT] flow end
6887 19:53:01.839569 ============ LP4 DIFF to SE enter ============
6888 19:53:01.842736 ============ LP4 DIFF to SE exit ============
6889 19:53:01.846399 [ANA_INIT] <<<<<<<<<<<<<
6890 19:53:01.849799 [Flow] Enable top DCM control >>>>>
6891 19:53:01.852846 [Flow] Enable top DCM control <<<<<
6892 19:53:01.855973 Enable DLL master slave shuffle
6893 19:53:01.859484 ==============================================================
6894 19:53:01.862766 Gating Mode config
6895 19:53:01.869411 ==============================================================
6896 19:53:01.869517 Config description:
6897 19:53:01.879173 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6898 19:53:01.886159 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6899 19:53:01.889235 SELPH_MODE 0: By rank 1: By Phase
6900 19:53:01.895669 ==============================================================
6901 19:53:01.899167 GAT_TRACK_EN = 1
6902 19:53:01.902533 RX_GATING_MODE = 2
6903 19:53:01.905712 RX_GATING_TRACK_MODE = 2
6904 19:53:01.909239 SELPH_MODE = 1
6905 19:53:01.912453 PICG_EARLY_EN = 1
6906 19:53:01.915847 VALID_LAT_VALUE = 1
6907 19:53:01.919192 ==============================================================
6908 19:53:01.922315 Enter into Gating configuration >>>>
6909 19:53:01.925517 Exit from Gating configuration <<<<
6910 19:53:01.928967 Enter into DVFS_PRE_config >>>>>
6911 19:53:01.942120 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6912 19:53:01.945348 Exit from DVFS_PRE_config <<<<<
6913 19:53:01.948588 Enter into PICG configuration >>>>
6914 19:53:01.948663 Exit from PICG configuration <<<<
6915 19:53:01.951944 [RX_INPUT] configuration >>>>>
6916 19:53:01.955159 [RX_INPUT] configuration <<<<<
6917 19:53:01.961829 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6918 19:53:01.964989 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6919 19:53:01.972086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6920 19:53:01.978797 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6921 19:53:01.985010 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6922 19:53:01.991755 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6923 19:53:01.994852 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6924 19:53:01.998555 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6925 19:53:02.002125 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6926 19:53:02.008303 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6927 19:53:02.011639 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6928 19:53:02.015099 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6929 19:53:02.018131 ===================================
6930 19:53:02.021702 LPDDR4 DRAM CONFIGURATION
6931 19:53:02.025052 ===================================
6932 19:53:02.028183 EX_ROW_EN[0] = 0x0
6933 19:53:02.028269 EX_ROW_EN[1] = 0x0
6934 19:53:02.031567 LP4Y_EN = 0x0
6935 19:53:02.031647 WORK_FSP = 0x1
6936 19:53:02.035233 WL = 0x5
6937 19:53:02.035315 RL = 0x5
6938 19:53:02.038346 BL = 0x2
6939 19:53:02.038428 RPST = 0x0
6940 19:53:02.041317 RD_PRE = 0x0
6941 19:53:02.041398 WR_PRE = 0x1
6942 19:53:02.044822 WR_PST = 0x1
6943 19:53:02.044904 DBI_WR = 0x0
6944 19:53:02.048325 DBI_RD = 0x0
6945 19:53:02.051360 OTF = 0x1
6946 19:53:02.051441 ===================================
6947 19:53:02.058170 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6948 19:53:02.061631 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6949 19:53:02.064586 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6950 19:53:02.068057 ===================================
6951 19:53:02.071257 LPDDR4 DRAM CONFIGURATION
6952 19:53:02.074638 ===================================
6953 19:53:02.077647 EX_ROW_EN[0] = 0x10
6954 19:53:02.077749 EX_ROW_EN[1] = 0x0
6955 19:53:02.081119 LP4Y_EN = 0x0
6956 19:53:02.081222 WORK_FSP = 0x1
6957 19:53:02.084581 WL = 0x5
6958 19:53:02.084678 RL = 0x5
6959 19:53:02.088000 BL = 0x2
6960 19:53:02.088098 RPST = 0x0
6961 19:53:02.091200 RD_PRE = 0x0
6962 19:53:02.091288 WR_PRE = 0x1
6963 19:53:02.094451 WR_PST = 0x1
6964 19:53:02.094532 DBI_WR = 0x0
6965 19:53:02.097638 DBI_RD = 0x0
6966 19:53:02.097719 OTF = 0x1
6967 19:53:02.101057 ===================================
6968 19:53:02.107470 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6969 19:53:02.107552 ==
6970 19:53:02.110969 Dram Type= 6, Freq= 0, CH_0, rank 0
6971 19:53:02.117656 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6972 19:53:02.117738 ==
6973 19:53:02.117803 [Duty_Offset_Calibration]
6974 19:53:02.120927 B0:0 B1:2 CA:1
6975 19:53:02.121008
6976 19:53:02.124180 [DutyScan_Calibration_Flow] k_type=0
6977 19:53:02.133844
6978 19:53:02.133924 ==CLK 0==
6979 19:53:02.136876 Final CLK duty delay cell = 0
6980 19:53:02.140105 [0] MAX Duty = 5156%(X100), DQS PI = 22
6981 19:53:02.143463 [0] MIN Duty = 4938%(X100), DQS PI = 38
6982 19:53:02.146685 [0] AVG Duty = 5047%(X100)
6983 19:53:02.146767
6984 19:53:02.149917 CH0 CLK Duty spec in!! Max-Min= 218%
6985 19:53:02.153234 [DutyScan_Calibration_Flow] ====Done====
6986 19:53:02.153315
6987 19:53:02.156630 [DutyScan_Calibration_Flow] k_type=1
6988 19:53:02.172785
6989 19:53:02.172866 ==DQS 0 ==
6990 19:53:02.176048 Final DQS duty delay cell = -4
6991 19:53:02.179342 [-4] MAX Duty = 4969%(X100), DQS PI = 4
6992 19:53:02.182984 [-4] MIN Duty = 4875%(X100), DQS PI = 8
6993 19:53:02.186224 [-4] AVG Duty = 4922%(X100)
6994 19:53:02.186305
6995 19:53:02.186370 ==DQS 1 ==
6996 19:53:02.189552 Final DQS duty delay cell = 0
6997 19:53:02.192925 [0] MAX Duty = 5031%(X100), DQS PI = 2
6998 19:53:02.195827 [0] MIN Duty = 4876%(X100), DQS PI = 16
6999 19:53:02.199271 [0] AVG Duty = 4953%(X100)
7000 19:53:02.199352
7001 19:53:02.202683 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7002 19:53:02.202764
7003 19:53:02.205833 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7004 19:53:02.209199 [DutyScan_Calibration_Flow] ====Done====
7005 19:53:02.209280
7006 19:53:02.212297 [DutyScan_Calibration_Flow] k_type=3
7007 19:53:02.230599
7008 19:53:02.230679 ==DQM 0 ==
7009 19:53:02.233473 Final DQM duty delay cell = 0
7010 19:53:02.236522 [0] MAX Duty = 5187%(X100), DQS PI = 22
7011 19:53:02.240064 [0] MIN Duty = 4907%(X100), DQS PI = 56
7012 19:53:02.243259 [0] AVG Duty = 5047%(X100)
7013 19:53:02.243350
7014 19:53:02.243415 ==DQM 1 ==
7015 19:53:02.246457 Final DQM duty delay cell = 0
7016 19:53:02.249835 [0] MAX Duty = 5031%(X100), DQS PI = 4
7017 19:53:02.253070 [0] MIN Duty = 4813%(X100), DQS PI = 14
7018 19:53:02.256506 [0] AVG Duty = 4922%(X100)
7019 19:53:02.256586
7020 19:53:02.259965 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7021 19:53:02.260046
7022 19:53:02.263227 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7023 19:53:02.266529 [DutyScan_Calibration_Flow] ====Done====
7024 19:53:02.266610
7025 19:53:02.269718 [DutyScan_Calibration_Flow] k_type=2
7026 19:53:02.286262
7027 19:53:02.286342 ==DQ 0 ==
7028 19:53:02.289751 Final DQ duty delay cell = 0
7029 19:53:02.293275 [0] MAX Duty = 5218%(X100), DQS PI = 18
7030 19:53:02.296649 [0] MIN Duty = 4938%(X100), DQS PI = 56
7031 19:53:02.296730 [0] AVG Duty = 5078%(X100)
7032 19:53:02.296795
7033 19:53:02.299755 ==DQ 1 ==
7034 19:53:02.303197 Final DQ duty delay cell = -4
7035 19:53:02.306333 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7036 19:53:02.309987 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7037 19:53:02.310070 [-4] AVG Duty = 4969%(X100)
7038 19:53:02.313069
7039 19:53:02.316562 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7040 19:53:02.316644
7041 19:53:02.319570 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7042 19:53:02.323080 [DutyScan_Calibration_Flow] ====Done====
7043 19:53:02.323162 ==
7044 19:53:02.326216 Dram Type= 6, Freq= 0, CH_1, rank 0
7045 19:53:02.329625 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7046 19:53:02.329707 ==
7047 19:53:02.332816 [Duty_Offset_Calibration]
7048 19:53:02.332897 B0:0 B1:4 CA:-5
7049 19:53:02.332962
7050 19:53:02.336086 [DutyScan_Calibration_Flow] k_type=0
7051 19:53:02.347318
7052 19:53:02.347398 ==CLK 0==
7053 19:53:02.350332 Final CLK duty delay cell = 0
7054 19:53:02.353528 [0] MAX Duty = 5156%(X100), DQS PI = 22
7055 19:53:02.356941 [0] MIN Duty = 4906%(X100), DQS PI = 50
7056 19:53:02.357022 [0] AVG Duty = 5031%(X100)
7057 19:53:02.360035
7058 19:53:02.363475 CH1 CLK Duty spec in!! Max-Min= 250%
7059 19:53:02.367165 [DutyScan_Calibration_Flow] ====Done====
7060 19:53:02.367246
7061 19:53:02.370215 [DutyScan_Calibration_Flow] k_type=1
7062 19:53:02.385848
7063 19:53:02.385928 ==DQS 0 ==
7064 19:53:02.389151 Final DQS duty delay cell = 0
7065 19:53:02.392571 [0] MAX Duty = 5156%(X100), DQS PI = 18
7066 19:53:02.395791 [0] MIN Duty = 4907%(X100), DQS PI = 42
7067 19:53:02.399071 [0] AVG Duty = 5031%(X100)
7068 19:53:02.399152
7069 19:53:02.399217 ==DQS 1 ==
7070 19:53:02.402419 Final DQS duty delay cell = -4
7071 19:53:02.406063 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7072 19:53:02.408949 [-4] MIN Duty = 4844%(X100), DQS PI = 42
7073 19:53:02.412411 [-4] AVG Duty = 4922%(X100)
7074 19:53:02.412492
7075 19:53:02.415792 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7076 19:53:02.415873
7077 19:53:02.418969 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7078 19:53:02.422505 [DutyScan_Calibration_Flow] ====Done====
7079 19:53:02.422586
7080 19:53:02.425808 [DutyScan_Calibration_Flow] k_type=3
7081 19:53:02.441619
7082 19:53:02.441700 ==DQM 0 ==
7083 19:53:02.444788 Final DQM duty delay cell = -4
7084 19:53:02.448413 [-4] MAX Duty = 5062%(X100), DQS PI = 32
7085 19:53:02.451769 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7086 19:53:02.454682 [-4] AVG Duty = 4937%(X100)
7087 19:53:02.454789
7088 19:53:02.454857 ==DQM 1 ==
7089 19:53:02.458099 Final DQM duty delay cell = -4
7090 19:53:02.461782 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7091 19:53:02.464629 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7092 19:53:02.468078 [-4] AVG Duty = 5000%(X100)
7093 19:53:02.468208
7094 19:53:02.471418 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7095 19:53:02.471500
7096 19:53:02.474583 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7097 19:53:02.478410 [DutyScan_Calibration_Flow] ====Done====
7098 19:53:02.478491
7099 19:53:02.481375 [DutyScan_Calibration_Flow] k_type=2
7100 19:53:02.499295
7101 19:53:02.499386 ==DQ 0 ==
7102 19:53:02.502421 Final DQ duty delay cell = 0
7103 19:53:02.505723 [0] MAX Duty = 5093%(X100), DQS PI = 20
7104 19:53:02.509166 [0] MIN Duty = 4938%(X100), DQS PI = 48
7105 19:53:02.509246 [0] AVG Duty = 5015%(X100)
7106 19:53:02.512861
7107 19:53:02.512942 ==DQ 1 ==
7108 19:53:02.516111 Final DQ duty delay cell = 0
7109 19:53:02.519108 [0] MAX Duty = 5031%(X100), DQS PI = 4
7110 19:53:02.522360 [0] MIN Duty = 4876%(X100), DQS PI = 30
7111 19:53:02.522441 [0] AVG Duty = 4953%(X100)
7112 19:53:02.522505
7113 19:53:02.526230 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7114 19:53:02.529235
7115 19:53:02.532665 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7116 19:53:02.535743 [DutyScan_Calibration_Flow] ====Done====
7117 19:53:02.538963 nWR fixed to 30
7118 19:53:02.539054 [ModeRegInit_LP4] CH0 RK0
7119 19:53:02.542179 [ModeRegInit_LP4] CH0 RK1
7120 19:53:02.545558 [ModeRegInit_LP4] CH1 RK0
7121 19:53:02.548749 [ModeRegInit_LP4] CH1 RK1
7122 19:53:02.548830 match AC timing 4
7123 19:53:02.552109 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7124 19:53:02.558926 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7125 19:53:02.562399 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7126 19:53:02.568666 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7127 19:53:02.572132 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7128 19:53:02.572264 [MiockJmeterHQA]
7129 19:53:02.572329
7130 19:53:02.575519 [DramcMiockJmeter] u1RxGatingPI = 0
7131 19:53:02.578759 0 : 4255, 4027
7132 19:53:02.578842 4 : 4252, 4027
7133 19:53:02.581949 8 : 4252, 4027
7134 19:53:02.582031 12 : 4252, 4027
7135 19:53:02.582097 16 : 4252, 4026
7136 19:53:02.585520 20 : 4363, 4137
7137 19:53:02.585601 24 : 4363, 4138
7138 19:53:02.588580 28 : 4253, 4027
7139 19:53:02.588689 32 : 4252, 4027
7140 19:53:02.591987 36 : 4252, 4027
7141 19:53:02.592101 40 : 4253, 4027
7142 19:53:02.592234 44 : 4255, 4029
7143 19:53:02.595360 48 : 4363, 4138
7144 19:53:02.595441 52 : 4250, 4027
7145 19:53:02.598673 56 : 4250, 4027
7146 19:53:02.598755 60 : 4250, 4027
7147 19:53:02.602112 64 : 4253, 4029
7148 19:53:02.602194 68 : 4250, 4027
7149 19:53:02.605552 72 : 4361, 4137
7150 19:53:02.605634 76 : 4361, 4137
7151 19:53:02.605699 80 : 4250, 4027
7152 19:53:02.608570 84 : 4253, 4029
7153 19:53:02.608652 88 : 4250, 4027
7154 19:53:02.612004 92 : 4250, 4027
7155 19:53:02.612086 96 : 4253, 4029
7156 19:53:02.615356 100 : 4360, 2535
7157 19:53:02.615438 104 : 4250, 0
7158 19:53:02.615504 108 : 4250, 0
7159 19:53:02.618690 112 : 4253, 0
7160 19:53:02.618772 116 : 4361, 0
7161 19:53:02.622273 120 : 4249, 0
7162 19:53:02.622355 124 : 4361, 0
7163 19:53:02.622422 128 : 4250, 0
7164 19:53:02.625145 132 : 4250, 0
7165 19:53:02.625228 136 : 4250, 0
7166 19:53:02.628926 140 : 4250, 0
7167 19:53:02.629008 144 : 4250, 0
7168 19:53:02.629074 148 : 4360, 0
7169 19:53:02.631816 152 : 4250, 0
7170 19:53:02.631898 156 : 4250, 0
7171 19:53:02.635428 160 : 4250, 0
7172 19:53:02.635510 164 : 4253, 0
7173 19:53:02.635576 168 : 4361, 0
7174 19:53:02.638530 172 : 4360, 0
7175 19:53:02.638612 176 : 4363, 0
7176 19:53:02.638678 180 : 4250, 0
7177 19:53:02.642145 184 : 4360, 0
7178 19:53:02.642228 188 : 4250, 0
7179 19:53:02.645245 192 : 4250, 0
7180 19:53:02.645327 196 : 4250, 0
7181 19:53:02.645393 200 : 4361, 0
7182 19:53:02.648514 204 : 4361, 0
7183 19:53:02.648596 208 : 4250, 0
7184 19:53:02.652195 212 : 4250, 0
7185 19:53:02.652277 216 : 4252, 0
7186 19:53:02.652343 220 : 4250, 481
7187 19:53:02.655501 224 : 4361, 4084
7188 19:53:02.655583 228 : 4253, 4029
7189 19:53:02.658507 232 : 4250, 4026
7190 19:53:02.658589 236 : 4250, 4027
7191 19:53:02.661974 240 : 4252, 4029
7192 19:53:02.662057 244 : 4250, 4027
7193 19:53:02.664923 248 : 4250, 4027
7194 19:53:02.665005 252 : 4361, 4137
7195 19:53:02.668615 256 : 4250, 4026
7196 19:53:02.668698 260 : 4250, 4027
7197 19:53:02.671811 264 : 4360, 4137
7198 19:53:02.671894 268 : 4250, 4027
7199 19:53:02.671959 272 : 4252, 4026
7200 19:53:02.675304 276 : 4363, 4139
7201 19:53:02.675386 280 : 4250, 4027
7202 19:53:02.678275 284 : 4250, 4027
7203 19:53:02.678357 288 : 4250, 4027
7204 19:53:02.681595 292 : 4252, 4029
7205 19:53:02.681677 296 : 4250, 4027
7206 19:53:02.684886 300 : 4250, 4027
7207 19:53:02.684968 304 : 4361, 4137
7208 19:53:02.688356 308 : 4250, 4026
7209 19:53:02.688438 312 : 4250, 4027
7210 19:53:02.691476 316 : 4360, 4138
7211 19:53:02.691558 320 : 4250, 4027
7212 19:53:02.695118 324 : 4250, 4027
7213 19:53:02.695201 328 : 4250, 4027
7214 19:53:02.698256 332 : 4250, 4027
7215 19:53:02.698338 336 : 4250, 3952
7216 19:53:02.698404 340 : 4250, 2081
7217 19:53:02.698466
7218 19:53:02.701616 MIOCK jitter meter ch=0
7219 19:53:02.701697
7220 19:53:02.704912 1T = (340-104) = 236 dly cells
7221 19:53:02.711359 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7222 19:53:02.711441 ==
7223 19:53:02.714693 Dram Type= 6, Freq= 0, CH_0, rank 0
7224 19:53:02.718232 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7225 19:53:02.718313 ==
7226 19:53:02.724715 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7227 19:53:02.727966 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7228 19:53:02.731287 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7229 19:53:02.737750 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7230 19:53:02.746738 [CA 0] Center 42 (12~73) winsize 62
7231 19:53:02.749784 [CA 1] Center 42 (12~73) winsize 62
7232 19:53:02.752951 [CA 2] Center 39 (9~69) winsize 61
7233 19:53:02.756229 [CA 3] Center 38 (9~68) winsize 60
7234 19:53:02.759762 [CA 4] Center 36 (6~67) winsize 62
7235 19:53:02.763017 [CA 5] Center 36 (6~66) winsize 61
7236 19:53:02.763100
7237 19:53:02.766339 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7238 19:53:02.766420
7239 19:53:02.769904 [CATrainingPosCal] consider 1 rank data
7240 19:53:02.772952 u2DelayCellTimex100 = 275/100 ps
7241 19:53:02.776340 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7242 19:53:02.783161 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7243 19:53:02.786217 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7244 19:53:02.789563 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7245 19:53:02.793297 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
7246 19:53:02.796134 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7247 19:53:02.796237
7248 19:53:02.799634 CA PerBit enable=1, Macro0, CA PI delay=36
7249 19:53:02.799714
7250 19:53:02.802898 [CBTSetCACLKResult] CA Dly = 36
7251 19:53:02.806325 CS Dly: 10 (0~41)
7252 19:53:02.809484 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7253 19:53:02.812677 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7254 19:53:02.812757 ==
7255 19:53:02.816392 Dram Type= 6, Freq= 0, CH_0, rank 1
7256 19:53:02.819470 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7257 19:53:02.822743 ==
7258 19:53:02.826133 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7259 19:53:02.829359 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7260 19:53:02.836129 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7261 19:53:02.842605 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7262 19:53:02.849176 [CA 0] Center 42 (12~73) winsize 62
7263 19:53:02.852595 [CA 1] Center 41 (11~72) winsize 62
7264 19:53:02.855975 [CA 2] Center 38 (8~68) winsize 61
7265 19:53:02.858989 [CA 3] Center 37 (7~67) winsize 61
7266 19:53:02.862430 [CA 4] Center 35 (5~65) winsize 61
7267 19:53:02.865974 [CA 5] Center 35 (5~66) winsize 62
7268 19:53:02.866055
7269 19:53:02.869137 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7270 19:53:02.869218
7271 19:53:02.872438 [CATrainingPosCal] consider 2 rank data
7272 19:53:02.875628 u2DelayCellTimex100 = 275/100 ps
7273 19:53:02.879480 CA0 delay=42 (12~73),Diff = 7 PI (24 cell)
7274 19:53:02.885508 CA1 delay=42 (12~72),Diff = 7 PI (24 cell)
7275 19:53:02.888946 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7276 19:53:02.892348 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7277 19:53:02.895562 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7278 19:53:02.898891 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
7279 19:53:02.898961
7280 19:53:02.902267 CA PerBit enable=1, Macro0, CA PI delay=35
7281 19:53:02.902341
7282 19:53:02.905538 [CBTSetCACLKResult] CA Dly = 35
7283 19:53:02.909286 CS Dly: 11 (0~43)
7284 19:53:02.912127 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7285 19:53:02.915553 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7286 19:53:02.915633
7287 19:53:02.918740 ----->DramcWriteLeveling(PI) begin...
7288 19:53:02.918809 ==
7289 19:53:02.921902 Dram Type= 6, Freq= 0, CH_0, rank 0
7290 19:53:02.928513 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7291 19:53:02.928595 ==
7292 19:53:02.932068 Write leveling (Byte 0): 30 => 30
7293 19:53:02.932149 Write leveling (Byte 1): 25 => 25
7294 19:53:02.935435 DramcWriteLeveling(PI) end<-----
7295 19:53:02.935516
7296 19:53:02.939030 ==
7297 19:53:02.942304 Dram Type= 6, Freq= 0, CH_0, rank 0
7298 19:53:02.945414 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7299 19:53:02.945495 ==
7300 19:53:02.948737 [Gating] SW mode calibration
7301 19:53:02.955264 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7302 19:53:02.958413 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7303 19:53:02.965017 0 12 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7304 19:53:02.968709 0 12 4 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
7305 19:53:02.971884 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7306 19:53:02.978305 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7307 19:53:02.981508 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7308 19:53:02.984961 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7309 19:53:02.991690 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7310 19:53:02.994861 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7311 19:53:02.998237 0 13 0 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
7312 19:53:03.004680 0 13 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
7313 19:53:03.008165 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7314 19:53:03.011395 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7315 19:53:03.018243 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7316 19:53:03.021683 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7317 19:53:03.024672 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7318 19:53:03.031345 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7319 19:53:03.034670 0 14 0 | B1->B0 | 2424 3b3b | 1 0 | (0 0) (1 1)
7320 19:53:03.038100 0 14 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7321 19:53:03.044609 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7322 19:53:03.048017 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7323 19:53:03.051611 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7324 19:53:03.054653 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7325 19:53:03.061125 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7326 19:53:03.064437 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7327 19:53:03.068210 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7328 19:53:03.074312 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7329 19:53:03.077842 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7330 19:53:03.081064 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7331 19:53:03.087586 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7332 19:53:03.091106 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7333 19:53:03.094221 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7334 19:53:03.101287 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7335 19:53:03.104122 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7336 19:53:03.107414 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7337 19:53:03.114056 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7338 19:53:03.117266 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7339 19:53:03.120778 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7340 19:53:03.127431 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 19:53:03.130756 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7342 19:53:03.134346 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7343 19:53:03.140487 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7344 19:53:03.143872 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7345 19:53:03.147223 Total UI for P1: 0, mck2ui 16
7346 19:53:03.150473 best dqsien dly found for B0: ( 1, 0, 28)
7347 19:53:03.153746 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7348 19:53:03.160797 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7349 19:53:03.163667 Total UI for P1: 0, mck2ui 16
7350 19:53:03.166880 best dqsien dly found for B1: ( 1, 1, 6)
7351 19:53:03.170507 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7352 19:53:03.173789 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7353 19:53:03.173861
7354 19:53:03.176998 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7355 19:53:03.180324 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7356 19:53:03.183600 [Gating] SW calibration Done
7357 19:53:03.183668 ==
7358 19:53:03.186857 Dram Type= 6, Freq= 0, CH_0, rank 0
7359 19:53:03.190317 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7360 19:53:03.190392 ==
7361 19:53:03.193482 RX Vref Scan: 0
7362 19:53:03.193562
7363 19:53:03.193628 RX Vref 0 -> 0, step: 1
7364 19:53:03.193687
7365 19:53:03.196794 RX Delay 0 -> 252, step: 8
7366 19:53:03.200210 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7367 19:53:03.206670 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7368 19:53:03.210434 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7369 19:53:03.213329 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7370 19:53:03.216618 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7371 19:53:03.219812 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7372 19:53:03.226392 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7373 19:53:03.229705 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7374 19:53:03.232961 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7375 19:53:03.236684 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7376 19:53:03.239745 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7377 19:53:03.246237 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7378 19:53:03.249533 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7379 19:53:03.252875 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7380 19:53:03.256760 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7381 19:53:03.262672 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7382 19:53:03.262753 ==
7383 19:53:03.266309 Dram Type= 6, Freq= 0, CH_0, rank 0
7384 19:53:03.269470 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7385 19:53:03.269553 ==
7386 19:53:03.269618 DQS Delay:
7387 19:53:03.272911 DQS0 = 0, DQS1 = 0
7388 19:53:03.272987 DQM Delay:
7389 19:53:03.276151 DQM0 = 130, DQM1 = 124
7390 19:53:03.276264 DQ Delay:
7391 19:53:03.279468 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7392 19:53:03.283009 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7393 19:53:03.286130 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7394 19:53:03.289405 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7395 19:53:03.289517
7396 19:53:03.292548
7397 19:53:03.292629 ==
7398 19:53:03.295756 Dram Type= 6, Freq= 0, CH_0, rank 0
7399 19:53:03.299228 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7400 19:53:03.299310 ==
7401 19:53:03.299375
7402 19:53:03.299434
7403 19:53:03.302584 TX Vref Scan disable
7404 19:53:03.302665 == TX Byte 0 ==
7405 19:53:03.308932 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7406 19:53:03.312349 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7407 19:53:03.312460 == TX Byte 1 ==
7408 19:53:03.318996 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7409 19:53:03.322390 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7410 19:53:03.322466 ==
7411 19:53:03.325874 Dram Type= 6, Freq= 0, CH_0, rank 0
7412 19:53:03.329280 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7413 19:53:03.329349 ==
7414 19:53:03.342777
7415 19:53:03.346656 TX Vref early break, caculate TX vref
7416 19:53:03.349280 TX Vref=16, minBit 1, minWin=21, winSum=362
7417 19:53:03.352552 TX Vref=18, minBit 10, minWin=22, winSum=376
7418 19:53:03.356141 TX Vref=20, minBit 7, minWin=23, winSum=386
7419 19:53:03.359261 TX Vref=22, minBit 7, minWin=23, winSum=390
7420 19:53:03.362801 TX Vref=24, minBit 1, minWin=24, winSum=402
7421 19:53:03.369491 TX Vref=26, minBit 10, minWin=24, winSum=404
7422 19:53:03.372663 TX Vref=28, minBit 3, minWin=24, winSum=409
7423 19:53:03.376229 TX Vref=30, minBit 0, minWin=24, winSum=400
7424 19:53:03.379140 TX Vref=32, minBit 1, minWin=23, winSum=392
7425 19:53:03.382840 TX Vref=34, minBit 1, minWin=23, winSum=387
7426 19:53:03.389048 [TxChooseVref] Worse bit 3, Min win 24, Win sum 409, Final Vref 28
7427 19:53:03.389124
7428 19:53:03.392556 Final TX Range 0 Vref 28
7429 19:53:03.392633
7430 19:53:03.392704 ==
7431 19:53:03.396054 Dram Type= 6, Freq= 0, CH_0, rank 0
7432 19:53:03.399115 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7433 19:53:03.399188 ==
7434 19:53:03.399249
7435 19:53:03.399307
7436 19:53:03.402341 TX Vref Scan disable
7437 19:53:03.409454 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7438 19:53:03.409530 == TX Byte 0 ==
7439 19:53:03.412242 u2DelayCellOfst[0]=10 cells (3 PI)
7440 19:53:03.415752 u2DelayCellOfst[1]=17 cells (5 PI)
7441 19:53:03.419190 u2DelayCellOfst[2]=14 cells (4 PI)
7442 19:53:03.422137 u2DelayCellOfst[3]=10 cells (3 PI)
7443 19:53:03.425703 u2DelayCellOfst[4]=7 cells (2 PI)
7444 19:53:03.428996 u2DelayCellOfst[5]=0 cells (0 PI)
7445 19:53:03.432180 u2DelayCellOfst[6]=17 cells (5 PI)
7446 19:53:03.435709 u2DelayCellOfst[7]=17 cells (5 PI)
7447 19:53:03.438815 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7448 19:53:03.442315 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7449 19:53:03.445617 == TX Byte 1 ==
7450 19:53:03.448986 u2DelayCellOfst[8]=3 cells (1 PI)
7451 19:53:03.449061 u2DelayCellOfst[9]=0 cells (0 PI)
7452 19:53:03.452282 u2DelayCellOfst[10]=10 cells (3 PI)
7453 19:53:03.455603 u2DelayCellOfst[11]=3 cells (1 PI)
7454 19:53:03.458816 u2DelayCellOfst[12]=14 cells (4 PI)
7455 19:53:03.462089 u2DelayCellOfst[13]=14 cells (4 PI)
7456 19:53:03.465536 u2DelayCellOfst[14]=17 cells (5 PI)
7457 19:53:03.468843 u2DelayCellOfst[15]=14 cells (4 PI)
7458 19:53:03.472042 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7459 19:53:03.478758 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7460 19:53:03.478846 DramC Write-DBI on
7461 19:53:03.478911 ==
7462 19:53:03.481903 Dram Type= 6, Freq= 0, CH_0, rank 0
7463 19:53:03.488407 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7464 19:53:03.488488 ==
7465 19:53:03.488553
7466 19:53:03.488613
7467 19:53:03.488670 TX Vref Scan disable
7468 19:53:03.492510 == TX Byte 0 ==
7469 19:53:03.495773 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7470 19:53:03.499214 == TX Byte 1 ==
7471 19:53:03.502440 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7472 19:53:03.505616 DramC Write-DBI off
7473 19:53:03.505697
7474 19:53:03.505761 [DATLAT]
7475 19:53:03.505821 Freq=1600, CH0 RK0
7476 19:53:03.505879
7477 19:53:03.508981 DATLAT Default: 0xf
7478 19:53:03.509061 0, 0xFFFF, sum = 0
7479 19:53:03.512147 1, 0xFFFF, sum = 0
7480 19:53:03.515625 2, 0xFFFF, sum = 0
7481 19:53:03.515707 3, 0xFFFF, sum = 0
7482 19:53:03.518844 4, 0xFFFF, sum = 0
7483 19:53:03.518926 5, 0xFFFF, sum = 0
7484 19:53:03.522251 6, 0xFFFF, sum = 0
7485 19:53:03.522334 7, 0xFFFF, sum = 0
7486 19:53:03.525502 8, 0xFFFF, sum = 0
7487 19:53:03.525584 9, 0xFFFF, sum = 0
7488 19:53:03.529057 10, 0xFFFF, sum = 0
7489 19:53:03.529140 11, 0xFFFF, sum = 0
7490 19:53:03.532220 12, 0xFFF, sum = 0
7491 19:53:03.532303 13, 0x0, sum = 1
7492 19:53:03.535636 14, 0x0, sum = 2
7493 19:53:03.535719 15, 0x0, sum = 3
7494 19:53:03.538750 16, 0x0, sum = 4
7495 19:53:03.538832 best_step = 14
7496 19:53:03.538897
7497 19:53:03.538957 ==
7498 19:53:03.542347 Dram Type= 6, Freq= 0, CH_0, rank 0
7499 19:53:03.545495 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7500 19:53:03.548780 ==
7501 19:53:03.548861 RX Vref Scan: 1
7502 19:53:03.548927
7503 19:53:03.551982 Set Vref Range= 24 -> 127
7504 19:53:03.552063
7505 19:53:03.552127 RX Vref 24 -> 127, step: 1
7506 19:53:03.555786
7507 19:53:03.555867 RX Delay 11 -> 252, step: 4
7508 19:53:03.555932
7509 19:53:03.558558 Set Vref, RX VrefLevel [Byte0]: 24
7510 19:53:03.562169 [Byte1]: 24
7511 19:53:03.565732
7512 19:53:03.565812 Set Vref, RX VrefLevel [Byte0]: 25
7513 19:53:03.569111 [Byte1]: 25
7514 19:53:03.573335
7515 19:53:03.573415 Set Vref, RX VrefLevel [Byte0]: 26
7516 19:53:03.576583 [Byte1]: 26
7517 19:53:03.580916
7518 19:53:03.580997 Set Vref, RX VrefLevel [Byte0]: 27
7519 19:53:03.584065 [Byte1]: 27
7520 19:53:03.588515
7521 19:53:03.588595 Set Vref, RX VrefLevel [Byte0]: 28
7522 19:53:03.591659 [Byte1]: 28
7523 19:53:03.596139
7524 19:53:03.596271 Set Vref, RX VrefLevel [Byte0]: 29
7525 19:53:03.599399 [Byte1]: 29
7526 19:53:03.603686
7527 19:53:03.603767 Set Vref, RX VrefLevel [Byte0]: 30
7528 19:53:03.607037 [Byte1]: 30
7529 19:53:03.611160
7530 19:53:03.611241 Set Vref, RX VrefLevel [Byte0]: 31
7531 19:53:03.614629 [Byte1]: 31
7532 19:53:03.618951
7533 19:53:03.619032 Set Vref, RX VrefLevel [Byte0]: 32
7534 19:53:03.622159 [Byte1]: 32
7535 19:53:03.626651
7536 19:53:03.626731 Set Vref, RX VrefLevel [Byte0]: 33
7537 19:53:03.629794 [Byte1]: 33
7538 19:53:03.634217
7539 19:53:03.634298 Set Vref, RX VrefLevel [Byte0]: 34
7540 19:53:03.637333 [Byte1]: 34
7541 19:53:03.641861
7542 19:53:03.641942 Set Vref, RX VrefLevel [Byte0]: 35
7543 19:53:03.645042 [Byte1]: 35
7544 19:53:03.649188
7545 19:53:03.649268 Set Vref, RX VrefLevel [Byte0]: 36
7546 19:53:03.652560 [Byte1]: 36
7547 19:53:03.656977
7548 19:53:03.657058 Set Vref, RX VrefLevel [Byte0]: 37
7549 19:53:03.660344 [Byte1]: 37
7550 19:53:03.664720
7551 19:53:03.664801 Set Vref, RX VrefLevel [Byte0]: 38
7552 19:53:03.667794 [Byte1]: 38
7553 19:53:03.672041
7554 19:53:03.672148 Set Vref, RX VrefLevel [Byte0]: 39
7555 19:53:03.675430 [Byte1]: 39
7556 19:53:03.679788
7557 19:53:03.679868 Set Vref, RX VrefLevel [Byte0]: 40
7558 19:53:03.683284 [Byte1]: 40
7559 19:53:03.687376
7560 19:53:03.687456 Set Vref, RX VrefLevel [Byte0]: 41
7561 19:53:03.690678 [Byte1]: 41
7562 19:53:03.694968
7563 19:53:03.695048 Set Vref, RX VrefLevel [Byte0]: 42
7564 19:53:03.698260 [Byte1]: 42
7565 19:53:03.702728
7566 19:53:03.702808 Set Vref, RX VrefLevel [Byte0]: 43
7567 19:53:03.705997 [Byte1]: 43
7568 19:53:03.710178
7569 19:53:03.710259 Set Vref, RX VrefLevel [Byte0]: 44
7570 19:53:03.713462 [Byte1]: 44
7571 19:53:03.718191
7572 19:53:03.718271 Set Vref, RX VrefLevel [Byte0]: 45
7573 19:53:03.721112 [Byte1]: 45
7574 19:53:03.725615
7575 19:53:03.725696 Set Vref, RX VrefLevel [Byte0]: 46
7576 19:53:03.729008 [Byte1]: 46
7577 19:53:03.733081
7578 19:53:03.733161 Set Vref, RX VrefLevel [Byte0]: 47
7579 19:53:03.736477 [Byte1]: 47
7580 19:53:03.740761
7581 19:53:03.740841 Set Vref, RX VrefLevel [Byte0]: 48
7582 19:53:03.744066 [Byte1]: 48
7583 19:53:03.748442
7584 19:53:03.748522 Set Vref, RX VrefLevel [Byte0]: 49
7585 19:53:03.751934 [Byte1]: 49
7586 19:53:03.755906
7587 19:53:03.755987 Set Vref, RX VrefLevel [Byte0]: 50
7588 19:53:03.759431 [Byte1]: 50
7589 19:53:03.763616
7590 19:53:03.763696 Set Vref, RX VrefLevel [Byte0]: 51
7591 19:53:03.767149 [Byte1]: 51
7592 19:53:03.771337
7593 19:53:03.771417 Set Vref, RX VrefLevel [Byte0]: 52
7594 19:53:03.774317 [Byte1]: 52
7595 19:53:03.778800
7596 19:53:03.778880 Set Vref, RX VrefLevel [Byte0]: 53
7597 19:53:03.782096 [Byte1]: 53
7598 19:53:03.786261
7599 19:53:03.786341 Set Vref, RX VrefLevel [Byte0]: 54
7600 19:53:03.790078 [Byte1]: 54
7601 19:53:03.794010
7602 19:53:03.794091 Set Vref, RX VrefLevel [Byte0]: 55
7603 19:53:03.797335 [Byte1]: 55
7604 19:53:03.801545
7605 19:53:03.801625 Set Vref, RX VrefLevel [Byte0]: 56
7606 19:53:03.804974 [Byte1]: 56
7607 19:53:03.809149
7608 19:53:03.809230 Set Vref, RX VrefLevel [Byte0]: 57
7609 19:53:03.812595 [Byte1]: 57
7610 19:53:03.816705
7611 19:53:03.816785 Set Vref, RX VrefLevel [Byte0]: 58
7612 19:53:03.820128 [Byte1]: 58
7613 19:53:03.824422
7614 19:53:03.824502 Set Vref, RX VrefLevel [Byte0]: 59
7615 19:53:03.827671 [Byte1]: 59
7616 19:53:03.832028
7617 19:53:03.832134 Set Vref, RX VrefLevel [Byte0]: 60
7618 19:53:03.835402 [Byte1]: 60
7619 19:53:03.839638
7620 19:53:03.839718 Set Vref, RX VrefLevel [Byte0]: 61
7621 19:53:03.843509 [Byte1]: 61
7622 19:53:03.847179
7623 19:53:03.847259 Set Vref, RX VrefLevel [Byte0]: 62
7624 19:53:03.850782 [Byte1]: 62
7625 19:53:03.855391
7626 19:53:03.855471 Set Vref, RX VrefLevel [Byte0]: 63
7627 19:53:03.858375 [Byte1]: 63
7628 19:53:03.862607
7629 19:53:03.862689 Set Vref, RX VrefLevel [Byte0]: 64
7630 19:53:03.865854 [Byte1]: 64
7631 19:53:03.870219
7632 19:53:03.870300 Set Vref, RX VrefLevel [Byte0]: 65
7633 19:53:03.873404 [Byte1]: 65
7634 19:53:03.878246
7635 19:53:03.878327 Set Vref, RX VrefLevel [Byte0]: 66
7636 19:53:03.881094 [Byte1]: 66
7637 19:53:03.885494
7638 19:53:03.885574 Set Vref, RX VrefLevel [Byte0]: 67
7639 19:53:03.888492 [Byte1]: 67
7640 19:53:03.893085
7641 19:53:03.893165 Set Vref, RX VrefLevel [Byte0]: 68
7642 19:53:03.896193 [Byte1]: 68
7643 19:53:03.900648
7644 19:53:03.900728 Set Vref, RX VrefLevel [Byte0]: 69
7645 19:53:03.903904 [Byte1]: 69
7646 19:53:03.908479
7647 19:53:03.908560 Set Vref, RX VrefLevel [Byte0]: 70
7648 19:53:03.911533 [Byte1]: 70
7649 19:53:03.915926
7650 19:53:03.916006 Set Vref, RX VrefLevel [Byte0]: 71
7651 19:53:03.919372 [Byte1]: 71
7652 19:53:03.923400
7653 19:53:03.923481 Set Vref, RX VrefLevel [Byte0]: 72
7654 19:53:03.926663 [Byte1]: 72
7655 19:53:03.930992
7656 19:53:03.931072 Final RX Vref Byte 0 = 54 to rank0
7657 19:53:03.934500 Final RX Vref Byte 1 = 55 to rank0
7658 19:53:03.937723 Final RX Vref Byte 0 = 54 to rank1
7659 19:53:03.940967 Final RX Vref Byte 1 = 55 to rank1==
7660 19:53:03.944131 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 19:53:03.950677 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7662 19:53:03.950759 ==
7663 19:53:03.950825 DQS Delay:
7664 19:53:03.954331 DQS0 = 0, DQS1 = 0
7665 19:53:03.954411 DQM Delay:
7666 19:53:03.954476 DQM0 = 126, DQM1 = 121
7667 19:53:03.957378 DQ Delay:
7668 19:53:03.960749 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7669 19:53:03.964307 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7670 19:53:03.967467 DQ8 =112, DQ9 =104, DQ10 =122, DQ11 =112
7671 19:53:03.970459 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7672 19:53:03.970540
7673 19:53:03.970605
7674 19:53:03.970665
7675 19:53:03.973723 [DramC_TX_OE_Calibration] TA2
7676 19:53:03.977204 Original DQ_B0 (3 6) =30, OEN = 27
7677 19:53:03.980469 Original DQ_B1 (3 6) =30, OEN = 27
7678 19:53:03.983780 24, 0x0, End_B0=24 End_B1=24
7679 19:53:03.983862 25, 0x0, End_B0=25 End_B1=25
7680 19:53:03.986958 26, 0x0, End_B0=26 End_B1=26
7681 19:53:03.990399 27, 0x0, End_B0=27 End_B1=27
7682 19:53:03.993791 28, 0x0, End_B0=28 End_B1=28
7683 19:53:03.997191 29, 0x0, End_B0=29 End_B1=29
7684 19:53:03.997301 30, 0x0, End_B0=30 End_B1=30
7685 19:53:04.000324 31, 0x4141, End_B0=30 End_B1=30
7686 19:53:04.004087 Byte0 end_step=30 best_step=27
7687 19:53:04.006941 Byte1 end_step=30 best_step=27
7688 19:53:04.010417 Byte0 TX OE(2T, 0.5T) = (3, 3)
7689 19:53:04.013594 Byte1 TX OE(2T, 0.5T) = (3, 3)
7690 19:53:04.013675
7691 19:53:04.013739
7692 19:53:04.020500 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7693 19:53:04.023653 CH0 RK0: MR19=303, MR18=1919
7694 19:53:04.029982 CH0_RK0: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
7695 19:53:04.030063
7696 19:53:04.033284 ----->DramcWriteLeveling(PI) begin...
7697 19:53:04.033366 ==
7698 19:53:04.036891 Dram Type= 6, Freq= 0, CH_0, rank 1
7699 19:53:04.039939 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7700 19:53:04.040020 ==
7701 19:53:04.043520 Write leveling (Byte 0): 29 => 29
7702 19:53:04.046485 Write leveling (Byte 1): 27 => 27
7703 19:53:04.049928 DramcWriteLeveling(PI) end<-----
7704 19:53:04.050009
7705 19:53:04.050074 ==
7706 19:53:04.053660 Dram Type= 6, Freq= 0, CH_0, rank 1
7707 19:53:04.056661 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7708 19:53:04.056742 ==
7709 19:53:04.059753 [Gating] SW mode calibration
7710 19:53:04.066857 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7711 19:53:04.073450 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7712 19:53:04.076558 0 12 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
7713 19:53:04.083304 0 12 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7714 19:53:04.086791 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7715 19:53:04.090130 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7716 19:53:04.096530 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7717 19:53:04.100019 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7718 19:53:04.103100 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7719 19:53:04.109931 0 12 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7720 19:53:04.113460 0 13 0 | B1->B0 | 3434 2929 | 1 1 | (1 0) (1 0)
7721 19:53:04.116481 0 13 4 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7722 19:53:04.123163 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7723 19:53:04.126562 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7724 19:53:04.129950 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7725 19:53:04.133223 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7726 19:53:04.139700 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7727 19:53:04.143421 0 13 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7728 19:53:04.146626 0 14 0 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7729 19:53:04.153184 0 14 4 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
7730 19:53:04.156298 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7731 19:53:04.159636 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7732 19:53:04.166080 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7733 19:53:04.169533 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7734 19:53:04.172979 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7735 19:53:04.179551 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7736 19:53:04.182797 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7737 19:53:04.186120 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7738 19:53:04.192759 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7739 19:53:04.196150 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7740 19:53:04.199318 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7741 19:53:04.205917 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7742 19:53:04.209212 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7743 19:53:04.212846 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7744 19:53:04.219201 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7745 19:53:04.222673 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7746 19:53:04.225833 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 19:53:04.232432 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 19:53:04.235628 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 19:53:04.239298 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 19:53:04.245777 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7751 19:53:04.248892 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7752 19:53:04.252333 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7753 19:53:04.259017 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7754 19:53:04.259117 Total UI for P1: 0, mck2ui 16
7755 19:53:04.265553 best dqsien dly found for B0: ( 1, 0, 28)
7756 19:53:04.268987 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7757 19:53:04.272621 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7758 19:53:04.276004 Total UI for P1: 0, mck2ui 16
7759 19:53:04.278948 best dqsien dly found for B1: ( 1, 1, 6)
7760 19:53:04.282226 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7761 19:53:04.285639 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7762 19:53:04.285737
7763 19:53:04.289176 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7764 19:53:04.295419 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7765 19:53:04.295507 [Gating] SW calibration Done
7766 19:53:04.295573 ==
7767 19:53:04.298664 Dram Type= 6, Freq= 0, CH_0, rank 1
7768 19:53:04.305280 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7769 19:53:04.305361 ==
7770 19:53:04.305427 RX Vref Scan: 0
7771 19:53:04.305488
7772 19:53:04.308470 RX Vref 0 -> 0, step: 1
7773 19:53:04.308551
7774 19:53:04.312061 RX Delay 0 -> 252, step: 8
7775 19:53:04.315144 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7776 19:53:04.318710 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7777 19:53:04.322035 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7778 19:53:04.328463 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7779 19:53:04.331989 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7780 19:53:04.335438 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7781 19:53:04.338775 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7782 19:53:04.341976 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7783 19:53:04.348484 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7784 19:53:04.352039 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7785 19:53:04.355132 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7786 19:53:04.358313 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7787 19:53:04.361569 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7788 19:53:04.368383 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7789 19:53:04.371736 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7790 19:53:04.374840 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7791 19:53:04.374940 ==
7792 19:53:04.378270 Dram Type= 6, Freq= 0, CH_0, rank 1
7793 19:53:04.381653 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7794 19:53:04.381758 ==
7795 19:53:04.385059 DQS Delay:
7796 19:53:04.385160 DQS0 = 0, DQS1 = 0
7797 19:53:04.388301 DQM Delay:
7798 19:53:04.388399 DQM0 = 131, DQM1 = 124
7799 19:53:04.388491 DQ Delay:
7800 19:53:04.395228 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7801 19:53:04.398469 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7802 19:53:04.401771 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7803 19:53:04.404891 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7804 19:53:04.404988
7805 19:53:04.405069
7806 19:53:04.405131 ==
7807 19:53:04.408064 Dram Type= 6, Freq= 0, CH_0, rank 1
7808 19:53:04.411390 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7809 19:53:04.411487 ==
7810 19:53:04.411580
7811 19:53:04.411666
7812 19:53:04.414851 TX Vref Scan disable
7813 19:53:04.418303 == TX Byte 0 ==
7814 19:53:04.421572 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7815 19:53:04.424891 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7816 19:53:04.428057 == TX Byte 1 ==
7817 19:53:04.431153 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7818 19:53:04.434648 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7819 19:53:04.434749 ==
7820 19:53:04.437951 Dram Type= 6, Freq= 0, CH_0, rank 1
7821 19:53:04.444530 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7822 19:53:04.444630 ==
7823 19:53:04.456821
7824 19:53:04.460088 TX Vref early break, caculate TX vref
7825 19:53:04.463407 TX Vref=16, minBit 1, minWin=22, winSum=368
7826 19:53:04.466624 TX Vref=18, minBit 0, minWin=22, winSum=377
7827 19:53:04.470042 TX Vref=20, minBit 1, minWin=23, winSum=388
7828 19:53:04.473331 TX Vref=22, minBit 1, minWin=23, winSum=394
7829 19:53:04.476887 TX Vref=24, minBit 0, minWin=24, winSum=403
7830 19:53:04.483442 TX Vref=26, minBit 1, minWin=24, winSum=406
7831 19:53:04.486773 TX Vref=28, minBit 4, minWin=24, winSum=408
7832 19:53:04.490155 TX Vref=30, minBit 1, minWin=23, winSum=399
7833 19:53:04.493270 TX Vref=32, minBit 7, minWin=23, winSum=394
7834 19:53:04.496597 TX Vref=34, minBit 8, minWin=22, winSum=387
7835 19:53:04.499954 TX Vref=36, minBit 1, minWin=22, winSum=380
7836 19:53:04.506502 [TxChooseVref] Worse bit 4, Min win 24, Win sum 408, Final Vref 28
7837 19:53:04.506603
7838 19:53:04.510072 Final TX Range 0 Vref 28
7839 19:53:04.510170
7840 19:53:04.510258 ==
7841 19:53:04.513143 Dram Type= 6, Freq= 0, CH_0, rank 1
7842 19:53:04.516382 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7843 19:53:04.516468 ==
7844 19:53:04.516557
7845 19:53:04.519640
7846 19:53:04.519737 TX Vref Scan disable
7847 19:53:04.526564 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7848 19:53:04.526662 == TX Byte 0 ==
7849 19:53:04.530206 u2DelayCellOfst[0]=10 cells (3 PI)
7850 19:53:04.532976 u2DelayCellOfst[1]=17 cells (5 PI)
7851 19:53:04.536632 u2DelayCellOfst[2]=10 cells (3 PI)
7852 19:53:04.539522 u2DelayCellOfst[3]=14 cells (4 PI)
7853 19:53:04.543018 u2DelayCellOfst[4]=7 cells (2 PI)
7854 19:53:04.546697 u2DelayCellOfst[5]=0 cells (0 PI)
7855 19:53:04.549541 u2DelayCellOfst[6]=17 cells (5 PI)
7856 19:53:04.552958 u2DelayCellOfst[7]=17 cells (5 PI)
7857 19:53:04.556214 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7858 19:53:04.560032 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7859 19:53:04.563146 == TX Byte 1 ==
7860 19:53:04.566776 u2DelayCellOfst[8]=3 cells (1 PI)
7861 19:53:04.569420 u2DelayCellOfst[9]=0 cells (0 PI)
7862 19:53:04.573016 u2DelayCellOfst[10]=10 cells (3 PI)
7863 19:53:04.573118 u2DelayCellOfst[11]=3 cells (1 PI)
7864 19:53:04.576210 u2DelayCellOfst[12]=14 cells (4 PI)
7865 19:53:04.579538 u2DelayCellOfst[13]=14 cells (4 PI)
7866 19:53:04.582906 u2DelayCellOfst[14]=17 cells (5 PI)
7867 19:53:04.586298 u2DelayCellOfst[15]=14 cells (4 PI)
7868 19:53:04.592782 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7869 19:53:04.596380 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7870 19:53:04.596480 DramC Write-DBI on
7871 19:53:04.596548 ==
7872 19:53:04.599597 Dram Type= 6, Freq= 0, CH_0, rank 1
7873 19:53:04.606039 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7874 19:53:04.606143 ==
7875 19:53:04.606249
7876 19:53:04.606339
7877 19:53:04.606429 TX Vref Scan disable
7878 19:53:04.610127 == TX Byte 0 ==
7879 19:53:04.613590 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7880 19:53:04.616893 == TX Byte 1 ==
7881 19:53:04.620083 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7882 19:53:04.623649 DramC Write-DBI off
7883 19:53:04.623748
7884 19:53:04.623839 [DATLAT]
7885 19:53:04.623925 Freq=1600, CH0 RK1
7886 19:53:04.624014
7887 19:53:04.627124 DATLAT Default: 0xe
7888 19:53:04.627220 0, 0xFFFF, sum = 0
7889 19:53:04.630283 1, 0xFFFF, sum = 0
7890 19:53:04.633252 2, 0xFFFF, sum = 0
7891 19:53:04.633350 3, 0xFFFF, sum = 0
7892 19:53:04.636917 4, 0xFFFF, sum = 0
7893 19:53:04.637020 5, 0xFFFF, sum = 0
7894 19:53:04.640078 6, 0xFFFF, sum = 0
7895 19:53:04.640181 7, 0xFFFF, sum = 0
7896 19:53:04.643544 8, 0xFFFF, sum = 0
7897 19:53:04.643642 9, 0xFFFF, sum = 0
7898 19:53:04.646782 10, 0xFFFF, sum = 0
7899 19:53:04.646883 11, 0xFFFF, sum = 0
7900 19:53:04.650104 12, 0xCFFF, sum = 0
7901 19:53:04.650204 13, 0x0, sum = 1
7902 19:53:04.653260 14, 0x0, sum = 2
7903 19:53:04.653368 15, 0x0, sum = 3
7904 19:53:04.656698 16, 0x0, sum = 4
7905 19:53:04.656770 best_step = 14
7906 19:53:04.656834
7907 19:53:04.656894 ==
7908 19:53:04.659858 Dram Type= 6, Freq= 0, CH_0, rank 1
7909 19:53:04.663159 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7910 19:53:04.666512 ==
7911 19:53:04.666609 RX Vref Scan: 0
7912 19:53:04.666700
7913 19:53:04.669956 RX Vref 0 -> 0, step: 1
7914 19:53:04.670061
7915 19:53:04.670157 RX Delay 11 -> 252, step: 4
7916 19:53:04.677307 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7917 19:53:04.680610 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7918 19:53:04.684038 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7919 19:53:04.687370 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7920 19:53:04.690891 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7921 19:53:04.696972 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7922 19:53:04.700747 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7923 19:53:04.703714 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7924 19:53:04.707162 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7925 19:53:04.710294 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7926 19:53:04.716835 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7927 19:53:04.720170 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7928 19:53:04.723665 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7929 19:53:04.726991 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7930 19:53:04.733786 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7931 19:53:04.736843 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7932 19:53:04.736942 ==
7933 19:53:04.740272 Dram Type= 6, Freq= 0, CH_0, rank 1
7934 19:53:04.743827 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7935 19:53:04.743926 ==
7936 19:53:04.746757 DQS Delay:
7937 19:53:04.746876 DQS0 = 0, DQS1 = 0
7938 19:53:04.746970 DQM Delay:
7939 19:53:04.750456 DQM0 = 128, DQM1 = 120
7940 19:53:04.750527 DQ Delay:
7941 19:53:04.753764 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
7942 19:53:04.757065 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7943 19:53:04.760363 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7944 19:53:04.766649 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7945 19:53:04.766747
7946 19:53:04.766835
7947 19:53:04.766929
7948 19:53:04.769975 [DramC_TX_OE_Calibration] TA2
7949 19:53:04.770056 Original DQ_B0 (3 6) =30, OEN = 27
7950 19:53:04.773501 Original DQ_B1 (3 6) =30, OEN = 27
7951 19:53:04.776602 24, 0x0, End_B0=24 End_B1=24
7952 19:53:04.780212 25, 0x0, End_B0=25 End_B1=25
7953 19:53:04.783258 26, 0x0, End_B0=26 End_B1=26
7954 19:53:04.786661 27, 0x0, End_B0=27 End_B1=27
7955 19:53:04.786745 28, 0x0, End_B0=28 End_B1=28
7956 19:53:04.789805 29, 0x0, End_B0=29 End_B1=29
7957 19:53:04.793225 30, 0x0, End_B0=30 End_B1=30
7958 19:53:04.796660 31, 0x4141, End_B0=30 End_B1=30
7959 19:53:04.799909 Byte0 end_step=30 best_step=27
7960 19:53:04.800007 Byte1 end_step=30 best_step=27
7961 19:53:04.802948 Byte0 TX OE(2T, 0.5T) = (3, 3)
7962 19:53:04.806328 Byte1 TX OE(2T, 0.5T) = (3, 3)
7963 19:53:04.806428
7964 19:53:04.806522
7965 19:53:04.816186 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7966 19:53:04.816289 CH0 RK1: MR19=303, MR18=2222
7967 19:53:04.822740 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
7968 19:53:04.826022 [RxdqsGatingPostProcess] freq 1600
7969 19:53:04.832837 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7970 19:53:04.836155 Pre-setting of DQS Precalculation
7971 19:53:04.839464 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7972 19:53:04.839557 ==
7973 19:53:04.843097 Dram Type= 6, Freq= 0, CH_1, rank 0
7974 19:53:04.849380 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7975 19:53:04.849489 ==
7976 19:53:04.852962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7977 19:53:04.859363 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7978 19:53:04.862622 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7979 19:53:04.869403 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7980 19:53:04.876120 [CA 0] Center 41 (11~71) winsize 61
7981 19:53:04.879393 [CA 1] Center 40 (10~71) winsize 62
7982 19:53:04.882757 [CA 2] Center 36 (6~66) winsize 61
7983 19:53:04.885992 [CA 3] Center 35 (5~65) winsize 61
7984 19:53:04.889640 [CA 4] Center 33 (3~63) winsize 61
7985 19:53:04.892727 [CA 5] Center 33 (4~63) winsize 60
7986 19:53:04.892857
7987 19:53:04.896151 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7988 19:53:04.896291
7989 19:53:04.899516 [CATrainingPosCal] consider 1 rank data
7990 19:53:04.902680 u2DelayCellTimex100 = 275/100 ps
7991 19:53:04.906076 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
7992 19:53:04.912996 CA1 delay=40 (10~71),Diff = 7 PI (24 cell)
7993 19:53:04.915906 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
7994 19:53:04.919181 CA3 delay=35 (5~65),Diff = 2 PI (7 cell)
7995 19:53:04.923167 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
7996 19:53:04.926124 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
7997 19:53:04.926228
7998 19:53:04.929360 CA PerBit enable=1, Macro0, CA PI delay=33
7999 19:53:04.929431
8000 19:53:04.932639 [CBTSetCACLKResult] CA Dly = 33
8001 19:53:04.936123 CS Dly: 8 (0~39)
8002 19:53:04.939197 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8003 19:53:04.942440 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8004 19:53:04.942544 ==
8005 19:53:04.945633 Dram Type= 6, Freq= 0, CH_1, rank 1
8006 19:53:04.949090 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8007 19:53:04.952188 ==
8008 19:53:04.955555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8009 19:53:04.958982 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8010 19:53:04.965725 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8011 19:53:04.972058 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8012 19:53:04.978747 [CA 0] Center 41 (11~71) winsize 61
8013 19:53:04.981916 [CA 1] Center 41 (11~71) winsize 61
8014 19:53:04.985612 [CA 2] Center 36 (7~66) winsize 60
8015 19:53:04.988381 [CA 3] Center 36 (7~65) winsize 59
8016 19:53:04.991921 [CA 4] Center 34 (5~64) winsize 60
8017 19:53:04.995112 [CA 5] Center 34 (4~64) winsize 61
8018 19:53:04.995187
8019 19:53:04.998494 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8020 19:53:04.998564
8021 19:53:05.001687 [CATrainingPosCal] consider 2 rank data
8022 19:53:05.005096 u2DelayCellTimex100 = 275/100 ps
8023 19:53:05.008491 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8024 19:53:05.015006 CA1 delay=41 (11~71),Diff = 8 PI (28 cell)
8025 19:53:05.018240 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8026 19:53:05.022111 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8027 19:53:05.024980 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8028 19:53:05.028249 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8029 19:53:05.028352
8030 19:53:05.031782 CA PerBit enable=1, Macro0, CA PI delay=33
8031 19:53:05.031884
8032 19:53:05.035516 [CBTSetCACLKResult] CA Dly = 33
8033 19:53:05.038694 CS Dly: 9 (0~42)
8034 19:53:05.041792 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8035 19:53:05.044893 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8036 19:53:05.044990
8037 19:53:05.048361 ----->DramcWriteLeveling(PI) begin...
8038 19:53:05.048460 ==
8039 19:53:05.051670 Dram Type= 6, Freq= 0, CH_1, rank 0
8040 19:53:05.058226 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8041 19:53:05.058309 ==
8042 19:53:05.062026 Write leveling (Byte 0): 24 => 24
8043 19:53:05.062124 Write leveling (Byte 1): 24 => 24
8044 19:53:05.065095 DramcWriteLeveling(PI) end<-----
8045 19:53:05.065194
8046 19:53:05.065284 ==
8047 19:53:05.068483 Dram Type= 6, Freq= 0, CH_1, rank 0
8048 19:53:05.074995 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8049 19:53:05.075104 ==
8050 19:53:05.078432 [Gating] SW mode calibration
8051 19:53:05.085150 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8052 19:53:05.088554 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8053 19:53:05.095025 0 12 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8054 19:53:05.098211 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 19:53:05.101727 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 19:53:05.108315 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 19:53:05.111401 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 19:53:05.114805 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 19:53:05.118046 0 12 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8060 19:53:05.124687 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8061 19:53:05.128040 0 13 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8062 19:53:05.131352 0 13 4 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
8063 19:53:05.137880 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 19:53:05.141448 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 19:53:05.144864 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 19:53:05.151339 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 19:53:05.154623 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8068 19:53:05.157846 0 13 28 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8069 19:53:05.164826 0 14 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8070 19:53:05.167773 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 19:53:05.171099 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 19:53:05.177831 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 19:53:05.180971 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 19:53:05.184437 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 19:53:05.190971 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 19:53:05.194428 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8077 19:53:05.197763 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8078 19:53:05.204426 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8079 19:53:05.207655 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 19:53:05.210757 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 19:53:05.217697 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 19:53:05.220927 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 19:53:05.224309 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 19:53:05.230827 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 19:53:05.234104 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 19:53:05.237386 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 19:53:05.244212 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 19:53:05.247276 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 19:53:05.250977 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 19:53:05.257788 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 19:53:05.260880 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8092 19:53:05.264014 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8093 19:53:05.267726 Total UI for P1: 0, mck2ui 16
8094 19:53:05.270663 best dqsien dly found for B0: ( 1, 0, 24)
8095 19:53:05.274390 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8096 19:53:05.281031 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8097 19:53:05.284102 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 19:53:05.287375 Total UI for P1: 0, mck2ui 16
8099 19:53:05.290774 best dqsien dly found for B1: ( 1, 1, 0)
8100 19:53:05.294222 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8101 19:53:05.297286 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8102 19:53:05.297385
8103 19:53:05.301117 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8104 19:53:05.303977 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8105 19:53:05.307375 [Gating] SW calibration Done
8106 19:53:05.307474 ==
8107 19:53:05.310428 Dram Type= 6, Freq= 0, CH_1, rank 0
8108 19:53:05.317239 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8109 19:53:05.317341 ==
8110 19:53:05.317434 RX Vref Scan: 0
8111 19:53:05.317521
8112 19:53:05.320348 RX Vref 0 -> 0, step: 1
8113 19:53:05.320427
8114 19:53:05.323794 RX Delay 0 -> 252, step: 8
8115 19:53:05.327105 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8116 19:53:05.330295 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8117 19:53:05.333841 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8118 19:53:05.337213 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8119 19:53:05.343715 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8120 19:53:05.346921 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8121 19:53:05.350722 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8122 19:53:05.353899 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8123 19:53:05.356988 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8124 19:53:05.363438 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8125 19:53:05.366964 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8126 19:53:05.370063 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8127 19:53:05.373219 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8128 19:53:05.380149 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8129 19:53:05.383552 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8130 19:53:05.386887 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8131 19:53:05.386986 ==
8132 19:53:05.390319 Dram Type= 6, Freq= 0, CH_1, rank 0
8133 19:53:05.393697 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8134 19:53:05.393805 ==
8135 19:53:05.396687 DQS Delay:
8136 19:53:05.396789 DQS0 = 0, DQS1 = 0
8137 19:53:05.400118 DQM Delay:
8138 19:53:05.400248 DQM0 = 130, DQM1 = 125
8139 19:53:05.400311 DQ Delay:
8140 19:53:05.403219 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8141 19:53:05.409857 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8142 19:53:05.413256 DQ8 =107, DQ9 =115, DQ10 =131, DQ11 =115
8143 19:53:05.416381 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8144 19:53:05.416455
8145 19:53:05.416516
8146 19:53:05.416575 ==
8147 19:53:05.419897 Dram Type= 6, Freq= 0, CH_1, rank 0
8148 19:53:05.423063 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8149 19:53:05.423162 ==
8150 19:53:05.423250
8151 19:53:05.423339
8152 19:53:05.426659 TX Vref Scan disable
8153 19:53:05.429795 == TX Byte 0 ==
8154 19:53:05.433037 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8155 19:53:05.436770 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8156 19:53:05.439805 == TX Byte 1 ==
8157 19:53:05.442800 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8158 19:53:05.446441 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8159 19:53:05.446538 ==
8160 19:53:05.449645 Dram Type= 6, Freq= 0, CH_1, rank 0
8161 19:53:05.456339 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8162 19:53:05.456439 ==
8163 19:53:05.466997
8164 19:53:05.469926 TX Vref early break, caculate TX vref
8165 19:53:05.473492 TX Vref=16, minBit 3, minWin=21, winSum=366
8166 19:53:05.476858 TX Vref=18, minBit 0, minWin=22, winSum=376
8167 19:53:05.479929 TX Vref=20, minBit 3, minWin=23, winSum=387
8168 19:53:05.483389 TX Vref=22, minBit 0, minWin=24, winSum=399
8169 19:53:05.486579 TX Vref=24, minBit 0, minWin=24, winSum=404
8170 19:53:05.493191 TX Vref=26, minBit 8, minWin=24, winSum=413
8171 19:53:05.496787 TX Vref=28, minBit 1, minWin=25, winSum=417
8172 19:53:05.500147 TX Vref=30, minBit 9, minWin=24, winSum=405
8173 19:53:05.503500 TX Vref=32, minBit 9, minWin=23, winSum=398
8174 19:53:05.506706 TX Vref=34, minBit 9, minWin=23, winSum=388
8175 19:53:05.513113 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 28
8176 19:53:05.513199
8177 19:53:05.517007 Final TX Range 0 Vref 28
8178 19:53:05.517104
8179 19:53:05.517183 ==
8180 19:53:05.519814 Dram Type= 6, Freq= 0, CH_1, rank 0
8181 19:53:05.523688 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8182 19:53:05.523785 ==
8183 19:53:05.523873
8184 19:53:05.523964
8185 19:53:05.526619 TX Vref Scan disable
8186 19:53:05.533056 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8187 19:53:05.533155 == TX Byte 0 ==
8188 19:53:05.536563 u2DelayCellOfst[0]=14 cells (4 PI)
8189 19:53:05.540037 u2DelayCellOfst[1]=10 cells (3 PI)
8190 19:53:05.543534 u2DelayCellOfst[2]=0 cells (0 PI)
8191 19:53:05.546512 u2DelayCellOfst[3]=7 cells (2 PI)
8192 19:53:05.549874 u2DelayCellOfst[4]=7 cells (2 PI)
8193 19:53:05.553388 u2DelayCellOfst[5]=14 cells (4 PI)
8194 19:53:05.556460 u2DelayCellOfst[6]=17 cells (5 PI)
8195 19:53:05.556550 u2DelayCellOfst[7]=7 cells (2 PI)
8196 19:53:05.563263 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8197 19:53:05.566568 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8198 19:53:05.566664 == TX Byte 1 ==
8199 19:53:05.569563 u2DelayCellOfst[8]=0 cells (0 PI)
8200 19:53:05.572978 u2DelayCellOfst[9]=7 cells (2 PI)
8201 19:53:05.576292 u2DelayCellOfst[10]=10 cells (3 PI)
8202 19:53:05.579905 u2DelayCellOfst[11]=3 cells (1 PI)
8203 19:53:05.583376 u2DelayCellOfst[12]=17 cells (5 PI)
8204 19:53:05.586049 u2DelayCellOfst[13]=21 cells (6 PI)
8205 19:53:05.589358 u2DelayCellOfst[14]=21 cells (6 PI)
8206 19:53:05.592974 u2DelayCellOfst[15]=21 cells (6 PI)
8207 19:53:05.596160 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8208 19:53:05.602581 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8209 19:53:05.602683 DramC Write-DBI on
8210 19:53:05.602774 ==
8211 19:53:05.605883 Dram Type= 6, Freq= 0, CH_1, rank 0
8212 19:53:05.609376 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8213 19:53:05.612424 ==
8214 19:53:05.612524
8215 19:53:05.612618
8216 19:53:05.612706 TX Vref Scan disable
8217 19:53:05.616262 == TX Byte 0 ==
8218 19:53:05.619501 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8219 19:53:05.622636 == TX Byte 1 ==
8220 19:53:05.625920 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8221 19:53:05.626020 DramC Write-DBI off
8222 19:53:05.629337
8223 19:53:05.629434 [DATLAT]
8224 19:53:05.629525 Freq=1600, CH1 RK0
8225 19:53:05.629614
8226 19:53:05.632572 DATLAT Default: 0xf
8227 19:53:05.632666 0, 0xFFFF, sum = 0
8228 19:53:05.636088 1, 0xFFFF, sum = 0
8229 19:53:05.636192 2, 0xFFFF, sum = 0
8230 19:53:05.639156 3, 0xFFFF, sum = 0
8231 19:53:05.642628 4, 0xFFFF, sum = 0
8232 19:53:05.642728 5, 0xFFFF, sum = 0
8233 19:53:05.645931 6, 0xFFFF, sum = 0
8234 19:53:05.646031 7, 0xFFFF, sum = 0
8235 19:53:05.649508 8, 0xFFFF, sum = 0
8236 19:53:05.649590 9, 0xFFFF, sum = 0
8237 19:53:05.652440 10, 0xFFFF, sum = 0
8238 19:53:05.652546 11, 0xFFFF, sum = 0
8239 19:53:05.656057 12, 0x8F7F, sum = 0
8240 19:53:05.656155 13, 0x0, sum = 1
8241 19:53:05.659482 14, 0x0, sum = 2
8242 19:53:05.659582 15, 0x0, sum = 3
8243 19:53:05.662597 16, 0x0, sum = 4
8244 19:53:05.662694 best_step = 14
8245 19:53:05.662786
8246 19:53:05.662873 ==
8247 19:53:05.665949 Dram Type= 6, Freq= 0, CH_1, rank 0
8248 19:53:05.669267 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8249 19:53:05.669377 ==
8250 19:53:05.672468 RX Vref Scan: 1
8251 19:53:05.672567
8252 19:53:05.675741 Set Vref Range= 24 -> 127
8253 19:53:05.675837
8254 19:53:05.675928 RX Vref 24 -> 127, step: 1
8255 19:53:05.679168
8256 19:53:05.679267 RX Delay 3 -> 252, step: 4
8257 19:53:05.679356
8258 19:53:05.682345 Set Vref, RX VrefLevel [Byte0]: 24
8259 19:53:05.685519 [Byte1]: 24
8260 19:53:05.689347
8261 19:53:05.689448 Set Vref, RX VrefLevel [Byte0]: 25
8262 19:53:05.692550 [Byte1]: 25
8263 19:53:05.696942
8264 19:53:05.697044 Set Vref, RX VrefLevel [Byte0]: 26
8265 19:53:05.700360 [Byte1]: 26
8266 19:53:05.704609
8267 19:53:05.704706 Set Vref, RX VrefLevel [Byte0]: 27
8268 19:53:05.707783 [Byte1]: 27
8269 19:53:05.712143
8270 19:53:05.712251 Set Vref, RX VrefLevel [Byte0]: 28
8271 19:53:05.715433 [Byte1]: 28
8272 19:53:05.719829
8273 19:53:05.719926 Set Vref, RX VrefLevel [Byte0]: 29
8274 19:53:05.723288 [Byte1]: 29
8275 19:53:05.727588
8276 19:53:05.727688 Set Vref, RX VrefLevel [Byte0]: 30
8277 19:53:05.730727 [Byte1]: 30
8278 19:53:05.735378
8279 19:53:05.735479 Set Vref, RX VrefLevel [Byte0]: 31
8280 19:53:05.738529 [Byte1]: 31
8281 19:53:05.742827
8282 19:53:05.742927 Set Vref, RX VrefLevel [Byte0]: 32
8283 19:53:05.746061 [Byte1]: 32
8284 19:53:05.750801
8285 19:53:05.750882 Set Vref, RX VrefLevel [Byte0]: 33
8286 19:53:05.753940 [Byte1]: 33
8287 19:53:05.758289
8288 19:53:05.758385 Set Vref, RX VrefLevel [Byte0]: 34
8289 19:53:05.761385 [Byte1]: 34
8290 19:53:05.766023
8291 19:53:05.766118 Set Vref, RX VrefLevel [Byte0]: 35
8292 19:53:05.769131 [Byte1]: 35
8293 19:53:05.773798
8294 19:53:05.773902 Set Vref, RX VrefLevel [Byte0]: 36
8295 19:53:05.776853 [Byte1]: 36
8296 19:53:05.781341
8297 19:53:05.781438 Set Vref, RX VrefLevel [Byte0]: 37
8298 19:53:05.784702 [Byte1]: 37
8299 19:53:05.788709
8300 19:53:05.788811 Set Vref, RX VrefLevel [Byte0]: 38
8301 19:53:05.792081 [Byte1]: 38
8302 19:53:05.796603
8303 19:53:05.796688 Set Vref, RX VrefLevel [Byte0]: 39
8304 19:53:05.799716 [Byte1]: 39
8305 19:53:05.804221
8306 19:53:05.804300 Set Vref, RX VrefLevel [Byte0]: 40
8307 19:53:05.807662 [Byte1]: 40
8308 19:53:05.811874
8309 19:53:05.811952 Set Vref, RX VrefLevel [Byte0]: 41
8310 19:53:05.815003 [Byte1]: 41
8311 19:53:05.819432
8312 19:53:05.819510 Set Vref, RX VrefLevel [Byte0]: 42
8313 19:53:05.822890 [Byte1]: 42
8314 19:53:05.827190
8315 19:53:05.827268 Set Vref, RX VrefLevel [Byte0]: 43
8316 19:53:05.830507 [Byte1]: 43
8317 19:53:05.834566
8318 19:53:05.834645 Set Vref, RX VrefLevel [Byte0]: 44
8319 19:53:05.837997 [Byte1]: 44
8320 19:53:05.842291
8321 19:53:05.842364 Set Vref, RX VrefLevel [Byte0]: 45
8322 19:53:05.845912 [Byte1]: 45
8323 19:53:05.849930
8324 19:53:05.850037 Set Vref, RX VrefLevel [Byte0]: 46
8325 19:53:05.853355 [Byte1]: 46
8326 19:53:05.857741
8327 19:53:05.857819 Set Vref, RX VrefLevel [Byte0]: 47
8328 19:53:05.860909 [Byte1]: 47
8329 19:53:05.865256
8330 19:53:05.865334 Set Vref, RX VrefLevel [Byte0]: 48
8331 19:53:05.868594 [Byte1]: 48
8332 19:53:05.872934
8333 19:53:05.873012 Set Vref, RX VrefLevel [Byte0]: 49
8334 19:53:05.876413 [Byte1]: 49
8335 19:53:05.880867
8336 19:53:05.880945 Set Vref, RX VrefLevel [Byte0]: 50
8337 19:53:05.884015 [Byte1]: 50
8338 19:53:05.888075
8339 19:53:05.888203 Set Vref, RX VrefLevel [Byte0]: 51
8340 19:53:05.891754 [Byte1]: 51
8341 19:53:05.895853
8342 19:53:05.895931 Set Vref, RX VrefLevel [Byte0]: 52
8343 19:53:05.899220 [Byte1]: 52
8344 19:53:05.903553
8345 19:53:05.903632 Set Vref, RX VrefLevel [Byte0]: 53
8346 19:53:05.906883 [Byte1]: 53
8347 19:53:05.911324
8348 19:53:05.911402 Set Vref, RX VrefLevel [Byte0]: 54
8349 19:53:05.914483 [Byte1]: 54
8350 19:53:05.918975
8351 19:53:05.919053 Set Vref, RX VrefLevel [Byte0]: 55
8352 19:53:05.922225 [Byte1]: 55
8353 19:53:05.926756
8354 19:53:05.926834 Set Vref, RX VrefLevel [Byte0]: 56
8355 19:53:05.929737 [Byte1]: 56
8356 19:53:05.934170
8357 19:53:05.934249 Set Vref, RX VrefLevel [Byte0]: 57
8358 19:53:05.937743 [Byte1]: 57
8359 19:53:05.941781
8360 19:53:05.941861 Set Vref, RX VrefLevel [Byte0]: 58
8361 19:53:05.945530 [Byte1]: 58
8362 19:53:05.949590
8363 19:53:05.949670 Set Vref, RX VrefLevel [Byte0]: 59
8364 19:53:05.952973 [Byte1]: 59
8365 19:53:05.957098
8366 19:53:05.957168 Set Vref, RX VrefLevel [Byte0]: 60
8367 19:53:05.960441 [Byte1]: 60
8368 19:53:05.964746
8369 19:53:05.964816 Set Vref, RX VrefLevel [Byte0]: 61
8370 19:53:05.971466 [Byte1]: 61
8371 19:53:05.971543
8372 19:53:05.974410 Set Vref, RX VrefLevel [Byte0]: 62
8373 19:53:05.977839 [Byte1]: 62
8374 19:53:05.977909
8375 19:53:05.981084 Set Vref, RX VrefLevel [Byte0]: 63
8376 19:53:05.984436 [Byte1]: 63
8377 19:53:05.987942
8378 19:53:05.988015 Set Vref, RX VrefLevel [Byte0]: 64
8379 19:53:05.990997 [Byte1]: 64
8380 19:53:05.995607
8381 19:53:05.995679 Set Vref, RX VrefLevel [Byte0]: 65
8382 19:53:05.998557 [Byte1]: 65
8383 19:53:06.002937
8384 19:53:06.003016 Set Vref, RX VrefLevel [Byte0]: 66
8385 19:53:06.006215 [Byte1]: 66
8386 19:53:06.010486
8387 19:53:06.010587 Set Vref, RX VrefLevel [Byte0]: 67
8388 19:53:06.014264 [Byte1]: 67
8389 19:53:06.018234
8390 19:53:06.018334 Set Vref, RX VrefLevel [Byte0]: 68
8391 19:53:06.021810 [Byte1]: 68
8392 19:53:06.026205
8393 19:53:06.026305 Set Vref, RX VrefLevel [Byte0]: 69
8394 19:53:06.029238 [Byte1]: 69
8395 19:53:06.033707
8396 19:53:06.033808 Set Vref, RX VrefLevel [Byte0]: 70
8397 19:53:06.037188 [Byte1]: 70
8398 19:53:06.041717
8399 19:53:06.041813 Set Vref, RX VrefLevel [Byte0]: 71
8400 19:53:06.044517 [Byte1]: 71
8401 19:53:06.048987
8402 19:53:06.049083 Set Vref, RX VrefLevel [Byte0]: 72
8403 19:53:06.052483 [Byte1]: 72
8404 19:53:06.056611
8405 19:53:06.056709 Set Vref, RX VrefLevel [Byte0]: 73
8406 19:53:06.059799 [Byte1]: 73
8407 19:53:06.064070
8408 19:53:06.064169 Final RX Vref Byte 0 = 60 to rank0
8409 19:53:06.067439 Final RX Vref Byte 1 = 52 to rank0
8410 19:53:06.070702 Final RX Vref Byte 0 = 60 to rank1
8411 19:53:06.074080 Final RX Vref Byte 1 = 52 to rank1==
8412 19:53:06.077317 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 19:53:06.083918 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8414 19:53:06.084019 ==
8415 19:53:06.084110 DQS Delay:
8416 19:53:06.087336 DQS0 = 0, DQS1 = 0
8417 19:53:06.087432 DQM Delay:
8418 19:53:06.087522 DQM0 = 128, DQM1 = 123
8419 19:53:06.090774 DQ Delay:
8420 19:53:06.093932 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8421 19:53:06.097116 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =124
8422 19:53:06.100558 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114
8423 19:53:06.103699 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8424 19:53:06.103797
8425 19:53:06.103887
8426 19:53:06.103977
8427 19:53:06.107005 [DramC_TX_OE_Calibration] TA2
8428 19:53:06.110244 Original DQ_B0 (3 6) =30, OEN = 27
8429 19:53:06.113732 Original DQ_B1 (3 6) =30, OEN = 27
8430 19:53:06.116955 24, 0x0, End_B0=24 End_B1=24
8431 19:53:06.117027 25, 0x0, End_B0=25 End_B1=25
8432 19:53:06.120277 26, 0x0, End_B0=26 End_B1=26
8433 19:53:06.123756 27, 0x0, End_B0=27 End_B1=27
8434 19:53:06.127196 28, 0x0, End_B0=28 End_B1=28
8435 19:53:06.130769 29, 0x0, End_B0=29 End_B1=29
8436 19:53:06.130873 30, 0x0, End_B0=30 End_B1=30
8437 19:53:06.133522 31, 0x4141, End_B0=30 End_B1=30
8438 19:53:06.137026 Byte0 end_step=30 best_step=27
8439 19:53:06.140279 Byte1 end_step=30 best_step=27
8440 19:53:06.143427 Byte0 TX OE(2T, 0.5T) = (3, 3)
8441 19:53:06.146764 Byte1 TX OE(2T, 0.5T) = (3, 3)
8442 19:53:06.146863
8443 19:53:06.146955
8444 19:53:06.153501 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8445 19:53:06.156801 CH1 RK0: MR19=303, MR18=2626
8446 19:53:06.163352 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8447 19:53:06.163454
8448 19:53:06.166751 ----->DramcWriteLeveling(PI) begin...
8449 19:53:06.166856 ==
8450 19:53:06.170189 Dram Type= 6, Freq= 0, CH_1, rank 1
8451 19:53:06.173246 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8452 19:53:06.173346 ==
8453 19:53:06.176891 Write leveling (Byte 0): 23 => 23
8454 19:53:06.179834 Write leveling (Byte 1): 21 => 21
8455 19:53:06.183517 DramcWriteLeveling(PI) end<-----
8456 19:53:06.183611
8457 19:53:06.183702 ==
8458 19:53:06.187129 Dram Type= 6, Freq= 0, CH_1, rank 1
8459 19:53:06.189904 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8460 19:53:06.190015 ==
8461 19:53:06.193175 [Gating] SW mode calibration
8462 19:53:06.200033 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8463 19:53:06.206595 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8464 19:53:06.209787 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8465 19:53:06.216438 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8466 19:53:06.219711 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8467 19:53:06.222885 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8468 19:53:06.229810 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8469 19:53:06.233039 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8470 19:53:06.236417 0 12 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8471 19:53:06.242982 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (1 0) (0 0)
8472 19:53:06.246262 0 13 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
8473 19:53:06.249777 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8474 19:53:06.256419 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 19:53:06.259336 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8476 19:53:06.262813 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8477 19:53:06.269302 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8478 19:53:06.273252 0 13 24 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
8479 19:53:06.276578 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8480 19:53:06.279491 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8481 19:53:06.286002 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8482 19:53:06.289678 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 19:53:06.292765 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 19:53:06.299273 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 19:53:06.302533 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 19:53:06.305991 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8487 19:53:06.312491 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8488 19:53:06.315926 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8489 19:53:06.319430 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 19:53:06.326061 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 19:53:06.329206 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 19:53:06.332614 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 19:53:06.339348 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 19:53:06.342454 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 19:53:06.345791 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 19:53:06.352390 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 19:53:06.355846 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 19:53:06.359068 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 19:53:06.365698 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 19:53:06.368934 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 19:53:06.372392 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 19:53:06.378857 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8503 19:53:06.382334 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8504 19:53:06.385396 Total UI for P1: 0, mck2ui 16
8505 19:53:06.388599 best dqsien dly found for B0: ( 1, 0, 24)
8506 19:53:06.391937 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8507 19:53:06.398892 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8508 19:53:06.399004 Total UI for P1: 0, mck2ui 16
8509 19:53:06.405307 best dqsien dly found for B1: ( 1, 0, 30)
8510 19:53:06.408543 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8511 19:53:06.412071 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8512 19:53:06.412169
8513 19:53:06.415299 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8514 19:53:06.418576 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8515 19:53:06.422201 [Gating] SW calibration Done
8516 19:53:06.422305 ==
8517 19:53:06.425499 Dram Type= 6, Freq= 0, CH_1, rank 1
8518 19:53:06.428614 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8519 19:53:06.428689 ==
8520 19:53:06.431769 RX Vref Scan: 0
8521 19:53:06.431865
8522 19:53:06.431957 RX Vref 0 -> 0, step: 1
8523 19:53:06.432047
8524 19:53:06.435261 RX Delay 0 -> 252, step: 8
8525 19:53:06.438461 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8526 19:53:06.445179 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8527 19:53:06.448643 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8528 19:53:06.451921 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8529 19:53:06.455084 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8530 19:53:06.458403 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8531 19:53:06.464931 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8532 19:53:06.468495 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8533 19:53:06.471927 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8534 19:53:06.475137 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8535 19:53:06.478386 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8536 19:53:06.485231 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8537 19:53:06.488426 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8538 19:53:06.491619 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8539 19:53:06.494646 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8540 19:53:06.498297 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8541 19:53:06.501450 ==
8542 19:53:06.505059 Dram Type= 6, Freq= 0, CH_1, rank 1
8543 19:53:06.508143 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8544 19:53:06.508233 ==
8545 19:53:06.508298 DQS Delay:
8546 19:53:06.511444 DQS0 = 0, DQS1 = 0
8547 19:53:06.511524 DQM Delay:
8548 19:53:06.514825 DQM0 = 130, DQM1 = 125
8549 19:53:06.514905 DQ Delay:
8550 19:53:06.517898 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8551 19:53:06.521401 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8552 19:53:06.524880 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8553 19:53:06.528083 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8554 19:53:06.528199
8555 19:53:06.528291
8556 19:53:06.528376 ==
8557 19:53:06.531468 Dram Type= 6, Freq= 0, CH_1, rank 1
8558 19:53:06.538171 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8559 19:53:06.538251 ==
8560 19:53:06.538315
8561 19:53:06.538375
8562 19:53:06.538432 TX Vref Scan disable
8563 19:53:06.541620 == TX Byte 0 ==
8564 19:53:06.544835 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8565 19:53:06.551526 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8566 19:53:06.551607 == TX Byte 1 ==
8567 19:53:06.554775 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8568 19:53:06.561278 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8569 19:53:06.561385 ==
8570 19:53:06.564831 Dram Type= 6, Freq= 0, CH_1, rank 1
8571 19:53:06.568013 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8572 19:53:06.568110 ==
8573 19:53:06.580092
8574 19:53:06.583366 TX Vref early break, caculate TX vref
8575 19:53:06.586885 TX Vref=16, minBit 0, minWin=21, winSum=376
8576 19:53:06.590075 TX Vref=18, minBit 0, minWin=22, winSum=385
8577 19:53:06.593415 TX Vref=20, minBit 5, minWin=22, winSum=391
8578 19:53:06.596957 TX Vref=22, minBit 0, minWin=22, winSum=403
8579 19:53:06.600483 TX Vref=24, minBit 0, minWin=23, winSum=408
8580 19:53:06.606599 TX Vref=26, minBit 0, minWin=24, winSum=416
8581 19:53:06.610043 TX Vref=28, minBit 5, minWin=24, winSum=415
8582 19:53:06.613295 TX Vref=30, minBit 0, minWin=24, winSum=413
8583 19:53:06.616492 TX Vref=32, minBit 0, minWin=22, winSum=404
8584 19:53:06.619917 TX Vref=34, minBit 0, minWin=21, winSum=394
8585 19:53:06.626684 [TxChooseVref] Worse bit 0, Min win 24, Win sum 416, Final Vref 26
8586 19:53:06.626785
8587 19:53:06.629903 Final TX Range 0 Vref 26
8588 19:53:06.630003
8589 19:53:06.630093 ==
8590 19:53:06.633113 Dram Type= 6, Freq= 0, CH_1, rank 1
8591 19:53:06.636484 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8592 19:53:06.636555 ==
8593 19:53:06.636616
8594 19:53:06.636677
8595 19:53:06.639773 TX Vref Scan disable
8596 19:53:06.646659 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8597 19:53:06.646755 == TX Byte 0 ==
8598 19:53:06.649827 u2DelayCellOfst[0]=17 cells (5 PI)
8599 19:53:06.653045 u2DelayCellOfst[1]=10 cells (3 PI)
8600 19:53:06.656584 u2DelayCellOfst[2]=0 cells (0 PI)
8601 19:53:06.659806 u2DelayCellOfst[3]=10 cells (3 PI)
8602 19:53:06.663250 u2DelayCellOfst[4]=10 cells (3 PI)
8603 19:53:06.666420 u2DelayCellOfst[5]=21 cells (6 PI)
8604 19:53:06.669812 u2DelayCellOfst[6]=17 cells (5 PI)
8605 19:53:06.669892 u2DelayCellOfst[7]=7 cells (2 PI)
8606 19:53:06.676797 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8607 19:53:06.679971 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8608 19:53:06.680051 == TX Byte 1 ==
8609 19:53:06.683525 u2DelayCellOfst[8]=0 cells (0 PI)
8610 19:53:06.686676 u2DelayCellOfst[9]=3 cells (1 PI)
8611 19:53:06.689739 u2DelayCellOfst[10]=10 cells (3 PI)
8612 19:53:06.693388 u2DelayCellOfst[11]=0 cells (0 PI)
8613 19:53:06.696352 u2DelayCellOfst[12]=14 cells (4 PI)
8614 19:53:06.699744 u2DelayCellOfst[13]=17 cells (5 PI)
8615 19:53:06.702891 u2DelayCellOfst[14]=17 cells (5 PI)
8616 19:53:06.706393 u2DelayCellOfst[15]=14 cells (4 PI)
8617 19:53:06.709587 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8618 19:53:06.716262 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8619 19:53:06.716346 DramC Write-DBI on
8620 19:53:06.716432 ==
8621 19:53:06.719486 Dram Type= 6, Freq= 0, CH_1, rank 1
8622 19:53:06.722931 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8623 19:53:06.726436 ==
8624 19:53:06.726520
8625 19:53:06.726605
8626 19:53:06.726685 TX Vref Scan disable
8627 19:53:06.729568 == TX Byte 0 ==
8628 19:53:06.732840 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8629 19:53:06.736171 == TX Byte 1 ==
8630 19:53:06.739751 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8631 19:53:06.742829 DramC Write-DBI off
8632 19:53:06.742912
8633 19:53:06.742997 [DATLAT]
8634 19:53:06.743078 Freq=1600, CH1 RK1
8635 19:53:06.743157
8636 19:53:06.746188 DATLAT Default: 0xe
8637 19:53:06.746272 0, 0xFFFF, sum = 0
8638 19:53:06.749341 1, 0xFFFF, sum = 0
8639 19:53:06.752862 2, 0xFFFF, sum = 0
8640 19:53:06.752947 3, 0xFFFF, sum = 0
8641 19:53:06.755978 4, 0xFFFF, sum = 0
8642 19:53:06.756062 5, 0xFFFF, sum = 0
8643 19:53:06.759520 6, 0xFFFF, sum = 0
8644 19:53:06.759606 7, 0xFFFF, sum = 0
8645 19:53:06.762902 8, 0xFFFF, sum = 0
8646 19:53:06.762987 9, 0xFFFF, sum = 0
8647 19:53:06.766032 10, 0xFFFF, sum = 0
8648 19:53:06.766116 11, 0xFFFF, sum = 0
8649 19:53:06.769317 12, 0xF7F, sum = 0
8650 19:53:06.769402 13, 0x0, sum = 1
8651 19:53:06.772458 14, 0x0, sum = 2
8652 19:53:06.772543 15, 0x0, sum = 3
8653 19:53:06.775958 16, 0x0, sum = 4
8654 19:53:06.776043 best_step = 14
8655 19:53:06.776143
8656 19:53:06.776268 ==
8657 19:53:06.779296 Dram Type= 6, Freq= 0, CH_1, rank 1
8658 19:53:06.782506 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8659 19:53:06.785796 ==
8660 19:53:06.785879 RX Vref Scan: 0
8661 19:53:06.785964
8662 19:53:06.789069 RX Vref 0 -> 0, step: 1
8663 19:53:06.789152
8664 19:53:06.789237 RX Delay 3 -> 252, step: 4
8665 19:53:06.796725 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8666 19:53:06.799981 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8667 19:53:06.803002 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8668 19:53:06.806540 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8669 19:53:06.809614 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8670 19:53:06.816540 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8671 19:53:06.819667 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8672 19:53:06.823010 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8673 19:53:06.826398 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8674 19:53:06.829914 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8675 19:53:06.836298 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8676 19:53:06.839704 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8677 19:53:06.843056 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8678 19:53:06.846289 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8679 19:53:06.853313 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8680 19:53:06.856249 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8681 19:53:06.856334 ==
8682 19:53:06.859855 Dram Type= 6, Freq= 0, CH_1, rank 1
8683 19:53:06.863166 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8684 19:53:06.863249 ==
8685 19:53:06.863334 DQS Delay:
8686 19:53:06.866347 DQS0 = 0, DQS1 = 0
8687 19:53:06.866430 DQM Delay:
8688 19:53:06.869548 DQM0 = 127, DQM1 = 122
8689 19:53:06.869631 DQ Delay:
8690 19:53:06.873129 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8691 19:53:06.876046 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8692 19:53:06.879935 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8693 19:53:06.886177 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8694 19:53:06.886261
8695 19:53:06.886346
8696 19:53:06.886426
8697 19:53:06.886504 [DramC_TX_OE_Calibration] TA2
8698 19:53:06.889470 Original DQ_B0 (3 6) =30, OEN = 27
8699 19:53:06.892760 Original DQ_B1 (3 6) =30, OEN = 27
8700 19:53:06.896107 24, 0x0, End_B0=24 End_B1=24
8701 19:53:06.899393 25, 0x0, End_B0=25 End_B1=25
8702 19:53:06.902902 26, 0x0, End_B0=26 End_B1=26
8703 19:53:06.902986 27, 0x0, End_B0=27 End_B1=27
8704 19:53:06.906138 28, 0x0, End_B0=28 End_B1=28
8705 19:53:06.909348 29, 0x0, End_B0=29 End_B1=29
8706 19:53:06.912785 30, 0x0, End_B0=30 End_B1=30
8707 19:53:06.916520 31, 0x4141, End_B0=30 End_B1=30
8708 19:53:06.916601 Byte0 end_step=30 best_step=27
8709 19:53:06.919551 Byte1 end_step=30 best_step=27
8710 19:53:06.923023 Byte0 TX OE(2T, 0.5T) = (3, 3)
8711 19:53:06.926037 Byte1 TX OE(2T, 0.5T) = (3, 3)
8712 19:53:06.926118
8713 19:53:06.926182
8714 19:53:06.936153 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8715 19:53:06.936273 CH1 RK1: MR19=303, MR18=1C1C
8716 19:53:06.942392 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8717 19:53:06.946018 [RxdqsGatingPostProcess] freq 1600
8718 19:53:06.952343 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8719 19:53:06.955886 Pre-setting of DQS Precalculation
8720 19:53:06.959566 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8721 19:53:06.968836 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8722 19:53:06.975399 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8723 19:53:06.975481
8724 19:53:06.975545
8725 19:53:06.978668 [Calibration Summary] 3200 Mbps
8726 19:53:06.978749 CH 0, Rank 0
8727 19:53:06.982118 SW Impedance : PASS
8728 19:53:06.982199 DUTY Scan : NO K
8729 19:53:06.985600 ZQ Calibration : PASS
8730 19:53:06.988989 Jitter Meter : NO K
8731 19:53:06.989070 CBT Training : PASS
8732 19:53:06.992149 Write leveling : PASS
8733 19:53:06.995199 RX DQS gating : PASS
8734 19:53:06.995280 RX DQ/DQS(RDDQC) : PASS
8735 19:53:06.998474 TX DQ/DQS : PASS
8736 19:53:07.001927 RX DATLAT : PASS
8737 19:53:07.002008 RX DQ/DQS(Engine): PASS
8738 19:53:07.005440 TX OE : PASS
8739 19:53:07.005521 All Pass.
8740 19:53:07.005586
8741 19:53:07.008403 CH 0, Rank 1
8742 19:53:07.008484 SW Impedance : PASS
8743 19:53:07.011824 DUTY Scan : NO K
8744 19:53:07.011905 ZQ Calibration : PASS
8745 19:53:07.015185 Jitter Meter : NO K
8746 19:53:07.018495 CBT Training : PASS
8747 19:53:07.018576 Write leveling : PASS
8748 19:53:07.021908 RX DQS gating : PASS
8749 19:53:07.024931 RX DQ/DQS(RDDQC) : PASS
8750 19:53:07.025012 TX DQ/DQS : PASS
8751 19:53:07.028246 RX DATLAT : PASS
8752 19:53:07.031759 RX DQ/DQS(Engine): PASS
8753 19:53:07.031840 TX OE : PASS
8754 19:53:07.034850 All Pass.
8755 19:53:07.034930
8756 19:53:07.034994 CH 1, Rank 0
8757 19:53:07.038356 SW Impedance : PASS
8758 19:53:07.038436 DUTY Scan : NO K
8759 19:53:07.041475 ZQ Calibration : PASS
8760 19:53:07.044870 Jitter Meter : NO K
8761 19:53:07.044951 CBT Training : PASS
8762 19:53:07.048116 Write leveling : PASS
8763 19:53:07.051339 RX DQS gating : PASS
8764 19:53:07.051420 RX DQ/DQS(RDDQC) : PASS
8765 19:53:07.055000 TX DQ/DQS : PASS
8766 19:53:07.057906 RX DATLAT : PASS
8767 19:53:07.057987 RX DQ/DQS(Engine): PASS
8768 19:53:07.061226 TX OE : PASS
8769 19:53:07.061308 All Pass.
8770 19:53:07.061372
8771 19:53:07.064732 CH 1, Rank 1
8772 19:53:07.064812 SW Impedance : PASS
8773 19:53:07.067902 DUTY Scan : NO K
8774 19:53:07.071112 ZQ Calibration : PASS
8775 19:53:07.071192 Jitter Meter : NO K
8776 19:53:07.074704 CBT Training : PASS
8777 19:53:07.074785 Write leveling : PASS
8778 19:53:07.077711 RX DQS gating : PASS
8779 19:53:07.081274 RX DQ/DQS(RDDQC) : PASS
8780 19:53:07.081355 TX DQ/DQS : PASS
8781 19:53:07.084397 RX DATLAT : PASS
8782 19:53:07.087980 RX DQ/DQS(Engine): PASS
8783 19:53:07.088087 TX OE : PASS
8784 19:53:07.091127 All Pass.
8785 19:53:07.091208
8786 19:53:07.091272 DramC Write-DBI on
8787 19:53:07.094437 PER_BANK_REFRESH: Hybrid Mode
8788 19:53:07.097907 TX_TRACKING: ON
8789 19:53:07.104759 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8790 19:53:07.114304 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8791 19:53:07.120974 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8792 19:53:07.124337 [FAST_K] Save calibration result to emmc
8793 19:53:07.127739 sync common calibartion params.
8794 19:53:07.127820 sync cbt_mode0:0, 1:0
8795 19:53:07.131138 dram_init: ddr_geometry: 0
8796 19:53:07.134277 dram_init: ddr_geometry: 0
8797 19:53:07.137367 dram_init: ddr_geometry: 0
8798 19:53:07.137448 0:dram_rank_size:80000000
8799 19:53:07.140877 1:dram_rank_size:80000000
8800 19:53:07.147896 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8801 19:53:07.147978 DFS_SHUFFLE_HW_MODE: ON
8802 19:53:07.150866 dramc_set_vcore_voltage set vcore to 725000
8803 19:53:07.154161 Read voltage for 1600, 0
8804 19:53:07.154241 Vio18 = 0
8805 19:53:07.157264 Vcore = 725000
8806 19:53:07.157345 Vdram = 0
8807 19:53:07.157429 Vddq = 0
8808 19:53:07.160603 Vmddr = 0
8809 19:53:07.160683 switch to 3200 Mbps bootup
8810 19:53:07.164394 [DramcRunTimeConfig]
8811 19:53:07.164474 PHYPLL
8812 19:53:07.167436 DPM_CONTROL_AFTERK: ON
8813 19:53:07.167517 PER_BANK_REFRESH: ON
8814 19:53:07.170562 REFRESH_OVERHEAD_REDUCTION: ON
8815 19:53:07.174018 CMD_PICG_NEW_MODE: OFF
8816 19:53:07.174098 XRTWTW_NEW_MODE: ON
8817 19:53:07.177187 XRTRTR_NEW_MODE: ON
8818 19:53:07.177267 TX_TRACKING: ON
8819 19:53:07.180739 RDSEL_TRACKING: OFF
8820 19:53:07.183872 DQS Precalculation for DVFS: ON
8821 19:53:07.183982 RX_TRACKING: OFF
8822 19:53:07.187324 HW_GATING DBG: ON
8823 19:53:07.187405 ZQCS_ENABLE_LP4: ON
8824 19:53:07.190891 RX_PICG_NEW_MODE: ON
8825 19:53:07.190972 TX_PICG_NEW_MODE: ON
8826 19:53:07.193883 ENABLE_RX_DCM_DPHY: ON
8827 19:53:07.197148 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8828 19:53:07.200740 DUMMY_READ_FOR_TRACKING: OFF
8829 19:53:07.200821 !!! SPM_CONTROL_AFTERK: OFF
8830 19:53:07.203989 !!! SPM could not control APHY
8831 19:53:07.207151 IMPEDANCE_TRACKING: ON
8832 19:53:07.207232 TEMP_SENSOR: ON
8833 19:53:07.210386 HW_SAVE_FOR_SR: OFF
8834 19:53:07.213619 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8835 19:53:07.217004 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8836 19:53:07.220219 Read ODT Tracking: ON
8837 19:53:07.220300 Refresh Rate DeBounce: ON
8838 19:53:07.223570 DFS_NO_QUEUE_FLUSH: ON
8839 19:53:07.226947 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8840 19:53:07.229996 ENABLE_DFS_RUNTIME_MRW: OFF
8841 19:53:07.230076 DDR_RESERVE_NEW_MODE: ON
8842 19:53:07.233702 MR_CBT_SWITCH_FREQ: ON
8843 19:53:07.236598 =========================
8844 19:53:07.254268 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8845 19:53:07.257257 dram_init: ddr_geometry: 0
8846 19:53:07.275555 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8847 19:53:07.278616 dram_init: dram init end (result: 0)
8848 19:53:07.285474 DRAM-K: Full calibration passed in 23369 msecs
8849 19:53:07.288674 MRC: failed to locate region type 0.
8850 19:53:07.288755 DRAM rank0 size:0x80000000,
8851 19:53:07.292093 DRAM rank1 size=0x80000000
8852 19:53:07.301905 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8853 19:53:07.308502 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8854 19:53:07.315370 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8855 19:53:07.321618 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8856 19:53:07.325118 DRAM rank0 size:0x80000000,
8857 19:53:07.328439 DRAM rank1 size=0x80000000
8858 19:53:07.328520 CBMEM:
8859 19:53:07.331810 IMD: root @ 0xfffff000 254 entries.
8860 19:53:07.335067 IMD: root @ 0xffffec00 62 entries.
8861 19:53:07.338450 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8862 19:53:07.341945 WARNING: RO_VPD is uninitialized or empty.
8863 19:53:07.348397 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8864 19:53:07.354973 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8865 19:53:07.367753 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
8866 19:53:07.379048 BS: romstage times (exec / console): total (unknown) / 22919 ms
8867 19:53:07.379130
8868 19:53:07.379194
8869 19:53:07.389049 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8870 19:53:07.392310 ARM64: Exception handlers installed.
8871 19:53:07.395624 ARM64: Testing exception
8872 19:53:07.399121 ARM64: Done test exception
8873 19:53:07.399201 Enumerating buses...
8874 19:53:07.402178 Show all devs... Before device enumeration.
8875 19:53:07.405494 Root Device: enabled 1
8876 19:53:07.408775 CPU_CLUSTER: 0: enabled 1
8877 19:53:07.408855 CPU: 00: enabled 1
8878 19:53:07.412053 Compare with tree...
8879 19:53:07.412160 Root Device: enabled 1
8880 19:53:07.415546 CPU_CLUSTER: 0: enabled 1
8881 19:53:07.419076 CPU: 00: enabled 1
8882 19:53:07.419157 Root Device scanning...
8883 19:53:07.422482 scan_static_bus for Root Device
8884 19:53:07.425327 CPU_CLUSTER: 0 enabled
8885 19:53:07.428723 scan_static_bus for Root Device done
8886 19:53:07.432021 scan_bus: bus Root Device finished in 8 msecs
8887 19:53:07.432127 done
8888 19:53:07.438964 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8889 19:53:07.441782 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8890 19:53:07.448825 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8891 19:53:07.452168 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8892 19:53:07.455204 Allocating resources...
8893 19:53:07.458645 Reading resources...
8894 19:53:07.462190 Root Device read_resources bus 0 link: 0
8895 19:53:07.462270 DRAM rank0 size:0x80000000,
8896 19:53:07.465384 DRAM rank1 size=0x80000000
8897 19:53:07.468715 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8898 19:53:07.471785 CPU: 00 missing read_resources
8899 19:53:07.475220 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8900 19:53:07.481947 Root Device read_resources bus 0 link: 0 done
8901 19:53:07.482027 Done reading resources.
8902 19:53:07.488583 Show resources in subtree (Root Device)...After reading.
8903 19:53:07.492108 Root Device child on link 0 CPU_CLUSTER: 0
8904 19:53:07.495466 CPU_CLUSTER: 0 child on link 0 CPU: 00
8905 19:53:07.505104 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8906 19:53:07.505185 CPU: 00
8907 19:53:07.508490 Root Device assign_resources, bus 0 link: 0
8908 19:53:07.512112 CPU_CLUSTER: 0 missing set_resources
8909 19:53:07.518544 Root Device assign_resources, bus 0 link: 0 done
8910 19:53:07.518624 Done setting resources.
8911 19:53:07.525179 Show resources in subtree (Root Device)...After assigning values.
8912 19:53:07.528392 Root Device child on link 0 CPU_CLUSTER: 0
8913 19:53:07.531672 CPU_CLUSTER: 0 child on link 0 CPU: 00
8914 19:53:07.541826 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8915 19:53:07.541907 CPU: 00
8916 19:53:07.544953 Done allocating resources.
8917 19:53:07.548283 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8918 19:53:07.551441 Enabling resources...
8919 19:53:07.551520 done.
8920 19:53:07.558246 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8921 19:53:07.558326 Initializing devices...
8922 19:53:07.561696 Root Device init
8923 19:53:07.561775 init hardware done!
8924 19:53:07.564847 0x00000018: ctrlr->caps
8925 19:53:07.568197 52.000 MHz: ctrlr->f_max
8926 19:53:07.568279 0.400 MHz: ctrlr->f_min
8927 19:53:07.571645 0x40ff8080: ctrlr->voltages
8928 19:53:07.571727 sclk: 390625
8929 19:53:07.574682 Bus Width = 1
8930 19:53:07.574790 sclk: 390625
8931 19:53:07.577900 Bus Width = 1
8932 19:53:07.577983 Early init status = 3
8933 19:53:07.584990 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8934 19:53:07.588145 in-header: 03 fc 00 00 01 00 00 00
8935 19:53:07.591115 in-data: 00
8936 19:53:07.594771 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8937 19:53:07.598543 in-header: 03 fd 00 00 00 00 00 00
8938 19:53:07.601849 in-data:
8939 19:53:07.604762 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8940 19:53:07.608145 in-header: 03 fc 00 00 01 00 00 00
8941 19:53:07.611698 in-data: 00
8942 19:53:07.614809 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8943 19:53:07.619668 in-header: 03 fd 00 00 00 00 00 00
8944 19:53:07.623030 in-data:
8945 19:53:07.626490 [SSUSB] Setting up USB HOST controller...
8946 19:53:07.629645 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8947 19:53:07.633173 [SSUSB] phy power-on done.
8948 19:53:07.636106 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8949 19:53:07.642851 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8950 19:53:07.646269 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8951 19:53:07.652774 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8952 19:53:07.659573 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8953 19:53:07.666138 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8954 19:53:07.672747 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8955 19:53:07.679411 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8956 19:53:07.682734 SPM: binary array size = 0x9dc
8957 19:53:07.686017 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8958 19:53:07.692595 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8959 19:53:07.699209 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8960 19:53:07.702611 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8961 19:53:07.709036 configure_display: Starting display init
8962 19:53:07.742839 anx7625_power_on_init: Init interface.
8963 19:53:07.746158 anx7625_disable_pd_protocol: Disabled PD feature.
8964 19:53:07.749211 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8965 19:53:07.777325 anx7625_start_dp_work: Secure OCM version=00
8966 19:53:07.780489 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8967 19:53:07.795352 sp_tx_get_edid_block: EDID Block = 1
8968 19:53:07.898051 Extracted contents:
8969 19:53:07.901085 header: 00 ff ff ff ff ff ff 00
8970 19:53:07.904547 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8971 19:53:07.907930 version: 01 04
8972 19:53:07.911058 basic params: 95 1f 11 78 0a
8973 19:53:07.914288 chroma info: 76 90 94 55 54 90 27 21 50 54
8974 19:53:07.917698 established: 00 00 00
8975 19:53:07.924153 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8976 19:53:07.927854 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8977 19:53:07.934168 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8978 19:53:07.940763 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8979 19:53:07.947307 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8980 19:53:07.950602 extensions: 00
8981 19:53:07.950683 checksum: fb
8982 19:53:07.950748
8983 19:53:07.954285 Manufacturer: IVO Model 57d Serial Number 0
8984 19:53:07.957343 Made week 0 of 2020
8985 19:53:07.957424 EDID version: 1.4
8986 19:53:07.960488 Digital display
8987 19:53:07.963846 6 bits per primary color channel
8988 19:53:07.963928 DisplayPort interface
8989 19:53:07.967166 Maximum image size: 31 cm x 17 cm
8990 19:53:07.970357 Gamma: 220%
8991 19:53:07.970439 Check DPMS levels
8992 19:53:07.973698 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
8993 19:53:07.980492 First detailed timing is preferred timing
8994 19:53:07.980574 Established timings supported:
8995 19:53:07.983639 Standard timings supported:
8996 19:53:07.987144 Detailed timings
8997 19:53:07.990614 Hex of detail: 383680a07038204018303c0035ae10000019
8998 19:53:07.996947 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
8999 19:53:08.000333 0780 0798 07c8 0820 hborder 0
9000 19:53:08.003451 0438 043b 0447 0458 vborder 0
9001 19:53:08.006928 -hsync -vsync
9002 19:53:08.007010 Did detailed timing
9003 19:53:08.013569 Hex of detail: 000000000000000000000000000000000000
9004 19:53:08.016638 Manufacturer-specified data, tag 0
9005 19:53:08.020204 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9006 19:53:08.023322 ASCII string: InfoVision
9007 19:53:08.026926 Hex of detail: 000000fe00523134304e574635205248200a
9008 19:53:08.030085 ASCII string: R140NWF5 RH
9009 19:53:08.030167 Checksum
9010 19:53:08.033356 Checksum: 0xfb (valid)
9011 19:53:08.036917 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9012 19:53:08.040014 DSI data_rate: 832800000 bps
9013 19:53:08.046376 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9014 19:53:08.049893 anx7625_parse_edid: pixelclock(138800).
9015 19:53:08.053351 hactive(1920), hsync(48), hfp(24), hbp(88)
9016 19:53:08.056389 vactive(1080), vsync(12), vfp(3), vbp(17)
9017 19:53:08.059669 anx7625_dsi_config: config dsi.
9018 19:53:08.066338 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9019 19:53:08.079781 anx7625_dsi_config: success to config DSI
9020 19:53:08.083322 anx7625_dp_start: MIPI phy setup OK.
9021 19:53:08.086505 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9022 19:53:08.089878 mtk_ddp_mode_set invalid vrefresh 60
9023 19:53:08.093259 main_disp_path_setup
9024 19:53:08.093339 ovl_layer_smi_id_en
9025 19:53:08.096580 ovl_layer_smi_id_en
9026 19:53:08.096661 ccorr_config
9027 19:53:08.096724 aal_config
9028 19:53:08.099747 gamma_config
9029 19:53:08.099827 postmask_config
9030 19:53:08.103091 dither_config
9031 19:53:08.106768 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9032 19:53:08.113162 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9033 19:53:08.116167 Root Device init finished in 552 msecs
9034 19:53:08.119810 CPU_CLUSTER: 0 init
9035 19:53:08.126236 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9036 19:53:08.129439 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9037 19:53:08.132937 APU_MBOX 0x190000b0 = 0x10001
9038 19:53:08.136231 APU_MBOX 0x190001b0 = 0x10001
9039 19:53:08.139554 APU_MBOX 0x190005b0 = 0x10001
9040 19:53:08.142649 APU_MBOX 0x190006b0 = 0x10001
9041 19:53:08.149079 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9042 19:53:08.158742 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9043 19:53:08.171442 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9044 19:53:08.177877 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9045 19:53:08.189423 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9046 19:53:08.198494 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9047 19:53:08.201947 CPU_CLUSTER: 0 init finished in 81 msecs
9048 19:53:08.205194 Devices initialized
9049 19:53:08.208572 Show all devs... After init.
9050 19:53:08.208652 Root Device: enabled 1
9051 19:53:08.211966 CPU_CLUSTER: 0: enabled 1
9052 19:53:08.215281 CPU: 00: enabled 1
9053 19:53:08.218399 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9054 19:53:08.221959 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9055 19:53:08.224934 ELOG: NV offset 0x57f000 size 0x1000
9056 19:53:08.231908 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9057 19:53:08.238298 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9058 19:53:08.241739 ELOG: Event(17) added with size 13 at 2023-10-28 19:53:09 UTC
9059 19:53:08.245252 out: cmd=0x121: 03 db 21 01 00 00 00 00
9060 19:53:08.248903 in-header: 03 1d 00 00 2c 00 00 00
9061 19:53:08.262166 in-data: 46 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9062 19:53:08.269042 ELOG: Event(A1) added with size 10 at 2023-10-28 19:53:09 UTC
9063 19:53:08.275562 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9064 19:53:08.282576 ELOG: Event(A0) added with size 9 at 2023-10-28 19:53:09 UTC
9065 19:53:08.285729 elog_add_boot_reason: Logged dev mode boot
9066 19:53:08.289036 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9067 19:53:08.292166 Finalize devices...
9068 19:53:08.292276 Devices finalized
9069 19:53:08.298958 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9070 19:53:08.302325 Writing coreboot table at 0xffe64000
9071 19:53:08.305573 0. 000000000010a000-0000000000113fff: RAMSTAGE
9072 19:53:08.308795 1. 0000000040000000-00000000400fffff: RAM
9073 19:53:08.312365 2. 0000000040100000-000000004032afff: RAMSTAGE
9074 19:53:08.318926 3. 000000004032b000-00000000545fffff: RAM
9075 19:53:08.322180 4. 0000000054600000-000000005465ffff: BL31
9076 19:53:08.325646 5. 0000000054660000-00000000ffe63fff: RAM
9077 19:53:08.332088 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9078 19:53:08.335300 7. 0000000100000000-000000013fffffff: RAM
9079 19:53:08.335384 Passing 5 GPIOs to payload:
9080 19:53:08.342467 NAME | PORT | POLARITY | VALUE
9081 19:53:08.345461 EC in RW | 0x000000aa | low | undefined
9082 19:53:08.351962 EC interrupt | 0x00000005 | low | undefined
9083 19:53:08.355498 TPM interrupt | 0x000000ab | high | undefined
9084 19:53:08.358582 SD card detect | 0x00000011 | high | undefined
9085 19:53:08.365538 speaker enable | 0x00000093 | high | undefined
9086 19:53:08.368910 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9087 19:53:08.372054 in-header: 03 f4 00 00 02 00 00 00
9088 19:53:08.372135 in-data: 07 00
9089 19:53:08.375612 ADC[4]: Raw value=668222 ID=5
9090 19:53:08.378418 ADC[3]: Raw value=212549 ID=1
9091 19:53:08.378499 RAM Code: 0x51
9092 19:53:08.381899 ADC[6]: Raw value=74778 ID=0
9093 19:53:08.385127 ADC[5]: Raw value=211444 ID=1
9094 19:53:08.385210 SKU Code: 0x1
9095 19:53:08.391605 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3414
9096 19:53:08.394997 coreboot table: 964 bytes.
9097 19:53:08.398249 IMD ROOT 0. 0xfffff000 0x00001000
9098 19:53:08.401657 IMD SMALL 1. 0xffffe000 0x00001000
9099 19:53:08.405210 RO MCACHE 2. 0xffffc000 0x00001104
9100 19:53:08.408216 CONSOLE 3. 0xfff7c000 0x00080000
9101 19:53:08.411594 FMAP 4. 0xfff7b000 0x00000452
9102 19:53:08.415054 TIME STAMP 5. 0xfff7a000 0x00000910
9103 19:53:08.418063 VBOOT WORK 6. 0xfff66000 0x00014000
9104 19:53:08.421596 RAMOOPS 7. 0xffe66000 0x00100000
9105 19:53:08.424744 COREBOOT 8. 0xffe64000 0x00002000
9106 19:53:08.424825 IMD small region:
9107 19:53:08.428079 IMD ROOT 0. 0xffffec00 0x00000400
9108 19:53:08.431289 VPD 1. 0xffffeb80 0x0000006c
9109 19:53:08.434938 MMC STATUS 2. 0xffffeb60 0x00000004
9110 19:53:08.441446 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9111 19:53:08.444825 Probing TPM: done!
9112 19:53:08.448084 Connected to device vid:did:rid of 1ae0:0028:00
9113 19:53:08.458190 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9114 19:53:08.461414 Initialized TPM device CR50 revision 0
9115 19:53:08.465300 Checking cr50 for pending updates
9116 19:53:08.468753 Reading cr50 TPM mode
9117 19:53:08.476859 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9118 19:53:08.483667 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9119 19:53:08.523562 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9120 19:53:08.527335 Checking segment from ROM address 0x40100000
9121 19:53:08.530536 Checking segment from ROM address 0x4010001c
9122 19:53:08.536881 Loading segment from ROM address 0x40100000
9123 19:53:08.536962 code (compression=0)
9124 19:53:08.546973 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9125 19:53:08.553577 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9126 19:53:08.553659 it's not compressed!
9127 19:53:08.560335 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9128 19:53:08.563874 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9129 19:53:08.584040 Loading segment from ROM address 0x4010001c
9130 19:53:08.584122 Entry Point 0x80000000
9131 19:53:08.587475 Loaded segments
9132 19:53:08.590597 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9133 19:53:08.597256 Jumping to boot code at 0x80000000(0xffe64000)
9134 19:53:08.604054 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9135 19:53:08.610530 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9136 19:53:08.618622 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9137 19:53:08.621919 Checking segment from ROM address 0x40100000
9138 19:53:08.625092 Checking segment from ROM address 0x4010001c
9139 19:53:08.632208 Loading segment from ROM address 0x40100000
9140 19:53:08.632303 code (compression=1)
9141 19:53:08.638680 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9142 19:53:08.648678 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9143 19:53:08.648760 using LZMA
9144 19:53:08.656799 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9145 19:53:08.663609 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9146 19:53:08.666852 Loading segment from ROM address 0x4010001c
9147 19:53:08.666933 Entry Point 0x54601000
9148 19:53:08.670235 Loaded segments
9149 19:53:08.673592 NOTICE: MT8192 bl31_setup
9150 19:53:08.680514 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9151 19:53:08.683729 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9152 19:53:08.687187 WARNING: region 0:
9153 19:53:08.690483 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9154 19:53:08.690565 WARNING: region 1:
9155 19:53:08.697144 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9156 19:53:08.700678 WARNING: region 2:
9157 19:53:08.703584 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9158 19:53:08.707162 WARNING: region 3:
9159 19:53:08.710547 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9160 19:53:08.713903 WARNING: region 4:
9161 19:53:08.720687 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9162 19:53:08.720769 WARNING: region 5:
9163 19:53:08.723967 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9164 19:53:08.727050 WARNING: region 6:
9165 19:53:08.730754 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9166 19:53:08.730836 WARNING: region 7:
9167 19:53:08.737183 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9168 19:53:08.744005 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9169 19:53:08.747201 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9170 19:53:08.750518 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9171 19:53:08.757074 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9172 19:53:08.760537 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9173 19:53:08.763816 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9174 19:53:08.770497 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9175 19:53:08.773819 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9176 19:53:08.780825 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9177 19:53:08.783910 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9178 19:53:08.787108 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9179 19:53:08.793744 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9180 19:53:08.797205 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9181 19:53:08.800931 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9182 19:53:08.807208 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9183 19:53:08.810566 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9184 19:53:08.813938 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9185 19:53:08.820591 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9186 19:53:08.823878 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9187 19:53:08.830539 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9188 19:53:08.834117 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9189 19:53:08.837493 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9190 19:53:08.843946 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9191 19:53:08.847338 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9192 19:53:08.853857 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9193 19:53:08.857147 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9194 19:53:08.860599 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9195 19:53:08.867399 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9196 19:53:08.870673 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9197 19:53:08.874050 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9198 19:53:08.880444 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9199 19:53:08.883938 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9200 19:53:08.887350 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9201 19:53:08.893881 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9202 19:53:08.897310 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9203 19:53:08.901090 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9204 19:53:08.903896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9205 19:53:08.910607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9206 19:53:08.913745 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9207 19:53:08.917168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9208 19:53:08.920707 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9209 19:53:08.927380 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9210 19:53:08.930426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9211 19:53:08.934139 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9212 19:53:08.937090 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9213 19:53:08.943831 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9214 19:53:08.947026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9215 19:53:08.950604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9216 19:53:08.957298 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9217 19:53:08.960516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9218 19:53:08.967030 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9219 19:53:08.970416 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9220 19:53:08.974454 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9221 19:53:08.980614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9222 19:53:08.984141 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9223 19:53:08.990468 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9224 19:53:08.993930 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9225 19:53:08.997585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9226 19:53:09.004048 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9227 19:53:09.006847 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9228 19:53:09.013828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9229 19:53:09.017301 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9230 19:53:09.023962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9231 19:53:09.027035 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9232 19:53:09.033866 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9233 19:53:09.037014 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9234 19:53:09.040568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9235 19:53:09.047055 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9236 19:53:09.050376 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9237 19:53:09.056982 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9238 19:53:09.060256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9239 19:53:09.067059 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9240 19:53:09.070623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9241 19:53:09.073611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9242 19:53:09.080519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9243 19:53:09.083555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9244 19:53:09.090541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9245 19:53:09.094271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9246 19:53:09.100509 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9247 19:53:09.103541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9248 19:53:09.110144 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9249 19:53:09.113456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9250 19:53:09.116897 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9251 19:53:09.123239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9252 19:53:09.126775 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9253 19:53:09.133386 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9254 19:53:09.136794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9255 19:53:09.143339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9256 19:53:09.147119 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9257 19:53:09.150140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9258 19:53:09.156949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9259 19:53:09.160583 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9260 19:53:09.167016 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9261 19:53:09.170083 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9262 19:53:09.176783 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9263 19:53:09.180404 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9264 19:53:09.183712 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9265 19:53:09.190228 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9266 19:53:09.193337 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9267 19:53:09.196810 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9268 19:53:09.200563 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9269 19:53:09.206793 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9270 19:53:09.209993 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9271 19:53:09.216751 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9272 19:53:09.219931 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9273 19:53:09.223700 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9274 19:53:09.230046 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9275 19:53:09.233461 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9276 19:53:09.240505 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9277 19:53:09.243486 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9278 19:53:09.246711 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9279 19:53:09.253299 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9280 19:53:09.257186 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9281 19:53:09.263372 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9282 19:53:09.266684 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9283 19:53:09.269879 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9284 19:53:09.273088 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9285 19:53:09.280070 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9286 19:53:09.283175 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9287 19:53:09.286833 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9288 19:53:09.293310 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9289 19:53:09.296627 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9290 19:53:09.300160 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9291 19:53:09.303303 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9292 19:53:09.309929 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9293 19:53:09.313148 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9294 19:53:09.319933 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9295 19:53:09.323466 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9296 19:53:09.326492 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9297 19:53:09.333179 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9298 19:53:09.336449 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9299 19:53:09.343198 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9300 19:53:09.346390 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9301 19:53:09.350001 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9302 19:53:09.356517 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9303 19:53:09.359685 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9304 19:53:09.366300 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9305 19:53:09.369664 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9306 19:53:09.373463 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9307 19:53:09.379710 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9308 19:53:09.382995 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9309 19:53:09.386332 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9310 19:53:09.393117 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9311 19:53:09.396537 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9312 19:53:09.402868 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9313 19:53:09.406444 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9314 19:53:09.409828 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9315 19:53:09.416286 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9316 19:53:09.419710 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9317 19:53:09.426269 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9318 19:53:09.429659 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9319 19:53:09.432928 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9320 19:53:09.440025 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9321 19:53:09.443189 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9322 19:53:09.446328 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9323 19:53:09.453147 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9324 19:53:09.456797 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9325 19:53:09.463153 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9326 19:53:09.466619 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9327 19:53:09.469942 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9328 19:53:09.476433 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9329 19:53:09.479796 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9330 19:53:09.483201 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9331 19:53:09.489925 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9332 19:53:09.493254 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9333 19:53:09.499935 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9334 19:53:09.502966 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9335 19:53:09.506368 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9336 19:53:09.513320 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9337 19:53:09.516131 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9338 19:53:09.522641 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9339 19:53:09.526067 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9340 19:53:09.529473 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9341 19:53:09.536090 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9342 19:53:09.539630 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9343 19:53:09.546554 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9344 19:53:09.549253 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9345 19:53:09.552783 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9346 19:53:09.559314 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9347 19:53:09.562692 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9348 19:53:09.569178 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9349 19:53:09.572649 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9350 19:53:09.575864 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9351 19:53:09.582382 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9352 19:53:09.585730 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9353 19:53:09.592581 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9354 19:53:09.596312 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9355 19:53:09.598999 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9356 19:53:09.605650 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9357 19:53:09.608767 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9358 19:53:09.615841 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9359 19:53:09.618970 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9360 19:53:09.622234 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9361 19:53:09.628793 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9362 19:53:09.632242 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9363 19:53:09.638973 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9364 19:53:09.642417 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9365 19:53:09.645870 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9366 19:53:09.652166 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9367 19:53:09.655543 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9368 19:53:09.662408 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9369 19:53:09.665619 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9370 19:53:09.672345 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9371 19:53:09.675501 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9372 19:53:09.678769 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9373 19:53:09.685320 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9374 19:53:09.688733 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9375 19:53:09.695272 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9376 19:53:09.698618 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9377 19:53:09.701971 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9378 19:53:09.708510 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9379 19:53:09.712129 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9380 19:53:09.718778 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9381 19:53:09.722035 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9382 19:53:09.728779 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9383 19:53:09.731750 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9384 19:53:09.735216 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9385 19:53:09.741830 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9386 19:53:09.745148 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9387 19:53:09.751763 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9388 19:53:09.755080 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9389 19:53:09.758579 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9390 19:53:09.764907 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9391 19:53:09.768244 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9392 19:53:09.775174 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9393 19:53:09.778229 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9394 19:53:09.784702 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9395 19:53:09.788078 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9396 19:53:09.791433 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9397 19:53:09.798059 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9398 19:53:09.801338 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9399 19:53:09.804579 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9400 19:53:09.808026 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9401 19:53:09.814733 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9402 19:53:09.817775 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9403 19:53:09.821113 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9404 19:53:09.827787 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9405 19:53:09.831337 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9406 19:53:09.834400 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9407 19:53:09.841364 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9408 19:53:09.844294 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9409 19:53:09.850896 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9410 19:53:09.854373 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9411 19:53:09.857743 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9412 19:53:09.864064 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9413 19:53:09.867726 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9414 19:53:09.870864 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9415 19:53:09.877571 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9416 19:53:09.880814 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9417 19:53:09.884425 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9418 19:53:09.890705 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9419 19:53:09.894026 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9420 19:53:09.900715 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9421 19:53:09.904351 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9422 19:53:09.907263 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9423 19:53:09.914014 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9424 19:53:09.917322 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9425 19:53:09.923718 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9426 19:53:09.927314 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9427 19:53:09.930404 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9428 19:53:09.937347 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9429 19:53:09.940237 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9430 19:53:09.943755 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9431 19:53:09.950397 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9432 19:53:09.953582 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9433 19:53:09.956855 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9434 19:53:09.963707 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9435 19:53:09.966807 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9436 19:53:09.973560 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9437 19:53:09.976702 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9438 19:53:09.979962 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9439 19:53:09.983298 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9440 19:53:09.987091 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9441 19:53:09.993146 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9442 19:53:09.996532 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9443 19:53:09.999859 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9444 19:53:10.003217 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9445 19:53:10.009978 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9446 19:53:10.013281 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9447 19:53:10.016433 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9448 19:53:10.023210 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9449 19:53:10.026465 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9450 19:53:10.029775 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9451 19:53:10.036279 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9452 19:53:10.039996 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9453 19:53:10.042866 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9454 19:53:10.049659 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9455 19:53:10.052806 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9456 19:53:10.059225 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9457 19:53:10.062880 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9458 19:53:10.069446 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9459 19:53:10.072906 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9460 19:53:10.075842 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9461 19:53:10.082837 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9462 19:53:10.086339 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9463 19:53:10.092472 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9464 19:53:10.095971 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9465 19:53:10.099049 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9466 19:53:10.106099 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9467 19:53:10.109185 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9468 19:53:10.116162 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9469 19:53:10.119264 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9470 19:53:10.122583 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9471 19:53:10.129396 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9472 19:53:10.132432 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9473 19:53:10.139063 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9474 19:53:10.142302 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9475 19:53:10.145588 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9476 19:53:10.152447 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9477 19:53:10.155502 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9478 19:53:10.162046 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9479 19:53:10.165585 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9480 19:53:10.172138 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9481 19:53:10.175554 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9482 19:53:10.178873 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9483 19:53:10.185531 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9484 19:53:10.189032 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9485 19:53:10.195393 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9486 19:53:10.198998 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9487 19:53:10.202276 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9488 19:53:10.208597 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9489 19:53:10.212020 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9490 19:53:10.218469 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9491 19:53:10.221884 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9492 19:53:10.225012 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9493 19:53:10.231725 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9494 19:53:10.234953 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9495 19:53:10.242228 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9496 19:53:10.245025 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9497 19:53:10.248643 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9498 19:53:10.254847 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9499 19:53:10.258168 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9500 19:53:10.264939 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9501 19:53:10.268046 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9502 19:53:10.274824 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9503 19:53:10.278144 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9504 19:53:10.281510 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9505 19:53:10.288339 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9506 19:53:10.291281 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9507 19:53:10.297950 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9508 19:53:10.301221 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9509 19:53:10.308153 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9510 19:53:10.311239 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9511 19:53:10.314753 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9512 19:53:10.321341 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9513 19:53:10.324777 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9514 19:53:10.331119 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9515 19:53:10.334319 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9516 19:53:10.337833 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9517 19:53:10.344367 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9518 19:53:10.347622 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9519 19:53:10.354132 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9520 19:53:10.357459 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9521 19:53:10.361076 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9522 19:53:10.367594 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9523 19:53:10.370904 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9524 19:53:10.377452 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9525 19:53:10.380815 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9526 19:53:10.387423 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9527 19:53:10.390505 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9528 19:53:10.397240 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9529 19:53:10.400557 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9530 19:53:10.403751 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9531 19:53:10.410525 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9532 19:53:10.413623 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9533 19:53:10.420241 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9534 19:53:10.423617 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9535 19:53:10.430391 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9536 19:53:10.433869 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9537 19:53:10.436881 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9538 19:53:10.443654 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9539 19:53:10.446680 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9540 19:53:10.453785 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9541 19:53:10.456793 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9542 19:53:10.463681 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9543 19:53:10.467144 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9544 19:53:10.473538 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9545 19:53:10.476970 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9546 19:53:10.479948 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9547 19:53:10.486727 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9548 19:53:10.490349 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9549 19:53:10.496608 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9550 19:53:10.499919 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9551 19:53:10.506751 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9552 19:53:10.509961 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9553 19:53:10.513501 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9554 19:53:10.519872 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9555 19:53:10.523146 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9556 19:53:10.529848 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9557 19:53:10.533152 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9558 19:53:10.539933 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9559 19:53:10.543042 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9560 19:53:10.549751 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9561 19:53:10.552933 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9562 19:53:10.556152 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9563 19:53:10.563118 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9564 19:53:10.566508 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9565 19:53:10.572892 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9566 19:53:10.576101 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9567 19:53:10.583125 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9568 19:53:10.586101 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9569 19:53:10.589563 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9570 19:53:10.595979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9571 19:53:10.599306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9572 19:53:10.605862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9573 19:53:10.609282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9574 19:53:10.615744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9575 19:53:10.619153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9576 19:53:10.625670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9577 19:53:10.628942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9578 19:53:10.635596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9579 19:53:10.638996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9580 19:53:10.645866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9581 19:53:10.649006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9582 19:53:10.652115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9583 19:53:10.658577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9584 19:53:10.665196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9585 19:53:10.668465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9586 19:53:10.675116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9587 19:53:10.678500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9588 19:53:10.681909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9589 19:53:10.688493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9590 19:53:10.691631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9591 19:53:10.698238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9592 19:53:10.701504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9593 19:53:10.708068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9594 19:53:10.714627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9595 19:53:10.718151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9596 19:53:10.724551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9597 19:53:10.727988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9598 19:53:10.734730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9599 19:53:10.737802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9600 19:53:10.744464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9601 19:53:10.748091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9602 19:53:10.750935 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9603 19:53:10.754553 INFO: [APUAPC] vio 0
9604 19:53:10.760938 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9605 19:53:10.764438 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9606 19:53:10.767602 INFO: [APUAPC] D0_APC_0: 0x400510
9607 19:53:10.770784 INFO: [APUAPC] D0_APC_1: 0x0
9608 19:53:10.774338 INFO: [APUAPC] D0_APC_2: 0x1540
9609 19:53:10.777394 INFO: [APUAPC] D0_APC_3: 0x0
9610 19:53:10.780830 INFO: [APUAPC] D1_APC_0: 0xffffffff
9611 19:53:10.784126 INFO: [APUAPC] D1_APC_1: 0xffffffff
9612 19:53:10.787565 INFO: [APUAPC] D1_APC_2: 0x3fffff
9613 19:53:10.787644 INFO: [APUAPC] D1_APC_3: 0x0
9614 19:53:10.794286 INFO: [APUAPC] D2_APC_0: 0xffffffff
9615 19:53:10.797345 INFO: [APUAPC] D2_APC_1: 0xffffffff
9616 19:53:10.800605 INFO: [APUAPC] D2_APC_2: 0x3fffff
9617 19:53:10.800683 INFO: [APUAPC] D2_APC_3: 0x0
9618 19:53:10.803913 INFO: [APUAPC] D3_APC_0: 0xffffffff
9619 19:53:10.810885 INFO: [APUAPC] D3_APC_1: 0xffffffff
9620 19:53:10.813687 INFO: [APUAPC] D3_APC_2: 0x3fffff
9621 19:53:10.813766 INFO: [APUAPC] D3_APC_3: 0x0
9622 19:53:10.817152 INFO: [APUAPC] D4_APC_0: 0xffffffff
9623 19:53:10.820737 INFO: [APUAPC] D4_APC_1: 0xffffffff
9624 19:53:10.824193 INFO: [APUAPC] D4_APC_2: 0x3fffff
9625 19:53:10.827055 INFO: [APUAPC] D4_APC_3: 0x0
9626 19:53:10.830514 INFO: [APUAPC] D5_APC_0: 0xffffffff
9627 19:53:10.833829 INFO: [APUAPC] D5_APC_1: 0xffffffff
9628 19:53:10.836953 INFO: [APUAPC] D5_APC_2: 0x3fffff
9629 19:53:10.840393 INFO: [APUAPC] D5_APC_3: 0x0
9630 19:53:10.843476 INFO: [APUAPC] D6_APC_0: 0xffffffff
9631 19:53:10.847013 INFO: [APUAPC] D6_APC_1: 0xffffffff
9632 19:53:10.850261 INFO: [APUAPC] D6_APC_2: 0x3fffff
9633 19:53:10.853599 INFO: [APUAPC] D6_APC_3: 0x0
9634 19:53:10.856967 INFO: [APUAPC] D7_APC_0: 0xffffffff
9635 19:53:10.860421 INFO: [APUAPC] D7_APC_1: 0xffffffff
9636 19:53:10.863435 INFO: [APUAPC] D7_APC_2: 0x3fffff
9637 19:53:10.866956 INFO: [APUAPC] D7_APC_3: 0x0
9638 19:53:10.870135 INFO: [APUAPC] D8_APC_0: 0xffffffff
9639 19:53:10.873435 INFO: [APUAPC] D8_APC_1: 0xffffffff
9640 19:53:10.876822 INFO: [APUAPC] D8_APC_2: 0x3fffff
9641 19:53:10.880090 INFO: [APUAPC] D8_APC_3: 0x0
9642 19:53:10.883247 INFO: [APUAPC] D9_APC_0: 0xffffffff
9643 19:53:10.887005 INFO: [APUAPC] D9_APC_1: 0xffffffff
9644 19:53:10.890023 INFO: [APUAPC] D9_APC_2: 0x3fffff
9645 19:53:10.893277 INFO: [APUAPC] D9_APC_3: 0x0
9646 19:53:10.897132 INFO: [APUAPC] D10_APC_0: 0xffffffff
9647 19:53:10.899994 INFO: [APUAPC] D10_APC_1: 0xffffffff
9648 19:53:10.903096 INFO: [APUAPC] D10_APC_2: 0x3fffff
9649 19:53:10.906469 INFO: [APUAPC] D10_APC_3: 0x0
9650 19:53:10.910064 INFO: [APUAPC] D11_APC_0: 0xffffffff
9651 19:53:10.913029 INFO: [APUAPC] D11_APC_1: 0xffffffff
9652 19:53:10.916579 INFO: [APUAPC] D11_APC_2: 0x3fffff
9653 19:53:10.919789 INFO: [APUAPC] D11_APC_3: 0x0
9654 19:53:10.923212 INFO: [APUAPC] D12_APC_0: 0xffffffff
9655 19:53:10.926106 INFO: [APUAPC] D12_APC_1: 0xffffffff
9656 19:53:10.929560 INFO: [APUAPC] D12_APC_2: 0x3fffff
9657 19:53:10.932904 INFO: [APUAPC] D12_APC_3: 0x0
9658 19:53:10.936343 INFO: [APUAPC] D13_APC_0: 0xffffffff
9659 19:53:10.939508 INFO: [APUAPC] D13_APC_1: 0xffffffff
9660 19:53:10.942707 INFO: [APUAPC] D13_APC_2: 0x3fffff
9661 19:53:10.946274 INFO: [APUAPC] D13_APC_3: 0x0
9662 19:53:10.949449 INFO: [APUAPC] D14_APC_0: 0xffffffff
9663 19:53:10.952958 INFO: [APUAPC] D14_APC_1: 0xffffffff
9664 19:53:10.956032 INFO: [APUAPC] D14_APC_2: 0x3fffff
9665 19:53:10.959359 INFO: [APUAPC] D14_APC_3: 0x0
9666 19:53:10.962778 INFO: [APUAPC] D15_APC_0: 0xffffffff
9667 19:53:10.966198 INFO: [APUAPC] D15_APC_1: 0xffffffff
9668 19:53:10.969669 INFO: [APUAPC] D15_APC_2: 0x3fffff
9669 19:53:10.972483 INFO: [APUAPC] D15_APC_3: 0x0
9670 19:53:10.975701 INFO: [APUAPC] APC_CON: 0x4
9671 19:53:10.979300 INFO: [NOCDAPC] D0_APC_0: 0x0
9672 19:53:10.982307 INFO: [NOCDAPC] D0_APC_1: 0x0
9673 19:53:10.985769 INFO: [NOCDAPC] D1_APC_0: 0x0
9674 19:53:10.989154 INFO: [NOCDAPC] D1_APC_1: 0xfff
9675 19:53:10.992401 INFO: [NOCDAPC] D2_APC_0: 0x0
9676 19:53:10.992481 INFO: [NOCDAPC] D2_APC_1: 0xfff
9677 19:53:10.995483 INFO: [NOCDAPC] D3_APC_0: 0x0
9678 19:53:10.998881 INFO: [NOCDAPC] D3_APC_1: 0xfff
9679 19:53:11.002262 INFO: [NOCDAPC] D4_APC_0: 0x0
9680 19:53:11.005765 INFO: [NOCDAPC] D4_APC_1: 0xfff
9681 19:53:11.008854 INFO: [NOCDAPC] D5_APC_0: 0x0
9682 19:53:11.012030 INFO: [NOCDAPC] D5_APC_1: 0xfff
9683 19:53:11.015530 INFO: [NOCDAPC] D6_APC_0: 0x0
9684 19:53:11.018702 INFO: [NOCDAPC] D6_APC_1: 0xfff
9685 19:53:11.022183 INFO: [NOCDAPC] D7_APC_0: 0x0
9686 19:53:11.025400 INFO: [NOCDAPC] D7_APC_1: 0xfff
9687 19:53:11.028896 INFO: [NOCDAPC] D8_APC_0: 0x0
9688 19:53:11.028976 INFO: [NOCDAPC] D8_APC_1: 0xfff
9689 19:53:11.032202 INFO: [NOCDAPC] D9_APC_0: 0x0
9690 19:53:11.035474 INFO: [NOCDAPC] D9_APC_1: 0xfff
9691 19:53:11.038985 INFO: [NOCDAPC] D10_APC_0: 0x0
9692 19:53:11.042014 INFO: [NOCDAPC] D10_APC_1: 0xfff
9693 19:53:11.045370 INFO: [NOCDAPC] D11_APC_0: 0x0
9694 19:53:11.048787 INFO: [NOCDAPC] D11_APC_1: 0xfff
9695 19:53:11.052469 INFO: [NOCDAPC] D12_APC_0: 0x0
9696 19:53:11.055066 INFO: [NOCDAPC] D12_APC_1: 0xfff
9697 19:53:11.058351 INFO: [NOCDAPC] D13_APC_0: 0x0
9698 19:53:11.061628 INFO: [NOCDAPC] D13_APC_1: 0xfff
9699 19:53:11.065361 INFO: [NOCDAPC] D14_APC_0: 0x0
9700 19:53:11.068274 INFO: [NOCDAPC] D14_APC_1: 0xfff
9701 19:53:11.071756 INFO: [NOCDAPC] D15_APC_0: 0x0
9702 19:53:11.075293 INFO: [NOCDAPC] D15_APC_1: 0xfff
9703 19:53:11.075373 INFO: [NOCDAPC] APC_CON: 0x4
9704 19:53:11.078137 INFO: [APUAPC] set_apusys_apc done
9705 19:53:11.081518 INFO: [DEVAPC] devapc_init done
9706 19:53:11.088152 INFO: GICv3 without legacy support detected.
9707 19:53:11.091294 INFO: ARM GICv3 driver initialized in EL3
9708 19:53:11.094749 INFO: Maximum SPI INTID supported: 639
9709 19:53:11.098413 INFO: BL31: Initializing runtime services
9710 19:53:11.104835 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9711 19:53:11.108106 INFO: SPM: enable CPC mode
9712 19:53:11.111423 INFO: mcdi ready for mcusys-off-idle and system suspend
9713 19:53:11.118100 INFO: BL31: Preparing for EL3 exit to normal world
9714 19:53:11.121672 INFO: Entry point address = 0x80000000
9715 19:53:11.121752 INFO: SPSR = 0x8
9716 19:53:11.128191
9717 19:53:11.128271
9718 19:53:11.128334
9719 19:53:11.131508 Starting depthcharge on Spherion...
9720 19:53:11.131587
9721 19:53:11.131651 Wipe memory regions:
9722 19:53:11.131710
9723 19:53:11.132360 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9724 19:53:11.132457 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9725 19:53:11.132538 Setting prompt string to ['asurada:']
9726 19:53:11.132618 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9727 19:53:11.134776 [0x00000040000000, 0x00000054600000)
9728 19:53:11.257646
9729 19:53:11.257748 [0x00000054660000, 0x00000080000000)
9730 19:53:11.517990
9731 19:53:11.518119 [0x000000821a7280, 0x000000ffe64000)
9732 19:53:12.263106
9733 19:53:12.263659 [0x00000100000000, 0x00000140000000)
9734 19:53:12.644501
9735 19:53:12.647513 Initializing XHCI USB controller at 0x11200000.
9736 19:53:13.685528
9737 19:53:13.688810 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9738 19:53:13.689280
9739 19:53:13.689679
9740 19:53:13.690263
9741 19:53:13.691165 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9743 19:53:13.792542 asurada: tftpboot 192.168.201.1 11899575/tftp-deploy-vq85ut5t/kernel/image.itb 11899575/tftp-deploy-vq85ut5t/kernel/cmdline
9744 19:53:13.793207 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9745 19:53:13.793748 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9746 19:53:13.798668 tftpboot 192.168.201.1 11899575/tftp-deploy-vq85ut5t/kernel/image.itp-deploy-vq85ut5t/kernel/cmdline
9747 19:53:13.799231
9748 19:53:13.799596 Waiting for link
9749 19:53:13.959128
9750 19:53:13.959679 R8152: Initializing
9751 19:53:13.960048
9752 19:53:13.962326 Version 9 (ocp_data = 6010)
9753 19:53:13.962910
9754 19:53:13.965506 R8152: Done initializing
9755 19:53:13.965967
9756 19:53:13.966338 Adding net device
9757 19:53:15.973121
9758 19:53:15.973722 done.
9759 19:53:15.974094
9760 19:53:15.974435 MAC: 00:e0:4c:68:03:bd
9761 19:53:15.974764
9762 19:53:15.976080 Sending DHCP discover... done.
9763 19:53:15.976703
9764 19:53:15.979064 Waiting for reply... done.
9765 19:53:15.979521
9766 19:53:15.982303 Sending DHCP request... done.
9767 19:53:15.982382
9768 19:53:15.987908 Waiting for reply... done.
9769 19:53:15.988061
9770 19:53:15.988133 My ip is 192.168.201.16
9771 19:53:15.988237
9772 19:53:15.991272 The DHCP server ip is 192.168.201.1
9773 19:53:15.991430
9774 19:53:15.997671 TFTP server IP predefined by user: 192.168.201.1
9775 19:53:15.997820
9776 19:53:16.004064 Bootfile predefined by user: 11899575/tftp-deploy-vq85ut5t/kernel/image.itb
9777 19:53:16.004266
9778 19:53:16.007655 Sending tftp read request... done.
9779 19:53:16.007762
9780 19:53:16.011493 Waiting for the transfer...
9781 19:53:16.011610
9782 19:53:16.317775 00000000 ################################################################
9783 19:53:16.317907
9784 19:53:16.620995 00080000 ################################################################
9785 19:53:16.621125
9786 19:53:16.935915 00100000 ################################################################
9787 19:53:16.936083
9788 19:53:17.268721 00180000 ################################################################
9789 19:53:17.268857
9790 19:53:17.569796 00200000 ################################################################
9791 19:53:17.569931
9792 19:53:17.873118 00280000 ################################################################
9793 19:53:17.873259
9794 19:53:18.154877 00300000 ################################################################
9795 19:53:18.155007
9796 19:53:18.449694 00380000 ################################################################
9797 19:53:18.449832
9798 19:53:18.753196 00400000 ################################################################
9799 19:53:18.753332
9800 19:53:19.057564 00480000 ################################################################
9801 19:53:19.057696
9802 19:53:19.450686 00500000 ################################################################
9803 19:53:19.451196
9804 19:53:19.779917 00580000 ################################################################
9805 19:53:19.780049
9806 19:53:20.082293 00600000 ################################################################
9807 19:53:20.082423
9808 19:53:20.377775 00680000 ################################################################
9809 19:53:20.377899
9810 19:53:20.682781 00700000 ################################################################
9811 19:53:20.682925
9812 19:53:20.987461 00780000 ################################################################
9813 19:53:20.987592
9814 19:53:21.290926 00800000 ################################################################
9815 19:53:21.291061
9816 19:53:21.595114 00880000 ################################################################
9817 19:53:21.595260
9818 19:53:21.898344 00900000 ################################################################
9819 19:53:21.898479
9820 19:53:22.198843 00980000 ################################################################
9821 19:53:22.198973
9822 19:53:22.576595 00a00000 ################################################################
9823 19:53:22.577089
9824 19:53:22.962538 00a80000 ################################################################
9825 19:53:22.963049
9826 19:53:23.335019 00b00000 ################################################################
9827 19:53:23.335521
9828 19:53:23.722727 00b80000 ################################################################
9829 19:53:23.723223
9830 19:53:24.038180 00c00000 ################################################################
9831 19:53:24.038320
9832 19:53:24.341894 00c80000 ################################################################
9833 19:53:24.342026
9834 19:53:24.645435 00d00000 ################################################################
9835 19:53:24.645563
9836 19:53:24.948555 00d80000 ################################################################
9837 19:53:24.948696
9838 19:53:25.251506 00e00000 ################################################################
9839 19:53:25.251637
9840 19:53:25.555030 00e80000 ################################################################
9841 19:53:25.555159
9842 19:53:25.857696 00f00000 ################################################################
9843 19:53:25.857830
9844 19:53:26.161074 00f80000 ################################################################
9845 19:53:26.161214
9846 19:53:26.464859 01000000 ################################################################
9847 19:53:26.464995
9848 19:53:26.764281 01080000 ################################################################
9849 19:53:26.764416
9850 19:53:27.050959 01100000 ################################################################
9851 19:53:27.051090
9852 19:53:27.338585 01180000 ################################################################
9853 19:53:27.338729
9854 19:53:27.642855 01200000 ################################################################
9855 19:53:27.642988
9856 19:53:27.945160 01280000 ################################################################
9857 19:53:27.945296
9858 19:53:28.247243 01300000 ################################################################
9859 19:53:28.247382
9860 19:53:28.548866 01380000 ################################################################
9861 19:53:28.548991
9862 19:53:28.837574 01400000 ################################################################
9863 19:53:28.837735
9864 19:53:29.125938 01480000 ################################################################
9865 19:53:29.126072
9866 19:53:29.420924 01500000 ################################################################
9867 19:53:29.421090
9868 19:53:29.697189 01580000 ################################################################
9869 19:53:29.697322
9870 19:53:29.951475 01600000 ################################################################
9871 19:53:29.951615
9872 19:53:30.246803 01680000 ################################################################
9873 19:53:30.246934
9874 19:53:30.539852 01700000 ################################################################
9875 19:53:30.539984
9876 19:53:30.833478 01780000 ################################################################
9877 19:53:30.833617
9878 19:53:31.134419 01800000 ################################################################
9879 19:53:31.134561
9880 19:53:31.437147 01880000 ################################################################
9881 19:53:31.437278
9882 19:53:31.740079 01900000 ################################################################
9883 19:53:31.740273
9884 19:53:32.043736 01980000 ################################################################
9885 19:53:32.043876
9886 19:53:32.362685 01a00000 ################################################################
9887 19:53:32.362824
9888 19:53:32.681301 01a80000 ################################################################
9889 19:53:32.681442
9890 19:53:32.976675 01b00000 ################################################################
9891 19:53:32.976802
9892 19:53:33.260908 01b80000 ################################################################
9893 19:53:33.261045
9894 19:53:33.545541 01c00000 ################################################################
9895 19:53:33.545681
9896 19:53:33.807102 01c80000 ################################################################
9897 19:53:33.807252
9898 19:53:34.098773 01d00000 ################################################################
9899 19:53:34.098897
9900 19:53:34.400692 01d80000 ################################################################
9901 19:53:34.400821
9902 19:53:34.706289 01e00000 ################################################################
9903 19:53:34.706419
9904 19:53:35.007731 01e80000 ################################################################
9905 19:53:35.007860
9906 19:53:35.299454 01f00000 ################################################################
9907 19:53:35.299599
9908 19:53:35.578956 01f80000 ################################################################
9909 19:53:35.579104
9910 19:53:35.869483 02000000 ################################################################
9911 19:53:35.869632
9912 19:53:36.150711 02080000 ################################################################
9913 19:53:36.150857
9914 19:53:36.427790 02100000 ################################################################
9915 19:53:36.427934
9916 19:53:36.718153 02180000 ################################################################
9917 19:53:36.718283
9918 19:53:37.000267 02200000 ################################################################
9919 19:53:37.000399
9920 19:53:37.292614 02280000 ################################################################
9921 19:53:37.292745
9922 19:53:37.567202 02300000 ################################################################
9923 19:53:37.567342
9924 19:53:37.830967 02380000 ################################################################
9925 19:53:37.831097
9926 19:53:38.133817 02400000 ################################################################
9927 19:53:38.133949
9928 19:53:38.448908 02480000 ################################################################
9929 19:53:38.449049
9930 19:53:38.761070 02500000 ################################################################
9931 19:53:38.761236
9932 19:53:39.075950 02580000 ################################################################
9933 19:53:39.076092
9934 19:53:39.376124 02600000 ################################################################
9935 19:53:39.376263
9936 19:53:39.684133 02680000 ################################################################
9937 19:53:39.684283
9938 19:53:39.989971 02700000 ################################################################
9939 19:53:39.990105
9940 19:53:40.287318 02780000 ################################################################
9941 19:53:40.287484
9942 19:53:40.591230 02800000 ################################################################
9943 19:53:40.591360
9944 19:53:40.894015 02880000 ################################################################
9945 19:53:40.894147
9946 19:53:41.184473 02900000 ################################################################
9947 19:53:41.184603
9948 19:53:41.488634 02980000 ################################################################
9949 19:53:41.488765
9950 19:53:41.793466 02a00000 ################################################################
9951 19:53:41.793659
9952 19:53:42.088801 02a80000 ################################################################
9953 19:53:42.088935
9954 19:53:42.385609 02b00000 ################################################################
9955 19:53:42.385737
9956 19:53:42.686191 02b80000 ################################################################
9957 19:53:42.686322
9958 19:53:42.987436 02c00000 ################################################################
9959 19:53:42.987563
9960 19:53:43.291820 02c80000 ################################################################
9961 19:53:43.291958
9962 19:53:43.592539 02d00000 ################################################################
9963 19:53:43.592674
9964 19:53:43.881825 02d80000 ################################################################
9965 19:53:43.881976
9966 19:53:44.164548 02e00000 ################################################################
9967 19:53:44.164686
9968 19:53:44.410136 02e80000 ################################################################
9969 19:53:44.410273
9970 19:53:44.656339 02f00000 ################################################################
9971 19:53:44.656482
9972 19:53:44.903190 02f80000 ################################################################
9973 19:53:44.903330
9974 19:53:45.148890 03000000 ################################################################
9975 19:53:45.149038
9976 19:53:45.420965 03080000 ################################################################
9977 19:53:45.421106
9978 19:53:45.690515 03100000 ################################################################
9979 19:53:45.690656
9980 19:53:45.951203 03180000 ################################################################
9981 19:53:45.951345
9982 19:53:46.237573 03200000 ################################################################
9983 19:53:46.237713
9984 19:53:46.502177 03280000 ################################################################
9985 19:53:46.502321
9986 19:53:46.759881 03300000 ################################################################
9987 19:53:46.760049
9988 19:53:47.008572 03380000 ################################################################
9989 19:53:47.008717
9990 19:53:47.254979 03400000 ################################################################
9991 19:53:47.255118
9992 19:53:47.534528 03480000 ################################################################
9993 19:53:47.534669
9994 19:53:47.819288 03500000 ################################################################
9995 19:53:47.819433
9996 19:53:48.082904 03580000 ################################################################
9997 19:53:48.083051
9998 19:53:48.340566 03600000 ################################################################
9999 19:53:48.340711
10000 19:53:48.629346 03680000 ################################################################
10001 19:53:48.629482
10002 19:53:48.928014 03700000 ################################################################
10003 19:53:48.928187
10004 19:53:49.225388 03780000 ################################################################
10005 19:53:49.225528
10006 19:53:49.521773 03800000 ################################################################
10007 19:53:49.521914
10008 19:53:49.781504 03880000 ################################################################
10009 19:53:49.781633
10010 19:53:50.038708 03900000 ################################################################
10011 19:53:50.038845
10012 19:53:50.329745 03980000 ################################################################
10013 19:53:50.329883
10014 19:53:50.625199 03a00000 ################################################################
10015 19:53:50.625345
10016 19:53:50.922564 03a80000 ################################################################
10017 19:53:50.922700
10018 19:53:51.223152 03b00000 ################################################################
10019 19:53:51.223292
10020 19:53:51.504212 03b80000 ################################################################
10021 19:53:51.504348
10022 19:53:51.778914 03c00000 ################################################################
10023 19:53:51.779044
10024 19:53:52.065256 03c80000 ################################################################
10025 19:53:52.065384
10026 19:53:52.353431 03d00000 ################################################################
10027 19:53:52.353563
10028 19:53:52.643026 03d80000 ################################################################
10029 19:53:52.643157
10030 19:53:52.936290 03e00000 ################################################################
10031 19:53:52.936427
10032 19:53:53.238598 03e80000 ################################################################
10033 19:53:53.238758
10034 19:53:53.540032 03f00000 ################################################################
10035 19:53:53.540187
10036 19:53:53.844978 03f80000 ################################################################
10037 19:53:53.845124
10038 19:53:54.146081 04000000 ################################################################
10039 19:53:54.146230
10040 19:53:54.446871 04080000 ################################################################
10041 19:53:54.447022
10042 19:53:54.750157 04100000 ################################################################
10043 19:53:54.750295
10044 19:53:55.042351 04180000 ################################################################
10045 19:53:55.042494
10046 19:53:55.331271 04200000 ################################################################
10047 19:53:55.331398
10048 19:53:55.627487 04280000 ################################################################
10049 19:53:55.627620
10050 19:53:55.926654 04300000 ################################################################
10051 19:53:55.926784
10052 19:53:56.230890 04380000 ################################################################
10053 19:53:56.231024
10054 19:53:56.524020 04400000 ################################################################
10055 19:53:56.524151
10056 19:53:56.819789 04480000 ################################################################
10057 19:53:56.819932
10058 19:53:57.117820 04500000 ################################################################
10059 19:53:57.117980
10060 19:53:57.419321 04580000 ################################################################
10061 19:53:57.419455
10062 19:53:57.722957 04600000 ################################################################
10063 19:53:57.723104
10064 19:53:58.008833 04680000 ################################################################
10065 19:53:58.008965
10066 19:53:58.307963 04700000 ################################################################
10067 19:53:58.308096
10068 19:53:58.606192 04780000 ################################################################
10069 19:53:58.606326
10070 19:53:58.903471 04800000 ################################################################
10071 19:53:58.903617
10072 19:53:59.203947 04880000 ################################################################
10073 19:53:59.204106
10074 19:53:59.504969 04900000 ################################################################
10075 19:53:59.505102
10076 19:53:59.806347 04980000 ################################################################
10077 19:53:59.806490
10078 19:54:00.105031 04a00000 ################################################################
10079 19:54:00.105172
10080 19:54:00.408114 04a80000 ################################################################
10081 19:54:00.408254
10082 19:54:00.711714 04b00000 ################################################################
10083 19:54:00.711840
10084 19:54:01.015644 04b80000 ################################################################
10085 19:54:01.015778
10086 19:54:01.317795 04c00000 ################################################################
10087 19:54:01.317925
10088 19:54:01.609863 04c80000 ################################################################
10089 19:54:01.609994
10090 19:54:01.889261 04d00000 ################################################################
10091 19:54:01.889400
10092 19:54:02.149562 04d80000 ################################################################
10093 19:54:02.149721
10094 19:54:02.400428 04e00000 ################################################################
10095 19:54:02.400563
10096 19:54:02.667148 04e80000 ################################################################
10097 19:54:02.667274
10098 19:54:02.948555 04f00000 ################################################################
10099 19:54:02.948687
10100 19:54:03.242123 04f80000 ################################################################
10101 19:54:03.242258
10102 19:54:03.539036 05000000 ################################################################
10103 19:54:03.539169
10104 19:54:03.838212 05080000 ################################################################
10105 19:54:03.838349
10106 19:54:04.139154 05100000 ################################################################
10107 19:54:04.139284
10108 19:54:04.442559 05180000 ################################################################
10109 19:54:04.442703
10110 19:54:04.820292 05200000 ################################################################
10111 19:54:04.820829
10112 19:54:05.205263 05280000 ################################################################
10113 19:54:05.205806
10114 19:54:05.585200 05300000 ################################################################
10115 19:54:05.585738
10116 19:54:05.967319 05380000 ################################################################
10117 19:54:05.967852
10118 19:54:06.353689 05400000 ################################################################
10119 19:54:06.353825
10120 19:54:06.657409 05480000 ################################################################
10121 19:54:06.657544
10122 19:54:06.958234 05500000 ################################################################
10123 19:54:06.958365
10124 19:54:07.261529 05580000 ################################################################
10125 19:54:07.261658
10126 19:54:07.563376 05600000 ################################################################
10127 19:54:07.563552
10128 19:54:07.866055 05680000 ################################################################
10129 19:54:07.866188
10130 19:54:08.166121 05700000 ################################################################
10131 19:54:08.166258
10132 19:54:08.467325 05780000 ################################################################
10133 19:54:08.467457
10134 19:54:08.767189 05800000 ################################################################
10135 19:54:08.767324
10136 19:54:09.070955 05880000 ################################################################
10137 19:54:09.071086
10138 19:54:09.367509 05900000 ################################################################
10139 19:54:09.367640
10140 19:54:09.669935 05980000 ################################################################
10141 19:54:09.670073
10142 19:54:09.973882 05a00000 ################################################################
10143 19:54:09.974016
10144 19:54:10.277531 05a80000 ################################################################
10145 19:54:10.277660
10146 19:54:10.574511 05b00000 ################################################################
10147 19:54:10.574640
10148 19:54:10.895205 05b80000 ################################################################
10149 19:54:10.895727
10150 19:54:11.301109 05c00000 ################################################################
10151 19:54:11.301787
10152 19:54:11.695121 05c80000 ################################################################
10153 19:54:11.695647
10154 19:54:12.102043 05d00000 ################################################################
10155 19:54:12.102607
10156 19:54:12.463442 05d80000 ################################################################
10157 19:54:12.463573
10158 19:54:12.755846 05e00000 ################################################################
10159 19:54:12.755982
10160 19:54:13.058126 05e80000 ################################################################
10161 19:54:13.058260
10162 19:54:13.361776 05f00000 ################################################################
10163 19:54:13.361916
10164 19:54:13.665092 05f80000 ################################################################
10165 19:54:13.665224
10166 19:54:13.968605 06000000 ################################################################
10167 19:54:13.968737
10168 19:54:14.270955 06080000 ################################################################
10169 19:54:14.271093
10170 19:54:14.573938 06100000 ################################################################
10171 19:54:14.574069
10172 19:54:14.874529 06180000 ################################################################
10173 19:54:14.874664
10174 19:54:15.174579 06200000 ################################################################
10175 19:54:15.174709
10176 19:54:15.477586 06280000 ################################################################
10177 19:54:15.477721
10178 19:54:15.780476 06300000 ################################################################
10179 19:54:15.780608
10180 19:54:16.085024 06380000 ################################################################
10181 19:54:16.085154
10182 19:54:16.387802 06400000 ################################################################
10183 19:54:16.387934
10184 19:54:16.691293 06480000 ################################################################
10185 19:54:16.691426
10186 19:54:16.994592 06500000 ################################################################
10187 19:54:16.994726
10188 19:54:17.297263 06580000 ################################################################
10189 19:54:17.297394
10190 19:54:17.600709 06600000 ################################################################
10191 19:54:17.600844
10192 19:54:17.904103 06680000 ################################################################
10193 19:54:17.904276
10194 19:54:18.207369 06700000 ################################################################
10195 19:54:18.207511
10196 19:54:18.509709 06780000 ################################################################
10197 19:54:18.509837
10198 19:54:18.718243 06800000 ############################################# done.
10199 19:54:18.718369
10200 19:54:18.721643 The bootfile was 109415822 bytes long.
10201 19:54:18.721729
10202 19:54:18.724713 Sending tftp read request... done.
10203 19:54:18.724805
10204 19:54:18.728042 Waiting for the transfer...
10205 19:54:18.728254
10206 19:54:18.728337 00000000 # done.
10207 19:54:18.731488
10208 19:54:18.738198 Command line loaded dynamically from TFTP file: 11899575/tftp-deploy-vq85ut5t/kernel/cmdline
10209 19:54:18.738408
10210 19:54:18.751652 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10211 19:54:18.751884
10212 19:54:18.752017 Loading FIT.
10213 19:54:18.752137
10214 19:54:18.755431 Image ramdisk-1 has 98318988 bytes.
10215 19:54:18.755689
10216 19:54:18.758371 Image fdt-1 has 47278 bytes.
10217 19:54:18.758651
10218 19:54:18.761528 Image kernel-1 has 11047522 bytes.
10219 19:54:18.761811
10220 19:54:18.771506 Compat preference: google,spherion-rev7-sku1 google,spherion-rev7 google,spherion-sku1 google,spherion
10221 19:54:18.771896
10222 19:54:18.788080 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
10223 19:54:18.788682
10224 19:54:18.791244 Choosing best match conf-1 for compat google,spherion.
10225 19:54:18.794808
10226 19:54:18.798748 Connected to device vid:did:rid of 1ae0:0028:00
10227 19:54:18.808805
10228 19:54:18.811925 tpm_get_response: command 0x17b, return code 0x0
10229 19:54:18.812422
10230 19:54:18.815025 ec_init: CrosEC protocol v3 supported (256, 248)
10231 19:54:18.819390
10232 19:54:18.822647 tpm_cleanup: add release locality here.
10233 19:54:18.823203
10234 19:54:18.823563 Shutting down all USB controllers.
10235 19:54:18.825997
10236 19:54:18.826448 Removing current net device
10237 19:54:18.826808
10238 19:54:18.832641 Exiting depthcharge with code 4 at timestamp: 95888243
10239 19:54:18.833093
10240 19:54:18.835879 LZMA decompressing kernel-1 to 0x821a6718
10241 19:54:18.836356
10242 19:54:18.839456 LZMA decompressing kernel-1 to 0x40000000
10243 19:54:20.226772
10244 19:54:20.227317 jumping to kernel
10245 19:54:20.229671 end: 2.2.4 bootloader-commands (duration 00:01:09) [common]
10246 19:54:20.230228 start: 2.2.5 auto-login-action (timeout 00:03:17) [common]
10247 19:54:20.230628 Setting prompt string to ['Linux version [0-9]']
10248 19:54:20.231007 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10249 19:54:20.231380 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10250 19:54:20.277882
10251 19:54:20.280893 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10252 19:54:20.285235 start: 2.2.5.1 login-action (timeout 00:03:17) [common]
10253 19:54:20.285607 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10254 19:54:20.285842 Setting prompt string to []
10255 19:54:20.286103 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10256 19:54:20.286337 Using line separator: #'\n'#
10257 19:54:20.286535 No login prompt set.
10258 19:54:20.286745 Parsing kernel messages
10259 19:54:20.287023 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10260 19:54:20.287458 [login-action] Waiting for messages, (timeout 00:03:17)
10261 19:54:20.304577 [ 0.000000] Linux version 6.1.59-cip8-rt4 (KernelCI@build-j84202-arm64-gcc-10-defconfig-arm64-chromebook-st8dj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023
10262 19:54:20.307692 [ 0.000000] random: crng init done
10263 19:54:20.314342 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10264 19:54:20.317795 [ 0.000000] efi: UEFI not found.
10265 19:54:20.324245 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10266 19:54:20.330936 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10267 19:54:20.341733 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10268 19:54:20.350790 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10269 19:54:20.357582 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10270 19:54:20.364167 [ 0.000000] printk: bootconsole [mtk8250] enabled
10271 19:54:20.370867 [ 0.000000] NUMA: No NUMA configuration found
10272 19:54:20.377528 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10273 19:54:20.380739 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10274 19:54:20.383962 [ 0.000000] Zone ranges:
10275 19:54:20.390306 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10276 19:54:20.393819 [ 0.000000] DMA32 empty
10277 19:54:20.400474 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10278 19:54:20.403694 [ 0.000000] Movable zone start for each node
10279 19:54:20.407028 [ 0.000000] Early memory node ranges
10280 19:54:20.413438 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10281 19:54:20.420115 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10282 19:54:20.426886 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10283 19:54:20.433626 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10284 19:54:20.440082 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10285 19:54:20.446445 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10286 19:54:20.476717 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10287 19:54:20.482621 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10288 19:54:20.489826 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10289 19:54:20.492798 [ 0.000000] psci: probing for conduit method from DT.
10290 19:54:20.499463 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10291 19:54:20.502627 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10292 19:54:20.509225 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10293 19:54:20.512438 [ 0.000000] psci: SMC Calling Convention v1.2
10294 19:54:20.518977 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10295 19:54:20.522577 [ 0.000000] Detected VIPT I-cache on CPU0
10296 19:54:20.529133 [ 0.000000] CPU features: detected: GIC system register CPU interface
10297 19:54:20.535809 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10298 19:54:20.542329 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10299 19:54:20.549000 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10300 19:54:20.558756 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10301 19:54:20.565063 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10302 19:54:20.568665 [ 0.000000] alternatives: applying boot alternatives
10303 19:54:20.575162 [ 0.000000] Fallback order for Node 0: 0
10304 19:54:20.581693 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10305 19:54:20.585096 [ 0.000000] Policy zone: Normal
10306 19:54:20.598127 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10307 19:54:20.607736 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10308 19:54:20.618639 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10309 19:54:20.629012 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10310 19:54:20.635640 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10311 19:54:20.638876 <6>[ 0.000000] software IO TLB: area num 8.
10312 19:54:20.694186 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10313 19:54:20.774326 <6>[ 0.000000] Memory: 3759000K/4191232K available (17984K kernel code, 4116K rwdata, 17476K rodata, 8448K init, 615K bss, 399464K reserved, 32768K cma-reserved)
10314 19:54:20.781140 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10315 19:54:20.787446 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10316 19:54:20.790830 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10317 19:54:20.797602 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10318 19:54:20.804147 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10319 19:54:20.807219 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10320 19:54:20.816789 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10321 19:54:20.823701 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10322 19:54:20.830403 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10323 19:54:20.836839 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10324 19:54:20.840251 <6>[ 0.000000] GICv3: 608 SPIs implemented
10325 19:54:20.843801 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10326 19:54:20.850351 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10327 19:54:20.853522 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10328 19:54:20.860134 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10329 19:54:20.873740 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10330 19:54:20.886777 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10331 19:54:20.893041 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10332 19:54:20.900411 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10333 19:54:20.913768 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10334 19:54:20.920319 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10335 19:54:20.927207 <6>[ 0.009174] Console: colour dummy device 80x25
10336 19:54:20.936800 <6>[ 0.013895] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10337 19:54:20.943427 <6>[ 0.024403] pid_max: default: 32768 minimum: 301
10338 19:54:20.947081 <6>[ 0.029304] LSM: Security Framework initializing
10339 19:54:20.953626 <6>[ 0.034217] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10340 19:54:20.963471 <6>[ 0.041825] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10341 19:54:20.970249 <6>[ 0.051051] cblist_init_generic: Setting adjustable number of callback queues.
10342 19:54:20.976918 <6>[ 0.058496] cblist_init_generic: Setting shift to 3 and lim to 1.
10343 19:54:20.986315 <6>[ 0.064871] cblist_init_generic: Setting adjustable number of callback queues.
10344 19:54:20.992841 <6>[ 0.072298] cblist_init_generic: Setting shift to 3 and lim to 1.
10345 19:54:20.996356 <6>[ 0.078735] rcu: Hierarchical SRCU implementation.
10346 19:54:21.002893 <6>[ 0.078737] rcu: Max phase no-delay instances is 1000.
10347 19:54:21.009538 <6>[ 0.078761] printk: bootconsole [mtk8250] printing thread started
10348 19:54:21.015895 <6>[ 0.097065] EFI services will not be available.
10349 19:54:21.019275 <6>[ 0.097265] smp: Bringing up secondary CPUs ...
10350 19:54:21.022720 <6>[ 0.097574] Detected VIPT I-cache on CPU1
10351 19:54:21.032680 <6>[ 0.097642] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10352 19:54:21.038870 <6>[ 0.097674] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10353 19:54:21.048418 <6>[ 0.125563] Detected VIPT I-cache on CPU2
10354 19:54:21.054864 <6>[ 0.125610] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10355 19:54:21.061635 <6>[ 0.125624] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10356 19:54:21.068292 <6>[ 0.125880] Detected VIPT I-cache on CPU3
10357 19:54:21.074575 <6>[ 0.125926] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10358 19:54:21.081751 <6>[ 0.125939] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10359 19:54:21.084757 <6>[ 0.126250] CPU features: detected: Spectre-v4
10360 19:54:21.091453 <6>[ 0.126257] CPU features: detected: Spectre-BHB
10361 19:54:21.094547 <6>[ 0.126261] Detected PIPT I-cache on CPU4
10362 19:54:21.101372 <6>[ 0.126319] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10363 19:54:21.107830 <6>[ 0.126335] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10364 19:54:21.114281 <6>[ 0.126626] Detected PIPT I-cache on CPU5
10365 19:54:21.120840 <6>[ 0.126686] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10366 19:54:21.127435 <6>[ 0.126703] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10367 19:54:21.131043 <6>[ 0.126976] Detected PIPT I-cache on CPU6
10368 19:54:21.137785 <6>[ 0.127035] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10369 19:54:21.144400 <6>[ 0.127052] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10370 19:54:21.150836 <6>[ 0.127345] Detected PIPT I-cache on CPU7
10371 19:54:21.157048 <6>[ 0.127408] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10372 19:54:21.164276 <6>[ 0.127424] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10373 19:54:21.167401 <6>[ 0.127472] smp: Brought up 1 node, 8 CPUs
10374 19:54:21.173668 <6>[ 0.127477] SMP: Total of 8 processors activated.
10375 19:54:21.177164 <6>[ 0.127480] CPU features: detected: 32-bit EL0 Support
10376 19:54:21.187302 <6>[ 0.127482] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10377 19:54:21.193550 <6>[ 0.127485] CPU features: detected: Common not Private translations
10378 19:54:21.200317 <6>[ 0.127486] CPU features: detected: CRC32 instructions
10379 19:54:21.207012 <6>[ 0.127489] CPU features: detected: RCpc load-acquire (LDAPR)
10380 19:54:21.210528 <6>[ 0.127491] CPU features: detected: LSE atomic instructions
10381 19:54:21.216756 <6>[ 0.127492] CPU features: detected: Privileged Access Never
10382 19:54:21.223313 <6>[ 0.127494] CPU features: detected: RAS Extension Support
10383 19:54:21.230270 <6>[ 0.127497] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10384 19:54:21.233273 <6>[ 0.127562] CPU: All CPU(s) started at EL2
10385 19:54:21.240103 <6>[ 0.127564] alternatives: applying system-wide alternatives
10386 19:54:21.243338 <6>[ 0.139890] devtmpfs: initialized
10387 19:54:21.275279 �A�͡�Å�������ɥ��郪��Bzɑ�Ɂ�b��ʲ�ѕͥ+R�<6>[ 0.354601]< printk: console [ttyS0] printing thread started
10388 19:54:21.278480 6>[ <6>[ 0.354625] printk: console [ttyS0] enabled
10389 19:54:21.281313 0.220200] pnp: PnP ACPI: disabled
10390 19:54:21.287931 <6>[ 0.222646] NET: Registered PF_INET protocol family
10391 19:54:21.294621 <6>[ 0.354630] printk: bootconsole [mtk8250] disabled
10392 19:54:21.301239 <6>[ 0.373763] printk: bootconsole [mtk8250] printing thread stopped
10393 19:54:21.304464 <6>[ 0.374863] SuperH (H)SCI(F) driver initialized
10394 19:54:21.307872 <6>[ 0.375340] msm_serial: driver initialized
10395 19:54:21.317736 <6>[ 0.379970] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10396 19:54:21.328030 <6>[ 0.380000] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10397 19:54:21.334676 <6>[ 0.380031] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10398 19:54:21.348293 <6>[ 0.380060] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10399 19:54:21.353538 <6>[ 0.380082] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10400 19:54:21.377341 <6>[ 0.380111] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10401 19:54:21.377899 <6>[ 0.380138] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10402 19:54:21.381583 <6>[ 0.380247] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10403 19:54:21.390817 <6>[ 0.380276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10404 19:54:21.391371 <6>[ 0.390942] loop: module loaded
10405 19:54:21.398609 <6>[ 0.393514] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10406 19:54:21.402091 <4>[ 0.410213] mtk-pmic-keys: Failed to locate of_node [id: -1]
10407 19:54:21.405383 <6>[ 0.411032] megasas: 07.719.03.00-rc1
10408 19:54:21.411915 <6>[ 0.423405] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10409 19:54:21.418474 <6>[ 0.423406] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10410 19:54:21.425251 <6>[ 0.435231] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10411 19:54:21.435367 <6>[ 0.487296] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10412 19:54:25.153143 <6>[ 4.234575] Freeing initrd memory: 96012K
10413 19:54:25.161258 <6>[ 4.240817] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10414 19:54:25.168111 <6>[ 4.245447] tun: Universal TUN/TAP device driver, 1.6
10415 19:54:25.171590 <6>[ 4.246191] thunder_xcv, ver 1.0
10416 19:54:25.174436 <6>[ 4.246209] thunder_bgx, ver 1.0
10417 19:54:25.177823 <6>[ 4.246222] nicpf, ver 1.0
10418 19:54:25.184622 <6>[ 4.247264] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10419 19:54:25.191373 <6>[ 4.247266] hns3: Copyright (c) 2017 Huawei Corporation.
10420 19:54:25.195062 <6>[ 4.247291] hclge is initializing
10421 19:54:25.197945 <6>[ 4.247303] e1000: Intel(R) PRO/1000 Network Driver
10422 19:54:25.204969 <6>[ 4.247305] e1000: Copyright (c) 1999-2006 Intel Corporation.
10423 19:54:25.212281 <6>[ 4.247324] e1000e: Intel(R) PRO/1000 Network Driver
10424 19:54:25.215457 <6>[ 4.247325] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10425 19:54:25.222838 <6>[ 4.247341] igb: Intel(R) Gigabit Ethernet Network Driver
10426 19:54:25.229178 <6>[ 4.247343] igb: Copyright (c) 2007-2014 Intel Corporation.
10427 19:54:25.236356 <6>[ 4.247356] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10428 19:54:25.239393 <6>[ 4.247358] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10429 19:54:25.246450 <6>[ 4.247652] sky2: driver version 1.30
10430 19:54:25.249359 <6>[ 4.248737] VFIO - User Level meta-driver version: 0.3
10431 19:54:25.256470 <6>[ 4.251543] usbcore: registered new interface driver usb-storage
10432 19:54:25.262591 <6>[ 4.251721] usbcore: registered new device driver onboard-usb-hub
10433 19:54:25.269504 <6>[ 4.254436] mt6397-rtc mt6359-rtc: registered as rtc0
10434 19:54:25.276111 <6>[ 4.254587] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-28T19:54:26 UTC (1698522866)
10435 19:54:25.282679 <6>[ 4.255196] i2c_dev: i2c /dev entries driver
10436 19:54:25.289354 <6>[ 4.262237] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10437 19:54:25.296050 <6>[ 4.278214] cpu cpu0: EM: created perf domain
10438 19:54:25.299410 <6>[ 4.278535] cpu cpu4: EM: created perf domain
10439 19:54:25.305957 <6>[ 4.282151] sdhci: Secure Digital Host Controller Interface driver
10440 19:54:25.309003 <6>[ 4.282152] sdhci: Copyright(c) Pierre Ossman
10441 19:54:25.315524 <6>[ 4.282484] Synopsys Designware Multimedia Card Interface Driver
10442 19:54:25.322038 <6>[ 4.282857] sdhci-pltfm: SDHCI platform and OF driver helper
10443 19:54:25.328755 <6>[ 4.287161] ledtrig-cpu: registered to indicate activity on CPUs
10444 19:54:25.335589 <6>[ 4.287796] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10445 19:54:25.338596 <6>[ 4.287812] mmc0: CQHCI version 5.10
10446 19:54:25.345336 <6>[ 4.288112] usbcore: registered new interface driver usbhid
10447 19:54:25.348633 <6>[ 4.288113] usbhid: USB HID core driver
10448 19:54:25.355102 <6>[ 4.288221] spi_master spi0: will run message pump with realtime priority
10449 19:54:25.368315 <6>[ 4.317780] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10450 19:54:25.382131 <6>[ 4.319489] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10451 19:54:25.388694 <6>[ 4.321566] cros-ec-spi spi0.0: Chrome EC device registered
10452 19:54:25.397954 <6>[ 4.334376] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10453 19:54:25.401324 <6>[ 4.335268] NET: Registered PF_PACKET protocol family
10454 19:54:25.408395 <6>[ 4.335338] 9pnet: Installing 9P2000 support
10455 19:54:25.411593 <5>[ 4.335366] Key type dns_resolver registered
10456 19:54:25.414899 <6>[ 4.335628] registered taskstats version 1
10457 19:54:25.421534 <5>[ 4.335643] Loading compiled-in X.509 certificates
10458 19:54:25.431116 <4>[ 4.352265] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10459 19:54:25.440926 <4>[ 4.352432] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10460 19:54:25.447442 <3>[ 4.352442] debugfs: File 'uA_load' in directory '/' already present!
10461 19:54:25.454148 <3>[ 4.352447] debugfs: File 'min_uV' in directory '/' already present!
10462 19:54:25.460644 <3>[ 4.352451] debugfs: File 'max_uV' in directory '/' already present!
10463 19:54:25.471024 <3>[ 4.352453] debugfs: File 'constraint_flags' in directory '/' already present!
10464 19:54:25.477086 <3>[ 4.354561] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10465 19:54:25.483978 <6>[ 4.361751] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10466 19:54:25.490688 <6>[ 4.362560] xhci-mtk 11200000.usb: xHCI Host Controller
10467 19:54:25.497203 <6>[ 4.362589] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10468 19:54:25.507173 <6>[ 4.362835] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10469 19:54:25.513727 <6>[ 4.362903] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10470 19:54:25.517073 <6>[ 4.363066] xhci-mtk 11200000.usb: xHCI Host Controller
10471 19:54:25.526582 <6>[ 4.363085] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10472 19:54:25.533239 <6>[ 4.363099] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10473 19:54:25.536989 <6>[ 4.363789] hub 1-0:1.0: USB hub found
10474 19:54:25.539826 <6>[ 4.363847] hub 1-0:1.0: 1 port detected
10475 19:54:25.550229 <6>[ 4.364389] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10476 19:54:25.552895 <6>[ 4.365026] hub 2-0:1.0: USB hub found
10477 19:54:25.556595 <6>[ 4.365071] hub 2-0:1.0: 1 port detected
10478 19:54:25.563327 <6>[ 4.371140] mtk-msdc 11f70000.mmc: Got CD GPIO
10479 19:54:25.566308 <6>[ 4.382059] mmc0: Command Queue Engine enabled
10480 19:54:25.572890 <6>[ 4.382074] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10481 19:54:25.579704 <6>[ 4.382704] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10482 19:54:25.586272 <6>[ 4.385502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10483 19:54:25.593090 <6>[ 4.385510] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10484 19:54:25.603016 <4>[ 4.385665] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10485 19:54:25.609569 <6>[ 4.386064] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10486 19:54:25.616493 <6>[ 4.386294] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10487 19:54:25.625762 <6>[ 4.386299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10488 19:54:25.632402 <6>[ 4.386481] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10489 19:54:25.639280 <6>[ 4.386492] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10490 19:54:25.648972 <6>[ 4.386502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10491 19:54:25.659002 <6>[ 4.386511] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10492 19:54:25.662621 <6>[ 4.387875] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10493 19:54:25.672670 <6>[ 4.388422] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10494 19:54:25.678851 <6>[ 4.388441] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10495 19:54:25.689026 <6>[ 4.388447] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10496 19:54:25.695135 <6>[ 4.388453] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10497 19:54:25.704938 <6>[ 4.388460] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10498 19:54:25.712137 <6>[ 4.388465] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10499 19:54:25.721586 <6>[ 4.388472] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10500 19:54:25.728700 <6>[ 4.388478] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10501 19:54:25.738503 <6>[ 4.388484] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10502 19:54:25.745153 <6>[ 4.388491] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10503 19:54:25.754794 <6>[ 4.388497] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10504 19:54:25.761066 <6>[ 4.388503] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10505 19:54:25.771327 <6>[ 4.388511] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10506 19:54:25.780929 <6>[ 4.388518] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10507 19:54:25.787812 <6>[ 4.388525] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10508 19:54:25.794500 <6>[ 4.388590] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10509 19:54:25.800825 <6>[ 4.389328] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10510 19:54:25.807541 <6>[ 4.389372] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10511 19:54:25.814285 <6>[ 4.390307] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10512 19:54:25.820791 <6>[ 4.390866] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10513 19:54:25.826983 <6>[ 4.391490] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10514 19:54:25.833841 <6>[ 4.392188] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10515 19:54:25.840409 <6>[ 4.392404] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10516 19:54:25.850467 <6>[ 4.392416] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10517 19:54:25.860354 <6>[ 4.392421] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10518 19:54:25.870245 <6>[ 4.392426] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10519 19:54:25.880517 <6>[ 4.392432] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10520 19:54:25.886905 <6>[ 4.392442] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10521 19:54:25.896413 <6>[ 4.392449] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10522 19:54:25.906669 <6>[ 4.392454] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10523 19:54:25.916550 <6>[ 4.392458] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10524 19:54:25.926575 <6>[ 4.392465] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10525 19:54:25.936371 <6>[ 4.392469] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10526 19:54:25.943012 <6>[ 4.393127] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10527 19:54:25.952825 <6>[ 4.792071] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10528 19:54:25.956224 <6>[ 4.951774] hub 1-1:1.0: USB hub found
10529 19:54:25.959509 <6>[ 4.952156] hub 1-1:1.0: 4 ports detected
10530 19:54:26.000787 <6>[ 5.076364] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10531 19:54:26.021558 <6>[ 5.101378] hub 2-1:1.0: USB hub found
10532 19:54:26.024844 <6>[ 5.101787] hub 2-1:1.0: 3 ports detected
10533 19:54:26.188791 <6>[ 5.264278] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10534 19:54:26.309823 <6>[ 5.391251] hub 1-1.4:1.0: USB hub found
10535 19:54:26.312726 <6>[ 5.391566] hub 1-1.4:1.0: 2 ports detected
10536 19:54:26.392906 <6>[ 5.468356] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10537 19:54:26.604723 <6>[ 5.680258] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10538 19:54:26.788657 <6>[ 5.864061] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10539 19:54:37.620351 <6>[ 16.705245] ALSA device list:
10540 19:54:37.627185 <6>[ 16.705266] No soundcards found.
10541 19:54:37.630380 <6>[ 16.709576] Freeing unused kernel memory: 8448K
10542 19:54:37.633805 <6>[ 16.709736] Run /init as init process
10543 19:54:37.667606 <6>[ 16.750335] NET: Registered PF_INET6 protocol family
10544 19:54:37.670761 <6>[ 16.751392] Segment Routing with IPv6
10545 19:54:37.677424 <6>[ 16.751404] In-situ OAM (IOAM) with IPv6
10546 19:54:37.700565 <30>[ 16.767994] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10547 19:54:37.707503 <30>[ 16.768444] systemd[1]: Detected architecture arm64.
10548 19:54:37.707620
10549 19:54:37.710478 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10550 19:54:37.713746
10551 19:54:37.731871 <30>[ 16.812341] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10552 19:54:37.846968 <30>[ 16.926127] systemd[1]: Queued start job for default target Graphical Interface.
10553 19:54:37.872776 [[0;32m OK [0m] Created slic<30>[ 16.953254] systemd[1]: Created slice system-getty.slice.
10554 19:54:37.875805 e [0;1;39msystem-getty.slice[0m.
10555 19:54:37.898963 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 16.976791] systemd[1]: Created slice system-modprobe.slice.
10556 19:54:37.899089 m-modprobe.slice[0m.
10557 19:54:37.921461 [[0;32m OK [0m] Created slic<30>[ 17.002084] systemd[1]: Created slice system-serial\x2dgetty.slice.
10558 19:54:37.927607 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10559 19:54:37.951186 [[0;32m OK [0m] Created slice [0;1;39mUser <30>[ 17.029183] systemd[1]: Created slice User and Session Slice.
10560 19:54:37.951287 and Session Slice[0m.
10561 19:54:37.975494 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 17.053010] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10562 19:54:37.978569 ssword …ts to Console Directory Watch[0m.
10563 19:54:38.002741 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 17.080418] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10564 19:54:38.006264 sword R…uests to Wall Directory Watch[0m.
10565 19:54:38.029626 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 17.104188] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10566 19:54:38.036557 <30>[ 17.104328] systemd[1]: Reached target Local Encrypted Volumes.
10567 19:54:38.039703 l Encrypted Volumes[0m.
10568 19:54:38.059139 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 17.140166] systemd[1]: Reached target Paths.
10569 19:54:38.059263 s[0m.
10570 19:54:38.082561 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 17.160216] systemd[1]: Reached target Remote File Systems.
10571 19:54:38.082682 te File Systems[0m.
10572 19:54:38.099016 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 17.180134] systemd[1]: Reached target Slices.
10573 19:54:38.099130 es[0m.
10574 19:54:38.118954 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 17.200247] systemd[1]: Reached target Swap.
10575 19:54:38.119074 [0m.
10576 19:54:38.142876 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 17.220621] systemd[1]: Listening on initctl Compatibility Named Pipe.
10577 19:54:38.146097 l Compatibility Named Pipe[0m.
10578 19:54:38.164731 [[0;32m OK [0m] Listening on<30>[ 17.245703] systemd[1]: Listening on Journal Audit Socket.
10579 19:54:38.167777 [0;1;39mJournal Audit Socket[0m.
10580 19:54:38.188508 [[0;32m OK [0m] Listening on<30>[ 17.269446] systemd[1]: Listening on Journal Socket (/dev/log).
10581 19:54:38.191953 [0;1;39mJournal Socket (/dev/log)[0m.
10582 19:54:38.212374 [[0;32m OK [0m] Listening on<30>[ 17.293420] systemd[1]: Listening on Journal Socket.
10583 19:54:38.215712 [0;1;39mJournal Socket[0m.
10584 19:54:38.231585 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 17.312800] systemd[1]: Listening on udev Control Socket.
10585 19:54:38.234818 ontrol Socket[0m.
10586 19:54:38.256065 [[0;32m OK [0m] Listening on<30>[ 17.337277] systemd[1]: Listening on udev Kernel Socket.
10587 19:54:38.259423 [0;1;39mudev Kernel Socket[0m.
10588 19:54:38.315142 Mounting [0;1;39mHuge Pages File Syste<30>[ 17.392486] systemd[1]: Mounting Huge Pages File System...
10589 19:54:38.315314 m[0m...
10590 19:54:38.338266 Mounting [0;1;39mPOSIX Message Queue F<30>[ 17.416144] systemd[1]: Mounting POSIX Message Queue File System...
10591 19:54:38.338395 ile System[0m...
10592 19:54:38.366366 Mounting [0;1;39mKernel Debug File Sys<30>[ 17.444265] systemd[1]: Mounting Kernel Debug File System...
10593 19:54:38.366497 tem[0m...
10594 19:54:38.386546 <30>[ 17.464712] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10595 19:54:38.396595 <30>[ 17.469152] systemd[1]: Starting Create list of static device nodes for the current kernel...
10596 19:54:38.403455 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10597 19:54:38.430903 Starting [0;1;39mLoad Kernel Module co<30>[ 17.508641] systemd[1]: Starting Load Kernel Module configfs...
10598 19:54:38.431039 nfigfs[0m...
10599 19:54:38.449572 Startin<30>[ 17.530621] systemd[1]: Starting Load Kernel Module drm...
10600 19:54:38.452654 g [0;1;39mLoad Kernel Module drm[0m...
10601 19:54:38.474669 <30>[ 17.552578] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10602 19:54:38.503584 Starting [0;1;39mJournal Service[0m..<30>[ 17.584787] systemd[1]: Starting Journal Service...
10603 19:54:38.503713 .
10604 19:54:38.527031 Starting [0;1;39mLoad Kernel Modules[<30>[ 17.608077] systemd[1]: Starting Load Kernel Modules...
10605 19:54:38.530193 0m...
10606 19:54:38.555294 Starting [0;1;39mRemount Root and Kern<30>[ 17.632915] systemd[1]: Starting Remount Root and Kernel File Systems...
10607 19:54:38.558570 el File Systems[0m...
10608 19:54:38.582348 Starting [0;1;39mColdplug All udev Dev<30>[ 17.659943] systemd[1]: Starting Coldplug All udev Devices...
10609 19:54:38.582444 ices[0m...
10610 19:54:38.603004 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 17.683991] systemd[1]: Started Journal Service.
10611 19:54:38.606118 vice[0m.
10612 19:54:38.622762 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10613 19:54:38.640939 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10614 19:54:38.657392 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10615 19:54:38.676621 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10616 19:54:38.693881 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10617 19:54:38.710461 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10618 19:54:38.729951 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10619 19:54:38.749471 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10620 19:54:38.763565 See 'systemctl status systemd-remount-fs.service' for details.
10621 19:54:38.825299 Mounting [0;1;39mKernel Configuration File System[0m...
10622 19:54:38.842657 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10623 19:54:38.858588 <46>[ 17.936395] systemd-journald[192]: Received client request to flush runtime journal.
10624 19:54:38.867455 Starting [0;1;39mLoad/Save Random Seed[0m...
10625 19:54:38.892803 Starting [0;1;39mApply Kernel Variables[0m...
10626 19:54:38.911614 Starting [0;1;39mCreate System Users[0m...
10627 19:54:38.932638 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10628 19:54:38.948621 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10629 19:54:38.972640 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10630 19:54:38.985450 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10631 19:54:39.001619 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10632 19:54:39.017148 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10633 19:54:39.068651 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10634 19:54:39.093150 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10635 19:54:39.108452 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10636 19:54:39.123891 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10637 19:54:39.156154 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10638 19:54:39.180494 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10639 19:54:39.200612 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10640 19:54:39.220961 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10641 19:54:39.285647 Starting [0;1;39mNetwork Time Synchronization[0m...
10642 19:54:39.310297 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10643 19:54:39.344932 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10644 19:54:39.370534 <6>[ 18.451851] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10645 19:54:39.377235 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10646 19:54:39.383756 <6>[ 18.464239] remoteproc remoteproc0: scp is available
10647 19:54:39.387047 <6>[ 18.464419] remoteproc remoteproc0: powering up scp
10648 19:54:39.397174 <6>[ 18.464426] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10649 19:54:39.403687 <6>[ 18.464476] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10650 19:54:39.407155 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10651 19:54:39.418675 <6>[ 18.497621] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10652 19:54:39.425266 <6>[ 18.497655] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10653 19:54:39.435204 <6>[ 18.497664] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10654 19:54:39.445050 [[0;32m OK [0m] Created slic<4>[ 18.508792] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10655 19:54:39.454883 e [0;1;39msyste<4>[ 18.509074] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10656 19:54:39.458421 <6>[ 18.517199] mc: Linux media interface: v0.10
10657 19:54:39.461448 m-systemd\x2dbacklight.slice[0m.
10658 19:54:39.475404 <6>[ 18.557104] videodev: Linux video capture interface: v2.00
10659 19:54:39.485123 <6>[ 18.557790] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10660 19:54:39.491796 <3>[ 18.558494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 19:54:39.505125 [[0;32m OK [0m] Reached target [0;1;39mSyst<3>[ 18.558565] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 19:54:39.515060 em Time Set[0m.<3>[ 18.558585] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 19:54:39.515169
10664 19:54:39.522322 <3>[ 18.568642] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 19:54:39.529121 <3>[ 18.568662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 19:54:39.539308 <3>[ 18.568671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 19:54:39.545505 <3>[ 18.568680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 19:54:39.558732 [[0;32m OK [0m] Reached target [0;1;39mSyst<3>[ 18.568687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 19:54:39.568688 em Time Synchron<3>[ 18.569039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 19:54:39.568803 ized[0m.
10671 19:54:39.579015 <3>[ 18.569271] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 19:54:39.586064 <3>[ 18.569282] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10673 19:54:39.592596 <3>[ 18.569290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10674 19:54:39.599373 <6>[ 18.569636] usbcore: registered new interface driver r8152
10675 19:54:39.609331 <3>[ 18.576114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10676 19:54:39.616071 <3>[ 18.576201] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10677 19:54:39.622357 <3>[ 18.576212] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10678 19:54:39.632485 <3>[ 18.576229] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10679 19:54:39.638990 <3>[ 18.576302] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10680 19:54:39.648772 <3>[ 18.581605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10681 19:54:39.655363 <6>[ 18.590414] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10682 19:54:39.665429 <6>[ 18.594154] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10683 19:54:39.668624 <6>[ 18.594232] remoteproc remoteproc0: remote processor scp is now up
10684 19:54:39.678425 <4>[ 18.596060] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10685 19:54:39.685128 <4>[ 18.596060] Fallback method does not support PEC.
10686 19:54:39.692166 <3>[ 18.614671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10687 19:54:39.702228 <6>[ 18.615838] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10688 19:54:39.708740 <6>[ 18.622260] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10689 19:54:39.715732 <6>[ 18.622322] pci_bus 0000:00: root bus resource [bus 00-ff]
10690 19:54:39.722031 <6>[ 18.622348] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10691 19:54:39.732498 <6>[ 18.622356] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10692 19:54:39.736141 <6>[ 18.622495] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10693 19:54:39.746178 <6>[ 18.622566] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10694 19:54:39.749444 <6>[ 18.622796] pci 0000:00:00.0: supports D1 D2
10695 19:54:39.756293 <6>[ 18.622804] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10696 19:54:39.763576 <6>[ 18.625181] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10697 19:54:39.770087 <6>[ 18.625352] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10698 19:54:39.777258 <6>[ 18.625388] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10699 19:54:39.787265 <6>[ 18.625412] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10700 19:54:39.794131 <6>[ 18.625430] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10701 19:54:39.797582 <6>[ 18.625560] pci 0000:01:00.0: supports D1 D2
10702 19:54:39.804414 <6>[ 18.625566] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10703 19:54:39.814136 <6>[ 18.627734] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10704 19:54:39.825029 <6>[ 18.628155] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10705 19:54:39.831371 <6>[ 18.638537] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10706 19:54:39.838148 <6>[ 18.638702] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10707 19:54:39.848484 <6>[ 18.638709] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10708 19:54:39.855141 <6>[ 18.638730] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10709 19:54:39.862132 <6>[ 18.638747] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10710 19:54:39.872427 <6>[ 18.638763] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10711 19:54:39.879064 Starting [0;1;39mLoad/Save Screen …o<6>[ 18.638781] pci 0000:00:00.0: PCI bridge to [bus 01]
10712 19:54:39.889403 <6>[ 18.638791] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10713 19:54:39.896067 f leds:white:kbd<6>[ 18.658822] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10714 19:54:39.903356 _backlight[0m..<6>[ 18.668178] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10715 19:54:39.906934 .
10716 19:54:39.913485 <3>[ 18.679432] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10717 19:54:39.919866 <3>[ 18.680231] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10718 19:54:39.926488 <6>[ 18.690994] usbcore: registered new interface driver cdc_ether
10719 19:54:39.939855 [[0;32m OK [0m] Finished [0<4>[ 18.695000] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10720 19:54:39.946293 <4>[ 18.695108] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10721 19:54:39.952839 <6>[ 18.719659] Bluetooth: Core ver 2.22
10722 19:54:39.956216 <6>[ 18.720236] NET: Registered PF_BLUETOOTH protocol family
10723 19:54:39.962792 <6>[ 18.720240] Bluetooth: HCI device and connection manager initialized
10724 19:54:39.969466 <6>[ 18.722736] Bluetooth: HCI socket layer initialized
10725 19:54:39.973200 <6>[ 18.722771] Bluetooth: L2CAP socket layer initialized
10726 19:54:39.979595 <6>[ 18.722802] Bluetooth: SCO socket layer initialized
10727 19:54:39.985908 <6>[ 18.730271] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10728 19:54:39.992847 <6>[ 18.731368] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10729 19:54:39.996051 <6>[ 18.738641] usbcore: registered new interface driver r8153_ecm
10730 19:54:40.005787 <6>[ 18.741333] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10731 19:54:40.008976 <6>[ 18.754347] r8152 2-1.3:1.0 eth0: v1.12.13
10732 19:54:40.022206 <6>[ 18.762943] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10733 19:54:40.025763 <6>[ 18.774284] usbcore: registered new interface driver uvcvideo
10734 19:54:40.035940 <3>[ 18.782509] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10735 19:54:40.045634 <6>[ 18.813733] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10736 19:54:40.048784 <6>[ 18.813879] usbcore: registered new interface driver btusb
10737 19:54:40.058844 <4>[ 18.814434] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10738 19:54:40.065523 <3>[ 18.814451] Bluetooth: hci0: Failed to load firmware file (-2)
10739 19:54:40.071976 <3>[ 18.814456] Bluetooth: hci0: Failed to set up firmware (-2)
10740 19:54:40.082052 <4>[ 18.814463] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10741 19:54:40.088483 <6>[ 18.819429] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10742 19:54:40.095079 <6>[ 18.822282] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10743 19:54:40.104891 <3>[ 18.827589] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10744 19:54:40.111452 <6>[ 18.829541] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10745 19:54:40.121643 <3>[ 18.856141] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10746 19:54:40.131603 <3>[ 18.856921] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10747 19:54:40.138236 <3>[ 18.870168] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10748 19:54:40.147763 <3>[ 18.891641] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10749 19:54:40.157786 <3>[ 18.911496] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10750 19:54:40.164220 <5>[ 18.944941] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10751 19:54:40.174273 ;1;39mLoad/Save <5>[ 18.963384] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10752 19:54:40.180821 <4>[ 18.963474] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10753 19:54:40.187775 <6>[ 18.963482] cfg80211: failed to load regulatory.db
10754 19:54:40.194010 <6>[ 19.046053] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10755 19:54:40.200838 <6>[ 19.046154] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10756 19:54:40.207303 <6>[ 19.064067] mt7921e 0000:01:00.0: ASIC revision: 79610010
10757 19:54:40.217222 <4>[ 19.158809] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10758 19:54:40.227421 <4>[ 19.265774] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10759 19:54:40.233643 Screen …s of leds:white:kbd_backlight[0m.
10760 19:54:40.294076 <4>[ 19.369599] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10761 19:54:40.300637 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10762 19:54:40.315530 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10763 19:54:40.335044 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10764 19:54:40.350714 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10765 19:54:40.367450 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10766 19:54:40.397720 [[0;32m OK [0m] Listening on [0;1;39mD-Bus <4>[ 19.474620] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10767 19:54:40.401036 System Message Bus Socket[0m.
10768 19:54:40.415979 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10769 19:54:40.431614 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10770 19:54:40.451302 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10771 19:54:40.507027 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0<4>[ 19.582659] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 19:54:40.507205 m.
10773 19:54:40.547780 Starting [0;1;39mUser Login Management[0m...
10774 19:54:40.569934 Starting [0;1;39mPermit User Sessions[0m...
10775 19:54:40.584944 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10776 19:54:40.618104 <4>[ 19.692261] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 19:54:40.656758 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10778 19:54:40.680472 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10779 19:54:40.700218 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10780 19:54:40.724016 <4>[ 19.798372] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 19:54:40.764559 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10782 19:54:40.781486 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10783 19:54:40.797739 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10784 19:54:40.833494 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0<4>[ 19.906961] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 19:54:40.833608 m.
10786 19:54:40.848306 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10787 19:54:40.892319 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10788 19:54:40.929891 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10789 19:54:40.939445 <4>[ 20.014681] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 19:54:40.971759
10791 19:54:40.971893
10792 19:54:40.975752 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10793 19:54:40.975861
10794 19:54:40.978223 debian-bullseye-arm64 login: root (automatic login)
10795 19:54:40.978353
10796 19:54:40.978500
10797 19:54:40.994188 Linux debian-bullseye-arm64 6.1.59-cip8-rt4 #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023 aarch64
10798 19:54:40.994294
10799 19:54:41.000507 The programs included with the Debian GNU/Linux system are free software;
10800 19:54:41.007186 the exact distribution terms for each program are described in the
10801 19:54:41.010396 individual files in /usr/share/doc/*/copyright.
10802 19:54:41.010500
10803 19:54:41.016963 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10804 19:54:41.020711 permitted by applicable law.
10805 19:54:41.021181 Matched prompt #10: / #
10807 19:54:41.021478 Setting prompt string to ['/ #']
10808 19:54:41.021606 end: 2.2.5.1 login-action (duration 00:00:21) [common]
10810 19:54:41.021897 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10811 19:54:41.022020 start: 2.2.6 expect-shell-connection (timeout 00:02:56) [common]
10812 19:54:41.022124 Setting prompt string to ['/ #']
10813 19:54:41.022215 Forcing a shell prompt, looking for ['/ #']
10815 19:54:41.072476 / #
10816 19:54:41.072647 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10817 19:54:41.072761 Waiting using forced prompt support (timeout 00:02:30)
10818 19:54:41.072901 <4>[ 20.122458] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10819 19:54:41.077983
10820 19:54:41.078298 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10821 19:54:41.078434 start: 2.2.7 export-device-env (timeout 00:02:56) [common]
10822 19:54:41.078571 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10823 19:54:41.078701 end: 2.2 depthcharge-retry (duration 00:02:04) [common]
10824 19:54:41.078831 end: 2 depthcharge-action (duration 00:02:04) [common]
10825 19:54:41.078963 start: 3 lava-test-retry (timeout 00:05:00) [common]
10826 19:54:41.079088 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10827 19:54:41.079196 Using namespace: common
10829 19:54:41.179562 / # #
10830 19:54:41.179772 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10831 19:54:41.179932 #<3>[ 20.228004] mt7921e 0000:01:00.0: hardware init failed
10832 19:54:41.184534
10833 19:54:41.184833 Using /lava-11899575
10835 19:54:41.285201 / # export SHELL=/bin/sh
10836 19:54:41.290430 export SHELL=/bin/sh
10838 19:54:41.390981 / # . /lava-11899575/environment
10839 19:54:41.396543 . /lava-11899575/environment
10841 19:54:41.497112 / # /lava-11899575/bin/lava-test-runner /lava-11899575/0
10842 19:54:41.497319 Test shell timeout: 10s (minimum of the action and connection timeout)
10843 19:54:41.502180 /lava-11899575/bin/lava-test-runner /lava-11899575/0
10844 19:54:41.521120 + export TESTRUN_ID=0_sleep
10845 19:54:41.524451 + cd /lava-11899575/0/tests/0_sleep
10846 19:54:41.527823 + cat uuid
10847 19:54:41.527928 + UUID=11899575_1.5.2.3.1
10848 19:54:41.531031 + set +x
10849 19:54:41.534396 <LAVA_SIGNAL_STARTRUN 0_sleep 11899575_1.5.2.3.1>
10850 19:54:41.534692 Received signal: <STARTRUN> 0_sleep 11899575_1.5.2.3.1
10851 19:54:41.534798 Starting test lava.0_sleep (11899575_1.5.2.3.1)
10852 19:54:41.534916 Skipping test definition patterns.
10853 19:54:41.537699 + ./config/lava/sleep/sleep.sh mem freeze
10854 19:54:41.541055 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
10856 19:54:41.544475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
10857 19:54:41.548025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
10858 19:54:41.548278 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
10860 19:54:41.550813 rtcwake: assuming RTC uses UTC ...
10861 19:54:41.557530 rtcwake: wakeup from "mem" using rtc0 at Sat Oct 28 19:54:48 2023
10862 19:54:41.560777 <6>[ 20.643807] PM: suspend entry (deep)
10863 19:54:41.567503 <6>[ 20.643861] Filesystems sync: 0.000 seconds
10864 19:54:41.570763 <6>[ 20.645954] Freezing user space processes
10865 19:54:41.577646 <6>[ 20.647496] Freezing user space processes completed (elapsed 0.001 seconds)
10866 19:54:41.580729 <6>[ 20.647500] OOM killer disabled.
10867 19:54:41.587397 <6>[ 20.647502] Freezing remaining freezable tasks
10868 19:54:41.593868 <6>[ 20.648644] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
10869 19:54:41.600360 <6>[ 20.648648] printk: Suspending console(s) (use no_console_suspend to debug)
10870 19:54:44.950691 <3>[ 23.808284] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
10871 19:54:44.960758 <3>[ 23.808316] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
10872 19:54:44.970694 <3>[ 23.808360] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
10873 19:54:44.977318 <3>[ 23.808397] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
10874 19:54:44.983768 <3>[ 23.808646] PM: Some devices failed to suspend, or early wake event detected
10875 19:54:44.993591 <4>[ 23.823786] typec port0-partner: PM: parent port0 should not be sleeping
10876 19:54:45.058272 rtcwake: <6>[ 24.140305] OOM killer enabled.
10877 19:54:45.058361 write error
10878 19:54:45.061758 <6>[ 24.140316] Restarting tasks ... done.
10879 19:54:45.068357 <5>[ 24.142396] random: crng reseeded on system resumption
10880 19:54:45.071763 <6>[ 24.143330] PM: suspend exit
10881 19:54:45.074979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
10882 19:54:45.075236 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
10884 19:54:45.078002 rtcwake: assuming RTC uses UTC ...
10885 19:54:45.084562 rtcwake: wakeup from "mem" using rtc0 at Sat Oct 28 19:54:52 2023
10886 19:54:45.098658 <6>[ 24.181659] PM: suspend entry (deep)
10887 19:54:45.101910 <6>[ 24.181712] Filesystems sync: 0.000 seconds
10888 19:54:45.105466 <6>[ 24.182230] Freezing user space processes
10889 19:54:45.111979 <6>[ 24.183830] Freezing user space processes completed (elapsed 0.001 seconds)
10890 19:54:45.118518 <6>[ 24.183836] OOM killer disabled.
10891 19:54:45.122053 <6>[ 24.183838] Freezing remaining freezable tasks
10892 19:54:45.128487 <6>[ 24.185065] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
10893 19:54:45.135040 <6>[ 24.185069] printk: Suspending console(s) (use no_console_suspend to debug)
10894 19:54:48.534358 <3>[ 27.392281] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
10895 19:54:48.544328 <3>[ 27.392309] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
10896 19:54:48.554314 <3>[ 27.392344] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
10897 19:54:48.560710 <3>[ 27.392375] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
10898 19:54:48.570375 <3>[ 27.392607] PM: Some devices failed to suspend, or early wake event detected
10899 19:54:48.641455 rtcwake: <6>[ 27.724319] OOM killer enabled.
10900 19:54:48.644910 <6>[ 27.724331] Restarting tasks ... done.
10901 19:54:48.651442 <5>[ 27.726339] random: crng reseeded on system resumption
10902 19:54:48.655132 <6>[ 27.727299] PM: suspend exit
10903 19:54:48.655237 write error
10904 19:54:48.658846 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
10906 19:54:48.661645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
10907 19:54:48.661761 rtcwake: assuming RTC uses UTC ...
10908 19:54:48.668073 rtcwake: wakeup from "mem" using rtc0 at Sat Oct 28 19:54:55 2023
10909 19:54:48.682413 <6>[ 27.764428] PM: suspend entry (deep)
10910 19:54:48.685533 <6>[ 27.764480] Filesystems sync: 0.000 seconds
10911 19:54:48.689214 <6>[ 27.765006] Freezing user space processes
10912 19:54:48.695614 <6>[ 27.766677] Freezing user space processes completed (elapsed 0.001 seconds)
10913 19:54:48.702265 <6>[ 27.766686] OOM killer disabled.
10914 19:54:48.705464 <6>[ 27.766689] Freezing remaining freezable tasks
10915 19:54:48.712144 <6>[ 27.768092] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
10916 19:54:48.718737 <6>[ 27.768103] printk: Suspending console(s) (use no_console_suspend to debug)
10917 19:54:52.118087 <3>[ 30.976329] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
10918 19:54:52.127864 <3>[ 30.976365] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
10919 19:54:52.138154 <3>[ 30.976408] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
10920 19:54:52.144654 <3>[ 30.976449] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
10921 19:54:52.154444 <3>[ 30.976681] PM: Some devices failed to suspend, or early wake event detected
10922 19:54:52.225268 rtcwake: <6>[ 31.308313] OOM killer enabled.
10923 19:54:52.228671 <6>[ 31.308324] Restarting tasks ... done.
10924 19:54:52.235190 <5>[ 31.310162] random: crng reseeded on system resumption
10925 19:54:52.235270 write error
10926 19:54:52.238458 <LA<6>[ 31.311233] PM: suspend exit
10927 19:54:52.245182 VA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
10928 19:54:52.245261 rtcwake: assuming RTC uses UTC ...
10929 19:54:52.252010 rtcwake: wakeup from "mem" using rtc0 at Sat Oct 28 19:54:59 2023
10930 19:54:52.266119 <6>[ 31.349918] PM: suspend entry (deep)
10931 19:54:52.269574 <6>[ 31.349968] Filesystems sync: 0.000 seconds
10932 19:54:52.272726 <6>[ 31.350477] Freezing user space processes
10933 19:54:52.279096 <6>[ 31.352198] Freezing user space processes completed (elapsed 0.001 seconds)
10934 19:54:52.285913 <6>[ 31.352207] OOM killer disabled.
10935 19:54:52.289108 <6>[ 31.352210] Freezing remaining freezable tasks
10936 19:54:52.295747 <6>[ 31.353595] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
10937 19:54:52.302276 <6>[ 31.353604] printk: Suspending console(s) (use no_console_suspend to debug)
10938 19:54:55.701582 <3>[ 34.560264] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
10939 19:54:55.711436 <3>[ 34.560291] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
10940 19:54:55.721251 <3>[ 34.560334] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
10941 19:54:55.728246 <3>[ 34.560366] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
10942 19:54:55.737641 <3>[ 34.560661] PM: Some devices failed to suspend, or early wake event detected
10943 19:54:55.809772 rtcwake: <6>[ 34.892319] OOM killer enabled.
10944 19:54:55.813065 <6>[ 34.892330] Restarting tasks ... done.
10945 19:54:55.813144 write error
10946 19:54:55.819820 <5>[ 34.894397] random: crng reseeded on system resumption
10947 19:54:55.823038 <6>[ 34.896150] PM: suspend exit
10948 19:54:55.826658 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
10950 19:54:55.829870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
10951 19:54:55.829950 rtcwake: assuming RTC uses UTC ...
10952 19:54:55.836338 rtcwake: wakeup from "mem" using rtc0 at Sat Oct 28 19:55:03 2023
10953 19:54:55.849675 <6>[ 34.935638] PM: suspend entry (deep)
10954 19:54:55.852961 <6>[ 34.935687] Filesystems sync: 0.000 seconds
10955 19:54:55.856158 <6>[ 34.936366] Freezing user space processes
10956 19:54:55.862800 <6>[ 34.940193] Freezing user space processes completed (elapsed 0.003 seconds)
10957 19:54:55.869308 <6>[ 34.940201] OOM killer disabled.
10958 19:54:55.872694 <6>[ 34.940203] Freezing remaining freezable tasks
10959 19:54:55.879513 <6>[ 34.941387] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
10960 19:54:55.886008 <6>[ 34.941391] printk: Suspending console(s) (use no_console_suspend to debug)
10961 19:54:59.289048 <3>[ 38.144336] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
10962 19:54:59.298856 <3>[ 38.144370] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
10963 19:54:59.308986 <3>[ 38.144422] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
10964 19:54:59.315490 <3>[ 38.144476] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
10965 19:54:59.325384 <3>[ 38.144869] PM: Some devices failed to suspend, or early wake event detected
10966 19:54:59.397143 <6>[ 38.480322] OOM killer enabled.
10967 19:54:59.400515 <6>[ 38.480333] Restarting tasks ... done.
10968 19:54:59.407102 rtcwake: <5>[ 38.482361] random: crng reseeded on system resumption
10969 19:54:59.407423 write error
10970 19:54:59.410949 <6>[ 38.484088] PM: suspend exit
10971 19:54:59.417300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
10972 19:54:59.417878 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
10974 19:54:59.420714 rtcwake: assuming RTC uses UTC ...
10975 19:54:59.423817 rtcwake: wakeup from "mem" using rtc0 at Sat Oct 28 19:55:06 2023
10976 19:54:59.441210 <6>[ 38.525502] PM: suspend entry (deep)
10977 19:54:59.444479 <6>[ 38.525560] Filesystems sync: 0.000 seconds
10978 19:54:59.447763 <6>[ 38.526280] Freezing user space processes
10979 19:54:59.454431 <6>[ 38.528128] Freezing user space processes completed (elapsed 0.001 seconds)
10980 19:54:59.457729 <6>[ 38.528140] OOM killer disabled.
10981 19:54:59.464419 <6>[ 38.528143] Freezing remaining freezable tasks
10982 19:54:59.470908 <6>[ 38.535838] Freezing remaining freezable tasks completed (elapsed 0.007 seconds)
10983 19:54:59.477802 <6>[ 38.535850] printk: Suspending console(s) (use no_console_suspend to debug)
10984 19:55:02.876580 <3>[ 41.728243] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
10985 19:55:02.886525 <3>[ 41.728268] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
10986 19:55:02.896643 <3>[ 41.728302] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
10987 19:55:02.903284 <3>[ 41.728332] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
10988 19:55:02.913074 <3>[ 41.728598] PM: Some devices failed to suspend, or early wake event detected
10989 19:55:02.984526 rtcwake: write e<6>[ 42.068355] OOM killer enabled.
10990 19:55:02.987826 <6>[ 42.068367] Restarting tasks ... done.
10991 19:55:02.994527 <5>[ 42.070587] random: crng reseeded on system resumption
10992 19:55:02.994633 rror
10993 19:55:02.998086 Received signal: <TESTCASE> TEST<6
10994 19:55:02.998179 Ignoring malformed parameter for signal: "TEST<6".
10995 19:55:03.001132 <LAVA_SIGNAL_TESTCASE TEST<6>[ 42.071864] PM: suspend exit
10996 19:55:03.004390 _CASE_ID=rtcwake-mem-6 RESULT=fail>
10997 19:55:03.004472 rtcwake: assuming RTC uses UTC ...
10998 19:55:03.011184 rtcwake: wakeup from "mem" using rtc0 at Sat Oct 28 19:55:10 2023
10999 19:55:03.020705 <6>[ 42.106602] PM: suspend entry (deep)
11000 19:55:03.023755 <6>[ 42.106653] Filesystems sync: 0.000 seconds
11001 19:55:03.027290 <6>[ 42.107160] Freezing user space processes
11002 19:55:03.033899 <6>[ 42.108710] Freezing user space processes completed (elapsed 0.001 seconds)
11003 19:55:03.040390 <6>[ 42.108715] OOM killer disabled.
11004 19:55:03.043831 <6>[ 42.108717] Freezing remaining freezable tasks
11005 19:55:03.050456 <6>[ 42.112280] Freezing remaining freezable tasks completed (elapsed 0.003 seconds)
11006 19:55:03.056917 <6>[ 42.112289] printk: Suspending console(s) (use no_console_suspend to debug)
11007 19:55:06.452219 <3>[ 45.312234] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11008 19:55:06.461926 <3>[ 45.312258] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11009 19:55:06.472091 <3>[ 45.312287] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11010 19:55:06.478544 <3>[ 45.312315] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11011 19:55:06.488453 <3>[ 45.312546] PM: Some devices failed to suspend, or early wake event detected
11012 19:55:06.560068 rtcwake: write e<6>[ 45.644309] OOM killer enabled.
11013 19:55:06.560274 rror
11014 19:55:06.563545 <6>[ 45.644320] Restarting tasks ... done.
11015 19:55:06.570367 <LAVA_SIGNAL_TES<5>[ 45.646360] random: crng reseeded on system resumption
11016 19:55:06.570678 Received signal: <TES<5>[> 45.646360] random: crng reseeded on system resumption
<6
11017 19:55:06.573332 <6>[ 45.647885] PM: suspend exit
11018 19:55:06.580065 TCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11019 19:55:06.580164 rtcwake: assuming RTC uses UTC ...
11020 19:55:06.586452 rtcwake: wakeup from "mem" using rtc0 at Sat Oct 28 19:55:13 2023
11021 19:55:06.600197 <6>[ 45.687699] PM: suspend entry (deep)
11022 19:55:06.603307 <6>[ 45.687744] Filesystems sync: 0.000 seconds
11023 19:55:06.606758 <6>[ 45.688388] Freezing user space processes
11024 19:55:06.613293 <6>[ 45.692232] Freezing user space processes completed (elapsed 0.003 seconds)
11025 19:55:06.619990 <6>[ 45.692240] OOM killer disabled.
11026 19:55:06.623195 <6>[ 45.692242] Freezing remaining freezable tasks
11027 19:55:06.629870 <6>[ 45.699941] Freezing remaining freezable tasks completed (elapsed 0.007 seconds)
11028 19:55:06.636406 <6>[ 45.699965] printk: Suspending console(s) (use no_console_suspend to debug)
11029 19:55:10.032601 <6>[ 48.128302] vpu: disabling
11030 19:55:10.035945 <6>[ 48.128414] vproc2: disabling
11031 19:55:10.039186 <6>[ 48.128456] vproc1: disabling
11032 19:55:10.042507 <6>[ 48.128500] vaud18: disabling
11033 19:55:10.045902 <6>[ 48.128700] vsram_others: disabling
11034 19:55:10.049417 <6>[ 48.128861] va09: disabling
11035 19:55:10.052383 <6>[ 48.128922] vsram_md: disabling
11036 19:55:10.055753 <6>[ 48.129029] Vgpu: disabling
11037 19:55:10.062429 <3>[ 48.896310] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11038 19:55:10.072685 <3>[ 48.896339] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11039 19:55:10.082251 <3>[ 48.896372] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11040 19:55:10.088813 <3>[ 48.896405] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11041 19:55:10.095498 <3>[ 48.896585] PM: Some devices failed to suspend, or early wake event detected
11042 19:55:10.143772 <6>[ 49.228300] OOM killer enabled.
11043 19:55:10.147027 rtcwake: write e<6>[ 49.228311] Restarting tasks ... done.
11044 19:55:10.147118 rror
11045 19:55:10.155626 <5>[ 49.230864] random: crng reseeded on system resumption
11046 19:55:10.158945 <6>[ 49.232093] PM: suspend exit
11047 19:55:10.165801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11048 19:55:10.166077 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11050 19:55:10.169123 rtcwake: assuming RTC uses UTC ...
11051 19:55:10.172418 rtcwake: wakeup from "mem" using rtc0 at Sat Oct 28 19:55:17 2023
11052 19:55:10.187748 <6>[ 49.273892] PM: suspend entry (deep)
11053 19:55:10.191231 <6>[ 49.273935] Filesystems sync: 0.000 seconds
11054 19:55:10.194355 <6>[ 49.274449] Freezing user space processes
11055 19:55:10.201023 <6>[ 49.276201] Freezing user space processes completed (elapsed 0.001 seconds)
11056 19:55:10.207645 <6>[ 49.276222] OOM killer disabled.
11057 19:55:10.210913 <6>[ 49.276226] Freezing remaining freezable tasks
11058 19:55:10.217573 <6>[ 49.277628] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11059 19:55:10.224187 <6>[ 49.277638] printk: Suspending console(s) (use no_console_suspend to debug)
11060 19:55:13.619391 <3>[ 52.480292] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11061 19:55:13.632602 <3>[ 52.480329] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11062 19:55:13.639085 <3>[ 52.480384] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11063 19:55:13.645877 <3>[ 52.480438] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11064 19:55:13.655657 <3>[ 52.480877] PM: Some devices failed to suspend, or early wake event detected
11065 19:55:13.726895 rtcwake: write e<6>[ 52.812313] OOM killer enabled.
11066 19:55:13.730326 <6>[ 52.812325] Restarting tasks ... done.
11067 19:55:13.730443 rror
11068 19:55:13.737381 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9<5
11069 19:55:13.737491 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'rtcwake-mem-9<5', 'result': 'unknown'}
11070 19:55:13.740492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9<5>[ 52.814497] random: crng reseeded on system resumption
11071 19:55:13.743590 <6>[ 52.815506] PM: suspend exit
11072 19:55:13.747120 RESULT=fail>
11073 19:55:13.747305 rtcwake: assuming RTC uses UTC ...
11074 19:55:13.753776 rtcwake: wakeup from "mem" using rtc0 at Sat Oct 28 19:55:21 2023
11075 19:55:13.757218 <6>[ 52.847456] PM: suspend entry (deep)
11076 19:55:13.763850 <6>[ 52.847504] Filesystems sync: 0.000 seconds
11077 19:55:13.766835 <6>[ 52.848070] Freezing user space processes
11078 19:55:13.773648 <6>[ 52.856004] Freezing user space processes completed (elapsed 0.007 seconds)
11079 19:55:13.777084 <6>[ 52.856018] OOM killer disabled.
11080 19:55:13.783530 <6>[ 52.856024] Freezing remaining freezable tasks
11081 19:55:13.790504 <6>[ 52.857343] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11082 19:55:13.797032 <6>[ 52.857352] printk: Suspending console(s) (use no_console_suspend to debug)
11083 19:55:17.207100 <3>[ 56.064312] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11084 19:55:17.217252 <3>[ 56.064339] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11085 19:55:17.226964 <3>[ 56.064381] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11086 19:55:17.233605 <3>[ 56.064421] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11087 19:55:17.243324 <3>[ 56.064716] PM: Some devices failed to suspend, or early wake event detected
11088 19:55:17.311438 rtcwake: write error
11089 19:55:17.314823 <6>[ 56.400306] OOM killer enabled.
11090 19:55:17.317879 <6>[ 56.400317] Restarting tasks ... done.
11091 19:55:17.325086 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1<5
11092 19:55:17.325482 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'rtcwake-mem-1<5', 'result': 'unknown'}
11093 19:55:17.327902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1<5>[ 56.402425] random: crng reseeded on system resumption
11094 19:55:17.331380 <6>[ 56.403374] PM: suspend exit
11095 19:55:17.334802 0 RESULT=fail>
11096 19:55:17.338254 rtcwake: assuming RTC uses UTC ...
11097 19:55:17.341468 rtcwake: wakeup from "freeze" using rtc0 at Sat Oct 28 19:55:24 2023
11098 19:55:17.359598 <6>[ 56.445939] PM: suspend entry (s2idle)
11099 19:55:17.362928 <6>[ 56.445981] Filesystems sync: 0.000 seconds
11100 19:55:17.366545 <6>[ 56.446499] Freezing user space processes
11101 19:55:17.376554 <6>[ 56.448231] Freezing user space processes completed (elapsed 0.001 seconds)
11102 19:55:17.379257 <6>[ 56.448242] OOM killer disabled.
11103 19:55:17.382605 <6>[ 56.448244] Freezing remaining freezable tasks
11104 19:55:17.389193 <6>[ 56.449637] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11105 19:55:17.395892 <6>[ 56.449646] printk: Suspending console(s) (use no_console_suspend to debug)
11106 19:55:20.787540 <3>[ 59.648269] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11107 19:55:20.797169 <3>[ 59.648293] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11108 19:55:20.806823 <3>[ 59.648325] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11109 19:55:20.813571 <3>[ 59.648357] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11110 19:55:20.820299 <3>[ 59.648600] PM: Some devices failed to suspend, or early wake event detected
11111 19:55:20.894468 rtcwake: write e<6>[ 59.980307] OOM killer enabled.
11112 19:55:20.894980 rror
11113 19:55:20.898140 <6>[ 59.980318] Restarting tasks ... done.
11114 19:55:20.905201 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freez<5
11115 19:55:20.905781 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'rtcwake-freez<5', 'result': 'unknown'}
11116 19:55:20.907914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freez<5>[ 59.982259] random: crng reseeded on system resumption
11117 19:55:20.911515 <6>[ 59.983686] PM: suspend exit
11118 19:55:20.914515 e-1 RESULT=fail>
11119 19:55:20.918016 rtcwake: assuming RTC uses UTC ...
11120 19:55:20.921243 rtcwake: wakeup from "freeze" using rtc0 at Sat Oct 28 19:55:28 2023
11121 19:55:20.927697 <6>[ 60.015847] PM: suspend entry (s2idle)
11122 19:55:20.931495 <6>[ 60.015892] Filesystems sync: 0.000 seconds
11123 19:55:20.934637 <6>[ 60.016512] Freezing user space processes
11124 19:55:20.941436 <6>[ 60.024328] Freezing user space processes completed (elapsed 0.007 seconds)
11125 19:55:20.944521 <6>[ 60.024337] OOM killer disabled.
11126 19:55:20.951056 <6>[ 60.024339] Freezing remaining freezable tasks
11127 19:55:20.958239 <6>[ 60.025635] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11128 19:55:20.964318 <6>[ 60.025643] printk: Suspending console(s) (use no_console_suspend to debug)
11129 19:55:24.369989 <3>[ 63.232281] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11130 19:55:24.380127 <3>[ 63.232309] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11131 19:55:24.389761 <3>[ 63.232352] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11132 19:55:24.396564 <3>[ 63.232392] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11133 19:55:24.403101 <3>[ 63.232756] PM: Some devices failed to suspend, or early wake event detected
11134 19:55:24.473773 rtcwake: write error
11135 19:55:24.477302 <6>[ 63.564358] OOM killer enabled.
11136 19:55:24.480564 <6>[ 63.564368] Restarting tasks ... done.
11137 19:55:24.487245 <5>[ 63.566046] random: crng reseeded on system resumption
11138 19:55:24.490398 <6>[ 63.567066] PM: suspend exit
11139 19:55:24.497032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11140 19:55:24.497292 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11142 19:55:24.500313 rtcwake: assuming RTC uses UTC ...
11143 19:55:24.506628 rtcwake: wakeup from "freeze" using rtc0 at Sat Oct 28 19:55:31 2023
11144 19:55:24.518019 <6>[ 63.605666] PM: suspend entry (s2idle)
11145 19:55:24.521475 <6>[ 63.605715] Filesystems sync: 0.000 seconds
11146 19:55:24.524650 <6>[ 63.606224] Freezing user space processes
11147 19:55:24.531462 <6>[ 63.607861] Freezing user space processes completed (elapsed 0.001 seconds)
11148 19:55:24.538161 <6>[ 63.607869] OOM killer disabled.
11149 19:55:24.541462 <6>[ 63.607871] Freezing remaining freezable tasks
11150 19:55:24.548146 <6>[ 63.609195] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11151 19:55:24.554564 <6>[ 63.609204] printk: Suspending console(s) (use no_console_suspend to debug)
11152 19:55:27.953870 <3>[ 66.816275] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11153 19:55:27.963711 <3>[ 66.816298] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11154 19:55:27.973741 <3>[ 66.816329] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11155 19:55:27.980340 <3>[ 66.816359] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11156 19:55:27.987231 <3>[ 66.816591] PM: Some devices failed to suspend, or early wake event detected
11157 19:55:28.060646 rtcwake: write e<6>[ 67.148330] OOM killer enabled.
11158 19:55:28.060743 rror
11159 19:55:28.064049 <6>[ 67.148341] Restarting tasks ... done.
11160 19:55:28.070796 <5>[ 67.150080] random: crng reseeded on system resumption
11161 19:55:28.074189 <6>[ 67.150973] PM: suspend exit
11162 19:55:28.080880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11163 19:55:28.081140 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11165 19:55:28.084138 rtcwake: assuming RTC uses UTC ...
11166 19:55:28.087502 rtcwake: wakeup from "freeze" using rtc0 at Sat Oct 28 19:55:35 2023
11167 19:55:28.101673 <6>[ 67.191588] PM: suspend entry (s2idle)
11168 19:55:28.105055 <6>[ 67.191631] Filesystems sync: 0.000 seconds
11169 19:55:28.108501 <6>[ 67.192372] Freezing user space processes
11170 19:55:28.118356 <6>[ 67.196265] Freezing user space processes completed (elapsed 0.003 seconds)
11171 19:55:28.121736 <6>[ 67.196273] OOM killer disabled.
11172 19:55:28.125019 <6>[ 67.196276] Freezing remaining freezable tasks
11173 19:55:28.131635 <6>[ 67.197558] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11174 19:55:28.141325 <6>[ 67.197567] printk: Suspending console(s) (use no_console_suspend to debug)
11175 19:55:31.537367 <3>[ 70.400266] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11176 19:55:31.547300 <3>[ 70.400294] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11177 19:55:31.556961 <3>[ 70.400336] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11178 19:55:31.563978 <3>[ 70.400376] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11179 19:55:31.573529 <3>[ 70.400671] PM: Some devices failed to suspend, or early wake event detected
11180 19:55:31.644939 rtcwake: write e<6>[ 70.732310] OOM killer enabled.
11181 19:55:31.645029 rror
11182 19:55:31.648642 Received signal: <TESTCASE> TEST_CASE_<6
11183 19:55:31.648728 Ignoring malformed parameter for signal: "TEST_CASE_<6".
11184 19:55:31.655041 <LAVA_SIGNAL_TESTCASE TEST_CASE_<6>[ 70.732322] Restarting tasks ... done.
11185 19:55:31.661864 ID=rtcwake-freez<5>[ 70.734185] random: crng reseeded on system resumption
11186 19:55:31.665248 e-4 RESULT=fail><6>[ 70.735851] PM: suspend exit
11187 19:55:31.665328
11188 19:55:31.668515 rtcwake: assuming RTC uses UTC ...
11189 19:55:31.675227 rtcwake: wakeup from "freeze" using rtc0 at Sat Oct 28 19:55:38 2023
11190 19:55:31.689173 <6>[ 70.776666] PM: suspend entry (s2idle)
11191 19:55:31.692619 <6>[ 70.776715] Filesystems sync: 0.000 seconds
11192 19:55:31.696115 <6>[ 70.777220] Freezing user space processes
11193 19:55:31.706127 <6>[ 70.778766] Freezing user space processes completed (elapsed 0.001 seconds)
11194 19:55:31.709494 <6>[ 70.778775] OOM killer disabled.
11195 19:55:31.712803 <6>[ 70.778777] Freezing remaining freezable tasks
11196 19:55:31.719399 <6>[ 70.780218] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11197 19:55:31.725834 <6>[ 70.780229] printk: Suspending console(s) (use no_console_suspend to debug)
11198 19:55:35.120992 <3>[ 73.984237] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11199 19:55:35.131268 <3>[ 73.984262] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11200 19:55:35.140602 <3>[ 73.984296] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11201 19:55:35.147183 <3>[ 73.984326] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11202 19:55:35.156887 <3>[ 73.984573] PM: Some devices failed to suspend, or early wake event detected
11203 19:55:35.228059 rtcwake: write e<6>[ 74.316348] OOM killer enabled.
11204 19:55:35.231388 <6>[ 74.316359] Restarting tasks ... done.
11205 19:55:35.238103 <5>[ 74.318200] random: crng reseeded on system resumption
11206 19:55:35.241470 <6>[ 74.319222] PM: suspend exit
11207 19:55:35.241549 rror
11208 19:55:35.248105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11209 19:55:35.248370 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11211 19:55:35.251225 rtcwake: assuming RTC uses UTC ...
11212 19:55:35.254481 rtcwake: wakeup from "freeze" using rtc0 at Sat Oct 28 19:55:42 2023
11213 19:55:35.269424 <6>[ 74.358050] PM: suspend entry (s2idle)
11214 19:55:35.272599 <6>[ 74.358103] Filesystems sync: 0.000 seconds
11215 19:55:35.275522 <6>[ 74.358627] Freezing user space processes
11216 19:55:35.282472 <6>[ 74.360243] Freezing user space processes completed (elapsed 0.001 seconds)
11217 19:55:35.288873 <6>[ 74.360253] OOM killer disabled.
11218 19:55:35.292564 <6>[ 74.360256] Freezing remaining freezable tasks
11219 19:55:35.298750 <6>[ 74.367905] Freezing remaining freezable tasks completed (elapsed 0.007 seconds)
11220 19:55:35.305526 <6>[ 74.367914] printk: Suspending console(s) (use no_console_suspend to debug)
11221 19:55:38.704636 <3>[ 77.568351] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11222 19:55:38.714624 <3>[ 77.568411] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11223 19:55:38.724587 <3>[ 77.568482] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11224 19:55:38.730959 <3>[ 77.568520] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11225 19:55:38.738066 <3>[ 77.568909] PM: Some devices failed to suspend, or early wake event detected
11226 19:55:38.811485 rtcwake: write e<6>[ 77.900367] OOM killer enabled.
11227 19:55:38.814595 <6>[ 77.900378] Restarting tasks ... done.
11228 19:55:38.821819 <5>[ 77.902046] random: crng reseeded on system resumption
11229 19:55:38.824750 <6>[ 77.902948] PM: suspend exit
11230 19:55:38.824830 rror
11231 19:55:38.831359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11232 19:55:38.831617 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11234 19:55:38.834878 rtcwake: assuming RTC uses UTC ...
11235 19:55:38.837871 rtcwake: wakeup from "freeze" using rtc0 at Sat Oct 28 19:55:46 2023
11236 19:55:38.852647 <6>[ 77.941712] PM: suspend entry (s2idle)
11237 19:55:38.856192 <6>[ 77.941764] Filesystems sync: 0.000 seconds
11238 19:55:38.859391 <6>[ 77.942288] Freezing user space processes
11239 19:55:38.865672 <6>[ 77.943911] Freezing user space processes completed (elapsed 0.001 seconds)
11240 19:55:38.869507 <6>[ 77.943922] OOM killer disabled.
11241 19:55:38.875746 <6>[ 77.943924] Freezing remaining freezable tasks
11242 19:55:38.882606 <6>[ 77.945325] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11243 19:55:38.888988 <6>[ 77.945335] printk: Suspending console(s) (use no_console_suspend to debug)
11244 19:55:42.288600 <3>[ 81.152239] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11245 19:55:42.298354 <3>[ 81.152263] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11246 19:55:42.308568 <3>[ 81.152298] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11247 19:55:42.314767 <3>[ 81.152331] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11248 19:55:42.324599 <3>[ 81.152530] PM: Some devices failed to suspend, or early wake event detected
11249 19:55:42.396370 rtcwake: write e<6>[ 81.484361] OOM killer enabled.
11250 19:55:42.396885 rror
11251 19:55:42.399708 <6>[ 81.484372] Restarting tasks ... done.
11252 19:55:42.406569 <5>[ 81.485990] random: crng reseeded on system resumption
11253 19:55:42.409538 <LAVA_SIGNAL_TES<6>[ 81.487870] PM: suspend exit
11254 19:55:42.416867 TCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11255 19:55:42.417699 Received signal: <TES<6>[> 81.487870] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11256 19:55:42.419713 rtcwake: assuming RTC uses UTC ...
11257 19:55:42.422976 rtcwake: wakeup from "freeze" using rtc0 at Sat Oct 28 19:55:49 2023
11258 19:55:42.440803 <6>[ 81.528457] PM: suspend entry (s2idle)
11259 19:55:42.443841 <6>[ 81.528500] Filesystems sync: 0.000 seconds
11260 19:55:42.447305 <6>[ 81.529001] Freezing user space processes
11261 19:55:42.453923 <6>[ 81.530531] Freezing user space processes completed (elapsed 0.001 seconds)
11262 19:55:42.460312 <6>[ 81.530541] OOM killer disabled.
11263 19:55:42.464005 <6>[ 81.530544] Freezing remaining freezable tasks
11264 19:55:42.470306 <6>[ 81.531986] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11265 19:55:42.477038 <6>[ 81.532002] printk: Suspending console(s) (use no_console_suspend to debug)
11266 19:55:45.872217 <3>[ 84.736284] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11267 19:55:45.881958 <3>[ 84.736312] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11268 19:55:45.891975 <3>[ 84.736355] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11269 19:55:45.898346 <3>[ 84.736398] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11270 19:55:45.905340 <3>[ 84.736947] PM: Some devices failed to suspend, or early wake event detected
11271 19:55:45.979786 rtcwake: write e<6>[ 85.068319] OOM killer enabled.
11272 19:55:45.983451 <6>[ 85.068330] Restarting tasks ... done.
11273 19:55:45.989607 <5>[ 85.070413] random: crng reseeded on system resumption
11274 19:55:45.993085 <6>[ 85.071410] PM: suspend exit
11275 19:55:45.993547 rror
11276 19:55:45.999598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11277 19:55:46.000457 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11279 19:55:46.003123 rtcwake: assuming RTC uses UTC ...
11280 19:55:46.005892 rtcwake: wakeup from "freeze" using rtc0 at Sat Oct 28 19:55:53 2023
11281 19:55:46.020334 <6>[ 85.110244] PM: suspend entry (s2idle)
11282 19:55:46.023681 <6>[ 85.110295] Filesystems sync: 0.000 seconds
11283 19:55:46.026886 <6>[ 85.110819] Freezing user space processes
11284 19:55:46.037124 <6>[ 85.112086] Freezing user space processes completed (elapsed 0.001 seconds)
11285 19:55:46.040056 <6>[ 85.112095] OOM killer disabled.
11286 19:55:46.043566 <6>[ 85.112097] Freezing remaining freezable tasks
11287 19:55:46.049985 <6>[ 85.119859] Freezing remaining freezable tasks completed (elapsed 0.007 seconds)
11288 19:55:46.057075 <6>[ 85.119869] printk: Suspending console(s) (use no_console_suspend to debug)
11289 19:55:49.455919 <3>[ 88.320242] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11290 19:55:49.466110 <3>[ 88.320266] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11291 19:55:49.475423 <3>[ 88.320300] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11292 19:55:49.482248 <3>[ 88.320333] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11293 19:55:49.491502 <3>[ 88.320556] PM: Some devices failed to suspend, or early wake event detected
11294 19:55:49.562782 rtcwake: write e<6>[ 88.652368] OOM killer enabled.
11295 19:55:49.566247 <6>[ 88.652379] Restarting tasks ... done.
11296 19:55:49.573122 <5>[ 88.653965] random: crng reseeded on system resumption
11297 19:55:49.576068 <6>[ 88.655096] PM: suspend exit
11298 19:55:49.576632 rror
11299 19:55:49.583190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11300 19:55:49.584069 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11302 19:55:49.586514 rtcwake: assuming RTC uses UTC ...
11303 19:55:49.589296 rtcwake: wakeup from "freeze" using rtc0 at Sat Oct 28 19:55:56 2023
11304 19:55:49.603959 <6>[ 88.693874] PM: suspend entry (s2idle)
11305 19:55:49.607290 <6>[ 88.693914] Filesystems sync: 0.000 seconds
11306 19:55:49.610399 <6>[ 88.694400] Freezing user space processes
11307 19:55:49.620232 <6>[ 88.695923] Freezing user space processes completed (elapsed 0.001 seconds)
11308 19:55:49.623805 <6>[ 88.695932] OOM killer disabled.
11309 19:55:49.627073 <6>[ 88.695934] Freezing remaining freezable tasks
11310 19:55:49.633862 <6>[ 88.703604] Freezing remaining freezable tasks completed (elapsed 0.007 seconds)
11311 19:55:49.640141 <6>[ 88.703612] printk: Suspending console(s) (use no_console_suspend to debug)
11312 19:55:53.039152 <3>[ 91.904247] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11313 19:55:53.049104 <3>[ 91.904272] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11314 19:55:53.059358 <3>[ 91.904306] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11315 19:55:53.065964 <3>[ 91.904339] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11316 19:55:53.072861 <3>[ 91.904553] PM: Some devices failed to suspend, or early wake event detected
11317 19:55:53.147456 rtcwake: write e<6>[ 92.236363] OOM killer enabled.
11318 19:55:53.151136 <6>[ 92.236373] Restarting tasks ... done.
11319 19:55:53.157380 <5>[ 92.237989] random: crng reseeded on system resumption
11320 19:55:53.160808 <6>[ 92.239992] PM: suspend exit
11321 19:55:53.161363 rror
11322 19:55:53.167671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11323 19:55:53.168281 + set +x
11324 19:55:53.168966 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11326 19:55:53.170402 <LAVA_SIGNAL_ENDRUN 0_sleep 11899575_1.5.2.3.1>
11327 19:55:53.171124 Received signal: <ENDRUN> 0_sleep 11899575_1.5.2.3.1
11328 19:55:53.171563 Ending use of test pattern.
11329 19:55:53.171910 Ending test lava.0_sleep (11899575_1.5.2.3.1), duration 71.64
11331 19:55:53.173678 <LAVA_TEST_RUNNER EXIT>
11332 19:55:53.174396 ok: lava_test_shell seems to have completed
11333 19:55:53.175295 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-2: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-8: fail
11334 19:55:53.175770 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11335 19:55:53.176324 end: 3 lava-test-retry (duration 00:01:12) [common]
11336 19:55:53.176809 start: 4 finalize (timeout 00:06:11) [common]
11337 19:55:53.177284 start: 4.1 power-off (timeout 00:00:30) [common]
11338 19:55:53.178090 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11339 19:55:53.261192 >> Command sent successfully.
11340 19:55:53.273130 Returned 0 in 0 seconds
11341 19:55:53.374878 end: 4.1 power-off (duration 00:00:00) [common]
11343 19:55:53.376548 start: 4.2 read-feedback (timeout 00:06:11) [common]
11344 19:55:53.378113 Listened to connection for namespace 'common' for up to 1s
11345 19:55:54.378623 Finalising connection for namespace 'common'
11346 19:55:54.379356 Disconnecting from shell: Finalise
11347 19:55:54.379809 / #
11348 19:55:54.480837 end: 4.2 read-feedback (duration 00:00:01) [common]
11349 19:55:54.481569 end: 4 finalize (duration 00:00:01) [common]
11350 19:55:54.482191 Cleaning after the job
11351 19:55:54.482735 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/ramdisk
11352 19:55:54.530041 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/kernel
11353 19:55:54.559068 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/dtb
11354 19:55:54.559291 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899575/tftp-deploy-vq85ut5t/modules
11355 19:55:54.566659 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11899575
11356 19:55:54.737276 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11899575
11357 19:55:54.737454 Job finished correctly