Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 19
- Kernel Errors: 27
- Errors: 3
- Boot result: FAIL
1 19:56:02.577637 lava-dispatcher, installed at version: 2023.08
2 19:56:02.577855 start: 0 validate
3 19:56:02.577994 Start time: 2023-10-28 19:56:02.577986+00:00 (UTC)
4 19:56:02.578124 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:56:02.578258 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 19:56:02.841296 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:56:02.841565 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:56:03.107634 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:56:03.107860 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:56:03.373209 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:56:03.373395 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:56:03.640048 validate duration: 1.06
14 19:56:03.640332 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:56:03.640434 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:56:03.640522 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:56:03.640652 Not decompressing ramdisk as can be used compressed.
18 19:56:03.640744 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 19:56:03.640812 saving as /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/ramdisk/rootfs.cpio.gz
20 19:56:03.640881 total size: 8181372 (7 MB)
21 19:56:03.642009 progress 0 % (0 MB)
22 19:56:03.644552 progress 5 % (0 MB)
23 19:56:03.646692 progress 10 % (0 MB)
24 19:56:03.649115 progress 15 % (1 MB)
25 19:56:03.651248 progress 20 % (1 MB)
26 19:56:03.653546 progress 25 % (1 MB)
27 19:56:03.655763 progress 30 % (2 MB)
28 19:56:03.658029 progress 35 % (2 MB)
29 19:56:03.660298 progress 40 % (3 MB)
30 19:56:03.662742 progress 45 % (3 MB)
31 19:56:03.665053 progress 50 % (3 MB)
32 19:56:03.667414 progress 55 % (4 MB)
33 19:56:03.669548 progress 60 % (4 MB)
34 19:56:03.671796 progress 65 % (5 MB)
35 19:56:03.673867 progress 70 % (5 MB)
36 19:56:03.676156 progress 75 % (5 MB)
37 19:56:03.678210 progress 80 % (6 MB)
38 19:56:03.680564 progress 85 % (6 MB)
39 19:56:03.682833 progress 90 % (7 MB)
40 19:56:03.685110 progress 95 % (7 MB)
41 19:56:03.687205 progress 100 % (7 MB)
42 19:56:03.687405 7 MB downloaded in 0.05 s (167.71 MB/s)
43 19:56:03.687565 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:56:03.687846 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:56:03.687933 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:56:03.688018 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:56:03.688158 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:56:03.688232 saving as /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/kernel/Image
50 19:56:03.688294 total size: 49304064 (47 MB)
51 19:56:03.688374 No compression specified
52 19:56:03.689510 progress 0 % (0 MB)
53 19:56:03.702625 progress 5 % (2 MB)
54 19:56:03.715743 progress 10 % (4 MB)
55 19:56:03.728738 progress 15 % (7 MB)
56 19:56:03.741435 progress 20 % (9 MB)
57 19:56:03.754521 progress 25 % (11 MB)
58 19:56:03.767526 progress 30 % (14 MB)
59 19:56:03.780442 progress 35 % (16 MB)
60 19:56:03.793375 progress 40 % (18 MB)
61 19:56:03.806548 progress 45 % (21 MB)
62 19:56:03.819480 progress 50 % (23 MB)
63 19:56:03.832385 progress 55 % (25 MB)
64 19:56:03.845320 progress 60 % (28 MB)
65 19:56:03.858487 progress 65 % (30 MB)
66 19:56:03.871267 progress 70 % (32 MB)
67 19:56:03.884197 progress 75 % (35 MB)
68 19:56:03.897207 progress 80 % (37 MB)
69 19:56:03.910194 progress 85 % (39 MB)
70 19:56:03.923177 progress 90 % (42 MB)
71 19:56:03.936018 progress 95 % (44 MB)
72 19:56:03.948695 progress 100 % (47 MB)
73 19:56:03.948918 47 MB downloaded in 0.26 s (180.42 MB/s)
74 19:56:03.949072 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:56:03.949326 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:56:03.949419 start: 1.3 download-retry (timeout 00:10:00) [common]
78 19:56:03.949507 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 19:56:03.949648 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:56:03.949723 saving as /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/dtb/mt8192-asurada-spherion-r0.dtb
81 19:56:03.949790 total size: 47278 (0 MB)
82 19:56:03.949855 No compression specified
83 19:56:03.950957 progress 69 % (0 MB)
84 19:56:03.951249 progress 100 % (0 MB)
85 19:56:03.951421 0 MB downloaded in 0.00 s (27.68 MB/s)
86 19:56:03.951544 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:56:03.951820 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:56:03.951907 start: 1.4 download-retry (timeout 00:10:00) [common]
90 19:56:03.951990 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 19:56:03.952107 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:56:03.952181 saving as /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/modules/modules.tar
93 19:56:03.952244 total size: 8635496 (8 MB)
94 19:56:03.952307 Using unxz to decompress xz
95 19:56:03.956639 progress 0 % (0 MB)
96 19:56:03.978618 progress 5 % (0 MB)
97 19:56:04.001900 progress 10 % (0 MB)
98 19:56:04.028319 progress 15 % (1 MB)
99 19:56:04.053986 progress 20 % (1 MB)
100 19:56:04.080480 progress 25 % (2 MB)
101 19:56:04.108571 progress 30 % (2 MB)
102 19:56:04.133278 progress 35 % (2 MB)
103 19:56:04.158568 progress 40 % (3 MB)
104 19:56:04.182941 progress 45 % (3 MB)
105 19:56:04.209637 progress 50 % (4 MB)
106 19:56:04.234889 progress 55 % (4 MB)
107 19:56:04.262589 progress 60 % (4 MB)
108 19:56:04.286305 progress 65 % (5 MB)
109 19:56:04.311904 progress 70 % (5 MB)
110 19:56:04.336109 progress 75 % (6 MB)
111 19:56:04.362476 progress 80 % (6 MB)
112 19:56:04.394912 progress 85 % (7 MB)
113 19:56:04.421247 progress 90 % (7 MB)
114 19:56:04.445994 progress 95 % (7 MB)
115 19:56:04.469138 progress 100 % (8 MB)
116 19:56:04.474667 8 MB downloaded in 0.52 s (15.76 MB/s)
117 19:56:04.474960 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:56:04.475381 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:56:04.475513 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 19:56:04.475691 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 19:56:04.475812 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:56:04.475947 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 19:56:04.476231 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak
125 19:56:04.476434 makedir: /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin
126 19:56:04.476581 makedir: /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/tests
127 19:56:04.476721 makedir: /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/results
128 19:56:04.476873 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-add-keys
129 19:56:04.477062 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-add-sources
130 19:56:04.477232 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-background-process-start
131 19:56:04.477401 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-background-process-stop
132 19:56:04.477563 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-common-functions
133 19:56:04.477729 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-echo-ipv4
134 19:56:04.477892 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-install-packages
135 19:56:04.478054 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-installed-packages
136 19:56:04.478218 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-os-build
137 19:56:04.478383 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-probe-channel
138 19:56:04.478545 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-probe-ip
139 19:56:04.478711 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-target-ip
140 19:56:04.478873 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-target-mac
141 19:56:04.479036 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-target-storage
142 19:56:04.479205 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-test-case
143 19:56:04.479369 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-test-event
144 19:56:04.479529 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-test-feedback
145 19:56:04.479741 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-test-raise
146 19:56:04.479915 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-test-reference
147 19:56:04.480095 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-test-runner
148 19:56:04.480264 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-test-set
149 19:56:04.480432 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-test-shell
150 19:56:04.480606 Updating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-install-packages (oe)
151 19:56:04.480815 Updating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/bin/lava-installed-packages (oe)
152 19:56:04.480976 Creating /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/environment
153 19:56:04.481113 LAVA metadata
154 19:56:04.481216 - LAVA_JOB_ID=11899601
155 19:56:04.481314 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:56:04.481455 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 19:56:04.481550 skipped lava-vland-overlay
158 19:56:04.481661 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:56:04.481784 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 19:56:04.481885 skipped lava-multinode-overlay
161 19:56:04.481991 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:56:04.482109 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 19:56:04.482218 Loading test definitions
164 19:56:04.482349 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 19:56:04.482470 Using /lava-11899601 at stage 0
166 19:56:04.482943 uuid=11899601_1.5.2.3.1 testdef=None
167 19:56:04.483064 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 19:56:04.483188 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 19:56:04.484032 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 19:56:04.484396 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 19:56:04.485395 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 19:56:04.485814 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 19:56:04.486766 runner path: /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/0/tests/0_dmesg test_uuid 11899601_1.5.2.3.1
176 19:56:04.487002 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 19:56:04.487429 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 19:56:04.487547 Using /lava-11899601 at stage 1
180 19:56:04.488090 uuid=11899601_1.5.2.3.5 testdef=None
181 19:56:04.488241 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 19:56:04.488371 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 19:56:04.489139 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 19:56:04.489510 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 19:56:04.491057 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 19:56:04.491453 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 19:56:04.492478 runner path: /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/1/tests/1_bootrr test_uuid 11899601_1.5.2.3.5
190 19:56:04.492680 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 19:56:04.493036 Creating lava-test-runner.conf files
193 19:56:04.493145 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/0 for stage 0
194 19:56:04.493271 - 0_dmesg
195 19:56:04.493391 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899601/lava-overlay-wuuavzak/lava-11899601/1 for stage 1
196 19:56:04.493518 - 1_bootrr
197 19:56:04.493650 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 19:56:04.493769 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 19:56:04.504139 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 19:56:04.504283 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 19:56:04.504403 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 19:56:04.504524 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 19:56:04.504644 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 19:56:04.759832 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 19:56:04.760269 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 19:56:04.760423 extracting modules file /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899601/extract-overlay-ramdisk-ufyvn4ww/ramdisk
207 19:56:05.082308 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 19:56:05.082506 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
209 19:56:05.082645 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899601/compress-overlay-ez90bjkc/overlay-1.5.2.4.tar.gz to ramdisk
210 19:56:05.082739 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899601/compress-overlay-ez90bjkc/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11899601/extract-overlay-ramdisk-ufyvn4ww/ramdisk
211 19:56:05.096078 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 19:56:05.096234 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
213 19:56:05.096364 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 19:56:05.096488 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
215 19:56:05.096599 Building ramdisk /var/lib/lava/dispatcher/tmp/11899601/extract-overlay-ramdisk-ufyvn4ww/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11899601/extract-overlay-ramdisk-ufyvn4ww/ramdisk
216 19:56:05.465190 >> 145288 blocks
217 19:56:07.802579 rename /var/lib/lava/dispatcher/tmp/11899601/extract-overlay-ramdisk-ufyvn4ww/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/ramdisk/ramdisk.cpio.gz
218 19:56:07.803091 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 19:56:07.803252 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 19:56:07.803398 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 19:56:07.803554 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/kernel/Image'
222 19:56:20.502493 Returned 0 in 12 seconds
223 19:56:20.603130 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/kernel/image.itb
224 19:56:21.007165 output: FIT description: Kernel Image image with one or more FDT blobs
225 19:56:21.007555 output: Created: Sat Oct 28 20:56:20 2023
226 19:56:21.007635 output: Image 0 (kernel-1)
227 19:56:21.007748 output: Description:
228 19:56:21.007815 output: Created: Sat Oct 28 20:56:20 2023
229 19:56:21.007903 output: Type: Kernel Image
230 19:56:21.007971 output: Compression: lzma compressed
231 19:56:21.008033 output: Data Size: 11047522 Bytes = 10788.60 KiB = 10.54 MiB
232 19:56:21.008095 output: Architecture: AArch64
233 19:56:21.008154 output: OS: Linux
234 19:56:21.008215 output: Load Address: 0x00000000
235 19:56:21.008276 output: Entry Point: 0x00000000
236 19:56:21.008332 output: Hash algo: crc32
237 19:56:21.008394 output: Hash value: da40eda2
238 19:56:21.008473 output: Image 1 (fdt-1)
239 19:56:21.008534 output: Description: mt8192-asurada-spherion-r0
240 19:56:21.008594 output: Created: Sat Oct 28 20:56:20 2023
241 19:56:21.008650 output: Type: Flat Device Tree
242 19:56:21.008705 output: Compression: uncompressed
243 19:56:21.008760 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 19:56:21.008815 output: Architecture: AArch64
245 19:56:21.008870 output: Hash algo: crc32
246 19:56:21.008924 output: Hash value: cc4352de
247 19:56:21.008979 output: Image 2 (ramdisk-1)
248 19:56:21.009051 output: Description: unavailable
249 19:56:21.009110 output: Created: Sat Oct 28 20:56:20 2023
250 19:56:21.009164 output: Type: RAMDisk Image
251 19:56:21.009219 output: Compression: Unknown Compression
252 19:56:21.009273 output: Data Size: 21394895 Bytes = 20893.45 KiB = 20.40 MiB
253 19:56:21.009328 output: Architecture: AArch64
254 19:56:21.009382 output: OS: Linux
255 19:56:21.009436 output: Load Address: unavailable
256 19:56:21.009490 output: Entry Point: unavailable
257 19:56:21.009545 output: Hash algo: crc32
258 19:56:21.009609 output: Hash value: b1100a9c
259 19:56:21.009670 output: Default Configuration: 'conf-1'
260 19:56:21.009724 output: Configuration 0 (conf-1)
261 19:56:21.009779 output: Description: mt8192-asurada-spherion-r0
262 19:56:21.009832 output: Kernel: kernel-1
263 19:56:21.009886 output: Init Ramdisk: ramdisk-1
264 19:56:21.009941 output: FDT: fdt-1
265 19:56:21.009995 output: Loadables: kernel-1
266 19:56:21.010048 output:
267 19:56:21.010259 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 19:56:21.010391 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 19:56:21.010496 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 19:56:21.010594 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
271 19:56:21.010675 No LXC device requested
272 19:56:21.010758 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 19:56:21.010846 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
274 19:56:21.010924 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 19:56:21.010996 Checking files for TFTP limit of 4294967296 bytes.
276 19:56:21.011494 end: 1 tftp-deploy (duration 00:00:17) [common]
277 19:56:21.011598 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 19:56:21.011732 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 19:56:21.011851 substitutions:
280 19:56:21.011918 - {DTB}: 11899601/tftp-deploy-4azv24sg/dtb/mt8192-asurada-spherion-r0.dtb
281 19:56:21.011983 - {INITRD}: 11899601/tftp-deploy-4azv24sg/ramdisk/ramdisk.cpio.gz
282 19:56:21.012043 - {KERNEL}: 11899601/tftp-deploy-4azv24sg/kernel/Image
283 19:56:21.012103 - {LAVA_MAC}: None
284 19:56:21.012161 - {PRESEED_CONFIG}: None
285 19:56:21.012218 - {PRESEED_LOCAL}: None
286 19:56:21.012274 - {RAMDISK}: 11899601/tftp-deploy-4azv24sg/ramdisk/ramdisk.cpio.gz
287 19:56:21.012331 - {ROOT_PART}: None
288 19:56:21.012386 - {ROOT}: None
289 19:56:21.012442 - {SERVER_IP}: 192.168.201.1
290 19:56:21.012497 - {TEE}: None
291 19:56:21.012553 Parsed boot commands:
292 19:56:21.012607 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 19:56:21.012787 Parsed boot commands: tftpboot 192.168.201.1 11899601/tftp-deploy-4azv24sg/kernel/image.itb 11899601/tftp-deploy-4azv24sg/kernel/cmdline
294 19:56:21.012878 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 19:56:21.012967 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 19:56:21.013062 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 19:56:21.013147 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 19:56:21.013218 Not connected, no need to disconnect.
299 19:56:21.013295 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 19:56:21.013378 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 19:56:21.013447 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
302 19:56:21.017543 Setting prompt string to ['lava-test: # ']
303 19:56:21.017945 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 19:56:21.018059 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 19:56:21.018165 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 19:56:21.018434 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 19:56:21.018672 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
308 19:56:26.156560 >> Command sent successfully.
309 19:56:26.158951 Returned 0 in 5 seconds
310 19:56:26.259346 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 19:56:26.259722 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 19:56:26.259823 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 19:56:26.259917 Setting prompt string to 'Starting depthcharge on Spherion...'
315 19:56:26.259989 Changing prompt to 'Starting depthcharge on Spherion...'
316 19:56:26.260057 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 19:56:26.260327 [Enter `^Ec?' for help]
318 19:56:26.432511
319 19:56:26.432669
320 19:56:26.432744 F0: 102B 0000
321 19:56:26.432816
322 19:56:26.432879 F3: 1001 0000 [0200]
323 19:56:26.432939
324 19:56:26.435733 F3: 1001 0000
325 19:56:26.435817
326 19:56:26.435884 F7: 102D 0000
327 19:56:26.435947
328 19:56:26.438948 F1: 0000 0000
329 19:56:26.439032
330 19:56:26.439100 V0: 0000 0000 [0001]
331 19:56:26.439166
332 19:56:26.442325 00: 0007 8000
333 19:56:26.442412
334 19:56:26.442479 01: 0000 0000
335 19:56:26.442542
336 19:56:26.445596 BP: 0C00 0209 [0000]
337 19:56:26.445680
338 19:56:26.445747 G0: 1182 0000
339 19:56:26.445810
340 19:56:26.445869 EC: 0000 0021 [4000]
341 19:56:26.449365
342 19:56:26.449449 S7: 0000 0000 [0000]
343 19:56:26.449516
344 19:56:26.449578 CC: 0000 0000 [0001]
345 19:56:26.453104
346 19:56:26.453188 T0: 0000 0040 [010F]
347 19:56:26.453256
348 19:56:26.453317 Jump to BL
349 19:56:26.453376
350 19:56:26.479474
351 19:56:26.479559
352 19:56:26.479625
353 19:56:26.487319 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 19:56:26.490987 ARM64: Exception handlers installed.
355 19:56:26.494336 ARM64: Testing exception
356 19:56:26.497670 ARM64: Done test exception
357 19:56:26.504583 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 19:56:26.514702 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 19:56:26.521390 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 19:56:26.531238 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 19:56:26.538406 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 19:56:26.544843 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 19:56:26.556111 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 19:56:26.562796 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 19:56:26.582046 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 19:56:26.585410 WDT: Last reset was cold boot
367 19:56:26.588689 SPI1(PAD0) initialized at 2873684 Hz
368 19:56:26.592466 SPI5(PAD0) initialized at 992727 Hz
369 19:56:26.595574 VBOOT: Loading verstage.
370 19:56:26.602207 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 19:56:26.605462 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 19:56:26.609060 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 19:56:26.612091 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 19:56:26.619594 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 19:56:26.626260 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 19:56:26.637296 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 19:56:26.637382
378 19:56:26.637497
379 19:56:26.648111 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 19:56:26.651542 ARM64: Exception handlers installed.
381 19:56:26.651627 ARM64: Testing exception
382 19:56:26.654844 ARM64: Done test exception
383 19:56:26.657884 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 19:56:26.664948 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 19:56:26.678469 Probing TPM: . done!
386 19:56:26.678554 TPM ready after 0 ms
387 19:56:26.685291 Connected to device vid:did:rid of 1ae0:0028:00
388 19:56:26.692454 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 19:56:26.752377 Initialized TPM device CR50 revision 0
390 19:56:26.763718 tlcl_send_startup: Startup return code is 0
391 19:56:26.763885 TPM: setup succeeded
392 19:56:26.775156 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 19:56:26.784592 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 19:56:26.797381 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 19:56:26.805457 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 19:56:26.808542 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 19:56:26.813187 in-header: 03 07 00 00 08 00 00 00
398 19:56:26.817092 in-data: aa e4 47 04 13 02 00 00
399 19:56:26.820801 Chrome EC: UHEPI supported
400 19:56:26.827681 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 19:56:26.831440 in-header: 03 95 00 00 08 00 00 00
402 19:56:26.831779 in-data: 18 20 20 08 00 00 00 00
403 19:56:26.835804 Phase 1
404 19:56:26.839958 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 19:56:26.843609 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 19:56:26.850707 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 19:56:26.854247 Recovery requested (1009000e)
408 19:56:26.864326 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 19:56:26.867832 tlcl_extend: response is 0
410 19:56:26.876657 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 19:56:26.882198 tlcl_extend: response is 0
412 19:56:26.889462 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 19:56:26.908881 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 19:56:26.915463 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 19:56:26.915993
416 19:56:26.916377
417 19:56:26.925116 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 19:56:26.928922 ARM64: Exception handlers installed.
419 19:56:26.932152 ARM64: Testing exception
420 19:56:26.932649 ARM64: Done test exception
421 19:56:26.954896 pmic_efuse_setting: Set efuses in 11 msecs
422 19:56:26.958160 pmwrap_interface_init: Select PMIF_VLD_RDY
423 19:56:26.964998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 19:56:26.968242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 19:56:26.972122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 19:56:26.979629 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 19:56:26.983565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 19:56:26.987365 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 19:56:26.994436 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 19:56:26.998172 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 19:56:27.001466 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 19:56:27.005601 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 19:56:27.012833 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 19:56:27.016167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 19:56:27.019956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 19:56:27.027777 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 19:56:27.031583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 19:56:27.039247 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 19:56:27.043339 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 19:56:27.050406 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 19:56:27.054236 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 19:56:27.061684 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 19:56:27.064866 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 19:56:27.072452 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 19:56:27.076286 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 19:56:27.084135 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 19:56:27.087696 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 19:56:27.095063 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 19:56:27.098935 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 19:56:27.102319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 19:56:27.109636 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 19:56:27.113247 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 19:56:27.117125 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 19:56:27.124086 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 19:56:27.128117 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 19:56:27.135534 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 19:56:27.138924 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 19:56:27.142922 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 19:56:27.150289 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 19:56:27.154093 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 19:56:27.157451 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 19:56:27.161750 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 19:56:27.164692 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 19:56:27.172191 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 19:56:27.176451 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 19:56:27.179841 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 19:56:27.183869 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 19:56:27.187831 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 19:56:27.190753 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 19:56:27.198356 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 19:56:27.202175 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 19:56:27.205292 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 19:56:27.209723 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 19:56:27.216743 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 19:56:27.223908 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 19:56:27.231869 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 19:56:27.238856 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 19:56:27.246670 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 19:56:27.250351 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 19:56:27.258267 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 19:56:27.262314 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 19:56:27.269384 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
483 19:56:27.273010 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 19:56:27.276740 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 19:56:27.280390 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 19:56:27.291740 [RTC]rtc_get_frequency_meter,154: input=15, output=760
487 19:56:27.300960 [RTC]rtc_get_frequency_meter,154: input=23, output=941
488 19:56:27.310565 [RTC]rtc_get_frequency_meter,154: input=19, output=851
489 19:56:27.319963 [RTC]rtc_get_frequency_meter,154: input=17, output=805
490 19:56:27.330343 [RTC]rtc_get_frequency_meter,154: input=16, output=781
491 19:56:27.339752 [RTC]rtc_get_frequency_meter,154: input=16, output=781
492 19:56:27.349239 [RTC]rtc_get_frequency_meter,154: input=17, output=804
493 19:56:27.352462 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 19:56:27.360107 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 19:56:27.363827 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 19:56:27.368031 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 19:56:27.371444 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 19:56:27.375400 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 19:56:27.379300 ADC[4]: Raw value=906203 ID=7
500 19:56:27.379934 ADC[3]: Raw value=213441 ID=1
501 19:56:27.383147 RAM Code: 0x71
502 19:56:27.386964 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 19:56:27.390676 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 19:56:27.401445 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 19:56:27.405361 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 19:56:27.408576 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 19:56:27.412591 in-header: 03 07 00 00 08 00 00 00
508 19:56:27.416163 in-data: aa e4 47 04 13 02 00 00
509 19:56:27.419736 Chrome EC: UHEPI supported
510 19:56:27.426833 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 19:56:27.431317 in-header: 03 95 00 00 08 00 00 00
512 19:56:27.434745 in-data: 18 20 20 08 00 00 00 00
513 19:56:27.435181 MRC: failed to locate region type 0.
514 19:56:27.442039 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 19:56:27.445948 DRAM-K: Running full calibration
516 19:56:27.453260 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 19:56:27.453710 header.status = 0x0
518 19:56:27.456802 header.version = 0x6 (expected: 0x6)
519 19:56:27.460619 header.size = 0xd00 (expected: 0xd00)
520 19:56:27.461059 header.flags = 0x0
521 19:56:27.467716 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 19:56:27.486229 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
523 19:56:27.494442 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 19:56:27.498251 dram_init: ddr_geometry: 2
525 19:56:27.498794 [EMI] MDL number = 2
526 19:56:27.502008 [EMI] Get MDL freq = 0
527 19:56:27.502544 dram_init: ddr_type: 0
528 19:56:27.505610 is_discrete_lpddr4: 1
529 19:56:27.506048 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 19:56:27.506397
531 19:56:27.509793
532 19:56:27.510329 [Bian_co] ETT version 0.0.0.1
533 19:56:27.513190 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 19:56:27.516950
535 19:56:27.520739 dramc_set_vcore_voltage set vcore to 650000
536 19:56:27.521256 Read voltage for 800, 4
537 19:56:27.521620 Vio18 = 0
538 19:56:27.524239 Vcore = 650000
539 19:56:27.524673 Vdram = 0
540 19:56:27.525088 Vddq = 0
541 19:56:27.525427 Vmddr = 0
542 19:56:27.528364 dram_init: config_dvfs: 1
543 19:56:27.531746 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 19:56:27.539839 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 19:56:27.543491 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
546 19:56:27.547766 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
547 19:56:27.551300 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
548 19:56:27.554961 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
549 19:56:27.555404 MEM_TYPE=3, freq_sel=18
550 19:56:27.558168 sv_algorithm_assistance_LP4_1600
551 19:56:27.565199 ============ PULL DRAM RESETB DOWN ============
552 19:56:27.568519 ========== PULL DRAM RESETB DOWN end =========
553 19:56:27.571720 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 19:56:27.575185 ===================================
555 19:56:27.578578 LPDDR4 DRAM CONFIGURATION
556 19:56:27.582261 ===================================
557 19:56:27.582733 EX_ROW_EN[0] = 0x0
558 19:56:27.586383 EX_ROW_EN[1] = 0x0
559 19:56:27.587068 LP4Y_EN = 0x0
560 19:56:27.589847 WORK_FSP = 0x0
561 19:56:27.590330 WL = 0x2
562 19:56:27.593429 RL = 0x2
563 19:56:27.593886 BL = 0x2
564 19:56:27.594351 RPST = 0x0
565 19:56:27.597562 RD_PRE = 0x0
566 19:56:27.598253 WR_PRE = 0x1
567 19:56:27.601044 WR_PST = 0x0
568 19:56:27.601512 DBI_WR = 0x0
569 19:56:27.605043 DBI_RD = 0x0
570 19:56:27.605571 OTF = 0x1
571 19:56:27.607953 ===================================
572 19:56:27.611105 ===================================
573 19:56:27.614485 ANA top config
574 19:56:27.618240 ===================================
575 19:56:27.621216 DLL_ASYNC_EN = 0
576 19:56:27.621722 ALL_SLAVE_EN = 1
577 19:56:27.624400 NEW_RANK_MODE = 1
578 19:56:27.627803 DLL_IDLE_MODE = 1
579 19:56:27.631759 LP45_APHY_COMB_EN = 1
580 19:56:27.632286 TX_ODT_DIS = 1
581 19:56:27.634824 NEW_8X_MODE = 1
582 19:56:27.638504 ===================================
583 19:56:27.641942 ===================================
584 19:56:27.645192 data_rate = 1600
585 19:56:27.648470 CKR = 1
586 19:56:27.648908 DQ_P2S_RATIO = 8
587 19:56:27.651889 ===================================
588 19:56:27.655411 CA_P2S_RATIO = 8
589 19:56:27.658374 DQ_CA_OPEN = 0
590 19:56:27.661661 DQ_SEMI_OPEN = 0
591 19:56:27.665595 CA_SEMI_OPEN = 0
592 19:56:27.668598 CA_FULL_RATE = 0
593 19:56:27.669134 DQ_CKDIV4_EN = 1
594 19:56:27.672096 CA_CKDIV4_EN = 1
595 19:56:27.675796 CA_PREDIV_EN = 0
596 19:56:27.679263 PH8_DLY = 0
597 19:56:27.682169 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 19:56:27.685407 DQ_AAMCK_DIV = 4
599 19:56:27.685937 CA_AAMCK_DIV = 4
600 19:56:27.688470 CA_ADMCK_DIV = 4
601 19:56:27.692024 DQ_TRACK_CA_EN = 0
602 19:56:27.695713 CA_PICK = 800
603 19:56:27.698964 CA_MCKIO = 800
604 19:56:27.702034 MCKIO_SEMI = 0
605 19:56:27.702484 PLL_FREQ = 3068
606 19:56:27.705702 DQ_UI_PI_RATIO = 32
607 19:56:27.709875 CA_UI_PI_RATIO = 0
608 19:56:27.713014 ===================================
609 19:56:27.717412 ===================================
610 19:56:27.717858 memory_type:LPDDR4
611 19:56:27.721201 GP_NUM : 10
612 19:56:27.721647 SRAM_EN : 1
613 19:56:27.724932 MD32_EN : 0
614 19:56:27.728164 ===================================
615 19:56:27.728607 [ANA_INIT] >>>>>>>>>>>>>>
616 19:56:27.731939 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 19:56:27.735751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 19:56:27.739036 ===================================
619 19:56:27.742799 data_rate = 1600,PCW = 0X7600
620 19:56:27.746264 ===================================
621 19:56:27.749146 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 19:56:27.756202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 19:56:27.759770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 19:56:27.766390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 19:56:27.769572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 19:56:27.773091 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 19:56:27.773531 [ANA_INIT] flow start
628 19:56:27.776500 [ANA_INIT] PLL >>>>>>>>
629 19:56:27.779583 [ANA_INIT] PLL <<<<<<<<
630 19:56:27.780167 [ANA_INIT] MIDPI >>>>>>>>
631 19:56:27.783369 [ANA_INIT] MIDPI <<<<<<<<
632 19:56:27.786602 [ANA_INIT] DLL >>>>>>>>
633 19:56:27.787147 [ANA_INIT] flow end
634 19:56:27.789443 ============ LP4 DIFF to SE enter ============
635 19:56:27.796498 ============ LP4 DIFF to SE exit ============
636 19:56:27.797021 [ANA_INIT] <<<<<<<<<<<<<
637 19:56:27.799759 [Flow] Enable top DCM control >>>>>
638 19:56:27.803310 [Flow] Enable top DCM control <<<<<
639 19:56:27.806395 Enable DLL master slave shuffle
640 19:56:27.813221 ==============================================================
641 19:56:27.813827 Gating Mode config
642 19:56:27.819701 ==============================================================
643 19:56:27.823292 Config description:
644 19:56:27.833419 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 19:56:27.836902 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 19:56:27.843119 SELPH_MODE 0: By rank 1: By Phase
647 19:56:27.850125 ==============================================================
648 19:56:27.850657 GAT_TRACK_EN = 1
649 19:56:27.853388 RX_GATING_MODE = 2
650 19:56:27.856490 RX_GATING_TRACK_MODE = 2
651 19:56:27.860366 SELPH_MODE = 1
652 19:56:27.863736 PICG_EARLY_EN = 1
653 19:56:27.866647 VALID_LAT_VALUE = 1
654 19:56:27.873274 ==============================================================
655 19:56:27.876487 Enter into Gating configuration >>>>
656 19:56:27.880096 Exit from Gating configuration <<<<
657 19:56:27.883538 Enter into DVFS_PRE_config >>>>>
658 19:56:27.893539 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 19:56:27.896796 Exit from DVFS_PRE_config <<<<<
660 19:56:27.900197 Enter into PICG configuration >>>>
661 19:56:27.903630 Exit from PICG configuration <<<<
662 19:56:27.904223 [RX_INPUT] configuration >>>>>
663 19:56:27.907224 [RX_INPUT] configuration <<<<<
664 19:56:27.913502 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 19:56:27.917046 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 19:56:27.923921 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 19:56:27.930197 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 19:56:27.937032 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 19:56:27.943461 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 19:56:27.947338 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 19:56:27.950523 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 19:56:27.954277 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 19:56:27.960606 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 19:56:27.964525 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 19:56:27.967534 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 19:56:27.970781 ===================================
677 19:56:27.973625 LPDDR4 DRAM CONFIGURATION
678 19:56:27.977248 ===================================
679 19:56:27.981107 EX_ROW_EN[0] = 0x0
680 19:56:27.981653 EX_ROW_EN[1] = 0x0
681 19:56:27.983980 LP4Y_EN = 0x0
682 19:56:27.984514 WORK_FSP = 0x0
683 19:56:27.987002 WL = 0x2
684 19:56:27.987443 RL = 0x2
685 19:56:27.990413 BL = 0x2
686 19:56:27.990899 RPST = 0x0
687 19:56:27.993721 RD_PRE = 0x0
688 19:56:27.994162 WR_PRE = 0x1
689 19:56:27.997867 WR_PST = 0x0
690 19:56:27.998417 DBI_WR = 0x0
691 19:56:28.001139 DBI_RD = 0x0
692 19:56:28.001692 OTF = 0x1
693 19:56:28.004366 ===================================
694 19:56:28.007379 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 19:56:28.013854 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 19:56:28.017889 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 19:56:28.020768 ===================================
698 19:56:28.023847 LPDDR4 DRAM CONFIGURATION
699 19:56:28.027141 ===================================
700 19:56:28.027587 EX_ROW_EN[0] = 0x10
701 19:56:28.030857 EX_ROW_EN[1] = 0x0
702 19:56:28.031332 LP4Y_EN = 0x0
703 19:56:28.034125 WORK_FSP = 0x0
704 19:56:28.034566 WL = 0x2
705 19:56:28.038043 RL = 0x2
706 19:56:28.040892 BL = 0x2
707 19:56:28.041362 RPST = 0x0
708 19:56:28.044020 RD_PRE = 0x0
709 19:56:28.044464 WR_PRE = 0x1
710 19:56:28.047550 WR_PST = 0x0
711 19:56:28.048125 DBI_WR = 0x0
712 19:56:28.051061 DBI_RD = 0x0
713 19:56:28.051626 OTF = 0x1
714 19:56:28.053836 ===================================
715 19:56:28.060862 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 19:56:28.064532 nWR fixed to 40
717 19:56:28.068228 [ModeRegInit_LP4] CH0 RK0
718 19:56:28.068778 [ModeRegInit_LP4] CH0 RK1
719 19:56:28.072143 [ModeRegInit_LP4] CH1 RK0
720 19:56:28.074414 [ModeRegInit_LP4] CH1 RK1
721 19:56:28.074856 match AC timing 13
722 19:56:28.081558 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 19:56:28.085300 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 19:56:28.088242 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 19:56:28.094476 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 19:56:28.098524 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 19:56:28.099073 [EMI DOE] emi_dcm 0
728 19:56:28.105241 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 19:56:28.105791 ==
730 19:56:28.107762 Dram Type= 6, Freq= 0, CH_0, rank 0
731 19:56:28.111457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 19:56:28.111998 ==
733 19:56:28.118518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 19:56:28.121302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 19:56:28.131721 [CA 0] Center 36 (6~67) winsize 62
736 19:56:28.135608 [CA 1] Center 36 (6~67) winsize 62
737 19:56:28.138856 [CA 2] Center 34 (4~65) winsize 62
738 19:56:28.141983 [CA 3] Center 33 (3~64) winsize 62
739 19:56:28.145731 [CA 4] Center 33 (3~64) winsize 62
740 19:56:28.148639 [CA 5] Center 32 (2~62) winsize 61
741 19:56:28.149183
742 19:56:28.152205 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 19:56:28.152765
744 19:56:28.155390 [CATrainingPosCal] consider 1 rank data
745 19:56:28.158866 u2DelayCellTimex100 = 270/100 ps
746 19:56:28.162301 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
747 19:56:28.165470 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
748 19:56:28.172135 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
749 19:56:28.175142 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
750 19:56:28.179109 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
751 19:56:28.181983 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
752 19:56:28.182533
753 19:56:28.185659 CA PerBit enable=1, Macro0, CA PI delay=32
754 19:56:28.186209
755 19:56:28.188337 [CBTSetCACLKResult] CA Dly = 32
756 19:56:28.188914 CS Dly: 5 (0~36)
757 19:56:28.189454 ==
758 19:56:28.192259 Dram Type= 6, Freq= 0, CH_0, rank 1
759 19:56:28.198545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 19:56:28.199095 ==
761 19:56:28.202176 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 19:56:28.208398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 19:56:28.218363 [CA 0] Center 36 (6~67) winsize 62
764 19:56:28.221330 [CA 1] Center 36 (6~67) winsize 62
765 19:56:28.224551 [CA 2] Center 34 (4~65) winsize 62
766 19:56:28.228380 [CA 3] Center 34 (4~65) winsize 62
767 19:56:28.231524 [CA 4] Center 32 (2~63) winsize 62
768 19:56:28.235172 [CA 5] Center 32 (2~63) winsize 62
769 19:56:28.235763
770 19:56:28.238162 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 19:56:28.238651
772 19:56:28.241430 [CATrainingPosCal] consider 2 rank data
773 19:56:28.245055 u2DelayCellTimex100 = 270/100 ps
774 19:56:28.248012 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
775 19:56:28.251333 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
776 19:56:28.258535 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
777 19:56:28.261432 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
778 19:56:28.264837 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
779 19:56:28.268078 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
780 19:56:28.268626
781 19:56:28.271734 CA PerBit enable=1, Macro0, CA PI delay=32
782 19:56:28.272183
783 19:56:28.274730 [CBTSetCACLKResult] CA Dly = 32
784 19:56:28.275168 CS Dly: 5 (0~37)
785 19:56:28.275615
786 19:56:28.278483 ----->DramcWriteLeveling(PI) begin...
787 19:56:28.281586 ==
788 19:56:28.282029 Dram Type= 6, Freq= 0, CH_0, rank 0
789 19:56:28.285841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 19:56:28.289476 ==
791 19:56:28.289920 Write leveling (Byte 0): 34 => 34
792 19:56:28.293533 Write leveling (Byte 1): 31 => 31
793 19:56:28.296852 DramcWriteLeveling(PI) end<-----
794 19:56:28.297440
795 19:56:28.297903 ==
796 19:56:28.300103 Dram Type= 6, Freq= 0, CH_0, rank 0
797 19:56:28.303213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 19:56:28.303691 ==
799 19:56:28.306881 [Gating] SW mode calibration
800 19:56:28.313909 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 19:56:28.320975 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 19:56:28.323824 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 19:56:28.327153 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 19:56:28.334142 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 19:56:28.337761 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 19:56:28.340717 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 19:56:28.347245 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 19:56:28.350809 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 19:56:28.353652 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 19:56:28.361049 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 19:56:28.363997 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 19:56:28.366963 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 19:56:28.371117 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 19:56:28.377378 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 19:56:28.381121 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 19:56:28.383851 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 19:56:28.390800 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 19:56:28.394223 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 19:56:28.397473 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 19:56:28.404325 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
821 19:56:28.407765 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
822 19:56:28.410692 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 19:56:28.417437 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 19:56:28.420775 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 19:56:28.424013 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 19:56:28.430780 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 19:56:28.433934 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
828 19:56:28.437747 0 9 8 | B1->B0 | 2525 3030 | 0 1 | (0 0) (1 1)
829 19:56:28.444276 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
830 19:56:28.447360 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 19:56:28.450865 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 19:56:28.454152 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 19:56:28.460894 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 19:56:28.464225 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 19:56:28.467895 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
836 19:56:28.474182 0 10 8 | B1->B0 | 3232 2424 | 0 0 | (0 1) (0 0)
837 19:56:28.477476 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 19:56:28.481063 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 19:56:28.487839 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 19:56:28.490757 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 19:56:28.494854 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 19:56:28.501019 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 19:56:28.503954 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
844 19:56:28.507718 0 11 8 | B1->B0 | 2929 3f3f | 0 1 | (0 0) (0 0)
845 19:56:28.514190 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
846 19:56:28.517805 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 19:56:28.520870 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 19:56:28.527817 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 19:56:28.531405 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 19:56:28.534403 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 19:56:28.537778 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
852 19:56:28.544295 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
853 19:56:28.547455 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 19:56:28.551229 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 19:56:28.558020 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 19:56:28.560830 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 19:56:28.564557 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 19:56:28.571420 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 19:56:28.574752 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 19:56:28.578070 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 19:56:28.584878 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 19:56:28.588235 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 19:56:28.591393 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 19:56:28.598175 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 19:56:28.601389 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 19:56:28.604461 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 19:56:28.611158 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 19:56:28.614470 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
869 19:56:28.618269 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
870 19:56:28.621457 Total UI for P1: 0, mck2ui 16
871 19:56:28.624446 best dqsien dly found for B0: ( 0, 14, 6)
872 19:56:28.628134 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 19:56:28.631413 Total UI for P1: 0, mck2ui 16
874 19:56:28.635376 best dqsien dly found for B1: ( 0, 14, 12)
875 19:56:28.639324 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
876 19:56:28.642305 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
877 19:56:28.642749
878 19:56:28.645928 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
879 19:56:28.649449 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
880 19:56:28.652234 [Gating] SW calibration Done
881 19:56:28.652702 ==
882 19:56:28.655540 Dram Type= 6, Freq= 0, CH_0, rank 0
883 19:56:28.658841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
884 19:56:28.662513 ==
885 19:56:28.663060 RX Vref Scan: 0
886 19:56:28.663414
887 19:56:28.666245 RX Vref 0 -> 0, step: 1
888 19:56:28.666844
889 19:56:28.669423 RX Delay -130 -> 252, step: 16
890 19:56:28.672397 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
891 19:56:28.676043 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
892 19:56:28.679779 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
893 19:56:28.682411 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
894 19:56:28.689386 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
895 19:56:28.693118 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
896 19:56:28.695776 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
897 19:56:28.699346 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
898 19:56:28.702682 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
899 19:56:28.705772 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
900 19:56:28.712656 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
901 19:56:28.715911 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
902 19:56:28.719696 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
903 19:56:28.722877 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
904 19:56:28.729655 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
905 19:56:28.732659 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
906 19:56:28.733108 ==
907 19:56:28.735924 Dram Type= 6, Freq= 0, CH_0, rank 0
908 19:56:28.739149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
909 19:56:28.739709 ==
910 19:56:28.740224 DQS Delay:
911 19:56:28.743005 DQS0 = 0, DQS1 = 0
912 19:56:28.743436 DQM Delay:
913 19:56:28.745998 DQM0 = 90, DQM1 = 80
914 19:56:28.746424 DQ Delay:
915 19:56:28.749762 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
916 19:56:28.752860 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
917 19:56:28.755986 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
918 19:56:28.759508 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
919 19:56:28.759961
920 19:56:28.760302
921 19:56:28.760618 ==
922 19:56:28.762723 Dram Type= 6, Freq= 0, CH_0, rank 0
923 19:56:28.766082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
924 19:56:28.766511 ==
925 19:56:28.769629
926 19:56:28.770054
927 19:56:28.770391 TX Vref Scan disable
928 19:56:28.773029 == TX Byte 0 ==
929 19:56:28.776425 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
930 19:56:28.779684 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
931 19:56:28.783288 == TX Byte 1 ==
932 19:56:28.786183 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
933 19:56:28.790064 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
934 19:56:28.790607 ==
935 19:56:28.792852 Dram Type= 6, Freq= 0, CH_0, rank 0
936 19:56:28.799743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 19:56:28.800176 ==
938 19:56:28.811583 TX Vref=22, minBit 9, minWin=27, winSum=446
939 19:56:28.815169 TX Vref=24, minBit 9, minWin=27, winSum=449
940 19:56:28.818714 TX Vref=26, minBit 0, minWin=28, winSum=456
941 19:56:28.821443 TX Vref=28, minBit 5, minWin=28, winSum=456
942 19:56:28.825593 TX Vref=30, minBit 5, minWin=28, winSum=457
943 19:56:28.828804 TX Vref=32, minBit 2, minWin=28, winSum=454
944 19:56:28.835352 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 30
945 19:56:28.836034
946 19:56:28.838590 Final TX Range 1 Vref 30
947 19:56:28.839165
948 19:56:28.839754 ==
949 19:56:28.841879 Dram Type= 6, Freq= 0, CH_0, rank 0
950 19:56:28.844981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 19:56:28.845418 ==
952 19:56:28.845766
953 19:56:28.846086
954 19:56:28.848725 TX Vref Scan disable
955 19:56:28.851944 == TX Byte 0 ==
956 19:56:28.855073 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
957 19:56:28.858769 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
958 19:56:28.862030 == TX Byte 1 ==
959 19:56:28.865049 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
960 19:56:28.868443 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
961 19:56:28.871604
962 19:56:28.872073 [DATLAT]
963 19:56:28.872425 Freq=800, CH0 RK0
964 19:56:28.872752
965 19:56:28.875321 DATLAT Default: 0xa
966 19:56:28.875862 0, 0xFFFF, sum = 0
967 19:56:28.878841 1, 0xFFFF, sum = 0
968 19:56:28.879316 2, 0xFFFF, sum = 0
969 19:56:28.881686 3, 0xFFFF, sum = 0
970 19:56:28.882125 4, 0xFFFF, sum = 0
971 19:56:28.884917 5, 0xFFFF, sum = 0
972 19:56:28.885358 6, 0xFFFF, sum = 0
973 19:56:28.888664 7, 0xFFFF, sum = 0
974 19:56:28.889151 8, 0xFFFF, sum = 0
975 19:56:28.891570 9, 0x0, sum = 1
976 19:56:28.892067 10, 0x0, sum = 2
977 19:56:28.895288 11, 0x0, sum = 3
978 19:56:28.895761 12, 0x0, sum = 4
979 19:56:28.898447 best_step = 10
980 19:56:28.898879
981 19:56:28.899241 ==
982 19:56:28.902068 Dram Type= 6, Freq= 0, CH_0, rank 0
983 19:56:28.905711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 19:56:28.906252 ==
985 19:56:28.908943 RX Vref Scan: 1
986 19:56:28.909473
987 19:56:28.909953 Set Vref Range= 32 -> 127
988 19:56:28.910291
989 19:56:28.912222 RX Vref 32 -> 127, step: 1
990 19:56:28.912657
991 19:56:28.915098 RX Delay -95 -> 252, step: 8
992 19:56:28.915532
993 19:56:28.918919 Set Vref, RX VrefLevel [Byte0]: 32
994 19:56:28.922005 [Byte1]: 32
995 19:56:28.922433
996 19:56:28.925529 Set Vref, RX VrefLevel [Byte0]: 33
997 19:56:28.928416 [Byte1]: 33
998 19:56:28.932207
999 19:56:28.932735 Set Vref, RX VrefLevel [Byte0]: 34
1000 19:56:28.935786 [Byte1]: 34
1001 19:56:28.940114
1002 19:56:28.940648 Set Vref, RX VrefLevel [Byte0]: 35
1003 19:56:28.943284 [Byte1]: 35
1004 19:56:28.947995
1005 19:56:28.948424 Set Vref, RX VrefLevel [Byte0]: 36
1006 19:56:28.951147 [Byte1]: 36
1007 19:56:28.955311
1008 19:56:28.955876 Set Vref, RX VrefLevel [Byte0]: 37
1009 19:56:28.958379 [Byte1]: 37
1010 19:56:28.962933
1011 19:56:28.963547 Set Vref, RX VrefLevel [Byte0]: 38
1012 19:56:28.966339 [Byte1]: 38
1013 19:56:28.970791
1014 19:56:28.971498 Set Vref, RX VrefLevel [Byte0]: 39
1015 19:56:28.973776 [Byte1]: 39
1016 19:56:28.977599
1017 19:56:28.978036 Set Vref, RX VrefLevel [Byte0]: 40
1018 19:56:28.981526 [Byte1]: 40
1019 19:56:28.985574
1020 19:56:28.986105 Set Vref, RX VrefLevel [Byte0]: 41
1021 19:56:28.988409 [Byte1]: 41
1022 19:56:28.992833
1023 19:56:28.993263 Set Vref, RX VrefLevel [Byte0]: 42
1024 19:56:28.996583 [Byte1]: 42
1025 19:56:29.000734
1026 19:56:29.001269 Set Vref, RX VrefLevel [Byte0]: 43
1027 19:56:29.004010 [Byte1]: 43
1028 19:56:29.008019
1029 19:56:29.008446 Set Vref, RX VrefLevel [Byte0]: 44
1030 19:56:29.011537 [Byte1]: 44
1031 19:56:29.015769
1032 19:56:29.016220 Set Vref, RX VrefLevel [Byte0]: 45
1033 19:56:29.019092 [Byte1]: 45
1034 19:56:29.023378
1035 19:56:29.023850 Set Vref, RX VrefLevel [Byte0]: 46
1036 19:56:29.026476 [Byte1]: 46
1037 19:56:29.030790
1038 19:56:29.031284 Set Vref, RX VrefLevel [Byte0]: 47
1039 19:56:29.034815 [Byte1]: 47
1040 19:56:29.038536
1041 19:56:29.039114 Set Vref, RX VrefLevel [Byte0]: 48
1042 19:56:29.042153 [Byte1]: 48
1043 19:56:29.046208
1044 19:56:29.046638 Set Vref, RX VrefLevel [Byte0]: 49
1045 19:56:29.049385 [Byte1]: 49
1046 19:56:29.053489
1047 19:56:29.053909 Set Vref, RX VrefLevel [Byte0]: 50
1048 19:56:29.057640 [Byte1]: 50
1049 19:56:29.062024
1050 19:56:29.062547 Set Vref, RX VrefLevel [Byte0]: 51
1051 19:56:29.064847 [Byte1]: 51
1052 19:56:29.069291
1053 19:56:29.069813 Set Vref, RX VrefLevel [Byte0]: 52
1054 19:56:29.072384 [Byte1]: 52
1055 19:56:29.076849
1056 19:56:29.077270 Set Vref, RX VrefLevel [Byte0]: 53
1057 19:56:29.080339 [Byte1]: 53
1058 19:56:29.084819
1059 19:56:29.085348 Set Vref, RX VrefLevel [Byte0]: 54
1060 19:56:29.087889 [Byte1]: 54
1061 19:56:29.092127
1062 19:56:29.092583 Set Vref, RX VrefLevel [Byte0]: 55
1063 19:56:29.095728 [Byte1]: 55
1064 19:56:29.099677
1065 19:56:29.100208 Set Vref, RX VrefLevel [Byte0]: 56
1066 19:56:29.102805 [Byte1]: 56
1067 19:56:29.107556
1068 19:56:29.108124 Set Vref, RX VrefLevel [Byte0]: 57
1069 19:56:29.110061 [Byte1]: 57
1070 19:56:29.114637
1071 19:56:29.115412 Set Vref, RX VrefLevel [Byte0]: 58
1072 19:56:29.118434 [Byte1]: 58
1073 19:56:29.122112
1074 19:56:29.122555 Set Vref, RX VrefLevel [Byte0]: 59
1075 19:56:29.125197 [Byte1]: 59
1076 19:56:29.129592
1077 19:56:29.130012 Set Vref, RX VrefLevel [Byte0]: 60
1078 19:56:29.133582 [Byte1]: 60
1079 19:56:29.137489
1080 19:56:29.138021 Set Vref, RX VrefLevel [Byte0]: 61
1081 19:56:29.140762 [Byte1]: 61
1082 19:56:29.145182
1083 19:56:29.145604 Set Vref, RX VrefLevel [Byte0]: 62
1084 19:56:29.148265 [Byte1]: 62
1085 19:56:29.152727
1086 19:56:29.153263 Set Vref, RX VrefLevel [Byte0]: 63
1087 19:56:29.155747 [Byte1]: 63
1088 19:56:29.159834
1089 19:56:29.160253 Set Vref, RX VrefLevel [Byte0]: 64
1090 19:56:29.163412 [Byte1]: 64
1091 19:56:29.168126
1092 19:56:29.168654 Set Vref, RX VrefLevel [Byte0]: 65
1093 19:56:29.171454 [Byte1]: 65
1094 19:56:29.175410
1095 19:56:29.175948 Set Vref, RX VrefLevel [Byte0]: 66
1096 19:56:29.178723 [Byte1]: 66
1097 19:56:29.183094
1098 19:56:29.183624 Set Vref, RX VrefLevel [Byte0]: 67
1099 19:56:29.186313 [Byte1]: 67
1100 19:56:29.190813
1101 19:56:29.191337 Set Vref, RX VrefLevel [Byte0]: 68
1102 19:56:29.193934 [Byte1]: 68
1103 19:56:29.198446
1104 19:56:29.198973 Set Vref, RX VrefLevel [Byte0]: 69
1105 19:56:29.201653 [Byte1]: 69
1106 19:56:29.206017
1107 19:56:29.206538 Set Vref, RX VrefLevel [Byte0]: 70
1108 19:56:29.209257 [Byte1]: 70
1109 19:56:29.213694
1110 19:56:29.214221 Set Vref, RX VrefLevel [Byte0]: 71
1111 19:56:29.216765 [Byte1]: 71
1112 19:56:29.221010
1113 19:56:29.221450 Set Vref, RX VrefLevel [Byte0]: 72
1114 19:56:29.223896 [Byte1]: 72
1115 19:56:29.228529
1116 19:56:29.229064 Set Vref, RX VrefLevel [Byte0]: 73
1117 19:56:29.232030 [Byte1]: 73
1118 19:56:29.236189
1119 19:56:29.236719 Set Vref, RX VrefLevel [Byte0]: 74
1120 19:56:29.239207 [Byte1]: 74
1121 19:56:29.243688
1122 19:56:29.244225 Set Vref, RX VrefLevel [Byte0]: 75
1123 19:56:29.247583 [Byte1]: 75
1124 19:56:29.251391
1125 19:56:29.252078 Set Vref, RX VrefLevel [Byte0]: 76
1126 19:56:29.254777 [Byte1]: 76
1127 19:56:29.259485
1128 19:56:29.260059 Set Vref, RX VrefLevel [Byte0]: 77
1129 19:56:29.262260 [Byte1]: 77
1130 19:56:29.266150
1131 19:56:29.269971 Final RX Vref Byte 0 = 58 to rank0
1132 19:56:29.270509 Final RX Vref Byte 1 = 59 to rank0
1133 19:56:29.273391 Final RX Vref Byte 0 = 58 to rank1
1134 19:56:29.276387 Final RX Vref Byte 1 = 59 to rank1==
1135 19:56:29.279822 Dram Type= 6, Freq= 0, CH_0, rank 0
1136 19:56:29.283123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 19:56:29.286581 ==
1138 19:56:29.287117 DQS Delay:
1139 19:56:29.287464 DQS0 = 0, DQS1 = 0
1140 19:56:29.290253 DQM Delay:
1141 19:56:29.290775 DQM0 = 92, DQM1 = 85
1142 19:56:29.293034 DQ Delay:
1143 19:56:29.296758 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1144 19:56:29.300023 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1145 19:56:29.300449 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1146 19:56:29.307196 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1147 19:56:29.307799
1148 19:56:29.308153
1149 19:56:29.313476 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e44, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1150 19:56:29.316894 CH0 RK0: MR19=606, MR18=4E44
1151 19:56:29.323115 CH0_RK0: MR19=0x606, MR18=0x4E44, DQSOSC=390, MR23=63, INC=97, DEC=64
1152 19:56:29.323545
1153 19:56:29.326864 ----->DramcWriteLeveling(PI) begin...
1154 19:56:29.327296 ==
1155 19:56:29.329758 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 19:56:29.333464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 19:56:29.333996 ==
1158 19:56:29.336456 Write leveling (Byte 0): 33 => 33
1159 19:56:29.340420 Write leveling (Byte 1): 30 => 30
1160 19:56:29.343624 DramcWriteLeveling(PI) end<-----
1161 19:56:29.344183
1162 19:56:29.344522 ==
1163 19:56:29.346909 Dram Type= 6, Freq= 0, CH_0, rank 1
1164 19:56:29.350322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1165 19:56:29.350842 ==
1166 19:56:29.353261 [Gating] SW mode calibration
1167 19:56:29.398037 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1168 19:56:29.398610 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1169 19:56:29.398960 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1170 19:56:29.399282 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1171 19:56:29.399593 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1172 19:56:29.400278 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 19:56:29.400607 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 19:56:29.400911 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 19:56:29.401209 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 19:56:29.441892 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 19:56:29.442786 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 19:56:29.443161 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 19:56:29.443489 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 19:56:29.443888 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 19:56:29.444199 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 19:56:29.444498 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 19:56:29.444793 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 19:56:29.445082 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 19:56:29.445372 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 19:56:29.469945 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 19:56:29.470578 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1188 19:56:29.471138 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 19:56:29.471598 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 19:56:29.471978 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 19:56:29.472632 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 19:56:29.473761 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 19:56:29.476894 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 19:56:29.480698 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 19:56:29.483722 0 9 8 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
1196 19:56:29.487704 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 19:56:29.493695 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 19:56:29.496912 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 19:56:29.500515 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 19:56:29.507683 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 19:56:29.510838 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 19:56:29.514049 0 10 4 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
1203 19:56:29.520244 0 10 8 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
1204 19:56:29.524270 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1205 19:56:29.527593 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 19:56:29.531397 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 19:56:29.535799 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 19:56:29.539582 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 19:56:29.546382 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 19:56:29.549652 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1211 19:56:29.553574 0 11 8 | B1->B0 | 4343 3a3a | 0 0 | (1 1) (0 0)
1212 19:56:29.560172 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 19:56:29.563752 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 19:56:29.567019 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 19:56:29.574047 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 19:56:29.576810 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 19:56:29.580470 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 19:56:29.583371 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 19:56:29.590047 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1220 19:56:29.594228 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 19:56:29.597215 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 19:56:29.603630 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 19:56:29.607365 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 19:56:29.610636 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 19:56:29.617369 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 19:56:29.620599 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 19:56:29.623678 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 19:56:29.630634 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 19:56:29.634200 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 19:56:29.636752 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 19:56:29.643952 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 19:56:29.647321 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 19:56:29.650542 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 19:56:29.657050 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 19:56:29.660735 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1236 19:56:29.663756 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 19:56:29.667155 Total UI for P1: 0, mck2ui 16
1238 19:56:29.670844 best dqsien dly found for B0: ( 0, 14, 8)
1239 19:56:29.673969 Total UI for P1: 0, mck2ui 16
1240 19:56:29.677025 best dqsien dly found for B1: ( 0, 14, 8)
1241 19:56:29.680779 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1242 19:56:29.684151 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1243 19:56:29.684672
1244 19:56:29.687366 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1245 19:56:29.690815 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1246 19:56:29.693663 [Gating] SW calibration Done
1247 19:56:29.694104 ==
1248 19:56:29.697387 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 19:56:29.704257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1250 19:56:29.704779 ==
1251 19:56:29.705122 RX Vref Scan: 0
1252 19:56:29.705442
1253 19:56:29.707416 RX Vref 0 -> 0, step: 1
1254 19:56:29.707983
1255 19:56:29.710891 RX Delay -130 -> 252, step: 16
1256 19:56:29.714220 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1257 19:56:29.717295 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1258 19:56:29.720282 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1259 19:56:29.724003 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1260 19:56:29.731172 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1261 19:56:29.734374 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1262 19:56:29.737399 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1263 19:56:29.740301 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1264 19:56:29.744306 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1265 19:56:29.751001 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1266 19:56:29.754479 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1267 19:56:29.757044 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1268 19:56:29.760844 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1269 19:56:29.763956 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1270 19:56:29.770610 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1271 19:56:29.774105 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1272 19:56:29.774632 ==
1273 19:56:29.777330 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 19:56:29.780716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 19:56:29.781242 ==
1276 19:56:29.784099 DQS Delay:
1277 19:56:29.784618 DQS0 = 0, DQS1 = 0
1278 19:56:29.784961 DQM Delay:
1279 19:56:29.787843 DQM0 = 91, DQM1 = 80
1280 19:56:29.788366 DQ Delay:
1281 19:56:29.790641 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1282 19:56:29.794151 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =109
1283 19:56:29.797421 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1284 19:56:29.800983 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1285 19:56:29.801509
1286 19:56:29.801847
1287 19:56:29.802161 ==
1288 19:56:29.804385 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 19:56:29.810675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 19:56:29.811106 ==
1291 19:56:29.811444
1292 19:56:29.811806
1293 19:56:29.812122 TX Vref Scan disable
1294 19:56:29.814222 == TX Byte 0 ==
1295 19:56:29.816993 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1296 19:56:29.820290 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1297 19:56:29.824282 == TX Byte 1 ==
1298 19:56:29.827280 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1299 19:56:29.830909 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1300 19:56:29.834114 ==
1301 19:56:29.837258 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 19:56:29.840836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 19:56:29.841267 ==
1304 19:56:29.853520 TX Vref=22, minBit 10, minWin=27, winSum=448
1305 19:56:29.856812 TX Vref=24, minBit 8, minWin=27, winSum=450
1306 19:56:29.860314 TX Vref=26, minBit 4, minWin=28, winSum=456
1307 19:56:29.863629 TX Vref=28, minBit 6, minWin=28, winSum=458
1308 19:56:29.866884 TX Vref=30, minBit 4, minWin=28, winSum=457
1309 19:56:29.869842 TX Vref=32, minBit 2, minWin=28, winSum=454
1310 19:56:29.876800 [TxChooseVref] Worse bit 6, Min win 28, Win sum 458, Final Vref 28
1311 19:56:29.877225
1312 19:56:29.879730 Final TX Range 1 Vref 28
1313 19:56:29.880212
1314 19:56:29.880552 ==
1315 19:56:29.883289 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 19:56:29.886617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 19:56:29.887048 ==
1318 19:56:29.887390
1319 19:56:29.889888
1320 19:56:29.890309 TX Vref Scan disable
1321 19:56:29.893092 == TX Byte 0 ==
1322 19:56:29.896926 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1323 19:56:29.900036 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1324 19:56:29.903008 == TX Byte 1 ==
1325 19:56:29.906516 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1326 19:56:29.909717 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1327 19:56:29.913295
1328 19:56:29.913652 [DATLAT]
1329 19:56:29.913907 Freq=800, CH0 RK1
1330 19:56:29.914149
1331 19:56:29.916506 DATLAT Default: 0xa
1332 19:56:29.916807 0, 0xFFFF, sum = 0
1333 19:56:29.920155 1, 0xFFFF, sum = 0
1334 19:56:29.920463 2, 0xFFFF, sum = 0
1335 19:56:29.923181 3, 0xFFFF, sum = 0
1336 19:56:29.923543 4, 0xFFFF, sum = 0
1337 19:56:29.926585 5, 0xFFFF, sum = 0
1338 19:56:29.926891 6, 0xFFFF, sum = 0
1339 19:56:29.929707 7, 0xFFFF, sum = 0
1340 19:56:29.933118 8, 0xFFFF, sum = 0
1341 19:56:29.933424 9, 0x0, sum = 1
1342 19:56:29.933668 10, 0x0, sum = 2
1343 19:56:29.936544 11, 0x0, sum = 3
1344 19:56:29.936849 12, 0x0, sum = 4
1345 19:56:29.939562 best_step = 10
1346 19:56:29.939897
1347 19:56:29.940134 ==
1348 19:56:29.942931 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 19:56:29.946696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 19:56:29.946999 ==
1351 19:56:29.949802 RX Vref Scan: 0
1352 19:56:29.950101
1353 19:56:29.950346 RX Vref 0 -> 0, step: 1
1354 19:56:29.950570
1355 19:56:29.952921 RX Delay -95 -> 252, step: 8
1356 19:56:29.959737 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1357 19:56:29.962962 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1358 19:56:29.966797 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1359 19:56:29.970209 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1360 19:56:29.973524 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1361 19:56:29.979808 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1362 19:56:29.983487 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1363 19:56:29.986706 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1364 19:56:29.990155 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1365 19:56:29.993382 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1366 19:56:30.000228 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1367 19:56:30.003768 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1368 19:56:30.006964 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1369 19:56:30.009939 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1370 19:56:30.013697 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1371 19:56:30.019995 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1372 19:56:30.020452 ==
1373 19:56:30.023236 Dram Type= 6, Freq= 0, CH_0, rank 1
1374 19:56:30.026746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 19:56:30.027165 ==
1376 19:56:30.027510 DQS Delay:
1377 19:56:30.030258 DQS0 = 0, DQS1 = 0
1378 19:56:30.030789 DQM Delay:
1379 19:56:30.033681 DQM0 = 93, DQM1 = 82
1380 19:56:30.034093 DQ Delay:
1381 19:56:30.036789 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1382 19:56:30.040639 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1383 19:56:30.043594 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1384 19:56:30.046871 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1385 19:56:30.047388
1386 19:56:30.047776
1387 19:56:30.053792 [DQSOSCAuto] RK1, (LSB)MR18= 0x4415, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1388 19:56:30.056996 CH0 RK1: MR19=606, MR18=4415
1389 19:56:30.063412 CH0_RK1: MR19=0x606, MR18=0x4415, DQSOSC=392, MR23=63, INC=96, DEC=64
1390 19:56:30.067405 [RxdqsGatingPostProcess] freq 800
1391 19:56:30.073986 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1392 19:56:30.074413 Pre-setting of DQS Precalculation
1393 19:56:30.080808 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1394 19:56:30.081233 ==
1395 19:56:30.083809 Dram Type= 6, Freq= 0, CH_1, rank 0
1396 19:56:30.087184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 19:56:30.087790 ==
1398 19:56:30.093999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1399 19:56:30.100661 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1400 19:56:30.108285 [CA 0] Center 36 (6~67) winsize 62
1401 19:56:30.111966 [CA 1] Center 36 (6~67) winsize 62
1402 19:56:30.115161 [CA 2] Center 35 (5~66) winsize 62
1403 19:56:30.118604 [CA 3] Center 34 (4~65) winsize 62
1404 19:56:30.121429 [CA 4] Center 34 (4~65) winsize 62
1405 19:56:30.125056 [CA 5] Center 34 (4~64) winsize 61
1406 19:56:30.125471
1407 19:56:30.128559 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1408 19:56:30.129029
1409 19:56:30.131769 [CATrainingPosCal] consider 1 rank data
1410 19:56:30.134976 u2DelayCellTimex100 = 270/100 ps
1411 19:56:30.138271 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1412 19:56:30.141625 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1413 19:56:30.148414 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1414 19:56:30.151403 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1415 19:56:30.155212 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1416 19:56:30.158406 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1417 19:56:30.158840
1418 19:56:30.161870 CA PerBit enable=1, Macro0, CA PI delay=34
1419 19:56:30.162287
1420 19:56:30.164883 [CBTSetCACLKResult] CA Dly = 34
1421 19:56:30.165338 CS Dly: 5 (0~36)
1422 19:56:30.165671 ==
1423 19:56:30.168358 Dram Type= 6, Freq= 0, CH_1, rank 1
1424 19:56:30.174808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 19:56:30.175280 ==
1426 19:56:30.178163 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1427 19:56:30.185062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1428 19:56:30.195682 [CA 0] Center 36 (6~67) winsize 62
1429 19:56:30.199079 [CA 1] Center 36 (6~67) winsize 62
1430 19:56:30.203263 [CA 2] Center 35 (5~66) winsize 62
1431 19:56:30.206930 [CA 3] Center 34 (4~65) winsize 62
1432 19:56:30.207350 [CA 4] Center 35 (4~66) winsize 63
1433 19:56:30.210841 [CA 5] Center 35 (5~65) winsize 61
1434 19:56:30.211365
1435 19:56:30.214524 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1436 19:56:30.215036
1437 19:56:30.218527 [CATrainingPosCal] consider 2 rank data
1438 19:56:30.221342 u2DelayCellTimex100 = 270/100 ps
1439 19:56:30.225320 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1440 19:56:30.228535 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1441 19:56:30.231728 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1442 19:56:30.235608 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1443 19:56:30.238518 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1444 19:56:30.245264 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
1445 19:56:30.245778
1446 19:56:30.248553 CA PerBit enable=1, Macro0, CA PI delay=34
1447 19:56:30.248979
1448 19:56:30.252438 [CBTSetCACLKResult] CA Dly = 34
1449 19:56:30.252981 CS Dly: 6 (0~38)
1450 19:56:30.253328
1451 19:56:30.255406 ----->DramcWriteLeveling(PI) begin...
1452 19:56:30.256039 ==
1453 19:56:30.259244 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 19:56:30.262086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 19:56:30.265275 ==
1456 19:56:30.265790 Write leveling (Byte 0): 27 => 27
1457 19:56:30.269117 Write leveling (Byte 1): 30 => 30
1458 19:56:30.272193 DramcWriteLeveling(PI) end<-----
1459 19:56:30.272620
1460 19:56:30.272956 ==
1461 19:56:30.275304 Dram Type= 6, Freq= 0, CH_1, rank 0
1462 19:56:30.282663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 19:56:30.283186 ==
1464 19:56:30.283522 [Gating] SW mode calibration
1465 19:56:30.292389 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1466 19:56:30.295720 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1467 19:56:30.298958 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1468 19:56:30.305691 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1469 19:56:30.308715 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 19:56:30.312498 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 19:56:30.319544 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 19:56:30.322537 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 19:56:30.325594 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 19:56:30.332651 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 19:56:30.335906 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 19:56:30.338926 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 19:56:30.346029 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 19:56:30.348848 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 19:56:30.352656 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 19:56:30.359560 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 19:56:30.362160 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 19:56:30.366018 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 19:56:30.368747 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 19:56:30.376106 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1485 19:56:30.378857 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1486 19:56:30.382793 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 19:56:30.389131 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 19:56:30.392300 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 19:56:30.395766 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 19:56:30.402719 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 19:56:30.406116 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 19:56:30.409415 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1493 19:56:30.415966 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1494 19:56:30.419689 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 19:56:30.422866 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 19:56:30.429914 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 19:56:30.432747 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 19:56:30.435892 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 19:56:30.439098 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1500 19:56:30.446358 0 10 4 | B1->B0 | 3333 2d2d | 1 1 | (1 0) (1 0)
1501 19:56:30.449159 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1502 19:56:30.453158 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 19:56:30.459628 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 19:56:30.463406 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 19:56:30.466630 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 19:56:30.472606 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 19:56:30.476637 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 19:56:30.479801 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
1509 19:56:30.486436 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1510 19:56:30.489595 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 19:56:30.493241 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 19:56:30.499397 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 19:56:30.503379 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 19:56:30.506441 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 19:56:30.513212 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1516 19:56:30.516546 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1517 19:56:30.519517 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 19:56:30.526067 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 19:56:30.529106 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 19:56:30.532489 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 19:56:30.535880 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 19:56:30.543085 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 19:56:30.546306 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 19:56:30.549112 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 19:56:30.555832 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 19:56:30.558914 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 19:56:30.562785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 19:56:30.569219 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 19:56:30.572847 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 19:56:30.575999 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 19:56:30.582866 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1532 19:56:30.586020 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1533 19:56:30.589712 Total UI for P1: 0, mck2ui 16
1534 19:56:30.592674 best dqsien dly found for B1: ( 0, 14, 0)
1535 19:56:30.596198 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 19:56:30.599526 Total UI for P1: 0, mck2ui 16
1537 19:56:30.602651 best dqsien dly found for B0: ( 0, 14, 2)
1538 19:56:30.606041 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1539 19:56:30.609255 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1540 19:56:30.609567
1541 19:56:30.612866 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1542 19:56:30.616161 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1543 19:56:30.619225 [Gating] SW calibration Done
1544 19:56:30.619529 ==
1545 19:56:30.623022 Dram Type= 6, Freq= 0, CH_1, rank 0
1546 19:56:30.629271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1547 19:56:30.629577 ==
1548 19:56:30.629818 RX Vref Scan: 0
1549 19:56:30.630047
1550 19:56:30.633060 RX Vref 0 -> 0, step: 1
1551 19:56:30.633364
1552 19:56:30.636132 RX Delay -130 -> 252, step: 16
1553 19:56:30.639504 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1554 19:56:30.642981 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1555 19:56:30.646403 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1556 19:56:30.649422 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1557 19:56:30.656546 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1558 19:56:30.660192 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1559 19:56:30.663172 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1560 19:56:30.666379 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1561 19:56:30.669893 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1562 19:56:30.673186 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1563 19:56:30.679683 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1564 19:56:30.683482 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1565 19:56:30.686851 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1566 19:56:30.690064 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1567 19:56:30.696903 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1568 19:56:30.700076 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1569 19:56:30.700479 ==
1570 19:56:30.703556 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 19:56:30.706790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 19:56:30.707198 ==
1573 19:56:30.707618 DQS Delay:
1574 19:56:30.710536 DQS0 = 0, DQS1 = 0
1575 19:56:30.711038 DQM Delay:
1576 19:56:30.713262 DQM0 = 94, DQM1 = 93
1577 19:56:30.713673 DQ Delay:
1578 19:56:30.716947 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1579 19:56:30.720293 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1580 19:56:30.723240 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1581 19:56:30.726680 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1582 19:56:30.726995
1583 19:56:30.727236
1584 19:56:30.727459 ==
1585 19:56:30.730176 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 19:56:30.733662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 19:56:30.736509 ==
1588 19:56:30.736814
1589 19:56:30.737054
1590 19:56:30.737278 TX Vref Scan disable
1591 19:56:30.740233 == TX Byte 0 ==
1592 19:56:30.743540 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1593 19:56:30.746958 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1594 19:56:30.750284 == TX Byte 1 ==
1595 19:56:30.753389 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1596 19:56:30.756989 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1597 19:56:30.759979 ==
1598 19:56:30.760285 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 19:56:30.767013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 19:56:30.767410 ==
1601 19:56:30.779411 TX Vref=22, minBit 3, minWin=26, winSum=433
1602 19:56:30.782422 TX Vref=24, minBit 3, minWin=26, winSum=436
1603 19:56:30.786075 TX Vref=26, minBit 3, minWin=26, winSum=440
1604 19:56:30.789392 TX Vref=28, minBit 3, minWin=26, winSum=444
1605 19:56:30.793311 TX Vref=30, minBit 0, minWin=27, winSum=450
1606 19:56:30.795992 TX Vref=32, minBit 0, minWin=27, winSum=446
1607 19:56:30.803249 [TxChooseVref] Worse bit 0, Min win 27, Win sum 450, Final Vref 30
1608 19:56:30.803804
1609 19:56:30.806421 Final TX Range 1 Vref 30
1610 19:56:30.806945
1611 19:56:30.807283 ==
1612 19:56:30.809337 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 19:56:30.813148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 19:56:30.813647 ==
1615 19:56:30.813989
1616 19:56:30.814304
1617 19:56:30.816282 TX Vref Scan disable
1618 19:56:30.819614 == TX Byte 0 ==
1619 19:56:30.822723 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1620 19:56:30.826028 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1621 19:56:30.829104 == TX Byte 1 ==
1622 19:56:30.832787 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1623 19:56:30.835787 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1624 19:56:30.839245
1625 19:56:30.839724 [DATLAT]
1626 19:56:30.840071 Freq=800, CH1 RK0
1627 19:56:30.840385
1628 19:56:30.842667 DATLAT Default: 0xa
1629 19:56:30.843184 0, 0xFFFF, sum = 0
1630 19:56:30.846046 1, 0xFFFF, sum = 0
1631 19:56:30.846745 2, 0xFFFF, sum = 0
1632 19:56:30.849297 3, 0xFFFF, sum = 0
1633 19:56:30.849872 4, 0xFFFF, sum = 0
1634 19:56:30.852729 5, 0xFFFF, sum = 0
1635 19:56:30.853331 6, 0xFFFF, sum = 0
1636 19:56:30.856083 7, 0xFFFF, sum = 0
1637 19:56:30.856664 8, 0xFFFF, sum = 0
1638 19:56:30.859104 9, 0x0, sum = 1
1639 19:56:30.859612 10, 0x0, sum = 2
1640 19:56:30.862898 11, 0x0, sum = 3
1641 19:56:30.863422 12, 0x0, sum = 4
1642 19:56:30.866208 best_step = 10
1643 19:56:30.866770
1644 19:56:30.867111 ==
1645 19:56:30.869447 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 19:56:30.873047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 19:56:30.873671 ==
1648 19:56:30.876245 RX Vref Scan: 1
1649 19:56:30.876665
1650 19:56:30.877002 Set Vref Range= 32 -> 127
1651 19:56:30.877313
1652 19:56:30.879314 RX Vref 32 -> 127, step: 1
1653 19:56:30.879781
1654 19:56:30.883023 RX Delay -63 -> 252, step: 8
1655 19:56:30.883444
1656 19:56:30.886481 Set Vref, RX VrefLevel [Byte0]: 32
1657 19:56:30.889765 [Byte1]: 32
1658 19:56:30.890320
1659 19:56:30.892814 Set Vref, RX VrefLevel [Byte0]: 33
1660 19:56:30.896373 [Byte1]: 33
1661 19:56:30.896902
1662 19:56:30.899489 Set Vref, RX VrefLevel [Byte0]: 34
1663 19:56:30.902869 [Byte1]: 34
1664 19:56:30.907126
1665 19:56:30.907672 Set Vref, RX VrefLevel [Byte0]: 35
1666 19:56:30.910241 [Byte1]: 35
1667 19:56:30.914255
1668 19:56:30.914763 Set Vref, RX VrefLevel [Byte0]: 36
1669 19:56:30.918142 [Byte1]: 36
1670 19:56:30.921769
1671 19:56:30.922191 Set Vref, RX VrefLevel [Byte0]: 37
1672 19:56:30.924784 [Byte1]: 37
1673 19:56:30.929293
1674 19:56:30.929911 Set Vref, RX VrefLevel [Byte0]: 38
1675 19:56:30.932419 [Byte1]: 38
1676 19:56:30.936748
1677 19:56:30.937164 Set Vref, RX VrefLevel [Byte0]: 39
1678 19:56:30.939859 [Byte1]: 39
1679 19:56:30.944331
1680 19:56:30.944839 Set Vref, RX VrefLevel [Byte0]: 40
1681 19:56:30.947346 [Byte1]: 40
1682 19:56:30.951836
1683 19:56:30.952344 Set Vref, RX VrefLevel [Byte0]: 41
1684 19:56:30.954917 [Byte1]: 41
1685 19:56:30.959444
1686 19:56:30.960038 Set Vref, RX VrefLevel [Byte0]: 42
1687 19:56:30.962747 [Byte1]: 42
1688 19:56:30.967000
1689 19:56:30.967418 Set Vref, RX VrefLevel [Byte0]: 43
1690 19:56:30.970058 [Byte1]: 43
1691 19:56:30.974126
1692 19:56:30.974546 Set Vref, RX VrefLevel [Byte0]: 44
1693 19:56:30.977655 [Byte1]: 44
1694 19:56:30.981655
1695 19:56:30.982075 Set Vref, RX VrefLevel [Byte0]: 45
1696 19:56:30.985106 [Byte1]: 45
1697 19:56:30.989258
1698 19:56:30.989684 Set Vref, RX VrefLevel [Byte0]: 46
1699 19:56:30.992922 [Byte1]: 46
1700 19:56:30.996851
1701 19:56:30.997275 Set Vref, RX VrefLevel [Byte0]: 47
1702 19:56:31.000297 [Byte1]: 47
1703 19:56:31.004469
1704 19:56:31.004974 Set Vref, RX VrefLevel [Byte0]: 48
1705 19:56:31.007558 [Byte1]: 48
1706 19:56:31.012133
1707 19:56:31.012639 Set Vref, RX VrefLevel [Byte0]: 49
1708 19:56:31.015034 [Byte1]: 49
1709 19:56:31.019566
1710 19:56:31.022668 Set Vref, RX VrefLevel [Byte0]: 50
1711 19:56:31.023098 [Byte1]: 50
1712 19:56:31.026481
1713 19:56:31.026964 Set Vref, RX VrefLevel [Byte0]: 51
1714 19:56:31.030229 [Byte1]: 51
1715 19:56:31.034016
1716 19:56:31.034436 Set Vref, RX VrefLevel [Byte0]: 52
1717 19:56:31.037823 [Byte1]: 52
1718 19:56:31.042413
1719 19:56:31.042934 Set Vref, RX VrefLevel [Byte0]: 53
1720 19:56:31.045360 [Byte1]: 53
1721 19:56:31.048974
1722 19:56:31.049398 Set Vref, RX VrefLevel [Byte0]: 54
1723 19:56:31.052968 [Byte1]: 54
1724 19:56:31.056913
1725 19:56:31.057336 Set Vref, RX VrefLevel [Byte0]: 55
1726 19:56:31.060164 [Byte1]: 55
1727 19:56:31.063995
1728 19:56:31.064417 Set Vref, RX VrefLevel [Byte0]: 56
1729 19:56:31.067674 [Byte1]: 56
1730 19:56:31.071507
1731 19:56:31.071960 Set Vref, RX VrefLevel [Byte0]: 57
1732 19:56:31.075523 [Byte1]: 57
1733 19:56:31.079182
1734 19:56:31.079602 Set Vref, RX VrefLevel [Byte0]: 58
1735 19:56:31.082777 [Byte1]: 58
1736 19:56:31.086547
1737 19:56:31.087048 Set Vref, RX VrefLevel [Byte0]: 59
1738 19:56:31.089983 [Byte1]: 59
1739 19:56:31.094236
1740 19:56:31.094727 Set Vref, RX VrefLevel [Byte0]: 60
1741 19:56:31.097281 [Byte1]: 60
1742 19:56:31.101953
1743 19:56:31.102482 Set Vref, RX VrefLevel [Byte0]: 61
1744 19:56:31.105226 [Byte1]: 61
1745 19:56:31.109499
1746 19:56:31.110002 Set Vref, RX VrefLevel [Byte0]: 62
1747 19:56:31.112373 [Byte1]: 62
1748 19:56:31.116782
1749 19:56:31.117289 Set Vref, RX VrefLevel [Byte0]: 63
1750 19:56:31.120238 [Byte1]: 63
1751 19:56:31.123997
1752 19:56:31.124416 Set Vref, RX VrefLevel [Byte0]: 64
1753 19:56:31.127745 [Byte1]: 64
1754 19:56:31.131835
1755 19:56:31.132262 Set Vref, RX VrefLevel [Byte0]: 65
1756 19:56:31.134722 [Byte1]: 65
1757 19:56:31.139096
1758 19:56:31.139708 Set Vref, RX VrefLevel [Byte0]: 66
1759 19:56:31.142315 [Byte1]: 66
1760 19:56:31.146543
1761 19:56:31.147051 Set Vref, RX VrefLevel [Byte0]: 67
1762 19:56:31.150326 [Byte1]: 67
1763 19:56:31.154507
1764 19:56:31.155026 Set Vref, RX VrefLevel [Byte0]: 68
1765 19:56:31.157902 [Byte1]: 68
1766 19:56:31.161900
1767 19:56:31.162323 Set Vref, RX VrefLevel [Byte0]: 69
1768 19:56:31.165250 [Byte1]: 69
1769 19:56:31.169501
1770 19:56:31.169931 Set Vref, RX VrefLevel [Byte0]: 70
1771 19:56:31.172578 [Byte1]: 70
1772 19:56:31.177273
1773 19:56:31.177801 Set Vref, RX VrefLevel [Byte0]: 71
1774 19:56:31.180097 [Byte1]: 71
1775 19:56:31.184427
1776 19:56:31.184851 Set Vref, RX VrefLevel [Byte0]: 72
1777 19:56:31.187812 [Byte1]: 72
1778 19:56:31.191749
1779 19:56:31.192177 Set Vref, RX VrefLevel [Byte0]: 73
1780 19:56:31.195050 [Byte1]: 73
1781 19:56:31.199345
1782 19:56:31.199813 Final RX Vref Byte 0 = 57 to rank0
1783 19:56:31.202547 Final RX Vref Byte 1 = 55 to rank0
1784 19:56:31.206438 Final RX Vref Byte 0 = 57 to rank1
1785 19:56:31.209076 Final RX Vref Byte 1 = 55 to rank1==
1786 19:56:31.212731 Dram Type= 6, Freq= 0, CH_1, rank 0
1787 19:56:31.216157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 19:56:31.219817 ==
1789 19:56:31.220342 DQS Delay:
1790 19:56:31.220693 DQS0 = 0, DQS1 = 0
1791 19:56:31.222510 DQM Delay:
1792 19:56:31.222928 DQM0 = 96, DQM1 = 90
1793 19:56:31.225754 DQ Delay:
1794 19:56:31.229170 DQ0 =96, DQ1 =88, DQ2 =88, DQ3 =92
1795 19:56:31.229592 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1796 19:56:31.232787 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1797 19:56:31.239190 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1798 19:56:31.239611
1799 19:56:31.240001
1800 19:56:31.246152 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1801 19:56:31.249426 CH1 RK0: MR19=606, MR18=2D49
1802 19:56:31.255899 CH1_RK0: MR19=0x606, MR18=0x2D49, DQSOSC=391, MR23=63, INC=96, DEC=64
1803 19:56:31.256406
1804 19:56:31.259421 ----->DramcWriteLeveling(PI) begin...
1805 19:56:31.259983 ==
1806 19:56:31.262618 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 19:56:31.265523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 19:56:31.265970 ==
1809 19:56:31.269724 Write leveling (Byte 0): 26 => 26
1810 19:56:31.272845 Write leveling (Byte 1): 26 => 26
1811 19:56:31.275743 DramcWriteLeveling(PI) end<-----
1812 19:56:31.276168
1813 19:56:31.276503 ==
1814 19:56:31.279488 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 19:56:31.282699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 19:56:31.283143 ==
1817 19:56:31.285850 [Gating] SW mode calibration
1818 19:56:31.292833 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1819 19:56:31.299382 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1820 19:56:31.303133 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1821 19:56:31.306342 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1822 19:56:31.312825 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 19:56:31.315978 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 19:56:31.319326 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 19:56:31.325917 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 19:56:31.329279 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 19:56:31.332505 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 19:56:31.339617 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 19:56:31.342532 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 19:56:31.345844 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 19:56:31.352343 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 19:56:31.355582 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 19:56:31.359167 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 19:56:31.365501 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 19:56:31.369014 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1836 19:56:31.372110 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1837 19:56:31.378832 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1838 19:56:31.382572 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 19:56:31.385483 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 19:56:31.392549 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 19:56:31.395769 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 19:56:31.398943 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 19:56:31.402496 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 19:56:31.409419 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 19:56:31.412595 0 9 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1846 19:56:31.415800 0 9 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1847 19:56:31.422640 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 19:56:31.425837 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 19:56:31.428688 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 19:56:31.435866 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 19:56:31.439301 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 19:56:31.442689 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1853 19:56:31.449284 0 10 4 | B1->B0 | 2a2a 3131 | 1 1 | (1 0) (1 0)
1854 19:56:31.452329 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1855 19:56:31.456473 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 19:56:31.462524 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 19:56:31.465806 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 19:56:31.469219 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 19:56:31.475856 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 19:56:31.479213 0 11 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1861 19:56:31.482338 0 11 4 | B1->B0 | 3939 2e2e | 0 1 | (1 1) (0 0)
1862 19:56:31.485989 0 11 8 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
1863 19:56:31.492268 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 19:56:31.495750 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 19:56:31.499445 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 19:56:31.506118 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 19:56:31.509852 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 19:56:31.512878 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 19:56:31.519417 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1870 19:56:31.522969 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 19:56:31.526180 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 19:56:31.532751 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 19:56:31.536005 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 19:56:31.539132 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 19:56:31.546576 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 19:56:31.549518 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 19:56:31.553174 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 19:56:31.559351 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 19:56:31.563175 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 19:56:31.566388 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 19:56:31.569692 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 19:56:31.576176 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 19:56:31.579228 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 19:56:31.582661 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1885 19:56:31.589505 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1886 19:56:31.592691 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1887 19:56:31.596139 Total UI for P1: 0, mck2ui 16
1888 19:56:31.599090 best dqsien dly found for B1: ( 0, 14, 2)
1889 19:56:31.602572 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 19:56:31.606051 Total UI for P1: 0, mck2ui 16
1891 19:56:31.609021 best dqsien dly found for B0: ( 0, 14, 6)
1892 19:56:31.612890 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1893 19:56:31.616107 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1894 19:56:31.616528
1895 19:56:31.622579 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1896 19:56:31.626031 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1897 19:56:31.626656 [Gating] SW calibration Done
1898 19:56:31.629018 ==
1899 19:56:31.629670 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 19:56:31.635768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 19:56:31.636207 ==
1902 19:56:31.636646 RX Vref Scan: 0
1903 19:56:31.637057
1904 19:56:31.639687 RX Vref 0 -> 0, step: 1
1905 19:56:31.640122
1906 19:56:31.642898 RX Delay -130 -> 252, step: 16
1907 19:56:31.646227 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1908 19:56:31.649853 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1909 19:56:31.653167 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1910 19:56:31.659764 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1911 19:56:31.662661 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1912 19:56:31.665747 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1913 19:56:31.669617 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1914 19:56:31.672560 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1915 19:56:31.679319 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1916 19:56:31.682305 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1917 19:56:31.686135 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1918 19:56:31.689078 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1919 19:56:31.692443 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1920 19:56:31.699779 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1921 19:56:31.702907 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1922 19:56:31.706477 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1923 19:56:31.707004 ==
1924 19:56:31.709607 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 19:56:31.713037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 19:56:31.713569 ==
1927 19:56:31.716532 DQS Delay:
1928 19:56:31.717124 DQS0 = 0, DQS1 = 0
1929 19:56:31.719579 DQM Delay:
1930 19:56:31.720158 DQM0 = 93, DQM1 = 91
1931 19:56:31.720635 DQ Delay:
1932 19:56:31.723121 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1933 19:56:31.725936 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1934 19:56:31.729171 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1935 19:56:31.733279 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1936 19:56:31.733813
1937 19:56:31.734155
1938 19:56:31.735940 ==
1939 19:56:31.739320 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 19:56:31.742635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 19:56:31.743065 ==
1942 19:56:31.743401
1943 19:56:31.743753
1944 19:56:31.746715 TX Vref Scan disable
1945 19:56:31.747233 == TX Byte 0 ==
1946 19:56:31.749613 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1947 19:56:31.756531 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1948 19:56:31.757054 == TX Byte 1 ==
1949 19:56:31.759825 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1950 19:56:31.766486 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1951 19:56:31.766993 ==
1952 19:56:31.769632 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 19:56:31.773596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 19:56:31.774118 ==
1955 19:56:31.786062 TX Vref=22, minBit 3, minWin=25, winSum=436
1956 19:56:31.789560 TX Vref=24, minBit 3, minWin=25, winSum=441
1957 19:56:31.792593 TX Vref=26, minBit 1, minWin=26, winSum=443
1958 19:56:31.796558 TX Vref=28, minBit 3, minWin=26, winSum=448
1959 19:56:31.799023 TX Vref=30, minBit 0, minWin=27, winSum=446
1960 19:56:31.803023 TX Vref=32, minBit 7, minWin=26, winSum=446
1961 19:56:31.809212 [TxChooseVref] Worse bit 0, Min win 27, Win sum 446, Final Vref 30
1962 19:56:31.809639
1963 19:56:31.813207 Final TX Range 1 Vref 30
1964 19:56:31.813719
1965 19:56:31.814059 ==
1966 19:56:31.816196 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 19:56:31.819622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 19:56:31.820180 ==
1969 19:56:31.820522
1970 19:56:31.822890
1971 19:56:31.823313 TX Vref Scan disable
1972 19:56:31.825936 == TX Byte 0 ==
1973 19:56:31.829483 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1974 19:56:31.833380 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1975 19:56:31.835833 == TX Byte 1 ==
1976 19:56:31.839583 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1977 19:56:31.842976 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1978 19:56:31.843408
1979 19:56:31.846083 [DATLAT]
1980 19:56:31.846604 Freq=800, CH1 RK1
1981 19:56:31.846943
1982 19:56:31.849569 DATLAT Default: 0xa
1983 19:56:31.850090 0, 0xFFFF, sum = 0
1984 19:56:31.852373 1, 0xFFFF, sum = 0
1985 19:56:31.852808 2, 0xFFFF, sum = 0
1986 19:56:31.856609 3, 0xFFFF, sum = 0
1987 19:56:31.857135 4, 0xFFFF, sum = 0
1988 19:56:31.859886 5, 0xFFFF, sum = 0
1989 19:56:31.860416 6, 0xFFFF, sum = 0
1990 19:56:31.862927 7, 0xFFFF, sum = 0
1991 19:56:31.863452 8, 0xFFFF, sum = 0
1992 19:56:31.866521 9, 0x0, sum = 1
1993 19:56:31.867046 10, 0x0, sum = 2
1994 19:56:31.869712 11, 0x0, sum = 3
1995 19:56:31.870240 12, 0x0, sum = 4
1996 19:56:31.872670 best_step = 10
1997 19:56:31.873096
1998 19:56:31.873435 ==
1999 19:56:31.876039 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 19:56:31.879679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 19:56:31.880113 ==
2002 19:56:31.882700 RX Vref Scan: 0
2003 19:56:31.883126
2004 19:56:31.883460 RX Vref 0 -> 0, step: 1
2005 19:56:31.883819
2006 19:56:31.886533 RX Delay -63 -> 252, step: 8
2007 19:56:31.893135 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2008 19:56:31.896095 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2009 19:56:31.899591 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2010 19:56:31.903344 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2011 19:56:31.906303 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2012 19:56:31.909317 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2013 19:56:31.916331 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2014 19:56:31.919367 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2015 19:56:31.923411 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2016 19:56:31.926079 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2017 19:56:31.929268 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2018 19:56:31.932904 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2019 19:56:31.940442 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2020 19:56:31.943490 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2021 19:56:31.946554 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2022 19:56:31.950073 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2023 19:56:31.950597 ==
2024 19:56:31.953057 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 19:56:31.959828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 19:56:31.960347 ==
2027 19:56:31.960687 DQS Delay:
2028 19:56:31.961079 DQS0 = 0, DQS1 = 0
2029 19:56:31.963405 DQM Delay:
2030 19:56:31.963867 DQM0 = 97, DQM1 = 91
2031 19:56:31.967027 DQ Delay:
2032 19:56:31.970222 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2033 19:56:31.972954 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2034 19:56:31.976393 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2035 19:56:31.979871 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2036 19:56:31.980300
2037 19:56:31.980706
2038 19:56:31.986699 [DQSOSCAuto] RK1, (LSB)MR18= 0x4812, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2039 19:56:31.989785 CH1 RK1: MR19=606, MR18=4812
2040 19:56:31.996558 CH1_RK1: MR19=0x606, MR18=0x4812, DQSOSC=391, MR23=63, INC=96, DEC=64
2041 19:56:32.000095 [RxdqsGatingPostProcess] freq 800
2042 19:56:32.002986 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2043 19:56:32.006847 Pre-setting of DQS Precalculation
2044 19:56:32.013171 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2045 19:56:32.020414 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2046 19:56:32.026866 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2047 19:56:32.027409
2048 19:56:32.027922
2049 19:56:32.030275 [Calibration Summary] 1600 Mbps
2050 19:56:32.030958 CH 0, Rank 0
2051 19:56:32.033541 SW Impedance : PASS
2052 19:56:32.036560 DUTY Scan : NO K
2053 19:56:32.037001 ZQ Calibration : PASS
2054 19:56:32.040230 Jitter Meter : NO K
2055 19:56:32.043226 CBT Training : PASS
2056 19:56:32.043789 Write leveling : PASS
2057 19:56:32.046640 RX DQS gating : PASS
2058 19:56:32.047061 RX DQ/DQS(RDDQC) : PASS
2059 19:56:32.050408 TX DQ/DQS : PASS
2060 19:56:32.053528 RX DATLAT : PASS
2061 19:56:32.053951 RX DQ/DQS(Engine): PASS
2062 19:56:32.057310 TX OE : NO K
2063 19:56:32.057838 All Pass.
2064 19:56:32.058173
2065 19:56:32.060003 CH 0, Rank 1
2066 19:56:32.060424 SW Impedance : PASS
2067 19:56:32.063707 DUTY Scan : NO K
2068 19:56:32.067042 ZQ Calibration : PASS
2069 19:56:32.067462 Jitter Meter : NO K
2070 19:56:32.070498 CBT Training : PASS
2071 19:56:32.073380 Write leveling : PASS
2072 19:56:32.073852 RX DQS gating : PASS
2073 19:56:32.076681 RX DQ/DQS(RDDQC) : PASS
2074 19:56:32.077100 TX DQ/DQS : PASS
2075 19:56:32.079981 RX DATLAT : PASS
2076 19:56:32.083679 RX DQ/DQS(Engine): PASS
2077 19:56:32.084101 TX OE : NO K
2078 19:56:32.086746 All Pass.
2079 19:56:32.087164
2080 19:56:32.087499 CH 1, Rank 0
2081 19:56:32.090590 SW Impedance : PASS
2082 19:56:32.091101 DUTY Scan : NO K
2083 19:56:32.093446 ZQ Calibration : PASS
2084 19:56:32.097353 Jitter Meter : NO K
2085 19:56:32.097877 CBT Training : PASS
2086 19:56:32.100148 Write leveling : PASS
2087 19:56:32.103240 RX DQS gating : PASS
2088 19:56:32.103841 RX DQ/DQS(RDDQC) : PASS
2089 19:56:32.107451 TX DQ/DQS : PASS
2090 19:56:32.110746 RX DATLAT : PASS
2091 19:56:32.111266 RX DQ/DQS(Engine): PASS
2092 19:56:32.113752 TX OE : NO K
2093 19:56:32.114270 All Pass.
2094 19:56:32.114609
2095 19:56:32.117326 CH 1, Rank 1
2096 19:56:32.117844 SW Impedance : PASS
2097 19:56:32.120624 DUTY Scan : NO K
2098 19:56:32.123803 ZQ Calibration : PASS
2099 19:56:32.124373 Jitter Meter : NO K
2100 19:56:32.127083 CBT Training : PASS
2101 19:56:32.127614 Write leveling : PASS
2102 19:56:32.130000 RX DQS gating : PASS
2103 19:56:32.133675 RX DQ/DQS(RDDQC) : PASS
2104 19:56:32.134096 TX DQ/DQS : PASS
2105 19:56:32.136912 RX DATLAT : PASS
2106 19:56:32.140198 RX DQ/DQS(Engine): PASS
2107 19:56:32.140618 TX OE : NO K
2108 19:56:32.143563 All Pass.
2109 19:56:32.144136
2110 19:56:32.144477 DramC Write-DBI off
2111 19:56:32.147163 PER_BANK_REFRESH: Hybrid Mode
2112 19:56:32.147582 TX_TRACKING: ON
2113 19:56:32.150095 [GetDramInforAfterCalByMRR] Vendor 6.
2114 19:56:32.156579 [GetDramInforAfterCalByMRR] Revision 606.
2115 19:56:32.159940 [GetDramInforAfterCalByMRR] Revision 2 0.
2116 19:56:32.160363 MR0 0x3b3b
2117 19:56:32.160694 MR8 0x5151
2118 19:56:32.163309 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 19:56:32.167096
2120 19:56:32.167516 MR0 0x3b3b
2121 19:56:32.167885 MR8 0x5151
2122 19:56:32.170416 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 19:56:32.170934
2124 19:56:32.180665 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2125 19:56:32.183515 [FAST_K] Save calibration result to emmc
2126 19:56:32.186902 [FAST_K] Save calibration result to emmc
2127 19:56:32.190591 dram_init: config_dvfs: 1
2128 19:56:32.194080 dramc_set_vcore_voltage set vcore to 662500
2129 19:56:32.197021 Read voltage for 1200, 2
2130 19:56:32.197447 Vio18 = 0
2131 19:56:32.197783 Vcore = 662500
2132 19:56:32.200583 Vdram = 0
2133 19:56:32.201011 Vddq = 0
2134 19:56:32.201343 Vmddr = 0
2135 19:56:32.207481 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2136 19:56:32.210586 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2137 19:56:32.213949 MEM_TYPE=3, freq_sel=15
2138 19:56:32.217704 sv_algorithm_assistance_LP4_1600
2139 19:56:32.220528 ============ PULL DRAM RESETB DOWN ============
2140 19:56:32.223891 ========== PULL DRAM RESETB DOWN end =========
2141 19:56:32.230550 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 19:56:32.233727 ===================================
2143 19:56:32.234150 LPDDR4 DRAM CONFIGURATION
2144 19:56:32.237550 ===================================
2145 19:56:32.240700 EX_ROW_EN[0] = 0x0
2146 19:56:32.243813 EX_ROW_EN[1] = 0x0
2147 19:56:32.244234 LP4Y_EN = 0x0
2148 19:56:32.247053 WORK_FSP = 0x0
2149 19:56:32.247472 WL = 0x4
2150 19:56:32.250605 RL = 0x4
2151 19:56:32.251119 BL = 0x2
2152 19:56:32.254270 RPST = 0x0
2153 19:56:32.254786 RD_PRE = 0x0
2154 19:56:32.257220 WR_PRE = 0x1
2155 19:56:32.257640 WR_PST = 0x0
2156 19:56:32.260327 DBI_WR = 0x0
2157 19:56:32.260775 DBI_RD = 0x0
2158 19:56:32.264166 OTF = 0x1
2159 19:56:32.267297 ===================================
2160 19:56:32.270599 ===================================
2161 19:56:32.271117 ANA top config
2162 19:56:32.273744 ===================================
2163 19:56:32.277369 DLL_ASYNC_EN = 0
2164 19:56:32.280645 ALL_SLAVE_EN = 0
2165 19:56:32.281199 NEW_RANK_MODE = 1
2166 19:56:32.283541 DLL_IDLE_MODE = 1
2167 19:56:32.287243 LP45_APHY_COMB_EN = 1
2168 19:56:32.290522 TX_ODT_DIS = 1
2169 19:56:32.291041 NEW_8X_MODE = 1
2170 19:56:32.294097 ===================================
2171 19:56:32.296975 ===================================
2172 19:56:32.300372 data_rate = 2400
2173 19:56:32.304160 CKR = 1
2174 19:56:32.307551 DQ_P2S_RATIO = 8
2175 19:56:32.310517 ===================================
2176 19:56:32.313677 CA_P2S_RATIO = 8
2177 19:56:32.317578 DQ_CA_OPEN = 0
2178 19:56:32.318283 DQ_SEMI_OPEN = 0
2179 19:56:32.320526 CA_SEMI_OPEN = 0
2180 19:56:32.324345 CA_FULL_RATE = 0
2181 19:56:32.327498 DQ_CKDIV4_EN = 0
2182 19:56:32.330703 CA_CKDIV4_EN = 0
2183 19:56:32.333843 CA_PREDIV_EN = 0
2184 19:56:32.334270 PH8_DLY = 17
2185 19:56:32.336991 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2186 19:56:32.340775 DQ_AAMCK_DIV = 4
2187 19:56:32.344095 CA_AAMCK_DIV = 4
2188 19:56:32.347536 CA_ADMCK_DIV = 4
2189 19:56:32.350300 DQ_TRACK_CA_EN = 0
2190 19:56:32.354526 CA_PICK = 1200
2191 19:56:32.355049 CA_MCKIO = 1200
2192 19:56:32.357734 MCKIO_SEMI = 0
2193 19:56:32.360647 PLL_FREQ = 2366
2194 19:56:32.364125 DQ_UI_PI_RATIO = 32
2195 19:56:32.367999 CA_UI_PI_RATIO = 0
2196 19:56:32.371029 ===================================
2197 19:56:32.374176 ===================================
2198 19:56:32.377151 memory_type:LPDDR4
2199 19:56:32.377576 GP_NUM : 10
2200 19:56:32.380582 SRAM_EN : 1
2201 19:56:32.381098 MD32_EN : 0
2202 19:56:32.383458 ===================================
2203 19:56:32.387387 [ANA_INIT] >>>>>>>>>>>>>>
2204 19:56:32.390551 <<<<<< [CONFIGURE PHASE]: ANA_TX
2205 19:56:32.394120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2206 19:56:32.397175 ===================================
2207 19:56:32.400383 data_rate = 2400,PCW = 0X5b00
2208 19:56:32.404211 ===================================
2209 19:56:32.407468 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2210 19:56:32.410853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 19:56:32.417291 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 19:56:32.420609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2213 19:56:32.424051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2214 19:56:32.427145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2215 19:56:32.430589 [ANA_INIT] flow start
2216 19:56:32.434277 [ANA_INIT] PLL >>>>>>>>
2217 19:56:32.434707 [ANA_INIT] PLL <<<<<<<<
2218 19:56:32.437422 [ANA_INIT] MIDPI >>>>>>>>
2219 19:56:32.440811 [ANA_INIT] MIDPI <<<<<<<<
2220 19:56:32.444364 [ANA_INIT] DLL >>>>>>>>
2221 19:56:32.444789 [ANA_INIT] DLL <<<<<<<<
2222 19:56:32.447424 [ANA_INIT] flow end
2223 19:56:32.450926 ============ LP4 DIFF to SE enter ============
2224 19:56:32.454716 ============ LP4 DIFF to SE exit ============
2225 19:56:32.457817 [ANA_INIT] <<<<<<<<<<<<<
2226 19:56:32.460847 [Flow] Enable top DCM control >>>>>
2227 19:56:32.464169 [Flow] Enable top DCM control <<<<<
2228 19:56:32.467999 Enable DLL master slave shuffle
2229 19:56:32.470812 ==============================================================
2230 19:56:32.473889 Gating Mode config
2231 19:56:32.480921 ==============================================================
2232 19:56:32.481482 Config description:
2233 19:56:32.491175 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2234 19:56:32.497594 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2235 19:56:32.504367 SELPH_MODE 0: By rank 1: By Phase
2236 19:56:32.507917 ==============================================================
2237 19:56:32.511259 GAT_TRACK_EN = 1
2238 19:56:32.514430 RX_GATING_MODE = 2
2239 19:56:32.517279 RX_GATING_TRACK_MODE = 2
2240 19:56:32.520783 SELPH_MODE = 1
2241 19:56:32.524331 PICG_EARLY_EN = 1
2242 19:56:32.527533 VALID_LAT_VALUE = 1
2243 19:56:32.530786 ==============================================================
2244 19:56:32.534179 Enter into Gating configuration >>>>
2245 19:56:32.537705 Exit from Gating configuration <<<<
2246 19:56:32.540661 Enter into DVFS_PRE_config >>>>>
2247 19:56:32.550902 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2248 19:56:32.554586 Exit from DVFS_PRE_config <<<<<
2249 19:56:32.557534 Enter into PICG configuration >>>>
2250 19:56:32.560808 Exit from PICG configuration <<<<
2251 19:56:32.564278 [RX_INPUT] configuration >>>>>
2252 19:56:32.567464 [RX_INPUT] configuration <<<<<
2253 19:56:32.573917 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2254 19:56:32.577108 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2255 19:56:32.584310 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 19:56:32.590682 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 19:56:32.597875 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 19:56:32.604158 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 19:56:32.607854 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2260 19:56:32.611309 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2261 19:56:32.614040 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2262 19:56:32.617867 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2263 19:56:32.624374 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2264 19:56:32.627483 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 19:56:32.631052 ===================================
2266 19:56:32.634182 LPDDR4 DRAM CONFIGURATION
2267 19:56:32.637683 ===================================
2268 19:56:32.638281 EX_ROW_EN[0] = 0x0
2269 19:56:32.640745 EX_ROW_EN[1] = 0x0
2270 19:56:32.641207 LP4Y_EN = 0x0
2271 19:56:32.644285 WORK_FSP = 0x0
2272 19:56:32.644712 WL = 0x4
2273 19:56:32.647442 RL = 0x4
2274 19:56:32.647899 BL = 0x2
2275 19:56:32.651504 RPST = 0x0
2276 19:56:32.652001 RD_PRE = 0x0
2277 19:56:32.654362 WR_PRE = 0x1
2278 19:56:32.658057 WR_PST = 0x0
2279 19:56:32.658578 DBI_WR = 0x0
2280 19:56:32.661389 DBI_RD = 0x0
2281 19:56:32.661917 OTF = 0x1
2282 19:56:32.664167 ===================================
2283 19:56:32.667627 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2284 19:56:32.671237 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2285 19:56:32.677705 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2286 19:56:32.681464 ===================================
2287 19:56:32.684144 LPDDR4 DRAM CONFIGURATION
2288 19:56:32.687786 ===================================
2289 19:56:32.688328 EX_ROW_EN[0] = 0x10
2290 19:56:32.691137 EX_ROW_EN[1] = 0x0
2291 19:56:32.691564 LP4Y_EN = 0x0
2292 19:56:32.694472 WORK_FSP = 0x0
2293 19:56:32.694993 WL = 0x4
2294 19:56:32.697400 RL = 0x4
2295 19:56:32.697824 BL = 0x2
2296 19:56:32.701138 RPST = 0x0
2297 19:56:32.701562 RD_PRE = 0x0
2298 19:56:32.704363 WR_PRE = 0x1
2299 19:56:32.704785 WR_PST = 0x0
2300 19:56:32.707466 DBI_WR = 0x0
2301 19:56:32.707926 DBI_RD = 0x0
2302 19:56:32.711261 OTF = 0x1
2303 19:56:32.714749 ===================================
2304 19:56:32.721055 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2305 19:56:32.721580 ==
2306 19:56:32.724388 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 19:56:32.727633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2308 19:56:32.728109 ==
2309 19:56:32.730951 [Duty_Offset_Calibration]
2310 19:56:32.731386 B0:2 B1:1 CA:1
2311 19:56:32.731766
2312 19:56:32.734141 [DutyScan_Calibration_Flow] k_type=0
2313 19:56:32.744970
2314 19:56:32.745388 ==CLK 0==
2315 19:56:32.747736 Final CLK duty delay cell = 0
2316 19:56:32.751587 [0] MAX Duty = 5187%(X100), DQS PI = 24
2317 19:56:32.754755 [0] MIN Duty = 4875%(X100), DQS PI = 0
2318 19:56:32.755288 [0] AVG Duty = 5031%(X100)
2319 19:56:32.755624
2320 19:56:32.758318 CH0 CLK Duty spec in!! Max-Min= 312%
2321 19:56:32.764563 [DutyScan_Calibration_Flow] ====Done====
2322 19:56:32.765078
2323 19:56:32.768076 [DutyScan_Calibration_Flow] k_type=1
2324 19:56:32.783521
2325 19:56:32.784092 ==DQS 0 ==
2326 19:56:32.786630 Final DQS duty delay cell = -4
2327 19:56:32.790470 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2328 19:56:32.793572 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2329 19:56:32.796626 [-4] AVG Duty = 4937%(X100)
2330 19:56:32.797164
2331 19:56:32.797504 ==DQS 1 ==
2332 19:56:32.800075 Final DQS duty delay cell = 0
2333 19:56:32.803106 [0] MAX Duty = 5156%(X100), DQS PI = 0
2334 19:56:32.806927 [0] MIN Duty = 5000%(X100), DQS PI = 34
2335 19:56:32.809991 [0] AVG Duty = 5078%(X100)
2336 19:56:32.810418
2337 19:56:32.813192 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2338 19:56:32.813617
2339 19:56:32.816485 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2340 19:56:32.820299 [DutyScan_Calibration_Flow] ====Done====
2341 19:56:32.820723
2342 19:56:32.823387 [DutyScan_Calibration_Flow] k_type=3
2343 19:56:32.839305
2344 19:56:32.839792 ==DQM 0 ==
2345 19:56:32.842485 Final DQM duty delay cell = 0
2346 19:56:32.846248 [0] MAX Duty = 5156%(X100), DQS PI = 24
2347 19:56:32.849389 [0] MIN Duty = 4906%(X100), DQS PI = 52
2348 19:56:32.849807 [0] AVG Duty = 5031%(X100)
2349 19:56:32.852982
2350 19:56:32.853393 ==DQM 1 ==
2351 19:56:32.855839 Final DQM duty delay cell = -4
2352 19:56:32.859337 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2353 19:56:32.862771 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2354 19:56:32.866308 [-4] AVG Duty = 4922%(X100)
2355 19:56:32.866720
2356 19:56:32.869447 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2357 19:56:32.869826
2358 19:56:32.872670 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2359 19:56:32.876389 [DutyScan_Calibration_Flow] ====Done====
2360 19:56:32.876770
2361 19:56:32.879191 [DutyScan_Calibration_Flow] k_type=2
2362 19:56:32.895985
2363 19:56:32.896460 ==DQ 0 ==
2364 19:56:32.899544 Final DQ duty delay cell = 0
2365 19:56:32.902535 [0] MAX Duty = 5031%(X100), DQS PI = 24
2366 19:56:32.906034 [0] MIN Duty = 4875%(X100), DQS PI = 0
2367 19:56:32.906115 [0] AVG Duty = 4953%(X100)
2368 19:56:32.906180
2369 19:56:32.909219 ==DQ 1 ==
2370 19:56:32.912492 Final DQ duty delay cell = 0
2371 19:56:32.915393 [0] MAX Duty = 5093%(X100), DQS PI = 24
2372 19:56:32.919208 [0] MIN Duty = 4938%(X100), DQS PI = 36
2373 19:56:32.919295 [0] AVG Duty = 5015%(X100)
2374 19:56:32.919363
2375 19:56:32.922421 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2376 19:56:32.922515
2377 19:56:32.925812 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2378 19:56:32.932582 [DutyScan_Calibration_Flow] ====Done====
2379 19:56:32.932783 ==
2380 19:56:32.935755 Dram Type= 6, Freq= 0, CH_1, rank 0
2381 19:56:32.939496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 19:56:32.939628 ==
2383 19:56:32.942592 [Duty_Offset_Calibration]
2384 19:56:32.942724 B0:1 B1:0 CA:0
2385 19:56:32.942829
2386 19:56:32.945904 [DutyScan_Calibration_Flow] k_type=0
2387 19:56:32.954946
2388 19:56:32.955326 ==CLK 0==
2389 19:56:32.958621 Final CLK duty delay cell = -4
2390 19:56:32.961835 [-4] MAX Duty = 5000%(X100), DQS PI = 22
2391 19:56:32.964873 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2392 19:56:32.968378 [-4] AVG Duty = 4937%(X100)
2393 19:56:32.968773
2394 19:56:32.971744 CH1 CLK Duty spec in!! Max-Min= 125%
2395 19:56:32.975104 [DutyScan_Calibration_Flow] ====Done====
2396 19:56:32.975493
2397 19:56:32.978100 [DutyScan_Calibration_Flow] k_type=1
2398 19:56:32.994800
2399 19:56:32.995177 ==DQS 0 ==
2400 19:56:32.998715 Final DQS duty delay cell = 0
2401 19:56:33.001680 [0] MAX Duty = 5094%(X100), DQS PI = 26
2402 19:56:33.005451 [0] MIN Duty = 4875%(X100), DQS PI = 0
2403 19:56:33.005992 [0] AVG Duty = 4984%(X100)
2404 19:56:33.008327
2405 19:56:33.008740 ==DQS 1 ==
2406 19:56:33.011603 Final DQS duty delay cell = 0
2407 19:56:33.015378 [0] MAX Duty = 5187%(X100), DQS PI = 18
2408 19:56:33.018942 [0] MIN Duty = 4938%(X100), DQS PI = 12
2409 19:56:33.019455 [0] AVG Duty = 5062%(X100)
2410 19:56:33.021916
2411 19:56:33.025173 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2412 19:56:33.025688
2413 19:56:33.028663 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2414 19:56:33.031945 [DutyScan_Calibration_Flow] ====Done====
2415 19:56:33.032475
2416 19:56:33.034961 [DutyScan_Calibration_Flow] k_type=3
2417 19:56:33.051934
2418 19:56:33.052456 ==DQM 0 ==
2419 19:56:33.055058 Final DQM duty delay cell = 0
2420 19:56:33.058576 [0] MAX Duty = 5156%(X100), DQS PI = 6
2421 19:56:33.061700 [0] MIN Duty = 5031%(X100), DQS PI = 0
2422 19:56:33.062232 [0] AVG Duty = 5093%(X100)
2423 19:56:33.062572
2424 19:56:33.064648 ==DQM 1 ==
2425 19:56:33.068484 Final DQM duty delay cell = 0
2426 19:56:33.071922 [0] MAX Duty = 5031%(X100), DQS PI = 16
2427 19:56:33.075037 [0] MIN Duty = 4907%(X100), DQS PI = 36
2428 19:56:33.075571 [0] AVG Duty = 4969%(X100)
2429 19:56:33.075980
2430 19:56:33.078547 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2431 19:56:33.081863
2432 19:56:33.085004 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2433 19:56:33.088557 [DutyScan_Calibration_Flow] ====Done====
2434 19:56:33.088982
2435 19:56:33.091250 [DutyScan_Calibration_Flow] k_type=2
2436 19:56:33.107569
2437 19:56:33.108123 ==DQ 0 ==
2438 19:56:33.110466 Final DQ duty delay cell = -4
2439 19:56:33.114118 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2440 19:56:33.117559 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2441 19:56:33.120518 [-4] AVG Duty = 4984%(X100)
2442 19:56:33.121053
2443 19:56:33.121389 ==DQ 1 ==
2444 19:56:33.124249 Final DQ duty delay cell = 0
2445 19:56:33.127406 [0] MAX Duty = 5125%(X100), DQS PI = 20
2446 19:56:33.130322 [0] MIN Duty = 4938%(X100), DQS PI = 34
2447 19:56:33.130771 [0] AVG Duty = 5031%(X100)
2448 19:56:33.133831
2449 19:56:33.137159 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2450 19:56:33.137583
2451 19:56:33.140757 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2452 19:56:33.143745 [DutyScan_Calibration_Flow] ====Done====
2453 19:56:33.147568 nWR fixed to 30
2454 19:56:33.148026 [ModeRegInit_LP4] CH0 RK0
2455 19:56:33.150452 [ModeRegInit_LP4] CH0 RK1
2456 19:56:33.154052 [ModeRegInit_LP4] CH1 RK0
2457 19:56:33.157276 [ModeRegInit_LP4] CH1 RK1
2458 19:56:33.157793 match AC timing 7
2459 19:56:33.160458 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2460 19:56:33.167387 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2461 19:56:33.170542 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2462 19:56:33.177430 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2463 19:56:33.180685 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2464 19:56:33.180982 ==
2465 19:56:33.183729 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 19:56:33.186905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 19:56:33.187086 ==
2468 19:56:33.193936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 19:56:33.197020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2470 19:56:33.207346 [CA 0] Center 39 (8~70) winsize 63
2471 19:56:33.210460 [CA 1] Center 39 (8~70) winsize 63
2472 19:56:33.213712 [CA 2] Center 35 (5~66) winsize 62
2473 19:56:33.216976 [CA 3] Center 34 (4~65) winsize 62
2474 19:56:33.220294 [CA 4] Center 33 (3~64) winsize 62
2475 19:56:33.223619 [CA 5] Center 32 (3~62) winsize 60
2476 19:56:33.223724
2477 19:56:33.227322 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2478 19:56:33.227403
2479 19:56:33.230908 [CATrainingPosCal] consider 1 rank data
2480 19:56:33.233976 u2DelayCellTimex100 = 270/100 ps
2481 19:56:33.237188 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2482 19:56:33.240698 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2483 19:56:33.246970 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2484 19:56:33.250450 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2485 19:56:33.253800 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2486 19:56:33.257479 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2487 19:56:33.257563
2488 19:56:33.260773 CA PerBit enable=1, Macro0, CA PI delay=32
2489 19:56:33.260857
2490 19:56:33.264045 [CBTSetCACLKResult] CA Dly = 32
2491 19:56:33.264132 CS Dly: 6 (0~37)
2492 19:56:33.264203 ==
2493 19:56:33.267277 Dram Type= 6, Freq= 0, CH_0, rank 1
2494 19:56:33.273797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 19:56:33.273892 ==
2496 19:56:33.276955 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 19:56:33.283595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2498 19:56:33.292692 [CA 0] Center 38 (8~69) winsize 62
2499 19:56:33.295839 [CA 1] Center 38 (8~69) winsize 62
2500 19:56:33.299348 [CA 2] Center 35 (5~66) winsize 62
2501 19:56:33.302420 [CA 3] Center 34 (4~65) winsize 62
2502 19:56:33.305912 [CA 4] Center 33 (3~64) winsize 62
2503 19:56:33.309506 [CA 5] Center 32 (3~62) winsize 60
2504 19:56:33.309588
2505 19:56:33.312877 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2506 19:56:33.313242
2507 19:56:33.316920 [CATrainingPosCal] consider 2 rank data
2508 19:56:33.319816 u2DelayCellTimex100 = 270/100 ps
2509 19:56:33.323393 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2510 19:56:33.329464 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2511 19:56:33.333275 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2512 19:56:33.336533 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2513 19:56:33.339498 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2514 19:56:33.343297 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2515 19:56:33.343889
2516 19:56:33.346797 CA PerBit enable=1, Macro0, CA PI delay=32
2517 19:56:33.347228
2518 19:56:33.350578 [CBTSetCACLKResult] CA Dly = 32
2519 19:56:33.351109 CS Dly: 6 (0~38)
2520 19:56:33.351623
2521 19:56:33.353526 ----->DramcWriteLeveling(PI) begin...
2522 19:56:33.356631 ==
2523 19:56:33.360125 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 19:56:33.363358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 19:56:33.363984 ==
2526 19:56:33.367439 Write leveling (Byte 0): 34 => 34
2527 19:56:33.369897 Write leveling (Byte 1): 29 => 29
2528 19:56:33.373671 DramcWriteLeveling(PI) end<-----
2529 19:56:33.374223
2530 19:56:33.374559 ==
2531 19:56:33.376262 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 19:56:33.380259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 19:56:33.380775 ==
2534 19:56:33.383163 [Gating] SW mode calibration
2535 19:56:33.390681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2536 19:56:33.393728 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2537 19:56:33.400385 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2538 19:56:33.403799 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2539 19:56:33.406868 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 19:56:33.413289 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 19:56:33.417102 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 19:56:33.420523 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 19:56:33.427409 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2544 19:56:33.430517 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2545 19:56:33.433965 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2546 19:56:33.440191 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 19:56:33.443748 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 19:56:33.447620 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 19:56:33.450709 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 19:56:33.457419 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 19:56:33.460374 1 0 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2552 19:56:33.463890 1 0 28 | B1->B0 | 2727 4444 | 0 0 | (0 0) (0 0)
2553 19:56:33.470867 1 1 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2554 19:56:33.473846 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 19:56:33.477227 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 19:56:33.484024 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 19:56:33.487511 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 19:56:33.490978 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 19:56:33.497297 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 19:56:33.500366 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2561 19:56:33.503969 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2562 19:56:33.510686 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 19:56:33.514156 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 19:56:33.517413 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 19:56:33.524237 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 19:56:33.527457 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 19:56:33.530932 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 19:56:33.533864 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 19:56:33.540665 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 19:56:33.543806 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 19:56:33.547337 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 19:56:33.554205 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 19:56:33.557074 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 19:56:33.561151 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 19:56:33.567579 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 19:56:33.570633 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2577 19:56:33.574043 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 19:56:33.577603 Total UI for P1: 0, mck2ui 16
2579 19:56:33.580620 best dqsien dly found for B0: ( 1, 3, 28)
2580 19:56:33.584273 Total UI for P1: 0, mck2ui 16
2581 19:56:33.587107 best dqsien dly found for B1: ( 1, 3, 30)
2582 19:56:33.590831 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2583 19:56:33.594064 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2584 19:56:33.594588
2585 19:56:33.597576 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2586 19:56:33.603766 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2587 19:56:33.604276 [Gating] SW calibration Done
2588 19:56:33.607073 ==
2589 19:56:33.607505 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 19:56:33.614017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 19:56:33.614448 ==
2592 19:56:33.614789 RX Vref Scan: 0
2593 19:56:33.615111
2594 19:56:33.617240 RX Vref 0 -> 0, step: 1
2595 19:56:33.617671
2596 19:56:33.620858 RX Delay -40 -> 252, step: 8
2597 19:56:33.623925 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2598 19:56:33.626890 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2599 19:56:33.630497 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2600 19:56:33.636826 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2601 19:56:33.639952 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2602 19:56:33.643695 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2603 19:56:33.646826 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2604 19:56:33.650293 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2605 19:56:33.656492 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2606 19:56:33.660399 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2607 19:56:33.663451 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2608 19:56:33.666634 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2609 19:56:33.670494 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2610 19:56:33.676961 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2611 19:56:33.679944 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2612 19:56:33.683301 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2613 19:56:33.683387 ==
2614 19:56:33.686967 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 19:56:33.690226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 19:56:33.690328 ==
2617 19:56:33.693274 DQS Delay:
2618 19:56:33.693398 DQS0 = 0, DQS1 = 0
2619 19:56:33.696963 DQM Delay:
2620 19:56:33.697046 DQM0 = 121, DQM1 = 113
2621 19:56:33.697111 DQ Delay:
2622 19:56:33.700172 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2623 19:56:33.703673 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2624 19:56:33.710279 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
2625 19:56:33.713513 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2626 19:56:33.713620
2627 19:56:33.713687
2628 19:56:33.713747 ==
2629 19:56:33.717069 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 19:56:33.720026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 19:56:33.720139 ==
2632 19:56:33.720233
2633 19:56:33.720297
2634 19:56:33.723354 TX Vref Scan disable
2635 19:56:33.727086 == TX Byte 0 ==
2636 19:56:33.730324 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2637 19:56:33.733280 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2638 19:56:33.736740 == TX Byte 1 ==
2639 19:56:33.739910 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2640 19:56:33.743148 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2641 19:56:33.743232 ==
2642 19:56:33.746589 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 19:56:33.750168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 19:56:33.750251 ==
2645 19:56:33.763854 TX Vref=22, minBit 0, minWin=25, winSum=407
2646 19:56:33.766922 TX Vref=24, minBit 0, minWin=24, winSum=410
2647 19:56:33.770171 TX Vref=26, minBit 7, minWin=25, winSum=418
2648 19:56:33.773483 TX Vref=28, minBit 0, minWin=26, winSum=422
2649 19:56:33.776706 TX Vref=30, minBit 0, minWin=26, winSum=422
2650 19:56:33.780023 TX Vref=32, minBit 0, minWin=26, winSum=424
2651 19:56:33.787049 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 32
2652 19:56:33.787139
2653 19:56:33.789957 Final TX Range 1 Vref 32
2654 19:56:33.790062
2655 19:56:33.790134 ==
2656 19:56:33.793698 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 19:56:33.796832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 19:56:33.796935 ==
2659 19:56:33.797016
2660 19:56:33.800025
2661 19:56:33.800127 TX Vref Scan disable
2662 19:56:33.803467 == TX Byte 0 ==
2663 19:56:33.806769 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2664 19:56:33.810057 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2665 19:56:33.813780 == TX Byte 1 ==
2666 19:56:33.817165 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2667 19:56:33.819622 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2668 19:56:33.823504
2669 19:56:33.823673 [DATLAT]
2670 19:56:33.823775 Freq=1200, CH0 RK0
2671 19:56:33.823868
2672 19:56:33.826687 DATLAT Default: 0xd
2673 19:56:33.826809 0, 0xFFFF, sum = 0
2674 19:56:33.829766 1, 0xFFFF, sum = 0
2675 19:56:33.829891 2, 0xFFFF, sum = 0
2676 19:56:33.833734 3, 0xFFFF, sum = 0
2677 19:56:33.833857 4, 0xFFFF, sum = 0
2678 19:56:33.836978 5, 0xFFFF, sum = 0
2679 19:56:33.837102 6, 0xFFFF, sum = 0
2680 19:56:33.839795 7, 0xFFFF, sum = 0
2681 19:56:33.843484 8, 0xFFFF, sum = 0
2682 19:56:33.843622 9, 0xFFFF, sum = 0
2683 19:56:33.847188 10, 0xFFFF, sum = 0
2684 19:56:33.847342 11, 0xFFFF, sum = 0
2685 19:56:33.850354 12, 0x0, sum = 1
2686 19:56:33.850540 13, 0x0, sum = 2
2687 19:56:33.850681 14, 0x0, sum = 3
2688 19:56:33.853321 15, 0x0, sum = 4
2689 19:56:33.853498 best_step = 13
2690 19:56:33.853637
2691 19:56:33.856675 ==
2692 19:56:33.856877 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 19:56:33.863423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 19:56:33.863510 ==
2695 19:56:33.863577 RX Vref Scan: 1
2696 19:56:33.863646
2697 19:56:33.866821 Set Vref Range= 32 -> 127
2698 19:56:33.866896
2699 19:56:33.869891 RX Vref 32 -> 127, step: 1
2700 19:56:33.869965
2701 19:56:33.873665 RX Delay -13 -> 252, step: 4
2702 19:56:33.873749
2703 19:56:33.877231 Set Vref, RX VrefLevel [Byte0]: 32
2704 19:56:33.880254 [Byte1]: 32
2705 19:56:33.880342
2706 19:56:33.883500 Set Vref, RX VrefLevel [Byte0]: 33
2707 19:56:33.886658 [Byte1]: 33
2708 19:56:33.886793
2709 19:56:33.889974 Set Vref, RX VrefLevel [Byte0]: 34
2710 19:56:33.893196 [Byte1]: 34
2711 19:56:33.897395
2712 19:56:33.897477 Set Vref, RX VrefLevel [Byte0]: 35
2713 19:56:33.900677 [Byte1]: 35
2714 19:56:33.905142
2715 19:56:33.905224 Set Vref, RX VrefLevel [Byte0]: 36
2716 19:56:33.909044 [Byte1]: 36
2717 19:56:33.913511
2718 19:56:33.913593 Set Vref, RX VrefLevel [Byte0]: 37
2719 19:56:33.916663 [Byte1]: 37
2720 19:56:33.921383
2721 19:56:33.921465 Set Vref, RX VrefLevel [Byte0]: 38
2722 19:56:33.924237 [Byte1]: 38
2723 19:56:33.929186
2724 19:56:33.929262 Set Vref, RX VrefLevel [Byte0]: 39
2725 19:56:33.932418 [Byte1]: 39
2726 19:56:33.936742
2727 19:56:33.936832 Set Vref, RX VrefLevel [Byte0]: 40
2728 19:56:33.940606 [Byte1]: 40
2729 19:56:33.944861
2730 19:56:33.944965 Set Vref, RX VrefLevel [Byte0]: 41
2731 19:56:33.947902 [Byte1]: 41
2732 19:56:33.952882
2733 19:56:33.952964 Set Vref, RX VrefLevel [Byte0]: 42
2734 19:56:33.956176 [Byte1]: 42
2735 19:56:33.960753
2736 19:56:33.960836 Set Vref, RX VrefLevel [Byte0]: 43
2737 19:56:33.963937 [Byte1]: 43
2738 19:56:33.968714
2739 19:56:33.968798 Set Vref, RX VrefLevel [Byte0]: 44
2740 19:56:33.971954 [Byte1]: 44
2741 19:56:33.976998
2742 19:56:33.977158 Set Vref, RX VrefLevel [Byte0]: 45
2743 19:56:33.979963 [Byte1]: 45
2744 19:56:33.984560
2745 19:56:33.984643 Set Vref, RX VrefLevel [Byte0]: 46
2746 19:56:33.987611 [Byte1]: 46
2747 19:56:33.991914
2748 19:56:33.991996 Set Vref, RX VrefLevel [Byte0]: 47
2749 19:56:33.995698 [Byte1]: 47
2750 19:56:34.000232
2751 19:56:34.000314 Set Vref, RX VrefLevel [Byte0]: 48
2752 19:56:34.003435 [Byte1]: 48
2753 19:56:34.008112
2754 19:56:34.008193 Set Vref, RX VrefLevel [Byte0]: 49
2755 19:56:34.011136 [Byte1]: 49
2756 19:56:34.015597
2757 19:56:34.015700 Set Vref, RX VrefLevel [Byte0]: 50
2758 19:56:34.018947 [Byte1]: 50
2759 19:56:34.023845
2760 19:56:34.023927 Set Vref, RX VrefLevel [Byte0]: 51
2761 19:56:34.027027 [Byte1]: 51
2762 19:56:34.031770
2763 19:56:34.031878 Set Vref, RX VrefLevel [Byte0]: 52
2764 19:56:34.034936 [Byte1]: 52
2765 19:56:34.039826
2766 19:56:34.039912 Set Vref, RX VrefLevel [Byte0]: 53
2767 19:56:34.042518 [Byte1]: 53
2768 19:56:34.047009
2769 19:56:34.047092 Set Vref, RX VrefLevel [Byte0]: 54
2770 19:56:34.050863 [Byte1]: 54
2771 19:56:34.055232
2772 19:56:34.055315 Set Vref, RX VrefLevel [Byte0]: 55
2773 19:56:34.058812 [Byte1]: 55
2774 19:56:34.063575
2775 19:56:34.063679 Set Vref, RX VrefLevel [Byte0]: 56
2776 19:56:34.066186 [Byte1]: 56
2777 19:56:34.071360
2778 19:56:34.071442 Set Vref, RX VrefLevel [Byte0]: 57
2779 19:56:34.074545 [Byte1]: 57
2780 19:56:34.079080
2781 19:56:34.079163 Set Vref, RX VrefLevel [Byte0]: 58
2782 19:56:34.082430 [Byte1]: 58
2783 19:56:34.086691
2784 19:56:34.086787 Set Vref, RX VrefLevel [Byte0]: 59
2785 19:56:34.090018 [Byte1]: 59
2786 19:56:34.094900
2787 19:56:34.094996 Set Vref, RX VrefLevel [Byte0]: 60
2788 19:56:34.098104 [Byte1]: 60
2789 19:56:34.102674
2790 19:56:34.102757 Set Vref, RX VrefLevel [Byte0]: 61
2791 19:56:34.105706 [Byte1]: 61
2792 19:56:34.110758
2793 19:56:34.110840 Set Vref, RX VrefLevel [Byte0]: 62
2794 19:56:34.113701 [Byte1]: 62
2795 19:56:34.118453
2796 19:56:34.118536 Set Vref, RX VrefLevel [Byte0]: 63
2797 19:56:34.121653 [Byte1]: 63
2798 19:56:34.126057
2799 19:56:34.126139 Set Vref, RX VrefLevel [Byte0]: 64
2800 19:56:34.129814 [Byte1]: 64
2801 19:56:34.134341
2802 19:56:34.134421 Set Vref, RX VrefLevel [Byte0]: 65
2803 19:56:34.137270 [Byte1]: 65
2804 19:56:34.141954
2805 19:56:34.142040 Set Vref, RX VrefLevel [Byte0]: 66
2806 19:56:34.145287 [Byte1]: 66
2807 19:56:34.150294
2808 19:56:34.150376 Set Vref, RX VrefLevel [Byte0]: 67
2809 19:56:34.153534 [Byte1]: 67
2810 19:56:34.158012
2811 19:56:34.158094 Set Vref, RX VrefLevel [Byte0]: 68
2812 19:56:34.161109 [Byte1]: 68
2813 19:56:34.165919
2814 19:56:34.166001 Set Vref, RX VrefLevel [Byte0]: 69
2815 19:56:34.168852 [Byte1]: 69
2816 19:56:34.173838
2817 19:56:34.173920 Final RX Vref Byte 0 = 56 to rank0
2818 19:56:34.176997 Final RX Vref Byte 1 = 48 to rank0
2819 19:56:34.180201 Final RX Vref Byte 0 = 56 to rank1
2820 19:56:34.183543 Final RX Vref Byte 1 = 48 to rank1==
2821 19:56:34.186721 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 19:56:34.193467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 19:56:34.193551 ==
2824 19:56:34.193619 DQS Delay:
2825 19:56:34.193680 DQS0 = 0, DQS1 = 0
2826 19:56:34.197259 DQM Delay:
2827 19:56:34.197340 DQM0 = 120, DQM1 = 111
2828 19:56:34.200463 DQ Delay:
2829 19:56:34.203484 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2830 19:56:34.207196 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2831 19:56:34.210189 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =106
2832 19:56:34.213681 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2833 19:56:34.213763
2834 19:56:34.213828
2835 19:56:34.220239 [DQSOSCAuto] RK0, (LSB)MR18= 0x150e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2836 19:56:34.223484 CH0 RK0: MR19=404, MR18=150E
2837 19:56:34.230167 CH0_RK0: MR19=0x404, MR18=0x150E, DQSOSC=401, MR23=63, INC=40, DEC=27
2838 19:56:34.230248
2839 19:56:34.233802 ----->DramcWriteLeveling(PI) begin...
2840 19:56:34.233908 ==
2841 19:56:34.236972 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 19:56:34.240126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 19:56:34.243303 ==
2844 19:56:34.243379 Write leveling (Byte 0): 34 => 34
2845 19:56:34.247034 Write leveling (Byte 1): 29 => 29
2846 19:56:34.250487 DramcWriteLeveling(PI) end<-----
2847 19:56:34.250569
2848 19:56:34.250635 ==
2849 19:56:34.253686 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 19:56:34.260122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 19:56:34.260205 ==
2852 19:56:34.260271 [Gating] SW mode calibration
2853 19:56:34.270274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 19:56:34.273381 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 19:56:34.276991 0 15 0 | B1->B0 | 3232 2e2e | 1 0 | (1 1) (1 1)
2856 19:56:34.283807 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 19:56:34.287161 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 19:56:34.290395 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 19:56:34.296943 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 19:56:34.300098 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 19:56:34.303834 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 19:56:34.310202 0 15 28 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 0)
2863 19:56:34.313985 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2864 19:56:34.317210 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 19:56:34.323747 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 19:56:34.326940 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 19:56:34.330520 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 19:56:34.337175 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 19:56:34.340275 1 0 24 | B1->B0 | 2929 2726 | 0 1 | (0 0) (0 0)
2870 19:56:34.343763 1 0 28 | B1->B0 | 3636 3939 | 1 1 | (0 0) (0 0)
2871 19:56:34.347284 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 19:56:34.353565 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 19:56:34.356999 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 19:56:34.360463 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 19:56:34.367248 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 19:56:34.370437 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 19:56:34.373643 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 19:56:34.380493 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2879 19:56:34.384200 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2880 19:56:34.386994 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 19:56:34.394231 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 19:56:34.397248 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 19:56:34.400909 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 19:56:34.407430 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 19:56:34.410638 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 19:56:34.413888 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 19:56:34.420901 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 19:56:34.423860 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 19:56:34.427619 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 19:56:34.430832 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 19:56:34.437265 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 19:56:34.441034 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 19:56:34.444235 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 19:56:34.451157 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2895 19:56:34.454001 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2896 19:56:34.457326 Total UI for P1: 0, mck2ui 16
2897 19:56:34.460667 best dqsien dly found for B1: ( 1, 3, 28)
2898 19:56:34.464269 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 19:56:34.467275 Total UI for P1: 0, mck2ui 16
2900 19:56:34.470994 best dqsien dly found for B0: ( 1, 3, 30)
2901 19:56:34.474417 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2902 19:56:34.477695 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2903 19:56:34.477946
2904 19:56:34.484593 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2905 19:56:34.487710 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2906 19:56:34.487961 [Gating] SW calibration Done
2907 19:56:34.490872 ==
2908 19:56:34.494432 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 19:56:34.497404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 19:56:34.497653 ==
2911 19:56:34.497905 RX Vref Scan: 0
2912 19:56:34.498146
2913 19:56:34.500587 RX Vref 0 -> 0, step: 1
2914 19:56:34.500837
2915 19:56:34.503974 RX Delay -40 -> 252, step: 8
2916 19:56:34.507482 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2917 19:56:34.510925 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2918 19:56:34.514448 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2919 19:56:34.520654 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2920 19:56:34.523775 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2921 19:56:34.527518 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2922 19:56:34.530482 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2923 19:56:34.534321 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2924 19:56:34.540599 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2925 19:56:34.544333 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2926 19:56:34.547563 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2927 19:56:34.550721 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2928 19:56:34.554465 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2929 19:56:34.561199 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2930 19:56:34.564351 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2931 19:56:34.567600 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2932 19:56:34.567721 ==
2933 19:56:34.570680 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 19:56:34.574324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 19:56:34.574407 ==
2936 19:56:34.577705 DQS Delay:
2937 19:56:34.577788 DQS0 = 0, DQS1 = 0
2938 19:56:34.581252 DQM Delay:
2939 19:56:34.581389 DQM0 = 122, DQM1 = 113
2940 19:56:34.581457 DQ Delay:
2941 19:56:34.584175 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2942 19:56:34.587595 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2943 19:56:34.594414 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2944 19:56:34.597381 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2945 19:56:34.597462
2946 19:56:34.597528
2947 19:56:34.597588 ==
2948 19:56:34.601128 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 19:56:34.604167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 19:56:34.604243 ==
2951 19:56:34.604305
2952 19:56:34.604363
2953 19:56:34.607555 TX Vref Scan disable
2954 19:56:34.610946 == TX Byte 0 ==
2955 19:56:34.614384 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2956 19:56:34.617702 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2957 19:56:34.617780 == TX Byte 1 ==
2958 19:56:34.624538 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2959 19:56:34.627764 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2960 19:56:34.627844 ==
2961 19:56:34.630784 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 19:56:34.634382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 19:56:34.634456 ==
2964 19:56:34.647666 TX Vref=22, minBit 1, minWin=25, winSum=409
2965 19:56:34.650828 TX Vref=24, minBit 3, minWin=25, winSum=420
2966 19:56:34.654563 TX Vref=26, minBit 0, minWin=26, winSum=422
2967 19:56:34.657734 TX Vref=28, minBit 1, minWin=26, winSum=427
2968 19:56:34.660900 TX Vref=30, minBit 5, minWin=25, winSum=423
2969 19:56:34.667589 TX Vref=32, minBit 5, minWin=25, winSum=425
2970 19:56:34.670726 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
2971 19:56:34.670804
2972 19:56:34.674420 Final TX Range 1 Vref 28
2973 19:56:34.674493
2974 19:56:34.674555 ==
2975 19:56:34.677444 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 19:56:34.681144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 19:56:34.681218 ==
2978 19:56:34.681288
2979 19:56:34.684704
2980 19:56:34.684777 TX Vref Scan disable
2981 19:56:34.687850 == TX Byte 0 ==
2982 19:56:34.691086 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2983 19:56:34.694341 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2984 19:56:34.698101 == TX Byte 1 ==
2985 19:56:34.701186 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2986 19:56:34.704159 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2987 19:56:34.704277
2988 19:56:34.707677 [DATLAT]
2989 19:56:34.707760 Freq=1200, CH0 RK1
2990 19:56:34.707826
2991 19:56:34.710779 DATLAT Default: 0xd
2992 19:56:34.710861 0, 0xFFFF, sum = 0
2993 19:56:34.714323 1, 0xFFFF, sum = 0
2994 19:56:34.714407 2, 0xFFFF, sum = 0
2995 19:56:34.717852 3, 0xFFFF, sum = 0
2996 19:56:34.717936 4, 0xFFFF, sum = 0
2997 19:56:34.721437 5, 0xFFFF, sum = 0
2998 19:56:34.724406 6, 0xFFFF, sum = 0
2999 19:56:34.724490 7, 0xFFFF, sum = 0
3000 19:56:34.727360 8, 0xFFFF, sum = 0
3001 19:56:34.727444 9, 0xFFFF, sum = 0
3002 19:56:34.730720 10, 0xFFFF, sum = 0
3003 19:56:34.730804 11, 0xFFFF, sum = 0
3004 19:56:34.734338 12, 0x0, sum = 1
3005 19:56:34.734421 13, 0x0, sum = 2
3006 19:56:34.737358 14, 0x0, sum = 3
3007 19:56:34.737510 15, 0x0, sum = 4
3008 19:56:34.737593 best_step = 13
3009 19:56:34.737655
3010 19:56:34.741171 ==
3011 19:56:34.744321 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 19:56:34.747552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 19:56:34.747694 ==
3014 19:56:34.747763 RX Vref Scan: 0
3015 19:56:34.747825
3016 19:56:34.750620 RX Vref 0 -> 0, step: 1
3017 19:56:34.750702
3018 19:56:34.754349 RX Delay -13 -> 252, step: 4
3019 19:56:34.757522 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3020 19:56:34.764470 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3021 19:56:34.767627 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3022 19:56:34.771286 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3023 19:56:34.774430 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3024 19:56:34.777658 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3025 19:56:34.780739 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3026 19:56:34.787923 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3027 19:56:34.791124 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3028 19:56:34.794225 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3029 19:56:34.798142 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3030 19:56:34.801173 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3031 19:56:34.808147 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3032 19:56:34.811326 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3033 19:56:34.814410 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3034 19:56:34.817681 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3035 19:56:34.817764 ==
3036 19:56:34.820937 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 19:56:34.827680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 19:56:34.827776 ==
3039 19:56:34.827842 DQS Delay:
3040 19:56:34.827902 DQS0 = 0, DQS1 = 0
3041 19:56:34.831416 DQM Delay:
3042 19:56:34.831497 DQM0 = 120, DQM1 = 110
3043 19:56:34.834233 DQ Delay:
3044 19:56:34.837741 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3045 19:56:34.841281 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3046 19:56:34.844490 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3047 19:56:34.847693 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3048 19:56:34.847776
3049 19:56:34.847841
3050 19:56:34.854692 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3051 19:56:34.857926 CH0 RK1: MR19=403, MR18=11F2
3052 19:56:34.865295 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3053 19:56:34.868142 [RxdqsGatingPostProcess] freq 1200
3054 19:56:34.874966 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3055 19:56:34.878035 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 19:56:34.878118 best DQS1 dly(2T, 0.5T) = (0, 11)
3057 19:56:34.881755 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 19:56:34.884865 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3059 19:56:34.888139 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 19:56:34.891161 best DQS1 dly(2T, 0.5T) = (0, 11)
3061 19:56:34.894686 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 19:56:34.898400 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3063 19:56:34.901679 Pre-setting of DQS Precalculation
3064 19:56:34.908382 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3065 19:56:34.908464 ==
3066 19:56:34.911511 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 19:56:34.914782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 19:56:34.914865 ==
3069 19:56:34.921750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 19:56:34.924997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3071 19:56:34.934289 [CA 0] Center 37 (6~68) winsize 63
3072 19:56:34.937757 [CA 1] Center 37 (7~68) winsize 62
3073 19:56:34.941355 [CA 2] Center 34 (4~65) winsize 62
3074 19:56:34.944628 [CA 3] Center 34 (4~64) winsize 61
3075 19:56:34.947544 [CA 4] Center 34 (4~64) winsize 61
3076 19:56:34.951380 [CA 5] Center 33 (3~63) winsize 61
3077 19:56:34.951516
3078 19:56:34.954549 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3079 19:56:34.954685
3080 19:56:34.957710 [CATrainingPosCal] consider 1 rank data
3081 19:56:34.960875 u2DelayCellTimex100 = 270/100 ps
3082 19:56:34.964556 CA0 delay=37 (6~68),Diff = 4 PI (19 cell)
3083 19:56:34.967522 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3084 19:56:34.974673 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3085 19:56:34.977986 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3086 19:56:34.981539 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3087 19:56:34.984552 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3088 19:56:34.984944
3089 19:56:34.988172 CA PerBit enable=1, Macro0, CA PI delay=33
3090 19:56:34.988620
3091 19:56:34.991030 [CBTSetCACLKResult] CA Dly = 33
3092 19:56:34.991454 CS Dly: 7 (0~38)
3093 19:56:34.991852 ==
3094 19:56:34.994958 Dram Type= 6, Freq= 0, CH_1, rank 1
3095 19:56:35.001240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 19:56:35.001672 ==
3097 19:56:35.004681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 19:56:35.011267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3099 19:56:35.020220 [CA 0] Center 37 (7~68) winsize 62
3100 19:56:35.023277 [CA 1] Center 38 (8~68) winsize 61
3101 19:56:35.027129 [CA 2] Center 35 (5~65) winsize 61
3102 19:56:35.030293 [CA 3] Center 34 (4~65) winsize 62
3103 19:56:35.033527 [CA 4] Center 34 (4~65) winsize 62
3104 19:56:35.036777 [CA 5] Center 34 (4~64) winsize 61
3105 19:56:35.037202
3106 19:56:35.040508 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3107 19:56:35.041063
3108 19:56:35.043557 [CATrainingPosCal] consider 2 rank data
3109 19:56:35.046795 u2DelayCellTimex100 = 270/100 ps
3110 19:56:35.050357 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3111 19:56:35.053559 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3112 19:56:35.060272 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3113 19:56:35.063697 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3114 19:56:35.066627 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3115 19:56:35.070535 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3116 19:56:35.070924
3117 19:56:35.073673 CA PerBit enable=1, Macro0, CA PI delay=33
3118 19:56:35.074042
3119 19:56:35.076896 [CBTSetCACLKResult] CA Dly = 33
3120 19:56:35.077331 CS Dly: 8 (0~40)
3121 19:56:35.077723
3122 19:56:35.080010 ----->DramcWriteLeveling(PI) begin...
3123 19:56:35.083576 ==
3124 19:56:35.084066 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 19:56:35.090407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 19:56:35.090851 ==
3127 19:56:35.093822 Write leveling (Byte 0): 27 => 27
3128 19:56:35.097076 Write leveling (Byte 1): 29 => 29
3129 19:56:35.100154 DramcWriteLeveling(PI) end<-----
3130 19:56:35.100598
3131 19:56:35.100944 ==
3132 19:56:35.103507 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 19:56:35.106961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 19:56:35.107481 ==
3135 19:56:35.110722 [Gating] SW mode calibration
3136 19:56:35.117092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3137 19:56:35.120476 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3138 19:56:35.126791 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3139 19:56:35.130601 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 19:56:35.133578 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 19:56:35.140576 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 19:56:35.143615 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 19:56:35.147081 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 19:56:35.153805 0 15 24 | B1->B0 | 3131 2c2c | 1 1 | (1 0) (1 0)
3145 19:56:35.156967 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3146 19:56:35.160912 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 19:56:35.167318 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 19:56:35.170204 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 19:56:35.173564 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 19:56:35.180523 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 19:56:35.184261 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3152 19:56:35.187016 1 0 24 | B1->B0 | 2b2b 4040 | 0 0 | (0 0) (0 0)
3153 19:56:35.190543 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 19:56:35.197048 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 19:56:35.200322 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 19:56:35.203989 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 19:56:35.210333 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 19:56:35.214030 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 19:56:35.217017 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 19:56:35.223751 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3161 19:56:35.226872 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3162 19:56:35.230465 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 19:56:35.237016 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 19:56:35.240712 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 19:56:35.243904 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 19:56:35.250625 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 19:56:35.253681 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 19:56:35.257433 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 19:56:35.263602 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 19:56:35.267234 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 19:56:35.270726 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 19:56:35.273673 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 19:56:35.280842 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 19:56:35.283769 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 19:56:35.287335 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 19:56:35.294138 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3177 19:56:35.297284 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3178 19:56:35.300522 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 19:56:35.304319 Total UI for P1: 0, mck2ui 16
3180 19:56:35.307124 best dqsien dly found for B0: ( 1, 3, 26)
3181 19:56:35.310852 Total UI for P1: 0, mck2ui 16
3182 19:56:35.313871 best dqsien dly found for B1: ( 1, 3, 26)
3183 19:56:35.317615 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3184 19:56:35.320749 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3185 19:56:35.321170
3186 19:56:35.327424 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3187 19:56:35.330427 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3188 19:56:35.330871 [Gating] SW calibration Done
3189 19:56:35.334351 ==
3190 19:56:35.334764 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 19:56:35.340469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 19:56:35.340898 ==
3193 19:56:35.341312 RX Vref Scan: 0
3194 19:56:35.341632
3195 19:56:35.344015 RX Vref 0 -> 0, step: 1
3196 19:56:35.344467
3197 19:56:35.347518 RX Delay -40 -> 252, step: 8
3198 19:56:35.350687 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3199 19:56:35.354225 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3200 19:56:35.357568 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3201 19:56:35.364318 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3202 19:56:35.367422 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3203 19:56:35.370577 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3204 19:56:35.374305 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3205 19:56:35.377351 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3206 19:56:35.384294 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3207 19:56:35.387215 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3208 19:56:35.391012 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3209 19:56:35.393920 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3210 19:56:35.397335 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3211 19:56:35.403901 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3212 19:56:35.407271 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3213 19:56:35.410967 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3214 19:56:35.411488 ==
3215 19:56:35.413929 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 19:56:35.417299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 19:56:35.417718 ==
3218 19:56:35.420906 DQS Delay:
3219 19:56:35.421321 DQS0 = 0, DQS1 = 0
3220 19:56:35.424141 DQM Delay:
3221 19:56:35.424561 DQM0 = 119, DQM1 = 116
3222 19:56:35.424894 DQ Delay:
3223 19:56:35.430962 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3224 19:56:35.433920 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3225 19:56:35.437507 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3226 19:56:35.440929 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3227 19:56:35.441350
3228 19:56:35.441685
3229 19:56:35.441995 ==
3230 19:56:35.443888 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 19:56:35.447722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 19:56:35.448151 ==
3233 19:56:35.448488
3234 19:56:35.448798
3235 19:56:35.450597 TX Vref Scan disable
3236 19:56:35.454336 == TX Byte 0 ==
3237 19:56:35.457838 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3238 19:56:35.460809 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3239 19:56:35.463845 == TX Byte 1 ==
3240 19:56:35.467561 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3241 19:56:35.470419 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3242 19:56:35.470842 ==
3243 19:56:35.473872 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 19:56:35.477015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 19:56:35.480521 ==
3246 19:56:35.490812 TX Vref=22, minBit 11, minWin=24, winSum=413
3247 19:56:35.493894 TX Vref=24, minBit 9, minWin=25, winSum=419
3248 19:56:35.497253 TX Vref=26, minBit 10, minWin=25, winSum=426
3249 19:56:35.500770 TX Vref=28, minBit 1, minWin=26, winSum=428
3250 19:56:35.504185 TX Vref=30, minBit 9, minWin=26, winSum=433
3251 19:56:35.507680 TX Vref=32, minBit 9, minWin=26, winSum=431
3252 19:56:35.514123 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3253 19:56:35.514544
3254 19:56:35.517752 Final TX Range 1 Vref 30
3255 19:56:35.518174
3256 19:56:35.518510 ==
3257 19:56:35.520761 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 19:56:35.524242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 19:56:35.524666 ==
3260 19:56:35.525002
3261 19:56:35.525312
3262 19:56:35.527539 TX Vref Scan disable
3263 19:56:35.530619 == TX Byte 0 ==
3264 19:56:35.534574 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3265 19:56:35.537779 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3266 19:56:35.540950 == TX Byte 1 ==
3267 19:56:35.544470 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3268 19:56:35.547591 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3269 19:56:35.548065
3270 19:56:35.550890 [DATLAT]
3271 19:56:35.551312 Freq=1200, CH1 RK0
3272 19:56:35.551715
3273 19:56:35.554582 DATLAT Default: 0xd
3274 19:56:35.554999 0, 0xFFFF, sum = 0
3275 19:56:35.557953 1, 0xFFFF, sum = 0
3276 19:56:35.558381 2, 0xFFFF, sum = 0
3277 19:56:35.561093 3, 0xFFFF, sum = 0
3278 19:56:35.561521 4, 0xFFFF, sum = 0
3279 19:56:35.564250 5, 0xFFFF, sum = 0
3280 19:56:35.564679 6, 0xFFFF, sum = 0
3281 19:56:35.568013 7, 0xFFFF, sum = 0
3282 19:56:35.568441 8, 0xFFFF, sum = 0
3283 19:56:35.571127 9, 0xFFFF, sum = 0
3284 19:56:35.571551 10, 0xFFFF, sum = 0
3285 19:56:35.574368 11, 0xFFFF, sum = 0
3286 19:56:35.574796 12, 0x0, sum = 1
3287 19:56:35.577967 13, 0x0, sum = 2
3288 19:56:35.578394 14, 0x0, sum = 3
3289 19:56:35.581007 15, 0x0, sum = 4
3290 19:56:35.581437 best_step = 13
3291 19:56:35.581773
3292 19:56:35.582082 ==
3293 19:56:35.584469 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 19:56:35.591401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 19:56:35.591870 ==
3296 19:56:35.592212 RX Vref Scan: 1
3297 19:56:35.592525
3298 19:56:35.594342 Set Vref Range= 32 -> 127
3299 19:56:35.594761
3300 19:56:35.597907 RX Vref 32 -> 127, step: 1
3301 19:56:35.598326
3302 19:56:35.598658 RX Delay -5 -> 252, step: 4
3303 19:56:35.598969
3304 19:56:35.601451 Set Vref, RX VrefLevel [Byte0]: 32
3305 19:56:35.604797 [Byte1]: 32
3306 19:56:35.608844
3307 19:56:35.609265 Set Vref, RX VrefLevel [Byte0]: 33
3308 19:56:35.611861 [Byte1]: 33
3309 19:56:35.616681
3310 19:56:35.617099 Set Vref, RX VrefLevel [Byte0]: 34
3311 19:56:35.620010 [Byte1]: 34
3312 19:56:35.624591
3313 19:56:35.625008 Set Vref, RX VrefLevel [Byte0]: 35
3314 19:56:35.627843 [Byte1]: 35
3315 19:56:35.632350
3316 19:56:35.632771 Set Vref, RX VrefLevel [Byte0]: 36
3317 19:56:35.635578 [Byte1]: 36
3318 19:56:35.639930
3319 19:56:35.640344 Set Vref, RX VrefLevel [Byte0]: 37
3320 19:56:35.643471 [Byte1]: 37
3321 19:56:35.648024
3322 19:56:35.648443 Set Vref, RX VrefLevel [Byte0]: 38
3323 19:56:35.651175 [Byte1]: 38
3324 19:56:35.655757
3325 19:56:35.656130 Set Vref, RX VrefLevel [Byte0]: 39
3326 19:56:35.659254 [Byte1]: 39
3327 19:56:35.663932
3328 19:56:35.664362 Set Vref, RX VrefLevel [Byte0]: 40
3329 19:56:35.667297 [Byte1]: 40
3330 19:56:35.671580
3331 19:56:35.672055 Set Vref, RX VrefLevel [Byte0]: 41
3332 19:56:35.674800 [Byte1]: 41
3333 19:56:35.679336
3334 19:56:35.679792 Set Vref, RX VrefLevel [Byte0]: 42
3335 19:56:35.683223 [Byte1]: 42
3336 19:56:35.687544
3337 19:56:35.688007 Set Vref, RX VrefLevel [Byte0]: 43
3338 19:56:35.690621 [Byte1]: 43
3339 19:56:35.695603
3340 19:56:35.696046 Set Vref, RX VrefLevel [Byte0]: 44
3341 19:56:35.698804 [Byte1]: 44
3342 19:56:35.703253
3343 19:56:35.703697 Set Vref, RX VrefLevel [Byte0]: 45
3344 19:56:35.706599 [Byte1]: 45
3345 19:56:35.710628
3346 19:56:35.711048 Set Vref, RX VrefLevel [Byte0]: 46
3347 19:56:35.714220 [Byte1]: 46
3348 19:56:35.718760
3349 19:56:35.719173 Set Vref, RX VrefLevel [Byte0]: 47
3350 19:56:35.722276 [Byte1]: 47
3351 19:56:35.726497
3352 19:56:35.726912 Set Vref, RX VrefLevel [Byte0]: 48
3353 19:56:35.729933 [Byte1]: 48
3354 19:56:35.734632
3355 19:56:35.735160 Set Vref, RX VrefLevel [Byte0]: 49
3356 19:56:35.737423 [Byte1]: 49
3357 19:56:35.742147
3358 19:56:35.742569 Set Vref, RX VrefLevel [Byte0]: 50
3359 19:56:35.745651 [Byte1]: 50
3360 19:56:35.750184
3361 19:56:35.750602 Set Vref, RX VrefLevel [Byte0]: 51
3362 19:56:35.753502 [Byte1]: 51
3363 19:56:35.758220
3364 19:56:35.758739 Set Vref, RX VrefLevel [Byte0]: 52
3365 19:56:35.761035 [Byte1]: 52
3366 19:56:35.765756
3367 19:56:35.766166 Set Vref, RX VrefLevel [Byte0]: 53
3368 19:56:35.769273 [Byte1]: 53
3369 19:56:35.773399
3370 19:56:35.773815 Set Vref, RX VrefLevel [Byte0]: 54
3371 19:56:35.776847 [Byte1]: 54
3372 19:56:35.781296
3373 19:56:35.781710 Set Vref, RX VrefLevel [Byte0]: 55
3374 19:56:35.784593 [Byte1]: 55
3375 19:56:35.789495
3376 19:56:35.789908 Set Vref, RX VrefLevel [Byte0]: 56
3377 19:56:35.792712 [Byte1]: 56
3378 19:56:35.796878
3379 19:56:35.797332 Set Vref, RX VrefLevel [Byte0]: 57
3380 19:56:35.800465 [Byte1]: 57
3381 19:56:35.804988
3382 19:56:35.805406 Set Vref, RX VrefLevel [Byte0]: 58
3383 19:56:35.808182 [Byte1]: 58
3384 19:56:35.812654
3385 19:56:35.813073 Set Vref, RX VrefLevel [Byte0]: 59
3386 19:56:35.816447 [Byte1]: 59
3387 19:56:35.820794
3388 19:56:35.821213 Set Vref, RX VrefLevel [Byte0]: 60
3389 19:56:35.823983 [Byte1]: 60
3390 19:56:35.828807
3391 19:56:35.829332 Set Vref, RX VrefLevel [Byte0]: 61
3392 19:56:35.831797 [Byte1]: 61
3393 19:56:35.836131
3394 19:56:35.836580 Set Vref, RX VrefLevel [Byte0]: 62
3395 19:56:35.839859 [Byte1]: 62
3396 19:56:35.844489
3397 19:56:35.844931 Set Vref, RX VrefLevel [Byte0]: 63
3398 19:56:35.847367 [Byte1]: 63
3399 19:56:35.851980
3400 19:56:35.852400 Set Vref, RX VrefLevel [Byte0]: 64
3401 19:56:35.855121 [Byte1]: 64
3402 19:56:35.860039
3403 19:56:35.860467 Set Vref, RX VrefLevel [Byte0]: 65
3404 19:56:35.863246 [Byte1]: 65
3405 19:56:35.867481
3406 19:56:35.867935 Set Vref, RX VrefLevel [Byte0]: 66
3407 19:56:35.871188 [Byte1]: 66
3408 19:56:35.875683
3409 19:56:35.876104 Set Vref, RX VrefLevel [Byte0]: 67
3410 19:56:35.879079 [Byte1]: 67
3411 19:56:35.883270
3412 19:56:35.883884 Set Vref, RX VrefLevel [Byte0]: 68
3413 19:56:35.886977 [Byte1]: 68
3414 19:56:35.891582
3415 19:56:35.892155 Final RX Vref Byte 0 = 56 to rank0
3416 19:56:35.894577 Final RX Vref Byte 1 = 48 to rank0
3417 19:56:35.898414 Final RX Vref Byte 0 = 56 to rank1
3418 19:56:35.901586 Final RX Vref Byte 1 = 48 to rank1==
3419 19:56:35.905001 Dram Type= 6, Freq= 0, CH_1, rank 0
3420 19:56:35.908129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3421 19:56:35.911595 ==
3422 19:56:35.912162 DQS Delay:
3423 19:56:35.912509 DQS0 = 0, DQS1 = 0
3424 19:56:35.914573 DQM Delay:
3425 19:56:35.914995 DQM0 = 120, DQM1 = 116
3426 19:56:35.918264 DQ Delay:
3427 19:56:35.921528 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3428 19:56:35.925084 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =120
3429 19:56:35.928133 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3430 19:56:35.931387 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3431 19:56:35.931943
3432 19:56:35.932286
3433 19:56:35.938072 [DQSOSCAuto] RK0, (LSB)MR18= 0x12, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3434 19:56:35.941197 CH1 RK0: MR19=404, MR18=12
3435 19:56:35.948193 CH1_RK0: MR19=0x404, MR18=0x12, DQSOSC=403, MR23=63, INC=40, DEC=26
3436 19:56:35.948616
3437 19:56:35.951322 ----->DramcWriteLeveling(PI) begin...
3438 19:56:35.951874 ==
3439 19:56:35.954845 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 19:56:35.957831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 19:56:35.958254 ==
3442 19:56:35.961176 Write leveling (Byte 0): 25 => 25
3443 19:56:35.964876 Write leveling (Byte 1): 29 => 29
3444 19:56:35.967997 DramcWriteLeveling(PI) end<-----
3445 19:56:35.968417
3446 19:56:35.968754 ==
3447 19:56:35.971482 Dram Type= 6, Freq= 0, CH_1, rank 1
3448 19:56:35.974806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 19:56:35.978112 ==
3450 19:56:35.978539 [Gating] SW mode calibration
3451 19:56:35.984897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3452 19:56:35.991295 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3453 19:56:35.994821 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 19:56:36.001652 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 19:56:36.005489 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 19:56:36.008429 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 19:56:36.012007 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 19:56:36.018448 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3459 19:56:36.021729 0 15 24 | B1->B0 | 2d2d 3434 | 0 1 | (1 0) (1 1)
3460 19:56:36.025646 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3461 19:56:36.031833 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 19:56:36.035294 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 19:56:36.038296 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 19:56:36.044991 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 19:56:36.048159 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 19:56:36.051339 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3467 19:56:36.058374 1 0 24 | B1->B0 | 4141 2727 | 0 1 | (0 0) (0 0)
3468 19:56:36.061455 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 19:56:36.064451 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 19:56:36.071896 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 19:56:36.074447 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 19:56:36.078528 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 19:56:36.084657 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 19:56:36.087924 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3475 19:56:36.091632 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3476 19:56:36.097750 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3477 19:56:36.101222 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 19:56:36.104860 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 19:56:36.111375 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 19:56:36.114449 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 19:56:36.117531 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 19:56:36.124364 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 19:56:36.128053 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 19:56:36.131335 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 19:56:36.138128 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 19:56:36.140973 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 19:56:36.144183 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 19:56:36.151302 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 19:56:36.154816 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 19:56:36.158148 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3491 19:56:36.161059 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3492 19:56:36.168010 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3493 19:56:36.171098 Total UI for P1: 0, mck2ui 16
3494 19:56:36.174312 best dqsien dly found for B1: ( 1, 3, 22)
3495 19:56:36.177901 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 19:56:36.181455 Total UI for P1: 0, mck2ui 16
3497 19:56:36.184649 best dqsien dly found for B0: ( 1, 3, 26)
3498 19:56:36.187580 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3499 19:56:36.191034 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3500 19:56:36.191453
3501 19:56:36.194623 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3502 19:56:36.197882 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3503 19:56:36.201007 [Gating] SW calibration Done
3504 19:56:36.201424 ==
3505 19:56:36.204707 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 19:56:36.211296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 19:56:36.211850 ==
3508 19:56:36.212197 RX Vref Scan: 0
3509 19:56:36.212510
3510 19:56:36.214261 RX Vref 0 -> 0, step: 1
3511 19:56:36.214677
3512 19:56:36.218265 RX Delay -40 -> 252, step: 8
3513 19:56:36.221317 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3514 19:56:36.224878 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3515 19:56:36.228062 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3516 19:56:36.231245 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3517 19:56:36.237910 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3518 19:56:36.241426 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3519 19:56:36.244339 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3520 19:56:36.247801 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3521 19:56:36.251055 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3522 19:56:36.255120 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3523 19:56:36.261223 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3524 19:56:36.264985 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3525 19:56:36.268464 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3526 19:56:36.271686 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3527 19:56:36.278311 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3528 19:56:36.281530 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3529 19:56:36.281950 ==
3530 19:56:36.284715 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 19:56:36.287807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 19:56:36.288285 ==
3533 19:56:36.288659 DQS Delay:
3534 19:56:36.291349 DQS0 = 0, DQS1 = 0
3535 19:56:36.291819 DQM Delay:
3536 19:56:36.294650 DQM0 = 120, DQM1 = 119
3537 19:56:36.295072 DQ Delay:
3538 19:56:36.298098 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3539 19:56:36.301010 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3540 19:56:36.304417 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3541 19:56:36.311368 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3542 19:56:36.311986
3543 19:56:36.312519
3544 19:56:36.312956 ==
3545 19:56:36.314387 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 19:56:36.318378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 19:56:36.319051 ==
3548 19:56:36.319529
3549 19:56:36.319902
3550 19:56:36.321139 TX Vref Scan disable
3551 19:56:36.321559 == TX Byte 0 ==
3552 19:56:36.328040 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3553 19:56:36.330722 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3554 19:56:36.331146 == TX Byte 1 ==
3555 19:56:36.337931 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3556 19:56:36.340668 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3557 19:56:36.341123 ==
3558 19:56:36.344224 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 19:56:36.347477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 19:56:36.347994 ==
3561 19:56:36.360280 TX Vref=22, minBit 9, minWin=25, winSum=418
3562 19:56:36.364173 TX Vref=24, minBit 10, minWin=25, winSum=425
3563 19:56:36.366972 TX Vref=26, minBit 1, minWin=26, winSum=429
3564 19:56:36.370145 TX Vref=28, minBit 9, minWin=26, winSum=433
3565 19:56:36.373755 TX Vref=30, minBit 9, minWin=26, winSum=434
3566 19:56:36.380543 TX Vref=32, minBit 11, minWin=26, winSum=435
3567 19:56:36.383880 [TxChooseVref] Worse bit 11, Min win 26, Win sum 435, Final Vref 32
3568 19:56:36.384299
3569 19:56:36.387013 Final TX Range 1 Vref 32
3570 19:56:36.387434
3571 19:56:36.387820 ==
3572 19:56:36.390141 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 19:56:36.394308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 19:56:36.397363 ==
3575 19:56:36.397892
3576 19:56:36.398235
3577 19:56:36.398541 TX Vref Scan disable
3578 19:56:36.400637 == TX Byte 0 ==
3579 19:56:36.403537 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3580 19:56:36.407010 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3581 19:56:36.410243 == TX Byte 1 ==
3582 19:56:36.413775 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3583 19:56:36.420534 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3584 19:56:36.421038
3585 19:56:36.421438 [DATLAT]
3586 19:56:36.421788 Freq=1200, CH1 RK1
3587 19:56:36.422128
3588 19:56:36.423753 DATLAT Default: 0xd
3589 19:56:36.424221 0, 0xFFFF, sum = 0
3590 19:56:36.426798 1, 0xFFFF, sum = 0
3591 19:56:36.427221 2, 0xFFFF, sum = 0
3592 19:56:36.430592 3, 0xFFFF, sum = 0
3593 19:56:36.431056 4, 0xFFFF, sum = 0
3594 19:56:36.433767 5, 0xFFFF, sum = 0
3595 19:56:36.437038 6, 0xFFFF, sum = 0
3596 19:56:36.437512 7, 0xFFFF, sum = 0
3597 19:56:36.440780 8, 0xFFFF, sum = 0
3598 19:56:36.441274 9, 0xFFFF, sum = 0
3599 19:56:36.443819 10, 0xFFFF, sum = 0
3600 19:56:36.444245 11, 0xFFFF, sum = 0
3601 19:56:36.447054 12, 0x0, sum = 1
3602 19:56:36.447477 13, 0x0, sum = 2
3603 19:56:36.450223 14, 0x0, sum = 3
3604 19:56:36.450692 15, 0x0, sum = 4
3605 19:56:36.451032 best_step = 13
3606 19:56:36.451341
3607 19:56:36.453562 ==
3608 19:56:36.456758 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 19:56:36.460342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 19:56:36.460765 ==
3611 19:56:36.461130 RX Vref Scan: 0
3612 19:56:36.461509
3613 19:56:36.463628 RX Vref 0 -> 0, step: 1
3614 19:56:36.464086
3615 19:56:36.467031 RX Delay -5 -> 252, step: 4
3616 19:56:36.470373 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3617 19:56:36.476333 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3618 19:56:36.480226 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3619 19:56:36.483158 iDelay=195, Bit 3, Center 114 (55 ~ 174) 120
3620 19:56:36.486481 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3621 19:56:36.489824 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3622 19:56:36.496691 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3623 19:56:36.499864 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3624 19:56:36.502936 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3625 19:56:36.506660 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3626 19:56:36.509791 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3627 19:56:36.516315 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3628 19:56:36.519782 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3629 19:56:36.522955 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3630 19:56:36.526390 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3631 19:56:36.529804 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3632 19:56:36.533157 ==
3633 19:56:36.536586 Dram Type= 6, Freq= 0, CH_1, rank 1
3634 19:56:36.539525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3635 19:56:36.539995 ==
3636 19:56:36.540336 DQS Delay:
3637 19:56:36.543174 DQS0 = 0, DQS1 = 0
3638 19:56:36.543599 DQM Delay:
3639 19:56:36.546495 DQM0 = 119, DQM1 = 116
3640 19:56:36.546916 DQ Delay:
3641 19:56:36.549544 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =114
3642 19:56:36.553397 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3643 19:56:36.556448 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3644 19:56:36.559674 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3645 19:56:36.560097
3646 19:56:36.560430
3647 19:56:36.569948 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3648 19:56:36.573203 CH1 RK1: MR19=403, MR18=12EF
3649 19:56:36.577114 CH1_RK1: MR19=0x403, MR18=0x12EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3650 19:56:36.580010 [RxdqsGatingPostProcess] freq 1200
3651 19:56:36.586757 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3652 19:56:36.589761 best DQS0 dly(2T, 0.5T) = (0, 11)
3653 19:56:36.593243 best DQS1 dly(2T, 0.5T) = (0, 11)
3654 19:56:36.596487 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3655 19:56:36.599792 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3656 19:56:36.603156 best DQS0 dly(2T, 0.5T) = (0, 11)
3657 19:56:36.606530 best DQS1 dly(2T, 0.5T) = (0, 11)
3658 19:56:36.609739 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3659 19:56:36.612918 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3660 19:56:36.613341 Pre-setting of DQS Precalculation
3661 19:56:36.619949 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3662 19:56:36.626578 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3663 19:56:36.633018 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3664 19:56:36.633442
3665 19:56:36.633771
3666 19:56:36.636691 [Calibration Summary] 2400 Mbps
3667 19:56:36.639832 CH 0, Rank 0
3668 19:56:36.640256 SW Impedance : PASS
3669 19:56:36.643220 DUTY Scan : NO K
3670 19:56:36.646449 ZQ Calibration : PASS
3671 19:56:36.646870 Jitter Meter : NO K
3672 19:56:36.649601 CBT Training : PASS
3673 19:56:36.652720 Write leveling : PASS
3674 19:56:36.653145 RX DQS gating : PASS
3675 19:56:36.656598 RX DQ/DQS(RDDQC) : PASS
3676 19:56:36.657022 TX DQ/DQS : PASS
3677 19:56:36.659742 RX DATLAT : PASS
3678 19:56:36.662837 RX DQ/DQS(Engine): PASS
3679 19:56:36.663256 TX OE : NO K
3680 19:56:36.666637 All Pass.
3681 19:56:36.667058
3682 19:56:36.667392 CH 0, Rank 1
3683 19:56:36.669752 SW Impedance : PASS
3684 19:56:36.670222 DUTY Scan : NO K
3685 19:56:36.672883 ZQ Calibration : PASS
3686 19:56:36.676517 Jitter Meter : NO K
3687 19:56:36.677141 CBT Training : PASS
3688 19:56:36.679421 Write leveling : PASS
3689 19:56:36.682997 RX DQS gating : PASS
3690 19:56:36.683417 RX DQ/DQS(RDDQC) : PASS
3691 19:56:36.686229 TX DQ/DQS : PASS
3692 19:56:36.689255 RX DATLAT : PASS
3693 19:56:36.689670 RX DQ/DQS(Engine): PASS
3694 19:56:36.693166 TX OE : NO K
3695 19:56:36.693625 All Pass.
3696 19:56:36.693961
3697 19:56:36.696117 CH 1, Rank 0
3698 19:56:36.696534 SW Impedance : PASS
3699 19:56:36.699346 DUTY Scan : NO K
3700 19:56:36.702575 ZQ Calibration : PASS
3701 19:56:36.702991 Jitter Meter : NO K
3702 19:56:36.706212 CBT Training : PASS
3703 19:56:36.706633 Write leveling : PASS
3704 19:56:36.709834 RX DQS gating : PASS
3705 19:56:36.712586 RX DQ/DQS(RDDQC) : PASS
3706 19:56:36.713005 TX DQ/DQS : PASS
3707 19:56:36.716347 RX DATLAT : PASS
3708 19:56:36.719673 RX DQ/DQS(Engine): PASS
3709 19:56:36.720099 TX OE : NO K
3710 19:56:36.723099 All Pass.
3711 19:56:36.723517
3712 19:56:36.723908 CH 1, Rank 1
3713 19:56:36.726412 SW Impedance : PASS
3714 19:56:36.726829 DUTY Scan : NO K
3715 19:56:36.729507 ZQ Calibration : PASS
3716 19:56:36.732649 Jitter Meter : NO K
3717 19:56:36.733067 CBT Training : PASS
3718 19:56:36.736186 Write leveling : PASS
3719 19:56:36.739293 RX DQS gating : PASS
3720 19:56:36.739767 RX DQ/DQS(RDDQC) : PASS
3721 19:56:36.742631 TX DQ/DQS : PASS
3722 19:56:36.743049 RX DATLAT : PASS
3723 19:56:36.746361 RX DQ/DQS(Engine): PASS
3724 19:56:36.749505 TX OE : NO K
3725 19:56:36.750073 All Pass.
3726 19:56:36.750707
3727 19:56:36.752476 DramC Write-DBI off
3728 19:56:36.756039 PER_BANK_REFRESH: Hybrid Mode
3729 19:56:36.756500 TX_TRACKING: ON
3730 19:56:36.766118 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3731 19:56:36.769143 [FAST_K] Save calibration result to emmc
3732 19:56:36.772535 dramc_set_vcore_voltage set vcore to 650000
3733 19:56:36.776252 Read voltage for 600, 5
3734 19:56:36.776806 Vio18 = 0
3735 19:56:36.777415 Vcore = 650000
3736 19:56:36.778013 Vdram = 0
3737 19:56:36.779303 Vddq = 0
3738 19:56:36.779836 Vmddr = 0
3739 19:56:36.786259 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3740 19:56:36.789147 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3741 19:56:36.792930 MEM_TYPE=3, freq_sel=19
3742 19:56:36.796062 sv_algorithm_assistance_LP4_1600
3743 19:56:36.799131 ============ PULL DRAM RESETB DOWN ============
3744 19:56:36.802957 ========== PULL DRAM RESETB DOWN end =========
3745 19:56:36.809355 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3746 19:56:36.812501 ===================================
3747 19:56:36.812919 LPDDR4 DRAM CONFIGURATION
3748 19:56:36.816260 ===================================
3749 19:56:36.819485 EX_ROW_EN[0] = 0x0
3750 19:56:36.819952 EX_ROW_EN[1] = 0x0
3751 19:56:36.822655 LP4Y_EN = 0x0
3752 19:56:36.823098 WORK_FSP = 0x0
3753 19:56:36.826537 WL = 0x2
3754 19:56:36.829870 RL = 0x2
3755 19:56:36.830396 BL = 0x2
3756 19:56:36.833201 RPST = 0x0
3757 19:56:36.833730 RD_PRE = 0x0
3758 19:56:36.835899 WR_PRE = 0x1
3759 19:56:36.836317 WR_PST = 0x0
3760 19:56:36.839240 DBI_WR = 0x0
3761 19:56:36.839708 DBI_RD = 0x0
3762 19:56:36.842809 OTF = 0x1
3763 19:56:36.845937 ===================================
3764 19:56:36.849405 ===================================
3765 19:56:36.849828 ANA top config
3766 19:56:36.852575 ===================================
3767 19:56:36.856194 DLL_ASYNC_EN = 0
3768 19:56:36.859284 ALL_SLAVE_EN = 1
3769 19:56:36.859733 NEW_RANK_MODE = 1
3770 19:56:36.862566 DLL_IDLE_MODE = 1
3771 19:56:36.865609 LP45_APHY_COMB_EN = 1
3772 19:56:36.869301 TX_ODT_DIS = 1
3773 19:56:36.869728 NEW_8X_MODE = 1
3774 19:56:36.872673 ===================================
3775 19:56:36.875995 ===================================
3776 19:56:36.879461 data_rate = 1200
3777 19:56:36.882874 CKR = 1
3778 19:56:36.885630 DQ_P2S_RATIO = 8
3779 19:56:36.889350 ===================================
3780 19:56:36.892302 CA_P2S_RATIO = 8
3781 19:56:36.895705 DQ_CA_OPEN = 0
3782 19:56:36.896300 DQ_SEMI_OPEN = 0
3783 19:56:36.899385 CA_SEMI_OPEN = 0
3784 19:56:36.902437 CA_FULL_RATE = 0
3785 19:56:36.906332 DQ_CKDIV4_EN = 1
3786 19:56:36.909735 CA_CKDIV4_EN = 1
3787 19:56:36.912695 CA_PREDIV_EN = 0
3788 19:56:36.913115 PH8_DLY = 0
3789 19:56:36.915971 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3790 19:56:36.919048 DQ_AAMCK_DIV = 4
3791 19:56:36.922925 CA_AAMCK_DIV = 4
3792 19:56:36.926167 CA_ADMCK_DIV = 4
3793 19:56:36.929369 DQ_TRACK_CA_EN = 0
3794 19:56:36.929943 CA_PICK = 600
3795 19:56:36.933047 CA_MCKIO = 600
3796 19:56:36.936250 MCKIO_SEMI = 0
3797 19:56:36.939362 PLL_FREQ = 2288
3798 19:56:36.942500 DQ_UI_PI_RATIO = 32
3799 19:56:36.946038 CA_UI_PI_RATIO = 0
3800 19:56:36.949178 ===================================
3801 19:56:36.952459 ===================================
3802 19:56:36.952891 memory_type:LPDDR4
3803 19:56:36.955863 GP_NUM : 10
3804 19:56:36.959110 SRAM_EN : 1
3805 19:56:36.959531 MD32_EN : 0
3806 19:56:36.962375 ===================================
3807 19:56:36.965834 [ANA_INIT] >>>>>>>>>>>>>>
3808 19:56:36.968966 <<<<<< [CONFIGURE PHASE]: ANA_TX
3809 19:56:36.972261 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3810 19:56:36.975536 ===================================
3811 19:56:36.979222 data_rate = 1200,PCW = 0X5800
3812 19:56:36.982187 ===================================
3813 19:56:36.985861 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3814 19:56:36.988717 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3815 19:56:36.995579 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3816 19:56:36.999236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3817 19:56:37.002126 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3818 19:56:37.009174 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3819 19:56:37.009598 [ANA_INIT] flow start
3820 19:56:37.012342 [ANA_INIT] PLL >>>>>>>>
3821 19:56:37.015871 [ANA_INIT] PLL <<<<<<<<
3822 19:56:37.016397 [ANA_INIT] MIDPI >>>>>>>>
3823 19:56:37.019090 [ANA_INIT] MIDPI <<<<<<<<
3824 19:56:37.022429 [ANA_INIT] DLL >>>>>>>>
3825 19:56:37.022952 [ANA_INIT] flow end
3826 19:56:37.025585 ============ LP4 DIFF to SE enter ============
3827 19:56:37.032359 ============ LP4 DIFF to SE exit ============
3828 19:56:37.032785 [ANA_INIT] <<<<<<<<<<<<<
3829 19:56:37.035891 [Flow] Enable top DCM control >>>>>
3830 19:56:37.038696 [Flow] Enable top DCM control <<<<<
3831 19:56:37.041811 Enable DLL master slave shuffle
3832 19:56:37.048987 ==============================================================
3833 19:56:37.049479 Gating Mode config
3834 19:56:37.055501 ==============================================================
3835 19:56:37.059023 Config description:
3836 19:56:37.069166 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3837 19:56:37.075790 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3838 19:56:37.079092 SELPH_MODE 0: By rank 1: By Phase
3839 19:56:37.085223 ==============================================================
3840 19:56:37.088770 GAT_TRACK_EN = 1
3841 19:56:37.089382 RX_GATING_MODE = 2
3842 19:56:37.091784 RX_GATING_TRACK_MODE = 2
3843 19:56:37.095391 SELPH_MODE = 1
3844 19:56:37.098996 PICG_EARLY_EN = 1
3845 19:56:37.102600 VALID_LAT_VALUE = 1
3846 19:56:37.109034 ==============================================================
3847 19:56:37.112247 Enter into Gating configuration >>>>
3848 19:56:37.115504 Exit from Gating configuration <<<<
3849 19:56:37.118785 Enter into DVFS_PRE_config >>>>>
3850 19:56:37.128333 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3851 19:56:37.132002 Exit from DVFS_PRE_config <<<<<
3852 19:56:37.135152 Enter into PICG configuration >>>>
3853 19:56:37.138326 Exit from PICG configuration <<<<
3854 19:56:37.142116 [RX_INPUT] configuration >>>>>
3855 19:56:37.145238 [RX_INPUT] configuration <<<<<
3856 19:56:37.148246 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3857 19:56:37.155216 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3858 19:56:37.161505 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 19:56:37.165273 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 19:56:37.171574 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3861 19:56:37.178696 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3862 19:56:37.181992 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3863 19:56:37.185314 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3864 19:56:37.191913 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3865 19:56:37.194947 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3866 19:56:37.198137 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3867 19:56:37.204831 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3868 19:56:37.208263 ===================================
3869 19:56:37.208699 LPDDR4 DRAM CONFIGURATION
3870 19:56:37.211793 ===================================
3871 19:56:37.214959 EX_ROW_EN[0] = 0x0
3872 19:56:37.217951 EX_ROW_EN[1] = 0x0
3873 19:56:37.218741 LP4Y_EN = 0x0
3874 19:56:37.221254 WORK_FSP = 0x0
3875 19:56:37.221990 WL = 0x2
3876 19:56:37.224943 RL = 0x2
3877 19:56:37.225583 BL = 0x2
3878 19:56:37.228479 RPST = 0x0
3879 19:56:37.229101 RD_PRE = 0x0
3880 19:56:37.231455 WR_PRE = 0x1
3881 19:56:37.232024 WR_PST = 0x0
3882 19:56:37.235045 DBI_WR = 0x0
3883 19:56:37.235469 DBI_RD = 0x0
3884 19:56:37.238425 OTF = 0x1
3885 19:56:37.241354 ===================================
3886 19:56:37.245058 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3887 19:56:37.248497 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3888 19:56:37.255073 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3889 19:56:37.258073 ===================================
3890 19:56:37.258501 LPDDR4 DRAM CONFIGURATION
3891 19:56:37.261311 ===================================
3892 19:56:37.264928 EX_ROW_EN[0] = 0x10
3893 19:56:37.265354 EX_ROW_EN[1] = 0x0
3894 19:56:37.268129 LP4Y_EN = 0x0
3895 19:56:37.268551 WORK_FSP = 0x0
3896 19:56:37.271427 WL = 0x2
3897 19:56:37.271895 RL = 0x2
3898 19:56:37.274598 BL = 0x2
3899 19:56:37.277969 RPST = 0x0
3900 19:56:37.278397 RD_PRE = 0x0
3901 19:56:37.281824 WR_PRE = 0x1
3902 19:56:37.282246 WR_PST = 0x0
3903 19:56:37.284778 DBI_WR = 0x0
3904 19:56:37.285194 DBI_RD = 0x0
3905 19:56:37.287908 OTF = 0x1
3906 19:56:37.291612 ===================================
3907 19:56:37.294551 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3908 19:56:37.300275 nWR fixed to 30
3909 19:56:37.303417 [ModeRegInit_LP4] CH0 RK0
3910 19:56:37.303887 [ModeRegInit_LP4] CH0 RK1
3911 19:56:37.307173 [ModeRegInit_LP4] CH1 RK0
3912 19:56:37.310344 [ModeRegInit_LP4] CH1 RK1
3913 19:56:37.310773 match AC timing 17
3914 19:56:37.316660 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3915 19:56:37.320123 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3916 19:56:37.323438 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3917 19:56:37.330216 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3918 19:56:37.333620 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3919 19:56:37.334050 ==
3920 19:56:37.336829 Dram Type= 6, Freq= 0, CH_0, rank 0
3921 19:56:37.340219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3922 19:56:37.340644 ==
3923 19:56:37.346512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3924 19:56:37.353467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3925 19:56:37.356879 [CA 0] Center 35 (5~66) winsize 62
3926 19:56:37.360111 [CA 1] Center 35 (5~66) winsize 62
3927 19:56:37.363100 [CA 2] Center 33 (3~64) winsize 62
3928 19:56:37.366708 [CA 3] Center 33 (2~64) winsize 63
3929 19:56:37.369798 [CA 4] Center 33 (2~64) winsize 63
3930 19:56:37.372987 [CA 5] Center 32 (2~63) winsize 62
3931 19:56:37.373171
3932 19:56:37.376224 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3933 19:56:37.376411
3934 19:56:37.380027 [CATrainingPosCal] consider 1 rank data
3935 19:56:37.383176 u2DelayCellTimex100 = 270/100 ps
3936 19:56:37.386319 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3937 19:56:37.389506 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3938 19:56:37.393241 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3939 19:56:37.396560 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3940 19:56:37.399374 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3941 19:56:37.402936 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3942 19:56:37.403018
3943 19:56:37.409868 CA PerBit enable=1, Macro0, CA PI delay=32
3944 19:56:37.409949
3945 19:56:37.413056 [CBTSetCACLKResult] CA Dly = 32
3946 19:56:37.413137 CS Dly: 4 (0~35)
3947 19:56:37.413201 ==
3948 19:56:37.416109 Dram Type= 6, Freq= 0, CH_0, rank 1
3949 19:56:37.419899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3950 19:56:37.419980 ==
3951 19:56:37.426179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3952 19:56:37.433098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3953 19:56:37.436217 [CA 0] Center 35 (5~66) winsize 62
3954 19:56:37.439526 [CA 1] Center 35 (5~66) winsize 62
3955 19:56:37.442694 [CA 2] Center 33 (3~64) winsize 62
3956 19:56:37.445874 [CA 3] Center 33 (2~64) winsize 63
3957 19:56:37.449558 [CA 4] Center 32 (2~63) winsize 62
3958 19:56:37.452664 [CA 5] Center 32 (1~63) winsize 63
3959 19:56:37.452745
3960 19:56:37.456301 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3961 19:56:37.456385
3962 19:56:37.459295 [CATrainingPosCal] consider 2 rank data
3963 19:56:37.462404 u2DelayCellTimex100 = 270/100 ps
3964 19:56:37.466037 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3965 19:56:37.469443 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3966 19:56:37.472427 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3967 19:56:37.475827 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3968 19:56:37.479156 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3969 19:56:37.485686 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3970 19:56:37.485767
3971 19:56:37.489035 CA PerBit enable=1, Macro0, CA PI delay=32
3972 19:56:37.489117
3973 19:56:37.492825 [CBTSetCACLKResult] CA Dly = 32
3974 19:56:37.492907 CS Dly: 4 (0~36)
3975 19:56:37.492973
3976 19:56:37.495759 ----->DramcWriteLeveling(PI) begin...
3977 19:56:37.495841 ==
3978 19:56:37.499126 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 19:56:37.505798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 19:56:37.505880 ==
3981 19:56:37.509376 Write leveling (Byte 0): 33 => 33
3982 19:56:37.509457 Write leveling (Byte 1): 30 => 30
3983 19:56:37.512571 DramcWriteLeveling(PI) end<-----
3984 19:56:37.512651
3985 19:56:37.512716 ==
3986 19:56:37.515801 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 19:56:37.522610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 19:56:37.522691 ==
3989 19:56:37.525783 [Gating] SW mode calibration
3990 19:56:37.532063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3991 19:56:37.535810 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3992 19:56:37.542174 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 19:56:37.545394 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 19:56:37.548659 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 19:56:37.555552 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
3996 19:56:37.558838 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
3997 19:56:37.561833 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 19:56:37.569053 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 19:56:37.572260 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 19:56:37.575769 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 19:56:37.581793 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 19:56:37.585562 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 19:56:37.588708 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4004 19:56:37.595248 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4005 19:56:37.598374 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 19:56:37.601875 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 19:56:37.605030 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 19:56:37.611698 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 19:56:37.615147 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 19:56:37.618667 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 19:56:37.624974 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4012 19:56:37.628476 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4013 19:56:37.631494 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 19:56:37.638704 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 19:56:37.641777 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 19:56:37.644980 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 19:56:37.651927 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 19:56:37.655264 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 19:56:37.658494 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 19:56:37.664769 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 19:56:37.668380 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 19:56:37.671879 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 19:56:37.678349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 19:56:37.681721 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 19:56:37.685257 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 19:56:37.691823 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 19:56:37.694862 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4028 19:56:37.698179 Total UI for P1: 0, mck2ui 16
4029 19:56:37.701431 best dqsien dly found for B0: ( 0, 13, 10)
4030 19:56:37.705192 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 19:56:37.708691 Total UI for P1: 0, mck2ui 16
4032 19:56:37.711604 best dqsien dly found for B1: ( 0, 13, 14)
4033 19:56:37.715161 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4034 19:56:37.718566 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4035 19:56:37.718650
4036 19:56:37.721606 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4037 19:56:37.728233 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4038 19:56:37.728318 [Gating] SW calibration Done
4039 19:56:37.728404 ==
4040 19:56:37.731758 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 19:56:37.738531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 19:56:37.738617 ==
4043 19:56:37.738703 RX Vref Scan: 0
4044 19:56:37.738783
4045 19:56:37.741317 RX Vref 0 -> 0, step: 1
4046 19:56:37.741421
4047 19:56:37.744885 RX Delay -230 -> 252, step: 16
4048 19:56:37.748140 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4049 19:56:37.751430 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4050 19:56:37.758135 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4051 19:56:37.761733 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4052 19:56:37.764889 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4053 19:56:37.768127 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4054 19:56:37.771587 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4055 19:56:37.778117 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4056 19:56:37.781213 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4057 19:56:37.784364 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4058 19:56:37.788169 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4059 19:56:37.794629 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4060 19:56:37.798099 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4061 19:56:37.801303 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4062 19:56:37.804400 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4063 19:56:37.811180 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4064 19:56:37.811266 ==
4065 19:56:37.814292 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 19:56:37.817894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 19:56:37.817979 ==
4068 19:56:37.818066 DQS Delay:
4069 19:56:37.820939 DQS0 = 0, DQS1 = 0
4070 19:56:37.821023 DQM Delay:
4071 19:56:37.824442 DQM0 = 49, DQM1 = 45
4072 19:56:37.824526 DQ Delay:
4073 19:56:37.827909 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4074 19:56:37.831117 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4075 19:56:37.834307 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4076 19:56:37.838094 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4077 19:56:37.838177
4078 19:56:37.838263
4079 19:56:37.838343 ==
4080 19:56:37.841136 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 19:56:37.844685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 19:56:37.844769 ==
4083 19:56:37.844855
4084 19:56:37.844936
4085 19:56:37.847927 TX Vref Scan disable
4086 19:56:37.851097 == TX Byte 0 ==
4087 19:56:37.854402 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4088 19:56:37.857758 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4089 19:56:37.861259 == TX Byte 1 ==
4090 19:56:37.864462 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4091 19:56:37.867556 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4092 19:56:37.867701 ==
4093 19:56:37.871312 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 19:56:37.877642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 19:56:37.877729 ==
4096 19:56:37.877794
4097 19:56:37.877853
4098 19:56:37.877911 TX Vref Scan disable
4099 19:56:37.882403 == TX Byte 0 ==
4100 19:56:37.885845 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4101 19:56:37.889108 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4102 19:56:37.892188 == TX Byte 1 ==
4103 19:56:37.895472 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4104 19:56:37.898683 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4105 19:56:37.902582
4106 19:56:37.902663 [DATLAT]
4107 19:56:37.902728 Freq=600, CH0 RK0
4108 19:56:37.902788
4109 19:56:37.905542 DATLAT Default: 0x9
4110 19:56:37.905624 0, 0xFFFF, sum = 0
4111 19:56:37.909111 1, 0xFFFF, sum = 0
4112 19:56:37.909196 2, 0xFFFF, sum = 0
4113 19:56:37.912599 3, 0xFFFF, sum = 0
4114 19:56:37.912682 4, 0xFFFF, sum = 0
4115 19:56:37.915549 5, 0xFFFF, sum = 0
4116 19:56:37.915696 6, 0xFFFF, sum = 0
4117 19:56:37.919319 7, 0xFFFF, sum = 0
4118 19:56:37.919402 8, 0x0, sum = 1
4119 19:56:37.922538 9, 0x0, sum = 2
4120 19:56:37.922621 10, 0x0, sum = 3
4121 19:56:37.925703 11, 0x0, sum = 4
4122 19:56:37.925795 best_step = 9
4123 19:56:37.925865
4124 19:56:37.925926 ==
4125 19:56:37.928740 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 19:56:37.935723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 19:56:37.935806 ==
4128 19:56:37.935871 RX Vref Scan: 1
4129 19:56:37.935931
4130 19:56:37.938886 RX Vref 0 -> 0, step: 1
4131 19:56:37.938955
4132 19:56:37.942122 RX Delay -163 -> 252, step: 8
4133 19:56:37.942196
4134 19:56:37.945389 Set Vref, RX VrefLevel [Byte0]: 56
4135 19:56:37.948597 [Byte1]: 48
4136 19:56:37.948679
4137 19:56:37.951753 Final RX Vref Byte 0 = 56 to rank0
4138 19:56:37.955386 Final RX Vref Byte 1 = 48 to rank0
4139 19:56:37.958822 Final RX Vref Byte 0 = 56 to rank1
4140 19:56:37.961784 Final RX Vref Byte 1 = 48 to rank1==
4141 19:56:37.965260 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 19:56:37.968442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 19:56:37.968525 ==
4144 19:56:37.971783 DQS Delay:
4145 19:56:37.971865 DQS0 = 0, DQS1 = 0
4146 19:56:37.971931 DQM Delay:
4147 19:56:37.975255 DQM0 = 52, DQM1 = 46
4148 19:56:37.975337 DQ Delay:
4149 19:56:37.978759 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =52
4150 19:56:37.982025 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4151 19:56:37.985094 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4152 19:56:37.988548 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4153 19:56:37.988630
4154 19:56:37.988694
4155 19:56:37.998233 [DQSOSCAuto] RK0, (LSB)MR18= 0x7366, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4156 19:56:38.001595 CH0 RK0: MR19=808, MR18=7366
4157 19:56:38.005063 CH0_RK0: MR19=0x808, MR18=0x7366, DQSOSC=388, MR23=63, INC=174, DEC=116
4158 19:56:38.005536
4159 19:56:38.012084 ----->DramcWriteLeveling(PI) begin...
4160 19:56:38.012513 ==
4161 19:56:38.015137 Dram Type= 6, Freq= 0, CH_0, rank 1
4162 19:56:38.018934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 19:56:38.019363 ==
4164 19:56:38.022123 Write leveling (Byte 0): 35 => 35
4165 19:56:38.025239 Write leveling (Byte 1): 31 => 31
4166 19:56:38.028944 DramcWriteLeveling(PI) end<-----
4167 19:56:38.029369
4168 19:56:38.029704 ==
4169 19:56:38.031577 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 19:56:38.035040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 19:56:38.035463 ==
4172 19:56:38.038308 [Gating] SW mode calibration
4173 19:56:38.045135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4174 19:56:38.051799 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4175 19:56:38.055096 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 19:56:38.058750 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 19:56:38.061955 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 19:56:38.068577 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4179 19:56:38.071634 0 9 16 | B1->B0 | 2c2c 2c2c | 0 0 | (0 0) (0 0)
4180 19:56:38.075361 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 19:56:38.081630 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 19:56:38.085009 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 19:56:38.088516 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 19:56:38.094902 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 19:56:38.097980 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 19:56:38.101558 0 10 12 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
4187 19:56:38.108004 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 19:56:38.111611 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 19:56:38.114755 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 19:56:38.121546 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 19:56:38.124683 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 19:56:38.127744 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 19:56:38.134663 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 19:56:38.137857 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4195 19:56:38.140994 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 19:56:38.147629 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 19:56:38.151406 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 19:56:38.154407 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 19:56:38.161519 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 19:56:38.164679 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 19:56:38.167814 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 19:56:38.174775 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 19:56:38.177725 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 19:56:38.181393 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 19:56:38.187949 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 19:56:38.190923 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 19:56:38.194515 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 19:56:38.197940 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 19:56:38.204409 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 19:56:38.207520 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4211 19:56:38.210880 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4212 19:56:38.214603 Total UI for P1: 0, mck2ui 16
4213 19:56:38.217801 best dqsien dly found for B0: ( 0, 13, 12)
4214 19:56:38.224522 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 19:56:38.227863 Total UI for P1: 0, mck2ui 16
4216 19:56:38.230955 best dqsien dly found for B1: ( 0, 13, 16)
4217 19:56:38.234022 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4218 19:56:38.237857 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4219 19:56:38.237940
4220 19:56:38.241049 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4221 19:56:38.244283 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4222 19:56:38.247194 [Gating] SW calibration Done
4223 19:56:38.247276 ==
4224 19:56:38.251080 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 19:56:38.254211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 19:56:38.254293 ==
4227 19:56:38.257368 RX Vref Scan: 0
4228 19:56:38.257451
4229 19:56:38.260487 RX Vref 0 -> 0, step: 1
4230 19:56:38.260570
4231 19:56:38.260635 RX Delay -230 -> 252, step: 16
4232 19:56:38.267416 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4233 19:56:38.271034 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4234 19:56:38.274254 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4235 19:56:38.277482 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4236 19:56:38.284326 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4237 19:56:38.287397 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4238 19:56:38.290887 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4239 19:56:38.294246 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4240 19:56:38.297537 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4241 19:56:38.304120 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4242 19:56:38.307383 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4243 19:56:38.310709 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4244 19:56:38.314210 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4245 19:56:38.320916 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4246 19:56:38.324153 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4247 19:56:38.327714 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4248 19:56:38.327815 ==
4249 19:56:38.330542 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 19:56:38.334274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 19:56:38.334357 ==
4252 19:56:38.337446 DQS Delay:
4253 19:56:38.337529 DQS0 = 0, DQS1 = 0
4254 19:56:38.340569 DQM Delay:
4255 19:56:38.340651 DQM0 = 50, DQM1 = 42
4256 19:56:38.340716 DQ Delay:
4257 19:56:38.344439 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =41
4258 19:56:38.347533 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4259 19:56:38.350565 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =33
4260 19:56:38.354280 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4261 19:56:38.354362
4262 19:56:38.354427
4263 19:56:38.357381 ==
4264 19:56:38.360612 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 19:56:38.364368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 19:56:38.364450 ==
4267 19:56:38.364515
4268 19:56:38.364575
4269 19:56:38.367594 TX Vref Scan disable
4270 19:56:38.367713 == TX Byte 0 ==
4271 19:56:38.373731 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4272 19:56:38.377520 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4273 19:56:38.377603 == TX Byte 1 ==
4274 19:56:38.383962 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4275 19:56:38.387164 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4276 19:56:38.387246 ==
4277 19:56:38.390361 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 19:56:38.393551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 19:56:38.393633 ==
4280 19:56:38.393698
4281 19:56:38.393759
4282 19:56:38.397366 TX Vref Scan disable
4283 19:56:38.400410 == TX Byte 0 ==
4284 19:56:38.403901 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4285 19:56:38.407279 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4286 19:56:38.410190 == TX Byte 1 ==
4287 19:56:38.413528 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4288 19:56:38.417505 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4289 19:56:38.417587
4290 19:56:38.420362 [DATLAT]
4291 19:56:38.420444 Freq=600, CH0 RK1
4292 19:56:38.420510
4293 19:56:38.423965 DATLAT Default: 0x9
4294 19:56:38.424047 0, 0xFFFF, sum = 0
4295 19:56:38.427214 1, 0xFFFF, sum = 0
4296 19:56:38.427297 2, 0xFFFF, sum = 0
4297 19:56:38.430358 3, 0xFFFF, sum = 0
4298 19:56:38.430443 4, 0xFFFF, sum = 0
4299 19:56:38.433575 5, 0xFFFF, sum = 0
4300 19:56:38.433688 6, 0xFFFF, sum = 0
4301 19:56:38.436965 7, 0xFFFF, sum = 0
4302 19:56:38.437049 8, 0x0, sum = 1
4303 19:56:38.440520 9, 0x0, sum = 2
4304 19:56:38.440603 10, 0x0, sum = 3
4305 19:56:38.443537 11, 0x0, sum = 4
4306 19:56:38.443655 best_step = 9
4307 19:56:38.443731
4308 19:56:38.443792 ==
4309 19:56:38.447084 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 19:56:38.450287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 19:56:38.453774 ==
4312 19:56:38.453856 RX Vref Scan: 0
4313 19:56:38.453920
4314 19:56:38.456832 RX Vref 0 -> 0, step: 1
4315 19:56:38.456914
4316 19:56:38.460038 RX Delay -179 -> 252, step: 8
4317 19:56:38.463858 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4318 19:56:38.467055 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4319 19:56:38.473463 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4320 19:56:38.477293 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4321 19:56:38.480442 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4322 19:56:38.483514 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4323 19:56:38.487041 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4324 19:56:38.493759 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4325 19:56:38.496890 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4326 19:56:38.500096 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4327 19:56:38.503229 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4328 19:56:38.507121 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4329 19:56:38.513650 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4330 19:56:38.516699 iDelay=205, Bit 13, Center 56 (-83 ~ 196) 280
4331 19:56:38.519921 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4332 19:56:38.523494 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4333 19:56:38.523602 ==
4334 19:56:38.526647 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 19:56:38.533186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 19:56:38.533268 ==
4337 19:56:38.533332 DQS Delay:
4338 19:56:38.536623 DQS0 = 0, DQS1 = 0
4339 19:56:38.536704 DQM Delay:
4340 19:56:38.536768 DQM0 = 54, DQM1 = 46
4341 19:56:38.540252 DQ Delay:
4342 19:56:38.543173 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4343 19:56:38.546742 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4344 19:56:38.550195 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4345 19:56:38.553176 DQ12 =48, DQ13 =56, DQ14 =56, DQ15 =52
4346 19:56:38.553257
4347 19:56:38.553321
4348 19:56:38.559594 [DQSOSCAuto] RK1, (LSB)MR18= 0x6525, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4349 19:56:38.563273 CH0 RK1: MR19=808, MR18=6525
4350 19:56:38.569869 CH0_RK1: MR19=0x808, MR18=0x6525, DQSOSC=390, MR23=63, INC=172, DEC=114
4351 19:56:38.573353 [RxdqsGatingPostProcess] freq 600
4352 19:56:38.576599 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4353 19:56:38.579700 Pre-setting of DQS Precalculation
4354 19:56:38.586595 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4355 19:56:38.586678 ==
4356 19:56:38.589753 Dram Type= 6, Freq= 0, CH_1, rank 0
4357 19:56:38.593421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 19:56:38.593507 ==
4359 19:56:38.599954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4360 19:56:38.603230 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4361 19:56:38.607602 [CA 0] Center 35 (5~66) winsize 62
4362 19:56:38.610785 [CA 1] Center 35 (5~66) winsize 62
4363 19:56:38.614570 [CA 2] Center 34 (4~65) winsize 62
4364 19:56:38.617605 [CA 3] Center 34 (3~65) winsize 63
4365 19:56:38.621056 [CA 4] Center 34 (4~65) winsize 62
4366 19:56:38.624112 [CA 5] Center 33 (3~64) winsize 62
4367 19:56:38.624195
4368 19:56:38.627868 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4369 19:56:38.627962
4370 19:56:38.630894 [CATrainingPosCal] consider 1 rank data
4371 19:56:38.634002 u2DelayCellTimex100 = 270/100 ps
4372 19:56:38.637550 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4373 19:56:38.644064 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4374 19:56:38.647469 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 19:56:38.650807 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4376 19:56:38.654252 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 19:56:38.657400 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4378 19:56:38.657482
4379 19:56:38.660627 CA PerBit enable=1, Macro0, CA PI delay=33
4380 19:56:38.660710
4381 19:56:38.663587 [CBTSetCACLKResult] CA Dly = 33
4382 19:56:38.667268 CS Dly: 6 (0~37)
4383 19:56:38.667350 ==
4384 19:56:38.670279 Dram Type= 6, Freq= 0, CH_1, rank 1
4385 19:56:38.673662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 19:56:38.673744 ==
4387 19:56:38.680429 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4388 19:56:38.683614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4389 19:56:38.687690 [CA 0] Center 36 (6~67) winsize 62
4390 19:56:38.691340 [CA 1] Center 36 (6~67) winsize 62
4391 19:56:38.694586 [CA 2] Center 35 (5~66) winsize 62
4392 19:56:38.697626 [CA 3] Center 35 (4~66) winsize 63
4393 19:56:38.701091 [CA 4] Center 35 (4~66) winsize 63
4394 19:56:38.704547 [CA 5] Center 34 (4~65) winsize 62
4395 19:56:38.704630
4396 19:56:38.707633 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4397 19:56:38.707739
4398 19:56:38.711417 [CATrainingPosCal] consider 2 rank data
4399 19:56:38.714605 u2DelayCellTimex100 = 270/100 ps
4400 19:56:38.717780 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4401 19:56:38.720938 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4402 19:56:38.727805 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4403 19:56:38.731077 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4404 19:56:38.734591 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4405 19:56:38.737687 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4406 19:56:38.737769
4407 19:56:38.740820 CA PerBit enable=1, Macro0, CA PI delay=34
4408 19:56:38.740903
4409 19:56:38.744464 [CBTSetCACLKResult] CA Dly = 34
4410 19:56:38.744547 CS Dly: 6 (0~38)
4411 19:56:38.744612
4412 19:56:38.747531 ----->DramcWriteLeveling(PI) begin...
4413 19:56:38.751267 ==
4414 19:56:38.754265 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 19:56:38.757341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 19:56:38.757425 ==
4417 19:56:38.760837 Write leveling (Byte 0): 29 => 29
4418 19:56:38.764199 Write leveling (Byte 1): 30 => 30
4419 19:56:38.767536 DramcWriteLeveling(PI) end<-----
4420 19:56:38.767618
4421 19:56:38.767725 ==
4422 19:56:38.771202 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 19:56:38.774398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 19:56:38.774481 ==
4425 19:56:38.777547 [Gating] SW mode calibration
4426 19:56:38.784396 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4427 19:56:38.790964 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4428 19:56:38.794072 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4429 19:56:38.797455 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4430 19:56:38.803737 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 19:56:38.807363 0 9 12 | B1->B0 | 3030 2c2c | 1 0 | (1 0) (0 0)
4432 19:56:38.810820 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 19:56:38.813709 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 19:56:38.820668 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 19:56:38.824433 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 19:56:38.827571 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 19:56:38.834374 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 19:56:38.837381 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4439 19:56:38.840716 0 10 12 | B1->B0 | 3737 3535 | 0 0 | (0 0) (0 0)
4440 19:56:38.847544 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 19:56:38.850518 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 19:56:38.854304 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 19:56:38.860517 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 19:56:38.864154 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 19:56:38.867276 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 19:56:38.873647 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 19:56:38.877079 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4448 19:56:38.880456 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4449 19:56:38.887378 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 19:56:38.890485 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 19:56:38.893656 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 19:56:38.900642 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 19:56:38.904078 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 19:56:38.906918 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 19:56:38.913731 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 19:56:38.917013 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 19:56:38.920311 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 19:56:38.927306 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 19:56:38.930508 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 19:56:38.933562 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 19:56:38.936747 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 19:56:38.943650 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4463 19:56:38.946966 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4464 19:56:38.950509 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 19:56:38.953660 Total UI for P1: 0, mck2ui 16
4466 19:56:38.956658 best dqsien dly found for B0: ( 0, 13, 10)
4467 19:56:38.960320 Total UI for P1: 0, mck2ui 16
4468 19:56:38.963501 best dqsien dly found for B1: ( 0, 13, 12)
4469 19:56:38.967098 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4470 19:56:38.970281 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4471 19:56:38.973534
4472 19:56:38.976674 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4473 19:56:38.980228 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4474 19:56:38.983733 [Gating] SW calibration Done
4475 19:56:38.983816 ==
4476 19:56:38.986720 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 19:56:38.990420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 19:56:38.990503 ==
4479 19:56:38.990569 RX Vref Scan: 0
4480 19:56:38.990631
4481 19:56:38.993529 RX Vref 0 -> 0, step: 1
4482 19:56:38.993611
4483 19:56:38.996746 RX Delay -230 -> 252, step: 16
4484 19:56:39.000542 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4485 19:56:39.003548 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4486 19:56:39.010489 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4487 19:56:39.013446 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4488 19:56:39.017186 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4489 19:56:39.020179 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4490 19:56:39.027235 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4491 19:56:39.030075 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4492 19:56:39.033743 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4493 19:56:39.037210 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4494 19:56:39.043614 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4495 19:56:39.047021 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4496 19:56:39.050015 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4497 19:56:39.053620 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4498 19:56:39.056680 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4499 19:56:39.063219 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4500 19:56:39.063344 ==
4501 19:56:39.066830 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 19:56:39.069893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 19:56:39.070012 ==
4504 19:56:39.070104 DQS Delay:
4505 19:56:39.073602 DQS0 = 0, DQS1 = 0
4506 19:56:39.073714 DQM Delay:
4507 19:56:39.076710 DQM0 = 48, DQM1 = 46
4508 19:56:39.076784 DQ Delay:
4509 19:56:39.079844 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4510 19:56:39.083526 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4511 19:56:39.086577 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4512 19:56:39.090360 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4513 19:56:39.090459
4514 19:56:39.090554
4515 19:56:39.090643 ==
4516 19:56:39.093215 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 19:56:39.096821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 19:56:39.100069 ==
4519 19:56:39.100171
4520 19:56:39.100264
4521 19:56:39.100352 TX Vref Scan disable
4522 19:56:39.103339 == TX Byte 0 ==
4523 19:56:39.106479 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4524 19:56:39.109714 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4525 19:56:39.113424 == TX Byte 1 ==
4526 19:56:39.116311 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4527 19:56:39.119944 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4528 19:56:39.123104 ==
4529 19:56:39.126094 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 19:56:39.129900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 19:56:39.130006 ==
4532 19:56:39.130104
4533 19:56:39.130196
4534 19:56:39.133123 TX Vref Scan disable
4535 19:56:39.133205 == TX Byte 0 ==
4536 19:56:39.140036 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4537 19:56:39.142975 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4538 19:56:39.143071 == TX Byte 1 ==
4539 19:56:39.149659 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4540 19:56:39.153504 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4541 19:56:39.153615
4542 19:56:39.153703 [DATLAT]
4543 19:56:39.156509 Freq=600, CH1 RK0
4544 19:56:39.156632
4545 19:56:39.156730 DATLAT Default: 0x9
4546 19:56:39.159537 0, 0xFFFF, sum = 0
4547 19:56:39.159687 1, 0xFFFF, sum = 0
4548 19:56:39.163357 2, 0xFFFF, sum = 0
4549 19:56:39.163496 3, 0xFFFF, sum = 0
4550 19:56:39.166290 4, 0xFFFF, sum = 0
4551 19:56:39.169746 5, 0xFFFF, sum = 0
4552 19:56:39.169924 6, 0xFFFF, sum = 0
4553 19:56:39.173337 7, 0xFFFF, sum = 0
4554 19:56:39.173515 8, 0x0, sum = 1
4555 19:56:39.173657 9, 0x0, sum = 2
4556 19:56:39.176544 10, 0x0, sum = 3
4557 19:56:39.176975 11, 0x0, sum = 4
4558 19:56:39.180153 best_step = 9
4559 19:56:39.180579
4560 19:56:39.180920 ==
4561 19:56:39.183275 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 19:56:39.186433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 19:56:39.186861 ==
4564 19:56:39.190200 RX Vref Scan: 1
4565 19:56:39.190626
4566 19:56:39.190966 RX Vref 0 -> 0, step: 1
4567 19:56:39.191285
4568 19:56:39.193194 RX Delay -163 -> 252, step: 8
4569 19:56:39.193727
4570 19:56:39.196867 Set Vref, RX VrefLevel [Byte0]: 56
4571 19:56:39.199856 [Byte1]: 48
4572 19:56:39.204149
4573 19:56:39.204572 Final RX Vref Byte 0 = 56 to rank0
4574 19:56:39.207191 Final RX Vref Byte 1 = 48 to rank0
4575 19:56:39.210293 Final RX Vref Byte 0 = 56 to rank1
4576 19:56:39.213537 Final RX Vref Byte 1 = 48 to rank1==
4577 19:56:39.217065 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 19:56:39.223497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 19:56:39.223956 ==
4580 19:56:39.224302 DQS Delay:
4581 19:56:39.224622 DQS0 = 0, DQS1 = 0
4582 19:56:39.227086 DQM Delay:
4583 19:56:39.227511 DQM0 = 49, DQM1 = 45
4584 19:56:39.230491 DQ Delay:
4585 19:56:39.233880 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4586 19:56:39.236962 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4587 19:56:39.240158 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4588 19:56:39.243951 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4589 19:56:39.244437
4590 19:56:39.244806
4591 19:56:39.250279 [DQSOSCAuto] RK0, (LSB)MR18= 0x496e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4592 19:56:39.253801 CH1 RK0: MR19=808, MR18=496E
4593 19:56:39.260216 CH1_RK0: MR19=0x808, MR18=0x496E, DQSOSC=389, MR23=63, INC=173, DEC=115
4594 19:56:39.260776
4595 19:56:39.263608 ----->DramcWriteLeveling(PI) begin...
4596 19:56:39.264173 ==
4597 19:56:39.267055 Dram Type= 6, Freq= 0, CH_1, rank 1
4598 19:56:39.270263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 19:56:39.270727 ==
4600 19:56:39.273295 Write leveling (Byte 0): 31 => 31
4601 19:56:39.276873 Write leveling (Byte 1): 30 => 30
4602 19:56:39.280399 DramcWriteLeveling(PI) end<-----
4603 19:56:39.280823
4604 19:56:39.281160 ==
4605 19:56:39.283265 Dram Type= 6, Freq= 0, CH_1, rank 1
4606 19:56:39.286663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 19:56:39.287087 ==
4608 19:56:39.289780 [Gating] SW mode calibration
4609 19:56:39.296692 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4610 19:56:39.303140 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4611 19:56:39.306851 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 19:56:39.313155 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4613 19:56:39.316850 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4614 19:56:39.320096 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (0 0)
4615 19:56:39.323141 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 19:56:39.329852 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 19:56:39.333354 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 19:56:39.336841 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 19:56:39.343131 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 19:56:39.346934 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 19:56:39.350041 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 19:56:39.356730 0 10 12 | B1->B0 | 3837 3535 | 1 1 | (0 0) (0 0)
4623 19:56:39.359835 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 19:56:39.363391 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 19:56:39.370079 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 19:56:39.373033 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 19:56:39.376392 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 19:56:39.383138 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 19:56:39.386789 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 19:56:39.389892 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 19:56:39.396690 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 19:56:39.399553 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 19:56:39.402962 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 19:56:39.409867 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 19:56:39.413005 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 19:56:39.416636 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 19:56:39.422937 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 19:56:39.426547 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 19:56:39.429609 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 19:56:39.436540 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 19:56:39.439538 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 19:56:39.443132 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 19:56:39.449791 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 19:56:39.452776 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 19:56:39.456004 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4646 19:56:39.459836 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 19:56:39.462864 Total UI for P1: 0, mck2ui 16
4648 19:56:39.466096 best dqsien dly found for B0: ( 0, 13, 10)
4649 19:56:39.469736 Total UI for P1: 0, mck2ui 16
4650 19:56:39.472787 best dqsien dly found for B1: ( 0, 13, 8)
4651 19:56:39.476328 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4652 19:56:39.482723 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4653 19:56:39.483152
4654 19:56:39.486258 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4655 19:56:39.489822 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4656 19:56:39.493225 [Gating] SW calibration Done
4657 19:56:39.493646 ==
4658 19:56:39.496190 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 19:56:39.500076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 19:56:39.500499 ==
4661 19:56:39.500832 RX Vref Scan: 0
4662 19:56:39.501144
4663 19:56:39.502843 RX Vref 0 -> 0, step: 1
4664 19:56:39.503265
4665 19:56:39.506428 RX Delay -230 -> 252, step: 16
4666 19:56:39.509668 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4667 19:56:39.513026 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4668 19:56:39.519551 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4669 19:56:39.523111 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4670 19:56:39.526337 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4671 19:56:39.529559 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4672 19:56:39.532973 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4673 19:56:39.539700 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4674 19:56:39.542921 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4675 19:56:39.546105 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4676 19:56:39.549804 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4677 19:56:39.556219 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4678 19:56:39.559351 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4679 19:56:39.562760 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4680 19:56:39.566605 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4681 19:56:39.572782 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4682 19:56:39.573205 ==
4683 19:56:39.576306 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 19:56:39.579286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 19:56:39.579752 ==
4686 19:56:39.580097 DQS Delay:
4687 19:56:39.582851 DQS0 = 0, DQS1 = 0
4688 19:56:39.583272 DQM Delay:
4689 19:56:39.585882 DQM0 = 49, DQM1 = 45
4690 19:56:39.586305 DQ Delay:
4691 19:56:39.589637 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4692 19:56:39.592734 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4693 19:56:39.596422 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4694 19:56:39.599720 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4695 19:56:39.600144
4696 19:56:39.600478
4697 19:56:39.600786 ==
4698 19:56:39.602930 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 19:56:39.606215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 19:56:39.606643 ==
4701 19:56:39.609180
4702 19:56:39.609599
4703 19:56:39.609935 TX Vref Scan disable
4704 19:56:39.612705 == TX Byte 0 ==
4705 19:56:39.616224 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4706 19:56:39.619617 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4707 19:56:39.622821 == TX Byte 1 ==
4708 19:56:39.626210 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4709 19:56:39.629217 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4710 19:56:39.629683 ==
4711 19:56:39.632856 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 19:56:39.639537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 19:56:39.639831 ==
4714 19:56:39.640013
4715 19:56:39.640183
4716 19:56:39.640357 TX Vref Scan disable
4717 19:56:39.643837 == TX Byte 0 ==
4718 19:56:39.646946 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4719 19:56:39.653308 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4720 19:56:39.653463 == TX Byte 1 ==
4721 19:56:39.657143 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4722 19:56:39.663132 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4723 19:56:39.663334
4724 19:56:39.663486 [DATLAT]
4725 19:56:39.663619 Freq=600, CH1 RK1
4726 19:56:39.663778
4727 19:56:39.666588 DATLAT Default: 0x9
4728 19:56:39.666714 0, 0xFFFF, sum = 0
4729 19:56:39.669917 1, 0xFFFF, sum = 0
4730 19:56:39.673506 2, 0xFFFF, sum = 0
4731 19:56:39.673594 3, 0xFFFF, sum = 0
4732 19:56:39.676582 4, 0xFFFF, sum = 0
4733 19:56:39.676656 5, 0xFFFF, sum = 0
4734 19:56:39.680206 6, 0xFFFF, sum = 0
4735 19:56:39.680284 7, 0xFFFF, sum = 0
4736 19:56:39.683292 8, 0x0, sum = 1
4737 19:56:39.683362 9, 0x0, sum = 2
4738 19:56:39.683425 10, 0x0, sum = 3
4739 19:56:39.686879 11, 0x0, sum = 4
4740 19:56:39.686949 best_step = 9
4741 19:56:39.687007
4742 19:56:39.687064 ==
4743 19:56:39.689885 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 19:56:39.696878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 19:56:39.696966 ==
4746 19:56:39.697031 RX Vref Scan: 0
4747 19:56:39.697092
4748 19:56:39.700120 RX Vref 0 -> 0, step: 1
4749 19:56:39.700210
4750 19:56:39.703310 RX Delay -163 -> 252, step: 8
4751 19:56:39.706388 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4752 19:56:39.713598 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4753 19:56:39.716352 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4754 19:56:39.719853 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4755 19:56:39.723124 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4756 19:56:39.726377 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4757 19:56:39.732924 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4758 19:56:39.736435 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4759 19:56:39.739844 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4760 19:56:39.742968 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4761 19:56:39.746652 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4762 19:56:39.752955 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4763 19:56:39.756231 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4764 19:56:39.759919 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4765 19:56:39.763155 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4766 19:56:39.769793 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4767 19:56:39.769876 ==
4768 19:56:39.772896 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 19:56:39.776315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 19:56:39.776398 ==
4771 19:56:39.776463 DQS Delay:
4772 19:56:39.779616 DQS0 = 0, DQS1 = 0
4773 19:56:39.779739 DQM Delay:
4774 19:56:39.783088 DQM0 = 48, DQM1 = 46
4775 19:56:39.783169 DQ Delay:
4776 19:56:39.786206 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4777 19:56:39.789792 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4778 19:56:39.792650 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4779 19:56:39.796331 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4780 19:56:39.796413
4781 19:56:39.796478
4782 19:56:39.802750 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f26, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4783 19:56:39.805936 CH1 RK1: MR19=808, MR18=6F26
4784 19:56:39.812790 CH1_RK1: MR19=0x808, MR18=0x6F26, DQSOSC=389, MR23=63, INC=173, DEC=115
4785 19:56:39.815892 [RxdqsGatingPostProcess] freq 600
4786 19:56:39.822760 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4787 19:56:39.825871 Pre-setting of DQS Precalculation
4788 19:56:39.829539 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4789 19:56:39.836181 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4790 19:56:39.842663 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4791 19:56:39.842809
4792 19:56:39.842937
4793 19:56:39.845702 [Calibration Summary] 1200 Mbps
4794 19:56:39.849154 CH 0, Rank 0
4795 19:56:39.849306 SW Impedance : PASS
4796 19:56:39.852408 DUTY Scan : NO K
4797 19:56:39.855901 ZQ Calibration : PASS
4798 19:56:39.856121 Jitter Meter : NO K
4799 19:56:39.859085 CBT Training : PASS
4800 19:56:39.862424 Write leveling : PASS
4801 19:56:39.862724 RX DQS gating : PASS
4802 19:56:39.865580 RX DQ/DQS(RDDQC) : PASS
4803 19:56:39.869489 TX DQ/DQS : PASS
4804 19:56:39.869878 RX DATLAT : PASS
4805 19:56:39.872667 RX DQ/DQS(Engine): PASS
4806 19:56:39.873052 TX OE : NO K
4807 19:56:39.875867 All Pass.
4808 19:56:39.876287
4809 19:56:39.876676 CH 0, Rank 1
4810 19:56:39.879582 SW Impedance : PASS
4811 19:56:39.880018 DUTY Scan : NO K
4812 19:56:39.882435 ZQ Calibration : PASS
4813 19:56:39.886021 Jitter Meter : NO K
4814 19:56:39.886405 CBT Training : PASS
4815 19:56:39.889377 Write leveling : PASS
4816 19:56:39.892617 RX DQS gating : PASS
4817 19:56:39.893032 RX DQ/DQS(RDDQC) : PASS
4818 19:56:39.895782 TX DQ/DQS : PASS
4819 19:56:39.899100 RX DATLAT : PASS
4820 19:56:39.899483 RX DQ/DQS(Engine): PASS
4821 19:56:39.902995 TX OE : NO K
4822 19:56:39.903379 All Pass.
4823 19:56:39.903731
4824 19:56:39.906504 CH 1, Rank 0
4825 19:56:39.906987 SW Impedance : PASS
4826 19:56:39.909224 DUTY Scan : NO K
4827 19:56:39.913155 ZQ Calibration : PASS
4828 19:56:39.913610 Jitter Meter : NO K
4829 19:56:39.916299 CBT Training : PASS
4830 19:56:39.916695 Write leveling : PASS
4831 19:56:39.919449 RX DQS gating : PASS
4832 19:56:39.922774 RX DQ/DQS(RDDQC) : PASS
4833 19:56:39.923160 TX DQ/DQS : PASS
4834 19:56:39.926450 RX DATLAT : PASS
4835 19:56:39.929769 RX DQ/DQS(Engine): PASS
4836 19:56:39.930259 TX OE : NO K
4837 19:56:39.933381 All Pass.
4838 19:56:39.933861
4839 19:56:39.934173 CH 1, Rank 1
4840 19:56:39.936228 SW Impedance : PASS
4841 19:56:39.936610 DUTY Scan : NO K
4842 19:56:39.939390 ZQ Calibration : PASS
4843 19:56:39.942866 Jitter Meter : NO K
4844 19:56:39.943405 CBT Training : PASS
4845 19:56:39.945913 Write leveling : PASS
4846 19:56:39.949396 RX DQS gating : PASS
4847 19:56:39.949856 RX DQ/DQS(RDDQC) : PASS
4848 19:56:39.952880 TX DQ/DQS : PASS
4849 19:56:39.956183 RX DATLAT : PASS
4850 19:56:39.956567 RX DQ/DQS(Engine): PASS
4851 19:56:39.959580 TX OE : NO K
4852 19:56:39.960122 All Pass.
4853 19:56:39.960538
4854 19:56:39.962957 DramC Write-DBI off
4855 19:56:39.965853 PER_BANK_REFRESH: Hybrid Mode
4856 19:56:39.966371 TX_TRACKING: ON
4857 19:56:39.976415 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4858 19:56:39.979569 [FAST_K] Save calibration result to emmc
4859 19:56:39.983021 dramc_set_vcore_voltage set vcore to 662500
4860 19:56:39.983503 Read voltage for 933, 3
4861 19:56:39.985834 Vio18 = 0
4862 19:56:39.986219 Vcore = 662500
4863 19:56:39.986524 Vdram = 0
4864 19:56:39.989518 Vddq = 0
4865 19:56:39.989910 Vmddr = 0
4866 19:56:39.996104 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4867 19:56:39.999056 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4868 19:56:40.002626 MEM_TYPE=3, freq_sel=17
4869 19:56:40.005900 sv_algorithm_assistance_LP4_1600
4870 19:56:40.009680 ============ PULL DRAM RESETB DOWN ============
4871 19:56:40.012604 ========== PULL DRAM RESETB DOWN end =========
4872 19:56:40.019497 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4873 19:56:40.022822 ===================================
4874 19:56:40.023398 LPDDR4 DRAM CONFIGURATION
4875 19:56:40.026110 ===================================
4876 19:56:40.029020 EX_ROW_EN[0] = 0x0
4877 19:56:40.029489 EX_ROW_EN[1] = 0x0
4878 19:56:40.032760 LP4Y_EN = 0x0
4879 19:56:40.035879 WORK_FSP = 0x0
4880 19:56:40.036306 WL = 0x3
4881 19:56:40.039404 RL = 0x3
4882 19:56:40.039872 BL = 0x2
4883 19:56:40.042370 RPST = 0x0
4884 19:56:40.042835 RD_PRE = 0x0
4885 19:56:40.045381 WR_PRE = 0x1
4886 19:56:40.045860 WR_PST = 0x0
4887 19:56:40.049294 DBI_WR = 0x0
4888 19:56:40.049708 DBI_RD = 0x0
4889 19:56:40.052281 OTF = 0x1
4890 19:56:40.055751 ===================================
4891 19:56:40.058838 ===================================
4892 19:56:40.059319 ANA top config
4893 19:56:40.062437 ===================================
4894 19:56:40.065628 DLL_ASYNC_EN = 0
4895 19:56:40.068905 ALL_SLAVE_EN = 1
4896 19:56:40.069325 NEW_RANK_MODE = 1
4897 19:56:40.072024 DLL_IDLE_MODE = 1
4898 19:56:40.075609 LP45_APHY_COMB_EN = 1
4899 19:56:40.079075 TX_ODT_DIS = 1
4900 19:56:40.082398 NEW_8X_MODE = 1
4901 19:56:40.085549 ===================================
4902 19:56:40.085969 ===================================
4903 19:56:40.089268 data_rate = 1866
4904 19:56:40.092174 CKR = 1
4905 19:56:40.095413 DQ_P2S_RATIO = 8
4906 19:56:40.099227 ===================================
4907 19:56:40.102208 CA_P2S_RATIO = 8
4908 19:56:40.105317 DQ_CA_OPEN = 0
4909 19:56:40.108946 DQ_SEMI_OPEN = 0
4910 19:56:40.109506 CA_SEMI_OPEN = 0
4911 19:56:40.112330 CA_FULL_RATE = 0
4912 19:56:40.115685 DQ_CKDIV4_EN = 1
4913 19:56:40.118440 CA_CKDIV4_EN = 1
4914 19:56:40.121855 CA_PREDIV_EN = 0
4915 19:56:40.125473 PH8_DLY = 0
4916 19:56:40.125891 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4917 19:56:40.128615 DQ_AAMCK_DIV = 4
4918 19:56:40.132448 CA_AAMCK_DIV = 4
4919 19:56:40.135584 CA_ADMCK_DIV = 4
4920 19:56:40.138933 DQ_TRACK_CA_EN = 0
4921 19:56:40.141875 CA_PICK = 933
4922 19:56:40.142255 CA_MCKIO = 933
4923 19:56:40.145680 MCKIO_SEMI = 0
4924 19:56:40.148608 PLL_FREQ = 3732
4925 19:56:40.152141 DQ_UI_PI_RATIO = 32
4926 19:56:40.155213 CA_UI_PI_RATIO = 0
4927 19:56:40.158817 ===================================
4928 19:56:40.161685 ===================================
4929 19:56:40.165257 memory_type:LPDDR4
4930 19:56:40.165706 GP_NUM : 10
4931 19:56:40.169002 SRAM_EN : 1
4932 19:56:40.169420 MD32_EN : 0
4933 19:56:40.171612 ===================================
4934 19:56:40.175600 [ANA_INIT] >>>>>>>>>>>>>>
4935 19:56:40.178689 <<<<<< [CONFIGURE PHASE]: ANA_TX
4936 19:56:40.181913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4937 19:56:40.185297 ===================================
4938 19:56:40.188488 data_rate = 1866,PCW = 0X8f00
4939 19:56:40.191611 ===================================
4940 19:56:40.195037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4941 19:56:40.201709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 19:56:40.205373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 19:56:40.212150 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4944 19:56:40.215136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4945 19:56:40.218451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4946 19:56:40.219022 [ANA_INIT] flow start
4947 19:56:40.222215 [ANA_INIT] PLL >>>>>>>>
4948 19:56:40.224968 [ANA_INIT] PLL <<<<<<<<
4949 19:56:40.225488 [ANA_INIT] MIDPI >>>>>>>>
4950 19:56:40.228327 [ANA_INIT] MIDPI <<<<<<<<
4951 19:56:40.231912 [ANA_INIT] DLL >>>>>>>>
4952 19:56:40.232486 [ANA_INIT] flow end
4953 19:56:40.238626 ============ LP4 DIFF to SE enter ============
4954 19:56:40.241623 ============ LP4 DIFF to SE exit ============
4955 19:56:40.244816 [ANA_INIT] <<<<<<<<<<<<<
4956 19:56:40.248064 [Flow] Enable top DCM control >>>>>
4957 19:56:40.251768 [Flow] Enable top DCM control <<<<<
4958 19:56:40.252222 Enable DLL master slave shuffle
4959 19:56:40.258464 ==============================================================
4960 19:56:40.261175 Gating Mode config
4961 19:56:40.264922 ==============================================================
4962 19:56:40.268441 Config description:
4963 19:56:40.278004 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4964 19:56:40.284892 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4965 19:56:40.287919 SELPH_MODE 0: By rank 1: By Phase
4966 19:56:40.294773 ==============================================================
4967 19:56:40.298003 GAT_TRACK_EN = 1
4968 19:56:40.301067 RX_GATING_MODE = 2
4969 19:56:40.304203 RX_GATING_TRACK_MODE = 2
4970 19:56:40.304652 SELPH_MODE = 1
4971 19:56:40.307768 PICG_EARLY_EN = 1
4972 19:56:40.311330 VALID_LAT_VALUE = 1
4973 19:56:40.317794 ==============================================================
4974 19:56:40.321186 Enter into Gating configuration >>>>
4975 19:56:40.324654 Exit from Gating configuration <<<<
4976 19:56:40.327986 Enter into DVFS_PRE_config >>>>>
4977 19:56:40.338084 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4978 19:56:40.341471 Exit from DVFS_PRE_config <<<<<
4979 19:56:40.344234 Enter into PICG configuration >>>>
4980 19:56:40.348141 Exit from PICG configuration <<<<
4981 19:56:40.351365 [RX_INPUT] configuration >>>>>
4982 19:56:40.354599 [RX_INPUT] configuration <<<<<
4983 19:56:40.357620 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4984 19:56:40.364598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4985 19:56:40.371144 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 19:56:40.377839 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 19:56:40.384062 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4988 19:56:40.387730 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4989 19:56:40.393937 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4990 19:56:40.397241 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4991 19:56:40.401045 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4992 19:56:40.404210 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4993 19:56:40.411185 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4994 19:56:40.414374 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4995 19:56:40.417491 ===================================
4996 19:56:40.421128 LPDDR4 DRAM CONFIGURATION
4997 19:56:40.424181 ===================================
4998 19:56:40.424658 EX_ROW_EN[0] = 0x0
4999 19:56:40.427384 EX_ROW_EN[1] = 0x0
5000 19:56:40.427885 LP4Y_EN = 0x0
5001 19:56:40.431106 WORK_FSP = 0x0
5002 19:56:40.431523 WL = 0x3
5003 19:56:40.434383 RL = 0x3
5004 19:56:40.434826 BL = 0x2
5005 19:56:40.437365 RPST = 0x0
5006 19:56:40.437809 RD_PRE = 0x0
5007 19:56:40.440988 WR_PRE = 0x1
5008 19:56:40.441454 WR_PST = 0x0
5009 19:56:40.443854 DBI_WR = 0x0
5010 19:56:40.444291 DBI_RD = 0x0
5011 19:56:40.447612 OTF = 0x1
5012 19:56:40.451009 ===================================
5013 19:56:40.454160 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5014 19:56:40.457543 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5015 19:56:40.463983 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 19:56:40.467938 ===================================
5017 19:56:40.468364 LPDDR4 DRAM CONFIGURATION
5018 19:56:40.471049 ===================================
5019 19:56:40.474166 EX_ROW_EN[0] = 0x10
5020 19:56:40.477707 EX_ROW_EN[1] = 0x0
5021 19:56:40.478135 LP4Y_EN = 0x0
5022 19:56:40.480830 WORK_FSP = 0x0
5023 19:56:40.481257 WL = 0x3
5024 19:56:40.484129 RL = 0x3
5025 19:56:40.484548 BL = 0x2
5026 19:56:40.487330 RPST = 0x0
5027 19:56:40.487879 RD_PRE = 0x0
5028 19:56:40.490711 WR_PRE = 0x1
5029 19:56:40.491128 WR_PST = 0x0
5030 19:56:40.493836 DBI_WR = 0x0
5031 19:56:40.494299 DBI_RD = 0x0
5032 19:56:40.497355 OTF = 0x1
5033 19:56:40.500643 ===================================
5034 19:56:40.507581 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5035 19:56:40.510827 nWR fixed to 30
5036 19:56:40.511246 [ModeRegInit_LP4] CH0 RK0
5037 19:56:40.514017 [ModeRegInit_LP4] CH0 RK1
5038 19:56:40.517229 [ModeRegInit_LP4] CH1 RK0
5039 19:56:40.520988 [ModeRegInit_LP4] CH1 RK1
5040 19:56:40.521482 match AC timing 9
5041 19:56:40.527113 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5042 19:56:40.530904 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5043 19:56:40.534118 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5044 19:56:40.540377 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5045 19:56:40.544249 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5046 19:56:40.544669 ==
5047 19:56:40.547154 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 19:56:40.550778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 19:56:40.551195 ==
5050 19:56:40.557224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 19:56:40.564106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5052 19:56:40.567430 [CA 0] Center 37 (6~68) winsize 63
5053 19:56:40.570847 [CA 1] Center 37 (6~68) winsize 63
5054 19:56:40.573795 [CA 2] Center 34 (4~65) winsize 62
5055 19:56:40.577389 [CA 3] Center 34 (3~65) winsize 63
5056 19:56:40.580309 [CA 4] Center 33 (3~64) winsize 62
5057 19:56:40.580725 [CA 5] Center 32 (2~62) winsize 61
5058 19:56:40.583767
5059 19:56:40.586962 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5060 19:56:40.587407
5061 19:56:40.590822 [CATrainingPosCal] consider 1 rank data
5062 19:56:40.593647 u2DelayCellTimex100 = 270/100 ps
5063 19:56:40.597045 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5064 19:56:40.600307 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5065 19:56:40.603634 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5066 19:56:40.606587 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5067 19:56:40.609985 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5068 19:56:40.613624 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5069 19:56:40.613707
5070 19:56:40.619991 CA PerBit enable=1, Macro0, CA PI delay=32
5071 19:56:40.620068
5072 19:56:40.620132 [CBTSetCACLKResult] CA Dly = 32
5073 19:56:40.623262 CS Dly: 5 (0~36)
5074 19:56:40.623359 ==
5075 19:56:40.626486 Dram Type= 6, Freq= 0, CH_0, rank 1
5076 19:56:40.629990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 19:56:40.630073 ==
5078 19:56:40.636975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 19:56:40.643193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5080 19:56:40.646406 [CA 0] Center 37 (6~68) winsize 63
5081 19:56:40.650133 [CA 1] Center 37 (7~68) winsize 62
5082 19:56:40.653235 [CA 2] Center 34 (4~65) winsize 62
5083 19:56:40.656360 [CA 3] Center 34 (3~65) winsize 63
5084 19:56:40.660182 [CA 4] Center 32 (2~63) winsize 62
5085 19:56:40.663407 [CA 5] Center 32 (2~62) winsize 61
5086 19:56:40.663530
5087 19:56:40.666501 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5088 19:56:40.666638
5089 19:56:40.670079 [CATrainingPosCal] consider 2 rank data
5090 19:56:40.672921 u2DelayCellTimex100 = 270/100 ps
5091 19:56:40.676659 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5092 19:56:40.679805 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5093 19:56:40.683020 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5094 19:56:40.686372 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5095 19:56:40.689874 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5096 19:56:40.693339 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5097 19:56:40.693644
5098 19:56:40.700105 CA PerBit enable=1, Macro0, CA PI delay=32
5099 19:56:40.700496
5100 19:56:40.703560 [CBTSetCACLKResult] CA Dly = 32
5101 19:56:40.704028 CS Dly: 5 (0~37)
5102 19:56:40.704429
5103 19:56:40.706715 ----->DramcWriteLeveling(PI) begin...
5104 19:56:40.707167 ==
5105 19:56:40.710098 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 19:56:40.713083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 19:56:40.713519 ==
5108 19:56:40.716770 Write leveling (Byte 0): 32 => 32
5109 19:56:40.720315 Write leveling (Byte 1): 32 => 32
5110 19:56:40.723434 DramcWriteLeveling(PI) end<-----
5111 19:56:40.723974
5112 19:56:40.724379 ==
5113 19:56:40.726444 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 19:56:40.733489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 19:56:40.733915 ==
5116 19:56:40.734255 [Gating] SW mode calibration
5117 19:56:40.743203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5118 19:56:40.746398 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5119 19:56:40.749596 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5120 19:56:40.756516 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 19:56:40.759684 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 19:56:40.762795 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 19:56:40.769899 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 19:56:40.772953 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 19:56:40.776719 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5126 19:56:40.782795 0 14 28 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
5127 19:56:40.786602 0 15 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
5128 19:56:40.789752 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 19:56:40.796482 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 19:56:40.799631 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 19:56:40.802608 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 19:56:40.809561 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 19:56:40.812339 0 15 24 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
5134 19:56:40.816008 0 15 28 | B1->B0 | 2424 3b3b | 0 0 | (1 1) (0 0)
5135 19:56:40.822448 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5136 19:56:40.826042 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 19:56:40.829476 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 19:56:40.835650 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 19:56:40.838857 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 19:56:40.841927 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 19:56:40.848672 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5142 19:56:40.851900 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5143 19:56:40.855699 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5144 19:56:40.861825 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 19:56:40.865647 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 19:56:40.868917 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 19:56:40.875502 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 19:56:40.878848 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 19:56:40.881998 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 19:56:40.888805 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 19:56:40.892054 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 19:56:40.895182 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 19:56:40.902053 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 19:56:40.905084 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 19:56:40.908240 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 19:56:40.915267 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 19:56:40.918367 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5158 19:56:40.921863 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5159 19:56:40.925226 Total UI for P1: 0, mck2ui 16
5160 19:56:40.928489 best dqsien dly found for B0: ( 1, 2, 24)
5161 19:56:40.931588 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5162 19:56:40.938207 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 19:56:40.941901 Total UI for P1: 0, mck2ui 16
5164 19:56:40.945218 best dqsien dly found for B1: ( 1, 2, 30)
5165 19:56:40.948207 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5166 19:56:40.951594 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5167 19:56:40.951736
5168 19:56:40.954931 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5169 19:56:40.958105 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5170 19:56:40.961565 [Gating] SW calibration Done
5171 19:56:40.961671 ==
5172 19:56:40.964685 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 19:56:40.968175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 19:56:40.968258 ==
5175 19:56:40.971544 RX Vref Scan: 0
5176 19:56:40.971625
5177 19:56:40.975080 RX Vref 0 -> 0, step: 1
5178 19:56:40.975161
5179 19:56:40.975248 RX Delay -80 -> 252, step: 8
5180 19:56:40.981484 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5181 19:56:40.985081 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5182 19:56:40.988124 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5183 19:56:40.991317 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5184 19:56:40.995147 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5185 19:56:40.998348 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5186 19:56:41.004602 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5187 19:56:41.008223 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5188 19:56:41.011867 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5189 19:56:41.015009 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5190 19:56:41.018248 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5191 19:56:41.021428 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5192 19:56:41.028184 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5193 19:56:41.031554 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5194 19:56:41.034595 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5195 19:56:41.038326 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5196 19:56:41.038438 ==
5197 19:56:41.041458 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 19:56:41.044556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 19:56:41.048143 ==
5200 19:56:41.048254 DQS Delay:
5201 19:56:41.048346 DQS0 = 0, DQS1 = 0
5202 19:56:41.051275 DQM Delay:
5203 19:56:41.051356 DQM0 = 104, DQM1 = 95
5204 19:56:41.054438 DQ Delay:
5205 19:56:41.058334 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5206 19:56:41.061532 DQ4 =103, DQ5 =91, DQ6 =115, DQ7 =115
5207 19:56:41.064546 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5208 19:56:41.068161 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5209 19:56:41.068244
5210 19:56:41.068309
5211 19:56:41.068370 ==
5212 19:56:41.071237 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 19:56:41.074739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 19:56:41.074821 ==
5215 19:56:41.074886
5216 19:56:41.074945
5217 19:56:41.077840 TX Vref Scan disable
5218 19:56:41.077921 == TX Byte 0 ==
5219 19:56:41.084811 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5220 19:56:41.088193 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5221 19:56:41.088275 == TX Byte 1 ==
5222 19:56:41.094790 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5223 19:56:41.097975 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5224 19:56:41.098057 ==
5225 19:56:41.101130 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 19:56:41.104725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 19:56:41.104806 ==
5228 19:56:41.104871
5229 19:56:41.107901
5230 19:56:41.107982 TX Vref Scan disable
5231 19:56:41.110872 == TX Byte 0 ==
5232 19:56:41.114711 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5233 19:56:41.117814 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5234 19:56:41.121085 == TX Byte 1 ==
5235 19:56:41.124160 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5236 19:56:41.127959 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5237 19:56:41.128041
5238 19:56:41.131152 [DATLAT]
5239 19:56:41.131233 Freq=933, CH0 RK0
5240 19:56:41.131297
5241 19:56:41.134369 DATLAT Default: 0xd
5242 19:56:41.134450 0, 0xFFFF, sum = 0
5243 19:56:41.138034 1, 0xFFFF, sum = 0
5244 19:56:41.138116 2, 0xFFFF, sum = 0
5245 19:56:41.141007 3, 0xFFFF, sum = 0
5246 19:56:41.141090 4, 0xFFFF, sum = 0
5247 19:56:41.144462 5, 0xFFFF, sum = 0
5248 19:56:41.144545 6, 0xFFFF, sum = 0
5249 19:56:41.147581 7, 0xFFFF, sum = 0
5250 19:56:41.151333 8, 0xFFFF, sum = 0
5251 19:56:41.151421 9, 0xFFFF, sum = 0
5252 19:56:41.154289 10, 0x0, sum = 1
5253 19:56:41.154384 11, 0x0, sum = 2
5254 19:56:41.154460 12, 0x0, sum = 3
5255 19:56:41.157890 13, 0x0, sum = 4
5256 19:56:41.157992 best_step = 11
5257 19:56:41.158073
5258 19:56:41.161056 ==
5259 19:56:41.161158 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 19:56:41.167434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 19:56:41.167557 ==
5262 19:56:41.167668 RX Vref Scan: 1
5263 19:56:41.167763
5264 19:56:41.171031 RX Vref 0 -> 0, step: 1
5265 19:56:41.171151
5266 19:56:41.174636 RX Delay -45 -> 252, step: 4
5267 19:56:41.174759
5268 19:56:41.178015 Set Vref, RX VrefLevel [Byte0]: 56
5269 19:56:41.181072 [Byte1]: 48
5270 19:56:41.181226
5271 19:56:41.184088 Final RX Vref Byte 0 = 56 to rank0
5272 19:56:41.187612 Final RX Vref Byte 1 = 48 to rank0
5273 19:56:41.191017 Final RX Vref Byte 0 = 56 to rank1
5274 19:56:41.194521 Final RX Vref Byte 1 = 48 to rank1==
5275 19:56:41.197478 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 19:56:41.201065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 19:56:41.201364 ==
5278 19:56:41.204779 DQS Delay:
5279 19:56:41.205236 DQS0 = 0, DQS1 = 0
5280 19:56:41.207632 DQM Delay:
5281 19:56:41.208180 DQM0 = 105, DQM1 = 94
5282 19:56:41.208737 DQ Delay:
5283 19:56:41.210924 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5284 19:56:41.214516 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5285 19:56:41.217831 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =88
5286 19:56:41.224628 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5287 19:56:41.225225
5288 19:56:41.225677
5289 19:56:41.230800 [DQSOSCAuto] RK0, (LSB)MR18= 0x3229, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5290 19:56:41.234600 CH0 RK0: MR19=505, MR18=3229
5291 19:56:41.241033 CH0_RK0: MR19=0x505, MR18=0x3229, DQSOSC=406, MR23=63, INC=65, DEC=43
5292 19:56:41.241461
5293 19:56:41.244802 ----->DramcWriteLeveling(PI) begin...
5294 19:56:41.245228 ==
5295 19:56:41.247870 Dram Type= 6, Freq= 0, CH_0, rank 1
5296 19:56:41.251320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 19:56:41.251786 ==
5298 19:56:41.254652 Write leveling (Byte 0): 32 => 32
5299 19:56:41.257468 Write leveling (Byte 1): 30 => 30
5300 19:56:41.261188 DramcWriteLeveling(PI) end<-----
5301 19:56:41.261607
5302 19:56:41.261942 ==
5303 19:56:41.264525 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 19:56:41.267706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 19:56:41.268133 ==
5306 19:56:41.270770 [Gating] SW mode calibration
5307 19:56:41.277800 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5308 19:56:41.284119 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5309 19:56:41.287141 0 14 0 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 1)
5310 19:56:41.294149 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 19:56:41.297372 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 19:56:41.300714 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 19:56:41.303978 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 19:56:41.310739 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 19:56:41.313683 0 14 24 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 1)
5316 19:56:41.317274 0 14 28 | B1->B0 | 2f2f 2e2e | 0 0 | (1 0) (1 0)
5317 19:56:41.323890 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 19:56:41.326866 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 19:56:41.330580 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 19:56:41.337076 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 19:56:41.340303 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 19:56:41.343485 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 19:56:41.350609 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5324 19:56:41.353740 0 15 28 | B1->B0 | 3b3b 3c3c | 0 1 | (1 1) (0 0)
5325 19:56:41.357339 1 0 0 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
5326 19:56:41.363609 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 19:56:41.366678 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 19:56:41.370381 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 19:56:41.376916 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 19:56:41.380695 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 19:56:41.383610 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 19:56:41.390456 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5333 19:56:41.393480 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 19:56:41.396719 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 19:56:41.403466 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 19:56:41.406952 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 19:56:41.410441 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 19:56:41.417107 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 19:56:41.420363 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 19:56:41.423418 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 19:56:41.429973 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 19:56:41.433910 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 19:56:41.436979 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 19:56:41.443573 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 19:56:41.446967 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 19:56:41.450330 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 19:56:41.453487 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 19:56:41.460323 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5349 19:56:41.463406 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 19:56:41.466477 Total UI for P1: 0, mck2ui 16
5351 19:56:41.470153 best dqsien dly found for B0: ( 1, 2, 28)
5352 19:56:41.473147 Total UI for P1: 0, mck2ui 16
5353 19:56:41.476875 best dqsien dly found for B1: ( 1, 2, 28)
5354 19:56:41.480142 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5355 19:56:41.483445 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5356 19:56:41.483929
5357 19:56:41.486423 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5358 19:56:41.493230 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5359 19:56:41.493655 [Gating] SW calibration Done
5360 19:56:41.494037 ==
5361 19:56:41.496284 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 19:56:41.503284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 19:56:41.503762 ==
5364 19:56:41.504197 RX Vref Scan: 0
5365 19:56:41.504591
5366 19:56:41.506370 RX Vref 0 -> 0, step: 1
5367 19:56:41.506850
5368 19:56:41.509622 RX Delay -80 -> 252, step: 8
5369 19:56:41.512909 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5370 19:56:41.515611 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5371 19:56:41.519178 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5372 19:56:41.526040 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5373 19:56:41.529192 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5374 19:56:41.532818 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5375 19:56:41.535840 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5376 19:56:41.539111 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5377 19:56:41.542289 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5378 19:56:41.546163 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5379 19:56:41.552338 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5380 19:56:41.555624 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5381 19:56:41.559042 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5382 19:56:41.562551 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5383 19:56:41.565391 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5384 19:56:41.572126 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5385 19:56:41.572213 ==
5386 19:56:41.575762 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 19:56:41.578881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 19:56:41.578965 ==
5389 19:56:41.579031 DQS Delay:
5390 19:56:41.582705 DQS0 = 0, DQS1 = 0
5391 19:56:41.582789 DQM Delay:
5392 19:56:41.585753 DQM0 = 105, DQM1 = 94
5393 19:56:41.585836 DQ Delay:
5394 19:56:41.588753 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5395 19:56:41.592356 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =115
5396 19:56:41.595478 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5397 19:56:41.598610 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5398 19:56:41.598694
5399 19:56:41.598760
5400 19:56:41.598828 ==
5401 19:56:41.602303 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 19:56:41.605576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 19:56:41.608725 ==
5404 19:56:41.608817
5405 19:56:41.608881
5406 19:56:41.608957 TX Vref Scan disable
5407 19:56:41.612062 == TX Byte 0 ==
5408 19:56:41.615766 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5409 19:56:41.618871 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5410 19:56:41.622291 == TX Byte 1 ==
5411 19:56:41.625711 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5412 19:56:41.628623 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5413 19:56:41.628701 ==
5414 19:56:41.632099 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 19:56:41.638892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 19:56:41.639007 ==
5417 19:56:41.639082
5418 19:56:41.639146
5419 19:56:41.641746 TX Vref Scan disable
5420 19:56:41.641822 == TX Byte 0 ==
5421 19:56:41.649005 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5422 19:56:41.652162 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5423 19:56:41.652237 == TX Byte 1 ==
5424 19:56:41.658470 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5425 19:56:41.662071 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5426 19:56:41.662150
5427 19:56:41.662213 [DATLAT]
5428 19:56:41.665157 Freq=933, CH0 RK1
5429 19:56:41.665240
5430 19:56:41.665311 DATLAT Default: 0xb
5431 19:56:41.668672 0, 0xFFFF, sum = 0
5432 19:56:41.668784 1, 0xFFFF, sum = 0
5433 19:56:41.671725 2, 0xFFFF, sum = 0
5434 19:56:41.671829 3, 0xFFFF, sum = 0
5435 19:56:41.675024 4, 0xFFFF, sum = 0
5436 19:56:41.675137 5, 0xFFFF, sum = 0
5437 19:56:41.678263 6, 0xFFFF, sum = 0
5438 19:56:41.678344 7, 0xFFFF, sum = 0
5439 19:56:41.681795 8, 0xFFFF, sum = 0
5440 19:56:41.681871 9, 0xFFFF, sum = 0
5441 19:56:41.685206 10, 0x0, sum = 1
5442 19:56:41.685284 11, 0x0, sum = 2
5443 19:56:41.688833 12, 0x0, sum = 3
5444 19:56:41.688938 13, 0x0, sum = 4
5445 19:56:41.691939 best_step = 11
5446 19:56:41.692042
5447 19:56:41.692110 ==
5448 19:56:41.695497 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 19:56:41.698640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 19:56:41.698748 ==
5451 19:56:41.701815 RX Vref Scan: 0
5452 19:56:41.701919
5453 19:56:41.702023 RX Vref 0 -> 0, step: 1
5454 19:56:41.702116
5455 19:56:41.704970 RX Delay -45 -> 252, step: 4
5456 19:56:41.711866 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5457 19:56:41.715665 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5458 19:56:41.718929 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5459 19:56:41.722227 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5460 19:56:41.725384 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5461 19:56:41.732341 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5462 19:56:41.735414 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5463 19:56:41.739029 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5464 19:56:41.741985 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5465 19:56:41.745626 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5466 19:56:41.748861 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5467 19:56:41.755605 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5468 19:56:41.758830 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5469 19:56:41.762018 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5470 19:56:41.765227 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5471 19:56:41.772102 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5472 19:56:41.772210 ==
5473 19:56:41.775229 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 19:56:41.778411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 19:56:41.778518 ==
5476 19:56:41.778620 DQS Delay:
5477 19:56:41.781873 DQS0 = 0, DQS1 = 0
5478 19:56:41.781980 DQM Delay:
5479 19:56:41.785002 DQM0 = 104, DQM1 = 94
5480 19:56:41.785101 DQ Delay:
5481 19:56:41.788438 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5482 19:56:41.791758 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5483 19:56:41.795371 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =86
5484 19:56:41.798149 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5485 19:56:41.798249
5486 19:56:41.798347
5487 19:56:41.808280 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5488 19:56:41.808398 CH0 RK1: MR19=505, MR18=2902
5489 19:56:41.814885 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5490 19:56:41.818674 [RxdqsGatingPostProcess] freq 933
5491 19:56:41.825105 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5492 19:56:41.828265 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 19:56:41.832060 best DQS1 dly(2T, 0.5T) = (0, 10)
5494 19:56:41.835235 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 19:56:41.838397 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5496 19:56:41.841960 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 19:56:41.845300 best DQS1 dly(2T, 0.5T) = (0, 10)
5498 19:56:41.845415 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 19:56:41.848487 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5500 19:56:41.851734 Pre-setting of DQS Precalculation
5501 19:56:41.858195 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5502 19:56:41.858317 ==
5503 19:56:41.861564 Dram Type= 6, Freq= 0, CH_1, rank 0
5504 19:56:41.864732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 19:56:41.864812 ==
5506 19:56:41.871264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5507 19:56:41.878372 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5508 19:56:41.882056 [CA 0] Center 36 (6~67) winsize 62
5509 19:56:41.885172 [CA 1] Center 36 (6~67) winsize 62
5510 19:56:41.888477 [CA 2] Center 34 (4~65) winsize 62
5511 19:56:41.891789 [CA 3] Center 34 (4~65) winsize 62
5512 19:56:41.894954 [CA 4] Center 34 (4~64) winsize 61
5513 19:56:41.898347 [CA 5] Center 33 (3~64) winsize 62
5514 19:56:41.898424
5515 19:56:41.901346 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5516 19:56:41.901420
5517 19:56:41.905231 [CATrainingPosCal] consider 1 rank data
5518 19:56:41.908102 u2DelayCellTimex100 = 270/100 ps
5519 19:56:41.911558 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5520 19:56:41.915097 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5521 19:56:41.918408 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5522 19:56:41.921651 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5523 19:56:41.925093 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5524 19:56:41.928287 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5525 19:56:41.928372
5526 19:56:41.931412 CA PerBit enable=1, Macro0, CA PI delay=33
5527 19:56:41.934655
5528 19:56:41.934758 [CBTSetCACLKResult] CA Dly = 33
5529 19:56:41.938352 CS Dly: 7 (0~38)
5530 19:56:41.938453 ==
5531 19:56:41.941481 Dram Type= 6, Freq= 0, CH_1, rank 1
5532 19:56:41.944508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 19:56:41.944587 ==
5534 19:56:41.951484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 19:56:41.957870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5536 19:56:41.961560 [CA 0] Center 36 (6~67) winsize 62
5537 19:56:41.964855 [CA 1] Center 37 (6~68) winsize 63
5538 19:56:41.967883 [CA 2] Center 35 (5~65) winsize 61
5539 19:56:41.971358 [CA 3] Center 34 (4~65) winsize 62
5540 19:56:41.974606 [CA 4] Center 34 (4~65) winsize 62
5541 19:56:41.978115 [CA 5] Center 33 (3~64) winsize 62
5542 19:56:41.978198
5543 19:56:41.981547 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5544 19:56:41.981629
5545 19:56:41.984527 [CATrainingPosCal] consider 2 rank data
5546 19:56:41.988005 u2DelayCellTimex100 = 270/100 ps
5547 19:56:41.991161 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5548 19:56:41.994408 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5549 19:56:41.997975 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5550 19:56:42.001190 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5551 19:56:42.004358 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5552 19:56:42.008070 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 19:56:42.008154
5554 19:56:42.014464 CA PerBit enable=1, Macro0, CA PI delay=33
5555 19:56:42.014548
5556 19:56:42.018151 [CBTSetCACLKResult] CA Dly = 33
5557 19:56:42.018578 CS Dly: 8 (0~40)
5558 19:56:42.018920
5559 19:56:42.021017 ----->DramcWriteLeveling(PI) begin...
5560 19:56:42.021483 ==
5561 19:56:42.024669 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 19:56:42.028252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 19:56:42.031174 ==
5564 19:56:42.031597 Write leveling (Byte 0): 27 => 27
5565 19:56:42.034730 Write leveling (Byte 1): 27 => 27
5566 19:56:42.038367 DramcWriteLeveling(PI) end<-----
5567 19:56:42.038809
5568 19:56:42.039148 ==
5569 19:56:42.041184 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 19:56:42.048016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 19:56:42.048544 ==
5572 19:56:42.049002 [Gating] SW mode calibration
5573 19:56:42.058106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5574 19:56:42.061248 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5575 19:56:42.067587 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 19:56:42.071430 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 19:56:42.074584 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 19:56:42.077759 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 19:56:42.084414 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 19:56:42.087522 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 19:56:42.090852 0 14 24 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
5582 19:56:42.097285 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
5583 19:56:42.100650 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 19:56:42.103738 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 19:56:42.110645 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 19:56:42.113681 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 19:56:42.117554 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 19:56:42.123711 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 19:56:42.127247 0 15 24 | B1->B0 | 2828 3333 | 0 0 | (1 1) (0 0)
5590 19:56:42.130275 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5591 19:56:42.137234 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 19:56:42.140156 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 19:56:42.143419 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 19:56:42.150174 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 19:56:42.153548 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 19:56:42.156971 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 19:56:42.163896 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5598 19:56:42.167083 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5599 19:56:42.170321 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 19:56:42.177172 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 19:56:42.180293 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 19:56:42.183459 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 19:56:42.190201 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 19:56:42.193752 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 19:56:42.197035 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 19:56:42.203311 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 19:56:42.206765 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 19:56:42.210275 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 19:56:42.216996 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 19:56:42.220261 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 19:56:42.223282 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 19:56:42.226739 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 19:56:42.233563 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5614 19:56:42.236562 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 19:56:42.240261 Total UI for P1: 0, mck2ui 16
5616 19:56:42.243426 best dqsien dly found for B0: ( 1, 2, 24)
5617 19:56:42.246535 Total UI for P1: 0, mck2ui 16
5618 19:56:42.250290 best dqsien dly found for B1: ( 1, 2, 26)
5619 19:56:42.253279 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5620 19:56:42.256648 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5621 19:56:42.256732
5622 19:56:42.259988 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5623 19:56:42.266566 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5624 19:56:42.266649 [Gating] SW calibration Done
5625 19:56:42.266716 ==
5626 19:56:42.269545 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 19:56:42.276540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 19:56:42.276625 ==
5629 19:56:42.276691 RX Vref Scan: 0
5630 19:56:42.276755
5631 19:56:42.279770 RX Vref 0 -> 0, step: 1
5632 19:56:42.279852
5633 19:56:42.282971 RX Delay -80 -> 252, step: 8
5634 19:56:42.286661 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5635 19:56:42.289716 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5636 19:56:42.292855 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5637 19:56:42.296075 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5638 19:56:42.303291 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5639 19:56:42.306184 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5640 19:56:42.309611 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5641 19:56:42.312964 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5642 19:56:42.316563 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5643 19:56:42.319781 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5644 19:56:42.326269 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5645 19:56:42.329563 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5646 19:56:42.332850 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5647 19:56:42.336346 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5648 19:56:42.339538 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5649 19:56:42.346108 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5650 19:56:42.346191 ==
5651 19:56:42.349282 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 19:56:42.352953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 19:56:42.353037 ==
5654 19:56:42.353103 DQS Delay:
5655 19:56:42.356203 DQS0 = 0, DQS1 = 0
5656 19:56:42.356285 DQM Delay:
5657 19:56:42.359317 DQM0 = 102, DQM1 = 99
5658 19:56:42.359400 DQ Delay:
5659 19:56:42.362437 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5660 19:56:42.365933 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5661 19:56:42.369394 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5662 19:56:42.372260 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =107
5663 19:56:42.372342
5664 19:56:42.372407
5665 19:56:42.372511 ==
5666 19:56:42.375546 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 19:56:42.382219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 19:56:42.382303 ==
5669 19:56:42.382369
5670 19:56:42.382431
5671 19:56:42.382489 TX Vref Scan disable
5672 19:56:42.386151 == TX Byte 0 ==
5673 19:56:42.389310 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5674 19:56:42.395817 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5675 19:56:42.395900 == TX Byte 1 ==
5676 19:56:42.398940 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5677 19:56:42.405773 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5678 19:56:42.405859 ==
5679 19:56:42.409282 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 19:56:42.412399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 19:56:42.412483 ==
5682 19:56:42.412549
5683 19:56:42.412610
5684 19:56:42.416032 TX Vref Scan disable
5685 19:56:42.416114 == TX Byte 0 ==
5686 19:56:42.422280 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5687 19:56:42.426101 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5688 19:56:42.426185 == TX Byte 1 ==
5689 19:56:42.432597 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5690 19:56:42.435615 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5691 19:56:42.435739
5692 19:56:42.435806 [DATLAT]
5693 19:56:42.439267 Freq=933, CH1 RK0
5694 19:56:42.439350
5695 19:56:42.439416 DATLAT Default: 0xd
5696 19:56:42.442606 0, 0xFFFF, sum = 0
5697 19:56:42.442695 1, 0xFFFF, sum = 0
5698 19:56:42.445607 2, 0xFFFF, sum = 0
5699 19:56:42.445682 3, 0xFFFF, sum = 0
5700 19:56:42.449097 4, 0xFFFF, sum = 0
5701 19:56:42.449174 5, 0xFFFF, sum = 0
5702 19:56:42.452113 6, 0xFFFF, sum = 0
5703 19:56:42.455793 7, 0xFFFF, sum = 0
5704 19:56:42.455865 8, 0xFFFF, sum = 0
5705 19:56:42.458825 9, 0xFFFF, sum = 0
5706 19:56:42.458909 10, 0x0, sum = 1
5707 19:56:42.458976 11, 0x0, sum = 2
5708 19:56:42.462393 12, 0x0, sum = 3
5709 19:56:42.462476 13, 0x0, sum = 4
5710 19:56:42.465587 best_step = 11
5711 19:56:42.465670
5712 19:56:42.465735 ==
5713 19:56:42.468753 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 19:56:42.472358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 19:56:42.472442 ==
5716 19:56:42.475495 RX Vref Scan: 1
5717 19:56:42.475578
5718 19:56:42.475671 RX Vref 0 -> 0, step: 1
5719 19:56:42.475750
5720 19:56:42.478954 RX Delay -45 -> 252, step: 4
5721 19:56:42.479036
5722 19:56:42.482026 Set Vref, RX VrefLevel [Byte0]: 56
5723 19:56:42.485329 [Byte1]: 48
5724 19:56:42.489781
5725 19:56:42.489863 Final RX Vref Byte 0 = 56 to rank0
5726 19:56:42.492911 Final RX Vref Byte 1 = 48 to rank0
5727 19:56:42.496673 Final RX Vref Byte 0 = 56 to rank1
5728 19:56:42.499828 Final RX Vref Byte 1 = 48 to rank1==
5729 19:56:42.503094 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 19:56:42.509320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 19:56:42.509403 ==
5732 19:56:42.509468 DQS Delay:
5733 19:56:42.512946 DQS0 = 0, DQS1 = 0
5734 19:56:42.513028 DQM Delay:
5735 19:56:42.513093 DQM0 = 104, DQM1 = 99
5736 19:56:42.516394 DQ Delay:
5737 19:56:42.519546 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5738 19:56:42.522570 DQ4 =104, DQ5 =114, DQ6 =112, DQ7 =104
5739 19:56:42.525957 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =96
5740 19:56:42.529491 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =108
5741 19:56:42.529574
5742 19:56:42.529639
5743 19:56:42.536082 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a31, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5744 19:56:42.539189 CH1 RK0: MR19=505, MR18=1A31
5745 19:56:42.545974 CH1_RK0: MR19=0x505, MR18=0x1A31, DQSOSC=406, MR23=63, INC=65, DEC=43
5746 19:56:42.546058
5747 19:56:42.549467 ----->DramcWriteLeveling(PI) begin...
5748 19:56:42.549551 ==
5749 19:56:42.552428 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 19:56:42.556091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 19:56:42.559353 ==
5752 19:56:42.559436 Write leveling (Byte 0): 29 => 29
5753 19:56:42.562871 Write leveling (Byte 1): 29 => 29
5754 19:56:42.566196 DramcWriteLeveling(PI) end<-----
5755 19:56:42.566279
5756 19:56:42.566345 ==
5757 19:56:42.569658 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 19:56:42.575772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 19:56:42.575855 ==
5760 19:56:42.575922 [Gating] SW mode calibration
5761 19:56:42.585787 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5762 19:56:42.589375 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5763 19:56:42.595926 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 19:56:42.599084 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 19:56:42.602178 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 19:56:42.605917 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 19:56:42.612355 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 19:56:42.615991 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 19:56:42.619090 0 14 24 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 0)
5770 19:56:42.625579 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
5771 19:56:42.629349 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 19:56:42.632363 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 19:56:42.638852 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 19:56:42.642409 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 19:56:42.645569 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 19:56:42.652431 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 19:56:42.655549 0 15 24 | B1->B0 | 3a3a 2727 | 0 0 | (0 0) (0 0)
5778 19:56:42.658808 0 15 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
5779 19:56:42.665893 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 19:56:42.668832 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 19:56:42.672338 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 19:56:42.679072 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 19:56:42.682466 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 19:56:42.685272 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 19:56:42.692527 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5786 19:56:42.695603 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 19:56:42.699064 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 19:56:42.705805 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 19:56:42.708956 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 19:56:42.712072 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 19:56:42.715796 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 19:56:42.722069 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 19:56:42.725639 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 19:56:42.728998 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 19:56:42.735752 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 19:56:42.738762 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 19:56:42.742417 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 19:56:42.748458 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 19:56:42.752249 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 19:56:42.755565 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 19:56:42.761777 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5802 19:56:42.765302 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5803 19:56:42.768817 Total UI for P1: 0, mck2ui 16
5804 19:56:42.772339 best dqsien dly found for B0: ( 1, 2, 24)
5805 19:56:42.774923 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 19:56:42.778673 Total UI for P1: 0, mck2ui 16
5807 19:56:42.781852 best dqsien dly found for B1: ( 1, 2, 26)
5808 19:56:42.784919 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5809 19:56:42.788465 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5810 19:56:42.791904
5811 19:56:42.794951 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5812 19:56:42.798073 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5813 19:56:42.801745 [Gating] SW calibration Done
5814 19:56:42.801856 ==
5815 19:56:42.804701 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 19:56:42.808176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 19:56:42.808261 ==
5818 19:56:42.808339 RX Vref Scan: 0
5819 19:56:42.808402
5820 19:56:42.811428 RX Vref 0 -> 0, step: 1
5821 19:56:42.811524
5822 19:56:42.814600 RX Delay -80 -> 252, step: 8
5823 19:56:42.818425 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5824 19:56:42.821646 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5825 19:56:42.828576 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5826 19:56:42.831609 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5827 19:56:42.835128 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5828 19:56:42.838353 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5829 19:56:42.841649 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5830 19:56:42.844653 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5831 19:56:42.851787 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5832 19:56:42.854811 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5833 19:56:42.858067 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5834 19:56:42.861791 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5835 19:56:42.865012 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5836 19:56:42.871266 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5837 19:56:42.875080 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5838 19:56:42.877982 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5839 19:56:42.878057 ==
5840 19:56:42.881589 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 19:56:42.884581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 19:56:42.884665 ==
5843 19:56:42.888441 DQS Delay:
5844 19:56:42.888521 DQS0 = 0, DQS1 = 0
5845 19:56:42.891585 DQM Delay:
5846 19:56:42.891705 DQM0 = 104, DQM1 = 98
5847 19:56:42.891774 DQ Delay:
5848 19:56:42.894648 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =99
5849 19:56:42.897783 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5850 19:56:42.901641 DQ8 =87, DQ9 =87, DQ10 =103, DQ11 =91
5851 19:56:42.908028 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5852 19:56:42.908111
5853 19:56:42.908177
5854 19:56:42.908247 ==
5855 19:56:42.911553 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 19:56:42.914723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 19:56:42.914799 ==
5858 19:56:42.914863
5859 19:56:42.914923
5860 19:56:42.917848 TX Vref Scan disable
5861 19:56:42.917918 == TX Byte 0 ==
5862 19:56:42.924236 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5863 19:56:42.927898 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5864 19:56:42.927983 == TX Byte 1 ==
5865 19:56:42.934766 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5866 19:56:42.937933 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5867 19:56:42.938021 ==
5868 19:56:42.940996 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 19:56:42.944283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 19:56:42.944364 ==
5871 19:56:42.944430
5872 19:56:42.947757
5873 19:56:42.947841 TX Vref Scan disable
5874 19:56:42.951129 == TX Byte 0 ==
5875 19:56:42.954380 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5876 19:56:42.957770 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5877 19:56:42.961210 == TX Byte 1 ==
5878 19:56:42.964386 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5879 19:56:42.968202 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5880 19:56:42.968299
5881 19:56:42.971366 [DATLAT]
5882 19:56:42.971484 Freq=933, CH1 RK1
5883 19:56:42.971585
5884 19:56:42.974393 DATLAT Default: 0xb
5885 19:56:42.974468 0, 0xFFFF, sum = 0
5886 19:56:42.978092 1, 0xFFFF, sum = 0
5887 19:56:42.978182 2, 0xFFFF, sum = 0
5888 19:56:42.981129 3, 0xFFFF, sum = 0
5889 19:56:42.981215 4, 0xFFFF, sum = 0
5890 19:56:42.984406 5, 0xFFFF, sum = 0
5891 19:56:42.984490 6, 0xFFFF, sum = 0
5892 19:56:42.987961 7, 0xFFFF, sum = 0
5893 19:56:42.988045 8, 0xFFFF, sum = 0
5894 19:56:42.991044 9, 0xFFFF, sum = 0
5895 19:56:42.991119 10, 0x0, sum = 1
5896 19:56:42.994200 11, 0x0, sum = 2
5897 19:56:42.994273 12, 0x0, sum = 3
5898 19:56:42.997482 13, 0x0, sum = 4
5899 19:56:42.997566 best_step = 11
5900 19:56:42.997632
5901 19:56:42.997693 ==
5902 19:56:43.001290 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 19:56:43.007545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 19:56:43.007697 ==
5905 19:56:43.007768 RX Vref Scan: 0
5906 19:56:43.007832
5907 19:56:43.011339 RX Vref 0 -> 0, step: 1
5908 19:56:43.011421
5909 19:56:43.014237 RX Delay -45 -> 252, step: 4
5910 19:56:43.017910 iDelay=203, Bit 0, Center 108 (23 ~ 194) 172
5911 19:56:43.021083 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5912 19:56:43.027619 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5913 19:56:43.031091 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5914 19:56:43.034315 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5915 19:56:43.037576 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5916 19:56:43.040985 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5917 19:56:43.047411 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5918 19:56:43.051161 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5919 19:56:43.054150 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5920 19:56:43.057728 iDelay=203, Bit 10, Center 98 (15 ~ 182) 168
5921 19:56:43.060585 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5922 19:56:43.067400 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5923 19:56:43.070635 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5924 19:56:43.074161 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5925 19:56:43.077301 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5926 19:56:43.077393 ==
5927 19:56:43.080809 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 19:56:43.083934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 19:56:43.087853 ==
5930 19:56:43.087945 DQS Delay:
5931 19:56:43.088018 DQS0 = 0, DQS1 = 0
5932 19:56:43.091100 DQM Delay:
5933 19:56:43.091183 DQM0 = 105, DQM1 = 99
5934 19:56:43.094219 DQ Delay:
5935 19:56:43.097091 DQ0 =108, DQ1 =102, DQ2 =94, DQ3 =100
5936 19:56:43.100732 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5937 19:56:43.103928 DQ8 =90, DQ9 =88, DQ10 =98, DQ11 =92
5938 19:56:43.107629 DQ12 =108, DQ13 =104, DQ14 =106, DQ15 =108
5939 19:56:43.107774
5940 19:56:43.107851
5941 19:56:43.114182 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5942 19:56:43.117334 CH1 RK1: MR19=505, MR18=2E01
5943 19:56:43.124021 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5944 19:56:43.127161 [RxdqsGatingPostProcess] freq 933
5945 19:56:43.133874 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5946 19:56:43.134013 best DQS0 dly(2T, 0.5T) = (0, 10)
5947 19:56:43.137683 best DQS1 dly(2T, 0.5T) = (0, 10)
5948 19:56:43.140556 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5949 19:56:43.143616 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5950 19:56:43.147328 best DQS0 dly(2T, 0.5T) = (0, 10)
5951 19:56:43.150346 best DQS1 dly(2T, 0.5T) = (0, 10)
5952 19:56:43.153839 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5953 19:56:43.157225 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5954 19:56:43.160282 Pre-setting of DQS Precalculation
5955 19:56:43.167258 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5956 19:56:43.173636 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5957 19:56:43.180188 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5958 19:56:43.180272
5959 19:56:43.180337
5960 19:56:43.183256 [Calibration Summary] 1866 Mbps
5961 19:56:43.183338 CH 0, Rank 0
5962 19:56:43.186759 SW Impedance : PASS
5963 19:56:43.190410 DUTY Scan : NO K
5964 19:56:43.190492 ZQ Calibration : PASS
5965 19:56:43.193469 Jitter Meter : NO K
5966 19:56:43.193561 CBT Training : PASS
5967 19:56:43.196641 Write leveling : PASS
5968 19:56:43.199823 RX DQS gating : PASS
5969 19:56:43.199929 RX DQ/DQS(RDDQC) : PASS
5970 19:56:43.203527 TX DQ/DQS : PASS
5971 19:56:43.206611 RX DATLAT : PASS
5972 19:56:43.206693 RX DQ/DQS(Engine): PASS
5973 19:56:43.210283 TX OE : NO K
5974 19:56:43.210366 All Pass.
5975 19:56:43.210432
5976 19:56:43.213374 CH 0, Rank 1
5977 19:56:43.213455 SW Impedance : PASS
5978 19:56:43.216538 DUTY Scan : NO K
5979 19:56:43.219797 ZQ Calibration : PASS
5980 19:56:43.219879 Jitter Meter : NO K
5981 19:56:43.223514 CBT Training : PASS
5982 19:56:43.226485 Write leveling : PASS
5983 19:56:43.226567 RX DQS gating : PASS
5984 19:56:43.230074 RX DQ/DQS(RDDQC) : PASS
5985 19:56:43.233228 TX DQ/DQS : PASS
5986 19:56:43.233311 RX DATLAT : PASS
5987 19:56:43.236886 RX DQ/DQS(Engine): PASS
5988 19:56:43.240022 TX OE : NO K
5989 19:56:43.240105 All Pass.
5990 19:56:43.240170
5991 19:56:43.240230 CH 1, Rank 0
5992 19:56:43.243779 SW Impedance : PASS
5993 19:56:43.243861 DUTY Scan : NO K
5994 19:56:43.246760 ZQ Calibration : PASS
5995 19:56:43.249783 Jitter Meter : NO K
5996 19:56:43.249866 CBT Training : PASS
5997 19:56:43.253601 Write leveling : PASS
5998 19:56:43.256683 RX DQS gating : PASS
5999 19:56:43.256765 RX DQ/DQS(RDDQC) : PASS
6000 19:56:43.260353 TX DQ/DQS : PASS
6001 19:56:43.263478 RX DATLAT : PASS
6002 19:56:43.263561 RX DQ/DQS(Engine): PASS
6003 19:56:43.266603 TX OE : NO K
6004 19:56:43.266685 All Pass.
6005 19:56:43.266751
6006 19:56:43.269759 CH 1, Rank 1
6007 19:56:43.269841 SW Impedance : PASS
6008 19:56:43.273466 DUTY Scan : NO K
6009 19:56:43.276318 ZQ Calibration : PASS
6010 19:56:43.276401 Jitter Meter : NO K
6011 19:56:43.279767 CBT Training : PASS
6012 19:56:43.283096 Write leveling : PASS
6013 19:56:43.283179 RX DQS gating : PASS
6014 19:56:43.286243 RX DQ/DQS(RDDQC) : PASS
6015 19:56:43.289930 TX DQ/DQS : PASS
6016 19:56:43.290013 RX DATLAT : PASS
6017 19:56:43.293035 RX DQ/DQS(Engine): PASS
6018 19:56:43.293118 TX OE : NO K
6019 19:56:43.296283 All Pass.
6020 19:56:43.296365
6021 19:56:43.296431 DramC Write-DBI off
6022 19:56:43.299686 PER_BANK_REFRESH: Hybrid Mode
6023 19:56:43.303175 TX_TRACKING: ON
6024 19:56:43.310031 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6025 19:56:43.313357 [FAST_K] Save calibration result to emmc
6026 19:56:43.320068 dramc_set_vcore_voltage set vcore to 650000
6027 19:56:43.320151 Read voltage for 400, 6
6028 19:56:43.320217 Vio18 = 0
6029 19:56:43.323216 Vcore = 650000
6030 19:56:43.323299 Vdram = 0
6031 19:56:43.323364 Vddq = 0
6032 19:56:43.326332 Vmddr = 0
6033 19:56:43.330004 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6034 19:56:43.336152 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6035 19:56:43.336237 MEM_TYPE=3, freq_sel=20
6036 19:56:43.339795 sv_algorithm_assistance_LP4_800
6037 19:56:43.346528 ============ PULL DRAM RESETB DOWN ============
6038 19:56:43.349655 ========== PULL DRAM RESETB DOWN end =========
6039 19:56:43.352808 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6040 19:56:43.356650 ===================================
6041 19:56:43.359712 LPDDR4 DRAM CONFIGURATION
6042 19:56:43.362727 ===================================
6043 19:56:43.366480 EX_ROW_EN[0] = 0x0
6044 19:56:43.366563 EX_ROW_EN[1] = 0x0
6045 19:56:43.369602 LP4Y_EN = 0x0
6046 19:56:43.369685 WORK_FSP = 0x0
6047 19:56:43.372774 WL = 0x2
6048 19:56:43.372857 RL = 0x2
6049 19:56:43.376559 BL = 0x2
6050 19:56:43.376642 RPST = 0x0
6051 19:56:43.379661 RD_PRE = 0x0
6052 19:56:43.379758 WR_PRE = 0x1
6053 19:56:43.382736 WR_PST = 0x0
6054 19:56:43.382819 DBI_WR = 0x0
6055 19:56:43.386529 DBI_RD = 0x0
6056 19:56:43.386612 OTF = 0x1
6057 19:56:43.389524 ===================================
6058 19:56:43.392597 ===================================
6059 19:56:43.396231 ANA top config
6060 19:56:43.399410 ===================================
6061 19:56:43.403046 DLL_ASYNC_EN = 0
6062 19:56:43.403129 ALL_SLAVE_EN = 1
6063 19:56:43.406277 NEW_RANK_MODE = 1
6064 19:56:43.409830 DLL_IDLE_MODE = 1
6065 19:56:43.412638 LP45_APHY_COMB_EN = 1
6066 19:56:43.412721 TX_ODT_DIS = 1
6067 19:56:43.415851 NEW_8X_MODE = 1
6068 19:56:43.419359 ===================================
6069 19:56:43.422663 ===================================
6070 19:56:43.425899 data_rate = 800
6071 19:56:43.429395 CKR = 1
6072 19:56:43.432858 DQ_P2S_RATIO = 4
6073 19:56:43.436102 ===================================
6074 19:56:43.439459 CA_P2S_RATIO = 4
6075 19:56:43.439542 DQ_CA_OPEN = 0
6076 19:56:43.442843 DQ_SEMI_OPEN = 1
6077 19:56:43.446206 CA_SEMI_OPEN = 1
6078 19:56:43.449392 CA_FULL_RATE = 0
6079 19:56:43.452453 DQ_CKDIV4_EN = 0
6080 19:56:43.456169 CA_CKDIV4_EN = 1
6081 19:56:43.456258 CA_PREDIV_EN = 0
6082 19:56:43.459308 PH8_DLY = 0
6083 19:56:43.463088 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6084 19:56:43.466145 DQ_AAMCK_DIV = 0
6085 19:56:43.469305 CA_AAMCK_DIV = 0
6086 19:56:43.472486 CA_ADMCK_DIV = 4
6087 19:56:43.472681 DQ_TRACK_CA_EN = 0
6088 19:56:43.476391 CA_PICK = 800
6089 19:56:43.479402 CA_MCKIO = 400
6090 19:56:43.482608 MCKIO_SEMI = 400
6091 19:56:43.486073 PLL_FREQ = 3016
6092 19:56:43.489937 DQ_UI_PI_RATIO = 32
6093 19:56:43.492693 CA_UI_PI_RATIO = 32
6094 19:56:43.495939 ===================================
6095 19:56:43.499581 ===================================
6096 19:56:43.499937 memory_type:LPDDR4
6097 19:56:43.502776 GP_NUM : 10
6098 19:56:43.506632 SRAM_EN : 1
6099 19:56:43.507027 MD32_EN : 0
6100 19:56:43.509897 ===================================
6101 19:56:43.513062 [ANA_INIT] >>>>>>>>>>>>>>
6102 19:56:43.516156 <<<<<< [CONFIGURE PHASE]: ANA_TX
6103 19:56:43.519627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6104 19:56:43.522900 ===================================
6105 19:56:43.526757 data_rate = 800,PCW = 0X7400
6106 19:56:43.527278 ===================================
6107 19:56:43.532795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6108 19:56:43.536097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 19:56:43.549220 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 19:56:43.552855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6111 19:56:43.556336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6112 19:56:43.559444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6113 19:56:43.562588 [ANA_INIT] flow start
6114 19:56:43.562974 [ANA_INIT] PLL >>>>>>>>
6115 19:56:43.565901 [ANA_INIT] PLL <<<<<<<<
6116 19:56:43.569087 [ANA_INIT] MIDPI >>>>>>>>
6117 19:56:43.572539 [ANA_INIT] MIDPI <<<<<<<<
6118 19:56:43.573065 [ANA_INIT] DLL >>>>>>>>
6119 19:56:43.576275 [ANA_INIT] flow end
6120 19:56:43.579158 ============ LP4 DIFF to SE enter ============
6121 19:56:43.582379 ============ LP4 DIFF to SE exit ============
6122 19:56:43.585950 [ANA_INIT] <<<<<<<<<<<<<
6123 19:56:43.589484 [Flow] Enable top DCM control >>>>>
6124 19:56:43.592685 [Flow] Enable top DCM control <<<<<
6125 19:56:43.595691 Enable DLL master slave shuffle
6126 19:56:43.602219 ==============================================================
6127 19:56:43.602731 Gating Mode config
6128 19:56:43.609155 ==============================================================
6129 19:56:43.609666 Config description:
6130 19:56:43.619116 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6131 19:56:43.625793 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6132 19:56:43.632809 SELPH_MODE 0: By rank 1: By Phase
6133 19:56:43.636011 ==============================================================
6134 19:56:43.639091 GAT_TRACK_EN = 0
6135 19:56:43.641834 RX_GATING_MODE = 2
6136 19:56:43.644925 RX_GATING_TRACK_MODE = 2
6137 19:56:43.648175 SELPH_MODE = 1
6138 19:56:43.652119 PICG_EARLY_EN = 1
6139 19:56:43.655362 VALID_LAT_VALUE = 1
6140 19:56:43.658517 ==============================================================
6141 19:56:43.664945 Enter into Gating configuration >>>>
6142 19:56:43.665040 Exit from Gating configuration <<<<
6143 19:56:43.668947 Enter into DVFS_PRE_config >>>>>
6144 19:56:43.682060 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6145 19:56:43.684866 Exit from DVFS_PRE_config <<<<<
6146 19:56:43.688053 Enter into PICG configuration >>>>
6147 19:56:43.691695 Exit from PICG configuration <<<<
6148 19:56:43.691777 [RX_INPUT] configuration >>>>>
6149 19:56:43.694804 [RX_INPUT] configuration <<<<<
6150 19:56:43.701525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6151 19:56:43.704905 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6152 19:56:43.711242 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 19:56:43.718310 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 19:56:43.724742 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6155 19:56:43.731316 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6156 19:56:43.735173 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6157 19:56:43.738387 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6158 19:56:43.741430 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6159 19:56:43.748024 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6160 19:56:43.751229 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6161 19:56:43.755005 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6162 19:56:43.758074 ===================================
6163 19:56:43.761255 LPDDR4 DRAM CONFIGURATION
6164 19:56:43.765013 ===================================
6165 19:56:43.768013 EX_ROW_EN[0] = 0x0
6166 19:56:43.768091 EX_ROW_EN[1] = 0x0
6167 19:56:43.771520 LP4Y_EN = 0x0
6168 19:56:43.771642 WORK_FSP = 0x0
6169 19:56:43.774742 WL = 0x2
6170 19:56:43.774824 RL = 0x2
6171 19:56:43.778073 BL = 0x2
6172 19:56:43.778154 RPST = 0x0
6173 19:56:43.781681 RD_PRE = 0x0
6174 19:56:43.781763 WR_PRE = 0x1
6175 19:56:43.785053 WR_PST = 0x0
6176 19:56:43.785134 DBI_WR = 0x0
6177 19:56:43.788126 DBI_RD = 0x0
6178 19:56:43.788207 OTF = 0x1
6179 19:56:43.791831 ===================================
6180 19:56:43.797975 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6181 19:56:43.801247 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6182 19:56:43.804842 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 19:56:43.807953 ===================================
6184 19:56:43.811488 LPDDR4 DRAM CONFIGURATION
6185 19:56:43.814537 ===================================
6186 19:56:43.814615 EX_ROW_EN[0] = 0x10
6187 19:56:43.818370 EX_ROW_EN[1] = 0x0
6188 19:56:43.821283 LP4Y_EN = 0x0
6189 19:56:43.821366 WORK_FSP = 0x0
6190 19:56:43.824758 WL = 0x2
6191 19:56:43.824832 RL = 0x2
6192 19:56:43.827956 BL = 0x2
6193 19:56:43.828029 RPST = 0x0
6194 19:56:43.831530 RD_PRE = 0x0
6195 19:56:43.831647 WR_PRE = 0x1
6196 19:56:43.834397 WR_PST = 0x0
6197 19:56:43.834477 DBI_WR = 0x0
6198 19:56:43.838158 DBI_RD = 0x0
6199 19:56:43.838236 OTF = 0x1
6200 19:56:43.841174 ===================================
6201 19:56:43.847987 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6202 19:56:43.852000 nWR fixed to 30
6203 19:56:43.855675 [ModeRegInit_LP4] CH0 RK0
6204 19:56:43.855765 [ModeRegInit_LP4] CH0 RK1
6205 19:56:43.859006 [ModeRegInit_LP4] CH1 RK0
6206 19:56:43.862370 [ModeRegInit_LP4] CH1 RK1
6207 19:56:43.862448 match AC timing 19
6208 19:56:43.868722 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6209 19:56:43.872381 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6210 19:56:43.875482 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6211 19:56:43.882465 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6212 19:56:43.885487 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6213 19:56:43.885563 ==
6214 19:56:43.888642 Dram Type= 6, Freq= 0, CH_0, rank 0
6215 19:56:43.892391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 19:56:43.892469 ==
6217 19:56:43.899274 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 19:56:43.905507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6219 19:56:43.908645 [CA 0] Center 36 (8~64) winsize 57
6220 19:56:43.912393 [CA 1] Center 36 (8~64) winsize 57
6221 19:56:43.912470 [CA 2] Center 36 (8~64) winsize 57
6222 19:56:43.915435 [CA 3] Center 36 (8~64) winsize 57
6223 19:56:43.919455 [CA 4] Center 36 (8~64) winsize 57
6224 19:56:43.922419 [CA 5] Center 36 (8~64) winsize 57
6225 19:56:43.922524
6226 19:56:43.925621 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6227 19:56:43.928799
6228 19:56:43.931984 [CATrainingPosCal] consider 1 rank data
6229 19:56:43.932081 u2DelayCellTimex100 = 270/100 ps
6230 19:56:43.938724 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 19:56:43.942289 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 19:56:43.945379 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 19:56:43.949127 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 19:56:43.952266 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 19:56:43.955318 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 19:56:43.955430
6237 19:56:43.958700 CA PerBit enable=1, Macro0, CA PI delay=36
6238 19:56:43.958790
6239 19:56:43.962107 [CBTSetCACLKResult] CA Dly = 36
6240 19:56:43.965369 CS Dly: 1 (0~32)
6241 19:56:43.965470 ==
6242 19:56:43.968761 Dram Type= 6, Freq= 0, CH_0, rank 1
6243 19:56:43.972379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 19:56:43.972486 ==
6245 19:56:43.978968 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 19:56:43.982037 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6247 19:56:43.985143 [CA 0] Center 36 (8~64) winsize 57
6248 19:56:43.988805 [CA 1] Center 36 (8~64) winsize 57
6249 19:56:43.992021 [CA 2] Center 36 (8~64) winsize 57
6250 19:56:43.995076 [CA 3] Center 36 (8~64) winsize 57
6251 19:56:43.998796 [CA 4] Center 36 (8~64) winsize 57
6252 19:56:44.001832 [CA 5] Center 36 (8~64) winsize 57
6253 19:56:44.001943
6254 19:56:44.005551 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6255 19:56:44.005672
6256 19:56:44.008766 [CATrainingPosCal] consider 2 rank data
6257 19:56:44.011805 u2DelayCellTimex100 = 270/100 ps
6258 19:56:44.014968 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 19:56:44.018722 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 19:56:44.021854 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 19:56:44.028591 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 19:56:44.031730 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 19:56:44.034813 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 19:56:44.034886
6265 19:56:44.038629 CA PerBit enable=1, Macro0, CA PI delay=36
6266 19:56:44.038717
6267 19:56:44.041745 [CBTSetCACLKResult] CA Dly = 36
6268 19:56:44.041830 CS Dly: 1 (0~32)
6269 19:56:44.041915
6270 19:56:44.045343 ----->DramcWriteLeveling(PI) begin...
6271 19:56:44.045512 ==
6272 19:56:44.048169 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 19:56:44.054871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 19:56:44.054956 ==
6275 19:56:44.058679 Write leveling (Byte 0): 40 => 8
6276 19:56:44.062002 Write leveling (Byte 1): 40 => 8
6277 19:56:44.062081 DramcWriteLeveling(PI) end<-----
6278 19:56:44.062168
6279 19:56:44.065092 ==
6280 19:56:44.065173 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 19:56:44.072021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 19:56:44.072136 ==
6283 19:56:44.075039 [Gating] SW mode calibration
6284 19:56:44.081742 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6285 19:56:44.085257 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6286 19:56:44.091519 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 19:56:44.094925 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 19:56:44.098313 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 19:56:44.104976 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 19:56:44.108423 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 19:56:44.111602 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 19:56:44.118363 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 19:56:44.121686 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 19:56:44.124980 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 19:56:44.128183 Total UI for P1: 0, mck2ui 16
6296 19:56:44.131608 best dqsien dly found for B0: ( 0, 14, 24)
6297 19:56:44.134750 Total UI for P1: 0, mck2ui 16
6298 19:56:44.138545 best dqsien dly found for B1: ( 0, 14, 24)
6299 19:56:44.141774 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6300 19:56:44.144989 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6301 19:56:44.145061
6302 19:56:44.148230 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 19:56:44.154759 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 19:56:44.154859 [Gating] SW calibration Done
6305 19:56:44.154960 ==
6306 19:56:44.158130 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 19:56:44.165218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 19:56:44.165309 ==
6309 19:56:44.165405 RX Vref Scan: 0
6310 19:56:44.165511
6311 19:56:44.168316 RX Vref 0 -> 0, step: 1
6312 19:56:44.168393
6313 19:56:44.171544 RX Delay -410 -> 252, step: 16
6314 19:56:44.174673 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6315 19:56:44.178434 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6316 19:56:44.184683 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6317 19:56:44.188447 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6318 19:56:44.191513 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6319 19:56:44.194950 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6320 19:56:44.201700 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6321 19:56:44.204745 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6322 19:56:44.207801 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6323 19:56:44.211081 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6324 19:56:44.218054 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6325 19:56:44.221356 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6326 19:56:44.224862 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6327 19:56:44.227950 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6328 19:56:44.234273 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6329 19:56:44.237802 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6330 19:56:44.237911 ==
6331 19:56:44.241399 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 19:56:44.244345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 19:56:44.244428 ==
6334 19:56:44.248007 DQS Delay:
6335 19:56:44.248093 DQS0 = 27, DQS1 = 35
6336 19:56:44.251057 DQM Delay:
6337 19:56:44.251165 DQM0 = 10, DQM1 = 11
6338 19:56:44.251259 DQ Delay:
6339 19:56:44.254237 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6340 19:56:44.257989 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6341 19:56:44.261003 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6342 19:56:44.264456 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6343 19:56:44.264531
6344 19:56:44.264593
6345 19:56:44.264653 ==
6346 19:56:44.268001 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 19:56:44.274279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 19:56:44.274397 ==
6349 19:56:44.274494
6350 19:56:44.274585
6351 19:56:44.274678 TX Vref Scan disable
6352 19:56:44.277474 == TX Byte 0 ==
6353 19:56:44.281192 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 19:56:44.284164 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 19:56:44.287902 == TX Byte 1 ==
6356 19:56:44.291064 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 19:56:44.294218 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 19:56:44.294329 ==
6359 19:56:44.297418 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 19:56:44.304000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 19:56:44.304087 ==
6362 19:56:44.304160
6363 19:56:44.304224
6364 19:56:44.304282 TX Vref Scan disable
6365 19:56:44.307315 == TX Byte 0 ==
6366 19:56:44.310748 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 19:56:44.314102 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 19:56:44.317312 == TX Byte 1 ==
6369 19:56:44.321016 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 19:56:44.324013 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 19:56:44.324089
6372 19:56:44.327569 [DATLAT]
6373 19:56:44.327675 Freq=400, CH0 RK0
6374 19:56:44.327767
6375 19:56:44.330720 DATLAT Default: 0xf
6376 19:56:44.330815 0, 0xFFFF, sum = 0
6377 19:56:44.333797 1, 0xFFFF, sum = 0
6378 19:56:44.333899 2, 0xFFFF, sum = 0
6379 19:56:44.337690 3, 0xFFFF, sum = 0
6380 19:56:44.337763 4, 0xFFFF, sum = 0
6381 19:56:44.340734 5, 0xFFFF, sum = 0
6382 19:56:44.340818 6, 0xFFFF, sum = 0
6383 19:56:44.344368 7, 0xFFFF, sum = 0
6384 19:56:44.344455 8, 0xFFFF, sum = 0
6385 19:56:44.347408 9, 0xFFFF, sum = 0
6386 19:56:44.347520 10, 0xFFFF, sum = 0
6387 19:56:44.350829 11, 0xFFFF, sum = 0
6388 19:56:44.353912 12, 0xFFFF, sum = 0
6389 19:56:44.354019 13, 0x0, sum = 1
6390 19:56:44.354097 14, 0x0, sum = 2
6391 19:56:44.357155 15, 0x0, sum = 3
6392 19:56:44.357275 16, 0x0, sum = 4
6393 19:56:44.361088 best_step = 14
6394 19:56:44.361163
6395 19:56:44.361231 ==
6396 19:56:44.363720 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 19:56:44.367479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 19:56:44.367566 ==
6399 19:56:44.370810 RX Vref Scan: 1
6400 19:56:44.370913
6401 19:56:44.371005 RX Vref 0 -> 0, step: 1
6402 19:56:44.371100
6403 19:56:44.373863 RX Delay -311 -> 252, step: 8
6404 19:56:44.373948
6405 19:56:44.377246 Set Vref, RX VrefLevel [Byte0]: 56
6406 19:56:44.380349 [Byte1]: 48
6407 19:56:44.385276
6408 19:56:44.385357 Final RX Vref Byte 0 = 56 to rank0
6409 19:56:44.388884 Final RX Vref Byte 1 = 48 to rank0
6410 19:56:44.392079 Final RX Vref Byte 0 = 56 to rank1
6411 19:56:44.395337 Final RX Vref Byte 1 = 48 to rank1==
6412 19:56:44.398591 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 19:56:44.405059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 19:56:44.405141 ==
6415 19:56:44.405206 DQS Delay:
6416 19:56:44.408772 DQS0 = 28, DQS1 = 36
6417 19:56:44.408854 DQM Delay:
6418 19:56:44.408920 DQM0 = 11, DQM1 = 13
6419 19:56:44.411946 DQ Delay:
6420 19:56:44.415279 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6421 19:56:44.415361 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6422 19:56:44.418560 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6423 19:56:44.421826 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6424 19:56:44.421908
6425 19:56:44.425253
6426 19:56:44.431432 [DQSOSCAuto] RK0, (LSB)MR18= 0xccb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6427 19:56:44.435243 CH0 RK0: MR19=C0C, MR18=CCB8
6428 19:56:44.441465 CH0_RK0: MR19=0xC0C, MR18=0xCCB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6429 19:56:44.441548 ==
6430 19:56:44.445219 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 19:56:44.448195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 19:56:44.448278 ==
6433 19:56:44.451304 [Gating] SW mode calibration
6434 19:56:44.458294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6435 19:56:44.465101 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6436 19:56:44.468132 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 19:56:44.471884 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 19:56:44.478523 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 19:56:44.481766 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 19:56:44.484679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 19:56:44.491455 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 19:56:44.494745 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 19:56:44.497937 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 19:56:44.501661 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 19:56:44.504947 Total UI for P1: 0, mck2ui 16
6446 19:56:44.508371 best dqsien dly found for B0: ( 0, 14, 24)
6447 19:56:44.512145 Total UI for P1: 0, mck2ui 16
6448 19:56:44.515210 best dqsien dly found for B1: ( 0, 14, 24)
6449 19:56:44.518073 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6450 19:56:44.524982 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6451 19:56:44.525065
6452 19:56:44.528309 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 19:56:44.531879 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 19:56:44.535121 [Gating] SW calibration Done
6455 19:56:44.535203 ==
6456 19:56:44.538341 Dram Type= 6, Freq= 0, CH_0, rank 1
6457 19:56:44.541322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 19:56:44.541405 ==
6459 19:56:44.541470 RX Vref Scan: 0
6460 19:56:44.544790
6461 19:56:44.544872 RX Vref 0 -> 0, step: 1
6462 19:56:44.544937
6463 19:56:44.548124 RX Delay -410 -> 252, step: 16
6464 19:56:44.551178 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6465 19:56:44.557944 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6466 19:56:44.561130 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6467 19:56:44.564899 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6468 19:56:44.567939 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6469 19:56:44.574736 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6470 19:56:44.577779 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6471 19:56:44.581067 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6472 19:56:44.584760 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6473 19:56:44.591460 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6474 19:56:44.594628 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6475 19:56:44.597780 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6476 19:56:44.601251 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6477 19:56:44.608123 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6478 19:56:44.611033 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6479 19:56:44.614510 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6480 19:56:44.614593 ==
6481 19:56:44.617699 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 19:56:44.624385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 19:56:44.624495 ==
6484 19:56:44.624590 DQS Delay:
6485 19:56:44.627541 DQS0 = 19, DQS1 = 35
6486 19:56:44.627657 DQM Delay:
6487 19:56:44.627737 DQM0 = 3, DQM1 = 11
6488 19:56:44.631295 DQ Delay:
6489 19:56:44.634322 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6490 19:56:44.634406 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =8
6491 19:56:44.638064 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6492 19:56:44.641008 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6493 19:56:44.641091
6494 19:56:44.641155
6495 19:56:44.644491 ==
6496 19:56:44.644573 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 19:56:44.650830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 19:56:44.650913 ==
6499 19:56:44.650978
6500 19:56:44.651037
6501 19:56:44.651094 TX Vref Scan disable
6502 19:56:44.654173 == TX Byte 0 ==
6503 19:56:44.657672 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6504 19:56:44.660813 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6505 19:56:44.664176 == TX Byte 1 ==
6506 19:56:44.668025 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6507 19:56:44.671169 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6508 19:56:44.674246 ==
6509 19:56:44.674329 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 19:56:44.681335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 19:56:44.681419 ==
6512 19:56:44.681485
6513 19:56:44.681544
6514 19:56:44.684346 TX Vref Scan disable
6515 19:56:44.684428 == TX Byte 0 ==
6516 19:56:44.687533 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6517 19:56:44.693828 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6518 19:56:44.693914 == TX Byte 1 ==
6519 19:56:44.697453 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6520 19:56:44.700587 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6521 19:56:44.704540
6522 19:56:44.704622 [DATLAT]
6523 19:56:44.704687 Freq=400, CH0 RK1
6524 19:56:44.704749
6525 19:56:44.707617 DATLAT Default: 0xe
6526 19:56:44.707736 0, 0xFFFF, sum = 0
6527 19:56:44.710738 1, 0xFFFF, sum = 0
6528 19:56:44.710822 2, 0xFFFF, sum = 0
6529 19:56:44.713912 3, 0xFFFF, sum = 0
6530 19:56:44.713996 4, 0xFFFF, sum = 0
6531 19:56:44.717691 5, 0xFFFF, sum = 0
6532 19:56:44.717775 6, 0xFFFF, sum = 0
6533 19:56:44.720665 7, 0xFFFF, sum = 0
6534 19:56:44.724584 8, 0xFFFF, sum = 0
6535 19:56:44.724668 9, 0xFFFF, sum = 0
6536 19:56:44.727594 10, 0xFFFF, sum = 0
6537 19:56:44.727698 11, 0xFFFF, sum = 0
6538 19:56:44.730660 12, 0xFFFF, sum = 0
6539 19:56:44.730760 13, 0x0, sum = 1
6540 19:56:44.733769 14, 0x0, sum = 2
6541 19:56:44.733852 15, 0x0, sum = 3
6542 19:56:44.737068 16, 0x0, sum = 4
6543 19:56:44.737152 best_step = 14
6544 19:56:44.737217
6545 19:56:44.737278 ==
6546 19:56:44.740366 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 19:56:44.743807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 19:56:44.743891 ==
6549 19:56:44.747506 RX Vref Scan: 0
6550 19:56:44.747587
6551 19:56:44.750291 RX Vref 0 -> 0, step: 1
6552 19:56:44.750396
6553 19:56:44.750491 RX Delay -311 -> 252, step: 8
6554 19:56:44.758964 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6555 19:56:44.762700 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6556 19:56:44.765960 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6557 19:56:44.769508 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6558 19:56:44.775677 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6559 19:56:44.778822 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6560 19:56:44.782655 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6561 19:56:44.785751 iDelay=217, Bit 7, Center -4 (-223 ~ 216) 440
6562 19:56:44.793081 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6563 19:56:44.796230 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6564 19:56:44.799273 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6565 19:56:44.802833 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6566 19:56:44.809640 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6567 19:56:44.812785 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6568 19:56:44.815758 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6569 19:56:44.822912 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6570 19:56:44.823351 ==
6571 19:56:44.826099 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 19:56:44.829260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 19:56:44.829686 ==
6574 19:56:44.830023 DQS Delay:
6575 19:56:44.832386 DQS0 = 24, DQS1 = 32
6576 19:56:44.832809 DQM Delay:
6577 19:56:44.836037 DQM0 = 8, DQM1 = 10
6578 19:56:44.836477 DQ Delay:
6579 19:56:44.839574 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6580 19:56:44.842850 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =20
6581 19:56:44.845621 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6582 19:56:44.849562 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6583 19:56:44.849986
6584 19:56:44.850408
6585 19:56:44.856116 [DQSOSCAuto] RK1, (LSB)MR18= 0xb959, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6586 19:56:44.859700 CH0 RK1: MR19=C0C, MR18=B959
6587 19:56:44.865933 CH0_RK1: MR19=0xC0C, MR18=0xB959, DQSOSC=386, MR23=63, INC=396, DEC=264
6588 19:56:44.869063 [RxdqsGatingPostProcess] freq 400
6589 19:56:44.872556 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6590 19:56:44.875876 best DQS0 dly(2T, 0.5T) = (0, 10)
6591 19:56:44.879004 best DQS1 dly(2T, 0.5T) = (0, 10)
6592 19:56:44.882428 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6593 19:56:44.885461 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6594 19:56:44.888932 best DQS0 dly(2T, 0.5T) = (0, 10)
6595 19:56:44.892150 best DQS1 dly(2T, 0.5T) = (0, 10)
6596 19:56:44.895442 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6597 19:56:44.899063 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6598 19:56:44.902263 Pre-setting of DQS Precalculation
6599 19:56:44.905470 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6600 19:56:44.909007 ==
6601 19:56:44.912032 Dram Type= 6, Freq= 0, CH_1, rank 0
6602 19:56:44.915747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 19:56:44.916176 ==
6604 19:56:44.918895 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 19:56:44.925075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6606 19:56:44.928446 [CA 0] Center 36 (8~64) winsize 57
6607 19:56:44.932172 [CA 1] Center 36 (8~64) winsize 57
6608 19:56:44.935390 [CA 2] Center 36 (8~64) winsize 57
6609 19:56:44.938436 [CA 3] Center 36 (8~64) winsize 57
6610 19:56:44.942325 [CA 4] Center 36 (8~64) winsize 57
6611 19:56:44.945470 [CA 5] Center 36 (8~64) winsize 57
6612 19:56:44.946044
6613 19:56:44.948165 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6614 19:56:44.948246
6615 19:56:44.951543 [CATrainingPosCal] consider 1 rank data
6616 19:56:44.954891 u2DelayCellTimex100 = 270/100 ps
6617 19:56:44.957901 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 19:56:44.961549 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 19:56:44.964750 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 19:56:44.968477 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 19:56:44.975197 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 19:56:44.978111 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 19:56:44.978194
6624 19:56:44.981526 CA PerBit enable=1, Macro0, CA PI delay=36
6625 19:56:44.981607
6626 19:56:44.985333 [CBTSetCACLKResult] CA Dly = 36
6627 19:56:44.985414 CS Dly: 1 (0~32)
6628 19:56:44.985480 ==
6629 19:56:44.988349 Dram Type= 6, Freq= 0, CH_1, rank 1
6630 19:56:44.991743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 19:56:44.994940 ==
6632 19:56:44.998175 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 19:56:45.004717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6634 19:56:45.008235 [CA 0] Center 36 (8~64) winsize 57
6635 19:56:45.011164 [CA 1] Center 36 (8~64) winsize 57
6636 19:56:45.014877 [CA 2] Center 36 (8~64) winsize 57
6637 19:56:45.017890 [CA 3] Center 36 (8~64) winsize 57
6638 19:56:45.021305 [CA 4] Center 36 (8~64) winsize 57
6639 19:56:45.024482 [CA 5] Center 36 (8~64) winsize 57
6640 19:56:45.024582
6641 19:56:45.028113 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6642 19:56:45.028196
6643 19:56:45.031294 [CATrainingPosCal] consider 2 rank data
6644 19:56:45.034391 u2DelayCellTimex100 = 270/100 ps
6645 19:56:45.038139 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 19:56:45.041314 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 19:56:45.044448 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 19:56:45.047716 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 19:56:45.051544 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 19:56:45.054752 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 19:56:45.054855
6652 19:56:45.061059 CA PerBit enable=1, Macro0, CA PI delay=36
6653 19:56:45.061156
6654 19:56:45.061240 [CBTSetCACLKResult] CA Dly = 36
6655 19:56:45.064450 CS Dly: 1 (0~32)
6656 19:56:45.064534
6657 19:56:45.067650 ----->DramcWriteLeveling(PI) begin...
6658 19:56:45.067736 ==
6659 19:56:45.070845 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 19:56:45.074495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 19:56:45.074576 ==
6662 19:56:45.077732 Write leveling (Byte 0): 40 => 8
6663 19:56:45.080832 Write leveling (Byte 1): 40 => 8
6664 19:56:45.084518 DramcWriteLeveling(PI) end<-----
6665 19:56:45.084603
6666 19:56:45.084697 ==
6667 19:56:45.087851 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 19:56:45.090471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 19:56:45.093822 ==
6670 19:56:45.093906 [Gating] SW mode calibration
6671 19:56:45.103778 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6672 19:56:45.107986 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6673 19:56:45.111095 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 19:56:45.117380 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6675 19:56:45.121232 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 19:56:45.124286 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 19:56:45.130420 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 19:56:45.133746 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 19:56:45.137427 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 19:56:45.143853 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 19:56:45.147168 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 19:56:45.150539 Total UI for P1: 0, mck2ui 16
6683 19:56:45.154015 best dqsien dly found for B0: ( 0, 14, 24)
6684 19:56:45.156976 Total UI for P1: 0, mck2ui 16
6685 19:56:45.160116 best dqsien dly found for B1: ( 0, 14, 24)
6686 19:56:45.163799 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6687 19:56:45.166721 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6688 19:56:45.167186
6689 19:56:45.170891 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 19:56:45.176876 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 19:56:45.177431 [Gating] SW calibration Done
6692 19:56:45.177996 ==
6693 19:56:45.180578 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 19:56:45.186870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 19:56:45.187301 ==
6696 19:56:45.187705 RX Vref Scan: 0
6697 19:56:45.188030
6698 19:56:45.189958 RX Vref 0 -> 0, step: 1
6699 19:56:45.190373
6700 19:56:45.193250 RX Delay -410 -> 252, step: 16
6701 19:56:45.196870 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6702 19:56:45.199912 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6703 19:56:45.206420 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6704 19:56:45.209876 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6705 19:56:45.212976 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6706 19:56:45.216810 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6707 19:56:45.222843 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6708 19:56:45.226042 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6709 19:56:45.229921 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6710 19:56:45.233227 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6711 19:56:45.239508 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6712 19:56:45.242596 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6713 19:56:45.245993 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6714 19:56:45.252261 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6715 19:56:45.255814 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6716 19:56:45.258644 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6717 19:56:45.258746 ==
6718 19:56:45.262349 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 19:56:45.265564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 19:56:45.269000 ==
6721 19:56:45.269085 DQS Delay:
6722 19:56:45.269170 DQS0 = 27, DQS1 = 27
6723 19:56:45.272031 DQM Delay:
6724 19:56:45.272115 DQM0 = 11, DQM1 = 8
6725 19:56:45.275663 DQ Delay:
6726 19:56:45.275763 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6727 19:56:45.278869 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6728 19:56:45.282155 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6729 19:56:45.285704 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6730 19:56:45.285785
6731 19:56:45.285868
6732 19:56:45.285950 ==
6733 19:56:45.288611 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 19:56:45.295261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 19:56:45.295341 ==
6736 19:56:45.295444
6737 19:56:45.295564
6738 19:56:45.295683 TX Vref Scan disable
6739 19:56:45.298914 == TX Byte 0 ==
6740 19:56:45.301998 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 19:56:45.305146 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 19:56:45.308702 == TX Byte 1 ==
6743 19:56:45.311581 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 19:56:45.315251 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 19:56:45.315354 ==
6746 19:56:45.318640 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 19:56:45.325424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 19:56:45.325508 ==
6749 19:56:45.325595
6750 19:56:45.325675
6751 19:56:45.325754 TX Vref Scan disable
6752 19:56:45.328563 == TX Byte 0 ==
6753 19:56:45.331621 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 19:56:45.335412 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 19:56:45.338618 == TX Byte 1 ==
6756 19:56:45.341774 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 19:56:45.344899 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 19:56:45.344975
6759 19:56:45.348055 [DATLAT]
6760 19:56:45.348165 Freq=400, CH1 RK0
6761 19:56:45.348252
6762 19:56:45.351769 DATLAT Default: 0xf
6763 19:56:45.351908 0, 0xFFFF, sum = 0
6764 19:56:45.354888 1, 0xFFFF, sum = 0
6765 19:56:45.354976 2, 0xFFFF, sum = 0
6766 19:56:45.358072 3, 0xFFFF, sum = 0
6767 19:56:45.358179 4, 0xFFFF, sum = 0
6768 19:56:45.361317 5, 0xFFFF, sum = 0
6769 19:56:45.361416 6, 0xFFFF, sum = 0
6770 19:56:45.365112 7, 0xFFFF, sum = 0
6771 19:56:45.368305 8, 0xFFFF, sum = 0
6772 19:56:45.368376 9, 0xFFFF, sum = 0
6773 19:56:45.371377 10, 0xFFFF, sum = 0
6774 19:56:45.371445 11, 0xFFFF, sum = 0
6775 19:56:45.374882 12, 0xFFFF, sum = 0
6776 19:56:45.374953 13, 0x0, sum = 1
6777 19:56:45.378096 14, 0x0, sum = 2
6778 19:56:45.378167 15, 0x0, sum = 3
6779 19:56:45.381531 16, 0x0, sum = 4
6780 19:56:45.381600 best_step = 14
6781 19:56:45.381659
6782 19:56:45.381715 ==
6783 19:56:45.384940 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 19:56:45.388380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 19:56:45.388454 ==
6786 19:56:45.391287 RX Vref Scan: 1
6787 19:56:45.391365
6788 19:56:45.394841 RX Vref 0 -> 0, step: 1
6789 19:56:45.394909
6790 19:56:45.394969 RX Delay -295 -> 252, step: 8
6791 19:56:45.395026
6792 19:56:45.398308 Set Vref, RX VrefLevel [Byte0]: 56
6793 19:56:45.401412 [Byte1]: 48
6794 19:56:45.406591
6795 19:56:45.406672 Final RX Vref Byte 0 = 56 to rank0
6796 19:56:45.410020 Final RX Vref Byte 1 = 48 to rank0
6797 19:56:45.413262 Final RX Vref Byte 0 = 56 to rank1
6798 19:56:45.416639 Final RX Vref Byte 1 = 48 to rank1==
6799 19:56:45.420239 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 19:56:45.423066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 19:56:45.426653 ==
6802 19:56:45.426730 DQS Delay:
6803 19:56:45.426793 DQS0 = 28, DQS1 = 32
6804 19:56:45.430047 DQM Delay:
6805 19:56:45.430129 DQM0 = 9, DQM1 = 11
6806 19:56:45.433327 DQ Delay:
6807 19:56:45.433408 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6808 19:56:45.436570 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6809 19:56:45.439747 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6810 19:56:45.442996 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6811 19:56:45.443067
6812 19:56:45.443128
6813 19:56:45.453049 [DQSOSCAuto] RK0, (LSB)MR18= 0x95cd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6814 19:56:45.456710 CH1 RK0: MR19=C0C, MR18=95CD
6815 19:56:45.460033 CH1_RK0: MR19=0xC0C, MR18=0x95CD, DQSOSC=384, MR23=63, INC=400, DEC=267
6816 19:56:45.463105 ==
6817 19:56:45.466779 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 19:56:45.469933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 19:56:45.470008 ==
6820 19:56:45.473056 [Gating] SW mode calibration
6821 19:56:45.479928 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6822 19:56:45.483071 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6823 19:56:45.489762 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 19:56:45.492810 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6825 19:56:45.496253 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 19:56:45.503085 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 19:56:45.506328 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 19:56:45.509937 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 19:56:45.516377 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 19:56:45.519426 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 19:56:45.522741 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 19:56:45.526488 Total UI for P1: 0, mck2ui 16
6833 19:56:45.529125 best dqsien dly found for B0: ( 0, 14, 24)
6834 19:56:45.532809 Total UI for P1: 0, mck2ui 16
6835 19:56:45.535970 best dqsien dly found for B1: ( 0, 14, 24)
6836 19:56:45.539427 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6837 19:56:45.542520 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6838 19:56:45.546064
6839 19:56:45.549485 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 19:56:45.552555 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 19:56:45.555910 [Gating] SW calibration Done
6842 19:56:45.556019 ==
6843 19:56:45.559274 Dram Type= 6, Freq= 0, CH_1, rank 1
6844 19:56:45.562447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 19:56:45.562529 ==
6846 19:56:45.562594 RX Vref Scan: 0
6847 19:56:45.565633
6848 19:56:45.565714 RX Vref 0 -> 0, step: 1
6849 19:56:45.565779
6850 19:56:45.568817 RX Delay -410 -> 252, step: 16
6851 19:56:45.572595 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6852 19:56:45.578897 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6853 19:56:45.582016 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6854 19:56:45.585747 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6855 19:56:45.589033 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6856 19:56:45.595184 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6857 19:56:45.599006 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6858 19:56:45.601912 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6859 19:56:45.605400 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6860 19:56:45.611815 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6861 19:56:45.615439 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6862 19:56:45.618463 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6863 19:56:45.622133 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6864 19:56:45.628240 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6865 19:56:45.632098 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6866 19:56:45.635194 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6867 19:56:45.635278 ==
6868 19:56:45.638752 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 19:56:45.645207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 19:56:45.645292 ==
6871 19:56:45.645378 DQS Delay:
6872 19:56:45.648734 DQS0 = 35, DQS1 = 35
6873 19:56:45.648822 DQM Delay:
6874 19:56:45.648911 DQM0 = 19, DQM1 = 13
6875 19:56:45.651787 DQ Delay:
6876 19:56:45.655267 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6877 19:56:45.658413 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6878 19:56:45.658499 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6879 19:56:45.664791 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6880 19:56:45.664878
6881 19:56:45.664964
6882 19:56:45.665049 ==
6883 19:56:45.668087 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 19:56:45.671530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 19:56:45.671620 ==
6886 19:56:45.671746
6887 19:56:45.671830
6888 19:56:45.675220 TX Vref Scan disable
6889 19:56:45.675341 == TX Byte 0 ==
6890 19:56:45.678522 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6891 19:56:45.685232 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6892 19:56:45.685310 == TX Byte 1 ==
6893 19:56:45.688210 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6894 19:56:45.695244 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6895 19:56:45.695334 ==
6896 19:56:45.698298 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 19:56:45.701389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 19:56:45.701466 ==
6899 19:56:45.701565
6900 19:56:45.701662
6901 19:56:45.705094 TX Vref Scan disable
6902 19:56:45.705171 == TX Byte 0 ==
6903 19:56:45.708082 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6904 19:56:45.714616 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6905 19:56:45.714701 == TX Byte 1 ==
6906 19:56:45.718329 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6907 19:56:45.725046 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6908 19:56:45.725134
6909 19:56:45.725221 [DATLAT]
6910 19:56:45.725305 Freq=400, CH1 RK1
6911 19:56:45.728197
6912 19:56:45.728272 DATLAT Default: 0xe
6913 19:56:45.731176 0, 0xFFFF, sum = 0
6914 19:56:45.731254 1, 0xFFFF, sum = 0
6915 19:56:45.734771 2, 0xFFFF, sum = 0
6916 19:56:45.734846 3, 0xFFFF, sum = 0
6917 19:56:45.738084 4, 0xFFFF, sum = 0
6918 19:56:45.738178 5, 0xFFFF, sum = 0
6919 19:56:45.741830 6, 0xFFFF, sum = 0
6920 19:56:45.741922 7, 0xFFFF, sum = 0
6921 19:56:45.744892 8, 0xFFFF, sum = 0
6922 19:56:45.744993 9, 0xFFFF, sum = 0
6923 19:56:45.747823 10, 0xFFFF, sum = 0
6924 19:56:45.747929 11, 0xFFFF, sum = 0
6925 19:56:45.751547 12, 0xFFFF, sum = 0
6926 19:56:45.751666 13, 0x0, sum = 1
6927 19:56:45.755103 14, 0x0, sum = 2
6928 19:56:45.755224 15, 0x0, sum = 3
6929 19:56:45.758198 16, 0x0, sum = 4
6930 19:56:45.758325 best_step = 14
6931 19:56:45.758452
6932 19:56:45.758571 ==
6933 19:56:45.761493 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 19:56:45.767558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 19:56:45.767634 ==
6936 19:56:45.767770 RX Vref Scan: 0
6937 19:56:45.767835
6938 19:56:45.771001 RX Vref 0 -> 0, step: 1
6939 19:56:45.771071
6940 19:56:45.774600 RX Delay -311 -> 252, step: 8
6941 19:56:45.781174 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6942 19:56:45.784806 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6943 19:56:45.787600 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6944 19:56:45.791232 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6945 19:56:45.798100 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6946 19:56:45.801211 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6947 19:56:45.804368 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6948 19:56:45.808255 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6949 19:56:45.814938 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6950 19:56:45.817492 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6951 19:56:45.820929 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6952 19:56:45.824596 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6953 19:56:45.830870 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6954 19:56:45.834558 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6955 19:56:45.837606 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6956 19:56:45.841332 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6957 19:56:45.841414 ==
6958 19:56:45.844952 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 19:56:45.851137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 19:56:45.851559 ==
6961 19:56:45.852032 DQS Delay:
6962 19:56:45.854782 DQS0 = 28, DQS1 = 36
6963 19:56:45.855200 DQM Delay:
6964 19:56:45.857801 DQM0 = 10, DQM1 = 15
6965 19:56:45.858300 DQ Delay:
6966 19:56:45.861972 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6967 19:56:45.864749 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6968 19:56:45.867876 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6969 19:56:45.871177 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6970 19:56:45.871596
6971 19:56:45.871990
6972 19:56:45.878098 [DQSOSCAuto] RK1, (LSB)MR18= 0xcb5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
6973 19:56:45.881132 CH1 RK1: MR19=C0C, MR18=CB5C
6974 19:56:45.888110 CH1_RK1: MR19=0xC0C, MR18=0xCB5C, DQSOSC=384, MR23=63, INC=400, DEC=267
6975 19:56:45.891570 [RxdqsGatingPostProcess] freq 400
6976 19:56:45.894646 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6977 19:56:45.897734 best DQS0 dly(2T, 0.5T) = (0, 10)
6978 19:56:45.901471 best DQS1 dly(2T, 0.5T) = (0, 10)
6979 19:56:45.904787 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6980 19:56:45.908168 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6981 19:56:45.911496 best DQS0 dly(2T, 0.5T) = (0, 10)
6982 19:56:45.914541 best DQS1 dly(2T, 0.5T) = (0, 10)
6983 19:56:45.918179 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6984 19:56:45.921295 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6985 19:56:45.924530 Pre-setting of DQS Precalculation
6986 19:56:45.928239 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6987 19:56:45.934444 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6988 19:56:45.944264 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6989 19:56:45.944700
6990 19:56:45.945167
6991 19:56:45.948075 [Calibration Summary] 800 Mbps
6992 19:56:45.948508 CH 0, Rank 0
6993 19:56:45.951073 SW Impedance : PASS
6994 19:56:45.951506 DUTY Scan : NO K
6995 19:56:45.954749 ZQ Calibration : PASS
6996 19:56:45.957727 Jitter Meter : NO K
6997 19:56:45.958156 CBT Training : PASS
6998 19:56:45.961637 Write leveling : PASS
6999 19:56:45.962069 RX DQS gating : PASS
7000 19:56:45.964604 RX DQ/DQS(RDDQC) : PASS
7001 19:56:45.968120 TX DQ/DQS : PASS
7002 19:56:45.968602 RX DATLAT : PASS
7003 19:56:45.971339 RX DQ/DQS(Engine): PASS
7004 19:56:45.974519 TX OE : NO K
7005 19:56:45.974960 All Pass.
7006 19:56:45.975404
7007 19:56:45.975977 CH 0, Rank 1
7008 19:56:45.978227 SW Impedance : PASS
7009 19:56:45.981422 DUTY Scan : NO K
7010 19:56:45.981896 ZQ Calibration : PASS
7011 19:56:45.984456 Jitter Meter : NO K
7012 19:56:45.988003 CBT Training : PASS
7013 19:56:45.988681 Write leveling : NO K
7014 19:56:45.991227 RX DQS gating : PASS
7015 19:56:45.994186 RX DQ/DQS(RDDQC) : PASS
7016 19:56:45.994654 TX DQ/DQS : PASS
7017 19:56:45.998040 RX DATLAT : PASS
7018 19:56:45.998518 RX DQ/DQS(Engine): PASS
7019 19:56:46.001241 TX OE : NO K
7020 19:56:46.001740 All Pass.
7021 19:56:46.002223
7022 19:56:46.004202 CH 1, Rank 0
7023 19:56:46.004690 SW Impedance : PASS
7024 19:56:46.007755 DUTY Scan : NO K
7025 19:56:46.011169 ZQ Calibration : PASS
7026 19:56:46.011679 Jitter Meter : NO K
7027 19:56:46.014381 CBT Training : PASS
7028 19:56:46.017825 Write leveling : PASS
7029 19:56:46.018257 RX DQS gating : PASS
7030 19:56:46.021261 RX DQ/DQS(RDDQC) : PASS
7031 19:56:46.024499 TX DQ/DQS : PASS
7032 19:56:46.024965 RX DATLAT : PASS
7033 19:56:46.027733 RX DQ/DQS(Engine): PASS
7034 19:56:46.030824 TX OE : NO K
7035 19:56:46.031252 All Pass.
7036 19:56:46.031555
7037 19:56:46.031684 CH 1, Rank 1
7038 19:56:46.033880 SW Impedance : PASS
7039 19:56:46.037290 DUTY Scan : NO K
7040 19:56:46.037377 ZQ Calibration : PASS
7041 19:56:46.040552 Jitter Meter : NO K
7042 19:56:46.044271 CBT Training : PASS
7043 19:56:46.044356 Write leveling : NO K
7044 19:56:46.047107 RX DQS gating : PASS
7045 19:56:46.047190 RX DQ/DQS(RDDQC) : PASS
7046 19:56:46.050881 TX DQ/DQS : PASS
7047 19:56:46.053966 RX DATLAT : PASS
7048 19:56:46.054056 RX DQ/DQS(Engine): PASS
7049 19:56:46.057291 TX OE : NO K
7050 19:56:46.057375 All Pass.
7051 19:56:46.057460
7052 19:56:46.060919 DramC Write-DBI off
7053 19:56:46.064162 PER_BANK_REFRESH: Hybrid Mode
7054 19:56:46.064252 TX_TRACKING: ON
7055 19:56:46.073763 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7056 19:56:46.077741 [FAST_K] Save calibration result to emmc
7057 19:56:46.081033 dramc_set_vcore_voltage set vcore to 725000
7058 19:56:46.084323 Read voltage for 1600, 0
7059 19:56:46.084444 Vio18 = 0
7060 19:56:46.084542 Vcore = 725000
7061 19:56:46.087930 Vdram = 0
7062 19:56:46.088348 Vddq = 0
7063 19:56:46.088685 Vmddr = 0
7064 19:56:46.094148 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7065 19:56:46.097207 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7066 19:56:46.100472 MEM_TYPE=3, freq_sel=13
7067 19:56:46.104701 sv_algorithm_assistance_LP4_3733
7068 19:56:46.107741 ============ PULL DRAM RESETB DOWN ============
7069 19:56:46.114528 ========== PULL DRAM RESETB DOWN end =========
7070 19:56:46.117739 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7071 19:56:46.120865 ===================================
7072 19:56:46.123914 LPDDR4 DRAM CONFIGURATION
7073 19:56:46.127153 ===================================
7074 19:56:46.127234 EX_ROW_EN[0] = 0x0
7075 19:56:46.130507 EX_ROW_EN[1] = 0x0
7076 19:56:46.130588 LP4Y_EN = 0x0
7077 19:56:46.133975 WORK_FSP = 0x1
7078 19:56:46.134056 WL = 0x5
7079 19:56:46.136990 RL = 0x5
7080 19:56:46.137071 BL = 0x2
7081 19:56:46.140326 RPST = 0x0
7082 19:56:46.140407 RD_PRE = 0x0
7083 19:56:46.143601 WR_PRE = 0x1
7084 19:56:46.143688 WR_PST = 0x1
7085 19:56:46.146990 DBI_WR = 0x0
7086 19:56:46.147071 DBI_RD = 0x0
7087 19:56:46.150449 OTF = 0x1
7088 19:56:46.153758 ===================================
7089 19:56:46.156909 ===================================
7090 19:56:46.156982 ANA top config
7091 19:56:46.160416 ===================================
7092 19:56:46.163604 DLL_ASYNC_EN = 0
7093 19:56:46.166940 ALL_SLAVE_EN = 0
7094 19:56:46.170726 NEW_RANK_MODE = 1
7095 19:56:46.170841 DLL_IDLE_MODE = 1
7096 19:56:46.173861 LP45_APHY_COMB_EN = 1
7097 19:56:46.177040 TX_ODT_DIS = 0
7098 19:56:46.180531 NEW_8X_MODE = 1
7099 19:56:46.183663 ===================================
7100 19:56:46.186837 ===================================
7101 19:56:46.190056 data_rate = 3200
7102 19:56:46.193759 CKR = 1
7103 19:56:46.193841 DQ_P2S_RATIO = 8
7104 19:56:46.196989 ===================================
7105 19:56:46.200238 CA_P2S_RATIO = 8
7106 19:56:46.203743 DQ_CA_OPEN = 0
7107 19:56:46.206882 DQ_SEMI_OPEN = 0
7108 19:56:46.209975 CA_SEMI_OPEN = 0
7109 19:56:46.213786 CA_FULL_RATE = 0
7110 19:56:46.213891 DQ_CKDIV4_EN = 0
7111 19:56:46.216740 CA_CKDIV4_EN = 0
7112 19:56:46.220588 CA_PREDIV_EN = 0
7113 19:56:46.223518 PH8_DLY = 12
7114 19:56:46.226693 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7115 19:56:46.226767 DQ_AAMCK_DIV = 4
7116 19:56:46.229893 CA_AAMCK_DIV = 4
7117 19:56:46.233739 CA_ADMCK_DIV = 4
7118 19:56:46.236780 DQ_TRACK_CA_EN = 0
7119 19:56:46.240211 CA_PICK = 1600
7120 19:56:46.243782 CA_MCKIO = 1600
7121 19:56:46.246794 MCKIO_SEMI = 0
7122 19:56:46.250233 PLL_FREQ = 3068
7123 19:56:46.250329 DQ_UI_PI_RATIO = 32
7124 19:56:46.253335 CA_UI_PI_RATIO = 0
7125 19:56:46.256869 ===================================
7126 19:56:46.260316 ===================================
7127 19:56:46.263262 memory_type:LPDDR4
7128 19:56:46.266646 GP_NUM : 10
7129 19:56:46.266729 SRAM_EN : 1
7130 19:56:46.270162 MD32_EN : 0
7131 19:56:46.273376 ===================================
7132 19:56:46.273459 [ANA_INIT] >>>>>>>>>>>>>>
7133 19:56:46.276599 <<<<<< [CONFIGURE PHASE]: ANA_TX
7134 19:56:46.280192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7135 19:56:46.283304 ===================================
7136 19:56:46.286956 data_rate = 3200,PCW = 0X7600
7137 19:56:46.289833 ===================================
7138 19:56:46.293233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7139 19:56:46.299944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 19:56:46.306936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 19:56:46.310035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7142 19:56:46.313132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7143 19:56:46.316284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7144 19:56:46.319855 [ANA_INIT] flow start
7145 19:56:46.319937 [ANA_INIT] PLL >>>>>>>>
7146 19:56:46.323076 [ANA_INIT] PLL <<<<<<<<
7147 19:56:46.326214 [ANA_INIT] MIDPI >>>>>>>>
7148 19:56:46.326297 [ANA_INIT] MIDPI <<<<<<<<
7149 19:56:46.330042 [ANA_INIT] DLL >>>>>>>>
7150 19:56:46.333136 [ANA_INIT] DLL <<<<<<<<
7151 19:56:46.333219 [ANA_INIT] flow end
7152 19:56:46.340245 ============ LP4 DIFF to SE enter ============
7153 19:56:46.343268 ============ LP4 DIFF to SE exit ============
7154 19:56:46.343350 [ANA_INIT] <<<<<<<<<<<<<
7155 19:56:46.346714 [Flow] Enable top DCM control >>>>>
7156 19:56:46.349673 [Flow] Enable top DCM control <<<<<
7157 19:56:46.353119 Enable DLL master slave shuffle
7158 19:56:46.359539 ==============================================================
7159 19:56:46.363170 Gating Mode config
7160 19:56:46.366328 ==============================================================
7161 19:56:46.370038 Config description:
7162 19:56:46.379593 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7163 19:56:46.386222 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7164 19:56:46.389551 SELPH_MODE 0: By rank 1: By Phase
7165 19:56:46.396172 ==============================================================
7166 19:56:46.399276 GAT_TRACK_EN = 1
7167 19:56:46.402812 RX_GATING_MODE = 2
7168 19:56:46.406226 RX_GATING_TRACK_MODE = 2
7169 19:56:46.406309 SELPH_MODE = 1
7170 19:56:46.409528 PICG_EARLY_EN = 1
7171 19:56:46.412530 VALID_LAT_VALUE = 1
7172 19:56:46.419393 ==============================================================
7173 19:56:46.422451 Enter into Gating configuration >>>>
7174 19:56:46.426283 Exit from Gating configuration <<<<
7175 19:56:46.429408 Enter into DVFS_PRE_config >>>>>
7176 19:56:46.439370 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7177 19:56:46.442583 Exit from DVFS_PRE_config <<<<<
7178 19:56:46.445756 Enter into PICG configuration >>>>
7179 19:56:46.448842 Exit from PICG configuration <<<<
7180 19:56:46.452500 [RX_INPUT] configuration >>>>>
7181 19:56:46.455668 [RX_INPUT] configuration <<<<<
7182 19:56:46.459187 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7183 19:56:46.465727 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7184 19:56:46.472803 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 19:56:46.479352 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 19:56:46.485947 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7187 19:56:46.489706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7188 19:56:46.496091 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7189 19:56:46.499035 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7190 19:56:46.502391 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7191 19:56:46.506144 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7192 19:56:46.512501 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7193 19:56:46.515583 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7194 19:56:46.519400 ===================================
7195 19:56:46.522268 LPDDR4 DRAM CONFIGURATION
7196 19:56:46.525581 ===================================
7197 19:56:46.525997 EX_ROW_EN[0] = 0x0
7198 19:56:46.528982 EX_ROW_EN[1] = 0x0
7199 19:56:46.529376 LP4Y_EN = 0x0
7200 19:56:46.532300 WORK_FSP = 0x1
7201 19:56:46.532764 WL = 0x5
7202 19:56:46.535988 RL = 0x5
7203 19:56:46.536455 BL = 0x2
7204 19:56:46.539097 RPST = 0x0
7205 19:56:46.539495 RD_PRE = 0x0
7206 19:56:46.542294 WR_PRE = 0x1
7207 19:56:46.542711 WR_PST = 0x1
7208 19:56:46.545530 DBI_WR = 0x0
7209 19:56:46.549232 DBI_RD = 0x0
7210 19:56:46.549680 OTF = 0x1
7211 19:56:46.552582 ===================================
7212 19:56:46.555618 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7213 19:56:46.559270 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7214 19:56:46.565541 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 19:56:46.568853 ===================================
7216 19:56:46.572474 LPDDR4 DRAM CONFIGURATION
7217 19:56:46.575527 ===================================
7218 19:56:46.576076 EX_ROW_EN[0] = 0x10
7219 19:56:46.579039 EX_ROW_EN[1] = 0x0
7220 19:56:46.579711 LP4Y_EN = 0x0
7221 19:56:46.582069 WORK_FSP = 0x1
7222 19:56:46.582597 WL = 0x5
7223 19:56:46.585559 RL = 0x5
7224 19:56:46.585662 BL = 0x2
7225 19:56:46.588464 RPST = 0x0
7226 19:56:46.588570 RD_PRE = 0x0
7227 19:56:46.591642 WR_PRE = 0x1
7228 19:56:46.591770 WR_PST = 0x1
7229 19:56:46.594996 DBI_WR = 0x0
7230 19:56:46.595106 DBI_RD = 0x0
7231 19:56:46.598174 OTF = 0x1
7232 19:56:46.601938 ===================================
7233 19:56:46.608375 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7234 19:56:46.608459 ==
7235 19:56:46.611970 Dram Type= 6, Freq= 0, CH_0, rank 0
7236 19:56:46.615288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7237 19:56:46.615372 ==
7238 19:56:46.618369 [Duty_Offset_Calibration]
7239 19:56:46.618451 B0:2 B1:1 CA:1
7240 19:56:46.618517
7241 19:56:46.622058 [DutyScan_Calibration_Flow] k_type=0
7242 19:56:46.632740
7243 19:56:46.632843 ==CLK 0==
7244 19:56:46.635983 Final CLK duty delay cell = 0
7245 19:56:46.639558 [0] MAX Duty = 5156%(X100), DQS PI = 22
7246 19:56:46.643029 [0] MIN Duty = 4907%(X100), DQS PI = 0
7247 19:56:46.643195 [0] AVG Duty = 5031%(X100)
7248 19:56:46.645966
7249 19:56:46.649487 CH0 CLK Duty spec in!! Max-Min= 249%
7250 19:56:46.653212 [DutyScan_Calibration_Flow] ====Done====
7251 19:56:46.653636
7252 19:56:46.656436 [DutyScan_Calibration_Flow] k_type=1
7253 19:56:46.672041
7254 19:56:46.672467 ==DQS 0 ==
7255 19:56:46.675683 Final DQS duty delay cell = -4
7256 19:56:46.678567 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7257 19:56:46.682400 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7258 19:56:46.685536 [-4] AVG Duty = 4891%(X100)
7259 19:56:46.685965
7260 19:56:46.686306 ==DQS 1 ==
7261 19:56:46.688850 Final DQS duty delay cell = 0
7262 19:56:46.692139 [0] MAX Duty = 5187%(X100), DQS PI = 20
7263 19:56:46.695595 [0] MIN Duty = 5031%(X100), DQS PI = 52
7264 19:56:46.698638 [0] AVG Duty = 5109%(X100)
7265 19:56:46.699077
7266 19:56:46.702034 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7267 19:56:46.702491
7268 19:56:46.705025 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7269 19:56:46.708507 [DutyScan_Calibration_Flow] ====Done====
7270 19:56:46.708938
7271 19:56:46.712306 [DutyScan_Calibration_Flow] k_type=3
7272 19:56:46.728466
7273 19:56:46.728549 ==DQM 0 ==
7274 19:56:46.732017 Final DQM duty delay cell = 0
7275 19:56:46.735435 [0] MAX Duty = 5218%(X100), DQS PI = 32
7276 19:56:46.738603 [0] MIN Duty = 4876%(X100), DQS PI = 60
7277 19:56:46.738685 [0] AVG Duty = 5047%(X100)
7278 19:56:46.738751
7279 19:56:46.742138 ==DQM 1 ==
7280 19:56:46.745584 Final DQM duty delay cell = -4
7281 19:56:46.748503 [-4] MAX Duty = 4969%(X100), DQS PI = 4
7282 19:56:46.751896 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7283 19:56:46.755412 [-4] AVG Duty = 4906%(X100)
7284 19:56:46.755494
7285 19:56:46.758389 CH0 DQM 0 Duty spec in!! Max-Min= 342%
7286 19:56:46.758479
7287 19:56:46.762198 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7288 19:56:46.765281 [DutyScan_Calibration_Flow] ====Done====
7289 19:56:46.765377
7290 19:56:46.768830 [DutyScan_Calibration_Flow] k_type=2
7291 19:56:46.786195
7292 19:56:46.786623 ==DQ 0 ==
7293 19:56:46.789468 Final DQ duty delay cell = 0
7294 19:56:46.793105 [0] MAX Duty = 5062%(X100), DQS PI = 26
7295 19:56:46.796560 [0] MIN Duty = 4907%(X100), DQS PI = 0
7296 19:56:46.797060 [0] AVG Duty = 4984%(X100)
7297 19:56:46.799456
7298 19:56:46.799935 ==DQ 1 ==
7299 19:56:46.802618 Final DQ duty delay cell = 0
7300 19:56:46.806642 [0] MAX Duty = 5125%(X100), DQS PI = 6
7301 19:56:46.809481 [0] MIN Duty = 4907%(X100), DQS PI = 34
7302 19:56:46.809909 [0] AVG Duty = 5016%(X100)
7303 19:56:46.810247
7304 19:56:46.813095 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7305 19:56:46.816256
7306 19:56:46.819515 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7307 19:56:46.822475 [DutyScan_Calibration_Flow] ====Done====
7308 19:56:46.822896 ==
7309 19:56:46.825961 Dram Type= 6, Freq= 0, CH_1, rank 0
7310 19:56:46.829438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7311 19:56:46.829858 ==
7312 19:56:46.832665 [Duty_Offset_Calibration]
7313 19:56:46.833083 B0:1 B1:0 CA:0
7314 19:56:46.833414
7315 19:56:46.835720 [DutyScan_Calibration_Flow] k_type=0
7316 19:56:46.845234
7317 19:56:46.845316 ==CLK 0==
7318 19:56:46.848885 Final CLK duty delay cell = -4
7319 19:56:46.851950 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7320 19:56:46.855216 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7321 19:56:46.858652 [-4] AVG Duty = 4922%(X100)
7322 19:56:46.858734
7323 19:56:46.862274 CH1 CLK Duty spec in!! Max-Min= 156%
7324 19:56:46.865046 [DutyScan_Calibration_Flow] ====Done====
7325 19:56:46.865128
7326 19:56:46.868597 [DutyScan_Calibration_Flow] k_type=1
7327 19:56:46.885123
7328 19:56:46.885207 ==DQS 0 ==
7329 19:56:46.888812 Final DQS duty delay cell = 0
7330 19:56:46.891840 [0] MAX Duty = 5094%(X100), DQS PI = 28
7331 19:56:46.895447 [0] MIN Duty = 4875%(X100), DQS PI = 2
7332 19:56:46.895548 [0] AVG Duty = 4984%(X100)
7333 19:56:46.898597
7334 19:56:46.898693 ==DQS 1 ==
7335 19:56:46.901639 Final DQS duty delay cell = 0
7336 19:56:46.905011 [0] MAX Duty = 5249%(X100), DQS PI = 16
7337 19:56:46.908800 [0] MIN Duty = 4969%(X100), DQS PI = 6
7338 19:56:46.908882 [0] AVG Duty = 5109%(X100)
7339 19:56:46.911709
7340 19:56:46.914918 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7341 19:56:46.915000
7342 19:56:46.918450 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7343 19:56:46.921680 [DutyScan_Calibration_Flow] ====Done====
7344 19:56:46.921761
7345 19:56:46.925419 [DutyScan_Calibration_Flow] k_type=3
7346 19:56:46.942355
7347 19:56:46.942435 ==DQM 0 ==
7348 19:56:46.945426 Final DQM duty delay cell = 0
7349 19:56:46.948437 [0] MAX Duty = 5218%(X100), DQS PI = 18
7350 19:56:46.952086 [0] MIN Duty = 4969%(X100), DQS PI = 48
7351 19:56:46.955324 [0] AVG Duty = 5093%(X100)
7352 19:56:46.955421
7353 19:56:46.955494 ==DQM 1 ==
7354 19:56:46.958331 Final DQM duty delay cell = 0
7355 19:56:46.962136 [0] MAX Duty = 5093%(X100), DQS PI = 16
7356 19:56:46.965275 [0] MIN Duty = 4907%(X100), DQS PI = 34
7357 19:56:46.969202 [0] AVG Duty = 5000%(X100)
7358 19:56:46.969624
7359 19:56:46.972028 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7360 19:56:46.972622
7361 19:56:46.975774 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7362 19:56:46.979098 [DutyScan_Calibration_Flow] ====Done====
7363 19:56:46.979520
7364 19:56:46.982008 [DutyScan_Calibration_Flow] k_type=2
7365 19:56:46.998410
7366 19:56:46.998837 ==DQ 0 ==
7367 19:56:47.001718 Final DQ duty delay cell = -4
7368 19:56:47.005395 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7369 19:56:47.008526 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7370 19:56:47.011916 [-4] AVG Duty = 4968%(X100)
7371 19:56:47.012341
7372 19:56:47.012677 ==DQ 1 ==
7373 19:56:47.014910 Final DQ duty delay cell = 0
7374 19:56:47.018428 [0] MAX Duty = 5156%(X100), DQS PI = 18
7375 19:56:47.021488 [0] MIN Duty = 4938%(X100), DQS PI = 8
7376 19:56:47.021570 [0] AVG Duty = 5047%(X100)
7377 19:56:47.025107
7378 19:56:47.028307 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7379 19:56:47.028390
7380 19:56:47.031455 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7381 19:56:47.034637 [DutyScan_Calibration_Flow] ====Done====
7382 19:56:47.038055 nWR fixed to 30
7383 19:56:47.038139 [ModeRegInit_LP4] CH0 RK0
7384 19:56:47.041615 [ModeRegInit_LP4] CH0 RK1
7385 19:56:47.044822 [ModeRegInit_LP4] CH1 RK0
7386 19:56:47.048031 [ModeRegInit_LP4] CH1 RK1
7387 19:56:47.048119 match AC timing 5
7388 19:56:47.055086 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7389 19:56:47.057999 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7390 19:56:47.061396 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7391 19:56:47.067931 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7392 19:56:47.070929 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7393 19:56:47.071012 [MiockJmeterHQA]
7394 19:56:47.071078
7395 19:56:47.074710 [DramcMiockJmeter] u1RxGatingPI = 0
7396 19:56:47.077841 0 : 4257, 4029
7397 19:56:47.077999 4 : 4255, 4029
7398 19:56:47.081665 8 : 4363, 4138
7399 19:56:47.081782 12 : 4252, 4027
7400 19:56:47.081883 16 : 4252, 4027
7401 19:56:47.084193 20 : 4362, 4137
7402 19:56:47.084277 24 : 4363, 4137
7403 19:56:47.087795 28 : 4253, 4027
7404 19:56:47.087943 32 : 4252, 4027
7405 19:56:47.091157 36 : 4252, 4027
7406 19:56:47.091241 40 : 4253, 4027
7407 19:56:47.094738 44 : 4255, 4029
7408 19:56:47.094847 48 : 4363, 4137
7409 19:56:47.094917 52 : 4252, 4029
7410 19:56:47.097944 56 : 4253, 4027
7411 19:56:47.098028 60 : 4250, 4027
7412 19:56:47.101039 64 : 4252, 4029
7413 19:56:47.101123 68 : 4250, 4027
7414 19:56:47.104632 72 : 4361, 4137
7415 19:56:47.104717 76 : 4361, 4137
7416 19:56:47.107769 80 : 4250, 4027
7417 19:56:47.107852 84 : 4250, 4027
7418 19:56:47.107919 88 : 4250, 121
7419 19:56:47.111078 92 : 4250, 0
7420 19:56:47.111162 96 : 4250, 0
7421 19:56:47.111229 100 : 4250, 0
7422 19:56:47.114144 104 : 4360, 0
7423 19:56:47.114228 108 : 4250, 0
7424 19:56:47.117834 112 : 4250, 0
7425 19:56:47.117918 116 : 4250, 0
7426 19:56:47.117984 120 : 4249, 0
7427 19:56:47.120890 124 : 4250, 0
7428 19:56:47.120974 128 : 4250, 0
7429 19:56:47.124220 132 : 4252, 0
7430 19:56:47.124304 136 : 4361, 0
7431 19:56:47.124370 140 : 4360, 0
7432 19:56:47.127724 144 : 4363, 0
7433 19:56:47.127808 148 : 4250, 0
7434 19:56:47.130920 152 : 4250, 0
7435 19:56:47.131004 156 : 4363, 0
7436 19:56:47.131071 160 : 4250, 0
7437 19:56:47.134584 164 : 4250, 0
7438 19:56:47.134669 168 : 4250, 0
7439 19:56:47.134735 172 : 4249, 0
7440 19:56:47.137747 176 : 4250, 0
7441 19:56:47.137831 180 : 4250, 0
7442 19:56:47.141422 184 : 4252, 0
7443 19:56:47.141507 188 : 4250, 0
7444 19:56:47.141573 192 : 4250, 0
7445 19:56:47.144373 196 : 4363, 0
7446 19:56:47.144463 200 : 4250, 0
7447 19:56:47.148060 204 : 4361, 1414
7448 19:56:47.148158 208 : 4361, 4086
7449 19:56:47.151096 212 : 4248, 4025
7450 19:56:47.151180 216 : 4361, 4138
7451 19:56:47.154187 220 : 4360, 4137
7452 19:56:47.154271 224 : 4250, 4027
7453 19:56:47.154338 228 : 4250, 4027
7454 19:56:47.157408 232 : 4363, 4139
7455 19:56:47.157492 236 : 4250, 4027
7456 19:56:47.161202 240 : 4250, 4027
7457 19:56:47.161286 244 : 4250, 4027
7458 19:56:47.164198 248 : 4252, 4029
7459 19:56:47.164282 252 : 4250, 4027
7460 19:56:47.167381 256 : 4250, 4027
7461 19:56:47.167464 260 : 4361, 4137
7462 19:56:47.170960 264 : 4250, 4026
7463 19:56:47.171044 268 : 4250, 4027
7464 19:56:47.174248 272 : 4363, 4139
7465 19:56:47.174332 276 : 4250, 4027
7466 19:56:47.177611 280 : 4250, 4027
7467 19:56:47.177694 284 : 4361, 4137
7468 19:56:47.177761 288 : 4250, 4027
7469 19:56:47.180954 292 : 4250, 4027
7470 19:56:47.181039 296 : 4250, 4027
7471 19:56:47.184055 300 : 4253, 4029
7472 19:56:47.184138 304 : 4250, 4027
7473 19:56:47.187775 308 : 4250, 3956
7474 19:56:47.187886 312 : 4361, 2198
7475 19:56:47.190787 316 : 4250, 2
7476 19:56:47.190870
7477 19:56:47.190935 MIOCK jitter meter ch=0
7478 19:56:47.190996
7479 19:56:47.194351 1T = (316-88) = 228 dly cells
7480 19:56:47.200876 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7481 19:56:47.200959 ==
7482 19:56:47.204487 Dram Type= 6, Freq= 0, CH_0, rank 0
7483 19:56:47.207515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7484 19:56:47.207600 ==
7485 19:56:47.214221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7486 19:56:47.217411 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7487 19:56:47.220527 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7488 19:56:47.227495 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7489 19:56:47.237365 [CA 0] Center 42 (12~73) winsize 62
7490 19:56:47.240621 [CA 1] Center 42 (12~73) winsize 62
7491 19:56:47.244131 [CA 2] Center 38 (8~68) winsize 61
7492 19:56:47.247309 [CA 3] Center 37 (8~67) winsize 60
7493 19:56:47.250242 [CA 4] Center 36 (6~66) winsize 61
7494 19:56:47.254057 [CA 5] Center 35 (6~64) winsize 59
7495 19:56:47.254155
7496 19:56:47.256988 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7497 19:56:47.257092
7498 19:56:47.260447 [CATrainingPosCal] consider 1 rank data
7499 19:56:47.263425 u2DelayCellTimex100 = 285/100 ps
7500 19:56:47.267164 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7501 19:56:47.273725 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7502 19:56:47.276816 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7503 19:56:47.280396 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7504 19:56:47.283781 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7505 19:56:47.287265 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7506 19:56:47.287445
7507 19:56:47.290544 CA PerBit enable=1, Macro0, CA PI delay=35
7508 19:56:47.290721
7509 19:56:47.293979 [CBTSetCACLKResult] CA Dly = 35
7510 19:56:47.297113 CS Dly: 8 (0~39)
7511 19:56:47.300714 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7512 19:56:47.303600 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7513 19:56:47.303942 ==
7514 19:56:47.306935 Dram Type= 6, Freq= 0, CH_0, rank 1
7515 19:56:47.310708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7516 19:56:47.311116 ==
7517 19:56:47.317234 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7518 19:56:47.320960 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7519 19:56:47.327109 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7520 19:56:47.330325 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7521 19:56:47.340889 [CA 0] Center 42 (12~73) winsize 62
7522 19:56:47.343845 [CA 1] Center 42 (12~73) winsize 62
7523 19:56:47.347296 [CA 2] Center 38 (8~68) winsize 61
7524 19:56:47.350602 [CA 3] Center 37 (8~67) winsize 60
7525 19:56:47.354279 [CA 4] Center 36 (6~66) winsize 61
7526 19:56:47.357629 [CA 5] Center 34 (5~64) winsize 60
7527 19:56:47.358072
7528 19:56:47.360650 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7529 19:56:47.361082
7530 19:56:47.364115 [CATrainingPosCal] consider 2 rank data
7531 19:56:47.367347 u2DelayCellTimex100 = 285/100 ps
7532 19:56:47.370989 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7533 19:56:47.377193 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7534 19:56:47.381024 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7535 19:56:47.384126 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7536 19:56:47.387186 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7537 19:56:47.390456 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7538 19:56:47.390901
7539 19:56:47.394105 CA PerBit enable=1, Macro0, CA PI delay=35
7540 19:56:47.394553
7541 19:56:47.397119 [CBTSetCACLKResult] CA Dly = 35
7542 19:56:47.400803 CS Dly: 9 (0~42)
7543 19:56:47.404341 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7544 19:56:47.407056 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7545 19:56:47.407491
7546 19:56:47.410758 ----->DramcWriteLeveling(PI) begin...
7547 19:56:47.411204 ==
7548 19:56:47.413690 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 19:56:47.417039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 19:56:47.420769 ==
7551 19:56:47.421275 Write leveling (Byte 0): 33 => 33
7552 19:56:47.423770 Write leveling (Byte 1): 28 => 28
7553 19:56:47.427253 DramcWriteLeveling(PI) end<-----
7554 19:56:47.427875
7555 19:56:47.428409 ==
7556 19:56:47.430751 Dram Type= 6, Freq= 0, CH_0, rank 0
7557 19:56:47.437075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 19:56:47.437502 ==
7559 19:56:47.437837 [Gating] SW mode calibration
7560 19:56:47.447301 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7561 19:56:47.450324 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7562 19:56:47.453680 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7563 19:56:47.460100 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 19:56:47.463696 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7565 19:56:47.466580 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7566 19:56:47.473107 1 4 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7567 19:56:47.476761 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7568 19:56:47.480091 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7569 19:56:47.487067 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7570 19:56:47.490092 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7571 19:56:47.493182 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 19:56:47.499858 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
7573 19:56:47.502998 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7574 19:56:47.506716 1 5 16 | B1->B0 | 3333 2625 | 1 1 | (1 1) (1 0)
7575 19:56:47.513389 1 5 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
7576 19:56:47.516374 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7577 19:56:47.520056 1 5 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7578 19:56:47.526380 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7579 19:56:47.529925 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7580 19:56:47.533640 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7581 19:56:47.539633 1 6 12 | B1->B0 | 2323 4544 | 0 1 | (0 0) (0 0)
7582 19:56:47.543222 1 6 16 | B1->B0 | 2d2d 4645 | 0 1 | (0 0) (0 0)
7583 19:56:47.546295 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 19:56:47.553198 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 19:56:47.556342 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 19:56:47.560221 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 19:56:47.566401 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 19:56:47.570113 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7589 19:56:47.573256 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7590 19:56:47.579961 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7591 19:56:47.582794 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7592 19:56:47.586166 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 19:56:47.589880 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 19:56:47.596326 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 19:56:47.599384 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 19:56:47.603035 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 19:56:47.609500 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 19:56:47.613235 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 19:56:47.616257 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 19:56:47.623307 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 19:56:47.626272 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 19:56:47.629518 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 19:56:47.636906 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 19:56:47.639702 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 19:56:47.643593 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7606 19:56:47.649942 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7607 19:56:47.650367 Total UI for P1: 0, mck2ui 16
7608 19:56:47.656744 best dqsien dly found for B0: ( 1, 9, 12)
7609 19:56:47.659910 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7610 19:56:47.663552 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 19:56:47.666878 Total UI for P1: 0, mck2ui 16
7612 19:56:47.669928 best dqsien dly found for B1: ( 1, 9, 18)
7613 19:56:47.673246 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7614 19:56:47.676794 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7615 19:56:47.677223
7616 19:56:47.679815 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7617 19:56:47.686787 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7618 19:56:47.687215 [Gating] SW calibration Done
7619 19:56:47.689683 ==
7620 19:56:47.690173 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 19:56:47.696747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 19:56:47.697179 ==
7623 19:56:47.697517 RX Vref Scan: 0
7624 19:56:47.697831
7625 19:56:47.700097 RX Vref 0 -> 0, step: 1
7626 19:56:47.700523
7627 19:56:47.703199 RX Delay 0 -> 252, step: 8
7628 19:56:47.706314 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7629 19:56:47.709832 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7630 19:56:47.713560 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7631 19:56:47.719777 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7632 19:56:47.722868 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7633 19:56:47.726535 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7634 19:56:47.729897 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7635 19:56:47.733194 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7636 19:56:47.736582 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7637 19:56:47.742836 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7638 19:56:47.746008 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7639 19:56:47.749861 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7640 19:56:47.753112 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7641 19:56:47.759578 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7642 19:56:47.763179 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7643 19:56:47.766088 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7644 19:56:47.766514 ==
7645 19:56:47.769343 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 19:56:47.772670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 19:56:47.773095 ==
7648 19:56:47.775976 DQS Delay:
7649 19:56:47.776398 DQS0 = 0, DQS1 = 0
7650 19:56:47.779444 DQM Delay:
7651 19:56:47.779920 DQM0 = 136, DQM1 = 130
7652 19:56:47.780263 DQ Delay:
7653 19:56:47.786561 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7654 19:56:47.789666 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7655 19:56:47.792751 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7656 19:56:47.795934 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7657 19:56:47.796356
7658 19:56:47.796690
7659 19:56:47.797002 ==
7660 19:56:47.799509 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 19:56:47.803020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 19:56:47.803450 ==
7663 19:56:47.804060
7664 19:56:47.804587
7665 19:56:47.806030 TX Vref Scan disable
7666 19:56:47.809518 == TX Byte 0 ==
7667 19:56:47.812781 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7668 19:56:47.816081 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7669 19:56:47.819523 == TX Byte 1 ==
7670 19:56:47.822906 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7671 19:56:47.826514 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7672 19:56:47.826989 ==
7673 19:56:47.829742 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 19:56:47.832867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 19:56:47.835756 ==
7676 19:56:47.846348
7677 19:56:47.849819 TX Vref early break, caculate TX vref
7678 19:56:47.853000 TX Vref=16, minBit 9, minWin=22, winSum=380
7679 19:56:47.856718 TX Vref=18, minBit 0, minWin=24, winSum=391
7680 19:56:47.859879 TX Vref=20, minBit 9, minWin=24, winSum=402
7681 19:56:47.863122 TX Vref=22, minBit 1, minWin=25, winSum=411
7682 19:56:47.866227 TX Vref=24, minBit 3, minWin=25, winSum=421
7683 19:56:47.873277 TX Vref=26, minBit 8, minWin=25, winSum=429
7684 19:56:47.876210 TX Vref=28, minBit 1, minWin=25, winSum=430
7685 19:56:47.879573 TX Vref=30, minBit 6, minWin=24, winSum=414
7686 19:56:47.882461 TX Vref=32, minBit 1, minWin=24, winSum=405
7687 19:56:47.889339 [TxChooseVref] Worse bit 1, Min win 25, Win sum 430, Final Vref 28
7688 19:56:47.889426
7689 19:56:47.892624 Final TX Range 0 Vref 28
7690 19:56:47.892709
7691 19:56:47.892774 ==
7692 19:56:47.895837 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 19:56:47.899382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 19:56:47.899514 ==
7695 19:56:47.899619
7696 19:56:47.899706
7697 19:56:47.902473 TX Vref Scan disable
7698 19:56:47.906126 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7699 19:56:47.909082 == TX Byte 0 ==
7700 19:56:47.912853 u2DelayCellOfst[0]=13 cells (4 PI)
7701 19:56:47.915909 u2DelayCellOfst[1]=17 cells (5 PI)
7702 19:56:47.919581 u2DelayCellOfst[2]=10 cells (3 PI)
7703 19:56:47.922650 u2DelayCellOfst[3]=10 cells (3 PI)
7704 19:56:47.925736 u2DelayCellOfst[4]=10 cells (3 PI)
7705 19:56:47.925837 u2DelayCellOfst[5]=0 cells (0 PI)
7706 19:56:47.929284 u2DelayCellOfst[6]=17 cells (5 PI)
7707 19:56:47.932960 u2DelayCellOfst[7]=17 cells (5 PI)
7708 19:56:47.939192 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7709 19:56:47.942944 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7710 19:56:47.943063 == TX Byte 1 ==
7711 19:56:47.945860 u2DelayCellOfst[8]=0 cells (0 PI)
7712 19:56:47.949301 u2DelayCellOfst[9]=3 cells (1 PI)
7713 19:56:47.952350 u2DelayCellOfst[10]=10 cells (3 PI)
7714 19:56:47.955459 u2DelayCellOfst[11]=3 cells (1 PI)
7715 19:56:47.959147 u2DelayCellOfst[12]=13 cells (4 PI)
7716 19:56:47.962424 u2DelayCellOfst[13]=13 cells (4 PI)
7717 19:56:47.965536 u2DelayCellOfst[14]=13 cells (4 PI)
7718 19:56:47.969333 u2DelayCellOfst[15]=10 cells (3 PI)
7719 19:56:47.972571 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7720 19:56:47.975863 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7721 19:56:47.978904 DramC Write-DBI on
7722 19:56:47.978987 ==
7723 19:56:47.982218 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 19:56:47.986392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 19:56:47.986822 ==
7726 19:56:47.987162
7727 19:56:47.987475
7728 19:56:47.989625 TX Vref Scan disable
7729 19:56:47.992706 == TX Byte 0 ==
7730 19:56:47.996145 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7731 19:56:47.999694 == TX Byte 1 ==
7732 19:56:48.002498 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7733 19:56:48.002925 DramC Write-DBI off
7734 19:56:48.003261
7735 19:56:48.005877 [DATLAT]
7736 19:56:48.006304 Freq=1600, CH0 RK0
7737 19:56:48.006643
7738 19:56:48.009688 DATLAT Default: 0xf
7739 19:56:48.010109 0, 0xFFFF, sum = 0
7740 19:56:48.012812 1, 0xFFFF, sum = 0
7741 19:56:48.013244 2, 0xFFFF, sum = 0
7742 19:56:48.015920 3, 0xFFFF, sum = 0
7743 19:56:48.016355 4, 0xFFFF, sum = 0
7744 19:56:48.019422 5, 0xFFFF, sum = 0
7745 19:56:48.019926 6, 0xFFFF, sum = 0
7746 19:56:48.022797 7, 0xFFFF, sum = 0
7747 19:56:48.023229 8, 0xFFFF, sum = 0
7748 19:56:48.026117 9, 0xFFFF, sum = 0
7749 19:56:48.026549 10, 0xFFFF, sum = 0
7750 19:56:48.029481 11, 0xFFFF, sum = 0
7751 19:56:48.032498 12, 0xFFFF, sum = 0
7752 19:56:48.032961 13, 0xFFFF, sum = 0
7753 19:56:48.035944 14, 0x0, sum = 1
7754 19:56:48.036379 15, 0x0, sum = 2
7755 19:56:48.039089 16, 0x0, sum = 3
7756 19:56:48.039727 17, 0x0, sum = 4
7757 19:56:48.040110 best_step = 15
7758 19:56:48.040579
7759 19:56:48.042589 ==
7760 19:56:48.045672 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 19:56:48.049012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 19:56:48.049577 ==
7763 19:56:48.050066 RX Vref Scan: 1
7764 19:56:48.050528
7765 19:56:48.052713 Set Vref Range= 24 -> 127
7766 19:56:48.053142
7767 19:56:48.055687 RX Vref 24 -> 127, step: 1
7768 19:56:48.056142
7769 19:56:48.058881 RX Delay 27 -> 252, step: 4
7770 19:56:48.059612
7771 19:56:48.062331 Set Vref, RX VrefLevel [Byte0]: 24
7772 19:56:48.065465 [Byte1]: 24
7773 19:56:48.066138
7774 19:56:48.069399 Set Vref, RX VrefLevel [Byte0]: 25
7775 19:56:48.072651 [Byte1]: 25
7776 19:56:48.073197
7777 19:56:48.075972 Set Vref, RX VrefLevel [Byte0]: 26
7778 19:56:48.078981 [Byte1]: 26
7779 19:56:48.082144
7780 19:56:48.082682 Set Vref, RX VrefLevel [Byte0]: 27
7781 19:56:48.085435 [Byte1]: 27
7782 19:56:48.089620
7783 19:56:48.089992 Set Vref, RX VrefLevel [Byte0]: 28
7784 19:56:48.093387 [Byte1]: 28
7785 19:56:48.097244
7786 19:56:48.097503 Set Vref, RX VrefLevel [Byte0]: 29
7787 19:56:48.100294 [Byte1]: 29
7788 19:56:48.104664
7789 19:56:48.104907 Set Vref, RX VrefLevel [Byte0]: 30
7790 19:56:48.107908 [Byte1]: 30
7791 19:56:48.112330
7792 19:56:48.112574 Set Vref, RX VrefLevel [Byte0]: 31
7793 19:56:48.115439 [Byte1]: 31
7794 19:56:48.119872
7795 19:56:48.120116 Set Vref, RX VrefLevel [Byte0]: 32
7796 19:56:48.122656 [Byte1]: 32
7797 19:56:48.127142
7798 19:56:48.127251 Set Vref, RX VrefLevel [Byte0]: 33
7799 19:56:48.130372 [Byte1]: 33
7800 19:56:48.134554
7801 19:56:48.134665 Set Vref, RX VrefLevel [Byte0]: 34
7802 19:56:48.138180 [Byte1]: 34
7803 19:56:48.142281
7804 19:56:48.142368 Set Vref, RX VrefLevel [Byte0]: 35
7805 19:56:48.145686 [Byte1]: 35
7806 19:56:48.150016
7807 19:56:48.150106 Set Vref, RX VrefLevel [Byte0]: 36
7808 19:56:48.152887 [Byte1]: 36
7809 19:56:48.157333
7810 19:56:48.157438 Set Vref, RX VrefLevel [Byte0]: 37
7811 19:56:48.160380 [Byte1]: 37
7812 19:56:48.165114
7813 19:56:48.165229 Set Vref, RX VrefLevel [Byte0]: 38
7814 19:56:48.168269 [Byte1]: 38
7815 19:56:48.172278
7816 19:56:48.172418 Set Vref, RX VrefLevel [Byte0]: 39
7817 19:56:48.176209 [Byte1]: 39
7818 19:56:48.180554
7819 19:56:48.180987 Set Vref, RX VrefLevel [Byte0]: 40
7820 19:56:48.183504 [Byte1]: 40
7821 19:56:48.188147
7822 19:56:48.188583 Set Vref, RX VrefLevel [Byte0]: 41
7823 19:56:48.190949 [Byte1]: 41
7824 19:56:48.195475
7825 19:56:48.196074 Set Vref, RX VrefLevel [Byte0]: 42
7826 19:56:48.198741 [Byte1]: 42
7827 19:56:48.202626
7828 19:56:48.203064 Set Vref, RX VrefLevel [Byte0]: 43
7829 19:56:48.206463 [Byte1]: 43
7830 19:56:48.210195
7831 19:56:48.210714 Set Vref, RX VrefLevel [Byte0]: 44
7832 19:56:48.214068 [Byte1]: 44
7833 19:56:48.217910
7834 19:56:48.218324 Set Vref, RX VrefLevel [Byte0]: 45
7835 19:56:48.220978 [Byte1]: 45
7836 19:56:48.225330
7837 19:56:48.225743 Set Vref, RX VrefLevel [Byte0]: 46
7838 19:56:48.228512 [Byte1]: 46
7839 19:56:48.232855
7840 19:56:48.233269 Set Vref, RX VrefLevel [Byte0]: 47
7841 19:56:48.236071 [Byte1]: 47
7842 19:56:48.240563
7843 19:56:48.240979 Set Vref, RX VrefLevel [Byte0]: 48
7844 19:56:48.243661 [Byte1]: 48
7845 19:56:48.248323
7846 19:56:48.248740 Set Vref, RX VrefLevel [Byte0]: 49
7847 19:56:48.251235 [Byte1]: 49
7848 19:56:48.255930
7849 19:56:48.256344 Set Vref, RX VrefLevel [Byte0]: 50
7850 19:56:48.259115 [Byte1]: 50
7851 19:56:48.263373
7852 19:56:48.263833 Set Vref, RX VrefLevel [Byte0]: 51
7853 19:56:48.266336 [Byte1]: 51
7854 19:56:48.270462
7855 19:56:48.270877 Set Vref, RX VrefLevel [Byte0]: 52
7856 19:56:48.273626 [Byte1]: 52
7857 19:56:48.277955
7858 19:56:48.278369 Set Vref, RX VrefLevel [Byte0]: 53
7859 19:56:48.281521 [Byte1]: 53
7860 19:56:48.285719
7861 19:56:48.286137 Set Vref, RX VrefLevel [Byte0]: 54
7862 19:56:48.289012 [Byte1]: 54
7863 19:56:48.293263
7864 19:56:48.293676 Set Vref, RX VrefLevel [Byte0]: 55
7865 19:56:48.296412 [Byte1]: 55
7866 19:56:48.300649
7867 19:56:48.301081 Set Vref, RX VrefLevel [Byte0]: 56
7868 19:56:48.304259 [Byte1]: 56
7869 19:56:48.308504
7870 19:56:48.308940 Set Vref, RX VrefLevel [Byte0]: 57
7871 19:56:48.311471 [Byte1]: 57
7872 19:56:48.315793
7873 19:56:48.316367 Set Vref, RX VrefLevel [Byte0]: 58
7874 19:56:48.318968 [Byte1]: 58
7875 19:56:48.323367
7876 19:56:48.323819 Set Vref, RX VrefLevel [Byte0]: 59
7877 19:56:48.326506 [Byte1]: 59
7878 19:56:48.330868
7879 19:56:48.331283 Set Vref, RX VrefLevel [Byte0]: 60
7880 19:56:48.333976 [Byte1]: 60
7881 19:56:48.338442
7882 19:56:48.338858 Set Vref, RX VrefLevel [Byte0]: 61
7883 19:56:48.341694 [Byte1]: 61
7884 19:56:48.346018
7885 19:56:48.346431 Set Vref, RX VrefLevel [Byte0]: 62
7886 19:56:48.349171 [Byte1]: 62
7887 19:56:48.353603
7888 19:56:48.354029 Set Vref, RX VrefLevel [Byte0]: 63
7889 19:56:48.357178 [Byte1]: 63
7890 19:56:48.361228
7891 19:56:48.361650 Set Vref, RX VrefLevel [Byte0]: 64
7892 19:56:48.364177 [Byte1]: 64
7893 19:56:48.368572
7894 19:56:48.368999 Set Vref, RX VrefLevel [Byte0]: 65
7895 19:56:48.371738 [Byte1]: 65
7896 19:56:48.375952
7897 19:56:48.376367 Set Vref, RX VrefLevel [Byte0]: 66
7898 19:56:48.379148 [Byte1]: 66
7899 19:56:48.383513
7900 19:56:48.383629 Set Vref, RX VrefLevel [Byte0]: 67
7901 19:56:48.389814 [Byte1]: 67
7902 19:56:48.389908
7903 19:56:48.392992 Set Vref, RX VrefLevel [Byte0]: 68
7904 19:56:48.396782 [Byte1]: 68
7905 19:56:48.396892
7906 19:56:48.399892 Set Vref, RX VrefLevel [Byte0]: 69
7907 19:56:48.402801 [Byte1]: 69
7908 19:56:48.402927
7909 19:56:48.406232 Set Vref, RX VrefLevel [Byte0]: 70
7910 19:56:48.409605 [Byte1]: 70
7911 19:56:48.413363
7912 19:56:48.413520 Set Vref, RX VrefLevel [Byte0]: 71
7913 19:56:48.416684 [Byte1]: 71
7914 19:56:48.421049
7915 19:56:48.421228 Set Vref, RX VrefLevel [Byte0]: 72
7916 19:56:48.424196 [Byte1]: 72
7917 19:56:48.428632
7918 19:56:48.428880 Set Vref, RX VrefLevel [Byte0]: 73
7919 19:56:48.432040 [Byte1]: 73
7920 19:56:48.436418
7921 19:56:48.436835 Final RX Vref Byte 0 = 55 to rank0
7922 19:56:48.440005 Final RX Vref Byte 1 = 63 to rank0
7923 19:56:48.442734 Final RX Vref Byte 0 = 55 to rank1
7924 19:56:48.446508 Final RX Vref Byte 1 = 63 to rank1==
7925 19:56:48.449779 Dram Type= 6, Freq= 0, CH_0, rank 0
7926 19:56:48.455826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7927 19:56:48.456331 ==
7928 19:56:48.456678 DQS Delay:
7929 19:56:48.459571 DQS0 = 0, DQS1 = 0
7930 19:56:48.460041 DQM Delay:
7931 19:56:48.460381 DQM0 = 133, DQM1 = 127
7932 19:56:48.462779 DQ Delay:
7933 19:56:48.466282 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7934 19:56:48.469717 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7935 19:56:48.472740 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7936 19:56:48.475935 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7937 19:56:48.476352
7938 19:56:48.476683
7939 19:56:48.476986
7940 19:56:48.479594 [DramC_TX_OE_Calibration] TA2
7941 19:56:48.482550 Original DQ_B0 (3 6) =30, OEN = 27
7942 19:56:48.485719 Original DQ_B1 (3 6) =30, OEN = 27
7943 19:56:48.489342 24, 0x0, End_B0=24 End_B1=24
7944 19:56:48.489767 25, 0x0, End_B0=25 End_B1=25
7945 19:56:48.492587 26, 0x0, End_B0=26 End_B1=26
7946 19:56:48.495717 27, 0x0, End_B0=27 End_B1=27
7947 19:56:48.499528 28, 0x0, End_B0=28 End_B1=28
7948 19:56:48.502640 29, 0x0, End_B0=29 End_B1=29
7949 19:56:48.503168 30, 0x0, End_B0=30 End_B1=30
7950 19:56:48.505840 31, 0x4141, End_B0=30 End_B1=30
7951 19:56:48.509078 Byte0 end_step=30 best_step=27
7952 19:56:48.512649 Byte1 end_step=30 best_step=27
7953 19:56:48.515858 Byte0 TX OE(2T, 0.5T) = (3, 3)
7954 19:56:48.519100 Byte1 TX OE(2T, 0.5T) = (3, 3)
7955 19:56:48.519737
7956 19:56:48.520163
7957 19:56:48.525680 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7958 19:56:48.528856 CH0 RK0: MR19=303, MR18=2420
7959 19:56:48.535610 CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16
7960 19:56:48.536290
7961 19:56:48.538471 ----->DramcWriteLeveling(PI) begin...
7962 19:56:48.539012 ==
7963 19:56:48.542044 Dram Type= 6, Freq= 0, CH_0, rank 1
7964 19:56:48.545332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 19:56:48.546031 ==
7966 19:56:48.548417 Write leveling (Byte 0): 36 => 36
7967 19:56:48.551944 Write leveling (Byte 1): 29 => 29
7968 19:56:48.555163 DramcWriteLeveling(PI) end<-----
7969 19:56:48.555583
7970 19:56:48.556078 ==
7971 19:56:48.558708 Dram Type= 6, Freq= 0, CH_0, rank 1
7972 19:56:48.561877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 19:56:48.562502 ==
7974 19:56:48.565448 [Gating] SW mode calibration
7975 19:56:48.571772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7976 19:56:48.578499 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7977 19:56:48.581921 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 19:56:48.588531 1 4 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7979 19:56:48.591572 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7980 19:56:48.594590 1 4 12 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7981 19:56:48.601830 1 4 16 | B1->B0 | 2f2f 3635 | 0 1 | (0 0) (0 0)
7982 19:56:48.604868 1 4 20 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7983 19:56:48.608166 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7984 19:56:48.615061 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7985 19:56:48.618216 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 19:56:48.621437 1 5 4 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7987 19:56:48.628269 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7988 19:56:48.631238 1 5 12 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
7989 19:56:48.634519 1 5 16 | B1->B0 | 2d2d 2423 | 0 1 | (0 1) (1 0)
7990 19:56:48.641143 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 19:56:48.644457 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7992 19:56:48.648318 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7993 19:56:48.651360 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 19:56:48.657822 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7995 19:56:48.661009 1 6 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7996 19:56:48.664153 1 6 12 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
7997 19:56:48.670835 1 6 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7998 19:56:48.674350 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 19:56:48.677589 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 19:56:48.684577 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 19:56:48.687607 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 19:56:48.691369 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 19:56:48.697612 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 19:56:48.700785 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8005 19:56:48.704030 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8006 19:56:48.711057 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 19:56:48.714158 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 19:56:48.717466 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 19:56:48.724097 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 19:56:48.727967 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 19:56:48.731045 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 19:56:48.738077 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 19:56:48.741105 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 19:56:48.744050 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 19:56:48.750832 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 19:56:48.753922 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 19:56:48.757749 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 19:56:48.763997 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 19:56:48.767124 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 19:56:48.770924 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8021 19:56:48.777784 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8022 19:56:48.780764 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 19:56:48.783843 Total UI for P1: 0, mck2ui 16
8024 19:56:48.787119 best dqsien dly found for B0: ( 1, 9, 14)
8025 19:56:48.790903 Total UI for P1: 0, mck2ui 16
8026 19:56:48.793841 best dqsien dly found for B1: ( 1, 9, 14)
8027 19:56:48.797095 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8028 19:56:48.800785 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8029 19:56:48.800882
8030 19:56:48.803818 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8031 19:56:48.807518 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8032 19:56:48.810594 [Gating] SW calibration Done
8033 19:56:48.810677 ==
8034 19:56:48.813702 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 19:56:48.817315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 19:56:48.817417 ==
8037 19:56:48.820676 RX Vref Scan: 0
8038 19:56:48.820758
8039 19:56:48.824234 RX Vref 0 -> 0, step: 1
8040 19:56:48.824315
8041 19:56:48.824380 RX Delay 0 -> 252, step: 8
8042 19:56:48.830428 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8043 19:56:48.833702 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8044 19:56:48.836979 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8045 19:56:48.840485 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8046 19:56:48.843881 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8047 19:56:48.850425 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8048 19:56:48.853609 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8049 19:56:48.857026 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8050 19:56:48.860165 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8051 19:56:48.863971 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8052 19:56:48.870496 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8053 19:56:48.873653 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8054 19:56:48.877331 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8055 19:56:48.880496 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8056 19:56:48.883582 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8057 19:56:48.890434 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8058 19:56:48.890520 ==
8059 19:56:48.894087 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 19:56:48.897085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 19:56:48.897161 ==
8062 19:56:48.897224 DQS Delay:
8063 19:56:48.900673 DQS0 = 0, DQS1 = 0
8064 19:56:48.900774 DQM Delay:
8065 19:56:48.903848 DQM0 = 137, DQM1 = 130
8066 19:56:48.903952 DQ Delay:
8067 19:56:48.906988 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8068 19:56:48.910782 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8069 19:56:48.913695 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8070 19:56:48.917096 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8071 19:56:48.917177
8072 19:56:48.917241
8073 19:56:48.920682 ==
8074 19:56:48.920762 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 19:56:48.926929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 19:56:48.927011 ==
8077 19:56:48.927080
8078 19:56:48.927143
8079 19:56:48.930702 TX Vref Scan disable
8080 19:56:48.930784 == TX Byte 0 ==
8081 19:56:48.933901 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8082 19:56:48.940639 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8083 19:56:48.940727 == TX Byte 1 ==
8084 19:56:48.943607 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8085 19:56:48.950354 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8086 19:56:48.950511 ==
8087 19:56:48.953270 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 19:56:48.956896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 19:56:48.957009 ==
8090 19:56:48.971235
8091 19:56:48.974071 TX Vref early break, caculate TX vref
8092 19:56:48.977425 TX Vref=16, minBit 3, minWin=22, winSum=385
8093 19:56:48.980889 TX Vref=18, minBit 1, minWin=23, winSum=396
8094 19:56:48.984021 TX Vref=20, minBit 1, minWin=24, winSum=404
8095 19:56:48.987213 TX Vref=22, minBit 1, minWin=24, winSum=413
8096 19:56:48.990829 TX Vref=24, minBit 1, minWin=24, winSum=421
8097 19:56:48.997026 TX Vref=26, minBit 0, minWin=25, winSum=425
8098 19:56:49.000858 TX Vref=28, minBit 0, minWin=25, winSum=423
8099 19:56:49.003806 TX Vref=30, minBit 4, minWin=25, winSum=419
8100 19:56:49.007046 TX Vref=32, minBit 1, minWin=24, winSum=410
8101 19:56:49.010754 TX Vref=34, minBit 0, minWin=24, winSum=396
8102 19:56:49.017065 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8103 19:56:49.017143
8104 19:56:49.020633 Final TX Range 0 Vref 26
8105 19:56:49.020705
8106 19:56:49.020765 ==
8107 19:56:49.023671 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 19:56:49.027491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 19:56:49.027564 ==
8110 19:56:49.027625
8111 19:56:49.027719
8112 19:56:49.030586 TX Vref Scan disable
8113 19:56:49.037101 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8114 19:56:49.037178 == TX Byte 0 ==
8115 19:56:49.040842 u2DelayCellOfst[0]=10 cells (3 PI)
8116 19:56:49.044027 u2DelayCellOfst[1]=13 cells (4 PI)
8117 19:56:49.047176 u2DelayCellOfst[2]=10 cells (3 PI)
8118 19:56:49.050312 u2DelayCellOfst[3]=10 cells (3 PI)
8119 19:56:49.054046 u2DelayCellOfst[4]=6 cells (2 PI)
8120 19:56:49.057269 u2DelayCellOfst[5]=0 cells (0 PI)
8121 19:56:49.060413 u2DelayCellOfst[6]=13 cells (4 PI)
8122 19:56:49.063996 u2DelayCellOfst[7]=13 cells (4 PI)
8123 19:56:49.066982 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8124 19:56:49.070736 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8125 19:56:49.073615 == TX Byte 1 ==
8126 19:56:49.073720 u2DelayCellOfst[8]=3 cells (1 PI)
8127 19:56:49.077301 u2DelayCellOfst[9]=0 cells (0 PI)
8128 19:56:49.080172 u2DelayCellOfst[10]=6 cells (2 PI)
8129 19:56:49.083585 u2DelayCellOfst[11]=3 cells (1 PI)
8130 19:56:49.087022 u2DelayCellOfst[12]=10 cells (3 PI)
8131 19:56:49.090390 u2DelayCellOfst[13]=13 cells (4 PI)
8132 19:56:49.093586 u2DelayCellOfst[14]=13 cells (4 PI)
8133 19:56:49.097004 u2DelayCellOfst[15]=10 cells (3 PI)
8134 19:56:49.100187 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8135 19:56:49.107465 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8136 19:56:49.107975 DramC Write-DBI on
8137 19:56:49.108315 ==
8138 19:56:49.110928 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 19:56:49.113904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 19:56:49.117244 ==
8141 19:56:49.117840
8142 19:56:49.118337
8143 19:56:49.118861 TX Vref Scan disable
8144 19:56:49.121146 == TX Byte 0 ==
8145 19:56:49.124187 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8146 19:56:49.127709 == TX Byte 1 ==
8147 19:56:49.130365 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8148 19:56:49.133733 DramC Write-DBI off
8149 19:56:49.134369
8150 19:56:49.134936 [DATLAT]
8151 19:56:49.135569 Freq=1600, CH0 RK1
8152 19:56:49.135979
8153 19:56:49.136913 DATLAT Default: 0xf
8154 19:56:49.137258 0, 0xFFFF, sum = 0
8155 19:56:49.140775 1, 0xFFFF, sum = 0
8156 19:56:49.143969 2, 0xFFFF, sum = 0
8157 19:56:49.144423 3, 0xFFFF, sum = 0
8158 19:56:49.147421 4, 0xFFFF, sum = 0
8159 19:56:49.147871 5, 0xFFFF, sum = 0
8160 19:56:49.150685 6, 0xFFFF, sum = 0
8161 19:56:49.151068 7, 0xFFFF, sum = 0
8162 19:56:49.153874 8, 0xFFFF, sum = 0
8163 19:56:49.154300 9, 0xFFFF, sum = 0
8164 19:56:49.157049 10, 0xFFFF, sum = 0
8165 19:56:49.157503 11, 0xFFFF, sum = 0
8166 19:56:49.160101 12, 0xFFFF, sum = 0
8167 19:56:49.160552 13, 0xFFFF, sum = 0
8168 19:56:49.164094 14, 0x0, sum = 1
8169 19:56:49.164727 15, 0x0, sum = 2
8170 19:56:49.167398 16, 0x0, sum = 3
8171 19:56:49.168075 17, 0x0, sum = 4
8172 19:56:49.170591 best_step = 15
8173 19:56:49.171041
8174 19:56:49.171376 ==
8175 19:56:49.173576 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 19:56:49.176629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 19:56:49.177050 ==
8178 19:56:49.180290 RX Vref Scan: 0
8179 19:56:49.180774
8180 19:56:49.181116 RX Vref 0 -> 0, step: 1
8181 19:56:49.181431
8182 19:56:49.183875 RX Delay 19 -> 252, step: 4
8183 19:56:49.186913 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8184 19:56:49.193749 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8185 19:56:49.196963 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8186 19:56:49.200438 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8187 19:56:49.204002 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8188 19:56:49.207085 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8189 19:56:49.213892 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8190 19:56:49.216931 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8191 19:56:49.220545 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8192 19:56:49.223707 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8193 19:56:49.227077 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8194 19:56:49.233645 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8195 19:56:49.237431 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8196 19:56:49.240136 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8197 19:56:49.243512 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8198 19:56:49.246729 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8199 19:56:49.249970 ==
8200 19:56:49.253474 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 19:56:49.256535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 19:56:49.257138 ==
8203 19:56:49.257657 DQS Delay:
8204 19:56:49.260050 DQS0 = 0, DQS1 = 0
8205 19:56:49.260535 DQM Delay:
8206 19:56:49.263019 DQM0 = 134, DQM1 = 127
8207 19:56:49.263620 DQ Delay:
8208 19:56:49.266894 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8209 19:56:49.270074 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8210 19:56:49.273182 DQ8 =120, DQ9 =116, DQ10 =128, DQ11 =118
8211 19:56:49.276810 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8212 19:56:49.277232
8213 19:56:49.277566
8214 19:56:49.277879
8215 19:56:49.280074 [DramC_TX_OE_Calibration] TA2
8216 19:56:49.283237 Original DQ_B0 (3 6) =30, OEN = 27
8217 19:56:49.286859 Original DQ_B1 (3 6) =30, OEN = 27
8218 19:56:49.289767 24, 0x0, End_B0=24 End_B1=24
8219 19:56:49.293195 25, 0x0, End_B0=25 End_B1=25
8220 19:56:49.293652 26, 0x0, End_B0=26 End_B1=26
8221 19:56:49.296650 27, 0x0, End_B0=27 End_B1=27
8222 19:56:49.299683 28, 0x0, End_B0=28 End_B1=28
8223 19:56:49.302971 29, 0x0, End_B0=29 End_B1=29
8224 19:56:49.306542 30, 0x0, End_B0=30 End_B1=30
8225 19:56:49.307078 31, 0x4141, End_B0=30 End_B1=30
8226 19:56:49.310074 Byte0 end_step=30 best_step=27
8227 19:56:49.313461 Byte1 end_step=30 best_step=27
8228 19:56:49.316512 Byte0 TX OE(2T, 0.5T) = (3, 3)
8229 19:56:49.320219 Byte1 TX OE(2T, 0.5T) = (3, 3)
8230 19:56:49.320640
8231 19:56:49.320970
8232 19:56:49.326655 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
8233 19:56:49.329611 CH0 RK1: MR19=303, MR18=1F08
8234 19:56:49.336782 CH0_RK1: MR19=0x303, MR18=0x1F08, DQSOSC=394, MR23=63, INC=23, DEC=15
8235 19:56:49.339563 [RxdqsGatingPostProcess] freq 1600
8236 19:56:49.343157 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8237 19:56:49.346433 best DQS0 dly(2T, 0.5T) = (1, 1)
8238 19:56:49.349821 best DQS1 dly(2T, 0.5T) = (1, 1)
8239 19:56:49.352821 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8240 19:56:49.356466 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8241 19:56:49.359692 best DQS0 dly(2T, 0.5T) = (1, 1)
8242 19:56:49.363078 best DQS1 dly(2T, 0.5T) = (1, 1)
8243 19:56:49.366140 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8244 19:56:49.369928 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8245 19:56:49.373034 Pre-setting of DQS Precalculation
8246 19:56:49.376200 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8247 19:56:49.376638 ==
8248 19:56:49.379377 Dram Type= 6, Freq= 0, CH_1, rank 0
8249 19:56:49.386106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8250 19:56:49.386537 ==
8251 19:56:49.389838 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8252 19:56:49.395956 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8253 19:56:49.399485 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8254 19:56:49.406207 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8255 19:56:49.413591 [CA 0] Center 42 (13~72) winsize 60
8256 19:56:49.417191 [CA 1] Center 42 (13~72) winsize 60
8257 19:56:49.419973 [CA 2] Center 38 (9~68) winsize 60
8258 19:56:49.423408 [CA 3] Center 38 (9~68) winsize 60
8259 19:56:49.426943 [CA 4] Center 39 (10~68) winsize 59
8260 19:56:49.430172 [CA 5] Center 37 (8~67) winsize 60
8261 19:56:49.430596
8262 19:56:49.433420 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8263 19:56:49.433844
8264 19:56:49.436908 [CATrainingPosCal] consider 1 rank data
8265 19:56:49.439794 u2DelayCellTimex100 = 285/100 ps
8266 19:56:49.443762 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8267 19:56:49.449956 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8268 19:56:49.453700 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8269 19:56:49.456577 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8270 19:56:49.460025 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8271 19:56:49.463329 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8272 19:56:49.463964
8273 19:56:49.466438 CA PerBit enable=1, Macro0, CA PI delay=37
8274 19:56:49.466941
8275 19:56:49.469981 [CBTSetCACLKResult] CA Dly = 37
8276 19:56:49.473439 CS Dly: 11 (0~42)
8277 19:56:49.476498 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8278 19:56:49.480010 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8279 19:56:49.480462 ==
8280 19:56:49.483255 Dram Type= 6, Freq= 0, CH_1, rank 1
8281 19:56:49.489971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 19:56:49.490405 ==
8283 19:56:49.493187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8284 19:56:49.496281 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8285 19:56:49.503066 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8286 19:56:49.509717 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8287 19:56:49.516648 [CA 0] Center 42 (12~72) winsize 61
8288 19:56:49.520458 [CA 1] Center 41 (12~71) winsize 60
8289 19:56:49.523720 [CA 2] Center 38 (9~68) winsize 60
8290 19:56:49.526653 [CA 3] Center 37 (8~67) winsize 60
8291 19:56:49.530215 [CA 4] Center 38 (8~68) winsize 61
8292 19:56:49.533683 [CA 5] Center 37 (8~67) winsize 60
8293 19:56:49.534293
8294 19:56:49.537026 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8295 19:56:49.537499
8296 19:56:49.540249 [CATrainingPosCal] consider 2 rank data
8297 19:56:49.543550 u2DelayCellTimex100 = 285/100 ps
8298 19:56:49.547170 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8299 19:56:49.553570 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8300 19:56:49.556747 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8301 19:56:49.560509 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8302 19:56:49.563679 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8303 19:56:49.566882 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8304 19:56:49.567306
8305 19:56:49.570041 CA PerBit enable=1, Macro0, CA PI delay=37
8306 19:56:49.570592
8307 19:56:49.573926 [CBTSetCACLKResult] CA Dly = 37
8308 19:56:49.576853 CS Dly: 12 (0~44)
8309 19:56:49.580419 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8310 19:56:49.583715 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8311 19:56:49.584188
8312 19:56:49.586853 ----->DramcWriteLeveling(PI) begin...
8313 19:56:49.587281 ==
8314 19:56:49.590079 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 19:56:49.593591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 19:56:49.596921 ==
8317 19:56:49.597537 Write leveling (Byte 0): 25 => 25
8318 19:56:49.600163 Write leveling (Byte 1): 26 => 26
8319 19:56:49.603536 DramcWriteLeveling(PI) end<-----
8320 19:56:49.604020
8321 19:56:49.604303 ==
8322 19:56:49.606694 Dram Type= 6, Freq= 0, CH_1, rank 0
8323 19:56:49.613376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 19:56:49.613681 ==
8325 19:56:49.613922 [Gating] SW mode calibration
8326 19:56:49.623376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8327 19:56:49.626499 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8328 19:56:49.632815 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 19:56:49.636499 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 19:56:49.639444 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8331 19:56:49.646418 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 19:56:49.649350 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 19:56:49.652861 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 19:56:49.656408 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 19:56:49.662713 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 19:56:49.665884 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 19:56:49.669628 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 19:56:49.676071 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
8339 19:56:49.679242 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
8340 19:56:49.683144 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 19:56:49.689343 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 19:56:49.692939 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 19:56:49.695929 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 19:56:49.702941 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 19:56:49.706498 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 19:56:49.709679 1 6 8 | B1->B0 | 2727 4343 | 0 0 | (0 0) (0 0)
8347 19:56:49.715823 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8348 19:56:49.719188 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 19:56:49.722568 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 19:56:49.729226 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 19:56:49.733175 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 19:56:49.735847 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 19:56:49.742536 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 19:56:49.746232 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8355 19:56:49.749240 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8356 19:56:49.755751 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8357 19:56:49.759287 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 19:56:49.762459 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 19:56:49.769375 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 19:56:49.772709 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 19:56:49.775923 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 19:56:49.779154 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 19:56:49.786160 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 19:56:49.789352 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 19:56:49.792509 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 19:56:49.799412 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 19:56:49.802525 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 19:56:49.805994 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 19:56:49.812855 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 19:56:49.815915 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8371 19:56:49.819723 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 19:56:49.822906 Total UI for P1: 0, mck2ui 16
8373 19:56:49.825870 best dqsien dly found for B0: ( 1, 9, 8)
8374 19:56:49.829476 Total UI for P1: 0, mck2ui 16
8375 19:56:49.832548 best dqsien dly found for B1: ( 1, 9, 10)
8376 19:56:49.835696 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8377 19:56:49.839503 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8378 19:56:49.839616
8379 19:56:49.846162 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8380 19:56:49.849237 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8381 19:56:49.849348 [Gating] SW calibration Done
8382 19:56:49.852494 ==
8383 19:56:49.856052 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 19:56:49.858875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 19:56:49.858971 ==
8386 19:56:49.859075 RX Vref Scan: 0
8387 19:56:49.859181
8388 19:56:49.862180 RX Vref 0 -> 0, step: 1
8389 19:56:49.862283
8390 19:56:49.865589 RX Delay 0 -> 252, step: 8
8391 19:56:49.868979 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8392 19:56:49.872571 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8393 19:56:49.875804 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8394 19:56:49.882762 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8395 19:56:49.885962 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8396 19:56:49.888994 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8397 19:56:49.892106 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8398 19:56:49.895867 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8399 19:56:49.902324 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8400 19:56:49.905403 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8401 19:56:49.908993 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8402 19:56:49.912549 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8403 19:56:49.915373 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8404 19:56:49.922384 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8405 19:56:49.925632 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8406 19:56:49.928813 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8407 19:56:49.928910 ==
8408 19:56:49.932560 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 19:56:49.935528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 19:56:49.935611 ==
8411 19:56:49.939272 DQS Delay:
8412 19:56:49.939381 DQS0 = 0, DQS1 = 0
8413 19:56:49.942358 DQM Delay:
8414 19:56:49.942440 DQM0 = 136, DQM1 = 133
8415 19:56:49.942507 DQ Delay:
8416 19:56:49.945499 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8417 19:56:49.952587 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8418 19:56:49.955624 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8419 19:56:49.958743 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8420 19:56:49.958826
8421 19:56:49.958891
8422 19:56:49.958951 ==
8423 19:56:49.962047 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 19:56:49.965648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 19:56:49.965732 ==
8426 19:56:49.965797
8427 19:56:49.965859
8428 19:56:49.968669 TX Vref Scan disable
8429 19:56:49.972408 == TX Byte 0 ==
8430 19:56:49.975597 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8431 19:56:49.978613 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8432 19:56:49.981895 == TX Byte 1 ==
8433 19:56:49.985034 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8434 19:56:49.988392 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8435 19:56:49.988482 ==
8436 19:56:49.991950 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 19:56:49.995323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 19:56:49.998632 ==
8439 19:56:50.010692
8440 19:56:50.013904 TX Vref early break, caculate TX vref
8441 19:56:50.017160 TX Vref=16, minBit 1, minWin=22, winSum=379
8442 19:56:50.020145 TX Vref=18, minBit 1, minWin=23, winSum=395
8443 19:56:50.023603 TX Vref=20, minBit 1, minWin=23, winSum=401
8444 19:56:50.027073 TX Vref=22, minBit 0, minWin=23, winSum=403
8445 19:56:50.030411 TX Vref=24, minBit 0, minWin=25, winSum=420
8446 19:56:50.037449 TX Vref=26, minBit 0, minWin=25, winSum=424
8447 19:56:50.040495 TX Vref=28, minBit 2, minWin=25, winSum=429
8448 19:56:50.043759 TX Vref=30, minBit 2, minWin=25, winSum=422
8449 19:56:50.047478 TX Vref=32, minBit 0, minWin=24, winSum=415
8450 19:56:50.050557 TX Vref=34, minBit 0, minWin=24, winSum=408
8451 19:56:50.053789 TX Vref=36, minBit 2, minWin=23, winSum=395
8452 19:56:50.060250 [TxChooseVref] Worse bit 2, Min win 25, Win sum 429, Final Vref 28
8453 19:56:50.060938
8454 19:56:50.064108 Final TX Range 0 Vref 28
8455 19:56:50.064689
8456 19:56:50.065168 ==
8457 19:56:50.067040 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 19:56:50.070682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 19:56:50.071194 ==
8460 19:56:50.071785
8461 19:56:50.072381
8462 19:56:50.074113 TX Vref Scan disable
8463 19:56:50.080375 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8464 19:56:50.081085 == TX Byte 0 ==
8465 19:56:50.083970 u2DelayCellOfst[0]=17 cells (5 PI)
8466 19:56:50.087037 u2DelayCellOfst[1]=10 cells (3 PI)
8467 19:56:50.090877 u2DelayCellOfst[2]=0 cells (0 PI)
8468 19:56:50.093947 u2DelayCellOfst[3]=6 cells (2 PI)
8469 19:56:50.097389 u2DelayCellOfst[4]=6 cells (2 PI)
8470 19:56:50.100908 u2DelayCellOfst[5]=17 cells (5 PI)
8471 19:56:50.103675 u2DelayCellOfst[6]=17 cells (5 PI)
8472 19:56:50.107014 u2DelayCellOfst[7]=3 cells (1 PI)
8473 19:56:50.110529 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8474 19:56:50.113962 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8475 19:56:50.117134 == TX Byte 1 ==
8476 19:56:50.117606 u2DelayCellOfst[8]=0 cells (0 PI)
8477 19:56:50.120583 u2DelayCellOfst[9]=3 cells (1 PI)
8478 19:56:50.124373 u2DelayCellOfst[10]=13 cells (4 PI)
8479 19:56:50.127427 u2DelayCellOfst[11]=3 cells (1 PI)
8480 19:56:50.130488 u2DelayCellOfst[12]=17 cells (5 PI)
8481 19:56:50.134017 u2DelayCellOfst[13]=17 cells (5 PI)
8482 19:56:50.137453 u2DelayCellOfst[14]=17 cells (5 PI)
8483 19:56:50.140409 u2DelayCellOfst[15]=17 cells (5 PI)
8484 19:56:50.143837 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8485 19:56:50.150464 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8486 19:56:50.150895 DramC Write-DBI on
8487 19:56:50.151236 ==
8488 19:56:50.153564 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 19:56:50.157070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 19:56:50.160316 ==
8491 19:56:50.160745
8492 19:56:50.161084
8493 19:56:50.161399 TX Vref Scan disable
8494 19:56:50.164147 == TX Byte 0 ==
8495 19:56:50.167149 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8496 19:56:50.170312 == TX Byte 1 ==
8497 19:56:50.174147 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8498 19:56:50.177180 DramC Write-DBI off
8499 19:56:50.177623
8500 19:56:50.178076 [DATLAT]
8501 19:56:50.178527 Freq=1600, CH1 RK0
8502 19:56:50.179047
8503 19:56:50.180553 DATLAT Default: 0xf
8504 19:56:50.181168 0, 0xFFFF, sum = 0
8505 19:56:50.183554 1, 0xFFFF, sum = 0
8506 19:56:50.184178 2, 0xFFFF, sum = 0
8507 19:56:50.187122 3, 0xFFFF, sum = 0
8508 19:56:50.190187 4, 0xFFFF, sum = 0
8509 19:56:50.190687 5, 0xFFFF, sum = 0
8510 19:56:50.193977 6, 0xFFFF, sum = 0
8511 19:56:50.194383 7, 0xFFFF, sum = 0
8512 19:56:50.197295 8, 0xFFFF, sum = 0
8513 19:56:50.197746 9, 0xFFFF, sum = 0
8514 19:56:50.200436 10, 0xFFFF, sum = 0
8515 19:56:50.200882 11, 0xFFFF, sum = 0
8516 19:56:50.203503 12, 0xFFFF, sum = 0
8517 19:56:50.204107 13, 0xFFFF, sum = 0
8518 19:56:50.207148 14, 0x0, sum = 1
8519 19:56:50.207613 15, 0x0, sum = 2
8520 19:56:50.210223 16, 0x0, sum = 3
8521 19:56:50.210671 17, 0x0, sum = 4
8522 19:56:50.214110 best_step = 15
8523 19:56:50.214623
8524 19:56:50.215066 ==
8525 19:56:50.217067 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 19:56:50.220743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 19:56:50.221240 ==
8528 19:56:50.221688 RX Vref Scan: 1
8529 19:56:50.223437
8530 19:56:50.224021 Set Vref Range= 24 -> 127
8531 19:56:50.224415
8532 19:56:50.227450 RX Vref 24 -> 127, step: 1
8533 19:56:50.227971
8534 19:56:50.230384 RX Delay 27 -> 252, step: 4
8535 19:56:50.230909
8536 19:56:50.233549 Set Vref, RX VrefLevel [Byte0]: 24
8537 19:56:50.237192 [Byte1]: 24
8538 19:56:50.237767
8539 19:56:50.240323 Set Vref, RX VrefLevel [Byte0]: 25
8540 19:56:50.243769 [Byte1]: 25
8541 19:56:50.244272
8542 19:56:50.246743 Set Vref, RX VrefLevel [Byte0]: 26
8543 19:56:50.250442 [Byte1]: 26
8544 19:56:50.254119
8545 19:56:50.254539 Set Vref, RX VrefLevel [Byte0]: 27
8546 19:56:50.257237 [Byte1]: 27
8547 19:56:50.261542
8548 19:56:50.261959 Set Vref, RX VrefLevel [Byte0]: 28
8549 19:56:50.265100 [Byte1]: 28
8550 19:56:50.269033
8551 19:56:50.269530 Set Vref, RX VrefLevel [Byte0]: 29
8552 19:56:50.272171 [Byte1]: 29
8553 19:56:50.276490
8554 19:56:50.276940 Set Vref, RX VrefLevel [Byte0]: 30
8555 19:56:50.279624 [Byte1]: 30
8556 19:56:50.283911
8557 19:56:50.284439 Set Vref, RX VrefLevel [Byte0]: 31
8558 19:56:50.287334 [Byte1]: 31
8559 19:56:50.291759
8560 19:56:50.292169 Set Vref, RX VrefLevel [Byte0]: 32
8561 19:56:50.295189 [Byte1]: 32
8562 19:56:50.299107
8563 19:56:50.299544 Set Vref, RX VrefLevel [Byte0]: 33
8564 19:56:50.302794 [Byte1]: 33
8565 19:56:50.306433
8566 19:56:50.306925 Set Vref, RX VrefLevel [Byte0]: 34
8567 19:56:50.310100 [Byte1]: 34
8568 19:56:50.314530
8569 19:56:50.315030 Set Vref, RX VrefLevel [Byte0]: 35
8570 19:56:50.317700 [Byte1]: 35
8571 19:56:50.322075
8572 19:56:50.322501 Set Vref, RX VrefLevel [Byte0]: 36
8573 19:56:50.325212 [Byte1]: 36
8574 19:56:50.329552
8575 19:56:50.329989 Set Vref, RX VrefLevel [Byte0]: 37
8576 19:56:50.332435 [Byte1]: 37
8577 19:56:50.336743
8578 19:56:50.336826 Set Vref, RX VrefLevel [Byte0]: 38
8579 19:56:50.339657 [Byte1]: 38
8580 19:56:50.344492
8581 19:56:50.344908 Set Vref, RX VrefLevel [Byte0]: 39
8582 19:56:50.347565 [Byte1]: 39
8583 19:56:50.351940
8584 19:56:50.352379 Set Vref, RX VrefLevel [Byte0]: 40
8585 19:56:50.355341 [Byte1]: 40
8586 19:56:50.359465
8587 19:56:50.359989 Set Vref, RX VrefLevel [Byte0]: 41
8588 19:56:50.362512 [Byte1]: 41
8589 19:56:50.367473
8590 19:56:50.367924 Set Vref, RX VrefLevel [Byte0]: 42
8591 19:56:50.370516 [Byte1]: 42
8592 19:56:50.374449
8593 19:56:50.374942 Set Vref, RX VrefLevel [Byte0]: 43
8594 19:56:50.377500 [Byte1]: 43
8595 19:56:50.382087
8596 19:56:50.382592 Set Vref, RX VrefLevel [Byte0]: 44
8597 19:56:50.385267 [Byte1]: 44
8598 19:56:50.389641
8599 19:56:50.390133 Set Vref, RX VrefLevel [Byte0]: 45
8600 19:56:50.393054 [Byte1]: 45
8601 19:56:50.397173
8602 19:56:50.397686 Set Vref, RX VrefLevel [Byte0]: 46
8603 19:56:50.400716 [Byte1]: 46
8604 19:56:50.404439
8605 19:56:50.404896 Set Vref, RX VrefLevel [Byte0]: 47
8606 19:56:50.408165 [Byte1]: 47
8607 19:56:50.412565
8608 19:56:50.413140 Set Vref, RX VrefLevel [Byte0]: 48
8609 19:56:50.415576 [Byte1]: 48
8610 19:56:50.419928
8611 19:56:50.420375 Set Vref, RX VrefLevel [Byte0]: 49
8612 19:56:50.423084 [Byte1]: 49
8613 19:56:50.427417
8614 19:56:50.427907 Set Vref, RX VrefLevel [Byte0]: 50
8615 19:56:50.430805 [Byte1]: 50
8616 19:56:50.434572
8617 19:56:50.434990 Set Vref, RX VrefLevel [Byte0]: 51
8618 19:56:50.437960 [Byte1]: 51
8619 19:56:50.442524
8620 19:56:50.442989 Set Vref, RX VrefLevel [Byte0]: 52
8621 19:56:50.445677 [Byte1]: 52
8622 19:56:50.449999
8623 19:56:50.450468 Set Vref, RX VrefLevel [Byte0]: 53
8624 19:56:50.453126 [Byte1]: 53
8625 19:56:50.456990
8626 19:56:50.457546 Set Vref, RX VrefLevel [Byte0]: 54
8627 19:56:50.460642 [Byte1]: 54
8628 19:56:50.464830
8629 19:56:50.465394 Set Vref, RX VrefLevel [Byte0]: 55
8630 19:56:50.468271 [Byte1]: 55
8631 19:56:50.472264
8632 19:56:50.472684 Set Vref, RX VrefLevel [Byte0]: 56
8633 19:56:50.475828 [Byte1]: 56
8634 19:56:50.480332
8635 19:56:50.480755 Set Vref, RX VrefLevel [Byte0]: 57
8636 19:56:50.483106 [Byte1]: 57
8637 19:56:50.487393
8638 19:56:50.487869 Set Vref, RX VrefLevel [Byte0]: 58
8639 19:56:50.490588 [Byte1]: 58
8640 19:56:50.494434
8641 19:56:50.498046 Set Vref, RX VrefLevel [Byte0]: 59
8642 19:56:50.501605 [Byte1]: 59
8643 19:56:50.502030
8644 19:56:50.504589 Set Vref, RX VrefLevel [Byte0]: 60
8645 19:56:50.508081 [Byte1]: 60
8646 19:56:50.508629
8647 19:56:50.511308 Set Vref, RX VrefLevel [Byte0]: 61
8648 19:56:50.514237 [Byte1]: 61
8649 19:56:50.514653
8650 19:56:50.517837 Set Vref, RX VrefLevel [Byte0]: 62
8651 19:56:50.520963 [Byte1]: 62
8652 19:56:50.525412
8653 19:56:50.525960 Set Vref, RX VrefLevel [Byte0]: 63
8654 19:56:50.528612 [Byte1]: 63
8655 19:56:50.532465
8656 19:56:50.532886 Set Vref, RX VrefLevel [Byte0]: 64
8657 19:56:50.535707 [Byte1]: 64
8658 19:56:50.540145
8659 19:56:50.540579 Set Vref, RX VrefLevel [Byte0]: 65
8660 19:56:50.543298 [Byte1]: 65
8661 19:56:50.547614
8662 19:56:50.548073 Set Vref, RX VrefLevel [Byte0]: 66
8663 19:56:50.550763 [Byte1]: 66
8664 19:56:50.555227
8665 19:56:50.555779 Set Vref, RX VrefLevel [Byte0]: 67
8666 19:56:50.558498 [Byte1]: 67
8667 19:56:50.562735
8668 19:56:50.563295 Set Vref, RX VrefLevel [Byte0]: 68
8669 19:56:50.566117 [Byte1]: 68
8670 19:56:50.570479
8671 19:56:50.570925 Set Vref, RX VrefLevel [Byte0]: 69
8672 19:56:50.573675 [Byte1]: 69
8673 19:56:50.577833
8674 19:56:50.578260 Set Vref, RX VrefLevel [Byte0]: 70
8675 19:56:50.580860 [Byte1]: 70
8676 19:56:50.585018
8677 19:56:50.585523 Set Vref, RX VrefLevel [Byte0]: 71
8678 19:56:50.588302 [Byte1]: 71
8679 19:56:50.592883
8680 19:56:50.592966 Set Vref, RX VrefLevel [Byte0]: 72
8681 19:56:50.595883 [Byte1]: 72
8682 19:56:50.599890
8683 19:56:50.599973 Set Vref, RX VrefLevel [Byte0]: 73
8684 19:56:50.603306 [Byte1]: 73
8685 19:56:50.607527
8686 19:56:50.607622 Set Vref, RX VrefLevel [Byte0]: 74
8687 19:56:50.610823 [Byte1]: 74
8688 19:56:50.615266
8689 19:56:50.615369 Set Vref, RX VrefLevel [Byte0]: 75
8690 19:56:50.618415 [Byte1]: 75
8691 19:56:50.623035
8692 19:56:50.623148 Set Vref, RX VrefLevel [Byte0]: 76
8693 19:56:50.625921 [Byte1]: 76
8694 19:56:50.630340
8695 19:56:50.630462 Set Vref, RX VrefLevel [Byte0]: 77
8696 19:56:50.633650 [Byte1]: 77
8697 19:56:50.638037
8698 19:56:50.638185 Set Vref, RX VrefLevel [Byte0]: 78
8699 19:56:50.641246 [Byte1]: 78
8700 19:56:50.645516
8701 19:56:50.645699 Final RX Vref Byte 0 = 63 to rank0
8702 19:56:50.648732 Final RX Vref Byte 1 = 53 to rank0
8703 19:56:50.651936 Final RX Vref Byte 0 = 63 to rank1
8704 19:56:50.655743 Final RX Vref Byte 1 = 53 to rank1==
8705 19:56:50.659261 Dram Type= 6, Freq= 0, CH_1, rank 0
8706 19:56:50.665501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8707 19:56:50.665930 ==
8708 19:56:50.666284 DQS Delay:
8709 19:56:50.666599 DQS0 = 0, DQS1 = 0
8710 19:56:50.668519 DQM Delay:
8711 19:56:50.669103 DQM0 = 134, DQM1 = 130
8712 19:56:50.672553 DQ Delay:
8713 19:56:50.675404 DQ0 =140, DQ1 =128, DQ2 =120, DQ3 =130
8714 19:56:50.678937 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8715 19:56:50.682300 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8716 19:56:50.685520 DQ12 =138, DQ13 =136, DQ14 =140, DQ15 =140
8717 19:56:50.685981
8718 19:56:50.686322
8719 19:56:50.686637
8720 19:56:50.689032 [DramC_TX_OE_Calibration] TA2
8721 19:56:50.691955 Original DQ_B0 (3 6) =30, OEN = 27
8722 19:56:50.695363 Original DQ_B1 (3 6) =30, OEN = 27
8723 19:56:50.698959 24, 0x0, End_B0=24 End_B1=24
8724 19:56:50.699403 25, 0x0, End_B0=25 End_B1=25
8725 19:56:50.702177 26, 0x0, End_B0=26 End_B1=26
8726 19:56:50.705427 27, 0x0, End_B0=27 End_B1=27
8727 19:56:50.708513 28, 0x0, End_B0=28 End_B1=28
8728 19:56:50.708947 29, 0x0, End_B0=29 End_B1=29
8729 19:56:50.711929 30, 0x0, End_B0=30 End_B1=30
8730 19:56:50.715378 31, 0x5151, End_B0=30 End_B1=30
8731 19:56:50.718933 Byte0 end_step=30 best_step=27
8732 19:56:50.722536 Byte1 end_step=30 best_step=27
8733 19:56:50.725358 Byte0 TX OE(2T, 0.5T) = (3, 3)
8734 19:56:50.728507 Byte1 TX OE(2T, 0.5T) = (3, 3)
8735 19:56:50.729118
8736 19:56:50.729565
8737 19:56:50.735143 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8738 19:56:50.738759 CH1 RK0: MR19=303, MR18=1825
8739 19:56:50.745501 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8740 19:56:50.745931
8741 19:56:50.748645 ----->DramcWriteLeveling(PI) begin...
8742 19:56:50.749052 ==
8743 19:56:50.751785 Dram Type= 6, Freq= 0, CH_1, rank 1
8744 19:56:50.755580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 19:56:50.756048 ==
8746 19:56:50.758889 Write leveling (Byte 0): 27 => 27
8747 19:56:50.762000 Write leveling (Byte 1): 28 => 28
8748 19:56:50.765053 DramcWriteLeveling(PI) end<-----
8749 19:56:50.765502
8750 19:56:50.765880 ==
8751 19:56:50.768913 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 19:56:50.772197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8753 19:56:50.772815 ==
8754 19:56:50.775406 [Gating] SW mode calibration
8755 19:56:50.781872 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8756 19:56:50.788555 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8757 19:56:50.792022 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 19:56:50.795274 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 19:56:50.801700 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8760 19:56:50.805152 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8761 19:56:50.808481 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 19:56:50.814911 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 19:56:50.818611 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 19:56:50.821965 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 19:56:50.828657 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 19:56:50.831620 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8767 19:56:50.835336 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8768 19:56:50.841612 1 5 12 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
8769 19:56:50.845526 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 19:56:50.848596 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 19:56:50.855262 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 19:56:50.858096 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 19:56:50.861768 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 19:56:50.868248 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 19:56:50.871916 1 6 8 | B1->B0 | 4141 2424 | 0 0 | (1 1) (0 0)
8776 19:56:50.875205 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 19:56:50.882035 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 19:56:50.885170 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 19:56:50.888167 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 19:56:50.891909 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 19:56:50.898232 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 19:56:50.901733 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8783 19:56:50.904945 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8784 19:56:50.911911 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8785 19:56:50.914804 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8786 19:56:50.918248 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 19:56:50.925229 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 19:56:50.927894 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 19:56:50.931411 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 19:56:50.938254 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 19:56:50.941650 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 19:56:50.945048 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 19:56:50.951841 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 19:56:50.954881 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 19:56:50.958506 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 19:56:50.964735 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 19:56:50.968166 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 19:56:50.971094 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8799 19:56:50.977766 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8800 19:56:50.981595 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8801 19:56:50.984799 Total UI for P1: 0, mck2ui 16
8802 19:56:50.987965 best dqsien dly found for B1: ( 1, 9, 6)
8803 19:56:50.991604 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 19:56:50.994643 Total UI for P1: 0, mck2ui 16
8805 19:56:50.997965 best dqsien dly found for B0: ( 1, 9, 12)
8806 19:56:51.001158 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8807 19:56:51.004536 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8808 19:56:51.004961
8809 19:56:51.008309 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8810 19:56:51.014743 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8811 19:56:51.015172 [Gating] SW calibration Done
8812 19:56:51.015511 ==
8813 19:56:51.017887 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 19:56:51.024810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 19:56:51.025240 ==
8816 19:56:51.025579 RX Vref Scan: 0
8817 19:56:51.025894
8818 19:56:51.028295 RX Vref 0 -> 0, step: 1
8819 19:56:51.028719
8820 19:56:51.030993 RX Delay 0 -> 252, step: 8
8821 19:56:51.034825 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8822 19:56:51.037695 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8823 19:56:51.041059 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8824 19:56:51.047890 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8825 19:56:51.051294 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8826 19:56:51.054544 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8827 19:56:51.058143 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8828 19:56:51.061102 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8829 19:56:51.064837 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8830 19:56:51.071127 iDelay=208, Bit 9, Center 123 (64 ~ 183) 120
8831 19:56:51.074438 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8832 19:56:51.078025 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8833 19:56:51.081124 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8834 19:56:51.084584 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8835 19:56:51.091246 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8836 19:56:51.094704 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8837 19:56:51.095212 ==
8838 19:56:51.097922 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 19:56:51.100959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 19:56:51.101390 ==
8841 19:56:51.104177 DQS Delay:
8842 19:56:51.104603 DQS0 = 0, DQS1 = 0
8843 19:56:51.108076 DQM Delay:
8844 19:56:51.108499 DQM0 = 136, DQM1 = 134
8845 19:56:51.108897 DQ Delay:
8846 19:56:51.111295 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8847 19:56:51.114453 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8848 19:56:51.121217 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8849 19:56:51.125122 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8850 19:56:51.125551
8851 19:56:51.125885
8852 19:56:51.126195 ==
8853 19:56:51.127966 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 19:56:51.131405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 19:56:51.131940 ==
8856 19:56:51.132286
8857 19:56:51.132600
8858 19:56:51.134226 TX Vref Scan disable
8859 19:56:51.134656 == TX Byte 0 ==
8860 19:56:51.141269 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8861 19:56:51.144310 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8862 19:56:51.144737 == TX Byte 1 ==
8863 19:56:51.150943 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8864 19:56:51.154337 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8865 19:56:51.154765 ==
8866 19:56:51.157649 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 19:56:51.161031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 19:56:51.161459 ==
8869 19:56:51.175108
8870 19:56:51.178309 TX Vref early break, caculate TX vref
8871 19:56:51.181495 TX Vref=16, minBit 0, minWin=22, winSum=381
8872 19:56:51.184715 TX Vref=18, minBit 1, minWin=23, winSum=395
8873 19:56:51.188574 TX Vref=20, minBit 0, minWin=24, winSum=403
8874 19:56:51.191623 TX Vref=22, minBit 2, minWin=24, winSum=406
8875 19:56:51.195088 TX Vref=24, minBit 0, minWin=25, winSum=417
8876 19:56:51.201295 TX Vref=26, minBit 0, minWin=25, winSum=425
8877 19:56:51.204804 TX Vref=28, minBit 0, minWin=26, winSum=428
8878 19:56:51.207968 TX Vref=30, minBit 1, minWin=25, winSum=420
8879 19:56:51.211670 TX Vref=32, minBit 0, minWin=25, winSum=413
8880 19:56:51.214743 TX Vref=34, minBit 6, minWin=24, winSum=403
8881 19:56:51.221809 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8882 19:56:51.222231
8883 19:56:51.225067 Final TX Range 0 Vref 28
8884 19:56:51.225626
8885 19:56:51.226041 ==
8886 19:56:51.228087 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 19:56:51.231215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 19:56:51.231720 ==
8889 19:56:51.232065
8890 19:56:51.232404
8891 19:56:51.234613 TX Vref Scan disable
8892 19:56:51.241343 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8893 19:56:51.241763 == TX Byte 0 ==
8894 19:56:51.244905 u2DelayCellOfst[0]=17 cells (5 PI)
8895 19:56:51.247776 u2DelayCellOfst[1]=10 cells (3 PI)
8896 19:56:51.251476 u2DelayCellOfst[2]=0 cells (0 PI)
8897 19:56:51.254670 u2DelayCellOfst[3]=6 cells (2 PI)
8898 19:56:51.258316 u2DelayCellOfst[4]=6 cells (2 PI)
8899 19:56:51.261278 u2DelayCellOfst[5]=17 cells (5 PI)
8900 19:56:51.264359 u2DelayCellOfst[6]=17 cells (5 PI)
8901 19:56:51.264787 u2DelayCellOfst[7]=6 cells (2 PI)
8902 19:56:51.271422 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8903 19:56:51.274660 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8904 19:56:51.275212 == TX Byte 1 ==
8905 19:56:51.277982 u2DelayCellOfst[8]=0 cells (0 PI)
8906 19:56:51.281163 u2DelayCellOfst[9]=3 cells (1 PI)
8907 19:56:51.284572 u2DelayCellOfst[10]=10 cells (3 PI)
8908 19:56:51.287692 u2DelayCellOfst[11]=6 cells (2 PI)
8909 19:56:51.291363 u2DelayCellOfst[12]=13 cells (4 PI)
8910 19:56:51.294553 u2DelayCellOfst[13]=13 cells (4 PI)
8911 19:56:51.297692 u2DelayCellOfst[14]=17 cells (5 PI)
8912 19:56:51.301417 u2DelayCellOfst[15]=17 cells (5 PI)
8913 19:56:51.304371 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8914 19:56:51.308261 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8915 19:56:51.311420 DramC Write-DBI on
8916 19:56:51.311897 ==
8917 19:56:51.314356 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 19:56:51.318020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 19:56:51.318444 ==
8920 19:56:51.318780
8921 19:56:51.320853
8922 19:56:51.321270 TX Vref Scan disable
8923 19:56:51.324155 == TX Byte 0 ==
8924 19:56:51.327830 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8925 19:56:51.330992 == TX Byte 1 ==
8926 19:56:51.334257 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8927 19:56:51.334683 DramC Write-DBI off
8928 19:56:51.335019
8929 19:56:51.337435 [DATLAT]
8930 19:56:51.337955 Freq=1600, CH1 RK1
8931 19:56:51.338473
8932 19:56:51.341134 DATLAT Default: 0xf
8933 19:56:51.341737 0, 0xFFFF, sum = 0
8934 19:56:51.344750 1, 0xFFFF, sum = 0
8935 19:56:51.345367 2, 0xFFFF, sum = 0
8936 19:56:51.347625 3, 0xFFFF, sum = 0
8937 19:56:51.348119 4, 0xFFFF, sum = 0
8938 19:56:51.351343 5, 0xFFFF, sum = 0
8939 19:56:51.351815 6, 0xFFFF, sum = 0
8940 19:56:51.354448 7, 0xFFFF, sum = 0
8941 19:56:51.354875 8, 0xFFFF, sum = 0
8942 19:56:51.357559 9, 0xFFFF, sum = 0
8943 19:56:51.360895 10, 0xFFFF, sum = 0
8944 19:56:51.361320 11, 0xFFFF, sum = 0
8945 19:56:51.364153 12, 0xFFFF, sum = 0
8946 19:56:51.364581 13, 0xFFFF, sum = 0
8947 19:56:51.368039 14, 0x0, sum = 1
8948 19:56:51.368466 15, 0x0, sum = 2
8949 19:56:51.371102 16, 0x0, sum = 3
8950 19:56:51.371590 17, 0x0, sum = 4
8951 19:56:51.372060 best_step = 15
8952 19:56:51.374244
8953 19:56:51.374663 ==
8954 19:56:51.378035 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 19:56:51.380952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 19:56:51.381378 ==
8957 19:56:51.381713 RX Vref Scan: 0
8958 19:56:51.382027
8959 19:56:51.384298 RX Vref 0 -> 0, step: 1
8960 19:56:51.384910
8961 19:56:51.388078 RX Delay 19 -> 252, step: 4
8962 19:56:51.391098 iDelay=199, Bit 0, Center 140 (91 ~ 190) 100
8963 19:56:51.394326 iDelay=199, Bit 1, Center 132 (83 ~ 182) 100
8964 19:56:51.401156 iDelay=199, Bit 2, Center 122 (75 ~ 170) 96
8965 19:56:51.404379 iDelay=199, Bit 3, Center 130 (83 ~ 178) 96
8966 19:56:51.408155 iDelay=199, Bit 4, Center 130 (83 ~ 178) 96
8967 19:56:51.411140 iDelay=199, Bit 5, Center 148 (99 ~ 198) 100
8968 19:56:51.414293 iDelay=199, Bit 6, Center 146 (95 ~ 198) 104
8969 19:56:51.420666 iDelay=199, Bit 7, Center 134 (83 ~ 186) 104
8970 19:56:51.424569 iDelay=199, Bit 8, Center 116 (63 ~ 170) 108
8971 19:56:51.427617 iDelay=199, Bit 9, Center 120 (67 ~ 174) 108
8972 19:56:51.430712 iDelay=199, Bit 10, Center 132 (83 ~ 182) 100
8973 19:56:51.434183 iDelay=199, Bit 11, Center 126 (75 ~ 178) 104
8974 19:56:51.441052 iDelay=199, Bit 12, Center 140 (87 ~ 194) 108
8975 19:56:51.444137 iDelay=199, Bit 13, Center 138 (87 ~ 190) 104
8976 19:56:51.447115 iDelay=199, Bit 14, Center 136 (87 ~ 186) 100
8977 19:56:51.450257 iDelay=199, Bit 15, Center 140 (87 ~ 194) 108
8978 19:56:51.450687 ==
8979 19:56:51.454044 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 19:56:51.460682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 19:56:51.461116 ==
8982 19:56:51.461455 DQS Delay:
8983 19:56:51.464131 DQS0 = 0, DQS1 = 0
8984 19:56:51.464567 DQM Delay:
8985 19:56:51.464901 DQM0 = 135, DQM1 = 131
8986 19:56:51.467373 DQ Delay:
8987 19:56:51.470363 DQ0 =140, DQ1 =132, DQ2 =122, DQ3 =130
8988 19:56:51.473769 DQ4 =130, DQ5 =148, DQ6 =146, DQ7 =134
8989 19:56:51.477110 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =126
8990 19:56:51.480443 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8991 19:56:51.480864
8992 19:56:51.481196
8993 19:56:51.481505
8994 19:56:51.484057 [DramC_TX_OE_Calibration] TA2
8995 19:56:51.487197 Original DQ_B0 (3 6) =30, OEN = 27
8996 19:56:51.490120 Original DQ_B1 (3 6) =30, OEN = 27
8997 19:56:51.493745 24, 0x0, End_B0=24 End_B1=24
8998 19:56:51.496969 25, 0x0, End_B0=25 End_B1=25
8999 19:56:51.497408 26, 0x0, End_B0=26 End_B1=26
9000 19:56:51.500193 27, 0x0, End_B0=27 End_B1=27
9001 19:56:51.503285 28, 0x0, End_B0=28 End_B1=28
9002 19:56:51.507081 29, 0x0, End_B0=29 End_B1=29
9003 19:56:51.507507 30, 0x0, End_B0=30 End_B1=30
9004 19:56:51.510416 31, 0x4141, End_B0=30 End_B1=30
9005 19:56:51.513550 Byte0 end_step=30 best_step=27
9006 19:56:51.517060 Byte1 end_step=30 best_step=27
9007 19:56:51.520028 Byte0 TX OE(2T, 0.5T) = (3, 3)
9008 19:56:51.523842 Byte1 TX OE(2T, 0.5T) = (3, 3)
9009 19:56:51.524292
9010 19:56:51.524642
9011 19:56:51.530005 [DQSOSCAuto] RK1, (LSB)MR18= 0x2309, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9012 19:56:51.533124 CH1 RK1: MR19=303, MR18=2309
9013 19:56:51.540271 CH1_RK1: MR19=0x303, MR18=0x2309, DQSOSC=392, MR23=63, INC=24, DEC=16
9014 19:56:51.543294 [RxdqsGatingPostProcess] freq 1600
9015 19:56:51.546658 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9016 19:56:51.550060 best DQS0 dly(2T, 0.5T) = (1, 1)
9017 19:56:51.553630 best DQS1 dly(2T, 0.5T) = (1, 1)
9018 19:56:51.556520 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9019 19:56:51.559890 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9020 19:56:51.563015 best DQS0 dly(2T, 0.5T) = (1, 1)
9021 19:56:51.566529 best DQS1 dly(2T, 0.5T) = (1, 1)
9022 19:56:51.570183 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9023 19:56:51.573184 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9024 19:56:51.576528 Pre-setting of DQS Precalculation
9025 19:56:51.579592 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9026 19:56:51.586496 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9027 19:56:51.596679 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9028 19:56:51.597196
9029 19:56:51.597536
9030 19:56:51.599628 [Calibration Summary] 3200 Mbps
9031 19:56:51.600102 CH 0, Rank 0
9032 19:56:51.603243 SW Impedance : PASS
9033 19:56:51.603701 DUTY Scan : NO K
9034 19:56:51.606736 ZQ Calibration : PASS
9035 19:56:51.607154 Jitter Meter : NO K
9036 19:56:51.609857 CBT Training : PASS
9037 19:56:51.613138 Write leveling : PASS
9038 19:56:51.613563 RX DQS gating : PASS
9039 19:56:51.616302 RX DQ/DQS(RDDQC) : PASS
9040 19:56:51.620002 TX DQ/DQS : PASS
9041 19:56:51.620426 RX DATLAT : PASS
9042 19:56:51.623141 RX DQ/DQS(Engine): PASS
9043 19:56:51.626383 TX OE : PASS
9044 19:56:51.626808 All Pass.
9045 19:56:51.627144
9046 19:56:51.627460 CH 0, Rank 1
9047 19:56:51.629529 SW Impedance : PASS
9048 19:56:51.633367 DUTY Scan : NO K
9049 19:56:51.633789 ZQ Calibration : PASS
9050 19:56:51.636523 Jitter Meter : NO K
9051 19:56:51.639735 CBT Training : PASS
9052 19:56:51.640157 Write leveling : PASS
9053 19:56:51.642841 RX DQS gating : PASS
9054 19:56:51.646063 RX DQ/DQS(RDDQC) : PASS
9055 19:56:51.646484 TX DQ/DQS : PASS
9056 19:56:51.650027 RX DATLAT : PASS
9057 19:56:51.653003 RX DQ/DQS(Engine): PASS
9058 19:56:51.653446 TX OE : PASS
9059 19:56:51.653812 All Pass.
9060 19:56:51.654173
9061 19:56:51.656747 CH 1, Rank 0
9062 19:56:51.657191 SW Impedance : PASS
9063 19:56:51.660068 DUTY Scan : NO K
9064 19:56:51.662611 ZQ Calibration : PASS
9065 19:56:51.663065 Jitter Meter : NO K
9066 19:56:51.666444 CBT Training : PASS
9067 19:56:51.669413 Write leveling : PASS
9068 19:56:51.669832 RX DQS gating : PASS
9069 19:56:51.672946 RX DQ/DQS(RDDQC) : PASS
9070 19:56:51.676716 TX DQ/DQS : PASS
9071 19:56:51.677137 RX DATLAT : PASS
9072 19:56:51.679555 RX DQ/DQS(Engine): PASS
9073 19:56:51.682720 TX OE : PASS
9074 19:56:51.683158 All Pass.
9075 19:56:51.683495
9076 19:56:51.683887 CH 1, Rank 1
9077 19:56:51.686431 SW Impedance : PASS
9078 19:56:51.689415 DUTY Scan : NO K
9079 19:56:51.689865 ZQ Calibration : PASS
9080 19:56:51.693038 Jitter Meter : NO K
9081 19:56:51.695777 CBT Training : PASS
9082 19:56:51.696201 Write leveling : PASS
9083 19:56:51.699502 RX DQS gating : PASS
9084 19:56:51.702994 RX DQ/DQS(RDDQC) : PASS
9085 19:56:51.703427 TX DQ/DQS : PASS
9086 19:56:51.706086 RX DATLAT : PASS
9087 19:56:51.706521 RX DQ/DQS(Engine): PASS
9088 19:56:51.709167 TX OE : PASS
9089 19:56:51.709592 All Pass.
9090 19:56:51.709950
9091 19:56:51.712926 DramC Write-DBI on
9092 19:56:51.716030 PER_BANK_REFRESH: Hybrid Mode
9093 19:56:51.716481 TX_TRACKING: ON
9094 19:56:51.725941 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9095 19:56:51.732308 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9096 19:56:51.742481 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9097 19:56:51.745682 [FAST_K] Save calibration result to emmc
9098 19:56:51.748992 sync common calibartion params.
9099 19:56:51.749415 sync cbt_mode0:1, 1:1
9100 19:56:51.752799 dram_init: ddr_geometry: 2
9101 19:56:51.755975 dram_init: ddr_geometry: 2
9102 19:56:51.756398 dram_init: ddr_geometry: 2
9103 19:56:51.759541 0:dram_rank_size:100000000
9104 19:56:51.762340 1:dram_rank_size:100000000
9105 19:56:51.766007 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9106 19:56:51.769069 DFS_SHUFFLE_HW_MODE: ON
9107 19:56:51.772161 dramc_set_vcore_voltage set vcore to 725000
9108 19:56:51.775436 Read voltage for 1600, 0
9109 19:56:51.775925 Vio18 = 0
9110 19:56:51.778995 Vcore = 725000
9111 19:56:51.779415 Vdram = 0
9112 19:56:51.779793 Vddq = 0
9113 19:56:51.780113 Vmddr = 0
9114 19:56:51.782292 switch to 3200 Mbps bootup
9115 19:56:51.785819 [DramcRunTimeConfig]
9116 19:56:51.786241 PHYPLL
9117 19:56:51.788810 DPM_CONTROL_AFTERK: ON
9118 19:56:51.789232 PER_BANK_REFRESH: ON
9119 19:56:51.791931 REFRESH_OVERHEAD_REDUCTION: ON
9120 19:56:51.795428 CMD_PICG_NEW_MODE: OFF
9121 19:56:51.795881 XRTWTW_NEW_MODE: ON
9122 19:56:51.798870 XRTRTR_NEW_MODE: ON
9123 19:56:51.799533 TX_TRACKING: ON
9124 19:56:51.802311 RDSEL_TRACKING: OFF
9125 19:56:51.805785 DQS Precalculation for DVFS: ON
9126 19:56:51.806213 RX_TRACKING: OFF
9127 19:56:51.808492 HW_GATING DBG: ON
9128 19:56:51.808930 ZQCS_ENABLE_LP4: ON
9129 19:56:51.812136 RX_PICG_NEW_MODE: ON
9130 19:56:51.812727 TX_PICG_NEW_MODE: ON
9131 19:56:51.815351 ENABLE_RX_DCM_DPHY: ON
9132 19:56:51.818562 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9133 19:56:51.821866 DUMMY_READ_FOR_TRACKING: OFF
9134 19:56:51.822323 !!! SPM_CONTROL_AFTERK: OFF
9135 19:56:51.825544 !!! SPM could not control APHY
9136 19:56:51.829072 IMPEDANCE_TRACKING: ON
9137 19:56:51.829527 TEMP_SENSOR: ON
9138 19:56:51.832087 HW_SAVE_FOR_SR: OFF
9139 19:56:51.835575 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9140 19:56:51.838352 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9141 19:56:51.838844 Read ODT Tracking: ON
9142 19:56:51.841937 Refresh Rate DeBounce: ON
9143 19:56:51.845133 DFS_NO_QUEUE_FLUSH: ON
9144 19:56:51.848569 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9145 19:56:51.849008 ENABLE_DFS_RUNTIME_MRW: OFF
9146 19:56:51.851571 DDR_RESERVE_NEW_MODE: ON
9147 19:56:51.854798 MR_CBT_SWITCH_FREQ: ON
9148 19:56:51.855296 =========================
9149 19:56:51.875561 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9150 19:56:51.878840 dram_init: ddr_geometry: 2
9151 19:56:51.896765 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9152 19:56:51.899993 dram_init: dram init end (result: 0)
9153 19:56:51.906999 DRAM-K: Full calibration passed in 24449 msecs
9154 19:56:51.910263 MRC: failed to locate region type 0.
9155 19:56:51.910693 DRAM rank0 size:0x100000000,
9156 19:56:51.913637 DRAM rank1 size=0x100000000
9157 19:56:51.923496 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9158 19:56:51.930422 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9159 19:56:51.936795 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9160 19:56:51.943528 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9161 19:56:51.947344 DRAM rank0 size:0x100000000,
9162 19:56:51.950300 DRAM rank1 size=0x100000000
9163 19:56:51.950726 CBMEM:
9164 19:56:51.953646 IMD: root @ 0xfffff000 254 entries.
9165 19:56:51.956847 IMD: root @ 0xffffec00 62 entries.
9166 19:56:51.960111 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9167 19:56:51.963697 WARNING: RO_VPD is uninitialized or empty.
9168 19:56:51.969792 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9169 19:56:51.976859 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9170 19:56:51.989374 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9171 19:56:52.000870 BS: romstage times (exec / console): total (unknown) / 23985 ms
9172 19:56:52.000955
9173 19:56:52.001021
9174 19:56:52.010848 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9175 19:56:52.014158 ARM64: Exception handlers installed.
9176 19:56:52.017300 ARM64: Testing exception
9177 19:56:52.020396 ARM64: Done test exception
9178 19:56:52.020498 Enumerating buses...
9179 19:56:52.023790 Show all devs... Before device enumeration.
9180 19:56:52.027070 Root Device: enabled 1
9181 19:56:52.030653 CPU_CLUSTER: 0: enabled 1
9182 19:56:52.030776 CPU: 00: enabled 1
9183 19:56:52.034204 Compare with tree...
9184 19:56:52.034339 Root Device: enabled 1
9185 19:56:52.037669 CPU_CLUSTER: 0: enabled 1
9186 19:56:52.040545 CPU: 00: enabled 1
9187 19:56:52.040697 Root Device scanning...
9188 19:56:52.044685 scan_static_bus for Root Device
9189 19:56:52.047503 CPU_CLUSTER: 0 enabled
9190 19:56:52.050690 scan_static_bus for Root Device done
9191 19:56:52.054243 scan_bus: bus Root Device finished in 8 msecs
9192 19:56:52.054537 done
9193 19:56:52.061030 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9194 19:56:52.064480 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9195 19:56:52.070798 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9196 19:56:52.074132 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9197 19:56:52.077415 Allocating resources...
9198 19:56:52.080683 Reading resources...
9199 19:56:52.084040 Root Device read_resources bus 0 link: 0
9200 19:56:52.084464 DRAM rank0 size:0x100000000,
9201 19:56:52.087632 DRAM rank1 size=0x100000000
9202 19:56:52.090820 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9203 19:56:52.094044 CPU: 00 missing read_resources
9204 19:56:52.097186 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9205 19:56:52.104468 Root Device read_resources bus 0 link: 0 done
9206 19:56:52.104893 Done reading resources.
9207 19:56:52.110832 Show resources in subtree (Root Device)...After reading.
9208 19:56:52.113823 Root Device child on link 0 CPU_CLUSTER: 0
9209 19:56:52.117714 CPU_CLUSTER: 0 child on link 0 CPU: 00
9210 19:56:52.127261 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9211 19:56:52.127716 CPU: 00
9212 19:56:52.130322 Root Device assign_resources, bus 0 link: 0
9213 19:56:52.133889 CPU_CLUSTER: 0 missing set_resources
9214 19:56:52.140322 Root Device assign_resources, bus 0 link: 0 done
9215 19:56:52.140745 Done setting resources.
9216 19:56:52.147134 Show resources in subtree (Root Device)...After assigning values.
9217 19:56:52.150868 Root Device child on link 0 CPU_CLUSTER: 0
9218 19:56:52.153655 CPU_CLUSTER: 0 child on link 0 CPU: 00
9219 19:56:52.163875 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9220 19:56:52.164337 CPU: 00
9221 19:56:52.167212 Done allocating resources.
9222 19:56:52.170488 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9223 19:56:52.173524 Enabling resources...
9224 19:56:52.174049 done.
9225 19:56:52.180189 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9226 19:56:52.180637 Initializing devices...
9227 19:56:52.183754 Root Device init
9228 19:56:52.184176 init hardware done!
9229 19:56:52.186883 0x00000018: ctrlr->caps
9230 19:56:52.190330 52.000 MHz: ctrlr->f_max
9231 19:56:52.190788 0.400 MHz: ctrlr->f_min
9232 19:56:52.193693 0x40ff8080: ctrlr->voltages
9233 19:56:52.194122 sclk: 390625
9234 19:56:52.197251 Bus Width = 1
9235 19:56:52.197673 sclk: 390625
9236 19:56:52.200534 Bus Width = 1
9237 19:56:52.200952 Early init status = 3
9238 19:56:52.206772 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9239 19:56:52.210086 in-header: 03 fc 00 00 01 00 00 00
9240 19:56:52.214006 in-data: 00
9241 19:56:52.216985 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9242 19:56:52.221659 in-header: 03 fd 00 00 00 00 00 00
9243 19:56:52.224992 in-data:
9244 19:56:52.228135 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9245 19:56:52.232640 in-header: 03 fc 00 00 01 00 00 00
9246 19:56:52.235703 in-data: 00
9247 19:56:52.239269 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9248 19:56:52.244971 in-header: 03 fd 00 00 00 00 00 00
9249 19:56:52.247825 in-data:
9250 19:56:52.251591 [SSUSB] Setting up USB HOST controller...
9251 19:56:52.254804 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9252 19:56:52.257911 [SSUSB] phy power-on done.
9253 19:56:52.261463 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9254 19:56:52.267748 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9255 19:56:52.271501 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9256 19:56:52.277794 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9257 19:56:52.284588 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9258 19:56:52.291282 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9259 19:56:52.298000 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9260 19:56:52.304705 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9261 19:56:52.307749 SPM: binary array size = 0x9dc
9262 19:56:52.311300 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9263 19:56:52.318138 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9264 19:56:52.324147 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9265 19:56:52.327778 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9266 19:56:52.334301 configure_display: Starting display init
9267 19:56:52.367931 anx7625_power_on_init: Init interface.
9268 19:56:52.371219 anx7625_disable_pd_protocol: Disabled PD feature.
9269 19:56:52.374976 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9270 19:56:52.402416 anx7625_start_dp_work: Secure OCM version=00
9271 19:56:52.406067 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9272 19:56:52.420615 sp_tx_get_edid_block: EDID Block = 1
9273 19:56:52.522987 Extracted contents:
9274 19:56:52.526695 header: 00 ff ff ff ff ff ff 00
9275 19:56:52.529846 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9276 19:56:52.533055 version: 01 04
9277 19:56:52.536188 basic params: 95 1f 11 78 0a
9278 19:56:52.539449 chroma info: 76 90 94 55 54 90 27 21 50 54
9279 19:56:52.543237 established: 00 00 00
9280 19:56:52.549392 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9281 19:56:52.552910 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9282 19:56:52.559600 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9283 19:56:52.566171 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9284 19:56:52.572692 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9285 19:56:52.576103 extensions: 00
9286 19:56:52.576545 checksum: fb
9287 19:56:52.576978
9288 19:56:52.579316 Manufacturer: IVO Model 57d Serial Number 0
9289 19:56:52.582319 Made week 0 of 2020
9290 19:56:52.582749 EDID version: 1.4
9291 19:56:52.586092 Digital display
9292 19:56:52.589679 6 bits per primary color channel
9293 19:56:52.590112 DisplayPort interface
9294 19:56:52.593063 Maximum image size: 31 cm x 17 cm
9295 19:56:52.596492 Gamma: 220%
9296 19:56:52.596919 Check DPMS levels
9297 19:56:52.599664 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9298 19:56:52.602630 First detailed timing is preferred timing
9299 19:56:52.606159 Established timings supported:
9300 19:56:52.608962 Standard timings supported:
9301 19:56:52.612949 Detailed timings
9302 19:56:52.616180 Hex of detail: 383680a07038204018303c0035ae10000019
9303 19:56:52.619157 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9304 19:56:52.626366 0780 0798 07c8 0820 hborder 0
9305 19:56:52.629532 0438 043b 0447 0458 vborder 0
9306 19:56:52.632734 -hsync -vsync
9307 19:56:52.633159 Did detailed timing
9308 19:56:52.636299 Hex of detail: 000000000000000000000000000000000000
9309 19:56:52.639558 Manufacturer-specified data, tag 0
9310 19:56:52.645798 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9311 19:56:52.646220 ASCII string: InfoVision
9312 19:56:52.652707 Hex of detail: 000000fe00523134304e574635205248200a
9313 19:56:52.655671 ASCII string: R140NWF5 RH
9314 19:56:52.656095 Checksum
9315 19:56:52.656429 Checksum: 0xfb (valid)
9316 19:56:52.662418 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9317 19:56:52.665390 DSI data_rate: 832800000 bps
9318 19:56:52.669302 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9319 19:56:52.676172 anx7625_parse_edid: pixelclock(138800).
9320 19:56:52.678886 hactive(1920), hsync(48), hfp(24), hbp(88)
9321 19:56:52.682431 vactive(1080), vsync(12), vfp(3), vbp(17)
9322 19:56:52.685437 anx7625_dsi_config: config dsi.
9323 19:56:52.692286 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9324 19:56:52.704945 anx7625_dsi_config: success to config DSI
9325 19:56:52.708845 anx7625_dp_start: MIPI phy setup OK.
9326 19:56:52.711891 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9327 19:56:52.714971 mtk_ddp_mode_set invalid vrefresh 60
9328 19:56:52.718689 main_disp_path_setup
9329 19:56:52.719152 ovl_layer_smi_id_en
9330 19:56:52.721855 ovl_layer_smi_id_en
9331 19:56:52.722277 ccorr_config
9332 19:56:52.722613 aal_config
9333 19:56:52.724937 gamma_config
9334 19:56:52.725360 postmask_config
9335 19:56:52.728515 dither_config
9336 19:56:52.731519 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9337 19:56:52.738290 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9338 19:56:52.741502 Root Device init finished in 555 msecs
9339 19:56:52.741925 CPU_CLUSTER: 0 init
9340 19:56:52.751763 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9341 19:56:52.755022 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9342 19:56:52.758819 APU_MBOX 0x190000b0 = 0x10001
9343 19:56:52.761778 APU_MBOX 0x190001b0 = 0x10001
9344 19:56:52.765423 APU_MBOX 0x190005b0 = 0x10001
9345 19:56:52.768624 APU_MBOX 0x190006b0 = 0x10001
9346 19:56:52.771804 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9347 19:56:52.784256 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9348 19:56:52.796471 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9349 19:56:52.802857 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9350 19:56:52.814712 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9351 19:56:52.823753 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9352 19:56:52.826967 CPU_CLUSTER: 0 init finished in 81 msecs
9353 19:56:52.830745 Devices initialized
9354 19:56:52.833974 Show all devs... After init.
9355 19:56:52.834434 Root Device: enabled 1
9356 19:56:52.837732 CPU_CLUSTER: 0: enabled 1
9357 19:56:52.840178 CPU: 00: enabled 1
9358 19:56:52.844181 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9359 19:56:52.847280 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9360 19:56:52.850602 ELOG: NV offset 0x57f000 size 0x1000
9361 19:56:52.857199 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9362 19:56:52.864040 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9363 19:56:52.867197 ELOG: Event(17) added with size 13 at 2023-10-28 19:55:18 UTC
9364 19:56:52.870311 out: cmd=0x121: 03 db 21 01 00 00 00 00
9365 19:56:52.874188 in-header: 03 e5 00 00 2c 00 00 00
9366 19:56:52.887461 in-data: 7a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9367 19:56:52.893745 ELOG: Event(A1) added with size 10 at 2023-10-28 19:55:18 UTC
9368 19:56:52.900513 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9369 19:56:52.906831 ELOG: Event(A0) added with size 9 at 2023-10-28 19:55:18 UTC
9370 19:56:52.910407 elog_add_boot_reason: Logged dev mode boot
9371 19:56:52.913570 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9372 19:56:52.916924 Finalize devices...
9373 19:56:52.917028 Devices finalized
9374 19:56:52.923706 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9375 19:56:52.926793 Writing coreboot table at 0xffe64000
9376 19:56:52.930615 0. 000000000010a000-0000000000113fff: RAMSTAGE
9377 19:56:52.933521 1. 0000000040000000-00000000400fffff: RAM
9378 19:56:52.936952 2. 0000000040100000-000000004032afff: RAMSTAGE
9379 19:56:52.943656 3. 000000004032b000-00000000545fffff: RAM
9380 19:56:52.947347 4. 0000000054600000-000000005465ffff: BL31
9381 19:56:52.950271 5. 0000000054660000-00000000ffe63fff: RAM
9382 19:56:52.953748 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9383 19:56:52.960476 7. 0000000100000000-000000023fffffff: RAM
9384 19:56:52.960878 Passing 5 GPIOs to payload:
9385 19:56:52.967597 NAME | PORT | POLARITY | VALUE
9386 19:56:52.970709 EC in RW | 0x000000aa | low | undefined
9387 19:56:52.976851 EC interrupt | 0x00000005 | low | undefined
9388 19:56:52.980617 TPM interrupt | 0x000000ab | high | undefined
9389 19:56:52.983561 SD card detect | 0x00000011 | high | undefined
9390 19:56:52.990472 speaker enable | 0x00000093 | high | undefined
9391 19:56:52.993506 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9392 19:56:52.997454 in-header: 03 f9 00 00 02 00 00 00
9393 19:56:52.997977 in-data: 02 00
9394 19:56:53.000276 ADC[4]: Raw value=904726 ID=7
9395 19:56:53.003918 ADC[3]: Raw value=213441 ID=1
9396 19:56:53.004511 RAM Code: 0x71
9397 19:56:53.006914 ADC[6]: Raw value=75701 ID=0
9398 19:56:53.010634 ADC[5]: Raw value=212703 ID=1
9399 19:56:53.011060 SKU Code: 0x1
9400 19:56:53.017445 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b7d7
9401 19:56:53.020587 coreboot table: 964 bytes.
9402 19:56:53.023681 IMD ROOT 0. 0xfffff000 0x00001000
9403 19:56:53.027378 IMD SMALL 1. 0xffffe000 0x00001000
9404 19:56:53.030404 RO MCACHE 2. 0xffffc000 0x00001104
9405 19:56:53.033564 CONSOLE 3. 0xfff7c000 0x00080000
9406 19:56:53.037010 FMAP 4. 0xfff7b000 0x00000452
9407 19:56:53.040706 TIME STAMP 5. 0xfff7a000 0x00000910
9408 19:56:53.043575 VBOOT WORK 6. 0xfff66000 0x00014000
9409 19:56:53.047128 RAMOOPS 7. 0xffe66000 0x00100000
9410 19:56:53.050553 COREBOOT 8. 0xffe64000 0x00002000
9411 19:56:53.050976 IMD small region:
9412 19:56:53.053632 IMD ROOT 0. 0xffffec00 0x00000400
9413 19:56:53.057162 VPD 1. 0xffffeb80 0x0000006c
9414 19:56:53.060284 MMC STATUS 2. 0xffffeb60 0x00000004
9415 19:56:53.067542 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9416 19:56:53.068020 Probing TPM: done!
9417 19:56:53.074190 Connected to device vid:did:rid of 1ae0:0028:00
9418 19:56:53.080727 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9419 19:56:53.084042 Initialized TPM device CR50 revision 0
9420 19:56:53.087469 Checking cr50 for pending updates
9421 19:56:53.093498 Reading cr50 TPM mode
9422 19:56:53.102608 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9423 19:56:53.109470 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9424 19:56:53.149140 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9425 19:56:53.152701 Checking segment from ROM address 0x40100000
9426 19:56:53.155682 Checking segment from ROM address 0x4010001c
9427 19:56:53.162738 Loading segment from ROM address 0x40100000
9428 19:56:53.163295 code (compression=0)
9429 19:56:53.169423 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9430 19:56:53.179538 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9431 19:56:53.180075 it's not compressed!
9432 19:56:53.186365 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9433 19:56:53.189429 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9434 19:56:53.209600 Loading segment from ROM address 0x4010001c
9435 19:56:53.210042 Entry Point 0x80000000
9436 19:56:53.212730 Loaded segments
9437 19:56:53.215993 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9438 19:56:53.222522 Jumping to boot code at 0x80000000(0xffe64000)
9439 19:56:53.229221 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9440 19:56:53.236103 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9441 19:56:53.244132 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9442 19:56:53.247308 Checking segment from ROM address 0x40100000
9443 19:56:53.250833 Checking segment from ROM address 0x4010001c
9444 19:56:53.257250 Loading segment from ROM address 0x40100000
9445 19:56:53.257759 code (compression=1)
9446 19:56:53.263968 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9447 19:56:53.273913 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9448 19:56:53.274358 using LZMA
9449 19:56:53.282446 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9450 19:56:53.289153 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9451 19:56:53.292163 Loading segment from ROM address 0x4010001c
9452 19:56:53.292730 Entry Point 0x54601000
9453 19:56:53.295422 Loaded segments
9454 19:56:53.298603 NOTICE: MT8192 bl31_setup
9455 19:56:53.306121 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9456 19:56:53.309009 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9457 19:56:53.312328 WARNING: region 0:
9458 19:56:53.315907 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 19:56:53.316350 WARNING: region 1:
9460 19:56:53.322571 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9461 19:56:53.325985 WARNING: region 2:
9462 19:56:53.329358 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9463 19:56:53.332686 WARNING: region 3:
9464 19:56:53.335720 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9465 19:56:53.339171 WARNING: region 4:
9466 19:56:53.345818 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9467 19:56:53.346243 WARNING: region 5:
9468 19:56:53.349337 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 19:56:53.352524 WARNING: region 6:
9470 19:56:53.356221 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 19:56:53.356645 WARNING: region 7:
9472 19:56:53.362387 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 19:56:53.369295 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9474 19:56:53.372824 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9475 19:56:53.375768 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9476 19:56:53.382818 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9477 19:56:53.386338 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9478 19:56:53.389553 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9479 19:56:53.395804 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9480 19:56:53.399033 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9481 19:56:53.405989 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9482 19:56:53.409142 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9483 19:56:53.413075 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9484 19:56:53.419197 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9485 19:56:53.423037 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9486 19:56:53.426160 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9487 19:56:53.432696 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9488 19:56:53.436217 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9489 19:56:53.439554 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9490 19:56:53.446104 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9491 19:56:53.449149 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9492 19:56:53.452912 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9493 19:56:53.459005 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9494 19:56:53.462711 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9495 19:56:53.469390 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9496 19:56:53.472961 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9497 19:56:53.476041 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9498 19:56:53.482751 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9499 19:56:53.486475 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9500 19:56:53.492870 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9501 19:56:53.496566 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9502 19:56:53.499622 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9503 19:56:53.506543 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9504 19:56:53.509688 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9505 19:56:53.512886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9506 19:56:53.519461 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9507 19:56:53.522746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9508 19:56:53.525873 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9509 19:56:53.529104 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9510 19:56:53.535519 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9511 19:56:53.539428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9512 19:56:53.542859 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9513 19:56:53.545805 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9514 19:56:53.552347 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9515 19:56:53.555938 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9516 19:56:53.559428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9517 19:56:53.562652 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9518 19:56:53.569246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9519 19:56:53.572672 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9520 19:56:53.576087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9521 19:56:53.582877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9522 19:56:53.586253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9523 19:56:53.589577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9524 19:56:53.596018 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9525 19:56:53.599734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9526 19:56:53.606448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9527 19:56:53.609557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9528 19:56:53.616260 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9529 19:56:53.619438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9530 19:56:53.623328 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9531 19:56:53.629680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9532 19:56:53.632853 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9533 19:56:53.639779 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9534 19:56:53.642852 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9535 19:56:53.649855 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9536 19:56:53.653046 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9537 19:56:53.656273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9538 19:56:53.662969 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9539 19:56:53.666732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9540 19:56:53.673510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9541 19:56:53.676792 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9542 19:56:53.680256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9543 19:56:53.686938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9544 19:56:53.690050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9545 19:56:53.696601 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9546 19:56:53.699585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9547 19:56:53.706369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9548 19:56:53.709456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9549 19:56:53.713252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9550 19:56:53.719401 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9551 19:56:53.723248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9552 19:56:53.729534 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9553 19:56:53.733181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9554 19:56:53.739788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9555 19:56:53.743046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9556 19:56:53.750163 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9557 19:56:53.753122 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9558 19:56:53.756112 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9559 19:56:53.763134 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9560 19:56:53.766330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9561 19:56:53.773214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9562 19:56:53.776668 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9563 19:56:53.780488 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9564 19:56:53.786939 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9565 19:56:53.789872 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9566 19:56:53.796435 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9567 19:56:53.799572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9568 19:56:53.806476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9569 19:56:53.809971 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9570 19:56:53.812727 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9571 19:56:53.819623 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9572 19:56:53.823418 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9573 19:56:53.826518 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9574 19:56:53.829661 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9575 19:56:53.836927 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9576 19:56:53.839876 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9577 19:56:53.846397 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9578 19:56:53.849904 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9579 19:56:53.853079 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9580 19:56:53.860100 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9581 19:56:53.863184 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9582 19:56:53.870146 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9583 19:56:53.873359 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9584 19:56:53.876980 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9585 19:56:53.883157 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9586 19:56:53.886930 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9587 19:56:53.893275 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9588 19:56:53.896783 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9589 19:56:53.900232 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9590 19:56:53.903319 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9591 19:56:53.910235 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9592 19:56:53.913289 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9593 19:56:53.916675 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9594 19:56:53.919793 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9595 19:56:53.926589 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9596 19:56:53.929999 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9597 19:56:53.933176 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9598 19:56:53.940094 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9599 19:56:53.943813 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9600 19:56:53.950472 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9601 19:56:53.953564 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9602 19:56:53.956683 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9603 19:56:53.964419 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9604 19:56:53.966964 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9605 19:56:53.970090 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9606 19:56:53.977088 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9607 19:56:53.980121 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9608 19:56:53.986599 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9609 19:56:53.989842 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9610 19:56:53.993178 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9611 19:56:53.999972 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9612 19:56:54.003505 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9613 19:56:54.006632 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9614 19:56:54.013501 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9615 19:56:54.017139 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9616 19:56:54.023143 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9617 19:56:54.026893 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9618 19:56:54.030082 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9619 19:56:54.036654 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9620 19:56:54.040004 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9621 19:56:54.046622 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9622 19:56:54.050461 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9623 19:56:54.053450 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9624 19:56:54.060261 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9625 19:56:54.063567 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9626 19:56:54.066820 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9627 19:56:54.073526 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9628 19:56:54.077208 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9629 19:56:54.083537 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9630 19:56:54.086639 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9631 19:56:54.090369 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9632 19:56:54.097230 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9633 19:56:54.100267 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9634 19:56:54.103352 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9635 19:56:54.110110 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9636 19:56:54.113677 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9637 19:56:54.120087 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9638 19:56:54.123546 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9639 19:56:54.126713 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9640 19:56:54.133650 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9641 19:56:54.136875 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9642 19:56:54.143666 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9643 19:56:54.146603 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9644 19:56:54.149998 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9645 19:56:54.156715 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9646 19:56:54.160379 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9647 19:56:54.166997 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9648 19:56:54.170224 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9649 19:56:54.173511 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9650 19:56:54.180480 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9651 19:56:54.183442 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9652 19:56:54.187072 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9653 19:56:54.193465 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9654 19:56:54.197217 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9655 19:56:54.203725 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9656 19:56:54.206958 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9657 19:56:54.210653 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9658 19:56:54.216853 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9659 19:56:54.220341 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9660 19:56:54.227014 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9661 19:56:54.230592 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9662 19:56:54.233540 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9663 19:56:54.240600 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9664 19:56:54.243942 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9665 19:56:54.250240 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9666 19:56:54.253459 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9667 19:56:54.257183 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9668 19:56:54.263350 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9669 19:56:54.266884 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9670 19:56:54.273197 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9671 19:56:54.276851 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9672 19:56:54.283004 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9673 19:56:54.286888 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9674 19:56:54.289945 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9675 19:56:54.296474 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9676 19:56:54.299812 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9677 19:56:54.306163 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9678 19:56:54.309918 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9679 19:56:54.316357 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9680 19:56:54.320017 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9681 19:56:54.323061 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9682 19:56:54.329760 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9683 19:56:54.333149 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9684 19:56:54.339576 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9685 19:56:54.342828 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9686 19:56:54.349861 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9687 19:56:54.352928 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9688 19:56:54.356651 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9689 19:56:54.363795 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9690 19:56:54.366519 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9691 19:56:54.373428 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9692 19:56:54.376659 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9693 19:56:54.380013 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9694 19:56:54.386551 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9695 19:56:54.389601 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9696 19:56:54.396196 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9697 19:56:54.399950 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9698 19:56:54.403125 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9699 19:56:54.409687 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9700 19:56:54.413304 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9701 19:56:54.419608 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9702 19:56:54.422621 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9703 19:56:54.426117 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9704 19:56:54.429453 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9705 19:56:54.432594 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9706 19:56:54.439548 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9707 19:56:54.442823 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9708 19:56:54.449743 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9709 19:56:54.453630 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9710 19:56:54.456098 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9711 19:56:54.459741 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9712 19:56:54.466211 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9713 19:56:54.469373 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9714 19:56:54.476294 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9715 19:56:54.479425 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9716 19:56:54.482616 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9717 19:56:54.489618 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9718 19:56:54.492722 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9719 19:56:54.499529 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9720 19:56:54.502558 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9721 19:56:54.506005 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9722 19:56:54.512334 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9723 19:56:54.515615 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9724 19:56:54.518779 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9725 19:56:54.525595 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9726 19:56:54.528730 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9727 19:56:54.532545 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9728 19:56:54.538863 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9729 19:56:54.542282 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9730 19:56:54.548688 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9731 19:56:54.552122 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9732 19:56:54.555461 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9733 19:56:54.562431 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9734 19:56:54.565625 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9735 19:56:54.569234 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9736 19:56:54.575379 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9737 19:56:54.579070 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9738 19:56:54.582223 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9739 19:56:54.589283 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9740 19:56:54.592484 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9741 19:56:54.595585 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9742 19:56:54.602316 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9743 19:56:54.605505 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9744 19:56:54.609075 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9745 19:56:54.611929 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9746 19:56:54.615128 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9747 19:56:54.622058 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9748 19:56:54.625330 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9749 19:56:54.628806 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9750 19:56:54.635206 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9751 19:56:54.638682 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9752 19:56:54.642078 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9753 19:56:54.645146 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9754 19:56:54.651759 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9755 19:56:54.655437 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9756 19:56:54.662081 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9757 19:56:54.665006 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9758 19:56:54.668297 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9759 19:56:54.675304 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9760 19:56:54.678629 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9761 19:56:54.685242 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9762 19:56:54.688253 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9763 19:56:54.691611 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9764 19:56:54.698525 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9765 19:56:54.701782 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9766 19:56:54.708222 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9767 19:56:54.711998 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9768 19:56:54.718213 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9769 19:56:54.721749 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9770 19:56:54.724674 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9771 19:56:54.731707 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9772 19:56:54.735051 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9773 19:56:54.741398 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9774 19:56:54.745001 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9775 19:56:54.748279 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9776 19:56:54.754386 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9777 19:56:54.758231 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9778 19:56:54.764887 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9779 19:56:54.767759 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9780 19:56:54.771489 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9781 19:56:54.778028 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9782 19:56:54.781353 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9783 19:56:54.788145 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9784 19:56:54.791137 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9785 19:56:54.797953 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9786 19:56:54.801061 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9787 19:56:54.804227 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9788 19:56:54.811083 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9789 19:56:54.814240 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9790 19:56:54.821163 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9791 19:56:54.824256 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9792 19:56:54.827426 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9793 19:56:54.834110 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9794 19:56:54.837152 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9795 19:56:54.843753 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9796 19:56:54.847684 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9797 19:56:54.850679 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9798 19:56:54.857721 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9799 19:56:54.860870 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9800 19:56:54.867529 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9801 19:56:54.870950 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9802 19:56:54.874256 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9803 19:56:54.880423 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9804 19:56:54.883771 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9805 19:56:54.890844 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9806 19:56:54.894164 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9807 19:56:54.900294 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9808 19:56:54.904093 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9809 19:56:54.907514 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9810 19:56:54.913801 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9811 19:56:54.917611 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9812 19:56:54.923974 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9813 19:56:54.927369 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9814 19:56:54.930884 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9815 19:56:54.936909 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9816 19:56:54.940848 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9817 19:56:54.947618 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9818 19:56:54.950436 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9819 19:56:54.953940 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9820 19:56:54.960591 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9821 19:56:54.963719 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9822 19:56:54.970020 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9823 19:56:54.973636 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9824 19:56:54.976763 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9825 19:56:54.983590 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9826 19:56:54.987097 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9827 19:56:54.994003 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9828 19:56:54.996808 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9829 19:56:55.003714 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9830 19:56:55.006915 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9831 19:56:55.010321 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9832 19:56:55.017006 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9833 19:56:55.020214 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9834 19:56:55.027486 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9835 19:56:55.030406 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9836 19:56:55.037539 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9837 19:56:55.040299 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9838 19:56:55.043479 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9839 19:56:55.050477 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9840 19:56:55.053697 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9841 19:56:55.060066 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9842 19:56:55.063803 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9843 19:56:55.070107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9844 19:56:55.073156 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9845 19:56:55.076915 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9846 19:56:55.083703 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9847 19:56:55.086837 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9848 19:56:55.092982 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9849 19:56:55.096490 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9850 19:56:55.103252 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9851 19:56:55.106299 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9852 19:56:55.110072 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9853 19:56:55.116243 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9854 19:56:55.119768 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9855 19:56:55.126296 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9856 19:56:55.129521 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9857 19:56:55.136453 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9858 19:56:55.139548 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9859 19:56:55.146530 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9860 19:56:55.149520 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9861 19:56:55.152525 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9862 19:56:55.159283 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9863 19:56:55.162833 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9864 19:56:55.169563 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9865 19:56:55.172973 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9866 19:56:55.179178 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9867 19:56:55.182421 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9868 19:56:55.186167 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9869 19:56:55.192913 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9870 19:56:55.196090 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9871 19:56:55.202296 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9872 19:56:55.205496 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9873 19:56:55.212642 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9874 19:56:55.215521 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9875 19:56:55.219141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9876 19:56:55.225690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9877 19:56:55.229257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9878 19:56:55.235532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9879 19:56:55.238832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9880 19:56:55.245559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9881 19:56:55.248997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9882 19:56:55.255609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9883 19:56:55.259175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9884 19:56:55.265828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9885 19:56:55.269000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9886 19:56:55.275749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9887 19:56:55.278758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9888 19:56:55.285698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9889 19:56:55.288783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9890 19:56:55.295365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9891 19:56:55.298511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9892 19:56:55.305457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9893 19:56:55.308570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9894 19:56:55.311779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9895 19:56:55.318847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9896 19:56:55.321729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9897 19:56:55.328445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9898 19:56:55.332170 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9899 19:56:55.338458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9900 19:56:55.342346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9901 19:56:55.348767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9902 19:56:55.351807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9903 19:56:55.358413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9904 19:56:55.361803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9905 19:56:55.368406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9906 19:56:55.375022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9907 19:56:55.378458 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9908 19:56:55.378876 INFO: [APUAPC] vio 0
9909 19:56:55.385429 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9910 19:56:55.388741 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9911 19:56:55.392416 INFO: [APUAPC] D0_APC_0: 0x400510
9912 19:56:55.395560 INFO: [APUAPC] D0_APC_1: 0x0
9913 19:56:55.398740 INFO: [APUAPC] D0_APC_2: 0x1540
9914 19:56:55.402217 INFO: [APUAPC] D0_APC_3: 0x0
9915 19:56:55.405446 INFO: [APUAPC] D1_APC_0: 0xffffffff
9916 19:56:55.409090 INFO: [APUAPC] D1_APC_1: 0xffffffff
9917 19:56:55.412106 INFO: [APUAPC] D1_APC_2: 0x3fffff
9918 19:56:55.416036 INFO: [APUAPC] D1_APC_3: 0x0
9919 19:56:55.419240 INFO: [APUAPC] D2_APC_0: 0xffffffff
9920 19:56:55.422317 INFO: [APUAPC] D2_APC_1: 0xffffffff
9921 19:56:55.425455 INFO: [APUAPC] D2_APC_2: 0x3fffff
9922 19:56:55.429067 INFO: [APUAPC] D2_APC_3: 0x0
9923 19:56:55.432145 INFO: [APUAPC] D3_APC_0: 0xffffffff
9924 19:56:55.435615 INFO: [APUAPC] D3_APC_1: 0xffffffff
9925 19:56:55.438762 INFO: [APUAPC] D3_APC_2: 0x3fffff
9926 19:56:55.439239 INFO: [APUAPC] D3_APC_3: 0x0
9927 19:56:55.445682 INFO: [APUAPC] D4_APC_0: 0xffffffff
9928 19:56:55.448644 INFO: [APUAPC] D4_APC_1: 0xffffffff
9929 19:56:55.452510 INFO: [APUAPC] D4_APC_2: 0x3fffff
9930 19:56:55.452936 INFO: [APUAPC] D4_APC_3: 0x0
9931 19:56:55.455532 INFO: [APUAPC] D5_APC_0: 0xffffffff
9932 19:56:55.458624 INFO: [APUAPC] D5_APC_1: 0xffffffff
9933 19:56:55.462271 INFO: [APUAPC] D5_APC_2: 0x3fffff
9934 19:56:55.465314 INFO: [APUAPC] D5_APC_3: 0x0
9935 19:56:55.468783 INFO: [APUAPC] D6_APC_0: 0xffffffff
9936 19:56:55.472386 INFO: [APUAPC] D6_APC_1: 0xffffffff
9937 19:56:55.475356 INFO: [APUAPC] D6_APC_2: 0x3fffff
9938 19:56:55.478922 INFO: [APUAPC] D6_APC_3: 0x0
9939 19:56:55.481926 INFO: [APUAPC] D7_APC_0: 0xffffffff
9940 19:56:55.485382 INFO: [APUAPC] D7_APC_1: 0xffffffff
9941 19:56:55.488962 INFO: [APUAPC] D7_APC_2: 0x3fffff
9942 19:56:55.492315 INFO: [APUAPC] D7_APC_3: 0x0
9943 19:56:55.495374 INFO: [APUAPC] D8_APC_0: 0xffffffff
9944 19:56:55.498374 INFO: [APUAPC] D8_APC_1: 0xffffffff
9945 19:56:55.501758 INFO: [APUAPC] D8_APC_2: 0x3fffff
9946 19:56:55.505478 INFO: [APUAPC] D8_APC_3: 0x0
9947 19:56:55.508462 INFO: [APUAPC] D9_APC_0: 0xffffffff
9948 19:56:55.512386 INFO: [APUAPC] D9_APC_1: 0xffffffff
9949 19:56:55.515506 INFO: [APUAPC] D9_APC_2: 0x3fffff
9950 19:56:55.518588 INFO: [APUAPC] D9_APC_3: 0x0
9951 19:56:55.522529 INFO: [APUAPC] D10_APC_0: 0xffffffff
9952 19:56:55.525673 INFO: [APUAPC] D10_APC_1: 0xffffffff
9953 19:56:55.528709 INFO: [APUAPC] D10_APC_2: 0x3fffff
9954 19:56:55.531594 INFO: [APUAPC] D10_APC_3: 0x0
9955 19:56:55.535411 INFO: [APUAPC] D11_APC_0: 0xffffffff
9956 19:56:55.538446 INFO: [APUAPC] D11_APC_1: 0xffffffff
9957 19:56:55.541881 INFO: [APUAPC] D11_APC_2: 0x3fffff
9958 19:56:55.544795 INFO: [APUAPC] D11_APC_3: 0x0
9959 19:56:55.548597 INFO: [APUAPC] D12_APC_0: 0xffffffff
9960 19:56:55.552089 INFO: [APUAPC] D12_APC_1: 0xffffffff
9961 19:56:55.555007 INFO: [APUAPC] D12_APC_2: 0x3fffff
9962 19:56:55.558800 INFO: [APUAPC] D12_APC_3: 0x0
9963 19:56:55.561536 INFO: [APUAPC] D13_APC_0: 0xffffffff
9964 19:56:55.564627 INFO: [APUAPC] D13_APC_1: 0xffffffff
9965 19:56:55.568288 INFO: [APUAPC] D13_APC_2: 0x3fffff
9966 19:56:55.571370 INFO: [APUAPC] D13_APC_3: 0x0
9967 19:56:55.574934 INFO: [APUAPC] D14_APC_0: 0xffffffff
9968 19:56:55.578629 INFO: [APUAPC] D14_APC_1: 0xffffffff
9969 19:56:55.581329 INFO: [APUAPC] D14_APC_2: 0x3fffff
9970 19:56:55.584710 INFO: [APUAPC] D14_APC_3: 0x0
9971 19:56:55.588254 INFO: [APUAPC] D15_APC_0: 0xffffffff
9972 19:56:55.591472 INFO: [APUAPC] D15_APC_1: 0xffffffff
9973 19:56:55.595089 INFO: [APUAPC] D15_APC_2: 0x3fffff
9974 19:56:55.598261 INFO: [APUAPC] D15_APC_3: 0x0
9975 19:56:55.601780 INFO: [APUAPC] APC_CON: 0x4
9976 19:56:55.604954 INFO: [NOCDAPC] D0_APC_0: 0x0
9977 19:56:55.608427 INFO: [NOCDAPC] D0_APC_1: 0x0
9978 19:56:55.608509 INFO: [NOCDAPC] D1_APC_0: 0x0
9979 19:56:55.611503 INFO: [NOCDAPC] D1_APC_1: 0xfff
9980 19:56:55.615111 INFO: [NOCDAPC] D2_APC_0: 0x0
9981 19:56:55.618162 INFO: [NOCDAPC] D2_APC_1: 0xfff
9982 19:56:55.621672 INFO: [NOCDAPC] D3_APC_0: 0x0
9983 19:56:55.624707 INFO: [NOCDAPC] D3_APC_1: 0xfff
9984 19:56:55.628386 INFO: [NOCDAPC] D4_APC_0: 0x0
9985 19:56:55.631542 INFO: [NOCDAPC] D4_APC_1: 0xfff
9986 19:56:55.634807 INFO: [NOCDAPC] D5_APC_0: 0x0
9987 19:56:55.637868 INFO: [NOCDAPC] D5_APC_1: 0xfff
9988 19:56:55.641617 INFO: [NOCDAPC] D6_APC_0: 0x0
9989 19:56:55.644791 INFO: [NOCDAPC] D6_APC_1: 0xfff
9990 19:56:55.644914 INFO: [NOCDAPC] D7_APC_0: 0x0
9991 19:56:55.647805 INFO: [NOCDAPC] D7_APC_1: 0xfff
9992 19:56:55.651201 INFO: [NOCDAPC] D8_APC_0: 0x0
9993 19:56:55.654997 INFO: [NOCDAPC] D8_APC_1: 0xfff
9994 19:56:55.658124 INFO: [NOCDAPC] D9_APC_0: 0x0
9995 19:56:55.661561 INFO: [NOCDAPC] D9_APC_1: 0xfff
9996 19:56:55.664818 INFO: [NOCDAPC] D10_APC_0: 0x0
9997 19:56:55.667958 INFO: [NOCDAPC] D10_APC_1: 0xfff
9998 19:56:55.671078 INFO: [NOCDAPC] D11_APC_0: 0x0
9999 19:56:55.674765 INFO: [NOCDAPC] D11_APC_1: 0xfff
10000 19:56:55.677949 INFO: [NOCDAPC] D12_APC_0: 0x0
10001 19:56:55.681710 INFO: [NOCDAPC] D12_APC_1: 0xfff
10002 19:56:55.684685 INFO: [NOCDAPC] D13_APC_0: 0x0
10003 19:56:55.685150 INFO: [NOCDAPC] D13_APC_1: 0xfff
10004 19:56:55.688072 INFO: [NOCDAPC] D14_APC_0: 0x0
10005 19:56:55.691701 INFO: [NOCDAPC] D14_APC_1: 0xfff
10006 19:56:55.694927 INFO: [NOCDAPC] D15_APC_0: 0x0
10007 19:56:55.698497 INFO: [NOCDAPC] D15_APC_1: 0xfff
10008 19:56:55.701199 INFO: [NOCDAPC] APC_CON: 0x4
10009 19:56:55.704442 INFO: [APUAPC] set_apusys_apc done
10010 19:56:55.707432 INFO: [DEVAPC] devapc_init done
10011 19:56:55.711220 INFO: GICv3 without legacy support detected.
10012 19:56:55.714255 INFO: ARM GICv3 driver initialized in EL3
10013 19:56:55.720910 INFO: Maximum SPI INTID supported: 639
10014 19:56:55.724348 INFO: BL31: Initializing runtime services
10015 19:56:55.730790 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10016 19:56:55.730874 INFO: SPM: enable CPC mode
10017 19:56:55.737588 INFO: mcdi ready for mcusys-off-idle and system suspend
10018 19:56:55.740717 INFO: BL31: Preparing for EL3 exit to normal world
10019 19:56:55.744434 INFO: Entry point address = 0x80000000
10020 19:56:55.747595 INFO: SPSR = 0x8
10021 19:56:55.753331
10022 19:56:55.753414
10023 19:56:55.753479
10024 19:56:55.757006 Starting depthcharge on Spherion...
10025 19:56:55.757115
10026 19:56:55.757208 Wipe memory regions:
10027 19:56:55.757297
10028 19:56:55.758115 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10029 19:56:55.758218 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10030 19:56:55.758300 Setting prompt string to ['asurada:']
10031 19:56:55.758379 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10032 19:56:55.759786 [0x00000040000000, 0x00000054600000)
10033 19:56:55.882709
10034 19:56:55.883245 [0x00000054660000, 0x00000080000000)
10035 19:56:56.142990
10036 19:56:56.143129 [0x000000821a7280, 0x000000ffe64000)
10037 19:56:56.888159
10038 19:56:56.888605 [0x00000100000000, 0x00000240000000)
10039 19:56:58.777895
10040 19:56:58.780981 Initializing XHCI USB controller at 0x11200000.
10041 19:56:59.818844
10042 19:56:59.821896 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10043 19:56:59.822461
10044 19:56:59.822833
10045 19:56:59.823179
10046 19:56:59.823975 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10048 19:56:59.925472 asurada: tftpboot 192.168.201.1 11899601/tftp-deploy-4azv24sg/kernel/image.itb 11899601/tftp-deploy-4azv24sg/kernel/cmdline
10049 19:56:59.926140 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10050 19:56:59.926710 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10051 19:56:59.931408 tftpboot 192.168.201.1 11899601/tftp-deploy-4azv24sg/kernel/image.itp-deploy-4azv24sg/kernel/cmdline
10052 19:56:59.932030
10053 19:56:59.932412 Waiting for link
10054 19:57:00.091588
10055 19:57:00.092259 R8152: Initializing
10056 19:57:00.092757
10057 19:57:00.095255 Version 9 (ocp_data = 6010)
10058 19:57:00.096132
10059 19:57:00.098521 R8152: Done initializing
10060 19:57:00.098989
10061 19:57:00.099401 Adding net device
10062 19:57:01.967222
10063 19:57:01.967851 done.
10064 19:57:01.968304
10065 19:57:01.968654 MAC: 00:e0:4c:78:7a:aa
10066 19:57:01.969024
10067 19:57:01.970088 Sending DHCP discover... done.
10068 19:57:01.970553
10069 19:57:01.973607 Waiting for reply... done.
10070 19:57:01.974193
10071 19:57:01.977844 Sending DHCP request... done.
10072 19:57:01.978553
10073 19:57:02.010193 Waiting for reply... done.
10074 19:57:02.010510
10075 19:57:02.010704 My ip is 192.168.201.12
10076 19:57:02.010881
10077 19:57:02.013411 The DHCP server ip is 192.168.201.1
10078 19:57:02.013639
10079 19:57:02.020344 TFTP server IP predefined by user: 192.168.201.1
10080 19:57:02.020663
10081 19:57:02.026763 Bootfile predefined by user: 11899601/tftp-deploy-4azv24sg/kernel/image.itb
10082 19:57:02.027078
10083 19:57:02.029493 Sending tftp read request... done.
10084 19:57:02.029779
10085 19:57:02.034751 Waiting for the transfer...
10086 19:57:02.034983
10087 19:57:02.321612 00000000 ################################################################
10088 19:57:02.321756
10089 19:57:02.577565 00080000 ################################################################
10090 19:57:02.577706
10091 19:57:02.844437 00100000 ################################################################
10092 19:57:02.844586
10093 19:57:03.100982 00180000 ################################################################
10094 19:57:03.101126
10095 19:57:03.357487 00200000 ################################################################
10096 19:57:03.357628
10097 19:57:03.621974 00280000 ################################################################
10098 19:57:03.622122
10099 19:57:03.898323 00300000 ################################################################
10100 19:57:03.898467
10101 19:57:04.167783 00380000 ################################################################
10102 19:57:04.167935
10103 19:57:04.441240 00400000 ################################################################
10104 19:57:04.441377
10105 19:57:04.707523 00480000 ################################################################
10106 19:57:04.707707
10107 19:57:04.987595 00500000 ################################################################
10108 19:57:04.987764
10109 19:57:05.266131 00580000 ################################################################
10110 19:57:05.266277
10111 19:57:05.538500 00600000 ################################################################
10112 19:57:05.538647
10113 19:57:05.813426 00680000 ################################################################
10114 19:57:05.813571
10115 19:57:06.074592 00700000 ################################################################
10116 19:57:06.074737
10117 19:57:06.341694 00780000 ################################################################
10118 19:57:06.341840
10119 19:57:06.597576 00800000 ################################################################
10120 19:57:06.597720
10121 19:57:06.869798 00880000 ################################################################
10122 19:57:06.869945
10123 19:57:07.147390 00900000 ################################################################
10124 19:57:07.147535
10125 19:57:07.406111 00980000 ################################################################
10126 19:57:07.406258
10127 19:57:07.671968 00a00000 ################################################################
10128 19:57:07.672116
10129 19:57:07.946249 00a80000 ################################################################
10130 19:57:07.946402
10131 19:57:08.207301 00b00000 ################################################################
10132 19:57:08.207447
10133 19:57:08.478697 00b80000 ################################################################
10134 19:57:08.478845
10135 19:57:08.731364 00c00000 ################################################################
10136 19:57:08.731502
10137 19:57:08.988883 00c80000 ################################################################
10138 19:57:08.989031
10139 19:57:09.255678 00d00000 ################################################################
10140 19:57:09.255827
10141 19:57:09.544539 00d80000 ################################################################
10142 19:57:09.544702
10143 19:57:09.834745 00e00000 ################################################################
10144 19:57:09.834888
10145 19:57:10.118050 00e80000 ################################################################
10146 19:57:10.118200
10147 19:57:10.406854 00f00000 ################################################################
10148 19:57:10.407001
10149 19:57:10.695727 00f80000 ################################################################
10150 19:57:10.695898
10151 19:57:10.972745 01000000 ################################################################
10152 19:57:10.972891
10153 19:57:11.223185 01080000 ################################################################
10154 19:57:11.223328
10155 19:57:11.477430 01100000 ################################################################
10156 19:57:11.477571
10157 19:57:11.744991 01180000 ################################################################
10158 19:57:11.745135
10159 19:57:12.016362 01200000 ################################################################
10160 19:57:12.016508
10161 19:57:12.291606 01280000 ################################################################
10162 19:57:12.291788
10163 19:57:12.579850 01300000 ################################################################
10164 19:57:12.579995
10165 19:57:12.838106 01380000 ################################################################
10166 19:57:12.838244
10167 19:57:13.113685 01400000 ################################################################
10168 19:57:13.113834
10169 19:57:13.393642 01480000 ################################################################
10170 19:57:13.393790
10171 19:57:13.682229 01500000 ################################################################
10172 19:57:13.682376
10173 19:57:13.970597 01580000 ################################################################
10174 19:57:13.970741
10175 19:57:14.237007 01600000 ################################################################
10176 19:57:14.237155
10177 19:57:14.515977 01680000 ################################################################
10178 19:57:14.516123
10179 19:57:14.794126 01700000 ################################################################
10180 19:57:14.794270
10181 19:57:15.050712 01780000 ################################################################
10182 19:57:15.050854
10183 19:57:15.306986 01800000 ################################################################
10184 19:57:15.307131
10185 19:57:15.572378 01880000 ################################################################
10186 19:57:15.572526
10187 19:57:15.868480 01900000 ################################################################
10188 19:57:15.868624
10189 19:57:16.134311 01980000 ################################################################
10190 19:57:16.134507
10191 19:57:16.426475 01a00000 ################################################################
10192 19:57:16.426622
10193 19:57:16.685646 01a80000 ################################################################
10194 19:57:16.685821
10195 19:57:16.952356 01b00000 ################################################################
10196 19:57:16.952492
10197 19:57:17.233372 01b80000 ################################################################
10198 19:57:17.233552
10199 19:57:17.525590 01c00000 ################################################################
10200 19:57:17.525767
10201 19:57:17.806719 01c80000 ################################################################
10202 19:57:17.806890
10203 19:57:18.074796 01d00000 ################################################################
10204 19:57:18.074942
10205 19:57:18.346707 01d80000 ################################################################
10206 19:57:18.346879
10207 19:57:18.617342 01e00000 ################################################################
10208 19:57:18.617488
10209 19:57:18.877778 01e80000 ############################################################### done.
10210 19:57:18.877919
10211 19:57:18.880964 The bootfile was 32491730 bytes long.
10212 19:57:18.881164
10213 19:57:18.883957 Sending tftp read request... done.
10214 19:57:18.884072
10215 19:57:18.887553 Waiting for the transfer...
10216 19:57:18.887657
10217 19:57:18.887735 00000000 # done.
10218 19:57:18.887808
10219 19:57:18.898153 Command line loaded dynamically from TFTP file: 11899601/tftp-deploy-4azv24sg/kernel/cmdline
10220 19:57:18.898344
10221 19:57:18.910973 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10222 19:57:18.911220
10223 19:57:18.911349 Loading FIT.
10224 19:57:18.911462
10225 19:57:18.914575 Image ramdisk-1 has 21394895 bytes.
10226 19:57:18.914810
10227 19:57:18.917491 Image fdt-1 has 47278 bytes.
10228 19:57:18.917675
10229 19:57:18.920880 Image kernel-1 has 11047522 bytes.
10230 19:57:18.921084
10231 19:57:18.927555 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10232 19:57:18.927909
10233 19:57:18.947595 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10234 19:57:18.948196
10235 19:57:18.951205 Choosing best match conf-1 for compat google,spherion-rev2.
10236 19:57:18.956357
10237 19:57:18.961083 Connected to device vid:did:rid of 1ae0:0028:00
10238 19:57:18.969325
10239 19:57:18.972234 tpm_get_response: command 0x17b, return code 0x0
10240 19:57:18.972710
10241 19:57:18.975493 ec_init: CrosEC protocol v3 supported (256, 248)
10242 19:57:18.979375
10243 19:57:18.983011 tpm_cleanup: add release locality here.
10244 19:57:18.983580
10245 19:57:18.984031 Shutting down all USB controllers.
10246 19:57:18.986184
10247 19:57:18.986652 Removing current net device
10248 19:57:18.987023
10249 19:57:18.993235 Exiting depthcharge with code 4 at timestamp: 52509133
10250 19:57:18.993803
10251 19:57:18.995897 LZMA decompressing kernel-1 to 0x821a6718
10252 19:57:18.996363
10253 19:57:18.999509 LZMA decompressing kernel-1 to 0x40000000
10254 19:57:20.387594
10255 19:57:20.388209 jumping to kernel
10256 19:57:20.389947 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10257 19:57:20.390469 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10258 19:57:20.390893 Setting prompt string to ['Linux version [0-9]']
10259 19:57:20.391230 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10260 19:57:20.391565 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10261 19:57:20.470072
10262 19:57:20.473418 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10263 19:57:20.476991 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10264 19:57:20.477579 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10265 19:57:20.477980 Setting prompt string to []
10266 19:57:20.478432 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10267 19:57:20.478844 Using line separator: #'\n'#
10268 19:57:20.479350 No login prompt set.
10269 19:57:20.479938 Parsing kernel messages
10270 19:57:20.480284 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10271 19:57:20.480856 [login-action] Waiting for messages, (timeout 00:04:01)
10272 19:57:20.496135 [ 0.000000] Linux version 6.1.59-cip8-rt4 (KernelCI@build-j84202-arm64-gcc-10-defconfig-arm64-chromebook-st8dj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023
10273 19:57:20.499161 [ 0.000000] random: crng init done
10274 19:57:20.506331 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10275 19:57:20.509572 [ 0.000000] efi: UEFI not found.
10276 19:57:20.516322 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10277 19:57:20.526163 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10278 19:57:20.536355 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10279 19:57:20.542653 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10280 19:57:20.549232 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10281 19:57:20.555803 [ 0.000000] printk: bootconsole [mtk8250] enabled
10282 19:57:20.562785 [ 0.000000] NUMA: No NUMA configuration found
10283 19:57:20.569212 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10284 19:57:20.576142 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10285 19:57:20.576667 [ 0.000000] Zone ranges:
10286 19:57:20.581939 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10287 19:57:20.585769 [ 0.000000] DMA32 empty
10288 19:57:20.592409 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10289 19:57:20.595503 [ 0.000000] Movable zone start for each node
10290 19:57:20.599008 [ 0.000000] Early memory node ranges
10291 19:57:20.605338 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10292 19:57:20.612007 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10293 19:57:20.618491 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10294 19:57:20.625364 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10295 19:57:20.631496 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10296 19:57:20.638399 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10297 19:57:20.694908 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10298 19:57:20.701490 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10299 19:57:20.708366 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10300 19:57:20.711187 [ 0.000000] psci: probing for conduit method from DT.
10301 19:57:20.718192 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10302 19:57:20.721046 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10303 19:57:20.727716 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10304 19:57:20.731088 [ 0.000000] psci: SMC Calling Convention v1.2
10305 19:57:20.737430 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10306 19:57:20.740839 [ 0.000000] Detected VIPT I-cache on CPU0
10307 19:57:20.747697 [ 0.000000] CPU features: detected: GIC system register CPU interface
10308 19:57:20.754253 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10309 19:57:20.760930 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10310 19:57:20.767345 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10311 19:57:20.777079 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10312 19:57:20.783867 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10313 19:57:20.787610 [ 0.000000] alternatives: applying boot alternatives
10314 19:57:20.793788 [ 0.000000] Fallback order for Node 0: 0
10315 19:57:20.800348 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10316 19:57:20.803619 [ 0.000000] Policy zone: Normal
10317 19:57:20.817283 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10318 19:57:20.826931 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10319 19:57:20.838981 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10320 19:57:20.849044 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10321 19:57:20.855206 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10322 19:57:20.858440 <6>[ 0.000000] software IO TLB: area num 8.
10323 19:57:20.915724 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10324 19:57:21.065223 <6>[ 0.000000] Memory: 7948532K/8385536K available (17984K kernel code, 4116K rwdata, 17476K rodata, 8448K init, 615K bss, 404236K reserved, 32768K cma-reserved)
10325 19:57:21.070853 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10326 19:57:21.077482 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10327 19:57:21.080855 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10328 19:57:21.087443 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10329 19:57:21.094709 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10330 19:57:21.097762 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10331 19:57:21.107797 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10332 19:57:21.114324 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10333 19:57:21.117889 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10334 19:57:21.125623 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10335 19:57:21.128489 <6>[ 0.000000] GICv3: 608 SPIs implemented
10336 19:57:21.135471 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10337 19:57:21.138667 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10338 19:57:21.142063 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10339 19:57:21.151999 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10340 19:57:21.161724 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10341 19:57:21.175412 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10342 19:57:21.182181 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10343 19:57:21.190832 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10344 19:57:21.204105 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10345 19:57:21.210337 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10346 19:57:21.217234 <6>[ 0.009179] Console: colour dummy device 80x25
10347 19:57:21.226886 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10348 19:57:21.233446 <6>[ 0.024412] pid_max: default: 32768 minimum: 301
10349 19:57:21.237167 <6>[ 0.029285] LSM: Security Framework initializing
10350 19:57:21.243460 <6>[ 0.034223] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10351 19:57:21.253943 <6>[ 0.042038] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10352 19:57:21.260377 <6>[ 0.051427] cblist_init_generic: Setting adjustable number of callback queues.
10353 19:57:21.267431 <6>[ 0.058870] cblist_init_generic: Setting shift to 3 and lim to 1.
10354 19:57:21.277005 <6>[ 0.065208] cblist_init_generic: Setting adjustable number of callback queues.
10355 19:57:21.283410 <6>[ 0.072635] cblist_init_generic: Setting shift to 3 and lim to 1.
10356 19:57:21.286618 <6>[ 0.079075] rcu: Hierarchical SRCU implementation.
10357 19:57:21.293800 <6>[ 0.079077] rcu: Max phase no-delay instances is 1000.
10358 19:57:21.300303 <6>[ 0.079102] printk: bootconsole [mtk8250] printing thread started
10359 19:57:21.306515 <6>[ 0.097426] EFI services will not be available.
10360 19:57:21.310464 <6>[ 0.097628] smp: Bringing up secondary CPUs ...
10361 19:57:21.313223 <6>[ 0.097932] Detected VIPT I-cache on CPU1
10362 19:57:21.323138 <6>[ 0.097999] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10363 19:57:21.329729 <6>[ 0.098029] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10364 19:57:21.339084 <6>[ 0.125911] Detected VIPT I-cache on CPU2
10365 19:57:21.345840 <6>[ 0.125962] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10366 19:57:21.355035 <6>[ 0.125978] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10367 19:57:21.358637 <6>[ 0.126234] Detected VIPT I-cache on CPU3
10368 19:57:21.365491 <6>[ 0.126281] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10369 19:57:21.371982 <6>[ 0.126294] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10370 19:57:21.375601 <6>[ 0.126608] CPU features: detected: Spectre-v4
10371 19:57:21.382046 <6>[ 0.126614] CPU features: detected: Spectre-BHB
10372 19:57:21.385060 <6>[ 0.126619] Detected PIPT I-cache on CPU4
10373 19:57:21.391603 <6>[ 0.126676] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10374 19:57:21.398494 <6>[ 0.126693] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10375 19:57:21.405182 <6>[ 0.126988] Detected PIPT I-cache on CPU5
10376 19:57:21.411832 <6>[ 0.127051] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10377 19:57:21.418587 <6>[ 0.127068] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10378 19:57:21.421368 <6>[ 0.127344] Detected PIPT I-cache on CPU6
10379 19:57:21.428551 <6>[ 0.127408] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10380 19:57:21.435042 <6>[ 0.127424] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10381 19:57:21.441684 <6>[ 0.127717] Detected PIPT I-cache on CPU7
10382 19:57:21.448324 <6>[ 0.127780] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10383 19:57:21.455100 <6>[ 0.127797] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10384 19:57:21.458049 <6>[ 0.127844] smp: Brought up 1 node, 8 CPUs
10385 19:57:21.464922 <6>[ 0.127849] SMP: Total of 8 processors activated.
10386 19:57:21.468023 <6>[ 0.127852] CPU features: detected: 32-bit EL0 Support
10387 19:57:21.478217 <6>[ 0.127853] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10388 19:57:21.484802 <6>[ 0.127856] CPU features: detected: Common not Private translations
10389 19:57:21.491692 <6>[ 0.127858] CPU features: detected: CRC32 instructions
10390 19:57:21.494597 <6>[ 0.127861] CPU features: detected: RCpc load-acquire (LDAPR)
10391 19:57:21.501942 <6>[ 0.127862] CPU features: detected: LSE atomic instructions
10392 19:57:21.508346 <6>[ 0.127864] CPU features: detected: Privileged Access Never
10393 19:57:21.514938 <6>[ 0.127866] CPU features: detected: RAS Extension Support
10394 19:57:21.521127 <6>[ 0.127869] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10395 19:57:21.524533 <6>[ 0.127936] CPU: All CPU(s) started at EL2
10396 19:57:21.531033 <6>[ 0.127937] alternatives: applying system-wide alternatives
10397 19:57:21.534706 <6>[ 0.140974] devtmpfs: initialized
10398 19:57:21.544647 <6>[ 0.147188] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10399 19:57:21.551157 <6>[ 0.147202] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10400 19:57:21.576337 �HL�lL�&$JKV�.'HN��1048576 bytes, linear)
10401 19:57:21.579255 <6>[ 0.372083<] printk: console [ttyS0] printing thread started
10402 19:57:21.585772 6<6>[ 0.372115] printk: console [ttyS0] enabled
10403 19:57:21.592669 >[ 0.233161] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10404 19:57:21.602928 <6>[ 0.233235] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10405 19:57:21.609605 <6>[ 0.372120] printk: bootconsole [mtk8250] disabled
10406 19:57:21.615876 <6>[ 0.399183] printk: bootconsole [mtk8250] printing thread stopped
10407 19:57:21.619559 <6>[ 0.400494] SuperH (H)SCI(F) driver initialized
10408 19:57:21.625655 <6>[ 0.400977] msm_serial: driver initialized
10409 19:57:21.632881 <6>[ 0.405653] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10410 19:57:21.643190 <6>[ 0.405684] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10411 19:57:21.649596 <6>[ 0.405714] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10412 19:57:21.670345 <6>[ 0.405743] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10413 19:57:21.677264 <6>[ 0.405765] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10414 19:57:21.677794 <6>[ 0.405793] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10415 19:57:21.693813 <6>[ 0.405821] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10416 19:57:21.695087 <6>[ 0.405940] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10417 19:57:21.704285 <6>[ 0.405970] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10418 19:57:21.704871 <6>[ 0.416376] loop: module loaded
10419 19:57:21.715411 <6>[ 0.419013] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10420 19:57:21.718836 <4>[ 0.435691] mtk-pmic-keys: Failed to locate of_node [id: -1]
10421 19:57:21.722343 <6>[ 0.436588] megasas: 07.719.03.00-rc1
10422 19:57:21.729040 <6>[ 0.448762] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10423 19:57:21.732125 <6>[ 0.448873] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10424 19:57:21.738785 <6>[ 0.460753] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10425 19:57:21.752045 <6>[ 0.514365] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10426 19:57:22.364983 <6>[ 1.155248] Freeing initrd memory: 20892K
10427 19:57:22.377734 <6>[ 1.166792] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10428 19:57:22.383595 <6>[ 1.171459] tun: Universal TUN/TAP device driver, 1.6
10429 19:57:22.387459 <6>[ 1.172208] thunder_xcv, ver 1.0
10430 19:57:22.390739 <6>[ 1.172227] thunder_bgx, ver 1.0
10431 19:57:22.393933 <6>[ 1.172240] nicpf, ver 1.0
10432 19:57:22.400461 <6>[ 1.173277] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10433 19:57:22.407553 <6>[ 1.173280] hns3: Copyright (c) 2017 Huawei Corporation.
10434 19:57:22.410632 <6>[ 1.173307] hclge is initializing
10435 19:57:22.414289 <6>[ 1.173320] e1000: Intel(R) PRO/1000 Network Driver
10436 19:57:22.421352 <6>[ 1.173322] e1000: Copyright (c) 1999-2006 Intel Corporation.
10437 19:57:22.428349 <6>[ 1.173350] e1000e: Intel(R) PRO/1000 Network Driver
10438 19:57:22.431861 <6>[ 1.173352] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10439 19:57:22.438930 <6>[ 1.173369] igb: Intel(R) Gigabit Ethernet Network Driver
10440 19:57:22.445823 <6>[ 1.173371] igb: Copyright (c) 2007-2014 Intel Corporation.
10441 19:57:22.452587 <6>[ 1.173385] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10442 19:57:22.456045 <6>[ 1.173387] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10443 19:57:22.458928 <6>[ 1.173683] sky2: driver version 1.30
10444 19:57:22.466403 <6>[ 1.174771] VFIO - User Level meta-driver version: 0.3
10445 19:57:22.472664 <6>[ 1.177621] usbcore: registered new interface driver usb-storage
10446 19:57:22.479291 <6>[ 1.177804] usbcore: registered new device driver onboard-usb-hub
10447 19:57:22.483006 <6>[ 1.180534] mt6397-rtc mt6359-rtc: registered as rtc0
10448 19:57:22.492475 <6>[ 1.180687] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-28T19:55:47 UTC (1698522947)
10449 19:57:22.499354 <6>[ 1.181296] i2c_dev: i2c /dev entries driver
10450 19:57:22.505831 <6>[ 1.188385] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10451 19:57:22.508815 <6>[ 1.203368] cpu cpu0: EM: created perf domain
10452 19:57:22.515595 <6>[ 1.203688] cpu cpu4: EM: created perf domain
10453 19:57:22.522429 <6>[ 1.207584] sdhci: Secure Digital Host Controller Interface driver
10454 19:57:22.525616 <6>[ 1.207585] sdhci: Copyright(c) Pierre Ossman
10455 19:57:22.532096 <6>[ 1.207935] Synopsys Designware Multimedia Card Interface Driver
10456 19:57:22.538619 <6>[ 1.208321] sdhci-pltfm: SDHCI platform and OF driver helper
10457 19:57:22.545550 <6>[ 1.212755] ledtrig-cpu: registered to indicate activity on CPUs
10458 19:57:22.548626 <6>[ 1.213063] mmc0: CQHCI version 5.10
10459 19:57:22.555248 <6>[ 1.213642] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10460 19:57:22.561605 <6>[ 1.213931] usbcore: registered new interface driver usbhid
10461 19:57:22.565341 <6>[ 1.213932] usbhid: USB HID core driver
10462 19:57:22.571708 <6>[ 1.214044] spi_master spi0: will run message pump with realtime priority
10463 19:57:22.585174 <6>[ 1.245157] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10464 19:57:22.598710 <6>[ 1.247547] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10465 19:57:22.601706 <6>[ 1.248589] cros-ec-spi spi0.0: Chrome EC device registered
10466 19:57:22.611915 <6>[ 1.266981] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10467 19:57:22.618608 <6>[ 1.269327] NET: Registered PF_PACKET protocol family
10468 19:57:22.621567 <6>[ 1.269453] 9pnet: Installing 9P2000 support
10469 19:57:22.627992 <5>[ 1.269498] Key type dns_resolver registered
10470 19:57:22.631510 <6>[ 1.269821] registered taskstats version 1
10471 19:57:22.634806 <5>[ 1.269837] Loading compiled-in X.509 certificates
10472 19:57:22.648390 <4>[ 1.286820] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10473 19:57:22.657792 <4>[ 1.286959] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10474 19:57:22.664854 <3>[ 1.286970] debugfs: File 'uA_load' in directory '/' already present!
10475 19:57:22.671709 <3>[ 1.286977] debugfs: File 'min_uV' in directory '/' already present!
10476 19:57:22.678205 <3>[ 1.286980] debugfs: File 'max_uV' in directory '/' already present!
10477 19:57:22.684313 <3>[ 1.286983] debugfs: File 'constraint_flags' in directory '/' already present!
10478 19:57:22.694822 <3>[ 1.288753] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10479 19:57:22.697725 <6>[ 1.301903] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10480 19:57:22.704298 <6>[ 1.302600] xhci-mtk 11200000.usb: xHCI Host Controller
10481 19:57:22.711387 <6>[ 1.302613] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10482 19:57:22.721074 <6>[ 1.302814] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10483 19:57:22.727623 <6>[ 1.302855] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10484 19:57:22.734646 <6>[ 1.302939] xhci-mtk 11200000.usb: xHCI Host Controller
10485 19:57:22.741177 <6>[ 1.302948] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10486 19:57:22.747810 <6>[ 1.302954] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10487 19:57:22.750685 <6>[ 1.303358] hub 1-0:1.0: USB hub found
10488 19:57:22.757559 <6>[ 1.303375] hub 1-0:1.0: 1 port detected
10489 19:57:22.764575 <6>[ 1.303545] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10490 19:57:22.768077 <6>[ 1.303829] hub 2-0:1.0: USB hub found
10491 19:57:22.774446 <6>[ 1.303842] hub 2-0:1.0: 1 port detected
10492 19:57:22.777860 <6>[ 1.307030] mtk-msdc 11f70000.mmc: Got CD GPIO
10493 19:57:22.780871 <6>[ 1.308214] mmc0: Command Queue Engine enabled
10494 19:57:22.787782 <6>[ 1.308225] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10495 19:57:22.794362 <6>[ 1.308739] mmcblk0: mmc0:0001 DA4128 116 GiB
10496 19:57:22.801137 <6>[ 1.312010] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10497 19:57:22.804503 <6>[ 1.313172] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10498 19:57:22.811096 <6>[ 1.314166] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10499 19:57:22.817730 <6>[ 1.315250] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10500 19:57:22.823948 <6>[ 1.321147] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10501 19:57:22.830721 <6>[ 1.321155] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10502 19:57:22.840836 <4>[ 1.321226] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10503 19:57:22.850850 <6>[ 1.321731] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10504 19:57:22.857442 <6>[ 1.321732] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10505 19:57:22.864218 <6>[ 1.321862] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10506 19:57:22.873934 <6>[ 1.321868] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10507 19:57:22.880832 <6>[ 1.321869] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10508 19:57:22.891115 <6>[ 1.321872] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10509 19:57:22.897727 <6>[ 1.323021] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10510 19:57:22.907581 <6>[ 1.323035] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10511 19:57:22.914267 <6>[ 1.323039] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10512 19:57:22.923827 <6>[ 1.323042] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10513 19:57:22.930707 <6>[ 1.323046] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10514 19:57:22.940275 <6>[ 1.323049] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10515 19:57:22.950226 <6>[ 1.323052] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10516 19:57:22.956754 <6>[ 1.323056] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10517 19:57:22.967170 <6>[ 1.323059] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10518 19:57:22.973569 <6>[ 1.323062] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10519 19:57:22.983179 <6>[ 1.323065] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10520 19:57:22.989773 <6>[ 1.323068] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10521 19:57:22.999510 <6>[ 1.323072] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10522 19:57:23.005976 <6>[ 1.323075] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10523 19:57:23.016248 <6>[ 1.323079] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10524 19:57:23.022582 <6>[ 1.323389] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10525 19:57:23.029067 <6>[ 1.323873] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10526 19:57:23.035938 <6>[ 1.324077] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10527 19:57:23.042479 <6>[ 1.324303] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10528 19:57:23.048942 <6>[ 1.324543] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10529 19:57:23.055590 <6>[ 1.324701] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10530 19:57:23.065913 <6>[ 1.324709] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10531 19:57:23.075276 <6>[ 1.324711] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10532 19:57:23.085258 <6>[ 1.324714] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10533 19:57:23.095267 <6>[ 1.324717] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10534 19:57:23.101957 <6>[ 1.324725] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10535 19:57:23.111514 <6>[ 1.324732] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10536 19:57:23.121923 <6>[ 1.324734] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10537 19:57:23.131317 <6>[ 1.324736] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10538 19:57:23.141414 <6>[ 1.324740] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10539 19:57:23.151561 <6>[ 1.324742] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10540 19:57:23.161045 <6>[ 1.325216] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10541 19:57:23.167521 <6>[ 1.721497] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10542 19:57:23.171305 <6>[ 1.873377] hub 1-1:1.0: USB hub found
10543 19:57:23.174604 <6>[ 1.873738] hub 1-1:1.0: 4 ports detected
10544 19:57:23.212084 <6>[ 1.997738] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10545 19:57:23.232862 <6>[ 2.024103] hub 2-1:1.0: USB hub found
10546 19:57:23.236607 <6>[ 2.024601] hub 2-1:1.0: 3 ports detected
10547 19:57:23.400662 <6>[ 2.185655] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10548 19:57:23.520959 <6>[ 2.312566] hub 1-1.4:1.0: USB hub found
10549 19:57:23.524360 <6>[ 2.312871] hub 1-1.4:1.0: 2 ports detected
10550 19:57:23.604746 <6>[ 2.389679] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10551 19:57:23.815897 <6>[ 2.601626] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10552 19:57:23.999859 <6>[ 2.785676] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10553 19:57:34.840351 <6>[ 13.634642] ALSA device list:
10554 19:57:34.847188 <6>[ 13.634664] No soundcards found.
10555 19:57:34.850199 <6>[ 13.639042] Freeing unused kernel memory: 8448K
10556 19:57:34.853796 <6>[ 13.639137] Run /init as init process
10557 19:57:34.867943 Starting syslogd: OK
10558 19:57:34.872549 Starting klogd: OK
10559 19:57:34.882736 Running sysctl: OK
10560 19:57:34.892806 Populating /dev using udev: <30>[ 13.685025] udevd[202]: starting version 3.2.9
10561 19:57:34.896349 <27>[ 13.688151] udevd[202]: specified user 'tss' unknown
10562 19:57:34.902658 <27>[ 13.688197] udevd[202]: specified group 'tss' unknown
10563 19:57:34.906408 <30>[ 13.689060] udevd[203]: starting eudev-3.2.9
10564 19:57:35.014512 <6>[ 13.805025] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10565 19:57:35.024361 <6>[ 13.805054] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10566 19:57:35.031422 <6>[ 13.805058] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10567 19:57:35.066750 <3>[ 13.855557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10568 19:57:35.073465 <6>[ 13.855583] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10569 19:57:35.082963 <3>[ 13.855603] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10570 19:57:35.090108 <3>[ 13.855623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10571 19:57:35.096675 <3>[ 13.855811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10572 19:57:35.106968 <3>[ 13.855816] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10573 19:57:35.113385 <3>[ 13.855818] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10574 19:57:35.123483 <3>[ 13.855828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10575 19:57:35.130048 <3>[ 13.855834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10576 19:57:35.141359 <3>[ 13.855881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10577 19:57:35.151035 <3>[ 13.855912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10578 19:57:35.157829 <3>[ 13.855917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10579 19:57:35.168162 <3>[ 13.855919] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10580 19:57:35.174907 <3>[ 13.855978] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10581 19:57:35.184831 <3>[ 13.855986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10582 19:57:35.191193 <3>[ 13.855989] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10583 19:57:35.198561 <3>[ 13.855994] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10584 19:57:35.208607 <3>[ 13.855997] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10585 19:57:35.215092 <3>[ 13.856018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10586 19:57:35.222358 <6>[ 13.877796] remoteproc remoteproc0: scp is available
10587 19:57:35.225663 <6>[ 13.877928] remoteproc remoteproc0: powering up scp
10588 19:57:35.235872 <6>[ 13.877935] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10589 19:57:35.238962 <6>[ 13.877975] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10590 19:57:35.245616 <6>[ 13.885002] usbcore: registered new interface driver r8152
10591 19:57:35.252664 <6>[ 13.908875] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10592 19:57:35.262189 <4>[ 13.910370] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10593 19:57:35.268883 <4>[ 13.913630] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10594 19:57:35.275904 <6>[ 13.922271] usbcore: registered new interface driver cdc_ether
10595 19:57:35.278939 <6>[ 13.930848] mc: Linux media interface: v0.10
10596 19:57:35.285592 <6>[ 13.934780] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10597 19:57:35.292013 <6>[ 13.934789] pci_bus 0000:00: root bus resource [bus 00-ff]
10598 19:57:35.298753 <6>[ 13.934793] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10599 19:57:35.308601 <6>[ 13.934795] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10600 19:57:35.315329 <6>[ 13.934826] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10601 19:57:35.322068 <6>[ 13.934839] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10602 19:57:35.328793 <6>[ 13.934903] pci 0000:00:00.0: supports D1 D2
10603 19:57:35.335226 <6>[ 13.934904] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10604 19:57:35.342112 <6>[ 13.935877] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10605 19:57:35.348340 <6>[ 13.935970] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10606 19:57:35.355167 <6>[ 13.935997] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10607 19:57:35.361887 <6>[ 13.936018] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10608 19:57:35.371489 <6>[ 13.936033] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10609 19:57:35.375083 <6>[ 13.936137] pci 0000:01:00.0: supports D1 D2
10610 19:57:35.381485 <6>[ 13.936139] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10611 19:57:35.388048 <6>[ 13.949552] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10612 19:57:35.398330 <6>[ 13.949600] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10613 19:57:35.404700 <6>[ 13.949602] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10614 19:57:35.411509 <6>[ 13.949610] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10615 19:57:35.421635 <6>[ 13.949623] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10616 19:57:35.428136 <6>[ 13.949636] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10617 19:57:35.434515 <6>[ 13.949649] pci 0000:00:00.0: PCI bridge to [bus 01]
10618 19:57:35.441592 <6>[ 13.949654] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10619 19:57:35.447773 <6>[ 13.949904] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10620 19:57:35.454800 <6>[ 13.950631] videodev: Linux video capture interface: v2.00
10621 19:57:35.461409 <6>[ 13.950653] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10622 19:57:35.467834 <6>[ 13.956103] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10623 19:57:35.474428 <6>[ 13.983332] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10624 19:57:35.481094 <4>[ 13.983934] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10625 19:57:35.487642 <4>[ 13.983934] Fallback method does not support PEC.
10626 19:57:35.494306 <3>[ 14.000445] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10627 19:57:35.504555 <6>[ 14.003397] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10628 19:57:35.510870 <6>[ 14.003405] remoteproc remoteproc0: remote processor scp is now up
10629 19:57:35.517762 <6>[ 14.003417] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10630 19:57:35.527523 <4>[ 14.004211] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10631 19:57:35.534092 <4>[ 14.004217] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10632 19:57:35.544003 <6>[ 14.021675] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10633 19:57:35.550807 <3>[ 14.023258] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10634 19:57:35.560843 <6>[ 14.023479] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10635 19:57:35.570931 <6>[ 14.029982] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10636 19:57:35.580739 <6>[ 14.038284] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10637 19:57:35.587559 <6>[ 14.038586] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10638 19:57:35.593752 <6>[ 14.053476] usbcore: registered new interface driver r8153_ecm
10639 19:57:35.600476 <6>[ 14.061576] r8152 2-1.3:1.0 eth0: v1.12.13
10640 19:57:35.606959 <5>[ 14.062817] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10641 19:57:35.613920 <5>[ 14.078604] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10642 19:57:35.623626 <4>[ 14.078675] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10643 19:57:35.627090 <6>[ 14.078685] cfg80211: failed to load regulatory.db
10644 19:57:35.630078 <6>[ 14.079331] Bluetooth: Core ver 2.22
10645 19:57:35.637179 <6>[ 14.079451] NET: Registered PF_BLUETOOTH protocol family
10646 19:57:35.643052 <6>[ 14.079453] Bluetooth: HCI device and connection manager initialized
10647 19:57:35.650152 <6>[ 14.079466] Bluetooth: HCI socket layer initialized
10648 19:57:35.653679 <6>[ 14.079468] Bluetooth: L2CAP socket layer initialized
10649 19:57:35.660371 <6>[ 14.079474] Bluetooth: SCO socket layer initialized
10650 19:57:35.666632 <6>[ 14.099934] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10651 19:57:35.680010 <6>[ 14.101025] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10652 19:57:35.683448 <6>[ 14.101121] usbcore: registered new interface driver uvcvideo
10653 19:57:35.690098 <6>[ 14.126740] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10654 19:57:35.696839 <6>[ 14.133869] usbcore: registered new interface driver btusb
10655 19:57:35.706506 <4>[ 14.134976] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10656 19:57:35.713211 <3>[ 14.134988] Bluetooth: hci0: Failed to load firmware file (-2)
10657 19:57:35.719779 <3>[ 14.134991] Bluetooth: hci0: Failed to set up firmware (-2)
10658 19:57:35.729878 <4>[ 14.134994] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10659 19:57:35.736426 <6>[ 14.174117] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10660 19:57:35.742995 <6>[ 14.174215] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10661 19:57:35.749478 <6>[ 14.193458] mt7921e 0000:01:00.0: ASIC revision: 79610010
10662 19:57:35.759576 <4>[ 14.288619] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10663 19:57:35.772493 <4>[ 14.395222] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10664 19:57:35.782720 <4>[ 14.502996] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10665 19:57:35.826397 <4>[ 14.611133] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10666 19:57:35.826529 done
10667 19:57:35.837085 Saving random seed: OK
10668 19:57:35.854907 Starting network: OK
10669 19:57:35.891293 Starting dropbear sshd: OK
10670 19:57:35.895027 <6>[ 14.685555] NET: Registered PF_INET6 protocol family
10671 19:57:35.898219 <6>[ 14.686886] Segment Routing with IPv6
10672 19:57:35.904854 <6>[ 14.686901] In-situ OAM (IOAM) with IPv6
10673 19:57:35.912085 /bin/sh: can't access tty; job control turned off
10674 19:57:35.912514 Matched prompt #10: / #
10676 19:57:35.912813 Setting prompt string to ['/ #']
10677 19:57:35.912942 end: 2.2.5.1 login-action (duration 00:00:15) [common]
10679 19:57:35.913241 end: 2.2.5 auto-login-action (duration 00:00:16) [common]
10680 19:57:35.913361 start: 2.2.6 expect-shell-connection (timeout 00:03:45) [common]
10681 19:57:35.913465 Setting prompt string to ['/ #']
10682 19:57:35.913561 Forcing a shell prompt, looking for ['/ #']
10684 19:57:35.963826 / #
10685 19:57:35.963986 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10686 19:57:35.964095 Waiting using forced prompt support (timeout 00:02:30)
10687 19:57:35.964241 <4>[ 14.716222] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10688 19:57:35.969634
10689 19:57:35.969944 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10690 19:57:35.970074 start: 2.2.7 export-device-env (timeout 00:03:45) [common]
10691 19:57:35.970202 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10692 19:57:35.970323 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
10693 19:57:35.970444 end: 2 depthcharge-action (duration 00:01:15) [common]
10694 19:57:35.970568 start: 3 lava-test-retry (timeout 00:01:00) [common]
10695 19:57:35.970693 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10696 19:57:35.970799 Using namespace: common
10698 19:57:36.071149 / # #
10699 19:57:36.071328 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10700 19:57:36.071504 #<4>[ 14.823983] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10701 19:57:36.076813
10702 19:57:36.077115 Using /lava-11899601
10704 19:57:36.177457 / # export SHELL=/bin/sh
10705 19:57:36.177680 export SHELL=/bin/sh<4>[ 14.932140] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10706 19:57:36.182911
10708 19:57:36.283438 / # . /lava-11899601/environment
10709 19:57:36.283656 . /lava-11899601/environment<4>[ 15.040386] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10710 19:57:36.288540
10712 19:57:36.389087 / # /lava-11899601/bin/lava-test-runner /lava-11899601/0
10713 19:57:36.389261 Test shell timeout: 10s (minimum of the action and connection timeout)
10714 19:57:36.389735 /lava-11899601/bin/lava-test-runner /lava-11899601/0<4>[ 15.148404] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10715 19:57:36.394046
10716 19:57:36.435813 + export 'TESTRUN_ID=0_dmesg'
10717 19:57:36.435939 + cd /lava-11899601<8>[ 15.211620] <LAVA_SIGNAL_STARTRUN 0_dmesg 11899601_1.5.2.3.1>
10718 19:57:36.436040 /0/tests/0_dmesg
10719 19:57:36.436134 + cat uuid
10720 19:57:36.436229 + UUID=11899601_1.5.2.3.1
10721 19:57:36.436323 + set +x
10722 19:57:36.436414 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10723 19:57:36.436692 Received signal: <STARTRUN> 0_dmesg 11899601_1.5.2.3.1
10724 19:57:36.436800 Starting test lava.0_dmesg (11899601_1.5.2.3.1)
10725 19:57:36.436924 Skipping test definition patterns.
10726 19:57:36.438457 <8>[ 15.225632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10727 19:57:36.438742 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10729 19:57:36.448147 <8>[ 15.237855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10730 19:57:36.448435 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10732 19:57:36.474385 <4>[ 15.257870] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10733 19:57:36.484693 + <8>[ 15.264151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10734 19:57:36.484982 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10736 19:57:36.488089 <8>[ 15.273999] <LAVA_SIGNAL_ENDRUN 0_dmesg 11899601_1.5.2.3.1>
10737 19:57:36.488377 Received signal: <ENDRUN> 0_dmesg 11899601_1.5.2.3.1
10738 19:57:36.488491 Ending use of test pattern.
10739 19:57:36.488584 Ending test lava.0_dmesg (11899601_1.5.2.3.1), duration 0.05
10741 19:57:36.491500 set +x
10742 19:57:36.491608 <LAVA_TEST_RUNNER EXIT>
10743 19:57:36.491916 ok: lava_test_shell seems to have completed
10744 19:57:36.492066 alert: pass
crit: pass
emerg: pass
10745 19:57:36.492191 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10746 19:57:36.492314 end: 3 lava-test-retry (duration 00:00:01) [common]
10747 19:57:36.492435 start: 4 lava-test-retry (timeout 00:01:00) [common]
10748 19:57:36.492556 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10749 19:57:36.492654 Using namespace: common
10751 19:57:36.593012 / # #
10752 19:57:36.593195 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10753 19:57:36.593348 Using /lava-11899601
10755 19:57:36.693691 export SHELL=/bin/sh
10756 19:57:36.693907 #<3>[ 15.366087] mt7921e 0000:01:00.0: hardware init failed
10757 19:57:36.694013
10759 19:57:36.794541 / # export SHELL=/bin/sh. /lava-11899601/environment
10760 19:57:36.794766
10762 19:57:36.895330 / # . /lava-11899601/environment/lava-11899601/bin/lava-test-runner /lava-11899601/1
10763 19:57:36.895521 Test shell timeout: 10s (minimum of the action and connection timeout)
10764 19:57:36.895727
10765 19:57:36.900678 / # /lava-11899601/bin/lava-test-runner /lava-11899601/1
10766 19:57:36.919960 + export 'TESTRUN_ID=1_bootrr'
10767 19:57:36.929985 + cd /lava-11899<8>[ 15.720070] <LAVA_SIGNAL_STARTRUN 1_bootrr 11899601_1.5.2.3.5>
10768 19:57:36.930103 601/1/tests/1_bootrr
10769 19:57:36.930198 + cat uuid
10770 19:57:36.930465 Received signal: <STARTRUN> 1_bootrr 11899601_1.5.2.3.5
10771 19:57:36.930567 Starting test lava.1_bootrr (11899601_1.5.2.3.5)
10772 19:57:36.930686 Skipping test definition patterns.
10773 19:57:36.933440 + UUID=11899601_1.5.2.3.5
10774 19:57:36.933545 + set +x
10775 19:57:36.946699 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-1<8>[ 15.734494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10776 19:57:36.946990 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10778 19:57:36.950142 1899601/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10779 19:57:36.953498 + cd /opt/bootrr/libexec/bootrr
10780 19:57:36.963275 + sh helpers/b<8>[ 15.750029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10781 19:57:36.963389 ootrr-auto
10782 19:57:36.963696 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10784 19:57:36.966752 /lava-11899601/1/../bin/lava-test-case
10785 19:57:36.970079 /lava-11899601/1/../bin/lava-test-case
10786 19:57:36.973459 /usr/bin/tpm2_getcap
10787 19:57:36.996251 /lava-11899601/1/../bin/lava-test-case
10788 19:57:37.006279 <8>[ 15.795528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10789 19:57:37.006565 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10791 19:57:37.013971 /lava-11899601/1/../bin/lava-test-case
10792 19:57:37.020653 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10794 19:57:37.024049 <8>[ 15.811981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10795 19:57:37.027346 /lava-11899601/1/../bin/lava-test-case
10796 19:57:37.033703 <8>[ 15.825065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10797 19:57:37.033986 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10799 19:57:37.037394 /lava-11899601/1/../bin/lava-test-case
10800 19:57:37.046995 <8>[ 15.837303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10801 19:57:37.047279 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10803 19:57:37.050501 /lava-11899601/1/../bin/lava-test-case
10804 19:57:37.056995 <8>[ 15.849109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10805 19:57:37.057279 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10807 19:57:37.060440 /lava-11899601/1/../bin/lava-test-case
10808 19:57:37.070627 <8>[ 15.860311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10809 19:57:37.070912 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10811 19:57:37.074038 /lava-11899601/1/../bin/lava-test-case
10812 19:57:37.087053 <8>[ 15.873506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10813 19:57:37.087336 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10815 19:57:37.089879 /lava-11899601/1/../bin/lava-test-case
10816 19:57:37.096965 <8>[ 15.888961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10817 19:57:37.097253 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10819 19:57:37.099857 /lava-11899601/1/../bin/lava-test-case
10820 19:57:37.114920 <8>[ 15.901839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10821 19:57:37.115207 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10823 19:57:37.117899 /lava-11899601/1/../bin/lava-test-case
10824 19:57:37.130869 <8>[ 15.918728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10825 19:57:37.131159 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10827 19:57:37.134050 /lava-11899601/1/../bin/lava-test-case
10828 19:57:37.146847 <8>[ 15.934331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10829 19:57:37.147135 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10831 19:57:37.149921 /lava-11899601/1/../bin/lava-test-case
10832 19:57:37.162385 <8>[ 15.950306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10833 19:57:37.162672 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10835 19:57:37.166045 /lava-11899601/1/../bin/lava-test-case
10836 19:57:37.175877 <8>[ 15.964980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10837 19:57:37.176166 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10839 19:57:37.179230 /lava-11899601/1/../bin/lava-test-case
10840 19:57:37.186134 <8>[ 15.977283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10841 19:57:37.186422 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10843 19:57:37.192339 /lava-11899601/1/../bin/lava-test-case
10844 19:57:37.202898 <8>[ 15.989324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10845 19:57:37.203185 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10847 19:57:37.206202 /lava-11899601/1/../bin/lava-test-case
10848 19:57:37.212993 <8>[ 16.005059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10849 19:57:37.213281 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10851 19:57:37.220142 /lava-11899601/1/../bin/lava-test-case
10852 19:57:37.226081 <8>[ 16.016672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10853 19:57:37.226365 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10855 19:57:37.229756 /lava-11899601/1/../bin/lava-test-case
10856 19:57:37.239520 <8>[ 16.028632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10857 19:57:37.239808 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10859 19:57:37.243025 /lava-11899601/1/../bin/lava-test-case
10860 19:57:37.249737 <8>[ 16.040264] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10861 19:57:37.250024 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10863 19:57:37.253339 /lava-11899601/1/../bin/lava-test-case
10864 19:57:37.262816 <8>[ 16.051755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10865 19:57:37.263104 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10867 19:57:37.266401 /lava-11899601/1/../bin/lava-test-case
10868 19:57:37.278796 <8>[ 16.066116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10869 19:57:37.279089 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10871 19:57:37.282179 /lava-11899601/1/../bin/lava-test-case
10872 19:57:37.292096 <8>[ 16.080310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10873 19:57:37.292384 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10875 19:57:37.295506 /lava-11899601/1/../bin/lava-test-case
10876 19:57:37.302149 <8>[ 16.092837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10877 19:57:37.302433 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10879 19:57:37.305678 /lava-11899601/1/../bin/lava-test-case
10880 19:57:37.315409 <8>[ 16.104809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10881 19:57:37.315665 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10883 19:57:37.319006 /lava-11899601/1/../bin/lava-test-case
10884 19:57:37.325383 <8>[ 16.115961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10885 19:57:37.325670 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10887 19:57:37.328910 /lava-11899601/1/../bin/lava-test-case
10888 19:57:37.342780 <8>[ 16.129899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10889 19:57:37.343066 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10891 19:57:37.346206 /lava-11899601/1/../bin/lava-test-case
10892 19:57:37.356141 <8>[ 16.144826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10893 19:57:37.356429 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10895 19:57:37.359433 /lava-11899601/1/../bin/lava-test-case
10896 19:57:37.370547 <8>[ 16.157871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10897 19:57:37.370832 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10899 19:57:37.374117 /lava-11899601/1/../bin/lava-test-case
10900 19:57:37.380778 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10902 19:57:37.384103 <8>[ 16.172214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10903 19:57:37.387478 /lava-11899601/1/../bin/lava-test-case
10904 19:57:37.394141 <8>[ 16.185309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10905 19:57:37.394424 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10907 19:57:37.397709 /lava-11899601/1/../bin/lava-test-case
10908 19:57:37.407582 <8>[ 16.196454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10909 19:57:37.407908 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10911 19:57:37.410535 /lava-11899601/1/../bin/lava-test-case
10912 19:57:37.417102 <8>[ 16.209179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10913 19:57:37.417388 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10915 19:57:37.420651 /lava-11899601/1/../bin/lava-test-case
10916 19:57:37.434382 <8>[ 16.222454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10917 19:57:37.434671 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10919 19:57:37.437866 /lava-11899601/1/../bin/lava-test-case
10920 19:57:37.444399 <8>[ 16.236126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10921 19:57:37.444685 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10923 19:57:37.451375 /lava-11899601/1/../bin/lava-test-case
10924 19:57:37.458076 <8>[ 16.248999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10925 19:57:37.458362 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10927 19:57:37.461262 /lava-11899601/1/../bin/lava-test-case
10928 19:57:37.474891 <8>[ 16.261478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10929 19:57:37.475180 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10931 19:57:37.477833 /lava-11899601/1/../bin/lava-test-case
10932 19:57:37.485207 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10934 19:57:37.488423 <8>[ 16.277028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10935 19:57:37.491881 /lava-11899601/1/../bin/lava-test-case
10936 19:57:37.498488 <8>[ 16.288783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10937 19:57:37.498774 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10939 19:57:37.501659 /lava-11899601/1/../bin/lava-test-case
10940 19:57:37.511585 <8>[ 16.299993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10941 19:57:37.511879 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10943 19:57:37.514734 /lava-11899601/1/../bin/lava-test-case
10944 19:57:37.527280 <8>[ 16.313381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10945 19:57:37.527570 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10947 19:57:37.530048 /lava-11899601/1/../bin/lava-test-case
10948 19:57:37.540353 <8>[ 16.328362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10949 19:57:37.540639 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10951 19:57:37.543342 /lava-11899601/1/../bin/lava-test-case
10952 19:57:37.554839 <8>[ 16.341404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
10953 19:57:37.555126 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
10955 19:57:37.557763 /lava-11899601/1/../bin/lava-test-case
10956 19:57:37.564799 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
10958 19:57:37.567862 <8>[ 16.356673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
10959 19:57:37.571268 /lava-11899601/1/../bin/lava-test-case
10960 19:57:37.582597 <8>[ 16.370657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
10961 19:57:37.582884 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
10963 19:57:37.586204 /lava-11899601/1/../bin/lava-test-case
10964 19:57:37.593066 <8>[ 16.385163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
10965 19:57:37.593368 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
10967 19:57:37.596019 /lava-11899601/1/../bin/lava-test-case
10968 19:57:37.606617 <8>[ 16.397110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
10969 19:57:37.606901 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
10971 19:57:37.609843 /lava-11899601/1/../bin/lava-test-case
10972 19:57:37.619924 <8>[ 16.407448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
10973 19:57:37.620213 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
10975 19:57:37.623415 /lava-11899601/1/../bin/lava-test-case
10976 19:57:37.629789 <8>[ 16.421100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
10977 19:57:37.630077 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
10979 19:57:37.633420 /lava-11899601/1/../bin/lava-test-case
10980 19:57:37.643406 <8>[ 16.433272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
10981 19:57:37.643697 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
10983 19:57:37.646893 /lava-11899601/1/../bin/lava-test-case
10984 19:57:37.653466 <8>[ 16.444409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
10985 19:57:37.653751 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
10987 19:57:37.656549 /lava-11899601/1/../bin/lava-test-case
10988 19:57:37.666821 <8>[ 16.457201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
10989 19:57:37.667107 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
10991 19:57:37.669815 /lava-11899601/1/../bin/lava-test-case
10992 19:57:37.676833 <8>[ 16.468645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
10993 19:57:37.677121 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
10995 19:57:37.683461 /lava-11899601/1/../bin/lava-test-case
10996 19:57:37.689883 <8>[ 16.480425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
10997 19:57:37.690169 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
10999 19:57:37.693540 /lava-11899601/1/../bin/lava-test-case
11000 19:57:37.699768 <8>[ 16.492586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11001 19:57:37.700055 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11003 19:57:37.706537 /lava-11899601/1/../bin/lava-test-case
11004 19:57:37.713190 <8>[ 16.503707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11005 19:57:37.713516 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11007 19:57:37.716826 /lava-11899601/1/../bin/lava-test-case
11008 19:57:37.726630 <8>[ 16.516847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11009 19:57:37.726892 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11011 19:57:37.730131 /lava-11899601/1/../bin/lava-test-case
11012 19:57:37.736768 <8>[ 16.528317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11013 19:57:37.737022 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11015 19:57:37.739660 /lava-11899601/1/../bin/lava-test-case
11016 19:57:37.750718 <8>[ 16.539883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11017 19:57:37.750977 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11019 19:57:37.754275 /lava-11899601/1/../bin/lava-test-case
11020 19:57:37.761007 <8>[ 16.552371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11021 19:57:37.761263 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11023 19:57:37.763931 /lava-11899601/1/../bin/lava-test-case
11024 19:57:37.774467 <8>[ 16.564549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11025 19:57:37.774723 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11027 19:57:37.778094 /lava-11899601/1/../bin/lava-test-case
11028 19:57:37.787607 <8>[ 16.575513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11029 19:57:37.787878 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11031 19:57:37.791130 /lava-11899601/1/../bin/lava-test-case
11032 19:57:37.797463 <8>[ 16.588753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11033 19:57:37.797720 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11035 19:57:37.801148 /lava-11899601/1/../bin/lava-test-case
11036 19:57:37.810815 <8>[ 16.600727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11037 19:57:37.811072 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11039 19:57:37.814233 /lava-11899601/1/../bin/lava-test-case
11040 19:57:37.826756 <8>[ 16.613365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11041 19:57:37.827009 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11043 19:57:37.830151 /lava-11899601/1/../bin/lava-test-case
11044 19:57:37.836666 <8>[ 16.628337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11045 19:57:37.836919 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11047 19:57:37.843322 /lava-11899601/1/../bin/lava-test-case
11048 19:57:37.849884 <8>[ 16.640367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11049 19:57:37.850171 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11051 19:57:37.853655 /lava-11899601/1/../bin/lava-test-case
11052 19:57:37.860589 <8>[ 16.653019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11053 19:57:37.860874 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11055 19:57:37.866555 /lava-11899601/1/../bin/lava-test-case
11056 19:57:37.873412 <8>[ 16.664923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11057 19:57:37.873698 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11059 19:57:37.877030 /lava-11899601/1/../bin/lava-test-case
11060 19:57:37.886442 <8>[ 16.676957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11061 19:57:37.886726 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11063 19:57:37.890115 /lava-11899601/1/../bin/lava-test-case
11064 19:57:37.896736 <8>[ 16.688707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11065 19:57:37.897024 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11067 19:57:37.899780 /lava-11899601/1/../bin/lava-test-case
11068 19:57:37.910476 <8>[ 16.700849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11069 19:57:37.910762 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11071 19:57:37.914181 /lava-11899601/1/../bin/lava-test-case
11072 19:57:37.920710 <8>[ 16.712665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11073 19:57:37.920998 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11075 19:57:37.924183 /lava-11899601/1/../bin/lava-test-case
11076 19:57:37.934223 <8>[ 16.724900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11077 19:57:37.934509 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11079 19:57:37.937736 /lava-11899601/1/../bin/lava-test-case
11080 19:57:37.944185 <8>[ 16.736908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11081 19:57:37.944468 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11083 19:57:37.948020 /lava-11899601/1/../bin/lava-test-case
11084 19:57:37.958757 <8>[ 16.748047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11085 19:57:37.959042 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11087 19:57:37.961852 /lava-11899601/1/../bin/lava-test-case
11088 19:57:37.968751 <8>[ 16.760079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11089 19:57:37.969038 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11091 19:57:37.971664 /lava-11899601/1/../bin/lava-test-case
11092 19:57:37.982653 <8>[ 16.772156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11093 19:57:37.982907 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11095 19:57:37.985705 /lava-11899601/1/../bin/lava-test-case
11096 19:57:37.992348 <8>[ 16.784010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11097 19:57:37.992601 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11099 19:57:37.999096 /lava-11899601/1/../bin/lava-test-case
11100 19:57:38.005884 <8>[ 16.796959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11101 19:57:38.006140 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11103 19:57:38.008946 /lava-11899601/1/../bin/lava-test-case
11104 19:57:38.019160 <8>[ 16.808120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11105 19:57:38.019413 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11107 19:57:38.022196 /lava-11899601/1/../bin/lava-test-case
11108 19:57:38.028909 <8>[ 16.821131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11109 19:57:38.029164 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11111 19:57:38.032334 /lava-11899601/1/../bin/lava-test-case
11112 19:57:38.042409 <8>[ 16.832989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11113 19:57:38.042661 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11115 19:57:38.045544 /lava-11899601/1/../bin/lava-test-case
11116 19:57:38.055478 <8>[ 16.843484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11117 19:57:38.055734 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11119 19:57:38.059059 /lava-11899601/1/../bin/lava-test-case
11120 19:57:38.070642 <8>[ 16.858147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11121 19:57:38.070933 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11123 19:57:38.073766 /lava-11899601/1/../bin/lava-test-case
11124 19:57:38.083897 <8>[ 16.872753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11125 19:57:38.084187 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11127 19:57:38.087311 /lava-11899601/1/../bin/lava-test-case
11128 19:57:38.093641 <8>[ 16.885164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11129 19:57:38.093925 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11131 19:57:38.097146 /lava-11899601/1/../bin/lava-test-case
11132 19:57:38.110595 <8>[ 16.897389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11133 19:57:38.110876 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11135 19:57:38.113757 /lava-11899601/1/../bin/lava-test-case
11136 19:57:38.126403 /lava-11899601/1<8>[ 16.913673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11137 19:57:38.126686 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11139 19:57:38.136125 <8>[ 16.921986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11140 19:57:38.136239 /../bin/lava-test-case
11141 19:57:38.136510 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11143 19:57:38.139260 /lava-11899601/1/../bin/lava-test-case
11144 19:57:38.150551 <8>[ 16.938664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11145 19:57:38.150831 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11147 19:57:38.153554 /lava-11899601/1/../bin/lava-test-case
11148 19:57:38.163466 <8>[ 16.951856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11149 19:57:38.163753 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11151 19:57:38.166933 /lava-11899601/1/../bin/lava-test-case
11152 19:57:38.173606 <8>[ 16.965144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11153 19:57:38.173893 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11155 19:57:38.177097 /lava-11899601/1/../bin/lava-test-case
11156 19:57:38.190900 <8>[ 16.978832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11157 19:57:38.191188 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11159 19:57:38.193727 /lava-11899601/1/../bin/lava-test-case
11160 19:57:38.203700 <8>[ 16.993206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11161 19:57:38.203988 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11163 19:57:38.206704 /lava-11899601/1/../bin/lava-test-case
11164 19:57:38.218646 <8>[ 17.005992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11165 19:57:38.218931 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11167 19:57:38.221681 /lava-11899601/1/../bin/lava-test-case
11168 19:57:38.234270 <8>[ 17.022295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11169 19:57:38.234554 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11171 19:57:38.237949 /lava-11899601/1/../bin/lava-test-case
11172 19:57:38.250278 <8>[ 17.038977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11173 19:57:38.250565 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11175 19:57:38.253527 /lava-11899601/1/../bin/lava-test-case
11176 19:57:38.266486 <8>[ 17.054612] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11177 19:57:38.266770 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11179 19:57:39.268767 /lava-11899601/1/../bin/lava-test-case
11180 19:57:39.278200 <8>[ 18.067328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11181 19:57:39.278604 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11183 19:57:39.281639 /lava-11899601/1/../bin/lava-test-case
11184 19:57:39.288464 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11186 19:57:39.291861 <8>[ 18.080186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11187 19:57:40.294330 /lava-11899601/1/../bin/lava-test-case
11188 19:57:40.300895 <8>[ 19.092834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11189 19:57:40.301273 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11191 19:57:40.304115 /lava-11899601/1/../bin/lava-test-case
11192 19:57:40.314384 <8>[ 19.103504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11193 19:57:40.314753 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11195 19:57:41.320735 /lava-11899601/1/../bin/lava-test-case
11196 19:57:41.330248 <8>[ 20.120094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11197 19:57:41.330587 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11199 19:57:41.333744 /lava-11899601/1/../bin/lava-test-case
11200 19:57:41.340287 <8>[ 20.132306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11201 19:57:41.340613 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11203 19:57:42.346130 /lava-11899601/1/../bin/lava-test-case
11204 19:57:42.352675 <8>[ 21.144393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11205 19:57:42.353007 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11207 19:57:42.356185 /lava-11899601/1/../bin/lava-test-case
11208 19:57:42.365911 <8>[ 21.155303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11209 19:57:42.366246 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11211 19:57:43.369032 /lava-11899601/1/../bin/lava-test-case
11212 19:57:43.375822 <8>[ 22.168504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11213 19:57:43.376157 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11215 19:57:43.379175 /lava-11899601/1/../bin/lava-test-case
11216 19:57:43.390396 <8>[ 22.179478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11217 19:57:43.390736 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11219 19:57:44.397683 /lava-11899601/1/../bin/lava-test-case
11220 19:57:44.409977 <8>[ 23.197580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11221 19:57:44.410318 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11223 19:57:44.412937 /lava-11899601/1/../bin/lava-test-case
11224 19:57:44.422873 <8>[ 23.212503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11225 19:57:44.423205 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11227 19:57:45.427601 /lava-11899601/1/../bin/lava-test-case
11228 19:57:45.437939 <8>[ 24.225896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11229 19:57:45.438275 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11231 19:57:45.440863 /lava-11899601/1/../bin/lava-test-case
11232 19:57:45.447598 <8>[ 24.240880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11233 19:57:45.447953 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11235 19:57:45.454188 /lava-11899601/1/../bin/lava-test-case
11236 19:57:45.465839 <8>[ 24.254051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11237 19:57:45.466175 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11239 19:57:46.469790 /lava-11899601/1/../bin/lava-test-case
11240 19:57:46.481233 /lava-11899601/1<8>[ 25.269534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11241 19:57:46.481569 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11243 19:57:46.491066 <8>[ 25.276057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11244 19:57:46.491445 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11246 19:57:46.501132 /../bin/lava-tes<8>[ 25.288031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11247 19:57:46.501302 t-case
11248 19:57:46.501553 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11250 19:57:46.504437 /lava-11899601/1/../bin/lava-test-case
11251 19:57:46.514274 /lava-11899601/1<8>[ 25.304089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11252 19:57:46.514611 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11254 19:57:46.517643 /../bin/lava-test-case
11255 19:57:46.521116 /lava-11899601/1/../bin/lava-test-case
11256 19:57:46.530966 <8>[ 25.317482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11257 19:57:46.531301 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11259 19:57:46.534113 /lava-11899601/1/../bin/lava-test-case
11260 19:57:46.540839 <8>[ 25.332601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11261 19:57:46.541172 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11263 19:57:46.544355 /lava-11899601/1/../bin/lava-test-case
11264 19:57:46.554293 <8>[ 25.344597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11265 19:57:46.554629 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11267 19:57:46.557148 /lava-11899601/1/../bin/lava-test-case
11268 19:57:46.569699 <8>[ 25.357361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11269 19:57:46.570039 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11271 19:57:46.572856 /lava-11899601/1/../bin/lava-test-case
11272 19:57:46.585824 <8>[ 25.374485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11273 19:57:46.586159 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11275 19:57:46.588859 /lava-11899601/1/../bin/lava-test-case
11276 19:57:46.601980 <8>[ 25.390060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11277 19:57:46.602320 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11279 19:57:46.605221 /lava-11899601/1/../bin/lava-test-case
11280 19:57:46.614955 <8>[ 25.404649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11281 19:57:46.615290 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11283 19:57:46.618348 /lava-11899601/1/../bin/lava-test-case
11284 19:57:46.625200 <8>[ 25.416965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11285 19:57:46.625530 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11287 19:57:46.628030 /lava-11899601/1/../bin/lava-test-case
11288 19:57:46.641793 <8>[ 25.429555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11289 19:57:46.642143 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11291 19:57:46.645188 /lava-11899601/1/../bin/lava-test-case
11292 19:57:46.657757 <8>[ 25.445370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11293 19:57:46.658097 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11295 19:57:46.661371 /lava-11899601/1/../bin/lava-test-case
11296 19:57:46.670993 <8>[ 25.460836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11297 19:57:46.671331 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11299 19:57:46.674105 /lava-11899601/1/../bin/lava-test-case
11300 19:57:46.685520 <8>[ 25.474876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11301 19:57:46.685874 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11303 19:57:46.689216 /lava-11899601/1/../bin/lava-test-case
11304 19:57:46.701777 <8>[ 25.489552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11305 19:57:46.702112 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11307 19:57:46.704799 /lava-11899601/1/../bin/lava-test-case
11308 19:57:46.718132 <8>[ 25.506148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11309 19:57:46.718470 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11311 19:57:46.721065 /lava-11899601/1/../bin/lava-test-case
11312 19:57:46.733815 <8>[ 25.522743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11313 19:57:46.734154 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11315 19:57:46.737143 /lava-11899601/1/../bin/lava-test-case
11316 19:57:46.749709 <8>[ 25.539189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11317 19:57:46.750059 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11319 19:57:46.753178 /lava-11899601/1/../bin/lava-test-case
11320 19:57:46.763122 <8>[ 25.552593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11321 19:57:46.763487 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11323 19:57:47.765757 /lava-11899601/1/../bin/lava-test-case
11324 19:57:47.777285 <8>[ 26.565582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11325 19:57:47.777598 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11327 19:57:48.777239 /lava-11899601/1/../bin/lava-test-case
11328 19:57:48.783835 <8>[ 27.576111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11329 19:57:48.784147 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11331 19:57:48.787036 /lava-11899601/1/../bin/lava-test-case
11332 19:57:48.797097 <8>[ 27.588827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11333 19:57:48.797444 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11335 19:57:48.800348 /lava-11899601/1/../bin/lava-test-case
11336 19:57:48.813426 <8>[ 27.602271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11337 19:57:48.813747 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11339 19:57:48.817069 /lava-11899601/1/../bin/lava-test-case
11340 19:57:48.826504 <8>[ 27.616154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11341 19:57:48.826796 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11343 19:57:48.830344 /lava-11899601/1/../bin/lava-test-case
11344 19:57:48.836340 <8>[ 27.628854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11345 19:57:48.836608 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11347 19:57:48.839947 /lava-11899601/1/../bin/lava-test-case
11348 19:57:48.849877 <8>[ 27.640073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11349 19:57:48.850198 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11351 19:57:48.853338 /lava-11899601/1/../bin/lava-test-case
11352 19:57:48.865405 <8>[ 27.654020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11353 19:57:48.865722 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11355 19:57:48.868950 /lava-11899601/1/../bin/lava-test-case
11356 19:57:48.875613 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11358 19:57:48.878885 <8>[ 27.667645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11359 19:57:48.881900 /lava-11899601/1/../bin/lava-test-case
11360 19:57:48.893662 <8>[ 27.683300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11361 19:57:48.893979 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11363 19:57:48.896463 /lava-11899601/1/../bin/lava-test-case
11364 19:57:48.909661 <8>[ 27.697379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11365 19:57:48.909980 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11367 19:57:48.912416 /lava-11899601/1/../bin/lava-test-case
11368 19:57:48.919444 <8>[ 27.712275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11369 19:57:48.919729 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11371 19:57:48.922425 /lava-11899601/1/../bin/lava-test-case
11372 19:57:48.933239 <8>[ 27.723665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11373 19:57:48.933552 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11375 19:57:48.936741 /lava-11899601/1/../bin/lava-test-case
11376 19:57:48.948725 /lava-11899601/1<8>[ 27.737401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11377 19:57:48.949049 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11379 19:57:48.958725 <8>[ 27.745059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11380 19:57:48.958853 /../bin/lava-test-case
11381 19:57:48.959126 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11383 19:57:48.968608 /lava-11899601/1/../bin/<8>[ 27.760834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11384 19:57:48.968735 lava-test-case
11385 19:57:48.969003 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11387 19:57:48.982071 /lava-11899601/1/../bin/lava-tes<8>[ 27.773138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11388 19:57:48.982215 t-case
11389 19:57:48.982494 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11391 19:57:48.985041 /lava-11899601/1/../bin/lava-test-case
11392 19:57:48.991705 <8>[ 27.784983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11393 19:57:48.991993 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11395 19:57:48.995057 /lava-11899601/1/../bin/lava-test-case
11396 19:57:49.005718 <8>[ 27.795783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11397 19:57:49.006035 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11399 19:57:49.008689 /lava-11899601/1/../bin/lava-test-case
11400 19:57:49.015362 <8>[ 27.808372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11401 19:57:49.015656 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11403 19:57:49.018462 /lava-11899601/1/../bin/lava-test-case
11404 19:57:49.029200 <8>[ 27.820366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11405 19:57:49.029518 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11407 19:57:49.032833 /lava-11899601/1/../bin/lava-test-case
11408 19:57:49.045495 <8>[ 27.835064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11409 19:57:49.045817 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11411 19:57:50.045196 /lava-11899601/1/../bin/lava-test-case
11412 19:57:50.057081 <8>[ 28.846060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11413 19:57:50.057402 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11415 19:57:51.057194 /lava-11899601/1/../bin/lava-test-case
11416 19:57:51.063516 <8>[ 29.856048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11417 19:57:51.063854 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11418 19:57:51.063946 Bad test result: blocked
11419 19:57:51.066730 /lava-11899601/1/../bin/lava-test-case
11420 19:57:51.080912 <8>[ 29.870488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11421 19:57:51.081214 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11423 19:57:52.083208 /lava-11899601/1/../bin/lava-test-case
11424 19:57:52.090325 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11426 19:57:52.093597 <8>[ 30.883025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11427 19:57:52.096502 /lava-11899601/1/../bin/lava-test-case
11428 19:57:52.108844 <8>[ 30.899852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11429 19:57:52.109146 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11431 19:57:52.112109 /lava-11899601/1/../bin/lava-test-case
11432 19:57:52.124715 <8>[ 30.913958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11433 19:57:52.125018 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11435 19:57:52.128241 /lava-11899601/1/../bin/lava-test-case
11436 19:57:52.135048 <8>[ 30.929308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11437 19:57:52.135318 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11439 19:57:52.137862 /lava-11899601/1/../bin/lava-test-case
11440 19:57:52.148960 <8>[ 30.939685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11441 19:57:52.149264 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11443 19:57:52.152538 /lava-11899601/1/../bin/lava-test-case
11444 19:57:52.158942 <8>[ 30.953295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11445 19:57:52.159226 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11447 19:57:52.161958 /lava-11899601/1/../bin/lava-test-case
11448 19:57:52.172490 <8>[ 30.965048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11449 19:57:52.172784 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11451 19:57:53.177735 /lava-11899601/1/../bin/lava-test-case
11452 19:57:53.184243 <8>[ 31.977059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11453 19:57:53.184589 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11455 19:57:53.187686 /lava-11899601/1/../bin/lava-test-case
11456 19:57:53.197534 <8>[ 31.988957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11457 19:57:53.197867 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11459 19:57:54.202630 /lava-11899601/1/../bin/lava-test-case
11460 19:57:54.213689 <8>[ 33.002143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11461 19:57:54.213967 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11463 19:57:54.217522 /lava-11899601/1/../bin/lava-test-case
11464 19:57:54.228520 <8>[ 33.018037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11465 19:57:54.228785 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11467 19:57:55.230074 /lava-11899601/1/../bin/lava-test-case
11468 19:57:55.236990 <8>[ 34.029207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11469 19:57:55.237828 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11471 19:57:55.240448 /lava-11899601/1/../bin/lava-test-case
11472 19:57:55.249383 <8>[ 34.040896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11473 19:57:55.250194 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11475 19:57:56.258410 /lava-11899601/1/../bin/lava-test-case
11476 19:57:56.268987 <8>[ 35.059623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11477 19:57:56.269782 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11479 19:57:56.272145 /lava-11899601/1/../bin/lava-test-case
11480 19:57:56.278766 <8>[ 35.071979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11481 19:57:56.279559 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11483 19:57:56.282454 /lava-11899601/1/../bin/lava-test-case
11484 19:57:56.293015 <8>[ 35.085012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11485 19:57:56.293698 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11487 19:57:56.296144 /lava-11899601/1/../bin/lava-test-case
11488 19:57:56.303093 <8>[ 35.096956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11489 19:57:56.303748 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11491 19:57:56.306436 /lava-11899601/1/../bin/lava-test-case
11492 19:57:56.317240 <8>[ 35.107277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11493 19:57:56.317962 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11495 19:57:56.320289 /lava-11899601/1/../bin/lava-test-case
11496 19:57:56.333145 <8>[ 35.122147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11497 19:57:56.333936 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11499 19:57:56.336552 /lava-11899601/1/../bin/lava-test-case
11500 19:57:56.346313 <8>[ 35.135518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11501 19:57:56.347108 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11503 19:57:56.350084 /lava-11899601/1/../bin/lava-test-case
11504 19:57:56.360628 /lava-11899601/1<8>[ 35.149601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11505 19:57:56.361413 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11507 19:57:56.370839 <8>[ 35.157007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11508 19:57:56.371360 /../bin/lava-test-case
11509 19:57:56.372080 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11511 19:57:56.373839 /lava-11899601/1/../bin/lava-test-case
11512 19:57:56.377417 + set +x
11513 19:57:56.383610 <LAVA_TEST_RUNNE<8>[ 35.173773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11514 19:57:56.384464 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11516 19:57:56.391204 <8>[ 35.176042] <LAVA_SIGNAL_ENDRUN 1_bootrr 11899601_1.5.2.3.5>
11517 19:57:56.391777 R EXIT>
11518 19:57:56.392389 Received signal: <ENDRUN> 1_bootrr 11899601_1.5.2.3.5
11519 19:57:56.392768 Ending use of test pattern.
11520 19:57:56.393083 Ending test lava.1_bootrr (11899601_1.5.2.3.5), duration 19.46
11522 19:58:05.236680 / # <6>[ 44.033825] vpu: disabling
11523 19:58:05.239777 <6>[ 44.033958] vproc2: disabling
11524 19:58:05.243556 <6>[ 44.034018] vproc1: disabling
11525 19:58:05.246680 <6>[ 44.034073] vaud18: disabling
11526 19:58:05.249937 <6>[ 44.034332] vsram_others: disabling
11527 19:58:05.253099 <6>[ 44.034512] va09: disabling
11528 19:58:05.256698 <6>[ 44.034593] vsram_md: disabling
11529 19:58:05.259877 <6>[ 44.034726] Vgpu: disabling
11531 19:58:36.492795 end: 4.1 lava-test-shell (duration 00:01:00) [common]
11533 19:58:36.492989 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
11535 19:58:36.493147 end: 4 lava-test-retry (duration 00:01:00) [common]
11537 19:58:36.493372 Cleaning after the job
11538 19:58:36.493463 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/ramdisk
11539 19:58:36.496907 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/kernel
11540 19:58:36.510349 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/dtb
11541 19:58:36.510522 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899601/tftp-deploy-4azv24sg/modules
11542 19:58:36.518004 start: 5.1 power-off (timeout 00:00:30) [common]
11543 19:58:36.518176 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11544 19:58:36.599362 >> Command sent successfully.
11545 19:58:36.602081 Returned 0 in 0 seconds
11546 19:58:36.702484 end: 5.1 power-off (duration 00:00:00) [common]
11548 19:58:36.702814 start: 5.2 read-feedback (timeout 00:10:00) [common]
11549 19:58:36.703093 Listened to connection for namespace 'common' for up to 1s
11550 19:58:37.703699 Finalising connection for namespace 'common'
11551 19:58:37.703892 Disconnecting from shell: Finalise
11552 19:58:37.804207 end: 5.2 read-feedback (duration 00:00:01) [common]
11553 19:58:37.804368 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11899601
11554 19:58:37.854038 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11899601
11555 19:58:37.854261 TestError: A test failed to run, look at the error message.