Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Kernel Errors: 35
- Errors: 2
- Boot result: FAIL
1 19:51:44.965775 lava-dispatcher, installed at version: 2023.08
2 19:51:44.965986 start: 0 validate
3 19:51:44.966121 Start time: 2023-10-28 19:51:44.966112+00:00 (UTC)
4 19:51:44.966243 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:51:44.966376 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 19:51:45.235373 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:51:45.236073 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:52:08.259714 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:52:08.260471 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:52:08.531746 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:52:08.532397 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:52:09.063443 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:52:09.064190 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:52:11.075736 validate duration: 26.11
16 19:52:11.075986 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:52:11.076083 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:52:11.076168 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:52:11.076291 Not decompressing ramdisk as can be used compressed.
20 19:52:11.076375 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 19:52:11.076437 saving as /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/ramdisk/initrd.cpio.gz
22 19:52:11.076499 total size: 4665412 (4 MB)
23 19:52:11.342248 progress 0 % (0 MB)
24 19:52:11.343836 progress 5 % (0 MB)
25 19:52:11.345084 progress 10 % (0 MB)
26 19:52:11.346345 progress 15 % (0 MB)
27 19:52:11.347692 progress 20 % (0 MB)
28 19:52:11.348907 progress 25 % (1 MB)
29 19:52:11.350119 progress 30 % (1 MB)
30 19:52:11.351326 progress 35 % (1 MB)
31 19:52:11.352591 progress 40 % (1 MB)
32 19:52:11.353951 progress 45 % (2 MB)
33 19:52:11.355150 progress 50 % (2 MB)
34 19:52:11.356414 progress 55 % (2 MB)
35 19:52:11.357624 progress 60 % (2 MB)
36 19:52:11.358826 progress 65 % (2 MB)
37 19:52:11.360081 progress 70 % (3 MB)
38 19:52:11.361278 progress 75 % (3 MB)
39 19:52:11.362510 progress 80 % (3 MB)
40 19:52:11.363990 progress 85 % (3 MB)
41 19:52:11.365237 progress 90 % (4 MB)
42 19:52:11.366538 progress 95 % (4 MB)
43 19:52:11.367866 progress 100 % (4 MB)
44 19:52:11.368036 4 MB downloaded in 0.29 s (15.26 MB/s)
45 19:52:11.368241 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:52:11.368520 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:52:11.368634 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:52:11.368744 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:52:11.368918 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:52:11.369000 saving as /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/kernel/Image
52 19:52:11.369061 total size: 49304064 (47 MB)
53 19:52:11.369120 No compression specified
54 19:52:11.370236 progress 0 % (0 MB)
55 19:52:11.383278 progress 5 % (2 MB)
56 19:52:11.396081 progress 10 % (4 MB)
57 19:52:11.409021 progress 15 % (7 MB)
58 19:52:11.421814 progress 20 % (9 MB)
59 19:52:11.434790 progress 25 % (11 MB)
60 19:52:11.447665 progress 30 % (14 MB)
61 19:52:11.460420 progress 35 % (16 MB)
62 19:52:11.473338 progress 40 % (18 MB)
63 19:52:11.486541 progress 45 % (21 MB)
64 19:52:11.499365 progress 50 % (23 MB)
65 19:52:11.512376 progress 55 % (25 MB)
66 19:52:11.525355 progress 60 % (28 MB)
67 19:52:11.538367 progress 65 % (30 MB)
68 19:52:11.551281 progress 70 % (32 MB)
69 19:52:11.564194 progress 75 % (35 MB)
70 19:52:11.576982 progress 80 % (37 MB)
71 19:52:11.589778 progress 85 % (39 MB)
72 19:52:11.602891 progress 90 % (42 MB)
73 19:52:11.615594 progress 95 % (44 MB)
74 19:52:11.628252 progress 100 % (47 MB)
75 19:52:11.628494 47 MB downloaded in 0.26 s (181.24 MB/s)
76 19:52:11.628652 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:52:11.628890 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:52:11.628977 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:52:11.629063 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:52:11.629202 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:52:11.629271 saving as /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/dtb/mt8192-asurada-spherion-r0.dtb
83 19:52:11.629339 total size: 47278 (0 MB)
84 19:52:11.629401 No compression specified
85 19:52:11.630611 progress 69 % (0 MB)
86 19:52:11.630887 progress 100 % (0 MB)
87 19:52:11.631043 0 MB downloaded in 0.00 s (26.50 MB/s)
88 19:52:11.631167 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:52:11.631409 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:52:11.631509 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:52:11.631589 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:52:11.631700 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 19:52:11.631770 saving as /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/nfsrootfs/full.rootfs.tar
95 19:52:11.631830 total size: 125290964 (119 MB)
96 19:52:11.631891 Using unxz to decompress xz
97 19:52:11.636116 progress 0 % (0 MB)
98 19:52:11.964929 progress 5 % (6 MB)
99 19:52:12.298422 progress 10 % (11 MB)
100 19:52:12.627313 progress 15 % (17 MB)
101 19:52:12.811598 progress 20 % (23 MB)
102 19:52:12.985657 progress 25 % (29 MB)
103 19:52:13.332353 progress 30 % (35 MB)
104 19:52:13.682513 progress 35 % (41 MB)
105 19:52:14.070557 progress 40 % (47 MB)
106 19:52:14.445193 progress 45 % (53 MB)
107 19:52:14.828638 progress 50 % (59 MB)
108 19:52:15.192717 progress 55 % (65 MB)
109 19:52:15.571616 progress 60 % (71 MB)
110 19:52:15.924564 progress 65 % (77 MB)
111 19:52:16.304178 progress 70 % (83 MB)
112 19:52:16.685306 progress 75 % (89 MB)
113 19:52:17.102954 progress 80 % (95 MB)
114 19:52:17.529492 progress 85 % (101 MB)
115 19:52:17.773962 progress 90 % (107 MB)
116 19:52:18.118088 progress 95 % (113 MB)
117 19:52:18.495233 progress 100 % (119 MB)
118 19:52:18.500858 119 MB downloaded in 6.87 s (17.40 MB/s)
119 19:52:18.501157 end: 1.4.1 http-download (duration 00:00:07) [common]
121 19:52:18.501453 end: 1.4 download-retry (duration 00:00:07) [common]
122 19:52:18.501543 start: 1.5 download-retry (timeout 00:09:53) [common]
123 19:52:18.501629 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 19:52:18.501784 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 19:52:18.501857 saving as /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/modules/modules.tar
126 19:52:18.501918 total size: 8635496 (8 MB)
127 19:52:18.501981 Using unxz to decompress xz
128 19:52:18.506233 progress 0 % (0 MB)
129 19:52:18.528172 progress 5 % (0 MB)
130 19:52:18.550522 progress 10 % (0 MB)
131 19:52:18.576875 progress 15 % (1 MB)
132 19:52:18.602242 progress 20 % (1 MB)
133 19:52:18.628265 progress 25 % (2 MB)
134 19:52:18.657160 progress 30 % (2 MB)
135 19:52:18.682511 progress 35 % (2 MB)
136 19:52:18.707584 progress 40 % (3 MB)
137 19:52:18.732669 progress 45 % (3 MB)
138 19:52:18.759568 progress 50 % (4 MB)
139 19:52:18.785300 progress 55 % (4 MB)
140 19:52:18.811630 progress 60 % (4 MB)
141 19:52:18.834574 progress 65 % (5 MB)
142 19:52:18.859574 progress 70 % (5 MB)
143 19:52:18.884117 progress 75 % (6 MB)
144 19:52:18.910926 progress 80 % (6 MB)
145 19:52:18.943424 progress 85 % (7 MB)
146 19:52:18.969190 progress 90 % (7 MB)
147 19:52:18.993758 progress 95 % (7 MB)
148 19:52:19.017014 progress 100 % (8 MB)
149 19:52:19.022698 8 MB downloaded in 0.52 s (15.81 MB/s)
150 19:52:19.023072 end: 1.5.1 http-download (duration 00:00:01) [common]
152 19:52:19.023508 end: 1.5 download-retry (duration 00:00:01) [common]
153 19:52:19.023643 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 19:52:19.023785 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 19:52:21.197979 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11899560/extract-nfsrootfs-d9ma_j26
156 19:52:21.198197 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 19:52:21.198304 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 19:52:21.198485 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6
159 19:52:21.198617 makedir: /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin
160 19:52:21.198718 makedir: /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/tests
161 19:52:21.198817 makedir: /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/results
162 19:52:21.198922 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-add-keys
163 19:52:21.199067 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-add-sources
164 19:52:21.199194 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-background-process-start
165 19:52:21.199322 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-background-process-stop
166 19:52:21.199489 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-common-functions
167 19:52:21.199614 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-echo-ipv4
168 19:52:21.199740 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-install-packages
169 19:52:21.199864 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-installed-packages
170 19:52:21.199990 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-os-build
171 19:52:21.200115 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-probe-channel
172 19:52:21.200239 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-probe-ip
173 19:52:21.200363 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-target-ip
174 19:52:21.200487 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-target-mac
175 19:52:21.200610 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-target-storage
176 19:52:21.200736 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-test-case
177 19:52:21.200864 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-test-event
178 19:52:21.200987 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-test-feedback
179 19:52:21.201109 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-test-raise
180 19:52:21.201232 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-test-reference
181 19:52:21.201355 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-test-runner
182 19:52:21.201478 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-test-set
183 19:52:21.201600 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-test-shell
184 19:52:21.201725 Updating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-install-packages (oe)
185 19:52:21.201881 Updating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/bin/lava-installed-packages (oe)
186 19:52:21.202004 Creating /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/environment
187 19:52:21.202110 LAVA metadata
188 19:52:21.202181 - LAVA_JOB_ID=11899560
189 19:52:21.202244 - LAVA_DISPATCHER_IP=192.168.201.1
190 19:52:21.202350 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 19:52:21.202416 skipped lava-vland-overlay
192 19:52:21.202490 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 19:52:21.202568 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 19:52:21.202627 skipped lava-multinode-overlay
195 19:52:21.202700 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 19:52:21.202776 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 19:52:21.202851 Loading test definitions
198 19:52:21.202940 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 19:52:21.203010 Using /lava-11899560 at stage 0
200 19:52:21.203320 uuid=11899560_1.6.2.3.1 testdef=None
201 19:52:21.203657 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 19:52:21.203745 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 19:52:21.204264 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 19:52:21.204485 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 19:52:21.205132 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 19:52:21.205361 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 19:52:21.205977 runner path: /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/0/tests/0_dmesg test_uuid 11899560_1.6.2.3.1
210 19:52:21.206135 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 19:52:21.206358 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 19:52:21.206428 Using /lava-11899560 at stage 1
214 19:52:21.206736 uuid=11899560_1.6.2.3.5 testdef=None
215 19:52:21.206824 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 19:52:21.206906 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 19:52:21.207373 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 19:52:21.207626 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 19:52:21.208269 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 19:52:21.208497 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 19:52:21.209135 runner path: /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/1/tests/1_bootrr test_uuid 11899560_1.6.2.3.5
224 19:52:21.209290 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 19:52:21.209491 Creating lava-test-runner.conf files
227 19:52:21.209553 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/0 for stage 0
228 19:52:21.209644 - 0_dmesg
229 19:52:21.209723 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899560/lava-overlay-_ollfgb6/lava-11899560/1 for stage 1
230 19:52:21.209813 - 1_bootrr
231 19:52:21.209907 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 19:52:21.209988 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 19:52:21.217502 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 19:52:21.217674 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 19:52:21.217788 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 19:52:21.217875 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 19:52:21.217960 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 19:52:21.339423 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 19:52:21.339827 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 19:52:21.339949 extracting modules file /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899560/extract-nfsrootfs-d9ma_j26
241 19:52:21.563369 extracting modules file /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899560/extract-overlay-ramdisk-rnp5l9qr/ramdisk
242 19:52:21.795895 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 19:52:21.796080 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 19:52:21.796181 [common] Applying overlay to NFS
245 19:52:21.796251 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899560/compress-overlay-pedmbt_f/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11899560/extract-nfsrootfs-d9ma_j26
246 19:52:21.804502 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 19:52:21.804668 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 19:52:21.804765 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 19:52:21.804854 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 19:52:21.804935 Building ramdisk /var/lib/lava/dispatcher/tmp/11899560/extract-overlay-ramdisk-rnp5l9qr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11899560/extract-overlay-ramdisk-rnp5l9qr/ramdisk
251 19:52:22.128194 >> 119376 blocks
252 19:52:24.051937 rename /var/lib/lava/dispatcher/tmp/11899560/extract-overlay-ramdisk-rnp5l9qr/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/ramdisk/ramdisk.cpio.gz
253 19:52:24.052395 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 19:52:24.052527 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 19:52:24.052639 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 19:52:24.052753 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/kernel/Image'
257 19:52:36.825398 Returned 0 in 12 seconds
258 19:52:36.926324 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/kernel/image.itb
259 19:52:37.305573 output: FIT description: Kernel Image image with one or more FDT blobs
260 19:52:37.305939 output: Created: Sat Oct 28 20:52:37 2023
261 19:52:37.306017 output: Image 0 (kernel-1)
262 19:52:37.306083 output: Description:
263 19:52:37.306146 output: Created: Sat Oct 28 20:52:37 2023
264 19:52:37.306209 output: Type: Kernel Image
265 19:52:37.306268 output: Compression: lzma compressed
266 19:52:37.306325 output: Data Size: 11047522 Bytes = 10788.60 KiB = 10.54 MiB
267 19:52:37.306387 output: Architecture: AArch64
268 19:52:37.306447 output: OS: Linux
269 19:52:37.306504 output: Load Address: 0x00000000
270 19:52:37.306564 output: Entry Point: 0x00000000
271 19:52:37.306621 output: Hash algo: crc32
272 19:52:37.306678 output: Hash value: da40eda2
273 19:52:37.306735 output: Image 1 (fdt-1)
274 19:52:37.306789 output: Description: mt8192-asurada-spherion-r0
275 19:52:37.306842 output: Created: Sat Oct 28 20:52:37 2023
276 19:52:37.306895 output: Type: Flat Device Tree
277 19:52:37.306947 output: Compression: uncompressed
278 19:52:37.307000 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 19:52:37.307053 output: Architecture: AArch64
280 19:52:37.307106 output: Hash algo: crc32
281 19:52:37.307157 output: Hash value: cc4352de
282 19:52:37.307210 output: Image 2 (ramdisk-1)
283 19:52:37.307261 output: Description: unavailable
284 19:52:37.307314 output: Created: Sat Oct 28 20:52:37 2023
285 19:52:37.307367 output: Type: RAMDisk Image
286 19:52:37.307453 output: Compression: Unknown Compression
287 19:52:37.307519 output: Data Size: 17794236 Bytes = 17377.18 KiB = 16.97 MiB
288 19:52:37.307572 output: Architecture: AArch64
289 19:52:37.307625 output: OS: Linux
290 19:52:37.307677 output: Load Address: unavailable
291 19:52:37.307730 output: Entry Point: unavailable
292 19:52:37.307782 output: Hash algo: crc32
293 19:52:37.307834 output: Hash value: 07165e8d
294 19:52:37.307887 output: Default Configuration: 'conf-1'
295 19:52:37.307939 output: Configuration 0 (conf-1)
296 19:52:37.307991 output: Description: mt8192-asurada-spherion-r0
297 19:52:37.308044 output: Kernel: kernel-1
298 19:52:37.308096 output: Init Ramdisk: ramdisk-1
299 19:52:37.308148 output: FDT: fdt-1
300 19:52:37.308200 output: Loadables: kernel-1
301 19:52:37.308252 output:
302 19:52:37.308459 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 19:52:37.308561 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 19:52:37.308663 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 19:52:37.308759 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
306 19:52:37.308837 No LXC device requested
307 19:52:37.308914 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 19:52:37.308999 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
309 19:52:37.309077 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 19:52:37.309149 Checking files for TFTP limit of 4294967296 bytes.
311 19:52:37.309652 end: 1 tftp-deploy (duration 00:00:26) [common]
312 19:52:37.309758 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 19:52:37.309852 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 19:52:37.309978 substitutions:
315 19:52:37.310045 - {DTB}: 11899560/tftp-deploy-11qjant5/dtb/mt8192-asurada-spherion-r0.dtb
316 19:52:37.310109 - {INITRD}: 11899560/tftp-deploy-11qjant5/ramdisk/ramdisk.cpio.gz
317 19:52:37.310168 - {KERNEL}: 11899560/tftp-deploy-11qjant5/kernel/Image
318 19:52:37.310226 - {LAVA_MAC}: None
319 19:52:37.310282 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11899560/extract-nfsrootfs-d9ma_j26
320 19:52:37.310338 - {NFS_SERVER_IP}: 192.168.201.1
321 19:52:37.310393 - {PRESEED_CONFIG}: None
322 19:52:37.310447 - {PRESEED_LOCAL}: None
323 19:52:37.310501 - {RAMDISK}: 11899560/tftp-deploy-11qjant5/ramdisk/ramdisk.cpio.gz
324 19:52:37.310556 - {ROOT_PART}: None
325 19:52:37.310609 - {ROOT}: None
326 19:52:37.310663 - {SERVER_IP}: 192.168.201.1
327 19:52:37.310716 - {TEE}: None
328 19:52:37.310770 Parsed boot commands:
329 19:52:37.310825 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 19:52:37.311008 Parsed boot commands: tftpboot 192.168.201.1 11899560/tftp-deploy-11qjant5/kernel/image.itb 11899560/tftp-deploy-11qjant5/kernel/cmdline
331 19:52:37.311094 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 19:52:37.311175 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 19:52:37.311267 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 19:52:37.311354 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 19:52:37.311435 Not connected, no need to disconnect.
336 19:52:37.311510 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 19:52:37.311596 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 19:52:37.311664 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
339 19:52:37.315619 Setting prompt string to ['lava-test: # ']
340 19:52:37.315997 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 19:52:37.316112 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 19:52:37.316203 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 19:52:37.316295 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 19:52:37.316533 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
345 19:52:42.451637 >> Command sent successfully.
346 19:52:42.462820 Returned 0 in 5 seconds
347 19:52:42.564106 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 19:52:42.565549 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 19:52:42.566046 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 19:52:42.566480 Setting prompt string to 'Starting depthcharge on Spherion...'
352 19:52:42.566836 Changing prompt to 'Starting depthcharge on Spherion...'
353 19:52:42.567206 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 19:52:42.568463 [Enter `^Ec?' for help]
355 19:52:42.725946
356 19:52:42.726492
357 19:52:42.726918 F0: 102B 0000
358 19:52:42.727263
359 19:52:42.727638 F3: 1001 0000 [0200]
360 19:52:42.729515
361 19:52:42.730042 F3: 1001 0000
362 19:52:42.730392
363 19:52:42.730708 F7: 102D 0000
364 19:52:42.731013
365 19:52:42.732651 F1: 0000 0000
366 19:52:42.733180
367 19:52:42.733527 V0: 0000 0000 [0001]
368 19:52:42.733860
369 19:52:42.735898 00: 0007 8000
370 19:52:42.736346
371 19:52:42.736685 01: 0000 0000
372 19:52:42.737008
373 19:52:42.738882 BP: 0C00 0209 [0000]
374 19:52:42.739309
375 19:52:42.739691 G0: 1182 0000
376 19:52:42.740009
377 19:52:42.742852 EC: 0000 0021 [4000]
378 19:52:42.743278
379 19:52:42.743661 S7: 0000 0000 [0000]
380 19:52:42.743980
381 19:52:42.746639 CC: 0000 0000 [0001]
382 19:52:42.747067
383 19:52:42.747448 T0: 0000 0040 [010F]
384 19:52:42.747783
385 19:52:42.748130 Jump to BL
386 19:52:42.748454
387 19:52:42.773048
388 19:52:42.773572
389 19:52:42.773909
390 19:52:42.780128 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 19:52:42.783748 ARM64: Exception handlers installed.
392 19:52:42.787404 ARM64: Testing exception
393 19:52:42.790910 ARM64: Done test exception
394 19:52:42.798125 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 19:52:42.807639 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 19:52:42.814839 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 19:52:42.824621 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 19:52:42.831292 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 19:52:42.838054 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 19:52:42.849994 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 19:52:42.856227 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 19:52:42.875897 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 19:52:42.879560 WDT: Last reset was cold boot
404 19:52:42.882323 SPI1(PAD0) initialized at 2873684 Hz
405 19:52:42.885982 SPI5(PAD0) initialized at 992727 Hz
406 19:52:42.888675 VBOOT: Loading verstage.
407 19:52:42.895527 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 19:52:42.899205 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 19:52:42.901938 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 19:52:42.905919 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 19:52:42.912973 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 19:52:42.920269 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 19:52:42.931339 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 19:52:42.931905
415 19:52:42.932250
416 19:52:42.940622 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 19:52:42.944161 ARM64: Exception handlers installed.
418 19:52:42.947454 ARM64: Testing exception
419 19:52:42.947884 ARM64: Done test exception
420 19:52:42.954214 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 19:52:42.957537 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 19:52:42.971937 Probing TPM: . done!
423 19:52:42.972456 TPM ready after 0 ms
424 19:52:42.978503 Connected to device vid:did:rid of 1ae0:0028:00
425 19:52:42.985108 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 19:52:43.026888 Initialized TPM device CR50 revision 0
427 19:52:43.038428 tlcl_send_startup: Startup return code is 0
428 19:52:43.038951 TPM: setup succeeded
429 19:52:43.050753 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 19:52:43.059106 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 19:52:43.071107 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 19:52:43.080563 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 19:52:43.083517 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 19:52:43.087671 in-header: 03 07 00 00 08 00 00 00
435 19:52:43.091047 in-data: aa e4 47 04 13 02 00 00
436 19:52:43.094784 Chrome EC: UHEPI supported
437 19:52:43.101502 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 19:52:43.105681 in-header: 03 9d 00 00 08 00 00 00
439 19:52:43.109306 in-data: 10 20 20 08 00 00 00 00
440 19:52:43.109829 Phase 1
441 19:52:43.112769 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 19:52:43.119616 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 19:52:43.127291 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 19:52:43.127879 Recovery requested (1009000e)
445 19:52:43.135492 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 19:52:43.140888 tlcl_extend: response is 0
447 19:52:43.150675 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 19:52:43.154839 tlcl_extend: response is 0
449 19:52:43.160866 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 19:52:43.181754 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 19:52:43.189364 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 19:52:43.189790
453 19:52:43.190203
454 19:52:43.197061 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 19:52:43.201045 ARM64: Exception handlers installed.
456 19:52:43.204458 ARM64: Testing exception
457 19:52:43.208020 ARM64: Done test exception
458 19:52:43.228105 pmic_efuse_setting: Set efuses in 11 msecs
459 19:52:43.231133 pmwrap_interface_init: Select PMIF_VLD_RDY
460 19:52:43.234456 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 19:52:43.242200 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 19:52:43.245303 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 19:52:43.249271 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 19:52:43.256470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 19:52:43.260259 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 19:52:43.263941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 19:52:43.271321 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 19:52:43.274505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 19:52:43.278141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 19:52:43.284363 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 19:52:43.287835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 19:52:43.294393 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 19:52:43.297505 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 19:52:43.304280 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 19:52:43.310686 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 19:52:43.318104 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 19:52:43.320778 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 19:52:43.327644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 19:52:43.336145 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 19:52:43.338783 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 19:52:43.342786 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 19:52:43.349408 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 19:52:43.356183 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 19:52:43.359766 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 19:52:43.366261 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 19:52:43.369706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 19:52:43.376904 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 19:52:43.380415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 19:52:43.386967 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 19:52:43.391065 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 19:52:43.394537 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 19:52:43.402152 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 19:52:43.405489 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 19:52:43.409303 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 19:52:43.416461 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 19:52:43.419980 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 19:52:43.427007 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 19:52:43.430402 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 19:52:43.433268 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 19:52:43.440284 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 19:52:43.443817 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 19:52:43.447089 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 19:52:43.453713 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 19:52:43.457344 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 19:52:43.460428 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 19:52:43.463367 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 19:52:43.470281 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 19:52:43.473943 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 19:52:43.477438 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 19:52:43.480425 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 19:52:43.490439 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 19:52:43.496956 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 19:52:43.503635 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 19:52:43.510913 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 19:52:43.520399 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 19:52:43.523709 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 19:52:43.527081 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 19:52:43.533469 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 19:52:43.540115 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xc
520 19:52:43.547012 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 19:52:43.550500 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 19:52:43.553610 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 19:52:43.564143 [RTC]rtc_get_frequency_meter,154: input=15, output=794
524 19:52:43.568007 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
525 19:52:43.574365 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
526 19:52:43.577470 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
527 19:52:43.580582 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
528 19:52:43.584283 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
529 19:52:43.587594 ADC[4]: Raw value=895191 ID=7
530 19:52:43.591033 ADC[3]: Raw value=213070 ID=1
531 19:52:43.594171 RAM Code: 0x71
532 19:52:43.597653 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
533 19:52:43.601217 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
534 19:52:43.611477 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
535 19:52:43.618248 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
536 19:52:43.621431 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
537 19:52:43.624433 in-header: 03 07 00 00 08 00 00 00
538 19:52:43.628052 in-data: aa e4 47 04 13 02 00 00
539 19:52:43.631632 Chrome EC: UHEPI supported
540 19:52:43.635205 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
541 19:52:43.639310 in-header: 03 d5 00 00 08 00 00 00
542 19:52:43.643459 in-data: 98 20 60 08 00 00 00 00
543 19:52:43.646338 MRC: failed to locate region type 0.
544 19:52:43.653502 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
545 19:52:43.656729 DRAM-K: Running full calibration
546 19:52:43.663677 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
547 19:52:43.663946 header.status = 0x0
548 19:52:43.666676 header.version = 0x6 (expected: 0x6)
549 19:52:43.670216 header.size = 0xd00 (expected: 0xd00)
550 19:52:43.673795 header.flags = 0x0
551 19:52:43.676861 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
552 19:52:43.695939 read SPI 0x72590 0x1c583: 12496 us, 9290 KB/s, 74.320 Mbps
553 19:52:43.702981 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
554 19:52:43.705909 dram_init: ddr_geometry: 2
555 19:52:43.709598 [EMI] MDL number = 2
556 19:52:43.709750 [EMI] Get MDL freq = 0
557 19:52:43.712915 dram_init: ddr_type: 0
558 19:52:43.713067 is_discrete_lpddr4: 1
559 19:52:43.716083 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
560 19:52:43.716237
561 19:52:43.716357
562 19:52:43.719291 [Bian_co] ETT version 0.0.0.1
563 19:52:43.725839 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
564 19:52:43.725992
565 19:52:43.728950 dramc_set_vcore_voltage set vcore to 650000
566 19:52:43.732628 Read voltage for 800, 4
567 19:52:43.732781 Vio18 = 0
568 19:52:43.732903 Vcore = 650000
569 19:52:43.735653 Vdram = 0
570 19:52:43.735805 Vddq = 0
571 19:52:43.735925 Vmddr = 0
572 19:52:43.739196 dram_init: config_dvfs: 1
573 19:52:43.742602 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
574 19:52:43.749220 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
575 19:52:43.752276 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
576 19:52:43.755378 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
577 19:52:43.759211 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
578 19:52:43.762168 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
579 19:52:43.765456 MEM_TYPE=3, freq_sel=18
580 19:52:43.770801 sv_algorithm_assistance_LP4_1600
581 19:52:43.772105 ============ PULL DRAM RESETB DOWN ============
582 19:52:43.778976 ========== PULL DRAM RESETB DOWN end =========
583 19:52:43.782155 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
584 19:52:43.785647 ===================================
585 19:52:43.789307 LPDDR4 DRAM CONFIGURATION
586 19:52:43.792399 ===================================
587 19:52:43.792558 EX_ROW_EN[0] = 0x0
588 19:52:43.795786 EX_ROW_EN[1] = 0x0
589 19:52:43.795951 LP4Y_EN = 0x0
590 19:52:43.798955 WORK_FSP = 0x0
591 19:52:43.799161 WL = 0x2
592 19:52:43.802221 RL = 0x2
593 19:52:43.802375 BL = 0x2
594 19:52:43.805555 RPST = 0x0
595 19:52:43.805710 RD_PRE = 0x0
596 19:52:43.809322 WR_PRE = 0x1
597 19:52:43.809475 WR_PST = 0x0
598 19:52:43.812407 DBI_WR = 0x0
599 19:52:43.812561 DBI_RD = 0x0
600 19:52:43.815651 OTF = 0x1
601 19:52:43.818722 ===================================
602 19:52:43.822155 ===================================
603 19:52:43.822308 ANA top config
604 19:52:43.826515 ===================================
605 19:52:43.829812 DLL_ASYNC_EN = 0
606 19:52:43.834231 ALL_SLAVE_EN = 1
607 19:52:43.834386 NEW_RANK_MODE = 1
608 19:52:43.837168 DLL_IDLE_MODE = 1
609 19:52:43.840856 LP45_APHY_COMB_EN = 1
610 19:52:43.841010 TX_ODT_DIS = 1
611 19:52:43.844547 NEW_8X_MODE = 1
612 19:52:43.848587 ===================================
613 19:52:43.852716 ===================================
614 19:52:43.856436 data_rate = 1600
615 19:52:43.856592 CKR = 1
616 19:52:43.859957 DQ_P2S_RATIO = 8
617 19:52:43.863443 ===================================
618 19:52:43.867248 CA_P2S_RATIO = 8
619 19:52:43.867482 DQ_CA_OPEN = 0
620 19:52:43.871371 DQ_SEMI_OPEN = 0
621 19:52:43.874881 CA_SEMI_OPEN = 0
622 19:52:43.878101 CA_FULL_RATE = 0
623 19:52:43.882116 DQ_CKDIV4_EN = 1
624 19:52:43.882327 CA_CKDIV4_EN = 1
625 19:52:43.885868 CA_PREDIV_EN = 0
626 19:52:43.889347 PH8_DLY = 0
627 19:52:43.889617 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
628 19:52:43.893743 DQ_AAMCK_DIV = 4
629 19:52:43.897203 CA_AAMCK_DIV = 4
630 19:52:43.900533 CA_ADMCK_DIV = 4
631 19:52:43.900764 DQ_TRACK_CA_EN = 0
632 19:52:43.904306 CA_PICK = 800
633 19:52:43.908081 CA_MCKIO = 800
634 19:52:43.911262 MCKIO_SEMI = 0
635 19:52:43.914537 PLL_FREQ = 3068
636 19:52:43.914674 DQ_UI_PI_RATIO = 32
637 19:52:43.918227 CA_UI_PI_RATIO = 0
638 19:52:43.921486 ===================================
639 19:52:43.925098 ===================================
640 19:52:43.928248 memory_type:LPDDR4
641 19:52:43.931227 GP_NUM : 10
642 19:52:43.931310 SRAM_EN : 1
643 19:52:43.935086 MD32_EN : 0
644 19:52:43.938101 ===================================
645 19:52:43.938187 [ANA_INIT] >>>>>>>>>>>>>>
646 19:52:43.941634 <<<<<< [CONFIGURE PHASE]: ANA_TX
647 19:52:43.944662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
648 19:52:43.948048 ===================================
649 19:52:43.951494 data_rate = 1600,PCW = 0X7600
650 19:52:43.954705 ===================================
651 19:52:43.958185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
652 19:52:43.964802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
653 19:52:43.971545 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
654 19:52:43.974553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
655 19:52:43.978066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
656 19:52:43.982108 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
657 19:52:43.982196 [ANA_INIT] flow start
658 19:52:43.985547 [ANA_INIT] PLL >>>>>>>>
659 19:52:43.989012 [ANA_INIT] PLL <<<<<<<<
660 19:52:43.989121 [ANA_INIT] MIDPI >>>>>>>>
661 19:52:43.992771 [ANA_INIT] MIDPI <<<<<<<<
662 19:52:43.996721 [ANA_INIT] DLL >>>>>>>>
663 19:52:43.996809 [ANA_INIT] flow end
664 19:52:44.000222 ============ LP4 DIFF to SE enter ============
665 19:52:44.003977 ============ LP4 DIFF to SE exit ============
666 19:52:44.007528 [ANA_INIT] <<<<<<<<<<<<<
667 19:52:44.011585 [Flow] Enable top DCM control >>>>>
668 19:52:44.015564 [Flow] Enable top DCM control <<<<<
669 19:52:44.015687 Enable DLL master slave shuffle
670 19:52:44.023137 ==============================================================
671 19:52:44.023223 Gating Mode config
672 19:52:44.029978 ==============================================================
673 19:52:44.033209 Config description:
674 19:52:44.042885 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
675 19:52:44.049212 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
676 19:52:44.052754 SELPH_MODE 0: By rank 1: By Phase
677 19:52:44.059489 ==============================================================
678 19:52:44.062866 GAT_TRACK_EN = 1
679 19:52:44.062951 RX_GATING_MODE = 2
680 19:52:44.066055 RX_GATING_TRACK_MODE = 2
681 19:52:44.069676 SELPH_MODE = 1
682 19:52:44.072570 PICG_EARLY_EN = 1
683 19:52:44.076291 VALID_LAT_VALUE = 1
684 19:52:44.082953 ==============================================================
685 19:52:44.086041 Enter into Gating configuration >>>>
686 19:52:44.089527 Exit from Gating configuration <<<<
687 19:52:44.092867 Enter into DVFS_PRE_config >>>>>
688 19:52:44.102806 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
689 19:52:44.106322 Exit from DVFS_PRE_config <<<<<
690 19:52:44.110099 Enter into PICG configuration >>>>
691 19:52:44.113008 Exit from PICG configuration <<<<
692 19:52:44.116137 [RX_INPUT] configuration >>>>>
693 19:52:44.116223 [RX_INPUT] configuration <<<<<
694 19:52:44.122896 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
695 19:52:44.129447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
696 19:52:44.132939 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
697 19:52:44.139640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
698 19:52:44.146508 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
699 19:52:44.153349 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
700 19:52:44.156885 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
701 19:52:44.160716 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
702 19:52:44.164167 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
703 19:52:44.168048 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
704 19:52:44.175338 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
705 19:52:44.178409 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
706 19:52:44.182442 ===================================
707 19:52:44.182530 LPDDR4 DRAM CONFIGURATION
708 19:52:44.186365 ===================================
709 19:52:44.189813 EX_ROW_EN[0] = 0x0
710 19:52:44.189928 EX_ROW_EN[1] = 0x0
711 19:52:44.193491 LP4Y_EN = 0x0
712 19:52:44.193574 WORK_FSP = 0x0
713 19:52:44.197284 WL = 0x2
714 19:52:44.197384 RL = 0x2
715 19:52:44.200776 BL = 0x2
716 19:52:44.200859 RPST = 0x0
717 19:52:44.204647 RD_PRE = 0x0
718 19:52:44.204729 WR_PRE = 0x1
719 19:52:44.208048 WR_PST = 0x0
720 19:52:44.208130 DBI_WR = 0x0
721 19:52:44.211816 DBI_RD = 0x0
722 19:52:44.211937 OTF = 0x1
723 19:52:44.215234 ===================================
724 19:52:44.218447 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
725 19:52:44.222629 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
726 19:52:44.226309 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 19:52:44.229521 ===================================
728 19:52:44.233513 LPDDR4 DRAM CONFIGURATION
729 19:52:44.236657 ===================================
730 19:52:44.236794 EX_ROW_EN[0] = 0x10
731 19:52:44.240640 EX_ROW_EN[1] = 0x0
732 19:52:44.240727 LP4Y_EN = 0x0
733 19:52:44.244181 WORK_FSP = 0x0
734 19:52:44.244265 WL = 0x2
735 19:52:44.248012 RL = 0x2
736 19:52:44.248095 BL = 0x2
737 19:52:44.251711 RPST = 0x0
738 19:52:44.251793 RD_PRE = 0x0
739 19:52:44.254841 WR_PRE = 0x1
740 19:52:44.254922 WR_PST = 0x0
741 19:52:44.258762 DBI_WR = 0x0
742 19:52:44.258846 DBI_RD = 0x0
743 19:52:44.262349 OTF = 0x1
744 19:52:44.266266 ===================================
745 19:52:44.269404 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
746 19:52:44.274427 nWR fixed to 40
747 19:52:44.278119 [ModeRegInit_LP4] CH0 RK0
748 19:52:44.278203 [ModeRegInit_LP4] CH0 RK1
749 19:52:44.281737 [ModeRegInit_LP4] CH1 RK0
750 19:52:44.281821 [ModeRegInit_LP4] CH1 RK1
751 19:52:44.285541 match AC timing 13
752 19:52:44.288583 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
753 19:52:44.292723 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
754 19:52:44.299628 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
755 19:52:44.303101 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
756 19:52:44.306661 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
757 19:52:44.310174 [EMI DOE] emi_dcm 0
758 19:52:44.313934 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
759 19:52:44.314017 ==
760 19:52:44.317878 Dram Type= 6, Freq= 0, CH_0, rank 0
761 19:52:44.321225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
762 19:52:44.321310 ==
763 19:52:44.328456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
764 19:52:44.332102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
765 19:52:44.342373 [CA 0] Center 38 (7~69) winsize 63
766 19:52:44.345740 [CA 1] Center 37 (7~68) winsize 62
767 19:52:44.349730 [CA 2] Center 35 (5~66) winsize 62
768 19:52:44.353587 [CA 3] Center 35 (5~66) winsize 62
769 19:52:44.356930 [CA 4] Center 34 (4~65) winsize 62
770 19:52:44.360692 [CA 5] Center 34 (4~65) winsize 62
771 19:52:44.360776
772 19:52:44.364174 [CmdBusTrainingLP45] Vref(ca) range 1: 34
773 19:52:44.364259
774 19:52:44.368064 [CATrainingPosCal] consider 1 rank data
775 19:52:44.368148 u2DelayCellTimex100 = 270/100 ps
776 19:52:44.372024 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
777 19:52:44.375768 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
778 19:52:44.379209 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
779 19:52:44.382973 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
780 19:52:44.386740 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
781 19:52:44.390232 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
782 19:52:44.390317
783 19:52:44.393558 CA PerBit enable=1, Macro0, CA PI delay=34
784 19:52:44.393641
785 19:52:44.398021 [CBTSetCACLKResult] CA Dly = 34
786 19:52:44.401026 CS Dly: 6 (0~37)
787 19:52:44.401109 ==
788 19:52:44.405018 Dram Type= 6, Freq= 0, CH_0, rank 1
789 19:52:44.408980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 19:52:44.409097 ==
791 19:52:44.412599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
792 19:52:44.419119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
793 19:52:44.428571 [CA 0] Center 38 (7~69) winsize 63
794 19:52:44.432411 [CA 1] Center 38 (7~69) winsize 63
795 19:52:44.436180 [CA 2] Center 35 (5~66) winsize 62
796 19:52:44.439519 [CA 3] Center 35 (5~66) winsize 62
797 19:52:44.442975 [CA 4] Center 34 (4~65) winsize 62
798 19:52:44.447143 [CA 5] Center 34 (4~65) winsize 62
799 19:52:44.447267
800 19:52:44.450352 [CmdBusTrainingLP45] Vref(ca) range 1: 32
801 19:52:44.450475
802 19:52:44.454311 [CATrainingPosCal] consider 2 rank data
803 19:52:44.454394 u2DelayCellTimex100 = 270/100 ps
804 19:52:44.460686 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
805 19:52:44.464113 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
806 19:52:44.467272 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
807 19:52:44.470747 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
808 19:52:44.474345 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
809 19:52:44.477689 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
810 19:52:44.477800
811 19:52:44.480714 CA PerBit enable=1, Macro0, CA PI delay=34
812 19:52:44.480822
813 19:52:44.484055 [CBTSetCACLKResult] CA Dly = 34
814 19:52:44.487620 CS Dly: 6 (0~38)
815 19:52:44.487698
816 19:52:44.490890 ----->DramcWriteLeveling(PI) begin...
817 19:52:44.490975 ==
818 19:52:44.493907 Dram Type= 6, Freq= 0, CH_0, rank 0
819 19:52:44.497512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
820 19:52:44.497648 ==
821 19:52:44.500558 Write leveling (Byte 0): 33 => 33
822 19:52:44.503973 Write leveling (Byte 1): 31 => 31
823 19:52:44.507809 DramcWriteLeveling(PI) end<-----
824 19:52:44.507912
825 19:52:44.508005 ==
826 19:52:44.511228 Dram Type= 6, Freq= 0, CH_0, rank 0
827 19:52:44.514329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
828 19:52:44.514432 ==
829 19:52:44.517678 [Gating] SW mode calibration
830 19:52:44.524148 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
831 19:52:44.530646 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
832 19:52:44.534027 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
833 19:52:44.537164 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
834 19:52:44.543868 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
835 19:52:44.547410 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
836 19:52:44.550358 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 19:52:44.557011 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 19:52:44.560555 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 19:52:44.563715 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 19:52:44.568001 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 19:52:44.575359 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 19:52:44.579056 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 19:52:44.583019 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 19:52:44.585990 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 19:52:44.592718 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 19:52:44.596825 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 19:52:44.599632 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 19:52:44.603144 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 19:52:44.609521 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
850 19:52:44.613336 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
851 19:52:44.616400 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
852 19:52:44.623215 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 19:52:44.626404 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 19:52:44.629645 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 19:52:44.636656 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 19:52:44.639836 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 19:52:44.643125 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 19:52:44.646275 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 19:52:44.653538 0 9 12 | B1->B0 | 2a2a 3434 | 1 0 | (1 1) (0 0)
860 19:52:44.656540 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
861 19:52:44.660104 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
862 19:52:44.666214 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
863 19:52:44.669992 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
864 19:52:44.673546 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 19:52:44.680017 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
866 19:52:44.683228 0 10 8 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
867 19:52:44.686701 0 10 12 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
868 19:52:44.693309 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 19:52:44.696944 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 19:52:44.700303 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 19:52:44.706928 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 19:52:44.709781 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 19:52:44.713321 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 19:52:44.720187 0 11 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
875 19:52:44.723654 0 11 12 | B1->B0 | 3030 4242 | 1 0 | (0 0) (0 0)
876 19:52:44.726366 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
877 19:52:44.730390 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
878 19:52:44.736512 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
879 19:52:44.740326 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
880 19:52:44.743185 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 19:52:44.750254 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
882 19:52:44.753551 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
883 19:52:44.756881 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
884 19:52:44.763357 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 19:52:44.766972 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 19:52:44.769968 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 19:52:44.776820 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 19:52:44.779774 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 19:52:44.783416 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 19:52:44.790156 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 19:52:44.793021 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 19:52:44.796638 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 19:52:44.803361 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 19:52:44.806697 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 19:52:44.810107 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 19:52:44.816775 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 19:52:44.819874 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 19:52:44.823168 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
899 19:52:44.829971 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 19:52:44.830084 Total UI for P1: 0, mck2ui 16
901 19:52:44.832942 best dqsien dly found for B0: ( 0, 14, 8)
902 19:52:44.836313 Total UI for P1: 0, mck2ui 16
903 19:52:44.839789 best dqsien dly found for B1: ( 0, 14, 10)
904 19:52:44.843401 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
905 19:52:44.850018 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
906 19:52:44.850101
907 19:52:44.853201 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
908 19:52:44.856653 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
909 19:52:44.859901 [Gating] SW calibration Done
910 19:52:44.859983 ==
911 19:52:44.863140 Dram Type= 6, Freq= 0, CH_0, rank 0
912 19:52:44.866409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 19:52:44.866492 ==
914 19:52:44.866557 RX Vref Scan: 0
915 19:52:44.866617
916 19:52:44.869898 RX Vref 0 -> 0, step: 1
917 19:52:44.869980
918 19:52:44.873553 RX Delay -130 -> 252, step: 16
919 19:52:44.877080 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
920 19:52:44.880101 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
921 19:52:44.886448 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
922 19:52:44.889693 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
923 19:52:44.893198 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
924 19:52:44.896917 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
925 19:52:44.899646 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
926 19:52:44.906300 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
927 19:52:44.909950 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
928 19:52:44.913087 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
929 19:52:44.916392 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
930 19:52:44.919342 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
931 19:52:44.926582 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
932 19:52:44.929892 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
933 19:52:44.933078 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
934 19:52:44.936526 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
935 19:52:44.936608 ==
936 19:52:44.939382 Dram Type= 6, Freq= 0, CH_0, rank 0
937 19:52:44.946516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
938 19:52:44.946598 ==
939 19:52:44.946700 DQS Delay:
940 19:52:44.949383 DQS0 = 0, DQS1 = 0
941 19:52:44.949465 DQM Delay:
942 19:52:44.949568 DQM0 = 84, DQM1 = 69
943 19:52:44.953067 DQ Delay:
944 19:52:44.956284 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
945 19:52:44.959884 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
946 19:52:44.962799 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
947 19:52:44.966189 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
948 19:52:44.966271
949 19:52:44.966351
950 19:52:44.966425 ==
951 19:52:44.969332 Dram Type= 6, Freq= 0, CH_0, rank 0
952 19:52:44.972781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 19:52:44.972878 ==
954 19:52:44.972958
955 19:52:44.973018
956 19:52:44.976378 TX Vref Scan disable
957 19:52:44.976461 == TX Byte 0 ==
958 19:52:44.983492 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
959 19:52:44.986797 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
960 19:52:44.986879 == TX Byte 1 ==
961 19:52:44.993045 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
962 19:52:44.996697 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
963 19:52:44.996779 ==
964 19:52:44.999657 Dram Type= 6, Freq= 0, CH_0, rank 0
965 19:52:45.003290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 19:52:45.003374 ==
967 19:52:45.017206 TX Vref=22, minBit 7, minWin=26, winSum=438
968 19:52:45.020157 TX Vref=24, minBit 9, minWin=26, winSum=435
969 19:52:45.023352 TX Vref=26, minBit 4, minWin=27, winSum=441
970 19:52:45.026955 TX Vref=28, minBit 4, minWin=27, winSum=440
971 19:52:45.030545 TX Vref=30, minBit 10, minWin=26, winSum=439
972 19:52:45.037190 TX Vref=32, minBit 12, minWin=26, winSum=439
973 19:52:45.040028 [TxChooseVref] Worse bit 4, Min win 27, Win sum 441, Final Vref 26
974 19:52:45.040109
975 19:52:45.043515 Final TX Range 1 Vref 26
976 19:52:45.043597
977 19:52:45.043662 ==
978 19:52:45.046858 Dram Type= 6, Freq= 0, CH_0, rank 0
979 19:52:45.050683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 19:52:45.050766 ==
981 19:52:45.053553
982 19:52:45.053635
983 19:52:45.053699 TX Vref Scan disable
984 19:52:45.057266 == TX Byte 0 ==
985 19:52:45.060331 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
986 19:52:45.066760 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
987 19:52:45.066875 == TX Byte 1 ==
988 19:52:45.070460 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
989 19:52:45.077322 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
990 19:52:45.077405
991 19:52:45.077469 [DATLAT]
992 19:52:45.077529 Freq=800, CH0 RK0
993 19:52:45.077588
994 19:52:45.080266 DATLAT Default: 0xa
995 19:52:45.080348 0, 0xFFFF, sum = 0
996 19:52:45.083579 1, 0xFFFF, sum = 0
997 19:52:45.083694 2, 0xFFFF, sum = 0
998 19:52:45.087038 3, 0xFFFF, sum = 0
999 19:52:45.087121 4, 0xFFFF, sum = 0
1000 19:52:45.090642 5, 0xFFFF, sum = 0
1001 19:52:45.093894 6, 0xFFFF, sum = 0
1002 19:52:45.093978 7, 0xFFFF, sum = 0
1003 19:52:45.096901 8, 0xFFFF, sum = 0
1004 19:52:45.097012 9, 0x0, sum = 1
1005 19:52:45.097108 10, 0x0, sum = 2
1006 19:52:45.100169 11, 0x0, sum = 3
1007 19:52:45.100253 12, 0x0, sum = 4
1008 19:52:45.103695 best_step = 10
1009 19:52:45.103777
1010 19:52:45.103842 ==
1011 19:52:45.107289 Dram Type= 6, Freq= 0, CH_0, rank 0
1012 19:52:45.110161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1013 19:52:45.110243 ==
1014 19:52:45.113556 RX Vref Scan: 1
1015 19:52:45.113638
1016 19:52:45.113702 Set Vref Range= 32 -> 127
1017 19:52:45.116724
1018 19:52:45.116822 RX Vref 32 -> 127, step: 1
1019 19:52:45.116888
1020 19:52:45.120343 RX Delay -111 -> 252, step: 8
1021 19:52:45.120425
1022 19:52:45.123710 Set Vref, RX VrefLevel [Byte0]: 32
1023 19:52:45.127161 [Byte1]: 32
1024 19:52:45.127243
1025 19:52:45.130541 Set Vref, RX VrefLevel [Byte0]: 33
1026 19:52:45.133680 [Byte1]: 33
1027 19:52:45.137514
1028 19:52:45.137594 Set Vref, RX VrefLevel [Byte0]: 34
1029 19:52:45.141172 [Byte1]: 34
1030 19:52:45.145290
1031 19:52:45.145371 Set Vref, RX VrefLevel [Byte0]: 35
1032 19:52:45.148444 [Byte1]: 35
1033 19:52:45.153010
1034 19:52:45.153106 Set Vref, RX VrefLevel [Byte0]: 36
1035 19:52:45.156111 [Byte1]: 36
1036 19:52:45.160219
1037 19:52:45.160298 Set Vref, RX VrefLevel [Byte0]: 37
1038 19:52:45.163843 [Byte1]: 37
1039 19:52:45.168154
1040 19:52:45.168264 Set Vref, RX VrefLevel [Byte0]: 38
1041 19:52:45.171312 [Byte1]: 38
1042 19:52:45.175747
1043 19:52:45.175848 Set Vref, RX VrefLevel [Byte0]: 39
1044 19:52:45.179186 [Byte1]: 39
1045 19:52:45.183379
1046 19:52:45.183498 Set Vref, RX VrefLevel [Byte0]: 40
1047 19:52:45.186873 [Byte1]: 40
1048 19:52:45.190961
1049 19:52:45.191061 Set Vref, RX VrefLevel [Byte0]: 41
1050 19:52:45.194079 [Byte1]: 41
1051 19:52:45.198525
1052 19:52:45.198632 Set Vref, RX VrefLevel [Byte0]: 42
1053 19:52:45.202062 [Byte1]: 42
1054 19:52:45.206097
1055 19:52:45.206171 Set Vref, RX VrefLevel [Byte0]: 43
1056 19:52:45.209776 [Byte1]: 43
1057 19:52:45.214763
1058 19:52:45.214873 Set Vref, RX VrefLevel [Byte0]: 44
1059 19:52:45.217396 [Byte1]: 44
1060 19:52:45.222104
1061 19:52:45.222178 Set Vref, RX VrefLevel [Byte0]: 45
1062 19:52:45.225149 [Byte1]: 45
1063 19:52:45.229973
1064 19:52:45.230054 Set Vref, RX VrefLevel [Byte0]: 46
1065 19:52:45.233020 [Byte1]: 46
1066 19:52:45.237556
1067 19:52:45.237638 Set Vref, RX VrefLevel [Byte0]: 47
1068 19:52:45.240236 [Byte1]: 47
1069 19:52:45.244911
1070 19:52:45.244991 Set Vref, RX VrefLevel [Byte0]: 48
1071 19:52:45.248471 [Byte1]: 48
1072 19:52:45.253189
1073 19:52:45.253270 Set Vref, RX VrefLevel [Byte0]: 49
1074 19:52:45.256000 [Byte1]: 49
1075 19:52:45.260061
1076 19:52:45.260142 Set Vref, RX VrefLevel [Byte0]: 50
1077 19:52:45.263264 [Byte1]: 50
1078 19:52:45.267298
1079 19:52:45.267439 Set Vref, RX VrefLevel [Byte0]: 51
1080 19:52:45.271092 [Byte1]: 51
1081 19:52:45.275261
1082 19:52:45.275368 Set Vref, RX VrefLevel [Byte0]: 52
1083 19:52:45.278249 [Byte1]: 52
1084 19:52:45.282559
1085 19:52:45.282639 Set Vref, RX VrefLevel [Byte0]: 53
1086 19:52:45.286069 [Byte1]: 53
1087 19:52:45.290487
1088 19:52:45.290567 Set Vref, RX VrefLevel [Byte0]: 54
1089 19:52:45.293620 [Byte1]: 54
1090 19:52:45.297921
1091 19:52:45.298002 Set Vref, RX VrefLevel [Byte0]: 55
1092 19:52:45.301492 [Byte1]: 55
1093 19:52:45.305801
1094 19:52:45.305911 Set Vref, RX VrefLevel [Byte0]: 56
1095 19:52:45.308818 [Byte1]: 56
1096 19:52:45.313477
1097 19:52:45.313558 Set Vref, RX VrefLevel [Byte0]: 57
1098 19:52:45.316546 [Byte1]: 57
1099 19:52:45.320948
1100 19:52:45.321028 Set Vref, RX VrefLevel [Byte0]: 58
1101 19:52:45.324356 [Byte1]: 58
1102 19:52:45.328924
1103 19:52:45.329004 Set Vref, RX VrefLevel [Byte0]: 59
1104 19:52:45.331856 [Byte1]: 59
1105 19:52:45.336076
1106 19:52:45.336156 Set Vref, RX VrefLevel [Byte0]: 60
1107 19:52:45.339882 [Byte1]: 60
1108 19:52:45.343811
1109 19:52:45.343891 Set Vref, RX VrefLevel [Byte0]: 61
1110 19:52:45.347090 [Byte1]: 61
1111 19:52:45.351629
1112 19:52:45.351725 Set Vref, RX VrefLevel [Byte0]: 62
1113 19:52:45.354775 [Byte1]: 62
1114 19:52:45.359014
1115 19:52:45.359109 Set Vref, RX VrefLevel [Byte0]: 63
1116 19:52:45.362600 [Byte1]: 63
1117 19:52:45.367048
1118 19:52:45.367160 Set Vref, RX VrefLevel [Byte0]: 64
1119 19:52:45.370114 [Byte1]: 64
1120 19:52:45.374941
1121 19:52:45.375050 Set Vref, RX VrefLevel [Byte0]: 65
1122 19:52:45.377789 [Byte1]: 65
1123 19:52:45.381982
1124 19:52:45.382063 Set Vref, RX VrefLevel [Byte0]: 66
1125 19:52:45.385747 [Byte1]: 66
1126 19:52:45.390049
1127 19:52:45.390160 Set Vref, RX VrefLevel [Byte0]: 67
1128 19:52:45.393126 [Byte1]: 67
1129 19:52:45.397625
1130 19:52:45.397705 Set Vref, RX VrefLevel [Byte0]: 68
1131 19:52:45.401017 [Byte1]: 68
1132 19:52:45.404907
1133 19:52:45.405033 Set Vref, RX VrefLevel [Byte0]: 69
1134 19:52:45.408180 [Byte1]: 69
1135 19:52:45.412553
1136 19:52:45.412634 Set Vref, RX VrefLevel [Byte0]: 70
1137 19:52:45.416369 [Byte1]: 70
1138 19:52:45.420427
1139 19:52:45.420544 Set Vref, RX VrefLevel [Byte0]: 71
1140 19:52:45.423834 [Byte1]: 71
1141 19:52:45.427909
1142 19:52:45.428007 Set Vref, RX VrefLevel [Byte0]: 72
1143 19:52:45.431347 [Byte1]: 72
1144 19:52:45.435824
1145 19:52:45.435939 Set Vref, RX VrefLevel [Byte0]: 73
1146 19:52:45.438853 [Byte1]: 73
1147 19:52:45.443296
1148 19:52:45.443410 Set Vref, RX VrefLevel [Byte0]: 74
1149 19:52:45.446911 [Byte1]: 74
1150 19:52:45.450853
1151 19:52:45.450987 Set Vref, RX VrefLevel [Byte0]: 75
1152 19:52:45.454232 [Byte1]: 75
1153 19:52:45.458851
1154 19:52:45.458991 Set Vref, RX VrefLevel [Byte0]: 76
1155 19:52:45.461829 [Byte1]: 76
1156 19:52:45.466104
1157 19:52:45.466200 Set Vref, RX VrefLevel [Byte0]: 77
1158 19:52:45.469683 [Byte1]: 77
1159 19:52:45.473820
1160 19:52:45.473902 Set Vref, RX VrefLevel [Byte0]: 78
1161 19:52:45.477490 [Byte1]: 78
1162 19:52:45.481308
1163 19:52:45.481390 Set Vref, RX VrefLevel [Byte0]: 79
1164 19:52:45.485098 [Byte1]: 79
1165 19:52:45.489268
1166 19:52:45.489351 Final RX Vref Byte 0 = 62 to rank0
1167 19:52:45.492805 Final RX Vref Byte 1 = 62 to rank0
1168 19:52:45.495689 Final RX Vref Byte 0 = 62 to rank1
1169 19:52:45.499404 Final RX Vref Byte 1 = 62 to rank1==
1170 19:52:45.502356 Dram Type= 6, Freq= 0, CH_0, rank 0
1171 19:52:45.509103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1172 19:52:45.509187 ==
1173 19:52:45.509253 DQS Delay:
1174 19:52:45.509314 DQS0 = 0, DQS1 = 0
1175 19:52:45.512471 DQM Delay:
1176 19:52:45.512553 DQM0 = 81, DQM1 = 69
1177 19:52:45.515828 DQ Delay:
1178 19:52:45.518887 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1179 19:52:45.518970 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1180 19:52:45.522534 DQ8 =64, DQ9 =56, DQ10 =68, DQ11 =60
1181 19:52:45.529243 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =76
1182 19:52:45.529328
1183 19:52:45.529393
1184 19:52:45.535870 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1185 19:52:45.538964 CH0 RK0: MR19=606, MR18=2525
1186 19:52:45.545588 CH0_RK0: MR19=0x606, MR18=0x2525, DQSOSC=400, MR23=63, INC=92, DEC=61
1187 19:52:45.545672
1188 19:52:45.549380 ----->DramcWriteLeveling(PI) begin...
1189 19:52:45.549465 ==
1190 19:52:45.552533 Dram Type= 6, Freq= 0, CH_0, rank 1
1191 19:52:45.555759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1192 19:52:45.555843 ==
1193 19:52:45.559194 Write leveling (Byte 0): 29 => 29
1194 19:52:45.562661 Write leveling (Byte 1): 29 => 29
1195 19:52:45.566249 DramcWriteLeveling(PI) end<-----
1196 19:52:45.566333
1197 19:52:45.566398 ==
1198 19:52:45.569306 Dram Type= 6, Freq= 0, CH_0, rank 1
1199 19:52:45.572548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1200 19:52:45.572633 ==
1201 19:52:45.576156 [Gating] SW mode calibration
1202 19:52:45.582687 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1203 19:52:45.589656 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1204 19:52:45.592516 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1205 19:52:45.596247 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1206 19:52:45.602304 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1207 19:52:45.605965 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 19:52:45.609619 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 19:52:45.615732 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 19:52:45.619299 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 19:52:45.622545 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 19:52:45.629389 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 19:52:45.632438 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 19:52:45.636042 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 19:52:45.642256 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 19:52:45.645751 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 19:52:45.649405 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 19:52:45.696252 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 19:52:45.696386 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 19:52:45.696683 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 19:52:45.696764 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1222 19:52:45.696824 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1223 19:52:45.696892 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 19:52:45.696951 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 19:52:45.697499 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 19:52:45.697797 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 19:52:45.697869 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 19:52:45.697931 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 19:52:45.737290 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 19:52:45.738047 0 9 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
1231 19:52:45.738313 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1232 19:52:45.738383 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 19:52:45.738444 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 19:52:45.738514 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 19:52:45.739268 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 19:52:45.739532 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 19:52:45.742208 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1238 19:52:45.742288 0 10 8 | B1->B0 | 2b2b 2525 | 0 0 | (1 0) (0 0)
1239 19:52:45.745954 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1240 19:52:45.752080 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 19:52:45.755541 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 19:52:45.758457 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 19:52:45.765218 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 19:52:45.768639 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 19:52:45.771902 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 19:52:45.778736 0 11 8 | B1->B0 | 3535 4040 | 0 0 | (0 0) (0 0)
1247 19:52:45.782351 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1248 19:52:45.785329 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 19:52:45.788682 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 19:52:45.795614 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 19:52:45.798900 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 19:52:45.802020 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 19:52:45.809549 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1254 19:52:45.813651 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1255 19:52:45.817375 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 19:52:45.820538 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 19:52:45.824057 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 19:52:45.830852 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 19:52:45.834535 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 19:52:45.838051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 19:52:45.841050 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 19:52:45.848038 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 19:52:45.851259 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 19:52:45.854757 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 19:52:45.861167 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 19:52:45.864736 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 19:52:45.868043 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 19:52:45.874770 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 19:52:45.878175 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1270 19:52:45.881546 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1271 19:52:45.884655 Total UI for P1: 0, mck2ui 16
1272 19:52:45.887768 best dqsien dly found for B0: ( 0, 14, 4)
1273 19:52:45.894584 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 19:52:45.894691 Total UI for P1: 0, mck2ui 16
1275 19:52:45.901722 best dqsien dly found for B1: ( 0, 14, 8)
1276 19:52:45.904621 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1277 19:52:45.908112 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1278 19:52:45.908207
1279 19:52:45.911440 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1280 19:52:45.914925 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1281 19:52:45.917980 [Gating] SW calibration Done
1282 19:52:45.918081 ==
1283 19:52:45.921384 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 19:52:45.924815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 19:52:45.924896 ==
1286 19:52:45.927852 RX Vref Scan: 0
1287 19:52:45.927932
1288 19:52:45.927995 RX Vref 0 -> 0, step: 1
1289 19:52:45.928055
1290 19:52:45.931436 RX Delay -130 -> 252, step: 16
1291 19:52:45.935141 iDelay=222, Bit 0, Center 69 (-50 ~ 189) 240
1292 19:52:45.941825 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1293 19:52:45.945200 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1294 19:52:45.948082 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1295 19:52:45.951735 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1296 19:52:45.954769 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1297 19:52:45.958351 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1298 19:52:45.964574 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1299 19:52:45.967812 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1300 19:52:45.971366 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1301 19:52:45.974866 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1302 19:52:45.978040 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1303 19:52:45.984517 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1304 19:52:45.988094 iDelay=222, Bit 13, Center 69 (-50 ~ 189) 240
1305 19:52:45.991129 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1306 19:52:45.994794 iDelay=222, Bit 15, Center 69 (-50 ~ 189) 240
1307 19:52:45.994875 ==
1308 19:52:45.997673 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 19:52:46.004709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 19:52:46.004791 ==
1311 19:52:46.004873 DQS Delay:
1312 19:52:46.007892 DQS0 = 0, DQS1 = 0
1313 19:52:46.007973 DQM Delay:
1314 19:52:46.008036 DQM0 = 75, DQM1 = 66
1315 19:52:46.011037 DQ Delay:
1316 19:52:46.014732 DQ0 =69, DQ1 =77, DQ2 =69, DQ3 =69
1317 19:52:46.017833 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1318 19:52:46.021693 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1319 19:52:46.024505 DQ12 =69, DQ13 =69, DQ14 =77, DQ15 =69
1320 19:52:46.024585
1321 19:52:46.024649
1322 19:52:46.024709 ==
1323 19:52:46.027951 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 19:52:46.031216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 19:52:46.031297 ==
1326 19:52:46.031361
1327 19:52:46.031463
1328 19:52:46.035066 TX Vref Scan disable
1329 19:52:46.035147 == TX Byte 0 ==
1330 19:52:46.041788 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1331 19:52:46.044766 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1332 19:52:46.044847 == TX Byte 1 ==
1333 19:52:46.052043 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1334 19:52:46.055082 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1335 19:52:46.055162 ==
1336 19:52:46.058752 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 19:52:46.061845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 19:52:46.061926 ==
1339 19:52:46.074887 TX Vref=22, minBit 1, minWin=26, winSum=436
1340 19:52:46.078570 TX Vref=24, minBit 1, minWin=27, winSum=441
1341 19:52:46.081559 TX Vref=26, minBit 2, minWin=26, winSum=439
1342 19:52:46.085159 TX Vref=28, minBit 6, minWin=27, winSum=444
1343 19:52:46.088196 TX Vref=30, minBit 5, minWin=27, winSum=444
1344 19:52:46.095268 TX Vref=32, minBit 9, minWin=27, winSum=446
1345 19:52:46.098296 [TxChooseVref] Worse bit 9, Min win 27, Win sum 446, Final Vref 32
1346 19:52:46.098378
1347 19:52:46.101754 Final TX Range 1 Vref 32
1348 19:52:46.101834
1349 19:52:46.101898 ==
1350 19:52:46.104689 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 19:52:46.108728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 19:52:46.108810 ==
1353 19:52:46.111510
1354 19:52:46.111590
1355 19:52:46.111653 TX Vref Scan disable
1356 19:52:46.115049 == TX Byte 0 ==
1357 19:52:46.118294 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1358 19:52:46.121441 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1359 19:52:46.124928 == TX Byte 1 ==
1360 19:52:46.128423 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1361 19:52:46.131766 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1362 19:52:46.134764
1363 19:52:46.134844 [DATLAT]
1364 19:52:46.134908 Freq=800, CH0 RK1
1365 19:52:46.134967
1366 19:52:46.138065 DATLAT Default: 0xa
1367 19:52:46.138145 0, 0xFFFF, sum = 0
1368 19:52:46.141660 1, 0xFFFF, sum = 0
1369 19:52:46.141742 2, 0xFFFF, sum = 0
1370 19:52:46.145129 3, 0xFFFF, sum = 0
1371 19:52:46.145211 4, 0xFFFF, sum = 0
1372 19:52:46.148296 5, 0xFFFF, sum = 0
1373 19:52:46.151608 6, 0xFFFF, sum = 0
1374 19:52:46.151689 7, 0xFFFF, sum = 0
1375 19:52:46.155042 8, 0xFFFF, sum = 0
1376 19:52:46.155124 9, 0x0, sum = 1
1377 19:52:46.155189 10, 0x0, sum = 2
1378 19:52:46.158205 11, 0x0, sum = 3
1379 19:52:46.158330 12, 0x0, sum = 4
1380 19:52:46.161810 best_step = 10
1381 19:52:46.161890
1382 19:52:46.161952 ==
1383 19:52:46.164810 Dram Type= 6, Freq= 0, CH_0, rank 1
1384 19:52:46.168544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1385 19:52:46.168625 ==
1386 19:52:46.172051 RX Vref Scan: 0
1387 19:52:46.172130
1388 19:52:46.172192 RX Vref 0 -> 0, step: 1
1389 19:52:46.172250
1390 19:52:46.174887 RX Delay -111 -> 252, step: 8
1391 19:52:46.181607 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1392 19:52:46.185250 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1393 19:52:46.188310 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1394 19:52:46.191729 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1395 19:52:46.194951 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1396 19:52:46.201880 iDelay=209, Bit 5, Center 68 (-47 ~ 184) 232
1397 19:52:46.204881 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1398 19:52:46.208413 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1399 19:52:46.211790 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1400 19:52:46.214911 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1401 19:52:46.221842 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1402 19:52:46.224748 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1403 19:52:46.228564 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1404 19:52:46.232151 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1405 19:52:46.234956 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1406 19:52:46.241659 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1407 19:52:46.241738 ==
1408 19:52:46.244891 Dram Type= 6, Freq= 0, CH_0, rank 1
1409 19:52:46.248214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 19:52:46.248296 ==
1411 19:52:46.248361 DQS Delay:
1412 19:52:46.251944 DQS0 = 0, DQS1 = 0
1413 19:52:46.252019 DQM Delay:
1414 19:52:46.254971 DQM0 = 79, DQM1 = 69
1415 19:52:46.255040 DQ Delay:
1416 19:52:46.258559 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1417 19:52:46.261993 DQ4 =76, DQ5 =68, DQ6 =92, DQ7 =88
1418 19:52:46.264782 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =60
1419 19:52:46.268264 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =76
1420 19:52:46.268359
1421 19:52:46.268441
1422 19:52:46.275156 [DQSOSCAuto] RK1, (LSB)MR18= 0x4721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1423 19:52:46.278191 CH0 RK1: MR19=606, MR18=4721
1424 19:52:46.285085 CH0_RK1: MR19=0x606, MR18=0x4721, DQSOSC=392, MR23=63, INC=96, DEC=64
1425 19:52:46.288520 [RxdqsGatingPostProcess] freq 800
1426 19:52:46.295093 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1427 19:52:46.298338 Pre-setting of DQS Precalculation
1428 19:52:46.301701 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1429 19:52:46.301773 ==
1430 19:52:46.305139 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 19:52:46.308109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 19:52:46.308181 ==
1433 19:52:46.315256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1434 19:52:46.321668 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1435 19:52:46.329905 [CA 0] Center 36 (6~67) winsize 62
1436 19:52:46.333617 [CA 1] Center 37 (7~67) winsize 61
1437 19:52:46.336515 [CA 2] Center 34 (5~64) winsize 60
1438 19:52:46.340140 [CA 3] Center 34 (4~64) winsize 61
1439 19:52:46.343121 [CA 4] Center 34 (4~64) winsize 61
1440 19:52:46.346509 [CA 5] Center 34 (4~64) winsize 61
1441 19:52:46.346579
1442 19:52:46.349820 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1443 19:52:46.349895
1444 19:52:46.353305 [CATrainingPosCal] consider 1 rank data
1445 19:52:46.356479 u2DelayCellTimex100 = 270/100 ps
1446 19:52:46.359924 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1447 19:52:46.363228 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1448 19:52:46.369906 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1449 19:52:46.373136 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1450 19:52:46.376737 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1451 19:52:46.379967 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1452 19:52:46.380036
1453 19:52:46.383312 CA PerBit enable=1, Macro0, CA PI delay=34
1454 19:52:46.383411
1455 19:52:46.386820 [CBTSetCACLKResult] CA Dly = 34
1456 19:52:46.386894 CS Dly: 5 (0~36)
1457 19:52:46.386958 ==
1458 19:52:46.390288 Dram Type= 6, Freq= 0, CH_1, rank 1
1459 19:52:46.397045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1460 19:52:46.397123 ==
1461 19:52:46.399921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1462 19:52:46.406910 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1463 19:52:46.415991 [CA 0] Center 37 (7~67) winsize 61
1464 19:52:46.419667 [CA 1] Center 36 (6~67) winsize 62
1465 19:52:46.422850 [CA 2] Center 35 (5~65) winsize 61
1466 19:52:46.426415 [CA 3] Center 33 (3~64) winsize 62
1467 19:52:46.429976 [CA 4] Center 34 (4~65) winsize 62
1468 19:52:46.432903 [CA 5] Center 33 (3~64) winsize 62
1469 19:52:46.432978
1470 19:52:46.436666 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1471 19:52:46.436737
1472 19:52:46.439467 [CATrainingPosCal] consider 2 rank data
1473 19:52:46.443222 u2DelayCellTimex100 = 270/100 ps
1474 19:52:46.446104 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1475 19:52:46.449593 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1476 19:52:46.456247 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1477 19:52:46.459505 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1478 19:52:46.462543 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1479 19:52:46.466360 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1480 19:52:46.466437
1481 19:52:46.469893 CA PerBit enable=1, Macro0, CA PI delay=34
1482 19:52:46.469967
1483 19:52:46.473790 [CBTSetCACLKResult] CA Dly = 34
1484 19:52:46.473869 CS Dly: 6 (0~38)
1485 19:52:46.473932
1486 19:52:46.477519 ----->DramcWriteLeveling(PI) begin...
1487 19:52:46.477596 ==
1488 19:52:46.480906 Dram Type= 6, Freq= 0, CH_1, rank 0
1489 19:52:46.485065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1490 19:52:46.485182 ==
1491 19:52:46.488506 Write leveling (Byte 0): 29 => 29
1492 19:52:46.492503 Write leveling (Byte 1): 29 => 29
1493 19:52:46.495990 DramcWriteLeveling(PI) end<-----
1494 19:52:46.496067
1495 19:52:46.496132 ==
1496 19:52:46.499647 Dram Type= 6, Freq= 0, CH_1, rank 0
1497 19:52:46.504019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1498 19:52:46.504098 ==
1499 19:52:46.504164 [Gating] SW mode calibration
1500 19:52:46.513457 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1501 19:52:46.517183 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1502 19:52:46.520786 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1503 19:52:46.527107 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1504 19:52:46.530630 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1505 19:52:46.533510 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 19:52:46.540734 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 19:52:46.543619 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 19:52:46.547334 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 19:52:46.554045 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 19:52:46.556977 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 19:52:46.560494 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 19:52:46.566988 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 19:52:46.570507 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 19:52:46.573747 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 19:52:46.580307 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 19:52:46.583753 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 19:52:46.587215 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 19:52:46.593668 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 19:52:46.597083 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1520 19:52:46.600649 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 19:52:46.603684 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 19:52:46.610532 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 19:52:46.613665 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 19:52:46.617043 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 19:52:46.623997 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 19:52:46.626994 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 19:52:46.630534 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 19:52:46.636956 0 9 8 | B1->B0 | 2d2d 2828 | 1 1 | (1 1) (1 1)
1529 19:52:46.640394 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 19:52:46.643554 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 19:52:46.650546 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 19:52:46.654137 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 19:52:46.657405 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 19:52:46.663687 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 19:52:46.667151 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1536 19:52:46.670411 0 10 8 | B1->B0 | 2828 2c2c | 0 0 | (1 0) (1 1)
1537 19:52:46.677195 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 19:52:46.680207 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 19:52:46.683695 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 19:52:46.690215 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 19:52:46.693731 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 19:52:46.697200 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 19:52:46.703533 0 11 4 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
1544 19:52:46.706668 0 11 8 | B1->B0 | 3939 3737 | 0 1 | (0 0) (0 0)
1545 19:52:46.710067 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 19:52:46.713668 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 19:52:46.720172 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 19:52:46.723784 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 19:52:46.727108 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 19:52:46.733729 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 19:52:46.737500 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 19:52:46.740353 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1553 19:52:46.746842 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 19:52:46.750587 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 19:52:46.753952 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 19:52:46.760106 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 19:52:46.763513 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 19:52:46.767197 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 19:52:46.773859 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 19:52:46.776831 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 19:52:46.780204 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 19:52:46.787048 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 19:52:46.790135 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 19:52:46.793863 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 19:52:46.800279 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 19:52:46.803535 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 19:52:46.807535 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 19:52:46.810389 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1569 19:52:46.817456 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 19:52:46.820380 Total UI for P1: 0, mck2ui 16
1571 19:52:46.823987 best dqsien dly found for B0: ( 0, 14, 8)
1572 19:52:46.824065 Total UI for P1: 0, mck2ui 16
1573 19:52:46.830475 best dqsien dly found for B1: ( 0, 14, 8)
1574 19:52:46.833515 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1575 19:52:46.837075 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1576 19:52:46.837151
1577 19:52:46.840666 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1578 19:52:46.843718 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1579 19:52:46.846914 [Gating] SW calibration Done
1580 19:52:46.846984 ==
1581 19:52:46.850262 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 19:52:46.853633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 19:52:46.853706 ==
1584 19:52:46.857012 RX Vref Scan: 0
1585 19:52:46.857128
1586 19:52:46.857219 RX Vref 0 -> 0, step: 1
1587 19:52:46.857307
1588 19:52:46.860700 RX Delay -130 -> 252, step: 16
1589 19:52:46.863754 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1590 19:52:46.870274 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1591 19:52:46.874176 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1592 19:52:46.877250 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1593 19:52:46.880785 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1594 19:52:46.883754 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1595 19:52:46.890530 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1596 19:52:46.893819 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1597 19:52:46.896939 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1598 19:52:46.900662 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1599 19:52:46.903659 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1600 19:52:46.910788 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1601 19:52:46.913696 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1602 19:52:46.917438 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1603 19:52:46.920275 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1604 19:52:46.923837 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1605 19:52:46.927052 ==
1606 19:52:46.927125 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 19:52:46.933922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 19:52:46.933999 ==
1609 19:52:46.934063 DQS Delay:
1610 19:52:46.937476 DQS0 = 0, DQS1 = 0
1611 19:52:46.937552 DQM Delay:
1612 19:52:46.940506 DQM0 = 80, DQM1 = 70
1613 19:52:46.940584 DQ Delay:
1614 19:52:46.943639 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1615 19:52:46.947144 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1616 19:52:46.950431 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1617 19:52:46.953534 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1618 19:52:46.953614
1619 19:52:46.953675
1620 19:52:46.953732 ==
1621 19:52:46.957164 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 19:52:46.960900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 19:52:46.960977 ==
1624 19:52:46.961041
1625 19:52:46.961101
1626 19:52:46.963975 TX Vref Scan disable
1627 19:52:46.967227 == TX Byte 0 ==
1628 19:52:46.970581 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1629 19:52:46.973762 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1630 19:52:46.977162 == TX Byte 1 ==
1631 19:52:46.980283 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1632 19:52:46.983920 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1633 19:52:46.984000 ==
1634 19:52:46.987122 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 19:52:46.990755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 19:52:46.990860 ==
1637 19:52:47.004660 TX Vref=22, minBit 1, minWin=27, winSum=439
1638 19:52:47.007731 TX Vref=24, minBit 1, minWin=26, winSum=439
1639 19:52:47.011278 TX Vref=26, minBit 1, minWin=27, winSum=443
1640 19:52:47.014371 TX Vref=28, minBit 5, minWin=27, winSum=445
1641 19:52:47.017976 TX Vref=30, minBit 6, minWin=27, winSum=448
1642 19:52:47.021558 TX Vref=32, minBit 5, minWin=27, winSum=446
1643 19:52:47.027682 [TxChooseVref] Worse bit 6, Min win 27, Win sum 448, Final Vref 30
1644 19:52:47.027764
1645 19:52:47.031183 Final TX Range 1 Vref 30
1646 19:52:47.031264
1647 19:52:47.031327 ==
1648 19:52:47.034262 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 19:52:47.038237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 19:52:47.038318 ==
1651 19:52:47.038382
1652 19:52:47.041131
1653 19:52:47.041211 TX Vref Scan disable
1654 19:52:47.044880 == TX Byte 0 ==
1655 19:52:47.048059 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1656 19:52:47.051540 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1657 19:52:47.054969 == TX Byte 1 ==
1658 19:52:47.058470 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1659 19:52:47.061440 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1660 19:52:47.061520
1661 19:52:47.065092 [DATLAT]
1662 19:52:47.065173 Freq=800, CH1 RK0
1663 19:52:47.065285
1664 19:52:47.068805 DATLAT Default: 0xa
1665 19:52:47.068886 0, 0xFFFF, sum = 0
1666 19:52:47.071732 1, 0xFFFF, sum = 0
1667 19:52:47.071814 2, 0xFFFF, sum = 0
1668 19:52:47.075140 3, 0xFFFF, sum = 0
1669 19:52:47.075221 4, 0xFFFF, sum = 0
1670 19:52:47.078689 5, 0xFFFF, sum = 0
1671 19:52:47.078769 6, 0xFFFF, sum = 0
1672 19:52:47.081571 7, 0xFFFF, sum = 0
1673 19:52:47.081645 8, 0xFFFF, sum = 0
1674 19:52:47.085217 9, 0x0, sum = 1
1675 19:52:47.085294 10, 0x0, sum = 2
1676 19:52:47.088577 11, 0x0, sum = 3
1677 19:52:47.088656 12, 0x0, sum = 4
1678 19:52:47.091738 best_step = 10
1679 19:52:47.091813
1680 19:52:47.091875 ==
1681 19:52:47.094914 Dram Type= 6, Freq= 0, CH_1, rank 0
1682 19:52:47.098219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1683 19:52:47.098295 ==
1684 19:52:47.101710 RX Vref Scan: 1
1685 19:52:47.101782
1686 19:52:47.101841 Set Vref Range= 32 -> 127
1687 19:52:47.101902
1688 19:52:47.104833 RX Vref 32 -> 127, step: 1
1689 19:52:47.104899
1690 19:52:47.108660 RX Delay -111 -> 252, step: 8
1691 19:52:47.108734
1692 19:52:47.111894 Set Vref, RX VrefLevel [Byte0]: 32
1693 19:52:47.114944 [Byte1]: 32
1694 19:52:47.115016
1695 19:52:47.118399 Set Vref, RX VrefLevel [Byte0]: 33
1696 19:52:47.121950 [Byte1]: 33
1697 19:52:47.124865
1698 19:52:47.124940 Set Vref, RX VrefLevel [Byte0]: 34
1699 19:52:47.128470 [Byte1]: 34
1700 19:52:47.132466
1701 19:52:47.132542 Set Vref, RX VrefLevel [Byte0]: 35
1702 19:52:47.136099 [Byte1]: 35
1703 19:52:47.140300
1704 19:52:47.140372 Set Vref, RX VrefLevel [Byte0]: 36
1705 19:52:47.143358 [Byte1]: 36
1706 19:52:47.148269
1707 19:52:47.148349 Set Vref, RX VrefLevel [Byte0]: 37
1708 19:52:47.151266 [Byte1]: 37
1709 19:52:47.155479
1710 19:52:47.155573 Set Vref, RX VrefLevel [Byte0]: 38
1711 19:52:47.158791 [Byte1]: 38
1712 19:52:47.163283
1713 19:52:47.163406 Set Vref, RX VrefLevel [Byte0]: 39
1714 19:52:47.166769 [Byte1]: 39
1715 19:52:47.171137
1716 19:52:47.171221 Set Vref, RX VrefLevel [Byte0]: 40
1717 19:52:47.174575 [Byte1]: 40
1718 19:52:47.178928
1719 19:52:47.179040 Set Vref, RX VrefLevel [Byte0]: 41
1720 19:52:47.182060 [Byte1]: 41
1721 19:52:47.186419
1722 19:52:47.186501 Set Vref, RX VrefLevel [Byte0]: 42
1723 19:52:47.189312 [Byte1]: 42
1724 19:52:47.193926
1725 19:52:47.194002 Set Vref, RX VrefLevel [Byte0]: 43
1726 19:52:47.197024 [Byte1]: 43
1727 19:52:47.201560
1728 19:52:47.201638 Set Vref, RX VrefLevel [Byte0]: 44
1729 19:52:47.204860 [Byte1]: 44
1730 19:52:47.208908
1731 19:52:47.208983 Set Vref, RX VrefLevel [Byte0]: 45
1732 19:52:47.212226 [Byte1]: 45
1733 19:52:47.216737
1734 19:52:47.216815 Set Vref, RX VrefLevel [Byte0]: 46
1735 19:52:47.220117 [Byte1]: 46
1736 19:52:47.224397
1737 19:52:47.224477 Set Vref, RX VrefLevel [Byte0]: 47
1738 19:52:47.227584 [Byte1]: 47
1739 19:52:47.231916
1740 19:52:47.231996 Set Vref, RX VrefLevel [Byte0]: 48
1741 19:52:47.235685 [Byte1]: 48
1742 19:52:47.239848
1743 19:52:47.239928 Set Vref, RX VrefLevel [Byte0]: 49
1744 19:52:47.243018 [Byte1]: 49
1745 19:52:47.247273
1746 19:52:47.247353 Set Vref, RX VrefLevel [Byte0]: 50
1747 19:52:47.250862 [Byte1]: 50
1748 19:52:47.255038
1749 19:52:47.255119 Set Vref, RX VrefLevel [Byte0]: 51
1750 19:52:47.258113 [Byte1]: 51
1751 19:52:47.262855
1752 19:52:47.262935 Set Vref, RX VrefLevel [Byte0]: 52
1753 19:52:47.266365 [Byte1]: 52
1754 19:52:47.270241
1755 19:52:47.270350 Set Vref, RX VrefLevel [Byte0]: 53
1756 19:52:47.273355 [Byte1]: 53
1757 19:52:47.278270
1758 19:52:47.278343 Set Vref, RX VrefLevel [Byte0]: 54
1759 19:52:47.281154 [Byte1]: 54
1760 19:52:47.285875
1761 19:52:47.285972 Set Vref, RX VrefLevel [Byte0]: 55
1762 19:52:47.288755 [Byte1]: 55
1763 19:52:47.293017
1764 19:52:47.293120 Set Vref, RX VrefLevel [Byte0]: 56
1765 19:52:47.296332 [Byte1]: 56
1766 19:52:47.301030
1767 19:52:47.301132 Set Vref, RX VrefLevel [Byte0]: 57
1768 19:52:47.304262 [Byte1]: 57
1769 19:52:47.308287
1770 19:52:47.308389 Set Vref, RX VrefLevel [Byte0]: 58
1771 19:52:47.311936 [Byte1]: 58
1772 19:52:47.316296
1773 19:52:47.316367 Set Vref, RX VrefLevel [Byte0]: 59
1774 19:52:47.319235 [Byte1]: 59
1775 19:52:47.323960
1776 19:52:47.324036 Set Vref, RX VrefLevel [Byte0]: 60
1777 19:52:47.327324 [Byte1]: 60
1778 19:52:47.331714
1779 19:52:47.331823 Set Vref, RX VrefLevel [Byte0]: 61
1780 19:52:47.334655 [Byte1]: 61
1781 19:52:47.339393
1782 19:52:47.339497 Set Vref, RX VrefLevel [Byte0]: 62
1783 19:52:47.342430 [Byte1]: 62
1784 19:52:47.347106
1785 19:52:47.347205 Set Vref, RX VrefLevel [Byte0]: 63
1786 19:52:47.350466 [Byte1]: 63
1787 19:52:47.354687
1788 19:52:47.354762 Set Vref, RX VrefLevel [Byte0]: 64
1789 19:52:47.357529 [Byte1]: 64
1790 19:52:47.362511
1791 19:52:47.362609 Set Vref, RX VrefLevel [Byte0]: 65
1792 19:52:47.365324 [Byte1]: 65
1793 19:52:47.369510
1794 19:52:47.369610 Set Vref, RX VrefLevel [Byte0]: 66
1795 19:52:47.373238 [Byte1]: 66
1796 19:52:47.377332
1797 19:52:47.377403 Set Vref, RX VrefLevel [Byte0]: 67
1798 19:52:47.380837 [Byte1]: 67
1799 19:52:47.385105
1800 19:52:47.385194 Set Vref, RX VrefLevel [Byte0]: 68
1801 19:52:47.388447 [Byte1]: 68
1802 19:52:47.392613
1803 19:52:47.392716 Set Vref, RX VrefLevel [Byte0]: 69
1804 19:52:47.396046 [Byte1]: 69
1805 19:52:47.400703
1806 19:52:47.400787 Set Vref, RX VrefLevel [Byte0]: 70
1807 19:52:47.403693 [Byte1]: 70
1808 19:52:47.408090
1809 19:52:47.408188 Set Vref, RX VrefLevel [Byte0]: 71
1810 19:52:47.411083 [Byte1]: 71
1811 19:52:47.415583
1812 19:52:47.415656 Set Vref, RX VrefLevel [Byte0]: 72
1813 19:52:47.419056 [Byte1]: 72
1814 19:52:47.423100
1815 19:52:47.426687 Set Vref, RX VrefLevel [Byte0]: 73
1816 19:52:47.426788 [Byte1]: 73
1817 19:52:47.430711
1818 19:52:47.430808 Set Vref, RX VrefLevel [Byte0]: 74
1819 19:52:47.434507 [Byte1]: 74
1820 19:52:47.438740
1821 19:52:47.438845 Final RX Vref Byte 0 = 62 to rank0
1822 19:52:47.441828 Final RX Vref Byte 1 = 52 to rank0
1823 19:52:47.445082 Final RX Vref Byte 0 = 62 to rank1
1824 19:52:47.448577 Final RX Vref Byte 1 = 52 to rank1==
1825 19:52:47.451690 Dram Type= 6, Freq= 0, CH_1, rank 0
1826 19:52:47.455233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 19:52:47.458491 ==
1828 19:52:47.458587 DQS Delay:
1829 19:52:47.458677 DQS0 = 0, DQS1 = 0
1830 19:52:47.462105 DQM Delay:
1831 19:52:47.462200 DQM0 = 80, DQM1 = 71
1832 19:52:47.465601 DQ Delay:
1833 19:52:47.468567 DQ0 =88, DQ1 =72, DQ2 =68, DQ3 =76
1834 19:52:47.468641 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1835 19:52:47.472021 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1836 19:52:47.475262 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =80
1837 19:52:47.478741
1838 19:52:47.478838
1839 19:52:47.485435 [DQSOSCAuto] RK0, (LSB)MR18= 0x101a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1840 19:52:47.488671 CH1 RK0: MR19=606, MR18=101A
1841 19:52:47.495327 CH1_RK0: MR19=0x606, MR18=0x101A, DQSOSC=403, MR23=63, INC=90, DEC=60
1842 19:52:47.495443
1843 19:52:47.498609 ----->DramcWriteLeveling(PI) begin...
1844 19:52:47.498708 ==
1845 19:52:47.502045 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 19:52:47.505100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 19:52:47.505207 ==
1848 19:52:47.508716 Write leveling (Byte 0): 27 => 27
1849 19:52:47.511842 Write leveling (Byte 1): 28 => 28
1850 19:52:47.515372 DramcWriteLeveling(PI) end<-----
1851 19:52:47.515488
1852 19:52:47.515576 ==
1853 19:52:47.518549 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 19:52:47.522272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 19:52:47.522372 ==
1856 19:52:47.525512 [Gating] SW mode calibration
1857 19:52:47.532242 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1858 19:52:47.538852 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1859 19:52:47.541850 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1860 19:52:47.545363 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1861 19:52:47.552234 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 19:52:47.555567 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 19:52:47.558450 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 19:52:47.565378 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 19:52:47.568754 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 19:52:47.572103 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 19:52:47.578451 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 19:52:47.582042 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 19:52:47.585589 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 19:52:47.591694 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 19:52:47.595234 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 19:52:47.598911 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 19:52:47.602145 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 19:52:47.608515 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 19:52:47.611768 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 19:52:47.615216 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1877 19:52:47.621853 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 19:52:47.625469 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 19:52:47.628501 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 19:52:47.635196 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 19:52:47.638591 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 19:52:47.641868 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 19:52:47.649012 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 19:52:47.652109 0 9 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1885 19:52:47.655588 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1886 19:52:47.661806 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 19:52:47.665502 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 19:52:47.668778 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 19:52:47.671781 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 19:52:47.679043 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 19:52:47.682339 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1892 19:52:47.685243 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (1 1)
1893 19:52:47.692067 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1894 19:52:47.695771 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 19:52:47.698642 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 19:52:47.705236 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 19:52:47.708763 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 19:52:47.712104 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 19:52:47.718847 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1900 19:52:47.722405 0 11 4 | B1->B0 | 2d2c 3737 | 1 0 | (0 0) (0 0)
1901 19:52:47.725388 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1902 19:52:47.731811 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 19:52:47.735611 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 19:52:47.738400 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 19:52:47.745132 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 19:52:47.748417 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 19:52:47.751825 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 19:52:47.758995 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1909 19:52:47.761822 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 19:52:47.765474 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 19:52:47.768427 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 19:52:47.775705 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 19:52:47.778764 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 19:52:47.782177 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 19:52:47.788373 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 19:52:47.791803 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 19:52:47.795424 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 19:52:47.801685 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 19:52:47.805206 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 19:52:47.808841 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 19:52:47.815443 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 19:52:47.818562 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 19:52:47.822356 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 19:52:47.829021 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1925 19:52:47.829122 Total UI for P1: 0, mck2ui 16
1926 19:52:47.835373 best dqsien dly found for B0: ( 0, 14, 2)
1927 19:52:47.838401 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 19:52:47.841909 Total UI for P1: 0, mck2ui 16
1929 19:52:47.845290 best dqsien dly found for B1: ( 0, 14, 4)
1930 19:52:47.848674 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1931 19:52:47.851623 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1932 19:52:47.851719
1933 19:52:47.855239 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1934 19:52:47.858665 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1935 19:52:47.861935 [Gating] SW calibration Done
1936 19:52:47.862010 ==
1937 19:52:47.865616 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 19:52:47.869054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 19:52:47.869137 ==
1940 19:52:47.871995 RX Vref Scan: 0
1941 19:52:47.872093
1942 19:52:47.874989 RX Vref 0 -> 0, step: 1
1943 19:52:47.875084
1944 19:52:47.875204 RX Delay -130 -> 252, step: 16
1945 19:52:47.882052 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1946 19:52:47.885077 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1947 19:52:47.889097 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1948 19:52:47.891967 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1949 19:52:47.895290 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1950 19:52:47.901830 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1951 19:52:47.905294 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1952 19:52:47.908356 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1953 19:52:47.911906 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1954 19:52:47.915588 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1955 19:52:47.922028 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1956 19:52:47.925187 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1957 19:52:47.928697 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1958 19:52:47.931681 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1959 19:52:47.935020 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1960 19:52:47.942043 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1961 19:52:47.942148 ==
1962 19:52:47.944974 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 19:52:47.948573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 19:52:47.948669 ==
1965 19:52:47.948760 DQS Delay:
1966 19:52:47.952098 DQS0 = 0, DQS1 = 0
1967 19:52:47.952195 DQM Delay:
1968 19:52:47.955267 DQM0 = 77, DQM1 = 71
1969 19:52:47.955364 DQ Delay:
1970 19:52:47.958755 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =69
1971 19:52:47.961737 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1972 19:52:47.965448 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1973 19:52:47.968837 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1974 19:52:47.968910
1975 19:52:47.968975
1976 19:52:47.969034 ==
1977 19:52:47.972060 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 19:52:47.975246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 19:52:47.975345 ==
1980 19:52:47.975463
1981 19:52:47.978580
1982 19:52:47.978675 TX Vref Scan disable
1983 19:52:47.982078 == TX Byte 0 ==
1984 19:52:47.985563 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1985 19:52:47.988507 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1986 19:52:47.991982 == TX Byte 1 ==
1987 19:52:47.995168 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1988 19:52:47.998426 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1989 19:52:47.998537 ==
1990 19:52:48.001884 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 19:52:48.008618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 19:52:48.008694 ==
1993 19:52:48.020540 TX Vref=22, minBit 4, minWin=27, winSum=448
1994 19:52:48.023504 TX Vref=24, minBit 6, minWin=27, winSum=453
1995 19:52:48.026935 TX Vref=26, minBit 6, minWin=27, winSum=455
1996 19:52:48.030541 TX Vref=28, minBit 1, minWin=28, winSum=458
1997 19:52:48.033645 TX Vref=30, minBit 0, minWin=28, winSum=460
1998 19:52:48.036676 TX Vref=32, minBit 1, minWin=28, winSum=459
1999 19:52:48.043819 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
2000 19:52:48.043902
2001 19:52:48.046977 Final TX Range 1 Vref 30
2002 19:52:48.047079
2003 19:52:48.047170 ==
2004 19:52:48.050549 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 19:52:48.053420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 19:52:48.053522 ==
2007 19:52:48.053613
2008 19:52:48.056985
2009 19:52:48.057083 TX Vref Scan disable
2010 19:52:48.060134 == TX Byte 0 ==
2011 19:52:48.063950 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2012 19:52:48.067036 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2013 19:52:48.070021 == TX Byte 1 ==
2014 19:52:48.073680 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2015 19:52:48.077218 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2016 19:52:48.077309
2017 19:52:48.080085 [DATLAT]
2018 19:52:48.080187 Freq=800, CH1 RK1
2019 19:52:48.080287
2020 19:52:48.083608 DATLAT Default: 0xa
2021 19:52:48.083687 0, 0xFFFF, sum = 0
2022 19:52:48.086843 1, 0xFFFF, sum = 0
2023 19:52:48.086922 2, 0xFFFF, sum = 0
2024 19:52:48.090060 3, 0xFFFF, sum = 0
2025 19:52:48.090168 4, 0xFFFF, sum = 0
2026 19:52:48.093376 5, 0xFFFF, sum = 0
2027 19:52:48.096729 6, 0xFFFF, sum = 0
2028 19:52:48.096839 7, 0xFFFF, sum = 0
2029 19:52:48.100063 8, 0xFFFF, sum = 0
2030 19:52:48.100171 9, 0x0, sum = 1
2031 19:52:48.100268 10, 0x0, sum = 2
2032 19:52:48.103505 11, 0x0, sum = 3
2033 19:52:48.103596 12, 0x0, sum = 4
2034 19:52:48.106813 best_step = 10
2035 19:52:48.106918
2036 19:52:48.107016 ==
2037 19:52:48.109918 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 19:52:48.113395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 19:52:48.113476 ==
2040 19:52:48.116516 RX Vref Scan: 0
2041 19:52:48.116597
2042 19:52:48.116664 RX Vref 0 -> 0, step: 1
2043 19:52:48.116753
2044 19:52:48.119927 RX Delay -111 -> 252, step: 8
2045 19:52:48.127192 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2046 19:52:48.130261 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2047 19:52:48.133851 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2048 19:52:48.136840 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2049 19:52:48.140611 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
2050 19:52:48.147134 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2051 19:52:48.150109 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2052 19:52:48.153524 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2053 19:52:48.156989 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2054 19:52:48.160166 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2055 19:52:48.167467 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2056 19:52:48.170378 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2057 19:52:48.173566 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2058 19:52:48.177187 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2059 19:52:48.180112 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2060 19:52:48.186749 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2061 19:52:48.186834 ==
2062 19:52:48.190484 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 19:52:48.193695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 19:52:48.193780 ==
2065 19:52:48.193846 DQS Delay:
2066 19:52:48.197332 DQS0 = 0, DQS1 = 0
2067 19:52:48.197424 DQM Delay:
2068 19:52:48.200561 DQM0 = 77, DQM1 = 74
2069 19:52:48.200644 DQ Delay:
2070 19:52:48.203513 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2071 19:52:48.207278 DQ4 =72, DQ5 =88, DQ6 =88, DQ7 =76
2072 19:52:48.210386 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2073 19:52:48.213869 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2074 19:52:48.213973
2075 19:52:48.214066
2076 19:52:48.220302 [DQSOSCAuto] RK1, (LSB)MR18= 0x2038, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2077 19:52:48.223547 CH1 RK1: MR19=606, MR18=2038
2078 19:52:48.230149 CH1_RK1: MR19=0x606, MR18=0x2038, DQSOSC=395, MR23=63, INC=94, DEC=63
2079 19:52:48.233849 [RxdqsGatingPostProcess] freq 800
2080 19:52:48.240393 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2081 19:52:48.243562 Pre-setting of DQS Precalculation
2082 19:52:48.246817 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2083 19:52:48.253374 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2084 19:52:48.260474 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2085 19:52:48.260589
2086 19:52:48.260660
2087 19:52:48.263803 [Calibration Summary] 1600 Mbps
2088 19:52:48.266853 CH 0, Rank 0
2089 19:52:48.266956 SW Impedance : PASS
2090 19:52:48.270496 DUTY Scan : NO K
2091 19:52:48.273871 ZQ Calibration : PASS
2092 19:52:48.273947 Jitter Meter : NO K
2093 19:52:48.277003 CBT Training : PASS
2094 19:52:48.280630 Write leveling : PASS
2095 19:52:48.280713 RX DQS gating : PASS
2096 19:52:48.283690 RX DQ/DQS(RDDQC) : PASS
2097 19:52:48.283772 TX DQ/DQS : PASS
2098 19:52:48.286874 RX DATLAT : PASS
2099 19:52:48.290488 RX DQ/DQS(Engine): PASS
2100 19:52:48.290571 TX OE : NO K
2101 19:52:48.293875 All Pass.
2102 19:52:48.293958
2103 19:52:48.294022 CH 0, Rank 1
2104 19:52:48.296836 SW Impedance : PASS
2105 19:52:48.296920 DUTY Scan : NO K
2106 19:52:48.300250 ZQ Calibration : PASS
2107 19:52:48.303693 Jitter Meter : NO K
2108 19:52:48.303782 CBT Training : PASS
2109 19:52:48.307242 Write leveling : PASS
2110 19:52:48.310196 RX DQS gating : PASS
2111 19:52:48.310281 RX DQ/DQS(RDDQC) : PASS
2112 19:52:48.313772 TX DQ/DQS : PASS
2113 19:52:48.317022 RX DATLAT : PASS
2114 19:52:48.317106 RX DQ/DQS(Engine): PASS
2115 19:52:48.320207 TX OE : NO K
2116 19:52:48.320290 All Pass.
2117 19:52:48.320356
2118 19:52:48.324121 CH 1, Rank 0
2119 19:52:48.324206 SW Impedance : PASS
2120 19:52:48.327181 DUTY Scan : NO K
2121 19:52:48.327263 ZQ Calibration : PASS
2122 19:52:48.330703 Jitter Meter : NO K
2123 19:52:48.333670 CBT Training : PASS
2124 19:52:48.333752 Write leveling : PASS
2125 19:52:48.336825 RX DQS gating : PASS
2126 19:52:48.340608 RX DQ/DQS(RDDQC) : PASS
2127 19:52:48.340691 TX DQ/DQS : PASS
2128 19:52:48.343634 RX DATLAT : PASS
2129 19:52:48.347116 RX DQ/DQS(Engine): PASS
2130 19:52:48.347198 TX OE : NO K
2131 19:52:48.350147 All Pass.
2132 19:52:48.350229
2133 19:52:48.350295 CH 1, Rank 1
2134 19:52:48.353758 SW Impedance : PASS
2135 19:52:48.353840 DUTY Scan : NO K
2136 19:52:48.357422 ZQ Calibration : PASS
2137 19:52:48.360187 Jitter Meter : NO K
2138 19:52:48.360269 CBT Training : PASS
2139 19:52:48.363557 Write leveling : PASS
2140 19:52:48.367078 RX DQS gating : PASS
2141 19:52:48.367159 RX DQ/DQS(RDDQC) : PASS
2142 19:52:48.370563 TX DQ/DQS : PASS
2143 19:52:48.370646 RX DATLAT : PASS
2144 19:52:48.373907 RX DQ/DQS(Engine): PASS
2145 19:52:48.376772 TX OE : NO K
2146 19:52:48.376854 All Pass.
2147 19:52:48.376919
2148 19:52:48.380525 DramC Write-DBI off
2149 19:52:48.380605 PER_BANK_REFRESH: Hybrid Mode
2150 19:52:48.384163 TX_TRACKING: ON
2151 19:52:48.387082 [GetDramInforAfterCalByMRR] Vendor 6.
2152 19:52:48.390107 [GetDramInforAfterCalByMRR] Revision 606.
2153 19:52:48.393703 [GetDramInforAfterCalByMRR] Revision 2 0.
2154 19:52:48.393785 MR0 0x3b3b
2155 19:52:48.397057 MR8 0x5151
2156 19:52:48.400713 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2157 19:52:48.400794
2158 19:52:48.400858 MR0 0x3b3b
2159 19:52:48.403688 MR8 0x5151
2160 19:52:48.406924 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2161 19:52:48.407013
2162 19:52:48.413732 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2163 19:52:48.416756 [FAST_K] Save calibration result to emmc
2164 19:52:48.423827 [FAST_K] Save calibration result to emmc
2165 19:52:48.423921 dram_init: config_dvfs: 1
2166 19:52:48.426726 dramc_set_vcore_voltage set vcore to 662500
2167 19:52:48.430052 Read voltage for 1200, 2
2168 19:52:48.430157 Vio18 = 0
2169 19:52:48.433621 Vcore = 662500
2170 19:52:48.433728 Vdram = 0
2171 19:52:48.433820 Vddq = 0
2172 19:52:48.436776 Vmddr = 0
2173 19:52:48.440424 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2174 19:52:48.446867 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2175 19:52:48.446949 MEM_TYPE=3, freq_sel=15
2176 19:52:48.449845 sv_algorithm_assistance_LP4_1600
2177 19:52:48.456685 ============ PULL DRAM RESETB DOWN ============
2178 19:52:48.460138 ========== PULL DRAM RESETB DOWN end =========
2179 19:52:48.463305 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2180 19:52:48.466757 ===================================
2181 19:52:48.469871 LPDDR4 DRAM CONFIGURATION
2182 19:52:48.473573 ===================================
2183 19:52:48.476875 EX_ROW_EN[0] = 0x0
2184 19:52:48.476956 EX_ROW_EN[1] = 0x0
2185 19:52:48.479952 LP4Y_EN = 0x0
2186 19:52:48.480034 WORK_FSP = 0x0
2187 19:52:48.483571 WL = 0x4
2188 19:52:48.483655 RL = 0x4
2189 19:52:48.486505 BL = 0x2
2190 19:52:48.486585 RPST = 0x0
2191 19:52:48.490158 RD_PRE = 0x0
2192 19:52:48.490238 WR_PRE = 0x1
2193 19:52:48.493590 WR_PST = 0x0
2194 19:52:48.493687 DBI_WR = 0x0
2195 19:52:48.496771 DBI_RD = 0x0
2196 19:52:48.496905 OTF = 0x1
2197 19:52:48.500051 ===================================
2198 19:52:48.503720 ===================================
2199 19:52:48.506712 ANA top config
2200 19:52:48.509783 ===================================
2201 19:52:48.509864 DLL_ASYNC_EN = 0
2202 19:52:48.513270 ALL_SLAVE_EN = 0
2203 19:52:48.516733 NEW_RANK_MODE = 1
2204 19:52:48.519940 DLL_IDLE_MODE = 1
2205 19:52:48.523434 LP45_APHY_COMB_EN = 1
2206 19:52:48.523517 TX_ODT_DIS = 1
2207 19:52:48.526778 NEW_8X_MODE = 1
2208 19:52:48.529921 ===================================
2209 19:52:48.533074 ===================================
2210 19:52:48.536280 data_rate = 2400
2211 19:52:48.539702 CKR = 1
2212 19:52:48.543338 DQ_P2S_RATIO = 8
2213 19:52:48.546382 ===================================
2214 19:52:48.546472 CA_P2S_RATIO = 8
2215 19:52:48.549833 DQ_CA_OPEN = 0
2216 19:52:48.553331 DQ_SEMI_OPEN = 0
2217 19:52:48.556996 CA_SEMI_OPEN = 0
2218 19:52:48.560093 CA_FULL_RATE = 0
2219 19:52:48.563675 DQ_CKDIV4_EN = 0
2220 19:52:48.563748 CA_CKDIV4_EN = 0
2221 19:52:48.566579 CA_PREDIV_EN = 0
2222 19:52:48.569702 PH8_DLY = 17
2223 19:52:48.573182 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2224 19:52:48.576486 DQ_AAMCK_DIV = 4
2225 19:52:48.579469 CA_AAMCK_DIV = 4
2226 19:52:48.579543 CA_ADMCK_DIV = 4
2227 19:52:48.583072 DQ_TRACK_CA_EN = 0
2228 19:52:48.586272 CA_PICK = 1200
2229 19:52:48.589697 CA_MCKIO = 1200
2230 19:52:48.593405 MCKIO_SEMI = 0
2231 19:52:48.596508 PLL_FREQ = 2366
2232 19:52:48.599706 DQ_UI_PI_RATIO = 32
2233 19:52:48.599785 CA_UI_PI_RATIO = 0
2234 19:52:48.602855 ===================================
2235 19:52:48.606193 ===================================
2236 19:52:48.610019 memory_type:LPDDR4
2237 19:52:48.613010 GP_NUM : 10
2238 19:52:48.613111 SRAM_EN : 1
2239 19:52:48.616290 MD32_EN : 0
2240 19:52:48.619941 ===================================
2241 19:52:48.622818 [ANA_INIT] >>>>>>>>>>>>>>
2242 19:52:48.625983 <<<<<< [CONFIGURE PHASE]: ANA_TX
2243 19:52:48.629838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2244 19:52:48.633220 ===================================
2245 19:52:48.633296 data_rate = 2400,PCW = 0X5b00
2246 19:52:48.636155 ===================================
2247 19:52:48.639790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2248 19:52:48.646116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2249 19:52:48.653005 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 19:52:48.656039 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2251 19:52:48.659459 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2252 19:52:48.663041 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2253 19:52:48.665990 [ANA_INIT] flow start
2254 19:52:48.669877 [ANA_INIT] PLL >>>>>>>>
2255 19:52:48.669958 [ANA_INIT] PLL <<<<<<<<
2256 19:52:48.672705 [ANA_INIT] MIDPI >>>>>>>>
2257 19:52:48.676220 [ANA_INIT] MIDPI <<<<<<<<
2258 19:52:48.676295 [ANA_INIT] DLL >>>>>>>>
2259 19:52:48.679322 [ANA_INIT] DLL <<<<<<<<
2260 19:52:48.682850 [ANA_INIT] flow end
2261 19:52:48.686476 ============ LP4 DIFF to SE enter ============
2262 19:52:48.689457 ============ LP4 DIFF to SE exit ============
2263 19:52:48.693170 [ANA_INIT] <<<<<<<<<<<<<
2264 19:52:48.696064 [Flow] Enable top DCM control >>>>>
2265 19:52:48.699348 [Flow] Enable top DCM control <<<<<
2266 19:52:48.703113 Enable DLL master slave shuffle
2267 19:52:48.706242 ==============================================================
2268 19:52:48.709522 Gating Mode config
2269 19:52:48.712741 ==============================================================
2270 19:52:48.716622 Config description:
2271 19:52:48.726389 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2272 19:52:48.733139 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2273 19:52:48.736080 SELPH_MODE 0: By rank 1: By Phase
2274 19:52:48.742938 ==============================================================
2275 19:52:48.746350 GAT_TRACK_EN = 1
2276 19:52:48.749340 RX_GATING_MODE = 2
2277 19:52:48.752924 RX_GATING_TRACK_MODE = 2
2278 19:52:48.756282 SELPH_MODE = 1
2279 19:52:48.759768 PICG_EARLY_EN = 1
2280 19:52:48.759845 VALID_LAT_VALUE = 1
2281 19:52:48.766128 ==============================================================
2282 19:52:48.771416 Enter into Gating configuration >>>>
2283 19:52:48.772697 Exit from Gating configuration <<<<
2284 19:52:48.776259 Enter into DVFS_PRE_config >>>>>
2285 19:52:48.786574 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2286 19:52:48.789668 Exit from DVFS_PRE_config <<<<<
2287 19:52:48.793155 Enter into PICG configuration >>>>
2288 19:52:48.796394 Exit from PICG configuration <<<<
2289 19:52:48.799975 [RX_INPUT] configuration >>>>>
2290 19:52:48.802827 [RX_INPUT] configuration <<<<<
2291 19:52:48.806456 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2292 19:52:48.812729 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2293 19:52:48.819333 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2294 19:52:48.826486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2295 19:52:48.832873 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 19:52:48.836036 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 19:52:48.842706 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2298 19:52:48.845987 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2299 19:52:48.849321 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2300 19:52:48.852827 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2301 19:52:48.859541 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2302 19:52:48.862564 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2303 19:52:48.865815 ===================================
2304 19:52:48.869537 LPDDR4 DRAM CONFIGURATION
2305 19:52:48.872825 ===================================
2306 19:52:48.872909 EX_ROW_EN[0] = 0x0
2307 19:52:48.875905 EX_ROW_EN[1] = 0x0
2308 19:52:48.876010 LP4Y_EN = 0x0
2309 19:52:48.879360 WORK_FSP = 0x0
2310 19:52:48.879454 WL = 0x4
2311 19:52:48.883110 RL = 0x4
2312 19:52:48.883191 BL = 0x2
2313 19:52:48.885953 RPST = 0x0
2314 19:52:48.886029 RD_PRE = 0x0
2315 19:52:48.889050 WR_PRE = 0x1
2316 19:52:48.889126 WR_PST = 0x0
2317 19:52:48.892859 DBI_WR = 0x0
2318 19:52:48.895681 DBI_RD = 0x0
2319 19:52:48.895785 OTF = 0x1
2320 19:52:48.899369 ===================================
2321 19:52:48.902458 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2322 19:52:48.906365 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2323 19:52:48.912819 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 19:52:48.915820 ===================================
2325 19:52:48.919306 LPDDR4 DRAM CONFIGURATION
2326 19:52:48.919416 ===================================
2327 19:52:48.922301 EX_ROW_EN[0] = 0x10
2328 19:52:48.925975 EX_ROW_EN[1] = 0x0
2329 19:52:48.926053 LP4Y_EN = 0x0
2330 19:52:48.929301 WORK_FSP = 0x0
2331 19:52:48.929376 WL = 0x4
2332 19:52:48.932400 RL = 0x4
2333 19:52:48.932476 BL = 0x2
2334 19:52:48.935431 RPST = 0x0
2335 19:52:48.935534 RD_PRE = 0x0
2336 19:52:48.939293 WR_PRE = 0x1
2337 19:52:48.939403 WR_PST = 0x0
2338 19:52:48.942433 DBI_WR = 0x0
2339 19:52:48.942511 DBI_RD = 0x0
2340 19:52:48.945318 OTF = 0x1
2341 19:52:48.948710 ===================================
2342 19:52:48.955793 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2343 19:52:48.955901 ==
2344 19:52:48.959174 Dram Type= 6, Freq= 0, CH_0, rank 0
2345 19:52:48.962112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2346 19:52:48.962194 ==
2347 19:52:48.965658 [Duty_Offset_Calibration]
2348 19:52:48.965734 B0:2 B1:0 CA:3
2349 19:52:48.965812
2350 19:52:48.968870 [DutyScan_Calibration_Flow] k_type=0
2351 19:52:48.979535
2352 19:52:48.979615 ==CLK 0==
2353 19:52:48.982858 Final CLK duty delay cell = 0
2354 19:52:48.986649 [0] MAX Duty = 5031%(X100), DQS PI = 12
2355 19:52:48.989472 [0] MIN Duty = 4875%(X100), DQS PI = 58
2356 19:52:48.989549 [0] AVG Duty = 4953%(X100)
2357 19:52:48.993191
2358 19:52:48.993290 CH0 CLK Duty spec in!! Max-Min= 156%
2359 19:52:48.999345 [DutyScan_Calibration_Flow] ====Done====
2360 19:52:48.999453
2361 19:52:49.002939 [DutyScan_Calibration_Flow] k_type=1
2362 19:52:49.017962
2363 19:52:49.018059 ==DQS 0 ==
2364 19:52:49.021543 Final DQS duty delay cell = 0
2365 19:52:49.024733 [0] MAX Duty = 5062%(X100), DQS PI = 14
2366 19:52:49.028106 [0] MIN Duty = 4907%(X100), DQS PI = 44
2367 19:52:49.031613 [0] AVG Duty = 4984%(X100)
2368 19:52:49.031709
2369 19:52:49.031772 ==DQS 1 ==
2370 19:52:49.034496 Final DQS duty delay cell = -4
2371 19:52:49.038145 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2372 19:52:49.041609 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2373 19:52:49.045011 [-4] AVG Duty = 4937%(X100)
2374 19:52:49.045091
2375 19:52:49.048011 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2376 19:52:49.048091
2377 19:52:49.051191 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2378 19:52:49.054558 [DutyScan_Calibration_Flow] ====Done====
2379 19:52:49.054664
2380 19:52:49.057873 [DutyScan_Calibration_Flow] k_type=3
2381 19:52:49.075514
2382 19:52:49.075631 ==DQM 0 ==
2383 19:52:49.078844 Final DQM duty delay cell = 0
2384 19:52:49.082179 [0] MAX Duty = 5124%(X100), DQS PI = 28
2385 19:52:49.085865 [0] MIN Duty = 4907%(X100), DQS PI = 0
2386 19:52:49.085962 [0] AVG Duty = 5015%(X100)
2387 19:52:49.089368
2388 19:52:49.089444 ==DQM 1 ==
2389 19:52:49.092238 Final DQM duty delay cell = 4
2390 19:52:49.095439 [4] MAX Duty = 5124%(X100), DQS PI = 0
2391 19:52:49.098889 [4] MIN Duty = 5031%(X100), DQS PI = 12
2392 19:52:49.098971 [4] AVG Duty = 5077%(X100)
2393 19:52:49.102630
2394 19:52:49.105597 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2395 19:52:49.105680
2396 19:52:49.109133 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2397 19:52:49.112196 [DutyScan_Calibration_Flow] ====Done====
2398 19:52:49.112277
2399 19:52:49.115914 [DutyScan_Calibration_Flow] k_type=2
2400 19:52:49.130440
2401 19:52:49.130526 ==DQ 0 ==
2402 19:52:49.134174 Final DQ duty delay cell = -4
2403 19:52:49.137014 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2404 19:52:49.140426 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2405 19:52:49.143346 [-4] AVG Duty = 4969%(X100)
2406 19:52:49.143438
2407 19:52:49.143503 ==DQ 1 ==
2408 19:52:49.146931 Final DQ duty delay cell = -4
2409 19:52:49.150390 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2410 19:52:49.153592 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2411 19:52:49.157094 [-4] AVG Duty = 4938%(X100)
2412 19:52:49.157176
2413 19:52:49.160077 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2414 19:52:49.160159
2415 19:52:49.163404 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2416 19:52:49.166635 [DutyScan_Calibration_Flow] ====Done====
2417 19:52:49.166717 ==
2418 19:52:49.169989 Dram Type= 6, Freq= 0, CH_1, rank 0
2419 19:52:49.173017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2420 19:52:49.173100 ==
2421 19:52:49.176437 [Duty_Offset_Calibration]
2422 19:52:49.176522 B0:1 B1:-2 CA:0
2423 19:52:49.180057
2424 19:52:49.183030 [DutyScan_Calibration_Flow] k_type=0
2425 19:52:49.191209
2426 19:52:49.191311 ==CLK 0==
2427 19:52:49.194078 Final CLK duty delay cell = 0
2428 19:52:49.197483 [0] MAX Duty = 5062%(X100), DQS PI = 30
2429 19:52:49.201002 [0] MIN Duty = 4876%(X100), DQS PI = 2
2430 19:52:49.201081 [0] AVG Duty = 4969%(X100)
2431 19:52:49.204099
2432 19:52:49.204174 CH1 CLK Duty spec in!! Max-Min= 186%
2433 19:52:49.210810 [DutyScan_Calibration_Flow] ====Done====
2434 19:52:49.210899
2435 19:52:49.214481 [DutyScan_Calibration_Flow] k_type=1
2436 19:52:49.229417
2437 19:52:49.229496 ==DQS 0 ==
2438 19:52:49.232933 Final DQS duty delay cell = -4
2439 19:52:49.235818 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2440 19:52:49.239350 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2441 19:52:49.242237 [-4] AVG Duty = 4969%(X100)
2442 19:52:49.242338
2443 19:52:49.242428 ==DQS 1 ==
2444 19:52:49.245972 Final DQS duty delay cell = 0
2445 19:52:49.248998 [0] MAX Duty = 5093%(X100), DQS PI = 0
2446 19:52:49.252693 [0] MIN Duty = 4875%(X100), DQS PI = 26
2447 19:52:49.256102 [0] AVG Duty = 4984%(X100)
2448 19:52:49.256187
2449 19:52:49.258938 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2450 19:52:49.259022
2451 19:52:49.262752 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2452 19:52:49.266207 [DutyScan_Calibration_Flow] ====Done====
2453 19:52:49.266290
2454 19:52:49.269065 [DutyScan_Calibration_Flow] k_type=3
2455 19:52:49.286355
2456 19:52:49.286451 ==DQM 0 ==
2457 19:52:49.289377 Final DQM duty delay cell = 0
2458 19:52:49.292828 [0] MAX Duty = 5000%(X100), DQS PI = 22
2459 19:52:49.296083 [0] MIN Duty = 4844%(X100), DQS PI = 56
2460 19:52:49.299345 [0] AVG Duty = 4922%(X100)
2461 19:52:49.299470
2462 19:52:49.299561 ==DQM 1 ==
2463 19:52:49.302711 Final DQM duty delay cell = 0
2464 19:52:49.306021 [0] MAX Duty = 5062%(X100), DQS PI = 38
2465 19:52:49.309740 [0] MIN Duty = 4907%(X100), DQS PI = 4
2466 19:52:49.309826 [0] AVG Duty = 4984%(X100)
2467 19:52:49.312657
2468 19:52:49.315916 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2469 19:52:49.315999
2470 19:52:49.319343 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2471 19:52:49.323028 [DutyScan_Calibration_Flow] ====Done====
2472 19:52:49.323114
2473 19:52:49.326008 [DutyScan_Calibration_Flow] k_type=2
2474 19:52:49.342526
2475 19:52:49.342645 ==DQ 0 ==
2476 19:52:49.346055 Final DQ duty delay cell = 0
2477 19:52:49.348909 [0] MAX Duty = 5062%(X100), DQS PI = 16
2478 19:52:49.352276 [0] MIN Duty = 4938%(X100), DQS PI = 54
2479 19:52:49.352380 [0] AVG Duty = 5000%(X100)
2480 19:52:49.352471
2481 19:52:49.356151 ==DQ 1 ==
2482 19:52:49.359166 Final DQ duty delay cell = 0
2483 19:52:49.362661 [0] MAX Duty = 5125%(X100), DQS PI = 36
2484 19:52:49.365561 [0] MIN Duty = 4938%(X100), DQS PI = 26
2485 19:52:49.365665 [0] AVG Duty = 5031%(X100)
2486 19:52:49.365755
2487 19:52:49.369037 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2488 19:52:49.372868
2489 19:52:49.375962 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2490 19:52:49.379367 [DutyScan_Calibration_Flow] ====Done====
2491 19:52:49.382186 nWR fixed to 30
2492 19:52:49.382260 [ModeRegInit_LP4] CH0 RK0
2493 19:52:49.385912 [ModeRegInit_LP4] CH0 RK1
2494 19:52:49.389394 [ModeRegInit_LP4] CH1 RK0
2495 19:52:49.389472 [ModeRegInit_LP4] CH1 RK1
2496 19:52:49.392433 match AC timing 7
2497 19:52:49.395536 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2498 19:52:49.398938 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2499 19:52:49.405662 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2500 19:52:49.408889 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2501 19:52:49.415664 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2502 19:52:49.415756 ==
2503 19:52:49.418957 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 19:52:49.422264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 19:52:49.422340 ==
2506 19:52:49.429217 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2507 19:52:49.435629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2508 19:52:49.442886 [CA 0] Center 40 (10~71) winsize 62
2509 19:52:49.445589 [CA 1] Center 39 (9~70) winsize 62
2510 19:52:49.448854 [CA 2] Center 36 (6~66) winsize 61
2511 19:52:49.452538 [CA 3] Center 35 (5~66) winsize 62
2512 19:52:49.455672 [CA 4] Center 34 (4~65) winsize 62
2513 19:52:49.459048 [CA 5] Center 33 (3~63) winsize 61
2514 19:52:49.459120
2515 19:52:49.462634 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2516 19:52:49.462704
2517 19:52:49.466227 [CATrainingPosCal] consider 1 rank data
2518 19:52:49.468945 u2DelayCellTimex100 = 270/100 ps
2519 19:52:49.472586 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2520 19:52:49.476146 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2521 19:52:49.482596 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2522 19:52:49.485691 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2523 19:52:49.489661 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2524 19:52:49.492877 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2525 19:52:49.492951
2526 19:52:49.496023 CA PerBit enable=1, Macro0, CA PI delay=33
2527 19:52:49.496103
2528 19:52:49.499589 [CBTSetCACLKResult] CA Dly = 33
2529 19:52:49.499664 CS Dly: 7 (0~38)
2530 19:52:49.499725 ==
2531 19:52:49.502687 Dram Type= 6, Freq= 0, CH_0, rank 1
2532 19:52:49.509539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 19:52:49.509616 ==
2534 19:52:49.512743 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2535 19:52:49.519114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2536 19:52:49.528488 [CA 0] Center 40 (10~70) winsize 61
2537 19:52:49.532004 [CA 1] Center 40 (10~70) winsize 61
2538 19:52:49.535467 [CA 2] Center 35 (5~66) winsize 62
2539 19:52:49.538419 [CA 3] Center 35 (5~66) winsize 62
2540 19:52:49.542242 [CA 4] Center 34 (4~65) winsize 62
2541 19:52:49.545334 [CA 5] Center 33 (3~64) winsize 62
2542 19:52:49.545426
2543 19:52:49.548744 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2544 19:52:49.548845
2545 19:52:49.552158 [CATrainingPosCal] consider 2 rank data
2546 19:52:49.555634 u2DelayCellTimex100 = 270/100 ps
2547 19:52:49.558937 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2548 19:52:49.565636 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2549 19:52:49.568653 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2550 19:52:49.572086 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2551 19:52:49.575567 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2552 19:52:49.578837 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2553 19:52:49.578922
2554 19:52:49.581722 CA PerBit enable=1, Macro0, CA PI delay=33
2555 19:52:49.581806
2556 19:52:49.585444 [CBTSetCACLKResult] CA Dly = 33
2557 19:52:49.585529 CS Dly: 8 (0~40)
2558 19:52:49.588433
2559 19:52:49.591884 ----->DramcWriteLeveling(PI) begin...
2560 19:52:49.591988 ==
2561 19:52:49.595645 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 19:52:49.598610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 19:52:49.598696 ==
2564 19:52:49.602018 Write leveling (Byte 0): 34 => 34
2565 19:52:49.605408 Write leveling (Byte 1): 29 => 29
2566 19:52:49.608815 DramcWriteLeveling(PI) end<-----
2567 19:52:49.608908
2568 19:52:49.608976 ==
2569 19:52:49.612462 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 19:52:49.615427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 19:52:49.615511 ==
2572 19:52:49.618878 [Gating] SW mode calibration
2573 19:52:49.625534 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2574 19:52:49.628951 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2575 19:52:49.635533 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 19:52:49.638526 0 15 4 | B1->B0 | 2828 3333 | 1 1 | (1 1) (1 1)
2577 19:52:49.641982 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 19:52:49.648854 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 19:52:49.651902 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 19:52:49.655347 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 19:52:49.662255 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 19:52:49.665146 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
2583 19:52:49.668452 1 0 0 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (1 0)
2584 19:52:49.675311 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2585 19:52:49.678976 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 19:52:49.682056 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 19:52:49.688552 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 19:52:49.692193 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 19:52:49.695186 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 19:52:49.701937 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 19:52:49.705543 1 1 0 | B1->B0 | 2a2a 3837 | 0 1 | (0 0) (0 0)
2592 19:52:49.708432 1 1 4 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2593 19:52:49.714960 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 19:52:49.718337 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 19:52:49.721969 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 19:52:49.728615 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 19:52:49.731787 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 19:52:49.735151 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2599 19:52:49.742044 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2600 19:52:49.744959 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2601 19:52:49.748272 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 19:52:49.755202 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 19:52:49.758672 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 19:52:49.761553 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 19:52:49.765139 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 19:52:49.771553 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 19:52:49.774876 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 19:52:49.778238 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 19:52:49.785404 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 19:52:49.788277 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 19:52:49.791595 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 19:52:49.798527 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 19:52:49.801558 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 19:52:49.805407 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2615 19:52:49.811556 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2616 19:52:49.815196 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2617 19:52:49.818153 Total UI for P1: 0, mck2ui 16
2618 19:52:49.821799 best dqsien dly found for B0: ( 1, 3, 30)
2619 19:52:49.825164 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 19:52:49.828849 Total UI for P1: 0, mck2ui 16
2621 19:52:49.831613 best dqsien dly found for B1: ( 1, 4, 2)
2622 19:52:49.835029 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2623 19:52:49.838305 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2624 19:52:49.838388
2625 19:52:49.841869 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2626 19:52:49.848681 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2627 19:52:49.848770 [Gating] SW calibration Done
2628 19:52:49.848870 ==
2629 19:52:49.852046 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 19:52:49.858713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 19:52:49.858831 ==
2632 19:52:49.858898 RX Vref Scan: 0
2633 19:52:49.858959
2634 19:52:49.862185 RX Vref 0 -> 0, step: 1
2635 19:52:49.862282
2636 19:52:49.865061 RX Delay -40 -> 252, step: 8
2637 19:52:49.868715 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2638 19:52:49.872156 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2639 19:52:49.875156 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2640 19:52:49.881622 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2641 19:52:49.885016 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2642 19:52:49.888235 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2643 19:52:49.891594 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2644 19:52:49.895533 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2645 19:52:49.898364 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2646 19:52:49.904947 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2647 19:52:49.908476 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2648 19:52:49.911746 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2649 19:52:49.915530 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2650 19:52:49.918358 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2651 19:52:49.925732 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2652 19:52:49.928606 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2653 19:52:49.928696 ==
2654 19:52:49.932071 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 19:52:49.935004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 19:52:49.935106 ==
2657 19:52:49.938665 DQS Delay:
2658 19:52:49.938749 DQS0 = 0, DQS1 = 0
2659 19:52:49.938816 DQM Delay:
2660 19:52:49.941715 DQM0 = 112, DQM1 = 103
2661 19:52:49.941799 DQ Delay:
2662 19:52:49.945015 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2663 19:52:49.948358 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2664 19:52:49.952106 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2665 19:52:49.955049 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2666 19:52:49.955133
2667 19:52:49.958492
2668 19:52:49.958591 ==
2669 19:52:49.961639 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 19:52:49.965195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 19:52:49.965281 ==
2672 19:52:49.965348
2673 19:52:49.965408
2674 19:52:49.968754 TX Vref Scan disable
2675 19:52:49.968839 == TX Byte 0 ==
2676 19:52:49.975326 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2677 19:52:49.978461 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2678 19:52:49.978547 == TX Byte 1 ==
2679 19:52:49.985076 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2680 19:52:49.988750 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2681 19:52:49.988836 ==
2682 19:52:49.991778 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 19:52:49.995196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 19:52:49.995284 ==
2685 19:52:50.007858 TX Vref=22, minBit 0, minWin=25, winSum=414
2686 19:52:50.011004 TX Vref=24, minBit 7, minWin=25, winSum=419
2687 19:52:50.014602 TX Vref=26, minBit 7, minWin=25, winSum=427
2688 19:52:50.017698 TX Vref=28, minBit 4, minWin=26, winSum=432
2689 19:52:50.021392 TX Vref=30, minBit 10, minWin=26, winSum=432
2690 19:52:50.027932 TX Vref=32, minBit 1, minWin=26, winSum=423
2691 19:52:50.031474 [TxChooseVref] Worse bit 4, Min win 26, Win sum 432, Final Vref 28
2692 19:52:50.031559
2693 19:52:50.034320 Final TX Range 1 Vref 28
2694 19:52:50.034405
2695 19:52:50.034470 ==
2696 19:52:50.037918 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 19:52:50.040974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 19:52:50.041058 ==
2699 19:52:50.044206
2700 19:52:50.044290
2701 19:52:50.044356 TX Vref Scan disable
2702 19:52:50.047987 == TX Byte 0 ==
2703 19:52:50.050836 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2704 19:52:50.054240 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2705 19:52:50.057592 == TX Byte 1 ==
2706 19:52:50.061017 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2707 19:52:50.064631 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2708 19:52:50.064719
2709 19:52:50.067533 [DATLAT]
2710 19:52:50.067640 Freq=1200, CH0 RK0
2711 19:52:50.067734
2712 19:52:50.071111 DATLAT Default: 0xd
2713 19:52:50.071213 0, 0xFFFF, sum = 0
2714 19:52:50.074535 1, 0xFFFF, sum = 0
2715 19:52:50.074623 2, 0xFFFF, sum = 0
2716 19:52:50.077569 3, 0xFFFF, sum = 0
2717 19:52:50.077654 4, 0xFFFF, sum = 0
2718 19:52:50.081120 5, 0xFFFF, sum = 0
2719 19:52:50.081203 6, 0xFFFF, sum = 0
2720 19:52:50.084206 7, 0xFFFF, sum = 0
2721 19:52:50.084289 8, 0xFFFF, sum = 0
2722 19:52:50.087790 9, 0xFFFF, sum = 0
2723 19:52:50.090870 10, 0xFFFF, sum = 0
2724 19:52:50.090952 11, 0xFFFF, sum = 0
2725 19:52:50.094207 12, 0x0, sum = 1
2726 19:52:50.094292 13, 0x0, sum = 2
2727 19:52:50.094359 14, 0x0, sum = 3
2728 19:52:50.097599 15, 0x0, sum = 4
2729 19:52:50.097706 best_step = 13
2730 19:52:50.097774
2731 19:52:50.101186 ==
2732 19:52:50.101274 Dram Type= 6, Freq= 0, CH_0, rank 0
2733 19:52:50.107717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2734 19:52:50.107938 ==
2735 19:52:50.108012 RX Vref Scan: 1
2736 19:52:50.108075
2737 19:52:50.111261 Set Vref Range= 32 -> 127
2738 19:52:50.111409
2739 19:52:50.114778 RX Vref 32 -> 127, step: 1
2740 19:52:50.114882
2741 19:52:50.117682 RX Delay -37 -> 252, step: 4
2742 19:52:50.117820
2743 19:52:50.121209 Set Vref, RX VrefLevel [Byte0]: 32
2744 19:52:50.124653 [Byte1]: 32
2745 19:52:50.124789
2746 19:52:50.127838 Set Vref, RX VrefLevel [Byte0]: 33
2747 19:52:50.131247 [Byte1]: 33
2748 19:52:50.134280
2749 19:52:50.134362 Set Vref, RX VrefLevel [Byte0]: 34
2750 19:52:50.137751 [Byte1]: 34
2751 19:52:50.142058
2752 19:52:50.142139 Set Vref, RX VrefLevel [Byte0]: 35
2753 19:52:50.145463 [Byte1]: 35
2754 19:52:50.150289
2755 19:52:50.150371 Set Vref, RX VrefLevel [Byte0]: 36
2756 19:52:50.153932 [Byte1]: 36
2757 19:52:50.158034
2758 19:52:50.158116 Set Vref, RX VrefLevel [Byte0]: 37
2759 19:52:50.161408 [Byte1]: 37
2760 19:52:50.166289
2761 19:52:50.166370 Set Vref, RX VrefLevel [Byte0]: 38
2762 19:52:50.169193 [Byte1]: 38
2763 19:52:50.174002
2764 19:52:50.174084 Set Vref, RX VrefLevel [Byte0]: 39
2765 19:52:50.177757 [Byte1]: 39
2766 19:52:50.182455
2767 19:52:50.182536 Set Vref, RX VrefLevel [Byte0]: 40
2768 19:52:50.185691 [Byte1]: 40
2769 19:52:50.190389
2770 19:52:50.190480 Set Vref, RX VrefLevel [Byte0]: 41
2771 19:52:50.193744 [Byte1]: 41
2772 19:52:50.198568
2773 19:52:50.198665 Set Vref, RX VrefLevel [Byte0]: 42
2774 19:52:50.201675 [Byte1]: 42
2775 19:52:50.206462
2776 19:52:50.206575 Set Vref, RX VrefLevel [Byte0]: 43
2777 19:52:50.209292 [Byte1]: 43
2778 19:52:50.214422
2779 19:52:50.214513 Set Vref, RX VrefLevel [Byte0]: 44
2780 19:52:50.217804 [Byte1]: 44
2781 19:52:50.222493
2782 19:52:50.222574 Set Vref, RX VrefLevel [Byte0]: 45
2783 19:52:50.225826 [Byte1]: 45
2784 19:52:50.230060
2785 19:52:50.230140 Set Vref, RX VrefLevel [Byte0]: 46
2786 19:52:50.233403 [Byte1]: 46
2787 19:52:50.238505
2788 19:52:50.238585 Set Vref, RX VrefLevel [Byte0]: 47
2789 19:52:50.241790 [Byte1]: 47
2790 19:52:50.246202
2791 19:52:50.246283 Set Vref, RX VrefLevel [Byte0]: 48
2792 19:52:50.249699 [Byte1]: 48
2793 19:52:50.254518
2794 19:52:50.254599 Set Vref, RX VrefLevel [Byte0]: 49
2795 19:52:50.257889 [Byte1]: 49
2796 19:52:50.262028
2797 19:52:50.262109 Set Vref, RX VrefLevel [Byte0]: 50
2798 19:52:50.265378 [Byte1]: 50
2799 19:52:50.270496
2800 19:52:50.270579 Set Vref, RX VrefLevel [Byte0]: 51
2801 19:52:50.273964 [Byte1]: 51
2802 19:52:50.278056
2803 19:52:50.278136 Set Vref, RX VrefLevel [Byte0]: 52
2804 19:52:50.281748 [Byte1]: 52
2805 19:52:50.285998
2806 19:52:50.286080 Set Vref, RX VrefLevel [Byte0]: 53
2807 19:52:50.289326 [Byte1]: 53
2808 19:52:50.294199
2809 19:52:50.294304 Set Vref, RX VrefLevel [Byte0]: 54
2810 19:52:50.297851 [Byte1]: 54
2811 19:52:50.301994
2812 19:52:50.302066 Set Vref, RX VrefLevel [Byte0]: 55
2813 19:52:50.305321 [Byte1]: 55
2814 19:52:50.310043
2815 19:52:50.310111 Set Vref, RX VrefLevel [Byte0]: 56
2816 19:52:50.313692 [Byte1]: 56
2817 19:52:50.318248
2818 19:52:50.318348 Set Vref, RX VrefLevel [Byte0]: 57
2819 19:52:50.321267 [Byte1]: 57
2820 19:52:50.326562
2821 19:52:50.326636 Set Vref, RX VrefLevel [Byte0]: 58
2822 19:52:50.329546 [Byte1]: 58
2823 19:52:50.333963
2824 19:52:50.334061 Set Vref, RX VrefLevel [Byte0]: 59
2825 19:52:50.337750 [Byte1]: 59
2826 19:52:50.342155
2827 19:52:50.342253 Set Vref, RX VrefLevel [Byte0]: 60
2828 19:52:50.345547 [Byte1]: 60
2829 19:52:50.350453
2830 19:52:50.350551 Set Vref, RX VrefLevel [Byte0]: 61
2831 19:52:50.353946 [Byte1]: 61
2832 19:52:50.358522
2833 19:52:50.358626 Set Vref, RX VrefLevel [Byte0]: 62
2834 19:52:50.364542 [Byte1]: 62
2835 19:52:50.364646
2836 19:52:50.367991 Set Vref, RX VrefLevel [Byte0]: 63
2837 19:52:50.371535 [Byte1]: 63
2838 19:52:50.371621
2839 19:52:50.374787 Set Vref, RX VrefLevel [Byte0]: 64
2840 19:52:50.377996 [Byte1]: 64
2841 19:52:50.382149
2842 19:52:50.382230 Set Vref, RX VrefLevel [Byte0]: 65
2843 19:52:50.385880 [Byte1]: 65
2844 19:52:50.390443
2845 19:52:50.390525 Set Vref, RX VrefLevel [Byte0]: 66
2846 19:52:50.393446 [Byte1]: 66
2847 19:52:50.398233
2848 19:52:50.398314 Set Vref, RX VrefLevel [Byte0]: 67
2849 19:52:50.401713 [Byte1]: 67
2850 19:52:50.405974
2851 19:52:50.406055 Set Vref, RX VrefLevel [Byte0]: 68
2852 19:52:50.409560 [Byte1]: 68
2853 19:52:50.414383
2854 19:52:50.414464 Set Vref, RX VrefLevel [Byte0]: 69
2855 19:52:50.417725 [Byte1]: 69
2856 19:52:50.422204
2857 19:52:50.422285 Set Vref, RX VrefLevel [Byte0]: 70
2858 19:52:50.425433 [Byte1]: 70
2859 19:52:50.430445
2860 19:52:50.430526 Set Vref, RX VrefLevel [Byte0]: 71
2861 19:52:50.433405 [Byte1]: 71
2862 19:52:50.438083
2863 19:52:50.438165 Set Vref, RX VrefLevel [Byte0]: 72
2864 19:52:50.441742 [Byte1]: 72
2865 19:52:50.446168
2866 19:52:50.446250 Set Vref, RX VrefLevel [Byte0]: 73
2867 19:52:50.449660 [Byte1]: 73
2868 19:52:50.454407
2869 19:52:50.454488 Set Vref, RX VrefLevel [Byte0]: 74
2870 19:52:50.457347 [Byte1]: 74
2871 19:52:50.462745
2872 19:52:50.462827 Final RX Vref Byte 0 = 61 to rank0
2873 19:52:50.465705 Final RX Vref Byte 1 = 53 to rank0
2874 19:52:50.469042 Final RX Vref Byte 0 = 61 to rank1
2875 19:52:50.472048 Final RX Vref Byte 1 = 53 to rank1==
2876 19:52:50.475287 Dram Type= 6, Freq= 0, CH_0, rank 0
2877 19:52:50.482299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 19:52:50.482380 ==
2879 19:52:50.482445 DQS Delay:
2880 19:52:50.482505 DQS0 = 0, DQS1 = 0
2881 19:52:50.485576 DQM Delay:
2882 19:52:50.485657 DQM0 = 112, DQM1 = 101
2883 19:52:50.488820 DQ Delay:
2884 19:52:50.492366 DQ0 =112, DQ1 =112, DQ2 =110, DQ3 =108
2885 19:52:50.495770 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2886 19:52:50.498832 DQ8 =92, DQ9 =86, DQ10 =104, DQ11 =94
2887 19:52:50.502324 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2888 19:52:50.502406
2889 19:52:50.502471
2890 19:52:50.508912 [DQSOSCAuto] RK0, (LSB)MR18= 0xffff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2891 19:52:50.512534 CH0 RK0: MR19=303, MR18=FFFF
2892 19:52:50.519078 CH0_RK0: MR19=0x303, MR18=0xFFFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2893 19:52:50.519160
2894 19:52:50.522050 ----->DramcWriteLeveling(PI) begin...
2895 19:52:50.522132 ==
2896 19:52:50.525431 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 19:52:50.528721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 19:52:50.532004 ==
2899 19:52:50.532086 Write leveling (Byte 0): 34 => 34
2900 19:52:50.535450 Write leveling (Byte 1): 31 => 31
2901 19:52:50.538921 DramcWriteLeveling(PI) end<-----
2902 19:52:50.539002
2903 19:52:50.539066 ==
2904 19:52:50.542129 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 19:52:50.548512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 19:52:50.548600 ==
2907 19:52:50.548674 [Gating] SW mode calibration
2908 19:52:50.558855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2909 19:52:50.562327 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2910 19:52:50.565338 0 15 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2911 19:52:50.571925 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 19:52:50.575491 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 19:52:50.578884 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 19:52:50.585272 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 19:52:50.589037 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 19:52:50.592588 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2917 19:52:50.598974 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
2918 19:52:50.602302 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2919 19:52:50.605345 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 19:52:50.612105 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 19:52:50.615709 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 19:52:50.618818 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 19:52:50.625390 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 19:52:50.629004 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
2925 19:52:50.632579 1 0 28 | B1->B0 | 2525 4545 | 0 0 | (0 0) (1 1)
2926 19:52:50.635824 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2927 19:52:50.642543 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 19:52:50.645643 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 19:52:50.649087 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 19:52:50.655601 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 19:52:50.659086 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 19:52:50.662067 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 19:52:50.668656 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2934 19:52:50.672308 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2935 19:52:50.675752 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 19:52:50.682297 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 19:52:50.686114 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 19:52:50.688999 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 19:52:50.695977 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 19:52:50.698932 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 19:52:50.702516 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 19:52:50.708964 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 19:52:50.711953 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 19:52:50.715358 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 19:52:50.721921 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 19:52:50.725505 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 19:52:50.728491 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 19:52:50.735758 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 19:52:50.738592 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2950 19:52:50.741910 Total UI for P1: 0, mck2ui 16
2951 19:52:50.745228 best dqsien dly found for B0: ( 1, 3, 26)
2952 19:52:50.748518 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2953 19:52:50.752425 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 19:52:50.755244 Total UI for P1: 0, mck2ui 16
2955 19:52:50.758850 best dqsien dly found for B1: ( 1, 3, 30)
2956 19:52:50.761923 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2957 19:52:50.765421 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2958 19:52:50.768878
2959 19:52:50.771885 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2960 19:52:50.775415 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2961 19:52:50.779067 [Gating] SW calibration Done
2962 19:52:50.779148 ==
2963 19:52:50.782062 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 19:52:50.785619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 19:52:50.785701 ==
2966 19:52:50.785765 RX Vref Scan: 0
2967 19:52:50.785825
2968 19:52:50.789049 RX Vref 0 -> 0, step: 1
2969 19:52:50.789130
2970 19:52:50.792044 RX Delay -40 -> 252, step: 8
2971 19:52:50.795606 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2972 19:52:50.799006 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2973 19:52:50.805646 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2974 19:52:50.809245 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2975 19:52:50.812187 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2976 19:52:50.815699 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2977 19:52:50.818799 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2978 19:52:50.822356 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2979 19:52:50.828772 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2980 19:52:50.832155 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2981 19:52:50.835918 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2982 19:52:50.838883 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2983 19:52:50.842601 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2984 19:52:50.848885 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2985 19:52:50.852346 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2986 19:52:50.855779 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2987 19:52:50.855861 ==
2988 19:52:50.859185 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 19:52:50.862087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 19:52:50.862169 ==
2991 19:52:50.865643 DQS Delay:
2992 19:52:50.865725 DQS0 = 0, DQS1 = 0
2993 19:52:50.868924 DQM Delay:
2994 19:52:50.869019 DQM0 = 113, DQM1 = 101
2995 19:52:50.869084 DQ Delay:
2996 19:52:50.875786 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2997 19:52:50.878815 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2998 19:52:50.882267 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2999 19:52:50.886044 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
3000 19:52:50.886126
3001 19:52:50.886190
3002 19:52:50.886311 ==
3003 19:52:50.889389 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 19:52:50.892456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 19:52:50.892553 ==
3006 19:52:50.892617
3007 19:52:50.892677
3008 19:52:50.895935 TX Vref Scan disable
3009 19:52:50.898955 == TX Byte 0 ==
3010 19:52:50.902188 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3011 19:52:50.905861 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3012 19:52:50.905942 == TX Byte 1 ==
3013 19:52:50.912461 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3014 19:52:50.915366 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3015 19:52:50.915472 ==
3016 19:52:50.918815 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 19:52:50.921955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 19:52:50.922040 ==
3019 19:52:50.935446 TX Vref=22, minBit 1, minWin=25, winSum=426
3020 19:52:50.939324 TX Vref=24, minBit 2, minWin=26, winSum=429
3021 19:52:50.942024 TX Vref=26, minBit 2, minWin=26, winSum=434
3022 19:52:50.945752 TX Vref=28, minBit 0, minWin=27, winSum=439
3023 19:52:50.948896 TX Vref=30, minBit 8, minWin=26, winSum=439
3024 19:52:50.955248 TX Vref=32, minBit 13, minWin=26, winSum=438
3025 19:52:50.958725 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 28
3026 19:52:50.958808
3027 19:52:50.962347 Final TX Range 1 Vref 28
3028 19:52:50.962461
3029 19:52:50.962525 ==
3030 19:52:50.965415 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 19:52:50.968549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 19:52:50.968631 ==
3033 19:52:50.972162
3034 19:52:50.972243
3035 19:52:50.972307 TX Vref Scan disable
3036 19:52:50.975615 == TX Byte 0 ==
3037 19:52:50.978901 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3038 19:52:50.981959 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3039 19:52:50.985966 == TX Byte 1 ==
3040 19:52:50.988637 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3041 19:52:50.992570 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3042 19:52:50.992691
3043 19:52:50.995267 [DATLAT]
3044 19:52:50.995375 Freq=1200, CH0 RK1
3045 19:52:50.995491
3046 19:52:50.999200 DATLAT Default: 0xd
3047 19:52:50.999307 0, 0xFFFF, sum = 0
3048 19:52:51.002205 1, 0xFFFF, sum = 0
3049 19:52:51.002314 2, 0xFFFF, sum = 0
3050 19:52:51.005650 3, 0xFFFF, sum = 0
3051 19:52:51.005758 4, 0xFFFF, sum = 0
3052 19:52:51.008758 5, 0xFFFF, sum = 0
3053 19:52:51.008834 6, 0xFFFF, sum = 0
3054 19:52:51.011927 7, 0xFFFF, sum = 0
3055 19:52:51.015281 8, 0xFFFF, sum = 0
3056 19:52:51.015404 9, 0xFFFF, sum = 0
3057 19:52:51.018973 10, 0xFFFF, sum = 0
3058 19:52:51.019071 11, 0xFFFF, sum = 0
3059 19:52:51.022142 12, 0x0, sum = 1
3060 19:52:51.022240 13, 0x0, sum = 2
3061 19:52:51.025758 14, 0x0, sum = 3
3062 19:52:51.025857 15, 0x0, sum = 4
3063 19:52:51.025947 best_step = 13
3064 19:52:51.026037
3065 19:52:51.028658 ==
3066 19:52:51.032207 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 19:52:51.035672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 19:52:51.035744 ==
3069 19:52:51.035804 RX Vref Scan: 0
3070 19:52:51.035894
3071 19:52:51.038727 RX Vref 0 -> 0, step: 1
3072 19:52:51.038822
3073 19:52:51.042023 RX Delay -37 -> 252, step: 4
3074 19:52:51.045252 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3075 19:52:51.051805 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3076 19:52:51.055169 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3077 19:52:51.058737 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3078 19:52:51.061766 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3079 19:52:51.065144 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3080 19:52:51.071815 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3081 19:52:51.075269 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3082 19:52:51.078310 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3083 19:52:51.082159 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3084 19:52:51.085023 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3085 19:52:51.088618 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3086 19:52:51.095003 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3087 19:52:51.098696 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3088 19:52:51.101892 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3089 19:52:51.105377 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3090 19:52:51.105457 ==
3091 19:52:51.108540 Dram Type= 6, Freq= 0, CH_0, rank 1
3092 19:52:51.114917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 19:52:51.114993 ==
3094 19:52:51.115055 DQS Delay:
3095 19:52:51.118707 DQS0 = 0, DQS1 = 0
3096 19:52:51.118807 DQM Delay:
3097 19:52:51.118896 DQM0 = 110, DQM1 = 101
3098 19:52:51.122222 DQ Delay:
3099 19:52:51.125027 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3100 19:52:51.128682 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3101 19:52:51.131639 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3102 19:52:51.135288 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3103 19:52:51.135414
3104 19:52:51.135520
3105 19:52:51.145495 [DQSOSCAuto] RK1, (LSB)MR18= 0x12fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3106 19:52:51.145571 CH0 RK1: MR19=403, MR18=12FA
3107 19:52:51.152040 CH0_RK1: MR19=0x403, MR18=0x12FA, DQSOSC=403, MR23=63, INC=40, DEC=26
3108 19:52:51.155335 [RxdqsGatingPostProcess] freq 1200
3109 19:52:51.162060 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3110 19:52:51.165192 best DQS0 dly(2T, 0.5T) = (0, 11)
3111 19:52:51.168926 best DQS1 dly(2T, 0.5T) = (0, 12)
3112 19:52:51.169008 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3113 19:52:51.171764 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3114 19:52:51.175697 best DQS0 dly(2T, 0.5T) = (0, 11)
3115 19:52:51.178503 best DQS1 dly(2T, 0.5T) = (0, 11)
3116 19:52:51.182474 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3117 19:52:51.185283 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3118 19:52:51.188654 Pre-setting of DQS Precalculation
3119 19:52:51.195736 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3120 19:52:51.195818 ==
3121 19:52:51.198502 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 19:52:51.202178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 19:52:51.202261 ==
3124 19:52:51.208975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3125 19:52:51.211948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3126 19:52:51.221859 [CA 0] Center 37 (7~67) winsize 61
3127 19:52:51.224828 [CA 1] Center 37 (7~68) winsize 62
3128 19:52:51.228213 [CA 2] Center 34 (5~64) winsize 60
3129 19:52:51.231428 [CA 3] Center 33 (3~64) winsize 62
3130 19:52:51.234731 [CA 4] Center 34 (4~64) winsize 61
3131 19:52:51.238404 [CA 5] Center 33 (3~63) winsize 61
3132 19:52:51.238485
3133 19:52:51.241610 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3134 19:52:51.241692
3135 19:52:51.245218 [CATrainingPosCal] consider 1 rank data
3136 19:52:51.248285 u2DelayCellTimex100 = 270/100 ps
3137 19:52:51.251571 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3138 19:52:51.254940 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3139 19:52:51.261876 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3140 19:52:51.264695 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3141 19:52:51.268351 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3142 19:52:51.271772 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3143 19:52:51.271854
3144 19:52:51.275038 CA PerBit enable=1, Macro0, CA PI delay=33
3145 19:52:51.275119
3146 19:52:51.278198 [CBTSetCACLKResult] CA Dly = 33
3147 19:52:51.278279 CS Dly: 6 (0~37)
3148 19:52:51.278345 ==
3149 19:52:51.281579 Dram Type= 6, Freq= 0, CH_1, rank 1
3150 19:52:51.288336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 19:52:51.288418 ==
3152 19:52:51.291541 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3153 19:52:51.297945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3154 19:52:51.307279 [CA 0] Center 37 (7~67) winsize 61
3155 19:52:51.310845 [CA 1] Center 37 (7~68) winsize 62
3156 19:52:51.313829 [CA 2] Center 34 (4~65) winsize 62
3157 19:52:51.317217 [CA 3] Center 33 (3~64) winsize 62
3158 19:52:51.320234 [CA 4] Center 34 (4~65) winsize 62
3159 19:52:51.323804 [CA 5] Center 32 (2~63) winsize 62
3160 19:52:51.323885
3161 19:52:51.326931 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3162 19:52:51.327012
3163 19:52:51.330477 [CATrainingPosCal] consider 2 rank data
3164 19:52:51.333960 u2DelayCellTimex100 = 270/100 ps
3165 19:52:51.337495 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3166 19:52:51.340275 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3167 19:52:51.347212 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3168 19:52:51.350765 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3169 19:52:51.354055 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3170 19:52:51.356993 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3171 19:52:51.357090
3172 19:52:51.360570 CA PerBit enable=1, Macro0, CA PI delay=33
3173 19:52:51.360651
3174 19:52:51.363745 [CBTSetCACLKResult] CA Dly = 33
3175 19:52:51.363827 CS Dly: 7 (0~40)
3176 19:52:51.363893
3177 19:52:51.367375 ----->DramcWriteLeveling(PI) begin...
3178 19:52:51.370472 ==
3179 19:52:51.370553 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 19:52:51.377340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 19:52:51.377423 ==
3182 19:52:51.380823 Write leveling (Byte 0): 25 => 25
3183 19:52:51.383779 Write leveling (Byte 1): 31 => 31
3184 19:52:51.387213 DramcWriteLeveling(PI) end<-----
3185 19:52:51.387294
3186 19:52:51.387357 ==
3187 19:52:51.390388 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 19:52:51.393637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 19:52:51.393719 ==
3190 19:52:51.396980 [Gating] SW mode calibration
3191 19:52:51.403876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3192 19:52:51.407335 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3193 19:52:51.414142 0 15 0 | B1->B0 | 3131 2e2e | 0 1 | (0 0) (1 1)
3194 19:52:51.417261 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 19:52:51.420621 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 19:52:51.427046 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 19:52:51.430389 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 19:52:51.434217 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 19:52:51.440775 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 19:52:51.443753 0 15 28 | B1->B0 | 2c2c 3333 | 1 1 | (1 0) (1 0)
3201 19:52:51.447157 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 19:52:51.453793 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 19:52:51.457285 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 19:52:51.460720 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 19:52:51.467293 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 19:52:51.470754 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 19:52:51.474364 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 19:52:51.477465 1 0 28 | B1->B0 | 3e3e 3e3e | 0 0 | (0 0) (0 0)
3209 19:52:51.483935 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 19:52:51.487277 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 19:52:51.490849 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 19:52:51.497177 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 19:52:51.500285 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 19:52:51.503692 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 19:52:51.510558 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 19:52:51.513953 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3217 19:52:51.517184 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3218 19:52:51.524127 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 19:52:51.527396 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 19:52:51.530485 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 19:52:51.537004 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 19:52:51.540378 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 19:52:51.543583 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 19:52:51.550105 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 19:52:51.553621 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 19:52:51.557058 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 19:52:51.563619 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 19:52:51.567125 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 19:52:51.570721 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 19:52:51.576760 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 19:52:51.580311 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 19:52:51.583518 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3233 19:52:51.590493 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 19:52:51.590569 Total UI for P1: 0, mck2ui 16
3235 19:52:51.593434 best dqsien dly found for B0: ( 1, 3, 28)
3236 19:52:51.597173 Total UI for P1: 0, mck2ui 16
3237 19:52:51.600619 best dqsien dly found for B1: ( 1, 3, 28)
3238 19:52:51.603719 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3239 19:52:51.610366 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3240 19:52:51.610448
3241 19:52:51.613353 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3242 19:52:51.616854 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3243 19:52:51.620372 [Gating] SW calibration Done
3244 19:52:51.620475 ==
3245 19:52:51.623819 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 19:52:51.626888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 19:52:51.627003 ==
3248 19:52:51.627098 RX Vref Scan: 0
3249 19:52:51.630141
3250 19:52:51.630218 RX Vref 0 -> 0, step: 1
3251 19:52:51.630283
3252 19:52:51.634280 RX Delay -40 -> 252, step: 8
3253 19:52:51.637052 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3254 19:52:51.640041 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3255 19:52:51.646708 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3256 19:52:51.650379 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3257 19:52:51.653972 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3258 19:52:51.657436 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3259 19:52:51.660427 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3260 19:52:51.667478 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3261 19:52:51.670452 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3262 19:52:51.674043 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3263 19:52:51.676910 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3264 19:52:51.680341 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3265 19:52:51.687181 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3266 19:52:51.690263 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3267 19:52:51.693647 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3268 19:52:51.697343 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3269 19:52:51.697441 ==
3270 19:52:51.700258 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 19:52:51.706833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 19:52:51.706933 ==
3273 19:52:51.707034 DQS Delay:
3274 19:52:51.707123 DQS0 = 0, DQS1 = 0
3275 19:52:51.710427 DQM Delay:
3276 19:52:51.710524 DQM0 = 115, DQM1 = 106
3277 19:52:51.713592 DQ Delay:
3278 19:52:51.717031 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3279 19:52:51.720367 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3280 19:52:51.723615 DQ8 =99, DQ9 =99, DQ10 =103, DQ11 =103
3281 19:52:51.726963 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3282 19:52:51.727046
3283 19:52:51.727122
3284 19:52:51.727212 ==
3285 19:52:51.730106 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 19:52:51.733891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 19:52:51.733963 ==
3288 19:52:51.734039
3289 19:52:51.736581
3290 19:52:51.736651 TX Vref Scan disable
3291 19:52:51.740498 == TX Byte 0 ==
3292 19:52:51.743315 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3293 19:52:51.746958 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3294 19:52:51.750111 == TX Byte 1 ==
3295 19:52:51.753722 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3296 19:52:51.756803 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3297 19:52:51.756891 ==
3298 19:52:51.760075 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 19:52:51.767012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 19:52:51.767117 ==
3301 19:52:51.777625 TX Vref=22, minBit 8, minWin=25, winSum=417
3302 19:52:51.781311 TX Vref=24, minBit 1, minWin=25, winSum=420
3303 19:52:51.784092 TX Vref=26, minBit 1, minWin=26, winSum=428
3304 19:52:51.787623 TX Vref=28, minBit 11, minWin=26, winSum=434
3305 19:52:51.791042 TX Vref=30, minBit 1, minWin=26, winSum=431
3306 19:52:51.794122 TX Vref=32, minBit 0, minWin=26, winSum=426
3307 19:52:51.800680 [TxChooseVref] Worse bit 11, Min win 26, Win sum 434, Final Vref 28
3308 19:52:51.800757
3309 19:52:51.804026 Final TX Range 1 Vref 28
3310 19:52:51.804132
3311 19:52:51.804197 ==
3312 19:52:51.807811 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 19:52:51.811248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 19:52:51.811352 ==
3315 19:52:51.813970
3316 19:52:51.814073
3317 19:52:51.814153 TX Vref Scan disable
3318 19:52:51.817177 == TX Byte 0 ==
3319 19:52:51.820622 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3320 19:52:51.823907 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3321 19:52:51.827658 == TX Byte 1 ==
3322 19:52:51.831115 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3323 19:52:51.833950 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3324 19:52:51.837558
3325 19:52:51.837685 [DATLAT]
3326 19:52:51.837791 Freq=1200, CH1 RK0
3327 19:52:51.837851
3328 19:52:51.840900 DATLAT Default: 0xd
3329 19:52:51.840979 0, 0xFFFF, sum = 0
3330 19:52:51.844210 1, 0xFFFF, sum = 0
3331 19:52:51.844315 2, 0xFFFF, sum = 0
3332 19:52:51.847211 3, 0xFFFF, sum = 0
3333 19:52:51.847319 4, 0xFFFF, sum = 0
3334 19:52:51.850817 5, 0xFFFF, sum = 0
3335 19:52:51.854389 6, 0xFFFF, sum = 0
3336 19:52:51.854473 7, 0xFFFF, sum = 0
3337 19:52:51.858022 8, 0xFFFF, sum = 0
3338 19:52:51.858103 9, 0xFFFF, sum = 0
3339 19:52:51.860739 10, 0xFFFF, sum = 0
3340 19:52:51.860820 11, 0xFFFF, sum = 0
3341 19:52:51.863926 12, 0x0, sum = 1
3342 19:52:51.864007 13, 0x0, sum = 2
3343 19:52:51.867508 14, 0x0, sum = 3
3344 19:52:51.867600 15, 0x0, sum = 4
3345 19:52:51.867665 best_step = 13
3346 19:52:51.867723
3347 19:52:51.870956 ==
3348 19:52:51.874227 Dram Type= 6, Freq= 0, CH_1, rank 0
3349 19:52:51.877353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3350 19:52:51.877460 ==
3351 19:52:51.877551 RX Vref Scan: 1
3352 19:52:51.877700
3353 19:52:51.880748 Set Vref Range= 32 -> 127
3354 19:52:51.880844
3355 19:52:51.884519 RX Vref 32 -> 127, step: 1
3356 19:52:51.884600
3357 19:52:51.887315 RX Delay -13 -> 252, step: 4
3358 19:52:51.887403
3359 19:52:51.890649 Set Vref, RX VrefLevel [Byte0]: 32
3360 19:52:51.894083 [Byte1]: 32
3361 19:52:51.894163
3362 19:52:51.897513 Set Vref, RX VrefLevel [Byte0]: 33
3363 19:52:51.900706 [Byte1]: 33
3364 19:52:51.900786
3365 19:52:51.904266 Set Vref, RX VrefLevel [Byte0]: 34
3366 19:52:51.907258 [Byte1]: 34
3367 19:52:51.911993
3368 19:52:51.912074 Set Vref, RX VrefLevel [Byte0]: 35
3369 19:52:51.914920 [Byte1]: 35
3370 19:52:51.919402
3371 19:52:51.919496 Set Vref, RX VrefLevel [Byte0]: 36
3372 19:52:51.923133 [Byte1]: 36
3373 19:52:51.927658
3374 19:52:51.927739 Set Vref, RX VrefLevel [Byte0]: 37
3375 19:52:51.931135 [Byte1]: 37
3376 19:52:51.935276
3377 19:52:51.935357 Set Vref, RX VrefLevel [Byte0]: 38
3378 19:52:51.938691 [Byte1]: 38
3379 19:52:51.943455
3380 19:52:51.943535 Set Vref, RX VrefLevel [Byte0]: 39
3381 19:52:51.946700 [Byte1]: 39
3382 19:52:51.950930
3383 19:52:51.951011 Set Vref, RX VrefLevel [Byte0]: 40
3384 19:52:51.954487 [Byte1]: 40
3385 19:52:51.959286
3386 19:52:51.959421 Set Vref, RX VrefLevel [Byte0]: 41
3387 19:52:51.962530 [Byte1]: 41
3388 19:52:51.967107
3389 19:52:51.967186 Set Vref, RX VrefLevel [Byte0]: 42
3390 19:52:51.970631 [Byte1]: 42
3391 19:52:51.974801
3392 19:52:51.974882 Set Vref, RX VrefLevel [Byte0]: 43
3393 19:52:51.977842 [Byte1]: 43
3394 19:52:51.982589
3395 19:52:51.982670 Set Vref, RX VrefLevel [Byte0]: 44
3396 19:52:51.985920 [Byte1]: 44
3397 19:52:51.990940
3398 19:52:51.991067 Set Vref, RX VrefLevel [Byte0]: 45
3399 19:52:51.993943 [Byte1]: 45
3400 19:52:51.998600
3401 19:52:51.998679 Set Vref, RX VrefLevel [Byte0]: 46
3402 19:52:52.001534 [Byte1]: 46
3403 19:52:52.006318
3404 19:52:52.006400 Set Vref, RX VrefLevel [Byte0]: 47
3405 19:52:52.009681 [Byte1]: 47
3406 19:52:52.014299
3407 19:52:52.014380 Set Vref, RX VrefLevel [Byte0]: 48
3408 19:52:52.017355 [Byte1]: 48
3409 19:52:52.022070
3410 19:52:52.022153 Set Vref, RX VrefLevel [Byte0]: 49
3411 19:52:52.025566 [Byte1]: 49
3412 19:52:52.030146
3413 19:52:52.030228 Set Vref, RX VrefLevel [Byte0]: 50
3414 19:52:52.033654 [Byte1]: 50
3415 19:52:52.037668
3416 19:52:52.037764 Set Vref, RX VrefLevel [Byte0]: 51
3417 19:52:52.041327 [Byte1]: 51
3418 19:52:52.045642
3419 19:52:52.045724 Set Vref, RX VrefLevel [Byte0]: 52
3420 19:52:52.049246 [Byte1]: 52
3421 19:52:52.053577
3422 19:52:52.053658 Set Vref, RX VrefLevel [Byte0]: 53
3423 19:52:52.056876 [Byte1]: 53
3424 19:52:52.061392
3425 19:52:52.061474 Set Vref, RX VrefLevel [Byte0]: 54
3426 19:52:52.065059 [Byte1]: 54
3427 19:52:52.069622
3428 19:52:52.069740 Set Vref, RX VrefLevel [Byte0]: 55
3429 19:52:52.072449 [Byte1]: 55
3430 19:52:52.077149
3431 19:52:52.077239 Set Vref, RX VrefLevel [Byte0]: 56
3432 19:52:52.080823 [Byte1]: 56
3433 19:52:52.085556
3434 19:52:52.085638 Set Vref, RX VrefLevel [Byte0]: 57
3435 19:52:52.088601 [Byte1]: 57
3436 19:52:52.092810
3437 19:52:52.092891 Set Vref, RX VrefLevel [Byte0]: 58
3438 19:52:52.096460 [Byte1]: 58
3439 19:52:52.101040
3440 19:52:52.101123 Set Vref, RX VrefLevel [Byte0]: 59
3441 19:52:52.104164 [Byte1]: 59
3442 19:52:52.108724
3443 19:52:52.108805 Set Vref, RX VrefLevel [Byte0]: 60
3444 19:52:52.112061 [Byte1]: 60
3445 19:52:52.116578
3446 19:52:52.116659 Set Vref, RX VrefLevel [Byte0]: 61
3447 19:52:52.119983 [Byte1]: 61
3448 19:52:52.124549
3449 19:52:52.124630 Set Vref, RX VrefLevel [Byte0]: 62
3450 19:52:52.128011 [Byte1]: 62
3451 19:52:52.132276
3452 19:52:52.132372 Set Vref, RX VrefLevel [Byte0]: 63
3453 19:52:52.135574 [Byte1]: 63
3454 19:52:52.140244
3455 19:52:52.140321 Set Vref, RX VrefLevel [Byte0]: 64
3456 19:52:52.143730 [Byte1]: 64
3457 19:52:52.148524
3458 19:52:52.148598 Set Vref, RX VrefLevel [Byte0]: 65
3459 19:52:52.151581 [Byte1]: 65
3460 19:52:52.156258
3461 19:52:52.156352 Set Vref, RX VrefLevel [Byte0]: 66
3462 19:52:52.159677 [Byte1]: 66
3463 19:52:52.164161
3464 19:52:52.164241 Set Vref, RX VrefLevel [Byte0]: 67
3465 19:52:52.167347 [Byte1]: 67
3466 19:52:52.171616
3467 19:52:52.171697 Set Vref, RX VrefLevel [Byte0]: 68
3468 19:52:52.175072 [Byte1]: 68
3469 19:52:52.179654
3470 19:52:52.179749 Set Vref, RX VrefLevel [Byte0]: 69
3471 19:52:52.183231 [Byte1]: 69
3472 19:52:52.187823
3473 19:52:52.187904 Final RX Vref Byte 0 = 57 to rank0
3474 19:52:52.191099 Final RX Vref Byte 1 = 47 to rank0
3475 19:52:52.194050 Final RX Vref Byte 0 = 57 to rank1
3476 19:52:52.197518 Final RX Vref Byte 1 = 47 to rank1==
3477 19:52:52.201134 Dram Type= 6, Freq= 0, CH_1, rank 0
3478 19:52:52.207581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 19:52:52.207655 ==
3480 19:52:52.207718 DQS Delay:
3481 19:52:52.207776 DQS0 = 0, DQS1 = 0
3482 19:52:52.211099 DQM Delay:
3483 19:52:52.211194 DQM0 = 115, DQM1 = 104
3484 19:52:52.214147 DQ Delay:
3485 19:52:52.217590 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3486 19:52:52.221110 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3487 19:52:52.224288 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =100
3488 19:52:52.227691 DQ12 =110, DQ13 =110, DQ14 =112, DQ15 =110
3489 19:52:52.227791
3490 19:52:52.227880
3491 19:52:52.234675 [DQSOSCAuto] RK0, (LSB)MR18= 0xeef5, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3492 19:52:52.237673 CH1 RK0: MR19=303, MR18=EEF5
3493 19:52:52.244218 CH1_RK0: MR19=0x303, MR18=0xEEF5, DQSOSC=414, MR23=63, INC=38, DEC=25
3494 19:52:52.244322
3495 19:52:52.247583 ----->DramcWriteLeveling(PI) begin...
3496 19:52:52.247657 ==
3497 19:52:52.251200 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 19:52:52.254197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 19:52:52.254266 ==
3500 19:52:52.257751 Write leveling (Byte 0): 22 => 22
3501 19:52:52.261419 Write leveling (Byte 1): 26 => 26
3502 19:52:52.264307 DramcWriteLeveling(PI) end<-----
3503 19:52:52.264388
3504 19:52:52.264452 ==
3505 19:52:52.268133 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 19:52:52.274710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 19:52:52.274793 ==
3508 19:52:52.274856 [Gating] SW mode calibration
3509 19:52:52.284603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3510 19:52:52.287661 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3511 19:52:52.291226 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 19:52:52.297613 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 19:52:52.301185 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 19:52:52.304178 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 19:52:52.311452 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 19:52:52.314334 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 19:52:52.317862 0 15 24 | B1->B0 | 3333 2727 | 0 0 | (0 1) (0 0)
3518 19:52:52.324878 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
3519 19:52:52.327844 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 19:52:52.331308 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 19:52:52.337918 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 19:52:52.341199 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 19:52:52.344287 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 19:52:52.351055 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3525 19:52:52.354183 1 0 24 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3526 19:52:52.357471 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 19:52:52.364716 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 19:52:52.367576 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 19:52:52.370822 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 19:52:52.377375 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 19:52:52.380808 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 19:52:52.384070 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 19:52:52.387514 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3534 19:52:52.394098 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3535 19:52:52.397703 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 19:52:52.400789 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 19:52:52.407592 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 19:52:52.411143 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 19:52:52.414113 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 19:52:52.420607 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 19:52:52.424094 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 19:52:52.427651 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 19:52:52.434261 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 19:52:52.437367 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 19:52:52.440885 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 19:52:52.447865 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 19:52:52.450728 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 19:52:52.454115 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3549 19:52:52.460849 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3550 19:52:52.463886 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3551 19:52:52.467525 Total UI for P1: 0, mck2ui 16
3552 19:52:52.470511 best dqsien dly found for B0: ( 1, 3, 22)
3553 19:52:52.474271 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 19:52:52.477070 Total UI for P1: 0, mck2ui 16
3555 19:52:52.480859 best dqsien dly found for B1: ( 1, 3, 26)
3556 19:52:52.483931 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3557 19:52:52.487082 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3558 19:52:52.487163
3559 19:52:52.493456 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3560 19:52:52.496839 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3561 19:52:52.496920 [Gating] SW calibration Done
3562 19:52:52.500520 ==
3563 19:52:52.503724 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 19:52:52.506861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 19:52:52.506943 ==
3566 19:52:52.507006 RX Vref Scan: 0
3567 19:52:52.507065
3568 19:52:52.510265 RX Vref 0 -> 0, step: 1
3569 19:52:52.510363
3570 19:52:52.514153 RX Delay -40 -> 252, step: 8
3571 19:52:52.517603 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3572 19:52:52.520434 iDelay=200, Bit 1, Center 107 (40 ~ 175) 136
3573 19:52:52.523772 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3574 19:52:52.530113 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3575 19:52:52.533680 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3576 19:52:52.536652 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3577 19:52:52.540184 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3578 19:52:52.543809 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3579 19:52:52.549970 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3580 19:52:52.553366 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3581 19:52:52.557068 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3582 19:52:52.560074 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3583 19:52:52.563552 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3584 19:52:52.570166 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3585 19:52:52.573382 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3586 19:52:52.577053 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3587 19:52:52.577134 ==
3588 19:52:52.580090 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 19:52:52.583568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 19:52:52.583651 ==
3591 19:52:52.587256 DQS Delay:
3592 19:52:52.587336 DQS0 = 0, DQS1 = 0
3593 19:52:52.590628 DQM Delay:
3594 19:52:52.590709 DQM0 = 110, DQM1 = 105
3595 19:52:52.590773 DQ Delay:
3596 19:52:52.593499 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3597 19:52:52.600262 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3598 19:52:52.603830 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3599 19:52:52.606683 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3600 19:52:52.606797
3601 19:52:52.606890
3602 19:52:52.606986 ==
3603 19:52:52.610173 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 19:52:52.613250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 19:52:52.613351 ==
3606 19:52:52.613448
3607 19:52:52.613538
3608 19:52:52.616347 TX Vref Scan disable
3609 19:52:52.619728 == TX Byte 0 ==
3610 19:52:52.623602 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3611 19:52:52.626561 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3612 19:52:52.629738 == TX Byte 1 ==
3613 19:52:52.633491 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3614 19:52:52.636423 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3615 19:52:52.636504 ==
3616 19:52:52.640094 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 19:52:52.643070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 19:52:52.643151 ==
3619 19:52:52.656368 TX Vref=22, minBit 3, minWin=25, winSum=419
3620 19:52:52.659961 TX Vref=24, minBit 9, minWin=25, winSum=424
3621 19:52:52.663287 TX Vref=26, minBit 13, minWin=26, winSum=431
3622 19:52:52.666501 TX Vref=28, minBit 9, minWin=25, winSum=428
3623 19:52:52.670108 TX Vref=30, minBit 0, minWin=26, winSum=427
3624 19:52:52.676518 TX Vref=32, minBit 0, minWin=25, winSum=422
3625 19:52:52.680193 [TxChooseVref] Worse bit 13, Min win 26, Win sum 431, Final Vref 26
3626 19:52:52.680274
3627 19:52:52.683613 Final TX Range 1 Vref 26
3628 19:52:52.683695
3629 19:52:52.683758 ==
3630 19:52:52.686272 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 19:52:52.689837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 19:52:52.689918 ==
3633 19:52:52.693199
3634 19:52:52.693279
3635 19:52:52.693342 TX Vref Scan disable
3636 19:52:52.696171 == TX Byte 0 ==
3637 19:52:52.699503 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3638 19:52:52.706614 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3639 19:52:52.706728 == TX Byte 1 ==
3640 19:52:52.709479 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3641 19:52:52.716510 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3642 19:52:52.716591
3643 19:52:52.716686 [DATLAT]
3644 19:52:52.716762 Freq=1200, CH1 RK1
3645 19:52:52.716821
3646 19:52:52.719587 DATLAT Default: 0xd
3647 19:52:52.719668 0, 0xFFFF, sum = 0
3648 19:52:52.722731 1, 0xFFFF, sum = 0
3649 19:52:52.726326 2, 0xFFFF, sum = 0
3650 19:52:52.726408 3, 0xFFFF, sum = 0
3651 19:52:52.729272 4, 0xFFFF, sum = 0
3652 19:52:52.729393 5, 0xFFFF, sum = 0
3653 19:52:52.732713 6, 0xFFFF, sum = 0
3654 19:52:52.732795 7, 0xFFFF, sum = 0
3655 19:52:52.736213 8, 0xFFFF, sum = 0
3656 19:52:52.736295 9, 0xFFFF, sum = 0
3657 19:52:52.739483 10, 0xFFFF, sum = 0
3658 19:52:52.739565 11, 0xFFFF, sum = 0
3659 19:52:52.742780 12, 0x0, sum = 1
3660 19:52:52.742861 13, 0x0, sum = 2
3661 19:52:52.745883 14, 0x0, sum = 3
3662 19:52:52.745964 15, 0x0, sum = 4
3663 19:52:52.749740 best_step = 13
3664 19:52:52.749819
3665 19:52:52.749883 ==
3666 19:52:52.752790 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 19:52:52.755888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 19:52:52.755969 ==
3669 19:52:52.756033 RX Vref Scan: 0
3670 19:52:52.756092
3671 19:52:52.759780 RX Vref 0 -> 0, step: 1
3672 19:52:52.759860
3673 19:52:52.763042 RX Delay -21 -> 252, step: 4
3674 19:52:52.766046 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3675 19:52:52.772662 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3676 19:52:52.776283 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3677 19:52:52.779302 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3678 19:52:52.782694 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3679 19:52:52.786255 iDelay=195, Bit 5, Center 118 (43 ~ 194) 152
3680 19:52:52.792615 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3681 19:52:52.796131 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3682 19:52:52.799209 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3683 19:52:52.802833 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3684 19:52:52.806411 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3685 19:52:52.812486 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3686 19:52:52.815939 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3687 19:52:52.819310 iDelay=195, Bit 13, Center 112 (43 ~ 182) 140
3688 19:52:52.822984 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3689 19:52:52.826241 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3690 19:52:52.829251 ==
3691 19:52:52.832712 Dram Type= 6, Freq= 0, CH_1, rank 1
3692 19:52:52.835644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3693 19:52:52.835758 ==
3694 19:52:52.835852 DQS Delay:
3695 19:52:52.839189 DQS0 = 0, DQS1 = 0
3696 19:52:52.839286 DQM Delay:
3697 19:52:52.842614 DQM0 = 111, DQM1 = 108
3698 19:52:52.842696 DQ Delay:
3699 19:52:52.845871 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =108
3700 19:52:52.849231 DQ4 =108, DQ5 =118, DQ6 =122, DQ7 =110
3701 19:52:52.852854 DQ8 =94, DQ9 =100, DQ10 =110, DQ11 =102
3702 19:52:52.855647 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =116
3703 19:52:52.855779
3704 19:52:52.855871
3705 19:52:52.865686 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3706 19:52:52.868750 CH1 RK1: MR19=304, MR18=FA0A
3707 19:52:52.872255 CH1_RK1: MR19=0x304, MR18=0xFA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3708 19:52:52.875592 [RxdqsGatingPostProcess] freq 1200
3709 19:52:52.882319 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3710 19:52:52.885957 best DQS0 dly(2T, 0.5T) = (0, 11)
3711 19:52:52.888977 best DQS1 dly(2T, 0.5T) = (0, 11)
3712 19:52:52.891997 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3713 19:52:52.895445 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3714 19:52:52.898902 best DQS0 dly(2T, 0.5T) = (0, 11)
3715 19:52:52.901920 best DQS1 dly(2T, 0.5T) = (0, 11)
3716 19:52:52.905668 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3717 19:52:52.909123 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3718 19:52:52.912470 Pre-setting of DQS Precalculation
3719 19:52:52.915268 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3720 19:52:52.922658 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3721 19:52:52.929090 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3722 19:52:52.929173
3723 19:52:52.929237
3724 19:52:52.932528 [Calibration Summary] 2400 Mbps
3725 19:52:52.935607 CH 0, Rank 0
3726 19:52:52.935689 SW Impedance : PASS
3727 19:52:52.938629 DUTY Scan : NO K
3728 19:52:52.942245 ZQ Calibration : PASS
3729 19:52:52.942326 Jitter Meter : NO K
3730 19:52:52.945187 CBT Training : PASS
3731 19:52:52.948741 Write leveling : PASS
3732 19:52:52.948822 RX DQS gating : PASS
3733 19:52:52.951906 RX DQ/DQS(RDDQC) : PASS
3734 19:52:52.955871 TX DQ/DQS : PASS
3735 19:52:52.955953 RX DATLAT : PASS
3736 19:52:52.958744 RX DQ/DQS(Engine): PASS
3737 19:52:52.961999 TX OE : NO K
3738 19:52:52.962080 All Pass.
3739 19:52:52.962144
3740 19:52:52.962203 CH 0, Rank 1
3741 19:52:52.965547 SW Impedance : PASS
3742 19:52:52.968652 DUTY Scan : NO K
3743 19:52:52.968732 ZQ Calibration : PASS
3744 19:52:52.972041 Jitter Meter : NO K
3745 19:52:52.972121 CBT Training : PASS
3746 19:52:52.975031 Write leveling : PASS
3747 19:52:52.978269 RX DQS gating : PASS
3748 19:52:52.978382 RX DQ/DQS(RDDQC) : PASS
3749 19:52:52.981814 TX DQ/DQS : PASS
3750 19:52:52.985360 RX DATLAT : PASS
3751 19:52:52.985441 RX DQ/DQS(Engine): PASS
3752 19:52:52.988683 TX OE : NO K
3753 19:52:52.988764 All Pass.
3754 19:52:52.988827
3755 19:52:52.991869 CH 1, Rank 0
3756 19:52:52.991949 SW Impedance : PASS
3757 19:52:52.994826 DUTY Scan : NO K
3758 19:52:52.998504 ZQ Calibration : PASS
3759 19:52:52.998585 Jitter Meter : NO K
3760 19:52:53.001791 CBT Training : PASS
3761 19:52:53.005280 Write leveling : PASS
3762 19:52:53.005361 RX DQS gating : PASS
3763 19:52:53.008477 RX DQ/DQS(RDDQC) : PASS
3764 19:52:53.011850 TX DQ/DQS : PASS
3765 19:52:53.011931 RX DATLAT : PASS
3766 19:52:53.015231 RX DQ/DQS(Engine): PASS
3767 19:52:53.018457 TX OE : NO K
3768 19:52:53.018539 All Pass.
3769 19:52:53.018603
3770 19:52:53.018662 CH 1, Rank 1
3771 19:52:53.022018 SW Impedance : PASS
3772 19:52:53.024787 DUTY Scan : NO K
3773 19:52:53.024867 ZQ Calibration : PASS
3774 19:52:53.028116 Jitter Meter : NO K
3775 19:52:53.028198 CBT Training : PASS
3776 19:52:53.031700 Write leveling : PASS
3777 19:52:53.034605 RX DQS gating : PASS
3778 19:52:53.034686 RX DQ/DQS(RDDQC) : PASS
3779 19:52:53.037925 TX DQ/DQS : PASS
3780 19:52:53.041399 RX DATLAT : PASS
3781 19:52:53.041479 RX DQ/DQS(Engine): PASS
3782 19:52:53.045075 TX OE : NO K
3783 19:52:53.045155 All Pass.
3784 19:52:53.045235
3785 19:52:53.048165 DramC Write-DBI off
3786 19:52:53.051789 PER_BANK_REFRESH: Hybrid Mode
3787 19:52:53.051870 TX_TRACKING: ON
3788 19:52:53.061230 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3789 19:52:53.065029 [FAST_K] Save calibration result to emmc
3790 19:52:53.068188 dramc_set_vcore_voltage set vcore to 650000
3791 19:52:53.071227 Read voltage for 600, 5
3792 19:52:53.071334 Vio18 = 0
3793 19:52:53.071455 Vcore = 650000
3794 19:52:53.074828 Vdram = 0
3795 19:52:53.074910 Vddq = 0
3796 19:52:53.074975 Vmddr = 0
3797 19:52:53.081126 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3798 19:52:53.084849 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3799 19:52:53.087975 MEM_TYPE=3, freq_sel=19
3800 19:52:53.091302 sv_algorithm_assistance_LP4_1600
3801 19:52:53.094613 ============ PULL DRAM RESETB DOWN ============
3802 19:52:53.097942 ========== PULL DRAM RESETB DOWN end =========
3803 19:52:53.104413 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3804 19:52:53.107866 ===================================
3805 19:52:53.111153 LPDDR4 DRAM CONFIGURATION
3806 19:52:53.114432 ===================================
3807 19:52:53.114513 EX_ROW_EN[0] = 0x0
3808 19:52:53.117657 EX_ROW_EN[1] = 0x0
3809 19:52:53.117737 LP4Y_EN = 0x0
3810 19:52:53.121151 WORK_FSP = 0x0
3811 19:52:53.121231 WL = 0x2
3812 19:52:53.124662 RL = 0x2
3813 19:52:53.124752 BL = 0x2
3814 19:52:53.127663 RPST = 0x0
3815 19:52:53.127743 RD_PRE = 0x0
3816 19:52:53.131151 WR_PRE = 0x1
3817 19:52:53.131261 WR_PST = 0x0
3818 19:52:53.134428 DBI_WR = 0x0
3819 19:52:53.134508 DBI_RD = 0x0
3820 19:52:53.137503 OTF = 0x1
3821 19:52:53.140833 ===================================
3822 19:52:53.144557 ===================================
3823 19:52:53.144671 ANA top config
3824 19:52:53.147352 ===================================
3825 19:52:53.151122 DLL_ASYNC_EN = 0
3826 19:52:53.154233 ALL_SLAVE_EN = 1
3827 19:52:53.157707 NEW_RANK_MODE = 1
3828 19:52:53.157790 DLL_IDLE_MODE = 1
3829 19:52:53.160787 LP45_APHY_COMB_EN = 1
3830 19:52:53.164449 TX_ODT_DIS = 1
3831 19:52:53.167619 NEW_8X_MODE = 1
3832 19:52:53.170873 ===================================
3833 19:52:53.174017 ===================================
3834 19:52:53.177445 data_rate = 1200
3835 19:52:53.180927 CKR = 1
3836 19:52:53.181008 DQ_P2S_RATIO = 8
3837 19:52:53.184076 ===================================
3838 19:52:53.187567 CA_P2S_RATIO = 8
3839 19:52:53.190560 DQ_CA_OPEN = 0
3840 19:52:53.194440 DQ_SEMI_OPEN = 0
3841 19:52:53.197261 CA_SEMI_OPEN = 0
3842 19:52:53.197341 CA_FULL_RATE = 0
3843 19:52:53.200547 DQ_CKDIV4_EN = 1
3844 19:52:53.204082 CA_CKDIV4_EN = 1
3845 19:52:53.207613 CA_PREDIV_EN = 0
3846 19:52:53.210726 PH8_DLY = 0
3847 19:52:53.213909 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3848 19:52:53.213991 DQ_AAMCK_DIV = 4
3849 19:52:53.216911 CA_AAMCK_DIV = 4
3850 19:52:53.220333 CA_ADMCK_DIV = 4
3851 19:52:53.223673 DQ_TRACK_CA_EN = 0
3852 19:52:53.227040 CA_PICK = 600
3853 19:52:53.230513 CA_MCKIO = 600
3854 19:52:53.233848 MCKIO_SEMI = 0
3855 19:52:53.233929 PLL_FREQ = 2288
3856 19:52:53.237357 DQ_UI_PI_RATIO = 32
3857 19:52:53.240366 CA_UI_PI_RATIO = 0
3858 19:52:53.243906 ===================================
3859 19:52:53.246858 ===================================
3860 19:52:53.250457 memory_type:LPDDR4
3861 19:52:53.253929 GP_NUM : 10
3862 19:52:53.254010 SRAM_EN : 1
3863 19:52:53.257071 MD32_EN : 0
3864 19:52:53.260683 ===================================
3865 19:52:53.260764 [ANA_INIT] >>>>>>>>>>>>>>
3866 19:52:53.263685 <<<<<< [CONFIGURE PHASE]: ANA_TX
3867 19:52:53.267283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3868 19:52:53.270365 ===================================
3869 19:52:53.273723 data_rate = 1200,PCW = 0X5800
3870 19:52:53.277046 ===================================
3871 19:52:53.280543 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3872 19:52:53.286899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 19:52:53.290498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3874 19:52:53.296904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3875 19:52:53.300578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3876 19:52:53.303338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3877 19:52:53.307003 [ANA_INIT] flow start
3878 19:52:53.307084 [ANA_INIT] PLL >>>>>>>>
3879 19:52:53.309904 [ANA_INIT] PLL <<<<<<<<
3880 19:52:53.313583 [ANA_INIT] MIDPI >>>>>>>>
3881 19:52:53.313664 [ANA_INIT] MIDPI <<<<<<<<
3882 19:52:53.317076 [ANA_INIT] DLL >>>>>>>>
3883 19:52:53.320126 [ANA_INIT] flow end
3884 19:52:53.323733 ============ LP4 DIFF to SE enter ============
3885 19:52:53.326683 ============ LP4 DIFF to SE exit ============
3886 19:52:53.330014 [ANA_INIT] <<<<<<<<<<<<<
3887 19:52:53.333209 [Flow] Enable top DCM control >>>>>
3888 19:52:53.336965 [Flow] Enable top DCM control <<<<<
3889 19:52:53.340181 Enable DLL master slave shuffle
3890 19:52:53.343375 ==============================================================
3891 19:52:53.346532 Gating Mode config
3892 19:52:53.353604 ==============================================================
3893 19:52:53.353734 Config description:
3894 19:52:53.363651 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3895 19:52:53.370077 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3896 19:52:53.373122 SELPH_MODE 0: By rank 1: By Phase
3897 19:52:53.380206 ==============================================================
3898 19:52:53.383405 GAT_TRACK_EN = 1
3899 19:52:53.386809 RX_GATING_MODE = 2
3900 19:52:53.390258 RX_GATING_TRACK_MODE = 2
3901 19:52:53.393052 SELPH_MODE = 1
3902 19:52:53.396536 PICG_EARLY_EN = 1
3903 19:52:53.399840 VALID_LAT_VALUE = 1
3904 19:52:53.403253 ==============================================================
3905 19:52:53.406986 Enter into Gating configuration >>>>
3906 19:52:53.410308 Exit from Gating configuration <<<<
3907 19:52:53.413174 Enter into DVFS_PRE_config >>>>>
3908 19:52:53.423461 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3909 19:52:53.426415 Exit from DVFS_PRE_config <<<<<
3910 19:52:53.429835 Enter into PICG configuration >>>>
3911 19:52:53.433347 Exit from PICG configuration <<<<
3912 19:52:53.436177 [RX_INPUT] configuration >>>>>
3913 19:52:53.439900 [RX_INPUT] configuration <<<<<
3914 19:52:53.446149 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3915 19:52:53.449838 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3916 19:52:53.456117 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3917 19:52:53.463042 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3918 19:52:53.469615 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3919 19:52:53.476222 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3920 19:52:53.479316 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3921 19:52:53.482804 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3922 19:52:53.486213 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3923 19:52:53.492626 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3924 19:52:53.496124 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3925 19:52:53.499612 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3926 19:52:53.502594 ===================================
3927 19:52:53.506293 LPDDR4 DRAM CONFIGURATION
3928 19:52:53.509312 ===================================
3929 19:52:53.509393 EX_ROW_EN[0] = 0x0
3930 19:52:53.512688 EX_ROW_EN[1] = 0x0
3931 19:52:53.516198 LP4Y_EN = 0x0
3932 19:52:53.516278 WORK_FSP = 0x0
3933 19:52:53.519192 WL = 0x2
3934 19:52:53.519273 RL = 0x2
3935 19:52:53.522737 BL = 0x2
3936 19:52:53.522817 RPST = 0x0
3937 19:52:53.525751 RD_PRE = 0x0
3938 19:52:53.525832 WR_PRE = 0x1
3939 19:52:53.529160 WR_PST = 0x0
3940 19:52:53.529240 DBI_WR = 0x0
3941 19:52:53.532314 DBI_RD = 0x0
3942 19:52:53.532394 OTF = 0x1
3943 19:52:53.535792 ===================================
3944 19:52:53.539341 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3945 19:52:53.545579 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3946 19:52:53.549256 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3947 19:52:53.552081 ===================================
3948 19:52:53.555514 LPDDR4 DRAM CONFIGURATION
3949 19:52:53.559369 ===================================
3950 19:52:53.559490 EX_ROW_EN[0] = 0x10
3951 19:52:53.562120 EX_ROW_EN[1] = 0x0
3952 19:52:53.565663 LP4Y_EN = 0x0
3953 19:52:53.565743 WORK_FSP = 0x0
3954 19:52:53.568951 WL = 0x2
3955 19:52:53.569031 RL = 0x2
3956 19:52:53.572456 BL = 0x2
3957 19:52:53.572536 RPST = 0x0
3958 19:52:53.575534 RD_PRE = 0x0
3959 19:52:53.575615 WR_PRE = 0x1
3960 19:52:53.578836 WR_PST = 0x0
3961 19:52:53.578917 DBI_WR = 0x0
3962 19:52:53.582541 DBI_RD = 0x0
3963 19:52:53.582621 OTF = 0x1
3964 19:52:53.585893 ===================================
3965 19:52:53.592163 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3966 19:52:53.596356 nWR fixed to 30
3967 19:52:53.599779 [ModeRegInit_LP4] CH0 RK0
3968 19:52:53.599860 [ModeRegInit_LP4] CH0 RK1
3969 19:52:53.603112 [ModeRegInit_LP4] CH1 RK0
3970 19:52:53.606207 [ModeRegInit_LP4] CH1 RK1
3971 19:52:53.606288 match AC timing 17
3972 19:52:53.612615 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3973 19:52:53.616111 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3974 19:52:53.619749 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3975 19:52:53.626403 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3976 19:52:53.629329 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3977 19:52:53.629410 ==
3978 19:52:53.632593 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 19:52:53.636226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 19:52:53.636307 ==
3981 19:52:53.642753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 19:52:53.649335 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3983 19:52:53.652714 [CA 0] Center 37 (7~67) winsize 61
3984 19:52:53.656058 [CA 1] Center 37 (7~67) winsize 61
3985 19:52:53.659063 [CA 2] Center 35 (5~65) winsize 61
3986 19:52:53.662544 [CA 3] Center 35 (5~65) winsize 61
3987 19:52:53.666019 [CA 4] Center 34 (4~65) winsize 62
3988 19:52:53.669142 [CA 5] Center 33 (3~64) winsize 62
3989 19:52:53.669223
3990 19:52:53.672578 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3991 19:52:53.672659
3992 19:52:53.675627 [CATrainingPosCal] consider 1 rank data
3993 19:52:53.679008 u2DelayCellTimex100 = 270/100 ps
3994 19:52:53.682359 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3995 19:52:53.685613 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3996 19:52:53.689185 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3997 19:52:53.692495 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3998 19:52:53.695798 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3999 19:52:53.702308 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 19:52:53.702389
4001 19:52:53.705670 CA PerBit enable=1, Macro0, CA PI delay=33
4002 19:52:53.705751
4003 19:52:53.709174 [CBTSetCACLKResult] CA Dly = 33
4004 19:52:53.709255 CS Dly: 5 (0~36)
4005 19:52:53.709319 ==
4006 19:52:53.712680 Dram Type= 6, Freq= 0, CH_0, rank 1
4007 19:52:53.715653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 19:52:53.719490 ==
4009 19:52:53.722184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4010 19:52:53.728936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4011 19:52:53.732166 [CA 0] Center 37 (7~67) winsize 61
4012 19:52:53.735600 [CA 1] Center 36 (6~67) winsize 62
4013 19:52:53.739118 [CA 2] Center 35 (5~65) winsize 61
4014 19:52:53.742203 [CA 3] Center 35 (5~65) winsize 61
4015 19:52:53.745572 [CA 4] Center 33 (3~64) winsize 62
4016 19:52:53.749174 [CA 5] Center 33 (3~64) winsize 62
4017 19:52:53.749255
4018 19:52:53.752086 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4019 19:52:53.752168
4020 19:52:53.755594 [CATrainingPosCal] consider 2 rank data
4021 19:52:53.758927 u2DelayCellTimex100 = 270/100 ps
4022 19:52:53.762294 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
4023 19:52:53.765494 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
4024 19:52:53.768587 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4025 19:52:53.775504 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
4026 19:52:53.778601 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4027 19:52:53.782010 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4028 19:52:53.782094
4029 19:52:53.785561 CA PerBit enable=1, Macro0, CA PI delay=33
4030 19:52:53.785642
4031 19:52:53.788721 [CBTSetCACLKResult] CA Dly = 33
4032 19:52:53.788802 CS Dly: 6 (0~38)
4033 19:52:53.788867
4034 19:52:53.792126 ----->DramcWriteLeveling(PI) begin...
4035 19:52:53.795647 ==
4036 19:52:53.795728 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 19:52:53.802025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 19:52:53.802107 ==
4039 19:52:53.805525 Write leveling (Byte 0): 32 => 32
4040 19:52:53.808674 Write leveling (Byte 1): 31 => 31
4041 19:52:53.812484 DramcWriteLeveling(PI) end<-----
4042 19:52:53.812565
4043 19:52:53.812629 ==
4044 19:52:53.815131 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 19:52:53.818936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 19:52:53.819018 ==
4047 19:52:53.821915 [Gating] SW mode calibration
4048 19:52:53.828788 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4049 19:52:53.832222 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4050 19:52:53.838447 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 19:52:53.841834 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 19:52:53.845048 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 19:52:53.852146 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4054 19:52:53.854886 0 9 16 | B1->B0 | 3030 2a2a | 1 0 | (1 0) (0 0)
4055 19:52:53.858467 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4056 19:52:53.865125 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 19:52:53.868319 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 19:52:53.871601 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 19:52:53.878196 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 19:52:53.881517 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 19:52:53.884487 0 10 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
4062 19:52:53.891711 0 10 16 | B1->B0 | 2f2f 3838 | 0 0 | (0 0) (0 0)
4063 19:52:53.894675 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 19:52:53.898107 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 19:52:53.904637 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 19:52:53.907996 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 19:52:53.911410 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 19:52:53.917462 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 19:52:53.921343 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 19:52:53.924208 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4071 19:52:53.930960 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 19:52:53.934697 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 19:52:53.938384 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 19:52:53.944448 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 19:52:53.947437 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 19:52:53.951143 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 19:52:53.957389 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 19:52:53.960995 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 19:52:53.964516 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 19:52:53.970445 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 19:52:53.974054 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 19:52:53.977233 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 19:52:53.983651 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 19:52:53.987364 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 19:52:53.990538 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4086 19:52:53.997284 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 19:52:53.997367 Total UI for P1: 0, mck2ui 16
4088 19:52:54.003715 best dqsien dly found for B0: ( 0, 13, 12)
4089 19:52:54.003799 Total UI for P1: 0, mck2ui 16
4090 19:52:54.010161 best dqsien dly found for B1: ( 0, 13, 14)
4091 19:52:54.013622 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4092 19:52:54.016762 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4093 19:52:54.016844
4094 19:52:54.020154 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4095 19:52:54.023588 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4096 19:52:54.026829 [Gating] SW calibration Done
4097 19:52:54.026910 ==
4098 19:52:54.030504 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 19:52:54.033258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 19:52:54.033354 ==
4101 19:52:54.036857 RX Vref Scan: 0
4102 19:52:54.036940
4103 19:52:54.037005 RX Vref 0 -> 0, step: 1
4104 19:52:54.037066
4105 19:52:54.039888 RX Delay -230 -> 252, step: 16
4106 19:52:54.046574 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4107 19:52:54.050471 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4108 19:52:54.053328 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4109 19:52:54.056532 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4110 19:52:54.059965 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4111 19:52:54.066295 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4112 19:52:54.069760 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4113 19:52:54.073067 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4114 19:52:54.076728 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4115 19:52:54.083305 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4116 19:52:54.086843 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4117 19:52:54.089654 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4118 19:52:54.092981 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4119 19:52:54.099536 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4120 19:52:54.103236 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4121 19:52:54.106628 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4122 19:52:54.106712 ==
4123 19:52:54.109458 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 19:52:54.113019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 19:52:54.116003 ==
4126 19:52:54.116086 DQS Delay:
4127 19:52:54.116151 DQS0 = 0, DQS1 = 0
4128 19:52:54.120139 DQM Delay:
4129 19:52:54.120222 DQM0 = 37, DQM1 = 29
4130 19:52:54.122938 DQ Delay:
4131 19:52:54.123021 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4132 19:52:54.126095 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4133 19:52:54.129551 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =25
4134 19:52:54.132927 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4135 19:52:54.133010
4136 19:52:54.136154
4137 19:52:54.136237 ==
4138 19:52:54.139398 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 19:52:54.143031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 19:52:54.143122 ==
4141 19:52:54.143222
4142 19:52:54.143314
4143 19:52:54.145849 TX Vref Scan disable
4144 19:52:54.145932 == TX Byte 0 ==
4145 19:52:54.152779 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4146 19:52:54.155899 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4147 19:52:54.155983 == TX Byte 1 ==
4148 19:52:54.162816 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4149 19:52:54.165894 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4150 19:52:54.165986 ==
4151 19:52:54.169693 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 19:52:54.172584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 19:52:54.172668 ==
4154 19:52:54.172734
4155 19:52:54.172795
4156 19:52:54.176225 TX Vref Scan disable
4157 19:52:54.179196 == TX Byte 0 ==
4158 19:52:54.182411 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4159 19:52:54.185878 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4160 19:52:54.189358 == TX Byte 1 ==
4161 19:52:54.192398 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4162 19:52:54.195938 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4163 19:52:54.196022
4164 19:52:54.199396 [DATLAT]
4165 19:52:54.199479 Freq=600, CH0 RK0
4166 19:52:54.199545
4167 19:52:54.202733 DATLAT Default: 0x9
4168 19:52:54.202816 0, 0xFFFF, sum = 0
4169 19:52:54.205864 1, 0xFFFF, sum = 0
4170 19:52:54.205948 2, 0xFFFF, sum = 0
4171 19:52:54.208875 3, 0xFFFF, sum = 0
4172 19:52:54.208959 4, 0xFFFF, sum = 0
4173 19:52:54.212833 5, 0xFFFF, sum = 0
4174 19:52:54.212917 6, 0xFFFF, sum = 0
4175 19:52:54.215802 7, 0xFFFF, sum = 0
4176 19:52:54.215887 8, 0x0, sum = 1
4177 19:52:54.218952 9, 0x0, sum = 2
4178 19:52:54.219037 10, 0x0, sum = 3
4179 19:52:54.222829 11, 0x0, sum = 4
4180 19:52:54.222914 best_step = 9
4181 19:52:54.222979
4182 19:52:54.223041 ==
4183 19:52:54.225852 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 19:52:54.232204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 19:52:54.232287 ==
4186 19:52:54.232353 RX Vref Scan: 1
4187 19:52:54.232413
4188 19:52:54.235899 RX Vref 0 -> 0, step: 1
4189 19:52:54.235982
4190 19:52:54.239099 RX Delay -195 -> 252, step: 8
4191 19:52:54.239182
4192 19:52:54.242657 Set Vref, RX VrefLevel [Byte0]: 61
4193 19:52:54.245517 [Byte1]: 53
4194 19:52:54.245600
4195 19:52:54.249037 Final RX Vref Byte 0 = 61 to rank0
4196 19:52:54.252758 Final RX Vref Byte 1 = 53 to rank0
4197 19:52:54.255508 Final RX Vref Byte 0 = 61 to rank1
4198 19:52:54.258968 Final RX Vref Byte 1 = 53 to rank1==
4199 19:52:54.262050 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 19:52:54.265643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 19:52:54.265727 ==
4202 19:52:54.268674 DQS Delay:
4203 19:52:54.268757 DQS0 = 0, DQS1 = 0
4204 19:52:54.268822 DQM Delay:
4205 19:52:54.271992 DQM0 = 34, DQM1 = 29
4206 19:52:54.272075 DQ Delay:
4207 19:52:54.275190 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4208 19:52:54.278686 DQ4 =36, DQ5 =20, DQ6 =40, DQ7 =44
4209 19:52:54.282011 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4210 19:52:54.285145 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4211 19:52:54.285227
4212 19:52:54.285291
4213 19:52:54.295255 [DQSOSCAuto] RK0, (LSB)MR18= 0x4040, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4214 19:52:54.298693 CH0 RK0: MR19=808, MR18=4040
4215 19:52:54.301684 CH0_RK0: MR19=0x808, MR18=0x4040, DQSOSC=397, MR23=63, INC=166, DEC=110
4216 19:52:54.301796
4217 19:52:54.305016 ----->DramcWriteLeveling(PI) begin...
4218 19:52:54.308670 ==
4219 19:52:54.311987 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 19:52:54.315232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 19:52:54.315349 ==
4222 19:52:54.318568 Write leveling (Byte 0): 33 => 33
4223 19:52:54.322175 Write leveling (Byte 1): 33 => 33
4224 19:52:54.325123 DramcWriteLeveling(PI) end<-----
4225 19:52:54.325205
4226 19:52:54.325269 ==
4227 19:52:54.328785 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 19:52:54.331625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 19:52:54.331721 ==
4230 19:52:54.335106 [Gating] SW mode calibration
4231 19:52:54.341588 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4232 19:52:54.348628 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4233 19:52:54.352032 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 19:52:54.355150 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 19:52:54.362073 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4236 19:52:54.365036 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
4237 19:52:54.368651 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
4238 19:52:54.375100 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 19:52:54.378080 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 19:52:54.381788 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 19:52:54.385119 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 19:52:54.391515 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 19:52:54.394587 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 19:52:54.397928 0 10 12 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
4245 19:52:54.404959 0 10 16 | B1->B0 | 3535 4242 | 0 0 | (0 0) (0 0)
4246 19:52:54.408032 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 19:52:54.411332 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 19:52:54.417738 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 19:52:54.421085 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 19:52:54.424732 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 19:52:54.431360 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 19:52:54.434766 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4253 19:52:54.437843 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 19:52:54.444922 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 19:52:54.448150 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 19:52:54.450987 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 19:52:54.457740 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 19:52:54.461312 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 19:52:54.464706 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 19:52:54.471337 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 19:52:54.474897 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 19:52:54.477742 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 19:52:54.484318 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 19:52:54.487769 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 19:52:54.491479 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 19:52:54.497760 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 19:52:54.501261 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 19:52:54.504465 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 19:52:54.511060 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 19:52:54.511155 Total UI for P1: 0, mck2ui 16
4271 19:52:54.514354 best dqsien dly found for B0: ( 0, 13, 14)
4272 19:52:54.517712 Total UI for P1: 0, mck2ui 16
4273 19:52:54.521183 best dqsien dly found for B1: ( 0, 13, 14)
4274 19:52:54.527702 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4275 19:52:54.530911 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4276 19:52:54.530994
4277 19:52:54.534047 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4278 19:52:54.537538 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4279 19:52:54.540963 [Gating] SW calibration Done
4280 19:52:54.541074 ==
4281 19:52:54.544018 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 19:52:54.547356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 19:52:54.547474 ==
4284 19:52:54.551100 RX Vref Scan: 0
4285 19:52:54.551216
4286 19:52:54.551318 RX Vref 0 -> 0, step: 1
4287 19:52:54.551417
4288 19:52:54.554775 RX Delay -230 -> 252, step: 16
4289 19:52:54.557498 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4290 19:52:54.564102 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4291 19:52:54.567544 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4292 19:52:54.571045 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4293 19:52:54.573965 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4294 19:52:54.577482 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4295 19:52:54.584203 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4296 19:52:54.587656 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4297 19:52:54.590645 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4298 19:52:54.594145 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4299 19:52:54.600832 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4300 19:52:54.604274 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4301 19:52:54.607371 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4302 19:52:54.610812 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4303 19:52:54.617036 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4304 19:52:54.620925 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4305 19:52:54.621031 ==
4306 19:52:54.624072 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 19:52:54.627102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 19:52:54.627205 ==
4309 19:52:54.630413 DQS Delay:
4310 19:52:54.630516 DQS0 = 0, DQS1 = 0
4311 19:52:54.630620 DQM Delay:
4312 19:52:54.633700 DQM0 = 35, DQM1 = 28
4313 19:52:54.633811 DQ Delay:
4314 19:52:54.637259 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4315 19:52:54.640575 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4316 19:52:54.644054 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4317 19:52:54.647314 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4318 19:52:54.647433
4319 19:52:54.647529
4320 19:52:54.647619 ==
4321 19:52:54.650434 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 19:52:54.656918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 19:52:54.657029 ==
4324 19:52:54.657124
4325 19:52:54.657215
4326 19:52:54.657306 TX Vref Scan disable
4327 19:52:54.660451 == TX Byte 0 ==
4328 19:52:54.664185 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4329 19:52:54.670540 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4330 19:52:54.670662 == TX Byte 1 ==
4331 19:52:54.673942 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4332 19:52:54.680461 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4333 19:52:54.680586 ==
4334 19:52:54.684103 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 19:52:54.687050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 19:52:54.687153 ==
4337 19:52:54.687249
4338 19:52:54.687338
4339 19:52:54.690394 TX Vref Scan disable
4340 19:52:54.694037 == TX Byte 0 ==
4341 19:52:54.697403 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4342 19:52:54.700582 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4343 19:52:54.703565 == TX Byte 1 ==
4344 19:52:54.707119 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4345 19:52:54.710699 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4346 19:52:54.710808
4347 19:52:54.710875 [DATLAT]
4348 19:52:54.713761 Freq=600, CH0 RK1
4349 19:52:54.713860
4350 19:52:54.717403 DATLAT Default: 0x9
4351 19:52:54.717505 0, 0xFFFF, sum = 0
4352 19:52:54.720375 1, 0xFFFF, sum = 0
4353 19:52:54.720475 2, 0xFFFF, sum = 0
4354 19:52:54.723538 3, 0xFFFF, sum = 0
4355 19:52:54.723609 4, 0xFFFF, sum = 0
4356 19:52:54.726939 5, 0xFFFF, sum = 0
4357 19:52:54.727012 6, 0xFFFF, sum = 0
4358 19:52:54.729877 7, 0xFFFF, sum = 0
4359 19:52:54.729952 8, 0x0, sum = 1
4360 19:52:54.733320 9, 0x0, sum = 2
4361 19:52:54.733395 10, 0x0, sum = 3
4362 19:52:54.736795 11, 0x0, sum = 4
4363 19:52:54.736868 best_step = 9
4364 19:52:54.736931
4365 19:52:54.736994 ==
4366 19:52:54.739865 Dram Type= 6, Freq= 0, CH_0, rank 1
4367 19:52:54.743090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 19:52:54.743206 ==
4369 19:52:54.746367 RX Vref Scan: 0
4370 19:52:54.746468
4371 19:52:54.749914 RX Vref 0 -> 0, step: 1
4372 19:52:54.750000
4373 19:52:54.750094 RX Delay -195 -> 252, step: 8
4374 19:52:54.757688 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4375 19:52:54.760956 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4376 19:52:54.764527 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4377 19:52:54.767737 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4378 19:52:54.774408 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4379 19:52:54.777580 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4380 19:52:54.780907 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4381 19:52:54.784665 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4382 19:52:54.788191 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4383 19:52:54.794052 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4384 19:52:54.798022 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4385 19:52:54.801146 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4386 19:52:54.804530 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4387 19:52:54.811141 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4388 19:52:54.814116 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4389 19:52:54.817733 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4390 19:52:54.817815 ==
4391 19:52:54.820624 Dram Type= 6, Freq= 0, CH_0, rank 1
4392 19:52:54.827228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 19:52:54.827337 ==
4394 19:52:54.827446 DQS Delay:
4395 19:52:54.827510 DQS0 = 0, DQS1 = 0
4396 19:52:54.830973 DQM Delay:
4397 19:52:54.831084 DQM0 = 33, DQM1 = 28
4398 19:52:54.834539 DQ Delay:
4399 19:52:54.837435 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4400 19:52:54.837536 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4401 19:52:54.840701 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4402 19:52:54.847678 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4403 19:52:54.847782
4404 19:52:54.847874
4405 19:52:54.854138 [DQSOSCAuto] RK1, (LSB)MR18= 0x7342, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4406 19:52:54.857048 CH0 RK1: MR19=808, MR18=7342
4407 19:52:54.863761 CH0_RK1: MR19=0x808, MR18=0x7342, DQSOSC=388, MR23=63, INC=174, DEC=116
4408 19:52:54.867345 [RxdqsGatingPostProcess] freq 600
4409 19:52:54.870511 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4410 19:52:54.873694 Pre-setting of DQS Precalculation
4411 19:52:54.880399 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4412 19:52:54.880478 ==
4413 19:52:54.884132 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 19:52:54.887286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 19:52:54.887409 ==
4416 19:52:54.893895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4417 19:52:54.897334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4418 19:52:54.901471 [CA 0] Center 35 (5~66) winsize 62
4419 19:52:54.904840 [CA 1] Center 36 (6~66) winsize 61
4420 19:52:54.908010 [CA 2] Center 34 (4~65) winsize 62
4421 19:52:54.911402 [CA 3] Center 34 (4~65) winsize 62
4422 19:52:54.914832 [CA 4] Center 34 (4~65) winsize 62
4423 19:52:54.918579 [CA 5] Center 33 (3~64) winsize 62
4424 19:52:54.918652
4425 19:52:54.921287 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4426 19:52:54.921358
4427 19:52:54.924525 [CATrainingPosCal] consider 1 rank data
4428 19:52:54.927923 u2DelayCellTimex100 = 270/100 ps
4429 19:52:54.931699 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4430 19:52:54.938304 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4431 19:52:54.941303 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4432 19:52:54.944819 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 19:52:54.948178 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 19:52:54.951162 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4435 19:52:54.951264
4436 19:52:54.954827 CA PerBit enable=1, Macro0, CA PI delay=33
4437 19:52:54.954926
4438 19:52:54.958122 [CBTSetCACLKResult] CA Dly = 33
4439 19:52:54.958224 CS Dly: 5 (0~36)
4440 19:52:54.960995 ==
4441 19:52:54.961093 Dram Type= 6, Freq= 0, CH_1, rank 1
4442 19:52:54.968160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 19:52:54.968250 ==
4444 19:52:54.971455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4445 19:52:54.977737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4446 19:52:54.981838 [CA 0] Center 36 (6~66) winsize 61
4447 19:52:54.985086 [CA 1] Center 36 (5~67) winsize 63
4448 19:52:54.988283 [CA 2] Center 34 (4~65) winsize 62
4449 19:52:54.991290 [CA 3] Center 34 (3~65) winsize 63
4450 19:52:54.994588 [CA 4] Center 34 (4~65) winsize 62
4451 19:52:54.998197 [CA 5] Center 33 (3~64) winsize 62
4452 19:52:54.998269
4453 19:52:55.001236 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4454 19:52:55.001337
4455 19:52:55.004603 [CATrainingPosCal] consider 2 rank data
4456 19:52:55.007770 u2DelayCellTimex100 = 270/100 ps
4457 19:52:55.011342 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4458 19:52:55.017964 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4459 19:52:55.021490 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4460 19:52:55.024942 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 19:52:55.027817 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 19:52:55.031313 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4463 19:52:55.031412
4464 19:52:55.034493 CA PerBit enable=1, Macro0, CA PI delay=33
4465 19:52:55.034591
4466 19:52:55.037948 [CBTSetCACLKResult] CA Dly = 33
4467 19:52:55.038044 CS Dly: 5 (0~37)
4468 19:52:55.040999
4469 19:52:55.044538 ----->DramcWriteLeveling(PI) begin...
4470 19:52:55.044609 ==
4471 19:52:55.047902 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 19:52:55.051071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 19:52:55.051186 ==
4474 19:52:55.054626 Write leveling (Byte 0): 30 => 30
4475 19:52:55.057649 Write leveling (Byte 1): 31 => 31
4476 19:52:55.061067 DramcWriteLeveling(PI) end<-----
4477 19:52:55.061205
4478 19:52:55.061296 ==
4479 19:52:55.064427 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 19:52:55.067668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 19:52:55.067748 ==
4482 19:52:55.071228 [Gating] SW mode calibration
4483 19:52:55.077728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4484 19:52:55.084506 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4485 19:52:55.087795 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4486 19:52:55.090930 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 19:52:55.098125 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 19:52:55.100886 0 9 12 | B1->B0 | 3333 3434 | 1 0 | (0 1) (0 1)
4489 19:52:55.104574 0 9 16 | B1->B0 | 2323 2626 | 0 1 | (1 0) (1 0)
4490 19:52:55.107939 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 19:52:55.114056 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 19:52:55.117455 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 19:52:55.120769 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 19:52:55.127289 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 19:52:55.130794 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 19:52:55.134030 0 10 12 | B1->B0 | 2d2d 3131 | 0 0 | (0 0) (0 0)
4497 19:52:55.141203 0 10 16 | B1->B0 | 3f3f 3f3f | 1 1 | (0 0) (0 0)
4498 19:52:55.144230 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 19:52:55.147582 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 19:52:55.154213 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 19:52:55.157194 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 19:52:55.160890 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 19:52:55.167324 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 19:52:55.170568 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4505 19:52:55.173922 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 19:52:55.180740 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 19:52:55.183899 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 19:52:55.187206 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 19:52:55.193967 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 19:52:55.197289 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 19:52:55.200619 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 19:52:55.207176 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 19:52:55.210679 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 19:52:55.213586 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 19:52:55.220274 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 19:52:55.223726 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 19:52:55.227074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 19:52:55.233825 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 19:52:55.236967 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 19:52:55.240150 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 19:52:55.246692 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 19:52:55.246772 Total UI for P1: 0, mck2ui 16
4523 19:52:55.253432 best dqsien dly found for B0: ( 0, 13, 14)
4524 19:52:55.253513 Total UI for P1: 0, mck2ui 16
4525 19:52:55.260313 best dqsien dly found for B1: ( 0, 13, 14)
4526 19:52:55.263292 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4527 19:52:55.266905 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4528 19:52:55.267001
4529 19:52:55.269674 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4530 19:52:55.273236 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4531 19:52:55.276824 [Gating] SW calibration Done
4532 19:52:55.276905 ==
4533 19:52:55.279870 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 19:52:55.283240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 19:52:55.283333 ==
4536 19:52:55.286565 RX Vref Scan: 0
4537 19:52:55.286658
4538 19:52:55.286721 RX Vref 0 -> 0, step: 1
4539 19:52:55.286780
4540 19:52:55.289671 RX Delay -230 -> 252, step: 16
4541 19:52:55.296782 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4542 19:52:55.299517 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4543 19:52:55.303074 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4544 19:52:55.306263 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4545 19:52:55.309469 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4546 19:52:55.316470 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4547 19:52:55.320030 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4548 19:52:55.322969 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4549 19:52:55.326203 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4550 19:52:55.333004 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4551 19:52:55.336421 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4552 19:52:55.339705 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4553 19:52:55.342607 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4554 19:52:55.349410 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4555 19:52:55.352715 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4556 19:52:55.356212 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4557 19:52:55.356289 ==
4558 19:52:55.359225 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 19:52:55.362547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 19:52:55.362621 ==
4561 19:52:55.365681 DQS Delay:
4562 19:52:55.365768 DQS0 = 0, DQS1 = 0
4563 19:52:55.369057 DQM Delay:
4564 19:52:55.369137 DQM0 = 38, DQM1 = 28
4565 19:52:55.372389 DQ Delay:
4566 19:52:55.372495 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4567 19:52:55.376089 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4568 19:52:55.379028 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4569 19:52:55.382505 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4570 19:52:55.382581
4571 19:52:55.385697
4572 19:52:55.385771 ==
4573 19:52:55.389018 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 19:52:55.392581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 19:52:55.392653 ==
4576 19:52:55.392712
4577 19:52:55.392768
4578 19:52:55.396079 TX Vref Scan disable
4579 19:52:55.396166 == TX Byte 0 ==
4580 19:52:55.402590 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4581 19:52:55.406165 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4582 19:52:55.406267 == TX Byte 1 ==
4583 19:52:55.412335 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4584 19:52:55.415620 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4585 19:52:55.415706 ==
4586 19:52:55.419088 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 19:52:55.422673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 19:52:55.422774 ==
4589 19:52:55.422867
4590 19:52:55.422955
4591 19:52:55.425554 TX Vref Scan disable
4592 19:52:55.428939 == TX Byte 0 ==
4593 19:52:55.432538 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4594 19:52:55.435925 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4595 19:52:55.438895 == TX Byte 1 ==
4596 19:52:55.442573 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4597 19:52:55.445518 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4598 19:52:55.445596
4599 19:52:55.448941 [DATLAT]
4600 19:52:55.449011 Freq=600, CH1 RK0
4601 19:52:55.449078
4602 19:52:55.452069 DATLAT Default: 0x9
4603 19:52:55.452143 0, 0xFFFF, sum = 0
4604 19:52:55.455449 1, 0xFFFF, sum = 0
4605 19:52:55.455560 2, 0xFFFF, sum = 0
4606 19:52:55.459125 3, 0xFFFF, sum = 0
4607 19:52:55.459223 4, 0xFFFF, sum = 0
4608 19:52:55.462071 5, 0xFFFF, sum = 0
4609 19:52:55.462170 6, 0xFFFF, sum = 0
4610 19:52:55.465648 7, 0xFFFF, sum = 0
4611 19:52:55.465745 8, 0x0, sum = 1
4612 19:52:55.468653 9, 0x0, sum = 2
4613 19:52:55.468725 10, 0x0, sum = 3
4614 19:52:55.472543 11, 0x0, sum = 4
4615 19:52:55.472643 best_step = 9
4616 19:52:55.472735
4617 19:52:55.472821 ==
4618 19:52:55.475758 Dram Type= 6, Freq= 0, CH_1, rank 0
4619 19:52:55.478758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 19:52:55.481857 ==
4621 19:52:55.481961 RX Vref Scan: 1
4622 19:52:55.482056
4623 19:52:55.485369 RX Vref 0 -> 0, step: 1
4624 19:52:55.485443
4625 19:52:55.488848 RX Delay -195 -> 252, step: 8
4626 19:52:55.488943
4627 19:52:55.492216 Set Vref, RX VrefLevel [Byte0]: 57
4628 19:52:55.495158 [Byte1]: 47
4629 19:52:55.495255
4630 19:52:55.498476 Final RX Vref Byte 0 = 57 to rank0
4631 19:52:55.502003 Final RX Vref Byte 1 = 47 to rank0
4632 19:52:55.505521 Final RX Vref Byte 0 = 57 to rank1
4633 19:52:55.508556 Final RX Vref Byte 1 = 47 to rank1==
4634 19:52:55.511945 Dram Type= 6, Freq= 0, CH_1, rank 0
4635 19:52:55.515653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 19:52:55.515756 ==
4637 19:52:55.515846 DQS Delay:
4638 19:52:55.518818 DQS0 = 0, DQS1 = 0
4639 19:52:55.518913 DQM Delay:
4640 19:52:55.522168 DQM0 = 38, DQM1 = 29
4641 19:52:55.522242 DQ Delay:
4642 19:52:55.525677 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4643 19:52:55.528640 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4644 19:52:55.532179 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =24
4645 19:52:55.535522 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4646 19:52:55.535611
4647 19:52:55.535673
4648 19:52:55.545262 [DQSOSCAuto] RK0, (LSB)MR18= 0x2533, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4649 19:52:55.545341 CH1 RK0: MR19=808, MR18=2533
4650 19:52:55.552155 CH1_RK0: MR19=0x808, MR18=0x2533, DQSOSC=400, MR23=63, INC=163, DEC=109
4651 19:52:55.552234
4652 19:52:55.555661 ----->DramcWriteLeveling(PI) begin...
4653 19:52:55.555743 ==
4654 19:52:55.558661 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 19:52:55.565000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 19:52:55.565101 ==
4657 19:52:55.568412 Write leveling (Byte 0): 31 => 31
4658 19:52:55.572067 Write leveling (Byte 1): 28 => 28
4659 19:52:55.572137 DramcWriteLeveling(PI) end<-----
4660 19:52:55.572202
4661 19:52:55.575570 ==
4662 19:52:55.578640 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 19:52:55.581932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 19:52:55.582077 ==
4665 19:52:55.585525 [Gating] SW mode calibration
4666 19:52:55.592095 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4667 19:52:55.595534 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4668 19:52:55.601999 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4669 19:52:55.605254 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4670 19:52:55.608741 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4671 19:52:55.615034 0 9 12 | B1->B0 | 3333 2828 | 1 1 | (1 0) (0 0)
4672 19:52:55.618388 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4673 19:52:55.622011 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 19:52:55.628247 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 19:52:55.631666 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 19:52:55.634815 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 19:52:55.641541 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 19:52:55.645139 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4679 19:52:55.647967 0 10 12 | B1->B0 | 2f2f 3939 | 0 0 | (0 0) (0 0)
4680 19:52:55.654720 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4681 19:52:55.658123 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 19:52:55.661700 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 19:52:55.668171 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 19:52:55.671504 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 19:52:55.674830 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 19:52:55.681567 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 19:52:55.685075 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4688 19:52:55.687976 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 19:52:55.691450 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 19:52:55.697995 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 19:52:55.701565 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 19:52:55.704469 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 19:52:55.711150 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 19:52:55.715057 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 19:52:55.718017 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 19:52:55.724863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 19:52:55.727863 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 19:52:55.731309 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 19:52:55.738154 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 19:52:55.741152 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 19:52:55.744661 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 19:52:55.751212 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 19:52:55.754307 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4704 19:52:55.757662 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4705 19:52:55.760987 Total UI for P1: 0, mck2ui 16
4706 19:52:55.764337 best dqsien dly found for B0: ( 0, 13, 14)
4707 19:52:55.770916 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 19:52:55.771025 Total UI for P1: 0, mck2ui 16
4709 19:52:55.777553 best dqsien dly found for B1: ( 0, 13, 14)
4710 19:52:55.781049 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4711 19:52:55.784530 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4712 19:52:55.784640
4713 19:52:55.788091 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4714 19:52:55.791150 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4715 19:52:55.794787 [Gating] SW calibration Done
4716 19:52:55.794896 ==
4717 19:52:55.797715 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 19:52:55.801097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 19:52:55.801205 ==
4720 19:52:55.804215 RX Vref Scan: 0
4721 19:52:55.804287
4722 19:52:55.804369 RX Vref 0 -> 0, step: 1
4723 19:52:55.804430
4724 19:52:55.807485 RX Delay -230 -> 252, step: 16
4725 19:52:55.814205 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4726 19:52:55.817624 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4727 19:52:55.820639 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4728 19:52:55.823879 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4729 19:52:55.827300 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4730 19:52:55.834049 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4731 19:52:55.837568 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4732 19:52:55.841008 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4733 19:52:55.843579 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4734 19:52:55.850235 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4735 19:52:55.853619 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4736 19:52:55.857257 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4737 19:52:55.860709 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4738 19:52:55.866764 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4739 19:52:55.870155 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4740 19:52:55.873637 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4741 19:52:55.873744 ==
4742 19:52:55.876817 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 19:52:55.880428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 19:52:55.883535 ==
4745 19:52:55.883620 DQS Delay:
4746 19:52:55.883705 DQS0 = 0, DQS1 = 0
4747 19:52:55.886670 DQM Delay:
4748 19:52:55.886769 DQM0 = 35, DQM1 = 27
4749 19:52:55.890145 DQ Delay:
4750 19:52:55.890242 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4751 19:52:55.893900 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4752 19:52:55.896960 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4753 19:52:55.900343 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4754 19:52:55.900441
4755 19:52:55.903516
4756 19:52:55.903635 ==
4757 19:52:55.906862 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 19:52:55.910561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 19:52:55.910657 ==
4760 19:52:55.910744
4761 19:52:55.910839
4762 19:52:55.913538 TX Vref Scan disable
4763 19:52:55.913651 == TX Byte 0 ==
4764 19:52:55.920356 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4765 19:52:55.923246 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4766 19:52:55.923365 == TX Byte 1 ==
4767 19:52:55.930231 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4768 19:52:55.933753 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4769 19:52:55.933827 ==
4770 19:52:55.936808 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 19:52:55.939908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 19:52:55.939988 ==
4773 19:52:55.940050
4774 19:52:55.940109
4775 19:52:55.943320 TX Vref Scan disable
4776 19:52:55.946863 == TX Byte 0 ==
4777 19:52:55.949979 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4778 19:52:55.953171 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4779 19:52:55.956443 == TX Byte 1 ==
4780 19:52:55.959895 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4781 19:52:55.963342 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4782 19:52:55.963472
4783 19:52:55.966404 [DATLAT]
4784 19:52:55.966558 Freq=600, CH1 RK1
4785 19:52:55.966650
4786 19:52:55.969948 DATLAT Default: 0x9
4787 19:52:55.970083 0, 0xFFFF, sum = 0
4788 19:52:55.973326 1, 0xFFFF, sum = 0
4789 19:52:55.973425 2, 0xFFFF, sum = 0
4790 19:52:55.976568 3, 0xFFFF, sum = 0
4791 19:52:55.976661 4, 0xFFFF, sum = 0
4792 19:52:55.979761 5, 0xFFFF, sum = 0
4793 19:52:55.979871 6, 0xFFFF, sum = 0
4794 19:52:55.983193 7, 0xFFFF, sum = 0
4795 19:52:55.983333 8, 0x0, sum = 1
4796 19:52:55.986574 9, 0x0, sum = 2
4797 19:52:55.986672 10, 0x0, sum = 3
4798 19:52:55.990035 11, 0x0, sum = 4
4799 19:52:55.990137 best_step = 9
4800 19:52:55.990226
4801 19:52:55.990316 ==
4802 19:52:55.993212 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 19:52:55.999685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 19:52:55.999768 ==
4805 19:52:55.999837 RX Vref Scan: 0
4806 19:52:55.999896
4807 19:52:56.003166 RX Vref 0 -> 0, step: 1
4808 19:52:56.003273
4809 19:52:56.006234 RX Delay -195 -> 252, step: 8
4810 19:52:56.009971 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4811 19:52:56.016361 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4812 19:52:56.019436 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4813 19:52:56.023110 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4814 19:52:56.026551 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4815 19:52:56.029862 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4816 19:52:56.036174 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4817 19:52:56.039822 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4818 19:52:56.043325 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4819 19:52:56.046198 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4820 19:52:56.052750 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4821 19:52:56.055978 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4822 19:52:56.059600 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4823 19:52:56.063127 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4824 19:52:56.069711 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4825 19:52:56.072911 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4826 19:52:56.073009 ==
4827 19:52:56.075909 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 19:52:56.079471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 19:52:56.079554 ==
4830 19:52:56.082826 DQS Delay:
4831 19:52:56.082925 DQS0 = 0, DQS1 = 0
4832 19:52:56.083016 DQM Delay:
4833 19:52:56.085783 DQM0 = 36, DQM1 = 29
4834 19:52:56.085886 DQ Delay:
4835 19:52:56.089434 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4836 19:52:56.092390 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4837 19:52:56.096052 DQ8 =20, DQ9 =20, DQ10 =28, DQ11 =20
4838 19:52:56.099447 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4839 19:52:56.099548
4840 19:52:56.099645
4841 19:52:56.109083 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4842 19:52:56.109170 CH1 RK1: MR19=808, MR18=3D5C
4843 19:52:56.115706 CH1_RK1: MR19=0x808, MR18=0x3D5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4844 19:52:56.119322 [RxdqsGatingPostProcess] freq 600
4845 19:52:56.125603 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4846 19:52:56.129134 Pre-setting of DQS Precalculation
4847 19:52:56.132792 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4848 19:52:56.139291 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4849 19:52:56.149404 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4850 19:52:56.149478
4851 19:52:56.149561
4852 19:52:56.152404 [Calibration Summary] 1200 Mbps
4853 19:52:56.152476 CH 0, Rank 0
4854 19:52:56.155916 SW Impedance : PASS
4855 19:52:56.155985 DUTY Scan : NO K
4856 19:52:56.159039 ZQ Calibration : PASS
4857 19:52:56.159134 Jitter Meter : NO K
4858 19:52:56.162329 CBT Training : PASS
4859 19:52:56.165722 Write leveling : PASS
4860 19:52:56.165828 RX DQS gating : PASS
4861 19:52:56.169463 RX DQ/DQS(RDDQC) : PASS
4862 19:52:56.172421 TX DQ/DQS : PASS
4863 19:52:56.172492 RX DATLAT : PASS
4864 19:52:56.176068 RX DQ/DQS(Engine): PASS
4865 19:52:56.178788 TX OE : NO K
4866 19:52:56.178871 All Pass.
4867 19:52:56.178941
4868 19:52:56.179000 CH 0, Rank 1
4869 19:52:56.182167 SW Impedance : PASS
4870 19:52:56.185461 DUTY Scan : NO K
4871 19:52:56.185536 ZQ Calibration : PASS
4872 19:52:56.189068 Jitter Meter : NO K
4873 19:52:56.192558 CBT Training : PASS
4874 19:52:56.192628 Write leveling : PASS
4875 19:52:56.195411 RX DQS gating : PASS
4876 19:52:56.199090 RX DQ/DQS(RDDQC) : PASS
4877 19:52:56.199185 TX DQ/DQS : PASS
4878 19:52:56.202518 RX DATLAT : PASS
4879 19:52:56.202587 RX DQ/DQS(Engine): PASS
4880 19:52:56.205679 TX OE : NO K
4881 19:52:56.205754 All Pass.
4882 19:52:56.205832
4883 19:52:56.208895 CH 1, Rank 0
4884 19:52:56.208963 SW Impedance : PASS
4885 19:52:56.212345 DUTY Scan : NO K
4886 19:52:56.215828 ZQ Calibration : PASS
4887 19:52:56.215968 Jitter Meter : NO K
4888 19:52:56.219082 CBT Training : PASS
4889 19:52:56.222331 Write leveling : PASS
4890 19:52:56.222430 RX DQS gating : PASS
4891 19:52:56.225922 RX DQ/DQS(RDDQC) : PASS
4892 19:52:56.229111 TX DQ/DQS : PASS
4893 19:52:56.229208 RX DATLAT : PASS
4894 19:52:56.232084 RX DQ/DQS(Engine): PASS
4895 19:52:56.235608 TX OE : NO K
4896 19:52:56.235692 All Pass.
4897 19:52:56.235752
4898 19:52:56.235816 CH 1, Rank 1
4899 19:52:56.238776 SW Impedance : PASS
4900 19:52:56.242057 DUTY Scan : NO K
4901 19:52:56.242132 ZQ Calibration : PASS
4902 19:52:56.245574 Jitter Meter : NO K
4903 19:52:56.248596 CBT Training : PASS
4904 19:52:56.248663 Write leveling : PASS
4905 19:52:56.251961 RX DQS gating : PASS
4906 19:52:56.252056 RX DQ/DQS(RDDQC) : PASS
4907 19:52:56.255207 TX DQ/DQS : PASS
4908 19:52:56.258800 RX DATLAT : PASS
4909 19:52:56.258867 RX DQ/DQS(Engine): PASS
4910 19:52:56.261827 TX OE : NO K
4911 19:52:56.261900 All Pass.
4912 19:52:56.261992
4913 19:52:56.265182 DramC Write-DBI off
4914 19:52:56.268822 PER_BANK_REFRESH: Hybrid Mode
4915 19:52:56.268892 TX_TRACKING: ON
4916 19:52:56.278598 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4917 19:52:56.282193 [FAST_K] Save calibration result to emmc
4918 19:52:56.285045 dramc_set_vcore_voltage set vcore to 662500
4919 19:52:56.288674 Read voltage for 933, 3
4920 19:52:56.288745 Vio18 = 0
4921 19:52:56.288827 Vcore = 662500
4922 19:52:56.291836 Vdram = 0
4923 19:52:56.291904 Vddq = 0
4924 19:52:56.291962 Vmddr = 0
4925 19:52:56.298651 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4926 19:52:56.302168 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4927 19:52:56.305016 MEM_TYPE=3, freq_sel=17
4928 19:52:56.308585 sv_algorithm_assistance_LP4_1600
4929 19:52:56.311742 ============ PULL DRAM RESETB DOWN ============
4930 19:52:56.318698 ========== PULL DRAM RESETB DOWN end =========
4931 19:52:56.321568 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4932 19:52:56.324949 ===================================
4933 19:52:56.328065 LPDDR4 DRAM CONFIGURATION
4934 19:52:56.331443 ===================================
4935 19:52:56.331519 EX_ROW_EN[0] = 0x0
4936 19:52:56.335141 EX_ROW_EN[1] = 0x0
4937 19:52:56.335243 LP4Y_EN = 0x0
4938 19:52:56.337926 WORK_FSP = 0x0
4939 19:52:56.338021 WL = 0x3
4940 19:52:56.341729 RL = 0x3
4941 19:52:56.341814 BL = 0x2
4942 19:52:56.344666 RPST = 0x0
4943 19:52:56.344745 RD_PRE = 0x0
4944 19:52:56.348284 WR_PRE = 0x1
4945 19:52:56.351463 WR_PST = 0x0
4946 19:52:56.351565 DBI_WR = 0x0
4947 19:52:56.354678 DBI_RD = 0x0
4948 19:52:56.354775 OTF = 0x1
4949 19:52:56.358049 ===================================
4950 19:52:56.361512 ===================================
4951 19:52:56.361610 ANA top config
4952 19:52:56.364648 ===================================
4953 19:52:56.368072 DLL_ASYNC_EN = 0
4954 19:52:56.371594 ALL_SLAVE_EN = 1
4955 19:52:56.374494 NEW_RANK_MODE = 1
4956 19:52:56.377851 DLL_IDLE_MODE = 1
4957 19:52:56.377977 LP45_APHY_COMB_EN = 1
4958 19:52:56.381623 TX_ODT_DIS = 1
4959 19:52:56.384957 NEW_8X_MODE = 1
4960 19:52:56.387881 ===================================
4961 19:52:56.391745 ===================================
4962 19:52:56.395128 data_rate = 1866
4963 19:52:56.397742 CKR = 1
4964 19:52:56.397817 DQ_P2S_RATIO = 8
4965 19:52:56.401065 ===================================
4966 19:52:56.404450 CA_P2S_RATIO = 8
4967 19:52:56.407813 DQ_CA_OPEN = 0
4968 19:52:56.411338 DQ_SEMI_OPEN = 0
4969 19:52:56.414931 CA_SEMI_OPEN = 0
4970 19:52:56.417611 CA_FULL_RATE = 0
4971 19:52:56.417715 DQ_CKDIV4_EN = 1
4972 19:52:56.420886 CA_CKDIV4_EN = 1
4973 19:52:56.424437 CA_PREDIV_EN = 0
4974 19:52:56.427641 PH8_DLY = 0
4975 19:52:56.431281 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4976 19:52:56.434479 DQ_AAMCK_DIV = 4
4977 19:52:56.434590 CA_AAMCK_DIV = 4
4978 19:52:56.437487 CA_ADMCK_DIV = 4
4979 19:52:56.441055 DQ_TRACK_CA_EN = 0
4980 19:52:56.444792 CA_PICK = 933
4981 19:52:56.447787 CA_MCKIO = 933
4982 19:52:56.451235 MCKIO_SEMI = 0
4983 19:52:56.454595 PLL_FREQ = 3732
4984 19:52:56.454679 DQ_UI_PI_RATIO = 32
4985 19:52:56.457804 CA_UI_PI_RATIO = 0
4986 19:52:56.460818 ===================================
4987 19:52:56.464224 ===================================
4988 19:52:56.467489 memory_type:LPDDR4
4989 19:52:56.470847 GP_NUM : 10
4990 19:52:56.470949 SRAM_EN : 1
4991 19:52:56.474569 MD32_EN : 0
4992 19:52:56.477602 ===================================
4993 19:52:56.481182 [ANA_INIT] >>>>>>>>>>>>>>
4994 19:52:56.481292 <<<<<< [CONFIGURE PHASE]: ANA_TX
4995 19:52:56.484575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4996 19:52:56.487355 ===================================
4997 19:52:56.490967 data_rate = 1866,PCW = 0X8f00
4998 19:52:56.494086 ===================================
4999 19:52:56.497538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5000 19:52:56.503946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 19:52:56.510692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 19:52:56.513989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5003 19:52:56.517788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5004 19:52:56.520556 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5005 19:52:56.524011 [ANA_INIT] flow start
5006 19:52:56.524108 [ANA_INIT] PLL >>>>>>>>
5007 19:52:56.527402 [ANA_INIT] PLL <<<<<<<<
5008 19:52:56.530943 [ANA_INIT] MIDPI >>>>>>>>
5009 19:52:56.531053 [ANA_INIT] MIDPI <<<<<<<<
5010 19:52:56.533858 [ANA_INIT] DLL >>>>>>>>
5011 19:52:56.537757 [ANA_INIT] flow end
5012 19:52:56.540643 ============ LP4 DIFF to SE enter ============
5013 19:52:56.544355 ============ LP4 DIFF to SE exit ============
5014 19:52:56.547242 [ANA_INIT] <<<<<<<<<<<<<
5015 19:52:56.550779 [Flow] Enable top DCM control >>>>>
5016 19:52:56.554415 [Flow] Enable top DCM control <<<<<
5017 19:52:56.557218 Enable DLL master slave shuffle
5018 19:52:56.560872 ==============================================================
5019 19:52:56.563739 Gating Mode config
5020 19:52:56.570696 ==============================================================
5021 19:52:56.570806 Config description:
5022 19:52:56.580388 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5023 19:52:56.586944 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5024 19:52:56.593966 SELPH_MODE 0: By rank 1: By Phase
5025 19:52:56.596918 ==============================================================
5026 19:52:56.600380 GAT_TRACK_EN = 1
5027 19:52:56.603562 RX_GATING_MODE = 2
5028 19:52:56.607160 RX_GATING_TRACK_MODE = 2
5029 19:52:56.610349 SELPH_MODE = 1
5030 19:52:56.613822 PICG_EARLY_EN = 1
5031 19:52:56.616668 VALID_LAT_VALUE = 1
5032 19:52:56.620204 ==============================================================
5033 19:52:56.623664 Enter into Gating configuration >>>>
5034 19:52:56.626708 Exit from Gating configuration <<<<
5035 19:52:56.630388 Enter into DVFS_PRE_config >>>>>
5036 19:52:56.643515 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5037 19:52:56.646799 Exit from DVFS_PRE_config <<<<<
5038 19:52:56.646906 Enter into PICG configuration >>>>
5039 19:52:56.650370 Exit from PICG configuration <<<<
5040 19:52:56.653166 [RX_INPUT] configuration >>>>>
5041 19:52:56.656521 [RX_INPUT] configuration <<<<<
5042 19:52:56.663092 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5043 19:52:56.666783 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5044 19:52:56.673124 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 19:52:56.679911 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 19:52:56.686379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5047 19:52:56.693245 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5048 19:52:56.696724 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5049 19:52:56.699540 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5050 19:52:56.703046 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5051 19:52:56.709802 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5052 19:52:56.713137 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5053 19:52:56.716127 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 19:52:56.719573 ===================================
5055 19:52:56.723216 LPDDR4 DRAM CONFIGURATION
5056 19:52:56.726282 ===================================
5057 19:52:56.729886 EX_ROW_EN[0] = 0x0
5058 19:52:56.729988 EX_ROW_EN[1] = 0x0
5059 19:52:56.732844 LP4Y_EN = 0x0
5060 19:52:56.732919 WORK_FSP = 0x0
5061 19:52:56.736421 WL = 0x3
5062 19:52:56.736520 RL = 0x3
5063 19:52:56.740049 BL = 0x2
5064 19:52:56.740148 RPST = 0x0
5065 19:52:56.742755 RD_PRE = 0x0
5066 19:52:56.742843 WR_PRE = 0x1
5067 19:52:56.746126 WR_PST = 0x0
5068 19:52:56.746199 DBI_WR = 0x0
5069 19:52:56.749344 DBI_RD = 0x0
5070 19:52:56.749414 OTF = 0x1
5071 19:52:56.752631 ===================================
5072 19:52:56.759521 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5073 19:52:56.762898 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5074 19:52:56.765955 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5075 19:52:56.769443 ===================================
5076 19:52:56.772999 LPDDR4 DRAM CONFIGURATION
5077 19:52:56.775998 ===================================
5078 19:52:56.776093 EX_ROW_EN[0] = 0x10
5079 19:52:56.779752 EX_ROW_EN[1] = 0x0
5080 19:52:56.782923 LP4Y_EN = 0x0
5081 19:52:56.783027 WORK_FSP = 0x0
5082 19:52:56.786259 WL = 0x3
5083 19:52:56.786333 RL = 0x3
5084 19:52:56.789612 BL = 0x2
5085 19:52:56.789723 RPST = 0x0
5086 19:52:56.792962 RD_PRE = 0x0
5087 19:52:56.793065 WR_PRE = 0x1
5088 19:52:56.796479 WR_PST = 0x0
5089 19:52:56.796554 DBI_WR = 0x0
5090 19:52:56.799773 DBI_RD = 0x0
5091 19:52:56.799872 OTF = 0x1
5092 19:52:56.802684 ===================================
5093 19:52:56.809094 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5094 19:52:56.814045 nWR fixed to 30
5095 19:52:56.816974 [ModeRegInit_LP4] CH0 RK0
5096 19:52:56.817081 [ModeRegInit_LP4] CH0 RK1
5097 19:52:56.820416 [ModeRegInit_LP4] CH1 RK0
5098 19:52:56.823871 [ModeRegInit_LP4] CH1 RK1
5099 19:52:56.823942 match AC timing 9
5100 19:52:56.830524 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5101 19:52:56.833748 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5102 19:52:56.836733 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5103 19:52:56.843364 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5104 19:52:56.846831 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5105 19:52:56.846930 ==
5106 19:52:56.850583 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 19:52:56.853378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 19:52:56.853475 ==
5109 19:52:56.860263 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 19:52:56.866824 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5111 19:52:56.870364 [CA 0] Center 38 (8~69) winsize 62
5112 19:52:56.873388 [CA 1] Center 38 (7~69) winsize 63
5113 19:52:56.877119 [CA 2] Center 35 (5~66) winsize 62
5114 19:52:56.880163 [CA 3] Center 35 (5~66) winsize 62
5115 19:52:56.883471 [CA 4] Center 34 (4~64) winsize 61
5116 19:52:56.886906 [CA 5] Center 34 (4~64) winsize 61
5117 19:52:56.887004
5118 19:52:56.890248 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5119 19:52:56.890346
5120 19:52:56.893624 [CATrainingPosCal] consider 1 rank data
5121 19:52:56.896628 u2DelayCellTimex100 = 270/100 ps
5122 19:52:56.899999 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5123 19:52:56.903541 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5124 19:52:56.906512 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5125 19:52:56.909869 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5126 19:52:56.913266 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5127 19:52:56.919963 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5128 19:52:56.920064
5129 19:52:56.923187 CA PerBit enable=1, Macro0, CA PI delay=34
5130 19:52:56.923283
5131 19:52:56.926867 [CBTSetCACLKResult] CA Dly = 34
5132 19:52:56.926964 CS Dly: 7 (0~38)
5133 19:52:56.927053 ==
5134 19:52:56.929811 Dram Type= 6, Freq= 0, CH_0, rank 1
5135 19:52:56.933300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 19:52:56.933397 ==
5137 19:52:56.939820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 19:52:56.946314 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5139 19:52:56.950084 [CA 0] Center 38 (8~69) winsize 62
5140 19:52:56.953104 [CA 1] Center 38 (8~69) winsize 62
5141 19:52:56.956627 [CA 2] Center 35 (5~66) winsize 62
5142 19:52:56.959646 [CA 3] Center 35 (5~66) winsize 62
5143 19:52:56.963231 [CA 4] Center 34 (4~65) winsize 62
5144 19:52:56.966431 [CA 5] Center 34 (4~64) winsize 61
5145 19:52:56.966506
5146 19:52:56.970022 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5147 19:52:56.970122
5148 19:52:56.973496 [CATrainingPosCal] consider 2 rank data
5149 19:52:56.976476 u2DelayCellTimex100 = 270/100 ps
5150 19:52:56.979907 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5151 19:52:56.982963 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5152 19:52:56.986385 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5153 19:52:56.989696 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5154 19:52:56.992680 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5155 19:52:56.999475 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5156 19:52:56.999584
5157 19:52:57.002985 CA PerBit enable=1, Macro0, CA PI delay=34
5158 19:52:57.003081
5159 19:52:57.005932 [CBTSetCACLKResult] CA Dly = 34
5160 19:52:57.006028 CS Dly: 7 (0~39)
5161 19:52:57.006115
5162 19:52:57.009388 ----->DramcWriteLeveling(PI) begin...
5163 19:52:57.009494 ==
5164 19:52:57.012809 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 19:52:57.019963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 19:52:57.020067 ==
5167 19:52:57.022958 Write leveling (Byte 0): 35 => 35
5168 19:52:57.023055 Write leveling (Byte 1): 30 => 30
5169 19:52:57.025900 DramcWriteLeveling(PI) end<-----
5170 19:52:57.025997
5171 19:52:57.029426 ==
5172 19:52:57.029523 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 19:52:57.036192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 19:52:57.036296 ==
5175 19:52:57.039187 [Gating] SW mode calibration
5176 19:52:57.045822 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5177 19:52:57.049113 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5178 19:52:57.056127 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5179 19:52:57.059116 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5180 19:52:57.062697 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 19:52:57.069230 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 19:52:57.072574 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 19:52:57.076130 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 19:52:57.082440 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 19:52:57.085602 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5186 19:52:57.089122 0 15 0 | B1->B0 | 3131 2727 | 1 0 | (1 1) (0 0)
5187 19:52:57.095681 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5188 19:52:57.098975 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5189 19:52:57.102472 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 19:52:57.108822 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 19:52:57.112431 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 19:52:57.115343 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 19:52:57.122238 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 19:52:57.125362 1 0 0 | B1->B0 | 2d2d 3c3c | 0 0 | (1 1) (0 0)
5195 19:52:57.128572 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5196 19:52:57.135660 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 19:52:57.138618 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 19:52:57.142142 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 19:52:57.148658 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 19:52:57.152312 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 19:52:57.154892 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 19:52:57.161574 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5203 19:52:57.165336 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5204 19:52:57.168224 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 19:52:57.171591 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 19:52:57.178621 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 19:52:57.181639 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 19:52:57.185154 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 19:52:57.191611 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 19:52:57.195200 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 19:52:57.198342 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 19:52:57.204712 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 19:52:57.208162 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 19:52:57.211393 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 19:52:57.218059 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 19:52:57.221545 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 19:52:57.224888 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 19:52:57.231326 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5219 19:52:57.234612 Total UI for P1: 0, mck2ui 16
5220 19:52:57.237924 best dqsien dly found for B0: ( 1, 2, 30)
5221 19:52:57.241169 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5222 19:52:57.244378 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 19:52:57.247831 Total UI for P1: 0, mck2ui 16
5224 19:52:57.250883 best dqsien dly found for B1: ( 1, 3, 2)
5225 19:52:57.254489 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5226 19:52:57.257452 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5227 19:52:57.257551
5228 19:52:57.264502 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5229 19:52:57.267933 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5230 19:52:57.270818 [Gating] SW calibration Done
5231 19:52:57.270915 ==
5232 19:52:57.274556 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 19:52:57.277424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 19:52:57.277520 ==
5235 19:52:57.277625 RX Vref Scan: 0
5236 19:52:57.277741
5237 19:52:57.281394 RX Vref 0 -> 0, step: 1
5238 19:52:57.281462
5239 19:52:57.284442 RX Delay -80 -> 252, step: 8
5240 19:52:57.287849 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5241 19:52:57.291315 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5242 19:52:57.294354 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5243 19:52:57.300912 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5244 19:52:57.303918 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5245 19:52:57.307472 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5246 19:52:57.310737 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5247 19:52:57.314275 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5248 19:52:57.320808 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5249 19:52:57.324179 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5250 19:52:57.327880 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5251 19:52:57.330634 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5252 19:52:57.334333 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5253 19:52:57.340582 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5254 19:52:57.344181 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5255 19:52:57.347469 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5256 19:52:57.347574 ==
5257 19:52:57.350567 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 19:52:57.354015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 19:52:57.354113 ==
5260 19:52:57.357591 DQS Delay:
5261 19:52:57.357689 DQS0 = 0, DQS1 = 0
5262 19:52:57.360733 DQM Delay:
5263 19:52:57.360812 DQM0 = 94, DQM1 = 82
5264 19:52:57.360874 DQ Delay:
5265 19:52:57.364317 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5266 19:52:57.367098 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5267 19:52:57.370442 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5268 19:52:57.373855 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5269 19:52:57.373948
5270 19:52:57.374038
5271 19:52:57.377378 ==
5272 19:52:57.377470 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 19:52:57.383907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 19:52:57.383981 ==
5275 19:52:57.384051
5276 19:52:57.384109
5277 19:52:57.387539 TX Vref Scan disable
5278 19:52:57.387605 == TX Byte 0 ==
5279 19:52:57.390370 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5280 19:52:57.396920 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5281 19:52:57.396995 == TX Byte 1 ==
5282 19:52:57.400569 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5283 19:52:57.406994 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5284 19:52:57.407096 ==
5285 19:52:57.410498 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 19:52:57.413513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 19:52:57.413613 ==
5288 19:52:57.413713
5289 19:52:57.413801
5290 19:52:57.417012 TX Vref Scan disable
5291 19:52:57.420372 == TX Byte 0 ==
5292 19:52:57.423531 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5293 19:52:57.426989 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5294 19:52:57.430075 == TX Byte 1 ==
5295 19:52:57.433813 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5296 19:52:57.436884 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5297 19:52:57.436963
5298 19:52:57.440384 [DATLAT]
5299 19:52:57.440480 Freq=933, CH0 RK0
5300 19:52:57.440580
5301 19:52:57.443802 DATLAT Default: 0xd
5302 19:52:57.443871 0, 0xFFFF, sum = 0
5303 19:52:57.447428 1, 0xFFFF, sum = 0
5304 19:52:57.447533 2, 0xFFFF, sum = 0
5305 19:52:57.450131 3, 0xFFFF, sum = 0
5306 19:52:57.450235 4, 0xFFFF, sum = 0
5307 19:52:57.453896 5, 0xFFFF, sum = 0
5308 19:52:57.454000 6, 0xFFFF, sum = 0
5309 19:52:57.456833 7, 0xFFFF, sum = 0
5310 19:52:57.456915 8, 0xFFFF, sum = 0
5311 19:52:57.460197 9, 0xFFFF, sum = 0
5312 19:52:57.460266 10, 0x0, sum = 1
5313 19:52:57.463493 11, 0x0, sum = 2
5314 19:52:57.463562 12, 0x0, sum = 3
5315 19:52:57.466633 13, 0x0, sum = 4
5316 19:52:57.466698 best_step = 11
5317 19:52:57.466755
5318 19:52:57.466810 ==
5319 19:52:57.470336 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 19:52:57.473409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 19:52:57.476644 ==
5322 19:52:57.476737 RX Vref Scan: 1
5323 19:52:57.476824
5324 19:52:57.480014 RX Vref 0 -> 0, step: 1
5325 19:52:57.480121
5326 19:52:57.483243 RX Delay -69 -> 252, step: 4
5327 19:52:57.483345
5328 19:52:57.486721 Set Vref, RX VrefLevel [Byte0]: 61
5329 19:52:57.490221 [Byte1]: 53
5330 19:52:57.490323
5331 19:52:57.493115 Final RX Vref Byte 0 = 61 to rank0
5332 19:52:57.496457 Final RX Vref Byte 1 = 53 to rank0
5333 19:52:57.499608 Final RX Vref Byte 0 = 61 to rank1
5334 19:52:57.503037 Final RX Vref Byte 1 = 53 to rank1==
5335 19:52:57.506562 Dram Type= 6, Freq= 0, CH_0, rank 0
5336 19:52:57.509691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 19:52:57.509800 ==
5338 19:52:57.513212 DQS Delay:
5339 19:52:57.513297 DQS0 = 0, DQS1 = 0
5340 19:52:57.513361 DQM Delay:
5341 19:52:57.516200 DQM0 = 95, DQM1 = 83
5342 19:52:57.516271 DQ Delay:
5343 19:52:57.519717 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5344 19:52:57.523073 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5345 19:52:57.526741 DQ8 =76, DQ9 =70, DQ10 =82, DQ11 =76
5346 19:52:57.529507 DQ12 =88, DQ13 =88, DQ14 =98, DQ15 =90
5347 19:52:57.529614
5348 19:52:57.529714
5349 19:52:57.539839 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5350 19:52:57.542850 CH0 RK0: MR19=505, MR18=1414
5351 19:52:57.546408 CH0_RK0: MR19=0x505, MR18=0x1414, DQSOSC=415, MR23=63, INC=62, DEC=41
5352 19:52:57.546529
5353 19:52:57.549865 ----->DramcWriteLeveling(PI) begin...
5354 19:52:57.553141 ==
5355 19:52:57.553242 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 19:52:57.559437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 19:52:57.559527 ==
5358 19:52:57.563161 Write leveling (Byte 0): 33 => 33
5359 19:52:57.566544 Write leveling (Byte 1): 30 => 30
5360 19:52:57.566624 DramcWriteLeveling(PI) end<-----
5361 19:52:57.569575
5362 19:52:57.569674 ==
5363 19:52:57.573163 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 19:52:57.576093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 19:52:57.576195 ==
5366 19:52:57.579523 [Gating] SW mode calibration
5367 19:52:57.586035 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5368 19:52:57.589672 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5369 19:52:57.596694 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
5370 19:52:57.599296 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 19:52:57.603055 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 19:52:57.609593 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 19:52:57.613028 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 19:52:57.616117 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 19:52:57.622860 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 19:52:57.626032 0 14 28 | B1->B0 | 3434 2929 | 0 0 | (0 0) (0 0)
5377 19:52:57.629657 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5378 19:52:57.636349 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 19:52:57.639112 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 19:52:57.642674 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 19:52:57.649072 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 19:52:57.652365 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 19:52:57.655825 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 19:52:57.662313 0 15 28 | B1->B0 | 2828 3636 | 0 0 | (0 0) (0 0)
5385 19:52:57.665609 1 0 0 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
5386 19:52:57.668962 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 19:52:57.675937 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 19:52:57.679028 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 19:52:57.682479 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 19:52:57.688985 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 19:52:57.691922 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 19:52:57.695628 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5393 19:52:57.702041 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5394 19:52:57.705383 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 19:52:57.708450 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 19:52:57.715093 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 19:52:57.718479 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 19:52:57.721716 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 19:52:57.728470 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 19:52:57.731780 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 19:52:57.735166 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 19:52:57.741606 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 19:52:57.745171 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 19:52:57.748750 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 19:52:57.755214 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 19:52:57.758254 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 19:52:57.761541 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 19:52:57.768199 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5409 19:52:57.768273 Total UI for P1: 0, mck2ui 16
5410 19:52:57.774981 best dqsien dly found for B0: ( 1, 2, 26)
5411 19:52:57.778314 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5412 19:52:57.781374 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 19:52:57.784941 Total UI for P1: 0, mck2ui 16
5414 19:52:57.788213 best dqsien dly found for B1: ( 1, 2, 30)
5415 19:52:57.791669 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5416 19:52:57.794624 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5417 19:52:57.794705
5418 19:52:57.798079 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5419 19:52:57.804876 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5420 19:52:57.804991 [Gating] SW calibration Done
5421 19:52:57.805057 ==
5422 19:52:57.808543 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 19:52:57.815039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 19:52:57.815119 ==
5425 19:52:57.815181 RX Vref Scan: 0
5426 19:52:57.815240
5427 19:52:57.818100 RX Vref 0 -> 0, step: 1
5428 19:52:57.818179
5429 19:52:57.821320 RX Delay -80 -> 252, step: 8
5430 19:52:57.824886 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5431 19:52:57.828580 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5432 19:52:57.831266 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5433 19:52:57.835028 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5434 19:52:57.841211 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5435 19:52:57.844612 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5436 19:52:57.847902 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5437 19:52:57.851211 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5438 19:52:57.854859 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5439 19:52:57.861376 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5440 19:52:57.864547 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5441 19:52:57.867824 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5442 19:52:57.870944 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5443 19:52:57.874256 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5444 19:52:57.881239 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5445 19:52:57.884525 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5446 19:52:57.884600 ==
5447 19:52:57.887764 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 19:52:57.890854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 19:52:57.890953 ==
5450 19:52:57.894561 DQS Delay:
5451 19:52:57.894630 DQS0 = 0, DQS1 = 0
5452 19:52:57.894715 DQM Delay:
5453 19:52:57.897822 DQM0 = 91, DQM1 = 83
5454 19:52:57.897920 DQ Delay:
5455 19:52:57.901336 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =91
5456 19:52:57.904149 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5457 19:52:57.907770 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5458 19:52:57.910751 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5459 19:52:57.910854
5460 19:52:57.910966
5461 19:52:57.911085 ==
5462 19:52:57.914178 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 19:52:57.920930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 19:52:57.921030 ==
5465 19:52:57.921120
5466 19:52:57.921215
5467 19:52:57.921304 TX Vref Scan disable
5468 19:52:57.924394 == TX Byte 0 ==
5469 19:52:57.927489 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5470 19:52:57.934223 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5471 19:52:57.934333 == TX Byte 1 ==
5472 19:52:57.937706 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5473 19:52:57.944237 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5474 19:52:57.944319 ==
5475 19:52:57.947814 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 19:52:57.951156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 19:52:57.951263 ==
5478 19:52:57.951406
5479 19:52:57.951482
5480 19:52:57.954281 TX Vref Scan disable
5481 19:52:57.954391 == TX Byte 0 ==
5482 19:52:57.960672 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5483 19:52:57.963951 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5484 19:52:57.964055 == TX Byte 1 ==
5485 19:52:57.970627 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5486 19:52:57.974004 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5487 19:52:57.974103
5488 19:52:57.974195 [DATLAT]
5489 19:52:57.977521 Freq=933, CH0 RK1
5490 19:52:57.977624
5491 19:52:57.977715 DATLAT Default: 0xb
5492 19:52:57.980658 0, 0xFFFF, sum = 0
5493 19:52:57.980763 1, 0xFFFF, sum = 0
5494 19:52:57.984228 2, 0xFFFF, sum = 0
5495 19:52:57.987621 3, 0xFFFF, sum = 0
5496 19:52:57.987695 4, 0xFFFF, sum = 0
5497 19:52:57.990721 5, 0xFFFF, sum = 0
5498 19:52:57.990820 6, 0xFFFF, sum = 0
5499 19:52:57.994053 7, 0xFFFF, sum = 0
5500 19:52:57.994153 8, 0xFFFF, sum = 0
5501 19:52:57.997477 9, 0xFFFF, sum = 0
5502 19:52:57.997580 10, 0x0, sum = 1
5503 19:52:58.000407 11, 0x0, sum = 2
5504 19:52:58.000486 12, 0x0, sum = 3
5505 19:52:58.000587 13, 0x0, sum = 4
5506 19:52:58.004058 best_step = 11
5507 19:52:58.004132
5508 19:52:58.004192 ==
5509 19:52:58.007372 Dram Type= 6, Freq= 0, CH_0, rank 1
5510 19:52:58.010354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 19:52:58.010455 ==
5512 19:52:58.013871 RX Vref Scan: 0
5513 19:52:58.013974
5514 19:52:58.016997 RX Vref 0 -> 0, step: 1
5515 19:52:58.017095
5516 19:52:58.017185 RX Delay -77 -> 252, step: 4
5517 19:52:58.025249 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5518 19:52:58.028207 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5519 19:52:58.031489 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5520 19:52:58.035087 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5521 19:52:58.038049 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5522 19:52:58.041784 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5523 19:52:58.048029 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5524 19:52:58.051654 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5525 19:52:58.054710 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5526 19:52:58.058586 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5527 19:52:58.061546 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5528 19:52:58.068431 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5529 19:52:58.071705 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5530 19:52:58.075331 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5531 19:52:58.078254 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5532 19:52:58.081431 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5533 19:52:58.085259 ==
5534 19:52:58.085360 Dram Type= 6, Freq= 0, CH_0, rank 1
5535 19:52:58.091208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 19:52:58.091313 ==
5537 19:52:58.091450 DQS Delay:
5538 19:52:58.094959 DQS0 = 0, DQS1 = 0
5539 19:52:58.095056 DQM Delay:
5540 19:52:58.097963 DQM0 = 93, DQM1 = 84
5541 19:52:58.098059 DQ Delay:
5542 19:52:58.101262 DQ0 =92, DQ1 =94, DQ2 =88, DQ3 =90
5543 19:52:58.104760 DQ4 =92, DQ5 =82, DQ6 =106, DQ7 =104
5544 19:52:58.108194 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =78
5545 19:52:58.111842 DQ12 =92, DQ13 =90, DQ14 =92, DQ15 =92
5546 19:52:58.111942
5547 19:52:58.112032
5548 19:52:58.117819 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5549 19:52:58.121386 CH0 RK1: MR19=505, MR18=2D0E
5550 19:52:58.127850 CH0_RK1: MR19=0x505, MR18=0x2D0E, DQSOSC=407, MR23=63, INC=65, DEC=43
5551 19:52:58.131342 [RxdqsGatingPostProcess] freq 933
5552 19:52:58.137826 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5553 19:52:58.137946 best DQS0 dly(2T, 0.5T) = (0, 10)
5554 19:52:58.141071 best DQS1 dly(2T, 0.5T) = (0, 11)
5555 19:52:58.144600 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5556 19:52:58.148226 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5557 19:52:58.151255 best DQS0 dly(2T, 0.5T) = (0, 10)
5558 19:52:58.154590 best DQS1 dly(2T, 0.5T) = (0, 10)
5559 19:52:58.157651 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5560 19:52:58.160777 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5561 19:52:58.164210 Pre-setting of DQS Precalculation
5562 19:52:58.170841 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5563 19:52:58.170951 ==
5564 19:52:58.174424 Dram Type= 6, Freq= 0, CH_1, rank 0
5565 19:52:58.177342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5566 19:52:58.177449 ==
5567 19:52:58.184051 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5568 19:52:58.187636 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5569 19:52:58.191530 [CA 0] Center 37 (7~67) winsize 61
5570 19:52:58.194794 [CA 1] Center 37 (7~68) winsize 62
5571 19:52:58.198099 [CA 2] Center 34 (5~64) winsize 60
5572 19:52:58.201178 [CA 3] Center 34 (4~64) winsize 61
5573 19:52:58.204303 [CA 4] Center 34 (5~64) winsize 60
5574 19:52:58.207839 [CA 5] Center 34 (4~64) winsize 61
5575 19:52:58.207934
5576 19:52:58.211493 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5577 19:52:58.211595
5578 19:52:58.214497 [CATrainingPosCal] consider 1 rank data
5579 19:52:58.218105 u2DelayCellTimex100 = 270/100 ps
5580 19:52:58.220927 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5581 19:52:58.227683 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5582 19:52:58.231522 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5583 19:52:58.234660 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5584 19:52:58.237721 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5585 19:52:58.241125 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5586 19:52:58.241225
5587 19:52:58.244313 CA PerBit enable=1, Macro0, CA PI delay=34
5588 19:52:58.244384
5589 19:52:58.247590 [CBTSetCACLKResult] CA Dly = 34
5590 19:52:58.247665 CS Dly: 6 (0~37)
5591 19:52:58.251061 ==
5592 19:52:58.254568 Dram Type= 6, Freq= 0, CH_1, rank 1
5593 19:52:58.257584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 19:52:58.257682 ==
5595 19:52:58.261089 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5596 19:52:58.267959 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5597 19:52:58.271638 [CA 0] Center 38 (8~68) winsize 61
5598 19:52:58.274537 [CA 1] Center 37 (7~68) winsize 62
5599 19:52:58.277723 [CA 2] Center 35 (5~65) winsize 61
5600 19:52:58.281390 [CA 3] Center 34 (4~64) winsize 61
5601 19:52:58.284806 [CA 4] Center 34 (4~65) winsize 62
5602 19:52:58.288075 [CA 5] Center 34 (4~64) winsize 61
5603 19:52:58.288148
5604 19:52:58.291275 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5605 19:52:58.291351
5606 19:52:58.294355 [CATrainingPosCal] consider 2 rank data
5607 19:52:58.297831 u2DelayCellTimex100 = 270/100 ps
5608 19:52:58.301316 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5609 19:52:58.307603 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5610 19:52:58.310877 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5611 19:52:58.314401 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5612 19:52:58.317488 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5613 19:52:58.320948 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5614 19:52:58.321048
5615 19:52:58.324616 CA PerBit enable=1, Macro0, CA PI delay=34
5616 19:52:58.324714
5617 19:52:58.327523 [CBTSetCACLKResult] CA Dly = 34
5618 19:52:58.331252 CS Dly: 6 (0~38)
5619 19:52:58.331348
5620 19:52:58.334835 ----->DramcWriteLeveling(PI) begin...
5621 19:52:58.334936 ==
5622 19:52:58.337726 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 19:52:58.340736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 19:52:58.340835 ==
5625 19:52:58.344119 Write leveling (Byte 0): 25 => 25
5626 19:52:58.347595 Write leveling (Byte 1): 26 => 26
5627 19:52:58.350604 DramcWriteLeveling(PI) end<-----
5628 19:52:58.350697
5629 19:52:58.350801 ==
5630 19:52:58.354425 Dram Type= 6, Freq= 0, CH_1, rank 0
5631 19:52:58.357337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 19:52:58.357437 ==
5633 19:52:58.360650 [Gating] SW mode calibration
5634 19:52:58.367231 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5635 19:52:58.374076 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5636 19:52:58.377319 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5637 19:52:58.380473 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 19:52:58.387212 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 19:52:58.390924 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 19:52:58.393978 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 19:52:58.400341 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 19:52:58.403751 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 19:52:58.407104 0 14 28 | B1->B0 | 2f2f 2f2f | 0 1 | (0 1) (1 0)
5644 19:52:58.413630 0 15 0 | B1->B0 | 2727 2626 | 0 0 | (1 1) (1 1)
5645 19:52:58.417152 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 19:52:58.420237 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 19:52:58.426944 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 19:52:58.430553 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 19:52:58.433377 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 19:52:58.440560 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 19:52:58.443604 0 15 28 | B1->B0 | 3131 3433 | 1 1 | (0 0) (0 0)
5652 19:52:58.447156 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 19:52:58.450618 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 19:52:58.457116 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 19:52:58.460021 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 19:52:58.463462 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 19:52:58.470282 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 19:52:58.473321 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 19:52:58.476801 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5660 19:52:58.483179 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5661 19:52:58.486867 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 19:52:58.490227 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 19:52:58.497007 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 19:52:58.500119 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 19:52:58.503638 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 19:52:58.510233 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 19:52:58.513260 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 19:52:58.517167 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 19:52:58.523557 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 19:52:58.526886 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 19:52:58.530203 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 19:52:58.536606 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 19:52:58.539897 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 19:52:58.543377 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5675 19:52:58.549873 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 19:52:58.549953 Total UI for P1: 0, mck2ui 16
5677 19:52:58.556471 best dqsien dly found for B0: ( 1, 2, 26)
5678 19:52:58.556552 Total UI for P1: 0, mck2ui 16
5679 19:52:58.560205 best dqsien dly found for B1: ( 1, 2, 24)
5680 19:52:58.566516 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5681 19:52:58.570105 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5682 19:52:58.570186
5683 19:52:58.573131 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5684 19:52:58.576591 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5685 19:52:58.579563 [Gating] SW calibration Done
5686 19:52:58.579643 ==
5687 19:52:58.583340 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 19:52:58.586664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 19:52:58.586745 ==
5690 19:52:58.589907 RX Vref Scan: 0
5691 19:52:58.589987
5692 19:52:58.590050 RX Vref 0 -> 0, step: 1
5693 19:52:58.590124
5694 19:52:58.592959 RX Delay -80 -> 252, step: 8
5695 19:52:58.596362 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5696 19:52:58.599723 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5697 19:52:58.606469 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5698 19:52:58.609481 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5699 19:52:58.613016 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5700 19:52:58.616437 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5701 19:52:58.619822 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5702 19:52:58.626793 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5703 19:52:58.629832 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5704 19:52:58.633424 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5705 19:52:58.636390 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5706 19:52:58.639758 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5707 19:52:58.642978 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5708 19:52:58.649381 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5709 19:52:58.652788 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5710 19:52:58.656121 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5711 19:52:58.656223 ==
5712 19:52:58.659704 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 19:52:58.662449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 19:52:58.666108 ==
5715 19:52:58.666210 DQS Delay:
5716 19:52:58.666305 DQS0 = 0, DQS1 = 0
5717 19:52:58.669649 DQM Delay:
5718 19:52:58.669748 DQM0 = 94, DQM1 = 86
5719 19:52:58.672487 DQ Delay:
5720 19:52:58.672581 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5721 19:52:58.676350 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5722 19:52:58.679830 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5723 19:52:58.685641 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5724 19:52:58.685742
5725 19:52:58.685835
5726 19:52:58.685922 ==
5727 19:52:58.689274 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 19:52:58.692494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 19:52:58.692593 ==
5730 19:52:58.692681
5731 19:52:58.692767
5732 19:52:58.695605 TX Vref Scan disable
5733 19:52:58.695701 == TX Byte 0 ==
5734 19:52:58.702457 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5735 19:52:58.705642 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5736 19:52:58.705747 == TX Byte 1 ==
5737 19:52:58.712512 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5738 19:52:58.715932 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5739 19:52:58.716031 ==
5740 19:52:58.719005 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 19:52:58.722541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 19:52:58.722644 ==
5743 19:52:58.722736
5744 19:52:58.722822
5745 19:52:58.725647 TX Vref Scan disable
5746 19:52:58.728985 == TX Byte 0 ==
5747 19:52:58.732554 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5748 19:52:58.735492 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5749 19:52:58.739150 == TX Byte 1 ==
5750 19:52:58.742743 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5751 19:52:58.745602 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5752 19:52:58.745699
5753 19:52:58.749337 [DATLAT]
5754 19:52:58.749432 Freq=933, CH1 RK0
5755 19:52:58.749523
5756 19:52:58.752093 DATLAT Default: 0xd
5757 19:52:58.752162 0, 0xFFFF, sum = 0
5758 19:52:58.755336 1, 0xFFFF, sum = 0
5759 19:52:58.755464 2, 0xFFFF, sum = 0
5760 19:52:58.758690 3, 0xFFFF, sum = 0
5761 19:52:58.758786 4, 0xFFFF, sum = 0
5762 19:52:58.762009 5, 0xFFFF, sum = 0
5763 19:52:58.762104 6, 0xFFFF, sum = 0
5764 19:52:58.765150 7, 0xFFFF, sum = 0
5765 19:52:58.765263 8, 0xFFFF, sum = 0
5766 19:52:58.772564 9, 0xFFFF, sum = 0
5767 19:52:58.772714 10, 0x0, sum = 1
5768 19:52:58.772808 11, 0x0, sum = 2
5769 19:52:58.772897 12, 0x0, sum = 3
5770 19:52:58.775257 13, 0x0, sum = 4
5771 19:52:58.775369 best_step = 11
5772 19:52:58.775514
5773 19:52:58.775601 ==
5774 19:52:58.778802 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 19:52:58.785509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 19:52:58.785616 ==
5777 19:52:58.785711 RX Vref Scan: 1
5778 19:52:58.785800
5779 19:52:58.788521 RX Vref 0 -> 0, step: 1
5780 19:52:58.788615
5781 19:52:58.792128 RX Delay -61 -> 252, step: 4
5782 19:52:58.792223
5783 19:52:58.795069 Set Vref, RX VrefLevel [Byte0]: 57
5784 19:52:58.798674 [Byte1]: 47
5785 19:52:58.798772
5786 19:52:58.801715 Final RX Vref Byte 0 = 57 to rank0
5787 19:52:58.804951 Final RX Vref Byte 1 = 47 to rank0
5788 19:52:58.808288 Final RX Vref Byte 0 = 57 to rank1
5789 19:52:58.811692 Final RX Vref Byte 1 = 47 to rank1==
5790 19:52:58.814678 Dram Type= 6, Freq= 0, CH_1, rank 0
5791 19:52:58.818269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 19:52:58.818438 ==
5793 19:52:58.821592 DQS Delay:
5794 19:52:58.821690 DQS0 = 0, DQS1 = 0
5795 19:52:58.824961 DQM Delay:
5796 19:52:58.825072 DQM0 = 96, DQM1 = 86
5797 19:52:58.825164 DQ Delay:
5798 19:52:58.828087 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =92
5799 19:52:58.831626 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =94
5800 19:52:58.834575 DQ8 =74, DQ9 =78, DQ10 =86, DQ11 =80
5801 19:52:58.838300 DQ12 =96, DQ13 =92, DQ14 =92, DQ15 =94
5802 19:52:58.838403
5803 19:52:58.841511
5804 19:52:58.848229 [DQSOSCAuto] RK0, (LSB)MR18= 0x8, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5805 19:52:58.851220 CH1 RK0: MR19=505, MR18=8
5806 19:52:58.854795 CH1_RK0: MR19=0x505, MR18=0x8, DQSOSC=419, MR23=63, INC=61, DEC=41
5807 19:52:58.854908
5808 19:52:58.858301 ----->DramcWriteLeveling(PI) begin...
5809 19:52:58.861297 ==
5810 19:52:58.861397 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 19:52:58.868219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 19:52:58.868294 ==
5813 19:52:58.871108 Write leveling (Byte 0): 28 => 28
5814 19:52:58.874579 Write leveling (Byte 1): 30 => 30
5815 19:52:58.878141 DramcWriteLeveling(PI) end<-----
5816 19:52:58.878238
5817 19:52:58.878330 ==
5818 19:52:58.880970 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 19:52:58.884603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 19:52:58.884727 ==
5821 19:52:58.888164 [Gating] SW mode calibration
5822 19:52:58.894697 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5823 19:52:58.898222 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5824 19:52:58.904998 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5825 19:52:58.908014 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 19:52:58.911030 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 19:52:58.917962 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 19:52:58.920954 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 19:52:58.924362 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 19:52:58.931088 0 14 24 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (1 0)
5831 19:52:58.934208 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5832 19:52:58.937705 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 19:52:58.944361 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 19:52:58.947223 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 19:52:58.950960 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 19:52:58.957516 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 19:52:58.960570 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 19:52:58.964072 0 15 24 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
5839 19:52:58.970823 0 15 28 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5840 19:52:58.974181 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 19:52:58.977177 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 19:52:58.984220 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 19:52:58.987167 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 19:52:58.990506 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 19:52:58.997157 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 19:52:59.000545 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5847 19:52:59.003890 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5848 19:52:59.010615 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 19:52:59.013873 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 19:52:59.017410 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 19:52:59.023811 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 19:52:59.027283 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 19:52:59.030617 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 19:52:59.037356 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 19:52:59.040502 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 19:52:59.043981 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 19:52:59.050007 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 19:52:59.053990 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 19:52:59.056645 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 19:52:59.063509 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 19:52:59.066927 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5862 19:52:59.070001 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5863 19:52:59.073582 Total UI for P1: 0, mck2ui 16
5864 19:52:59.076558 best dqsien dly found for B0: ( 1, 2, 20)
5865 19:52:59.083628 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5866 19:52:59.087050 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 19:52:59.089973 Total UI for P1: 0, mck2ui 16
5868 19:52:59.093490 best dqsien dly found for B1: ( 1, 2, 26)
5869 19:52:59.096712 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5870 19:52:59.100235 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5871 19:52:59.100330
5872 19:52:59.103539 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5873 19:52:59.106679 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5874 19:52:59.109911 [Gating] SW calibration Done
5875 19:52:59.110019 ==
5876 19:52:59.113110 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 19:52:59.116838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 19:52:59.116941 ==
5879 19:52:59.119772 RX Vref Scan: 0
5880 19:52:59.119841
5881 19:52:59.123299 RX Vref 0 -> 0, step: 1
5882 19:52:59.123417
5883 19:52:59.123522 RX Delay -80 -> 252, step: 8
5884 19:52:59.129909 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5885 19:52:59.133520 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5886 19:52:59.136498 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5887 19:52:59.140052 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5888 19:52:59.143191 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5889 19:52:59.146285 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5890 19:52:59.153286 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5891 19:52:59.156307 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5892 19:52:59.159557 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5893 19:52:59.163089 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5894 19:52:59.166199 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5895 19:52:59.172857 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5896 19:52:59.176644 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5897 19:52:59.179668 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5898 19:52:59.183087 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5899 19:52:59.186461 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5900 19:52:59.186564 ==
5901 19:52:59.189403 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 19:52:59.196212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 19:52:59.196294 ==
5904 19:52:59.196359 DQS Delay:
5905 19:52:59.199666 DQS0 = 0, DQS1 = 0
5906 19:52:59.199747 DQM Delay:
5907 19:52:59.199811 DQM0 = 94, DQM1 = 87
5908 19:52:59.202688 DQ Delay:
5909 19:52:59.206162 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5910 19:52:59.209966 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5911 19:52:59.212751 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =79
5912 19:52:59.215883 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5913 19:52:59.215961
5914 19:52:59.216024
5915 19:52:59.216087 ==
5916 19:52:59.219419 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 19:52:59.222523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 19:52:59.222596 ==
5919 19:52:59.222659
5920 19:52:59.222716
5921 19:52:59.225975 TX Vref Scan disable
5922 19:52:59.229497 == TX Byte 0 ==
5923 19:52:59.232981 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5924 19:52:59.235855 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5925 19:52:59.239315 == TX Byte 1 ==
5926 19:52:59.242984 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5927 19:52:59.245806 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5928 19:52:59.245876 ==
5929 19:52:59.249497 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 19:52:59.252885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 19:52:59.252961 ==
5932 19:52:59.256116
5933 19:52:59.256194
5934 19:52:59.256254 TX Vref Scan disable
5935 19:52:59.259336 == TX Byte 0 ==
5936 19:52:59.262751 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5937 19:52:59.266267 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5938 19:52:59.269303 == TX Byte 1 ==
5939 19:52:59.272645 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5940 19:52:59.278988 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5941 19:52:59.279092
5942 19:52:59.279184 [DATLAT]
5943 19:52:59.279270 Freq=933, CH1 RK1
5944 19:52:59.279358
5945 19:52:59.282357 DATLAT Default: 0xb
5946 19:52:59.282454 0, 0xFFFF, sum = 0
5947 19:52:59.285698 1, 0xFFFF, sum = 0
5948 19:52:59.285801 2, 0xFFFF, sum = 0
5949 19:52:59.289405 3, 0xFFFF, sum = 0
5950 19:52:59.292560 4, 0xFFFF, sum = 0
5951 19:52:59.292658 5, 0xFFFF, sum = 0
5952 19:52:59.295680 6, 0xFFFF, sum = 0
5953 19:52:59.295778 7, 0xFFFF, sum = 0
5954 19:52:59.299145 8, 0xFFFF, sum = 0
5955 19:52:59.299243 9, 0xFFFF, sum = 0
5956 19:52:59.302907 10, 0x0, sum = 1
5957 19:52:59.303005 11, 0x0, sum = 2
5958 19:52:59.305800 12, 0x0, sum = 3
5959 19:52:59.305898 13, 0x0, sum = 4
5960 19:52:59.305988 best_step = 11
5961 19:52:59.306074
5962 19:52:59.308754 ==
5963 19:52:59.312170 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 19:52:59.315759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 19:52:59.315860 ==
5966 19:52:59.315952 RX Vref Scan: 0
5967 19:52:59.316041
5968 19:52:59.319027 RX Vref 0 -> 0, step: 1
5969 19:52:59.319140
5970 19:52:59.322106 RX Delay -69 -> 252, step: 4
5971 19:52:59.325368 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5972 19:52:59.332120 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5973 19:52:59.335552 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5974 19:52:59.338560 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5975 19:52:59.342165 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5976 19:52:59.345707 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5977 19:52:59.352166 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5978 19:52:59.355546 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5979 19:52:59.358676 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5980 19:52:59.362130 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5981 19:52:59.365163 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5982 19:52:59.371955 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5983 19:52:59.375307 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5984 19:52:59.378999 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5985 19:52:59.381950 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5986 19:52:59.385311 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5987 19:52:59.385409 ==
5988 19:52:59.388832 Dram Type= 6, Freq= 0, CH_1, rank 1
5989 19:52:59.392029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5990 19:52:59.395567 ==
5991 19:52:59.395664 DQS Delay:
5992 19:52:59.395753 DQS0 = 0, DQS1 = 0
5993 19:52:59.398435 DQM Delay:
5994 19:52:59.398510 DQM0 = 91, DQM1 = 90
5995 19:52:59.402093 DQ Delay:
5996 19:52:59.402225 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5997 19:52:59.405060 DQ4 =88, DQ5 =100, DQ6 =102, DQ7 =88
5998 19:52:59.408414 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =84
5999 19:52:59.415073 DQ12 =98, DQ13 =98, DQ14 =94, DQ15 =96
6000 19:52:59.415174
6001 19:52:59.415266
6002 19:52:59.421713 [DQSOSCAuto] RK1, (LSB)MR18= 0x1024, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
6003 19:52:59.425455 CH1 RK1: MR19=505, MR18=1024
6004 19:52:59.431707 CH1_RK1: MR19=0x505, MR18=0x1024, DQSOSC=410, MR23=63, INC=64, DEC=42
6005 19:52:59.435057 [RxdqsGatingPostProcess] freq 933
6006 19:52:59.438206 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6007 19:52:59.441789 best DQS0 dly(2T, 0.5T) = (0, 10)
6008 19:52:59.445370 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 19:52:59.448321 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6010 19:52:59.451812 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 19:52:59.454854 best DQS0 dly(2T, 0.5T) = (0, 10)
6012 19:52:59.458343 best DQS1 dly(2T, 0.5T) = (0, 10)
6013 19:52:59.461964 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6014 19:52:59.464614 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6015 19:52:59.468354 Pre-setting of DQS Precalculation
6016 19:52:59.471369 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6017 19:52:59.481362 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6018 19:52:59.487709 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6019 19:52:59.487791
6020 19:52:59.487854
6021 19:52:59.490864 [Calibration Summary] 1866 Mbps
6022 19:52:59.490934 CH 0, Rank 0
6023 19:52:59.494267 SW Impedance : PASS
6024 19:52:59.494335 DUTY Scan : NO K
6025 19:52:59.497634 ZQ Calibration : PASS
6026 19:52:59.501070 Jitter Meter : NO K
6027 19:52:59.501144 CBT Training : PASS
6028 19:52:59.504655 Write leveling : PASS
6029 19:52:59.507852 RX DQS gating : PASS
6030 19:52:59.507921 RX DQ/DQS(RDDQC) : PASS
6031 19:52:59.510810 TX DQ/DQS : PASS
6032 19:52:59.514166 RX DATLAT : PASS
6033 19:52:59.514233 RX DQ/DQS(Engine): PASS
6034 19:52:59.517490 TX OE : NO K
6035 19:52:59.517565 All Pass.
6036 19:52:59.517625
6037 19:52:59.521001 CH 0, Rank 1
6038 19:52:59.521069 SW Impedance : PASS
6039 19:52:59.524337 DUTY Scan : NO K
6040 19:52:59.527602 ZQ Calibration : PASS
6041 19:52:59.527669 Jitter Meter : NO K
6042 19:52:59.530944 CBT Training : PASS
6043 19:52:59.531010 Write leveling : PASS
6044 19:52:59.533930 RX DQS gating : PASS
6045 19:52:59.537541 RX DQ/DQS(RDDQC) : PASS
6046 19:52:59.537608 TX DQ/DQS : PASS
6047 19:52:59.541260 RX DATLAT : PASS
6048 19:52:59.544242 RX DQ/DQS(Engine): PASS
6049 19:52:59.544314 TX OE : NO K
6050 19:52:59.547334 All Pass.
6051 19:52:59.547442
6052 19:52:59.547505 CH 1, Rank 0
6053 19:52:59.550782 SW Impedance : PASS
6054 19:52:59.550854 DUTY Scan : NO K
6055 19:52:59.553846 ZQ Calibration : PASS
6056 19:52:59.557464 Jitter Meter : NO K
6057 19:52:59.557532 CBT Training : PASS
6058 19:52:59.560965 Write leveling : PASS
6059 19:52:59.563933 RX DQS gating : PASS
6060 19:52:59.564001 RX DQ/DQS(RDDQC) : PASS
6061 19:52:59.567510 TX DQ/DQS : PASS
6062 19:52:59.570439 RX DATLAT : PASS
6063 19:52:59.570542 RX DQ/DQS(Engine): PASS
6064 19:52:59.573507 TX OE : NO K
6065 19:52:59.573603 All Pass.
6066 19:52:59.573690
6067 19:52:59.576866 CH 1, Rank 1
6068 19:52:59.576957 SW Impedance : PASS
6069 19:52:59.580462 DUTY Scan : NO K
6070 19:52:59.583550 ZQ Calibration : PASS
6071 19:52:59.583649 Jitter Meter : NO K
6072 19:52:59.586721 CBT Training : PASS
6073 19:52:59.590121 Write leveling : PASS
6074 19:52:59.590222 RX DQS gating : PASS
6075 19:52:59.593594 RX DQ/DQS(RDDQC) : PASS
6076 19:52:59.596897 TX DQ/DQS : PASS
6077 19:52:59.596998 RX DATLAT : PASS
6078 19:52:59.600016 RX DQ/DQS(Engine): PASS
6079 19:52:59.600112 TX OE : NO K
6080 19:52:59.603321 All Pass.
6081 19:52:59.603448
6082 19:52:59.603510 DramC Write-DBI off
6083 19:52:59.606875 PER_BANK_REFRESH: Hybrid Mode
6084 19:52:59.610486 TX_TRACKING: ON
6085 19:52:59.617114 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6086 19:52:59.620108 [FAST_K] Save calibration result to emmc
6087 19:52:59.626850 dramc_set_vcore_voltage set vcore to 650000
6088 19:52:59.626927 Read voltage for 400, 6
6089 19:52:59.626990 Vio18 = 0
6090 19:52:59.630355 Vcore = 650000
6091 19:52:59.630428 Vdram = 0
6092 19:52:59.630488 Vddq = 0
6093 19:52:59.633028 Vmddr = 0
6094 19:52:59.636550 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6095 19:52:59.643062 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6096 19:52:59.646599 MEM_TYPE=3, freq_sel=20
6097 19:52:59.646688 sv_algorithm_assistance_LP4_800
6098 19:52:59.653597 ============ PULL DRAM RESETB DOWN ============
6099 19:52:59.656539 ========== PULL DRAM RESETB DOWN end =========
6100 19:52:59.660017 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6101 19:52:59.663606 ===================================
6102 19:52:59.666589 LPDDR4 DRAM CONFIGURATION
6103 19:52:59.670205 ===================================
6104 19:52:59.673007 EX_ROW_EN[0] = 0x0
6105 19:52:59.673085 EX_ROW_EN[1] = 0x0
6106 19:52:59.676581 LP4Y_EN = 0x0
6107 19:52:59.676659 WORK_FSP = 0x0
6108 19:52:59.679639 WL = 0x2
6109 19:52:59.679719 RL = 0x2
6110 19:52:59.683149 BL = 0x2
6111 19:52:59.683226 RPST = 0x0
6112 19:52:59.686581 RD_PRE = 0x0
6113 19:52:59.686660 WR_PRE = 0x1
6114 19:52:59.689667 WR_PST = 0x0
6115 19:52:59.689738 DBI_WR = 0x0
6116 19:52:59.692931 DBI_RD = 0x0
6117 19:52:59.693006 OTF = 0x1
6118 19:52:59.695935 ===================================
6119 19:52:59.699303 ===================================
6120 19:52:59.702743 ANA top config
6121 19:52:59.705926 ===================================
6122 19:52:59.709429 DLL_ASYNC_EN = 0
6123 19:52:59.709499 ALL_SLAVE_EN = 1
6124 19:52:59.712620 NEW_RANK_MODE = 1
6125 19:52:59.715988 DLL_IDLE_MODE = 1
6126 19:52:59.719533 LP45_APHY_COMB_EN = 1
6127 19:52:59.723036 TX_ODT_DIS = 1
6128 19:52:59.723113 NEW_8X_MODE = 1
6129 19:52:59.725753 ===================================
6130 19:52:59.729314 ===================================
6131 19:52:59.733037 data_rate = 800
6132 19:52:59.736058 CKR = 1
6133 19:52:59.738955 DQ_P2S_RATIO = 4
6134 19:52:59.742439 ===================================
6135 19:52:59.745515 CA_P2S_RATIO = 4
6136 19:52:59.749147 DQ_CA_OPEN = 0
6137 19:52:59.749241 DQ_SEMI_OPEN = 1
6138 19:52:59.752313 CA_SEMI_OPEN = 1
6139 19:52:59.755602 CA_FULL_RATE = 0
6140 19:52:59.759038 DQ_CKDIV4_EN = 0
6141 19:52:59.762392 CA_CKDIV4_EN = 1
6142 19:52:59.765737 CA_PREDIV_EN = 0
6143 19:52:59.765811 PH8_DLY = 0
6144 19:52:59.769317 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6145 19:52:59.772344 DQ_AAMCK_DIV = 0
6146 19:52:59.775745 CA_AAMCK_DIV = 0
6147 19:52:59.779265 CA_ADMCK_DIV = 4
6148 19:52:59.779363 DQ_TRACK_CA_EN = 0
6149 19:52:59.782121 CA_PICK = 800
6150 19:52:59.785569 CA_MCKIO = 400
6151 19:52:59.789333 MCKIO_SEMI = 400
6152 19:52:59.792165 PLL_FREQ = 3016
6153 19:52:59.795324 DQ_UI_PI_RATIO = 32
6154 19:52:59.798895 CA_UI_PI_RATIO = 32
6155 19:52:59.802081 ===================================
6156 19:52:59.805899 ===================================
6157 19:52:59.805973 memory_type:LPDDR4
6158 19:52:59.808763 GP_NUM : 10
6159 19:52:59.811925 SRAM_EN : 1
6160 19:52:59.812001 MD32_EN : 0
6161 19:52:59.815566 ===================================
6162 19:52:59.818551 [ANA_INIT] >>>>>>>>>>>>>>
6163 19:52:59.821862 <<<<<< [CONFIGURE PHASE]: ANA_TX
6164 19:52:59.825066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6165 19:52:59.828823 ===================================
6166 19:52:59.831699 data_rate = 800,PCW = 0X7400
6167 19:52:59.835422 ===================================
6168 19:52:59.838392 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6169 19:52:59.841921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6170 19:52:59.855135 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 19:52:59.858711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6172 19:52:59.862074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6173 19:52:59.865307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6174 19:52:59.868617 [ANA_INIT] flow start
6175 19:52:59.871562 [ANA_INIT] PLL >>>>>>>>
6176 19:52:59.871635 [ANA_INIT] PLL <<<<<<<<
6177 19:52:59.875171 [ANA_INIT] MIDPI >>>>>>>>
6178 19:52:59.878156 [ANA_INIT] MIDPI <<<<<<<<
6179 19:52:59.878225 [ANA_INIT] DLL >>>>>>>>
6180 19:52:59.881554 [ANA_INIT] flow end
6181 19:52:59.884835 ============ LP4 DIFF to SE enter ============
6182 19:52:59.891650 ============ LP4 DIFF to SE exit ============
6183 19:52:59.891728 [ANA_INIT] <<<<<<<<<<<<<
6184 19:52:59.895044 [Flow] Enable top DCM control >>>>>
6185 19:52:59.898039 [Flow] Enable top DCM control <<<<<
6186 19:52:59.901861 Enable DLL master slave shuffle
6187 19:52:59.908060 ==============================================================
6188 19:52:59.908140 Gating Mode config
6189 19:52:59.914590 ==============================================================
6190 19:52:59.918263 Config description:
6191 19:52:59.924770 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6192 19:52:59.931544 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6193 19:52:59.937701 SELPH_MODE 0: By rank 1: By Phase
6194 19:52:59.944327 ==============================================================
6195 19:52:59.947567 GAT_TRACK_EN = 0
6196 19:52:59.947635 RX_GATING_MODE = 2
6197 19:52:59.951013 RX_GATING_TRACK_MODE = 2
6198 19:52:59.954670 SELPH_MODE = 1
6199 19:52:59.957802 PICG_EARLY_EN = 1
6200 19:52:59.961165 VALID_LAT_VALUE = 1
6201 19:52:59.967878 ==============================================================
6202 19:52:59.970729 Enter into Gating configuration >>>>
6203 19:52:59.974361 Exit from Gating configuration <<<<
6204 19:52:59.977804 Enter into DVFS_PRE_config >>>>>
6205 19:52:59.987435 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6206 19:52:59.991028 Exit from DVFS_PRE_config <<<<<
6207 19:52:59.994469 Enter into PICG configuration >>>>
6208 19:52:59.997439 Exit from PICG configuration <<<<
6209 19:53:00.001179 [RX_INPUT] configuration >>>>>
6210 19:53:00.004168 [RX_INPUT] configuration <<<<<
6211 19:53:00.007527 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6212 19:53:00.013915 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6213 19:53:00.020460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6214 19:53:00.024546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6215 19:53:00.030751 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6216 19:53:00.037333 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6217 19:53:00.041071 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6218 19:53:00.043782 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6219 19:53:00.050497 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6220 19:53:00.053779 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6221 19:53:00.057528 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6222 19:53:00.063993 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 19:53:00.067134 ===================================
6224 19:53:00.067240 LPDDR4 DRAM CONFIGURATION
6225 19:53:00.070645 ===================================
6226 19:53:00.073985 EX_ROW_EN[0] = 0x0
6227 19:53:00.077556 EX_ROW_EN[1] = 0x0
6228 19:53:00.077658 LP4Y_EN = 0x0
6229 19:53:00.080592 WORK_FSP = 0x0
6230 19:53:00.080688 WL = 0x2
6231 19:53:00.083733 RL = 0x2
6232 19:53:00.083809 BL = 0x2
6233 19:53:00.087046 RPST = 0x0
6234 19:53:00.087143 RD_PRE = 0x0
6235 19:53:00.090101 WR_PRE = 0x1
6236 19:53:00.090172 WR_PST = 0x0
6237 19:53:00.093798 DBI_WR = 0x0
6238 19:53:00.093869 DBI_RD = 0x0
6239 19:53:00.097323 OTF = 0x1
6240 19:53:00.100374 ===================================
6241 19:53:00.103889 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6242 19:53:00.107309 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6243 19:53:00.113704 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6244 19:53:00.117217 ===================================
6245 19:53:00.117291 LPDDR4 DRAM CONFIGURATION
6246 19:53:00.120548 ===================================
6247 19:53:00.123920 EX_ROW_EN[0] = 0x10
6248 19:53:00.123993 EX_ROW_EN[1] = 0x0
6249 19:53:00.126948 LP4Y_EN = 0x0
6250 19:53:00.127013 WORK_FSP = 0x0
6251 19:53:00.130546 WL = 0x2
6252 19:53:00.133458 RL = 0x2
6253 19:53:00.133525 BL = 0x2
6254 19:53:00.136924 RPST = 0x0
6255 19:53:00.136997 RD_PRE = 0x0
6256 19:53:00.140422 WR_PRE = 0x1
6257 19:53:00.140495 WR_PST = 0x0
6258 19:53:00.143816 DBI_WR = 0x0
6259 19:53:00.143890 DBI_RD = 0x0
6260 19:53:00.147164 OTF = 0x1
6261 19:53:00.150129 ===================================
6262 19:53:00.156984 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6263 19:53:00.160143 nWR fixed to 30
6264 19:53:00.160213 [ModeRegInit_LP4] CH0 RK0
6265 19:53:00.163261 [ModeRegInit_LP4] CH0 RK1
6266 19:53:00.166846 [ModeRegInit_LP4] CH1 RK0
6267 19:53:00.166944 [ModeRegInit_LP4] CH1 RK1
6268 19:53:00.170587 match AC timing 19
6269 19:53:00.173301 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6270 19:53:00.176375 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6271 19:53:00.183508 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6272 19:53:00.186465 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6273 19:53:00.193555 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6274 19:53:00.193634 ==
6275 19:53:00.196614 Dram Type= 6, Freq= 0, CH_0, rank 0
6276 19:53:00.199621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 19:53:00.199691 ==
6278 19:53:00.206886 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6279 19:53:00.213254 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6280 19:53:00.213331 [CA 0] Center 36 (8~64) winsize 57
6281 19:53:00.216252 [CA 1] Center 36 (8~64) winsize 57
6282 19:53:00.219878 [CA 2] Center 36 (8~64) winsize 57
6283 19:53:00.222771 [CA 3] Center 36 (8~64) winsize 57
6284 19:53:00.226347 [CA 4] Center 36 (8~64) winsize 57
6285 19:53:00.229367 [CA 5] Center 36 (8~64) winsize 57
6286 19:53:00.229437
6287 19:53:00.232937 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6288 19:53:00.233005
6289 19:53:00.236423 [CATrainingPosCal] consider 1 rank data
6290 19:53:00.239432 u2DelayCellTimex100 = 270/100 ps
6291 19:53:00.242874 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 19:53:00.246189 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 19:53:00.252649 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 19:53:00.256390 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 19:53:00.259474 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 19:53:00.263169 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 19:53:00.263265
6298 19:53:00.266031 CA PerBit enable=1, Macro0, CA PI delay=36
6299 19:53:00.266127
6300 19:53:00.269514 [CBTSetCACLKResult] CA Dly = 36
6301 19:53:00.269609 CS Dly: 1 (0~32)
6302 19:53:00.269696 ==
6303 19:53:00.272737 Dram Type= 6, Freq= 0, CH_0, rank 1
6304 19:53:00.279518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 19:53:00.279620 ==
6306 19:53:00.282803 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6307 19:53:00.289933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6308 19:53:00.292769 [CA 0] Center 36 (8~64) winsize 57
6309 19:53:00.296239 [CA 1] Center 36 (8~64) winsize 57
6310 19:53:00.299352 [CA 2] Center 36 (8~64) winsize 57
6311 19:53:00.302935 [CA 3] Center 36 (8~64) winsize 57
6312 19:53:00.306683 [CA 4] Center 36 (8~64) winsize 57
6313 19:53:00.309571 [CA 5] Center 36 (8~64) winsize 57
6314 19:53:00.309663
6315 19:53:00.312565 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6316 19:53:00.312664
6317 19:53:00.315735 [CATrainingPosCal] consider 2 rank data
6318 19:53:00.319476 u2DelayCellTimex100 = 270/100 ps
6319 19:53:00.323000 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 19:53:00.326079 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 19:53:00.329454 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 19:53:00.332524 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 19:53:00.336116 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 19:53:00.342907 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 19:53:00.343007
6326 19:53:00.345776 CA PerBit enable=1, Macro0, CA PI delay=36
6327 19:53:00.345881
6328 19:53:00.349569 [CBTSetCACLKResult] CA Dly = 36
6329 19:53:00.349702 CS Dly: 1 (0~32)
6330 19:53:00.349832
6331 19:53:00.352882 ----->DramcWriteLeveling(PI) begin...
6332 19:53:00.352986 ==
6333 19:53:00.355976 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 19:53:00.359016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 19:53:00.362805 ==
6336 19:53:00.362902 Write leveling (Byte 0): 40 => 8
6337 19:53:00.365694 Write leveling (Byte 1): 40 => 8
6338 19:53:00.369171 DramcWriteLeveling(PI) end<-----
6339 19:53:00.369241
6340 19:53:00.369332 ==
6341 19:53:00.372625 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 19:53:00.378833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 19:53:00.378906 ==
6344 19:53:00.379000 [Gating] SW mode calibration
6345 19:53:00.388852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6346 19:53:00.392193 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6347 19:53:00.398902 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6348 19:53:00.402109 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 19:53:00.405262 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6350 19:53:00.411925 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 19:53:00.415529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 19:53:00.418877 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 19:53:00.422009 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 19:53:00.428670 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 19:53:00.432049 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 19:53:00.435106 Total UI for P1: 0, mck2ui 16
6357 19:53:00.438550 best dqsien dly found for B0: ( 0, 14, 24)
6358 19:53:00.442042 Total UI for P1: 0, mck2ui 16
6359 19:53:00.445419 best dqsien dly found for B1: ( 0, 14, 24)
6360 19:53:00.448449 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6361 19:53:00.451897 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6362 19:53:00.451965
6363 19:53:00.455460 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6364 19:53:00.461505 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 19:53:00.461577 [Gating] SW calibration Done
6366 19:53:00.465098 ==
6367 19:53:00.465198 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 19:53:00.471744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 19:53:00.471825 ==
6370 19:53:00.471918 RX Vref Scan: 0
6371 19:53:00.472008
6372 19:53:00.474716 RX Vref 0 -> 0, step: 1
6373 19:53:00.474790
6374 19:53:00.478549 RX Delay -410 -> 252, step: 16
6375 19:53:00.481456 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6376 19:53:00.485181 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6377 19:53:00.491929 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6378 19:53:00.494726 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6379 19:53:00.498360 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6380 19:53:00.502054 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6381 19:53:00.508133 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6382 19:53:00.511632 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6383 19:53:00.514831 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6384 19:53:00.518063 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6385 19:53:00.524609 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6386 19:53:00.528489 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6387 19:53:00.531475 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6388 19:53:00.534799 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6389 19:53:00.541833 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6390 19:53:00.544796 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6391 19:53:00.544872 ==
6392 19:53:00.548067 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 19:53:00.551321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 19:53:00.551479 ==
6395 19:53:00.554673 DQS Delay:
6396 19:53:00.554769 DQS0 = 59, DQS1 = 59
6397 19:53:00.558210 DQM Delay:
6398 19:53:00.558281 DQM0 = 18, DQM1 = 10
6399 19:53:00.558340 DQ Delay:
6400 19:53:00.561982 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6401 19:53:00.564798 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6402 19:53:00.568533 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6403 19:53:00.571375 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6404 19:53:00.571479
6405 19:53:00.571540
6406 19:53:00.571597 ==
6407 19:53:00.574537 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 19:53:00.581078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 19:53:00.581160 ==
6410 19:53:00.581224
6411 19:53:00.581282
6412 19:53:00.581353 TX Vref Scan disable
6413 19:53:00.584582 == TX Byte 0 ==
6414 19:53:00.587822 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 19:53:00.591281 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 19:53:00.594695 == TX Byte 1 ==
6417 19:53:00.598208 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6418 19:53:00.600987 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6419 19:53:00.601060 ==
6420 19:53:00.604754 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 19:53:00.611181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 19:53:00.611260 ==
6423 19:53:00.611322
6424 19:53:00.611450
6425 19:53:00.614622 TX Vref Scan disable
6426 19:53:00.614694 == TX Byte 0 ==
6427 19:53:00.617605 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6428 19:53:00.621121 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6429 19:53:00.624588 == TX Byte 1 ==
6430 19:53:00.627789 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6431 19:53:00.631056 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6432 19:53:00.634660
6433 19:53:00.634756 [DATLAT]
6434 19:53:00.634891 Freq=400, CH0 RK0
6435 19:53:00.634954
6436 19:53:00.637726 DATLAT Default: 0xf
6437 19:53:00.637825 0, 0xFFFF, sum = 0
6438 19:53:00.640794 1, 0xFFFF, sum = 0
6439 19:53:00.640866 2, 0xFFFF, sum = 0
6440 19:53:00.644100 3, 0xFFFF, sum = 0
6441 19:53:00.644173 4, 0xFFFF, sum = 0
6442 19:53:00.647562 5, 0xFFFF, sum = 0
6443 19:53:00.650676 6, 0xFFFF, sum = 0
6444 19:53:00.650748 7, 0xFFFF, sum = 0
6445 19:53:00.654711 8, 0xFFFF, sum = 0
6446 19:53:00.654785 9, 0xFFFF, sum = 0
6447 19:53:00.657523 10, 0xFFFF, sum = 0
6448 19:53:00.657600 11, 0xFFFF, sum = 0
6449 19:53:00.660939 12, 0xFFFF, sum = 0
6450 19:53:00.661013 13, 0x0, sum = 1
6451 19:53:00.664154 14, 0x0, sum = 2
6452 19:53:00.664259 15, 0x0, sum = 3
6453 19:53:00.667271 16, 0x0, sum = 4
6454 19:53:00.667370 best_step = 14
6455 19:53:00.667473
6456 19:53:00.667574 ==
6457 19:53:00.670868 Dram Type= 6, Freq= 0, CH_0, rank 0
6458 19:53:00.673805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 19:53:00.673875 ==
6460 19:53:00.677224 RX Vref Scan: 1
6461 19:53:00.677292
6462 19:53:00.680442 RX Vref 0 -> 0, step: 1
6463 19:53:00.680512
6464 19:53:00.680572 RX Delay -359 -> 252, step: 8
6465 19:53:00.683790
6466 19:53:00.683869 Set Vref, RX VrefLevel [Byte0]: 61
6467 19:53:00.687318 [Byte1]: 53
6468 19:53:00.692673
6469 19:53:00.692747 Final RX Vref Byte 0 = 61 to rank0
6470 19:53:00.696110 Final RX Vref Byte 1 = 53 to rank0
6471 19:53:00.699731 Final RX Vref Byte 0 = 61 to rank1
6472 19:53:00.702722 Final RX Vref Byte 1 = 53 to rank1==
6473 19:53:00.706305 Dram Type= 6, Freq= 0, CH_0, rank 0
6474 19:53:00.712785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 19:53:00.712866 ==
6476 19:53:00.712928 DQS Delay:
6477 19:53:00.716201 DQS0 = 60, DQS1 = 68
6478 19:53:00.716268 DQM Delay:
6479 19:53:00.716329 DQM0 = 15, DQM1 = 14
6480 19:53:00.719389 DQ Delay:
6481 19:53:00.722931 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =16
6482 19:53:00.725906 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6483 19:53:00.725976 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6484 19:53:00.732378 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6485 19:53:00.732450
6486 19:53:00.732511
6487 19:53:00.738939 [DQSOSCAuto] RK0, (LSB)MR18= 0x8584, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6488 19:53:00.742613 CH0 RK0: MR19=C0C, MR18=8584
6489 19:53:00.749084 CH0_RK0: MR19=0xC0C, MR18=0x8584, DQSOSC=393, MR23=63, INC=382, DEC=254
6490 19:53:00.749169 ==
6491 19:53:00.752421 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 19:53:00.755923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 19:53:00.755997 ==
6494 19:53:00.758821 [Gating] SW mode calibration
6495 19:53:00.765736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6496 19:53:00.772034 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6497 19:53:00.775373 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6498 19:53:00.778485 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 19:53:00.785227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 19:53:00.789048 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 19:53:00.791798 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 19:53:00.798892 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 19:53:00.801725 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 19:53:00.805000 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 19:53:00.811794 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 19:53:00.811876 Total UI for P1: 0, mck2ui 16
6507 19:53:00.818759 best dqsien dly found for B0: ( 0, 14, 24)
6508 19:53:00.818841 Total UI for P1: 0, mck2ui 16
6509 19:53:00.825084 best dqsien dly found for B1: ( 0, 14, 24)
6510 19:53:00.828683 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6511 19:53:00.831666 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6512 19:53:00.831734
6513 19:53:00.835319 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6514 19:53:00.838317 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 19:53:00.841731 [Gating] SW calibration Done
6516 19:53:00.841803 ==
6517 19:53:00.844777 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 19:53:00.848369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 19:53:00.848447 ==
6520 19:53:00.851794 RX Vref Scan: 0
6521 19:53:00.851867
6522 19:53:00.851927 RX Vref 0 -> 0, step: 1
6523 19:53:00.851984
6524 19:53:00.854874 RX Delay -410 -> 252, step: 16
6525 19:53:00.861954 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6526 19:53:00.865248 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6527 19:53:00.868520 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6528 19:53:00.871518 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6529 19:53:00.878018 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6530 19:53:00.881665 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6531 19:53:00.885133 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6532 19:53:00.887900 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6533 19:53:00.894929 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6534 19:53:00.898242 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6535 19:53:00.901236 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6536 19:53:00.904661 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6537 19:53:00.911449 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6538 19:53:00.914940 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6539 19:53:00.917870 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6540 19:53:00.924401 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6541 19:53:00.924483 ==
6542 19:53:00.928060 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 19:53:00.931031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 19:53:00.931113 ==
6545 19:53:00.931177 DQS Delay:
6546 19:53:00.934576 DQS0 = 59, DQS1 = 59
6547 19:53:00.934646 DQM Delay:
6548 19:53:00.938093 DQM0 = 16, DQM1 = 10
6549 19:53:00.938173 DQ Delay:
6550 19:53:00.941521 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6551 19:53:00.944608 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6552 19:53:00.947627 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6553 19:53:00.951123 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6554 19:53:00.951205
6555 19:53:00.951268
6556 19:53:00.951326 ==
6557 19:53:00.954735 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 19:53:00.957654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 19:53:00.957736 ==
6560 19:53:00.957800
6561 19:53:00.957859
6562 19:53:00.961224 TX Vref Scan disable
6563 19:53:00.964193 == TX Byte 0 ==
6564 19:53:00.967834 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6565 19:53:00.970813 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6566 19:53:00.970898 == TX Byte 1 ==
6567 19:53:00.977721 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6568 19:53:00.980659 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6569 19:53:00.980732 ==
6570 19:53:00.984323 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 19:53:00.987576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 19:53:00.987653 ==
6573 19:53:00.987715
6574 19:53:00.990656
6575 19:53:00.990737 TX Vref Scan disable
6576 19:53:00.993833 == TX Byte 0 ==
6577 19:53:00.997388 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6578 19:53:01.000493 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6579 19:53:01.003813 == TX Byte 1 ==
6580 19:53:01.007294 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6581 19:53:01.010550 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6582 19:53:01.010631
6583 19:53:01.010709 [DATLAT]
6584 19:53:01.013626 Freq=400, CH0 RK1
6585 19:53:01.013725
6586 19:53:01.017426 DATLAT Default: 0xe
6587 19:53:01.017506 0, 0xFFFF, sum = 0
6588 19:53:01.020621 1, 0xFFFF, sum = 0
6589 19:53:01.020703 2, 0xFFFF, sum = 0
6590 19:53:01.023995 3, 0xFFFF, sum = 0
6591 19:53:01.024077 4, 0xFFFF, sum = 0
6592 19:53:01.026749 5, 0xFFFF, sum = 0
6593 19:53:01.026847 6, 0xFFFF, sum = 0
6594 19:53:01.030168 7, 0xFFFF, sum = 0
6595 19:53:01.030250 8, 0xFFFF, sum = 0
6596 19:53:01.033878 9, 0xFFFF, sum = 0
6597 19:53:01.033993 10, 0xFFFF, sum = 0
6598 19:53:01.037144 11, 0xFFFF, sum = 0
6599 19:53:01.037226 12, 0xFFFF, sum = 0
6600 19:53:01.040097 13, 0x0, sum = 1
6601 19:53:01.040179 14, 0x0, sum = 2
6602 19:53:01.043360 15, 0x0, sum = 3
6603 19:53:01.043483 16, 0x0, sum = 4
6604 19:53:01.047095 best_step = 14
6605 19:53:01.047190
6606 19:53:01.047255 ==
6607 19:53:01.050236 Dram Type= 6, Freq= 0, CH_0, rank 1
6608 19:53:01.053520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 19:53:01.053619 ==
6610 19:53:01.057077 RX Vref Scan: 0
6611 19:53:01.057175
6612 19:53:01.057271 RX Vref 0 -> 0, step: 1
6613 19:53:01.057346
6614 19:53:01.059881 RX Delay -359 -> 252, step: 8
6615 19:53:01.067822 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6616 19:53:01.071405 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6617 19:53:01.074370 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6618 19:53:01.077926 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6619 19:53:01.084192 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6620 19:53:01.087897 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6621 19:53:01.091091 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6622 19:53:01.094245 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6623 19:53:01.101102 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6624 19:53:01.104181 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6625 19:53:01.107458 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6626 19:53:01.113934 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6627 19:53:01.117550 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6628 19:53:01.120916 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6629 19:53:01.123881 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6630 19:53:01.130767 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6631 19:53:01.130841 ==
6632 19:53:01.133978 Dram Type= 6, Freq= 0, CH_0, rank 1
6633 19:53:01.137203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 19:53:01.137303 ==
6635 19:53:01.137368 DQS Delay:
6636 19:53:01.141043 DQS0 = 60, DQS1 = 72
6637 19:53:01.141179 DQM Delay:
6638 19:53:01.144010 DQM0 = 11, DQM1 = 17
6639 19:53:01.144086 DQ Delay:
6640 19:53:01.147108 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6641 19:53:01.150548 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6642 19:53:01.154156 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6643 19:53:01.157470 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6644 19:53:01.157568
6645 19:53:01.157656
6646 19:53:01.164142 [DQSOSCAuto] RK1, (LSB)MR18= 0xc87b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6647 19:53:01.166947 CH0 RK1: MR19=C0C, MR18=C87B
6648 19:53:01.173992 CH0_RK1: MR19=0xC0C, MR18=0xC87B, DQSOSC=385, MR23=63, INC=398, DEC=265
6649 19:53:01.176992 [RxdqsGatingPostProcess] freq 400
6650 19:53:01.183575 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6651 19:53:01.187067 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 19:53:01.187146 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 19:53:01.190424 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 19:53:01.193510 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 19:53:01.197374 best DQS0 dly(2T, 0.5T) = (0, 10)
6656 19:53:01.200331 best DQS1 dly(2T, 0.5T) = (0, 10)
6657 19:53:01.203418 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6658 19:53:01.206877 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6659 19:53:01.210321 Pre-setting of DQS Precalculation
6660 19:53:01.216840 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6661 19:53:01.216922 ==
6662 19:53:01.219944 Dram Type= 6, Freq= 0, CH_1, rank 0
6663 19:53:01.223723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 19:53:01.223802 ==
6665 19:53:01.230154 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6666 19:53:01.233210 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6667 19:53:01.236837 [CA 0] Center 36 (8~64) winsize 57
6668 19:53:01.239997 [CA 1] Center 36 (8~64) winsize 57
6669 19:53:01.243509 [CA 2] Center 36 (8~64) winsize 57
6670 19:53:01.246394 [CA 3] Center 36 (8~64) winsize 57
6671 19:53:01.249740 [CA 4] Center 36 (8~64) winsize 57
6672 19:53:01.252964 [CA 5] Center 36 (8~64) winsize 57
6673 19:53:01.253037
6674 19:53:01.256183 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6675 19:53:01.256258
6676 19:53:01.259920 [CATrainingPosCal] consider 1 rank data
6677 19:53:01.262907 u2DelayCellTimex100 = 270/100 ps
6678 19:53:01.266585 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 19:53:01.269467 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 19:53:01.276189 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 19:53:01.279634 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 19:53:01.282816 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 19:53:01.286459 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 19:53:01.286544
6685 19:53:01.289379 CA PerBit enable=1, Macro0, CA PI delay=36
6686 19:53:01.289466
6687 19:53:01.292894 [CBTSetCACLKResult] CA Dly = 36
6688 19:53:01.292976 CS Dly: 1 (0~32)
6689 19:53:01.296290 ==
6690 19:53:01.296391 Dram Type= 6, Freq= 0, CH_1, rank 1
6691 19:53:01.302769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 19:53:01.302850 ==
6693 19:53:01.306078 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6694 19:53:01.312688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6695 19:53:01.316238 [CA 0] Center 36 (8~64) winsize 57
6696 19:53:01.319323 [CA 1] Center 36 (8~64) winsize 57
6697 19:53:01.322983 [CA 2] Center 36 (8~64) winsize 57
6698 19:53:01.326015 [CA 3] Center 36 (8~64) winsize 57
6699 19:53:01.329432 [CA 4] Center 36 (8~64) winsize 57
6700 19:53:01.332937 [CA 5] Center 36 (8~64) winsize 57
6701 19:53:01.333018
6702 19:53:01.335970 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6703 19:53:01.336054
6704 19:53:01.339326 [CATrainingPosCal] consider 2 rank data
6705 19:53:01.342818 u2DelayCellTimex100 = 270/100 ps
6706 19:53:01.346311 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 19:53:01.349429 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 19:53:01.352719 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 19:53:01.355700 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 19:53:01.362727 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 19:53:01.365655 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 19:53:01.365736
6713 19:53:01.369462 CA PerBit enable=1, Macro0, CA PI delay=36
6714 19:53:01.369542
6715 19:53:01.372403 [CBTSetCACLKResult] CA Dly = 36
6716 19:53:01.372484 CS Dly: 1 (0~32)
6717 19:53:01.372548
6718 19:53:01.375849 ----->DramcWriteLeveling(PI) begin...
6719 19:53:01.375931 ==
6720 19:53:01.378996 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 19:53:01.385480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 19:53:01.385561 ==
6723 19:53:01.389176 Write leveling (Byte 0): 40 => 8
6724 19:53:01.389257 Write leveling (Byte 1): 40 => 8
6725 19:53:01.392082 DramcWriteLeveling(PI) end<-----
6726 19:53:01.392162
6727 19:53:01.392250 ==
6728 19:53:01.395742 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 19:53:01.402483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 19:53:01.402565 ==
6731 19:53:01.405572 [Gating] SW mode calibration
6732 19:53:01.412059 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6733 19:53:01.415640 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6734 19:53:01.422536 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6735 19:53:01.425419 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6736 19:53:01.429181 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6737 19:53:01.435495 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 19:53:01.438936 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 19:53:01.442023 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 19:53:01.448581 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 19:53:01.452560 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 19:53:01.455401 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 19:53:01.458627 Total UI for P1: 0, mck2ui 16
6744 19:53:01.462159 best dqsien dly found for B0: ( 0, 14, 24)
6745 19:53:01.465066 Total UI for P1: 0, mck2ui 16
6746 19:53:01.468838 best dqsien dly found for B1: ( 0, 14, 24)
6747 19:53:01.472110 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6748 19:53:01.475119 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6749 19:53:01.475203
6750 19:53:01.478727 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6751 19:53:01.485070 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 19:53:01.485150 [Gating] SW calibration Done
6753 19:53:01.488726 ==
6754 19:53:01.491858 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 19:53:01.495112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 19:53:01.495185 ==
6757 19:53:01.495248 RX Vref Scan: 0
6758 19:53:01.495308
6759 19:53:01.498109 RX Vref 0 -> 0, step: 1
6760 19:53:01.498173
6761 19:53:01.501433 RX Delay -410 -> 252, step: 16
6762 19:53:01.504940 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6763 19:53:01.508496 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6764 19:53:01.515111 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6765 19:53:01.518643 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6766 19:53:01.521202 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6767 19:53:01.525070 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6768 19:53:01.531166 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6769 19:53:01.534547 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6770 19:53:01.538276 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6771 19:53:01.541075 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6772 19:53:01.548051 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6773 19:53:01.551203 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6774 19:53:01.554735 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6775 19:53:01.561133 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6776 19:53:01.564437 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6777 19:53:01.567868 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6778 19:53:01.567942 ==
6779 19:53:01.571298 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 19:53:01.574341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 19:53:01.577727 ==
6782 19:53:01.577798 DQS Delay:
6783 19:53:01.577857 DQS0 = 51, DQS1 = 67
6784 19:53:01.581251 DQM Delay:
6785 19:53:01.581321 DQM0 = 13, DQM1 = 18
6786 19:53:01.584497 DQ Delay:
6787 19:53:01.584584 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6788 19:53:01.587698 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6789 19:53:01.591539 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6790 19:53:01.595192 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6791 19:53:01.595272
6792 19:53:01.595337
6793 19:53:01.595404 ==
6794 19:53:01.597986 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 19:53:01.604336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 19:53:01.604411 ==
6797 19:53:01.604494
6798 19:53:01.604592
6799 19:53:01.607819 TX Vref Scan disable
6800 19:53:01.607888 == TX Byte 0 ==
6801 19:53:01.611373 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 19:53:01.617354 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 19:53:01.617432 == TX Byte 1 ==
6804 19:53:01.620869 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 19:53:01.624344 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 19:53:01.627604 ==
6807 19:53:01.631027 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 19:53:01.634137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 19:53:01.634208 ==
6810 19:53:01.634270
6811 19:53:01.634325
6812 19:53:01.637374 TX Vref Scan disable
6813 19:53:01.637443 == TX Byte 0 ==
6814 19:53:01.640651 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 19:53:01.647423 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 19:53:01.647508 == TX Byte 1 ==
6817 19:53:01.650722 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6818 19:53:01.657652 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6819 19:53:01.657730
6820 19:53:01.657797 [DATLAT]
6821 19:53:01.657858 Freq=400, CH1 RK0
6822 19:53:01.657915
6823 19:53:01.660683 DATLAT Default: 0xf
6824 19:53:01.660752 0, 0xFFFF, sum = 0
6825 19:53:01.664201 1, 0xFFFF, sum = 0
6826 19:53:01.664270 2, 0xFFFF, sum = 0
6827 19:53:01.667223 3, 0xFFFF, sum = 0
6828 19:53:01.670651 4, 0xFFFF, sum = 0
6829 19:53:01.670721 5, 0xFFFF, sum = 0
6830 19:53:01.673980 6, 0xFFFF, sum = 0
6831 19:53:01.674049 7, 0xFFFF, sum = 0
6832 19:53:01.677791 8, 0xFFFF, sum = 0
6833 19:53:01.677860 9, 0xFFFF, sum = 0
6834 19:53:01.680950 10, 0xFFFF, sum = 0
6835 19:53:01.681018 11, 0xFFFF, sum = 0
6836 19:53:01.684384 12, 0xFFFF, sum = 0
6837 19:53:01.684457 13, 0x0, sum = 1
6838 19:53:01.687398 14, 0x0, sum = 2
6839 19:53:01.687499 15, 0x0, sum = 3
6840 19:53:01.690926 16, 0x0, sum = 4
6841 19:53:01.691008 best_step = 14
6842 19:53:01.691072
6843 19:53:01.691131 ==
6844 19:53:01.694180 Dram Type= 6, Freq= 0, CH_1, rank 0
6845 19:53:01.697412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 19:53:01.697490 ==
6847 19:53:01.700642 RX Vref Scan: 1
6848 19:53:01.700711
6849 19:53:01.704235 RX Vref 0 -> 0, step: 1
6850 19:53:01.704304
6851 19:53:01.704367 RX Delay -375 -> 252, step: 8
6852 19:53:01.707544
6853 19:53:01.707614 Set Vref, RX VrefLevel [Byte0]: 57
6854 19:53:01.710492 [Byte1]: 47
6855 19:53:01.716397
6856 19:53:01.716475 Final RX Vref Byte 0 = 57 to rank0
6857 19:53:01.719458 Final RX Vref Byte 1 = 47 to rank0
6858 19:53:01.722827 Final RX Vref Byte 0 = 57 to rank1
6859 19:53:01.725938 Final RX Vref Byte 1 = 47 to rank1==
6860 19:53:01.729944 Dram Type= 6, Freq= 0, CH_1, rank 0
6861 19:53:01.736065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 19:53:01.736173 ==
6863 19:53:01.736236 DQS Delay:
6864 19:53:01.739356 DQS0 = 56, DQS1 = 68
6865 19:53:01.739463 DQM Delay:
6866 19:53:01.739523 DQM0 = 13, DQM1 = 14
6867 19:53:01.742918 DQ Delay:
6868 19:53:01.746374 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6869 19:53:01.746445 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6870 19:53:01.749287 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6871 19:53:01.752937 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6872 19:53:01.753007
6873 19:53:01.755952
6874 19:53:01.762810 [DQSOSCAuto] RK0, (LSB)MR18= 0x586c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6875 19:53:01.766311 CH1 RK0: MR19=C0C, MR18=586C
6876 19:53:01.772843 CH1_RK0: MR19=0xC0C, MR18=0x586C, DQSOSC=396, MR23=63, INC=376, DEC=251
6877 19:53:01.772919 ==
6878 19:53:01.775722 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 19:53:01.779192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 19:53:01.779270 ==
6881 19:53:01.782815 [Gating] SW mode calibration
6882 19:53:01.788862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6883 19:53:01.795839 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6884 19:53:01.799232 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6885 19:53:01.802716 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 19:53:01.809175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6887 19:53:01.812811 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 19:53:01.816174 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 19:53:01.819067 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 19:53:01.825725 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 19:53:01.829283 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 19:53:01.832645 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 19:53:01.836258 Total UI for P1: 0, mck2ui 16
6894 19:53:01.839425 best dqsien dly found for B0: ( 0, 14, 24)
6895 19:53:01.842368 Total UI for P1: 0, mck2ui 16
6896 19:53:01.845667 best dqsien dly found for B1: ( 0, 14, 24)
6897 19:53:01.849058 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6898 19:53:01.855760 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6899 19:53:01.855841
6900 19:53:01.859076 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6901 19:53:01.862321 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 19:53:01.865875 [Gating] SW calibration Done
6903 19:53:01.865956 ==
6904 19:53:01.869185 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 19:53:01.872087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 19:53:01.872168 ==
6907 19:53:01.875753 RX Vref Scan: 0
6908 19:53:01.875834
6909 19:53:01.875898 RX Vref 0 -> 0, step: 1
6910 19:53:01.875958
6911 19:53:01.878911 RX Delay -410 -> 252, step: 16
6912 19:53:01.882097 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6913 19:53:01.888691 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6914 19:53:01.892022 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6915 19:53:01.895318 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6916 19:53:01.898571 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6917 19:53:01.905534 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6918 19:53:01.908636 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6919 19:53:01.912449 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6920 19:53:01.915328 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6921 19:53:01.921824 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6922 19:53:01.925359 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6923 19:53:01.928626 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6924 19:53:01.932087 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6925 19:53:01.938809 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6926 19:53:01.941686 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6927 19:53:01.945327 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6928 19:53:01.945409 ==
6929 19:53:01.948231 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 19:53:01.955110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 19:53:01.955191 ==
6932 19:53:01.955255 DQS Delay:
6933 19:53:01.958698 DQS0 = 59, DQS1 = 59
6934 19:53:01.958779 DQM Delay:
6935 19:53:01.958843 DQM0 = 19, DQM1 = 12
6936 19:53:01.962221 DQ Delay:
6937 19:53:01.965030 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6938 19:53:01.968173 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6939 19:53:01.971624 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6940 19:53:01.974883 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6941 19:53:01.974959
6942 19:53:01.975022
6943 19:53:01.975084 ==
6944 19:53:01.978245 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 19:53:01.981388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 19:53:01.981459 ==
6947 19:53:01.981518
6948 19:53:01.981575
6949 19:53:01.984920 TX Vref Scan disable
6950 19:53:01.985007 == TX Byte 0 ==
6951 19:53:01.991362 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6952 19:53:01.994787 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6953 19:53:01.994868 == TX Byte 1 ==
6954 19:53:01.997885 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6955 19:53:02.005037 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6956 19:53:02.005164 ==
6957 19:53:02.007954 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 19:53:02.011367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 19:53:02.011469 ==
6960 19:53:02.011534
6961 19:53:02.011593
6962 19:53:02.014747 TX Vref Scan disable
6963 19:53:02.014827 == TX Byte 0 ==
6964 19:53:02.021261 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6965 19:53:02.024883 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6966 19:53:02.024967 == TX Byte 1 ==
6967 19:53:02.031425 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6968 19:53:02.034844 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6969 19:53:02.034924
6970 19:53:02.035019 [DATLAT]
6971 19:53:02.038080 Freq=400, CH1 RK1
6972 19:53:02.038161
6973 19:53:02.038224 DATLAT Default: 0xe
6974 19:53:02.041128 0, 0xFFFF, sum = 0
6975 19:53:02.041211 1, 0xFFFF, sum = 0
6976 19:53:02.044608 2, 0xFFFF, sum = 0
6977 19:53:02.044689 3, 0xFFFF, sum = 0
6978 19:53:02.048227 4, 0xFFFF, sum = 0
6979 19:53:02.048309 5, 0xFFFF, sum = 0
6980 19:53:02.051789 6, 0xFFFF, sum = 0
6981 19:53:02.051871 7, 0xFFFF, sum = 0
6982 19:53:02.054474 8, 0xFFFF, sum = 0
6983 19:53:02.054556 9, 0xFFFF, sum = 0
6984 19:53:02.058138 10, 0xFFFF, sum = 0
6985 19:53:02.058220 11, 0xFFFF, sum = 0
6986 19:53:02.061112 12, 0xFFFF, sum = 0
6987 19:53:02.061194 13, 0x0, sum = 1
6988 19:53:02.064793 14, 0x0, sum = 2
6989 19:53:02.064875 15, 0x0, sum = 3
6990 19:53:02.067814 16, 0x0, sum = 4
6991 19:53:02.067895 best_step = 14
6992 19:53:02.067959
6993 19:53:02.068018 ==
6994 19:53:02.071399 Dram Type= 6, Freq= 0, CH_1, rank 1
6995 19:53:02.078171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6996 19:53:02.078253 ==
6997 19:53:02.078324 RX Vref Scan: 0
6998 19:53:02.078394
6999 19:53:02.081728 RX Vref 0 -> 0, step: 1
7000 19:53:02.081809
7001 19:53:02.084583 RX Delay -359 -> 252, step: 8
7002 19:53:02.091263 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7003 19:53:02.094669 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7004 19:53:02.097803 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7005 19:53:02.101408 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7006 19:53:02.107776 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
7007 19:53:02.111064 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7008 19:53:02.114074 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7009 19:53:02.117543 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7010 19:53:02.124084 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7011 19:53:02.127585 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7012 19:53:02.130895 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7013 19:53:02.134204 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7014 19:53:02.140726 iDelay=217, Bit 12, Center -44 (-295 ~ 208) 504
7015 19:53:02.143851 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7016 19:53:02.147306 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7017 19:53:02.154212 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7018 19:53:02.154293 ==
7019 19:53:02.157362 Dram Type= 6, Freq= 0, CH_1, rank 1
7020 19:53:02.160758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7021 19:53:02.160839 ==
7022 19:53:02.160903 DQS Delay:
7023 19:53:02.164289 DQS0 = 60, DQS1 = 64
7024 19:53:02.164370 DQM Delay:
7025 19:53:02.167509 DQM0 = 13, DQM1 = 11
7026 19:53:02.167589 DQ Delay:
7027 19:53:02.170631 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7028 19:53:02.174196 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7029 19:53:02.177200 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7030 19:53:02.180629 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7031 19:53:02.180710
7032 19:53:02.180774
7033 19:53:02.187484 [DQSOSCAuto] RK1, (LSB)MR18= 0x7eae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 393 ps
7034 19:53:02.190527 CH1 RK1: MR19=C0C, MR18=7EAE
7035 19:53:02.197495 CH1_RK1: MR19=0xC0C, MR18=0x7EAE, DQSOSC=388, MR23=63, INC=392, DEC=261
7036 19:53:02.200483 [RxdqsGatingPostProcess] freq 400
7037 19:53:02.207183 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7038 19:53:02.207263 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 19:53:02.210581 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 19:53:02.213815 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 19:53:02.217243 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 19:53:02.220406 best DQS0 dly(2T, 0.5T) = (0, 10)
7043 19:53:02.223659 best DQS1 dly(2T, 0.5T) = (0, 10)
7044 19:53:02.226836 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7045 19:53:02.230232 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7046 19:53:02.233633 Pre-setting of DQS Precalculation
7047 19:53:02.240503 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7048 19:53:02.247021 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7049 19:53:02.253605 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7050 19:53:02.253686
7051 19:53:02.253750
7052 19:53:02.257145 [Calibration Summary] 800 Mbps
7053 19:53:02.257226 CH 0, Rank 0
7054 19:53:02.260092 SW Impedance : PASS
7055 19:53:02.260172 DUTY Scan : NO K
7056 19:53:02.263440 ZQ Calibration : PASS
7057 19:53:02.267022 Jitter Meter : NO K
7058 19:53:02.267103 CBT Training : PASS
7059 19:53:02.270367 Write leveling : PASS
7060 19:53:02.273904 RX DQS gating : PASS
7061 19:53:02.273985 RX DQ/DQS(RDDQC) : PASS
7062 19:53:02.277172 TX DQ/DQS : PASS
7063 19:53:02.280369 RX DATLAT : PASS
7064 19:53:02.280449 RX DQ/DQS(Engine): PASS
7065 19:53:02.283965 TX OE : NO K
7066 19:53:02.284045 All Pass.
7067 19:53:02.284110
7068 19:53:02.286554 CH 0, Rank 1
7069 19:53:02.286635 SW Impedance : PASS
7070 19:53:02.290119 DUTY Scan : NO K
7071 19:53:02.293678 ZQ Calibration : PASS
7072 19:53:02.293758 Jitter Meter : NO K
7073 19:53:02.296674 CBT Training : PASS
7074 19:53:02.300261 Write leveling : NO K
7075 19:53:02.300342 RX DQS gating : PASS
7076 19:53:02.303263 RX DQ/DQS(RDDQC) : PASS
7077 19:53:02.303343 TX DQ/DQS : PASS
7078 19:53:02.307004 RX DATLAT : PASS
7079 19:53:02.309914 RX DQ/DQS(Engine): PASS
7080 19:53:02.309995 TX OE : NO K
7081 19:53:02.313491 All Pass.
7082 19:53:02.313571
7083 19:53:02.313635 CH 1, Rank 0
7084 19:53:02.317113 SW Impedance : PASS
7085 19:53:02.317194 DUTY Scan : NO K
7086 19:53:02.320009 ZQ Calibration : PASS
7087 19:53:02.323572 Jitter Meter : NO K
7088 19:53:02.323652 CBT Training : PASS
7089 19:53:02.327032 Write leveling : PASS
7090 19:53:02.330132 RX DQS gating : PASS
7091 19:53:02.330212 RX DQ/DQS(RDDQC) : PASS
7092 19:53:02.333574 TX DQ/DQS : PASS
7093 19:53:02.337120 RX DATLAT : PASS
7094 19:53:02.337200 RX DQ/DQS(Engine): PASS
7095 19:53:02.339870 TX OE : NO K
7096 19:53:02.339951 All Pass.
7097 19:53:02.340014
7098 19:53:02.343165 CH 1, Rank 1
7099 19:53:02.343245 SW Impedance : PASS
7100 19:53:02.347084 DUTY Scan : NO K
7101 19:53:02.350095 ZQ Calibration : PASS
7102 19:53:02.350176 Jitter Meter : NO K
7103 19:53:02.353632 CBT Training : PASS
7104 19:53:02.356492 Write leveling : NO K
7105 19:53:02.356573 RX DQS gating : PASS
7106 19:53:02.360369 RX DQ/DQS(RDDQC) : PASS
7107 19:53:02.360450 TX DQ/DQS : PASS
7108 19:53:02.363277 RX DATLAT : PASS
7109 19:53:02.366900 RX DQ/DQS(Engine): PASS
7110 19:53:02.366981 TX OE : NO K
7111 19:53:02.369671 All Pass.
7112 19:53:02.369751
7113 19:53:02.369814 DramC Write-DBI off
7114 19:53:02.373008 PER_BANK_REFRESH: Hybrid Mode
7115 19:53:02.376839 TX_TRACKING: ON
7116 19:53:02.382753 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7117 19:53:02.386724 [FAST_K] Save calibration result to emmc
7118 19:53:02.392977 dramc_set_vcore_voltage set vcore to 725000
7119 19:53:02.393057 Read voltage for 1600, 0
7120 19:53:02.393121 Vio18 = 0
7121 19:53:02.396263 Vcore = 725000
7122 19:53:02.396343 Vdram = 0
7123 19:53:02.396406 Vddq = 0
7124 19:53:02.399538 Vmddr = 0
7125 19:53:02.402869 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7126 19:53:02.409665 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7127 19:53:02.412846 MEM_TYPE=3, freq_sel=13
7128 19:53:02.416323 sv_algorithm_assistance_LP4_3733
7129 19:53:02.419058 ============ PULL DRAM RESETB DOWN ============
7130 19:53:02.422713 ========== PULL DRAM RESETB DOWN end =========
7131 19:53:02.425729 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7132 19:53:02.429016 ===================================
7133 19:53:02.432600 LPDDR4 DRAM CONFIGURATION
7134 19:53:02.435560 ===================================
7135 19:53:02.438970 EX_ROW_EN[0] = 0x0
7136 19:53:02.439051 EX_ROW_EN[1] = 0x0
7137 19:53:02.442357 LP4Y_EN = 0x0
7138 19:53:02.442438 WORK_FSP = 0x1
7139 19:53:02.445632 WL = 0x5
7140 19:53:02.445713 RL = 0x5
7141 19:53:02.448990 BL = 0x2
7142 19:53:02.449070 RPST = 0x0
7143 19:53:02.452477 RD_PRE = 0x0
7144 19:53:02.452557 WR_PRE = 0x1
7145 19:53:02.455626 WR_PST = 0x1
7146 19:53:02.459293 DBI_WR = 0x0
7147 19:53:02.459374 DBI_RD = 0x0
7148 19:53:02.462173 OTF = 0x1
7149 19:53:02.465513 ===================================
7150 19:53:02.468961 ===================================
7151 19:53:02.469041 ANA top config
7152 19:53:02.471853 ===================================
7153 19:53:02.475512 DLL_ASYNC_EN = 0
7154 19:53:02.478423 ALL_SLAVE_EN = 0
7155 19:53:02.478493 NEW_RANK_MODE = 1
7156 19:53:02.481625 DLL_IDLE_MODE = 1
7157 19:53:02.485500 LP45_APHY_COMB_EN = 1
7158 19:53:02.488443 TX_ODT_DIS = 0
7159 19:53:02.488518 NEW_8X_MODE = 1
7160 19:53:02.491620 ===================================
7161 19:53:02.495334 ===================================
7162 19:53:02.499019 data_rate = 3200
7163 19:53:02.501956 CKR = 1
7164 19:53:02.504885 DQ_P2S_RATIO = 8
7165 19:53:02.508688 ===================================
7166 19:53:02.511574 CA_P2S_RATIO = 8
7167 19:53:02.514876 DQ_CA_OPEN = 0
7168 19:53:02.518163 DQ_SEMI_OPEN = 0
7169 19:53:02.518232 CA_SEMI_OPEN = 0
7170 19:53:02.521630 CA_FULL_RATE = 0
7171 19:53:02.525189 DQ_CKDIV4_EN = 0
7172 19:53:02.527982 CA_CKDIV4_EN = 0
7173 19:53:02.531518 CA_PREDIV_EN = 0
7174 19:53:02.535141 PH8_DLY = 12
7175 19:53:02.535214 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7176 19:53:02.538044 DQ_AAMCK_DIV = 4
7177 19:53:02.541583 CA_AAMCK_DIV = 4
7178 19:53:02.544959 CA_ADMCK_DIV = 4
7179 19:53:02.548088 DQ_TRACK_CA_EN = 0
7180 19:53:02.551530 CA_PICK = 1600
7181 19:53:02.554722 CA_MCKIO = 1600
7182 19:53:02.554789 MCKIO_SEMI = 0
7183 19:53:02.557925 PLL_FREQ = 3068
7184 19:53:02.561489 DQ_UI_PI_RATIO = 32
7185 19:53:02.564831 CA_UI_PI_RATIO = 0
7186 19:53:02.568090 ===================================
7187 19:53:02.571321 ===================================
7188 19:53:02.574840 memory_type:LPDDR4
7189 19:53:02.574911 GP_NUM : 10
7190 19:53:02.577902 SRAM_EN : 1
7191 19:53:02.577968 MD32_EN : 0
7192 19:53:02.581534 ===================================
7193 19:53:02.584547 [ANA_INIT] >>>>>>>>>>>>>>
7194 19:53:02.587880 <<<<<< [CONFIGURE PHASE]: ANA_TX
7195 19:53:02.591173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7196 19:53:02.594918 ===================================
7197 19:53:02.597959 data_rate = 3200,PCW = 0X7600
7198 19:53:02.601174 ===================================
7199 19:53:02.604740 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7200 19:53:02.611028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7201 19:53:02.614795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 19:53:02.621358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7203 19:53:02.624474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7204 19:53:02.627802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7205 19:53:02.627882 [ANA_INIT] flow start
7206 19:53:02.631151 [ANA_INIT] PLL >>>>>>>>
7207 19:53:02.634730 [ANA_INIT] PLL <<<<<<<<
7208 19:53:02.634811 [ANA_INIT] MIDPI >>>>>>>>
7209 19:53:02.637851 [ANA_INIT] MIDPI <<<<<<<<
7210 19:53:02.641086 [ANA_INIT] DLL >>>>>>>>
7211 19:53:02.641166 [ANA_INIT] DLL <<<<<<<<
7212 19:53:02.644689 [ANA_INIT] flow end
7213 19:53:02.647578 ============ LP4 DIFF to SE enter ============
7214 19:53:02.654525 ============ LP4 DIFF to SE exit ============
7215 19:53:02.654607 [ANA_INIT] <<<<<<<<<<<<<
7216 19:53:02.657530 [Flow] Enable top DCM control >>>>>
7217 19:53:02.660870 [Flow] Enable top DCM control <<<<<
7218 19:53:02.664259 Enable DLL master slave shuffle
7219 19:53:02.671067 ==============================================================
7220 19:53:02.671148 Gating Mode config
7221 19:53:02.677350 ==============================================================
7222 19:53:02.681078 Config description:
7223 19:53:02.687624 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7224 19:53:02.694209 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7225 19:53:02.700945 SELPH_MODE 0: By rank 1: By Phase
7226 19:53:02.707458 ==============================================================
7227 19:53:02.710966 GAT_TRACK_EN = 1
7228 19:53:02.711047 RX_GATING_MODE = 2
7229 19:53:02.714014 RX_GATING_TRACK_MODE = 2
7230 19:53:02.717373 SELPH_MODE = 1
7231 19:53:02.720462 PICG_EARLY_EN = 1
7232 19:53:02.723726 VALID_LAT_VALUE = 1
7233 19:53:02.730957 ==============================================================
7234 19:53:02.733985 Enter into Gating configuration >>>>
7235 19:53:02.737450 Exit from Gating configuration <<<<
7236 19:53:02.740673 Enter into DVFS_PRE_config >>>>>
7237 19:53:02.750663 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7238 19:53:02.754210 Exit from DVFS_PRE_config <<<<<
7239 19:53:02.756984 Enter into PICG configuration >>>>
7240 19:53:02.760683 Exit from PICG configuration <<<<
7241 19:53:02.763598 [RX_INPUT] configuration >>>>>
7242 19:53:02.767117 [RX_INPUT] configuration <<<<<
7243 19:53:02.770567 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7244 19:53:02.777249 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7245 19:53:02.783553 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7246 19:53:02.786827 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7247 19:53:02.793573 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7248 19:53:02.799974 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7249 19:53:02.803635 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7250 19:53:02.809893 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7251 19:53:02.813334 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7252 19:53:02.816381 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7253 19:53:02.819792 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7254 19:53:02.826589 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 19:53:02.830150 ===================================
7256 19:53:02.830231 LPDDR4 DRAM CONFIGURATION
7257 19:53:02.833479 ===================================
7258 19:53:02.836644 EX_ROW_EN[0] = 0x0
7259 19:53:02.840296 EX_ROW_EN[1] = 0x0
7260 19:53:02.840377 LP4Y_EN = 0x0
7261 19:53:02.842965 WORK_FSP = 0x1
7262 19:53:02.843045 WL = 0x5
7263 19:53:02.846617 RL = 0x5
7264 19:53:02.846698 BL = 0x2
7265 19:53:02.849721 RPST = 0x0
7266 19:53:02.849801 RD_PRE = 0x0
7267 19:53:02.853192 WR_PRE = 0x1
7268 19:53:02.853273 WR_PST = 0x1
7269 19:53:02.856486 DBI_WR = 0x0
7270 19:53:02.856567 DBI_RD = 0x0
7271 19:53:02.859934 OTF = 0x1
7272 19:53:02.862954 ===================================
7273 19:53:02.866592 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7274 19:53:02.869638 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7275 19:53:02.876141 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7276 19:53:02.879362 ===================================
7277 19:53:02.879467 LPDDR4 DRAM CONFIGURATION
7278 19:53:02.882820 ===================================
7279 19:53:02.886382 EX_ROW_EN[0] = 0x10
7280 19:53:02.889375 EX_ROW_EN[1] = 0x0
7281 19:53:02.889456 LP4Y_EN = 0x0
7282 19:53:02.892653 WORK_FSP = 0x1
7283 19:53:02.892733 WL = 0x5
7284 19:53:02.895989 RL = 0x5
7285 19:53:02.896070 BL = 0x2
7286 19:53:02.899428 RPST = 0x0
7287 19:53:02.899508 RD_PRE = 0x0
7288 19:53:02.903076 WR_PRE = 0x1
7289 19:53:02.903156 WR_PST = 0x1
7290 19:53:02.905942 DBI_WR = 0x0
7291 19:53:02.906023 DBI_RD = 0x0
7292 19:53:02.909271 OTF = 0x1
7293 19:53:02.912934 ===================================
7294 19:53:02.919417 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7295 19:53:02.919512 ==
7296 19:53:02.922958 Dram Type= 6, Freq= 0, CH_0, rank 0
7297 19:53:02.925703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 19:53:02.925785 ==
7299 19:53:02.929493 [Duty_Offset_Calibration]
7300 19:53:02.929574 B0:2 B1:0 CA:3
7301 19:53:02.929637
7302 19:53:02.932709 [DutyScan_Calibration_Flow] k_type=0
7303 19:53:02.943356
7304 19:53:02.943461 ==CLK 0==
7305 19:53:02.946320 Final CLK duty delay cell = 0
7306 19:53:02.949915 [0] MAX Duty = 5031%(X100), DQS PI = 12
7307 19:53:02.953301 [0] MIN Duty = 4907%(X100), DQS PI = 6
7308 19:53:02.953382 [0] AVG Duty = 4969%(X100)
7309 19:53:02.956396
7310 19:53:02.959910 CH0 CLK Duty spec in!! Max-Min= 124%
7311 19:53:02.963222 [DutyScan_Calibration_Flow] ====Done====
7312 19:53:02.963302
7313 19:53:02.966860 [DutyScan_Calibration_Flow] k_type=1
7314 19:53:02.982811
7315 19:53:02.982894 ==DQS 0 ==
7316 19:53:02.986318 Final DQS duty delay cell = 0
7317 19:53:02.989600 [0] MAX Duty = 5094%(X100), DQS PI = 12
7318 19:53:02.993104 [0] MIN Duty = 4875%(X100), DQS PI = 48
7319 19:53:02.996244 [0] AVG Duty = 4984%(X100)
7320 19:53:02.996325
7321 19:53:02.996389 ==DQS 1 ==
7322 19:53:02.999663 Final DQS duty delay cell = 0
7323 19:53:03.002974 [0] MAX Duty = 5156%(X100), DQS PI = 32
7324 19:53:03.006419 [0] MIN Duty = 5031%(X100), DQS PI = 14
7325 19:53:03.009328 [0] AVG Duty = 5093%(X100)
7326 19:53:03.009409
7327 19:53:03.012580 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7328 19:53:03.012662
7329 19:53:03.016625 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7330 19:53:03.019547 [DutyScan_Calibration_Flow] ====Done====
7331 19:53:03.019627
7332 19:53:03.023012 [DutyScan_Calibration_Flow] k_type=3
7333 19:53:03.040466
7334 19:53:03.040547 ==DQM 0 ==
7335 19:53:03.043311 Final DQM duty delay cell = 0
7336 19:53:03.046853 [0] MAX Duty = 5156%(X100), DQS PI = 28
7337 19:53:03.050068 [0] MIN Duty = 4875%(X100), DQS PI = 48
7338 19:53:03.053387 [0] AVG Duty = 5015%(X100)
7339 19:53:03.053468
7340 19:53:03.053531 ==DQM 1 ==
7341 19:53:03.057026 Final DQM duty delay cell = 0
7342 19:53:03.059973 [0] MAX Duty = 4938%(X100), DQS PI = 50
7343 19:53:03.063576 [0] MIN Duty = 4813%(X100), DQS PI = 18
7344 19:53:03.066582 [0] AVG Duty = 4875%(X100)
7345 19:53:03.066663
7346 19:53:03.069903 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7347 19:53:03.069984
7348 19:53:03.073425 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7349 19:53:03.076531 [DutyScan_Calibration_Flow] ====Done====
7350 19:53:03.076611
7351 19:53:03.080119 [DutyScan_Calibration_Flow] k_type=2
7352 19:53:03.096647
7353 19:53:03.096728 ==DQ 0 ==
7354 19:53:03.100076 Final DQ duty delay cell = -4
7355 19:53:03.103174 [-4] MAX Duty = 5000%(X100), DQS PI = 12
7356 19:53:03.106625 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7357 19:53:03.109683 [-4] AVG Duty = 4938%(X100)
7358 19:53:03.109763
7359 19:53:03.109826 ==DQ 1 ==
7360 19:53:03.112978 Final DQ duty delay cell = 0
7361 19:53:03.116095 [0] MAX Duty = 5156%(X100), DQS PI = 58
7362 19:53:03.119945 [0] MIN Duty = 5000%(X100), DQS PI = 16
7363 19:53:03.122757 [0] AVG Duty = 5078%(X100)
7364 19:53:03.122837
7365 19:53:03.126441 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7366 19:53:03.126522
7367 19:53:03.129388 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7368 19:53:03.132847 [DutyScan_Calibration_Flow] ====Done====
7369 19:53:03.132927 ==
7370 19:53:03.135915 Dram Type= 6, Freq= 0, CH_1, rank 0
7371 19:53:03.139553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7372 19:53:03.139634 ==
7373 19:53:03.142476 [Duty_Offset_Calibration]
7374 19:53:03.142555 B0:1 B1:-2 CA:0
7375 19:53:03.146055
7376 19:53:03.149428 [DutyScan_Calibration_Flow] k_type=0
7377 19:53:03.157436
7378 19:53:03.157515 ==CLK 0==
7379 19:53:03.160839 Final CLK duty delay cell = 0
7380 19:53:03.163792 [0] MAX Duty = 5093%(X100), DQS PI = 30
7381 19:53:03.167463 [0] MIN Duty = 4813%(X100), DQS PI = 62
7382 19:53:03.167544 [0] AVG Duty = 4953%(X100)
7383 19:53:03.170419
7384 19:53:03.173833 CH1 CLK Duty spec in!! Max-Min= 280%
7385 19:53:03.177252 [DutyScan_Calibration_Flow] ====Done====
7386 19:53:03.177332
7387 19:53:03.180784 [DutyScan_Calibration_Flow] k_type=1
7388 19:53:03.196885
7389 19:53:03.196968 ==DQS 0 ==
7390 19:53:03.200148 Final DQS duty delay cell = 0
7391 19:53:03.203814 [0] MAX Duty = 5187%(X100), DQS PI = 22
7392 19:53:03.207033 [0] MIN Duty = 5062%(X100), DQS PI = 0
7393 19:53:03.207114 [0] AVG Duty = 5124%(X100)
7394 19:53:03.210607
7395 19:53:03.210687 ==DQS 1 ==
7396 19:53:03.213845 Final DQS duty delay cell = 0
7397 19:53:03.216787 [0] MAX Duty = 5093%(X100), DQS PI = 60
7398 19:53:03.220521 [0] MIN Duty = 4844%(X100), DQS PI = 24
7399 19:53:03.223299 [0] AVG Duty = 4968%(X100)
7400 19:53:03.223428
7401 19:53:03.226685 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7402 19:53:03.226766
7403 19:53:03.230475 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7404 19:53:03.233488 [DutyScan_Calibration_Flow] ====Done====
7405 19:53:03.233569
7406 19:53:03.236624 [DutyScan_Calibration_Flow] k_type=3
7407 19:53:03.253750
7408 19:53:03.253832 ==DQM 0 ==
7409 19:53:03.257268 Final DQM duty delay cell = 0
7410 19:53:03.260646 [0] MAX Duty = 5031%(X100), DQS PI = 24
7411 19:53:03.263530 [0] MIN Duty = 4813%(X100), DQS PI = 56
7412 19:53:03.267356 [0] AVG Duty = 4922%(X100)
7413 19:53:03.267448
7414 19:53:03.267512 ==DQM 1 ==
7415 19:53:03.270698 Final DQM duty delay cell = 0
7416 19:53:03.273711 [0] MAX Duty = 5062%(X100), DQS PI = 34
7417 19:53:03.276844 [0] MIN Duty = 4875%(X100), DQS PI = 24
7418 19:53:03.280558 [0] AVG Duty = 4968%(X100)
7419 19:53:03.280639
7420 19:53:03.283828 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7421 19:53:03.283909
7422 19:53:03.287352 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7423 19:53:03.290201 [DutyScan_Calibration_Flow] ====Done====
7424 19:53:03.290282
7425 19:53:03.293681 [DutyScan_Calibration_Flow] k_type=2
7426 19:53:03.310874
7427 19:53:03.310955 ==DQ 0 ==
7428 19:53:03.314350 Final DQ duty delay cell = 0
7429 19:53:03.317320 [0] MAX Duty = 5093%(X100), DQS PI = 22
7430 19:53:03.321097 [0] MIN Duty = 4907%(X100), DQS PI = 62
7431 19:53:03.321179 [0] AVG Duty = 5000%(X100)
7432 19:53:03.323994
7433 19:53:03.324075 ==DQ 1 ==
7434 19:53:03.327581 Final DQ duty delay cell = 0
7435 19:53:03.330935 [0] MAX Duty = 5156%(X100), DQS PI = 34
7436 19:53:03.333933 [0] MIN Duty = 4969%(X100), DQS PI = 24
7437 19:53:03.334014 [0] AVG Duty = 5062%(X100)
7438 19:53:03.337426
7439 19:53:03.340694 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7440 19:53:03.340777
7441 19:53:03.344034 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7442 19:53:03.347403 [DutyScan_Calibration_Flow] ====Done====
7443 19:53:03.351320 nWR fixed to 30
7444 19:53:03.351413 [ModeRegInit_LP4] CH0 RK0
7445 19:53:03.354078 [ModeRegInit_LP4] CH0 RK1
7446 19:53:03.356948 [ModeRegInit_LP4] CH1 RK0
7447 19:53:03.360882 [ModeRegInit_LP4] CH1 RK1
7448 19:53:03.360964 match AC timing 5
7449 19:53:03.366865 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7450 19:53:03.370324 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7451 19:53:03.373853 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7452 19:53:03.380225 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7453 19:53:03.383424 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7454 19:53:03.383506 [MiockJmeterHQA]
7455 19:53:03.383570
7456 19:53:03.387170 [DramcMiockJmeter] u1RxGatingPI = 0
7457 19:53:03.390482 0 : 4253, 4027
7458 19:53:03.390565 4 : 4255, 4030
7459 19:53:03.393692 8 : 4366, 4139
7460 19:53:03.393775 12 : 4366, 4140
7461 19:53:03.393841 16 : 4363, 4138
7462 19:53:03.397229 20 : 4253, 4027
7463 19:53:03.397311 24 : 4253, 4027
7464 19:53:03.400263 28 : 4253, 4027
7465 19:53:03.400346 32 : 4252, 4027
7466 19:53:03.403726 36 : 4257, 4032
7467 19:53:03.403808 40 : 4363, 4137
7468 19:53:03.407020 44 : 4253, 4026
7469 19:53:03.407102 48 : 4253, 4026
7470 19:53:03.407167 52 : 4252, 4027
7471 19:53:03.410603 56 : 4253, 4027
7472 19:53:03.410685 60 : 4250, 4026
7473 19:53:03.413700 64 : 4360, 4137
7474 19:53:03.413782 68 : 4361, 4137
7475 19:53:03.416681 72 : 4250, 4026
7476 19:53:03.416764 76 : 4250, 4027
7477 19:53:03.420257 80 : 4250, 4026
7478 19:53:03.420340 84 : 4250, 4027
7479 19:53:03.420405 88 : 4255, 4032
7480 19:53:03.423914 92 : 4361, 4138
7481 19:53:03.423997 96 : 4250, 4026
7482 19:53:03.426795 100 : 4250, 4027
7483 19:53:03.426877 104 : 4361, 3939
7484 19:53:03.430369 108 : 4250, 16
7485 19:53:03.430452 112 : 4360, 0
7486 19:53:03.430518 116 : 4250, 0
7487 19:53:03.433941 120 : 4250, 0
7488 19:53:03.434024 124 : 4250, 0
7489 19:53:03.436808 128 : 4252, 0
7490 19:53:03.436890 132 : 4250, 0
7491 19:53:03.436955 136 : 4250, 0
7492 19:53:03.439959 140 : 4250, 0
7493 19:53:03.440041 144 : 4361, 0
7494 19:53:03.443253 148 : 4361, 0
7495 19:53:03.443336 152 : 4250, 0
7496 19:53:03.443413 156 : 4250, 0
7497 19:53:03.446969 160 : 4252, 0
7498 19:53:03.447051 164 : 4250, 0
7499 19:53:03.447117 168 : 4250, 0
7500 19:53:03.449955 172 : 4250, 0
7501 19:53:03.450038 176 : 4250, 0
7502 19:53:03.453531 180 : 4250, 0
7503 19:53:03.453614 184 : 4250, 0
7504 19:53:03.453678 188 : 4250, 0
7505 19:53:03.456551 192 : 4250, 0
7506 19:53:03.456634 196 : 4360, 0
7507 19:53:03.460056 200 : 4363, 0
7508 19:53:03.460139 204 : 4361, 0
7509 19:53:03.460204 208 : 4250, 0
7510 19:53:03.463308 212 : 4250, 0
7511 19:53:03.463400 216 : 4250, 0
7512 19:53:03.466951 220 : 4250, 0
7513 19:53:03.467034 224 : 4249, 0
7514 19:53:03.467099 228 : 4250, 0
7515 19:53:03.470193 232 : 4250, 0
7516 19:53:03.470276 236 : 4250, 1073
7517 19:53:03.473397 240 : 4250, 4027
7518 19:53:03.473480 244 : 4363, 4140
7519 19:53:03.476726 248 : 4250, 4027
7520 19:53:03.476809 252 : 4250, 4027
7521 19:53:03.476875 256 : 4250, 4027
7522 19:53:03.480039 260 : 4250, 4027
7523 19:53:03.480121 264 : 4250, 4027
7524 19:53:03.483037 268 : 4250, 4027
7525 19:53:03.483119 272 : 4360, 4137
7526 19:53:03.486399 276 : 4250, 4027
7527 19:53:03.486482 280 : 4250, 4027
7528 19:53:03.489857 284 : 4360, 4138
7529 19:53:03.489940 288 : 4250, 4027
7530 19:53:03.492946 292 : 4250, 4027
7531 19:53:03.493036 296 : 4361, 4137
7532 19:53:03.496446 300 : 4250, 4026
7533 19:53:03.496529 304 : 4250, 4027
7534 19:53:03.499984 308 : 4250, 4026
7535 19:53:03.500070 312 : 4250, 4027
7536 19:53:03.503096 316 : 4250, 4027
7537 19:53:03.503181 320 : 4250, 4027
7538 19:53:03.503286 324 : 4360, 4137
7539 19:53:03.506629 328 : 4250, 4027
7540 19:53:03.506714 332 : 4250, 4027
7541 19:53:03.509477 336 : 4361, 4138
7542 19:53:03.509563 340 : 4250, 4027
7543 19:53:03.513214 344 : 4250, 4026
7544 19:53:03.513299 348 : 4361, 4137
7545 19:53:03.516239 352 : 4250, 4025
7546 19:53:03.516324 356 : 4251, 3010
7547 19:53:03.519675 360 : 4250, 2
7548 19:53:03.519760
7549 19:53:03.519845 MIOCK jitter meter ch=0
7550 19:53:03.519926
7551 19:53:03.523444 1T = (360-108) = 252 dly cells
7552 19:53:03.529987 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7553 19:53:03.530073 ==
7554 19:53:03.532858 Dram Type= 6, Freq= 0, CH_0, rank 0
7555 19:53:03.536561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 19:53:03.536651 ==
7557 19:53:03.542925 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7558 19:53:03.546162 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7559 19:53:03.549483 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7560 19:53:03.556109 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7561 19:53:03.566235 [CA 0] Center 43 (13~74) winsize 62
7562 19:53:03.569392 [CA 1] Center 43 (13~74) winsize 62
7563 19:53:03.572958 [CA 2] Center 39 (10~68) winsize 59
7564 19:53:03.576232 [CA 3] Center 39 (10~68) winsize 59
7565 19:53:03.579191 [CA 4] Center 36 (7~66) winsize 60
7566 19:53:03.582390 [CA 5] Center 36 (7~66) winsize 60
7567 19:53:03.582499
7568 19:53:03.585630 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7569 19:53:03.585750
7570 19:53:03.592630 [CATrainingPosCal] consider 1 rank data
7571 19:53:03.592791 u2DelayCellTimex100 = 258/100 ps
7572 19:53:03.599101 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7573 19:53:03.602664 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7574 19:53:03.605564 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7575 19:53:03.608987 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7576 19:53:03.612226 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7577 19:53:03.615313 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7578 19:53:03.615438
7579 19:53:03.618966 CA PerBit enable=1, Macro0, CA PI delay=36
7580 19:53:03.619040
7581 19:53:03.622390 [CBTSetCACLKResult] CA Dly = 36
7582 19:53:03.625257 CS Dly: 11 (0~42)
7583 19:53:03.628971 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7584 19:53:03.631860 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7585 19:53:03.631978 ==
7586 19:53:03.635215 Dram Type= 6, Freq= 0, CH_0, rank 1
7587 19:53:03.642096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 19:53:03.642175 ==
7589 19:53:03.645005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7590 19:53:03.652085 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7591 19:53:03.655569 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7592 19:53:03.661635 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7593 19:53:03.669737 [CA 0] Center 44 (14~74) winsize 61
7594 19:53:03.673636 [CA 1] Center 43 (13~74) winsize 62
7595 19:53:03.676777 [CA 2] Center 39 (10~68) winsize 59
7596 19:53:03.679661 [CA 3] Center 39 (10~68) winsize 59
7597 19:53:03.683280 [CA 4] Center 36 (7~66) winsize 60
7598 19:53:03.686492 [CA 5] Center 36 (7~66) winsize 60
7599 19:53:03.686567
7600 19:53:03.689911 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7601 19:53:03.690016
7602 19:53:03.693385 [CATrainingPosCal] consider 2 rank data
7603 19:53:03.696443 u2DelayCellTimex100 = 258/100 ps
7604 19:53:03.702777 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7605 19:53:03.706297 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7606 19:53:03.709882 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7607 19:53:03.713179 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7608 19:53:03.716570 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7609 19:53:03.719677 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7610 19:53:03.719754
7611 19:53:03.723057 CA PerBit enable=1, Macro0, CA PI delay=36
7612 19:53:03.723124
7613 19:53:03.726130 [CBTSetCACLKResult] CA Dly = 36
7614 19:53:03.729436 CS Dly: 11 (0~43)
7615 19:53:03.732669 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7616 19:53:03.735959 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7617 19:53:03.736042
7618 19:53:03.739568 ----->DramcWriteLeveling(PI) begin...
7619 19:53:03.739662 ==
7620 19:53:03.742548 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 19:53:03.749512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 19:53:03.749604 ==
7623 19:53:03.752495 Write leveling (Byte 0): 35 => 35
7624 19:53:03.756132 Write leveling (Byte 1): 27 => 27
7625 19:53:03.756202 DramcWriteLeveling(PI) end<-----
7626 19:53:03.759314
7627 19:53:03.759393 ==
7628 19:53:03.762988 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 19:53:03.766019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 19:53:03.766096 ==
7631 19:53:03.769018 [Gating] SW mode calibration
7632 19:53:03.775882 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7633 19:53:03.779476 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7634 19:53:03.786142 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 19:53:03.789316 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 19:53:03.792747 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 19:53:03.799102 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 19:53:03.802328 1 4 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7639 19:53:03.805928 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7640 19:53:03.812550 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7641 19:53:03.815548 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7642 19:53:03.818958 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7643 19:53:03.825561 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 19:53:03.828841 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 19:53:03.832147 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7646 19:53:03.838620 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
7647 19:53:03.842132 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
7648 19:53:03.845508 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7649 19:53:03.852302 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 19:53:03.855510 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 19:53:03.858945 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 19:53:03.865079 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 19:53:03.868487 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7654 19:53:03.871741 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7655 19:53:03.878840 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7656 19:53:03.881769 1 6 24 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
7657 19:53:03.885303 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 19:53:03.891870 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 19:53:03.895288 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 19:53:03.898081 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 19:53:03.905182 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7662 19:53:03.908240 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7663 19:53:03.911726 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7664 19:53:03.918323 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7665 19:53:03.921614 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 19:53:03.925106 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 19:53:03.931080 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 19:53:03.934496 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 19:53:03.937893 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 19:53:03.944332 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 19:53:03.947764 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 19:53:03.951725 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 19:53:03.957536 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 19:53:03.961443 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 19:53:03.964414 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 19:53:03.971223 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 19:53:03.973958 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7678 19:53:03.977676 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7679 19:53:03.980687 Total UI for P1: 0, mck2ui 16
7680 19:53:03.984028 best dqsien dly found for B0: ( 1, 9, 12)
7681 19:53:03.990792 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7682 19:53:03.993902 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7683 19:53:03.997155 Total UI for P1: 0, mck2ui 16
7684 19:53:04.000837 best dqsien dly found for B1: ( 1, 9, 20)
7685 19:53:04.003896 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7686 19:53:04.007460 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7687 19:53:04.007583
7688 19:53:04.010492 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7689 19:53:04.014164 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7690 19:53:04.017330 [Gating] SW calibration Done
7691 19:53:04.017436 ==
7692 19:53:04.020533 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 19:53:04.024164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 19:53:04.027735 ==
7695 19:53:04.027924 RX Vref Scan: 0
7696 19:53:04.028054
7697 19:53:04.030595 RX Vref 0 -> 0, step: 1
7698 19:53:04.030707
7699 19:53:04.030810 RX Delay 0 -> 252, step: 8
7700 19:53:04.037505 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7701 19:53:04.040448 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7702 19:53:04.044274 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7703 19:53:04.047532 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7704 19:53:04.051038 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7705 19:53:04.057357 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7706 19:53:04.060575 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7707 19:53:04.063981 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7708 19:53:04.067534 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7709 19:53:04.070423 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7710 19:53:04.076921 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7711 19:53:04.080314 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7712 19:53:04.084200 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7713 19:53:04.087163 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7714 19:53:04.093406 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7715 19:53:04.096875 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7716 19:53:04.096956 ==
7717 19:53:04.100648 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 19:53:04.103399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 19:53:04.103472 ==
7720 19:53:04.103535 DQS Delay:
7721 19:53:04.106809 DQS0 = 0, DQS1 = 0
7722 19:53:04.106883 DQM Delay:
7723 19:53:04.110399 DQM0 = 128, DQM1 = 123
7724 19:53:04.110482 DQ Delay:
7725 19:53:04.113622 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7726 19:53:04.116860 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7727 19:53:04.120440 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7728 19:53:04.126735 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7729 19:53:04.126821
7730 19:53:04.126887
7731 19:53:04.126945 ==
7732 19:53:04.130221 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 19:53:04.133763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 19:53:04.133840 ==
7735 19:53:04.133905
7736 19:53:04.133967
7737 19:53:04.136641 TX Vref Scan disable
7738 19:53:04.136718 == TX Byte 0 ==
7739 19:53:04.143185 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7740 19:53:04.146636 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7741 19:53:04.146710 == TX Byte 1 ==
7742 19:53:04.153382 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7743 19:53:04.156563 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7744 19:53:04.156648 ==
7745 19:53:04.160044 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 19:53:04.162977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 19:53:04.163051 ==
7748 19:53:04.177866
7749 19:53:04.181638 TX Vref early break, caculate TX vref
7750 19:53:04.184533 TX Vref=16, minBit 8, minWin=20, winSum=357
7751 19:53:04.187840 TX Vref=18, minBit 11, minWin=21, winSum=362
7752 19:53:04.191041 TX Vref=20, minBit 8, minWin=21, winSum=376
7753 19:53:04.194521 TX Vref=22, minBit 8, minWin=23, winSum=386
7754 19:53:04.197939 TX Vref=24, minBit 8, minWin=23, winSum=392
7755 19:53:04.204540 TX Vref=26, minBit 4, minWin=24, winSum=405
7756 19:53:04.208087 TX Vref=28, minBit 8, minWin=23, winSum=405
7757 19:53:04.210964 TX Vref=30, minBit 8, minWin=23, winSum=401
7758 19:53:04.214439 TX Vref=32, minBit 8, minWin=23, winSum=388
7759 19:53:04.217944 TX Vref=34, minBit 8, minWin=22, winSum=382
7760 19:53:04.224320 [TxChooseVref] Worse bit 4, Min win 24, Win sum 405, Final Vref 26
7761 19:53:04.224405
7762 19:53:04.227433 Final TX Range 0 Vref 26
7763 19:53:04.227513
7764 19:53:04.227575 ==
7765 19:53:04.230784 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 19:53:04.234254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 19:53:04.234330 ==
7768 19:53:04.234403
7769 19:53:04.234463
7770 19:53:04.237511 TX Vref Scan disable
7771 19:53:04.244031 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7772 19:53:04.244146 == TX Byte 0 ==
7773 19:53:04.247651 u2DelayCellOfst[0]=15 cells (4 PI)
7774 19:53:04.250786 u2DelayCellOfst[1]=18 cells (5 PI)
7775 19:53:04.254401 u2DelayCellOfst[2]=11 cells (3 PI)
7776 19:53:04.257649 u2DelayCellOfst[3]=11 cells (3 PI)
7777 19:53:04.260855 u2DelayCellOfst[4]=11 cells (3 PI)
7778 19:53:04.264338 u2DelayCellOfst[5]=0 cells (0 PI)
7779 19:53:04.267357 u2DelayCellOfst[6]=22 cells (6 PI)
7780 19:53:04.271251 u2DelayCellOfst[7]=18 cells (5 PI)
7781 19:53:04.274115 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7782 19:53:04.277721 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7783 19:53:04.280818 == TX Byte 1 ==
7784 19:53:04.284294 u2DelayCellOfst[8]=0 cells (0 PI)
7785 19:53:04.284368 u2DelayCellOfst[9]=7 cells (2 PI)
7786 19:53:04.287444 u2DelayCellOfst[10]=11 cells (3 PI)
7787 19:53:04.290896 u2DelayCellOfst[11]=7 cells (2 PI)
7788 19:53:04.294176 u2DelayCellOfst[12]=15 cells (4 PI)
7789 19:53:04.297811 u2DelayCellOfst[13]=15 cells (4 PI)
7790 19:53:04.300822 u2DelayCellOfst[14]=18 cells (5 PI)
7791 19:53:04.303908 u2DelayCellOfst[15]=15 cells (4 PI)
7792 19:53:04.307654 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7793 19:53:04.314241 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7794 19:53:04.314316 DramC Write-DBI on
7795 19:53:04.314381 ==
7796 19:53:04.317426 Dram Type= 6, Freq= 0, CH_0, rank 0
7797 19:53:04.324030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7798 19:53:04.324122 ==
7799 19:53:04.324218
7800 19:53:04.324305
7801 19:53:04.324390 TX Vref Scan disable
7802 19:53:04.327782 == TX Byte 0 ==
7803 19:53:04.331278 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7804 19:53:04.334079 == TX Byte 1 ==
7805 19:53:04.337935 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7806 19:53:04.340846 DramC Write-DBI off
7807 19:53:04.340960
7808 19:53:04.341025 [DATLAT]
7809 19:53:04.341086 Freq=1600, CH0 RK0
7810 19:53:04.341144
7811 19:53:04.344402 DATLAT Default: 0xf
7812 19:53:04.344487 0, 0xFFFF, sum = 0
7813 19:53:04.348180 1, 0xFFFF, sum = 0
7814 19:53:04.351115 2, 0xFFFF, sum = 0
7815 19:53:04.351224 3, 0xFFFF, sum = 0
7816 19:53:04.354443 4, 0xFFFF, sum = 0
7817 19:53:04.354623 5, 0xFFFF, sum = 0
7818 19:53:04.357603 6, 0xFFFF, sum = 0
7819 19:53:04.357699 7, 0xFFFF, sum = 0
7820 19:53:04.360668 8, 0xFFFF, sum = 0
7821 19:53:04.360750 9, 0xFFFF, sum = 0
7822 19:53:04.364253 10, 0xFFFF, sum = 0
7823 19:53:04.364335 11, 0xFFFF, sum = 0
7824 19:53:04.367738 12, 0xFFFF, sum = 0
7825 19:53:04.367838 13, 0xEFFF, sum = 0
7826 19:53:04.370577 14, 0x0, sum = 1
7827 19:53:04.370659 15, 0x0, sum = 2
7828 19:53:04.374495 16, 0x0, sum = 3
7829 19:53:04.374577 17, 0x0, sum = 4
7830 19:53:04.377612 best_step = 15
7831 19:53:04.377692
7832 19:53:04.377756 ==
7833 19:53:04.380938 Dram Type= 6, Freq= 0, CH_0, rank 0
7834 19:53:04.383920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7835 19:53:04.384004 ==
7836 19:53:04.387671 RX Vref Scan: 1
7837 19:53:04.387758
7838 19:53:04.387835 Set Vref Range= 24 -> 127
7839 19:53:04.387898
7840 19:53:04.390927 RX Vref 24 -> 127, step: 1
7841 19:53:04.391009
7842 19:53:04.394197 RX Delay 11 -> 252, step: 4
7843 19:53:04.394280
7844 19:53:04.397434 Set Vref, RX VrefLevel [Byte0]: 24
7845 19:53:04.401226 [Byte1]: 24
7846 19:53:04.401308
7847 19:53:04.404056 Set Vref, RX VrefLevel [Byte0]: 25
7848 19:53:04.407688 [Byte1]: 25
7849 19:53:04.407770
7850 19:53:04.410863 Set Vref, RX VrefLevel [Byte0]: 26
7851 19:53:04.414243 [Byte1]: 26
7852 19:53:04.417935
7853 19:53:04.418017 Set Vref, RX VrefLevel [Byte0]: 27
7854 19:53:04.421309 [Byte1]: 27
7855 19:53:04.425685
7856 19:53:04.425784 Set Vref, RX VrefLevel [Byte0]: 28
7857 19:53:04.428901 [Byte1]: 28
7858 19:53:04.433339
7859 19:53:04.433431 Set Vref, RX VrefLevel [Byte0]: 29
7860 19:53:04.436443 [Byte1]: 29
7861 19:53:04.441106
7862 19:53:04.441200 Set Vref, RX VrefLevel [Byte0]: 30
7863 19:53:04.444130 [Byte1]: 30
7864 19:53:04.448599
7865 19:53:04.448681 Set Vref, RX VrefLevel [Byte0]: 31
7866 19:53:04.451742 [Byte1]: 31
7867 19:53:04.456058
7868 19:53:04.456144 Set Vref, RX VrefLevel [Byte0]: 32
7869 19:53:04.459425 [Byte1]: 32
7870 19:53:04.463792
7871 19:53:04.463874 Set Vref, RX VrefLevel [Byte0]: 33
7872 19:53:04.467365 [Byte1]: 33
7873 19:53:04.471245
7874 19:53:04.471356 Set Vref, RX VrefLevel [Byte0]: 34
7875 19:53:04.474896 [Byte1]: 34
7876 19:53:04.478805
7877 19:53:04.478913 Set Vref, RX VrefLevel [Byte0]: 35
7878 19:53:04.482165 [Byte1]: 35
7879 19:53:04.486593
7880 19:53:04.486703 Set Vref, RX VrefLevel [Byte0]: 36
7881 19:53:04.490097 [Byte1]: 36
7882 19:53:04.494601
7883 19:53:04.494728 Set Vref, RX VrefLevel [Byte0]: 37
7884 19:53:04.497604 [Byte1]: 37
7885 19:53:04.501900
7886 19:53:04.502009 Set Vref, RX VrefLevel [Byte0]: 38
7887 19:53:04.505188 [Byte1]: 38
7888 19:53:04.509362
7889 19:53:04.509470 Set Vref, RX VrefLevel [Byte0]: 39
7890 19:53:04.512683 [Byte1]: 39
7891 19:53:04.516913
7892 19:53:04.517002 Set Vref, RX VrefLevel [Byte0]: 40
7893 19:53:04.520535 [Byte1]: 40
7894 19:53:04.524802
7895 19:53:04.524909 Set Vref, RX VrefLevel [Byte0]: 41
7896 19:53:04.527888 [Byte1]: 41
7897 19:53:04.532125
7898 19:53:04.532234 Set Vref, RX VrefLevel [Byte0]: 42
7899 19:53:04.535802 [Byte1]: 42
7900 19:53:04.539686
7901 19:53:04.539792 Set Vref, RX VrefLevel [Byte0]: 43
7902 19:53:04.542969 [Byte1]: 43
7903 19:53:04.547376
7904 19:53:04.547471 Set Vref, RX VrefLevel [Byte0]: 44
7905 19:53:04.550853 [Byte1]: 44
7906 19:53:04.555580
7907 19:53:04.555677 Set Vref, RX VrefLevel [Byte0]: 45
7908 19:53:04.558654 [Byte1]: 45
7909 19:53:04.562818
7910 19:53:04.562920 Set Vref, RX VrefLevel [Byte0]: 46
7911 19:53:04.565907 [Byte1]: 46
7912 19:53:04.570362
7913 19:53:04.570440 Set Vref, RX VrefLevel [Byte0]: 47
7914 19:53:04.573635 [Byte1]: 47
7915 19:53:04.577786
7916 19:53:04.577892 Set Vref, RX VrefLevel [Byte0]: 48
7917 19:53:04.581006 [Byte1]: 48
7918 19:53:04.585319
7919 19:53:04.585430 Set Vref, RX VrefLevel [Byte0]: 49
7920 19:53:04.588943 [Byte1]: 49
7921 19:53:04.593499
7922 19:53:04.593597 Set Vref, RX VrefLevel [Byte0]: 50
7923 19:53:04.596614 [Byte1]: 50
7924 19:53:04.600788
7925 19:53:04.600890 Set Vref, RX VrefLevel [Byte0]: 51
7926 19:53:04.604266 [Byte1]: 51
7927 19:53:04.608619
7928 19:53:04.608692 Set Vref, RX VrefLevel [Byte0]: 52
7929 19:53:04.611520 [Byte1]: 52
7930 19:53:04.616320
7931 19:53:04.616391 Set Vref, RX VrefLevel [Byte0]: 53
7932 19:53:04.619608 [Byte1]: 53
7933 19:53:04.623669
7934 19:53:04.623770 Set Vref, RX VrefLevel [Byte0]: 54
7935 19:53:04.627195 [Byte1]: 54
7936 19:53:04.631884
7937 19:53:04.631965 Set Vref, RX VrefLevel [Byte0]: 55
7938 19:53:04.634748 [Byte1]: 55
7939 19:53:04.638657
7940 19:53:04.638758 Set Vref, RX VrefLevel [Byte0]: 56
7941 19:53:04.642433 [Byte1]: 56
7942 19:53:04.646560
7943 19:53:04.646641 Set Vref, RX VrefLevel [Byte0]: 57
7944 19:53:04.650085 [Byte1]: 57
7945 19:53:04.654100
7946 19:53:04.654180 Set Vref, RX VrefLevel [Byte0]: 58
7947 19:53:04.657372 [Byte1]: 58
7948 19:53:04.661840
7949 19:53:04.661940 Set Vref, RX VrefLevel [Byte0]: 59
7950 19:53:04.665105 [Byte1]: 59
7951 19:53:04.669429
7952 19:53:04.669509 Set Vref, RX VrefLevel [Byte0]: 60
7953 19:53:04.672461 [Byte1]: 60
7954 19:53:04.677176
7955 19:53:04.677255 Set Vref, RX VrefLevel [Byte0]: 61
7956 19:53:04.680181 [Byte1]: 61
7957 19:53:04.684327
7958 19:53:04.684440 Set Vref, RX VrefLevel [Byte0]: 62
7959 19:53:04.687828 [Byte1]: 62
7960 19:53:04.692398
7961 19:53:04.692502 Set Vref, RX VrefLevel [Byte0]: 63
7962 19:53:04.695158 [Byte1]: 63
7963 19:53:04.699904
7964 19:53:04.700002 Set Vref, RX VrefLevel [Byte0]: 64
7965 19:53:04.702997 [Byte1]: 64
7966 19:53:04.707235
7967 19:53:04.707346 Set Vref, RX VrefLevel [Byte0]: 65
7968 19:53:04.710698 [Byte1]: 65
7969 19:53:04.714747
7970 19:53:04.714857 Set Vref, RX VrefLevel [Byte0]: 66
7971 19:53:04.718681 [Byte1]: 66
7972 19:53:04.722685
7973 19:53:04.722768 Set Vref, RX VrefLevel [Byte0]: 67
7974 19:53:04.726157 [Byte1]: 67
7975 19:53:04.730456
7976 19:53:04.730539 Set Vref, RX VrefLevel [Byte0]: 68
7977 19:53:04.733306 [Byte1]: 68
7978 19:53:04.738069
7979 19:53:04.738141 Set Vref, RX VrefLevel [Byte0]: 69
7980 19:53:04.740849 [Byte1]: 69
7981 19:53:04.745366
7982 19:53:04.745436 Set Vref, RX VrefLevel [Byte0]: 70
7983 19:53:04.748677 [Byte1]: 70
7984 19:53:04.753347
7985 19:53:04.753417 Set Vref, RX VrefLevel [Byte0]: 71
7986 19:53:04.756913 [Byte1]: 71
7987 19:53:04.760538
7988 19:53:04.760608 Set Vref, RX VrefLevel [Byte0]: 72
7989 19:53:04.764137 [Byte1]: 72
7990 19:53:04.768289
7991 19:53:04.768355 Set Vref, RX VrefLevel [Byte0]: 73
7992 19:53:04.771497 [Byte1]: 73
7993 19:53:04.776381
7994 19:53:04.776455 Set Vref, RX VrefLevel [Byte0]: 74
7995 19:53:04.779309 [Byte1]: 74
7996 19:53:04.783582
7997 19:53:04.783649 Set Vref, RX VrefLevel [Byte0]: 75
7998 19:53:04.786751 [Byte1]: 75
7999 19:53:04.790910
8000 19:53:04.790979 Set Vref, RX VrefLevel [Byte0]: 76
8001 19:53:04.794260 [Byte1]: 76
8002 19:53:04.798520
8003 19:53:04.798592 Final RX Vref Byte 0 = 61 to rank0
8004 19:53:04.801995 Final RX Vref Byte 1 = 61 to rank0
8005 19:53:04.805404 Final RX Vref Byte 0 = 61 to rank1
8006 19:53:04.809018 Final RX Vref Byte 1 = 61 to rank1==
8007 19:53:04.812143 Dram Type= 6, Freq= 0, CH_0, rank 0
8008 19:53:04.818762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 19:53:04.818844 ==
8010 19:53:04.818908 DQS Delay:
8011 19:53:04.818966 DQS0 = 0, DQS1 = 0
8012 19:53:04.822232 DQM Delay:
8013 19:53:04.822313 DQM0 = 125, DQM1 = 119
8014 19:53:04.825151 DQ Delay:
8015 19:53:04.828600 DQ0 =124, DQ1 =128, DQ2 =126, DQ3 =122
8016 19:53:04.831697 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =136
8017 19:53:04.835148 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8018 19:53:04.838276 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =126
8019 19:53:04.838356
8020 19:53:04.838420
8021 19:53:04.838478
8022 19:53:04.841632 [DramC_TX_OE_Calibration] TA2
8023 19:53:04.844991 Original DQ_B0 (3 6) =30, OEN = 27
8024 19:53:04.848595 Original DQ_B1 (3 6) =30, OEN = 27
8025 19:53:04.851631 24, 0x0, End_B0=24 End_B1=24
8026 19:53:04.851713 25, 0x0, End_B0=25 End_B1=25
8027 19:53:04.854983 26, 0x0, End_B0=26 End_B1=26
8028 19:53:04.858327 27, 0x0, End_B0=27 End_B1=27
8029 19:53:04.862024 28, 0x0, End_B0=28 End_B1=28
8030 19:53:04.864989 29, 0x0, End_B0=29 End_B1=29
8031 19:53:04.865071 30, 0x0, End_B0=30 End_B1=30
8032 19:53:04.868580 31, 0x4141, End_B0=30 End_B1=30
8033 19:53:04.871883 Byte0 end_step=30 best_step=27
8034 19:53:04.875066 Byte1 end_step=30 best_step=27
8035 19:53:04.878434 Byte0 TX OE(2T, 0.5T) = (3, 3)
8036 19:53:04.881416 Byte1 TX OE(2T, 0.5T) = (3, 3)
8037 19:53:04.881497
8038 19:53:04.881561
8039 19:53:04.888298 [DQSOSCAuto] RK0, (LSB)MR18= 0x1616, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
8040 19:53:04.891475 CH0 RK0: MR19=303, MR18=1616
8041 19:53:04.898056 CH0_RK0: MR19=0x303, MR18=0x1616, DQSOSC=398, MR23=63, INC=23, DEC=15
8042 19:53:04.898137
8043 19:53:04.901469 ----->DramcWriteLeveling(PI) begin...
8044 19:53:04.901551 ==
8045 19:53:04.905000 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 19:53:04.907859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 19:53:04.907941 ==
8048 19:53:04.911585 Write leveling (Byte 0): 34 => 34
8049 19:53:04.914474 Write leveling (Byte 1): 28 => 28
8050 19:53:04.918005 DramcWriteLeveling(PI) end<-----
8051 19:53:04.918085
8052 19:53:04.918148 ==
8053 19:53:04.921596 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 19:53:04.925134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 19:53:04.925214 ==
8056 19:53:04.928456 [Gating] SW mode calibration
8057 19:53:04.934755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8058 19:53:04.941475 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8059 19:53:04.945126 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 19:53:04.951298 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 19:53:04.954278 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 19:53:04.957887 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
8063 19:53:04.961130 1 4 16 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
8064 19:53:04.968247 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8065 19:53:04.971257 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 19:53:04.974282 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 19:53:04.981170 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 19:53:04.984600 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 19:53:04.987381 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8070 19:53:04.994465 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
8071 19:53:04.997934 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8072 19:53:05.001187 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 19:53:05.007539 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 19:53:05.011336 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 19:53:05.014227 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 19:53:05.020972 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 19:53:05.024558 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8078 19:53:05.027966 1 6 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8079 19:53:05.034151 1 6 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8080 19:53:05.037928 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 19:53:05.040591 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 19:53:05.047291 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 19:53:05.050788 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 19:53:05.053632 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 19:53:05.060595 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8086 19:53:05.063778 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8087 19:53:05.066912 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8088 19:53:05.073816 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8089 19:53:05.077353 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 19:53:05.080463 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 19:53:05.087497 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 19:53:05.090522 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 19:53:05.093938 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 19:53:05.100910 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 19:53:05.103884 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 19:53:05.107522 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 19:53:05.110355 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 19:53:05.117333 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 19:53:05.120470 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 19:53:05.124182 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 19:53:05.130820 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8102 19:53:05.133962 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8103 19:53:05.137105 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8104 19:53:05.140321 Total UI for P1: 0, mck2ui 16
8105 19:53:05.143531 best dqsien dly found for B0: ( 1, 9, 10)
8106 19:53:05.150483 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8107 19:53:05.153563 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 19:53:05.156900 Total UI for P1: 0, mck2ui 16
8109 19:53:05.160725 best dqsien dly found for B1: ( 1, 9, 18)
8110 19:53:05.163594 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8111 19:53:05.166979 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8112 19:53:05.167060
8113 19:53:05.170159 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8114 19:53:05.176697 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8115 19:53:05.176777 [Gating] SW calibration Done
8116 19:53:05.176844 ==
8117 19:53:05.180003 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 19:53:05.186941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 19:53:05.187018 ==
8120 19:53:05.187124 RX Vref Scan: 0
8121 19:53:05.187182
8122 19:53:05.190434 RX Vref 0 -> 0, step: 1
8123 19:53:05.190511
8124 19:53:05.193687 RX Delay 0 -> 252, step: 8
8125 19:53:05.196851 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8126 19:53:05.200272 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8127 19:53:05.203046 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8128 19:53:05.206518 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8129 19:53:05.213176 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8130 19:53:05.216552 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8131 19:53:05.220000 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8132 19:53:05.223141 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8133 19:53:05.226652 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8134 19:53:05.232929 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8135 19:53:05.236441 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8136 19:53:05.240032 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8137 19:53:05.242795 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8138 19:53:05.249594 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8139 19:53:05.252784 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8140 19:53:05.256200 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8141 19:53:05.256277 ==
8142 19:53:05.259729 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 19:53:05.262816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 19:53:05.262888 ==
8145 19:53:05.266318 DQS Delay:
8146 19:53:05.266383 DQS0 = 0, DQS1 = 0
8147 19:53:05.269528 DQM Delay:
8148 19:53:05.269594 DQM0 = 128, DQM1 = 122
8149 19:53:05.269651 DQ Delay:
8150 19:53:05.276297 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8151 19:53:05.279494 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8152 19:53:05.282642 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8153 19:53:05.286089 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8154 19:53:05.286154
8155 19:53:05.286215
8156 19:53:05.286271 ==
8157 19:53:05.289497 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 19:53:05.292652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 19:53:05.292717 ==
8160 19:53:05.292775
8161 19:53:05.292830
8162 19:53:05.295827 TX Vref Scan disable
8163 19:53:05.299281 == TX Byte 0 ==
8164 19:53:05.302491 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8165 19:53:05.306502 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8166 19:53:05.309283 == TX Byte 1 ==
8167 19:53:05.313045 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8168 19:53:05.315817 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8169 19:53:05.315888 ==
8170 19:53:05.319622 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 19:53:05.322403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 19:53:05.325640 ==
8173 19:53:05.338906
8174 19:53:05.342048 TX Vref early break, caculate TX vref
8175 19:53:05.345509 TX Vref=16, minBit 0, minWin=22, winSum=360
8176 19:53:05.349201 TX Vref=18, minBit 8, minWin=22, winSum=372
8177 19:53:05.352114 TX Vref=20, minBit 8, minWin=22, winSum=381
8178 19:53:05.355215 TX Vref=22, minBit 0, minWin=24, winSum=394
8179 19:53:05.358853 TX Vref=24, minBit 0, minWin=24, winSum=395
8180 19:53:05.365300 TX Vref=26, minBit 8, minWin=24, winSum=403
8181 19:53:05.368398 TX Vref=28, minBit 8, minWin=24, winSum=407
8182 19:53:05.372012 TX Vref=30, minBit 11, minWin=23, winSum=401
8183 19:53:05.375244 TX Vref=32, minBit 8, minWin=23, winSum=394
8184 19:53:05.378616 TX Vref=34, minBit 8, minWin=23, winSum=390
8185 19:53:05.381942 TX Vref=36, minBit 8, minWin=22, winSum=380
8186 19:53:05.388444 [TxChooseVref] Worse bit 8, Min win 24, Win sum 407, Final Vref 28
8187 19:53:05.388554
8188 19:53:05.391997 Final TX Range 0 Vref 28
8189 19:53:05.392097
8190 19:53:05.392192 ==
8191 19:53:05.395245 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 19:53:05.398709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 19:53:05.398810 ==
8194 19:53:05.398903
8195 19:53:05.398989
8196 19:53:05.401745 TX Vref Scan disable
8197 19:53:05.408277 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8198 19:53:05.408388 == TX Byte 0 ==
8199 19:53:05.411995 u2DelayCellOfst[0]=11 cells (3 PI)
8200 19:53:05.415398 u2DelayCellOfst[1]=15 cells (4 PI)
8201 19:53:05.418891 u2DelayCellOfst[2]=11 cells (3 PI)
8202 19:53:05.421641 u2DelayCellOfst[3]=11 cells (3 PI)
8203 19:53:05.425472 u2DelayCellOfst[4]=7 cells (2 PI)
8204 19:53:05.428488 u2DelayCellOfst[5]=0 cells (0 PI)
8205 19:53:05.431528 u2DelayCellOfst[6]=18 cells (5 PI)
8206 19:53:05.435130 u2DelayCellOfst[7]=18 cells (5 PI)
8207 19:53:05.438291 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8208 19:53:05.441735 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8209 19:53:05.444851 == TX Byte 1 ==
8210 19:53:05.448380 u2DelayCellOfst[8]=0 cells (0 PI)
8211 19:53:05.451542 u2DelayCellOfst[9]=3 cells (1 PI)
8212 19:53:05.454502 u2DelayCellOfst[10]=11 cells (3 PI)
8213 19:53:05.454609 u2DelayCellOfst[11]=3 cells (1 PI)
8214 19:53:05.458209 u2DelayCellOfst[12]=11 cells (3 PI)
8215 19:53:05.461583 u2DelayCellOfst[13]=15 cells (4 PI)
8216 19:53:05.464617 u2DelayCellOfst[14]=15 cells (4 PI)
8217 19:53:05.467877 u2DelayCellOfst[15]=11 cells (3 PI)
8218 19:53:05.474903 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8219 19:53:05.478116 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8220 19:53:05.478189 DramC Write-DBI on
8221 19:53:05.478251 ==
8222 19:53:05.481668 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 19:53:05.487734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 19:53:05.487812 ==
8225 19:53:05.487873
8226 19:53:05.487931
8227 19:53:05.491275 TX Vref Scan disable
8228 19:53:05.491375 == TX Byte 0 ==
8229 19:53:05.497829 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8230 19:53:05.497904 == TX Byte 1 ==
8231 19:53:05.501213 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8232 19:53:05.504683 DramC Write-DBI off
8233 19:53:05.504782
8234 19:53:05.504879 [DATLAT]
8235 19:53:05.507821 Freq=1600, CH0 RK1
8236 19:53:05.507896
8237 19:53:05.507958 DATLAT Default: 0xf
8238 19:53:05.511375 0, 0xFFFF, sum = 0
8239 19:53:05.511454 1, 0xFFFF, sum = 0
8240 19:53:05.514433 2, 0xFFFF, sum = 0
8241 19:53:05.514505 3, 0xFFFF, sum = 0
8242 19:53:05.517924 4, 0xFFFF, sum = 0
8243 19:53:05.518027 5, 0xFFFF, sum = 0
8244 19:53:05.521273 6, 0xFFFF, sum = 0
8245 19:53:05.521384 7, 0xFFFF, sum = 0
8246 19:53:05.524645 8, 0xFFFF, sum = 0
8247 19:53:05.524744 9, 0xFFFF, sum = 0
8248 19:53:05.527740 10, 0xFFFF, sum = 0
8249 19:53:05.531210 11, 0xFFFF, sum = 0
8250 19:53:05.531311 12, 0xFFFF, sum = 0
8251 19:53:05.534624 13, 0xCFFF, sum = 0
8252 19:53:05.534727 14, 0x0, sum = 1
8253 19:53:05.537690 15, 0x0, sum = 2
8254 19:53:05.537794 16, 0x0, sum = 3
8255 19:53:05.537889 17, 0x0, sum = 4
8256 19:53:05.541395 best_step = 15
8257 19:53:05.541466
8258 19:53:05.541530 ==
8259 19:53:05.544251 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 19:53:05.547767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 19:53:05.547837 ==
8262 19:53:05.550974 RX Vref Scan: 0
8263 19:53:05.551068
8264 19:53:05.551162 RX Vref 0 -> 0, step: 1
8265 19:53:05.554768
8266 19:53:05.554864 RX Delay 3 -> 252, step: 4
8267 19:53:05.560982 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8268 19:53:05.564597 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8269 19:53:05.567624 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8270 19:53:05.571087 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8271 19:53:05.574240 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8272 19:53:05.581186 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8273 19:53:05.584204 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8274 19:53:05.587462 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8275 19:53:05.590680 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8276 19:53:05.594385 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8277 19:53:05.600760 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8278 19:53:05.604033 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8279 19:53:05.607574 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8280 19:53:05.610967 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8281 19:53:05.617427 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8282 19:53:05.620999 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8283 19:53:05.621080 ==
8284 19:53:05.623967 Dram Type= 6, Freq= 0, CH_0, rank 1
8285 19:53:05.627620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 19:53:05.627697 ==
8287 19:53:05.627759 DQS Delay:
8288 19:53:05.630807 DQS0 = 0, DQS1 = 0
8289 19:53:05.630909 DQM Delay:
8290 19:53:05.634179 DQM0 = 124, DQM1 = 118
8291 19:53:05.634250 DQ Delay:
8292 19:53:05.637453 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8293 19:53:05.640816 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8294 19:53:05.643789 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8295 19:53:05.650683 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8296 19:53:05.650789
8297 19:53:05.650881
8298 19:53:05.650968
8299 19:53:05.654150 [DramC_TX_OE_Calibration] TA2
8300 19:53:05.654220 Original DQ_B0 (3 6) =30, OEN = 27
8301 19:53:05.657170 Original DQ_B1 (3 6) =30, OEN = 27
8302 19:53:05.660312 24, 0x0, End_B0=24 End_B1=24
8303 19:53:05.663889 25, 0x0, End_B0=25 End_B1=25
8304 19:53:05.666867 26, 0x0, End_B0=26 End_B1=26
8305 19:53:05.670906 27, 0x0, End_B0=27 End_B1=27
8306 19:53:05.671018 28, 0x0, End_B0=28 End_B1=28
8307 19:53:05.673968 29, 0x0, End_B0=29 End_B1=29
8308 19:53:05.677252 30, 0x0, End_B0=30 End_B1=30
8309 19:53:05.680836 31, 0x4545, End_B0=30 End_B1=30
8310 19:53:05.683825 Byte0 end_step=30 best_step=27
8311 19:53:05.683900 Byte1 end_step=30 best_step=27
8312 19:53:05.687039 Byte0 TX OE(2T, 0.5T) = (3, 3)
8313 19:53:05.690307 Byte1 TX OE(2T, 0.5T) = (3, 3)
8314 19:53:05.690411
8315 19:53:05.690494
8316 19:53:05.700179 [DQSOSCAuto] RK1, (LSB)MR18= 0x2513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8317 19:53:05.700290 CH0 RK1: MR19=303, MR18=2513
8318 19:53:05.706942 CH0_RK1: MR19=0x303, MR18=0x2513, DQSOSC=391, MR23=63, INC=24, DEC=16
8319 19:53:05.710444 [RxdqsGatingPostProcess] freq 1600
8320 19:53:05.717172 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8321 19:53:05.720411 best DQS0 dly(2T, 0.5T) = (1, 1)
8322 19:53:05.723840 best DQS1 dly(2T, 0.5T) = (1, 1)
8323 19:53:05.726913 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8324 19:53:05.730520 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8325 19:53:05.730592 best DQS0 dly(2T, 0.5T) = (1, 1)
8326 19:53:05.733658 best DQS1 dly(2T, 0.5T) = (1, 1)
8327 19:53:05.736755 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8328 19:53:05.740257 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8329 19:53:05.743315 Pre-setting of DQS Precalculation
8330 19:53:05.749929 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8331 19:53:05.750024 ==
8332 19:53:05.753711 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 19:53:05.756649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 19:53:05.756721 ==
8335 19:53:05.763229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8336 19:53:05.766907 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8337 19:53:05.769783 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8338 19:53:05.776350 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8339 19:53:05.785436 [CA 0] Center 41 (12~70) winsize 59
8340 19:53:05.788483 [CA 1] Center 42 (13~72) winsize 60
8341 19:53:05.791920 [CA 2] Center 37 (9~66) winsize 58
8342 19:53:05.795704 [CA 3] Center 36 (7~66) winsize 60
8343 19:53:05.798718 [CA 4] Center 37 (8~67) winsize 60
8344 19:53:05.801932 [CA 5] Center 36 (7~65) winsize 59
8345 19:53:05.802030
8346 19:53:05.805275 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8347 19:53:05.805351
8348 19:53:05.808527 [CATrainingPosCal] consider 1 rank data
8349 19:53:05.812231 u2DelayCellTimex100 = 258/100 ps
8350 19:53:05.815475 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8351 19:53:05.821868 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8352 19:53:05.825671 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8353 19:53:05.828821 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8354 19:53:05.831908 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8355 19:53:05.835281 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8356 19:53:05.835363
8357 19:53:05.838427 CA PerBit enable=1, Macro0, CA PI delay=36
8358 19:53:05.838510
8359 19:53:05.842095 [CBTSetCACLKResult] CA Dly = 36
8360 19:53:05.845481 CS Dly: 10 (0~41)
8361 19:53:05.849011 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8362 19:53:05.852020 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8363 19:53:05.852102 ==
8364 19:53:05.855280 Dram Type= 6, Freq= 0, CH_1, rank 1
8365 19:53:05.858512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 19:53:05.858595 ==
8367 19:53:05.865131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8368 19:53:05.868714 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8369 19:53:05.875602 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8370 19:53:05.878740 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8371 19:53:05.888539 [CA 0] Center 42 (13~72) winsize 60
8372 19:53:05.892065 [CA 1] Center 42 (12~72) winsize 61
8373 19:53:05.895538 [CA 2] Center 37 (8~67) winsize 60
8374 19:53:05.898548 [CA 3] Center 36 (7~66) winsize 60
8375 19:53:05.901747 [CA 4] Center 38 (8~68) winsize 61
8376 19:53:05.905460 [CA 5] Center 36 (7~66) winsize 60
8377 19:53:05.905531
8378 19:53:05.908441 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8379 19:53:05.908540
8380 19:53:05.911608 [CATrainingPosCal] consider 2 rank data
8381 19:53:05.914947 u2DelayCellTimex100 = 258/100 ps
8382 19:53:05.918503 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8383 19:53:05.925245 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8384 19:53:05.928449 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8385 19:53:05.931547 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8386 19:53:05.934771 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8387 19:53:05.938207 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8388 19:53:05.938283
8389 19:53:05.941598 CA PerBit enable=1, Macro0, CA PI delay=36
8390 19:53:05.941670
8391 19:53:05.945461 [CBTSetCACLKResult] CA Dly = 36
8392 19:53:05.948066 CS Dly: 11 (0~43)
8393 19:53:05.951653 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8394 19:53:05.955096 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8395 19:53:05.955172
8396 19:53:05.958114 ----->DramcWriteLeveling(PI) begin...
8397 19:53:05.958183 ==
8398 19:53:05.961636 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 19:53:05.968259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 19:53:05.968334 ==
8401 19:53:05.971564 Write leveling (Byte 0): 24 => 24
8402 19:53:05.971661 Write leveling (Byte 1): 27 => 27
8403 19:53:05.974835 DramcWriteLeveling(PI) end<-----
8404 19:53:05.974904
8405 19:53:05.974966 ==
8406 19:53:05.978219 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 19:53:05.984815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 19:53:05.984891 ==
8409 19:53:05.987893 [Gating] SW mode calibration
8410 19:53:05.994705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8411 19:53:05.997757 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8412 19:53:06.004486 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 19:53:06.007940 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 19:53:06.011567 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
8415 19:53:06.018213 1 4 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8416 19:53:06.020877 1 4 16 | B1->B0 | 3332 302f | 1 1 | (1 1) (1 1)
8417 19:53:06.024188 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 19:53:06.031308 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 19:53:06.034286 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 19:53:06.037938 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 19:53:06.044609 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 19:53:06.047962 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 19:53:06.051040 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8424 19:53:06.057695 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8425 19:53:06.061042 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 19:53:06.064088 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 19:53:06.071072 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 19:53:06.074107 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 19:53:06.077576 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 19:53:06.080822 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 19:53:06.087350 1 6 12 | B1->B0 | 2d2d 2727 | 0 0 | (0 0) (0 0)
8432 19:53:06.090680 1 6 16 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
8433 19:53:06.094172 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 19:53:06.100778 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 19:53:06.104100 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 19:53:06.107139 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 19:53:06.114588 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 19:53:06.117109 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 19:53:06.120849 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 19:53:06.127626 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8441 19:53:06.130770 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8442 19:53:06.133800 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 19:53:06.140479 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 19:53:06.143923 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 19:53:06.147038 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 19:53:06.153802 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 19:53:06.157297 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 19:53:06.160500 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 19:53:06.167117 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 19:53:06.170381 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 19:53:06.173332 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 19:53:06.180705 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 19:53:06.183653 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 19:53:06.186568 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 19:53:06.193234 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8456 19:53:06.196776 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8457 19:53:06.200088 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 19:53:06.203654 Total UI for P1: 0, mck2ui 16
8459 19:53:06.206753 best dqsien dly found for B0: ( 1, 9, 14)
8460 19:53:06.210078 Total UI for P1: 0, mck2ui 16
8461 19:53:06.213528 best dqsien dly found for B1: ( 1, 9, 16)
8462 19:53:06.216790 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8463 19:53:06.219799 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8464 19:53:06.219911
8465 19:53:06.226607 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8466 19:53:06.230114 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8467 19:53:06.230187 [Gating] SW calibration Done
8468 19:53:06.233026 ==
8469 19:53:06.236374 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 19:53:06.240160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 19:53:06.240254 ==
8472 19:53:06.240355 RX Vref Scan: 0
8473 19:53:06.240452
8474 19:53:06.243115 RX Vref 0 -> 0, step: 1
8475 19:53:06.243221
8476 19:53:06.246494 RX Delay 0 -> 252, step: 8
8477 19:53:06.250223 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8478 19:53:06.253204 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8479 19:53:06.256996 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8480 19:53:06.263551 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8481 19:53:06.266280 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8482 19:53:06.269937 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8483 19:53:06.272881 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8484 19:53:06.276070 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8485 19:53:06.283136 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8486 19:53:06.286479 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8487 19:53:06.290021 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8488 19:53:06.293161 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8489 19:53:06.295981 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8490 19:53:06.303101 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8491 19:53:06.306065 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8492 19:53:06.309700 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8493 19:53:06.309777 ==
8494 19:53:06.312919 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 19:53:06.316543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 19:53:06.319566 ==
8497 19:53:06.319633 DQS Delay:
8498 19:53:06.319691 DQS0 = 0, DQS1 = 0
8499 19:53:06.322736 DQM Delay:
8500 19:53:06.322817 DQM0 = 132, DQM1 = 126
8501 19:53:06.326167 DQ Delay:
8502 19:53:06.329743 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8503 19:53:06.332727 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8504 19:53:06.335843 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8505 19:53:06.339304 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8506 19:53:06.339392
8507 19:53:06.339488
8508 19:53:06.339563 ==
8509 19:53:06.342555 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 19:53:06.345857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 19:53:06.345938 ==
8512 19:53:06.346002
8513 19:53:06.349450
8514 19:53:06.349562 TX Vref Scan disable
8515 19:53:06.352818 == TX Byte 0 ==
8516 19:53:06.355736 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8517 19:53:06.359230 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8518 19:53:06.362894 == TX Byte 1 ==
8519 19:53:06.365705 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8520 19:53:06.369137 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8521 19:53:06.369217 ==
8522 19:53:06.372616 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 19:53:06.379065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 19:53:06.379139 ==
8525 19:53:06.392041
8526 19:53:06.395201 TX Vref early break, caculate TX vref
8527 19:53:06.398648 TX Vref=16, minBit 1, minWin=22, winSum=366
8528 19:53:06.401957 TX Vref=18, minBit 3, minWin=22, winSum=370
8529 19:53:06.404945 TX Vref=20, minBit 10, minWin=23, winSum=387
8530 19:53:06.408388 TX Vref=22, minBit 1, minWin=24, winSum=396
8531 19:53:06.411968 TX Vref=24, minBit 11, minWin=24, winSum=406
8532 19:53:06.418414 TX Vref=26, minBit 1, minWin=25, winSum=414
8533 19:53:06.421541 TX Vref=28, minBit 5, minWin=25, winSum=420
8534 19:53:06.425049 TX Vref=30, minBit 1, minWin=25, winSum=418
8535 19:53:06.428466 TX Vref=32, minBit 0, minWin=24, winSum=405
8536 19:53:06.431354 TX Vref=34, minBit 0, minWin=24, winSum=403
8537 19:53:06.434628 TX Vref=36, minBit 0, minWin=23, winSum=386
8538 19:53:06.441660 [TxChooseVref] Worse bit 5, Min win 25, Win sum 420, Final Vref 28
8539 19:53:06.441739
8540 19:53:06.444661 Final TX Range 0 Vref 28
8541 19:53:06.444729
8542 19:53:06.444791 ==
8543 19:53:06.447985 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 19:53:06.451685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 19:53:06.451756 ==
8546 19:53:06.451815
8547 19:53:06.455137
8548 19:53:06.455211 TX Vref Scan disable
8549 19:53:06.461867 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8550 19:53:06.461942 == TX Byte 0 ==
8551 19:53:06.464977 u2DelayCellOfst[0]=18 cells (5 PI)
8552 19:53:06.468522 u2DelayCellOfst[1]=11 cells (3 PI)
8553 19:53:06.471580 u2DelayCellOfst[2]=0 cells (0 PI)
8554 19:53:06.474555 u2DelayCellOfst[3]=7 cells (2 PI)
8555 19:53:06.477946 u2DelayCellOfst[4]=7 cells (2 PI)
8556 19:53:06.481479 u2DelayCellOfst[5]=22 cells (6 PI)
8557 19:53:06.484576 u2DelayCellOfst[6]=18 cells (5 PI)
8558 19:53:06.487972 u2DelayCellOfst[7]=7 cells (2 PI)
8559 19:53:06.491045 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8560 19:53:06.494875 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8561 19:53:06.497744 == TX Byte 1 ==
8562 19:53:06.501325 u2DelayCellOfst[8]=0 cells (0 PI)
8563 19:53:06.504589 u2DelayCellOfst[9]=3 cells (1 PI)
8564 19:53:06.504669 u2DelayCellOfst[10]=11 cells (3 PI)
8565 19:53:06.507915 u2DelayCellOfst[11]=3 cells (1 PI)
8566 19:53:06.511272 u2DelayCellOfst[12]=15 cells (4 PI)
8567 19:53:06.514503 u2DelayCellOfst[13]=18 cells (5 PI)
8568 19:53:06.517881 u2DelayCellOfst[14]=18 cells (5 PI)
8569 19:53:06.520971 u2DelayCellOfst[15]=18 cells (5 PI)
8570 19:53:06.528010 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8571 19:53:06.530928 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8572 19:53:06.531008 DramC Write-DBI on
8573 19:53:06.531071 ==
8574 19:53:06.534449 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 19:53:06.541006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 19:53:06.541088 ==
8577 19:53:06.541152
8578 19:53:06.541236
8579 19:53:06.541348 TX Vref Scan disable
8580 19:53:06.545154 == TX Byte 0 ==
8581 19:53:06.548841 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8582 19:53:06.551790 == TX Byte 1 ==
8583 19:53:06.555022 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8584 19:53:06.558321 DramC Write-DBI off
8585 19:53:06.558401
8586 19:53:06.558465 [DATLAT]
8587 19:53:06.558524 Freq=1600, CH1 RK0
8588 19:53:06.558581
8589 19:53:06.562001 DATLAT Default: 0xf
8590 19:53:06.562081 0, 0xFFFF, sum = 0
8591 19:53:06.565230 1, 0xFFFF, sum = 0
8592 19:53:06.568482 2, 0xFFFF, sum = 0
8593 19:53:06.568596 3, 0xFFFF, sum = 0
8594 19:53:06.571999 4, 0xFFFF, sum = 0
8595 19:53:06.572081 5, 0xFFFF, sum = 0
8596 19:53:06.574938 6, 0xFFFF, sum = 0
8597 19:53:06.575020 7, 0xFFFF, sum = 0
8598 19:53:06.578492 8, 0xFFFF, sum = 0
8599 19:53:06.578574 9, 0xFFFF, sum = 0
8600 19:53:06.582041 10, 0xFFFF, sum = 0
8601 19:53:06.582122 11, 0xFFFF, sum = 0
8602 19:53:06.585060 12, 0xFFFF, sum = 0
8603 19:53:06.585141 13, 0xCFFF, sum = 0
8604 19:53:06.588648 14, 0x0, sum = 1
8605 19:53:06.588729 15, 0x0, sum = 2
8606 19:53:06.591506 16, 0x0, sum = 3
8607 19:53:06.591591 17, 0x0, sum = 4
8608 19:53:06.595052 best_step = 15
8609 19:53:06.595132
8610 19:53:06.595196 ==
8611 19:53:06.598523 Dram Type= 6, Freq= 0, CH_1, rank 0
8612 19:53:06.601511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8613 19:53:06.601592 ==
8614 19:53:06.601656 RX Vref Scan: 1
8615 19:53:06.605072
8616 19:53:06.605152 Set Vref Range= 24 -> 127
8617 19:53:06.605216
8618 19:53:06.608506 RX Vref 24 -> 127, step: 1
8619 19:53:06.608587
8620 19:53:06.611340 RX Delay 11 -> 252, step: 4
8621 19:53:06.611429
8622 19:53:06.614838 Set Vref, RX VrefLevel [Byte0]: 24
8623 19:53:06.618210 [Byte1]: 24
8624 19:53:06.618291
8625 19:53:06.621474 Set Vref, RX VrefLevel [Byte0]: 25
8626 19:53:06.624711 [Byte1]: 25
8627 19:53:06.624791
8628 19:53:06.628186 Set Vref, RX VrefLevel [Byte0]: 26
8629 19:53:06.631585 [Byte1]: 26
8630 19:53:06.635815
8631 19:53:06.635896 Set Vref, RX VrefLevel [Byte0]: 27
8632 19:53:06.638694 [Byte1]: 27
8633 19:53:06.642993
8634 19:53:06.643073 Set Vref, RX VrefLevel [Byte0]: 28
8635 19:53:06.646603 [Byte1]: 28
8636 19:53:06.651133
8637 19:53:06.651213 Set Vref, RX VrefLevel [Byte0]: 29
8638 19:53:06.653946 [Byte1]: 29
8639 19:53:06.658300
8640 19:53:06.658397 Set Vref, RX VrefLevel [Byte0]: 30
8641 19:53:06.661942 [Byte1]: 30
8642 19:53:06.666235
8643 19:53:06.666314 Set Vref, RX VrefLevel [Byte0]: 31
8644 19:53:06.669074 [Byte1]: 31
8645 19:53:06.673938
8646 19:53:06.674018 Set Vref, RX VrefLevel [Byte0]: 32
8647 19:53:06.677065 [Byte1]: 32
8648 19:53:06.681441
8649 19:53:06.681525 Set Vref, RX VrefLevel [Byte0]: 33
8650 19:53:06.684841 [Byte1]: 33
8651 19:53:06.689103
8652 19:53:06.689182 Set Vref, RX VrefLevel [Byte0]: 34
8653 19:53:06.691970 [Byte1]: 34
8654 19:53:06.696591
8655 19:53:06.696671 Set Vref, RX VrefLevel [Byte0]: 35
8656 19:53:06.699589 [Byte1]: 35
8657 19:53:06.704291
8658 19:53:06.704366 Set Vref, RX VrefLevel [Byte0]: 36
8659 19:53:06.707102 [Byte1]: 36
8660 19:53:06.711794
8661 19:53:06.711868 Set Vref, RX VrefLevel [Byte0]: 37
8662 19:53:06.715309 [Byte1]: 37
8663 19:53:06.719510
8664 19:53:06.719580 Set Vref, RX VrefLevel [Byte0]: 38
8665 19:53:06.723043 [Byte1]: 38
8666 19:53:06.727025
8667 19:53:06.727097 Set Vref, RX VrefLevel [Byte0]: 39
8668 19:53:06.730480 [Byte1]: 39
8669 19:53:06.734773
8670 19:53:06.734841 Set Vref, RX VrefLevel [Byte0]: 40
8671 19:53:06.737896 [Byte1]: 40
8672 19:53:06.741870
8673 19:53:06.741944 Set Vref, RX VrefLevel [Byte0]: 41
8674 19:53:06.745580 [Byte1]: 41
8675 19:53:06.749854
8676 19:53:06.749921 Set Vref, RX VrefLevel [Byte0]: 42
8677 19:53:06.753324 [Byte1]: 42
8678 19:53:06.757344
8679 19:53:06.757415 Set Vref, RX VrefLevel [Byte0]: 43
8680 19:53:06.760665 [Byte1]: 43
8681 19:53:06.764956
8682 19:53:06.765023 Set Vref, RX VrefLevel [Byte0]: 44
8683 19:53:06.768366 [Byte1]: 44
8684 19:53:06.772593
8685 19:53:06.772670 Set Vref, RX VrefLevel [Byte0]: 45
8686 19:53:06.775714 [Byte1]: 45
8687 19:53:06.780006
8688 19:53:06.780076 Set Vref, RX VrefLevel [Byte0]: 46
8689 19:53:06.783236 [Byte1]: 46
8690 19:53:06.787589
8691 19:53:06.787656 Set Vref, RX VrefLevel [Byte0]: 47
8692 19:53:06.790932 [Byte1]: 47
8693 19:53:06.795088
8694 19:53:06.795159 Set Vref, RX VrefLevel [Byte0]: 48
8695 19:53:06.798501 [Byte1]: 48
8696 19:53:06.802993
8697 19:53:06.803067 Set Vref, RX VrefLevel [Byte0]: 49
8698 19:53:06.806306 [Byte1]: 49
8699 19:53:06.810346
8700 19:53:06.810417 Set Vref, RX VrefLevel [Byte0]: 50
8701 19:53:06.813835 [Byte1]: 50
8702 19:53:06.818014
8703 19:53:06.818082 Set Vref, RX VrefLevel [Byte0]: 51
8704 19:53:06.821440 [Byte1]: 51
8705 19:53:06.825919
8706 19:53:06.825987 Set Vref, RX VrefLevel [Byte0]: 52
8707 19:53:06.829512 [Byte1]: 52
8708 19:53:06.833319
8709 19:53:06.833384 Set Vref, RX VrefLevel [Byte0]: 53
8710 19:53:06.836702 [Byte1]: 53
8711 19:53:06.841141
8712 19:53:06.841223 Set Vref, RX VrefLevel [Byte0]: 54
8713 19:53:06.844087 [Byte1]: 54
8714 19:53:06.848899
8715 19:53:06.848967 Set Vref, RX VrefLevel [Byte0]: 55
8716 19:53:06.851775 [Byte1]: 55
8717 19:53:06.856187
8718 19:53:06.856268 Set Vref, RX VrefLevel [Byte0]: 56
8719 19:53:06.859802 [Byte1]: 56
8720 19:53:06.863857
8721 19:53:06.863937 Set Vref, RX VrefLevel [Byte0]: 57
8722 19:53:06.867549 [Byte1]: 57
8723 19:53:06.871721
8724 19:53:06.871804 Set Vref, RX VrefLevel [Byte0]: 58
8725 19:53:06.874600 [Byte1]: 58
8726 19:53:06.879337
8727 19:53:06.879459 Set Vref, RX VrefLevel [Byte0]: 59
8728 19:53:06.882233 [Byte1]: 59
8729 19:53:06.886879
8730 19:53:06.886959 Set Vref, RX VrefLevel [Byte0]: 60
8731 19:53:06.890007 [Byte1]: 60
8732 19:53:06.894398
8733 19:53:06.894478 Set Vref, RX VrefLevel [Byte0]: 61
8734 19:53:06.897649 [Byte1]: 61
8735 19:53:06.901770
8736 19:53:06.901850 Set Vref, RX VrefLevel [Byte0]: 62
8737 19:53:06.905027 [Byte1]: 62
8738 19:53:06.909805
8739 19:53:06.909885 Set Vref, RX VrefLevel [Byte0]: 63
8740 19:53:06.913117 [Byte1]: 63
8741 19:53:06.917191
8742 19:53:06.917271 Set Vref, RX VrefLevel [Byte0]: 64
8743 19:53:06.920804 [Byte1]: 64
8744 19:53:06.924936
8745 19:53:06.925017 Set Vref, RX VrefLevel [Byte0]: 65
8746 19:53:06.928483 [Byte1]: 65
8747 19:53:06.932700
8748 19:53:06.932781 Set Vref, RX VrefLevel [Byte0]: 66
8749 19:53:06.935623 [Byte1]: 66
8750 19:53:06.940051
8751 19:53:06.940131 Set Vref, RX VrefLevel [Byte0]: 67
8752 19:53:06.943179 [Byte1]: 67
8753 19:53:06.947861
8754 19:53:06.947941 Set Vref, RX VrefLevel [Byte0]: 68
8755 19:53:06.950905 [Byte1]: 68
8756 19:53:06.955790
8757 19:53:06.955870 Final RX Vref Byte 0 = 56 to rank0
8758 19:53:06.958377 Final RX Vref Byte 1 = 51 to rank0
8759 19:53:06.961565 Final RX Vref Byte 0 = 56 to rank1
8760 19:53:06.965332 Final RX Vref Byte 1 = 51 to rank1==
8761 19:53:06.968599 Dram Type= 6, Freq= 0, CH_1, rank 0
8762 19:53:06.974947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 19:53:06.975029 ==
8764 19:53:06.975093 DQS Delay:
8765 19:53:06.978567 DQS0 = 0, DQS1 = 0
8766 19:53:06.978647 DQM Delay:
8767 19:53:06.978711 DQM0 = 131, DQM1 = 123
8768 19:53:06.981497 DQ Delay:
8769 19:53:06.984933 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8770 19:53:06.988288 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8771 19:53:06.991784 DQ8 =110, DQ9 =112, DQ10 =122, DQ11 =116
8772 19:53:06.995276 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =132
8773 19:53:06.995357
8774 19:53:06.995466
8775 19:53:06.995527
8776 19:53:06.998486 [DramC_TX_OE_Calibration] TA2
8777 19:53:07.001605 Original DQ_B0 (3 6) =30, OEN = 27
8778 19:53:07.005043 Original DQ_B1 (3 6) =30, OEN = 27
8779 19:53:07.008502 24, 0x0, End_B0=24 End_B1=24
8780 19:53:07.008584 25, 0x0, End_B0=25 End_B1=25
8781 19:53:07.011815 26, 0x0, End_B0=26 End_B1=26
8782 19:53:07.015108 27, 0x0, End_B0=27 End_B1=27
8783 19:53:07.018302 28, 0x0, End_B0=28 End_B1=28
8784 19:53:07.021408 29, 0x0, End_B0=29 End_B1=29
8785 19:53:07.021491 30, 0x0, End_B0=30 End_B1=30
8786 19:53:07.024898 31, 0x5151, End_B0=30 End_B1=30
8787 19:53:07.028121 Byte0 end_step=30 best_step=27
8788 19:53:07.031217 Byte1 end_step=30 best_step=27
8789 19:53:07.034980 Byte0 TX OE(2T, 0.5T) = (3, 3)
8790 19:53:07.037961 Byte1 TX OE(2T, 0.5T) = (3, 3)
8791 19:53:07.038042
8792 19:53:07.038105
8793 19:53:07.044414 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8794 19:53:07.048417 CH1 RK0: MR19=303, MR18=B0F
8795 19:53:07.055083 CH1_RK0: MR19=0x303, MR18=0xB0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8796 19:53:07.055163
8797 19:53:07.058086 ----->DramcWriteLeveling(PI) begin...
8798 19:53:07.058169 ==
8799 19:53:07.061054 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 19:53:07.064470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 19:53:07.064551 ==
8802 19:53:07.068181 Write leveling (Byte 0): 23 => 23
8803 19:53:07.071071 Write leveling (Byte 1): 27 => 27
8804 19:53:07.074467 DramcWriteLeveling(PI) end<-----
8805 19:53:07.074547
8806 19:53:07.074610 ==
8807 19:53:07.078168 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 19:53:07.081511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 19:53:07.081592 ==
8810 19:53:07.084687 [Gating] SW mode calibration
8811 19:53:07.092022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8812 19:53:07.098305 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8813 19:53:07.101615 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 19:53:07.104555 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8815 19:53:07.111303 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8816 19:53:07.114863 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
8817 19:53:07.117860 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 19:53:07.124446 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 19:53:07.127620 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 19:53:07.131242 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 19:53:07.138022 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 19:53:07.141477 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 19:53:07.144865 1 5 8 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (1 0)
8824 19:53:07.151468 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8825 19:53:07.154385 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 19:53:07.157832 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 19:53:07.164519 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 19:53:07.168137 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 19:53:07.170906 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 19:53:07.177650 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8831 19:53:07.181091 1 6 8 | B1->B0 | 2626 4444 | 0 0 | (0 0) (0 0)
8832 19:53:07.184654 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8833 19:53:07.191109 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 19:53:07.194111 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 19:53:07.197465 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 19:53:07.200774 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 19:53:07.207840 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 19:53:07.211321 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 19:53:07.214770 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8840 19:53:07.220655 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8841 19:53:07.224220 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 19:53:07.227264 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 19:53:07.234053 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 19:53:07.237772 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 19:53:07.240746 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 19:53:07.247877 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 19:53:07.250698 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 19:53:07.254490 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 19:53:07.260754 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 19:53:07.263916 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 19:53:07.267314 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 19:53:07.273935 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 19:53:07.277510 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 19:53:07.280445 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 19:53:07.287648 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8856 19:53:07.290484 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 19:53:07.293798 Total UI for P1: 0, mck2ui 16
8858 19:53:07.297552 best dqsien dly found for B0: ( 1, 9, 8)
8859 19:53:07.300566 Total UI for P1: 0, mck2ui 16
8860 19:53:07.303940 best dqsien dly found for B1: ( 1, 9, 10)
8861 19:53:07.307470 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8862 19:53:07.310450 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8863 19:53:07.310530
8864 19:53:07.314234 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8865 19:53:07.317458 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8866 19:53:07.320517 [Gating] SW calibration Done
8867 19:53:07.320607 ==
8868 19:53:07.324178 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 19:53:07.327218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 19:53:07.327299 ==
8871 19:53:07.330569 RX Vref Scan: 0
8872 19:53:07.330650
8873 19:53:07.333805 RX Vref 0 -> 0, step: 1
8874 19:53:07.333885
8875 19:53:07.333948 RX Delay 0 -> 252, step: 8
8876 19:53:07.340283 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8877 19:53:07.343960 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8878 19:53:07.346717 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8879 19:53:07.350012 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8880 19:53:07.353639 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8881 19:53:07.360099 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8882 19:53:07.363436 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8883 19:53:07.366923 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8884 19:53:07.370009 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8885 19:53:07.373522 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8886 19:53:07.380040 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8887 19:53:07.383397 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8888 19:53:07.386966 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8889 19:53:07.389923 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8890 19:53:07.396585 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8891 19:53:07.400040 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8892 19:53:07.400122 ==
8893 19:53:07.403541 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 19:53:07.406592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 19:53:07.406673 ==
8896 19:53:07.406738 DQS Delay:
8897 19:53:07.409987 DQS0 = 0, DQS1 = 0
8898 19:53:07.410099 DQM Delay:
8899 19:53:07.413538 DQM0 = 129, DQM1 = 126
8900 19:53:07.413618 DQ Delay:
8901 19:53:07.416911 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =123
8902 19:53:07.420172 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =127
8903 19:53:07.423154 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8904 19:53:07.429874 DQ12 =131, DQ13 =135, DQ14 =131, DQ15 =131
8905 19:53:07.429955
8906 19:53:07.430018
8907 19:53:07.430077 ==
8908 19:53:07.433256 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 19:53:07.436598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 19:53:07.436679 ==
8911 19:53:07.436743
8912 19:53:07.436801
8913 19:53:07.439706 TX Vref Scan disable
8914 19:53:07.439786 == TX Byte 0 ==
8915 19:53:07.446597 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8916 19:53:07.449669 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8917 19:53:07.449749 == TX Byte 1 ==
8918 19:53:07.456312 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8919 19:53:07.459520 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8920 19:53:07.459601 ==
8921 19:53:07.462916 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 19:53:07.466079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 19:53:07.466160 ==
8924 19:53:07.481026
8925 19:53:07.484648 TX Vref early break, caculate TX vref
8926 19:53:07.488227 TX Vref=16, minBit 0, minWin=23, winSum=379
8927 19:53:07.491202 TX Vref=18, minBit 0, minWin=23, winSum=393
8928 19:53:07.494798 TX Vref=20, minBit 0, minWin=24, winSum=401
8929 19:53:07.497698 TX Vref=22, minBit 0, minWin=24, winSum=407
8930 19:53:07.501059 TX Vref=24, minBit 0, minWin=25, winSum=417
8931 19:53:07.508106 TX Vref=26, minBit 0, minWin=25, winSum=418
8932 19:53:07.511070 TX Vref=28, minBit 1, minWin=25, winSum=422
8933 19:53:07.514571 TX Vref=30, minBit 0, minWin=24, winSum=418
8934 19:53:07.517577 TX Vref=32, minBit 1, minWin=24, winSum=410
8935 19:53:07.521080 TX Vref=34, minBit 1, minWin=23, winSum=402
8936 19:53:07.524350 TX Vref=36, minBit 5, minWin=22, winSum=390
8937 19:53:07.530941 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
8938 19:53:07.531023
8939 19:53:07.534473 Final TX Range 0 Vref 28
8940 19:53:07.534554
8941 19:53:07.534617 ==
8942 19:53:07.537793 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 19:53:07.541107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 19:53:07.541189 ==
8945 19:53:07.541253
8946 19:53:07.544051
8947 19:53:07.544158 TX Vref Scan disable
8948 19:53:07.550730 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8949 19:53:07.550815 == TX Byte 0 ==
8950 19:53:07.554312 u2DelayCellOfst[0]=18 cells (5 PI)
8951 19:53:07.557618 u2DelayCellOfst[1]=11 cells (3 PI)
8952 19:53:07.561097 u2DelayCellOfst[2]=0 cells (0 PI)
8953 19:53:07.564300 u2DelayCellOfst[3]=3 cells (1 PI)
8954 19:53:07.567766 u2DelayCellOfst[4]=7 cells (2 PI)
8955 19:53:07.570927 u2DelayCellOfst[5]=18 cells (5 PI)
8956 19:53:07.574100 u2DelayCellOfst[6]=18 cells (5 PI)
8957 19:53:07.577159 u2DelayCellOfst[7]=3 cells (1 PI)
8958 19:53:07.580813 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8959 19:53:07.583910 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8960 19:53:07.587351 == TX Byte 1 ==
8961 19:53:07.590484 u2DelayCellOfst[8]=0 cells (0 PI)
8962 19:53:07.594031 u2DelayCellOfst[9]=7 cells (2 PI)
8963 19:53:07.594112 u2DelayCellOfst[10]=15 cells (4 PI)
8964 19:53:07.597048 u2DelayCellOfst[11]=7 cells (2 PI)
8965 19:53:07.600439 u2DelayCellOfst[12]=18 cells (5 PI)
8966 19:53:07.603882 u2DelayCellOfst[13]=18 cells (5 PI)
8967 19:53:07.606912 u2DelayCellOfst[14]=18 cells (5 PI)
8968 19:53:07.610428 u2DelayCellOfst[15]=18 cells (5 PI)
8969 19:53:07.616917 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8970 19:53:07.620491 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8971 19:53:07.620572 DramC Write-DBI on
8972 19:53:07.620635 ==
8973 19:53:07.624074 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 19:53:07.630290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 19:53:07.630371 ==
8976 19:53:07.630435
8977 19:53:07.630493
8978 19:53:07.630549 TX Vref Scan disable
8979 19:53:07.634279 == TX Byte 0 ==
8980 19:53:07.637956 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8981 19:53:07.640815 == TX Byte 1 ==
8982 19:53:07.644457 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8983 19:53:07.647403 DramC Write-DBI off
8984 19:53:07.647483
8985 19:53:07.647546 [DATLAT]
8986 19:53:07.647605 Freq=1600, CH1 RK1
8987 19:53:07.647662
8988 19:53:07.650899 DATLAT Default: 0xf
8989 19:53:07.654370 0, 0xFFFF, sum = 0
8990 19:53:07.654453 1, 0xFFFF, sum = 0
8991 19:53:07.657360 2, 0xFFFF, sum = 0
8992 19:53:07.657441 3, 0xFFFF, sum = 0
8993 19:53:07.661003 4, 0xFFFF, sum = 0
8994 19:53:07.661084 5, 0xFFFF, sum = 0
8995 19:53:07.664101 6, 0xFFFF, sum = 0
8996 19:53:07.664183 7, 0xFFFF, sum = 0
8997 19:53:07.667497 8, 0xFFFF, sum = 0
8998 19:53:07.667579 9, 0xFFFF, sum = 0
8999 19:53:07.670646 10, 0xFFFF, sum = 0
9000 19:53:07.670727 11, 0xFFFF, sum = 0
9001 19:53:07.674260 12, 0xFFFF, sum = 0
9002 19:53:07.674341 13, 0x8FFF, sum = 0
9003 19:53:07.677477 14, 0x0, sum = 1
9004 19:53:07.677559 15, 0x0, sum = 2
9005 19:53:07.680592 16, 0x0, sum = 3
9006 19:53:07.680673 17, 0x0, sum = 4
9007 19:53:07.683823 best_step = 15
9008 19:53:07.683943
9009 19:53:07.684010 ==
9010 19:53:07.687167 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 19:53:07.690842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 19:53:07.690921 ==
9013 19:53:07.693816 RX Vref Scan: 0
9014 19:53:07.693893
9015 19:53:07.693978 RX Vref 0 -> 0, step: 1
9016 19:53:07.694069
9017 19:53:07.697171 RX Delay 3 -> 252, step: 4
9018 19:53:07.704209 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9019 19:53:07.707132 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9020 19:53:07.710954 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9021 19:53:07.714021 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
9022 19:53:07.717139 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9023 19:53:07.720618 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9024 19:53:07.727096 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9025 19:53:07.730715 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9026 19:53:07.734235 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
9027 19:53:07.737587 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
9028 19:53:07.740396 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9029 19:53:07.746911 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9030 19:53:07.750411 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9031 19:53:07.753377 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9032 19:53:07.757044 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9033 19:53:07.763408 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9034 19:53:07.763505 ==
9035 19:53:07.767150 Dram Type= 6, Freq= 0, CH_1, rank 1
9036 19:53:07.770364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9037 19:53:07.770444 ==
9038 19:53:07.770507 DQS Delay:
9039 19:53:07.773480 DQS0 = 0, DQS1 = 0
9040 19:53:07.773566 DQM Delay:
9041 19:53:07.777008 DQM0 = 128, DQM1 = 125
9042 19:53:07.777087 DQ Delay:
9043 19:53:07.780028 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =126
9044 19:53:07.783346 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9045 19:53:07.786684 DQ8 =108, DQ9 =114, DQ10 =128, DQ11 =120
9046 19:53:07.789781 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
9047 19:53:07.789865
9048 19:53:07.793372
9049 19:53:07.793451
9050 19:53:07.793515 [DramC_TX_OE_Calibration] TA2
9051 19:53:07.796788 Original DQ_B0 (3 6) =30, OEN = 27
9052 19:53:07.800076 Original DQ_B1 (3 6) =30, OEN = 27
9053 19:53:07.803040 24, 0x0, End_B0=24 End_B1=24
9054 19:53:07.806554 25, 0x0, End_B0=25 End_B1=25
9055 19:53:07.809577 26, 0x0, End_B0=26 End_B1=26
9056 19:53:07.809659 27, 0x0, End_B0=27 End_B1=27
9057 19:53:07.813041 28, 0x0, End_B0=28 End_B1=28
9058 19:53:07.816292 29, 0x0, End_B0=29 End_B1=29
9059 19:53:07.820037 30, 0x0, End_B0=30 End_B1=30
9060 19:53:07.822864 31, 0x4545, End_B0=30 End_B1=30
9061 19:53:07.822952 Byte0 end_step=30 best_step=27
9062 19:53:07.826507 Byte1 end_step=30 best_step=27
9063 19:53:07.830014 Byte0 TX OE(2T, 0.5T) = (3, 3)
9064 19:53:07.833124 Byte1 TX OE(2T, 0.5T) = (3, 3)
9065 19:53:07.833197
9066 19:53:07.833289
9067 19:53:07.839991 [DQSOSCAuto] RK1, (LSB)MR18= 0x131f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9068 19:53:07.842905 CH1 RK1: MR19=303, MR18=131F
9069 19:53:07.849726 CH1_RK1: MR19=0x303, MR18=0x131F, DQSOSC=394, MR23=63, INC=23, DEC=15
9070 19:53:07.853463 [RxdqsGatingPostProcess] freq 1600
9071 19:53:07.859371 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9072 19:53:07.862871 best DQS0 dly(2T, 0.5T) = (1, 1)
9073 19:53:07.862976 best DQS1 dly(2T, 0.5T) = (1, 1)
9074 19:53:07.866584 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9075 19:53:07.869565 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9076 19:53:07.873075 best DQS0 dly(2T, 0.5T) = (1, 1)
9077 19:53:07.876500 best DQS1 dly(2T, 0.5T) = (1, 1)
9078 19:53:07.879301 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9079 19:53:07.883106 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9080 19:53:07.886533 Pre-setting of DQS Precalculation
9081 19:53:07.889471 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9082 19:53:07.899548 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9083 19:53:07.905948 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9084 19:53:07.906059
9085 19:53:07.906153
9086 19:53:07.909838 [Calibration Summary] 3200 Mbps
9087 19:53:07.909912 CH 0, Rank 0
9088 19:53:07.912882 SW Impedance : PASS
9089 19:53:07.916142 DUTY Scan : NO K
9090 19:53:07.916219 ZQ Calibration : PASS
9091 19:53:07.919739 Jitter Meter : NO K
9092 19:53:07.919840 CBT Training : PASS
9093 19:53:07.922577 Write leveling : PASS
9094 19:53:07.925999 RX DQS gating : PASS
9095 19:53:07.926099 RX DQ/DQS(RDDQC) : PASS
9096 19:53:07.928896 TX DQ/DQS : PASS
9097 19:53:07.932528 RX DATLAT : PASS
9098 19:53:07.932627 RX DQ/DQS(Engine): PASS
9099 19:53:07.935802 TX OE : PASS
9100 19:53:07.935879 All Pass.
9101 19:53:07.935946
9102 19:53:07.938901 CH 0, Rank 1
9103 19:53:07.939003 SW Impedance : PASS
9104 19:53:07.942319 DUTY Scan : NO K
9105 19:53:07.945915 ZQ Calibration : PASS
9106 19:53:07.946021 Jitter Meter : NO K
9107 19:53:07.948717 CBT Training : PASS
9108 19:53:07.952376 Write leveling : PASS
9109 19:53:07.952454 RX DQS gating : PASS
9110 19:53:07.955896 RX DQ/DQS(RDDQC) : PASS
9111 19:53:07.958892 TX DQ/DQS : PASS
9112 19:53:07.958994 RX DATLAT : PASS
9113 19:53:07.962389 RX DQ/DQS(Engine): PASS
9114 19:53:07.965141 TX OE : PASS
9115 19:53:07.965240 All Pass.
9116 19:53:07.965332
9117 19:53:07.965419 CH 1, Rank 0
9118 19:53:07.968756 SW Impedance : PASS
9119 19:53:07.972260 DUTY Scan : NO K
9120 19:53:07.972336 ZQ Calibration : PASS
9121 19:53:07.975286 Jitter Meter : NO K
9122 19:53:07.978885 CBT Training : PASS
9123 19:53:07.978984 Write leveling : PASS
9124 19:53:07.981857 RX DQS gating : PASS
9125 19:53:07.985258 RX DQ/DQS(RDDQC) : PASS
9126 19:53:07.985357 TX DQ/DQS : PASS
9127 19:53:07.988406 RX DATLAT : PASS
9128 19:53:07.988481 RX DQ/DQS(Engine): PASS
9129 19:53:07.992301 TX OE : PASS
9130 19:53:07.992439 All Pass.
9131 19:53:07.992516
9132 19:53:07.995167 CH 1, Rank 1
9133 19:53:07.995265 SW Impedance : PASS
9134 19:53:07.998509 DUTY Scan : NO K
9135 19:53:08.001602 ZQ Calibration : PASS
9136 19:53:08.001700 Jitter Meter : NO K
9137 19:53:08.004872 CBT Training : PASS
9138 19:53:08.008701 Write leveling : PASS
9139 19:53:08.008799 RX DQS gating : PASS
9140 19:53:08.011673 RX DQ/DQS(RDDQC) : PASS
9141 19:53:08.014981 TX DQ/DQS : PASS
9142 19:53:08.015088 RX DATLAT : PASS
9143 19:53:08.018579 RX DQ/DQS(Engine): PASS
9144 19:53:08.021803 TX OE : PASS
9145 19:53:08.021878 All Pass.
9146 19:53:08.021959
9147 19:53:08.022019 DramC Write-DBI on
9148 19:53:08.025230 PER_BANK_REFRESH: Hybrid Mode
9149 19:53:08.028552 TX_TRACKING: ON
9150 19:53:08.034978 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9151 19:53:08.044948 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9152 19:53:08.051284 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9153 19:53:08.055338 [FAST_K] Save calibration result to emmc
9154 19:53:08.058319 sync common calibartion params.
9155 19:53:08.061572 sync cbt_mode0:1, 1:1
9156 19:53:08.061678 dram_init: ddr_geometry: 2
9157 19:53:08.064717 dram_init: ddr_geometry: 2
9158 19:53:08.068031 dram_init: ddr_geometry: 2
9159 19:53:08.068130 0:dram_rank_size:100000000
9160 19:53:08.071613 1:dram_rank_size:100000000
9161 19:53:08.078057 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9162 19:53:08.081819 DFS_SHUFFLE_HW_MODE: ON
9163 19:53:08.084703 dramc_set_vcore_voltage set vcore to 725000
9164 19:53:08.084776 Read voltage for 1600, 0
9165 19:53:08.088014 Vio18 = 0
9166 19:53:08.088082 Vcore = 725000
9167 19:53:08.088142 Vdram = 0
9168 19:53:08.091653 Vddq = 0
9169 19:53:08.091719 Vmddr = 0
9170 19:53:08.094990 switch to 3200 Mbps bootup
9171 19:53:08.095059 [DramcRunTimeConfig]
9172 19:53:08.095118 PHYPLL
9173 19:53:08.097887 DPM_CONTROL_AFTERK: ON
9174 19:53:08.101153 PER_BANK_REFRESH: ON
9175 19:53:08.101228 REFRESH_OVERHEAD_REDUCTION: ON
9176 19:53:08.104776 CMD_PICG_NEW_MODE: OFF
9177 19:53:08.107809 XRTWTW_NEW_MODE: ON
9178 19:53:08.107876 XRTRTR_NEW_MODE: ON
9179 19:53:08.111146 TX_TRACKING: ON
9180 19:53:08.111219 RDSEL_TRACKING: OFF
9181 19:53:08.114524 DQS Precalculation for DVFS: ON
9182 19:53:08.114619 RX_TRACKING: OFF
9183 19:53:08.117989 HW_GATING DBG: ON
9184 19:53:08.121003 ZQCS_ENABLE_LP4: ON
9185 19:53:08.121101 RX_PICG_NEW_MODE: ON
9186 19:53:08.124345 TX_PICG_NEW_MODE: ON
9187 19:53:08.124419 ENABLE_RX_DCM_DPHY: ON
9188 19:53:08.127584 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9189 19:53:08.131016 DUMMY_READ_FOR_TRACKING: OFF
9190 19:53:08.134152 !!! SPM_CONTROL_AFTERK: OFF
9191 19:53:08.137611 !!! SPM could not control APHY
9192 19:53:08.137712 IMPEDANCE_TRACKING: ON
9193 19:53:08.140903 TEMP_SENSOR: ON
9194 19:53:08.140978 HW_SAVE_FOR_SR: OFF
9195 19:53:08.144286 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9196 19:53:08.147985 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9197 19:53:08.151341 Read ODT Tracking: ON
9198 19:53:08.154501 Refresh Rate DeBounce: ON
9199 19:53:08.154609 DFS_NO_QUEUE_FLUSH: ON
9200 19:53:08.157438 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9201 19:53:08.160841 ENABLE_DFS_RUNTIME_MRW: OFF
9202 19:53:08.164115 DDR_RESERVE_NEW_MODE: ON
9203 19:53:08.164220 MR_CBT_SWITCH_FREQ: ON
9204 19:53:08.167484 =========================
9205 19:53:08.186323 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9206 19:53:08.189274 dram_init: ddr_geometry: 2
9207 19:53:08.207281 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9208 19:53:08.211197 dram_init: dram init end (result: 0)
9209 19:53:08.217536 DRAM-K: Full calibration passed in 24549 msecs
9210 19:53:08.220868 MRC: failed to locate region type 0.
9211 19:53:08.220970 DRAM rank0 size:0x100000000,
9212 19:53:08.224387 DRAM rank1 size=0x100000000
9213 19:53:08.234434 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9214 19:53:08.240801 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9215 19:53:08.247170 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9216 19:53:08.253866 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9217 19:53:08.256968 DRAM rank0 size:0x100000000,
9218 19:53:08.260577 DRAM rank1 size=0x100000000
9219 19:53:08.260662 CBMEM:
9220 19:53:08.263502 IMD: root @ 0xfffff000 254 entries.
9221 19:53:08.267378 IMD: root @ 0xffffec00 62 entries.
9222 19:53:08.270488 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9223 19:53:08.276740 WARNING: RO_VPD is uninitialized or empty.
9224 19:53:08.280311 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9225 19:53:08.287845 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9226 19:53:08.300287 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9227 19:53:08.311875 BS: romstage times (exec / console): total (unknown) / 24015 ms
9228 19:53:08.311960
9229 19:53:08.312046
9230 19:53:08.321401 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9231 19:53:08.325036 ARM64: Exception handlers installed.
9232 19:53:08.328533 ARM64: Testing exception
9233 19:53:08.331696 ARM64: Done test exception
9234 19:53:08.331779 Enumerating buses...
9235 19:53:08.334736 Show all devs... Before device enumeration.
9236 19:53:08.338275 Root Device: enabled 1
9237 19:53:08.341348 CPU_CLUSTER: 0: enabled 1
9238 19:53:08.341431 CPU: 00: enabled 1
9239 19:53:08.344814 Compare with tree...
9240 19:53:08.344895 Root Device: enabled 1
9241 19:53:08.348443 CPU_CLUSTER: 0: enabled 1
9242 19:53:08.351201 CPU: 00: enabled 1
9243 19:53:08.351282 Root Device scanning...
9244 19:53:08.354637 scan_static_bus for Root Device
9245 19:53:08.357954 CPU_CLUSTER: 0 enabled
9246 19:53:08.361395 scan_static_bus for Root Device done
9247 19:53:08.364559 scan_bus: bus Root Device finished in 8 msecs
9248 19:53:08.364641 done
9249 19:53:08.371417 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9250 19:53:08.375011 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9251 19:53:08.381466 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9252 19:53:08.384404 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9253 19:53:08.387730 Allocating resources...
9254 19:53:08.391293 Reading resources...
9255 19:53:08.394244 Root Device read_resources bus 0 link: 0
9256 19:53:08.397463 DRAM rank0 size:0x100000000,
9257 19:53:08.397547 DRAM rank1 size=0x100000000
9258 19:53:08.400954 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9259 19:53:08.404404 CPU: 00 missing read_resources
9260 19:53:08.411101 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9261 19:53:08.414170 Root Device read_resources bus 0 link: 0 done
9262 19:53:08.414254 Done reading resources.
9263 19:53:08.420974 Show resources in subtree (Root Device)...After reading.
9264 19:53:08.424264 Root Device child on link 0 CPU_CLUSTER: 0
9265 19:53:08.427629 CPU_CLUSTER: 0 child on link 0 CPU: 00
9266 19:53:08.437354 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9267 19:53:08.437440 CPU: 00
9268 19:53:08.440639 Root Device assign_resources, bus 0 link: 0
9269 19:53:08.443817 CPU_CLUSTER: 0 missing set_resources
9270 19:53:08.451006 Root Device assign_resources, bus 0 link: 0 done
9271 19:53:08.451095 Done setting resources.
9272 19:53:08.457536 Show resources in subtree (Root Device)...After assigning values.
9273 19:53:08.460518 Root Device child on link 0 CPU_CLUSTER: 0
9274 19:53:08.464019 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 19:53:08.473948 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 19:53:08.474033 CPU: 00
9277 19:53:08.477153 Done allocating resources.
9278 19:53:08.483607 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9279 19:53:08.483693 Enabling resources...
9280 19:53:08.483779 done.
9281 19:53:08.490411 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9282 19:53:08.490496 Initializing devices...
9283 19:53:08.493909 Root Device init
9284 19:53:08.493993 init hardware done!
9285 19:53:08.496786 0x00000018: ctrlr->caps
9286 19:53:08.500319 52.000 MHz: ctrlr->f_max
9287 19:53:08.500405 0.400 MHz: ctrlr->f_min
9288 19:53:08.503596 0x40ff8080: ctrlr->voltages
9289 19:53:08.507191 sclk: 390625
9290 19:53:08.507276 Bus Width = 1
9291 19:53:08.507377 sclk: 390625
9292 19:53:08.510701 Bus Width = 1
9293 19:53:08.510820 Early init status = 3
9294 19:53:08.516891 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9295 19:53:08.520115 in-header: 03 fc 00 00 01 00 00 00
9296 19:53:08.523514 in-data: 00
9297 19:53:08.526760 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9298 19:53:08.530651 in-header: 03 fd 00 00 00 00 00 00
9299 19:53:08.533965 in-data:
9300 19:53:08.537464 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9301 19:53:08.542039 in-header: 03 fc 00 00 01 00 00 00
9302 19:53:08.544770 in-data: 00
9303 19:53:08.548345 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9304 19:53:08.554221 in-header: 03 fd 00 00 00 00 00 00
9305 19:53:08.557172 in-data:
9306 19:53:08.560832 [SSUSB] Setting up USB HOST controller...
9307 19:53:08.563922 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9308 19:53:08.566937 [SSUSB] phy power-on done.
9309 19:53:08.570485 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9310 19:53:08.577098 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9311 19:53:08.580518 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9312 19:53:08.587097 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9313 19:53:08.593636 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9314 19:53:08.600416 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9315 19:53:08.606778 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9316 19:53:08.613320 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9317 19:53:08.616798 SPM: binary array size = 0x9dc
9318 19:53:08.620115 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9319 19:53:08.626797 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9320 19:53:08.633450 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9321 19:53:08.640300 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9322 19:53:08.643481 configure_display: Starting display init
9323 19:53:08.677267 anx7625_power_on_init: Init interface.
9324 19:53:08.680789 anx7625_disable_pd_protocol: Disabled PD feature.
9325 19:53:08.683584 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9326 19:53:08.711572 anx7625_start_dp_work: Secure OCM version=00
9327 19:53:08.714688 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9328 19:53:08.729779 sp_tx_get_edid_block: EDID Block = 1
9329 19:53:08.832063 Extracted contents:
9330 19:53:08.835699 header: 00 ff ff ff ff ff ff 00
9331 19:53:08.838648 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9332 19:53:08.841955 version: 01 04
9333 19:53:08.845186 basic params: 95 1f 11 78 0a
9334 19:53:08.848827 chroma info: 76 90 94 55 54 90 27 21 50 54
9335 19:53:08.852195 established: 00 00 00
9336 19:53:08.858727 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9337 19:53:08.865336 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9338 19:53:08.868903 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9339 19:53:08.875169 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9340 19:53:08.881622 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9341 19:53:08.885185 extensions: 00
9342 19:53:08.885266 checksum: fb
9343 19:53:08.885331
9344 19:53:08.891789 Manufacturer: IVO Model 57d Serial Number 0
9345 19:53:08.891871 Made week 0 of 2020
9346 19:53:08.894758 EDID version: 1.4
9347 19:53:08.894839 Digital display
9348 19:53:08.898249 6 bits per primary color channel
9349 19:53:08.898332 DisplayPort interface
9350 19:53:08.901202 Maximum image size: 31 cm x 17 cm
9351 19:53:08.904523 Gamma: 220%
9352 19:53:08.904604 Check DPMS levels
9353 19:53:08.911607 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9354 19:53:08.914362 First detailed timing is preferred timing
9355 19:53:08.914443 Established timings supported:
9356 19:53:08.918046 Standard timings supported:
9357 19:53:08.921552 Detailed timings
9358 19:53:08.924351 Hex of detail: 383680a07038204018303c0035ae10000019
9359 19:53:08.930950 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9360 19:53:08.934516 0780 0798 07c8 0820 hborder 0
9361 19:53:08.937884 0438 043b 0447 0458 vborder 0
9362 19:53:08.941300 -hsync -vsync
9363 19:53:08.941409 Did detailed timing
9364 19:53:08.947607 Hex of detail: 000000000000000000000000000000000000
9365 19:53:08.951039 Manufacturer-specified data, tag 0
9366 19:53:08.954301 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9367 19:53:08.957748 ASCII string: InfoVision
9368 19:53:08.961083 Hex of detail: 000000fe00523134304e574635205248200a
9369 19:53:08.964267 ASCII string: R140NWF5 RH
9370 19:53:08.964348 Checksum
9371 19:53:08.967887 Checksum: 0xfb (valid)
9372 19:53:08.970746 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9373 19:53:08.974123 DSI data_rate: 832800000 bps
9374 19:53:08.981106 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9375 19:53:08.984198 anx7625_parse_edid: pixelclock(138800).
9376 19:53:08.987765 hactive(1920), hsync(48), hfp(24), hbp(88)
9377 19:53:08.990941 vactive(1080), vsync(12), vfp(3), vbp(17)
9378 19:53:08.994515 anx7625_dsi_config: config dsi.
9379 19:53:09.001160 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9380 19:53:09.013937 anx7625_dsi_config: success to config DSI
9381 19:53:09.017496 anx7625_dp_start: MIPI phy setup OK.
9382 19:53:09.021016 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9383 19:53:09.023822 mtk_ddp_mode_set invalid vrefresh 60
9384 19:53:09.027539 main_disp_path_setup
9385 19:53:09.027619 ovl_layer_smi_id_en
9386 19:53:09.030670 ovl_layer_smi_id_en
9387 19:53:09.030749 ccorr_config
9388 19:53:09.030813 aal_config
9389 19:53:09.033888 gamma_config
9390 19:53:09.033967 postmask_config
9391 19:53:09.037567 dither_config
9392 19:53:09.040766 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9393 19:53:09.047728 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9394 19:53:09.050456 Root Device init finished in 553 msecs
9395 19:53:09.053963 CPU_CLUSTER: 0 init
9396 19:53:09.060394 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9397 19:53:09.067158 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9398 19:53:09.067239 APU_MBOX 0x190000b0 = 0x10001
9399 19:53:09.070231 APU_MBOX 0x190001b0 = 0x10001
9400 19:53:09.073780 APU_MBOX 0x190005b0 = 0x10001
9401 19:53:09.077044 APU_MBOX 0x190006b0 = 0x10001
9402 19:53:09.083615 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9403 19:53:09.093246 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9404 19:53:09.105930 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9405 19:53:09.112459 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9406 19:53:09.124175 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9407 19:53:09.133061 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9408 19:53:09.136163 CPU_CLUSTER: 0 init finished in 81 msecs
9409 19:53:09.139614 Devices initialized
9410 19:53:09.143139 Show all devs... After init.
9411 19:53:09.143219 Root Device: enabled 1
9412 19:53:09.146060 CPU_CLUSTER: 0: enabled 1
9413 19:53:09.149433 CPU: 00: enabled 1
9414 19:53:09.153145 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9415 19:53:09.156240 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9416 19:53:09.159707 ELOG: NV offset 0x57f000 size 0x1000
9417 19:53:09.166382 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9418 19:53:09.172672 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9419 19:53:09.176060 ELOG: Event(17) added with size 13 at 2023-10-28 19:53:10 UTC
9420 19:53:09.182478 out: cmd=0x121: 03 db 21 01 00 00 00 00
9421 19:53:09.185935 in-header: 03 76 00 00 2c 00 00 00
9422 19:53:09.195829 in-data: e9 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9423 19:53:09.202579 ELOG: Event(A1) added with size 10 at 2023-10-28 19:53:10 UTC
9424 19:53:09.209063 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9425 19:53:09.216079 ELOG: Event(A0) added with size 9 at 2023-10-28 19:53:10 UTC
9426 19:53:09.219525 elog_add_boot_reason: Logged dev mode boot
9427 19:53:09.225842 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9428 19:53:09.225925 Finalize devices...
9429 19:53:09.229035 Devices finalized
9430 19:53:09.232292 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9431 19:53:09.235415 Writing coreboot table at 0xffe64000
9432 19:53:09.238810 0. 000000000010a000-0000000000113fff: RAMSTAGE
9433 19:53:09.242271 1. 0000000040000000-00000000400fffff: RAM
9434 19:53:09.248693 2. 0000000040100000-000000004032afff: RAMSTAGE
9435 19:53:09.251741 3. 000000004032b000-00000000545fffff: RAM
9436 19:53:09.255122 4. 0000000054600000-000000005465ffff: BL31
9437 19:53:09.258640 5. 0000000054660000-00000000ffe63fff: RAM
9438 19:53:09.265062 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9439 19:53:09.268598 7. 0000000100000000-000000023fffffff: RAM
9440 19:53:09.272374 Passing 5 GPIOs to payload:
9441 19:53:09.275262 NAME | PORT | POLARITY | VALUE
9442 19:53:09.281641 EC in RW | 0x000000aa | low | undefined
9443 19:53:09.284946 EC interrupt | 0x00000005 | low | undefined
9444 19:53:09.288467 TPM interrupt | 0x000000ab | high | undefined
9445 19:53:09.295020 SD card detect | 0x00000011 | high | undefined
9446 19:53:09.298313 speaker enable | 0x00000093 | high | undefined
9447 19:53:09.301921 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9448 19:53:09.304971 in-header: 03 f9 00 00 02 00 00 00
9449 19:53:09.308077 in-data: 02 00
9450 19:53:09.311600 ADC[4]: Raw value=894821 ID=7
9451 19:53:09.311681 ADC[3]: Raw value=212700 ID=1
9452 19:53:09.314829 RAM Code: 0x71
9453 19:53:09.318033 ADC[6]: Raw value=74722 ID=0
9454 19:53:09.318114 ADC[5]: Raw value=211960 ID=1
9455 19:53:09.321250 SKU Code: 0x1
9456 19:53:09.328332 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 360f
9457 19:53:09.328414 coreboot table: 964 bytes.
9458 19:53:09.331400 IMD ROOT 0. 0xfffff000 0x00001000
9459 19:53:09.334925 IMD SMALL 1. 0xffffe000 0x00001000
9460 19:53:09.338151 RO MCACHE 2. 0xffffc000 0x00001104
9461 19:53:09.341453 CONSOLE 3. 0xfff7c000 0x00080000
9462 19:53:09.344303 FMAP 4. 0xfff7b000 0x00000452
9463 19:53:09.347742 TIME STAMP 5. 0xfff7a000 0x00000910
9464 19:53:09.350945 VBOOT WORK 6. 0xfff66000 0x00014000
9465 19:53:09.354482 RAMOOPS 7. 0xffe66000 0x00100000
9466 19:53:09.357601 COREBOOT 8. 0xffe64000 0x00002000
9467 19:53:09.361116 IMD small region:
9468 19:53:09.364711 IMD ROOT 0. 0xffffec00 0x00000400
9469 19:53:09.367682 VPD 1. 0xffffeb80 0x0000006c
9470 19:53:09.371229 MMC STATUS 2. 0xffffeb60 0x00000004
9471 19:53:09.374639 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9472 19:53:09.377591 Probing TPM: done!
9473 19:53:09.381277 Connected to device vid:did:rid of 1ae0:0028:00
9474 19:53:09.392086 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9475 19:53:09.395234 Initialized TPM device CR50 revision 0
9476 19:53:09.398727 Checking cr50 for pending updates
9477 19:53:09.402952 Reading cr50 TPM mode
9478 19:53:09.411795 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9479 19:53:09.417848 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9480 19:53:09.458298 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9481 19:53:09.461436 Checking segment from ROM address 0x40100000
9482 19:53:09.464716 Checking segment from ROM address 0x4010001c
9483 19:53:09.471557 Loading segment from ROM address 0x40100000
9484 19:53:09.471639 code (compression=0)
9485 19:53:09.481310 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9486 19:53:09.487870 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9487 19:53:09.487953 it's not compressed!
9488 19:53:09.494711 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9489 19:53:09.498109 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9490 19:53:09.518450 Loading segment from ROM address 0x4010001c
9491 19:53:09.518532 Entry Point 0x80000000
9492 19:53:09.521637 Loaded segments
9493 19:53:09.524932 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9494 19:53:09.531431 Jumping to boot code at 0x80000000(0xffe64000)
9495 19:53:09.538571 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9496 19:53:09.545015 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9497 19:53:09.553024 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9498 19:53:09.556743 Checking segment from ROM address 0x40100000
9499 19:53:09.559416 Checking segment from ROM address 0x4010001c
9500 19:53:09.565965 Loading segment from ROM address 0x40100000
9501 19:53:09.566047 code (compression=1)
9502 19:53:09.572851 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9503 19:53:09.582789 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9504 19:53:09.582872 using LZMA
9505 19:53:09.591140 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9506 19:53:09.597839 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9507 19:53:09.601077 Loading segment from ROM address 0x4010001c
9508 19:53:09.601158 Entry Point 0x54601000
9509 19:53:09.604598 Loaded segments
9510 19:53:09.607609 NOTICE: MT8192 bl31_setup
9511 19:53:09.614621 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9512 19:53:09.618221 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9513 19:53:09.621763 WARNING: region 0:
9514 19:53:09.624889 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 19:53:09.624970 WARNING: region 1:
9516 19:53:09.631358 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9517 19:53:09.634586 WARNING: region 2:
9518 19:53:09.638705 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9519 19:53:09.641322 WARNING: region 3:
9520 19:53:09.645163 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9521 19:53:09.647962 WARNING: region 4:
9522 19:53:09.654508 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9523 19:53:09.654590 WARNING: region 5:
9524 19:53:09.657924 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 19:53:09.661125 WARNING: region 6:
9526 19:53:09.664894 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 19:53:09.667909 WARNING: region 7:
9528 19:53:09.671670 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 19:53:09.677966 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9530 19:53:09.680944 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9531 19:53:09.684568 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9532 19:53:09.691503 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9533 19:53:09.694775 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9534 19:53:09.697892 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9535 19:53:09.704729 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9536 19:53:09.708144 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9537 19:53:09.714458 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9538 19:53:09.717707 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9539 19:53:09.721185 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9540 19:53:09.727756 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9541 19:53:09.731193 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9542 19:53:09.734680 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9543 19:53:09.741349 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9544 19:53:09.744981 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9545 19:53:09.751534 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9546 19:53:09.754688 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9547 19:53:09.757925 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9548 19:53:09.764752 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9549 19:53:09.767888 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9550 19:53:09.771296 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9551 19:53:09.777872 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9552 19:53:09.781169 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9553 19:53:09.788450 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9554 19:53:09.791355 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9555 19:53:09.794956 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9556 19:53:09.801348 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9557 19:53:09.805219 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9558 19:53:09.808203 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9559 19:53:09.814933 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9560 19:53:09.818518 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9561 19:53:09.825028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9562 19:53:09.828201 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9563 19:53:09.831539 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9564 19:53:09.834614 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9565 19:53:09.841828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9566 19:53:09.845010 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9567 19:53:09.848367 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9568 19:53:09.851915 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9569 19:53:09.854834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9570 19:53:09.861202 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9571 19:53:09.864852 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9572 19:53:09.868029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9573 19:53:09.874519 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9574 19:53:09.877941 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9575 19:53:09.881164 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9576 19:53:09.884580 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9577 19:53:09.891201 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9578 19:53:09.894605 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9579 19:53:09.901362 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9580 19:53:09.904889 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9581 19:53:09.908275 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9582 19:53:09.915064 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9583 19:53:09.918103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9584 19:53:09.924874 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9585 19:53:09.927985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9586 19:53:09.934548 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9587 19:53:09.938121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9588 19:53:09.941629 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9589 19:53:09.947935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9590 19:53:09.951240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9591 19:53:09.958167 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9592 19:53:09.961151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9593 19:53:09.967668 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9594 19:53:09.970995 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9595 19:53:09.977645 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9596 19:53:09.981222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9597 19:53:09.984548 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9598 19:53:09.991095 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9599 19:53:09.994516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9600 19:53:10.001165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9601 19:53:10.004676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9602 19:53:10.007885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9603 19:53:10.014964 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9604 19:53:10.018107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9605 19:53:10.024473 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9606 19:53:10.028042 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9607 19:53:10.034485 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9608 19:53:10.038102 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9609 19:53:10.044648 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9610 19:53:10.047787 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9611 19:53:10.051550 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9612 19:53:10.057879 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9613 19:53:10.061290 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9614 19:53:10.068036 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9615 19:53:10.071486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9616 19:53:10.078006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9617 19:53:10.080953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9618 19:53:10.084415 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9619 19:53:10.091080 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9620 19:53:10.094573 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9621 19:53:10.100965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9622 19:53:10.104695 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9623 19:53:10.110878 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9624 19:53:10.114335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9625 19:53:10.117592 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9626 19:53:10.124332 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9627 19:53:10.127666 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9628 19:53:10.131577 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9629 19:53:10.134399 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9630 19:53:10.141304 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9631 19:53:10.144740 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9632 19:53:10.151227 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9633 19:53:10.154310 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9634 19:53:10.158237 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9635 19:53:10.164703 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9636 19:53:10.167989 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9637 19:53:10.174572 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9638 19:53:10.178067 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9639 19:53:10.181065 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9640 19:53:10.187657 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9641 19:53:10.191228 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9642 19:53:10.197514 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9643 19:53:10.201297 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9644 19:53:10.204701 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9645 19:53:10.207726 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9646 19:53:10.214797 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9647 19:53:10.217619 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9648 19:53:10.221356 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9649 19:53:10.227843 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9650 19:53:10.230934 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9651 19:53:10.234193 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9652 19:53:10.237818 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9653 19:53:10.244391 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9654 19:53:10.247818 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9655 19:53:10.254015 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9656 19:53:10.257803 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9657 19:53:10.261214 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9658 19:53:10.267820 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9659 19:53:10.271252 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9660 19:53:10.274259 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9661 19:53:10.281448 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9662 19:53:10.284592 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9663 19:53:10.291035 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9664 19:53:10.294662 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9665 19:53:10.298161 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9666 19:53:10.304179 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9667 19:53:10.307576 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9668 19:53:10.314650 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9669 19:53:10.318173 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9670 19:53:10.321047 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9671 19:53:10.327661 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9672 19:53:10.331168 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9673 19:53:10.334590 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9674 19:53:10.341163 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9675 19:53:10.344425 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9676 19:53:10.351178 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9677 19:53:10.354266 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9678 19:53:10.357719 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9679 19:53:10.364717 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9680 19:53:10.368094 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9681 19:53:10.371357 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9682 19:53:10.378138 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9683 19:53:10.381622 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9684 19:53:10.388321 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9685 19:53:10.391683 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9686 19:53:10.394869 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9687 19:53:10.401752 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9688 19:53:10.404669 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9689 19:53:10.411235 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9690 19:53:10.414824 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9691 19:53:10.418154 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9692 19:53:10.424625 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9693 19:53:10.428177 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9694 19:53:10.431203 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9695 19:53:10.437829 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9696 19:53:10.441236 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9697 19:53:10.447855 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9698 19:53:10.451513 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9699 19:53:10.457554 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9700 19:53:10.461253 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9701 19:53:10.464497 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9702 19:53:10.470846 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9703 19:53:10.474485 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9704 19:53:10.477991 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9705 19:53:10.484356 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9706 19:53:10.487365 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9707 19:53:10.494139 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9708 19:53:10.498150 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9709 19:53:10.500621 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9710 19:53:10.507392 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9711 19:53:10.510766 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9712 19:53:10.517537 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9713 19:53:10.521024 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9714 19:53:10.524416 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9715 19:53:10.530708 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9716 19:53:10.534321 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9717 19:53:10.540923 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9718 19:53:10.543823 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9719 19:53:10.547349 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9720 19:53:10.554082 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9721 19:53:10.557043 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9722 19:53:10.563926 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9723 19:53:10.567179 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9724 19:53:10.573570 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9725 19:53:10.577188 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9726 19:53:10.580417 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9727 19:53:10.586970 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9728 19:53:10.590424 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9729 19:53:10.597184 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9730 19:53:10.600284 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9731 19:53:10.603639 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9732 19:53:10.610216 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9733 19:53:10.613749 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9734 19:53:10.620139 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9735 19:53:10.623352 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9736 19:53:10.630010 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9737 19:53:10.633706 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9738 19:53:10.636870 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9739 19:53:10.643339 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9740 19:53:10.647079 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9741 19:53:10.653446 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9742 19:53:10.657230 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9743 19:53:10.660185 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9744 19:53:10.666811 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9745 19:53:10.670053 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9746 19:53:10.676858 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9747 19:53:10.680047 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9748 19:53:10.686840 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9749 19:53:10.690101 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9750 19:53:10.693102 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9751 19:53:10.699906 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9752 19:53:10.703579 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9753 19:53:10.709819 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9754 19:53:10.713321 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9755 19:53:10.716409 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9756 19:53:10.723622 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9757 19:53:10.726427 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9758 19:53:10.729797 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9759 19:53:10.736691 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9760 19:53:10.739725 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9761 19:53:10.743201 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9762 19:53:10.746192 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9763 19:53:10.752771 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9764 19:53:10.756716 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9765 19:53:10.762660 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9766 19:53:10.766143 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9767 19:53:10.769673 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9768 19:53:10.776287 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9769 19:53:10.779659 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9770 19:53:10.783044 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9771 19:53:10.789538 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9772 19:53:10.792548 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9773 19:53:10.796544 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9774 19:53:10.803141 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9775 19:53:10.806298 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9776 19:53:10.812944 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9777 19:53:10.816546 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9778 19:53:10.819597 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9779 19:53:10.826608 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9780 19:53:10.829345 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9781 19:53:10.832861 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9782 19:53:10.839759 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9783 19:53:10.842933 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9784 19:53:10.846313 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9785 19:53:10.852820 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9786 19:53:10.856287 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9787 19:53:10.859380 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9788 19:53:10.866068 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9789 19:53:10.869053 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9790 19:53:10.875762 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9791 19:53:10.879239 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9792 19:53:10.882377 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9793 19:53:10.889333 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9794 19:53:10.892403 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9795 19:53:10.899119 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9796 19:53:10.902343 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9797 19:53:10.905725 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9798 19:53:10.908855 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9799 19:53:10.915870 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9800 19:53:10.918900 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9801 19:53:10.922205 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9802 19:53:10.925750 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9803 19:53:10.932110 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9804 19:53:10.935177 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9805 19:53:10.938620 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9806 19:53:10.941972 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9807 19:53:10.948696 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9808 19:53:10.951622 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9809 19:53:10.954999 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9810 19:53:10.958574 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9811 19:53:10.965239 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9812 19:53:10.968563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9813 19:53:10.975108 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9814 19:53:10.978398 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9815 19:53:10.985201 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9816 19:53:10.988379 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9817 19:53:10.991933 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9818 19:53:10.998131 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9819 19:53:11.001335 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9820 19:53:11.008257 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9821 19:53:11.011565 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9822 19:53:11.015066 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9823 19:53:11.021596 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9824 19:53:11.024986 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9825 19:53:11.031271 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9826 19:53:11.034768 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9827 19:53:11.038352 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9828 19:53:11.044773 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9829 19:53:11.048280 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9830 19:53:11.054916 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9831 19:53:11.057921 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9832 19:53:11.064873 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9833 19:53:11.067985 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9834 19:53:11.071531 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9835 19:53:11.077839 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9836 19:53:11.081258 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9837 19:53:11.088002 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9838 19:53:11.090971 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9839 19:53:11.094596 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9840 19:53:11.101485 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9841 19:53:11.104341 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9842 19:53:11.111010 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9843 19:53:11.114547 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9844 19:53:11.118205 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9845 19:53:11.124458 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9846 19:53:11.127874 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9847 19:53:11.134474 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9848 19:53:11.137839 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9849 19:53:11.144615 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9850 19:53:11.148070 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9851 19:53:11.150826 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9852 19:53:11.157806 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9853 19:53:11.160752 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9854 19:53:11.167809 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9855 19:53:11.170693 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9856 19:53:11.174495 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9857 19:53:11.180671 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9858 19:53:11.184247 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9859 19:53:11.190629 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9860 19:53:11.194168 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9861 19:53:11.197169 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9862 19:53:11.204189 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9863 19:53:11.207347 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9864 19:53:11.213909 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9865 19:53:11.217658 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9866 19:53:11.220965 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9867 19:53:11.226999 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9868 19:53:11.230282 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9869 19:53:11.237139 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9870 19:53:11.240358 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9871 19:53:11.244212 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9872 19:53:11.250327 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9873 19:53:11.253874 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9874 19:53:11.260527 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9875 19:53:11.263500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9876 19:53:11.267050 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9877 19:53:11.273522 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9878 19:53:11.277168 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9879 19:53:11.283818 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9880 19:53:11.287127 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9881 19:53:11.293554 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9882 19:53:11.297175 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9883 19:53:11.300210 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9884 19:53:11.306721 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9885 19:53:11.310333 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9886 19:53:11.316859 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9887 19:53:11.320270 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9888 19:53:11.326545 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9889 19:53:11.329830 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9890 19:53:11.333304 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9891 19:53:11.339922 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9892 19:53:11.342947 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9893 19:53:11.349629 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9894 19:53:11.353069 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9895 19:53:11.359969 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9896 19:53:11.362932 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9897 19:53:11.369702 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9898 19:53:11.373272 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9899 19:53:11.376193 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9900 19:53:11.383300 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9901 19:53:11.386225 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9902 19:53:11.392736 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9903 19:53:11.396095 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9904 19:53:11.402824 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9905 19:53:11.406486 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9906 19:53:11.409437 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9907 19:53:11.415756 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9908 19:53:11.419286 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9909 19:53:11.425928 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9910 19:53:11.429408 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9911 19:53:11.435952 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9912 19:53:11.438819 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9913 19:53:11.445889 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9914 19:53:11.449157 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9915 19:53:11.452250 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9916 19:53:11.459025 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9917 19:53:11.462030 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9918 19:53:11.469078 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9919 19:53:11.472536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9920 19:53:11.478788 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9921 19:53:11.482449 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9922 19:53:11.485556 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9923 19:53:11.491922 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9924 19:53:11.495476 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9925 19:53:11.502194 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9926 19:53:11.505551 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9927 19:53:11.511852 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9928 19:53:11.515560 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9929 19:53:11.521971 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9930 19:53:11.525448 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9931 19:53:11.528779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9932 19:53:11.535262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9933 19:53:11.538833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9934 19:53:11.545382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9935 19:53:11.548887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9936 19:53:11.555535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9937 19:53:11.558980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9938 19:53:11.562441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9939 19:53:11.568754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9940 19:53:11.571884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9941 19:53:11.578531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9942 19:53:11.581671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9943 19:53:11.588268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9944 19:53:11.591968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9945 19:53:11.598416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9946 19:53:11.601913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9947 19:53:11.608287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9948 19:53:11.611843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9949 19:53:11.618589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9950 19:53:11.621608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9951 19:53:11.628506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9952 19:53:11.632066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9953 19:53:11.638014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9954 19:53:11.641479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9955 19:53:11.648255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9956 19:53:11.651663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9957 19:53:11.658227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9958 19:53:11.661800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9959 19:53:11.668264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9960 19:53:11.671212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9961 19:53:11.678002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9962 19:53:11.681131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9963 19:53:11.687853 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9964 19:53:11.687934 INFO: [APUAPC] vio 0
9965 19:53:11.694720 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9966 19:53:11.698108 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9967 19:53:11.701576 INFO: [APUAPC] D0_APC_0: 0x400510
9968 19:53:11.704624 INFO: [APUAPC] D0_APC_1: 0x0
9969 19:53:11.707707 INFO: [APUAPC] D0_APC_2: 0x1540
9970 19:53:11.711126 INFO: [APUAPC] D0_APC_3: 0x0
9971 19:53:11.714520 INFO: [APUAPC] D1_APC_0: 0xffffffff
9972 19:53:11.717777 INFO: [APUAPC] D1_APC_1: 0xffffffff
9973 19:53:11.721181 INFO: [APUAPC] D1_APC_2: 0x3fffff
9974 19:53:11.724649 INFO: [APUAPC] D1_APC_3: 0x0
9975 19:53:11.727940 INFO: [APUAPC] D2_APC_0: 0xffffffff
9976 19:53:11.730942 INFO: [APUAPC] D2_APC_1: 0xffffffff
9977 19:53:11.734333 INFO: [APUAPC] D2_APC_2: 0x3fffff
9978 19:53:11.737849 INFO: [APUAPC] D2_APC_3: 0x0
9979 19:53:11.741507 INFO: [APUAPC] D3_APC_0: 0xffffffff
9980 19:53:11.744527 INFO: [APUAPC] D3_APC_1: 0xffffffff
9981 19:53:11.747499 INFO: [APUAPC] D3_APC_2: 0x3fffff
9982 19:53:11.751239 INFO: [APUAPC] D3_APC_3: 0x0
9983 19:53:11.754275 INFO: [APUAPC] D4_APC_0: 0xffffffff
9984 19:53:11.757556 INFO: [APUAPC] D4_APC_1: 0xffffffff
9985 19:53:11.761140 INFO: [APUAPC] D4_APC_2: 0x3fffff
9986 19:53:11.761220 INFO: [APUAPC] D4_APC_3: 0x0
9987 19:53:11.764107 INFO: [APUAPC] D5_APC_0: 0xffffffff
9988 19:53:11.770888 INFO: [APUAPC] D5_APC_1: 0xffffffff
9989 19:53:11.774255 INFO: [APUAPC] D5_APC_2: 0x3fffff
9990 19:53:11.774336 INFO: [APUAPC] D5_APC_3: 0x0
9991 19:53:11.777828 INFO: [APUAPC] D6_APC_0: 0xffffffff
9992 19:53:11.781062 INFO: [APUAPC] D6_APC_1: 0xffffffff
9993 19:53:11.784016 INFO: [APUAPC] D6_APC_2: 0x3fffff
9994 19:53:11.787841 INFO: [APUAPC] D6_APC_3: 0x0
9995 19:53:11.790820 INFO: [APUAPC] D7_APC_0: 0xffffffff
9996 19:53:11.793905 INFO: [APUAPC] D7_APC_1: 0xffffffff
9997 19:53:11.797270 INFO: [APUAPC] D7_APC_2: 0x3fffff
9998 19:53:11.800623 INFO: [APUAPC] D7_APC_3: 0x0
9999 19:53:11.804078 INFO: [APUAPC] D8_APC_0: 0xffffffff
10000 19:53:11.807889 INFO: [APUAPC] D8_APC_1: 0xffffffff
10001 19:53:11.810731 INFO: [APUAPC] D8_APC_2: 0x3fffff
10002 19:53:11.813817 INFO: [APUAPC] D8_APC_3: 0x0
10003 19:53:11.817449 INFO: [APUAPC] D9_APC_0: 0xffffffff
10004 19:53:11.820609 INFO: [APUAPC] D9_APC_1: 0xffffffff
10005 19:53:11.824031 INFO: [APUAPC] D9_APC_2: 0x3fffff
10006 19:53:11.827646 INFO: [APUAPC] D9_APC_3: 0x0
10007 19:53:11.830448 INFO: [APUAPC] D10_APC_0: 0xffffffff
10008 19:53:11.834017 INFO: [APUAPC] D10_APC_1: 0xffffffff
10009 19:53:11.837071 INFO: [APUAPC] D10_APC_2: 0x3fffff
10010 19:53:11.840469 INFO: [APUAPC] D10_APC_3: 0x0
10011 19:53:11.843930 INFO: [APUAPC] D11_APC_0: 0xffffffff
10012 19:53:11.846897 INFO: [APUAPC] D11_APC_1: 0xffffffff
10013 19:53:11.850547 INFO: [APUAPC] D11_APC_2: 0x3fffff
10014 19:53:11.853968 INFO: [APUAPC] D11_APC_3: 0x0
10015 19:53:11.857087 INFO: [APUAPC] D12_APC_0: 0xffffffff
10016 19:53:11.860671 INFO: [APUAPC] D12_APC_1: 0xffffffff
10017 19:53:11.863457 INFO: [APUAPC] D12_APC_2: 0x3fffff
10018 19:53:11.867473 INFO: [APUAPC] D12_APC_3: 0x0
10019 19:53:11.870387 INFO: [APUAPC] D13_APC_0: 0xffffffff
10020 19:53:11.873983 INFO: [APUAPC] D13_APC_1: 0xffffffff
10021 19:53:11.876685 INFO: [APUAPC] D13_APC_2: 0x3fffff
10022 19:53:11.880193 INFO: [APUAPC] D13_APC_3: 0x0
10023 19:53:11.883508 INFO: [APUAPC] D14_APC_0: 0xffffffff
10024 19:53:11.887076 INFO: [APUAPC] D14_APC_1: 0xffffffff
10025 19:53:11.889982 INFO: [APUAPC] D14_APC_2: 0x3fffff
10026 19:53:11.893354 INFO: [APUAPC] D14_APC_3: 0x0
10027 19:53:11.896728 INFO: [APUAPC] D15_APC_0: 0xffffffff
10028 19:53:11.900458 INFO: [APUAPC] D15_APC_1: 0xffffffff
10029 19:53:11.903468 INFO: [APUAPC] D15_APC_2: 0x3fffff
10030 19:53:11.906645 INFO: [APUAPC] D15_APC_3: 0x0
10031 19:53:11.909793 INFO: [APUAPC] APC_CON: 0x4
10032 19:53:11.913355 INFO: [NOCDAPC] D0_APC_0: 0x0
10033 19:53:11.916956 INFO: [NOCDAPC] D0_APC_1: 0x0
10034 19:53:11.919751 INFO: [NOCDAPC] D1_APC_0: 0x0
10035 19:53:11.923695 INFO: [NOCDAPC] D1_APC_1: 0xfff
10036 19:53:11.926274 INFO: [NOCDAPC] D2_APC_0: 0x0
10037 19:53:11.929761 INFO: [NOCDAPC] D2_APC_1: 0xfff
10038 19:53:11.929843 INFO: [NOCDAPC] D3_APC_0: 0x0
10039 19:53:11.933182 INFO: [NOCDAPC] D3_APC_1: 0xfff
10040 19:53:11.936291 INFO: [NOCDAPC] D4_APC_0: 0x0
10041 19:53:11.940045 INFO: [NOCDAPC] D4_APC_1: 0xfff
10042 19:53:11.942817 INFO: [NOCDAPC] D5_APC_0: 0x0
10043 19:53:11.946226 INFO: [NOCDAPC] D5_APC_1: 0xfff
10044 19:53:11.949307 INFO: [NOCDAPC] D6_APC_0: 0x0
10045 19:53:11.952640 INFO: [NOCDAPC] D6_APC_1: 0xfff
10046 19:53:11.956404 INFO: [NOCDAPC] D7_APC_0: 0x0
10047 19:53:11.959171 INFO: [NOCDAPC] D7_APC_1: 0xfff
10048 19:53:11.962807 INFO: [NOCDAPC] D8_APC_0: 0x0
10049 19:53:11.966096 INFO: [NOCDAPC] D8_APC_1: 0xfff
10050 19:53:11.966179 INFO: [NOCDAPC] D9_APC_0: 0x0
10051 19:53:11.969323 INFO: [NOCDAPC] D9_APC_1: 0xfff
10052 19:53:11.972758 INFO: [NOCDAPC] D10_APC_0: 0x0
10053 19:53:11.975840 INFO: [NOCDAPC] D10_APC_1: 0xfff
10054 19:53:11.979679 INFO: [NOCDAPC] D11_APC_0: 0x0
10055 19:53:11.983189 INFO: [NOCDAPC] D11_APC_1: 0xfff
10056 19:53:11.986667 INFO: [NOCDAPC] D12_APC_0: 0x0
10057 19:53:11.989693 INFO: [NOCDAPC] D12_APC_1: 0xfff
10058 19:53:11.992846 INFO: [NOCDAPC] D13_APC_0: 0x0
10059 19:53:11.995921 INFO: [NOCDAPC] D13_APC_1: 0xfff
10060 19:53:11.999259 INFO: [NOCDAPC] D14_APC_0: 0x0
10061 19:53:12.002901 INFO: [NOCDAPC] D14_APC_1: 0xfff
10062 19:53:12.006051 INFO: [NOCDAPC] D15_APC_0: 0x0
10063 19:53:12.009581 INFO: [NOCDAPC] D15_APC_1: 0xfff
10064 19:53:12.009663 INFO: [NOCDAPC] APC_CON: 0x4
10065 19:53:12.012808 INFO: [APUAPC] set_apusys_apc done
10066 19:53:12.016059 INFO: [DEVAPC] devapc_init done
10067 19:53:12.022614 INFO: GICv3 without legacy support detected.
10068 19:53:12.025962 INFO: ARM GICv3 driver initialized in EL3
10069 19:53:12.029309 INFO: Maximum SPI INTID supported: 639
10070 19:53:12.032640 INFO: BL31: Initializing runtime services
10071 19:53:12.039077 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10072 19:53:12.042720 INFO: SPM: enable CPC mode
10073 19:53:12.045612 INFO: mcdi ready for mcusys-off-idle and system suspend
10074 19:53:12.052454 INFO: BL31: Preparing for EL3 exit to normal world
10075 19:53:12.055816 INFO: Entry point address = 0x80000000
10076 19:53:12.055898 INFO: SPSR = 0x8
10077 19:53:12.062640
10078 19:53:12.062723
10079 19:53:12.062787
10080 19:53:12.066270 Starting depthcharge on Spherion...
10081 19:53:12.066354
10082 19:53:12.066418 Wipe memory regions:
10083 19:53:12.066477
10084 19:53:12.067245 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10085 19:53:12.067345 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10086 19:53:12.067718 Setting prompt string to ['asurada:']
10087 19:53:12.067800 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10088 19:53:12.069291 [0x00000040000000, 0x00000054600000)
10089 19:53:12.192074
10090 19:53:12.192218 [0x00000054660000, 0x00000080000000)
10091 19:53:12.451899
10092 19:53:12.452165 [0x000000821a7280, 0x000000ffe64000)
10093 19:53:13.196557
10094 19:53:13.196708 [0x00000100000000, 0x00000240000000)
10095 19:53:15.085088
10096 19:53:15.087726 Initializing XHCI USB controller at 0x11200000.
10097 19:53:16.125884
10098 19:53:16.129012 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10099 19:53:16.129097
10100 19:53:16.129162
10101 19:53:16.129228
10102 19:53:16.129512 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10104 19:53:16.229829 asurada: tftpboot 192.168.201.1 11899560/tftp-deploy-11qjant5/kernel/image.itb 11899560/tftp-deploy-11qjant5/kernel/cmdline
10105 19:53:16.229968 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10106 19:53:16.230051 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10107 19:53:16.234974 tftpboot 192.168.201.1 11899560/tftp-deploy-11qjant5/kernel/image.itp-deploy-11qjant5/kernel/cmdline
10108 19:53:16.235056
10109 19:53:16.235119 Waiting for link
10110 19:53:16.394913
10111 19:53:16.395042 R8152: Initializing
10112 19:53:16.395108
10113 19:53:16.398165 Version 6 (ocp_data = 5c30)
10114 19:53:16.398246
10115 19:53:16.401503 R8152: Done initializing
10116 19:53:16.401583
10117 19:53:16.401647 Adding net device
10118 19:53:18.305194
10119 19:53:18.305680 done.
10120 19:53:18.306013
10121 19:53:18.306318 MAC: 00:24:32:30:78:ff
10122 19:53:18.306727
10123 19:53:18.308709 Sending DHCP discover... done.
10124 19:53:18.309240
10125 19:53:28.449417 Waiting for reply... R8152: Bulk read error 0xffffffbf
10126 19:53:28.449971
10127 19:53:28.452565 Receive failed.
10128 19:53:28.452984
10129 19:53:28.453312 done.
10130 19:53:28.453668
10131 19:53:28.455841 Sending DHCP request... done.
10132 19:53:28.456296
10133 19:53:28.462832 Waiting for reply... done.
10134 19:53:28.463348
10135 19:53:28.463757 My ip is 192.168.201.21
10136 19:53:28.464072
10137 19:53:28.466177 The DHCP server ip is 192.168.201.1
10138 19:53:28.466703
10139 19:53:28.473109 TFTP server IP predefined by user: 192.168.201.1
10140 19:53:28.473643
10141 19:53:28.479008 Bootfile predefined by user: 11899560/tftp-deploy-11qjant5/kernel/image.itb
10142 19:53:28.479578
10143 19:53:28.482319 Sending tftp read request... done.
10144 19:53:28.482730
10145 19:53:28.489724 Waiting for the transfer...
10146 19:53:28.490246
10147 19:53:29.191942 00000000 ################################################################
10148 19:53:29.192487
10149 19:53:29.826600 00080000 ################################################################
10150 19:53:29.827139
10151 19:53:30.389292 00100000 ################################################################
10152 19:53:30.389427
10153 19:53:31.052449 00180000 ################################################################
10154 19:53:31.052969
10155 19:53:31.760454 00200000 ################################################################
10156 19:53:31.760961
10157 19:53:32.410900 00280000 ################################################################
10158 19:53:32.411036
10159 19:53:33.034903 00300000 ################################################################
10160 19:53:33.035037
10161 19:53:33.677810 00380000 ################################################################
10162 19:53:33.678318
10163 19:53:34.382870 00400000 ################################################################
10164 19:53:34.383444
10165 19:53:35.093399 00480000 ################################################################
10166 19:53:35.093932
10167 19:53:35.789531 00500000 ################################################################
10168 19:53:35.790200
10169 19:53:36.478392 00580000 ################################################################
10170 19:53:36.478903
10171 19:53:37.184195 00600000 ################################################################
10172 19:53:37.184721
10173 19:53:37.894722 00680000 ################################################################
10174 19:53:37.895281
10175 19:53:38.582690 00700000 ################################################################
10176 19:53:38.583202
10177 19:53:39.287184 00780000 ################################################################
10178 19:53:39.287810
10179 19:53:39.989655 00800000 ################################################################
10180 19:53:39.989816
10181 19:53:40.698576 00880000 ################################################################
10182 19:53:40.699082
10183 19:53:41.340288 00900000 ################################################################
10184 19:53:41.340430
10185 19:53:42.034972 00980000 ################################################################
10186 19:53:42.035610
10187 19:53:42.685280 00a00000 ################################################################
10188 19:53:42.685411
10189 19:53:43.266285 00a80000 ################################################################
10190 19:53:43.266419
10191 19:53:43.826634 00b00000 ################################################################
10192 19:53:43.826800
10193 19:53:44.406494 00b80000 ################################################################
10194 19:53:44.407112
10195 19:53:45.006786 00c00000 ################################################################
10196 19:53:45.006929
10197 19:53:45.649426 00c80000 ################################################################
10198 19:53:45.649989
10199 19:53:46.334272 00d00000 ################################################################
10200 19:53:46.334429
10201 19:53:46.998983 00d80000 ################################################################
10202 19:53:46.999110
10203 19:53:47.595549 00e00000 ################################################################
10204 19:53:47.595683
10205 19:53:48.205442 00e80000 ################################################################
10206 19:53:48.205588
10207 19:53:48.841727 00f00000 ################################################################
10208 19:53:48.841873
10209 19:53:49.469497 00f80000 ################################################################
10210 19:53:49.469645
10211 19:53:50.118994 01000000 ################################################################
10212 19:53:50.119582
10213 19:53:50.804106 01080000 ################################################################
10214 19:53:50.804652
10215 19:53:51.509451 01100000 ################################################################
10216 19:53:51.510100
10217 19:53:52.223374 01180000 ################################################################
10218 19:53:52.223984
10219 19:53:52.928106 01200000 ################################################################
10220 19:53:52.928618
10221 19:53:53.631812 01280000 ################################################################
10222 19:53:53.632322
10223 19:53:54.339166 01300000 ################################################################
10224 19:53:54.339721
10225 19:53:55.033250 01380000 ################################################################
10226 19:53:55.033759
10227 19:53:55.739160 01400000 ################################################################
10228 19:53:55.739746
10229 19:53:56.453806 01480000 ################################################################
10230 19:53:56.454317
10231 19:53:57.157159 01500000 ################################################################
10232 19:53:57.157710
10233 19:53:57.866876 01580000 ################################################################
10234 19:53:57.867469
10235 19:53:58.578841 01600000 ################################################################
10236 19:53:58.579356
10237 19:53:59.272828 01680000 ################################################################
10238 19:53:59.273340
10239 19:53:59.975022 01700000 ################################################################
10240 19:53:59.975576
10241 19:54:00.687460 01780000 ################################################################
10242 19:54:00.687978
10243 19:54:01.397228 01800000 ################################################################
10244 19:54:01.397770
10245 19:54:02.101142 01880000 ################################################################
10246 19:54:02.101659
10247 19:54:02.797484 01900000 ################################################################
10248 19:54:02.798000
10249 19:54:03.491049 01980000 ################################################################
10250 19:54:03.491599
10251 19:54:04.192091 01a00000 ################################################################
10252 19:54:04.192746
10253 19:54:04.900270 01a80000 ################################################################
10254 19:54:04.900778
10255 19:54:05.612331 01b00000 ################################################################
10256 19:54:05.612836
10257 19:54:05.688475 01b80000 ####### done.
10258 19:54:05.688965
10259 19:54:05.692093 The bootfile was 28891070 bytes long.
10260 19:54:05.692583
10261 19:54:05.695603 Sending tftp read request... done.
10262 19:54:05.696068
10263 19:54:05.699263 Waiting for the transfer...
10264 19:54:05.699780
10265 19:54:05.700175 00000000 # done.
10266 19:54:05.700722
10267 19:54:05.705960 Command line loaded dynamically from TFTP file: 11899560/tftp-deploy-11qjant5/kernel/cmdline
10268 19:54:05.706639
10269 19:54:05.729425 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11899560/extract-nfsrootfs-d9ma_j26,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10270 19:54:05.729995
10271 19:54:05.730364 Loading FIT.
10272 19:54:05.732231
10273 19:54:05.732634 Image ramdisk-1 has 17794236 bytes.
10274 19:54:05.732983
10275 19:54:05.735492 Image fdt-1 has 47278 bytes.
10276 19:54:05.735958
10277 19:54:05.739267 Image kernel-1 has 11047522 bytes.
10278 19:54:05.739935
10279 19:54:05.748896 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10280 19:54:05.749363
10281 19:54:05.765929 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10282 19:54:05.766526
10283 19:54:05.772531 Choosing best match conf-1 for compat google,spherion-rev2.
10284 19:54:05.775327
10285 19:54:05.780187 Connected to device vid:did:rid of 1ae0:0028:00
10286 19:54:05.788594
10287 19:54:05.792055 tpm_get_response: command 0x17b, return code 0x0
10288 19:54:05.792532
10289 19:54:05.794421 ec_init: CrosEC protocol v3 supported (256, 248)
10290 19:54:05.799989
10291 19:54:05.802551 tpm_cleanup: add release locality here.
10292 19:54:05.803018
10293 19:54:05.803381 Shutting down all USB controllers.
10294 19:54:05.806244
10295 19:54:05.806707 Removing current net device
10296 19:54:05.807077
10297 19:54:05.812707 Exiting depthcharge with code 4 at timestamp: 83036130
10298 19:54:05.813176
10299 19:54:05.815847 LZMA decompressing kernel-1 to 0x821a6718
10300 19:54:05.816316
10301 19:54:05.819222 LZMA decompressing kernel-1 to 0x40000000
10302 19:54:07.207494
10303 19:54:07.208064 jumping to kernel
10304 19:54:07.210357 end: 2.2.4 bootloader-commands (duration 00:00:55) [common]
10305 19:54:07.210897 start: 2.2.5 auto-login-action (timeout 00:03:30) [common]
10306 19:54:07.211330 Setting prompt string to ['Linux version [0-9]']
10307 19:54:07.211836 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10308 19:54:07.212243 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10309 19:54:07.289757
10310 19:54:07.293389 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10311 19:54:07.296473 start: 2.2.5.1 login-action (timeout 00:03:30) [common]
10312 19:54:07.296989 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10313 19:54:07.297393 Setting prompt string to []
10314 19:54:07.297829 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10315 19:54:07.298237 Using line separator: #'\n'#
10316 19:54:07.298582 No login prompt set.
10317 19:54:07.298929 Parsing kernel messages
10318 19:54:07.299243 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10319 19:54:07.299870 [login-action] Waiting for messages, (timeout 00:03:30)
10320 19:54:07.316228 [ 0.000000] Linux version 6.1.59-cip8-rt4 (KernelCI@build-j84202-arm64-gcc-10-defconfig-arm64-chromebook-st8dj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023
10321 19:54:07.319663 [ 0.000000] random: crng init done
10322 19:54:07.326528 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10323 19:54:07.329618 [ 0.000000] efi: UEFI not found.
10324 19:54:07.336253 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10325 19:54:07.342546 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10326 19:54:07.352967 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10327 19:54:07.362923 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10328 19:54:07.368789 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10329 19:54:07.375817 [ 0.000000] printk: bootconsole [mtk8250] enabled
10330 19:54:07.383069 [ 0.000000] NUMA: No NUMA configuration found
10331 19:54:07.389395 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10332 19:54:07.392730 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10333 19:54:07.395836 [ 0.000000] Zone ranges:
10334 19:54:07.402264 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10335 19:54:07.405576 [ 0.000000] DMA32 empty
10336 19:54:07.411837 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10337 19:54:07.415435 [ 0.000000] Movable zone start for each node
10338 19:54:07.419125 [ 0.000000] Early memory node ranges
10339 19:54:07.425057 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10340 19:54:07.431673 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10341 19:54:07.438464 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10342 19:54:07.445483 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10343 19:54:07.451661 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10344 19:54:07.457998 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10345 19:54:07.514015 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10346 19:54:07.520962 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10347 19:54:07.527634 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10348 19:54:07.530968 [ 0.000000] psci: probing for conduit method from DT.
10349 19:54:07.537169 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10350 19:54:07.540509 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10351 19:54:07.547779 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10352 19:54:07.550355 [ 0.000000] psci: SMC Calling Convention v1.2
10353 19:54:07.557513 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10354 19:54:07.561064 [ 0.000000] Detected VIPT I-cache on CPU0
10355 19:54:07.566971 [ 0.000000] CPU features: detected: GIC system register CPU interface
10356 19:54:07.573278 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10357 19:54:07.580021 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10358 19:54:07.586593 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10359 19:54:07.593329 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10360 19:54:07.603414 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10361 19:54:07.606641 [ 0.000000] alternatives: applying boot alternatives
10362 19:54:07.613803 [ 0.000000] Fallback order for Node 0: 0
10363 19:54:07.620045 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10364 19:54:07.623194 [ 0.000000] Policy zone: Normal
10365 19:54:07.646763 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11899560/extract-nfsrootfs-d9ma_j26,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10366 19:54:07.656273 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10367 19:54:07.666164 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10368 19:54:07.676177 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10369 19:54:07.682759 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10370 19:54:07.686183 <6>[ 0.000000] software IO TLB: area num 8.
10371 19:54:07.742383 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10372 19:54:07.892340 <6>[ 0.000000] Memory: 7952048K/8385536K available (17984K kernel code, 4116K rwdata, 17476K rodata, 8448K init, 615K bss, 400720K reserved, 32768K cma-reserved)
10373 19:54:07.898641 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10374 19:54:07.905500 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10375 19:54:07.908315 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10376 19:54:07.915750 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10377 19:54:07.921975 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10378 19:54:07.925337 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10379 19:54:07.934710 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10380 19:54:07.941405 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10381 19:54:07.948415 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10382 19:54:07.954743 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10383 19:54:07.958131 <6>[ 0.000000] GICv3: 608 SPIs implemented
10384 19:54:07.961285 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10385 19:54:07.967892 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10386 19:54:07.971489 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10387 19:54:07.978523 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10388 19:54:07.991992 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10389 19:54:08.001257 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10390 19:54:08.011348 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10391 19:54:08.018319 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10392 19:54:08.031299 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10393 19:54:08.038726 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10394 19:54:08.044748 <6>[ 0.009184] Console: colour dummy device 80x25
10395 19:54:08.054711 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10396 19:54:08.061230 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10397 19:54:08.065412 <6>[ 0.029243] LSM: Security Framework initializing
10398 19:54:08.071459 <6>[ 0.034212] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10399 19:54:08.081221 <6>[ 0.042027] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10400 19:54:08.091576 <6>[ 0.051443] cblist_init_generic: Setting adjustable number of callback queues.
10401 19:54:08.094539 <6>[ 0.058887] cblist_init_generic: Setting shift to 3 and lim to 1.
10402 19:54:08.104732 <6>[ 0.065225] cblist_init_generic: Setting adjustable number of callback queues.
10403 19:54:08.111097 <6>[ 0.072652] cblist_init_generic: Setting shift to 3 and lim to 1.
10404 19:54:08.114141 <6>[ 0.079134] rcu: Hierarchical SRCU implementation.
10405 19:54:08.120951 <6>[ 0.079135] rcu: Max phase no-delay instances is 1000.
10406 19:54:08.127802 <6>[ 0.079160] printk: bootconsole [mtk8250] printing thread started
10407 19:54:08.133841 <6>[ 0.097455] EFI services will not be available.
10408 19:54:08.137085 <6>[ 0.097654] smp: Bringing up secondary CPUs ...
10409 19:54:08.140749 <6>[ 0.097966] Detected VIPT I-cache on CPU1
10410 19:54:08.150937 <6>[ 0.098036] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10411 19:54:08.157010 <6>[ 0.098068] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10412 19:54:08.166521 <6>[ 0.125964] Detected VIPT I-cache on CPU2
10413 19:54:08.176197 <6>[ 0.126015] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10414 19:54:08.183341 <6>[ 0.126033] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10415 19:54:08.186325 <6>[ 0.126292] Detected VIPT I-cache on CPU3
10416 19:54:08.193345 <6>[ 0.126338] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10417 19:54:08.200014 <6>[ 0.126351] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10418 19:54:08.206224 <6>[ 0.126664] CPU features: detected: Spectre-v4
10419 19:54:08.209607 <6>[ 0.126670] CPU features: detected: Spectre-BHB
10420 19:54:08.212967 <6>[ 0.126675] Detected PIPT I-cache on CPU4
10421 19:54:08.219523 <6>[ 0.126733] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10422 19:54:08.226079 <6>[ 0.126750] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10423 19:54:08.232701 <6>[ 0.127048] Detected PIPT I-cache on CPU5
10424 19:54:08.239223 <6>[ 0.127108] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10425 19:54:08.246834 <6>[ 0.127124] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10426 19:54:08.249155 <6>[ 0.127398] Detected PIPT I-cache on CPU6
10427 19:54:08.259621 <6>[ 0.127463] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10428 19:54:08.265870 <6>[ 0.127480] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10429 19:54:08.268876 <6>[ 0.127773] Detected PIPT I-cache on CPU7
10430 19:54:08.275475 <6>[ 0.127838] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10431 19:54:08.282806 <6>[ 0.127854] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10432 19:54:08.285442 <6>[ 0.127900] smp: Brought up 1 node, 8 CPUs
10433 19:54:08.292191 <6>[ 0.127905] SMP: Total of 8 processors activated.
10434 19:54:08.298867 <6>[ 0.127908] CPU features: detected: 32-bit EL0 Support
10435 19:54:08.305550 <6>[ 0.127909] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10436 19:54:08.311816 <6>[ 0.127912] CPU features: detected: Common not Private translations
10437 19:54:08.318616 <6>[ 0.127914] CPU features: detected: CRC32 instructions
10438 19:54:08.325330 <6>[ 0.127916] CPU features: detected: RCpc load-acquire (LDAPR)
10439 19:54:08.328735 <6>[ 0.127918] CPU features: detected: LSE atomic instructions
10440 19:54:08.335171 <6>[ 0.127920] CPU features: detected: Privileged Access Never
10441 19:54:08.341490 <6>[ 0.127921] CPU features: detected: RAS Extension Support
10442 19:54:08.347681 <6>[ 0.127924] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10443 19:54:08.351075 <6>[ 0.127990] CPU: All CPU(s) started at EL2
10444 19:54:08.358234 <6>[ 0.127991] alternatives: applying system-wide alternatives
10445 19:54:08.361435 <6>[ 0.141034] devtmpfs: initialized
10446 19:54:08.393843 �-�B�͡�������*��ɥ������Bzɑ�Ɂ�b��ʲ�ѕͥjR�<6>[ 0.355910] <printk: console [ttyS0] printing thread started
10447 19:54:08.397173 6>[<6>[ 0.355942] printk: console [ttyS0] enabled
10448 19:54:08.400403 0.221613] pnp: PnP ACPI: disabled
10449 19:54:08.408813 <6>[ 0.355945] printk: bootconsole [mtk8250] disabled
10450 19:54:08.415714 <6>[ 0.369927] printk: bootconsole [mtk8250] printing thread stopped
10451 19:54:08.418889 <6>[ 0.371305] SuperH (H)SCI(F) driver initialized
10452 19:54:08.425577 <6>[ 0.371784] msm_serial: driver initialized
10453 19:54:08.431856 <6>[ 0.376480] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10454 19:54:08.441714 <6>[ 0.376508] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10455 19:54:08.454063 <6>[ 0.376537] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10456 19:54:08.458608 <6>[ 0.376566] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10457 19:54:08.468336 <6>[ 0.376588] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10458 19:54:08.481804 <6>[ 0.376617] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10459 19:54:08.493225 <6>[ 0.376646] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10460 19:54:08.498167 <6>[ 0.376770] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10461 19:54:08.503121 <6>[ 0.376800] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10462 19:54:08.507352 <6>[ 0.388599] loop: module loaded
10463 19:54:08.512049 <6>[ 0.391181] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10464 19:54:08.518921 <4>[ 0.408158] mtk-pmic-keys: Failed to locate of_node [id: -1]
10465 19:54:08.521825 <6>[ 0.409097] megasas: 07.719.03.00-rc1
10466 19:54:08.529118 <6>[ 0.420787] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10467 19:54:08.532453 <6>[ 0.420884] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10468 19:54:08.539044 <6>[ 0.432781] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10469 19:54:08.548768 <6>[ 0.486227] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10470 19:54:09.001062 <6>[ 0.962131] Freeing initrd memory: 17376K
10471 19:54:09.008169 <6>[ 0.967930] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10472 19:54:09.010952 <6>[ 0.972548] tun: Universal TUN/TAP device driver, 1.6
10473 19:54:09.014355 <6>[ 0.973291] thunder_xcv, ver 1.0
10474 19:54:09.017804 <6>[ 0.973308] thunder_bgx, ver 1.0
10475 19:54:09.021642 <6>[ 0.973322] nicpf, ver 1.0
10476 19:54:09.027813 <6>[ 0.974372] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10477 19:54:09.034805 <6>[ 0.974375] hns3: Copyright (c) 2017 Huawei Corporation.
10478 19:54:09.038290 <6>[ 0.974400] hclge is initializing
10479 19:54:09.043927 <6>[ 0.974412] e1000: Intel(R) PRO/1000 Network Driver
10480 19:54:09.047668 <6>[ 0.974414] e1000: Copyright (c) 1999-2006 Intel Corporation.
10481 19:54:09.055007 <6>[ 0.974430] e1000e: Intel(R) PRO/1000 Network Driver
10482 19:54:09.062357 <6>[ 0.974432] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10483 19:54:09.066165 <6>[ 0.974449] igb: Intel(R) Gigabit Ethernet Network Driver
10484 19:54:09.072704 <6>[ 0.974451] igb: Copyright (c) 2007-2014 Intel Corporation.
10485 19:54:09.080046 <6>[ 0.974464] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10486 19:54:09.086960 <6>[ 0.974466] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10487 19:54:09.089754 <6>[ 0.974757] sky2: driver version 1.30
10488 19:54:09.093603 <6>[ 0.975832] VFIO - User Level meta-driver version: 0.3
10489 19:54:09.100415 <6>[ 0.978676] usbcore: registered new interface driver usb-storage
10490 19:54:09.106606 <6>[ 0.978852] usbcore: registered new device driver onboard-usb-hub
10491 19:54:09.112904 <6>[ 0.981600] mt6397-rtc mt6359-rtc: registered as rtc0
10492 19:54:09.122895 <6>[ 0.981756] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-28T19:54:10 UTC (1698522850)
10493 19:54:09.126286 <6>[ 0.982368] i2c_dev: i2c /dev entries driver
10494 19:54:09.133116 <6>[ 0.989394] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10495 19:54:09.138957 <6>[ 1.004383] cpu cpu0: EM: created perf domain
10496 19:54:09.142498 <6>[ 1.004689] cpu cpu4: EM: created perf domain
10497 19:54:09.148902 <6>[ 1.007837] sdhci: Secure Digital Host Controller Interface driver
10498 19:54:09.152209 <6>[ 1.007838] sdhci: Copyright(c) Pierre Ossman
10499 19:54:09.159087 <6>[ 1.008198] Synopsys Designware Multimedia Card Interface Driver
10500 19:54:09.165407 <6>[ 1.008594] sdhci-pltfm: SDHCI platform and OF driver helper
10501 19:54:09.172023 <6>[ 1.012839] ledtrig-cpu: registered to indicate activity on CPUs
10502 19:54:09.175827 <6>[ 1.013460] mmc0: CQHCI version 5.10
10503 19:54:09.182253 <6>[ 1.013532] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10504 19:54:09.189127 <6>[ 1.013804] usbcore: registered new interface driver usbhid
10505 19:54:09.192312 <6>[ 1.013806] usbhid: USB HID core driver
10506 19:54:09.199130 <6>[ 1.013924] spi_master spi0: will run message pump with realtime priority
10507 19:54:09.212368 <6>[ 1.043041] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10508 19:54:09.225104 <6>[ 1.046066] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10509 19:54:09.232258 <6>[ 1.047296] cros-ec-spi spi0.0: Chrome EC device registered
10510 19:54:09.242161 <6>[ 1.060716] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10511 19:54:09.245274 <6>[ 1.061646] NET: Registered PF_PACKET protocol family
10512 19:54:09.251470 <6>[ 1.061719] 9pnet: Installing 9P2000 support
10513 19:54:09.255373 <5>[ 1.061755] Key type dns_resolver registered
10514 19:54:09.258257 <6>[ 1.062295] registered taskstats version 1
10515 19:54:09.265002 <5>[ 1.062311] Loading compiled-in X.509 certificates
10516 19:54:09.274744 <4>[ 1.080927] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10517 19:54:09.284543 <4>[ 1.081122] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10518 19:54:09.291945 <3>[ 1.081137] debugfs: File 'uA_load' in directory '/' already present!
10519 19:54:09.298356 <3>[ 1.081144] debugfs: File 'min_uV' in directory '/' already present!
10520 19:54:09.305144 <3>[ 1.081147] debugfs: File 'max_uV' in directory '/' already present!
10521 19:54:09.311237 <3>[ 1.081150] debugfs: File 'constraint_flags' in directory '/' already present!
10522 19:54:09.321096 <3>[ 1.083174] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10523 19:54:09.328243 <6>[ 1.090438] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10524 19:54:09.335234 <6>[ 1.091060] xhci-mtk 11200000.usb: xHCI Host Controller
10525 19:54:09.341310 <6>[ 1.091077] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10526 19:54:09.351905 <6>[ 1.091289] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10527 19:54:09.354841 <6>[ 1.091335] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10528 19:54:09.361646 <6>[ 1.091426] xhci-mtk 11200000.usb: xHCI Host Controller
10529 19:54:09.368070 <6>[ 1.091433] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10530 19:54:09.378509 <6>[ 1.091440] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10531 19:54:09.381304 <6>[ 1.092293] hub 1-0:1.0: USB hub found
10532 19:54:09.384327 <6>[ 1.092315] hub 1-0:1.0: 1 port detected
10533 19:54:09.394595 <6>[ 1.092527] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10534 19:54:09.397465 <6>[ 1.092886] hub 2-0:1.0: USB hub found
10535 19:54:09.401340 <6>[ 1.092904] hub 2-0:1.0: 1 port detected
10536 19:54:09.404276 <6>[ 1.096019] mtk-msdc 11f70000.mmc: Got CD GPIO
10537 19:54:09.414625 <6>[ 1.104688] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10538 19:54:09.420863 <6>[ 1.104696] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10539 19:54:09.431270 <4>[ 1.104762] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10540 19:54:09.437647 <6>[ 1.105252] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10541 19:54:09.447194 <6>[ 1.105254] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10542 19:54:09.454478 <6>[ 1.105351] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10543 19:54:09.464116 <6>[ 1.105374] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10544 19:54:09.471008 <6>[ 1.105376] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10545 19:54:09.480772 <6>[ 1.105378] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10546 19:54:09.487159 <6>[ 1.106631] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10547 19:54:09.496655 <6>[ 1.106646] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10548 19:54:09.503523 <6>[ 1.106650] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10549 19:54:09.514009 <6>[ 1.106653] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10550 19:54:09.519766 <6>[ 1.106656] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10551 19:54:09.529994 <6>[ 1.106659] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10552 19:54:09.536949 <6>[ 1.106663] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10553 19:54:09.546735 <6>[ 1.106666] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10554 19:54:09.553108 <6>[ 1.106670] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10555 19:54:09.563602 <6>[ 1.106673] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10556 19:54:09.569841 <6>[ 1.106676] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10557 19:54:09.580062 <6>[ 1.106679] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10558 19:54:09.586262 <6>[ 1.106683] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10559 19:54:09.595814 <6>[ 1.106686] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10560 19:54:09.606085 <6>[ 1.106689] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10561 19:54:09.612939 <6>[ 1.107005] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10562 19:54:09.615897 <6>[ 1.107579] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10563 19:54:09.622212 <6>[ 1.107841] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10564 19:54:09.629138 <6>[ 1.108085] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10565 19:54:09.638779 <6>[ 1.108333] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10566 19:54:09.645132 <6>[ 1.108489] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10567 19:54:09.655208 <6>[ 1.108498] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10568 19:54:09.665716 <6>[ 1.108500] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10569 19:54:09.675631 <6>[ 1.108503] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10570 19:54:09.685403 <6>[ 1.108506] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10571 19:54:09.691901 <6>[ 1.108517] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10572 19:54:09.701961 <6>[ 1.108522] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10573 19:54:09.711836 <6>[ 1.108524] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10574 19:54:09.721651 <6>[ 1.108526] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10575 19:54:09.731676 <6>[ 1.108530] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10576 19:54:09.741636 <6>[ 1.108532] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10577 19:54:09.747908 <6>[ 1.108951] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10578 19:54:09.754447 <6>[ 1.112305] mmc0: Command Queue Engine enabled
10579 19:54:09.761630 <6>[ 1.112317] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10580 19:54:09.764747 <6>[ 1.112832] mmcblk0: mmc0:0001 DA4128 116 GiB
10581 19:54:09.771335 <6>[ 1.116090] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10582 19:54:09.777667 <6>[ 1.116968] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10583 19:54:09.781181 <6>[ 1.117572] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10584 19:54:09.787690 <6>[ 1.118196] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10585 19:54:09.794410 <6>[ 1.134050] Trying to probe devices needed for running init ...
10586 19:54:09.801311 <6>[ 1.473704] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10587 19:54:09.804435 <6>[ 1.500569] hub 2-1:1.0: USB hub found
10588 19:54:09.811130 <6>[ 1.500946] hub 2-1:1.0: 3 ports detected
10589 19:54:09.817927 <6>[ 1.621429] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10590 19:54:09.820687 <6>[ 1.774512] hub 1-1:1.0: USB hub found
10591 19:54:09.824006 <6>[ 1.774913] hub 1-1:1.0: 4 ports detected
10592 19:54:09.892534 <6>[ 1.849885] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10593 19:54:10.127920 <6>[ 2.085759] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10594 19:54:10.248929 <6>[ 2.212757] hub 1-1.4:1.0: USB hub found
10595 19:54:10.252357 <6>[ 2.213073] hub 1-1.4:1.0: 2 ports detected
10596 19:54:10.544073 <6>[ 2.501647] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10597 19:54:10.728093 <6>[ 2.685649] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10598 19:54:21.444298 <6>[ 13.410667] ALSA device list:
10599 19:54:21.451505 <6>[ 13.410688] No soundcards found.
10600 19:54:21.454746 <6>[ 13.415119] Freeing unused kernel memory: 8448K
10601 19:54:21.458502 <6>[ 13.415287] Run /init as init process
10602 19:54:21.461243 Loading, please wait...
10603 19:54:21.486015 Starting version 247.3-7+deb11u2
10604 19:54:21.718616 <6>[ 13.680985] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10605 19:54:21.742363 <6>[ 13.703710] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10606 19:54:21.749514 <6>[ 13.703732] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10607 19:54:21.759173 <6>[ 13.703745] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10608 19:54:21.765735 <6>[ 13.703752] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10609 19:54:21.775650 <3>[ 13.706157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10610 19:54:21.783052 <3>[ 13.706173] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10611 19:54:21.789823 <3>[ 13.706177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10612 19:54:21.799508 <4>[ 13.726713] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10613 19:54:21.806591 <4>[ 13.726713] Fallback method does not support PEC.
10614 19:54:21.814059 <3>[ 13.732001] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10615 19:54:21.820226 <3>[ 13.732022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10616 19:54:21.830640 <3>[ 13.732026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10617 19:54:21.836632 <3>[ 13.732032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10618 19:54:21.846368 <3>[ 13.732036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10619 19:54:21.853438 <3>[ 13.732233] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10620 19:54:21.863325 <3>[ 13.732271] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10621 19:54:21.869651 <3>[ 13.732274] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10622 19:54:21.876236 <3>[ 13.732277] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10623 19:54:21.885919 <3>[ 13.732304] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10624 19:54:21.892803 <3>[ 13.732307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10625 19:54:21.903033 <3>[ 13.732309] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10626 19:54:21.909653 <3>[ 13.732311] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10627 19:54:21.919465 <3>[ 13.732314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10628 19:54:21.926171 <3>[ 13.732328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10629 19:54:21.932798 <6>[ 13.753757] remoteproc remoteproc0: scp is available
10630 19:54:21.936113 <6>[ 13.753846] remoteproc remoteproc0: powering up scp
10631 19:54:21.946159 <3>[ 13.753848] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10632 19:54:21.952477 <6>[ 13.753851] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10633 19:54:21.959348 <6>[ 13.753874] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10634 19:54:21.965775 <4>[ 13.755570] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10635 19:54:21.975728 <4>[ 13.763263] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10636 19:54:21.978956 <6>[ 13.776313] mc: Linux media interface: v0.10
10637 19:54:21.988687 <3>[ 13.782297] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10638 19:54:21.991840 <6>[ 13.799208] usbcore: registered new interface driver r8152
10639 19:54:21.998593 <6>[ 13.817123] videodev: Linux video capture interface: v2.00
10640 19:54:22.005352 <6>[ 13.829790] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10641 19:54:22.012088 <6>[ 13.829801] pci_bus 0000:00: root bus resource [bus 00-ff]
10642 19:54:22.018345 <6>[ 13.829810] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10643 19:54:22.028496 <6>[ 13.829815] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10644 19:54:22.035251 <6>[ 13.829860] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10645 19:54:22.041389 <6>[ 13.829884] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10646 19:54:22.047935 <6>[ 13.829991] pci 0000:00:00.0: supports D1 D2
10647 19:54:22.055288 <6>[ 13.829995] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10648 19:54:22.061290 <6>[ 13.832481] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10649 19:54:22.068359 <6>[ 13.832693] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10650 19:54:22.074679 <6>[ 13.832729] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10651 19:54:22.084583 <6>[ 13.832753] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10652 19:54:22.091106 <6>[ 13.832771] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10653 19:54:22.095048 <6>[ 13.832902] pci 0000:01:00.0: supports D1 D2
10654 19:54:22.101045 <6>[ 13.832905] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10655 19:54:22.107833 <6>[ 13.841415] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10656 19:54:22.117545 <6>[ 13.841445] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10657 19:54:22.124278 <6>[ 13.841451] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10658 19:54:22.134212 <6>[ 13.841463] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10659 19:54:22.140768 <6>[ 13.841480] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10660 19:54:22.147168 <6>[ 13.841495] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10661 19:54:22.153780 <6>[ 13.841511] pci 0000:00:00.0: PCI bridge to [bus 01]
10662 19:54:22.160526 <6>[ 13.841519] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10663 19:54:22.166969 <6>[ 13.841668] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10664 19:54:22.173191 <6>[ 13.842610] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10665 19:54:22.180141 <6>[ 13.842902] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10666 19:54:22.190257 <6>[ 13.878412] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10667 19:54:22.196865 <6>[ 13.885936] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10668 19:54:22.202999 <6>[ 13.885954] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10669 19:54:22.213134 <6>[ 13.885988] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10670 19:54:22.219965 <6>[ 13.885997] remoteproc remoteproc0: remote processor scp is now up
10671 19:54:22.229811 <6>[ 13.894601] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10672 19:54:22.236438 <6>[ 13.895061] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10673 19:54:22.246643 <4>[ 13.909070] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10674 19:54:22.256016 <4>[ 13.909084] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10675 19:54:22.259447 <6>[ 13.930712] usbcore: registered new interface driver cdc_ether
10676 19:54:22.266191 <6>[ 13.938870] usbcore: registered new interface driver r8153_ecm
10677 19:54:22.275789 <6>[ 13.940749] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10678 19:54:22.279019 <6>[ 13.940800] Bluetooth: Core ver 2.22
10679 19:54:22.287064 <6>[ 13.940896] NET: Registered PF_BLUETOOTH protocol family
10680 19:54:22.292271 <6>[ 13.940898] Bluetooth: HCI device and connection manager initialized
10681 19:54:22.296050 <6>[ 13.940912] Bluetooth: HCI socket layer initialized
10682 19:54:22.302238 <6>[ 13.940916] Bluetooth: L2CAP socket layer initialized
10683 19:54:22.306148 <6>[ 13.940923] Bluetooth: SCO socket layer initialized
10684 19:54:22.315263 <5>[ 13.941037] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10685 19:54:22.322717 <6>[ 13.943715] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10686 19:54:22.328898 <5>[ 13.955346] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10687 19:54:22.338726 <4>[ 13.955429] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10688 19:54:22.344912 <6>[ 13.955438] cfg80211: failed to load regulatory.db
10689 19:54:22.351869 <6>[ 13.959465] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10690 19:54:22.361560 <6>[ 13.961395] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10691 19:54:22.368077 <6>[ 13.961543] usbcore: registered new interface driver uvcvideo
10692 19:54:22.375206 <6>[ 13.961543] r8152 2-1.3:1.0 eth0: v1.12.13
10693 19:54:22.378470 <6>[ 13.971882] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10694 19:54:22.384888 <6>[ 13.979398] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10695 19:54:22.391471 <6>[ 13.989936] usbcore: registered new interface driver btusb
10696 19:54:22.401780 <4>[ 13.990976] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10697 19:54:22.408134 <3>[ 13.990989] Bluetooth: hci0: Failed to load firmware file (-2)
10698 19:54:22.414523 <3>[ 13.990992] Bluetooth: hci0: Failed to set up firmware (-2)
10699 19:54:22.424949 <4>[ 13.990995] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10700 19:54:22.431627 <6>[ 14.383879] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10701 19:54:22.437470 <6>[ 14.383987] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10702 19:54:22.444291 <6>[ 14.401543] mt7921e 0000:01:00.0: ASIC revision: 79610010
10703 19:54:22.538068 <4>[ 14.497140] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10704 19:54:22.546269 Begin: Loading essential drivers ... done.
10705 19:54:22.549976 Begin: Running /scripts/init-premount ... done.
10706 19:54:22.555750 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10707 19:54:22.565902 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10708 19:54:22.569120 Device /sys/class/net/enx0024323078ff found
10709 19:54:22.569644 done.
10710 19:54:22.619144 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10711 19:54:22.650301 <4>[ 14.605512] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10712 19:54:22.758058 <4>[ 14.713351] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10713 19:54:22.862228 <4>[ 14.821208] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10714 19:54:22.974007 <4>[ 14.929486] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10715 19:54:23.077852 <4>[ 15.037281] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10716 19:54:23.189905 <4>[ 15.145348] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10717 19:54:23.294531 <4>[ 15.253183] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10718 19:54:23.401833 <4>[ 15.361286] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10719 19:54:23.509940 <4>[ 15.469170] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10720 19:54:23.611054 <3>[ 15.575187] mt7921e 0000:01:00.0: hardware init failed
10721 19:54:23.738878 <6>[ 15.702920] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10722 19:54:24.515835 IP-Config: no response after 2 secs - giving up
10723 19:54:24.551029 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10724 19:54:24.553913 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10725 19:54:24.564100 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10726 19:54:24.570670 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10727 19:54:24.577401 host : mt8192-asurada-spherion-r0-cbg-8
10728 19:54:24.583677 domain : lava-rack
10729 19:54:24.586875 rootserver: 192.168.201.1 rootpath:
10730 19:54:24.587516 filename :
10731 19:54:24.696906 done.
10732 19:54:24.705123 Begin: Running /scripts/nfs-bottom ... done.
10733 19:54:24.722696 Begin: Running /scripts/init-bottom ... done.
10734 19:54:25.991051 <6>[ 17.955050] NET: Registered PF_INET6 protocol family
10735 19:54:25.994064 <6>[ 17.957131] Segment Routing with IPv6
10736 19:54:26.000552 <6>[ 17.957157] In-situ OAM (IOAM) with IPv6
10737 19:54:26.114889 <30>[ 18.057853] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10738 19:54:26.118670 <30>[ 18.058849] systemd[1]: Detected architecture arm64.
10739 19:54:26.119192
10740 19:54:26.125176 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10741 19:54:26.125673
10742 19:54:26.142900 <30>[ 18.108637] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10743 19:54:27.049671 <30>[ 19.011793] systemd[1]: Queued start job for default target Graphical Interface.
10744 19:54:27.080746 [[0;32m OK [<30>[ 19.043955] systemd[1]: Created slice system-getty.slice.
10745 19:54:27.084142 0m] Created slice [0;1;39msystem-getty.slice[0m.
10746 19:54:27.103935 [[0;32m OK [0m] Created slic<30>[ 19.067096] systemd[1]: Created slice system-modprobe.slice.
10747 19:54:27.106583 e [0;1;39msystem-modprobe.slice[0m.
10748 19:54:27.127518 [[0;32m OK [0m] Created slic<30>[ 19.090874] systemd[1]: Created slice system-serial\x2dgetty.slice.
10749 19:54:27.134004 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10750 19:54:27.152265 [[0;32m OK [0m] Created slic<30>[ 19.115539] systemd[1]: Created slice User and Session Slice.
10751 19:54:27.155224 e [0;1;39mUser and Session Slice[0m.
10752 19:54:27.178431 [[0;32m OK [0m] Started [0;<30>[ 19.138575] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10753 19:54:27.181714 1;39mDispatch Password …ts to Console Directory Watch[0m.
10754 19:54:27.209468 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.169844] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10755 19:54:27.213084 sword R…uests to Wall Directory Watch[0m.
10756 19:54:27.236971 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.193808] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10757 19:54:27.243883 <30>[ 19.194002] systemd[1]: Reached target Local Encrypted Volumes.
10758 19:54:27.246967 l Encrypted Volumes[0m.
10759 19:54:27.266220 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.229781] systemd[1]: Reached target Paths.
10760 19:54:27.266342 s[0m.
10761 19:54:27.289652 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.249658] systemd[1]: Reached target Remote File Systems.
10762 19:54:27.289790 te File Systems[0m.
10763 19:54:27.310315 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.273647] systemd[1]: Reached target Slices.
10764 19:54:27.310437 es[0m.
10765 19:54:27.330052 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.293666] systemd[1]: Reached target Swap.
10766 19:54:27.330170 [0m.
10767 19:54:27.354078 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.314083] systemd[1]: Listening on initctl Compatibility Named Pipe.
10768 19:54:27.357402 l Compatibility Named Pipe[0m.
10769 19:54:27.367673 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.330190] systemd[1]: Listening on Journal Audit Socket.
10770 19:54:27.370712 l Audit Socket[0m.
10771 19:54:27.391575 [[0;32m OK [0m] Listening on<30>[ 19.355002] systemd[1]: Listening on Journal Socket (/dev/log).
10772 19:54:27.394516 [0;1;39mJournal Socket (/dev/log)[0m.
10773 19:54:27.415844 [[0;32m OK [0m] Listening on<30>[ 19.378964] systemd[1]: Listening on Journal Socket.
10774 19:54:27.418511 [0;1;39mJournal Socket[0m.
10775 19:54:27.435777 [[0;32m OK [0m] Listening on<30>[ 19.399527] systemd[1]: Listening on Network Service Netlink Socket.
10776 19:54:27.442295 [0;1;39mNetwork Service Netlink Socket[0m.
10777 19:54:27.462163 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 19.425800] systemd[1]: Listening on udev Control Socket.
10778 19:54:27.465703 ontrol Socket[0m.
10779 19:54:27.486361 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 19.450140] systemd[1]: Listening on udev Kernel Socket.
10780 19:54:27.489897 ernel Socket[0m.
10781 19:54:27.545742 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.505854] systemd[1]: Mounting Huge Pages File System...
10782 19:54:27.545881 m[0m...
10783 19:54:27.562279 <30>[ 19.529313] systemd[1]: Mounting POSIX Message Queue File System...
10784 19:54:27.569316 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10785 19:54:27.597949 Mounting [0;1;39mKernel Debug File Sys<30>[ 19.558279] systemd[1]: Mounting Kernel Debug File System...
10786 19:54:27.598084 tem[0m...
10787 19:54:27.617691 <30>[ 19.577792] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10788 19:54:27.690308 Starting [0;1;39mCreate list of st…o<30>[ 19.650303] systemd[1]: Starting Create list of static device nodes for the current kernel...
10789 19:54:27.693899 des for the current kernel[0m...
10790 19:54:27.720840 Startin<30>[ 19.684191] systemd[1]: Starting Load Kernel Module configfs...
10791 19:54:27.724316 g [0;1;39mLoad Kernel Module configfs[0m...
10792 19:54:27.749622 Starting [0;1;39mLoad Kernel Module dr<30>[ 19.709651] systemd[1]: Starting Load Kernel Module drm...
10793 19:54:27.749755 m[0m...
10794 19:54:27.771193 Starting [0;1;39mLoad <30>[ 19.734584] systemd[1]: Starting Load Kernel Module fuse...
10795 19:54:27.774604 Kernel Module fuse[0m...
10796 19:54:27.797693 <30>[ 19.760183] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10797 19:54:27.811959 Starting [0;1;39mJourn<30>[ 19.775211] systemd[1]: Starting Journal Service...
10798 19:54:27.812086 al Service[0m...
10799 19:54:27.830237 <6>[ 19.793729] fuse: init (API version 7.37)
10800 19:54:27.845048 Startin<30>[ 19.808057] systemd[1]: Starting Load Kernel Modules...
10801 19:54:27.848257 g [0;1;39mLoad Kernel Modules[0m...
10802 19:54:27.873390 Starting [0;1;39mRemount Root and Kern<30>[ 19.833779] systemd[1]: Starting Remount Root and Kernel File Systems...
10803 19:54:27.876627 el File Systems[0m...
10804 19:54:27.900703 Startin<30>[ 19.864014] systemd[1]: Starting Coldplug All udev Devices...
10805 19:54:27.904057 g [0;1;39mColdplug All udev Devices[0m...
10806 19:54:27.925981 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages <30>[ 19.889810] systemd[1]: Mounted Huge Pages File System.
10807 19:54:27.929463 File System[0m.
10808 19:54:27.947702 [[0;32m OK [0m] Mounted [0;<30>[ 19.911365] systemd[1]: Mounted POSIX Message Queue File System.
10809 19:54:27.950980 1;39mPOSIX Message Queue File System[0m.
10810 19:54:27.974653 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 19.938278] systemd[1]: Mounted Kernel Debug File System.
10811 19:54:27.978015 g File System[0m.
10812 19:54:28.003282 [[0;32m OK [0m] Finished [0<30>[ 19.963579] systemd[1]: Finished Create list of static device nodes for the current kernel.
10813 19:54:28.009567 ;1;39mCreate list of st… nodes for the current kernel[0m.
10814 19:54:28.030927 [[0;32m OK [0m] Finished [0<3>[ 19.989490] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10815 19:54:28.037650 ;1;39mLoad Kerne<30>[ 19.990568] systemd[1]: modprobe@configfs.service: Succeeded.
10816 19:54:28.047568 l Module configf<30>[ 19.991276] systemd[1]: Finished Load Kernel Module configfs.
10817 19:54:28.047671 s[0m.
10818 19:54:28.067326 [[0;32m OK [0m] Finished [0<30>[ 20.030177] systemd[1]: modprobe@drm.service: Succeeded.
10819 19:54:28.074208 ;1;39mLoad Kerne<30>[ 20.030735] systemd[1]: Finished Load Kernel Module drm.
10820 19:54:28.083970 l Module drm[0m<3>[ 20.035465] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10821 19:54:28.084072 .
10822 19:54:28.103865 [[0;32m OK [0m] Finished [0<30>[ 20.066531] systemd[1]: modprobe@fuse.service: Succeeded.
10823 19:54:28.110221 ;1;39mLoad Kerne<30>[ 20.067309] systemd[1]: Finished Load Kernel Module fuse.
10824 19:54:28.113736 l Module fuse[0m.
10825 19:54:28.134688 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 20.093538] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10826 19:54:28.138240 l Modules[0m.
10827 19:54:28.141487 <30>[ 20.094498] systemd[1]: Finished Load Kernel Modules.
10828 19:54:28.151904 <3>[ 20.113686] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10829 19:54:28.162375 [[0;32m OK [<30>[ 20.124149] systemd[1]: Finished Remount Root and Kernel File Systems.
10830 19:54:28.165651 0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10831 19:54:28.175727 <3>[ 20.135476] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10832 19:54:28.175834
10833 19:54:28.193723 <3>[ 20.155364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10834 19:54:28.214144 <3>[ 20.177144] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 19:54:28.224513 Mounting [0;1;39mFUSE <30>[ 20.186394] systemd[1]: Mounting FUSE Control File System...
10836 19:54:28.227848 Control File System[0m...
10837 19:54:28.237808 <3>[ 20.198005] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10838 19:54:28.254954 Mounting [0;1;39mKernel Configuration <30>[ 20.214156] systemd[1]: Mounting Kernel Configuration File System...
10839 19:54:28.264749 File System[0m.<3>[ 20.220072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10840 19:54:28.264861 ..
10841 19:54:28.277464 <3>[ 20.240088] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10842 19:54:28.294542 <30>[ 20.255731] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10843 19:54:28.307338 Starting [0;1;39mLoad/Save Random Seed<30>[ 20.255893] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10844 19:54:28.307497 [0m...
10845 19:54:28.314962 <30>[ 20.258290] systemd[1]: Starting Load/Save Random Seed...
10846 19:54:28.328289 Starting [0;1;39mApply<30>[ 20.291825] systemd[1]: Starting Apply Kernel Variables...
10847 19:54:28.331251 Kernel Variables[0m...
10848 19:54:28.354069 Starting [0;1;39mCreate System Users[<30>[ 20.317732] systemd[1]: Starting Create System Users...
10849 19:54:28.357634 0m...
10850 19:54:28.376072 [[0;32m OK [0m] Started [0;<30>[ 20.339732] systemd[1]: Started Journal Service.
10851 19:54:28.379541 1;39mJournal Service[0m.
10852 19:54:28.415860 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10853 19:54:28.431739 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10854 19:54:28.448089 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10855 19:54:28.464813 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10856 19:54:28.484966 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10857 19:54:28.531716 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10858 19:54:28.549912 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10859 19:54:28.568422 <4>[ 20.521633] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10860 19:54:28.575985 <3>[ 20.521758] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10861 19:54:28.586871 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10862 19:54:28.605547 <46>[ 20.567447] systemd-journald[307]: Received client request to flush runtime journal.
10863 19:54:28.612140 See 'systemctl status systemd-udev-trigger.service' for details.
10864 19:54:29.188966 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10865 19:54:29.207620 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10866 19:54:29.226876 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10867 19:54:29.290970 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10868 19:54:30.028087 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10869 19:54:30.067032 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10870 19:54:30.118399 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10871 19:54:30.180635 Starting [0;1;39mNetwork Service[0m...
10872 19:54:30.415013 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10873 19:54:30.471212 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10874 19:54:30.489636 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10875 19:54:30.856402 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10876 19:54:30.874297 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10877 19:54:30.943090 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10878 19:54:30.959092 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10879 19:54:30.983363 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10880 19:54:31.002734 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10881 19:54:31.027543 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10882 19:54:31.099520 Starting [0;1;39mNetwork Name Resolution[0m...
10883 19:54:31.126448 Starting [0;1;39mNetwork Time Synchronization[0m...
10884 19:54:31.147528 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10885 19:54:31.192916 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10886 19:54:31.292609 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10887 19:54:31.311932 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10888 19:54:31.330988 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10889 19:54:31.346561 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10890 19:54:31.362119 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10891 19:54:31.397428 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10892 19:54:31.601231 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10893 19:54:32.047832 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10894 19:54:32.139746 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10895 19:54:32.154828 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10896 19:54:32.499634 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10897 19:54:32.513946 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10898 19:54:32.530309 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10899 19:54:32.583940 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10900 19:54:32.730553 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10901 19:54:32.847378 Starting [0;1;39mUser Login Management[0m...
10902 19:54:32.864256 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10903 19:54:32.884888 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10904 19:54:32.901959 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10905 19:54:32.935697 Starting [0;1;39mPermit User Sessions[0m...
10906 19:54:33.046221 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10907 19:54:33.094998 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10908 19:54:33.137277 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10909 19:54:33.158782 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10910 19:54:33.186359 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10911 19:54:33.212639 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10912 19:54:33.221362 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10913 19:54:33.245007 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10914 19:54:33.290566 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10915 19:54:33.341941 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10916 19:54:33.445511
10917 19:54:33.445654
10918 19:54:33.448624 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10919 19:54:33.448708
10920 19:54:33.451505 debian-bullseye-arm64 login: root (automatic login)
10921 19:54:33.451588
10922 19:54:33.451652
10923 19:54:33.797177 Linux debian-bullseye-arm64 6.1.59-cip8-rt4 #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023 aarch64
10924 19:54:33.797313
10925 19:54:33.803981 The programs included with the Debian GNU/Linux system are free software;
10926 19:54:33.810261 the exact distribution terms for each program are described in the
10927 19:54:33.813418 individual files in /usr/share/doc/*/copyright.
10928 19:54:33.813530
10929 19:54:33.820384 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10930 19:54:33.823681 permitted by applicable law.
10931 19:54:33.924203 Matched prompt #10: / #
10933 19:54:33.924466 Setting prompt string to ['/ #']
10934 19:54:33.924559 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10936 19:54:33.924750 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10937 19:54:33.924877 start: 2.2.6 expect-shell-connection (timeout 00:03:03) [common]
10938 19:54:33.924988 Setting prompt string to ['/ #']
10939 19:54:33.925138 Forcing a shell prompt, looking for ['/ #']
10941 19:54:33.975481 / #
10942 19:54:33.975647 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10943 19:54:33.975748 Waiting using forced prompt support (timeout 00:02:30)
10944 19:54:33.980468
10945 19:54:33.980748 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10946 19:54:33.980860 start: 2.2.7 export-device-env (timeout 00:03:03) [common]
10948 19:54:34.081214 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11899560/extract-nfsrootfs-d9ma_j26'
10949 19:54:34.086407 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11899560/extract-nfsrootfs-d9ma_j26'
10951 19:54:34.186969 / # export NFS_SERVER_IP='192.168.201.1'
10952 19:54:34.192753 export NFS_SERVER_IP='192.168.201.1'
10953 19:54:34.193042 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10954 19:54:34.193150 end: 2.2 depthcharge-retry (duration 00:01:57) [common]
10955 19:54:34.193257 end: 2 depthcharge-action (duration 00:01:57) [common]
10956 19:54:34.193365 start: 3 lava-test-retry (timeout 00:01:00) [common]
10957 19:54:34.193470 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10958 19:54:34.193556 Using namespace: common
10960 19:54:34.293933 / # #
10961 19:54:34.294095 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10962 19:54:34.299350 #
10963 19:54:34.299640 Using /lava-11899560
10965 19:54:34.399952 / # export SHELL=/bin/sh
10966 19:54:34.405320 export SHELL=/bin/sh
10968 19:54:34.505853 / # . /lava-11899560/environment
10969 19:54:34.510967 . /lava-11899560/environment
10971 19:54:34.617946 / # /lava-11899560/bin/lava-test-runner /lava-11899560/0
10972 19:54:34.618082 Test shell timeout: 10s (minimum of the action and connection timeout)
10973 19:54:34.623412 /lava-11899560/bin/lava-test-runner /lava-11899560/0
10974 19:54:34.895947 + export TESTRUN_ID=0_dmesg
10975 19:54:34.898890 + cd /lava-11899560/0/tests/0_dmesg
10976 19:54:34.902689 + cat uuid
10977 19:54:34.912213 + UUID=11899560_1.6.2.3.1
10978 19:54:34.918284 + set<8>[ 26.883059] <LAVA_SIGNAL_STARTRUN 0_dmesg 11899560_1.6.2.3.1>
10979 19:54:34.918367 +x
10980 19:54:34.918611 Received signal: <STARTRUN> 0_dmesg 11899560_1.6.2.3.1
10981 19:54:34.918686 Starting test lava.0_dmesg (11899560_1.6.2.3.1)
10982 19:54:34.918773 Skipping test definition patterns.
10983 19:54:34.924800 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10984 19:54:35.025078 <8>[ 26.986590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10985 19:54:35.025384 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10987 19:54:35.096980 <8>[ 27.058948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10988 19:54:35.097285 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10990 19:54:35.163193 + set +x
10991 19:54:35.173457 <LAVA_TEST_RUNNE<8>[ 27.133710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10992 19:54:35.173725 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10994 19:54:35.176751 R EXIT>
10995 19:54:35.179642 <8>[ 27.134683] <LAVA_SIGNAL_ENDRUN 0_dmesg 11899560_1.6.2.3.1>
10996 19:54:35.179897 Received signal: <ENDRUN> 0_dmesg 11899560_1.6.2.3.1
10997 19:54:35.179979 Ending use of test pattern.
10998 19:54:35.180041 Ending test lava.0_dmesg (11899560_1.6.2.3.1), duration 0.26
11000 19:54:52.064586 / # <6>[ 44.033799] vpu: disabling
11001 19:54:52.067964 <6>[ 44.033937] vproc2: disabling
11002 19:54:52.071369 <6>[ 44.033992] vproc1: disabling
11003 19:54:52.074065 <6>[ 44.034047] vaud18: disabling
11004 19:54:52.077543 <6>[ 44.034301] vsram_others: disabling
11005 19:54:52.081134 <6>[ 44.034481] va09: disabling
11006 19:54:52.084698 <6>[ 44.034560] vsram_md: disabling
11007 19:54:52.087615 <6>[ 44.034691] Vgpu: disabling
11009 19:55:34.193744 end: 3.1 lava-test-shell (duration 00:01:00) [common]
11011 19:55:34.194104 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
11013 19:55:34.194353 end: 3 lava-test-retry (duration 00:01:00) [common]
11015 19:55:34.194730 Cleaning after the job
11016 19:55:34.194843 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/ramdisk
11017 19:55:34.197869 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/kernel
11018 19:55:34.212841 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/dtb
11019 19:55:34.213062 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/nfsrootfs
11020 19:55:34.288723 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899560/tftp-deploy-11qjant5/modules
11021 19:55:34.295970 start: 5.1 power-off (timeout 00:00:30) [common]
11022 19:55:34.296146 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11023 19:55:34.374444 >> Command sent successfully.
11024 19:55:34.379374 Returned 0 in 0 seconds
11025 19:55:34.480401 end: 5.1 power-off (duration 00:00:00) [common]
11027 19:55:34.482643 start: 5.2 read-feedback (timeout 00:10:00) [common]
11028 19:55:34.484077 Listened to connection for namespace 'common' for up to 1s
11029 19:55:35.484535 Finalising connection for namespace 'common'
11030 19:55:35.485068 Disconnecting from shell: Finalise
11031 19:55:35.586064 end: 5.2 read-feedback (duration 00:00:01) [common]
11032 19:55:35.586696 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11899560
11033 19:55:36.004392 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11899560
11034 19:55:36.004578 TestError: A test failed to run, look at the error message.