Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 20
- Kernel Errors: 29
- Errors: 1
- Boot result: PASS
1 19:59:24.961378 lava-dispatcher, installed at version: 2023.08
2 19:59:24.961592 start: 0 validate
3 19:59:24.961720 Start time: 2023-10-28 19:59:24.961712+00:00 (UTC)
4 19:59:24.961837 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:59:24.961968 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 19:59:25.237025 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:59:25.237780 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:59:25.501600 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:59:25.502569 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:59:25.773824 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:59:25.774588 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:59:26.050286 validate duration: 1.09
14 19:59:26.050572 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:59:26.050671 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:59:26.050757 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:59:26.050902 Not decompressing ramdisk as can be used compressed.
18 19:59:26.050989 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 19:59:26.051052 saving as /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/ramdisk/rootfs.cpio.gz
20 19:59:26.051117 total size: 34390042 (32 MB)
21 19:59:26.052247 progress 0 % (0 MB)
22 19:59:26.061179 progress 5 % (1 MB)
23 19:59:26.069917 progress 10 % (3 MB)
24 19:59:26.078730 progress 15 % (4 MB)
25 19:59:26.087522 progress 20 % (6 MB)
26 19:59:26.096470 progress 25 % (8 MB)
27 19:59:26.105174 progress 30 % (9 MB)
28 19:59:26.114069 progress 35 % (11 MB)
29 19:59:26.122802 progress 40 % (13 MB)
30 19:59:26.131854 progress 45 % (14 MB)
31 19:59:26.140545 progress 50 % (16 MB)
32 19:59:26.149304 progress 55 % (18 MB)
33 19:59:26.157961 progress 60 % (19 MB)
34 19:59:26.166837 progress 65 % (21 MB)
35 19:59:26.175605 progress 70 % (22 MB)
36 19:59:26.184421 progress 75 % (24 MB)
37 19:59:26.193199 progress 80 % (26 MB)
38 19:59:26.202050 progress 85 % (27 MB)
39 19:59:26.210697 progress 90 % (29 MB)
40 19:59:26.219478 progress 95 % (31 MB)
41 19:59:26.227980 progress 100 % (32 MB)
42 19:59:26.228157 32 MB downloaded in 0.18 s (185.25 MB/s)
43 19:59:26.228311 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:59:26.228549 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:59:26.228635 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:59:26.228719 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:59:26.228855 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:59:26.228928 saving as /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/kernel/Image
50 19:59:26.228989 total size: 49304064 (47 MB)
51 19:59:26.229050 No compression specified
52 19:59:26.230191 progress 0 % (0 MB)
53 19:59:26.242948 progress 5 % (2 MB)
54 19:59:26.255678 progress 10 % (4 MB)
55 19:59:26.268035 progress 15 % (7 MB)
56 19:59:26.280506 progress 20 % (9 MB)
57 19:59:26.293192 progress 25 % (11 MB)
58 19:59:26.305785 progress 30 % (14 MB)
59 19:59:26.318317 progress 35 % (16 MB)
60 19:59:26.330929 progress 40 % (18 MB)
61 19:59:26.343661 progress 45 % (21 MB)
62 19:59:26.356146 progress 50 % (23 MB)
63 19:59:26.368926 progress 55 % (25 MB)
64 19:59:26.381287 progress 60 % (28 MB)
65 19:59:26.394037 progress 65 % (30 MB)
66 19:59:26.406545 progress 70 % (32 MB)
67 19:59:26.418947 progress 75 % (35 MB)
68 19:59:26.431464 progress 80 % (37 MB)
69 19:59:26.444062 progress 85 % (39 MB)
70 19:59:26.456627 progress 90 % (42 MB)
71 19:59:26.468883 progress 95 % (44 MB)
72 19:59:26.481334 progress 100 % (47 MB)
73 19:59:26.481538 47 MB downloaded in 0.25 s (186.18 MB/s)
74 19:59:26.481686 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:59:26.481914 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:59:26.481999 start: 1.3 download-retry (timeout 00:10:00) [common]
78 19:59:26.482088 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 19:59:26.482229 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:59:26.482297 saving as /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/dtb/mt8192-asurada-spherion-r0.dtb
81 19:59:26.482361 total size: 47278 (0 MB)
82 19:59:26.482422 No compression specified
83 19:59:26.483587 progress 69 % (0 MB)
84 19:59:26.483858 progress 100 % (0 MB)
85 19:59:26.484010 0 MB downloaded in 0.00 s (27.38 MB/s)
86 19:59:26.484127 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:59:26.484343 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:59:26.484426 start: 1.4 download-retry (timeout 00:10:00) [common]
90 19:59:26.484507 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 19:59:26.484616 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:59:26.484691 saving as /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/modules/modules.tar
93 19:59:26.484751 total size: 8635496 (8 MB)
94 19:59:26.484812 Using unxz to decompress xz
95 19:59:26.488939 progress 0 % (0 MB)
96 19:59:26.510136 progress 5 % (0 MB)
97 19:59:26.531702 progress 10 % (0 MB)
98 19:59:26.557221 progress 15 % (1 MB)
99 19:59:26.581721 progress 20 % (1 MB)
100 19:59:26.606978 progress 25 % (2 MB)
101 19:59:26.634458 progress 30 % (2 MB)
102 19:59:26.658853 progress 35 % (2 MB)
103 19:59:26.683087 progress 40 % (3 MB)
104 19:59:26.706827 progress 45 % (3 MB)
105 19:59:26.732872 progress 50 % (4 MB)
106 19:59:26.757442 progress 55 % (4 MB)
107 19:59:26.783497 progress 60 % (4 MB)
108 19:59:26.805970 progress 65 % (5 MB)
109 19:59:26.830477 progress 70 % (5 MB)
110 19:59:26.854088 progress 75 % (6 MB)
111 19:59:26.879769 progress 80 % (6 MB)
112 19:59:26.911813 progress 85 % (7 MB)
113 19:59:26.937395 progress 90 % (7 MB)
114 19:59:26.961400 progress 95 % (7 MB)
115 19:59:26.984324 progress 100 % (8 MB)
116 19:59:26.989832 8 MB downloaded in 0.51 s (16.31 MB/s)
117 19:59:26.990075 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:59:26.990338 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:59:26.990431 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 19:59:26.990528 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 19:59:26.990612 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:59:26.990698 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 19:59:26.990927 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9
125 19:59:26.991065 makedir: /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin
126 19:59:26.991170 makedir: /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/tests
127 19:59:26.991270 makedir: /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/results
128 19:59:26.991392 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-add-keys
129 19:59:26.991581 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-add-sources
130 19:59:26.991714 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-background-process-start
131 19:59:26.991847 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-background-process-stop
132 19:59:26.991993 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-common-functions
133 19:59:26.992120 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-echo-ipv4
134 19:59:26.992246 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-install-packages
135 19:59:26.992370 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-installed-packages
136 19:59:26.992493 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-os-build
137 19:59:26.992618 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-probe-channel
138 19:59:26.992740 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-probe-ip
139 19:59:26.992863 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-target-ip
140 19:59:26.992986 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-target-mac
141 19:59:26.993108 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-target-storage
142 19:59:26.993235 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-test-case
143 19:59:26.993359 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-test-event
144 19:59:26.993481 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-test-feedback
145 19:59:26.993603 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-test-raise
146 19:59:26.993731 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-test-reference
147 19:59:26.993854 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-test-runner
148 19:59:26.993978 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-test-set
149 19:59:26.994103 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-test-shell
150 19:59:26.994230 Updating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-install-packages (oe)
151 19:59:26.994383 Updating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/bin/lava-installed-packages (oe)
152 19:59:26.994505 Creating /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/environment
153 19:59:26.994604 LAVA metadata
154 19:59:26.994678 - LAVA_JOB_ID=11899596
155 19:59:26.994743 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:59:26.994843 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 19:59:26.994910 skipped lava-vland-overlay
158 19:59:26.994983 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:59:26.995065 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 19:59:26.995128 skipped lava-multinode-overlay
161 19:59:26.995205 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:59:26.995288 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 19:59:26.995365 Loading test definitions
164 19:59:26.995503 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 19:59:26.995576 Using /lava-11899596 at stage 0
166 19:59:26.995887 uuid=11899596_1.5.2.3.1 testdef=None
167 19:59:26.995973 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 19:59:26.996061 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 19:59:26.996572 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 19:59:26.996793 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 19:59:26.997405 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 19:59:26.997633 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 19:59:26.998218 runner path: /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/0/tests/0_cros-ec test_uuid 11899596_1.5.2.3.1
176 19:59:26.998371 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 19:59:26.998576 Creating lava-test-runner.conf files
179 19:59:26.998637 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899596/lava-overlay-rmqbyzm9/lava-11899596/0 for stage 0
180 19:59:26.998728 - 0_cros-ec
181 19:59:26.998824 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 19:59:26.998909 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 19:59:27.005541 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 19:59:27.005647 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 19:59:27.005734 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 19:59:27.005817 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 19:59:27.005902 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 19:59:27.983912 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 19:59:27.984300 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 19:59:27.984414 extracting modules file /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899596/extract-overlay-ramdisk-av7f6yxp/ramdisk
191 19:59:28.209635 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 19:59:28.209803 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 19:59:28.209897 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899596/compress-overlay-8ad21ce4/overlay-1.5.2.4.tar.gz to ramdisk
194 19:59:28.209969 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899596/compress-overlay-8ad21ce4/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11899596/extract-overlay-ramdisk-av7f6yxp/ramdisk
195 19:59:28.216619 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 19:59:28.216731 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 19:59:28.216819 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 19:59:28.216910 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 19:59:28.216986 Building ramdisk /var/lib/lava/dispatcher/tmp/11899596/extract-overlay-ramdisk-av7f6yxp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11899596/extract-overlay-ramdisk-av7f6yxp/ramdisk
200 19:59:28.982497 >> 271044 blocks
201 19:59:33.617402 rename /var/lib/lava/dispatcher/tmp/11899596/extract-overlay-ramdisk-av7f6yxp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/ramdisk/ramdisk.cpio.gz
202 19:59:33.617854 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 19:59:33.617981 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 19:59:33.618088 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 19:59:33.618191 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/kernel/Image'
206 19:59:45.506785 Returned 0 in 11 seconds
207 19:59:45.607813 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/kernel/image.itb
208 19:59:46.335953 output: FIT description: Kernel Image image with one or more FDT blobs
209 19:59:46.336324 output: Created: Sat Oct 28 20:59:46 2023
210 19:59:46.336398 output: Image 0 (kernel-1)
211 19:59:46.336465 output: Description:
212 19:59:46.336524 output: Created: Sat Oct 28 20:59:46 2023
213 19:59:46.336586 output: Type: Kernel Image
214 19:59:46.336647 output: Compression: lzma compressed
215 19:59:46.336706 output: Data Size: 11047522 Bytes = 10788.60 KiB = 10.54 MiB
216 19:59:46.336766 output: Architecture: AArch64
217 19:59:46.336857 output: OS: Linux
218 19:59:46.336912 output: Load Address: 0x00000000
219 19:59:46.336970 output: Entry Point: 0x00000000
220 19:59:46.337024 output: Hash algo: crc32
221 19:59:46.337080 output: Hash value: da40eda2
222 19:59:46.337136 output: Image 1 (fdt-1)
223 19:59:46.337190 output: Description: mt8192-asurada-spherion-r0
224 19:59:46.337241 output: Created: Sat Oct 28 20:59:46 2023
225 19:59:46.337294 output: Type: Flat Device Tree
226 19:59:46.337345 output: Compression: uncompressed
227 19:59:46.337397 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 19:59:46.337449 output: Architecture: AArch64
229 19:59:46.337500 output: Hash algo: crc32
230 19:59:46.337551 output: Hash value: cc4352de
231 19:59:46.337602 output: Image 2 (ramdisk-1)
232 19:59:46.337653 output: Description: unavailable
233 19:59:46.337704 output: Created: Sat Oct 28 20:59:46 2023
234 19:59:46.337756 output: Type: RAMDisk Image
235 19:59:46.337807 output: Compression: Unknown Compression
236 19:59:46.337858 output: Data Size: 47514256 Bytes = 46400.64 KiB = 45.31 MiB
237 19:59:46.337910 output: Architecture: AArch64
238 19:59:46.337961 output: OS: Linux
239 19:59:46.338013 output: Load Address: unavailable
240 19:59:46.338064 output: Entry Point: unavailable
241 19:59:46.338115 output: Hash algo: crc32
242 19:59:46.338166 output: Hash value: 44561827
243 19:59:46.338217 output: Default Configuration: 'conf-1'
244 19:59:46.338268 output: Configuration 0 (conf-1)
245 19:59:46.338319 output: Description: mt8192-asurada-spherion-r0
246 19:59:46.338370 output: Kernel: kernel-1
247 19:59:46.338421 output: Init Ramdisk: ramdisk-1
248 19:59:46.338471 output: FDT: fdt-1
249 19:59:46.338522 output: Loadables: kernel-1
250 19:59:46.338573 output:
251 19:59:46.338775 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 19:59:46.338872 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 19:59:46.338976 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 19:59:46.339070 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 19:59:46.339154 No LXC device requested
256 19:59:46.339231 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 19:59:46.339317 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 19:59:46.339400 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 19:59:46.339506 Checking files for TFTP limit of 4294967296 bytes.
260 19:59:46.340002 end: 1 tftp-deploy (duration 00:00:20) [common]
261 19:59:46.340103 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 19:59:46.340193 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 19:59:46.340316 substitutions:
264 19:59:46.340382 - {DTB}: 11899596/tftp-deploy-qe5iq69e/dtb/mt8192-asurada-spherion-r0.dtb
265 19:59:46.340446 - {INITRD}: 11899596/tftp-deploy-qe5iq69e/ramdisk/ramdisk.cpio.gz
266 19:59:46.340503 - {KERNEL}: 11899596/tftp-deploy-qe5iq69e/kernel/Image
267 19:59:46.340559 - {LAVA_MAC}: None
268 19:59:46.340612 - {PRESEED_CONFIG}: None
269 19:59:46.340665 - {PRESEED_LOCAL}: None
270 19:59:46.340717 - {RAMDISK}: 11899596/tftp-deploy-qe5iq69e/ramdisk/ramdisk.cpio.gz
271 19:59:46.340770 - {ROOT_PART}: None
272 19:59:46.340851 - {ROOT}: None
273 19:59:46.340919 - {SERVER_IP}: 192.168.201.1
274 19:59:46.340971 - {TEE}: None
275 19:59:46.341023 Parsed boot commands:
276 19:59:46.341076 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 19:59:46.341250 Parsed boot commands: tftpboot 192.168.201.1 11899596/tftp-deploy-qe5iq69e/kernel/image.itb 11899596/tftp-deploy-qe5iq69e/kernel/cmdline
278 19:59:46.341336 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 19:59:46.341418 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 19:59:46.341512 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 19:59:46.341597 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 19:59:46.341666 Not connected, no need to disconnect.
283 19:59:46.341737 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 19:59:46.341815 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 19:59:46.341881 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 19:59:46.345972 Setting prompt string to ['lava-test: # ']
287 19:59:46.346336 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 19:59:46.346446 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 19:59:46.346543 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 19:59:46.346684 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 19:59:46.347020 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 19:59:51.504654 >> Command sent successfully.
293 19:59:51.514971 Returned 0 in 5 seconds
294 19:59:51.616210 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 19:59:51.617575 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 19:59:51.618057 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 19:59:51.618547 Setting prompt string to 'Starting depthcharge on Spherion...'
299 19:59:51.619064 Changing prompt to 'Starting depthcharge on Spherion...'
300 19:59:51.619556 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 19:59:51.620822 [Enter `^Ec?' for help]
302 19:59:51.778204
303 19:59:51.778740
304 19:59:51.779093 F0: 102B 0000
305 19:59:51.779483
306 19:59:51.779818 F3: 1001 0000 [0200]
307 19:59:51.781881
308 19:59:51.782315 F3: 1001 0000
309 19:59:51.782660
310 19:59:51.782979 F7: 102D 0000
311 19:59:51.783282
312 19:59:51.784511 F1: 0000 0000
313 19:59:51.784936
314 19:59:51.785270 V0: 0000 0000 [0001]
315 19:59:51.785595
316 19:59:51.787924 00: 0007 8000
317 19:59:51.788374
318 19:59:51.788710 01: 0000 0000
319 19:59:51.789033
320 19:59:51.791548 BP: 0C00 0209 [0000]
321 19:59:51.792079
322 19:59:51.792425 G0: 1182 0000
323 19:59:51.792742
324 19:59:51.795218 EC: 0000 0021 [4000]
325 19:59:51.795804
326 19:59:51.796150 S7: 0000 0000 [0000]
327 19:59:51.796463
328 19:59:51.799151 CC: 0000 0000 [0001]
329 19:59:51.799629
330 19:59:51.799971 T0: 0000 0040 [010F]
331 19:59:51.800285
332 19:59:51.800589 Jump to BL
333 19:59:51.800884
334 19:59:51.825690
335 19:59:51.826211
336 19:59:51.826546
337 19:59:51.833025 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 19:59:51.836648 ARM64: Exception handlers installed.
339 19:59:51.840465 ARM64: Testing exception
340 19:59:51.841003 ARM64: Done test exception
341 19:59:51.850874 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 19:59:51.860391 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 19:59:51.867801 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 19:59:51.877448 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 19:59:51.884259 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 19:59:51.890811 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 19:59:51.902094 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 19:59:51.908636 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 19:59:51.927792 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 19:59:51.932022 WDT: Last reset was cold boot
351 19:59:51.934763 SPI1(PAD0) initialized at 2873684 Hz
352 19:59:51.938618 SPI5(PAD0) initialized at 992727 Hz
353 19:59:51.941607 VBOOT: Loading verstage.
354 19:59:51.948158 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 19:59:51.951619 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 19:59:51.955453 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 19:59:51.958442 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 19:59:51.965339 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 19:59:51.972571 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 19:59:51.983512 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 19:59:51.984048
362 19:59:51.984389
363 19:59:51.993478 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 19:59:51.996452 ARM64: Exception handlers installed.
365 19:59:51.999591 ARM64: Testing exception
366 19:59:52.000018 ARM64: Done test exception
367 19:59:52.006483 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 19:59:52.009926 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 19:59:52.023849 Probing TPM: . done!
370 19:59:52.024470 TPM ready after 0 ms
371 19:59:52.030584 Connected to device vid:did:rid of 1ae0:0028:00
372 19:59:52.078866 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 19:59:52.079446 Initialized TPM device CR50 revision 0
374 19:59:52.090960 tlcl_send_startup: Startup return code is 0
375 19:59:52.091553 TPM: setup succeeded
376 19:59:52.102156 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 19:59:52.111096 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 19:59:52.122903 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 19:59:52.132460 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 19:59:52.135414 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 19:59:52.139608 in-header: 03 07 00 00 08 00 00 00
382 19:59:52.143653 in-data: aa e4 47 04 13 02 00 00
383 19:59:52.147237 Chrome EC: UHEPI supported
384 19:59:52.153788 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 19:59:52.157195 in-header: 03 9d 00 00 08 00 00 00
386 19:59:52.161074 in-data: 10 20 20 08 00 00 00 00
387 19:59:52.161517 Phase 1
388 19:59:52.168168 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 19:59:52.171757 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 19:59:52.179159 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 19:59:52.179746 Recovery requested (1009000e)
392 19:59:52.188820 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 19:59:52.194280 tlcl_extend: response is 0
394 19:59:52.204275 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 19:59:52.207759 tlcl_extend: response is 0
396 19:59:52.214456 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 19:59:52.234804 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 19:59:52.242603 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 19:59:52.243125
400 19:59:52.243662
401 19:59:52.249912 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 19:59:52.253812 ARM64: Exception handlers installed.
403 19:59:52.258544 ARM64: Testing exception
404 19:59:52.259072 ARM64: Done test exception
405 19:59:52.280221 pmic_efuse_setting: Set efuses in 11 msecs
406 19:59:52.284175 pmwrap_interface_init: Select PMIF_VLD_RDY
407 19:59:52.287542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 19:59:52.295965 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 19:59:52.299025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 19:59:52.302782 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 19:59:52.306702 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 19:59:52.314220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 19:59:52.317959 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 19:59:52.321585 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 19:59:52.328340 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 19:59:52.331709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 19:59:52.338312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 19:59:52.341906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 19:59:52.344997 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 19:59:52.351870 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 19:59:52.358282 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 19:59:52.364819 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 19:59:52.368107 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 19:59:52.375094 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 19:59:52.382055 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 19:59:52.386251 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 19:59:52.393013 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 19:59:52.396219 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 19:59:52.403415 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 19:59:52.406589 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 19:59:52.414039 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 19:59:52.420767 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 19:59:52.423928 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 19:59:52.427706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 19:59:52.434527 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 19:59:52.438246 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 19:59:52.445274 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 19:59:52.449853 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 19:59:52.452859 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 19:59:52.460220 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 19:59:52.463867 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 19:59:52.470797 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 19:59:52.474106 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 19:59:52.477575 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 19:59:52.484260 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 19:59:52.487595 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 19:59:52.491373 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 19:59:52.497572 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 19:59:52.501292 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 19:59:52.504141 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 19:59:52.511143 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 19:59:52.514276 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 19:59:52.518023 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 19:59:52.524287 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 19:59:52.527849 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 19:59:52.530631 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 19:59:52.534238 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 19:59:52.544603 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 19:59:52.550732 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 19:59:52.557302 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 19:59:52.563985 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 19:59:52.574287 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 19:59:52.577293 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 19:59:52.580430 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 19:59:52.587542 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 19:59:52.594255 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xc
467 19:59:52.596995 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 19:59:52.604336 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 19:59:52.608131 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 19:59:52.617122 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 19:59:52.620678 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 19:59:52.628011 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 19:59:52.630704 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 19:59:52.634313 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 19:59:52.637359 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 19:59:52.640431 ADC[4]: Raw value=898890 ID=7
477 19:59:52.643929 ADC[3]: Raw value=213810 ID=1
478 19:59:52.647871 RAM Code: 0x71
479 19:59:52.650730 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 19:59:52.653660 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 19:59:52.664186 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 19:59:52.670687 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 19:59:52.673980 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 19:59:52.677705 in-header: 03 07 00 00 08 00 00 00
485 19:59:52.680827 in-data: aa e4 47 04 13 02 00 00
486 19:59:52.684076 Chrome EC: UHEPI supported
487 19:59:52.688071 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 19:59:52.691748 in-header: 03 d5 00 00 08 00 00 00
489 19:59:52.695729 in-data: 98 20 60 08 00 00 00 00
490 19:59:52.699307 MRC: failed to locate region type 0.
491 19:59:52.706574 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 19:59:52.710445 DRAM-K: Running full calibration
493 19:59:52.716418 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 19:59:52.716857 header.status = 0x0
495 19:59:52.720228 header.version = 0x6 (expected: 0x6)
496 19:59:52.724315 header.size = 0xd00 (expected: 0xd00)
497 19:59:52.727347 header.flags = 0x0
498 19:59:52.730895 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 19:59:52.749656 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 19:59:52.756387 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 19:59:52.759427 dram_init: ddr_geometry: 2
502 19:59:52.763022 [EMI] MDL number = 2
503 19:59:52.763822 [EMI] Get MDL freq = 0
504 19:59:52.766407 dram_init: ddr_type: 0
505 19:59:52.766937 is_discrete_lpddr4: 1
506 19:59:52.769943 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 19:59:52.770487
508 19:59:52.770828
509 19:59:52.772586 [Bian_co] ETT version 0.0.0.1
510 19:59:52.779816 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 19:59:52.780378
512 19:59:52.783005 dramc_set_vcore_voltage set vcore to 650000
513 19:59:52.783591 Read voltage for 800, 4
514 19:59:52.786287 Vio18 = 0
515 19:59:52.786819 Vcore = 650000
516 19:59:52.787165 Vdram = 0
517 19:59:52.789641 Vddq = 0
518 19:59:52.790173 Vmddr = 0
519 19:59:52.792859 dram_init: config_dvfs: 1
520 19:59:52.795873 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 19:59:52.803161 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 19:59:52.805977 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 19:59:52.809631 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 19:59:52.812784 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 19:59:52.816093 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 19:59:52.819501 MEM_TYPE=3, freq_sel=18
527 19:59:52.822677 sv_algorithm_assistance_LP4_1600
528 19:59:52.826129 ============ PULL DRAM RESETB DOWN ============
529 19:59:52.829673 ========== PULL DRAM RESETB DOWN end =========
530 19:59:52.836456 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 19:59:52.839295 ===================================
532 19:59:52.839755 LPDDR4 DRAM CONFIGURATION
533 19:59:52.843263 ===================================
534 19:59:52.846854 EX_ROW_EN[0] = 0x0
535 19:59:52.849600 EX_ROW_EN[1] = 0x0
536 19:59:52.850128 LP4Y_EN = 0x0
537 19:59:52.853208 WORK_FSP = 0x0
538 19:59:52.853735 WL = 0x2
539 19:59:52.856786 RL = 0x2
540 19:59:52.857315 BL = 0x2
541 19:59:52.859334 RPST = 0x0
542 19:59:52.859811 RD_PRE = 0x0
543 19:59:52.863221 WR_PRE = 0x1
544 19:59:52.863815 WR_PST = 0x0
545 19:59:52.866775 DBI_WR = 0x0
546 19:59:52.867300 DBI_RD = 0x0
547 19:59:52.869658 OTF = 0x1
548 19:59:52.872986 ===================================
549 19:59:52.876114 ===================================
550 19:59:52.876544 ANA top config
551 19:59:52.879294 ===================================
552 19:59:52.882508 DLL_ASYNC_EN = 0
553 19:59:52.886160 ALL_SLAVE_EN = 1
554 19:59:52.889201 NEW_RANK_MODE = 1
555 19:59:52.889637 DLL_IDLE_MODE = 1
556 19:59:52.892931 LP45_APHY_COMB_EN = 1
557 19:59:52.896312 TX_ODT_DIS = 1
558 19:59:52.899826 NEW_8X_MODE = 1
559 19:59:52.900261 ===================================
560 19:59:52.903949 ===================================
561 19:59:52.907227 data_rate = 1600
562 19:59:52.910342 CKR = 1
563 19:59:52.914384 DQ_P2S_RATIO = 8
564 19:59:52.917780 ===================================
565 19:59:52.918355 CA_P2S_RATIO = 8
566 19:59:52.921101 DQ_CA_OPEN = 0
567 19:59:52.924888 DQ_SEMI_OPEN = 0
568 19:59:52.928817 CA_SEMI_OPEN = 0
569 19:59:52.929243 CA_FULL_RATE = 0
570 19:59:52.932435 DQ_CKDIV4_EN = 1
571 19:59:52.935981 CA_CKDIV4_EN = 1
572 19:59:52.939970 CA_PREDIV_EN = 0
573 19:59:52.942857 PH8_DLY = 0
574 19:59:52.943328 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 19:59:52.947364 DQ_AAMCK_DIV = 4
576 19:59:52.950851 CA_AAMCK_DIV = 4
577 19:59:52.954146 CA_ADMCK_DIV = 4
578 19:59:52.954647 DQ_TRACK_CA_EN = 0
579 19:59:52.958418 CA_PICK = 800
580 19:59:52.962120 CA_MCKIO = 800
581 19:59:52.965253 MCKIO_SEMI = 0
582 19:59:52.965750 PLL_FREQ = 3068
583 19:59:52.969059 DQ_UI_PI_RATIO = 32
584 19:59:52.972997 CA_UI_PI_RATIO = 0
585 19:59:52.976593 ===================================
586 19:59:52.979887 ===================================
587 19:59:52.980318 memory_type:LPDDR4
588 19:59:52.984073 GP_NUM : 10
589 19:59:52.984614 SRAM_EN : 1
590 19:59:52.987146 MD32_EN : 0
591 19:59:52.990739 ===================================
592 19:59:52.993913 [ANA_INIT] >>>>>>>>>>>>>>
593 19:59:52.996892 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 19:59:53.000152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 19:59:53.004080 ===================================
596 19:59:53.007006 data_rate = 1600,PCW = 0X7600
597 19:59:53.010551 ===================================
598 19:59:53.013654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 19:59:53.017318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 19:59:53.024311 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 19:59:53.027041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 19:59:53.030728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 19:59:53.033848 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 19:59:53.037536 [ANA_INIT] flow start
605 19:59:53.037966 [ANA_INIT] PLL >>>>>>>>
606 19:59:53.041591 [ANA_INIT] PLL <<<<<<<<
607 19:59:53.044971 [ANA_INIT] MIDPI >>>>>>>>
608 19:59:53.045400 [ANA_INIT] MIDPI <<<<<<<<
609 19:59:53.048928 [ANA_INIT] DLL >>>>>>>>
610 19:59:53.049356 [ANA_INIT] flow end
611 19:59:53.056302 ============ LP4 DIFF to SE enter ============
612 19:59:53.059813 ============ LP4 DIFF to SE exit ============
613 19:59:53.060249 [ANA_INIT] <<<<<<<<<<<<<
614 19:59:53.064202 [Flow] Enable top DCM control >>>>>
615 19:59:53.067657 [Flow] Enable top DCM control <<<<<
616 19:59:53.071544 Enable DLL master slave shuffle
617 19:59:53.074730 ==============================================================
618 19:59:53.078034 Gating Mode config
619 19:59:53.082059 ==============================================================
620 19:59:53.085062 Config description:
621 19:59:53.095526 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 19:59:53.101523 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 19:59:53.105357 SELPH_MODE 0: By rank 1: By Phase
624 19:59:53.111715 ==============================================================
625 19:59:53.115599 GAT_TRACK_EN = 1
626 19:59:53.118437 RX_GATING_MODE = 2
627 19:59:53.121806 RX_GATING_TRACK_MODE = 2
628 19:59:53.125170 SELPH_MODE = 1
629 19:59:53.125601 PICG_EARLY_EN = 1
630 19:59:53.128368 VALID_LAT_VALUE = 1
631 19:59:53.135289 ==============================================================
632 19:59:53.138473 Enter into Gating configuration >>>>
633 19:59:53.141825 Exit from Gating configuration <<<<
634 19:59:53.144854 Enter into DVFS_PRE_config >>>>>
635 19:59:53.155349 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 19:59:53.158560 Exit from DVFS_PRE_config <<<<<
637 19:59:53.161969 Enter into PICG configuration >>>>
638 19:59:53.164834 Exit from PICG configuration <<<<
639 19:59:53.168717 [RX_INPUT] configuration >>>>>
640 19:59:53.171834 [RX_INPUT] configuration <<<<<
641 19:59:53.175505 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 19:59:53.181643 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 19:59:53.188682 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 19:59:53.195348 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 19:59:53.201722 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 19:59:53.206050 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 19:59:53.208742 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 19:59:53.212735 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 19:59:53.220590 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 19:59:53.224142 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 19:59:53.227859 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 19:59:53.231319 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 19:59:53.234583 ===================================
654 19:59:53.238961 LPDDR4 DRAM CONFIGURATION
655 19:59:53.239433 ===================================
656 19:59:53.242447 EX_ROW_EN[0] = 0x0
657 19:59:53.242992 EX_ROW_EN[1] = 0x0
658 19:59:53.246594 LP4Y_EN = 0x0
659 19:59:53.247140 WORK_FSP = 0x0
660 19:59:53.249911 WL = 0x2
661 19:59:53.250340 RL = 0x2
662 19:59:53.253917 BL = 0x2
663 19:59:53.254455 RPST = 0x0
664 19:59:53.257012 RD_PRE = 0x0
665 19:59:53.257439 WR_PRE = 0x1
666 19:59:53.261314 WR_PST = 0x0
667 19:59:53.261741 DBI_WR = 0x0
668 19:59:53.264451 DBI_RD = 0x0
669 19:59:53.264912 OTF = 0x1
670 19:59:53.268070 ===================================
671 19:59:53.272010 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 19:59:53.276083 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 19:59:53.279490 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 19:59:53.283524 ===================================
675 19:59:53.287920 LPDDR4 DRAM CONFIGURATION
676 19:59:53.291287 ===================================
677 19:59:53.291879 EX_ROW_EN[0] = 0x10
678 19:59:53.294484 EX_ROW_EN[1] = 0x0
679 19:59:53.294907 LP4Y_EN = 0x0
680 19:59:53.298146 WORK_FSP = 0x0
681 19:59:53.298572 WL = 0x2
682 19:59:53.301775 RL = 0x2
683 19:59:53.302201 BL = 0x2
684 19:59:53.305796 RPST = 0x0
685 19:59:53.306362 RD_PRE = 0x0
686 19:59:53.309517 WR_PRE = 0x1
687 19:59:53.309941 WR_PST = 0x0
688 19:59:53.313115 DBI_WR = 0x0
689 19:59:53.313644 DBI_RD = 0x0
690 19:59:53.316182 OTF = 0x1
691 19:59:53.316607 ===================================
692 19:59:53.323539 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 19:59:53.327714 nWR fixed to 40
694 19:59:53.331286 [ModeRegInit_LP4] CH0 RK0
695 19:59:53.331772 [ModeRegInit_LP4] CH0 RK1
696 19:59:53.335670 [ModeRegInit_LP4] CH1 RK0
697 19:59:53.336111 [ModeRegInit_LP4] CH1 RK1
698 19:59:53.337984 match AC timing 13
699 19:59:53.342389 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 19:59:53.346302 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 19:59:53.353278 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 19:59:53.356392 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 19:59:53.360696 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 19:59:53.363802 [EMI DOE] emi_dcm 0
705 19:59:53.367745 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 19:59:53.368189 ==
707 19:59:53.371214 Dram Type= 6, Freq= 0, CH_0, rank 0
708 19:59:53.375105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 19:59:53.375774 ==
710 19:59:53.378567 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 19:59:53.385603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 19:59:53.395764 [CA 0] Center 38 (7~69) winsize 63
713 19:59:53.399893 [CA 1] Center 37 (7~68) winsize 62
714 19:59:53.403249 [CA 2] Center 35 (5~66) winsize 62
715 19:59:53.407135 [CA 3] Center 35 (5~66) winsize 62
716 19:59:53.411108 [CA 4] Center 34 (4~65) winsize 62
717 19:59:53.411680 [CA 5] Center 34 (4~65) winsize 62
718 19:59:53.412023
719 19:59:53.415068 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 19:59:53.415625
721 19:59:53.418814 [CATrainingPosCal] consider 1 rank data
722 19:59:53.422009 u2DelayCellTimex100 = 270/100 ps
723 19:59:53.425677 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 19:59:53.428948 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 19:59:53.432403 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 19:59:53.436297 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 19:59:53.440157 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 19:59:53.444346 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 19:59:53.444769
730 19:59:53.448500 CA PerBit enable=1, Macro0, CA PI delay=34
731 19:59:53.448922
732 19:59:53.452091 [CBTSetCACLKResult] CA Dly = 34
733 19:59:53.452519 CS Dly: 6 (0~37)
734 19:59:53.452858 ==
735 19:59:53.455746 Dram Type= 6, Freq= 0, CH_0, rank 1
736 19:59:53.459029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 19:59:53.463163 ==
738 19:59:53.466409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 19:59:53.473472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 19:59:53.481832 [CA 0] Center 38 (7~69) winsize 63
741 19:59:53.485410 [CA 1] Center 37 (7~68) winsize 62
742 19:59:53.489233 [CA 2] Center 35 (5~66) winsize 62
743 19:59:53.492281 [CA 3] Center 35 (5~66) winsize 62
744 19:59:53.495453 [CA 4] Center 34 (4~65) winsize 62
745 19:59:53.499076 [CA 5] Center 34 (4~64) winsize 61
746 19:59:53.499564
747 19:59:53.502527 [CmdBusTrainingLP45] Vref(ca) range 1: 30
748 19:59:53.502970
749 19:59:53.506193 [CATrainingPosCal] consider 2 rank data
750 19:59:53.508732 u2DelayCellTimex100 = 270/100 ps
751 19:59:53.511927 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 19:59:53.516133 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 19:59:53.519127 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 19:59:53.522058 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 19:59:53.525641 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 19:59:53.532054 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 19:59:53.532621
758 19:59:53.535465 CA PerBit enable=1, Macro0, CA PI delay=34
759 19:59:53.535897
760 19:59:53.538727 [CBTSetCACLKResult] CA Dly = 34
761 19:59:53.539376 CS Dly: 6 (0~38)
762 19:59:53.539788
763 19:59:53.542378 ----->DramcWriteLeveling(PI) begin...
764 19:59:53.542946 ==
765 19:59:53.545169 Dram Type= 6, Freq= 0, CH_0, rank 0
766 19:59:53.552017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 19:59:53.552484 ==
768 19:59:53.555503 Write leveling (Byte 0): 31 => 31
769 19:59:53.555927 Write leveling (Byte 1): 30 => 30
770 19:59:53.558685 DramcWriteLeveling(PI) end<-----
771 19:59:53.559107
772 19:59:53.559484 ==
773 19:59:53.562641 Dram Type= 6, Freq= 0, CH_0, rank 0
774 19:59:53.569006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 19:59:53.569533 ==
776 19:59:53.572009 [Gating] SW mode calibration
777 19:59:53.579585 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 19:59:53.582927 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 19:59:53.585851 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 19:59:53.592043 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 19:59:53.595854 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 19:59:53.598951 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 19:59:53.605687 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 19:59:53.609234 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 19:59:53.612116 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 19:59:53.619248 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 19:59:53.622649 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 19:59:53.626745 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 19:59:53.630321 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 19:59:53.634208 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 19:59:53.640778 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 19:59:53.643846 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 19:59:53.647786 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 19:59:53.654808 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:59:53.658113 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:59:53.661765 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 19:59:53.664926 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
798 19:59:53.671559 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 19:59:53.675031 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 19:59:53.678778 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 19:59:53.685001 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 19:59:53.688476 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 19:59:53.692027 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 19:59:53.698305 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 19:59:53.701725 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 19:59:53.705210 0 9 12 | B1->B0 | 2727 3131 | 0 1 | (0 0) (1 1)
807 19:59:53.711636 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 19:59:53.715248 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 19:59:53.718487 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 19:59:53.725147 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 19:59:53.728086 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 19:59:53.731279 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 19:59:53.738066 0 10 8 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 0)
814 19:59:53.741661 0 10 12 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
815 19:59:53.744964 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 19:59:53.751280 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 19:59:53.754954 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 19:59:53.758148 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 19:59:53.764463 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 19:59:53.768124 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 19:59:53.771250 0 11 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
822 19:59:53.774891 0 11 12 | B1->B0 | 3434 3c3c | 0 0 | (1 1) (0 0)
823 19:59:53.781416 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 19:59:53.784786 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 19:59:53.787845 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 19:59:53.794929 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 19:59:53.798600 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 19:59:53.801526 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 19:59:53.808245 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 19:59:53.811552 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 19:59:53.815076 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 19:59:53.822200 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 19:59:53.824937 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 19:59:53.828453 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 19:59:53.835170 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 19:59:53.837925 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 19:59:53.841256 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 19:59:53.848114 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 19:59:53.851632 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 19:59:53.855082 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 19:59:53.857989 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 19:59:53.865166 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 19:59:53.867980 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 19:59:53.871474 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 19:59:53.878212 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
846 19:59:53.881530 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 19:59:53.884974 Total UI for P1: 0, mck2ui 16
848 19:59:53.888138 best dqsien dly found for B0: ( 0, 14, 8)
849 19:59:53.891531 Total UI for P1: 0, mck2ui 16
850 19:59:53.895550 best dqsien dly found for B1: ( 0, 14, 8)
851 19:59:53.898486 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 19:59:53.901907 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
853 19:59:53.902453
854 19:59:53.905442 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 19:59:53.908325 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 19:59:53.911799 [Gating] SW calibration Done
857 19:59:53.912342 ==
858 19:59:53.914937 Dram Type= 6, Freq= 0, CH_0, rank 0
859 19:59:53.918626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 19:59:53.919165 ==
861 19:59:53.922211 RX Vref Scan: 0
862 19:59:53.922748
863 19:59:53.925548 RX Vref 0 -> 0, step: 1
864 19:59:53.926084
865 19:59:53.928155 RX Delay -130 -> 252, step: 16
866 19:59:53.931854 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
867 19:59:53.935547 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 19:59:53.938457 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 19:59:53.941711 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 19:59:53.945573 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 19:59:53.951926 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
872 19:59:53.955563 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 19:59:53.958203 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 19:59:53.962044 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 19:59:53.965195 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
876 19:59:53.971951 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 19:59:53.975200 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 19:59:53.979028 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 19:59:53.981447 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 19:59:53.985009 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 19:59:53.991983 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 19:59:53.992509 ==
883 19:59:53.994865 Dram Type= 6, Freq= 0, CH_0, rank 0
884 19:59:53.998194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 19:59:53.998632 ==
886 19:59:53.998974 DQS Delay:
887 19:59:54.001668 DQS0 = 0, DQS1 = 0
888 19:59:54.002269 DQM Delay:
889 19:59:54.004901 DQM0 = 81, DQM1 = 70
890 19:59:54.005328 DQ Delay:
891 19:59:54.008758 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
892 19:59:54.012386 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
893 19:59:54.014897 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
894 19:59:54.018407 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 19:59:54.018931
896 19:59:54.019273
897 19:59:54.019703 ==
898 19:59:54.021777 Dram Type= 6, Freq= 0, CH_0, rank 0
899 19:59:54.025199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 19:59:54.025725 ==
901 19:59:54.028814
902 19:59:54.029391
903 19:59:54.029759 TX Vref Scan disable
904 19:59:54.032120 == TX Byte 0 ==
905 19:59:54.035497 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
906 19:59:54.039117 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
907 19:59:54.041851 == TX Byte 1 ==
908 19:59:54.046141 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
909 19:59:54.049296 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
910 19:59:54.049825 ==
911 19:59:54.052328 Dram Type= 6, Freq= 0, CH_0, rank 0
912 19:59:54.056088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 19:59:54.058787 ==
914 19:59:54.069917 TX Vref=22, minBit 11, minWin=26, winSum=434
915 19:59:54.073655 TX Vref=24, minBit 12, minWin=26, winSum=438
916 19:59:54.076714 TX Vref=26, minBit 0, minWin=27, winSum=440
917 19:59:54.079907 TX Vref=28, minBit 11, minWin=27, winSum=443
918 19:59:54.083494 TX Vref=30, minBit 9, minWin=27, winSum=442
919 19:59:54.090539 TX Vref=32, minBit 12, minWin=26, winSum=440
920 19:59:54.094049 [TxChooseVref] Worse bit 11, Min win 27, Win sum 443, Final Vref 28
921 19:59:54.094581
922 19:59:54.096680 Final TX Range 1 Vref 28
923 19:59:54.097111
924 19:59:54.097452 ==
925 19:59:54.099922 Dram Type= 6, Freq= 0, CH_0, rank 0
926 19:59:54.103735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 19:59:54.107000 ==
928 19:59:54.107574
929 19:59:54.107923
930 19:59:54.108241 TX Vref Scan disable
931 19:59:54.110526 == TX Byte 0 ==
932 19:59:54.113652 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
933 19:59:54.117169 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
934 19:59:54.120781 == TX Byte 1 ==
935 19:59:54.123958 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
936 19:59:54.127030 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
937 19:59:54.130934
938 19:59:54.131501 [DATLAT]
939 19:59:54.131854 Freq=800, CH0 RK0
940 19:59:54.132178
941 19:59:54.134402 DATLAT Default: 0xa
942 19:59:54.134933 0, 0xFFFF, sum = 0
943 19:59:54.137003 1, 0xFFFF, sum = 0
944 19:59:54.137546 2, 0xFFFF, sum = 0
945 19:59:54.140247 3, 0xFFFF, sum = 0
946 19:59:54.140679 4, 0xFFFF, sum = 0
947 19:59:54.143953 5, 0xFFFF, sum = 0
948 19:59:54.144387 6, 0xFFFF, sum = 0
949 19:59:54.147480 7, 0xFFFF, sum = 0
950 19:59:54.150658 8, 0xFFFF, sum = 0
951 19:59:54.151184 9, 0x0, sum = 1
952 19:59:54.151579 10, 0x0, sum = 2
953 19:59:54.154013 11, 0x0, sum = 3
954 19:59:54.154539 12, 0x0, sum = 4
955 19:59:54.157660 best_step = 10
956 19:59:54.158192
957 19:59:54.158536 ==
958 19:59:54.160617 Dram Type= 6, Freq= 0, CH_0, rank 0
959 19:59:54.163423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 19:59:54.163875 ==
961 19:59:54.167327 RX Vref Scan: 1
962 19:59:54.167917
963 19:59:54.168259 Set Vref Range= 32 -> 127
964 19:59:54.168579
965 19:59:54.170586 RX Vref 32 -> 127, step: 1
966 19:59:54.171010
967 19:59:54.173919 RX Delay -111 -> 252, step: 8
968 19:59:54.174440
969 19:59:54.177287 Set Vref, RX VrefLevel [Byte0]: 32
970 19:59:54.180060 [Byte1]: 32
971 19:59:54.180619
972 19:59:54.183673 Set Vref, RX VrefLevel [Byte0]: 33
973 19:59:54.187018 [Byte1]: 33
974 19:59:54.190800
975 19:59:54.191331 Set Vref, RX VrefLevel [Byte0]: 34
976 19:59:54.194239 [Byte1]: 34
977 19:59:54.198833
978 19:59:54.201738 Set Vref, RX VrefLevel [Byte0]: 35
979 19:59:54.202299 [Byte1]: 35
980 19:59:54.205811
981 19:59:54.206250 Set Vref, RX VrefLevel [Byte0]: 36
982 19:59:54.209807 [Byte1]: 36
983 19:59:54.213712
984 19:59:54.214159 Set Vref, RX VrefLevel [Byte0]: 37
985 19:59:54.217506 [Byte1]: 37
986 19:59:54.221777
987 19:59:54.222309 Set Vref, RX VrefLevel [Byte0]: 38
988 19:59:54.224642 [Byte1]: 38
989 19:59:54.229159
990 19:59:54.229874 Set Vref, RX VrefLevel [Byte0]: 39
991 19:59:54.232508 [Byte1]: 39
992 19:59:54.237356
993 19:59:54.237890 Set Vref, RX VrefLevel [Byte0]: 40
994 19:59:54.240257 [Byte1]: 40
995 19:59:54.244749
996 19:59:54.245285 Set Vref, RX VrefLevel [Byte0]: 41
997 19:59:54.248060 [Byte1]: 41
998 19:59:54.252103
999 19:59:54.252653 Set Vref, RX VrefLevel [Byte0]: 42
1000 19:59:54.255582 [Byte1]: 42
1001 19:59:54.259895
1002 19:59:54.260426 Set Vref, RX VrefLevel [Byte0]: 43
1003 19:59:54.263611 [Byte1]: 43
1004 19:59:54.267604
1005 19:59:54.268135 Set Vref, RX VrefLevel [Byte0]: 44
1006 19:59:54.270856 [Byte1]: 44
1007 19:59:54.275205
1008 19:59:54.275789 Set Vref, RX VrefLevel [Byte0]: 45
1009 19:59:54.278211 [Byte1]: 45
1010 19:59:54.283003
1011 19:59:54.283580 Set Vref, RX VrefLevel [Byte0]: 46
1012 19:59:54.286100 [Byte1]: 46
1013 19:59:54.290755
1014 19:59:54.291196 Set Vref, RX VrefLevel [Byte0]: 47
1015 19:59:54.294464 [Byte1]: 47
1016 19:59:54.298696
1017 19:59:54.299137 Set Vref, RX VrefLevel [Byte0]: 48
1018 19:59:54.301720 [Byte1]: 48
1019 19:59:54.305851
1020 19:59:54.306286 Set Vref, RX VrefLevel [Byte0]: 49
1021 19:59:54.309322 [Byte1]: 49
1022 19:59:54.313834
1023 19:59:54.314273 Set Vref, RX VrefLevel [Byte0]: 50
1024 19:59:54.317545 [Byte1]: 50
1025 19:59:54.321030
1026 19:59:54.321554 Set Vref, RX VrefLevel [Byte0]: 51
1027 19:59:54.324067 [Byte1]: 51
1028 19:59:54.328569
1029 19:59:54.329097 Set Vref, RX VrefLevel [Byte0]: 52
1030 19:59:54.331964 [Byte1]: 52
1031 19:59:54.336275
1032 19:59:54.336798 Set Vref, RX VrefLevel [Byte0]: 53
1033 19:59:54.339367 [Byte1]: 53
1034 19:59:54.343513
1035 19:59:54.343941 Set Vref, RX VrefLevel [Byte0]: 54
1036 19:59:54.347197 [Byte1]: 54
1037 19:59:54.351642
1038 19:59:54.352148 Set Vref, RX VrefLevel [Byte0]: 55
1039 19:59:54.354791 [Byte1]: 55
1040 19:59:54.359621
1041 19:59:54.360127 Set Vref, RX VrefLevel [Byte0]: 56
1042 19:59:54.362170 [Byte1]: 56
1043 19:59:54.366716
1044 19:59:54.367249 Set Vref, RX VrefLevel [Byte0]: 57
1045 19:59:54.370257 [Byte1]: 57
1046 19:59:54.374780
1047 19:59:54.375293 Set Vref, RX VrefLevel [Byte0]: 58
1048 19:59:54.377538 [Byte1]: 58
1049 19:59:54.382346
1050 19:59:54.382853 Set Vref, RX VrefLevel [Byte0]: 59
1051 19:59:54.385417 [Byte1]: 59
1052 19:59:54.389886
1053 19:59:54.390393 Set Vref, RX VrefLevel [Byte0]: 60
1054 19:59:54.393033 [Byte1]: 60
1055 19:59:54.397309
1056 19:59:54.397913 Set Vref, RX VrefLevel [Byte0]: 61
1057 19:59:54.400212 [Byte1]: 61
1058 19:59:54.405065
1059 19:59:54.405582 Set Vref, RX VrefLevel [Byte0]: 62
1060 19:59:54.408029 [Byte1]: 62
1061 19:59:54.412668
1062 19:59:54.413086 Set Vref, RX VrefLevel [Byte0]: 63
1063 19:59:54.415973 [Byte1]: 63
1064 19:59:54.420074
1065 19:59:54.420592 Set Vref, RX VrefLevel [Byte0]: 64
1066 19:59:54.423421 [Byte1]: 64
1067 19:59:54.428018
1068 19:59:54.428531 Set Vref, RX VrefLevel [Byte0]: 65
1069 19:59:54.430914 [Byte1]: 65
1070 19:59:54.435333
1071 19:59:54.435803 Set Vref, RX VrefLevel [Byte0]: 66
1072 19:59:54.438860 [Byte1]: 66
1073 19:59:54.442973
1074 19:59:54.443434 Set Vref, RX VrefLevel [Byte0]: 67
1075 19:59:54.446671 [Byte1]: 67
1076 19:59:54.451268
1077 19:59:54.451731 Set Vref, RX VrefLevel [Byte0]: 68
1078 19:59:54.454055 [Byte1]: 68
1079 19:59:54.458717
1080 19:59:54.459225 Set Vref, RX VrefLevel [Byte0]: 69
1081 19:59:54.461603 [Byte1]: 69
1082 19:59:54.465742
1083 19:59:54.466154 Set Vref, RX VrefLevel [Byte0]: 70
1084 19:59:54.469340 [Byte1]: 70
1085 19:59:54.473943
1086 19:59:54.474360 Set Vref, RX VrefLevel [Byte0]: 71
1087 19:59:54.477331 [Byte1]: 71
1088 19:59:54.481364
1089 19:59:54.481783 Set Vref, RX VrefLevel [Byte0]: 72
1090 19:59:54.484524 [Byte1]: 72
1091 19:59:54.489064
1092 19:59:54.489482 Set Vref, RX VrefLevel [Byte0]: 73
1093 19:59:54.492089 [Byte1]: 73
1094 19:59:54.496456
1095 19:59:54.496936 Set Vref, RX VrefLevel [Byte0]: 74
1096 19:59:54.499877 [Byte1]: 74
1097 19:59:54.503918
1098 19:59:54.504337 Set Vref, RX VrefLevel [Byte0]: 75
1099 19:59:54.507838 [Byte1]: 75
1100 19:59:54.512010
1101 19:59:54.512426 Set Vref, RX VrefLevel [Byte0]: 76
1102 19:59:54.514867 [Byte1]: 76
1103 19:59:54.519693
1104 19:59:54.520112 Set Vref, RX VrefLevel [Byte0]: 77
1105 19:59:54.523124 [Byte1]: 77
1106 19:59:54.527521
1107 19:59:54.528059 Set Vref, RX VrefLevel [Byte0]: 78
1108 19:59:54.530924 [Byte1]: 78
1109 19:59:54.535165
1110 19:59:54.535718 Set Vref, RX VrefLevel [Byte0]: 79
1111 19:59:54.538007 [Byte1]: 79
1112 19:59:54.542339
1113 19:59:54.542828 Final RX Vref Byte 0 = 61 to rank0
1114 19:59:54.545774 Final RX Vref Byte 1 = 59 to rank0
1115 19:59:54.549383 Final RX Vref Byte 0 = 61 to rank1
1116 19:59:54.552295 Final RX Vref Byte 1 = 59 to rank1==
1117 19:59:54.555427 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 19:59:54.562622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 19:59:54.563083 ==
1120 19:59:54.563512 DQS Delay:
1121 19:59:54.563989 DQS0 = 0, DQS1 = 0
1122 19:59:54.565918 DQM Delay:
1123 19:59:54.566338 DQM0 = 81, DQM1 = 68
1124 19:59:54.569363 DQ Delay:
1125 19:59:54.572431 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1126 19:59:54.572848 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1127 19:59:54.575616 DQ8 =64, DQ9 =56, DQ10 =68, DQ11 =60
1128 19:59:54.578978 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1129 19:59:54.579433
1130 19:59:54.582768
1131 19:59:54.589236 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1132 19:59:54.592475 CH0 RK0: MR19=606, MR18=2929
1133 19:59:54.599101 CH0_RK0: MR19=0x606, MR18=0x2929, DQSOSC=399, MR23=63, INC=92, DEC=61
1134 19:59:54.599564
1135 19:59:54.602552 ----->DramcWriteLeveling(PI) begin...
1136 19:59:54.602974 ==
1137 19:59:54.605914 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 19:59:54.609297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 19:59:54.609720 ==
1140 19:59:54.612526 Write leveling (Byte 0): 33 => 33
1141 19:59:54.615985 Write leveling (Byte 1): 29 => 29
1142 19:59:54.619239 DramcWriteLeveling(PI) end<-----
1143 19:59:54.619778
1144 19:59:54.620176 ==
1145 19:59:54.622266 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 19:59:54.625814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 19:59:54.626234 ==
1148 19:59:54.629439 [Gating] SW mode calibration
1149 19:59:54.635950 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 19:59:54.642759 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 19:59:54.646606 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 19:59:54.649206 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1153 19:59:54.656000 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1154 19:59:54.659524 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 19:59:54.662892 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 19:59:54.666109 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 19:59:54.673058 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 19:59:54.675910 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 19:59:54.679335 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 19:59:54.686766 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 19:59:54.689187 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 19:59:54.692821 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 19:59:54.699599 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 19:59:54.703011 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 19:59:54.747487 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 19:59:54.748016 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 19:59:54.748361 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 19:59:54.748678 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1169 19:59:54.749315 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1170 19:59:54.749640 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 19:59:54.749994 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 19:59:54.750301 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 19:59:54.750595 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 19:59:54.750884 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 19:59:54.791326 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 19:59:54.792463 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 19:59:54.792895 0 9 8 | B1->B0 | 2424 3131 | 1 1 | (0 0) (0 0)
1178 19:59:54.793227 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1179 19:59:54.793534 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 19:59:54.793828 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 19:59:54.794114 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 19:59:54.794399 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 19:59:54.794680 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 19:59:54.794964 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1185 19:59:54.795750 0 10 8 | B1->B0 | 2f2f 2c2c | 1 1 | (1 1) (1 0)
1186 19:59:54.799364 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 19:59:54.802525 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 19:59:54.809546 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 19:59:54.812549 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 19:59:54.815904 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 19:59:54.822540 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 19:59:54.825923 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
1193 19:59:54.829366 0 11 8 | B1->B0 | 3535 4545 | 0 0 | (1 1) (0 0)
1194 19:59:54.836159 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1195 19:59:54.839300 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 19:59:54.842327 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 19:59:54.848875 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 19:59:54.852393 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 19:59:54.855956 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 19:59:54.862963 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1201 19:59:54.867249 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1202 19:59:54.870437 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 19:59:54.874393 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 19:59:54.877518 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 19:59:54.884089 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 19:59:54.887846 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 19:59:54.891229 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 19:59:54.897606 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 19:59:54.900972 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 19:59:54.904391 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 19:59:54.907526 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 19:59:54.914727 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 19:59:54.917992 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 19:59:54.921259 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 19:59:54.927969 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 19:59:54.931277 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1217 19:59:54.934779 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 19:59:54.938241 Total UI for P1: 0, mck2ui 16
1219 19:59:54.941122 best dqsien dly found for B0: ( 0, 14, 4)
1220 19:59:54.944413 Total UI for P1: 0, mck2ui 16
1221 19:59:54.947571 best dqsien dly found for B1: ( 0, 14, 4)
1222 19:59:54.951157 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1223 19:59:54.954369 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1224 19:59:54.954889
1225 19:59:54.961626 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1226 19:59:54.964772 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1227 19:59:54.965192 [Gating] SW calibration Done
1228 19:59:54.968156 ==
1229 19:59:54.971651 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 19:59:54.974664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 19:59:54.975183 ==
1232 19:59:54.975571 RX Vref Scan: 0
1233 19:59:54.975889
1234 19:59:54.978531 RX Vref 0 -> 0, step: 1
1235 19:59:54.978971
1236 19:59:54.981378 RX Delay -130 -> 252, step: 16
1237 19:59:54.984694 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1238 19:59:54.988341 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1239 19:59:54.991770 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1240 19:59:54.997734 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1241 19:59:55.000959 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1242 19:59:55.004483 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1243 19:59:55.007669 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1244 19:59:55.011556 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1245 19:59:55.018178 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1246 19:59:55.021506 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1247 19:59:55.025014 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1248 19:59:55.028035 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1249 19:59:55.031876 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1250 19:59:55.038035 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1251 19:59:55.041093 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1252 19:59:55.044563 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1253 19:59:55.044984 ==
1254 19:59:55.048217 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 19:59:55.051377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 19:59:55.052128 ==
1257 19:59:55.055260 DQS Delay:
1258 19:59:55.055829 DQS0 = 0, DQS1 = 0
1259 19:59:55.058327 DQM Delay:
1260 19:59:55.058844 DQM0 = 78, DQM1 = 69
1261 19:59:55.059181 DQ Delay:
1262 19:59:55.061371 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1263 19:59:55.064640 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1264 19:59:55.068089 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1265 19:59:55.071021 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1266 19:59:55.071507
1267 19:59:55.071861
1268 19:59:55.074986 ==
1269 19:59:55.075575 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 19:59:55.080964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 19:59:55.081466 ==
1272 19:59:55.081799
1273 19:59:55.082107
1274 19:59:55.084577 TX Vref Scan disable
1275 19:59:55.084996 == TX Byte 0 ==
1276 19:59:55.087878 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1277 19:59:55.094332 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1278 19:59:55.094837 == TX Byte 1 ==
1279 19:59:55.097628 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1280 19:59:55.104737 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1281 19:59:55.105251 ==
1282 19:59:55.108232 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 19:59:55.111288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 19:59:55.111845 ==
1285 19:59:55.124760 TX Vref=22, minBit 0, minWin=27, winSum=434
1286 19:59:55.128349 TX Vref=24, minBit 1, minWin=27, winSum=436
1287 19:59:55.131835 TX Vref=26, minBit 1, minWin=27, winSum=442
1288 19:59:55.134853 TX Vref=28, minBit 2, minWin=27, winSum=441
1289 19:59:55.138403 TX Vref=30, minBit 9, minWin=27, winSum=447
1290 19:59:55.141395 TX Vref=32, minBit 3, minWin=27, winSum=445
1291 19:59:55.147925 [TxChooseVref] Worse bit 9, Min win 27, Win sum 447, Final Vref 30
1292 19:59:55.148351
1293 19:59:55.151330 Final TX Range 1 Vref 30
1294 19:59:55.151808
1295 19:59:55.152202 ==
1296 19:59:55.153952 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 19:59:55.157548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 19:59:55.157631 ==
1299 19:59:55.157695
1300 19:59:55.160742
1301 19:59:55.160899 TX Vref Scan disable
1302 19:59:55.164153 == TX Byte 0 ==
1303 19:59:55.167412 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1304 19:59:55.171010 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1305 19:59:55.174199 == TX Byte 1 ==
1306 19:59:55.178098 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1307 19:59:55.180849 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1308 19:59:55.184359
1309 19:59:55.184556 [DATLAT]
1310 19:59:55.184661 Freq=800, CH0 RK1
1311 19:59:55.184755
1312 19:59:55.187988 DATLAT Default: 0xa
1313 19:59:55.188183 0, 0xFFFF, sum = 0
1314 19:59:55.190731 1, 0xFFFF, sum = 0
1315 19:59:55.190933 2, 0xFFFF, sum = 0
1316 19:59:55.194150 3, 0xFFFF, sum = 0
1317 19:59:55.194301 4, 0xFFFF, sum = 0
1318 19:59:55.197454 5, 0xFFFF, sum = 0
1319 19:59:55.200881 6, 0xFFFF, sum = 0
1320 19:59:55.201053 7, 0xFFFF, sum = 0
1321 19:59:55.204484 8, 0xFFFF, sum = 0
1322 19:59:55.204771 9, 0x0, sum = 1
1323 19:59:55.204940 10, 0x0, sum = 2
1324 19:59:55.207328 11, 0x0, sum = 3
1325 19:59:55.207641 12, 0x0, sum = 4
1326 19:59:55.210992 best_step = 10
1327 19:59:55.211312
1328 19:59:55.211541 ==
1329 19:59:55.214571 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 19:59:55.217933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 19:59:55.218325 ==
1332 19:59:55.221151 RX Vref Scan: 0
1333 19:59:55.221535
1334 19:59:55.221806 RX Vref 0 -> 0, step: 1
1335 19:59:55.222089
1336 19:59:55.224180 RX Delay -111 -> 252, step: 8
1337 19:59:55.231438 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1338 19:59:55.234736 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1339 19:59:55.237687 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1340 19:59:55.241075 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1341 19:59:55.244273 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1342 19:59:55.251781 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1343 19:59:55.254925 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1344 19:59:55.257852 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1345 19:59:55.261334 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1346 19:59:55.264518 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1347 19:59:55.271756 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1348 19:59:55.274967 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1349 19:59:55.278178 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1350 19:59:55.281643 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1351 19:59:55.284766 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1352 19:59:55.291210 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1353 19:59:55.291770 ==
1354 19:59:55.294739 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 19:59:55.298491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 19:59:55.298999 ==
1357 19:59:55.299332 DQS Delay:
1358 19:59:55.301585 DQS0 = 0, DQS1 = 0
1359 19:59:55.302026 DQM Delay:
1360 19:59:55.304741 DQM0 = 78, DQM1 = 71
1361 19:59:55.305150 DQ Delay:
1362 19:59:55.308016 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1363 19:59:55.311868 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1364 19:59:55.314882 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1365 19:59:55.318332 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =80
1366 19:59:55.318843
1367 19:59:55.319174
1368 19:59:55.324712 [DQSOSCAuto] RK1, (LSB)MR18= 0x4924, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1369 19:59:55.328172 CH0 RK1: MR19=606, MR18=4924
1370 19:59:55.334589 CH0_RK1: MR19=0x606, MR18=0x4924, DQSOSC=391, MR23=63, INC=96, DEC=64
1371 19:59:55.338316 [RxdqsGatingPostProcess] freq 800
1372 19:59:55.344710 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 19:59:55.348126 Pre-setting of DQS Precalculation
1374 19:59:55.351290 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 19:59:55.351846 ==
1376 19:59:55.354954 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 19:59:55.358024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 19:59:55.358444 ==
1379 19:59:55.364350 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 19:59:55.370953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 19:59:55.379963 [CA 0] Center 36 (6~67) winsize 62
1382 19:59:55.383023 [CA 1] Center 36 (6~67) winsize 62
1383 19:59:55.386455 [CA 2] Center 34 (5~64) winsize 60
1384 19:59:55.389978 [CA 3] Center 34 (4~64) winsize 61
1385 19:59:55.393239 [CA 4] Center 34 (4~64) winsize 61
1386 19:59:55.396291 [CA 5] Center 34 (4~64) winsize 61
1387 19:59:55.396715
1388 19:59:55.399792 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1389 19:59:55.400312
1390 19:59:55.402963 [CATrainingPosCal] consider 1 rank data
1391 19:59:55.406812 u2DelayCellTimex100 = 270/100 ps
1392 19:59:55.410017 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 19:59:55.413107 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1394 19:59:55.419540 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1395 19:59:55.423516 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1396 19:59:55.426315 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 19:59:55.429694 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 19:59:55.430212
1399 19:59:55.433198 CA PerBit enable=1, Macro0, CA PI delay=34
1400 19:59:55.433715
1401 19:59:55.436568 [CBTSetCACLKResult] CA Dly = 34
1402 19:59:55.437079 CS Dly: 5 (0~36)
1403 19:59:55.437409 ==
1404 19:59:55.439569 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 19:59:55.446564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 19:59:55.447083 ==
1407 19:59:55.449582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 19:59:55.456147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 19:59:55.466429 [CA 0] Center 36 (6~67) winsize 62
1410 19:59:55.469221 [CA 1] Center 36 (6~67) winsize 62
1411 19:59:55.472580 [CA 2] Center 34 (4~65) winsize 62
1412 19:59:55.475604 [CA 3] Center 34 (4~64) winsize 61
1413 19:59:55.479130 [CA 4] Center 34 (4~65) winsize 62
1414 19:59:55.482443 [CA 5] Center 33 (3~64) winsize 62
1415 19:59:55.482955
1416 19:59:55.486297 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1417 19:59:55.486831
1418 19:59:55.489615 [CATrainingPosCal] consider 2 rank data
1419 19:59:55.492331 u2DelayCellTimex100 = 270/100 ps
1420 19:59:55.495905 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 19:59:55.499382 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1422 19:59:55.505655 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1423 19:59:55.509518 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1424 19:59:55.512780 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 19:59:55.516406 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 19:59:55.516913
1427 19:59:55.519705 CA PerBit enable=1, Macro0, CA PI delay=34
1428 19:59:55.520234
1429 19:59:55.523135 [CBTSetCACLKResult] CA Dly = 34
1430 19:59:55.523692 CS Dly: 5 (0~37)
1431 19:59:55.524030
1432 19:59:55.526767 ----->DramcWriteLeveling(PI) begin...
1433 19:59:55.527186 ==
1434 19:59:55.530551 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 19:59:55.534294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 19:59:55.534812 ==
1437 19:59:55.538345 Write leveling (Byte 0): 28 => 28
1438 19:59:55.541417 Write leveling (Byte 1): 29 => 29
1439 19:59:55.545000 DramcWriteLeveling(PI) end<-----
1440 19:59:55.545461
1441 19:59:55.545794 ==
1442 19:59:55.549014 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 19:59:55.552104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 19:59:55.552521 ==
1445 19:59:55.555899 [Gating] SW mode calibration
1446 19:59:55.562779 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 19:59:55.566725 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 19:59:55.572882 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 19:59:55.576603 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1450 19:59:55.579526 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1451 19:59:55.585894 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 19:59:55.589724 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 19:59:55.592903 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 19:59:55.599257 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 19:59:55.602692 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 19:59:55.606016 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 19:59:55.613037 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 19:59:55.616000 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 19:59:55.619229 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 19:59:55.626768 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 19:59:55.629193 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 19:59:55.633124 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 19:59:55.635888 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 19:59:55.642398 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 19:59:55.646112 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 19:59:55.649441 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1467 19:59:55.655891 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 19:59:55.659329 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 19:59:55.662255 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 19:59:55.669000 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 19:59:55.672737 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 19:59:55.675988 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 19:59:55.682716 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 19:59:55.685904 0 9 8 | B1->B0 | 2626 2323 | 1 1 | (1 1) (1 1)
1475 19:59:55.689191 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 19:59:55.695857 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 19:59:55.699131 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 19:59:55.702352 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 19:59:55.709573 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 19:59:55.712957 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 19:59:55.716014 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 19:59:55.719631 0 10 8 | B1->B0 | 2c2c 2929 | 0 0 | (1 1) (0 0)
1483 19:59:55.726179 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1484 19:59:55.729515 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 19:59:55.732716 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 19:59:55.739486 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 19:59:55.742658 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 19:59:55.745801 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 19:59:55.752292 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1490 19:59:55.755848 0 11 8 | B1->B0 | 3636 3838 | 0 0 | (0 0) (0 0)
1491 19:59:55.759366 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 19:59:55.766362 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 19:59:55.769609 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 19:59:55.772317 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 19:59:55.779256 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 19:59:55.782553 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 19:59:55.786166 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 19:59:55.792548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1499 19:59:55.796076 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 19:59:55.799224 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 19:59:55.806083 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 19:59:55.809408 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 19:59:55.812279 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 19:59:55.819324 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 19:59:55.823168 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 19:59:55.826195 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 19:59:55.829460 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 19:59:55.836320 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 19:59:55.839539 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 19:59:55.842556 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 19:59:55.849333 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 19:59:55.852384 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 19:59:55.856172 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 19:59:55.862754 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1515 19:59:55.866044 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 19:59:55.869334 Total UI for P1: 0, mck2ui 16
1517 19:59:55.872323 best dqsien dly found for B0: ( 0, 14, 8)
1518 19:59:55.875879 Total UI for P1: 0, mck2ui 16
1519 19:59:55.879732 best dqsien dly found for B1: ( 0, 14, 10)
1520 19:59:55.882515 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1521 19:59:55.885762 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1522 19:59:55.886284
1523 19:59:55.889319 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1524 19:59:55.892649 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1525 19:59:55.895978 [Gating] SW calibration Done
1526 19:59:55.896484 ==
1527 19:59:55.899567 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 19:59:55.903022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 19:59:55.905809 ==
1530 19:59:55.906320 RX Vref Scan: 0
1531 19:59:55.906650
1532 19:59:55.909009 RX Vref 0 -> 0, step: 1
1533 19:59:55.909421
1534 19:59:55.912635 RX Delay -130 -> 252, step: 16
1535 19:59:55.916298 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1536 19:59:55.919604 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1537 19:59:55.923172 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1538 19:59:55.926155 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1539 19:59:55.930004 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1540 19:59:55.936180 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1541 19:59:55.939659 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1542 19:59:55.943073 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1543 19:59:55.946350 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1544 19:59:55.949657 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1545 19:59:55.956342 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1546 19:59:55.959844 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1547 19:59:55.962896 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1548 19:59:55.966133 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1549 19:59:55.969235 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1550 19:59:55.976200 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1551 19:59:55.976617 ==
1552 19:59:55.979493 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 19:59:55.982603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 19:59:55.983020 ==
1555 19:59:55.983345 DQS Delay:
1556 19:59:55.986242 DQS0 = 0, DQS1 = 0
1557 19:59:55.986748 DQM Delay:
1558 19:59:55.989677 DQM0 = 82, DQM1 = 75
1559 19:59:55.990186 DQ Delay:
1560 19:59:55.992555 DQ0 =85, DQ1 =85, DQ2 =61, DQ3 =77
1561 19:59:55.995988 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1562 19:59:55.999427 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1563 19:59:56.002835 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1564 19:59:56.003281
1565 19:59:56.003725
1566 19:59:56.004087 ==
1567 19:59:56.005781 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 19:59:56.009134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 19:59:56.009577 ==
1570 19:59:56.012457
1571 19:59:56.012863
1572 19:59:56.013189 TX Vref Scan disable
1573 19:59:56.015769 == TX Byte 0 ==
1574 19:59:56.019548 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1575 19:59:56.022963 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1576 19:59:56.025712 == TX Byte 1 ==
1577 19:59:56.029156 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1578 19:59:56.032915 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1579 19:59:56.033440 ==
1580 19:59:56.036133 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 19:59:56.042578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 19:59:56.043077 ==
1583 19:59:56.054653 TX Vref=22, minBit 1, minWin=26, winSum=439
1584 19:59:56.058329 TX Vref=24, minBit 1, minWin=27, winSum=440
1585 19:59:56.060934 TX Vref=26, minBit 1, minWin=27, winSum=443
1586 19:59:56.064589 TX Vref=28, minBit 5, minWin=27, winSum=446
1587 19:59:56.068174 TX Vref=30, minBit 5, minWin=27, winSum=448
1588 19:59:56.071264 TX Vref=32, minBit 5, minWin=27, winSum=447
1589 19:59:56.077640 [TxChooseVref] Worse bit 5, Min win 27, Win sum 448, Final Vref 30
1590 19:59:56.078137
1591 19:59:56.081015 Final TX Range 1 Vref 30
1592 19:59:56.081525
1593 19:59:56.081859 ==
1594 19:59:56.084524 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 19:59:56.087805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 19:59:56.088223 ==
1597 19:59:56.088550
1598 19:59:56.088852
1599 19:59:56.091069 TX Vref Scan disable
1600 19:59:56.094765 == TX Byte 0 ==
1601 19:59:56.098355 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1602 19:59:56.102430 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1603 19:59:56.105557 == TX Byte 1 ==
1604 19:59:56.108569 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1605 19:59:56.112260 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1606 19:59:56.112772
1607 19:59:56.115973 [DATLAT]
1608 19:59:56.116478 Freq=800, CH1 RK0
1609 19:59:56.116807
1610 19:59:56.118606 DATLAT Default: 0xa
1611 19:59:56.119017 0, 0xFFFF, sum = 0
1612 19:59:56.121830 1, 0xFFFF, sum = 0
1613 19:59:56.122247 2, 0xFFFF, sum = 0
1614 19:59:56.125348 3, 0xFFFF, sum = 0
1615 19:59:56.125860 4, 0xFFFF, sum = 0
1616 19:59:56.129111 5, 0xFFFF, sum = 0
1617 19:59:56.129623 6, 0xFFFF, sum = 0
1618 19:59:56.132226 7, 0xFFFF, sum = 0
1619 19:59:56.132644 8, 0xFFFF, sum = 0
1620 19:59:56.135167 9, 0x0, sum = 1
1621 19:59:56.135637 10, 0x0, sum = 2
1622 19:59:56.138718 11, 0x0, sum = 3
1623 19:59:56.139238 12, 0x0, sum = 4
1624 19:59:56.141902 best_step = 10
1625 19:59:56.142418
1626 19:59:56.142800 ==
1627 19:59:56.145242 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 19:59:56.148432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 19:59:56.148947 ==
1630 19:59:56.149283 RX Vref Scan: 1
1631 19:59:56.149591
1632 19:59:56.152104 Set Vref Range= 32 -> 127
1633 19:59:56.152530
1634 19:59:56.155234 RX Vref 32 -> 127, step: 1
1635 19:59:56.155686
1636 19:59:56.158675 RX Delay -111 -> 252, step: 8
1637 19:59:56.159089
1638 19:59:56.162472 Set Vref, RX VrefLevel [Byte0]: 32
1639 19:59:56.165635 [Byte1]: 32
1640 19:59:56.166052
1641 19:59:56.168900 Set Vref, RX VrefLevel [Byte0]: 33
1642 19:59:56.172212 [Byte1]: 33
1643 19:59:56.172712
1644 19:59:56.175558 Set Vref, RX VrefLevel [Byte0]: 34
1645 19:59:56.179049 [Byte1]: 34
1646 19:59:56.182082
1647 19:59:56.182491 Set Vref, RX VrefLevel [Byte0]: 35
1648 19:59:56.185843 [Byte1]: 35
1649 19:59:56.190645
1650 19:59:56.191157 Set Vref, RX VrefLevel [Byte0]: 36
1651 19:59:56.193486 [Byte1]: 36
1652 19:59:56.197648
1653 19:59:56.198157 Set Vref, RX VrefLevel [Byte0]: 37
1654 19:59:56.201237 [Byte1]: 37
1655 19:59:56.205167
1656 19:59:56.205579 Set Vref, RX VrefLevel [Byte0]: 38
1657 19:59:56.208936 [Byte1]: 38
1658 19:59:56.213248
1659 19:59:56.213755 Set Vref, RX VrefLevel [Byte0]: 39
1660 19:59:56.216714 [Byte1]: 39
1661 19:59:56.221162
1662 19:59:56.221681 Set Vref, RX VrefLevel [Byte0]: 40
1663 19:59:56.223784 [Byte1]: 40
1664 19:59:56.228113
1665 19:59:56.228546 Set Vref, RX VrefLevel [Byte0]: 41
1666 19:59:56.231760 [Byte1]: 41
1667 19:59:56.236113
1668 19:59:56.236627 Set Vref, RX VrefLevel [Byte0]: 42
1669 19:59:56.239563 [Byte1]: 42
1670 19:59:56.243847
1671 19:59:56.244357 Set Vref, RX VrefLevel [Byte0]: 43
1672 19:59:56.247148 [Byte1]: 43
1673 19:59:56.251303
1674 19:59:56.251856 Set Vref, RX VrefLevel [Byte0]: 44
1675 19:59:56.254657 [Byte1]: 44
1676 19:59:56.259137
1677 19:59:56.259707 Set Vref, RX VrefLevel [Byte0]: 45
1678 19:59:56.262658 [Byte1]: 45
1679 19:59:56.267246
1680 19:59:56.267806 Set Vref, RX VrefLevel [Byte0]: 46
1681 19:59:56.270171 [Byte1]: 46
1682 19:59:56.274461
1683 19:59:56.274971 Set Vref, RX VrefLevel [Byte0]: 47
1684 19:59:56.277498 [Byte1]: 47
1685 19:59:56.281955
1686 19:59:56.282469 Set Vref, RX VrefLevel [Byte0]: 48
1687 19:59:56.285512 [Byte1]: 48
1688 19:59:56.289838
1689 19:59:56.290344 Set Vref, RX VrefLevel [Byte0]: 49
1690 19:59:56.293204 [Byte1]: 49
1691 19:59:56.297167
1692 19:59:56.297580 Set Vref, RX VrefLevel [Byte0]: 50
1693 19:59:56.300375 [Byte1]: 50
1694 19:59:56.304988
1695 19:59:56.305493 Set Vref, RX VrefLevel [Byte0]: 51
1696 19:59:56.308248 [Byte1]: 51
1697 19:59:56.312574
1698 19:59:56.313087 Set Vref, RX VrefLevel [Byte0]: 52
1699 19:59:56.316038 [Byte1]: 52
1700 19:59:56.320426
1701 19:59:56.320937 Set Vref, RX VrefLevel [Byte0]: 53
1702 19:59:56.323770 [Byte1]: 53
1703 19:59:56.328347
1704 19:59:56.328854 Set Vref, RX VrefLevel [Byte0]: 54
1705 19:59:56.331382 [Byte1]: 54
1706 19:59:56.335301
1707 19:59:56.335842 Set Vref, RX VrefLevel [Byte0]: 55
1708 19:59:56.338883 [Byte1]: 55
1709 19:59:56.343062
1710 19:59:56.343632 Set Vref, RX VrefLevel [Byte0]: 56
1711 19:59:56.346590 [Byte1]: 56
1712 19:59:56.351163
1713 19:59:56.351730 Set Vref, RX VrefLevel [Byte0]: 57
1714 19:59:56.354032 [Byte1]: 57
1715 19:59:56.358425
1716 19:59:56.358973 Set Vref, RX VrefLevel [Byte0]: 58
1717 19:59:56.361890 [Byte1]: 58
1718 19:59:56.366097
1719 19:59:56.366608 Set Vref, RX VrefLevel [Byte0]: 59
1720 19:59:56.369305 [Byte1]: 59
1721 19:59:56.373532
1722 19:59:56.373984 Set Vref, RX VrefLevel [Byte0]: 60
1723 19:59:56.376565 [Byte1]: 60
1724 19:59:56.381177
1725 19:59:56.381586 Set Vref, RX VrefLevel [Byte0]: 61
1726 19:59:56.384597 [Byte1]: 61
1727 19:59:56.389575
1728 19:59:56.390106 Set Vref, RX VrefLevel [Byte0]: 62
1729 19:59:56.392035 [Byte1]: 62
1730 19:59:56.396451
1731 19:59:56.396970 Set Vref, RX VrefLevel [Byte0]: 63
1732 19:59:56.399627 [Byte1]: 63
1733 19:59:56.404266
1734 19:59:56.404772 Set Vref, RX VrefLevel [Byte0]: 64
1735 19:59:56.407232 [Byte1]: 64
1736 19:59:56.411976
1737 19:59:56.412390 Set Vref, RX VrefLevel [Byte0]: 65
1738 19:59:56.416063 [Byte1]: 65
1739 19:59:56.419860
1740 19:59:56.420366 Set Vref, RX VrefLevel [Byte0]: 66
1741 19:59:56.422786 [Byte1]: 66
1742 19:59:56.427224
1743 19:59:56.427807 Set Vref, RX VrefLevel [Byte0]: 67
1744 19:59:56.430231 [Byte1]: 67
1745 19:59:56.435163
1746 19:59:56.435728 Set Vref, RX VrefLevel [Byte0]: 68
1747 19:59:56.438184 [Byte1]: 68
1748 19:59:56.442599
1749 19:59:56.445405 Set Vref, RX VrefLevel [Byte0]: 69
1750 19:59:56.448942 [Byte1]: 69
1751 19:59:56.449449
1752 19:59:56.452151 Set Vref, RX VrefLevel [Byte0]: 70
1753 19:59:56.455561 [Byte1]: 70
1754 19:59:56.455973
1755 19:59:56.459317 Set Vref, RX VrefLevel [Byte0]: 71
1756 19:59:56.462469 [Byte1]: 71
1757 19:59:56.462978
1758 19:59:56.465932 Set Vref, RX VrefLevel [Byte0]: 72
1759 19:59:56.469106 [Byte1]: 72
1760 19:59:56.473145
1761 19:59:56.473558 Set Vref, RX VrefLevel [Byte0]: 73
1762 19:59:56.476353 [Byte1]: 73
1763 19:59:56.480493
1764 19:59:56.480904 Set Vref, RX VrefLevel [Byte0]: 74
1765 19:59:56.483965 [Byte1]: 74
1766 19:59:56.488601
1767 19:59:56.489016 Final RX Vref Byte 0 = 60 to rank0
1768 19:59:56.491291 Final RX Vref Byte 1 = 61 to rank0
1769 19:59:56.494890 Final RX Vref Byte 0 = 60 to rank1
1770 19:59:56.498639 Final RX Vref Byte 1 = 61 to rank1==
1771 19:59:56.501922 Dram Type= 6, Freq= 0, CH_1, rank 0
1772 19:59:56.508674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1773 19:59:56.509187 ==
1774 19:59:56.509517 DQS Delay:
1775 19:59:56.509823 DQS0 = 0, DQS1 = 0
1776 19:59:56.511697 DQM Delay:
1777 19:59:56.512110 DQM0 = 81, DQM1 = 70
1778 19:59:56.515836 DQ Delay:
1779 19:59:56.518525 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1780 19:59:56.519215 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1781 19:59:56.521927 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1782 19:59:56.525519 DQ12 =76, DQ13 =76, DQ14 =76, DQ15 =76
1783 19:59:56.527958
1784 19:59:56.528365
1785 19:59:56.535063 [DQSOSCAuto] RK0, (LSB)MR18= 0xd18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1786 19:59:56.538635 CH1 RK0: MR19=606, MR18=D18
1787 19:59:56.545750 CH1_RK0: MR19=0x606, MR18=0xD18, DQSOSC=403, MR23=63, INC=90, DEC=60
1788 19:59:56.546264
1789 19:59:56.548389 ----->DramcWriteLeveling(PI) begin...
1790 19:59:56.548804 ==
1791 19:59:56.552137 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 19:59:56.555369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 19:59:56.555830 ==
1794 19:59:56.558310 Write leveling (Byte 0): 26 => 26
1795 19:59:56.561978 Write leveling (Byte 1): 31 => 31
1796 19:59:56.565121 DramcWriteLeveling(PI) end<-----
1797 19:59:56.565638
1798 19:59:56.566040 ==
1799 19:59:56.568449 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 19:59:56.571586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 19:59:56.572096 ==
1802 19:59:56.575038 [Gating] SW mode calibration
1803 19:59:56.581646 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1804 19:59:56.588351 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1805 19:59:56.591888 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1806 19:59:56.595197 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1807 19:59:56.601567 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1808 19:59:56.605399 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 19:59:56.608266 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 19:59:56.611571 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 19:59:56.618663 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 19:59:56.621903 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 19:59:56.625587 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 19:59:56.632062 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 19:59:56.635652 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 19:59:56.639120 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 19:59:56.645397 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 19:59:56.648321 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 19:59:56.651609 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 19:59:56.658590 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 19:59:56.661925 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1822 19:59:56.665401 0 8 4 | B1->B0 | 2323 2322 | 0 1 | (0 1) (1 0)
1823 19:59:56.672055 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1824 19:59:56.675173 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 19:59:56.678554 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 19:59:56.685737 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 19:59:56.688523 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 19:59:56.691634 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 19:59:56.698422 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 19:59:56.701349 0 9 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1831 19:59:56.705029 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1832 19:59:56.712018 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 19:59:56.715233 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 19:59:56.718717 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 19:59:56.721699 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 19:59:56.728298 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 19:59:56.731892 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1838 19:59:56.734833 0 10 4 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (0 1)
1839 19:59:56.742074 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
1840 19:59:56.745656 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 19:59:56.748251 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 19:59:56.754729 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 19:59:56.758273 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 19:59:56.761978 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 19:59:56.768018 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1846 19:59:56.771140 0 11 4 | B1->B0 | 2b2b 3a3a | 1 0 | (0 0) (0 0)
1847 19:59:56.775349 0 11 8 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
1848 19:59:56.781834 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 19:59:56.785098 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 19:59:56.787981 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 19:59:56.795264 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 19:59:56.797958 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 19:59:56.801291 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 19:59:56.808107 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1855 19:59:56.811372 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1856 19:59:56.814661 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 19:59:56.821478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 19:59:56.824524 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 19:59:56.828612 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 19:59:56.831495 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 19:59:56.838130 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 19:59:56.841215 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 19:59:56.844623 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 19:59:56.851180 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 19:59:56.854675 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 19:59:56.857741 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 19:59:56.864861 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 19:59:56.868119 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 19:59:56.872074 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 19:59:56.877811 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1871 19:59:56.881856 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1872 19:59:56.884665 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 19:59:56.888067 Total UI for P1: 0, mck2ui 16
1874 19:59:56.891815 best dqsien dly found for B0: ( 0, 14, 6)
1875 19:59:56.895360 Total UI for P1: 0, mck2ui 16
1876 19:59:56.898363 best dqsien dly found for B1: ( 0, 14, 8)
1877 19:59:56.901773 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1878 19:59:56.904618 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1879 19:59:56.905086
1880 19:59:56.911212 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1881 19:59:56.914682 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1882 19:59:56.915191 [Gating] SW calibration Done
1883 19:59:56.918359 ==
1884 19:59:56.918865 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 19:59:56.925198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 19:59:56.925709 ==
1887 19:59:56.926046 RX Vref Scan: 0
1888 19:59:56.926354
1889 19:59:56.927728 RX Vref 0 -> 0, step: 1
1890 19:59:56.928139
1891 19:59:56.931174 RX Delay -130 -> 252, step: 16
1892 19:59:56.934593 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1893 19:59:56.937954 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1894 19:59:56.941837 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1895 19:59:56.947672 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1896 19:59:56.951533 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1897 19:59:56.954476 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1898 19:59:56.958225 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1899 19:59:56.961834 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1900 19:59:56.968003 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1901 19:59:56.970933 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1902 19:59:56.974742 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1903 19:59:56.978224 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1904 19:59:56.981337 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1905 19:59:56.988315 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1906 19:59:56.991717 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1907 19:59:56.995530 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1908 19:59:56.996045 ==
1909 19:59:56.998441 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 19:59:57.001483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 19:59:57.002049 ==
1912 19:59:57.004699 DQS Delay:
1913 19:59:57.005114 DQS0 = 0, DQS1 = 0
1914 19:59:57.008393 DQM Delay:
1915 19:59:57.008901 DQM0 = 77, DQM1 = 72
1916 19:59:57.009237 DQ Delay:
1917 19:59:57.011172 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1918 19:59:57.015245 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1919 19:59:57.017891 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1920 19:59:57.021659 DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77
1921 19:59:57.022173
1922 19:59:57.022504
1923 19:59:57.024967 ==
1924 19:59:57.025480 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 19:59:57.031465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 19:59:57.031984 ==
1927 19:59:57.032321
1928 19:59:57.032650
1929 19:59:57.034628 TX Vref Scan disable
1930 19:59:57.035144 == TX Byte 0 ==
1931 19:59:57.038377 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1932 19:59:57.044701 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1933 19:59:57.045421 == TX Byte 1 ==
1934 19:59:57.048119 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1935 19:59:57.054357 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1936 19:59:57.054919 ==
1937 19:59:57.057599 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 19:59:57.061296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 19:59:57.061806 ==
1940 19:59:57.075180 TX Vref=22, minBit 5, minWin=27, winSum=452
1941 19:59:57.078027 TX Vref=24, minBit 1, minWin=28, winSum=454
1942 19:59:57.081354 TX Vref=26, minBit 0, minWin=28, winSum=454
1943 19:59:57.084704 TX Vref=28, minBit 1, minWin=28, winSum=461
1944 19:59:57.088355 TX Vref=30, minBit 1, minWin=28, winSum=462
1945 19:59:57.091462 TX Vref=32, minBit 5, minWin=27, winSum=461
1946 19:59:57.098606 [TxChooseVref] Worse bit 1, Min win 28, Win sum 462, Final Vref 30
1947 19:59:57.099158
1948 19:59:57.101826 Final TX Range 1 Vref 30
1949 19:59:57.102381
1950 19:59:57.102708 ==
1951 19:59:57.104726 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 19:59:57.107949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 19:59:57.108370 ==
1954 19:59:57.108701
1955 19:59:57.111994
1956 19:59:57.112499 TX Vref Scan disable
1957 19:59:57.114868 == TX Byte 0 ==
1958 19:59:57.118072 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1959 19:59:57.121418 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1960 19:59:57.124654 == TX Byte 1 ==
1961 19:59:57.128288 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1962 19:59:57.131782 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1963 19:59:57.134670
1964 19:59:57.135175 [DATLAT]
1965 19:59:57.135535 Freq=800, CH1 RK1
1966 19:59:57.135851
1967 19:59:57.138384 DATLAT Default: 0xa
1968 19:59:57.138893 0, 0xFFFF, sum = 0
1969 19:59:57.141617 1, 0xFFFF, sum = 0
1970 19:59:57.142039 2, 0xFFFF, sum = 0
1971 19:59:57.144495 3, 0xFFFF, sum = 0
1972 19:59:57.144934 4, 0xFFFF, sum = 0
1973 19:59:57.148191 5, 0xFFFF, sum = 0
1974 19:59:57.151486 6, 0xFFFF, sum = 0
1975 19:59:57.152059 7, 0xFFFF, sum = 0
1976 19:59:57.154639 8, 0xFFFF, sum = 0
1977 19:59:57.155081 9, 0x0, sum = 1
1978 19:59:57.155450 10, 0x0, sum = 2
1979 19:59:57.157885 11, 0x0, sum = 3
1980 19:59:57.158449 12, 0x0, sum = 4
1981 19:59:57.161029 best_step = 10
1982 19:59:57.161445
1983 19:59:57.161772 ==
1984 19:59:57.164776 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 19:59:57.168349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 19:59:57.168772 ==
1987 19:59:57.171224 RX Vref Scan: 0
1988 19:59:57.171667
1989 19:59:57.171995 RX Vref 0 -> 0, step: 1
1990 19:59:57.172304
1991 19:59:57.174569 RX Delay -111 -> 252, step: 8
1992 19:59:57.181262 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
1993 19:59:57.184643 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1994 19:59:57.188302 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1995 19:59:57.192095 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1996 19:59:57.195665 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1997 19:59:57.201838 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1998 19:59:57.204894 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1999 19:59:57.208050 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2000 19:59:57.211558 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2001 19:59:57.214899 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2002 19:59:57.221851 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2003 19:59:57.224949 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2004 19:59:57.228638 iDelay=209, Bit 12, Center 84 (-39 ~ 208) 248
2005 19:59:57.231586 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2006 19:59:57.235521 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2007 19:59:57.242079 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2008 19:59:57.242609 ==
2009 19:59:57.244617 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 19:59:57.248339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 19:59:57.248887 ==
2012 19:59:57.249410 DQS Delay:
2013 19:59:57.251487 DQS0 = 0, DQS1 = 0
2014 19:59:57.251914 DQM Delay:
2015 19:59:57.254990 DQM0 = 78, DQM1 = 74
2016 19:59:57.255459 DQ Delay:
2017 19:59:57.258061 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2018 19:59:57.261303 DQ4 =76, DQ5 =88, DQ6 =92, DQ7 =76
2019 19:59:57.265016 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2020 19:59:57.268551 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2021 19:59:57.269084
2022 19:59:57.269537
2023 19:59:57.275031 [DQSOSCAuto] RK1, (LSB)MR18= 0x263d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2024 19:59:57.278034 CH1 RK1: MR19=606, MR18=263D
2025 19:59:57.285080 CH1_RK1: MR19=0x606, MR18=0x263D, DQSOSC=394, MR23=63, INC=95, DEC=63
2026 19:59:57.288563 [RxdqsGatingPostProcess] freq 800
2027 19:59:57.295089 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2028 19:59:57.298580 Pre-setting of DQS Precalculation
2029 19:59:57.302095 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2030 19:59:57.308501 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2031 19:59:57.315204 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2032 19:59:57.315771
2033 19:59:57.316219
2034 19:59:57.318500 [Calibration Summary] 1600 Mbps
2035 19:59:57.321627 CH 0, Rank 0
2036 19:59:57.322160 SW Impedance : PASS
2037 19:59:57.325025 DUTY Scan : NO K
2038 19:59:57.328607 ZQ Calibration : PASS
2039 19:59:57.329027 Jitter Meter : NO K
2040 19:59:57.331970 CBT Training : PASS
2041 19:59:57.332383 Write leveling : PASS
2042 19:59:57.334967 RX DQS gating : PASS
2043 19:59:57.339055 RX DQ/DQS(RDDQC) : PASS
2044 19:59:57.339623 TX DQ/DQS : PASS
2045 19:59:57.341778 RX DATLAT : PASS
2046 19:59:57.345104 RX DQ/DQS(Engine): PASS
2047 19:59:57.345521 TX OE : NO K
2048 19:59:57.348074 All Pass.
2049 19:59:57.348486
2050 19:59:57.348810 CH 0, Rank 1
2051 19:59:57.351572 SW Impedance : PASS
2052 19:59:57.351987 DUTY Scan : NO K
2053 19:59:57.355158 ZQ Calibration : PASS
2054 19:59:57.358642 Jitter Meter : NO K
2055 19:59:57.359080 CBT Training : PASS
2056 19:59:57.361500 Write leveling : PASS
2057 19:59:57.365571 RX DQS gating : PASS
2058 19:59:57.366104 RX DQ/DQS(RDDQC) : PASS
2059 19:59:57.368591 TX DQ/DQS : PASS
2060 19:59:57.371587 RX DATLAT : PASS
2061 19:59:57.372002 RX DQ/DQS(Engine): PASS
2062 19:59:57.375209 TX OE : NO K
2063 19:59:57.375800 All Pass.
2064 19:59:57.376138
2065 19:59:57.378281 CH 1, Rank 0
2066 19:59:57.378690 SW Impedance : PASS
2067 19:59:57.381596 DUTY Scan : NO K
2068 19:59:57.382008 ZQ Calibration : PASS
2069 19:59:57.385156 Jitter Meter : NO K
2070 19:59:57.388310 CBT Training : PASS
2071 19:59:57.388771 Write leveling : PASS
2072 19:59:57.391707 RX DQS gating : PASS
2073 19:59:57.394755 RX DQ/DQS(RDDQC) : PASS
2074 19:59:57.395164 TX DQ/DQS : PASS
2075 19:59:57.398278 RX DATLAT : PASS
2076 19:59:57.401568 RX DQ/DQS(Engine): PASS
2077 19:59:57.401979 TX OE : NO K
2078 19:59:57.405026 All Pass.
2079 19:59:57.405438
2080 19:59:57.405773 CH 1, Rank 1
2081 19:59:57.408064 SW Impedance : PASS
2082 19:59:57.408476 DUTY Scan : NO K
2083 19:59:57.411779 ZQ Calibration : PASS
2084 19:59:57.415446 Jitter Meter : NO K
2085 19:59:57.415973 CBT Training : PASS
2086 19:59:57.418491 Write leveling : PASS
2087 19:59:57.421539 RX DQS gating : PASS
2088 19:59:57.421952 RX DQ/DQS(RDDQC) : PASS
2089 19:59:57.425551 TX DQ/DQS : PASS
2090 19:59:57.426084 RX DATLAT : PASS
2091 19:59:57.428843 RX DQ/DQS(Engine): PASS
2092 19:59:57.432177 TX OE : NO K
2093 19:59:57.432703 All Pass.
2094 19:59:57.433033
2095 19:59:57.434898 DramC Write-DBI off
2096 19:59:57.435359 PER_BANK_REFRESH: Hybrid Mode
2097 19:59:57.438522 TX_TRACKING: ON
2098 19:59:57.442271 [GetDramInforAfterCalByMRR] Vendor 6.
2099 19:59:57.444917 [GetDramInforAfterCalByMRR] Revision 606.
2100 19:59:57.448339 [GetDramInforAfterCalByMRR] Revision 2 0.
2101 19:59:57.448937 MR0 0x3b3b
2102 19:59:57.451683 MR8 0x5151
2103 19:59:57.454936 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 19:59:57.455369
2105 19:59:57.455739 MR0 0x3b3b
2106 19:59:57.458284 MR8 0x5151
2107 19:59:57.461815 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 19:59:57.462356
2109 19:59:57.468226 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2110 19:59:57.471589 [FAST_K] Save calibration result to emmc
2111 19:59:57.478666 [FAST_K] Save calibration result to emmc
2112 19:59:57.479216 dram_init: config_dvfs: 1
2113 19:59:57.482069 dramc_set_vcore_voltage set vcore to 662500
2114 19:59:57.484501 Read voltage for 1200, 2
2115 19:59:57.484950 Vio18 = 0
2116 19:59:57.488186 Vcore = 662500
2117 19:59:57.488710 Vdram = 0
2118 19:59:57.489065 Vddq = 0
2119 19:59:57.491676 Vmddr = 0
2120 19:59:57.495225 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2121 19:59:57.501829 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2122 19:59:57.502340 MEM_TYPE=3, freq_sel=15
2123 19:59:57.504956 sv_algorithm_assistance_LP4_1600
2124 19:59:57.508515 ============ PULL DRAM RESETB DOWN ============
2125 19:59:57.515415 ========== PULL DRAM RESETB DOWN end =========
2126 19:59:57.519017 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2127 19:59:57.521908 ===================================
2128 19:59:57.525397 LPDDR4 DRAM CONFIGURATION
2129 19:59:57.528854 ===================================
2130 19:59:57.529369 EX_ROW_EN[0] = 0x0
2131 19:59:57.531312 EX_ROW_EN[1] = 0x0
2132 19:59:57.535111 LP4Y_EN = 0x0
2133 19:59:57.535750 WORK_FSP = 0x0
2134 19:59:57.538430 WL = 0x4
2135 19:59:57.538948 RL = 0x4
2136 19:59:57.541977 BL = 0x2
2137 19:59:57.542491 RPST = 0x0
2138 19:59:57.545088 RD_PRE = 0x0
2139 19:59:57.545609 WR_PRE = 0x1
2140 19:59:57.548134 WR_PST = 0x0
2141 19:59:57.548637 DBI_WR = 0x0
2142 19:59:57.551969 DBI_RD = 0x0
2143 19:59:57.552486 OTF = 0x1
2144 19:59:57.555033 ===================================
2145 19:59:57.558471 ===================================
2146 19:59:57.562416 ANA top config
2147 19:59:57.565188 ===================================
2148 19:59:57.565703 DLL_ASYNC_EN = 0
2149 19:59:57.568889 ALL_SLAVE_EN = 0
2150 19:59:57.572095 NEW_RANK_MODE = 1
2151 19:59:57.575113 DLL_IDLE_MODE = 1
2152 19:59:57.575694 LP45_APHY_COMB_EN = 1
2153 19:59:57.578198 TX_ODT_DIS = 1
2154 19:59:57.582218 NEW_8X_MODE = 1
2155 19:59:57.585229 ===================================
2156 19:59:57.588279 ===================================
2157 19:59:57.591472 data_rate = 2400
2158 19:59:57.595049 CKR = 1
2159 19:59:57.598981 DQ_P2S_RATIO = 8
2160 19:59:57.601911 ===================================
2161 19:59:57.602421 CA_P2S_RATIO = 8
2162 19:59:57.605287 DQ_CA_OPEN = 0
2163 19:59:57.608572 DQ_SEMI_OPEN = 0
2164 19:59:57.611564 CA_SEMI_OPEN = 0
2165 19:59:57.615252 CA_FULL_RATE = 0
2166 19:59:57.615817 DQ_CKDIV4_EN = 0
2167 19:59:57.618091 CA_CKDIV4_EN = 0
2168 19:59:57.621716 CA_PREDIV_EN = 0
2169 19:59:57.624851 PH8_DLY = 17
2170 19:59:57.628348 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2171 19:59:57.631893 DQ_AAMCK_DIV = 4
2172 19:59:57.632406 CA_AAMCK_DIV = 4
2173 19:59:57.635213 CA_ADMCK_DIV = 4
2174 19:59:57.638549 DQ_TRACK_CA_EN = 0
2175 19:59:57.641627 CA_PICK = 1200
2176 19:59:57.644869 CA_MCKIO = 1200
2177 19:59:57.648756 MCKIO_SEMI = 0
2178 19:59:57.651774 PLL_FREQ = 2366
2179 19:59:57.654714 DQ_UI_PI_RATIO = 32
2180 19:59:57.655231 CA_UI_PI_RATIO = 0
2181 19:59:57.658289 ===================================
2182 19:59:57.661741 ===================================
2183 19:59:57.664762 memory_type:LPDDR4
2184 19:59:57.668229 GP_NUM : 10
2185 19:59:57.668744 SRAM_EN : 1
2186 19:59:57.671530 MD32_EN : 0
2187 19:59:57.675146 ===================================
2188 19:59:57.678754 [ANA_INIT] >>>>>>>>>>>>>>
2189 19:59:57.679267 <<<<<< [CONFIGURE PHASE]: ANA_TX
2190 19:59:57.684838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2191 19:59:57.685376 ===================================
2192 19:59:57.688181 data_rate = 2400,PCW = 0X5b00
2193 19:59:57.691340 ===================================
2194 19:59:57.695043 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2195 19:59:57.701616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 19:59:57.707924 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 19:59:57.711232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2198 19:59:57.715101 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2199 19:59:57.718651 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2200 19:59:57.721842 [ANA_INIT] flow start
2201 19:59:57.722345 [ANA_INIT] PLL >>>>>>>>
2202 19:59:57.725030 [ANA_INIT] PLL <<<<<<<<
2203 19:59:57.728035 [ANA_INIT] MIDPI >>>>>>>>
2204 19:59:57.728606 [ANA_INIT] MIDPI <<<<<<<<
2205 19:59:57.731501 [ANA_INIT] DLL >>>>>>>>
2206 19:59:57.735312 [ANA_INIT] DLL <<<<<<<<
2207 19:59:57.735885 [ANA_INIT] flow end
2208 19:59:57.741947 ============ LP4 DIFF to SE enter ============
2209 19:59:57.744931 ============ LP4 DIFF to SE exit ============
2210 19:59:57.748386 [ANA_INIT] <<<<<<<<<<<<<
2211 19:59:57.751824 [Flow] Enable top DCM control >>>>>
2212 19:59:57.754935 [Flow] Enable top DCM control <<<<<
2213 19:59:57.755514 Enable DLL master slave shuffle
2214 19:59:57.761184 ==============================================================
2215 19:59:57.765030 Gating Mode config
2216 19:59:57.768039 ==============================================================
2217 19:59:57.771353 Config description:
2218 19:59:57.781016 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2219 19:59:57.788079 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2220 19:59:57.791751 SELPH_MODE 0: By rank 1: By Phase
2221 19:59:57.798229 ==============================================================
2222 19:59:57.801387 GAT_TRACK_EN = 1
2223 19:59:57.805261 RX_GATING_MODE = 2
2224 19:59:57.808010 RX_GATING_TRACK_MODE = 2
2225 19:59:57.808431 SELPH_MODE = 1
2226 19:59:57.811701 PICG_EARLY_EN = 1
2227 19:59:57.814661 VALID_LAT_VALUE = 1
2228 19:59:57.821301 ==============================================================
2229 19:59:57.824744 Enter into Gating configuration >>>>
2230 19:59:57.828382 Exit from Gating configuration <<<<
2231 19:59:57.831565 Enter into DVFS_PRE_config >>>>>
2232 19:59:57.841614 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2233 19:59:57.844850 Exit from DVFS_PRE_config <<<<<
2234 19:59:57.847979 Enter into PICG configuration >>>>
2235 19:59:57.851614 Exit from PICG configuration <<<<
2236 19:59:57.855006 [RX_INPUT] configuration >>>>>
2237 19:59:57.858395 [RX_INPUT] configuration <<<<<
2238 19:59:57.861525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2239 19:59:57.868974 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2240 19:59:57.874745 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 19:59:57.878160 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 19:59:57.884937 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 19:59:57.891560 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 19:59:57.894907 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2245 19:59:57.901216 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2246 19:59:57.905122 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2247 19:59:57.908260 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2248 19:59:57.911321 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2249 19:59:57.918460 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2250 19:59:57.921699 ===================================
2251 19:59:57.922121 LPDDR4 DRAM CONFIGURATION
2252 19:59:57.924300 ===================================
2253 19:59:57.927495 EX_ROW_EN[0] = 0x0
2254 19:59:57.930888 EX_ROW_EN[1] = 0x0
2255 19:59:57.931307 LP4Y_EN = 0x0
2256 19:59:57.934445 WORK_FSP = 0x0
2257 19:59:57.934866 WL = 0x4
2258 19:59:57.937611 RL = 0x4
2259 19:59:57.938031 BL = 0x2
2260 19:59:57.941141 RPST = 0x0
2261 19:59:57.941560 RD_PRE = 0x0
2262 19:59:57.944177 WR_PRE = 0x1
2263 19:59:57.944595 WR_PST = 0x0
2264 19:59:57.947453 DBI_WR = 0x0
2265 19:59:57.947998 DBI_RD = 0x0
2266 19:59:57.950990 OTF = 0x1
2267 19:59:57.954477 ===================================
2268 19:59:57.957959 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2269 19:59:57.961148 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2270 19:59:57.968209 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 19:59:57.970996 ===================================
2272 19:59:57.971460 LPDDR4 DRAM CONFIGURATION
2273 19:59:57.974698 ===================================
2274 19:59:57.978186 EX_ROW_EN[0] = 0x10
2275 19:59:57.978709 EX_ROW_EN[1] = 0x0
2276 19:59:57.981179 LP4Y_EN = 0x0
2277 19:59:57.984415 WORK_FSP = 0x0
2278 19:59:57.984832 WL = 0x4
2279 19:59:57.988099 RL = 0x4
2280 19:59:57.988518 BL = 0x2
2281 19:59:57.990974 RPST = 0x0
2282 19:59:57.991432 RD_PRE = 0x0
2283 19:59:57.994754 WR_PRE = 0x1
2284 19:59:57.995245 WR_PST = 0x0
2285 19:59:57.997998 DBI_WR = 0x0
2286 19:59:57.998522 DBI_RD = 0x0
2287 19:59:58.001087 OTF = 0x1
2288 19:59:58.004320 ===================================
2289 19:59:58.011560 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2290 19:59:58.012059 ==
2291 19:59:58.014296 Dram Type= 6, Freq= 0, CH_0, rank 0
2292 19:59:58.017846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2293 19:59:58.018261 ==
2294 19:59:58.021290 [Duty_Offset_Calibration]
2295 19:59:58.021702 B0:2 B1:0 CA:3
2296 19:59:58.022029
2297 19:59:58.024470 [DutyScan_Calibration_Flow] k_type=0
2298 19:59:58.034519
2299 19:59:58.034929 ==CLK 0==
2300 19:59:58.037355 Final CLK duty delay cell = 0
2301 19:59:58.041275 [0] MAX Duty = 5031%(X100), DQS PI = 12
2302 19:59:58.044130 [0] MIN Duty = 4875%(X100), DQS PI = 58
2303 19:59:58.044550 [0] AVG Duty = 4953%(X100)
2304 19:59:58.047552
2305 19:59:58.047967 CH0 CLK Duty spec in!! Max-Min= 156%
2306 19:59:58.054622 [DutyScan_Calibration_Flow] ====Done====
2307 19:59:58.055137
2308 19:59:58.057250 [DutyScan_Calibration_Flow] k_type=1
2309 19:59:58.073192
2310 19:59:58.073693 ==DQS 0 ==
2311 19:59:58.075771 Final DQS duty delay cell = 0
2312 19:59:58.079768 [0] MAX Duty = 5062%(X100), DQS PI = 14
2313 19:59:58.082837 [0] MIN Duty = 4907%(X100), DQS PI = 4
2314 19:59:58.086201 [0] AVG Duty = 4984%(X100)
2315 19:59:58.086615
2316 19:59:58.086941 ==DQS 1 ==
2317 19:59:58.089899 Final DQS duty delay cell = -4
2318 19:59:58.092585 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2319 19:59:58.096107 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2320 19:59:58.099373 [-4] AVG Duty = 4937%(X100)
2321 19:59:58.099848
2322 19:59:58.102747 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2323 19:59:58.103249
2324 19:59:58.105872 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2325 19:59:58.109085 [DutyScan_Calibration_Flow] ====Done====
2326 19:59:58.109503
2327 19:59:58.112803 [DutyScan_Calibration_Flow] k_type=3
2328 19:59:58.130480
2329 19:59:58.130993 ==DQM 0 ==
2330 19:59:58.133757 Final DQM duty delay cell = 0
2331 19:59:58.136971 [0] MAX Duty = 5124%(X100), DQS PI = 28
2332 19:59:58.140277 [0] MIN Duty = 4907%(X100), DQS PI = 0
2333 19:59:58.140787 [0] AVG Duty = 5015%(X100)
2334 19:59:58.143182
2335 19:59:58.143632 ==DQM 1 ==
2336 19:59:58.146842 Final DQM duty delay cell = 4
2337 19:59:58.150395 [4] MAX Duty = 5124%(X100), DQS PI = 50
2338 19:59:58.153509 [4] MIN Duty = 5000%(X100), DQS PI = 32
2339 19:59:58.154026 [4] AVG Duty = 5062%(X100)
2340 19:59:58.156566
2341 19:59:58.159883 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2342 19:59:58.160305
2343 19:59:58.163613 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2344 19:59:58.166674 [DutyScan_Calibration_Flow] ====Done====
2345 19:59:58.167085
2346 19:59:58.169888 [DutyScan_Calibration_Flow] k_type=2
2347 19:59:58.185520
2348 19:59:58.186031 ==DQ 0 ==
2349 19:59:58.188263 Final DQ duty delay cell = -4
2350 19:59:58.191678 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2351 19:59:58.195342 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2352 19:59:58.198782 [-4] AVG Duty = 4969%(X100)
2353 19:59:58.199299
2354 19:59:58.199685 ==DQ 1 ==
2355 19:59:58.202008 Final DQ duty delay cell = -4
2356 19:59:58.205525 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2357 19:59:58.208419 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2358 19:59:58.211691 [-4] AVG Duty = 4938%(X100)
2359 19:59:58.212099
2360 19:59:58.215257 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2361 19:59:58.215817
2362 19:59:58.218034 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2363 19:59:58.221849 [DutyScan_Calibration_Flow] ====Done====
2364 19:59:58.222372 ==
2365 19:59:58.224820 Dram Type= 6, Freq= 0, CH_1, rank 0
2366 19:59:58.228746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 19:59:58.229275 ==
2368 19:59:58.231955 [Duty_Offset_Calibration]
2369 19:59:58.232372 B0:1 B1:-2 CA:0
2370 19:59:58.232704
2371 19:59:58.235220 [DutyScan_Calibration_Flow] k_type=0
2372 19:59:58.246029
2373 19:59:58.246547 ==CLK 0==
2374 19:59:58.249375 Final CLK duty delay cell = 0
2375 19:59:58.252514 [0] MAX Duty = 5062%(X100), DQS PI = 30
2376 19:59:58.255995 [0] MIN Duty = 4876%(X100), DQS PI = 2
2377 19:59:58.256517 [0] AVG Duty = 4969%(X100)
2378 19:59:58.258874
2379 19:59:58.259289 CH1 CLK Duty spec in!! Max-Min= 186%
2380 19:59:58.266064 [DutyScan_Calibration_Flow] ====Done====
2381 19:59:58.266589
2382 19:59:58.268711 [DutyScan_Calibration_Flow] k_type=1
2383 19:59:58.284083
2384 19:59:58.284601 ==DQS 0 ==
2385 19:59:58.287459 Final DQS duty delay cell = -4
2386 19:59:58.290655 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2387 19:59:58.294497 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2388 19:59:58.297445 [-4] AVG Duty = 4969%(X100)
2389 19:59:58.297877
2390 19:59:58.298206 ==DQS 1 ==
2391 19:59:58.301071 Final DQS duty delay cell = 0
2392 19:59:58.304529 [0] MAX Duty = 5093%(X100), DQS PI = 0
2393 19:59:58.308016 [0] MIN Duty = 4875%(X100), DQS PI = 26
2394 19:59:58.310843 [0] AVG Duty = 4984%(X100)
2395 19:59:58.311261
2396 19:59:58.314673 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2397 19:59:58.315216
2398 19:59:58.317955 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2399 19:59:58.321715 [DutyScan_Calibration_Flow] ====Done====
2400 19:59:58.322239
2401 19:59:58.324045 [DutyScan_Calibration_Flow] k_type=3
2402 19:59:58.341571
2403 19:59:58.342088 ==DQM 0 ==
2404 19:59:58.344188 Final DQM duty delay cell = 0
2405 19:59:58.347980 [0] MAX Duty = 5031%(X100), DQS PI = 24
2406 19:59:58.350848 [0] MIN Duty = 4876%(X100), DQS PI = 0
2407 19:59:58.351250 [0] AVG Duty = 4953%(X100)
2408 19:59:58.354687
2409 19:59:58.355206 ==DQM 1 ==
2410 19:59:58.357396 Final DQM duty delay cell = 0
2411 19:59:58.360992 [0] MAX Duty = 5031%(X100), DQS PI = 36
2412 19:59:58.364352 [0] MIN Duty = 4907%(X100), DQS PI = 4
2413 19:59:58.364870 [0] AVG Duty = 4969%(X100)
2414 19:59:58.367224
2415 19:59:58.370501 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2416 19:59:58.370919
2417 19:59:58.374678 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2418 19:59:58.377619 [DutyScan_Calibration_Flow] ====Done====
2419 19:59:58.378041
2420 19:59:58.380835 [DutyScan_Calibration_Flow] k_type=2
2421 19:59:58.397590
2422 19:59:58.398099 ==DQ 0 ==
2423 19:59:58.400353 Final DQ duty delay cell = 0
2424 19:59:58.403858 [0] MAX Duty = 5093%(X100), DQS PI = 32
2425 19:59:58.407314 [0] MIN Duty = 4907%(X100), DQS PI = 56
2426 19:59:58.407891 [0] AVG Duty = 5000%(X100)
2427 19:59:58.410591
2428 19:59:58.411007 ==DQ 1 ==
2429 19:59:58.413614 Final DQ duty delay cell = 0
2430 19:59:58.417459 [0] MAX Duty = 5093%(X100), DQS PI = 22
2431 19:59:58.420835 [0] MIN Duty = 4969%(X100), DQS PI = 26
2432 19:59:58.421350 [0] AVG Duty = 5031%(X100)
2433 19:59:58.421685
2434 19:59:58.427474 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2435 19:59:58.427979
2436 19:59:58.430896 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2437 19:59:58.433809 [DutyScan_Calibration_Flow] ====Done====
2438 19:59:58.437771 nWR fixed to 30
2439 19:59:58.438290 [ModeRegInit_LP4] CH0 RK0
2440 19:59:58.440208 [ModeRegInit_LP4] CH0 RK1
2441 19:59:58.443848 [ModeRegInit_LP4] CH1 RK0
2442 19:59:58.444357 [ModeRegInit_LP4] CH1 RK1
2443 19:59:58.447030 match AC timing 7
2444 19:59:58.450433 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2445 19:59:58.454056 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2446 19:59:58.460818 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2447 19:59:58.464132 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2448 19:59:58.470771 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2449 19:59:58.471284 ==
2450 19:59:58.474140 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 19:59:58.477592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 19:59:58.478203 ==
2453 19:59:58.483932 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2454 19:59:58.487010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2455 19:59:58.497839 [CA 0] Center 40 (10~71) winsize 62
2456 19:59:58.500355 [CA 1] Center 39 (9~70) winsize 62
2457 19:59:58.503458 [CA 2] Center 36 (6~66) winsize 61
2458 19:59:58.506890 [CA 3] Center 35 (5~66) winsize 62
2459 19:59:58.510660 [CA 4] Center 34 (4~65) winsize 62
2460 19:59:58.513674 [CA 5] Center 33 (3~63) winsize 61
2461 19:59:58.514094
2462 19:59:58.517764 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2463 19:59:58.518289
2464 19:59:58.520577 [CATrainingPosCal] consider 1 rank data
2465 19:59:58.523681 u2DelayCellTimex100 = 270/100 ps
2466 19:59:58.527553 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2467 19:59:58.534072 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2468 19:59:58.537506 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2469 19:59:58.540902 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2470 19:59:58.543917 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2471 19:59:58.547789 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2472 19:59:58.548313
2473 19:59:58.550303 CA PerBit enable=1, Macro0, CA PI delay=33
2474 19:59:58.550721
2475 19:59:58.554021 [CBTSetCACLKResult] CA Dly = 33
2476 19:59:58.554540 CS Dly: 7 (0~38)
2477 19:59:58.556904 ==
2478 19:59:58.560431 Dram Type= 6, Freq= 0, CH_0, rank 1
2479 19:59:58.564432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 19:59:58.565008 ==
2481 19:59:58.567086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 19:59:58.573869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2483 19:59:58.583534 [CA 0] Center 40 (10~70) winsize 61
2484 19:59:58.586846 [CA 1] Center 40 (10~70) winsize 61
2485 19:59:58.590121 [CA 2] Center 35 (5~66) winsize 62
2486 19:59:58.593670 [CA 3] Center 35 (5~66) winsize 62
2487 19:59:58.596906 [CA 4] Center 34 (4~65) winsize 62
2488 19:59:58.600080 [CA 5] Center 33 (3~64) winsize 62
2489 19:59:58.600497
2490 19:59:58.603039 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2491 19:59:58.603499
2492 19:59:58.606546 [CATrainingPosCal] consider 2 rank data
2493 19:59:58.610213 u2DelayCellTimex100 = 270/100 ps
2494 19:59:58.613185 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2495 19:59:58.620014 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2496 19:59:58.623591 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2497 19:59:58.626377 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 19:59:58.630240 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2499 19:59:58.633515 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2500 19:59:58.634042
2501 19:59:58.636736 CA PerBit enable=1, Macro0, CA PI delay=33
2502 19:59:58.637229
2503 19:59:58.640385 [CBTSetCACLKResult] CA Dly = 33
2504 19:59:58.643362 CS Dly: 8 (0~40)
2505 19:59:58.643916
2506 19:59:58.646575 ----->DramcWriteLeveling(PI) begin...
2507 19:59:58.647106 ==
2508 19:59:58.649856 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 19:59:58.653354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 19:59:58.653772 ==
2511 19:59:58.657039 Write leveling (Byte 0): 34 => 34
2512 19:59:58.659902 Write leveling (Byte 1): 31 => 31
2513 19:59:58.663790 DramcWriteLeveling(PI) end<-----
2514 19:59:58.664316
2515 19:59:58.664649 ==
2516 19:59:58.666893 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 19:59:58.670213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 19:59:58.670747 ==
2519 19:59:58.673297 [Gating] SW mode calibration
2520 19:59:58.680086 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2521 19:59:58.686525 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2522 19:59:58.690303 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 19:59:58.693870 0 15 4 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 0)
2524 19:59:58.700310 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 19:59:58.703320 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 19:59:58.706801 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 19:59:58.709940 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 19:59:58.717127 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 19:59:58.720351 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2530 19:59:58.723543 1 0 0 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (1 0)
2531 19:59:58.729996 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2532 19:59:58.733267 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 19:59:58.736698 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 19:59:58.743269 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 19:59:58.746701 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 19:59:58.750033 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 19:59:58.756404 1 0 28 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
2538 19:59:58.759445 1 1 0 | B1->B0 | 2929 3333 | 0 0 | (0 0) (0 0)
2539 19:59:58.763201 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2540 19:59:58.769814 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 19:59:58.773212 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 19:59:58.776376 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 19:59:58.783099 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 19:59:58.786345 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 19:59:58.789631 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2546 19:59:58.796187 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2547 19:59:58.799954 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2548 19:59:58.803222 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 19:59:58.809985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 19:59:58.812802 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 19:59:58.816356 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 19:59:58.823162 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 19:59:58.825966 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 19:59:58.829684 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 19:59:58.836389 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 19:59:58.839633 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 19:59:58.842827 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 19:59:58.846541 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 19:59:58.852778 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 19:59:58.856395 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 19:59:58.859248 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2562 19:59:58.866040 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2563 19:59:58.869749 Total UI for P1: 0, mck2ui 16
2564 19:59:58.873012 best dqsien dly found for B0: ( 1, 3, 28)
2565 19:59:58.876474 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2566 19:59:58.879171 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 19:59:58.883200 Total UI for P1: 0, mck2ui 16
2568 19:59:58.885889 best dqsien dly found for B1: ( 1, 4, 2)
2569 19:59:58.889745 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2570 19:59:58.892824 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2571 19:59:58.893246
2572 19:59:58.899906 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2573 19:59:58.902934 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2574 19:59:58.903497 [Gating] SW calibration Done
2575 19:59:58.905989 ==
2576 19:59:58.909493 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 19:59:58.912549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 19:59:58.912973 ==
2579 19:59:58.913305 RX Vref Scan: 0
2580 19:59:58.913615
2581 19:59:58.916006 RX Vref 0 -> 0, step: 1
2582 19:59:58.916423
2583 19:59:58.919853 RX Delay -40 -> 252, step: 8
2584 19:59:58.922957 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2585 19:59:58.926367 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2586 19:59:58.929402 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2587 19:59:58.936256 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2588 19:59:58.939282 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2589 19:59:58.942938 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2590 19:59:58.946458 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2591 19:59:58.949464 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2592 19:59:58.956183 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2593 19:59:58.959603 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2594 19:59:58.962909 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2595 19:59:58.966160 iDelay=200, Bit 11, Center 95 (16 ~ 175) 160
2596 19:59:58.969504 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2597 19:59:58.976159 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2598 19:59:58.979537 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2599 19:59:58.982935 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2600 19:59:58.983357 ==
2601 19:59:58.985828 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 19:59:58.989182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 19:59:58.989798 ==
2604 19:59:58.992797 DQS Delay:
2605 19:59:58.993215 DQS0 = 0, DQS1 = 0
2606 19:59:58.993545 DQM Delay:
2607 19:59:58.996337 DQM0 = 112, DQM1 = 102
2608 19:59:58.997029 DQ Delay:
2609 19:59:58.999260 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2610 19:59:59.002578 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2611 19:59:59.005853 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =95
2612 19:59:59.012602 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2613 19:59:59.013109
2614 19:59:59.013442
2615 19:59:59.013750 ==
2616 19:59:59.016066 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 19:59:59.019203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 19:59:59.019664 ==
2619 19:59:59.019997
2620 19:59:59.020305
2621 19:59:59.023066 TX Vref Scan disable
2622 19:59:59.023533 == TX Byte 0 ==
2623 19:59:59.029327 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2624 19:59:59.032616 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2625 19:59:59.033040 == TX Byte 1 ==
2626 19:59:59.039426 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2627 19:59:59.042733 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2628 19:59:59.043151 ==
2629 19:59:59.046176 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 19:59:59.048978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 19:59:59.049456 ==
2632 19:59:59.062513 TX Vref=22, minBit 14, minWin=25, winSum=419
2633 19:59:59.065233 TX Vref=24, minBit 1, minWin=25, winSum=420
2634 19:59:59.069151 TX Vref=26, minBit 2, minWin=26, winSum=427
2635 19:59:59.072093 TX Vref=28, minBit 4, minWin=26, winSum=432
2636 19:59:59.075463 TX Vref=30, minBit 10, minWin=26, winSum=429
2637 19:59:59.082475 TX Vref=32, minBit 2, minWin=26, winSum=426
2638 19:59:59.085412 [TxChooseVref] Worse bit 4, Min win 26, Win sum 432, Final Vref 28
2639 19:59:59.085831
2640 19:59:59.088728 Final TX Range 1 Vref 28
2641 19:59:59.089149
2642 19:59:59.089483 ==
2643 19:59:59.092301 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 19:59:59.095222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 19:59:59.095688 ==
2646 19:59:59.098913
2647 19:59:59.099327
2648 19:59:59.099710 TX Vref Scan disable
2649 19:59:59.102459 == TX Byte 0 ==
2650 19:59:59.105284 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2651 19:59:59.108797 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2652 19:59:59.112074 == TX Byte 1 ==
2653 19:59:59.115120 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2654 19:59:59.118612 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2655 19:59:59.122091
2656 19:59:59.122504 [DATLAT]
2657 19:59:59.122833 Freq=1200, CH0 RK0
2658 19:59:59.123144
2659 19:59:59.125565 DATLAT Default: 0xd
2660 19:59:59.126087 0, 0xFFFF, sum = 0
2661 19:59:59.128609 1, 0xFFFF, sum = 0
2662 19:59:59.129035 2, 0xFFFF, sum = 0
2663 19:59:59.131803 3, 0xFFFF, sum = 0
2664 19:59:59.132225 4, 0xFFFF, sum = 0
2665 19:59:59.135277 5, 0xFFFF, sum = 0
2666 19:59:59.139050 6, 0xFFFF, sum = 0
2667 19:59:59.139547 7, 0xFFFF, sum = 0
2668 19:59:59.141969 8, 0xFFFF, sum = 0
2669 19:59:59.142391 9, 0xFFFF, sum = 0
2670 19:59:59.145424 10, 0xFFFF, sum = 0
2671 19:59:59.145849 11, 0xFFFF, sum = 0
2672 19:59:59.149300 12, 0x0, sum = 1
2673 19:59:59.149724 13, 0x0, sum = 2
2674 19:59:59.152198 14, 0x0, sum = 3
2675 19:59:59.152662 15, 0x0, sum = 4
2676 19:59:59.153045 best_step = 13
2677 19:59:59.153365
2678 19:59:59.155633 ==
2679 19:59:59.158765 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 19:59:59.162553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 19:59:59.163077 ==
2682 19:59:59.163455 RX Vref Scan: 1
2683 19:59:59.163780
2684 19:59:59.165412 Set Vref Range= 32 -> 127
2685 19:59:59.165834
2686 19:59:59.168596 RX Vref 32 -> 127, step: 1
2687 19:59:59.169016
2688 19:59:59.172205 RX Delay -37 -> 252, step: 4
2689 19:59:59.172636
2690 19:59:59.175504 Set Vref, RX VrefLevel [Byte0]: 32
2691 19:59:59.178968 [Byte1]: 32
2692 19:59:59.179543
2693 19:59:59.181945 Set Vref, RX VrefLevel [Byte0]: 33
2694 19:59:59.185141 [Byte1]: 33
2695 19:59:59.188690
2696 19:59:59.189104 Set Vref, RX VrefLevel [Byte0]: 34
2697 19:59:59.192279 [Byte1]: 34
2698 19:59:59.197220
2699 19:59:59.197734 Set Vref, RX VrefLevel [Byte0]: 35
2700 19:59:59.200275 [Byte1]: 35
2701 19:59:59.204528
2702 19:59:59.204944 Set Vref, RX VrefLevel [Byte0]: 36
2703 19:59:59.207962 [Byte1]: 36
2704 19:59:59.212540
2705 19:59:59.212954 Set Vref, RX VrefLevel [Byte0]: 37
2706 19:59:59.215872 [Byte1]: 37
2707 19:59:59.221031
2708 19:59:59.221538 Set Vref, RX VrefLevel [Byte0]: 38
2709 19:59:59.223914 [Byte1]: 38
2710 19:59:59.228974
2711 19:59:59.229483 Set Vref, RX VrefLevel [Byte0]: 39
2712 19:59:59.231955 [Byte1]: 39
2713 19:59:59.236788
2714 19:59:59.237306 Set Vref, RX VrefLevel [Byte0]: 40
2715 19:59:59.240392 [Byte1]: 40
2716 19:59:59.245027
2717 19:59:59.245543 Set Vref, RX VrefLevel [Byte0]: 41
2718 19:59:59.248468 [Byte1]: 41
2719 19:59:59.253021
2720 19:59:59.253541 Set Vref, RX VrefLevel [Byte0]: 42
2721 19:59:59.256337 [Byte1]: 42
2722 19:59:59.261044
2723 19:59:59.261568 Set Vref, RX VrefLevel [Byte0]: 43
2724 19:59:59.264006 [Byte1]: 43
2725 19:59:59.269033
2726 19:59:59.269449 Set Vref, RX VrefLevel [Byte0]: 44
2727 19:59:59.271923 [Byte1]: 44
2728 19:59:59.276775
2729 19:59:59.277296 Set Vref, RX VrefLevel [Byte0]: 45
2730 19:59:59.279897 [Byte1]: 45
2731 19:59:59.284593
2732 19:59:59.285114 Set Vref, RX VrefLevel [Byte0]: 46
2733 19:59:59.288013 [Byte1]: 46
2734 19:59:59.292667
2735 19:59:59.293164 Set Vref, RX VrefLevel [Byte0]: 47
2736 19:59:59.295996 [Byte1]: 47
2737 19:59:59.301030
2738 19:59:59.301536 Set Vref, RX VrefLevel [Byte0]: 48
2739 19:59:59.304220 [Byte1]: 48
2740 19:59:59.309526
2741 19:59:59.310034 Set Vref, RX VrefLevel [Byte0]: 49
2742 19:59:59.312039 [Byte1]: 49
2743 19:59:59.316553
2744 19:59:59.317058 Set Vref, RX VrefLevel [Byte0]: 50
2745 19:59:59.320306 [Byte1]: 50
2746 19:59:59.324817
2747 19:59:59.325329 Set Vref, RX VrefLevel [Byte0]: 51
2748 19:59:59.327949 [Byte1]: 51
2749 19:59:59.332957
2750 19:59:59.333462 Set Vref, RX VrefLevel [Byte0]: 52
2751 19:59:59.336100 [Byte1]: 52
2752 19:59:59.340618
2753 19:59:59.341173 Set Vref, RX VrefLevel [Byte0]: 53
2754 19:59:59.343897 [Byte1]: 53
2755 19:59:59.348631
2756 19:59:59.349048 Set Vref, RX VrefLevel [Byte0]: 54
2757 19:59:59.352089 [Byte1]: 54
2758 19:59:59.357392
2759 19:59:59.357901 Set Vref, RX VrefLevel [Byte0]: 55
2760 19:59:59.359782 [Byte1]: 55
2761 19:59:59.364781
2762 19:59:59.365289 Set Vref, RX VrefLevel [Byte0]: 56
2763 19:59:59.368075 [Byte1]: 56
2764 19:59:59.373088
2765 19:59:59.373623 Set Vref, RX VrefLevel [Byte0]: 57
2766 19:59:59.375977 [Byte1]: 57
2767 19:59:59.381099
2768 19:59:59.381619 Set Vref, RX VrefLevel [Byte0]: 58
2769 19:59:59.384008 [Byte1]: 58
2770 19:59:59.388718
2771 19:59:59.389250 Set Vref, RX VrefLevel [Byte0]: 59
2772 19:59:59.391922 [Byte1]: 59
2773 19:59:59.396499
2774 19:59:59.397015 Set Vref, RX VrefLevel [Byte0]: 60
2775 19:59:59.400048 [Byte1]: 60
2776 19:59:59.404492
2777 19:59:59.404918 Set Vref, RX VrefLevel [Byte0]: 61
2778 19:59:59.407990 [Byte1]: 61
2779 19:59:59.412949
2780 19:59:59.413379 Set Vref, RX VrefLevel [Byte0]: 62
2781 19:59:59.416506 [Byte1]: 62
2782 19:59:59.420609
2783 19:59:59.421025 Set Vref, RX VrefLevel [Byte0]: 63
2784 19:59:59.423686 [Byte1]: 63
2785 19:59:59.429140
2786 19:59:59.429660 Set Vref, RX VrefLevel [Byte0]: 64
2787 19:59:59.432271 [Byte1]: 64
2788 19:59:59.437453
2789 19:59:59.438012 Set Vref, RX VrefLevel [Byte0]: 65
2790 19:59:59.439820 [Byte1]: 65
2791 19:59:59.445357
2792 19:59:59.445877 Set Vref, RX VrefLevel [Byte0]: 66
2793 19:59:59.447945 [Byte1]: 66
2794 19:59:59.453287
2795 19:59:59.453879 Set Vref, RX VrefLevel [Byte0]: 67
2796 19:59:59.455982 [Byte1]: 67
2797 19:59:59.460763
2798 19:59:59.461280 Set Vref, RX VrefLevel [Byte0]: 68
2799 19:59:59.464115 [Byte1]: 68
2800 19:59:59.469086
2801 19:59:59.469608 Set Vref, RX VrefLevel [Byte0]: 69
2802 19:59:59.471838 [Byte1]: 69
2803 19:59:59.477173
2804 19:59:59.477690 Set Vref, RX VrefLevel [Byte0]: 70
2805 19:59:59.480119 [Byte1]: 70
2806 19:59:59.484957
2807 19:59:59.485372 Set Vref, RX VrefLevel [Byte0]: 71
2808 19:59:59.488076 [Byte1]: 71
2809 19:59:59.492714
2810 19:59:59.493223 Set Vref, RX VrefLevel [Byte0]: 72
2811 19:59:59.496018 [Byte1]: 72
2812 19:59:59.501050
2813 19:59:59.501569 Set Vref, RX VrefLevel [Byte0]: 73
2814 19:59:59.504087 [Byte1]: 73
2815 19:59:59.508816
2816 19:59:59.509339 Final RX Vref Byte 0 = 61 to rank0
2817 19:59:59.512063 Final RX Vref Byte 1 = 52 to rank0
2818 19:59:59.515487 Final RX Vref Byte 0 = 61 to rank1
2819 19:59:59.518693 Final RX Vref Byte 1 = 52 to rank1==
2820 19:59:59.521994 Dram Type= 6, Freq= 0, CH_0, rank 0
2821 19:59:59.528898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 19:59:59.529548 ==
2823 19:59:59.529912 DQS Delay:
2824 19:59:59.530223 DQS0 = 0, DQS1 = 0
2825 19:59:59.532008 DQM Delay:
2826 19:59:59.532425 DQM0 = 112, DQM1 = 101
2827 19:59:59.535251 DQ Delay:
2828 19:59:59.538680 DQ0 =112, DQ1 =112, DQ2 =114, DQ3 =106
2829 19:59:59.542651 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2830 19:59:59.545953 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2831 19:59:59.548605 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2832 19:59:59.549025
2833 19:59:59.549355
2834 19:59:59.555670 [DQSOSCAuto] RK0, (LSB)MR18= 0xfafa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2835 19:59:59.558776 CH0 RK0: MR19=303, MR18=FAFA
2836 19:59:59.565608 CH0_RK0: MR19=0x303, MR18=0xFAFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2837 19:59:59.566132
2838 19:59:59.568857 ----->DramcWriteLeveling(PI) begin...
2839 19:59:59.569400 ==
2840 19:59:59.572072 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 19:59:59.576030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 19:59:59.576553 ==
2843 19:59:59.578729 Write leveling (Byte 0): 33 => 33
2844 19:59:59.582677 Write leveling (Byte 1): 31 => 31
2845 19:59:59.585172 DramcWriteLeveling(PI) end<-----
2846 19:59:59.585591
2847 19:59:59.585920 ==
2848 19:59:59.588828 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 19:59:59.595513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 19:59:59.596021 ==
2851 19:59:59.596356 [Gating] SW mode calibration
2852 19:59:59.605506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2853 19:59:59.609110 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2854 19:59:59.611971 0 15 0 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
2855 19:59:59.618567 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 19:59:59.622977 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 19:59:59.625324 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 19:59:59.632282 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 19:59:59.635934 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 19:59:59.639065 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2861 19:59:59.646159 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2862 19:59:59.649197 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2863 19:59:59.652337 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 19:59:59.659154 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 19:59:59.662684 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 19:59:59.665984 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 19:59:59.669265 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 19:59:59.675854 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
2869 19:59:59.679438 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2870 19:59:59.682305 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2871 19:59:59.688723 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 19:59:59.692211 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 19:59:59.695855 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 19:59:59.702569 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 19:59:59.705439 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 19:59:59.708824 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2877 19:59:59.715597 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 19:59:59.719155 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 19:59:59.722520 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 19:59:59.729037 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 19:59:59.732379 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 19:59:59.736028 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 19:59:59.742625 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 19:59:59.746074 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 19:59:59.748646 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 19:59:59.755512 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 19:59:59.758684 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 19:59:59.762127 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 19:59:59.768936 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 19:59:59.772098 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 19:59:59.775628 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 19:59:59.779603 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 19:59:59.785522 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2894 19:59:59.788693 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2895 19:59:59.792123 Total UI for P1: 0, mck2ui 16
2896 19:59:59.795643 best dqsien dly found for B0: ( 1, 3, 28)
2897 19:59:59.799282 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 19:59:59.802293 Total UI for P1: 0, mck2ui 16
2899 19:59:59.805275 best dqsien dly found for B1: ( 1, 4, 0)
2900 19:59:59.808681 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2901 19:59:59.812037 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2902 19:59:59.812452
2903 19:59:59.818754 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2904 19:59:59.822125 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2905 19:59:59.822633 [Gating] SW calibration Done
2906 19:59:59.826122 ==
2907 19:59:59.829037 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 19:59:59.832836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 19:59:59.833376 ==
2910 19:59:59.833711 RX Vref Scan: 0
2911 19:59:59.834015
2912 19:59:59.835306 RX Vref 0 -> 0, step: 1
2913 19:59:59.835775
2914 19:59:59.839109 RX Delay -40 -> 252, step: 8
2915 19:59:59.842209 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2916 19:59:59.846151 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2917 19:59:59.849114 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2918 19:59:59.855634 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2919 19:59:59.859321 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2920 19:59:59.862314 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2921 19:59:59.865518 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2922 19:59:59.868815 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2923 19:59:59.875290 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2924 19:59:59.878824 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2925 19:59:59.882463 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2926 19:59:59.885306 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2927 19:59:59.888522 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2928 19:59:59.895442 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2929 19:59:59.899281 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2930 19:59:59.901952 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2931 19:59:59.902464 ==
2932 19:59:59.905239 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 19:59:59.909056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 19:59:59.909563 ==
2935 19:59:59.911611 DQS Delay:
2936 19:59:59.912021 DQS0 = 0, DQS1 = 0
2937 19:59:59.914976 DQM Delay:
2938 19:59:59.915516 DQM0 = 113, DQM1 = 101
2939 19:59:59.918647 DQ Delay:
2940 19:59:59.922516 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2941 19:59:59.926030 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2942 19:59:59.928768 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2943 19:59:59.932559 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
2944 19:59:59.933067
2945 19:59:59.933396
2946 19:59:59.933701 ==
2947 19:59:59.935063 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 19:59:59.938855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 19:59:59.939373 ==
2950 19:59:59.939742
2951 19:59:59.940050
2952 19:59:59.941923 TX Vref Scan disable
2953 19:59:59.945493 == TX Byte 0 ==
2954 19:59:59.948723 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2955 19:59:59.952236 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2956 19:59:59.952649 == TX Byte 1 ==
2957 19:59:59.958831 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2958 19:59:59.961768 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2959 19:59:59.962183 ==
2960 19:59:59.965427 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 19:59:59.968388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 19:59:59.968855 ==
2963 19:59:59.982137 TX Vref=22, minBit 1, minWin=26, winSum=424
2964 19:59:59.985342 TX Vref=24, minBit 7, minWin=26, winSum=428
2965 19:59:59.988265 TX Vref=26, minBit 1, minWin=26, winSum=434
2966 19:59:59.991912 TX Vref=28, minBit 1, minWin=27, winSum=442
2967 19:59:59.995319 TX Vref=30, minBit 0, minWin=27, winSum=441
2968 19:59:59.998507 TX Vref=32, minBit 1, minWin=27, winSum=440
2969 20:00:00.005160 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 28
2970 20:00:00.005671
2971 20:00:00.008618 Final TX Range 1 Vref 28
2972 20:00:00.009032
2973 20:00:00.009357 ==
2974 20:00:00.011913 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 20:00:00.014733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 20:00:00.015152 ==
2977 20:00:00.015519
2978 20:00:00.018211
2979 20:00:00.018621 TX Vref Scan disable
2980 20:00:00.021972 == TX Byte 0 ==
2981 20:00:00.025412 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2982 20:00:00.028196 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2983 20:00:00.031731 == TX Byte 1 ==
2984 20:00:00.035062 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2985 20:00:00.038587 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2986 20:00:00.039002
2987 20:00:00.041731 [DATLAT]
2988 20:00:00.042243 Freq=1200, CH0 RK1
2989 20:00:00.042576
2990 20:00:00.045159 DATLAT Default: 0xd
2991 20:00:00.045672 0, 0xFFFF, sum = 0
2992 20:00:00.048696 1, 0xFFFF, sum = 0
2993 20:00:00.049213 2, 0xFFFF, sum = 0
2994 20:00:00.051488 3, 0xFFFF, sum = 0
2995 20:00:00.051909 4, 0xFFFF, sum = 0
2996 20:00:00.055042 5, 0xFFFF, sum = 0
2997 20:00:00.055600 6, 0xFFFF, sum = 0
2998 20:00:00.058341 7, 0xFFFF, sum = 0
2999 20:00:00.058849 8, 0xFFFF, sum = 0
3000 20:00:00.061622 9, 0xFFFF, sum = 0
3001 20:00:00.065239 10, 0xFFFF, sum = 0
3002 20:00:00.065790 11, 0xFFFF, sum = 0
3003 20:00:00.068503 12, 0x0, sum = 1
3004 20:00:00.068916 13, 0x0, sum = 2
3005 20:00:00.069244 14, 0x0, sum = 3
3006 20:00:00.072110 15, 0x0, sum = 4
3007 20:00:00.072629 best_step = 13
3008 20:00:00.073162
3009 20:00:00.075817 ==
3010 20:00:00.076326 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 20:00:00.082109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 20:00:00.082622 ==
3013 20:00:00.082953 RX Vref Scan: 0
3014 20:00:00.083257
3015 20:00:00.085340 RX Vref 0 -> 0, step: 1
3016 20:00:00.085750
3017 20:00:00.088489 RX Delay -37 -> 252, step: 4
3018 20:00:00.091410 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3019 20:00:00.095112 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3020 20:00:00.102150 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3021 20:00:00.104772 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3022 20:00:00.108195 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3023 20:00:00.112130 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3024 20:00:00.115206 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3025 20:00:00.121478 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3026 20:00:00.125360 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3027 20:00:00.128511 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3028 20:00:00.131828 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3029 20:00:00.135436 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3030 20:00:00.142012 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3031 20:00:00.145524 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3032 20:00:00.148375 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3033 20:00:00.151786 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3034 20:00:00.152296 ==
3035 20:00:00.155379 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 20:00:00.161819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 20:00:00.162322 ==
3038 20:00:00.162770 DQS Delay:
3039 20:00:00.163091 DQS0 = 0, DQS1 = 0
3040 20:00:00.164895 DQM Delay:
3041 20:00:00.165417 DQM0 = 110, DQM1 = 101
3042 20:00:00.168426 DQ Delay:
3043 20:00:00.171457 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3044 20:00:00.175318 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =118
3045 20:00:00.178228 DQ8 =90, DQ9 =82, DQ10 =104, DQ11 =94
3046 20:00:00.181669 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3047 20:00:00.182097
3048 20:00:00.182421
3049 20:00:00.188658 [DQSOSCAuto] RK1, (LSB)MR18= 0x16fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps
3050 20:00:00.191559 CH0 RK1: MR19=403, MR18=16FE
3051 20:00:00.198226 CH0_RK1: MR19=0x403, MR18=0x16FE, DQSOSC=401, MR23=63, INC=40, DEC=27
3052 20:00:00.201347 [RxdqsGatingPostProcess] freq 1200
3053 20:00:00.208167 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3054 20:00:00.211448 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 20:00:00.211968 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 20:00:00.214619 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 20:00:00.218213 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 20:00:00.221703 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 20:00:00.224921 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 20:00:00.228216 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 20:00:00.231970 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 20:00:00.235238 Pre-setting of DQS Precalculation
3063 20:00:00.241491 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3064 20:00:00.241899 ==
3065 20:00:00.245364 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 20:00:00.248444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 20:00:00.248903 ==
3068 20:00:00.251735 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3069 20:00:00.258544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3070 20:00:00.267743 [CA 0] Center 37 (7~67) winsize 61
3071 20:00:00.271054 [CA 1] Center 37 (7~68) winsize 62
3072 20:00:00.274376 [CA 2] Center 34 (4~64) winsize 61
3073 20:00:00.277484 [CA 3] Center 34 (4~64) winsize 61
3074 20:00:00.281335 [CA 4] Center 34 (4~64) winsize 61
3075 20:00:00.284349 [CA 5] Center 33 (3~63) winsize 61
3076 20:00:00.284830
3077 20:00:00.287793 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3078 20:00:00.288204
3079 20:00:00.291054 [CATrainingPosCal] consider 1 rank data
3080 20:00:00.294928 u2DelayCellTimex100 = 270/100 ps
3081 20:00:00.297917 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3082 20:00:00.301055 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3083 20:00:00.304361 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3084 20:00:00.311334 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3085 20:00:00.314358 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3086 20:00:00.318404 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3087 20:00:00.318930
3088 20:00:00.320901 CA PerBit enable=1, Macro0, CA PI delay=33
3089 20:00:00.321312
3090 20:00:00.324313 [CBTSetCACLKResult] CA Dly = 33
3091 20:00:00.324721 CS Dly: 6 (0~37)
3092 20:00:00.325044 ==
3093 20:00:00.327581 Dram Type= 6, Freq= 0, CH_1, rank 1
3094 20:00:00.334784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 20:00:00.335314 ==
3096 20:00:00.338016 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 20:00:00.344302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3098 20:00:00.353553 [CA 0] Center 37 (7~67) winsize 61
3099 20:00:00.356738 [CA 1] Center 37 (7~68) winsize 62
3100 20:00:00.360014 [CA 2] Center 34 (4~65) winsize 62
3101 20:00:00.363042 [CA 3] Center 33 (3~64) winsize 62
3102 20:00:00.366439 [CA 4] Center 34 (4~65) winsize 62
3103 20:00:00.369868 [CA 5] Center 33 (3~63) winsize 61
3104 20:00:00.370279
3105 20:00:00.373530 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3106 20:00:00.374207
3107 20:00:00.376307 [CATrainingPosCal] consider 2 rank data
3108 20:00:00.379869 u2DelayCellTimex100 = 270/100 ps
3109 20:00:00.382969 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3110 20:00:00.386257 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3111 20:00:00.392748 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 20:00:00.396339 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 20:00:00.399702 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3114 20:00:00.403352 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3115 20:00:00.403550
3116 20:00:00.406315 CA PerBit enable=1, Macro0, CA PI delay=33
3117 20:00:00.406494
3118 20:00:00.409625 [CBTSetCACLKResult] CA Dly = 33
3119 20:00:00.409825 CS Dly: 7 (0~40)
3120 20:00:00.409946
3121 20:00:00.413212 ----->DramcWriteLeveling(PI) begin...
3122 20:00:00.413363 ==
3123 20:00:00.416138 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 20:00:00.423162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 20:00:00.423687 ==
3126 20:00:00.426590 Write leveling (Byte 0): 26 => 26
3127 20:00:00.429953 Write leveling (Byte 1): 30 => 30
3128 20:00:00.430361 DramcWriteLeveling(PI) end<-----
3129 20:00:00.433226
3130 20:00:00.433677 ==
3131 20:00:00.436101 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 20:00:00.439529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 20:00:00.439839 ==
3134 20:00:00.442552 [Gating] SW mode calibration
3135 20:00:00.449373 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3136 20:00:00.452940 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3137 20:00:00.459419 0 15 0 | B1->B0 | 3030 2928 | 1 1 | (1 1) (1 1)
3138 20:00:00.462882 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 20:00:00.466231 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 20:00:00.472824 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 20:00:00.476430 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 20:00:00.479969 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 20:00:00.485958 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3144 20:00:00.489855 0 15 28 | B1->B0 | 2f2f 3232 | 0 0 | (0 1) (0 1)
3145 20:00:00.492786 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3146 20:00:00.499762 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 20:00:00.502929 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 20:00:00.506018 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 20:00:00.512755 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 20:00:00.515988 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 20:00:00.519206 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 20:00:00.526277 1 0 28 | B1->B0 | 4343 3e3e | 0 1 | (0 0) (0 0)
3153 20:00:00.529372 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 20:00:00.532897 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 20:00:00.536347 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 20:00:00.543201 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 20:00:00.546021 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 20:00:00.549852 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 20:00:00.555853 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 20:00:00.559745 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 20:00:00.563079 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3162 20:00:00.569840 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 20:00:00.572744 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 20:00:00.576552 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 20:00:00.583078 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 20:00:00.586297 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 20:00:00.589393 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 20:00:00.596330 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 20:00:00.599649 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 20:00:00.603605 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 20:00:00.609499 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 20:00:00.613176 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 20:00:00.616612 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 20:00:00.623485 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 20:00:00.626350 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 20:00:00.629580 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 20:00:00.636180 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3178 20:00:00.636695 Total UI for P1: 0, mck2ui 16
3179 20:00:00.643232 best dqsien dly found for B1: ( 1, 3, 30)
3180 20:00:00.646529 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 20:00:00.650031 Total UI for P1: 0, mck2ui 16
3182 20:00:00.652800 best dqsien dly found for B0: ( 1, 4, 0)
3183 20:00:00.656043 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
3184 20:00:00.660110 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3185 20:00:00.660622
3186 20:00:00.663218 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
3187 20:00:00.666474 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3188 20:00:00.669644 [Gating] SW calibration Done
3189 20:00:00.670058 ==
3190 20:00:00.673077 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 20:00:00.676299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 20:00:00.676720 ==
3193 20:00:00.679234 RX Vref Scan: 0
3194 20:00:00.679687
3195 20:00:00.680018 RX Vref 0 -> 0, step: 1
3196 20:00:00.682961
3197 20:00:00.683510 RX Delay -40 -> 252, step: 8
3198 20:00:00.689836 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3199 20:00:00.693368 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3200 20:00:00.695996 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3201 20:00:00.699270 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3202 20:00:00.702978 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3203 20:00:00.709374 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3204 20:00:00.713182 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3205 20:00:00.716332 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3206 20:00:00.719230 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3207 20:00:00.723033 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3208 20:00:00.726914 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3209 20:00:00.733080 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3210 20:00:00.736380 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3211 20:00:00.740075 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3212 20:00:00.743159 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3213 20:00:00.746497 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3214 20:00:00.749902 ==
3215 20:00:00.752927 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 20:00:00.756544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 20:00:00.757058 ==
3218 20:00:00.757399 DQS Delay:
3219 20:00:00.759648 DQS0 = 0, DQS1 = 0
3220 20:00:00.760086 DQM Delay:
3221 20:00:00.763573 DQM0 = 114, DQM1 = 106
3222 20:00:00.764105 DQ Delay:
3223 20:00:00.766413 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3224 20:00:00.769775 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3225 20:00:00.772945 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3226 20:00:00.776406 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3227 20:00:00.776946
3228 20:00:00.777393
3229 20:00:00.777711 ==
3230 20:00:00.779580 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 20:00:00.786499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 20:00:00.787020 ==
3233 20:00:00.787352
3234 20:00:00.787719
3235 20:00:00.788018 TX Vref Scan disable
3236 20:00:00.789731 == TX Byte 0 ==
3237 20:00:00.793087 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3238 20:00:00.799620 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3239 20:00:00.800037 == TX Byte 1 ==
3240 20:00:00.803097 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3241 20:00:00.806245 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3242 20:00:00.809822 ==
3243 20:00:00.812761 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 20:00:00.816123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 20:00:00.816536 ==
3246 20:00:00.827805 TX Vref=22, minBit 2, minWin=25, winSum=414
3247 20:00:00.830874 TX Vref=24, minBit 8, minWin=25, winSum=421
3248 20:00:00.834447 TX Vref=26, minBit 9, minWin=25, winSum=425
3249 20:00:00.837728 TX Vref=28, minBit 1, minWin=26, winSum=429
3250 20:00:00.840910 TX Vref=30, minBit 1, minWin=26, winSum=428
3251 20:00:00.844261 TX Vref=32, minBit 9, minWin=25, winSum=424
3252 20:00:00.851419 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3253 20:00:00.851983
3254 20:00:00.854611 Final TX Range 1 Vref 28
3255 20:00:00.855131
3256 20:00:00.855516 ==
3257 20:00:00.857379 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 20:00:00.861170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 20:00:00.861583 ==
3260 20:00:00.861909
3261 20:00:00.864262
3262 20:00:00.864815 TX Vref Scan disable
3263 20:00:00.867599 == TX Byte 0 ==
3264 20:00:00.871144 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3265 20:00:00.874780 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3266 20:00:00.877554 == TX Byte 1 ==
3267 20:00:00.880670 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3268 20:00:00.884081 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3269 20:00:00.884589
3270 20:00:00.887490 [DATLAT]
3271 20:00:00.887989 Freq=1200, CH1 RK0
3272 20:00:00.888323
3273 20:00:00.890452 DATLAT Default: 0xd
3274 20:00:00.890920 0, 0xFFFF, sum = 0
3275 20:00:00.894003 1, 0xFFFF, sum = 0
3276 20:00:00.894418 2, 0xFFFF, sum = 0
3277 20:00:00.897374 3, 0xFFFF, sum = 0
3278 20:00:00.897998 4, 0xFFFF, sum = 0
3279 20:00:00.901589 5, 0xFFFF, sum = 0
3280 20:00:00.902100 6, 0xFFFF, sum = 0
3281 20:00:00.904122 7, 0xFFFF, sum = 0
3282 20:00:00.907620 8, 0xFFFF, sum = 0
3283 20:00:00.908034 9, 0xFFFF, sum = 0
3284 20:00:00.910824 10, 0xFFFF, sum = 0
3285 20:00:00.911241 11, 0xFFFF, sum = 0
3286 20:00:00.914216 12, 0x0, sum = 1
3287 20:00:00.914673 13, 0x0, sum = 2
3288 20:00:00.915010 14, 0x0, sum = 3
3289 20:00:00.917760 15, 0x0, sum = 4
3290 20:00:00.918173 best_step = 13
3291 20:00:00.918499
3292 20:00:00.920904 ==
3293 20:00:00.921381 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 20:00:00.927493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 20:00:00.927903 ==
3296 20:00:00.928225 RX Vref Scan: 1
3297 20:00:00.928523
3298 20:00:00.931110 Set Vref Range= 32 -> 127
3299 20:00:00.931578
3300 20:00:00.934328 RX Vref 32 -> 127, step: 1
3301 20:00:00.934734
3302 20:00:00.937232 RX Delay -21 -> 252, step: 4
3303 20:00:00.937637
3304 20:00:00.940372 Set Vref, RX VrefLevel [Byte0]: 32
3305 20:00:00.944000 [Byte1]: 32
3306 20:00:00.944548
3307 20:00:00.947606 Set Vref, RX VrefLevel [Byte0]: 33
3308 20:00:00.951309 [Byte1]: 33
3309 20:00:00.951870
3310 20:00:00.954240 Set Vref, RX VrefLevel [Byte0]: 34
3311 20:00:00.957498 [Byte1]: 34
3312 20:00:00.961872
3313 20:00:00.962409 Set Vref, RX VrefLevel [Byte0]: 35
3314 20:00:00.964831 [Byte1]: 35
3315 20:00:00.970045
3316 20:00:00.970565 Set Vref, RX VrefLevel [Byte0]: 36
3317 20:00:00.973027 [Byte1]: 36
3318 20:00:00.977728
3319 20:00:00.978244 Set Vref, RX VrefLevel [Byte0]: 37
3320 20:00:00.981240 [Byte1]: 37
3321 20:00:00.985790
3322 20:00:00.986292 Set Vref, RX VrefLevel [Byte0]: 38
3323 20:00:00.989116 [Byte1]: 38
3324 20:00:00.993565
3325 20:00:00.994065 Set Vref, RX VrefLevel [Byte0]: 39
3326 20:00:00.996718 [Byte1]: 39
3327 20:00:01.001304
3328 20:00:01.001709 Set Vref, RX VrefLevel [Byte0]: 40
3329 20:00:01.004928 [Byte1]: 40
3330 20:00:01.009306
3331 20:00:01.009809 Set Vref, RX VrefLevel [Byte0]: 41
3332 20:00:01.012449 [Byte1]: 41
3333 20:00:01.017861
3334 20:00:01.018364 Set Vref, RX VrefLevel [Byte0]: 42
3335 20:00:01.020629 [Byte1]: 42
3336 20:00:01.024896
3337 20:00:01.025434 Set Vref, RX VrefLevel [Byte0]: 43
3338 20:00:01.028252 [Byte1]: 43
3339 20:00:01.033274
3340 20:00:01.033833 Set Vref, RX VrefLevel [Byte0]: 44
3341 20:00:01.036412 [Byte1]: 44
3342 20:00:01.041154
3343 20:00:01.041591 Set Vref, RX VrefLevel [Byte0]: 45
3344 20:00:01.043906 [Byte1]: 45
3345 20:00:01.048394
3346 20:00:01.048900 Set Vref, RX VrefLevel [Byte0]: 46
3347 20:00:01.052051 [Byte1]: 46
3348 20:00:01.056784
3349 20:00:01.057190 Set Vref, RX VrefLevel [Byte0]: 47
3350 20:00:01.060211 [Byte1]: 47
3351 20:00:01.065018
3352 20:00:01.065514 Set Vref, RX VrefLevel [Byte0]: 48
3353 20:00:01.068101 [Byte1]: 48
3354 20:00:01.073040
3355 20:00:01.073452 Set Vref, RX VrefLevel [Byte0]: 49
3356 20:00:01.075870 [Byte1]: 49
3357 20:00:01.080552
3358 20:00:01.081054 Set Vref, RX VrefLevel [Byte0]: 50
3359 20:00:01.084070 [Byte1]: 50
3360 20:00:01.088353
3361 20:00:01.088861 Set Vref, RX VrefLevel [Byte0]: 51
3362 20:00:01.091690 [Byte1]: 51
3363 20:00:01.097023
3364 20:00:01.097525 Set Vref, RX VrefLevel [Byte0]: 52
3365 20:00:01.099589 [Byte1]: 52
3366 20:00:01.104936
3367 20:00:01.105436 Set Vref, RX VrefLevel [Byte0]: 53
3368 20:00:01.107759 [Byte1]: 53
3369 20:00:01.112287
3370 20:00:01.112850 Set Vref, RX VrefLevel [Byte0]: 54
3371 20:00:01.115887 [Byte1]: 54
3372 20:00:01.119751
3373 20:00:01.120156 Set Vref, RX VrefLevel [Byte0]: 55
3374 20:00:01.123556 [Byte1]: 55
3375 20:00:01.128091
3376 20:00:01.128545 Set Vref, RX VrefLevel [Byte0]: 56
3377 20:00:01.131183 [Byte1]: 56
3378 20:00:01.135763
3379 20:00:01.136270 Set Vref, RX VrefLevel [Byte0]: 57
3380 20:00:01.140031 [Byte1]: 57
3381 20:00:01.144131
3382 20:00:01.144642 Set Vref, RX VrefLevel [Byte0]: 58
3383 20:00:01.147509 [Byte1]: 58
3384 20:00:01.152100
3385 20:00:01.152615 Set Vref, RX VrefLevel [Byte0]: 59
3386 20:00:01.155526 [Byte1]: 59
3387 20:00:01.159928
3388 20:00:01.160340 Set Vref, RX VrefLevel [Byte0]: 60
3389 20:00:01.163256 [Byte1]: 60
3390 20:00:01.167743
3391 20:00:01.168253 Set Vref, RX VrefLevel [Byte0]: 61
3392 20:00:01.171312 [Byte1]: 61
3393 20:00:01.175563
3394 20:00:01.176086 Set Vref, RX VrefLevel [Byte0]: 62
3395 20:00:01.178761 [Byte1]: 62
3396 20:00:01.184196
3397 20:00:01.184704 Set Vref, RX VrefLevel [Byte0]: 63
3398 20:00:01.186800 [Byte1]: 63
3399 20:00:01.191665
3400 20:00:01.192183 Set Vref, RX VrefLevel [Byte0]: 64
3401 20:00:01.195037 [Byte1]: 64
3402 20:00:01.199479
3403 20:00:01.199985 Set Vref, RX VrefLevel [Byte0]: 65
3404 20:00:01.203299 [Byte1]: 65
3405 20:00:01.207552
3406 20:00:01.208061 Set Vref, RX VrefLevel [Byte0]: 66
3407 20:00:01.210342 [Byte1]: 66
3408 20:00:01.215652
3409 20:00:01.216166 Set Vref, RX VrefLevel [Byte0]: 67
3410 20:00:01.218343 [Byte1]: 67
3411 20:00:01.223240
3412 20:00:01.223825 Set Vref, RX VrefLevel [Byte0]: 68
3413 20:00:01.226403 [Byte1]: 68
3414 20:00:01.230740
3415 20:00:01.231151 Set Vref, RX VrefLevel [Byte0]: 69
3416 20:00:01.234228 [Byte1]: 69
3417 20:00:01.238939
3418 20:00:01.239480 Set Vref, RX VrefLevel [Byte0]: 70
3419 20:00:01.242557 [Byte1]: 70
3420 20:00:01.247292
3421 20:00:01.247839 Final RX Vref Byte 0 = 53 to rank0
3422 20:00:01.250644 Final RX Vref Byte 1 = 49 to rank0
3423 20:00:01.253257 Final RX Vref Byte 0 = 53 to rank1
3424 20:00:01.256871 Final RX Vref Byte 1 = 49 to rank1==
3425 20:00:01.260140 Dram Type= 6, Freq= 0, CH_1, rank 0
3426 20:00:01.267544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 20:00:01.268056 ==
3428 20:00:01.268381 DQS Delay:
3429 20:00:01.268683 DQS0 = 0, DQS1 = 0
3430 20:00:01.270077 DQM Delay:
3431 20:00:01.270495 DQM0 = 114, DQM1 = 105
3432 20:00:01.273680 DQ Delay:
3433 20:00:01.276720 DQ0 =120, DQ1 =108, DQ2 =104, DQ3 =112
3434 20:00:01.280395 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3435 20:00:01.283499 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3436 20:00:01.287555 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3437 20:00:01.287998
3438 20:00:01.288330
3439 20:00:01.296610 [DQSOSCAuto] RK0, (LSB)MR18= 0xeef5, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3440 20:00:01.297204 CH1 RK0: MR19=303, MR18=EEF5
3441 20:00:01.303275 CH1_RK0: MR19=0x303, MR18=0xEEF5, DQSOSC=414, MR23=63, INC=38, DEC=25
3442 20:00:01.303871
3443 20:00:01.306465 ----->DramcWriteLeveling(PI) begin...
3444 20:00:01.306958 ==
3445 20:00:01.310180 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 20:00:01.313709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 20:00:01.316542 ==
3448 20:00:01.316952 Write leveling (Byte 0): 24 => 24
3449 20:00:01.320303 Write leveling (Byte 1): 28 => 28
3450 20:00:01.323638 DramcWriteLeveling(PI) end<-----
3451 20:00:01.324047
3452 20:00:01.324372 ==
3453 20:00:01.326472 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 20:00:01.333341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 20:00:01.333754 ==
3456 20:00:01.336490 [Gating] SW mode calibration
3457 20:00:01.343368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3458 20:00:01.347143 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3459 20:00:01.353290 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 20:00:01.356747 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 20:00:01.360182 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 20:00:01.363456 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 20:00:01.369759 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 20:00:01.373406 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3465 20:00:01.377267 0 15 24 | B1->B0 | 3434 2828 | 0 0 | (1 0) (0 0)
3466 20:00:01.383439 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3467 20:00:01.386792 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 20:00:01.390621 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 20:00:01.396852 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 20:00:01.399781 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 20:00:01.403140 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 20:00:01.410075 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 20:00:01.413687 1 0 24 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
3474 20:00:01.416579 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3475 20:00:01.423611 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 20:00:01.427096 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 20:00:01.430200 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 20:00:01.436882 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 20:00:01.440183 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 20:00:01.443488 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 20:00:01.450273 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3482 20:00:01.453305 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3483 20:00:01.456849 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 20:00:01.463296 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 20:00:01.466382 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 20:00:01.469814 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 20:00:01.476371 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 20:00:01.479970 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 20:00:01.483369 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 20:00:01.489856 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 20:00:01.492611 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 20:00:01.496399 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 20:00:01.503089 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 20:00:01.506145 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 20:00:01.509366 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 20:00:01.512802 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 20:00:01.518899 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3498 20:00:01.522856 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 20:00:01.525991 Total UI for P1: 0, mck2ui 16
3500 20:00:01.528989 best dqsien dly found for B0: ( 1, 3, 24)
3501 20:00:01.532815 Total UI for P1: 0, mck2ui 16
3502 20:00:01.535952 best dqsien dly found for B1: ( 1, 3, 24)
3503 20:00:01.539504 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3504 20:00:01.542823 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3505 20:00:01.543367
3506 20:00:01.545920 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3507 20:00:01.552213 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3508 20:00:01.552710 [Gating] SW calibration Done
3509 20:00:01.553038 ==
3510 20:00:01.556188 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 20:00:01.562317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 20:00:01.562830 ==
3513 20:00:01.563160 RX Vref Scan: 0
3514 20:00:01.563528
3515 20:00:01.565814 RX Vref 0 -> 0, step: 1
3516 20:00:01.566237
3517 20:00:01.569296 RX Delay -40 -> 252, step: 8
3518 20:00:01.572587 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3519 20:00:01.575781 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3520 20:00:01.578944 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3521 20:00:01.582262 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3522 20:00:01.589534 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3523 20:00:01.592273 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3524 20:00:01.596054 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3525 20:00:01.599277 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3526 20:00:01.602205 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3527 20:00:01.608677 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3528 20:00:01.612469 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3529 20:00:01.615933 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3530 20:00:01.619558 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3531 20:00:01.622308 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3532 20:00:01.628744 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3533 20:00:01.632946 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3534 20:00:01.633499 ==
3535 20:00:01.635781 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 20:00:01.639009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 20:00:01.639593 ==
3538 20:00:01.642619 DQS Delay:
3539 20:00:01.643143 DQS0 = 0, DQS1 = 0
3540 20:00:01.643647 DQM Delay:
3541 20:00:01.646113 DQM0 = 110, DQM1 = 106
3542 20:00:01.646645 DQ Delay:
3543 20:00:01.649130 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3544 20:00:01.651963 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3545 20:00:01.655213 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3546 20:00:01.662264 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3547 20:00:01.662798
3548 20:00:01.663237
3549 20:00:01.663695 ==
3550 20:00:01.665469 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 20:00:01.668994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 20:00:01.669526 ==
3553 20:00:01.669965
3554 20:00:01.670373
3555 20:00:01.672188 TX Vref Scan disable
3556 20:00:01.672616 == TX Byte 0 ==
3557 20:00:01.679017 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3558 20:00:01.682158 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3559 20:00:01.682587 == TX Byte 1 ==
3560 20:00:01.689043 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3561 20:00:01.692225 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3562 20:00:01.692700 ==
3563 20:00:01.695414 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 20:00:01.698783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 20:00:01.699312 ==
3566 20:00:01.711640 TX Vref=22, minBit 0, minWin=25, winSum=421
3567 20:00:01.714769 TX Vref=24, minBit 9, minWin=25, winSum=427
3568 20:00:01.718380 TX Vref=26, minBit 8, minWin=26, winSum=434
3569 20:00:01.722012 TX Vref=28, minBit 8, minWin=25, winSum=431
3570 20:00:01.724488 TX Vref=30, minBit 8, minWin=26, winSum=436
3571 20:00:01.731316 TX Vref=32, minBit 8, minWin=25, winSum=432
3572 20:00:01.734808 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 30
3573 20:00:01.735324
3574 20:00:01.737747 Final TX Range 1 Vref 30
3575 20:00:01.738263
3576 20:00:01.738596 ==
3577 20:00:01.741464 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 20:00:01.744850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 20:00:01.747604 ==
3580 20:00:01.748014
3581 20:00:01.748338
3582 20:00:01.748637 TX Vref Scan disable
3583 20:00:01.751212 == TX Byte 0 ==
3584 20:00:01.754348 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3585 20:00:01.758017 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3586 20:00:01.761352 == TX Byte 1 ==
3587 20:00:01.764629 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3588 20:00:01.771451 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3589 20:00:01.771973
3590 20:00:01.772303 [DATLAT]
3591 20:00:01.772611 Freq=1200, CH1 RK1
3592 20:00:01.772904
3593 20:00:01.774180 DATLAT Default: 0xd
3594 20:00:01.774589 0, 0xFFFF, sum = 0
3595 20:00:01.777785 1, 0xFFFF, sum = 0
3596 20:00:01.781245 2, 0xFFFF, sum = 0
3597 20:00:01.781814 3, 0xFFFF, sum = 0
3598 20:00:01.784133 4, 0xFFFF, sum = 0
3599 20:00:01.784545 5, 0xFFFF, sum = 0
3600 20:00:01.787831 6, 0xFFFF, sum = 0
3601 20:00:01.788249 7, 0xFFFF, sum = 0
3602 20:00:01.790838 8, 0xFFFF, sum = 0
3603 20:00:01.791254 9, 0xFFFF, sum = 0
3604 20:00:01.794302 10, 0xFFFF, sum = 0
3605 20:00:01.794716 11, 0xFFFF, sum = 0
3606 20:00:01.797601 12, 0x0, sum = 1
3607 20:00:01.798016 13, 0x0, sum = 2
3608 20:00:01.801613 14, 0x0, sum = 3
3609 20:00:01.802133 15, 0x0, sum = 4
3610 20:00:01.804255 best_step = 13
3611 20:00:01.804663
3612 20:00:01.804986 ==
3613 20:00:01.807917 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 20:00:01.810841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 20:00:01.811364 ==
3616 20:00:01.811756 RX Vref Scan: 0
3617 20:00:01.814153
3618 20:00:01.814562 RX Vref 0 -> 0, step: 1
3619 20:00:01.814890
3620 20:00:01.817166 RX Delay -21 -> 252, step: 4
3621 20:00:01.824026 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3622 20:00:01.827205 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3623 20:00:01.830753 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3624 20:00:01.834601 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3625 20:00:01.837313 iDelay=195, Bit 4, Center 108 (35 ~ 182) 148
3626 20:00:01.844092 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3627 20:00:01.847310 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3628 20:00:01.850743 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3629 20:00:01.853567 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3630 20:00:01.857136 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3631 20:00:01.863862 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3632 20:00:01.867077 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3633 20:00:01.870352 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3634 20:00:01.873441 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3635 20:00:01.877117 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3636 20:00:01.883195 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3637 20:00:01.883737 ==
3638 20:00:01.886614 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 20:00:01.890468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 20:00:01.891012 ==
3641 20:00:01.891354 DQS Delay:
3642 20:00:01.893173 DQS0 = 0, DQS1 = 0
3643 20:00:01.893582 DQM Delay:
3644 20:00:01.896624 DQM0 = 111, DQM1 = 109
3645 20:00:01.897033 DQ Delay:
3646 20:00:01.900140 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3647 20:00:01.903167 DQ4 =108, DQ5 =122, DQ6 =122, DQ7 =110
3648 20:00:01.906839 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =102
3649 20:00:01.910368 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3650 20:00:01.910887
3651 20:00:01.913728
3652 20:00:01.920377 [DQSOSCAuto] RK1, (LSB)MR18= 0xf707, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3653 20:00:01.923982 CH1 RK1: MR19=304, MR18=F707
3654 20:00:01.930124 CH1_RK1: MR19=0x304, MR18=0xF707, DQSOSC=407, MR23=63, INC=39, DEC=26
3655 20:00:01.933110 [RxdqsGatingPostProcess] freq 1200
3656 20:00:01.936417 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3657 20:00:01.939745 best DQS0 dly(2T, 0.5T) = (0, 12)
3658 20:00:01.943005 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 20:00:01.946732 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3660 20:00:01.950248 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 20:00:01.953077 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 20:00:01.956564 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 20:00:01.959774 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 20:00:01.963140 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 20:00:01.966318 Pre-setting of DQS Precalculation
3666 20:00:01.969940 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3667 20:00:01.976238 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3668 20:00:01.986662 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3669 20:00:01.987172
3670 20:00:01.987554
3671 20:00:01.989725 [Calibration Summary] 2400 Mbps
3672 20:00:01.990237 CH 0, Rank 0
3673 20:00:01.992510 SW Impedance : PASS
3674 20:00:01.993118 DUTY Scan : NO K
3675 20:00:01.995998 ZQ Calibration : PASS
3676 20:00:01.999494 Jitter Meter : NO K
3677 20:00:02.000008 CBT Training : PASS
3678 20:00:02.002717 Write leveling : PASS
3679 20:00:02.003460 RX DQS gating : PASS
3680 20:00:02.006075 RX DQ/DQS(RDDQC) : PASS
3681 20:00:02.009041 TX DQ/DQS : PASS
3682 20:00:02.009454 RX DATLAT : PASS
3683 20:00:02.012357 RX DQ/DQS(Engine): PASS
3684 20:00:02.016111 TX OE : NO K
3685 20:00:02.016649 All Pass.
3686 20:00:02.016984
3687 20:00:02.017292 CH 0, Rank 1
3688 20:00:02.019485 SW Impedance : PASS
3689 20:00:02.023156 DUTY Scan : NO K
3690 20:00:02.023721 ZQ Calibration : PASS
3691 20:00:02.025898 Jitter Meter : NO K
3692 20:00:02.029465 CBT Training : PASS
3693 20:00:02.029975 Write leveling : PASS
3694 20:00:02.033016 RX DQS gating : PASS
3695 20:00:02.036029 RX DQ/DQS(RDDQC) : PASS
3696 20:00:02.036536 TX DQ/DQS : PASS
3697 20:00:02.039487 RX DATLAT : PASS
3698 20:00:02.042462 RX DQ/DQS(Engine): PASS
3699 20:00:02.042997 TX OE : NO K
3700 20:00:02.043340 All Pass.
3701 20:00:02.045828
3702 20:00:02.046333 CH 1, Rank 0
3703 20:00:02.049310 SW Impedance : PASS
3704 20:00:02.049923 DUTY Scan : NO K
3705 20:00:02.052936 ZQ Calibration : PASS
3706 20:00:02.053466 Jitter Meter : NO K
3707 20:00:02.055843 CBT Training : PASS
3708 20:00:02.059739 Write leveling : PASS
3709 20:00:02.060252 RX DQS gating : PASS
3710 20:00:02.062385 RX DQ/DQS(RDDQC) : PASS
3711 20:00:02.065702 TX DQ/DQS : PASS
3712 20:00:02.066216 RX DATLAT : PASS
3713 20:00:02.069024 RX DQ/DQS(Engine): PASS
3714 20:00:02.072572 TX OE : NO K
3715 20:00:02.073086 All Pass.
3716 20:00:02.073412
3717 20:00:02.073714 CH 1, Rank 1
3718 20:00:02.076200 SW Impedance : PASS
3719 20:00:02.078886 DUTY Scan : NO K
3720 20:00:02.079432 ZQ Calibration : PASS
3721 20:00:02.082701 Jitter Meter : NO K
3722 20:00:02.085676 CBT Training : PASS
3723 20:00:02.086103 Write leveling : PASS
3724 20:00:02.089308 RX DQS gating : PASS
3725 20:00:02.092105 RX DQ/DQS(RDDQC) : PASS
3726 20:00:02.092531 TX DQ/DQS : PASS
3727 20:00:02.095483 RX DATLAT : PASS
3728 20:00:02.099213 RX DQ/DQS(Engine): PASS
3729 20:00:02.099975 TX OE : NO K
3730 20:00:02.100424 All Pass.
3731 20:00:02.102257
3732 20:00:02.102663 DramC Write-DBI off
3733 20:00:02.105251 PER_BANK_REFRESH: Hybrid Mode
3734 20:00:02.105662 TX_TRACKING: ON
3735 20:00:02.115602 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3736 20:00:02.119281 [FAST_K] Save calibration result to emmc
3737 20:00:02.122967 dramc_set_vcore_voltage set vcore to 650000
3738 20:00:02.125481 Read voltage for 600, 5
3739 20:00:02.125892 Vio18 = 0
3740 20:00:02.129164 Vcore = 650000
3741 20:00:02.129672 Vdram = 0
3742 20:00:02.130000 Vddq = 0
3743 20:00:02.130303 Vmddr = 0
3744 20:00:02.135934 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3745 20:00:02.142243 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3746 20:00:02.142754 MEM_TYPE=3, freq_sel=19
3747 20:00:02.145624 sv_algorithm_assistance_LP4_1600
3748 20:00:02.148694 ============ PULL DRAM RESETB DOWN ============
3749 20:00:02.155487 ========== PULL DRAM RESETB DOWN end =========
3750 20:00:02.158518 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3751 20:00:02.161628 ===================================
3752 20:00:02.164766 LPDDR4 DRAM CONFIGURATION
3753 20:00:02.168250 ===================================
3754 20:00:02.168761 EX_ROW_EN[0] = 0x0
3755 20:00:02.172015 EX_ROW_EN[1] = 0x0
3756 20:00:02.174905 LP4Y_EN = 0x0
3757 20:00:02.175442 WORK_FSP = 0x0
3758 20:00:02.178971 WL = 0x2
3759 20:00:02.179540 RL = 0x2
3760 20:00:02.181461 BL = 0x2
3761 20:00:02.181968 RPST = 0x0
3762 20:00:02.184557 RD_PRE = 0x0
3763 20:00:02.185017 WR_PRE = 0x1
3764 20:00:02.188245 WR_PST = 0x0
3765 20:00:02.188657 DBI_WR = 0x0
3766 20:00:02.191416 DBI_RD = 0x0
3767 20:00:02.191833 OTF = 0x1
3768 20:00:02.195247 ===================================
3769 20:00:02.198281 ===================================
3770 20:00:02.201314 ANA top config
3771 20:00:02.204627 ===================================
3772 20:00:02.205226 DLL_ASYNC_EN = 0
3773 20:00:02.207842 ALL_SLAVE_EN = 1
3774 20:00:02.211581 NEW_RANK_MODE = 1
3775 20:00:02.215076 DLL_IDLE_MODE = 1
3776 20:00:02.218194 LP45_APHY_COMB_EN = 1
3777 20:00:02.218649 TX_ODT_DIS = 1
3778 20:00:02.220990 NEW_8X_MODE = 1
3779 20:00:02.224714 ===================================
3780 20:00:02.228339 ===================================
3781 20:00:02.231591 data_rate = 1200
3782 20:00:02.235234 CKR = 1
3783 20:00:02.238159 DQ_P2S_RATIO = 8
3784 20:00:02.241696 ===================================
3785 20:00:02.242227 CA_P2S_RATIO = 8
3786 20:00:02.244162 DQ_CA_OPEN = 0
3787 20:00:02.248020 DQ_SEMI_OPEN = 0
3788 20:00:02.251485 CA_SEMI_OPEN = 0
3789 20:00:02.255079 CA_FULL_RATE = 0
3790 20:00:02.257727 DQ_CKDIV4_EN = 1
3791 20:00:02.258240 CA_CKDIV4_EN = 1
3792 20:00:02.261061 CA_PREDIV_EN = 0
3793 20:00:02.264613 PH8_DLY = 0
3794 20:00:02.267917 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3795 20:00:02.271130 DQ_AAMCK_DIV = 4
3796 20:00:02.274633 CA_AAMCK_DIV = 4
3797 20:00:02.275143 CA_ADMCK_DIV = 4
3798 20:00:02.278103 DQ_TRACK_CA_EN = 0
3799 20:00:02.281438 CA_PICK = 600
3800 20:00:02.284571 CA_MCKIO = 600
3801 20:00:02.287711 MCKIO_SEMI = 0
3802 20:00:02.295997 PLL_FREQ = 2288
3803 20:00:02.296323 DQ_UI_PI_RATIO = 32
3804 20:00:02.296402 CA_UI_PI_RATIO = 0
3805 20:00:02.297051 ===================================
3806 20:00:02.300224 ===================================
3807 20:00:02.303772 memory_type:LPDDR4
3808 20:00:02.307012 GP_NUM : 10
3809 20:00:02.307095 SRAM_EN : 1
3810 20:00:02.310725 MD32_EN : 0
3811 20:00:02.313927 ===================================
3812 20:00:02.316759 [ANA_INIT] >>>>>>>>>>>>>>
3813 20:00:02.320222 <<<<<< [CONFIGURE PHASE]: ANA_TX
3814 20:00:02.323771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3815 20:00:02.327031 ===================================
3816 20:00:02.327185 data_rate = 1200,PCW = 0X5800
3817 20:00:02.330398 ===================================
3818 20:00:02.337034 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3819 20:00:02.340003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 20:00:02.347128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 20:00:02.350728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3822 20:00:02.353781 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3823 20:00:02.357126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3824 20:00:02.360730 [ANA_INIT] flow start
3825 20:00:02.363916 [ANA_INIT] PLL >>>>>>>>
3826 20:00:02.364276 [ANA_INIT] PLL <<<<<<<<
3827 20:00:02.366954 [ANA_INIT] MIDPI >>>>>>>>
3828 20:00:02.370377 [ANA_INIT] MIDPI <<<<<<<<
3829 20:00:02.370810 [ANA_INIT] DLL >>>>>>>>
3830 20:00:02.373492 [ANA_INIT] flow end
3831 20:00:02.377134 ============ LP4 DIFF to SE enter ============
3832 20:00:02.380004 ============ LP4 DIFF to SE exit ============
3833 20:00:02.383739 [ANA_INIT] <<<<<<<<<<<<<
3834 20:00:02.386915 [Flow] Enable top DCM control >>>>>
3835 20:00:02.390320 [Flow] Enable top DCM control <<<<<
3836 20:00:02.393564 Enable DLL master slave shuffle
3837 20:00:02.399985 ==============================================================
3838 20:00:02.400413 Gating Mode config
3839 20:00:02.406864 ==============================================================
3840 20:00:02.410005 Config description:
3841 20:00:02.416828 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3842 20:00:02.423184 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3843 20:00:02.429722 SELPH_MODE 0: By rank 1: By Phase
3844 20:00:02.436564 ==============================================================
3845 20:00:02.437078 GAT_TRACK_EN = 1
3846 20:00:02.440028 RX_GATING_MODE = 2
3847 20:00:02.443241 RX_GATING_TRACK_MODE = 2
3848 20:00:02.446909 SELPH_MODE = 1
3849 20:00:02.450207 PICG_EARLY_EN = 1
3850 20:00:02.453312 VALID_LAT_VALUE = 1
3851 20:00:02.460209 ==============================================================
3852 20:00:02.463233 Enter into Gating configuration >>>>
3853 20:00:02.466355 Exit from Gating configuration <<<<
3854 20:00:02.470150 Enter into DVFS_PRE_config >>>>>
3855 20:00:02.479845 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3856 20:00:02.483069 Exit from DVFS_PRE_config <<<<<
3857 20:00:02.486692 Enter into PICG configuration >>>>
3858 20:00:02.489981 Exit from PICG configuration <<<<
3859 20:00:02.493146 [RX_INPUT] configuration >>>>>
3860 20:00:02.493646 [RX_INPUT] configuration <<<<<
3861 20:00:02.499920 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3862 20:00:02.506806 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3863 20:00:02.510192 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3864 20:00:02.516375 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3865 20:00:02.523508 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 20:00:02.529433 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 20:00:02.532603 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3868 20:00:02.536367 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3869 20:00:02.543002 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3870 20:00:02.545713 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3871 20:00:02.549036 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3872 20:00:02.555837 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 20:00:02.559083 ===================================
3874 20:00:02.559647 LPDDR4 DRAM CONFIGURATION
3875 20:00:02.562330 ===================================
3876 20:00:02.566320 EX_ROW_EN[0] = 0x0
3877 20:00:02.568568 EX_ROW_EN[1] = 0x0
3878 20:00:02.569101 LP4Y_EN = 0x0
3879 20:00:02.572088 WORK_FSP = 0x0
3880 20:00:02.572608 WL = 0x2
3881 20:00:02.575519 RL = 0x2
3882 20:00:02.576033 BL = 0x2
3883 20:00:02.578666 RPST = 0x0
3884 20:00:02.579090 RD_PRE = 0x0
3885 20:00:02.581956 WR_PRE = 0x1
3886 20:00:02.582363 WR_PST = 0x0
3887 20:00:02.585208 DBI_WR = 0x0
3888 20:00:02.585613 DBI_RD = 0x0
3889 20:00:02.588811 OTF = 0x1
3890 20:00:02.592380 ===================================
3891 20:00:02.595119 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3892 20:00:02.598734 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3893 20:00:02.605429 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 20:00:02.608233 ===================================
3895 20:00:02.608645 LPDDR4 DRAM CONFIGURATION
3896 20:00:02.612161 ===================================
3897 20:00:02.615629 EX_ROW_EN[0] = 0x10
3898 20:00:02.619102 EX_ROW_EN[1] = 0x0
3899 20:00:02.619730 LP4Y_EN = 0x0
3900 20:00:02.622274 WORK_FSP = 0x0
3901 20:00:02.622781 WL = 0x2
3902 20:00:02.625296 RL = 0x2
3903 20:00:02.625798 BL = 0x2
3904 20:00:02.628910 RPST = 0x0
3905 20:00:02.629413 RD_PRE = 0x0
3906 20:00:02.632196 WR_PRE = 0x1
3907 20:00:02.632607 WR_PST = 0x0
3908 20:00:02.635226 DBI_WR = 0x0
3909 20:00:02.635782 DBI_RD = 0x0
3910 20:00:02.638969 OTF = 0x1
3911 20:00:02.641934 ===================================
3912 20:00:02.647947 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3913 20:00:02.651627 nWR fixed to 30
3914 20:00:02.652140 [ModeRegInit_LP4] CH0 RK0
3915 20:00:02.655293 [ModeRegInit_LP4] CH0 RK1
3916 20:00:02.658793 [ModeRegInit_LP4] CH1 RK0
3917 20:00:02.662122 [ModeRegInit_LP4] CH1 RK1
3918 20:00:02.662726 match AC timing 17
3919 20:00:02.668009 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3920 20:00:02.672031 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3921 20:00:02.674894 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3922 20:00:02.681850 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3923 20:00:02.684254 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3924 20:00:02.684666 ==
3925 20:00:02.687708 Dram Type= 6, Freq= 0, CH_0, rank 0
3926 20:00:02.692190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 20:00:02.692700 ==
3928 20:00:02.697697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 20:00:02.704135 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3930 20:00:02.707735 [CA 0] Center 37 (7~67) winsize 61
3931 20:00:02.711119 [CA 1] Center 36 (6~67) winsize 62
3932 20:00:02.714054 [CA 2] Center 35 (5~65) winsize 61
3933 20:00:02.717315 [CA 3] Center 35 (5~65) winsize 61
3934 20:00:02.721295 [CA 4] Center 34 (4~65) winsize 62
3935 20:00:02.724066 [CA 5] Center 34 (4~64) winsize 61
3936 20:00:02.724477
3937 20:00:02.727492 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3938 20:00:02.727995
3939 20:00:02.731264 [CATrainingPosCal] consider 1 rank data
3940 20:00:02.734349 u2DelayCellTimex100 = 270/100 ps
3941 20:00:02.737783 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3942 20:00:02.740979 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3943 20:00:02.744326 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3944 20:00:02.747600 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3945 20:00:02.750995 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3946 20:00:02.754071 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3947 20:00:02.756990
3948 20:00:02.760480 CA PerBit enable=1, Macro0, CA PI delay=34
3949 20:00:02.761038
3950 20:00:02.763900 [CBTSetCACLKResult] CA Dly = 34
3951 20:00:02.764313 CS Dly: 6 (0~37)
3952 20:00:02.764638 ==
3953 20:00:02.767524 Dram Type= 6, Freq= 0, CH_0, rank 1
3954 20:00:02.770606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 20:00:02.771119 ==
3956 20:00:02.777256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 20:00:02.783635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3958 20:00:02.787606 [CA 0] Center 37 (7~67) winsize 61
3959 20:00:02.790522 [CA 1] Center 37 (7~67) winsize 61
3960 20:00:02.793824 [CA 2] Center 35 (5~65) winsize 61
3961 20:00:02.797166 [CA 3] Center 34 (4~65) winsize 62
3962 20:00:02.800292 [CA 4] Center 34 (4~64) winsize 61
3963 20:00:02.803626 [CA 5] Center 33 (3~64) winsize 62
3964 20:00:02.804160
3965 20:00:02.807468 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3966 20:00:02.808054
3967 20:00:02.810162 [CATrainingPosCal] consider 2 rank data
3968 20:00:02.813249 u2DelayCellTimex100 = 270/100 ps
3969 20:00:02.816673 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3970 20:00:02.820156 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3971 20:00:02.823791 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3972 20:00:02.830187 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3973 20:00:02.833202 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3974 20:00:02.836545 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3975 20:00:02.837054
3976 20:00:02.839766 CA PerBit enable=1, Macro0, CA PI delay=34
3977 20:00:02.840195
3978 20:00:02.843041 [CBTSetCACLKResult] CA Dly = 34
3979 20:00:02.843640 CS Dly: 6 (0~38)
3980 20:00:02.843979
3981 20:00:02.846649 ----->DramcWriteLeveling(PI) begin...
3982 20:00:02.850096 ==
3983 20:00:02.850612 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 20:00:02.856069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 20:00:02.856581 ==
3986 20:00:02.859499 Write leveling (Byte 0): 34 => 34
3987 20:00:02.862922 Write leveling (Byte 1): 31 => 31
3988 20:00:02.866400 DramcWriteLeveling(PI) end<-----
3989 20:00:02.866904
3990 20:00:02.867229 ==
3991 20:00:02.869654 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 20:00:02.873538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 20:00:02.874053 ==
3994 20:00:02.876630 [Gating] SW mode calibration
3995 20:00:02.883267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3996 20:00:02.889533 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3997 20:00:02.893133 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 20:00:02.895772 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 20:00:02.899094 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 20:00:02.906593 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4001 20:00:02.908902 0 9 16 | B1->B0 | 3131 2e2e | 0 0 | (1 1) (1 1)
4002 20:00:02.912699 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 20:00:02.919677 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 20:00:02.922596 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 20:00:02.926362 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 20:00:02.933007 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 20:00:02.935654 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 20:00:02.939051 0 10 12 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
4009 20:00:02.945963 0 10 16 | B1->B0 | 3232 3838 | 0 0 | (0 0) (0 0)
4010 20:00:02.948868 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 20:00:02.952280 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 20:00:02.958848 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 20:00:02.962299 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 20:00:02.965513 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 20:00:02.972263 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 20:00:02.975522 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 20:00:02.978425 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4018 20:00:02.985539 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 20:00:02.988807 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 20:00:02.992283 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 20:00:02.998778 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 20:00:03.002287 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 20:00:03.005287 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 20:00:03.011850 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 20:00:03.015316 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 20:00:03.018275 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 20:00:03.025015 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 20:00:03.028063 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 20:00:03.031505 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 20:00:03.038425 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 20:00:03.042252 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 20:00:03.044944 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4033 20:00:03.051680 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4034 20:00:03.052186 Total UI for P1: 0, mck2ui 16
4035 20:00:03.058777 best dqsien dly found for B0: ( 0, 13, 12)
4036 20:00:03.062343 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 20:00:03.065313 Total UI for P1: 0, mck2ui 16
4038 20:00:03.068317 best dqsien dly found for B1: ( 0, 13, 18)
4039 20:00:03.071732 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4040 20:00:03.074575 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4041 20:00:03.075078
4042 20:00:03.078129 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4043 20:00:03.081174 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4044 20:00:03.084840 [Gating] SW calibration Done
4045 20:00:03.085346 ==
4046 20:00:03.088272 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 20:00:03.091644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 20:00:03.095036 ==
4049 20:00:03.095585 RX Vref Scan: 0
4050 20:00:03.095920
4051 20:00:03.097814 RX Vref 0 -> 0, step: 1
4052 20:00:03.098245
4053 20:00:03.101360 RX Delay -230 -> 252, step: 16
4054 20:00:03.104778 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4055 20:00:03.108257 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4056 20:00:03.111787 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4057 20:00:03.118456 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4058 20:00:03.121166 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4059 20:00:03.124950 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4060 20:00:03.128010 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4061 20:00:03.131637 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4062 20:00:03.138593 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4063 20:00:03.141628 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4064 20:00:03.144580 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4065 20:00:03.147840 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4066 20:00:03.155061 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4067 20:00:03.157784 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4068 20:00:03.161461 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4069 20:00:03.164647 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4070 20:00:03.165061 ==
4071 20:00:03.168236 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 20:00:03.174882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 20:00:03.175446 ==
4074 20:00:03.175859 DQS Delay:
4075 20:00:03.178295 DQS0 = 0, DQS1 = 0
4076 20:00:03.178799 DQM Delay:
4077 20:00:03.179127 DQM0 = 37, DQM1 = 28
4078 20:00:03.181212 DQ Delay:
4079 20:00:03.184331 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4080 20:00:03.188195 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4081 20:00:03.191330 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4082 20:00:03.194307 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4083 20:00:03.194816
4084 20:00:03.195141
4085 20:00:03.195506 ==
4086 20:00:03.197345 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 20:00:03.200810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 20:00:03.201234 ==
4089 20:00:03.201696
4090 20:00:03.202141
4091 20:00:03.204340 TX Vref Scan disable
4092 20:00:03.207332 == TX Byte 0 ==
4093 20:00:03.210830 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4094 20:00:03.213778 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4095 20:00:03.217846 == TX Byte 1 ==
4096 20:00:03.220770 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4097 20:00:03.224044 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4098 20:00:03.224459 ==
4099 20:00:03.227751 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 20:00:03.230572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 20:00:03.234089 ==
4102 20:00:03.234598
4103 20:00:03.234928
4104 20:00:03.235235 TX Vref Scan disable
4105 20:00:03.237760 == TX Byte 0 ==
4106 20:00:03.241376 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4107 20:00:03.248016 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4108 20:00:03.248536 == TX Byte 1 ==
4109 20:00:03.251543 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4110 20:00:03.257609 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4111 20:00:03.258116
4112 20:00:03.258445 [DATLAT]
4113 20:00:03.258748 Freq=600, CH0 RK0
4114 20:00:03.259047
4115 20:00:03.261162 DATLAT Default: 0x9
4116 20:00:03.261698 0, 0xFFFF, sum = 0
4117 20:00:03.263949 1, 0xFFFF, sum = 0
4118 20:00:03.264371 2, 0xFFFF, sum = 0
4119 20:00:03.268069 3, 0xFFFF, sum = 0
4120 20:00:03.270683 4, 0xFFFF, sum = 0
4121 20:00:03.271105 5, 0xFFFF, sum = 0
4122 20:00:03.274540 6, 0xFFFF, sum = 0
4123 20:00:03.275062 7, 0xFFFF, sum = 0
4124 20:00:03.278102 8, 0x0, sum = 1
4125 20:00:03.278626 9, 0x0, sum = 2
4126 20:00:03.278963 10, 0x0, sum = 3
4127 20:00:03.281338 11, 0x0, sum = 4
4128 20:00:03.281866 best_step = 9
4129 20:00:03.282199
4130 20:00:03.282500 ==
4131 20:00:03.283997 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 20:00:03.290979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 20:00:03.291517 ==
4134 20:00:03.291853 RX Vref Scan: 1
4135 20:00:03.292160
4136 20:00:03.294091 RX Vref 0 -> 0, step: 1
4137 20:00:03.294610
4138 20:00:03.297282 RX Delay -195 -> 252, step: 8
4139 20:00:03.297776
4140 20:00:03.300712 Set Vref, RX VrefLevel [Byte0]: 61
4141 20:00:03.304015 [Byte1]: 52
4142 20:00:03.304430
4143 20:00:03.307221 Final RX Vref Byte 0 = 61 to rank0
4144 20:00:03.310499 Final RX Vref Byte 1 = 52 to rank0
4145 20:00:03.314274 Final RX Vref Byte 0 = 61 to rank1
4146 20:00:03.317573 Final RX Vref Byte 1 = 52 to rank1==
4147 20:00:03.321090 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 20:00:03.323850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 20:00:03.324271 ==
4150 20:00:03.327577 DQS Delay:
4151 20:00:03.328085 DQS0 = 0, DQS1 = 0
4152 20:00:03.330746 DQM Delay:
4153 20:00:03.331252 DQM0 = 36, DQM1 = 29
4154 20:00:03.331674 DQ Delay:
4155 20:00:03.334331 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4156 20:00:03.337184 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =48
4157 20:00:03.340573 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
4158 20:00:03.343928 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4159 20:00:03.344444
4160 20:00:03.344777
4161 20:00:03.353780 [DQSOSCAuto] RK0, (LSB)MR18= 0x4040, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4162 20:00:03.357442 CH0 RK0: MR19=808, MR18=4040
4163 20:00:03.364017 CH0_RK0: MR19=0x808, MR18=0x4040, DQSOSC=397, MR23=63, INC=166, DEC=110
4164 20:00:03.364603
4165 20:00:03.367359 ----->DramcWriteLeveling(PI) begin...
4166 20:00:03.367921 ==
4167 20:00:03.370875 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 20:00:03.374009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 20:00:03.374527 ==
4170 20:00:03.377613 Write leveling (Byte 0): 35 => 35
4171 20:00:03.381043 Write leveling (Byte 1): 30 => 30
4172 20:00:03.384308 DramcWriteLeveling(PI) end<-----
4173 20:00:03.384821
4174 20:00:03.385146 ==
4175 20:00:03.387535 Dram Type= 6, Freq= 0, CH_0, rank 1
4176 20:00:03.390818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 20:00:03.391241 ==
4178 20:00:03.394123 [Gating] SW mode calibration
4179 20:00:03.400267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4180 20:00:03.407521 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4181 20:00:03.410473 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 20:00:03.413835 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 20:00:03.420190 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 20:00:03.423662 0 9 12 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
4185 20:00:03.427143 0 9 16 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
4186 20:00:03.433775 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 20:00:03.437476 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 20:00:03.440109 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 20:00:03.444307 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 20:00:03.450131 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 20:00:03.453807 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 20:00:03.457412 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4193 20:00:03.463590 0 10 16 | B1->B0 | 3737 4545 | 0 0 | (0 0) (1 1)
4194 20:00:03.466864 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 20:00:03.470242 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 20:00:03.476968 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 20:00:03.480265 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 20:00:03.483225 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 20:00:03.490258 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 20:00:03.493647 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 20:00:03.496680 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4202 20:00:03.502988 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 20:00:03.506484 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 20:00:03.510259 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 20:00:03.516239 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 20:00:03.519845 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 20:00:03.523374 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 20:00:03.530057 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 20:00:03.533300 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 20:00:03.536272 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 20:00:03.542931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 20:00:03.546144 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 20:00:03.549695 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 20:00:03.556336 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 20:00:03.559707 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 20:00:03.562685 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4217 20:00:03.569553 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4218 20:00:03.573225 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 20:00:03.575872 Total UI for P1: 0, mck2ui 16
4220 20:00:03.579084 best dqsien dly found for B0: ( 0, 13, 14)
4221 20:00:03.583210 Total UI for P1: 0, mck2ui 16
4222 20:00:03.585853 best dqsien dly found for B1: ( 0, 13, 18)
4223 20:00:03.589661 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4224 20:00:03.593008 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4225 20:00:03.593522
4226 20:00:03.596059 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4227 20:00:03.599121 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4228 20:00:03.602822 [Gating] SW calibration Done
4229 20:00:03.603353 ==
4230 20:00:03.605682 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 20:00:03.609564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 20:00:03.612562 ==
4233 20:00:03.612984 RX Vref Scan: 0
4234 20:00:03.613311
4235 20:00:03.616069 RX Vref 0 -> 0, step: 1
4236 20:00:03.616481
4237 20:00:03.619444 RX Delay -230 -> 252, step: 16
4238 20:00:03.623158 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4239 20:00:03.625726 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4240 20:00:03.629181 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4241 20:00:03.635990 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4242 20:00:03.639242 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4243 20:00:03.642808 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4244 20:00:03.646159 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4245 20:00:03.649036 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4246 20:00:03.655310 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4247 20:00:03.659128 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4248 20:00:03.663003 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4249 20:00:03.665559 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4250 20:00:03.673023 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4251 20:00:03.675832 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4252 20:00:03.679305 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4253 20:00:03.682321 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4254 20:00:03.682839 ==
4255 20:00:03.685775 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 20:00:03.692431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 20:00:03.692959 ==
4258 20:00:03.693295 DQS Delay:
4259 20:00:03.696094 DQS0 = 0, DQS1 = 0
4260 20:00:03.696610 DQM Delay:
4261 20:00:03.698750 DQM0 = 36, DQM1 = 30
4262 20:00:03.699165 DQ Delay:
4263 20:00:03.701811 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4264 20:00:03.705261 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4265 20:00:03.709037 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4266 20:00:03.711821 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4267 20:00:03.712237
4268 20:00:03.712564
4269 20:00:03.712871 ==
4270 20:00:03.716007 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 20:00:03.718751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 20:00:03.719308 ==
4273 20:00:03.719705
4274 20:00:03.720016
4275 20:00:03.722409 TX Vref Scan disable
4276 20:00:03.726082 == TX Byte 0 ==
4277 20:00:03.728407 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4278 20:00:03.731718 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4279 20:00:03.735545 == TX Byte 1 ==
4280 20:00:03.738900 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4281 20:00:03.741923 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4282 20:00:03.742444 ==
4283 20:00:03.745248 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 20:00:03.748932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 20:00:03.751921 ==
4286 20:00:03.752439
4287 20:00:03.752765
4288 20:00:03.753070 TX Vref Scan disable
4289 20:00:03.756055 == TX Byte 0 ==
4290 20:00:03.759100 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4291 20:00:03.762965 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4292 20:00:03.765597 == TX Byte 1 ==
4293 20:00:03.769087 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4294 20:00:03.772613 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4295 20:00:03.775815
4296 20:00:03.776224 [DATLAT]
4297 20:00:03.776553 Freq=600, CH0 RK1
4298 20:00:03.776862
4299 20:00:03.779361 DATLAT Default: 0x9
4300 20:00:03.779812 0, 0xFFFF, sum = 0
4301 20:00:03.782108 1, 0xFFFF, sum = 0
4302 20:00:03.782524 2, 0xFFFF, sum = 0
4303 20:00:03.785759 3, 0xFFFF, sum = 0
4304 20:00:03.786177 4, 0xFFFF, sum = 0
4305 20:00:03.789030 5, 0xFFFF, sum = 0
4306 20:00:03.792565 6, 0xFFFF, sum = 0
4307 20:00:03.793099 7, 0xFFFF, sum = 0
4308 20:00:03.793437 8, 0x0, sum = 1
4309 20:00:03.795859 9, 0x0, sum = 2
4310 20:00:03.796375 10, 0x0, sum = 3
4311 20:00:03.799174 11, 0x0, sum = 4
4312 20:00:03.799644 best_step = 9
4313 20:00:03.799975
4314 20:00:03.800277 ==
4315 20:00:03.802224 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 20:00:03.809172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 20:00:03.809690 ==
4318 20:00:03.810111 RX Vref Scan: 0
4319 20:00:03.810594
4320 20:00:03.812254 RX Vref 0 -> 0, step: 1
4321 20:00:03.812668
4322 20:00:03.815805 RX Delay -195 -> 252, step: 8
4323 20:00:03.819250 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4324 20:00:03.825896 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4325 20:00:03.829233 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4326 20:00:03.832102 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4327 20:00:03.835935 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4328 20:00:03.842023 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4329 20:00:03.845750 iDelay=205, Bit 6, Center 40 (-123 ~ 204) 328
4330 20:00:03.848759 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4331 20:00:03.852349 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4332 20:00:03.855795 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4333 20:00:03.862271 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4334 20:00:03.865270 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4335 20:00:03.869595 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4336 20:00:03.872385 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4337 20:00:03.879078 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4338 20:00:03.882854 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4339 20:00:03.883368 ==
4340 20:00:03.886350 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 20:00:03.889147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 20:00:03.889682 ==
4343 20:00:03.892617 DQS Delay:
4344 20:00:03.893027 DQS0 = 0, DQS1 = 0
4345 20:00:03.893356 DQM Delay:
4346 20:00:03.895798 DQM0 = 33, DQM1 = 27
4347 20:00:03.896309 DQ Delay:
4348 20:00:03.898806 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4349 20:00:03.902386 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4350 20:00:03.905644 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4351 20:00:03.908941 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4352 20:00:03.909457
4353 20:00:03.909785
4354 20:00:03.919362 [DQSOSCAuto] RK1, (LSB)MR18= 0x6835, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4355 20:00:03.919966 CH0 RK1: MR19=808, MR18=6835
4356 20:00:03.925916 CH0_RK1: MR19=0x808, MR18=0x6835, DQSOSC=390, MR23=63, INC=172, DEC=114
4357 20:00:03.928510 [RxdqsGatingPostProcess] freq 600
4358 20:00:03.935882 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4359 20:00:03.938561 Pre-setting of DQS Precalculation
4360 20:00:03.941812 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4361 20:00:03.942320 ==
4362 20:00:03.945622 Dram Type= 6, Freq= 0, CH_1, rank 0
4363 20:00:03.951835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 20:00:03.952342 ==
4365 20:00:03.955256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 20:00:03.961522 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4367 20:00:03.965370 [CA 0] Center 35 (5~66) winsize 62
4368 20:00:03.968748 [CA 1] Center 36 (6~66) winsize 61
4369 20:00:03.971621 [CA 2] Center 34 (4~65) winsize 62
4370 20:00:03.975493 [CA 3] Center 34 (4~65) winsize 62
4371 20:00:03.978470 [CA 4] Center 34 (4~65) winsize 62
4372 20:00:03.982298 [CA 5] Center 34 (4~64) winsize 61
4373 20:00:03.982808
4374 20:00:03.985103 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4375 20:00:03.985607
4376 20:00:03.988695 [CATrainingPosCal] consider 1 rank data
4377 20:00:03.991574 u2DelayCellTimex100 = 270/100 ps
4378 20:00:03.994775 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4379 20:00:03.998008 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4380 20:00:04.004846 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 20:00:04.007669 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4382 20:00:04.011244 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4383 20:00:04.014791 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4384 20:00:04.015205
4385 20:00:04.018141 CA PerBit enable=1, Macro0, CA PI delay=34
4386 20:00:04.018559
4387 20:00:04.021692 [CBTSetCACLKResult] CA Dly = 34
4388 20:00:04.022105 CS Dly: 5 (0~36)
4389 20:00:04.022432 ==
4390 20:00:04.025344 Dram Type= 6, Freq= 0, CH_1, rank 1
4391 20:00:04.031917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 20:00:04.032430 ==
4393 20:00:04.034799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 20:00:04.041825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4395 20:00:04.045240 [CA 0] Center 35 (5~66) winsize 62
4396 20:00:04.048299 [CA 1] Center 36 (5~67) winsize 63
4397 20:00:04.051631 [CA 2] Center 34 (4~65) winsize 62
4398 20:00:04.055457 [CA 3] Center 34 (3~65) winsize 63
4399 20:00:04.058831 [CA 4] Center 34 (4~65) winsize 62
4400 20:00:04.061802 [CA 5] Center 33 (3~64) winsize 62
4401 20:00:04.062311
4402 20:00:04.064771 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4403 20:00:04.065276
4404 20:00:04.067927 [CATrainingPosCal] consider 2 rank data
4405 20:00:04.071667 u2DelayCellTimex100 = 270/100 ps
4406 20:00:04.074555 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4407 20:00:04.081514 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4408 20:00:04.084997 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4409 20:00:04.088209 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4410 20:00:04.091178 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4411 20:00:04.094582 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4412 20:00:04.095094
4413 20:00:04.098256 CA PerBit enable=1, Macro0, CA PI delay=34
4414 20:00:04.098764
4415 20:00:04.101888 [CBTSetCACLKResult] CA Dly = 34
4416 20:00:04.102404 CS Dly: 5 (0~36)
4417 20:00:04.102739
4418 20:00:04.107909 ----->DramcWriteLeveling(PI) begin...
4419 20:00:04.108422 ==
4420 20:00:04.111483 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 20:00:04.114779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 20:00:04.115423 ==
4423 20:00:04.117879 Write leveling (Byte 0): 29 => 29
4424 20:00:04.121725 Write leveling (Byte 1): 31 => 31
4425 20:00:04.124259 DramcWriteLeveling(PI) end<-----
4426 20:00:04.124679
4427 20:00:04.125006 ==
4428 20:00:04.128151 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 20:00:04.130945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 20:00:04.131498 ==
4431 20:00:04.134576 [Gating] SW mode calibration
4432 20:00:04.141136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4433 20:00:04.147437 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4434 20:00:04.151202 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 20:00:04.154870 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 20:00:04.161133 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 20:00:04.164625 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
4438 20:00:04.167777 0 9 16 | B1->B0 | 2929 2626 | 1 0 | (1 1) (1 0)
4439 20:00:04.174381 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 20:00:04.178015 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 20:00:04.180837 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 20:00:04.184069 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 20:00:04.190920 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 20:00:04.194544 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 20:00:04.197408 0 10 12 | B1->B0 | 2e2e 3030 | 0 0 | (0 0) (0 0)
4446 20:00:04.204060 0 10 16 | B1->B0 | 4545 3f3f | 0 0 | (0 0) (0 0)
4447 20:00:04.208006 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 20:00:04.210720 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 20:00:04.217229 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 20:00:04.220561 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 20:00:04.224129 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 20:00:04.230514 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 20:00:04.234380 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 20:00:04.237555 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 20:00:04.243620 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 20:00:04.247361 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 20:00:04.250922 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 20:00:04.257479 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 20:00:04.259986 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 20:00:04.263614 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 20:00:04.270091 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 20:00:04.273816 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 20:00:04.277086 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 20:00:04.283885 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 20:00:04.286706 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 20:00:04.290023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 20:00:04.296967 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 20:00:04.300054 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 20:00:04.303666 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 20:00:04.310899 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4471 20:00:04.313494 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 20:00:04.316915 Total UI for P1: 0, mck2ui 16
4473 20:00:04.319973 best dqsien dly found for B0: ( 0, 13, 16)
4474 20:00:04.323630 Total UI for P1: 0, mck2ui 16
4475 20:00:04.326703 best dqsien dly found for B1: ( 0, 13, 16)
4476 20:00:04.330099 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4477 20:00:04.333439 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4478 20:00:04.333952
4479 20:00:04.337139 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4480 20:00:04.340205 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4481 20:00:04.343743 [Gating] SW calibration Done
4482 20:00:04.344257 ==
4483 20:00:04.346647 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 20:00:04.350255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 20:00:04.353340 ==
4486 20:00:04.353852 RX Vref Scan: 0
4487 20:00:04.354186
4488 20:00:04.356550 RX Vref 0 -> 0, step: 1
4489 20:00:04.356985
4490 20:00:04.360024 RX Delay -230 -> 252, step: 16
4491 20:00:04.363577 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4492 20:00:04.366316 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4493 20:00:04.369464 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4494 20:00:04.376744 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4495 20:00:04.379911 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4496 20:00:04.383532 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4497 20:00:04.386147 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4498 20:00:04.389788 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4499 20:00:04.396425 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4500 20:00:04.399462 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4501 20:00:04.402919 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4502 20:00:04.406608 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4503 20:00:04.413228 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4504 20:00:04.415955 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4505 20:00:04.419352 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4506 20:00:04.423000 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4507 20:00:04.423587 ==
4508 20:00:04.426619 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 20:00:04.433108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 20:00:04.433658 ==
4511 20:00:04.434003 DQS Delay:
4512 20:00:04.436045 DQS0 = 0, DQS1 = 0
4513 20:00:04.436549 DQM Delay:
4514 20:00:04.436886 DQM0 = 39, DQM1 = 28
4515 20:00:04.439942 DQ Delay:
4516 20:00:04.443041 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4517 20:00:04.446387 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4518 20:00:04.449833 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4519 20:00:04.453014 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4520 20:00:04.453531
4521 20:00:04.453861
4522 20:00:04.454168 ==
4523 20:00:04.456158 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 20:00:04.459995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 20:00:04.460520 ==
4526 20:00:04.460855
4527 20:00:04.461163
4528 20:00:04.462513 TX Vref Scan disable
4529 20:00:04.462924 == TX Byte 0 ==
4530 20:00:04.469853 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4531 20:00:04.472912 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4532 20:00:04.476315 == TX Byte 1 ==
4533 20:00:04.479292 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4534 20:00:04.482856 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4535 20:00:04.483378 ==
4536 20:00:04.486325 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 20:00:04.489196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 20:00:04.489727 ==
4539 20:00:04.492506
4540 20:00:04.493022
4541 20:00:04.493354 TX Vref Scan disable
4542 20:00:04.496383 == TX Byte 0 ==
4543 20:00:04.499688 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4544 20:00:04.503156 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4545 20:00:04.506264 == TX Byte 1 ==
4546 20:00:04.509754 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4547 20:00:04.515970 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4548 20:00:04.516474
4549 20:00:04.516801 [DATLAT]
4550 20:00:04.517111 Freq=600, CH1 RK0
4551 20:00:04.517427
4552 20:00:04.519153 DATLAT Default: 0x9
4553 20:00:04.519605 0, 0xFFFF, sum = 0
4554 20:00:04.522735 1, 0xFFFF, sum = 0
4555 20:00:04.523292 2, 0xFFFF, sum = 0
4556 20:00:04.526112 3, 0xFFFF, sum = 0
4557 20:00:04.529278 4, 0xFFFF, sum = 0
4558 20:00:04.529807 5, 0xFFFF, sum = 0
4559 20:00:04.533191 6, 0xFFFF, sum = 0
4560 20:00:04.533715 7, 0xFFFF, sum = 0
4561 20:00:04.536164 8, 0x0, sum = 1
4562 20:00:04.536618 9, 0x0, sum = 2
4563 20:00:04.536959 10, 0x0, sum = 3
4564 20:00:04.539343 11, 0x0, sum = 4
4565 20:00:04.539938 best_step = 9
4566 20:00:04.540276
4567 20:00:04.540586 ==
4568 20:00:04.542396 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 20:00:04.549465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 20:00:04.549980 ==
4571 20:00:04.550314 RX Vref Scan: 1
4572 20:00:04.550627
4573 20:00:04.552853 RX Vref 0 -> 0, step: 1
4574 20:00:04.553270
4575 20:00:04.555696 RX Delay -195 -> 252, step: 8
4576 20:00:04.556116
4577 20:00:04.558970 Set Vref, RX VrefLevel [Byte0]: 53
4578 20:00:04.562657 [Byte1]: 49
4579 20:00:04.563171
4580 20:00:04.566307 Final RX Vref Byte 0 = 53 to rank0
4581 20:00:04.569249 Final RX Vref Byte 1 = 49 to rank0
4582 20:00:04.572457 Final RX Vref Byte 0 = 53 to rank1
4583 20:00:04.575510 Final RX Vref Byte 1 = 49 to rank1==
4584 20:00:04.579120 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 20:00:04.582185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 20:00:04.582719 ==
4587 20:00:04.584991 DQS Delay:
4588 20:00:04.585411 DQS0 = 0, DQS1 = 0
4589 20:00:04.588962 DQM Delay:
4590 20:00:04.589476 DQM0 = 38, DQM1 = 28
4591 20:00:04.590060 DQ Delay:
4592 20:00:04.591980 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4593 20:00:04.595316 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4594 20:00:04.598590 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4595 20:00:04.601670 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4596 20:00:04.602090
4597 20:00:04.602422
4598 20:00:04.611735 [DQSOSCAuto] RK0, (LSB)MR18= 0x2230, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4599 20:00:04.615065 CH1 RK0: MR19=808, MR18=2230
4600 20:00:04.621718 CH1_RK0: MR19=0x808, MR18=0x2230, DQSOSC=400, MR23=63, INC=163, DEC=109
4601 20:00:04.622146
4602 20:00:04.625598 ----->DramcWriteLeveling(PI) begin...
4603 20:00:04.626154 ==
4604 20:00:04.628178 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 20:00:04.631814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 20:00:04.632239 ==
4607 20:00:04.635098 Write leveling (Byte 0): 30 => 30
4608 20:00:04.638226 Write leveling (Byte 1): 30 => 30
4609 20:00:04.641618 DramcWriteLeveling(PI) end<-----
4610 20:00:04.642036
4611 20:00:04.642369 ==
4612 20:00:04.644832 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 20:00:04.648444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 20:00:04.648951 ==
4615 20:00:04.651569 [Gating] SW mode calibration
4616 20:00:04.658239 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4617 20:00:04.664820 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4618 20:00:04.667912 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 20:00:04.674838 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4620 20:00:04.677580 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4621 20:00:04.681427 0 9 12 | B1->B0 | 2f2f 2e2e | 0 1 | (0 1) (1 0)
4622 20:00:04.687783 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
4623 20:00:04.690978 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 20:00:04.694983 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 20:00:04.697989 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 20:00:04.704343 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 20:00:04.708194 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 20:00:04.711534 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4629 20:00:04.717575 0 10 12 | B1->B0 | 3131 4040 | 0 0 | (0 0) (0 0)
4630 20:00:04.721056 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
4631 20:00:04.724073 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 20:00:04.730776 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 20:00:04.734251 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 20:00:04.737649 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 20:00:04.744101 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 20:00:04.747494 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 20:00:04.750559 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4638 20:00:04.757490 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 20:00:04.760360 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 20:00:04.764033 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 20:00:04.769967 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 20:00:04.773866 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 20:00:04.776692 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 20:00:04.783221 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 20:00:04.786565 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 20:00:04.790896 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 20:00:04.797021 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 20:00:04.800517 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 20:00:04.803267 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 20:00:04.810071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 20:00:04.813547 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 20:00:04.816932 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 20:00:04.823570 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 20:00:04.824097 Total UI for P1: 0, mck2ui 16
4655 20:00:04.830551 best dqsien dly found for B0: ( 0, 13, 10)
4656 20:00:04.831068 Total UI for P1: 0, mck2ui 16
4657 20:00:04.836932 best dqsien dly found for B1: ( 0, 13, 10)
4658 20:00:04.839585 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4659 20:00:04.843332 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4660 20:00:04.843908
4661 20:00:04.846717 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4662 20:00:04.849441 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4663 20:00:04.853161 [Gating] SW calibration Done
4664 20:00:04.853674 ==
4665 20:00:04.856380 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 20:00:04.859759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 20:00:04.860182 ==
4668 20:00:04.862572 RX Vref Scan: 0
4669 20:00:04.862988
4670 20:00:04.863322 RX Vref 0 -> 0, step: 1
4671 20:00:04.866208
4672 20:00:04.866626 RX Delay -230 -> 252, step: 16
4673 20:00:04.873140 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4674 20:00:04.876481 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4675 20:00:04.880028 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4676 20:00:04.882604 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4677 20:00:04.889769 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4678 20:00:04.892710 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4679 20:00:04.896254 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4680 20:00:04.899649 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4681 20:00:04.903210 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4682 20:00:04.910190 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4683 20:00:04.912628 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4684 20:00:04.916807 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4685 20:00:04.919430 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4686 20:00:04.926041 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4687 20:00:04.928888 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4688 20:00:04.932443 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4689 20:00:04.932896 ==
4690 20:00:04.935702 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 20:00:04.939346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 20:00:04.942520 ==
4693 20:00:04.943037 DQS Delay:
4694 20:00:04.943376 DQS0 = 0, DQS1 = 0
4695 20:00:04.945567 DQM Delay:
4696 20:00:04.945982 DQM0 = 36, DQM1 = 29
4697 20:00:04.949311 DQ Delay:
4698 20:00:04.949824 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4699 20:00:04.952998 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4700 20:00:04.956104 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4701 20:00:04.959299 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4702 20:00:04.962537
4703 20:00:04.963049
4704 20:00:04.963382 ==
4705 20:00:04.965912 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 20:00:04.968681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 20:00:04.969101 ==
4708 20:00:04.969435
4709 20:00:04.969744
4710 20:00:04.971884 TX Vref Scan disable
4711 20:00:04.972300 == TX Byte 0 ==
4712 20:00:04.979451 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4713 20:00:04.982306 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4714 20:00:04.982820 == TX Byte 1 ==
4715 20:00:04.988772 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4716 20:00:04.992331 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4717 20:00:04.992853 ==
4718 20:00:04.995641 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 20:00:04.998700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 20:00:04.999121 ==
4721 20:00:04.999515
4722 20:00:04.999841
4723 20:00:05.001885 TX Vref Scan disable
4724 20:00:05.005255 == TX Byte 0 ==
4725 20:00:05.008874 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4726 20:00:05.012342 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4727 20:00:05.015509 == TX Byte 1 ==
4728 20:00:05.018674 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4729 20:00:05.023702 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4730 20:00:05.024123
4731 20:00:05.025131 [DATLAT]
4732 20:00:05.025549 Freq=600, CH1 RK1
4733 20:00:05.025884
4734 20:00:05.028580 DATLAT Default: 0x9
4735 20:00:05.029001 0, 0xFFFF, sum = 0
4736 20:00:05.032345 1, 0xFFFF, sum = 0
4737 20:00:05.032880 2, 0xFFFF, sum = 0
4738 20:00:05.035534 3, 0xFFFF, sum = 0
4739 20:00:05.036054 4, 0xFFFF, sum = 0
4740 20:00:05.038821 5, 0xFFFF, sum = 0
4741 20:00:05.039427 6, 0xFFFF, sum = 0
4742 20:00:05.042214 7, 0xFFFF, sum = 0
4743 20:00:05.042735 8, 0x0, sum = 1
4744 20:00:05.045520 9, 0x0, sum = 2
4745 20:00:05.046039 10, 0x0, sum = 3
4746 20:00:05.048669 11, 0x0, sum = 4
4747 20:00:05.049211 best_step = 9
4748 20:00:05.049555
4749 20:00:05.049865 ==
4750 20:00:05.052650 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 20:00:05.058798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 20:00:05.059316 ==
4753 20:00:05.059806 RX Vref Scan: 0
4754 20:00:05.060136
4755 20:00:05.062134 RX Vref 0 -> 0, step: 1
4756 20:00:05.062551
4757 20:00:05.065470 RX Delay -195 -> 252, step: 8
4758 20:00:05.068144 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4759 20:00:05.075066 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4760 20:00:05.078320 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4761 20:00:05.082036 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4762 20:00:05.085607 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4763 20:00:05.088734 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4764 20:00:05.095867 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4765 20:00:05.098481 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4766 20:00:05.101730 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4767 20:00:05.104928 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4768 20:00:05.111456 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4769 20:00:05.115435 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4770 20:00:05.118594 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4771 20:00:05.122343 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4772 20:00:05.128345 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4773 20:00:05.131671 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4774 20:00:05.132224 ==
4775 20:00:05.135122 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 20:00:05.138246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 20:00:05.138766 ==
4778 20:00:05.141848 DQS Delay:
4779 20:00:05.142366 DQS0 = 0, DQS1 = 0
4780 20:00:05.142702 DQM Delay:
4781 20:00:05.145058 DQM0 = 36, DQM1 = 30
4782 20:00:05.145579 DQ Delay:
4783 20:00:05.148237 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4784 20:00:05.151273 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =32
4785 20:00:05.154966 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4786 20:00:05.158480 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =36
4787 20:00:05.158997
4788 20:00:05.159329
4789 20:00:05.168253 [DQSOSCAuto] RK1, (LSB)MR18= 0x3959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4790 20:00:05.168820 CH1 RK1: MR19=808, MR18=3959
4791 20:00:05.174826 CH1_RK1: MR19=0x808, MR18=0x3959, DQSOSC=393, MR23=63, INC=169, DEC=113
4792 20:00:05.178360 [RxdqsGatingPostProcess] freq 600
4793 20:00:05.184598 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4794 20:00:05.188048 Pre-setting of DQS Precalculation
4795 20:00:05.191566 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4796 20:00:05.197801 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4797 20:00:05.207545 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4798 20:00:05.208060
4799 20:00:05.208391
4800 20:00:05.211106 [Calibration Summary] 1200 Mbps
4801 20:00:05.211675 CH 0, Rank 0
4802 20:00:05.214598 SW Impedance : PASS
4803 20:00:05.215016 DUTY Scan : NO K
4804 20:00:05.217448 ZQ Calibration : PASS
4805 20:00:05.220573 Jitter Meter : NO K
4806 20:00:05.220992 CBT Training : PASS
4807 20:00:05.224403 Write leveling : PASS
4808 20:00:05.227306 RX DQS gating : PASS
4809 20:00:05.227783 RX DQ/DQS(RDDQC) : PASS
4810 20:00:05.231313 TX DQ/DQS : PASS
4811 20:00:05.231878 RX DATLAT : PASS
4812 20:00:05.234113 RX DQ/DQS(Engine): PASS
4813 20:00:05.237655 TX OE : NO K
4814 20:00:05.238173 All Pass.
4815 20:00:05.238504
4816 20:00:05.238812 CH 0, Rank 1
4817 20:00:05.241021 SW Impedance : PASS
4818 20:00:05.244369 DUTY Scan : NO K
4819 20:00:05.244882 ZQ Calibration : PASS
4820 20:00:05.248161 Jitter Meter : NO K
4821 20:00:05.250956 CBT Training : PASS
4822 20:00:05.251515 Write leveling : PASS
4823 20:00:05.254381 RX DQS gating : PASS
4824 20:00:05.258084 RX DQ/DQS(RDDQC) : PASS
4825 20:00:05.258593 TX DQ/DQS : PASS
4826 20:00:05.261378 RX DATLAT : PASS
4827 20:00:05.264095 RX DQ/DQS(Engine): PASS
4828 20:00:05.264512 TX OE : NO K
4829 20:00:05.264843 All Pass.
4830 20:00:05.267842
4831 20:00:05.268352 CH 1, Rank 0
4832 20:00:05.271263 SW Impedance : PASS
4833 20:00:05.271722 DUTY Scan : NO K
4834 20:00:05.273991 ZQ Calibration : PASS
4835 20:00:05.274410 Jitter Meter : NO K
4836 20:00:05.278042 CBT Training : PASS
4837 20:00:05.280878 Write leveling : PASS
4838 20:00:05.281396 RX DQS gating : PASS
4839 20:00:05.283989 RX DQ/DQS(RDDQC) : PASS
4840 20:00:05.287895 TX DQ/DQS : PASS
4841 20:00:05.288409 RX DATLAT : PASS
4842 20:00:05.291082 RX DQ/DQS(Engine): PASS
4843 20:00:05.294237 TX OE : NO K
4844 20:00:05.294757 All Pass.
4845 20:00:05.295095
4846 20:00:05.295441 CH 1, Rank 1
4847 20:00:05.297795 SW Impedance : PASS
4848 20:00:05.300503 DUTY Scan : NO K
4849 20:00:05.300923 ZQ Calibration : PASS
4850 20:00:05.303754 Jitter Meter : NO K
4851 20:00:05.307373 CBT Training : PASS
4852 20:00:05.307827 Write leveling : PASS
4853 20:00:05.310610 RX DQS gating : PASS
4854 20:00:05.314262 RX DQ/DQS(RDDQC) : PASS
4855 20:00:05.314774 TX DQ/DQS : PASS
4856 20:00:05.317134 RX DATLAT : PASS
4857 20:00:05.320844 RX DQ/DQS(Engine): PASS
4858 20:00:05.321264 TX OE : NO K
4859 20:00:05.321597 All Pass.
4860 20:00:05.323740
4861 20:00:05.324160 DramC Write-DBI off
4862 20:00:05.327114 PER_BANK_REFRESH: Hybrid Mode
4863 20:00:05.327560 TX_TRACKING: ON
4864 20:00:05.337461 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4865 20:00:05.340289 [FAST_K] Save calibration result to emmc
4866 20:00:05.343711 dramc_set_vcore_voltage set vcore to 662500
4867 20:00:05.347133 Read voltage for 933, 3
4868 20:00:05.347696 Vio18 = 0
4869 20:00:05.350251 Vcore = 662500
4870 20:00:05.350684 Vdram = 0
4871 20:00:05.351028 Vddq = 0
4872 20:00:05.351339 Vmddr = 0
4873 20:00:05.357137 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4874 20:00:05.363962 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4875 20:00:05.364485 MEM_TYPE=3, freq_sel=17
4876 20:00:05.367267 sv_algorithm_assistance_LP4_1600
4877 20:00:05.370193 ============ PULL DRAM RESETB DOWN ============
4878 20:00:05.377583 ========== PULL DRAM RESETB DOWN end =========
4879 20:00:05.380374 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4880 20:00:05.383928 ===================================
4881 20:00:05.387169 LPDDR4 DRAM CONFIGURATION
4882 20:00:05.390145 ===================================
4883 20:00:05.390564 EX_ROW_EN[0] = 0x0
4884 20:00:05.393487 EX_ROW_EN[1] = 0x0
4885 20:00:05.393903 LP4Y_EN = 0x0
4886 20:00:05.396860 WORK_FSP = 0x0
4887 20:00:05.397279 WL = 0x3
4888 20:00:05.400279 RL = 0x3
4889 20:00:05.403160 BL = 0x2
4890 20:00:05.403630 RPST = 0x0
4891 20:00:05.406918 RD_PRE = 0x0
4892 20:00:05.407335 WR_PRE = 0x1
4893 20:00:05.409877 WR_PST = 0x0
4894 20:00:05.410292 DBI_WR = 0x0
4895 20:00:05.413587 DBI_RD = 0x0
4896 20:00:05.414109 OTF = 0x1
4897 20:00:05.416774 ===================================
4898 20:00:05.419574 ===================================
4899 20:00:05.423223 ANA top config
4900 20:00:05.427165 ===================================
4901 20:00:05.427744 DLL_ASYNC_EN = 0
4902 20:00:05.429677 ALL_SLAVE_EN = 1
4903 20:00:05.433368 NEW_RANK_MODE = 1
4904 20:00:05.436276 DLL_IDLE_MODE = 1
4905 20:00:05.436698 LP45_APHY_COMB_EN = 1
4906 20:00:05.439934 TX_ODT_DIS = 1
4907 20:00:05.442778 NEW_8X_MODE = 1
4908 20:00:05.446652 ===================================
4909 20:00:05.449983 ===================================
4910 20:00:05.452985 data_rate = 1866
4911 20:00:05.456195 CKR = 1
4912 20:00:05.459470 DQ_P2S_RATIO = 8
4913 20:00:05.463314 ===================================
4914 20:00:05.463784 CA_P2S_RATIO = 8
4915 20:00:05.466482 DQ_CA_OPEN = 0
4916 20:00:05.469503 DQ_SEMI_OPEN = 0
4917 20:00:05.473139 CA_SEMI_OPEN = 0
4918 20:00:05.475909 CA_FULL_RATE = 0
4919 20:00:05.479635 DQ_CKDIV4_EN = 1
4920 20:00:05.480050 CA_CKDIV4_EN = 1
4921 20:00:05.482893 CA_PREDIV_EN = 0
4922 20:00:05.486399 PH8_DLY = 0
4923 20:00:05.489403 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4924 20:00:05.493306 DQ_AAMCK_DIV = 4
4925 20:00:05.496197 CA_AAMCK_DIV = 4
4926 20:00:05.496618 CA_ADMCK_DIV = 4
4927 20:00:05.499381 DQ_TRACK_CA_EN = 0
4928 20:00:05.502578 CA_PICK = 933
4929 20:00:05.506609 CA_MCKIO = 933
4930 20:00:05.509714 MCKIO_SEMI = 0
4931 20:00:05.513287 PLL_FREQ = 3732
4932 20:00:05.516614 DQ_UI_PI_RATIO = 32
4933 20:00:05.517135 CA_UI_PI_RATIO = 0
4934 20:00:05.519060 ===================================
4935 20:00:05.522895 ===================================
4936 20:00:05.526593 memory_type:LPDDR4
4937 20:00:05.529579 GP_NUM : 10
4938 20:00:05.530104 SRAM_EN : 1
4939 20:00:05.533128 MD32_EN : 0
4940 20:00:05.535749 ===================================
4941 20:00:05.539103 [ANA_INIT] >>>>>>>>>>>>>>
4942 20:00:05.542779 <<<<<< [CONFIGURE PHASE]: ANA_TX
4943 20:00:05.546202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4944 20:00:05.549584 ===================================
4945 20:00:05.550127 data_rate = 1866,PCW = 0X8f00
4946 20:00:05.553127 ===================================
4947 20:00:05.555775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4948 20:00:05.562913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 20:00:05.569182 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 20:00:05.572348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4951 20:00:05.576198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4952 20:00:05.579285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4953 20:00:05.582510 [ANA_INIT] flow start
4954 20:00:05.583029 [ANA_INIT] PLL >>>>>>>>
4955 20:00:05.585896 [ANA_INIT] PLL <<<<<<<<
4956 20:00:05.589293 [ANA_INIT] MIDPI >>>>>>>>
4957 20:00:05.592080 [ANA_INIT] MIDPI <<<<<<<<
4958 20:00:05.592609 [ANA_INIT] DLL >>>>>>>>
4959 20:00:05.595666 [ANA_INIT] flow end
4960 20:00:05.598790 ============ LP4 DIFF to SE enter ============
4961 20:00:05.602210 ============ LP4 DIFF to SE exit ============
4962 20:00:05.605249 [ANA_INIT] <<<<<<<<<<<<<
4963 20:00:05.608833 [Flow] Enable top DCM control >>>>>
4964 20:00:05.612267 [Flow] Enable top DCM control <<<<<
4965 20:00:05.615371 Enable DLL master slave shuffle
4966 20:00:05.621807 ==============================================================
4967 20:00:05.622279 Gating Mode config
4968 20:00:05.628703 ==============================================================
4969 20:00:05.629236 Config description:
4970 20:00:05.638693 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4971 20:00:05.645613 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4972 20:00:05.651674 SELPH_MODE 0: By rank 1: By Phase
4973 20:00:05.658909 ==============================================================
4974 20:00:05.659491 GAT_TRACK_EN = 1
4975 20:00:05.661564 RX_GATING_MODE = 2
4976 20:00:05.665139 RX_GATING_TRACK_MODE = 2
4977 20:00:05.668508 SELPH_MODE = 1
4978 20:00:05.671786 PICG_EARLY_EN = 1
4979 20:00:05.674991 VALID_LAT_VALUE = 1
4980 20:00:05.681865 ==============================================================
4981 20:00:05.684901 Enter into Gating configuration >>>>
4982 20:00:05.687832 Exit from Gating configuration <<<<
4983 20:00:05.691320 Enter into DVFS_PRE_config >>>>>
4984 20:00:05.701379 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4985 20:00:05.705028 Exit from DVFS_PRE_config <<<<<
4986 20:00:05.707709 Enter into PICG configuration >>>>
4987 20:00:05.711354 Exit from PICG configuration <<<<
4988 20:00:05.714542 [RX_INPUT] configuration >>>>>
4989 20:00:05.717386 [RX_INPUT] configuration <<<<<
4990 20:00:05.720777 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4991 20:00:05.727455 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4992 20:00:05.734300 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 20:00:05.737474 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 20:00:05.744109 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4995 20:00:05.751123 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4996 20:00:05.754841 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4997 20:00:05.757439 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4998 20:00:05.763917 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4999 20:00:05.767463 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5000 20:00:05.770398 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5001 20:00:05.777122 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 20:00:05.780836 ===================================
5003 20:00:05.781359 LPDDR4 DRAM CONFIGURATION
5004 20:00:05.783636 ===================================
5005 20:00:05.787297 EX_ROW_EN[0] = 0x0
5006 20:00:05.790542 EX_ROW_EN[1] = 0x0
5007 20:00:05.791067 LP4Y_EN = 0x0
5008 20:00:05.794126 WORK_FSP = 0x0
5009 20:00:05.794646 WL = 0x3
5010 20:00:05.797162 RL = 0x3
5011 20:00:05.797581 BL = 0x2
5012 20:00:05.800390 RPST = 0x0
5013 20:00:05.800908 RD_PRE = 0x0
5014 20:00:05.803466 WR_PRE = 0x1
5015 20:00:05.803889 WR_PST = 0x0
5016 20:00:05.807107 DBI_WR = 0x0
5017 20:00:05.807561 DBI_RD = 0x0
5018 20:00:05.810477 OTF = 0x1
5019 20:00:05.814324 ===================================
5020 20:00:05.817153 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5021 20:00:05.820419 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5022 20:00:05.826827 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5023 20:00:05.830619 ===================================
5024 20:00:05.831142 LPDDR4 DRAM CONFIGURATION
5025 20:00:05.833898 ===================================
5026 20:00:05.836846 EX_ROW_EN[0] = 0x10
5027 20:00:05.840168 EX_ROW_EN[1] = 0x0
5028 20:00:05.840721 LP4Y_EN = 0x0
5029 20:00:05.843682 WORK_FSP = 0x0
5030 20:00:05.844232 WL = 0x3
5031 20:00:05.846822 RL = 0x3
5032 20:00:05.847345 BL = 0x2
5033 20:00:05.850259 RPST = 0x0
5034 20:00:05.850779 RD_PRE = 0x0
5035 20:00:05.853554 WR_PRE = 0x1
5036 20:00:05.854102 WR_PST = 0x0
5037 20:00:05.856674 DBI_WR = 0x0
5038 20:00:05.857092 DBI_RD = 0x0
5039 20:00:05.860104 OTF = 0x1
5040 20:00:05.863465 ===================================
5041 20:00:05.870111 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5042 20:00:05.873640 nWR fixed to 30
5043 20:00:05.874169 [ModeRegInit_LP4] CH0 RK0
5044 20:00:05.876659 [ModeRegInit_LP4] CH0 RK1
5045 20:00:05.879964 [ModeRegInit_LP4] CH1 RK0
5046 20:00:05.883209 [ModeRegInit_LP4] CH1 RK1
5047 20:00:05.883778 match AC timing 9
5048 20:00:05.889893 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5049 20:00:05.893116 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5050 20:00:05.896692 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5051 20:00:05.902819 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5052 20:00:05.906565 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5053 20:00:05.906991 ==
5054 20:00:05.909714 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 20:00:05.913242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5056 20:00:05.913771 ==
5057 20:00:05.919612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5058 20:00:05.925995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5059 20:00:05.929491 [CA 0] Center 38 (8~69) winsize 62
5060 20:00:05.932367 [CA 1] Center 38 (7~69) winsize 63
5061 20:00:05.936045 [CA 2] Center 35 (5~66) winsize 62
5062 20:00:05.939201 [CA 3] Center 35 (5~65) winsize 61
5063 20:00:05.943199 [CA 4] Center 34 (4~65) winsize 62
5064 20:00:05.946557 [CA 5] Center 33 (3~64) winsize 62
5065 20:00:05.947079
5066 20:00:05.949518 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5067 20:00:05.950044
5068 20:00:05.952276 [CATrainingPosCal] consider 1 rank data
5069 20:00:05.956118 u2DelayCellTimex100 = 270/100 ps
5070 20:00:05.959136 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5071 20:00:05.962797 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5072 20:00:05.966217 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5073 20:00:05.969206 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5074 20:00:05.972275 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5075 20:00:05.975771 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5076 20:00:05.979457
5077 20:00:05.982606 CA PerBit enable=1, Macro0, CA PI delay=33
5078 20:00:05.983162
5079 20:00:05.985595 [CBTSetCACLKResult] CA Dly = 33
5080 20:00:05.986171 CS Dly: 6 (0~37)
5081 20:00:05.986514 ==
5082 20:00:05.989055 Dram Type= 6, Freq= 0, CH_0, rank 1
5083 20:00:05.992306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 20:00:05.995369 ==
5085 20:00:05.998854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5086 20:00:06.005377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5087 20:00:06.008736 [CA 0] Center 38 (8~69) winsize 62
5088 20:00:06.012020 [CA 1] Center 38 (8~69) winsize 62
5089 20:00:06.015121 [CA 2] Center 35 (5~66) winsize 62
5090 20:00:06.019027 [CA 3] Center 35 (4~66) winsize 63
5091 20:00:06.022577 [CA 4] Center 34 (4~64) winsize 61
5092 20:00:06.025010 [CA 5] Center 34 (4~64) winsize 61
5093 20:00:06.025435
5094 20:00:06.028704 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5095 20:00:06.029128
5096 20:00:06.031947 [CATrainingPosCal] consider 2 rank data
5097 20:00:06.035337 u2DelayCellTimex100 = 270/100 ps
5098 20:00:06.038495 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5099 20:00:06.041933 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5100 20:00:06.045205 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5101 20:00:06.048058 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5102 20:00:06.055199 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5103 20:00:06.058822 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5104 20:00:06.059346
5105 20:00:06.061756 CA PerBit enable=1, Macro0, CA PI delay=34
5106 20:00:06.062289
5107 20:00:06.064950 [CBTSetCACLKResult] CA Dly = 34
5108 20:00:06.065476 CS Dly: 7 (0~39)
5109 20:00:06.065812
5110 20:00:06.068242 ----->DramcWriteLeveling(PI) begin...
5111 20:00:06.068772 ==
5112 20:00:06.071653 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 20:00:06.077859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 20:00:06.078382 ==
5115 20:00:06.081415 Write leveling (Byte 0): 32 => 32
5116 20:00:06.084983 Write leveling (Byte 1): 28 => 28
5117 20:00:06.085509 DramcWriteLeveling(PI) end<-----
5118 20:00:06.085845
5119 20:00:06.088294 ==
5120 20:00:06.091473 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 20:00:06.094719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 20:00:06.095247 ==
5123 20:00:06.098124 [Gating] SW mode calibration
5124 20:00:06.104340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5125 20:00:06.108015 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5126 20:00:06.114484 0 14 0 | B1->B0 | 2322 2c2c | 1 1 | (0 0) (1 1)
5127 20:00:06.118215 0 14 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5128 20:00:06.121040 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 20:00:06.128500 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 20:00:06.131468 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 20:00:06.134639 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 20:00:06.141142 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 20:00:06.144392 0 14 28 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5134 20:00:06.147610 0 15 0 | B1->B0 | 3333 2b2b | 1 1 | (1 1) (1 0)
5135 20:00:06.153953 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5136 20:00:06.157503 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 20:00:06.161131 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 20:00:06.167521 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 20:00:06.171056 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 20:00:06.174259 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 20:00:06.180872 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 20:00:06.184705 1 0 0 | B1->B0 | 2a2a 3d3c | 0 1 | (0 0) (0 0)
5143 20:00:06.187560 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5144 20:00:06.194627 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 20:00:06.198047 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 20:00:06.200626 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 20:00:06.207210 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 20:00:06.211145 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 20:00:06.214063 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5150 20:00:06.220739 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5151 20:00:06.224238 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5152 20:00:06.227017 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 20:00:06.234032 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 20:00:06.237090 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 20:00:06.240747 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 20:00:06.246917 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 20:00:06.249911 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 20:00:06.253397 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 20:00:06.260164 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 20:00:06.263736 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 20:00:06.266790 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 20:00:06.273622 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 20:00:06.276832 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 20:00:06.279913 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 20:00:06.286776 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 20:00:06.290494 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5167 20:00:06.293388 Total UI for P1: 0, mck2ui 16
5168 20:00:06.296843 best dqsien dly found for B0: ( 1, 2, 30)
5169 20:00:06.300025 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5170 20:00:06.303610 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 20:00:06.306490 Total UI for P1: 0, mck2ui 16
5172 20:00:06.310389 best dqsien dly found for B1: ( 1, 3, 2)
5173 20:00:06.313954 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5174 20:00:06.316880 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5175 20:00:06.320066
5176 20:00:06.323291 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5177 20:00:06.326688 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5178 20:00:06.330026 [Gating] SW calibration Done
5179 20:00:06.330437 ==
5180 20:00:06.333400 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 20:00:06.336593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 20:00:06.337015 ==
5183 20:00:06.337344 RX Vref Scan: 0
5184 20:00:06.337649
5185 20:00:06.340091 RX Vref 0 -> 0, step: 1
5186 20:00:06.340506
5187 20:00:06.343530 RX Delay -80 -> 252, step: 8
5188 20:00:06.346975 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5189 20:00:06.350363 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5190 20:00:06.356642 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5191 20:00:06.359936 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5192 20:00:06.363536 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5193 20:00:06.366266 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5194 20:00:06.369797 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5195 20:00:06.373216 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5196 20:00:06.379766 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5197 20:00:06.383017 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5198 20:00:06.386250 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5199 20:00:06.389778 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5200 20:00:06.392595 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5201 20:00:06.399711 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5202 20:00:06.402838 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5203 20:00:06.405823 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5204 20:00:06.406261 ==
5205 20:00:06.409301 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 20:00:06.412809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 20:00:06.413227 ==
5208 20:00:06.416099 DQS Delay:
5209 20:00:06.416509 DQS0 = 0, DQS1 = 0
5210 20:00:06.420042 DQM Delay:
5211 20:00:06.420562 DQM0 = 92, DQM1 = 82
5212 20:00:06.420893 DQ Delay:
5213 20:00:06.423211 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =91
5214 20:00:06.426419 DQ4 =91, DQ5 =79, DQ6 =99, DQ7 =107
5215 20:00:06.429910 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5216 20:00:06.433521 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5217 20:00:06.434043
5218 20:00:06.434376
5219 20:00:06.436080 ==
5220 20:00:06.439382 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 20:00:06.443083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 20:00:06.443647 ==
5223 20:00:06.443981
5224 20:00:06.444286
5225 20:00:06.446898 TX Vref Scan disable
5226 20:00:06.447449 == TX Byte 0 ==
5227 20:00:06.449709 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5228 20:00:06.456692 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5229 20:00:06.457214 == TX Byte 1 ==
5230 20:00:06.459380 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5231 20:00:06.465785 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5232 20:00:06.466306 ==
5233 20:00:06.469635 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 20:00:06.472659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 20:00:06.473082 ==
5236 20:00:06.473412
5237 20:00:06.473719
5238 20:00:06.476021 TX Vref Scan disable
5239 20:00:06.479246 == TX Byte 0 ==
5240 20:00:06.482755 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5241 20:00:06.486217 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5242 20:00:06.489362 == TX Byte 1 ==
5243 20:00:06.492715 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5244 20:00:06.495685 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5245 20:00:06.496101
5246 20:00:06.499447 [DATLAT]
5247 20:00:06.499986 Freq=933, CH0 RK0
5248 20:00:06.500319
5249 20:00:06.502479 DATLAT Default: 0xd
5250 20:00:06.503011 0, 0xFFFF, sum = 0
5251 20:00:06.505613 1, 0xFFFF, sum = 0
5252 20:00:06.506038 2, 0xFFFF, sum = 0
5253 20:00:06.509085 3, 0xFFFF, sum = 0
5254 20:00:06.509612 4, 0xFFFF, sum = 0
5255 20:00:06.512520 5, 0xFFFF, sum = 0
5256 20:00:06.512944 6, 0xFFFF, sum = 0
5257 20:00:06.515664 7, 0xFFFF, sum = 0
5258 20:00:06.516087 8, 0xFFFF, sum = 0
5259 20:00:06.519119 9, 0xFFFF, sum = 0
5260 20:00:06.519574 10, 0x0, sum = 1
5261 20:00:06.522110 11, 0x0, sum = 2
5262 20:00:06.522571 12, 0x0, sum = 3
5263 20:00:06.525666 13, 0x0, sum = 4
5264 20:00:06.526090 best_step = 11
5265 20:00:06.526459
5266 20:00:06.526776 ==
5267 20:00:06.529383 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 20:00:06.532783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 20:00:06.535499 ==
5270 20:00:06.535919 RX Vref Scan: 1
5271 20:00:06.536250
5272 20:00:06.538808 RX Vref 0 -> 0, step: 1
5273 20:00:06.539227
5274 20:00:06.541944 RX Delay -69 -> 252, step: 4
5275 20:00:06.542423
5276 20:00:06.545401 Set Vref, RX VrefLevel [Byte0]: 61
5277 20:00:06.549243 [Byte1]: 52
5278 20:00:06.549762
5279 20:00:06.552743 Final RX Vref Byte 0 = 61 to rank0
5280 20:00:06.555599 Final RX Vref Byte 1 = 52 to rank0
5281 20:00:06.559246 Final RX Vref Byte 0 = 61 to rank1
5282 20:00:06.562860 Final RX Vref Byte 1 = 52 to rank1==
5283 20:00:06.565301 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 20:00:06.568886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 20:00:06.569434 ==
5286 20:00:06.572393 DQS Delay:
5287 20:00:06.572816 DQS0 = 0, DQS1 = 0
5288 20:00:06.573152 DQM Delay:
5289 20:00:06.575182 DQM0 = 95, DQM1 = 83
5290 20:00:06.575685 DQ Delay:
5291 20:00:06.578729 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5292 20:00:06.582084 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5293 20:00:06.585120 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =76
5294 20:00:06.588562 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =90
5295 20:00:06.588971
5296 20:00:06.589295
5297 20:00:06.598503 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5298 20:00:06.601575 CH0 RK0: MR19=505, MR18=1212
5299 20:00:06.605025 CH0_RK0: MR19=0x505, MR18=0x1212, DQSOSC=416, MR23=63, INC=62, DEC=41
5300 20:00:06.605435
5301 20:00:06.608428 ----->DramcWriteLeveling(PI) begin...
5302 20:00:06.611997 ==
5303 20:00:06.615249 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 20:00:06.618679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 20:00:06.619190 ==
5306 20:00:06.621551 Write leveling (Byte 0): 33 => 33
5307 20:00:06.625458 Write leveling (Byte 1): 32 => 32
5308 20:00:06.628633 DramcWriteLeveling(PI) end<-----
5309 20:00:06.629042
5310 20:00:06.629368 ==
5311 20:00:06.631988 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 20:00:06.635191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 20:00:06.635656 ==
5314 20:00:06.638449 [Gating] SW mode calibration
5315 20:00:06.645081 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5316 20:00:06.651888 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5317 20:00:06.655148 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5318 20:00:06.658020 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5319 20:00:06.664476 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 20:00:06.668216 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 20:00:06.671481 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 20:00:06.674666 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 20:00:06.682073 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 20:00:06.684675 0 14 28 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (0 0)
5325 20:00:06.688009 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5326 20:00:06.694613 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 20:00:06.698457 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 20:00:06.701158 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 20:00:06.707961 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 20:00:06.711527 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 20:00:06.715094 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 20:00:06.721233 0 15 28 | B1->B0 | 2727 3535 | 0 0 | (0 0) (0 0)
5333 20:00:06.724147 1 0 0 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
5334 20:00:06.728332 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 20:00:06.734855 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 20:00:06.738001 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 20:00:06.740637 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 20:00:06.747659 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 20:00:06.751127 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5340 20:00:06.754653 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5341 20:00:06.760551 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5342 20:00:06.764067 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 20:00:06.767506 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 20:00:06.773925 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 20:00:06.777142 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 20:00:06.780289 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 20:00:06.786943 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 20:00:06.790507 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 20:00:06.793910 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 20:00:06.800071 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 20:00:06.803653 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 20:00:06.806781 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 20:00:06.813447 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 20:00:06.816732 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 20:00:06.820534 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 20:00:06.827240 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5357 20:00:06.830512 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5358 20:00:06.833679 Total UI for P1: 0, mck2ui 16
5359 20:00:06.836609 best dqsien dly found for B0: ( 1, 2, 28)
5360 20:00:06.840587 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 20:00:06.843695 Total UI for P1: 0, mck2ui 16
5362 20:00:06.847269 best dqsien dly found for B1: ( 1, 3, 0)
5363 20:00:06.850402 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5364 20:00:06.853106 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5365 20:00:06.853530
5366 20:00:06.860163 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5367 20:00:06.863174 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5368 20:00:06.863733 [Gating] SW calibration Done
5369 20:00:06.866568 ==
5370 20:00:06.870177 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 20:00:06.872845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 20:00:06.873348 ==
5373 20:00:06.873705 RX Vref Scan: 0
5374 20:00:06.874021
5375 20:00:06.876361 RX Vref 0 -> 0, step: 1
5376 20:00:06.876851
5377 20:00:06.879525 RX Delay -80 -> 252, step: 8
5378 20:00:06.883639 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5379 20:00:06.886545 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5380 20:00:06.890044 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5381 20:00:06.896812 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5382 20:00:06.899581 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5383 20:00:06.903270 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5384 20:00:06.905867 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5385 20:00:06.909058 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5386 20:00:06.916148 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5387 20:00:06.919486 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5388 20:00:06.922608 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5389 20:00:06.926110 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5390 20:00:06.929550 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5391 20:00:06.935974 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5392 20:00:06.939069 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5393 20:00:06.943011 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5394 20:00:06.943571 ==
5395 20:00:06.946521 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 20:00:06.949442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 20:00:06.949961 ==
5398 20:00:06.953175 DQS Delay:
5399 20:00:06.953692 DQS0 = 0, DQS1 = 0
5400 20:00:06.956647 DQM Delay:
5401 20:00:06.957065 DQM0 = 92, DQM1 = 84
5402 20:00:06.957398 DQ Delay:
5403 20:00:06.959163 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5404 20:00:06.962991 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5405 20:00:06.966334 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5406 20:00:06.969783 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5407 20:00:06.970309
5408 20:00:06.970643
5409 20:00:06.970953 ==
5410 20:00:06.972884 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 20:00:06.979582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 20:00:06.980099 ==
5413 20:00:06.980431
5414 20:00:06.980738
5415 20:00:06.981031 TX Vref Scan disable
5416 20:00:06.983499 == TX Byte 0 ==
5417 20:00:06.987010 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5418 20:00:06.993604 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5419 20:00:06.994137 == TX Byte 1 ==
5420 20:00:06.996082 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5421 20:00:07.003573 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5422 20:00:07.004085 ==
5423 20:00:07.006276 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 20:00:07.010023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 20:00:07.010548 ==
5426 20:00:07.010884
5427 20:00:07.011190
5428 20:00:07.013008 TX Vref Scan disable
5429 20:00:07.013520 == TX Byte 0 ==
5430 20:00:07.019925 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5431 20:00:07.023070 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5432 20:00:07.023531 == TX Byte 1 ==
5433 20:00:07.029590 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5434 20:00:07.033188 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5435 20:00:07.033706
5436 20:00:07.034037 [DATLAT]
5437 20:00:07.036094 Freq=933, CH0 RK1
5438 20:00:07.036509
5439 20:00:07.036835 DATLAT Default: 0xb
5440 20:00:07.039224 0, 0xFFFF, sum = 0
5441 20:00:07.039682 1, 0xFFFF, sum = 0
5442 20:00:07.042563 2, 0xFFFF, sum = 0
5443 20:00:07.046206 3, 0xFFFF, sum = 0
5444 20:00:07.046724 4, 0xFFFF, sum = 0
5445 20:00:07.049615 5, 0xFFFF, sum = 0
5446 20:00:07.050133 6, 0xFFFF, sum = 0
5447 20:00:07.052476 7, 0xFFFF, sum = 0
5448 20:00:07.052896 8, 0xFFFF, sum = 0
5449 20:00:07.055915 9, 0xFFFF, sum = 0
5450 20:00:07.056335 10, 0x0, sum = 1
5451 20:00:07.059448 11, 0x0, sum = 2
5452 20:00:07.059965 12, 0x0, sum = 3
5453 20:00:07.063087 13, 0x0, sum = 4
5454 20:00:07.063677 best_step = 11
5455 20:00:07.064014
5456 20:00:07.064323 ==
5457 20:00:07.066235 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 20:00:07.068990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 20:00:07.069404 ==
5460 20:00:07.072546 RX Vref Scan: 0
5461 20:00:07.072976
5462 20:00:07.075651 RX Vref 0 -> 0, step: 1
5463 20:00:07.076066
5464 20:00:07.076389 RX Delay -69 -> 252, step: 4
5465 20:00:07.083594 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5466 20:00:07.087495 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5467 20:00:07.090746 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5468 20:00:07.093294 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5469 20:00:07.097062 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5470 20:00:07.103849 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5471 20:00:07.106444 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5472 20:00:07.110711 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5473 20:00:07.113401 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5474 20:00:07.117128 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5475 20:00:07.120284 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5476 20:00:07.126879 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5477 20:00:07.129789 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5478 20:00:07.133065 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5479 20:00:07.136651 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5480 20:00:07.139890 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5481 20:00:07.143239 ==
5482 20:00:07.146717 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 20:00:07.149845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 20:00:07.150377 ==
5485 20:00:07.150710 DQS Delay:
5486 20:00:07.152825 DQS0 = 0, DQS1 = 0
5487 20:00:07.153244 DQM Delay:
5488 20:00:07.156415 DQM0 = 93, DQM1 = 85
5489 20:00:07.156842 DQ Delay:
5490 20:00:07.159693 DQ0 =92, DQ1 =94, DQ2 =90, DQ3 =88
5491 20:00:07.163271 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =104
5492 20:00:07.166186 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =76
5493 20:00:07.169859 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =94
5494 20:00:07.170271
5495 20:00:07.170598
5496 20:00:07.176358 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5497 20:00:07.180100 CH0 RK1: MR19=505, MR18=2C0E
5498 20:00:07.186456 CH0_RK1: MR19=0x505, MR18=0x2C0E, DQSOSC=408, MR23=63, INC=65, DEC=43
5499 20:00:07.190184 [RxdqsGatingPostProcess] freq 933
5500 20:00:07.196137 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5501 20:00:07.196561 best DQS0 dly(2T, 0.5T) = (0, 10)
5502 20:00:07.200331 best DQS1 dly(2T, 0.5T) = (0, 11)
5503 20:00:07.203317 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5504 20:00:07.206475 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5505 20:00:07.209577 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 20:00:07.213131 best DQS1 dly(2T, 0.5T) = (0, 11)
5507 20:00:07.216136 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 20:00:07.219356 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5509 20:00:07.222934 Pre-setting of DQS Precalculation
5510 20:00:07.229846 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5511 20:00:07.230359 ==
5512 20:00:07.233450 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 20:00:07.236117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 20:00:07.236535 ==
5515 20:00:07.242744 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 20:00:07.245506 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5517 20:00:07.250293 [CA 0] Center 37 (7~68) winsize 62
5518 20:00:07.253093 [CA 1] Center 37 (7~68) winsize 62
5519 20:00:07.256487 [CA 2] Center 34 (5~64) winsize 60
5520 20:00:07.260055 [CA 3] Center 34 (4~64) winsize 61
5521 20:00:07.263214 [CA 4] Center 34 (5~64) winsize 60
5522 20:00:07.266891 [CA 5] Center 34 (4~64) winsize 61
5523 20:00:07.267450
5524 20:00:07.269718 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5525 20:00:07.270227
5526 20:00:07.273258 [CATrainingPosCal] consider 1 rank data
5527 20:00:07.276557 u2DelayCellTimex100 = 270/100 ps
5528 20:00:07.280104 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5529 20:00:07.286624 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5530 20:00:07.290143 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5531 20:00:07.293090 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5532 20:00:07.296438 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5533 20:00:07.299739 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5534 20:00:07.300252
5535 20:00:07.302996 CA PerBit enable=1, Macro0, CA PI delay=34
5536 20:00:07.303448
5537 20:00:07.306443 [CBTSetCACLKResult] CA Dly = 34
5538 20:00:07.306860 CS Dly: 6 (0~37)
5539 20:00:07.309773 ==
5540 20:00:07.312994 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 20:00:07.316194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 20:00:07.316614 ==
5543 20:00:07.319556 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5544 20:00:07.326625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5545 20:00:07.329934 [CA 0] Center 38 (8~68) winsize 61
5546 20:00:07.333382 [CA 1] Center 37 (7~68) winsize 62
5547 20:00:07.337003 [CA 2] Center 35 (5~65) winsize 61
5548 20:00:07.339996 [CA 3] Center 34 (4~64) winsize 61
5549 20:00:07.343248 [CA 4] Center 35 (5~66) winsize 62
5550 20:00:07.346787 [CA 5] Center 34 (4~64) winsize 61
5551 20:00:07.347312
5552 20:00:07.349961 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5553 20:00:07.350484
5554 20:00:07.353470 [CATrainingPosCal] consider 2 rank data
5555 20:00:07.356168 u2DelayCellTimex100 = 270/100 ps
5556 20:00:07.359704 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5557 20:00:07.366781 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5558 20:00:07.369568 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5559 20:00:07.373038 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5560 20:00:07.376325 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5561 20:00:07.379711 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5562 20:00:07.380126
5563 20:00:07.383258 CA PerBit enable=1, Macro0, CA PI delay=34
5564 20:00:07.383696
5565 20:00:07.386437 [CBTSetCACLKResult] CA Dly = 34
5566 20:00:07.386962 CS Dly: 7 (0~39)
5567 20:00:07.390027
5568 20:00:07.393015 ----->DramcWriteLeveling(PI) begin...
5569 20:00:07.393541 ==
5570 20:00:07.396274 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 20:00:07.399480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 20:00:07.399960 ==
5573 20:00:07.403468 Write leveling (Byte 0): 24 => 24
5574 20:00:07.406478 Write leveling (Byte 1): 31 => 31
5575 20:00:07.409422 DramcWriteLeveling(PI) end<-----
5576 20:00:07.409831
5577 20:00:07.410157 ==
5578 20:00:07.412571 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 20:00:07.416127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 20:00:07.416540 ==
5581 20:00:07.419957 [Gating] SW mode calibration
5582 20:00:07.426073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5583 20:00:07.432642 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5584 20:00:07.436241 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 20:00:07.440041 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 20:00:07.446196 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 20:00:07.449313 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 20:00:07.452304 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 20:00:07.459118 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 20:00:07.462646 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5591 20:00:07.466135 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 0)
5592 20:00:07.473079 0 15 0 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5593 20:00:07.475899 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 20:00:07.479083 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 20:00:07.485819 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 20:00:07.489408 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 20:00:07.492776 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 20:00:07.498956 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 20:00:07.502306 0 15 28 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (0 0)
5600 20:00:07.505306 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 20:00:07.512350 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 20:00:07.515976 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 20:00:07.518780 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 20:00:07.525265 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 20:00:07.528568 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 20:00:07.532333 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5607 20:00:07.538602 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 20:00:07.542147 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5609 20:00:07.545459 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 20:00:07.548452 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 20:00:07.555640 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 20:00:07.558668 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 20:00:07.562113 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 20:00:07.568033 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 20:00:07.571998 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 20:00:07.575009 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 20:00:07.581838 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 20:00:07.584868 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 20:00:07.588273 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 20:00:07.594787 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 20:00:07.598530 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 20:00:07.601438 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 20:00:07.608229 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5624 20:00:07.611787 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5625 20:00:07.615171 Total UI for P1: 0, mck2ui 16
5626 20:00:07.618414 best dqsien dly found for B0: ( 1, 2, 28)
5627 20:00:07.621930 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 20:00:07.624530 Total UI for P1: 0, mck2ui 16
5629 20:00:07.628181 best dqsien dly found for B1: ( 1, 3, 0)
5630 20:00:07.631829 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5631 20:00:07.634336 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5632 20:00:07.634751
5633 20:00:07.641290 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5634 20:00:07.644638 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5635 20:00:07.645277 [Gating] SW calibration Done
5636 20:00:07.647776 ==
5637 20:00:07.651604 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 20:00:07.654581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 20:00:07.655093 ==
5640 20:00:07.655462 RX Vref Scan: 0
5641 20:00:07.655776
5642 20:00:07.657830 RX Vref 0 -> 0, step: 1
5643 20:00:07.658340
5644 20:00:07.661288 RX Delay -80 -> 252, step: 8
5645 20:00:07.664127 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5646 20:00:07.667875 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5647 20:00:07.671436 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5648 20:00:07.677752 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5649 20:00:07.681099 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5650 20:00:07.684722 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5651 20:00:07.687780 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5652 20:00:07.690963 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5653 20:00:07.697343 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5654 20:00:07.701040 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5655 20:00:07.704100 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5656 20:00:07.707129 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5657 20:00:07.710986 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5658 20:00:07.717930 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5659 20:00:07.720323 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5660 20:00:07.724046 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5661 20:00:07.724460 ==
5662 20:00:07.727466 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 20:00:07.730866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 20:00:07.731374 ==
5665 20:00:07.734354 DQS Delay:
5666 20:00:07.734879 DQS0 = 0, DQS1 = 0
5667 20:00:07.735215 DQM Delay:
5668 20:00:07.737285 DQM0 = 94, DQM1 = 85
5669 20:00:07.737697 DQ Delay:
5670 20:00:07.740574 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5671 20:00:07.743560 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5672 20:00:07.746915 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5673 20:00:07.750517 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5674 20:00:07.750929
5675 20:00:07.751255
5676 20:00:07.754646 ==
5677 20:00:07.755152 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 20:00:07.760463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 20:00:07.760958 ==
5680 20:00:07.761287
5681 20:00:07.761593
5682 20:00:07.763885 TX Vref Scan disable
5683 20:00:07.764297 == TX Byte 0 ==
5684 20:00:07.767201 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5685 20:00:07.774012 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5686 20:00:07.774539 == TX Byte 1 ==
5687 20:00:07.777334 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5688 20:00:07.783959 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5689 20:00:07.784488 ==
5690 20:00:07.787066 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 20:00:07.790771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 20:00:07.791199 ==
5693 20:00:07.791671
5694 20:00:07.792090
5695 20:00:07.793677 TX Vref Scan disable
5696 20:00:07.797035 == TX Byte 0 ==
5697 20:00:07.800803 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5698 20:00:07.803904 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5699 20:00:07.807063 == TX Byte 1 ==
5700 20:00:07.810334 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5701 20:00:07.813475 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5702 20:00:07.813905
5703 20:00:07.816988 [DATLAT]
5704 20:00:07.817500 Freq=933, CH1 RK0
5705 20:00:07.817831
5706 20:00:07.820111 DATLAT Default: 0xd
5707 20:00:07.820524 0, 0xFFFF, sum = 0
5708 20:00:07.824107 1, 0xFFFF, sum = 0
5709 20:00:07.824628 2, 0xFFFF, sum = 0
5710 20:00:07.827057 3, 0xFFFF, sum = 0
5711 20:00:07.827610 4, 0xFFFF, sum = 0
5712 20:00:07.830138 5, 0xFFFF, sum = 0
5713 20:00:07.830579 6, 0xFFFF, sum = 0
5714 20:00:07.833463 7, 0xFFFF, sum = 0
5715 20:00:07.833882 8, 0xFFFF, sum = 0
5716 20:00:07.836815 9, 0xFFFF, sum = 0
5717 20:00:07.837235 10, 0x0, sum = 1
5718 20:00:07.840174 11, 0x0, sum = 2
5719 20:00:07.840594 12, 0x0, sum = 3
5720 20:00:07.843239 13, 0x0, sum = 4
5721 20:00:07.844009 best_step = 11
5722 20:00:07.844356
5723 20:00:07.844666 ==
5724 20:00:07.846877 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 20:00:07.850194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 20:00:07.853650 ==
5727 20:00:07.854138 RX Vref Scan: 1
5728 20:00:07.854548
5729 20:00:07.857073 RX Vref 0 -> 0, step: 1
5730 20:00:07.857604
5731 20:00:07.859858 RX Delay -69 -> 252, step: 4
5732 20:00:07.860285
5733 20:00:07.863624 Set Vref, RX VrefLevel [Byte0]: 53
5734 20:00:07.866569 [Byte1]: 49
5735 20:00:07.867100
5736 20:00:07.870002 Final RX Vref Byte 0 = 53 to rank0
5737 20:00:07.873175 Final RX Vref Byte 1 = 49 to rank0
5738 20:00:07.876041 Final RX Vref Byte 0 = 53 to rank1
5739 20:00:07.879369 Final RX Vref Byte 1 = 49 to rank1==
5740 20:00:07.882847 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 20:00:07.886372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 20:00:07.886789 ==
5743 20:00:07.889326 DQS Delay:
5744 20:00:07.889753 DQS0 = 0, DQS1 = 0
5745 20:00:07.890082 DQM Delay:
5746 20:00:07.893108 DQM0 = 95, DQM1 = 88
5747 20:00:07.893621 DQ Delay:
5748 20:00:07.896335 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =92
5749 20:00:07.899771 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =92
5750 20:00:07.903146 DQ8 =78, DQ9 =80, DQ10 =86, DQ11 =80
5751 20:00:07.906090 DQ12 =98, DQ13 =92, DQ14 =96, DQ15 =94
5752 20:00:07.906615
5753 20:00:07.907054
5754 20:00:07.916267 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5755 20:00:07.919529 CH1 RK0: MR19=405, MR18=FE07
5756 20:00:07.922368 CH1_RK0: MR19=0x405, MR18=0xFE07, DQSOSC=419, MR23=63, INC=61, DEC=41
5757 20:00:07.925810
5758 20:00:07.929519 ----->DramcWriteLeveling(PI) begin...
5759 20:00:07.929957 ==
5760 20:00:07.932408 Dram Type= 6, Freq= 0, CH_1, rank 1
5761 20:00:07.935697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 20:00:07.936159 ==
5763 20:00:07.939049 Write leveling (Byte 0): 27 => 27
5764 20:00:07.942986 Write leveling (Byte 1): 29 => 29
5765 20:00:07.945813 DramcWriteLeveling(PI) end<-----
5766 20:00:07.946338
5767 20:00:07.946785 ==
5768 20:00:07.949115 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 20:00:07.952690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 20:00:07.953125 ==
5771 20:00:07.955532 [Gating] SW mode calibration
5772 20:00:07.962191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5773 20:00:07.968889 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5774 20:00:07.972318 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5775 20:00:07.975775 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 20:00:07.981846 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 20:00:07.985299 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 20:00:07.988470 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 20:00:07.995276 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 20:00:07.998246 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5781 20:00:08.002196 0 14 28 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5782 20:00:08.008448 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 20:00:08.012152 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 20:00:08.015652 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 20:00:08.021595 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 20:00:08.025310 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 20:00:08.028463 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 20:00:08.035331 0 15 24 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
5789 20:00:08.038007 0 15 28 | B1->B0 | 3938 4545 | 1 0 | (0 0) (0 0)
5790 20:00:08.041766 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 20:00:08.048622 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 20:00:08.051843 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 20:00:08.055285 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 20:00:08.061635 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 20:00:08.064631 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5796 20:00:08.068346 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5797 20:00:08.075014 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5798 20:00:08.078461 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 20:00:08.081428 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 20:00:08.087923 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 20:00:08.091495 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 20:00:08.094391 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 20:00:08.101055 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 20:00:08.104903 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 20:00:08.107460 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 20:00:08.114278 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 20:00:08.117739 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 20:00:08.120808 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 20:00:08.124024 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 20:00:08.131107 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 20:00:08.134973 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 20:00:08.137809 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5813 20:00:08.143913 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5814 20:00:08.147476 Total UI for P1: 0, mck2ui 16
5815 20:00:08.151126 best dqsien dly found for B0: ( 1, 2, 24)
5816 20:00:08.154974 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 20:00:08.157681 Total UI for P1: 0, mck2ui 16
5818 20:00:08.160673 best dqsien dly found for B1: ( 1, 2, 28)
5819 20:00:08.164257 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5820 20:00:08.167772 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5821 20:00:08.168206
5822 20:00:08.171049 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5823 20:00:08.174313 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5824 20:00:08.177651 [Gating] SW calibration Done
5825 20:00:08.178079 ==
5826 20:00:08.181211 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 20:00:08.187698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 20:00:08.188215 ==
5829 20:00:08.188546 RX Vref Scan: 0
5830 20:00:08.188866
5831 20:00:08.191335 RX Vref 0 -> 0, step: 1
5832 20:00:08.191882
5833 20:00:08.194195 RX Delay -80 -> 252, step: 8
5834 20:00:08.197590 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5835 20:00:08.201248 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5836 20:00:08.204610 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5837 20:00:08.207287 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5838 20:00:08.214625 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5839 20:00:08.216999 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5840 20:00:08.220570 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5841 20:00:08.224110 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5842 20:00:08.227814 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5843 20:00:08.230959 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5844 20:00:08.237119 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5845 20:00:08.240785 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5846 20:00:08.244312 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5847 20:00:08.247091 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5848 20:00:08.250317 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5849 20:00:08.257265 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5850 20:00:08.257783 ==
5851 20:00:08.260425 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 20:00:08.263727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 20:00:08.264145 ==
5854 20:00:08.264473 DQS Delay:
5855 20:00:08.267220 DQS0 = 0, DQS1 = 0
5856 20:00:08.267802 DQM Delay:
5857 20:00:08.270531 DQM0 = 93, DQM1 = 88
5858 20:00:08.271046 DQ Delay:
5859 20:00:08.274169 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5860 20:00:08.276846 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =87
5861 20:00:08.280525 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5862 20:00:08.283891 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5863 20:00:08.284317
5864 20:00:08.284641
5865 20:00:08.284949 ==
5866 20:00:08.287259 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 20:00:08.290473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 20:00:08.290896 ==
5869 20:00:08.291223
5870 20:00:08.293975
5871 20:00:08.294480 TX Vref Scan disable
5872 20:00:08.297237 == TX Byte 0 ==
5873 20:00:08.300469 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5874 20:00:08.303705 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5875 20:00:08.306773 == TX Byte 1 ==
5876 20:00:08.310642 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5877 20:00:08.314348 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5878 20:00:08.314872 ==
5879 20:00:08.317282 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 20:00:08.324036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 20:00:08.324563 ==
5882 20:00:08.324898
5883 20:00:08.325207
5884 20:00:08.325502 TX Vref Scan disable
5885 20:00:08.327725 == TX Byte 0 ==
5886 20:00:08.331581 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5887 20:00:08.337443 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5888 20:00:08.337955 == TX Byte 1 ==
5889 20:00:08.341262 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5890 20:00:08.347497 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5891 20:00:08.348008
5892 20:00:08.348340 [DATLAT]
5893 20:00:08.348644 Freq=933, CH1 RK1
5894 20:00:08.348941
5895 20:00:08.351290 DATLAT Default: 0xb
5896 20:00:08.351856 0, 0xFFFF, sum = 0
5897 20:00:08.354778 1, 0xFFFF, sum = 0
5898 20:00:08.355302 2, 0xFFFF, sum = 0
5899 20:00:08.357911 3, 0xFFFF, sum = 0
5900 20:00:08.360901 4, 0xFFFF, sum = 0
5901 20:00:08.361500 5, 0xFFFF, sum = 0
5902 20:00:08.363854 6, 0xFFFF, sum = 0
5903 20:00:08.364384 7, 0xFFFF, sum = 0
5904 20:00:08.367747 8, 0xFFFF, sum = 0
5905 20:00:08.368266 9, 0xFFFF, sum = 0
5906 20:00:08.370589 10, 0x0, sum = 1
5907 20:00:08.371059 11, 0x0, sum = 2
5908 20:00:08.374127 12, 0x0, sum = 3
5909 20:00:08.374648 13, 0x0, sum = 4
5910 20:00:08.374983 best_step = 11
5911 20:00:08.377324
5912 20:00:08.377738 ==
5913 20:00:08.380809 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 20:00:08.383699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 20:00:08.384213 ==
5916 20:00:08.384543 RX Vref Scan: 0
5917 20:00:08.384849
5918 20:00:08.387170 RX Vref 0 -> 0, step: 1
5919 20:00:08.387633
5920 20:00:08.390687 RX Delay -69 -> 252, step: 4
5921 20:00:08.397129 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5922 20:00:08.400546 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5923 20:00:08.403702 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5924 20:00:08.407258 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5925 20:00:08.411291 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5926 20:00:08.414341 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5927 20:00:08.420722 iDelay=203, Bit 6, Center 100 (-1 ~ 202) 204
5928 20:00:08.423761 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5929 20:00:08.427338 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5930 20:00:08.431167 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5931 20:00:08.433872 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5932 20:00:08.440694 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5933 20:00:08.444016 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5934 20:00:08.447344 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5935 20:00:08.450640 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5936 20:00:08.454090 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5937 20:00:08.454511 ==
5938 20:00:08.457431 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 20:00:08.463635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 20:00:08.464145 ==
5941 20:00:08.464481 DQS Delay:
5942 20:00:08.467104 DQS0 = 0, DQS1 = 0
5943 20:00:08.467657 DQM Delay:
5944 20:00:08.467997 DQM0 = 91, DQM1 = 90
5945 20:00:08.470606 DQ Delay:
5946 20:00:08.474020 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5947 20:00:08.476589 DQ4 =90, DQ5 =102, DQ6 =100, DQ7 =88
5948 20:00:08.480336 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =82
5949 20:00:08.483574 DQ12 =100, DQ13 =96, DQ14 =100, DQ15 =98
5950 20:00:08.484082
5951 20:00:08.484417
5952 20:00:08.490344 [DQSOSCAuto] RK1, (LSB)MR18= 0x1125, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5953 20:00:08.493367 CH1 RK1: MR19=505, MR18=1125
5954 20:00:08.500065 CH1_RK1: MR19=0x505, MR18=0x1125, DQSOSC=410, MR23=63, INC=64, DEC=42
5955 20:00:08.503774 [RxdqsGatingPostProcess] freq 933
5956 20:00:08.509642 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5957 20:00:08.510061 best DQS0 dly(2T, 0.5T) = (0, 10)
5958 20:00:08.513717 best DQS1 dly(2T, 0.5T) = (0, 11)
5959 20:00:08.516449 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5960 20:00:08.519491 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5961 20:00:08.523108 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 20:00:08.526152 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 20:00:08.530547 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 20:00:08.533349 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 20:00:08.536428 Pre-setting of DQS Precalculation
5966 20:00:08.543354 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5967 20:00:08.550138 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5968 20:00:08.556660 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5969 20:00:08.557174
5970 20:00:08.557507
5971 20:00:08.559477 [Calibration Summary] 1866 Mbps
5972 20:00:08.559891 CH 0, Rank 0
5973 20:00:08.562896 SW Impedance : PASS
5974 20:00:08.566422 DUTY Scan : NO K
5975 20:00:08.566936 ZQ Calibration : PASS
5976 20:00:08.569305 Jitter Meter : NO K
5977 20:00:08.569722 CBT Training : PASS
5978 20:00:08.573089 Write leveling : PASS
5979 20:00:08.576329 RX DQS gating : PASS
5980 20:00:08.576833 RX DQ/DQS(RDDQC) : PASS
5981 20:00:08.579550 TX DQ/DQS : PASS
5982 20:00:08.582800 RX DATLAT : PASS
5983 20:00:08.583306 RX DQ/DQS(Engine): PASS
5984 20:00:08.586114 TX OE : NO K
5985 20:00:08.586624 All Pass.
5986 20:00:08.586957
5987 20:00:08.589442 CH 0, Rank 1
5988 20:00:08.589855 SW Impedance : PASS
5989 20:00:08.593101 DUTY Scan : NO K
5990 20:00:08.596247 ZQ Calibration : PASS
5991 20:00:08.596752 Jitter Meter : NO K
5992 20:00:08.599069 CBT Training : PASS
5993 20:00:08.602716 Write leveling : PASS
5994 20:00:08.603230 RX DQS gating : PASS
5995 20:00:08.606089 RX DQ/DQS(RDDQC) : PASS
5996 20:00:08.609025 TX DQ/DQS : PASS
5997 20:00:08.609462 RX DATLAT : PASS
5998 20:00:08.612703 RX DQ/DQS(Engine): PASS
5999 20:00:08.615913 TX OE : NO K
6000 20:00:08.616420 All Pass.
6001 20:00:08.616751
6002 20:00:08.617060 CH 1, Rank 0
6003 20:00:08.618959 SW Impedance : PASS
6004 20:00:08.622709 DUTY Scan : NO K
6005 20:00:08.623215 ZQ Calibration : PASS
6006 20:00:08.625667 Jitter Meter : NO K
6007 20:00:08.629041 CBT Training : PASS
6008 20:00:08.629548 Write leveling : PASS
6009 20:00:08.632179 RX DQS gating : PASS
6010 20:00:08.635551 RX DQ/DQS(RDDQC) : PASS
6011 20:00:08.636058 TX DQ/DQS : PASS
6012 20:00:08.639231 RX DATLAT : PASS
6013 20:00:08.639789 RX DQ/DQS(Engine): PASS
6014 20:00:08.642658 TX OE : NO K
6015 20:00:08.643177 All Pass.
6016 20:00:08.643591
6017 20:00:08.645707 CH 1, Rank 1
6018 20:00:08.646219 SW Impedance : PASS
6019 20:00:08.648699 DUTY Scan : NO K
6020 20:00:08.652540 ZQ Calibration : PASS
6021 20:00:08.653051 Jitter Meter : NO K
6022 20:00:08.655381 CBT Training : PASS
6023 20:00:08.659108 Write leveling : PASS
6024 20:00:08.659696 RX DQS gating : PASS
6025 20:00:08.661914 RX DQ/DQS(RDDQC) : PASS
6026 20:00:08.665214 TX DQ/DQS : PASS
6027 20:00:08.665733 RX DATLAT : PASS
6028 20:00:08.668502 RX DQ/DQS(Engine): PASS
6029 20:00:08.672251 TX OE : NO K
6030 20:00:08.672666 All Pass.
6031 20:00:08.672994
6032 20:00:08.675209 DramC Write-DBI off
6033 20:00:08.675664 PER_BANK_REFRESH: Hybrid Mode
6034 20:00:08.678685 TX_TRACKING: ON
6035 20:00:08.685448 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6036 20:00:08.692163 [FAST_K] Save calibration result to emmc
6037 20:00:08.695092 dramc_set_vcore_voltage set vcore to 650000
6038 20:00:08.695640 Read voltage for 400, 6
6039 20:00:08.698518 Vio18 = 0
6040 20:00:08.699032 Vcore = 650000
6041 20:00:08.699359 Vdram = 0
6042 20:00:08.701949 Vddq = 0
6043 20:00:08.702362 Vmddr = 0
6044 20:00:08.705379 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6045 20:00:08.711901 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6046 20:00:08.715124 MEM_TYPE=3, freq_sel=20
6047 20:00:08.718881 sv_algorithm_assistance_LP4_800
6048 20:00:08.722001 ============ PULL DRAM RESETB DOWN ============
6049 20:00:08.725192 ========== PULL DRAM RESETB DOWN end =========
6050 20:00:08.728962 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6051 20:00:08.731984 ===================================
6052 20:00:08.735214 LPDDR4 DRAM CONFIGURATION
6053 20:00:08.738835 ===================================
6054 20:00:08.741852 EX_ROW_EN[0] = 0x0
6055 20:00:08.742364 EX_ROW_EN[1] = 0x0
6056 20:00:08.745137 LP4Y_EN = 0x0
6057 20:00:08.745654 WORK_FSP = 0x0
6058 20:00:08.748708 WL = 0x2
6059 20:00:08.749223 RL = 0x2
6060 20:00:08.751770 BL = 0x2
6061 20:00:08.752280 RPST = 0x0
6062 20:00:08.755289 RD_PRE = 0x0
6063 20:00:08.755848 WR_PRE = 0x1
6064 20:00:08.758602 WR_PST = 0x0
6065 20:00:08.761683 DBI_WR = 0x0
6066 20:00:08.762231 DBI_RD = 0x0
6067 20:00:08.765018 OTF = 0x1
6068 20:00:08.767834 ===================================
6069 20:00:08.771911 ===================================
6070 20:00:08.772328 ANA top config
6071 20:00:08.775656 ===================================
6072 20:00:08.778103 DLL_ASYNC_EN = 0
6073 20:00:08.778550 ALL_SLAVE_EN = 1
6074 20:00:08.781726 NEW_RANK_MODE = 1
6075 20:00:08.784437 DLL_IDLE_MODE = 1
6076 20:00:08.788255 LP45_APHY_COMB_EN = 1
6077 20:00:08.791253 TX_ODT_DIS = 1
6078 20:00:08.791996 NEW_8X_MODE = 1
6079 20:00:08.794945 ===================================
6080 20:00:08.798423 ===================================
6081 20:00:08.801955 data_rate = 800
6082 20:00:08.805022 CKR = 1
6083 20:00:08.808334 DQ_P2S_RATIO = 4
6084 20:00:08.811746 ===================================
6085 20:00:08.815251 CA_P2S_RATIO = 4
6086 20:00:08.818283 DQ_CA_OPEN = 0
6087 20:00:08.818885 DQ_SEMI_OPEN = 1
6088 20:00:08.821134 CA_SEMI_OPEN = 1
6089 20:00:08.825048 CA_FULL_RATE = 0
6090 20:00:08.828094 DQ_CKDIV4_EN = 0
6091 20:00:08.831957 CA_CKDIV4_EN = 1
6092 20:00:08.834773 CA_PREDIV_EN = 0
6093 20:00:08.835311 PH8_DLY = 0
6094 20:00:08.838269 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6095 20:00:08.841966 DQ_AAMCK_DIV = 0
6096 20:00:08.844518 CA_AAMCK_DIV = 0
6097 20:00:08.848296 CA_ADMCK_DIV = 4
6098 20:00:08.848841 DQ_TRACK_CA_EN = 0
6099 20:00:08.851715 CA_PICK = 800
6100 20:00:08.854799 CA_MCKIO = 400
6101 20:00:08.858039 MCKIO_SEMI = 400
6102 20:00:08.861571 PLL_FREQ = 3016
6103 20:00:08.864737 DQ_UI_PI_RATIO = 32
6104 20:00:08.868041 CA_UI_PI_RATIO = 32
6105 20:00:08.871482 ===================================
6106 20:00:08.874988 ===================================
6107 20:00:08.877963 memory_type:LPDDR4
6108 20:00:08.878524 GP_NUM : 10
6109 20:00:08.881080 SRAM_EN : 1
6110 20:00:08.881514 MD32_EN : 0
6111 20:00:08.884564 ===================================
6112 20:00:08.888103 [ANA_INIT] >>>>>>>>>>>>>>
6113 20:00:08.891181 <<<<<< [CONFIGURE PHASE]: ANA_TX
6114 20:00:08.894639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6115 20:00:08.897487 ===================================
6116 20:00:08.900833 data_rate = 800,PCW = 0X7400
6117 20:00:08.904127 ===================================
6118 20:00:08.907775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6119 20:00:08.911034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6120 20:00:08.924600 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6121 20:00:08.927680 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6122 20:00:08.930609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6123 20:00:08.933985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6124 20:00:08.937560 [ANA_INIT] flow start
6125 20:00:08.940702 [ANA_INIT] PLL >>>>>>>>
6126 20:00:08.941125 [ANA_INIT] PLL <<<<<<<<
6127 20:00:08.944304 [ANA_INIT] MIDPI >>>>>>>>
6128 20:00:08.947429 [ANA_INIT] MIDPI <<<<<<<<
6129 20:00:08.947943 [ANA_INIT] DLL >>>>>>>>
6130 20:00:08.950632 [ANA_INIT] flow end
6131 20:00:08.954264 ============ LP4 DIFF to SE enter ============
6132 20:00:08.961081 ============ LP4 DIFF to SE exit ============
6133 20:00:08.961594 [ANA_INIT] <<<<<<<<<<<<<
6134 20:00:08.964080 [Flow] Enable top DCM control >>>>>
6135 20:00:08.967421 [Flow] Enable top DCM control <<<<<
6136 20:00:08.970500 Enable DLL master slave shuffle
6137 20:00:08.977322 ==============================================================
6138 20:00:08.977757 Gating Mode config
6139 20:00:08.983834 ==============================================================
6140 20:00:08.987291 Config description:
6141 20:00:08.994076 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6142 20:00:09.000469 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6143 20:00:09.006719 SELPH_MODE 0: By rank 1: By Phase
6144 20:00:09.013932 ==============================================================
6145 20:00:09.016868 GAT_TRACK_EN = 0
6146 20:00:09.017414 RX_GATING_MODE = 2
6147 20:00:09.020136 RX_GATING_TRACK_MODE = 2
6148 20:00:09.023104 SELPH_MODE = 1
6149 20:00:09.026912 PICG_EARLY_EN = 1
6150 20:00:09.029935 VALID_LAT_VALUE = 1
6151 20:00:09.036544 ==============================================================
6152 20:00:09.040271 Enter into Gating configuration >>>>
6153 20:00:09.043206 Exit from Gating configuration <<<<
6154 20:00:09.046432 Enter into DVFS_PRE_config >>>>>
6155 20:00:09.056379 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6156 20:00:09.060014 Exit from DVFS_PRE_config <<<<<
6157 20:00:09.063030 Enter into PICG configuration >>>>
6158 20:00:09.066509 Exit from PICG configuration <<<<
6159 20:00:09.069825 [RX_INPUT] configuration >>>>>
6160 20:00:09.073886 [RX_INPUT] configuration <<<<<
6161 20:00:09.076430 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6162 20:00:09.082697 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6163 20:00:09.089654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 20:00:09.092876 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 20:00:09.099659 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6166 20:00:09.106040 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6167 20:00:09.109519 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6168 20:00:09.116095 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6169 20:00:09.119300 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6170 20:00:09.122842 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6171 20:00:09.126234 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6172 20:00:09.132636 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6173 20:00:09.136170 ===================================
6174 20:00:09.136587 LPDDR4 DRAM CONFIGURATION
6175 20:00:09.139422 ===================================
6176 20:00:09.142504 EX_ROW_EN[0] = 0x0
6177 20:00:09.145865 EX_ROW_EN[1] = 0x0
6178 20:00:09.146283 LP4Y_EN = 0x0
6179 20:00:09.149730 WORK_FSP = 0x0
6180 20:00:09.150259 WL = 0x2
6181 20:00:09.152873 RL = 0x2
6182 20:00:09.153291 BL = 0x2
6183 20:00:09.156407 RPST = 0x0
6184 20:00:09.156919 RD_PRE = 0x0
6185 20:00:09.159481 WR_PRE = 0x1
6186 20:00:09.159902 WR_PST = 0x0
6187 20:00:09.162619 DBI_WR = 0x0
6188 20:00:09.163148 DBI_RD = 0x0
6189 20:00:09.166029 OTF = 0x1
6190 20:00:09.169332 ===================================
6191 20:00:09.172706 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6192 20:00:09.175696 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6193 20:00:09.182368 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 20:00:09.186210 ===================================
6195 20:00:09.186725 LPDDR4 DRAM CONFIGURATION
6196 20:00:09.189400 ===================================
6197 20:00:09.192144 EX_ROW_EN[0] = 0x10
6198 20:00:09.195731 EX_ROW_EN[1] = 0x0
6199 20:00:09.196241 LP4Y_EN = 0x0
6200 20:00:09.199545 WORK_FSP = 0x0
6201 20:00:09.200088 WL = 0x2
6202 20:00:09.202406 RL = 0x2
6203 20:00:09.202910 BL = 0x2
6204 20:00:09.206083 RPST = 0x0
6205 20:00:09.206594 RD_PRE = 0x0
6206 20:00:09.209371 WR_PRE = 0x1
6207 20:00:09.209785 WR_PST = 0x0
6208 20:00:09.212107 DBI_WR = 0x0
6209 20:00:09.212518 DBI_RD = 0x0
6210 20:00:09.215987 OTF = 0x1
6211 20:00:09.219114 ===================================
6212 20:00:09.226074 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6213 20:00:09.228745 nWR fixed to 30
6214 20:00:09.229179 [ModeRegInit_LP4] CH0 RK0
6215 20:00:09.232211 [ModeRegInit_LP4] CH0 RK1
6216 20:00:09.235720 [ModeRegInit_LP4] CH1 RK0
6217 20:00:09.239271 [ModeRegInit_LP4] CH1 RK1
6218 20:00:09.239986 match AC timing 19
6219 20:00:09.242325 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6220 20:00:09.249601 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6221 20:00:09.252250 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6222 20:00:09.255833 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6223 20:00:09.262692 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6224 20:00:09.263202 ==
6225 20:00:09.265281 Dram Type= 6, Freq= 0, CH_0, rank 0
6226 20:00:09.269062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6227 20:00:09.269592 ==
6228 20:00:09.275938 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6229 20:00:09.282906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6230 20:00:09.283482 [CA 0] Center 36 (8~64) winsize 57
6231 20:00:09.285783 [CA 1] Center 36 (8~64) winsize 57
6232 20:00:09.289361 [CA 2] Center 36 (8~64) winsize 57
6233 20:00:09.292332 [CA 3] Center 36 (8~64) winsize 57
6234 20:00:09.295789 [CA 4] Center 36 (8~64) winsize 57
6235 20:00:09.298972 [CA 5] Center 36 (8~64) winsize 57
6236 20:00:09.299530
6237 20:00:09.302377 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6238 20:00:09.302885
6239 20:00:09.305715 [CATrainingPosCal] consider 1 rank data
6240 20:00:09.308452 u2DelayCellTimex100 = 270/100 ps
6241 20:00:09.312485 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 20:00:09.315549 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 20:00:09.322244 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 20:00:09.325692 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 20:00:09.328636 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 20:00:09.332327 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 20:00:09.332836
6248 20:00:09.335079 CA PerBit enable=1, Macro0, CA PI delay=36
6249 20:00:09.335540
6250 20:00:09.338647 [CBTSetCACLKResult] CA Dly = 36
6251 20:00:09.339059 CS Dly: 1 (0~32)
6252 20:00:09.341943 ==
6253 20:00:09.342460 Dram Type= 6, Freq= 0, CH_0, rank 1
6254 20:00:09.348742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 20:00:09.349303 ==
6256 20:00:09.352321 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6257 20:00:09.358958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6258 20:00:09.362018 [CA 0] Center 36 (8~64) winsize 57
6259 20:00:09.365675 [CA 1] Center 36 (8~64) winsize 57
6260 20:00:09.368344 [CA 2] Center 36 (8~64) winsize 57
6261 20:00:09.371857 [CA 3] Center 36 (8~64) winsize 57
6262 20:00:09.375144 [CA 4] Center 36 (8~64) winsize 57
6263 20:00:09.378853 [CA 5] Center 36 (8~64) winsize 57
6264 20:00:09.379362
6265 20:00:09.381777 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6266 20:00:09.382287
6267 20:00:09.385110 [CATrainingPosCal] consider 2 rank data
6268 20:00:09.388701 u2DelayCellTimex100 = 270/100 ps
6269 20:00:09.391963 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 20:00:09.395659 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 20:00:09.398473 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 20:00:09.401813 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 20:00:09.408360 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 20:00:09.411241 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 20:00:09.411807
6276 20:00:09.415293 CA PerBit enable=1, Macro0, CA PI delay=36
6277 20:00:09.415864
6278 20:00:09.418577 [CBTSetCACLKResult] CA Dly = 36
6279 20:00:09.419201 CS Dly: 1 (0~32)
6280 20:00:09.419636
6281 20:00:09.421746 ----->DramcWriteLeveling(PI) begin...
6282 20:00:09.422264 ==
6283 20:00:09.424299 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 20:00:09.431189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 20:00:09.431827 ==
6286 20:00:09.434434 Write leveling (Byte 0): 40 => 8
6287 20:00:09.434845 Write leveling (Byte 1): 40 => 8
6288 20:00:09.437757 DramcWriteLeveling(PI) end<-----
6289 20:00:09.438266
6290 20:00:09.441261 ==
6291 20:00:09.441771 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 20:00:09.447860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 20:00:09.448268 ==
6294 20:00:09.450616 [Gating] SW mode calibration
6295 20:00:09.457377 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6296 20:00:09.460815 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6297 20:00:09.467575 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6298 20:00:09.470740 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6299 20:00:09.474050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 20:00:09.481011 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 20:00:09.483910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 20:00:09.487487 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 20:00:09.493925 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 20:00:09.496985 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 20:00:09.500572 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 20:00:09.504108 Total UI for P1: 0, mck2ui 16
6307 20:00:09.507831 best dqsien dly found for B0: ( 0, 14, 24)
6308 20:00:09.510184 Total UI for P1: 0, mck2ui 16
6309 20:00:09.513815 best dqsien dly found for B1: ( 0, 14, 24)
6310 20:00:09.517263 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6311 20:00:09.520397 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6312 20:00:09.520802
6313 20:00:09.527337 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6314 20:00:09.530612 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6315 20:00:09.533405 [Gating] SW calibration Done
6316 20:00:09.533816 ==
6317 20:00:09.537473 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 20:00:09.540804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 20:00:09.541314 ==
6320 20:00:09.541640 RX Vref Scan: 0
6321 20:00:09.541942
6322 20:00:09.543480 RX Vref 0 -> 0, step: 1
6323 20:00:09.543886
6324 20:00:09.546886 RX Delay -410 -> 252, step: 16
6325 20:00:09.550451 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6326 20:00:09.556611 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6327 20:00:09.560164 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6328 20:00:09.563222 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6329 20:00:09.566488 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6330 20:00:09.573040 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6331 20:00:09.576404 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6332 20:00:09.579512 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6333 20:00:09.582911 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6334 20:00:09.589972 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6335 20:00:09.592735 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6336 20:00:09.596194 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6337 20:00:09.599813 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6338 20:00:09.606042 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6339 20:00:09.609372 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6340 20:00:09.612992 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6341 20:00:09.613417 ==
6342 20:00:09.615906 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 20:00:09.623355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 20:00:09.623909 ==
6345 20:00:09.624240 DQS Delay:
6346 20:00:09.626039 DQS0 = 59, DQS1 = 59
6347 20:00:09.626537 DQM Delay:
6348 20:00:09.629450 DQM0 = 18, DQM1 = 10
6349 20:00:09.629856 DQ Delay:
6350 20:00:09.632715 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6351 20:00:09.636022 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6352 20:00:09.639259 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6353 20:00:09.642607 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6354 20:00:09.643114
6355 20:00:09.643476
6356 20:00:09.643784 ==
6357 20:00:09.646040 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 20:00:09.649342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 20:00:09.649863 ==
6360 20:00:09.650193
6361 20:00:09.650501
6362 20:00:09.653003 TX Vref Scan disable
6363 20:00:09.653521 == TX Byte 0 ==
6364 20:00:09.659499 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 20:00:09.662373 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 20:00:09.662888 == TX Byte 1 ==
6367 20:00:09.669421 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 20:00:09.672104 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 20:00:09.672525 ==
6370 20:00:09.675608 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 20:00:09.679089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 20:00:09.679653 ==
6373 20:00:09.680028
6374 20:00:09.680345
6375 20:00:09.682606 TX Vref Scan disable
6376 20:00:09.683122 == TX Byte 0 ==
6377 20:00:09.688384 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 20:00:09.692066 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 20:00:09.692723 == TX Byte 1 ==
6380 20:00:09.698847 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6381 20:00:09.701735 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6382 20:00:09.702155
6383 20:00:09.702483 [DATLAT]
6384 20:00:09.705697 Freq=400, CH0 RK0
6385 20:00:09.706264
6386 20:00:09.706598 DATLAT Default: 0xf
6387 20:00:09.708522 0, 0xFFFF, sum = 0
6388 20:00:09.708942 1, 0xFFFF, sum = 0
6389 20:00:09.712088 2, 0xFFFF, sum = 0
6390 20:00:09.712508 3, 0xFFFF, sum = 0
6391 20:00:09.716022 4, 0xFFFF, sum = 0
6392 20:00:09.716543 5, 0xFFFF, sum = 0
6393 20:00:09.718459 6, 0xFFFF, sum = 0
6394 20:00:09.718879 7, 0xFFFF, sum = 0
6395 20:00:09.722382 8, 0xFFFF, sum = 0
6396 20:00:09.725025 9, 0xFFFF, sum = 0
6397 20:00:09.725613 10, 0xFFFF, sum = 0
6398 20:00:09.728464 11, 0xFFFF, sum = 0
6399 20:00:09.728883 12, 0xFFFF, sum = 0
6400 20:00:09.731823 13, 0x0, sum = 1
6401 20:00:09.732366 14, 0x0, sum = 2
6402 20:00:09.735370 15, 0x0, sum = 3
6403 20:00:09.735930 16, 0x0, sum = 4
6404 20:00:09.736269 best_step = 14
6405 20:00:09.736576
6406 20:00:09.738723 ==
6407 20:00:09.742290 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 20:00:09.745150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 20:00:09.745579 ==
6410 20:00:09.745903 RX Vref Scan: 1
6411 20:00:09.746202
6412 20:00:09.748119 RX Vref 0 -> 0, step: 1
6413 20:00:09.748545
6414 20:00:09.751339 RX Delay -359 -> 252, step: 8
6415 20:00:09.751919
6416 20:00:09.755090 Set Vref, RX VrefLevel [Byte0]: 61
6417 20:00:09.758192 [Byte1]: 52
6418 20:00:09.762406
6419 20:00:09.762910 Final RX Vref Byte 0 = 61 to rank0
6420 20:00:09.765104 Final RX Vref Byte 1 = 52 to rank0
6421 20:00:09.768745 Final RX Vref Byte 0 = 61 to rank1
6422 20:00:09.772273 Final RX Vref Byte 1 = 52 to rank1==
6423 20:00:09.775071 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 20:00:09.782096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 20:00:09.782626 ==
6426 20:00:09.783111 DQS Delay:
6427 20:00:09.785319 DQS0 = 60, DQS1 = 68
6428 20:00:09.785736 DQM Delay:
6429 20:00:09.786067 DQM0 = 14, DQM1 = 13
6430 20:00:09.788938 DQ Delay:
6431 20:00:09.791920 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =12
6432 20:00:09.795345 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6433 20:00:09.795819 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6434 20:00:09.798796 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6435 20:00:09.801880
6436 20:00:09.802362
6437 20:00:09.809195 [DQSOSCAuto] RK0, (LSB)MR18= 0x8584, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6438 20:00:09.812093 CH0 RK0: MR19=C0C, MR18=8584
6439 20:00:09.818875 CH0_RK0: MR19=0xC0C, MR18=0x8584, DQSOSC=393, MR23=63, INC=382, DEC=254
6440 20:00:09.819436 ==
6441 20:00:09.821784 Dram Type= 6, Freq= 0, CH_0, rank 1
6442 20:00:09.825367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 20:00:09.826057 ==
6444 20:00:09.828927 [Gating] SW mode calibration
6445 20:00:09.835227 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6446 20:00:09.842073 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6447 20:00:09.845624 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6448 20:00:09.848322 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 20:00:09.855549 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 20:00:09.858664 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 20:00:09.862010 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 20:00:09.868214 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 20:00:09.871782 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 20:00:09.875756 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 20:00:09.881981 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 20:00:09.882488 Total UI for P1: 0, mck2ui 16
6457 20:00:09.884887 best dqsien dly found for B0: ( 0, 14, 24)
6458 20:00:09.887890 Total UI for P1: 0, mck2ui 16
6459 20:00:09.891521 best dqsien dly found for B1: ( 0, 14, 24)
6460 20:00:09.898145 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6461 20:00:09.902048 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6462 20:00:09.902577
6463 20:00:09.904669 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6464 20:00:09.908073 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6465 20:00:09.911064 [Gating] SW calibration Done
6466 20:00:09.911506 ==
6467 20:00:09.914801 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 20:00:09.918424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 20:00:09.918951 ==
6470 20:00:09.921402 RX Vref Scan: 0
6471 20:00:09.921928
6472 20:00:09.922267 RX Vref 0 -> 0, step: 1
6473 20:00:09.922579
6474 20:00:09.924576 RX Delay -410 -> 252, step: 16
6475 20:00:09.930958 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6476 20:00:09.934116 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6477 20:00:09.938093 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6478 20:00:09.941068 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6479 20:00:09.948300 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6480 20:00:09.951299 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6481 20:00:09.954678 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6482 20:00:09.958234 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6483 20:00:09.961817 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6484 20:00:09.968087 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6485 20:00:09.971171 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6486 20:00:09.974471 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6487 20:00:09.981353 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6488 20:00:09.984261 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6489 20:00:09.988030 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6490 20:00:09.991195 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6491 20:00:09.991769 ==
6492 20:00:09.994179 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 20:00:10.001075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 20:00:10.001587 ==
6495 20:00:10.001925 DQS Delay:
6496 20:00:10.004257 DQS0 = 59, DQS1 = 59
6497 20:00:10.004675 DQM Delay:
6498 20:00:10.007250 DQM0 = 16, DQM1 = 10
6499 20:00:10.007701 DQ Delay:
6500 20:00:10.010392 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6501 20:00:10.014162 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6502 20:00:10.017333 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6503 20:00:10.020708 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6504 20:00:10.021231
6505 20:00:10.021566
6506 20:00:10.021876 ==
6507 20:00:10.024064 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 20:00:10.027329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 20:00:10.027797 ==
6510 20:00:10.028133
6511 20:00:10.028444
6512 20:00:10.031095 TX Vref Scan disable
6513 20:00:10.031555 == TX Byte 0 ==
6514 20:00:10.037389 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6515 20:00:10.040691 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6516 20:00:10.041218 == TX Byte 1 ==
6517 20:00:10.047461 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6518 20:00:10.050612 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6519 20:00:10.051132 ==
6520 20:00:10.054433 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 20:00:10.057629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 20:00:10.058159 ==
6523 20:00:10.058493
6524 20:00:10.058856
6525 20:00:10.060330 TX Vref Scan disable
6526 20:00:10.060749 == TX Byte 0 ==
6527 20:00:10.067070 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6528 20:00:10.070961 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6529 20:00:10.071527 == TX Byte 1 ==
6530 20:00:10.077324 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6531 20:00:10.080572 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6532 20:00:10.080992
6533 20:00:10.081321 [DATLAT]
6534 20:00:10.083594 Freq=400, CH0 RK1
6535 20:00:10.084015
6536 20:00:10.084419 DATLAT Default: 0xe
6537 20:00:10.087295 0, 0xFFFF, sum = 0
6538 20:00:10.087903 1, 0xFFFF, sum = 0
6539 20:00:10.090223 2, 0xFFFF, sum = 0
6540 20:00:10.090691 3, 0xFFFF, sum = 0
6541 20:00:10.093483 4, 0xFFFF, sum = 0
6542 20:00:10.094016 5, 0xFFFF, sum = 0
6543 20:00:10.097002 6, 0xFFFF, sum = 0
6544 20:00:10.097532 7, 0xFFFF, sum = 0
6545 20:00:10.100101 8, 0xFFFF, sum = 0
6546 20:00:10.100526 9, 0xFFFF, sum = 0
6547 20:00:10.103375 10, 0xFFFF, sum = 0
6548 20:00:10.106704 11, 0xFFFF, sum = 0
6549 20:00:10.107127 12, 0xFFFF, sum = 0
6550 20:00:10.110355 13, 0x0, sum = 1
6551 20:00:10.110782 14, 0x0, sum = 2
6552 20:00:10.113708 15, 0x0, sum = 3
6553 20:00:10.114251 16, 0x0, sum = 4
6554 20:00:10.114615 best_step = 14
6555 20:00:10.115162
6556 20:00:10.117268 ==
6557 20:00:10.120269 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 20:00:10.123348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 20:00:10.123863 ==
6560 20:00:10.124204 RX Vref Scan: 0
6561 20:00:10.124521
6562 20:00:10.127085 RX Vref 0 -> 0, step: 1
6563 20:00:10.127737
6564 20:00:10.129778 RX Delay -359 -> 252, step: 8
6565 20:00:10.137257 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6566 20:00:10.140407 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6567 20:00:10.143714 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6568 20:00:10.147137 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6569 20:00:10.153204 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6570 20:00:10.156468 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6571 20:00:10.160301 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6572 20:00:10.163325 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6573 20:00:10.170486 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6574 20:00:10.172992 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6575 20:00:10.176408 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6576 20:00:10.183284 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6577 20:00:10.187232 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6578 20:00:10.190164 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6579 20:00:10.193192 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6580 20:00:10.199550 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6581 20:00:10.199972 ==
6582 20:00:10.202726 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 20:00:10.206442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 20:00:10.206967 ==
6585 20:00:10.207306 DQS Delay:
6586 20:00:10.209595 DQS0 = 60, DQS1 = 72
6587 20:00:10.210011 DQM Delay:
6588 20:00:10.213421 DQM0 = 11, DQM1 = 17
6589 20:00:10.213942 DQ Delay:
6590 20:00:10.216780 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6591 20:00:10.219345 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6592 20:00:10.222670 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6593 20:00:10.226462 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =24
6594 20:00:10.226883
6595 20:00:10.227219
6596 20:00:10.232521 [DQSOSCAuto] RK1, (LSB)MR18= 0xc77c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6597 20:00:10.235914 CH0 RK1: MR19=C0C, MR18=C77C
6598 20:00:10.243220 CH0_RK1: MR19=0xC0C, MR18=0xC77C, DQSOSC=385, MR23=63, INC=398, DEC=265
6599 20:00:10.246829 [RxdqsGatingPostProcess] freq 400
6600 20:00:10.253283 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6601 20:00:10.256450 best DQS0 dly(2T, 0.5T) = (0, 10)
6602 20:00:10.256979 best DQS1 dly(2T, 0.5T) = (0, 10)
6603 20:00:10.260250 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6604 20:00:10.263102 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6605 20:00:10.266401 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 20:00:10.270181 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 20:00:10.272614 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 20:00:10.276170 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 20:00:10.279360 Pre-setting of DQS Precalculation
6610 20:00:10.285735 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6611 20:00:10.286259 ==
6612 20:00:10.289777 Dram Type= 6, Freq= 0, CH_1, rank 0
6613 20:00:10.292958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 20:00:10.293470 ==
6615 20:00:10.299221 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6616 20:00:10.302902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6617 20:00:10.305854 [CA 0] Center 36 (8~64) winsize 57
6618 20:00:10.309374 [CA 1] Center 36 (8~64) winsize 57
6619 20:00:10.312412 [CA 2] Center 36 (8~64) winsize 57
6620 20:00:10.315317 [CA 3] Center 36 (8~64) winsize 57
6621 20:00:10.318859 [CA 4] Center 36 (8~64) winsize 57
6622 20:00:10.322018 [CA 5] Center 36 (8~64) winsize 57
6623 20:00:10.322433
6624 20:00:10.325199 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6625 20:00:10.325635
6626 20:00:10.328714 [CATrainingPosCal] consider 1 rank data
6627 20:00:10.331901 u2DelayCellTimex100 = 270/100 ps
6628 20:00:10.335438 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 20:00:10.342141 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 20:00:10.345804 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 20:00:10.348489 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 20:00:10.352120 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 20:00:10.355313 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 20:00:10.355892
6635 20:00:10.358528 CA PerBit enable=1, Macro0, CA PI delay=36
6636 20:00:10.359050
6637 20:00:10.362123 [CBTSetCACLKResult] CA Dly = 36
6638 20:00:10.362644 CS Dly: 1 (0~32)
6639 20:00:10.365751 ==
6640 20:00:10.368509 Dram Type= 6, Freq= 0, CH_1, rank 1
6641 20:00:10.372129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 20:00:10.372655 ==
6643 20:00:10.378457 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6644 20:00:10.381817 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6645 20:00:10.385480 [CA 0] Center 36 (8~64) winsize 57
6646 20:00:10.388458 [CA 1] Center 36 (8~64) winsize 57
6647 20:00:10.392197 [CA 2] Center 36 (8~64) winsize 57
6648 20:00:10.395318 [CA 3] Center 36 (8~64) winsize 57
6649 20:00:10.398410 [CA 4] Center 36 (8~64) winsize 57
6650 20:00:10.401442 [CA 5] Center 36 (8~64) winsize 57
6651 20:00:10.401947
6652 20:00:10.405370 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6653 20:00:10.405893
6654 20:00:10.408056 [CATrainingPosCal] consider 2 rank data
6655 20:00:10.411489 u2DelayCellTimex100 = 270/100 ps
6656 20:00:10.414771 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 20:00:10.418189 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 20:00:10.421217 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 20:00:10.424653 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 20:00:10.431214 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 20:00:10.434529 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 20:00:10.434952
6663 20:00:10.437880 CA PerBit enable=1, Macro0, CA PI delay=36
6664 20:00:10.438308
6665 20:00:10.441613 [CBTSetCACLKResult] CA Dly = 36
6666 20:00:10.442135 CS Dly: 1 (0~32)
6667 20:00:10.442603
6668 20:00:10.445059 ----->DramcWriteLeveling(PI) begin...
6669 20:00:10.445593 ==
6670 20:00:10.447776 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 20:00:10.454338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 20:00:10.454869 ==
6673 20:00:10.457841 Write leveling (Byte 0): 40 => 8
6674 20:00:10.461109 Write leveling (Byte 1): 40 => 8
6675 20:00:10.461646 DramcWriteLeveling(PI) end<-----
6676 20:00:10.462089
6677 20:00:10.464289 ==
6678 20:00:10.467817 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 20:00:10.471427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 20:00:10.471955 ==
6681 20:00:10.474384 [Gating] SW mode calibration
6682 20:00:10.481317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6683 20:00:10.484351 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6684 20:00:10.491075 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6685 20:00:10.494271 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6686 20:00:10.498175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 20:00:10.504378 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 20:00:10.507600 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 20:00:10.510892 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 20:00:10.517650 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 20:00:10.521321 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 20:00:10.524000 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 20:00:10.527853 Total UI for P1: 0, mck2ui 16
6694 20:00:10.530545 best dqsien dly found for B0: ( 0, 14, 24)
6695 20:00:10.534200 Total UI for P1: 0, mck2ui 16
6696 20:00:10.537592 best dqsien dly found for B1: ( 0, 14, 24)
6697 20:00:10.540815 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6698 20:00:10.543962 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6699 20:00:10.544483
6700 20:00:10.550430 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6701 20:00:10.554120 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6702 20:00:10.557151 [Gating] SW calibration Done
6703 20:00:10.557674 ==
6704 20:00:10.561046 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 20:00:10.563610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 20:00:10.564037 ==
6707 20:00:10.564372 RX Vref Scan: 0
6708 20:00:10.564684
6709 20:00:10.567104 RX Vref 0 -> 0, step: 1
6710 20:00:10.567672
6711 20:00:10.570295 RX Delay -410 -> 252, step: 16
6712 20:00:10.573485 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6713 20:00:10.580121 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6714 20:00:10.583489 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6715 20:00:10.587332 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6716 20:00:10.590246 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6717 20:00:10.596522 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6718 20:00:10.600388 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6719 20:00:10.603992 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6720 20:00:10.606854 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6721 20:00:10.613669 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6722 20:00:10.616518 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6723 20:00:10.620491 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6724 20:00:10.623606 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6725 20:00:10.629764 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6726 20:00:10.632861 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6727 20:00:10.636446 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6728 20:00:10.636900 ==
6729 20:00:10.639306 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 20:00:10.646344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 20:00:10.646870 ==
6732 20:00:10.647210 DQS Delay:
6733 20:00:10.649818 DQS0 = 51, DQS1 = 67
6734 20:00:10.650347 DQM Delay:
6735 20:00:10.650692 DQM0 = 12, DQM1 = 18
6736 20:00:10.652446 DQ Delay:
6737 20:00:10.655923 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6738 20:00:10.659335 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6739 20:00:10.659812 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6740 20:00:10.666266 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6741 20:00:10.666855
6742 20:00:10.667427
6743 20:00:10.667776 ==
6744 20:00:10.669607 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 20:00:10.672429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 20:00:10.672852 ==
6747 20:00:10.673184
6748 20:00:10.673494
6749 20:00:10.675748 TX Vref Scan disable
6750 20:00:10.676164 == TX Byte 0 ==
6751 20:00:10.679053 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 20:00:10.685931 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 20:00:10.686454 == TX Byte 1 ==
6754 20:00:10.689426 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 20:00:10.695821 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 20:00:10.696333 ==
6757 20:00:10.699614 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 20:00:10.702841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 20:00:10.703369 ==
6760 20:00:10.703778
6761 20:00:10.704095
6762 20:00:10.705655 TX Vref Scan disable
6763 20:00:10.706074 == TX Byte 0 ==
6764 20:00:10.712749 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 20:00:10.715779 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 20:00:10.716286 == TX Byte 1 ==
6767 20:00:10.722977 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 20:00:10.725775 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 20:00:10.726281
6770 20:00:10.726610 [DATLAT]
6771 20:00:10.729039 Freq=400, CH1 RK0
6772 20:00:10.729452
6773 20:00:10.729774 DATLAT Default: 0xf
6774 20:00:10.732014 0, 0xFFFF, sum = 0
6775 20:00:10.732429 1, 0xFFFF, sum = 0
6776 20:00:10.735437 2, 0xFFFF, sum = 0
6777 20:00:10.735859 3, 0xFFFF, sum = 0
6778 20:00:10.739063 4, 0xFFFF, sum = 0
6779 20:00:10.739629 5, 0xFFFF, sum = 0
6780 20:00:10.741813 6, 0xFFFF, sum = 0
6781 20:00:10.742229 7, 0xFFFF, sum = 0
6782 20:00:10.745287 8, 0xFFFF, sum = 0
6783 20:00:10.745708 9, 0xFFFF, sum = 0
6784 20:00:10.748639 10, 0xFFFF, sum = 0
6785 20:00:10.749062 11, 0xFFFF, sum = 0
6786 20:00:10.752304 12, 0xFFFF, sum = 0
6787 20:00:10.755205 13, 0x0, sum = 1
6788 20:00:10.755712 14, 0x0, sum = 2
6789 20:00:10.756050 15, 0x0, sum = 3
6790 20:00:10.758872 16, 0x0, sum = 4
6791 20:00:10.759289 best_step = 14
6792 20:00:10.759673
6793 20:00:10.759983 ==
6794 20:00:10.762239 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 20:00:10.769264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 20:00:10.769778 ==
6797 20:00:10.770112 RX Vref Scan: 1
6798 20:00:10.770416
6799 20:00:10.772009 RX Vref 0 -> 0, step: 1
6800 20:00:10.772447
6801 20:00:10.775724 RX Delay -375 -> 252, step: 8
6802 20:00:10.776136
6803 20:00:10.779216 Set Vref, RX VrefLevel [Byte0]: 53
6804 20:00:10.782311 [Byte1]: 49
6805 20:00:10.785865
6806 20:00:10.786370 Final RX Vref Byte 0 = 53 to rank0
6807 20:00:10.788929 Final RX Vref Byte 1 = 49 to rank0
6808 20:00:10.792302 Final RX Vref Byte 0 = 53 to rank1
6809 20:00:10.795169 Final RX Vref Byte 1 = 49 to rank1==
6810 20:00:10.798504 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 20:00:10.805352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 20:00:10.805868 ==
6813 20:00:10.806199 DQS Delay:
6814 20:00:10.809067 DQS0 = 52, DQS1 = 64
6815 20:00:10.809585 DQM Delay:
6816 20:00:10.809918 DQM0 = 10, DQM1 = 10
6817 20:00:10.812030 DQ Delay:
6818 20:00:10.815542 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6819 20:00:10.816102 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6820 20:00:10.819316 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6821 20:00:10.822110 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6822 20:00:10.822622
6823 20:00:10.822952
6824 20:00:10.831738 [DQSOSCAuto] RK0, (LSB)MR18= 0x586c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6825 20:00:10.835228 CH1 RK0: MR19=C0C, MR18=586C
6826 20:00:10.841463 CH1_RK0: MR19=0xC0C, MR18=0x586C, DQSOSC=396, MR23=63, INC=376, DEC=251
6827 20:00:10.841963 ==
6828 20:00:10.845073 Dram Type= 6, Freq= 0, CH_1, rank 1
6829 20:00:10.848314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 20:00:10.848833 ==
6831 20:00:10.851659 [Gating] SW mode calibration
6832 20:00:10.858286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6833 20:00:10.864914 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6834 20:00:10.868071 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6835 20:00:10.871671 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6836 20:00:10.874581 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 20:00:10.881676 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 20:00:10.884674 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 20:00:10.888122 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 20:00:10.895176 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 20:00:10.898862 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 20:00:10.901642 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 20:00:10.904578 Total UI for P1: 0, mck2ui 16
6844 20:00:10.908119 best dqsien dly found for B0: ( 0, 14, 24)
6845 20:00:10.911610 Total UI for P1: 0, mck2ui 16
6846 20:00:10.915152 best dqsien dly found for B1: ( 0, 14, 24)
6847 20:00:10.917829 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6848 20:00:10.924546 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6849 20:00:10.925138
6850 20:00:10.928192 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6851 20:00:10.931157 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6852 20:00:10.935086 [Gating] SW calibration Done
6853 20:00:10.935636 ==
6854 20:00:10.938049 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 20:00:10.941175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 20:00:10.941591 ==
6857 20:00:10.945129 RX Vref Scan: 0
6858 20:00:10.945640
6859 20:00:10.945969 RX Vref 0 -> 0, step: 1
6860 20:00:10.946274
6861 20:00:10.947868 RX Delay -410 -> 252, step: 16
6862 20:00:10.951466 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6863 20:00:10.958132 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6864 20:00:10.961536 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6865 20:00:10.964810 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6866 20:00:10.967561 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6867 20:00:10.974681 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6868 20:00:10.978489 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6869 20:00:10.980948 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6870 20:00:10.984051 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6871 20:00:10.990936 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6872 20:00:10.994773 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6873 20:00:10.998034 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6874 20:00:11.001717 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6875 20:00:11.008138 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6876 20:00:11.011092 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6877 20:00:11.014338 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6878 20:00:11.014888 ==
6879 20:00:11.017322 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 20:00:11.023921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 20:00:11.024434 ==
6882 20:00:11.024874 DQS Delay:
6883 20:00:11.027649 DQS0 = 59, DQS1 = 59
6884 20:00:11.028168 DQM Delay:
6885 20:00:11.028611 DQM0 = 19, DQM1 = 12
6886 20:00:11.030882 DQ Delay:
6887 20:00:11.034493 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6888 20:00:11.038071 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6889 20:00:11.040819 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6890 20:00:11.044365 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6891 20:00:11.044879
6892 20:00:11.045204
6893 20:00:11.045504 ==
6894 20:00:11.048008 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 20:00:11.050859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 20:00:11.051371 ==
6897 20:00:11.051744
6898 20:00:11.052055
6899 20:00:11.054043 TX Vref Scan disable
6900 20:00:11.054452 == TX Byte 0 ==
6901 20:00:11.057798 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6902 20:00:11.063933 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6903 20:00:11.064346 == TX Byte 1 ==
6904 20:00:11.067791 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6905 20:00:11.074307 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6906 20:00:11.074825 ==
6907 20:00:11.077806 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 20:00:11.080982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 20:00:11.081424 ==
6910 20:00:11.081855
6911 20:00:11.082261
6912 20:00:11.084502 TX Vref Scan disable
6913 20:00:11.084939 == TX Byte 0 ==
6914 20:00:11.087493 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6915 20:00:11.093967 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6916 20:00:11.094496 == TX Byte 1 ==
6917 20:00:11.097021 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6918 20:00:11.103516 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6919 20:00:11.104023
6920 20:00:11.104525 [DATLAT]
6921 20:00:11.107527 Freq=400, CH1 RK1
6922 20:00:11.108062
6923 20:00:11.108505 DATLAT Default: 0xe
6924 20:00:11.110562 0, 0xFFFF, sum = 0
6925 20:00:11.111009 1, 0xFFFF, sum = 0
6926 20:00:11.113701 2, 0xFFFF, sum = 0
6927 20:00:11.114191 3, 0xFFFF, sum = 0
6928 20:00:11.117205 4, 0xFFFF, sum = 0
6929 20:00:11.117632 5, 0xFFFF, sum = 0
6930 20:00:11.120106 6, 0xFFFF, sum = 0
6931 20:00:11.120536 7, 0xFFFF, sum = 0
6932 20:00:11.123812 8, 0xFFFF, sum = 0
6933 20:00:11.124347 9, 0xFFFF, sum = 0
6934 20:00:11.127030 10, 0xFFFF, sum = 0
6935 20:00:11.127601 11, 0xFFFF, sum = 0
6936 20:00:11.130517 12, 0xFFFF, sum = 0
6937 20:00:11.131050 13, 0x0, sum = 1
6938 20:00:11.133522 14, 0x0, sum = 2
6939 20:00:11.133995 15, 0x0, sum = 3
6940 20:00:11.137261 16, 0x0, sum = 4
6941 20:00:11.137690 best_step = 14
6942 20:00:11.138142
6943 20:00:11.138549 ==
6944 20:00:11.140199 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 20:00:11.146894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 20:00:11.147460 ==
6947 20:00:11.147902 RX Vref Scan: 0
6948 20:00:11.148310
6949 20:00:11.150172 RX Vref 0 -> 0, step: 1
6950 20:00:11.150595
6951 20:00:11.153629 RX Delay -359 -> 252, step: 8
6952 20:00:11.160251 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6953 20:00:11.163723 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6954 20:00:11.167177 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6955 20:00:11.170215 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6956 20:00:11.177333 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6957 20:00:11.180156 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6958 20:00:11.183539 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6959 20:00:11.186870 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6960 20:00:11.193426 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6961 20:00:11.196686 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6962 20:00:11.200261 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6963 20:00:11.202861 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6964 20:00:11.210465 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6965 20:00:11.213306 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6966 20:00:11.216273 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6967 20:00:11.223354 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6968 20:00:11.223990 ==
6969 20:00:11.226252 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 20:00:11.229733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 20:00:11.230153 ==
6972 20:00:11.230544 DQS Delay:
6973 20:00:11.232823 DQS0 = 60, DQS1 = 64
6974 20:00:11.233236 DQM Delay:
6975 20:00:11.236447 DQM0 = 13, DQM1 = 10
6976 20:00:11.236853 DQ Delay:
6977 20:00:11.239849 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6978 20:00:11.242911 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6979 20:00:11.246482 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6980 20:00:11.249715 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6981 20:00:11.250142
6982 20:00:11.250469
6983 20:00:11.256506 [DQSOSCAuto] RK1, (LSB)MR18= 0x75a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6984 20:00:11.259500 CH1 RK1: MR19=C0C, MR18=75A6
6985 20:00:11.266217 CH1_RK1: MR19=0xC0C, MR18=0x75A6, DQSOSC=389, MR23=63, INC=390, DEC=260
6986 20:00:11.270075 [RxdqsGatingPostProcess] freq 400
6987 20:00:11.276649 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6988 20:00:11.277165 best DQS0 dly(2T, 0.5T) = (0, 10)
6989 20:00:11.280155 best DQS1 dly(2T, 0.5T) = (0, 10)
6990 20:00:11.282711 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6991 20:00:11.286313 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6992 20:00:11.289434 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 20:00:11.292807 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 20:00:11.295864 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 20:00:11.299327 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 20:00:11.302569 Pre-setting of DQS Precalculation
6997 20:00:11.309286 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6998 20:00:11.315938 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6999 20:00:11.323332 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7000 20:00:11.323908
7001 20:00:11.324340
7002 20:00:11.325822 [Calibration Summary] 800 Mbps
7003 20:00:11.326233 CH 0, Rank 0
7004 20:00:11.329620 SW Impedance : PASS
7005 20:00:11.332371 DUTY Scan : NO K
7006 20:00:11.332812 ZQ Calibration : PASS
7007 20:00:11.335669 Jitter Meter : NO K
7008 20:00:11.338667 CBT Training : PASS
7009 20:00:11.339076 Write leveling : PASS
7010 20:00:11.342517 RX DQS gating : PASS
7011 20:00:11.343028 RX DQ/DQS(RDDQC) : PASS
7012 20:00:11.346005 TX DQ/DQS : PASS
7013 20:00:11.349257 RX DATLAT : PASS
7014 20:00:11.349768 RX DQ/DQS(Engine): PASS
7015 20:00:11.352114 TX OE : NO K
7016 20:00:11.352527 All Pass.
7017 20:00:11.352857
7018 20:00:11.355751 CH 0, Rank 1
7019 20:00:11.356191 SW Impedance : PASS
7020 20:00:11.358949 DUTY Scan : NO K
7021 20:00:11.362272 ZQ Calibration : PASS
7022 20:00:11.362687 Jitter Meter : NO K
7023 20:00:11.365366 CBT Training : PASS
7024 20:00:11.368973 Write leveling : NO K
7025 20:00:11.369484 RX DQS gating : PASS
7026 20:00:11.372081 RX DQ/DQS(RDDQC) : PASS
7027 20:00:11.375504 TX DQ/DQS : PASS
7028 20:00:11.376011 RX DATLAT : PASS
7029 20:00:11.379043 RX DQ/DQS(Engine): PASS
7030 20:00:11.382373 TX OE : NO K
7031 20:00:11.383048 All Pass.
7032 20:00:11.383580
7033 20:00:11.383906 CH 1, Rank 0
7034 20:00:11.385465 SW Impedance : PASS
7035 20:00:11.389387 DUTY Scan : NO K
7036 20:00:11.389898 ZQ Calibration : PASS
7037 20:00:11.392784 Jitter Meter : NO K
7038 20:00:11.393297 CBT Training : PASS
7039 20:00:11.395360 Write leveling : PASS
7040 20:00:11.398878 RX DQS gating : PASS
7041 20:00:11.399289 RX DQ/DQS(RDDQC) : PASS
7042 20:00:11.401932 TX DQ/DQS : PASS
7043 20:00:11.405704 RX DATLAT : PASS
7044 20:00:11.406221 RX DQ/DQS(Engine): PASS
7045 20:00:11.408551 TX OE : NO K
7046 20:00:11.409069 All Pass.
7047 20:00:11.409401
7048 20:00:11.411820 CH 1, Rank 1
7049 20:00:11.412326 SW Impedance : PASS
7050 20:00:11.414880 DUTY Scan : NO K
7051 20:00:11.418463 ZQ Calibration : PASS
7052 20:00:11.418872 Jitter Meter : NO K
7053 20:00:11.422364 CBT Training : PASS
7054 20:00:11.425394 Write leveling : NO K
7055 20:00:11.425806 RX DQS gating : PASS
7056 20:00:11.428404 RX DQ/DQS(RDDQC) : PASS
7057 20:00:11.432008 TX DQ/DQS : PASS
7058 20:00:11.432528 RX DATLAT : PASS
7059 20:00:11.435353 RX DQ/DQS(Engine): PASS
7060 20:00:11.438433 TX OE : NO K
7061 20:00:11.438950 All Pass.
7062 20:00:11.439279
7063 20:00:11.439630 DramC Write-DBI off
7064 20:00:11.441918 PER_BANK_REFRESH: Hybrid Mode
7065 20:00:11.445709 TX_TRACKING: ON
7066 20:00:11.452008 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7067 20:00:11.455026 [FAST_K] Save calibration result to emmc
7068 20:00:11.461667 dramc_set_vcore_voltage set vcore to 725000
7069 20:00:11.462172 Read voltage for 1600, 0
7070 20:00:11.465354 Vio18 = 0
7071 20:00:11.465860 Vcore = 725000
7072 20:00:11.466191 Vdram = 0
7073 20:00:11.468683 Vddq = 0
7074 20:00:11.469189 Vmddr = 0
7075 20:00:11.471309 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7076 20:00:11.478015 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7077 20:00:11.481356 MEM_TYPE=3, freq_sel=13
7078 20:00:11.485033 sv_algorithm_assistance_LP4_3733
7079 20:00:11.487908 ============ PULL DRAM RESETB DOWN ============
7080 20:00:11.491468 ========== PULL DRAM RESETB DOWN end =========
7081 20:00:11.494844 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7082 20:00:11.498715 ===================================
7083 20:00:11.501481 LPDDR4 DRAM CONFIGURATION
7084 20:00:11.505449 ===================================
7085 20:00:11.507983 EX_ROW_EN[0] = 0x0
7086 20:00:11.508392 EX_ROW_EN[1] = 0x0
7087 20:00:11.511501 LP4Y_EN = 0x0
7088 20:00:11.511915 WORK_FSP = 0x1
7089 20:00:11.514507 WL = 0x5
7090 20:00:11.514912 RL = 0x5
7091 20:00:11.517891 BL = 0x2
7092 20:00:11.518302 RPST = 0x0
7093 20:00:11.521440 RD_PRE = 0x0
7094 20:00:11.524667 WR_PRE = 0x1
7095 20:00:11.525079 WR_PST = 0x1
7096 20:00:11.528123 DBI_WR = 0x0
7097 20:00:11.528534 DBI_RD = 0x0
7098 20:00:11.531803 OTF = 0x1
7099 20:00:11.534517 ===================================
7100 20:00:11.538226 ===================================
7101 20:00:11.538635 ANA top config
7102 20:00:11.541887 ===================================
7103 20:00:11.544592 DLL_ASYNC_EN = 0
7104 20:00:11.548291 ALL_SLAVE_EN = 0
7105 20:00:11.548802 NEW_RANK_MODE = 1
7106 20:00:11.551357 DLL_IDLE_MODE = 1
7107 20:00:11.554432 LP45_APHY_COMB_EN = 1
7108 20:00:11.558283 TX_ODT_DIS = 0
7109 20:00:11.558798 NEW_8X_MODE = 1
7110 20:00:11.561575 ===================================
7111 20:00:11.564985 ===================================
7112 20:00:11.567637 data_rate = 3200
7113 20:00:11.571436 CKR = 1
7114 20:00:11.574530 DQ_P2S_RATIO = 8
7115 20:00:11.577932 ===================================
7116 20:00:11.581301 CA_P2S_RATIO = 8
7117 20:00:11.584448 DQ_CA_OPEN = 0
7118 20:00:11.584861 DQ_SEMI_OPEN = 0
7119 20:00:11.587640 CA_SEMI_OPEN = 0
7120 20:00:11.591226 CA_FULL_RATE = 0
7121 20:00:11.594792 DQ_CKDIV4_EN = 0
7122 20:00:11.597918 CA_CKDIV4_EN = 0
7123 20:00:11.600745 CA_PREDIV_EN = 0
7124 20:00:11.601163 PH8_DLY = 12
7125 20:00:11.604134 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7126 20:00:11.607361 DQ_AAMCK_DIV = 4
7127 20:00:11.610867 CA_AAMCK_DIV = 4
7128 20:00:11.614064 CA_ADMCK_DIV = 4
7129 20:00:11.617194 DQ_TRACK_CA_EN = 0
7130 20:00:11.621141 CA_PICK = 1600
7131 20:00:11.621705 CA_MCKIO = 1600
7132 20:00:11.623900 MCKIO_SEMI = 0
7133 20:00:11.627502 PLL_FREQ = 3068
7134 20:00:11.630677 DQ_UI_PI_RATIO = 32
7135 20:00:11.633775 CA_UI_PI_RATIO = 0
7136 20:00:11.637171 ===================================
7137 20:00:11.640976 ===================================
7138 20:00:11.644183 memory_type:LPDDR4
7139 20:00:11.644595 GP_NUM : 10
7140 20:00:11.647296 SRAM_EN : 1
7141 20:00:11.647863 MD32_EN : 0
7142 20:00:11.651112 ===================================
7143 20:00:11.653899 [ANA_INIT] >>>>>>>>>>>>>>
7144 20:00:11.657512 <<<<<< [CONFIGURE PHASE]: ANA_TX
7145 20:00:11.660118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7146 20:00:11.663761 ===================================
7147 20:00:11.667269 data_rate = 3200,PCW = 0X7600
7148 20:00:11.670785 ===================================
7149 20:00:11.674103 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7150 20:00:11.680504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7151 20:00:11.683795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7152 20:00:11.690614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7153 20:00:11.693822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7154 20:00:11.696676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7155 20:00:11.697093 [ANA_INIT] flow start
7156 20:00:11.700277 [ANA_INIT] PLL >>>>>>>>
7157 20:00:11.703352 [ANA_INIT] PLL <<<<<<<<
7158 20:00:11.703911 [ANA_INIT] MIDPI >>>>>>>>
7159 20:00:11.706941 [ANA_INIT] MIDPI <<<<<<<<
7160 20:00:11.710574 [ANA_INIT] DLL >>>>>>>>
7161 20:00:11.711081 [ANA_INIT] DLL <<<<<<<<
7162 20:00:11.713341 [ANA_INIT] flow end
7163 20:00:11.716779 ============ LP4 DIFF to SE enter ============
7164 20:00:11.724014 ============ LP4 DIFF to SE exit ============
7165 20:00:11.724525 [ANA_INIT] <<<<<<<<<<<<<
7166 20:00:11.726625 [Flow] Enable top DCM control >>>>>
7167 20:00:11.730016 [Flow] Enable top DCM control <<<<<
7168 20:00:11.733648 Enable DLL master slave shuffle
7169 20:00:11.740099 ==============================================================
7170 20:00:11.740509 Gating Mode config
7171 20:00:11.746988 ==============================================================
7172 20:00:11.750027 Config description:
7173 20:00:11.756959 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7174 20:00:11.763995 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7175 20:00:11.770133 SELPH_MODE 0: By rank 1: By Phase
7176 20:00:11.776745 ==============================================================
7177 20:00:11.777330 GAT_TRACK_EN = 1
7178 20:00:11.780120 RX_GATING_MODE = 2
7179 20:00:11.783304 RX_GATING_TRACK_MODE = 2
7180 20:00:11.786565 SELPH_MODE = 1
7181 20:00:11.789512 PICG_EARLY_EN = 1
7182 20:00:11.792726 VALID_LAT_VALUE = 1
7183 20:00:11.799536 ==============================================================
7184 20:00:11.803143 Enter into Gating configuration >>>>
7185 20:00:11.806105 Exit from Gating configuration <<<<
7186 20:00:11.809447 Enter into DVFS_PRE_config >>>>>
7187 20:00:11.819371 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7188 20:00:11.822995 Exit from DVFS_PRE_config <<<<<
7189 20:00:11.826159 Enter into PICG configuration >>>>
7190 20:00:11.829658 Exit from PICG configuration <<<<
7191 20:00:11.833068 [RX_INPUT] configuration >>>>>
7192 20:00:11.835922 [RX_INPUT] configuration <<<<<
7193 20:00:11.839490 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7194 20:00:11.846058 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7195 20:00:11.853084 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 20:00:11.855712 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 20:00:11.862881 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7198 20:00:11.869574 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7199 20:00:11.872886 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7200 20:00:11.878864 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7201 20:00:11.882354 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7202 20:00:11.885621 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7203 20:00:11.889488 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7204 20:00:11.895441 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7205 20:00:11.899086 ===================================
7206 20:00:11.899648 LPDDR4 DRAM CONFIGURATION
7207 20:00:11.902722 ===================================
7208 20:00:11.905878 EX_ROW_EN[0] = 0x0
7209 20:00:11.909273 EX_ROW_EN[1] = 0x0
7210 20:00:11.909682 LP4Y_EN = 0x0
7211 20:00:11.912806 WORK_FSP = 0x1
7212 20:00:11.913325 WL = 0x5
7213 20:00:11.915768 RL = 0x5
7214 20:00:11.916178 BL = 0x2
7215 20:00:11.918772 RPST = 0x0
7216 20:00:11.919185 RD_PRE = 0x0
7217 20:00:11.922471 WR_PRE = 0x1
7218 20:00:11.922880 WR_PST = 0x1
7219 20:00:11.925249 DBI_WR = 0x0
7220 20:00:11.925657 DBI_RD = 0x0
7221 20:00:11.928797 OTF = 0x1
7222 20:00:11.931848 ===================================
7223 20:00:11.935694 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7224 20:00:11.939173 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7225 20:00:11.945822 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 20:00:11.949193 ===================================
7227 20:00:11.949710 LPDDR4 DRAM CONFIGURATION
7228 20:00:11.951913 ===================================
7229 20:00:11.955306 EX_ROW_EN[0] = 0x10
7230 20:00:11.958409 EX_ROW_EN[1] = 0x0
7231 20:00:11.958823 LP4Y_EN = 0x0
7232 20:00:11.962001 WORK_FSP = 0x1
7233 20:00:11.962520 WL = 0x5
7234 20:00:11.965349 RL = 0x5
7235 20:00:11.965870 BL = 0x2
7236 20:00:11.968313 RPST = 0x0
7237 20:00:11.968724 RD_PRE = 0x0
7238 20:00:11.971865 WR_PRE = 0x1
7239 20:00:11.972273 WR_PST = 0x1
7240 20:00:11.975505 DBI_WR = 0x0
7241 20:00:11.976018 DBI_RD = 0x0
7242 20:00:11.978503 OTF = 0x1
7243 20:00:11.981897 ===================================
7244 20:00:11.988102 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7245 20:00:11.988523 ==
7246 20:00:11.991767 Dram Type= 6, Freq= 0, CH_0, rank 0
7247 20:00:11.995340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7248 20:00:11.995896 ==
7249 20:00:11.998587 [Duty_Offset_Calibration]
7250 20:00:11.999104 B0:2 B1:0 CA:3
7251 20:00:11.999481
7252 20:00:12.001599 [DutyScan_Calibration_Flow] k_type=0
7253 20:00:12.012233
7254 20:00:12.012746 ==CLK 0==
7255 20:00:12.015565 Final CLK duty delay cell = 0
7256 20:00:12.019111 [0] MAX Duty = 5031%(X100), DQS PI = 12
7257 20:00:12.022496 [0] MIN Duty = 4907%(X100), DQS PI = 6
7258 20:00:12.023007 [0] AVG Duty = 4969%(X100)
7259 20:00:12.023341
7260 20:00:12.025815 CH0 CLK Duty spec in!! Max-Min= 124%
7261 20:00:12.032080 [DutyScan_Calibration_Flow] ====Done====
7262 20:00:12.032504
7263 20:00:12.035511 [DutyScan_Calibration_Flow] k_type=1
7264 20:00:12.052206
7265 20:00:12.052719 ==DQS 0 ==
7266 20:00:12.055438 Final DQS duty delay cell = 0
7267 20:00:12.058895 [0] MAX Duty = 5094%(X100), DQS PI = 14
7268 20:00:12.062176 [0] MIN Duty = 4875%(X100), DQS PI = 50
7269 20:00:12.065336 [0] AVG Duty = 4984%(X100)
7270 20:00:12.065847
7271 20:00:12.066184 ==DQS 1 ==
7272 20:00:12.068492 Final DQS duty delay cell = 0
7273 20:00:12.071774 [0] MAX Duty = 5156%(X100), DQS PI = 32
7274 20:00:12.074915 [0] MIN Duty = 5031%(X100), DQS PI = 14
7275 20:00:12.078892 [0] AVG Duty = 5093%(X100)
7276 20:00:12.079444
7277 20:00:12.082430 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7278 20:00:12.082942
7279 20:00:12.084867 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7280 20:00:12.088341 [DutyScan_Calibration_Flow] ====Done====
7281 20:00:12.088755
7282 20:00:12.092151 [DutyScan_Calibration_Flow] k_type=3
7283 20:00:12.109753
7284 20:00:12.110256 ==DQM 0 ==
7285 20:00:12.112665 Final DQM duty delay cell = 0
7286 20:00:12.115679 [0] MAX Duty = 5156%(X100), DQS PI = 28
7287 20:00:12.118998 [0] MIN Duty = 4875%(X100), DQS PI = 46
7288 20:00:12.122742 [0] AVG Duty = 5015%(X100)
7289 20:00:12.123253
7290 20:00:12.123630 ==DQM 1 ==
7291 20:00:12.126355 Final DQM duty delay cell = 0
7292 20:00:12.128927 [0] MAX Duty = 4938%(X100), DQS PI = 0
7293 20:00:12.132526 [0] MIN Duty = 4813%(X100), DQS PI = 14
7294 20:00:12.135965 [0] AVG Duty = 4875%(X100)
7295 20:00:12.136376
7296 20:00:12.139121 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7297 20:00:12.139565
7298 20:00:12.142065 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7299 20:00:12.145460 [DutyScan_Calibration_Flow] ====Done====
7300 20:00:12.145869
7301 20:00:12.149067 [DutyScan_Calibration_Flow] k_type=2
7302 20:00:12.165808
7303 20:00:12.166318 ==DQ 0 ==
7304 20:00:12.169437 Final DQ duty delay cell = -4
7305 20:00:12.172249 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7306 20:00:12.175480 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7307 20:00:12.178993 [-4] AVG Duty = 4938%(X100)
7308 20:00:12.179550
7309 20:00:12.179891 ==DQ 1 ==
7310 20:00:12.182454 Final DQ duty delay cell = 0
7311 20:00:12.185597 [0] MAX Duty = 5156%(X100), DQS PI = 58
7312 20:00:12.189489 [0] MIN Duty = 5000%(X100), DQS PI = 18
7313 20:00:12.189998 [0] AVG Duty = 5078%(X100)
7314 20:00:12.192219
7315 20:00:12.195628 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7316 20:00:12.196040
7317 20:00:12.198924 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7318 20:00:12.202971 [DutyScan_Calibration_Flow] ====Done====
7319 20:00:12.203525 ==
7320 20:00:12.205849 Dram Type= 6, Freq= 0, CH_1, rank 0
7321 20:00:12.209177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7322 20:00:12.209683 ==
7323 20:00:12.212208 [Duty_Offset_Calibration]
7324 20:00:12.212708 B0:1 B1:-2 CA:0
7325 20:00:12.213101
7326 20:00:12.215239 [DutyScan_Calibration_Flow] k_type=0
7327 20:00:12.226428
7328 20:00:12.226933 ==CLK 0==
7329 20:00:12.229859 Final CLK duty delay cell = 0
7330 20:00:12.233223 [0] MAX Duty = 5093%(X100), DQS PI = 30
7331 20:00:12.235881 [0] MIN Duty = 4844%(X100), DQS PI = 58
7332 20:00:12.239692 [0] AVG Duty = 4968%(X100)
7333 20:00:12.240104
7334 20:00:12.243216 CH1 CLK Duty spec in!! Max-Min= 249%
7335 20:00:12.246148 [DutyScan_Calibration_Flow] ====Done====
7336 20:00:12.246662
7337 20:00:12.249348 [DutyScan_Calibration_Flow] k_type=1
7338 20:00:12.265518
7339 20:00:12.266021 ==DQS 0 ==
7340 20:00:12.268528 Final DQS duty delay cell = -4
7341 20:00:12.272022 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7342 20:00:12.275139 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7343 20:00:12.278871 [-4] AVG Duty = 4922%(X100)
7344 20:00:12.279378
7345 20:00:12.279766 ==DQS 1 ==
7346 20:00:12.282201 Final DQS duty delay cell = 0
7347 20:00:12.285490 [0] MAX Duty = 5093%(X100), DQS PI = 60
7348 20:00:12.288190 [0] MIN Duty = 4844%(X100), DQS PI = 24
7349 20:00:12.292039 [0] AVG Duty = 4968%(X100)
7350 20:00:12.292563
7351 20:00:12.295116 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7352 20:00:12.295681
7353 20:00:12.298612 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7354 20:00:12.302049 [DutyScan_Calibration_Flow] ====Done====
7355 20:00:12.302556
7356 20:00:12.304890 [DutyScan_Calibration_Flow] k_type=3
7357 20:00:12.323229
7358 20:00:12.323778 ==DQM 0 ==
7359 20:00:12.326146 Final DQM duty delay cell = 0
7360 20:00:12.329589 [0] MAX Duty = 5031%(X100), DQS PI = 24
7361 20:00:12.332511 [0] MIN Duty = 4813%(X100), DQS PI = 56
7362 20:00:12.336045 [0] AVG Duty = 4922%(X100)
7363 20:00:12.336575
7364 20:00:12.336907 ==DQM 1 ==
7365 20:00:12.339222 Final DQM duty delay cell = 0
7366 20:00:12.342709 [0] MAX Duty = 5062%(X100), DQS PI = 34
7367 20:00:12.345619 [0] MIN Duty = 4875%(X100), DQS PI = 24
7368 20:00:12.348905 [0] AVG Duty = 4968%(X100)
7369 20:00:12.349408
7370 20:00:12.352522 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7371 20:00:12.353025
7372 20:00:12.355335 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7373 20:00:12.359263 [DutyScan_Calibration_Flow] ====Done====
7374 20:00:12.359921
7375 20:00:12.363007 [DutyScan_Calibration_Flow] k_type=2
7376 20:00:12.379294
7377 20:00:12.379740 ==DQ 0 ==
7378 20:00:12.382939 Final DQ duty delay cell = 0
7379 20:00:12.386480 [0] MAX Duty = 5093%(X100), DQS PI = 22
7380 20:00:12.389084 [0] MIN Duty = 4907%(X100), DQS PI = 60
7381 20:00:12.389626 [0] AVG Duty = 5000%(X100)
7382 20:00:12.392789
7383 20:00:12.393197 ==DQ 1 ==
7384 20:00:12.396114 Final DQ duty delay cell = 0
7385 20:00:12.399360 [0] MAX Duty = 5156%(X100), DQS PI = 36
7386 20:00:12.402412 [0] MIN Duty = 4938%(X100), DQS PI = 24
7387 20:00:12.402824 [0] AVG Duty = 5047%(X100)
7388 20:00:12.403293
7389 20:00:12.409150 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7390 20:00:12.409692
7391 20:00:12.412803 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7392 20:00:12.416057 [DutyScan_Calibration_Flow] ====Done====
7393 20:00:12.419142 nWR fixed to 30
7394 20:00:12.419600 [ModeRegInit_LP4] CH0 RK0
7395 20:00:12.422812 [ModeRegInit_LP4] CH0 RK1
7396 20:00:12.426447 [ModeRegInit_LP4] CH1 RK0
7397 20:00:12.429353 [ModeRegInit_LP4] CH1 RK1
7398 20:00:12.429861 match AC timing 5
7399 20:00:12.432640 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7400 20:00:12.439223 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7401 20:00:12.442767 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7402 20:00:12.449812 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7403 20:00:12.453242 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7404 20:00:12.453655 [MiockJmeterHQA]
7405 20:00:12.453979
7406 20:00:12.455885 [DramcMiockJmeter] u1RxGatingPI = 0
7407 20:00:12.459325 0 : 4253, 4027
7408 20:00:12.459884 4 : 4252, 4027
7409 20:00:12.460217 8 : 4363, 4138
7410 20:00:12.462188 12 : 4253, 4026
7411 20:00:12.462604 16 : 4360, 4138
7412 20:00:12.465631 20 : 4252, 4027
7413 20:00:12.466140 24 : 4252, 4027
7414 20:00:12.469289 28 : 4253, 4027
7415 20:00:12.469706 32 : 4250, 4027
7416 20:00:12.472537 36 : 4250, 4027
7417 20:00:12.472954 40 : 4361, 4137
7418 20:00:12.473287 44 : 4360, 4138
7419 20:00:12.475839 48 : 4250, 4026
7420 20:00:12.476256 52 : 4252, 4027
7421 20:00:12.479231 56 : 4253, 4027
7422 20:00:12.479816 60 : 4250, 4026
7423 20:00:12.482776 64 : 4252, 4030
7424 20:00:12.483243 68 : 4360, 4137
7425 20:00:12.487781 72 : 4250, 4027
7426 20:00:12.488366 76 : 4250, 4027
7427 20:00:12.488708 80 : 4250, 4026
7428 20:00:12.489404 84 : 4252, 4030
7429 20:00:12.489737 88 : 4250, 4027
7430 20:00:12.492160 92 : 4361, 4137
7431 20:00:12.492576 96 : 4360, 4138
7432 20:00:12.495623 100 : 4250, 4026
7433 20:00:12.496169 104 : 4361, 3689
7434 20:00:12.499299 108 : 4250, 7
7435 20:00:12.499851 112 : 4249, 0
7436 20:00:12.500187 116 : 4250, 0
7437 20:00:12.502882 120 : 4250, 0
7438 20:00:12.503437 124 : 4361, 0
7439 20:00:12.503788 128 : 4360, 0
7440 20:00:12.505519 132 : 4363, 0
7441 20:00:12.506031 136 : 4250, 0
7442 20:00:12.508681 140 : 4253, 0
7443 20:00:12.509113 144 : 4250, 0
7444 20:00:12.509462 148 : 4250, 0
7445 20:00:12.512110 152 : 4250, 0
7446 20:00:12.512626 156 : 4250, 0
7447 20:00:12.515222 160 : 4250, 0
7448 20:00:12.515757 164 : 4250, 0
7449 20:00:12.516099 168 : 4250, 0
7450 20:00:12.518501 172 : 4252, 0
7451 20:00:12.518917 176 : 4361, 0
7452 20:00:12.522127 180 : 4360, 0
7453 20:00:12.522650 184 : 4250, 0
7454 20:00:12.522987 188 : 4360, 0
7455 20:00:12.525014 192 : 4361, 0
7456 20:00:12.525368 196 : 4249, 0
7457 20:00:12.528761 200 : 4250, 0
7458 20:00:12.529274 204 : 4250, 0
7459 20:00:12.529611 208 : 4250, 0
7460 20:00:12.532330 212 : 4252, 0
7461 20:00:12.532848 216 : 4250, 0
7462 20:00:12.533182 220 : 4250, 0
7463 20:00:12.535068 224 : 4253, 0
7464 20:00:12.535517 228 : 4250, 0
7465 20:00:12.538639 232 : 4360, 0
7466 20:00:12.539149 236 : 4360, 1445
7467 20:00:12.541997 240 : 4253, 4029
7468 20:00:12.542523 244 : 4250, 4027
7469 20:00:12.545400 248 : 4250, 4027
7470 20:00:12.545920 252 : 4250, 4027
7471 20:00:12.546258 256 : 4249, 4027
7472 20:00:12.548464 260 : 4250, 4026
7473 20:00:12.548972 264 : 4361, 4137
7474 20:00:12.552097 268 : 4250, 4027
7475 20:00:12.552606 272 : 4249, 4027
7476 20:00:12.555426 276 : 4360, 4137
7477 20:00:12.555946 280 : 4250, 4026
7478 20:00:12.558178 284 : 4250, 4027
7479 20:00:12.558693 288 : 4363, 4140
7480 20:00:12.561410 292 : 4249, 4027
7481 20:00:12.561831 296 : 4250, 4026
7482 20:00:12.565126 300 : 4250, 4027
7483 20:00:12.565642 304 : 4252, 4030
7484 20:00:12.568215 308 : 4249, 4027
7485 20:00:12.568732 312 : 4250, 4026
7486 20:00:12.571785 316 : 4361, 4138
7487 20:00:12.572298 320 : 4250, 4027
7488 20:00:12.572635 324 : 4249, 4027
7489 20:00:12.575452 328 : 4360, 4137
7490 20:00:12.575972 332 : 4250, 4026
7491 20:00:12.577983 336 : 4250, 4027
7492 20:00:12.578401 340 : 4363, 4140
7493 20:00:12.581833 344 : 4251, 4027
7494 20:00:12.582344 348 : 4250, 4026
7495 20:00:12.585066 352 : 4250, 4002
7496 20:00:12.585578 356 : 4252, 2938
7497 20:00:12.587868 360 : 4249, 0
7498 20:00:12.588287
7499 20:00:12.588614 MIOCK jitter meter ch=0
7500 20:00:12.588917
7501 20:00:12.591465 1T = (360-108) = 252 dly cells
7502 20:00:12.597925 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7503 20:00:12.598338 ==
7504 20:00:12.601694 Dram Type= 6, Freq= 0, CH_0, rank 0
7505 20:00:12.604430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 20:00:12.604847 ==
7507 20:00:12.611478 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 20:00:12.614987 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 20:00:12.617979 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 20:00:12.625022 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 20:00:12.634331 [CA 0] Center 43 (13~74) winsize 62
7512 20:00:12.637558 [CA 1] Center 43 (13~74) winsize 62
7513 20:00:12.641075 [CA 2] Center 39 (10~68) winsize 59
7514 20:00:12.644079 [CA 3] Center 39 (10~68) winsize 59
7515 20:00:12.647673 [CA 4] Center 36 (7~66) winsize 60
7516 20:00:12.651138 [CA 5] Center 36 (7~66) winsize 60
7517 20:00:12.651753
7518 20:00:12.654485 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7519 20:00:12.654903
7520 20:00:12.657719 [CATrainingPosCal] consider 1 rank data
7521 20:00:12.660812 u2DelayCellTimex100 = 258/100 ps
7522 20:00:12.664094 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7523 20:00:12.671345 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7524 20:00:12.673892 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7525 20:00:12.677492 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7526 20:00:12.681352 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7527 20:00:12.684060 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7528 20:00:12.684482
7529 20:00:12.687938 CA PerBit enable=1, Macro0, CA PI delay=36
7530 20:00:12.688569
7531 20:00:12.691164 [CBTSetCACLKResult] CA Dly = 36
7532 20:00:12.694270 CS Dly: 11 (0~42)
7533 20:00:12.697487 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 20:00:12.700804 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 20:00:12.701329 ==
7536 20:00:12.704291 Dram Type= 6, Freq= 0, CH_0, rank 1
7537 20:00:12.710700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 20:00:12.711225 ==
7539 20:00:12.713947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 20:00:12.720429 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 20:00:12.724179 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 20:00:12.730653 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 20:00:12.738322 [CA 0] Center 44 (14~75) winsize 62
7544 20:00:12.741493 [CA 1] Center 43 (13~74) winsize 62
7545 20:00:12.745354 [CA 2] Center 39 (10~69) winsize 60
7546 20:00:12.748547 [CA 3] Center 39 (10~69) winsize 60
7547 20:00:12.751850 [CA 4] Center 37 (8~67) winsize 60
7548 20:00:12.755006 [CA 5] Center 37 (7~67) winsize 61
7549 20:00:12.755559
7550 20:00:12.758632 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 20:00:12.759149
7552 20:00:12.761442 [CATrainingPosCal] consider 2 rank data
7553 20:00:12.765122 u2DelayCellTimex100 = 258/100 ps
7554 20:00:12.771688 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7555 20:00:12.774611 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7556 20:00:12.777972 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7557 20:00:12.781544 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7558 20:00:12.784849 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7559 20:00:12.788305 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7560 20:00:12.788895
7561 20:00:12.791849 CA PerBit enable=1, Macro0, CA PI delay=36
7562 20:00:12.792364
7563 20:00:12.794986 [CBTSetCACLKResult] CA Dly = 36
7564 20:00:12.798201 CS Dly: 11 (0~43)
7565 20:00:12.801709 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 20:00:12.804581 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 20:00:12.805007
7568 20:00:12.807984 ----->DramcWriteLeveling(PI) begin...
7569 20:00:12.808503 ==
7570 20:00:12.811430 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 20:00:12.817997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 20:00:12.818525 ==
7573 20:00:12.820978 Write leveling (Byte 0): 35 => 35
7574 20:00:12.824840 Write leveling (Byte 1): 29 => 29
7575 20:00:12.825357 DramcWriteLeveling(PI) end<-----
7576 20:00:12.828202
7577 20:00:12.828712 ==
7578 20:00:12.831695 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 20:00:12.834623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 20:00:12.835137 ==
7581 20:00:12.837702 [Gating] SW mode calibration
7582 20:00:12.844910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7583 20:00:12.847878 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7584 20:00:12.854631 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 20:00:12.857576 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 20:00:12.861159 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 20:00:12.867773 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 20:00:12.871195 1 4 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7589 20:00:12.874599 1 4 20 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
7590 20:00:12.880779 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7591 20:00:12.884151 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 20:00:12.887806 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 20:00:12.894243 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 20:00:12.897761 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 20:00:12.900841 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7596 20:00:12.907446 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
7597 20:00:12.910588 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7598 20:00:12.914029 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
7599 20:00:12.920814 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 20:00:12.923638 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 20:00:12.927270 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 20:00:12.934158 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 20:00:12.937328 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 20:00:12.940407 1 6 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7605 20:00:12.947156 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (1 1) (0 0)
7606 20:00:12.950024 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7607 20:00:12.953632 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 20:00:12.960375 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 20:00:12.963915 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 20:00:12.967028 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 20:00:12.973027 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 20:00:12.976890 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7613 20:00:12.980005 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 20:00:12.986939 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 20:00:12.989694 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 20:00:12.993522 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 20:00:13.000253 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 20:00:13.003199 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 20:00:13.006656 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 20:00:13.013284 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 20:00:13.016614 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 20:00:13.019545 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 20:00:13.026840 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 20:00:13.029804 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 20:00:13.032761 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 20:00:13.040044 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 20:00:13.042893 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 20:00:13.046547 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7629 20:00:13.053387 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7630 20:00:13.055971 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7631 20:00:13.059408 Total UI for P1: 0, mck2ui 16
7632 20:00:13.063029 best dqsien dly found for B0: ( 1, 9, 18)
7633 20:00:13.066436 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 20:00:13.069632 Total UI for P1: 0, mck2ui 16
7635 20:00:13.072694 best dqsien dly found for B1: ( 1, 9, 24)
7636 20:00:13.076041 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7637 20:00:13.079193 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7638 20:00:13.079648
7639 20:00:13.082782 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7640 20:00:13.089120 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7641 20:00:13.089791 [Gating] SW calibration Done
7642 20:00:13.092627 ==
7643 20:00:13.093047 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 20:00:13.099344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 20:00:13.099944 ==
7646 20:00:13.100322 RX Vref Scan: 0
7647 20:00:13.100641
7648 20:00:13.102150 RX Vref 0 -> 0, step: 1
7649 20:00:13.102569
7650 20:00:13.105731 RX Delay 0 -> 252, step: 8
7651 20:00:13.108998 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7652 20:00:13.112409 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7653 20:00:13.115836 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7654 20:00:13.122380 iDelay=192, Bit 3, Center 123 (64 ~ 183) 120
7655 20:00:13.125873 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7656 20:00:13.128948 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7657 20:00:13.132537 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7658 20:00:13.135717 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7659 20:00:13.142199 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7660 20:00:13.146002 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7661 20:00:13.148789 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7662 20:00:13.152340 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7663 20:00:13.155442 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7664 20:00:13.162444 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7665 20:00:13.165191 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7666 20:00:13.168730 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7667 20:00:13.169268 ==
7668 20:00:13.171874 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 20:00:13.175224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 20:00:13.178669 ==
7671 20:00:13.179092 DQS Delay:
7672 20:00:13.179470 DQS0 = 0, DQS1 = 0
7673 20:00:13.181647 DQM Delay:
7674 20:00:13.182061 DQM0 = 127, DQM1 = 123
7675 20:00:13.185179 DQ Delay:
7676 20:00:13.188635 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7677 20:00:13.191942 DQ4 =127, DQ5 =115, DQ6 =135, DQ7 =135
7678 20:00:13.195737 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7679 20:00:13.198768 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7680 20:00:13.199281
7681 20:00:13.199680
7682 20:00:13.199998 ==
7683 20:00:13.202075 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 20:00:13.205155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 20:00:13.205673 ==
7686 20:00:13.208407
7687 20:00:13.208914
7688 20:00:13.209246 TX Vref Scan disable
7689 20:00:13.211714 == TX Byte 0 ==
7690 20:00:13.215155 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7691 20:00:13.218600 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7692 20:00:13.221649 == TX Byte 1 ==
7693 20:00:13.225079 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7694 20:00:13.228143 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7695 20:00:13.228745 ==
7696 20:00:13.231837 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 20:00:13.237962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 20:00:13.238493 ==
7699 20:00:13.251031
7700 20:00:13.254157 TX Vref early break, caculate TX vref
7701 20:00:13.257581 TX Vref=16, minBit 13, minWin=21, winSum=362
7702 20:00:13.260346 TX Vref=18, minBit 8, minWin=22, winSum=372
7703 20:00:13.264060 TX Vref=20, minBit 0, minWin=23, winSum=379
7704 20:00:13.267161 TX Vref=22, minBit 0, minWin=24, winSum=391
7705 20:00:13.270394 TX Vref=24, minBit 4, minWin=24, winSum=398
7706 20:00:13.277010 TX Vref=26, minBit 8, minWin=24, winSum=410
7707 20:00:13.280174 TX Vref=28, minBit 4, minWin=24, winSum=408
7708 20:00:13.283634 TX Vref=30, minBit 3, minWin=24, winSum=401
7709 20:00:13.287018 TX Vref=32, minBit 8, minWin=23, winSum=389
7710 20:00:13.290228 TX Vref=34, minBit 9, minWin=23, winSum=384
7711 20:00:13.296616 [TxChooseVref] Worse bit 8, Min win 24, Win sum 410, Final Vref 26
7712 20:00:13.297040
7713 20:00:13.300572 Final TX Range 0 Vref 26
7714 20:00:13.301088
7715 20:00:13.301423 ==
7716 20:00:13.303321 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 20:00:13.306982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 20:00:13.307546 ==
7719 20:00:13.307891
7720 20:00:13.308202
7721 20:00:13.310442 TX Vref Scan disable
7722 20:00:13.316513 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7723 20:00:13.317026 == TX Byte 0 ==
7724 20:00:13.320325 u2DelayCellOfst[0]=15 cells (4 PI)
7725 20:00:13.323598 u2DelayCellOfst[1]=18 cells (5 PI)
7726 20:00:13.326423 u2DelayCellOfst[2]=15 cells (4 PI)
7727 20:00:13.329876 u2DelayCellOfst[3]=15 cells (4 PI)
7728 20:00:13.333337 u2DelayCellOfst[4]=11 cells (3 PI)
7729 20:00:13.336822 u2DelayCellOfst[5]=0 cells (0 PI)
7730 20:00:13.339710 u2DelayCellOfst[6]=18 cells (5 PI)
7731 20:00:13.343520 u2DelayCellOfst[7]=18 cells (5 PI)
7732 20:00:13.346756 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7733 20:00:13.349899 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7734 20:00:13.353530 == TX Byte 1 ==
7735 20:00:13.356620 u2DelayCellOfst[8]=3 cells (1 PI)
7736 20:00:13.357136 u2DelayCellOfst[9]=0 cells (0 PI)
7737 20:00:13.360159 u2DelayCellOfst[10]=7 cells (2 PI)
7738 20:00:13.363028 u2DelayCellOfst[11]=7 cells (2 PI)
7739 20:00:13.366555 u2DelayCellOfst[12]=15 cells (4 PI)
7740 20:00:13.369847 u2DelayCellOfst[13]=11 cells (3 PI)
7741 20:00:13.373152 u2DelayCellOfst[14]=15 cells (4 PI)
7742 20:00:13.376290 u2DelayCellOfst[15]=11 cells (3 PI)
7743 20:00:13.379619 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7744 20:00:13.386839 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7745 20:00:13.387353 DramC Write-DBI on
7746 20:00:13.387740 ==
7747 20:00:13.389923 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 20:00:13.395999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 20:00:13.396512 ==
7750 20:00:13.396846
7751 20:00:13.397157
7752 20:00:13.397456 TX Vref Scan disable
7753 20:00:13.400108 == TX Byte 0 ==
7754 20:00:13.403539 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7755 20:00:13.406918 == TX Byte 1 ==
7756 20:00:13.410384 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7757 20:00:13.413706 DramC Write-DBI off
7758 20:00:13.414217
7759 20:00:13.414554 [DATLAT]
7760 20:00:13.415099 Freq=1600, CH0 RK0
7761 20:00:13.415591
7762 20:00:13.416375 DATLAT Default: 0xf
7763 20:00:13.416902 0, 0xFFFF, sum = 0
7764 20:00:13.419895 1, 0xFFFF, sum = 0
7765 20:00:13.423092 2, 0xFFFF, sum = 0
7766 20:00:13.423551 3, 0xFFFF, sum = 0
7767 20:00:13.426699 4, 0xFFFF, sum = 0
7768 20:00:13.427219 5, 0xFFFF, sum = 0
7769 20:00:13.429858 6, 0xFFFF, sum = 0
7770 20:00:13.430418 7, 0xFFFF, sum = 0
7771 20:00:13.433814 8, 0xFFFF, sum = 0
7772 20:00:13.434336 9, 0xFFFF, sum = 0
7773 20:00:13.436735 10, 0xFFFF, sum = 0
7774 20:00:13.437253 11, 0xFFFF, sum = 0
7775 20:00:13.440131 12, 0xFFFF, sum = 0
7776 20:00:13.440788 13, 0xEFFF, sum = 0
7777 20:00:13.442776 14, 0x0, sum = 1
7778 20:00:13.443201 15, 0x0, sum = 2
7779 20:00:13.446660 16, 0x0, sum = 3
7780 20:00:13.447176 17, 0x0, sum = 4
7781 20:00:13.450191 best_step = 15
7782 20:00:13.450699
7783 20:00:13.451033 ==
7784 20:00:13.453117 Dram Type= 6, Freq= 0, CH_0, rank 0
7785 20:00:13.456064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7786 20:00:13.456810 ==
7787 20:00:13.459782 RX Vref Scan: 1
7788 20:00:13.460469
7789 20:00:13.460825 Set Vref Range= 24 -> 127
7790 20:00:13.461144
7791 20:00:13.462830 RX Vref 24 -> 127, step: 1
7792 20:00:13.463464
7793 20:00:13.466225 RX Delay 11 -> 252, step: 4
7794 20:00:13.466648
7795 20:00:13.469264 Set Vref, RX VrefLevel [Byte0]: 24
7796 20:00:13.472932 [Byte1]: 24
7797 20:00:13.473354
7798 20:00:13.476631 Set Vref, RX VrefLevel [Byte0]: 25
7799 20:00:13.479826 [Byte1]: 25
7800 20:00:13.480263
7801 20:00:13.483132 Set Vref, RX VrefLevel [Byte0]: 26
7802 20:00:13.486594 [Byte1]: 26
7803 20:00:13.490403
7804 20:00:13.490949 Set Vref, RX VrefLevel [Byte0]: 27
7805 20:00:13.493882 [Byte1]: 27
7806 20:00:13.498132
7807 20:00:13.498592 Set Vref, RX VrefLevel [Byte0]: 28
7808 20:00:13.501685 [Byte1]: 28
7809 20:00:13.505963
7810 20:00:13.506483 Set Vref, RX VrefLevel [Byte0]: 29
7811 20:00:13.509157 [Byte1]: 29
7812 20:00:13.513879
7813 20:00:13.514395 Set Vref, RX VrefLevel [Byte0]: 30
7814 20:00:13.516654 [Byte1]: 30
7815 20:00:13.521151
7816 20:00:13.521561 Set Vref, RX VrefLevel [Byte0]: 31
7817 20:00:13.524155 [Byte1]: 31
7818 20:00:13.528779
7819 20:00:13.529296 Set Vref, RX VrefLevel [Byte0]: 32
7820 20:00:13.532007 [Byte1]: 32
7821 20:00:13.536804
7822 20:00:13.537321 Set Vref, RX VrefLevel [Byte0]: 33
7823 20:00:13.539473 [Byte1]: 33
7824 20:00:13.544360
7825 20:00:13.544889 Set Vref, RX VrefLevel [Byte0]: 34
7826 20:00:13.547862 [Byte1]: 34
7827 20:00:13.552065
7828 20:00:13.552581 Set Vref, RX VrefLevel [Byte0]: 35
7829 20:00:13.554759 [Byte1]: 35
7830 20:00:13.559452
7831 20:00:13.559977 Set Vref, RX VrefLevel [Byte0]: 36
7832 20:00:13.562576 [Byte1]: 36
7833 20:00:13.566910
7834 20:00:13.567487 Set Vref, RX VrefLevel [Byte0]: 37
7835 20:00:13.570168 [Byte1]: 37
7836 20:00:13.574698
7837 20:00:13.575218 Set Vref, RX VrefLevel [Byte0]: 38
7838 20:00:13.577380 [Byte1]: 38
7839 20:00:13.582225
7840 20:00:13.582788 Set Vref, RX VrefLevel [Byte0]: 39
7841 20:00:13.585387 [Byte1]: 39
7842 20:00:13.589877
7843 20:00:13.590407 Set Vref, RX VrefLevel [Byte0]: 40
7844 20:00:13.593245 [Byte1]: 40
7845 20:00:13.597310
7846 20:00:13.597726 Set Vref, RX VrefLevel [Byte0]: 41
7847 20:00:13.600860 [Byte1]: 41
7848 20:00:13.605097
7849 20:00:13.605617 Set Vref, RX VrefLevel [Byte0]: 42
7850 20:00:13.608560 [Byte1]: 42
7851 20:00:13.613241
7852 20:00:13.613758 Set Vref, RX VrefLevel [Byte0]: 43
7853 20:00:13.615583 [Byte1]: 43
7854 20:00:13.620042
7855 20:00:13.620557 Set Vref, RX VrefLevel [Byte0]: 44
7856 20:00:13.623023 [Byte1]: 44
7857 20:00:13.627959
7858 20:00:13.628477 Set Vref, RX VrefLevel [Byte0]: 45
7859 20:00:13.630702 [Byte1]: 45
7860 20:00:13.635678
7861 20:00:13.636201 Set Vref, RX VrefLevel [Byte0]: 46
7862 20:00:13.638402 [Byte1]: 46
7863 20:00:13.642897
7864 20:00:13.643448 Set Vref, RX VrefLevel [Byte0]: 47
7865 20:00:13.646340 [Byte1]: 47
7866 20:00:13.650705
7867 20:00:13.651222 Set Vref, RX VrefLevel [Byte0]: 48
7868 20:00:13.654168 [Byte1]: 48
7869 20:00:13.658000
7870 20:00:13.658515 Set Vref, RX VrefLevel [Byte0]: 49
7871 20:00:13.661885 [Byte1]: 49
7872 20:00:13.665922
7873 20:00:13.666440 Set Vref, RX VrefLevel [Byte0]: 50
7874 20:00:13.669497 [Byte1]: 50
7875 20:00:13.673677
7876 20:00:13.674197 Set Vref, RX VrefLevel [Byte0]: 51
7877 20:00:13.676483 [Byte1]: 51
7878 20:00:13.681321
7879 20:00:13.681839 Set Vref, RX VrefLevel [Byte0]: 52
7880 20:00:13.684752 [Byte1]: 52
7881 20:00:13.688800
7882 20:00:13.689333 Set Vref, RX VrefLevel [Byte0]: 53
7883 20:00:13.691672 [Byte1]: 53
7884 20:00:13.696475
7885 20:00:13.697082 Set Vref, RX VrefLevel [Byte0]: 54
7886 20:00:13.699503 [Byte1]: 54
7887 20:00:13.703780
7888 20:00:13.704305 Set Vref, RX VrefLevel [Byte0]: 55
7889 20:00:13.707758 [Byte1]: 55
7890 20:00:13.711276
7891 20:00:13.711832 Set Vref, RX VrefLevel [Byte0]: 56
7892 20:00:13.715090 [Byte1]: 56
7893 20:00:13.718586
7894 20:00:13.719000 Set Vref, RX VrefLevel [Byte0]: 57
7895 20:00:13.721995 [Byte1]: 57
7896 20:00:13.726425
7897 20:00:13.726932 Set Vref, RX VrefLevel [Byte0]: 58
7898 20:00:13.729976 [Byte1]: 58
7899 20:00:13.734355
7900 20:00:13.734864 Set Vref, RX VrefLevel [Byte0]: 59
7901 20:00:13.737926 [Byte1]: 59
7902 20:00:13.741580
7903 20:00:13.741998 Set Vref, RX VrefLevel [Byte0]: 60
7904 20:00:13.745327 [Byte1]: 60
7905 20:00:13.749391
7906 20:00:13.749807 Set Vref, RX VrefLevel [Byte0]: 61
7907 20:00:13.753102 [Byte1]: 61
7908 20:00:13.757347
7909 20:00:13.757860 Set Vref, RX VrefLevel [Byte0]: 62
7910 20:00:13.760629 [Byte1]: 62
7911 20:00:13.765032
7912 20:00:13.765544 Set Vref, RX VrefLevel [Byte0]: 63
7913 20:00:13.768283 [Byte1]: 63
7914 20:00:13.772333
7915 20:00:13.772844 Set Vref, RX VrefLevel [Byte0]: 64
7916 20:00:13.775563 [Byte1]: 64
7917 20:00:13.779494
7918 20:00:13.779926 Set Vref, RX VrefLevel [Byte0]: 65
7919 20:00:13.783284 [Byte1]: 65
7920 20:00:13.787665
7921 20:00:13.788173 Set Vref, RX VrefLevel [Byte0]: 66
7922 20:00:13.790922 [Byte1]: 66
7923 20:00:13.795542
7924 20:00:13.796080 Set Vref, RX VrefLevel [Byte0]: 67
7925 20:00:13.798616 [Byte1]: 67
7926 20:00:13.802984
7927 20:00:13.803538 Set Vref, RX VrefLevel [Byte0]: 68
7928 20:00:13.806294 [Byte1]: 68
7929 20:00:13.810390
7930 20:00:13.810899 Set Vref, RX VrefLevel [Byte0]: 69
7931 20:00:13.813905 [Byte1]: 69
7932 20:00:13.817664
7933 20:00:13.818079 Set Vref, RX VrefLevel [Byte0]: 70
7934 20:00:13.821544 [Byte1]: 70
7935 20:00:13.825798
7936 20:00:13.826326 Set Vref, RX VrefLevel [Byte0]: 71
7937 20:00:13.829025 [Byte1]: 71
7938 20:00:13.833262
7939 20:00:13.833777 Set Vref, RX VrefLevel [Byte0]: 72
7940 20:00:13.836931 [Byte1]: 72
7941 20:00:13.840502
7942 20:00:13.840916 Set Vref, RX VrefLevel [Byte0]: 73
7943 20:00:13.844201 [Byte1]: 73
7944 20:00:13.848509
7945 20:00:13.848923 Set Vref, RX VrefLevel [Byte0]: 74
7946 20:00:13.851514 [Byte1]: 74
7947 20:00:13.856520
7948 20:00:13.857036 Set Vref, RX VrefLevel [Byte0]: 75
7949 20:00:13.859749 [Byte1]: 75
7950 20:00:13.863529
7951 20:00:13.864035 Set Vref, RX VrefLevel [Byte0]: 76
7952 20:00:13.867146 [Byte1]: 76
7953 20:00:13.871661
7954 20:00:13.872168 Final RX Vref Byte 0 = 63 to rank0
7955 20:00:13.875228 Final RX Vref Byte 1 = 59 to rank0
7956 20:00:13.877956 Final RX Vref Byte 0 = 63 to rank1
7957 20:00:13.881383 Final RX Vref Byte 1 = 59 to rank1==
7958 20:00:13.884587 Dram Type= 6, Freq= 0, CH_0, rank 0
7959 20:00:13.890915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 20:00:13.891517 ==
7961 20:00:13.891862 DQS Delay:
7962 20:00:13.892176 DQS0 = 0, DQS1 = 0
7963 20:00:13.894792 DQM Delay:
7964 20:00:13.895299 DQM0 = 126, DQM1 = 119
7965 20:00:13.898029 DQ Delay:
7966 20:00:13.900754 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7967 20:00:13.904286 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7968 20:00:13.907535 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7969 20:00:13.910946 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7970 20:00:13.911363
7971 20:00:13.911740
7972 20:00:13.912048
7973 20:00:13.914550 [DramC_TX_OE_Calibration] TA2
7974 20:00:13.917572 Original DQ_B0 (3 6) =30, OEN = 27
7975 20:00:13.921263 Original DQ_B1 (3 6) =30, OEN = 27
7976 20:00:13.924615 24, 0x0, End_B0=24 End_B1=24
7977 20:00:13.925039 25, 0x0, End_B0=25 End_B1=25
7978 20:00:13.927322 26, 0x0, End_B0=26 End_B1=26
7979 20:00:13.931043 27, 0x0, End_B0=27 End_B1=27
7980 20:00:13.934363 28, 0x0, End_B0=28 End_B1=28
7981 20:00:13.937212 29, 0x0, End_B0=29 End_B1=29
7982 20:00:13.937730 30, 0x0, End_B0=30 End_B1=30
7983 20:00:13.940934 31, 0x4141, End_B0=30 End_B1=30
7984 20:00:13.944255 Byte0 end_step=30 best_step=27
7985 20:00:13.947344 Byte1 end_step=30 best_step=27
7986 20:00:13.950764 Byte0 TX OE(2T, 0.5T) = (3, 3)
7987 20:00:13.954204 Byte1 TX OE(2T, 0.5T) = (3, 3)
7988 20:00:13.954739
7989 20:00:13.955079
7990 20:00:13.961060 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7991 20:00:13.963939 CH0 RK0: MR19=303, MR18=1515
7992 20:00:13.971233 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
7993 20:00:13.971792
7994 20:00:13.974080 ----->DramcWriteLeveling(PI) begin...
7995 20:00:13.974599 ==
7996 20:00:13.976871 Dram Type= 6, Freq= 0, CH_0, rank 1
7997 20:00:13.980435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 20:00:13.980951 ==
7999 20:00:13.984078 Write leveling (Byte 0): 35 => 35
8000 20:00:13.987087 Write leveling (Byte 1): 28 => 28
8001 20:00:13.990101 DramcWriteLeveling(PI) end<-----
8002 20:00:13.990522
8003 20:00:13.990852 ==
8004 20:00:13.993970 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 20:00:13.997086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 20:00:13.997507 ==
8007 20:00:14.000009 [Gating] SW mode calibration
8008 20:00:14.007375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8009 20:00:14.013247 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8010 20:00:14.016675 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 20:00:14.023507 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 20:00:14.027341 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 20:00:14.030183 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
8014 20:00:14.036644 1 4 16 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8015 20:00:14.039877 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8016 20:00:14.043502 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 20:00:14.050141 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 20:00:14.053235 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 20:00:14.056579 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 20:00:14.063627 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8021 20:00:14.066798 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8022 20:00:14.070255 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (0 1) (0 0)
8023 20:00:14.073596 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8024 20:00:14.080269 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 20:00:14.083076 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 20:00:14.086981 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 20:00:14.093556 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 20:00:14.096639 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8029 20:00:14.100011 1 6 12 | B1->B0 | 2323 4343 | 0 1 | (0 0) (0 0)
8030 20:00:14.106638 1 6 16 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
8031 20:00:14.110303 1 6 20 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
8032 20:00:14.113040 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 20:00:14.119962 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 20:00:14.122983 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 20:00:14.126768 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 20:00:14.133340 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8037 20:00:14.136548 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8038 20:00:14.139798 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 20:00:14.146377 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 20:00:14.149507 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 20:00:14.152835 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 20:00:14.159461 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 20:00:14.163245 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 20:00:14.166401 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 20:00:14.172724 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 20:00:14.176257 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 20:00:14.179459 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 20:00:14.186176 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 20:00:14.189872 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 20:00:14.192472 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 20:00:14.199709 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 20:00:14.203244 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8053 20:00:14.206178 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 20:00:14.213281 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8055 20:00:14.213826 Total UI for P1: 0, mck2ui 16
8056 20:00:14.215870 best dqsien dly found for B0: ( 1, 9, 10)
8057 20:00:14.222879 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 20:00:14.225875 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 20:00:14.229375 Total UI for P1: 0, mck2ui 16
8060 20:00:14.232782 best dqsien dly found for B1: ( 1, 9, 18)
8061 20:00:14.235611 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8062 20:00:14.239692 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8063 20:00:14.240297
8064 20:00:14.242075 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8065 20:00:14.248893 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8066 20:00:14.249428 [Gating] SW calibration Done
8067 20:00:14.252838 ==
8068 20:00:14.253355 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 20:00:14.259271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 20:00:14.259865 ==
8071 20:00:14.260328 RX Vref Scan: 0
8072 20:00:14.260746
8073 20:00:14.262454 RX Vref 0 -> 0, step: 1
8074 20:00:14.262991
8075 20:00:14.265775 RX Delay 0 -> 252, step: 8
8076 20:00:14.268898 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8077 20:00:14.272101 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8078 20:00:14.275459 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8079 20:00:14.282284 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8080 20:00:14.285572 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8081 20:00:14.288649 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8082 20:00:14.291973 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8083 20:00:14.295211 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8084 20:00:14.301879 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8085 20:00:14.305192 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8086 20:00:14.308747 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8087 20:00:14.311980 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8088 20:00:14.314970 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8089 20:00:14.322164 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8090 20:00:14.325035 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8091 20:00:14.328655 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8092 20:00:14.329169 ==
8093 20:00:14.331806 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 20:00:14.334809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 20:00:14.338166 ==
8096 20:00:14.338578 DQS Delay:
8097 20:00:14.338907 DQS0 = 0, DQS1 = 0
8098 20:00:14.341506 DQM Delay:
8099 20:00:14.341919 DQM0 = 128, DQM1 = 122
8100 20:00:14.345154 DQ Delay:
8101 20:00:14.348318 DQ0 =127, DQ1 =127, DQ2 =127, DQ3 =123
8102 20:00:14.351523 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8103 20:00:14.355081 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8104 20:00:14.358192 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8105 20:00:14.358719
8106 20:00:14.359051
8107 20:00:14.359371 ==
8108 20:00:14.361827 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 20:00:14.364601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 20:00:14.365116 ==
8111 20:00:14.367940
8112 20:00:14.368350
8113 20:00:14.368678 TX Vref Scan disable
8114 20:00:14.371281 == TX Byte 0 ==
8115 20:00:14.374962 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8116 20:00:14.378122 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8117 20:00:14.381396 == TX Byte 1 ==
8118 20:00:14.385170 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8119 20:00:14.387967 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8120 20:00:14.388383 ==
8121 20:00:14.391673 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 20:00:14.398354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 20:00:14.398887 ==
8124 20:00:14.411867
8125 20:00:14.415105 TX Vref early break, caculate TX vref
8126 20:00:14.418459 TX Vref=16, minBit 9, minWin=21, winSum=368
8127 20:00:14.421486 TX Vref=18, minBit 8, minWin=22, winSum=375
8128 20:00:14.424981 TX Vref=20, minBit 9, minWin=22, winSum=383
8129 20:00:14.428128 TX Vref=22, minBit 8, minWin=23, winSum=392
8130 20:00:14.431455 TX Vref=24, minBit 8, minWin=24, winSum=402
8131 20:00:14.437813 TX Vref=26, minBit 8, minWin=24, winSum=409
8132 20:00:14.441184 TX Vref=28, minBit 13, minWin=24, winSum=410
8133 20:00:14.444371 TX Vref=30, minBit 8, minWin=24, winSum=410
8134 20:00:14.447986 TX Vref=32, minBit 12, minWin=23, winSum=399
8135 20:00:14.450831 TX Vref=34, minBit 8, minWin=22, winSum=390
8136 20:00:14.455036 TX Vref=36, minBit 8, minWin=22, winSum=378
8137 20:00:14.461351 [TxChooseVref] Worse bit 13, Min win 24, Win sum 410, Final Vref 28
8138 20:00:14.461856
8139 20:00:14.464481 Final TX Range 0 Vref 28
8140 20:00:14.464902
8141 20:00:14.465233 ==
8142 20:00:14.467912 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 20:00:14.471075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 20:00:14.471571 ==
8145 20:00:14.472091
8146 20:00:14.474786
8147 20:00:14.475295 TX Vref Scan disable
8148 20:00:14.481279 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8149 20:00:14.481776 == TX Byte 0 ==
8150 20:00:14.485062 u2DelayCellOfst[0]=11 cells (3 PI)
8151 20:00:14.488017 u2DelayCellOfst[1]=15 cells (4 PI)
8152 20:00:14.491599 u2DelayCellOfst[2]=11 cells (3 PI)
8153 20:00:14.494266 u2DelayCellOfst[3]=11 cells (3 PI)
8154 20:00:14.497901 u2DelayCellOfst[4]=7 cells (2 PI)
8155 20:00:14.501600 u2DelayCellOfst[5]=0 cells (0 PI)
8156 20:00:14.505121 u2DelayCellOfst[6]=18 cells (5 PI)
8157 20:00:14.507900 u2DelayCellOfst[7]=18 cells (5 PI)
8158 20:00:14.511229 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8159 20:00:14.514765 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8160 20:00:14.517515 == TX Byte 1 ==
8161 20:00:14.521075 u2DelayCellOfst[8]=0 cells (0 PI)
8162 20:00:14.524183 u2DelayCellOfst[9]=3 cells (1 PI)
8163 20:00:14.527884 u2DelayCellOfst[10]=7 cells (2 PI)
8164 20:00:14.530992 u2DelayCellOfst[11]=7 cells (2 PI)
8165 20:00:14.531511 u2DelayCellOfst[12]=15 cells (4 PI)
8166 20:00:14.533897 u2DelayCellOfst[13]=11 cells (3 PI)
8167 20:00:14.537753 u2DelayCellOfst[14]=15 cells (4 PI)
8168 20:00:14.540706 u2DelayCellOfst[15]=15 cells (4 PI)
8169 20:00:14.547634 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8170 20:00:14.550992 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8171 20:00:14.551446 DramC Write-DBI on
8172 20:00:14.554269 ==
8173 20:00:14.557535 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 20:00:14.560309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 20:00:14.560743 ==
8176 20:00:14.561077
8177 20:00:14.561389
8178 20:00:14.563915 TX Vref Scan disable
8179 20:00:14.564330 == TX Byte 0 ==
8180 20:00:14.570748 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8181 20:00:14.571163 == TX Byte 1 ==
8182 20:00:14.574461 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8183 20:00:14.577224 DramC Write-DBI off
8184 20:00:14.577740
8185 20:00:14.578112 [DATLAT]
8186 20:00:14.580360 Freq=1600, CH0 RK1
8187 20:00:14.580808
8188 20:00:14.581138 DATLAT Default: 0xf
8189 20:00:14.583908 0, 0xFFFF, sum = 0
8190 20:00:14.584339 1, 0xFFFF, sum = 0
8191 20:00:14.586998 2, 0xFFFF, sum = 0
8192 20:00:14.587460 3, 0xFFFF, sum = 0
8193 20:00:14.591011 4, 0xFFFF, sum = 0
8194 20:00:14.591592 5, 0xFFFF, sum = 0
8195 20:00:14.593601 6, 0xFFFF, sum = 0
8196 20:00:14.594096 7, 0xFFFF, sum = 0
8197 20:00:14.597319 8, 0xFFFF, sum = 0
8198 20:00:14.600513 9, 0xFFFF, sum = 0
8199 20:00:14.600939 10, 0xFFFF, sum = 0
8200 20:00:14.603715 11, 0xFFFF, sum = 0
8201 20:00:14.604141 12, 0xFFFF, sum = 0
8202 20:00:14.607153 13, 0xCFFF, sum = 0
8203 20:00:14.607733 14, 0x0, sum = 1
8204 20:00:14.610614 15, 0x0, sum = 2
8205 20:00:14.611043 16, 0x0, sum = 3
8206 20:00:14.613568 17, 0x0, sum = 4
8207 20:00:14.613994 best_step = 15
8208 20:00:14.614329
8209 20:00:14.614643 ==
8210 20:00:14.616983 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 20:00:14.620116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 20:00:14.620542 ==
8213 20:00:14.623548 RX Vref Scan: 0
8214 20:00:14.624013
8215 20:00:14.626786 RX Vref 0 -> 0, step: 1
8216 20:00:14.627199
8217 20:00:14.627573 RX Delay 3 -> 252, step: 4
8218 20:00:14.634368 iDelay=191, Bit 0, Center 122 (67 ~ 178) 112
8219 20:00:14.637121 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8220 20:00:14.640450 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8221 20:00:14.644088 iDelay=191, Bit 3, Center 120 (63 ~ 178) 116
8222 20:00:14.647182 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8223 20:00:14.653702 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8224 20:00:14.657539 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8225 20:00:14.660875 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8226 20:00:14.664059 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8227 20:00:14.667189 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8228 20:00:14.673851 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8229 20:00:14.678003 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8230 20:00:14.680552 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8231 20:00:14.683585 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8232 20:00:14.690808 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8233 20:00:14.693718 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8234 20:00:14.694136 ==
8235 20:00:14.697144 Dram Type= 6, Freq= 0, CH_0, rank 1
8236 20:00:14.699943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 20:00:14.700389 ==
8238 20:00:14.703943 DQS Delay:
8239 20:00:14.704477 DQS0 = 0, DQS1 = 0
8240 20:00:14.704930 DQM Delay:
8241 20:00:14.706895 DQM0 = 124, DQM1 = 118
8242 20:00:14.707329 DQ Delay:
8243 20:00:14.710944 DQ0 =122, DQ1 =126, DQ2 =120, DQ3 =120
8244 20:00:14.713863 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8245 20:00:14.717478 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8246 20:00:14.723983 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8247 20:00:14.724524
8248 20:00:14.724973
8249 20:00:14.725388
8250 20:00:14.726530 [DramC_TX_OE_Calibration] TA2
8251 20:00:14.726950 Original DQ_B0 (3 6) =30, OEN = 27
8252 20:00:14.730421 Original DQ_B1 (3 6) =30, OEN = 27
8253 20:00:14.733380 24, 0x0, End_B0=24 End_B1=24
8254 20:00:14.736852 25, 0x0, End_B0=25 End_B1=25
8255 20:00:14.740382 26, 0x0, End_B0=26 End_B1=26
8256 20:00:14.743736 27, 0x0, End_B0=27 End_B1=27
8257 20:00:14.744181 28, 0x0, End_B0=28 End_B1=28
8258 20:00:14.746926 29, 0x0, End_B0=29 End_B1=29
8259 20:00:14.750325 30, 0x0, End_B0=30 End_B1=30
8260 20:00:14.753110 31, 0x4141, End_B0=30 End_B1=30
8261 20:00:14.756087 Byte0 end_step=30 best_step=27
8262 20:00:14.759792 Byte1 end_step=30 best_step=27
8263 20:00:14.760393 Byte0 TX OE(2T, 0.5T) = (3, 3)
8264 20:00:14.762936 Byte1 TX OE(2T, 0.5T) = (3, 3)
8265 20:00:14.763513
8266 20:00:14.763859
8267 20:00:14.773040 [DQSOSCAuto] RK1, (LSB)MR18= 0x230f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8268 20:00:14.776167 CH0 RK1: MR19=303, MR18=230F
8269 20:00:14.779499 CH0_RK1: MR19=0x303, MR18=0x230F, DQSOSC=392, MR23=63, INC=24, DEC=16
8270 20:00:14.783583 [RxdqsGatingPostProcess] freq 1600
8271 20:00:14.789946 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8272 20:00:14.792425 best DQS0 dly(2T, 0.5T) = (1, 1)
8273 20:00:14.796093 best DQS1 dly(2T, 0.5T) = (1, 1)
8274 20:00:14.799359 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8275 20:00:14.802863 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8276 20:00:14.806232 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 20:00:14.806779 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 20:00:14.809500 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 20:00:14.812403 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 20:00:14.816131 Pre-setting of DQS Precalculation
8281 20:00:14.822534 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8282 20:00:14.822952 ==
8283 20:00:14.825980 Dram Type= 6, Freq= 0, CH_1, rank 0
8284 20:00:14.828746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 20:00:14.829163 ==
8286 20:00:14.835884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8287 20:00:14.838775 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8288 20:00:14.841996 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8289 20:00:14.848790 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8290 20:00:14.858514 [CA 0] Center 42 (13~71) winsize 59
8291 20:00:14.861466 [CA 1] Center 42 (13~72) winsize 60
8292 20:00:14.864683 [CA 2] Center 37 (9~66) winsize 58
8293 20:00:14.868243 [CA 3] Center 37 (8~66) winsize 59
8294 20:00:14.871513 [CA 4] Center 37 (8~67) winsize 60
8295 20:00:14.874342 [CA 5] Center 36 (7~66) winsize 60
8296 20:00:14.874851
8297 20:00:14.877906 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8298 20:00:14.878412
8299 20:00:14.881165 [CATrainingPosCal] consider 1 rank data
8300 20:00:14.884310 u2DelayCellTimex100 = 258/100 ps
8301 20:00:14.891796 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8302 20:00:14.894516 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8303 20:00:14.898185 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8304 20:00:14.900937 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8305 20:00:14.905077 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8306 20:00:14.907963 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8307 20:00:14.908381
8308 20:00:14.911198 CA PerBit enable=1, Macro0, CA PI delay=36
8309 20:00:14.911663
8310 20:00:14.914544 [CBTSetCACLKResult] CA Dly = 36
8311 20:00:14.918149 CS Dly: 9 (0~40)
8312 20:00:14.921035 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8313 20:00:14.924351 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8314 20:00:14.924838 ==
8315 20:00:14.927880 Dram Type= 6, Freq= 0, CH_1, rank 1
8316 20:00:14.931274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 20:00:14.934062 ==
8318 20:00:14.937811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8319 20:00:14.941311 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8320 20:00:14.948309 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8321 20:00:14.954754 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8322 20:00:14.961586 [CA 0] Center 42 (13~71) winsize 59
8323 20:00:14.965256 [CA 1] Center 42 (12~72) winsize 61
8324 20:00:14.968365 [CA 2] Center 37 (8~67) winsize 60
8325 20:00:14.971814 [CA 3] Center 36 (7~66) winsize 60
8326 20:00:14.974742 [CA 4] Center 37 (7~67) winsize 61
8327 20:00:14.978261 [CA 5] Center 36 (6~66) winsize 61
8328 20:00:14.978777
8329 20:00:14.981060 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8330 20:00:14.981477
8331 20:00:14.985258 [CATrainingPosCal] consider 2 rank data
8332 20:00:14.988258 u2DelayCellTimex100 = 258/100 ps
8333 20:00:14.991430 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8334 20:00:14.998156 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8335 20:00:15.001342 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8336 20:00:15.004915 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8337 20:00:15.008104 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8338 20:00:15.011149 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8339 20:00:15.011728
8340 20:00:15.014579 CA PerBit enable=1, Macro0, CA PI delay=36
8341 20:00:15.015100
8342 20:00:15.018436 [CBTSetCACLKResult] CA Dly = 36
8343 20:00:15.020817 CS Dly: 11 (0~44)
8344 20:00:15.024730 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8345 20:00:15.027997 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8346 20:00:15.028418
8347 20:00:15.031144 ----->DramcWriteLeveling(PI) begin...
8348 20:00:15.031726 ==
8349 20:00:15.034126 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 20:00:15.040944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 20:00:15.041499 ==
8352 20:00:15.044389 Write leveling (Byte 0): 24 => 24
8353 20:00:15.044807 Write leveling (Byte 1): 28 => 28
8354 20:00:15.047737 DramcWriteLeveling(PI) end<-----
8355 20:00:15.048264
8356 20:00:15.050993 ==
8357 20:00:15.051448 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 20:00:15.057360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 20:00:15.057778 ==
8360 20:00:15.060953 [Gating] SW mode calibration
8361 20:00:15.068067 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8362 20:00:15.070583 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8363 20:00:15.077075 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 20:00:15.080489 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 20:00:15.083908 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 20:00:15.090861 1 4 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8367 20:00:15.094386 1 4 16 | B1->B0 | 3232 3131 | 1 1 | (1 1) (1 1)
8368 20:00:15.097114 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 20:00:15.103318 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 20:00:15.107515 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 20:00:15.110962 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 20:00:15.117367 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 20:00:15.120467 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 20:00:15.124264 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8375 20:00:15.130224 1 5 16 | B1->B0 | 2525 2929 | 0 0 | (0 0) (1 0)
8376 20:00:15.133989 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 20:00:15.136967 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 20:00:15.143679 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 20:00:15.147435 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 20:00:15.150304 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 20:00:15.153604 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 20:00:15.159978 1 6 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8383 20:00:15.163439 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 20:00:15.166930 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 20:00:15.173864 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 20:00:15.176992 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 20:00:15.180137 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 20:00:15.187192 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 20:00:15.190031 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 20:00:15.193499 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 20:00:15.200010 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8392 20:00:15.203481 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8393 20:00:15.206405 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 20:00:15.213534 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 20:00:15.216451 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 20:00:15.220287 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 20:00:15.226292 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 20:00:15.229972 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 20:00:15.233644 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 20:00:15.239546 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 20:00:15.243187 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 20:00:15.246572 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 20:00:15.252863 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 20:00:15.256328 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 20:00:15.259116 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 20:00:15.266202 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 20:00:15.269606 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8408 20:00:15.273075 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 20:00:15.276186 Total UI for P1: 0, mck2ui 16
8410 20:00:15.279527 best dqsien dly found for B0: ( 1, 9, 16)
8411 20:00:15.282871 Total UI for P1: 0, mck2ui 16
8412 20:00:15.286759 best dqsien dly found for B1: ( 1, 9, 16)
8413 20:00:15.290008 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8414 20:00:15.293500 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8415 20:00:15.294015
8416 20:00:15.299342 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8417 20:00:15.302586 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8418 20:00:15.306281 [Gating] SW calibration Done
8419 20:00:15.306793 ==
8420 20:00:15.309836 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 20:00:15.312686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 20:00:15.313112 ==
8423 20:00:15.313443 RX Vref Scan: 0
8424 20:00:15.313753
8425 20:00:15.316152 RX Vref 0 -> 0, step: 1
8426 20:00:15.316570
8427 20:00:15.319928 RX Delay 0 -> 252, step: 8
8428 20:00:15.322460 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8429 20:00:15.326078 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8430 20:00:15.329389 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8431 20:00:15.336019 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8432 20:00:15.339238 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8433 20:00:15.343147 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8434 20:00:15.345746 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8435 20:00:15.349006 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8436 20:00:15.355994 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8437 20:00:15.358988 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8438 20:00:15.362727 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8439 20:00:15.365846 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8440 20:00:15.369134 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8441 20:00:15.375675 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8442 20:00:15.379439 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8443 20:00:15.382710 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8444 20:00:15.383273 ==
8445 20:00:15.385857 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 20:00:15.389011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 20:00:15.392270 ==
8448 20:00:15.392710 DQS Delay:
8449 20:00:15.393149 DQS0 = 0, DQS1 = 0
8450 20:00:15.395380 DQM Delay:
8451 20:00:15.395856 DQM0 = 132, DQM1 = 126
8452 20:00:15.399308 DQ Delay:
8453 20:00:15.402522 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8454 20:00:15.405649 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8455 20:00:15.408882 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8456 20:00:15.412200 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8457 20:00:15.412623
8458 20:00:15.412954
8459 20:00:15.413259 ==
8460 20:00:15.415540 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 20:00:15.419417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 20:00:15.419959 ==
8463 20:00:15.420317
8464 20:00:15.422173
8465 20:00:15.422605 TX Vref Scan disable
8466 20:00:15.425882 == TX Byte 0 ==
8467 20:00:15.429409 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8468 20:00:15.432316 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8469 20:00:15.436011 == TX Byte 1 ==
8470 20:00:15.439288 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8471 20:00:15.442089 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8472 20:00:15.442631 ==
8473 20:00:15.445363 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 20:00:15.452246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 20:00:15.452788 ==
8476 20:00:15.463756
8477 20:00:15.467423 TX Vref early break, caculate TX vref
8478 20:00:15.470332 TX Vref=16, minBit 5, minWin=21, winSum=360
8479 20:00:15.473628 TX Vref=18, minBit 10, minWin=22, winSum=370
8480 20:00:15.476730 TX Vref=20, minBit 5, minWin=23, winSum=383
8481 20:00:15.479860 TX Vref=22, minBit 11, minWin=22, winSum=392
8482 20:00:15.483990 TX Vref=24, minBit 1, minWin=24, winSum=402
8483 20:00:15.490480 TX Vref=26, minBit 0, minWin=24, winSum=410
8484 20:00:15.493393 TX Vref=28, minBit 5, minWin=24, winSum=410
8485 20:00:15.496697 TX Vref=30, minBit 0, minWin=25, winSum=415
8486 20:00:15.499960 TX Vref=32, minBit 1, minWin=23, winSum=401
8487 20:00:15.503868 TX Vref=34, minBit 3, minWin=23, winSum=390
8488 20:00:15.510110 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 30
8489 20:00:15.510652
8490 20:00:15.512869 Final TX Range 0 Vref 30
8491 20:00:15.513415
8492 20:00:15.513864 ==
8493 20:00:15.516603 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 20:00:15.519792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 20:00:15.520336 ==
8496 20:00:15.520841
8497 20:00:15.521291
8498 20:00:15.522999 TX Vref Scan disable
8499 20:00:15.529903 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8500 20:00:15.530467 == TX Byte 0 ==
8501 20:00:15.533494 u2DelayCellOfst[0]=22 cells (6 PI)
8502 20:00:15.536232 u2DelayCellOfst[1]=15 cells (4 PI)
8503 20:00:15.539758 u2DelayCellOfst[2]=0 cells (0 PI)
8504 20:00:15.543523 u2DelayCellOfst[3]=7 cells (2 PI)
8505 20:00:15.546223 u2DelayCellOfst[4]=11 cells (3 PI)
8506 20:00:15.549834 u2DelayCellOfst[5]=22 cells (6 PI)
8507 20:00:15.553195 u2DelayCellOfst[6]=22 cells (6 PI)
8508 20:00:15.556316 u2DelayCellOfst[7]=7 cells (2 PI)
8509 20:00:15.560114 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8510 20:00:15.563567 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8511 20:00:15.566321 == TX Byte 1 ==
8512 20:00:15.569537 u2DelayCellOfst[8]=0 cells (0 PI)
8513 20:00:15.570083 u2DelayCellOfst[9]=11 cells (3 PI)
8514 20:00:15.572808 u2DelayCellOfst[10]=15 cells (4 PI)
8515 20:00:15.576391 u2DelayCellOfst[11]=11 cells (3 PI)
8516 20:00:15.579547 u2DelayCellOfst[12]=18 cells (5 PI)
8517 20:00:15.583353 u2DelayCellOfst[13]=22 cells (6 PI)
8518 20:00:15.586094 u2DelayCellOfst[14]=22 cells (6 PI)
8519 20:00:15.589260 u2DelayCellOfst[15]=26 cells (7 PI)
8520 20:00:15.595788 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8521 20:00:15.600061 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8522 20:00:15.600642 DramC Write-DBI on
8523 20:00:15.601085 ==
8524 20:00:15.602600 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 20:00:15.609138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 20:00:15.609576 ==
8527 20:00:15.610021
8528 20:00:15.610432
8529 20:00:15.610841 TX Vref Scan disable
8530 20:00:15.613567 == TX Byte 0 ==
8531 20:00:15.616952 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8532 20:00:15.620285 == TX Byte 1 ==
8533 20:00:15.623441 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8534 20:00:15.626259 DramC Write-DBI off
8535 20:00:15.626692
8536 20:00:15.627129 [DATLAT]
8537 20:00:15.627674 Freq=1600, CH1 RK0
8538 20:00:15.628209
8539 20:00:15.629634 DATLAT Default: 0xf
8540 20:00:15.630212 0, 0xFFFF, sum = 0
8541 20:00:15.632758 1, 0xFFFF, sum = 0
8542 20:00:15.636078 2, 0xFFFF, sum = 0
8543 20:00:15.636519 3, 0xFFFF, sum = 0
8544 20:00:15.639464 4, 0xFFFF, sum = 0
8545 20:00:15.639909 5, 0xFFFF, sum = 0
8546 20:00:15.643337 6, 0xFFFF, sum = 0
8547 20:00:15.643820 7, 0xFFFF, sum = 0
8548 20:00:15.646102 8, 0xFFFF, sum = 0
8549 20:00:15.646540 9, 0xFFFF, sum = 0
8550 20:00:15.650104 10, 0xFFFF, sum = 0
8551 20:00:15.650656 11, 0xFFFF, sum = 0
8552 20:00:15.652732 12, 0xFFFF, sum = 0
8553 20:00:15.653173 13, 0x8FFF, sum = 0
8554 20:00:15.656037 14, 0x0, sum = 1
8555 20:00:15.656571 15, 0x0, sum = 2
8556 20:00:15.659759 16, 0x0, sum = 3
8557 20:00:15.660202 17, 0x0, sum = 4
8558 20:00:15.663076 best_step = 15
8559 20:00:15.663667
8560 20:00:15.664107 ==
8561 20:00:15.666164 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 20:00:15.669714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 20:00:15.670149 ==
8564 20:00:15.672918 RX Vref Scan: 1
8565 20:00:15.673463
8566 20:00:15.673917 Set Vref Range= 24 -> 127
8567 20:00:15.674339
8568 20:00:15.676001 RX Vref 24 -> 127, step: 1
8569 20:00:15.676437
8570 20:00:15.679580 RX Delay 11 -> 252, step: 4
8571 20:00:15.680016
8572 20:00:15.682674 Set Vref, RX VrefLevel [Byte0]: 24
8573 20:00:15.686178 [Byte1]: 24
8574 20:00:15.686710
8575 20:00:15.689442 Set Vref, RX VrefLevel [Byte0]: 25
8576 20:00:15.692707 [Byte1]: 25
8577 20:00:15.696102
8578 20:00:15.696540 Set Vref, RX VrefLevel [Byte0]: 26
8579 20:00:15.698931 [Byte1]: 26
8580 20:00:15.703533
8581 20:00:15.703979 Set Vref, RX VrefLevel [Byte0]: 27
8582 20:00:15.706951 [Byte1]: 27
8583 20:00:15.711438
8584 20:00:15.711873 Set Vref, RX VrefLevel [Byte0]: 28
8585 20:00:15.714434 [Byte1]: 28
8586 20:00:15.719246
8587 20:00:15.719848 Set Vref, RX VrefLevel [Byte0]: 29
8588 20:00:15.722081 [Byte1]: 29
8589 20:00:15.726500
8590 20:00:15.727059 Set Vref, RX VrefLevel [Byte0]: 30
8591 20:00:15.729813 [Byte1]: 30
8592 20:00:15.734681
8593 20:00:15.735217 Set Vref, RX VrefLevel [Byte0]: 31
8594 20:00:15.737457 [Byte1]: 31
8595 20:00:15.741788
8596 20:00:15.742328 Set Vref, RX VrefLevel [Byte0]: 32
8597 20:00:15.744797 [Byte1]: 32
8598 20:00:15.749361
8599 20:00:15.749885 Set Vref, RX VrefLevel [Byte0]: 33
8600 20:00:15.752918 [Byte1]: 33
8601 20:00:15.757224
8602 20:00:15.757701 Set Vref, RX VrefLevel [Byte0]: 34
8603 20:00:15.760399 [Byte1]: 34
8604 20:00:15.764816
8605 20:00:15.765356 Set Vref, RX VrefLevel [Byte0]: 35
8606 20:00:15.767774 [Byte1]: 35
8607 20:00:15.772524
8608 20:00:15.773063 Set Vref, RX VrefLevel [Byte0]: 36
8609 20:00:15.775289 [Byte1]: 36
8610 20:00:15.779652
8611 20:00:15.780189 Set Vref, RX VrefLevel [Byte0]: 37
8612 20:00:15.786391 [Byte1]: 37
8613 20:00:15.786934
8614 20:00:15.789813 Set Vref, RX VrefLevel [Byte0]: 38
8615 20:00:15.793553 [Byte1]: 38
8616 20:00:15.794082
8617 20:00:15.795972 Set Vref, RX VrefLevel [Byte0]: 39
8618 20:00:15.799756 [Byte1]: 39
8619 20:00:15.800280
8620 20:00:15.802935 Set Vref, RX VrefLevel [Byte0]: 40
8621 20:00:15.806475 [Byte1]: 40
8622 20:00:15.810713
8623 20:00:15.811251 Set Vref, RX VrefLevel [Byte0]: 41
8624 20:00:15.813335 [Byte1]: 41
8625 20:00:15.818268
8626 20:00:15.818851 Set Vref, RX VrefLevel [Byte0]: 42
8627 20:00:15.820952 [Byte1]: 42
8628 20:00:15.825968
8629 20:00:15.826508 Set Vref, RX VrefLevel [Byte0]: 43
8630 20:00:15.828885 [Byte1]: 43
8631 20:00:15.833235
8632 20:00:15.833749 Set Vref, RX VrefLevel [Byte0]: 44
8633 20:00:15.836500 [Byte1]: 44
8634 20:00:15.840900
8635 20:00:15.841421 Set Vref, RX VrefLevel [Byte0]: 45
8636 20:00:15.844300 [Byte1]: 45
8637 20:00:15.849004
8638 20:00:15.849528 Set Vref, RX VrefLevel [Byte0]: 46
8639 20:00:15.851491 [Byte1]: 46
8640 20:00:15.856032
8641 20:00:15.856551 Set Vref, RX VrefLevel [Byte0]: 47
8642 20:00:15.859466 [Byte1]: 47
8643 20:00:15.863508
8644 20:00:15.863999 Set Vref, RX VrefLevel [Byte0]: 48
8645 20:00:15.866847 [Byte1]: 48
8646 20:00:15.871472
8647 20:00:15.872049 Set Vref, RX VrefLevel [Byte0]: 49
8648 20:00:15.874594 [Byte1]: 49
8649 20:00:15.878711
8650 20:00:15.879130 Set Vref, RX VrefLevel [Byte0]: 50
8651 20:00:15.882325 [Byte1]: 50
8652 20:00:15.886670
8653 20:00:15.887189 Set Vref, RX VrefLevel [Byte0]: 51
8654 20:00:15.889868 [Byte1]: 51
8655 20:00:15.894576
8656 20:00:15.895099 Set Vref, RX VrefLevel [Byte0]: 52
8657 20:00:15.897304 [Byte1]: 52
8658 20:00:15.902085
8659 20:00:15.902654 Set Vref, RX VrefLevel [Byte0]: 53
8660 20:00:15.905339 [Byte1]: 53
8661 20:00:15.909279
8662 20:00:15.909697 Set Vref, RX VrefLevel [Byte0]: 54
8663 20:00:15.912912 [Byte1]: 54
8664 20:00:15.917045
8665 20:00:15.917584 Set Vref, RX VrefLevel [Byte0]: 55
8666 20:00:15.920243 [Byte1]: 55
8667 20:00:15.924276
8668 20:00:15.924707 Set Vref, RX VrefLevel [Byte0]: 56
8669 20:00:15.928083 [Byte1]: 56
8670 20:00:15.932357
8671 20:00:15.932895 Set Vref, RX VrefLevel [Byte0]: 57
8672 20:00:15.935503 [Byte1]: 57
8673 20:00:15.939946
8674 20:00:15.940482 Set Vref, RX VrefLevel [Byte0]: 58
8675 20:00:15.942993 [Byte1]: 58
8676 20:00:15.947513
8677 20:00:15.947948 Set Vref, RX VrefLevel [Byte0]: 59
8678 20:00:15.950958 [Byte1]: 59
8679 20:00:15.955196
8680 20:00:15.955787 Set Vref, RX VrefLevel [Byte0]: 60
8681 20:00:15.957989 [Byte1]: 60
8682 20:00:15.962573
8683 20:00:15.963108 Set Vref, RX VrefLevel [Byte0]: 61
8684 20:00:15.965873 [Byte1]: 61
8685 20:00:15.970195
8686 20:00:15.970740 Set Vref, RX VrefLevel [Byte0]: 62
8687 20:00:15.973181 [Byte1]: 62
8688 20:00:15.977672
8689 20:00:15.978191 Set Vref, RX VrefLevel [Byte0]: 63
8690 20:00:15.980839 [Byte1]: 63
8691 20:00:15.985341
8692 20:00:15.985880 Set Vref, RX VrefLevel [Byte0]: 64
8693 20:00:15.988404 [Byte1]: 64
8694 20:00:15.992940
8695 20:00:15.993359 Set Vref, RX VrefLevel [Byte0]: 65
8696 20:00:15.996658 [Byte1]: 65
8697 20:00:16.000316
8698 20:00:16.000725 Set Vref, RX VrefLevel [Byte0]: 66
8699 20:00:16.003618 [Byte1]: 66
8700 20:00:16.007909
8701 20:00:16.008201 Set Vref, RX VrefLevel [Byte0]: 67
8702 20:00:16.011578 [Byte1]: 67
8703 20:00:16.015421
8704 20:00:16.015737 Set Vref, RX VrefLevel [Byte0]: 68
8705 20:00:16.019147 [Byte1]: 68
8706 20:00:16.023029
8707 20:00:16.023268 Set Vref, RX VrefLevel [Byte0]: 69
8708 20:00:16.026774 [Byte1]: 69
8709 20:00:16.031500
8710 20:00:16.031807 Set Vref, RX VrefLevel [Byte0]: 70
8711 20:00:16.034315 [Byte1]: 70
8712 20:00:16.038380
8713 20:00:16.038688 Set Vref, RX VrefLevel [Byte0]: 71
8714 20:00:16.042021 [Byte1]: 71
8715 20:00:16.046516
8716 20:00:16.046876 Final RX Vref Byte 0 = 54 to rank0
8717 20:00:16.049863 Final RX Vref Byte 1 = 57 to rank0
8718 20:00:16.053173 Final RX Vref Byte 0 = 54 to rank1
8719 20:00:16.056616 Final RX Vref Byte 1 = 57 to rank1==
8720 20:00:16.059920 Dram Type= 6, Freq= 0, CH_1, rank 0
8721 20:00:16.066494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8722 20:00:16.067003 ==
8723 20:00:16.067333 DQS Delay:
8724 20:00:16.067689 DQS0 = 0, DQS1 = 0
8725 20:00:16.069961 DQM Delay:
8726 20:00:16.070464 DQM0 = 130, DQM1 = 123
8727 20:00:16.072576 DQ Delay:
8728 20:00:16.076818 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8729 20:00:16.079735 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =128
8730 20:00:16.082770 DQ8 =110, DQ9 =114, DQ10 =122, DQ11 =116
8731 20:00:16.085832 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8732 20:00:16.086238
8733 20:00:16.086564
8734 20:00:16.086867
8735 20:00:16.089315 [DramC_TX_OE_Calibration] TA2
8736 20:00:16.092719 Original DQ_B0 (3 6) =30, OEN = 27
8737 20:00:16.096092 Original DQ_B1 (3 6) =30, OEN = 27
8738 20:00:16.099199 24, 0x0, End_B0=24 End_B1=24
8739 20:00:16.099668 25, 0x0, End_B0=25 End_B1=25
8740 20:00:16.102850 26, 0x0, End_B0=26 End_B1=26
8741 20:00:16.105966 27, 0x0, End_B0=27 End_B1=27
8742 20:00:16.109258 28, 0x0, End_B0=28 End_B1=28
8743 20:00:16.112626 29, 0x0, End_B0=29 End_B1=29
8744 20:00:16.113154 30, 0x0, End_B0=30 End_B1=30
8745 20:00:16.115619 31, 0x4141, End_B0=30 End_B1=30
8746 20:00:16.119255 Byte0 end_step=30 best_step=27
8747 20:00:16.122346 Byte1 end_step=30 best_step=27
8748 20:00:16.125713 Byte0 TX OE(2T, 0.5T) = (3, 3)
8749 20:00:16.129006 Byte1 TX OE(2T, 0.5T) = (3, 3)
8750 20:00:16.129438
8751 20:00:16.129880
8752 20:00:16.136226 [DQSOSCAuto] RK0, (LSB)MR18= 0x90e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
8753 20:00:16.139046 CH1 RK0: MR19=303, MR18=90E
8754 20:00:16.145825 CH1_RK0: MR19=0x303, MR18=0x90E, DQSOSC=402, MR23=63, INC=22, DEC=15
8755 20:00:16.146337
8756 20:00:16.148835 ----->DramcWriteLeveling(PI) begin...
8757 20:00:16.149365 ==
8758 20:00:16.152274 Dram Type= 6, Freq= 0, CH_1, rank 1
8759 20:00:16.155682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 20:00:16.156214 ==
8761 20:00:16.158681 Write leveling (Byte 0): 25 => 25
8762 20:00:16.162095 Write leveling (Byte 1): 27 => 27
8763 20:00:16.165690 DramcWriteLeveling(PI) end<-----
8764 20:00:16.166207
8765 20:00:16.166651 ==
8766 20:00:16.168796 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 20:00:16.171581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 20:00:16.172022 ==
8769 20:00:16.175501 [Gating] SW mode calibration
8770 20:00:16.181842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8771 20:00:16.189105 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8772 20:00:16.192010 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 20:00:16.198292 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 20:00:16.202084 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
8775 20:00:16.205486 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8776 20:00:16.208444 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 20:00:16.215307 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 20:00:16.218639 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 20:00:16.221953 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 20:00:16.228330 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 20:00:16.231526 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 20:00:16.235004 1 5 8 | B1->B0 | 3333 2727 | 1 0 | (1 0) (1 0)
8783 20:00:16.241830 1 5 12 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)
8784 20:00:16.244788 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 20:00:16.249030 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 20:00:16.255213 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 20:00:16.258516 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 20:00:16.261963 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 20:00:16.268434 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8790 20:00:16.271989 1 6 8 | B1->B0 | 2c2c 4545 | 0 0 | (1 1) (1 1)
8791 20:00:16.274853 1 6 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
8792 20:00:16.281814 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 20:00:16.284913 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 20:00:16.288267 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 20:00:16.295036 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 20:00:16.297936 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 20:00:16.301264 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 20:00:16.308254 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8799 20:00:16.311214 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8800 20:00:16.314490 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 20:00:16.321512 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 20:00:16.324564 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 20:00:16.327829 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 20:00:16.334501 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 20:00:16.337848 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 20:00:16.341066 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 20:00:16.348039 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 20:00:16.351164 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 20:00:16.354405 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 20:00:16.360744 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 20:00:16.363923 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 20:00:16.368020 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 20:00:16.374544 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 20:00:16.377619 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8815 20:00:16.380815 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8816 20:00:16.383967 Total UI for P1: 0, mck2ui 16
8817 20:00:16.387515 best dqsien dly found for B0: ( 1, 9, 8)
8818 20:00:16.391126 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 20:00:16.394576 Total UI for P1: 0, mck2ui 16
8820 20:00:16.397351 best dqsien dly found for B1: ( 1, 9, 10)
8821 20:00:16.400899 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8822 20:00:16.407479 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8823 20:00:16.407996
8824 20:00:16.410900 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8825 20:00:16.413993 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8826 20:00:16.417005 [Gating] SW calibration Done
8827 20:00:16.417527 ==
8828 20:00:16.420223 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 20:00:16.423556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 20:00:16.423981 ==
8831 20:00:16.427285 RX Vref Scan: 0
8832 20:00:16.427870
8833 20:00:16.428212 RX Vref 0 -> 0, step: 1
8834 20:00:16.428524
8835 20:00:16.430328 RX Delay 0 -> 252, step: 8
8836 20:00:16.433856 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8837 20:00:16.437529 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8838 20:00:16.443625 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8839 20:00:16.447363 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8840 20:00:16.450440 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8841 20:00:16.453867 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8842 20:00:16.456667 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8843 20:00:16.463457 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8844 20:00:16.466623 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8845 20:00:16.470443 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8846 20:00:16.473510 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8847 20:00:16.477105 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8848 20:00:16.483806 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8849 20:00:16.486803 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8850 20:00:16.490546 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8851 20:00:16.493259 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8852 20:00:16.493678 ==
8853 20:00:16.497149 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 20:00:16.503754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 20:00:16.504312 ==
8856 20:00:16.504654 DQS Delay:
8857 20:00:16.507258 DQS0 = 0, DQS1 = 0
8858 20:00:16.507830 DQM Delay:
8859 20:00:16.510103 DQM0 = 130, DQM1 = 128
8860 20:00:16.510627 DQ Delay:
8861 20:00:16.513598 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8862 20:00:16.516876 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =127
8863 20:00:16.520066 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8864 20:00:16.523258 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =139
8865 20:00:16.523752
8866 20:00:16.524086
8867 20:00:16.524399 ==
8868 20:00:16.526431 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 20:00:16.533307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 20:00:16.533847 ==
8871 20:00:16.534181
8872 20:00:16.534484
8873 20:00:16.534773 TX Vref Scan disable
8874 20:00:16.536550 == TX Byte 0 ==
8875 20:00:16.539755 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8876 20:00:16.546675 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8877 20:00:16.547250 == TX Byte 1 ==
8878 20:00:16.550243 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8879 20:00:16.556525 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8880 20:00:16.557039 ==
8881 20:00:16.560238 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 20:00:16.563378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 20:00:16.563827 ==
8884 20:00:16.576639
8885 20:00:16.579844 TX Vref early break, caculate TX vref
8886 20:00:16.583520 TX Vref=16, minBit 0, minWin=22, winSum=387
8887 20:00:16.587078 TX Vref=18, minBit 0, minWin=23, winSum=394
8888 20:00:16.589793 TX Vref=20, minBit 0, minWin=23, winSum=401
8889 20:00:16.592911 TX Vref=22, minBit 0, minWin=23, winSum=407
8890 20:00:16.596165 TX Vref=24, minBit 0, minWin=24, winSum=417
8891 20:00:16.603187 TX Vref=26, minBit 0, minWin=25, winSum=426
8892 20:00:16.606163 TX Vref=28, minBit 5, minWin=25, winSum=429
8893 20:00:16.610030 TX Vref=30, minBit 0, minWin=25, winSum=425
8894 20:00:16.613570 TX Vref=32, minBit 1, minWin=23, winSum=408
8895 20:00:16.616644 TX Vref=34, minBit 0, minWin=23, winSum=407
8896 20:00:16.619562 TX Vref=36, minBit 0, minWin=23, winSum=397
8897 20:00:16.626540 [TxChooseVref] Worse bit 5, Min win 25, Win sum 429, Final Vref 28
8898 20:00:16.627056
8899 20:00:16.629429 Final TX Range 0 Vref 28
8900 20:00:16.629839
8901 20:00:16.630164 ==
8902 20:00:16.632707 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 20:00:16.636348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 20:00:16.636859 ==
8905 20:00:16.637187
8906 20:00:16.637490
8907 20:00:16.639811 TX Vref Scan disable
8908 20:00:16.646595 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8909 20:00:16.647007 == TX Byte 0 ==
8910 20:00:16.649774 u2DelayCellOfst[0]=22 cells (6 PI)
8911 20:00:16.653518 u2DelayCellOfst[1]=18 cells (5 PI)
8912 20:00:16.656359 u2DelayCellOfst[2]=0 cells (0 PI)
8913 20:00:16.660046 u2DelayCellOfst[3]=7 cells (2 PI)
8914 20:00:16.663238 u2DelayCellOfst[4]=11 cells (3 PI)
8915 20:00:16.665993 u2DelayCellOfst[5]=26 cells (7 PI)
8916 20:00:16.669804 u2DelayCellOfst[6]=22 cells (6 PI)
8917 20:00:16.672851 u2DelayCellOfst[7]=7 cells (2 PI)
8918 20:00:16.676396 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8919 20:00:16.679429 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8920 20:00:16.682636 == TX Byte 1 ==
8921 20:00:16.685569 u2DelayCellOfst[8]=0 cells (0 PI)
8922 20:00:16.688981 u2DelayCellOfst[9]=7 cells (2 PI)
8923 20:00:16.689495 u2DelayCellOfst[10]=11 cells (3 PI)
8924 20:00:16.692255 u2DelayCellOfst[11]=7 cells (2 PI)
8925 20:00:16.695774 u2DelayCellOfst[12]=18 cells (5 PI)
8926 20:00:16.699270 u2DelayCellOfst[13]=22 cells (6 PI)
8927 20:00:16.702582 u2DelayCellOfst[14]=22 cells (6 PI)
8928 20:00:16.706163 u2DelayCellOfst[15]=18 cells (5 PI)
8929 20:00:16.713544 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8930 20:00:16.715523 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8931 20:00:16.715940 DramC Write-DBI on
8932 20:00:16.716265 ==
8933 20:00:16.718645 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 20:00:16.725310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 20:00:16.725734 ==
8936 20:00:16.726066
8937 20:00:16.726376
8938 20:00:16.726672 TX Vref Scan disable
8939 20:00:16.729290 == TX Byte 0 ==
8940 20:00:16.733266 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8941 20:00:16.736286 == TX Byte 1 ==
8942 20:00:16.739609 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8943 20:00:16.742657 DramC Write-DBI off
8944 20:00:16.743073
8945 20:00:16.743433 [DATLAT]
8946 20:00:16.743751 Freq=1600, CH1 RK1
8947 20:00:16.744056
8948 20:00:16.746065 DATLAT Default: 0xf
8949 20:00:16.746526 0, 0xFFFF, sum = 0
8950 20:00:16.749315 1, 0xFFFF, sum = 0
8951 20:00:16.749692 2, 0xFFFF, sum = 0
8952 20:00:16.752876 3, 0xFFFF, sum = 0
8953 20:00:16.755969 4, 0xFFFF, sum = 0
8954 20:00:16.756398 5, 0xFFFF, sum = 0
8955 20:00:16.759548 6, 0xFFFF, sum = 0
8956 20:00:16.759974 7, 0xFFFF, sum = 0
8957 20:00:16.763055 8, 0xFFFF, sum = 0
8958 20:00:16.763520 9, 0xFFFF, sum = 0
8959 20:00:16.765960 10, 0xFFFF, sum = 0
8960 20:00:16.766572 11, 0xFFFF, sum = 0
8961 20:00:16.769963 12, 0xFFFF, sum = 0
8962 20:00:16.770496 13, 0x8FFF, sum = 0
8963 20:00:16.772883 14, 0x0, sum = 1
8964 20:00:16.773330 15, 0x0, sum = 2
8965 20:00:16.776460 16, 0x0, sum = 3
8966 20:00:16.776885 17, 0x0, sum = 4
8967 20:00:16.779634 best_step = 15
8968 20:00:16.780149
8969 20:00:16.780483 ==
8970 20:00:16.782815 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 20:00:16.786255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 20:00:16.786679 ==
8973 20:00:16.789388 RX Vref Scan: 0
8974 20:00:16.789804
8975 20:00:16.790136 RX Vref 0 -> 0, step: 1
8976 20:00:16.790448
8977 20:00:16.792615 RX Delay 3 -> 252, step: 4
8978 20:00:16.796162 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8979 20:00:16.802500 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8980 20:00:16.806095 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8981 20:00:16.809655 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8982 20:00:16.812215 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8983 20:00:16.815976 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8984 20:00:16.822582 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8985 20:00:16.825886 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
8986 20:00:16.829604 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8987 20:00:16.832169 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8988 20:00:16.835733 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8989 20:00:16.842726 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8990 20:00:16.845819 iDelay=195, Bit 12, Center 134 (79 ~ 190) 112
8991 20:00:16.848781 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8992 20:00:16.852112 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8993 20:00:16.858984 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8994 20:00:16.859538 ==
8995 20:00:16.862240 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 20:00:16.865298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 20:00:16.865820 ==
8998 20:00:16.866154 DQS Delay:
8999 20:00:16.868545 DQS0 = 0, DQS1 = 0
9000 20:00:16.868954 DQM Delay:
9001 20:00:16.872316 DQM0 = 127, DQM1 = 125
9002 20:00:16.872829 DQ Delay:
9003 20:00:16.875944 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =124
9004 20:00:16.878716 DQ4 =124, DQ5 =140, DQ6 =138, DQ7 =122
9005 20:00:16.882265 DQ8 =108, DQ9 =112, DQ10 =128, DQ11 =120
9006 20:00:16.885051 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =134
9007 20:00:16.885467
9008 20:00:16.888886
9009 20:00:16.889402
9010 20:00:16.889731 [DramC_TX_OE_Calibration] TA2
9011 20:00:16.892250 Original DQ_B0 (3 6) =30, OEN = 27
9012 20:00:16.895051 Original DQ_B1 (3 6) =30, OEN = 27
9013 20:00:16.898795 24, 0x0, End_B0=24 End_B1=24
9014 20:00:16.901890 25, 0x0, End_B0=25 End_B1=25
9015 20:00:16.905024 26, 0x0, End_B0=26 End_B1=26
9016 20:00:16.905500 27, 0x0, End_B0=27 End_B1=27
9017 20:00:16.908220 28, 0x0, End_B0=28 End_B1=28
9018 20:00:16.911769 29, 0x0, End_B0=29 End_B1=29
9019 20:00:16.914557 30, 0x0, End_B0=30 End_B1=30
9020 20:00:16.918252 31, 0x4141, End_B0=30 End_B1=30
9021 20:00:16.918670 Byte0 end_step=30 best_step=27
9022 20:00:16.922161 Byte1 end_step=30 best_step=27
9023 20:00:16.924511 Byte0 TX OE(2T, 0.5T) = (3, 3)
9024 20:00:16.928322 Byte1 TX OE(2T, 0.5T) = (3, 3)
9025 20:00:16.928840
9026 20:00:16.929179
9027 20:00:16.938537 [DQSOSCAuto] RK1, (LSB)MR18= 0x121e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9028 20:00:16.939052 CH1 RK1: MR19=303, MR18=121E
9029 20:00:16.944892 CH1_RK1: MR19=0x303, MR18=0x121E, DQSOSC=394, MR23=63, INC=23, DEC=15
9030 20:00:16.947739 [RxdqsGatingPostProcess] freq 1600
9031 20:00:16.954478 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9032 20:00:16.958269 best DQS0 dly(2T, 0.5T) = (1, 1)
9033 20:00:16.961568 best DQS1 dly(2T, 0.5T) = (1, 1)
9034 20:00:16.964248 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9035 20:00:16.964665 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9036 20:00:16.967578 best DQS0 dly(2T, 0.5T) = (1, 1)
9037 20:00:16.971296 best DQS1 dly(2T, 0.5T) = (1, 1)
9038 20:00:16.974893 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9039 20:00:16.978460 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9040 20:00:16.981194 Pre-setting of DQS Precalculation
9041 20:00:16.987841 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9042 20:00:16.994907 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9043 20:00:17.001030 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9044 20:00:17.001530
9045 20:00:17.001853
9046 20:00:17.004347 [Calibration Summary] 3200 Mbps
9047 20:00:17.004860 CH 0, Rank 0
9048 20:00:17.007868 SW Impedance : PASS
9049 20:00:17.011198 DUTY Scan : NO K
9050 20:00:17.011834 ZQ Calibration : PASS
9051 20:00:17.013835 Jitter Meter : NO K
9052 20:00:17.017203 CBT Training : PASS
9053 20:00:17.017612 Write leveling : PASS
9054 20:00:17.021017 RX DQS gating : PASS
9055 20:00:17.023828 RX DQ/DQS(RDDQC) : PASS
9056 20:00:17.024367 TX DQ/DQS : PASS
9057 20:00:17.027587 RX DATLAT : PASS
9058 20:00:17.028274 RX DQ/DQS(Engine): PASS
9059 20:00:17.031129 TX OE : PASS
9060 20:00:17.031573 All Pass.
9061 20:00:17.031903
9062 20:00:17.033862 CH 0, Rank 1
9063 20:00:17.034271 SW Impedance : PASS
9064 20:00:17.037309 DUTY Scan : NO K
9065 20:00:17.040617 ZQ Calibration : PASS
9066 20:00:17.041133 Jitter Meter : NO K
9067 20:00:17.043962 CBT Training : PASS
9068 20:00:17.047120 Write leveling : PASS
9069 20:00:17.047574 RX DQS gating : PASS
9070 20:00:17.050328 RX DQ/DQS(RDDQC) : PASS
9071 20:00:17.053765 TX DQ/DQS : PASS
9072 20:00:17.054283 RX DATLAT : PASS
9073 20:00:17.057409 RX DQ/DQS(Engine): PASS
9074 20:00:17.060206 TX OE : PASS
9075 20:00:17.060620 All Pass.
9076 20:00:17.060947
9077 20:00:17.061249 CH 1, Rank 0
9078 20:00:17.064090 SW Impedance : PASS
9079 20:00:17.066689 DUTY Scan : NO K
9080 20:00:17.067116 ZQ Calibration : PASS
9081 20:00:17.070340 Jitter Meter : NO K
9082 20:00:17.073967 CBT Training : PASS
9083 20:00:17.074481 Write leveling : PASS
9084 20:00:17.076685 RX DQS gating : PASS
9085 20:00:17.080081 RX DQ/DQS(RDDQC) : PASS
9086 20:00:17.080588 TX DQ/DQS : PASS
9087 20:00:17.083510 RX DATLAT : PASS
9088 20:00:17.087085 RX DQ/DQS(Engine): PASS
9089 20:00:17.087637 TX OE : PASS
9090 20:00:17.090009 All Pass.
9091 20:00:17.090414
9092 20:00:17.090737 CH 1, Rank 1
9093 20:00:17.093287 SW Impedance : PASS
9094 20:00:17.093799 DUTY Scan : NO K
9095 20:00:17.096678 ZQ Calibration : PASS
9096 20:00:17.100163 Jitter Meter : NO K
9097 20:00:17.100672 CBT Training : PASS
9098 20:00:17.103590 Write leveling : PASS
9099 20:00:17.104102 RX DQS gating : PASS
9100 20:00:17.106959 RX DQ/DQS(RDDQC) : PASS
9101 20:00:17.110613 TX DQ/DQS : PASS
9102 20:00:17.111122 RX DATLAT : PASS
9103 20:00:17.113094 RX DQ/DQS(Engine): PASS
9104 20:00:17.116357 TX OE : PASS
9105 20:00:17.116871 All Pass.
9106 20:00:17.117199
9107 20:00:17.120040 DramC Write-DBI on
9108 20:00:17.120548 PER_BANK_REFRESH: Hybrid Mode
9109 20:00:17.123460 TX_TRACKING: ON
9110 20:00:17.133064 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9111 20:00:17.139921 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9112 20:00:17.146672 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9113 20:00:17.149702 [FAST_K] Save calibration result to emmc
9114 20:00:17.153426 sync common calibartion params.
9115 20:00:17.156838 sync cbt_mode0:1, 1:1
9116 20:00:17.157353 dram_init: ddr_geometry: 2
9117 20:00:17.159764 dram_init: ddr_geometry: 2
9118 20:00:17.163528 dram_init: ddr_geometry: 2
9119 20:00:17.166638 0:dram_rank_size:100000000
9120 20:00:17.167159 1:dram_rank_size:100000000
9121 20:00:17.173867 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9122 20:00:17.176163 DFS_SHUFFLE_HW_MODE: ON
9123 20:00:17.179985 dramc_set_vcore_voltage set vcore to 725000
9124 20:00:17.180658 Read voltage for 1600, 0
9125 20:00:17.182918 Vio18 = 0
9126 20:00:17.183325 Vcore = 725000
9127 20:00:17.183740 Vdram = 0
9128 20:00:17.186246 Vddq = 0
9129 20:00:17.186705 Vmddr = 0
9130 20:00:17.189917 switch to 3200 Mbps bootup
9131 20:00:17.190432 [DramcRunTimeConfig]
9132 20:00:17.190763 PHYPLL
9133 20:00:17.193228 DPM_CONTROL_AFTERK: ON
9134 20:00:17.196056 PER_BANK_REFRESH: ON
9135 20:00:17.199638 REFRESH_OVERHEAD_REDUCTION: ON
9136 20:00:17.200052 CMD_PICG_NEW_MODE: OFF
9137 20:00:17.203197 XRTWTW_NEW_MODE: ON
9138 20:00:17.203747 XRTRTR_NEW_MODE: ON
9139 20:00:17.206377 TX_TRACKING: ON
9140 20:00:17.206917 RDSEL_TRACKING: OFF
9141 20:00:17.210240 DQS Precalculation for DVFS: ON
9142 20:00:17.212834 RX_TRACKING: OFF
9143 20:00:17.213248 HW_GATING DBG: ON
9144 20:00:17.216468 ZQCS_ENABLE_LP4: ON
9145 20:00:17.216979 RX_PICG_NEW_MODE: ON
9146 20:00:17.219571 TX_PICG_NEW_MODE: ON
9147 20:00:17.220086 ENABLE_RX_DCM_DPHY: ON
9148 20:00:17.222836 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9149 20:00:17.226310 DUMMY_READ_FOR_TRACKING: OFF
9150 20:00:17.229721 !!! SPM_CONTROL_AFTERK: OFF
9151 20:00:17.232651 !!! SPM could not control APHY
9152 20:00:17.233174 IMPEDANCE_TRACKING: ON
9153 20:00:17.235906 TEMP_SENSOR: ON
9154 20:00:17.236318 HW_SAVE_FOR_SR: OFF
9155 20:00:17.239907 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9156 20:00:17.242651 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9157 20:00:17.246097 Read ODT Tracking: ON
9158 20:00:17.249319 Refresh Rate DeBounce: ON
9159 20:00:17.249730 DFS_NO_QUEUE_FLUSH: ON
9160 20:00:17.253304 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9161 20:00:17.256155 ENABLE_DFS_RUNTIME_MRW: OFF
9162 20:00:17.259079 DDR_RESERVE_NEW_MODE: ON
9163 20:00:17.259621 MR_CBT_SWITCH_FREQ: ON
9164 20:00:17.262233 =========================
9165 20:00:17.281428 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9166 20:00:17.284399 dram_init: ddr_geometry: 2
9167 20:00:17.302787 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9168 20:00:17.306347 dram_init: dram init end (result: 0)
9169 20:00:17.312652 DRAM-K: Full calibration passed in 24591 msecs
9170 20:00:17.316206 MRC: failed to locate region type 0.
9171 20:00:17.316621 DRAM rank0 size:0x100000000,
9172 20:00:17.319748 DRAM rank1 size=0x100000000
9173 20:00:17.329213 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9174 20:00:17.336336 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9175 20:00:17.342738 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9176 20:00:17.348617 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9177 20:00:17.352321 DRAM rank0 size:0x100000000,
9178 20:00:17.355847 DRAM rank1 size=0x100000000
9179 20:00:17.356436 CBMEM:
9180 20:00:17.359119 IMD: root @ 0xfffff000 254 entries.
9181 20:00:17.362149 IMD: root @ 0xffffec00 62 entries.
9182 20:00:17.365454 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9183 20:00:17.372108 WARNING: RO_VPD is uninitialized or empty.
9184 20:00:17.375457 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9185 20:00:17.382659 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9186 20:00:17.395543 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9187 20:00:17.407169 BS: romstage times (exec / console): total (unknown) / 24053 ms
9188 20:00:17.407713
9189 20:00:17.408043
9190 20:00:17.416677 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9191 20:00:17.420771 ARM64: Exception handlers installed.
9192 20:00:17.423541 ARM64: Testing exception
9193 20:00:17.426703 ARM64: Done test exception
9194 20:00:17.427261 Enumerating buses...
9195 20:00:17.430200 Show all devs... Before device enumeration.
9196 20:00:17.433853 Root Device: enabled 1
9197 20:00:17.436838 CPU_CLUSTER: 0: enabled 1
9198 20:00:17.437353 CPU: 00: enabled 1
9199 20:00:17.439968 Compare with tree...
9200 20:00:17.440376 Root Device: enabled 1
9201 20:00:17.443939 CPU_CLUSTER: 0: enabled 1
9202 20:00:17.446973 CPU: 00: enabled 1
9203 20:00:17.447524 Root Device scanning...
9204 20:00:17.449767 scan_static_bus for Root Device
9205 20:00:17.453752 CPU_CLUSTER: 0 enabled
9206 20:00:17.456690 scan_static_bus for Root Device done
9207 20:00:17.459960 scan_bus: bus Root Device finished in 8 msecs
9208 20:00:17.460480 done
9209 20:00:17.466835 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9210 20:00:17.470098 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9211 20:00:17.476306 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9212 20:00:17.479616 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9213 20:00:17.482949 Allocating resources...
9214 20:00:17.486878 Reading resources...
9215 20:00:17.489363 Root Device read_resources bus 0 link: 0
9216 20:00:17.492807 DRAM rank0 size:0x100000000,
9217 20:00:17.493360 DRAM rank1 size=0x100000000
9218 20:00:17.496161 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9219 20:00:17.499100 CPU: 00 missing read_resources
9220 20:00:17.506016 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9221 20:00:17.509150 Root Device read_resources bus 0 link: 0 done
9222 20:00:17.512324 Done reading resources.
9223 20:00:17.515936 Show resources in subtree (Root Device)...After reading.
9224 20:00:17.518926 Root Device child on link 0 CPU_CLUSTER: 0
9225 20:00:17.523313 CPU_CLUSTER: 0 child on link 0 CPU: 00
9226 20:00:17.532208 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9227 20:00:17.532713 CPU: 00
9228 20:00:17.536207 Root Device assign_resources, bus 0 link: 0
9229 20:00:17.539011 CPU_CLUSTER: 0 missing set_resources
9230 20:00:17.546544 Root Device assign_resources, bus 0 link: 0 done
9231 20:00:17.547075 Done setting resources.
9232 20:00:17.552275 Show resources in subtree (Root Device)...After assigning values.
9233 20:00:17.555966 Root Device child on link 0 CPU_CLUSTER: 0
9234 20:00:17.558924 CPU_CLUSTER: 0 child on link 0 CPU: 00
9235 20:00:17.569210 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9236 20:00:17.569774 CPU: 00
9237 20:00:17.572104 Done allocating resources.
9238 20:00:17.579134 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9239 20:00:17.579716 Enabling resources...
9240 20:00:17.580050 done.
9241 20:00:17.585489 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9242 20:00:17.588747 Initializing devices...
9243 20:00:17.589166 Root Device init
9244 20:00:17.591739 init hardware done!
9245 20:00:17.592147 0x00000018: ctrlr->caps
9246 20:00:17.596004 52.000 MHz: ctrlr->f_max
9247 20:00:17.598495 0.400 MHz: ctrlr->f_min
9248 20:00:17.599010 0x40ff8080: ctrlr->voltages
9249 20:00:17.602070 sclk: 390625
9250 20:00:17.602481 Bus Width = 1
9251 20:00:17.602804 sclk: 390625
9252 20:00:17.605428 Bus Width = 1
9253 20:00:17.605955 Early init status = 3
9254 20:00:17.612415 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9255 20:00:17.615071 in-header: 03 fc 00 00 01 00 00 00
9256 20:00:17.618553 in-data: 00
9257 20:00:17.622232 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9258 20:00:17.626892 in-header: 03 fd 00 00 00 00 00 00
9259 20:00:17.630279 in-data:
9260 20:00:17.633502 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9261 20:00:17.638061 in-header: 03 fc 00 00 01 00 00 00
9262 20:00:17.641175 in-data: 00
9263 20:00:17.644263 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9264 20:00:17.650337 in-header: 03 fd 00 00 00 00 00 00
9265 20:00:17.653529 in-data:
9266 20:00:17.656921 [SSUSB] Setting up USB HOST controller...
9267 20:00:17.660276 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9268 20:00:17.663368 [SSUSB] phy power-on done.
9269 20:00:17.667199 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9270 20:00:17.673373 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9271 20:00:17.676812 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9272 20:00:17.683478 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9273 20:00:17.690286 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9274 20:00:17.697057 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9275 20:00:17.702979 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9276 20:00:17.709748 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9277 20:00:17.713084 SPM: binary array size = 0x9dc
9278 20:00:17.716553 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9279 20:00:17.723564 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9280 20:00:17.729582 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9281 20:00:17.736447 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9282 20:00:17.739551 configure_display: Starting display init
9283 20:00:17.773607 anx7625_power_on_init: Init interface.
9284 20:00:17.776952 anx7625_disable_pd_protocol: Disabled PD feature.
9285 20:00:17.780002 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9286 20:00:17.808034 anx7625_start_dp_work: Secure OCM version=00
9287 20:00:17.811578 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9288 20:00:17.825819 sp_tx_get_edid_block: EDID Block = 1
9289 20:00:17.928310 Extracted contents:
9290 20:00:17.931776 header: 00 ff ff ff ff ff ff 00
9291 20:00:17.935090 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9292 20:00:17.938599 version: 01 04
9293 20:00:17.941400 basic params: 95 1f 11 78 0a
9294 20:00:17.944638 chroma info: 76 90 94 55 54 90 27 21 50 54
9295 20:00:17.947971 established: 00 00 00
9296 20:00:17.954871 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9297 20:00:17.957915 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9298 20:00:17.965155 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9299 20:00:17.971339 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9300 20:00:17.978423 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9301 20:00:17.981284 extensions: 00
9302 20:00:17.981791 checksum: fb
9303 20:00:17.982203
9304 20:00:17.984630 Manufacturer: IVO Model 57d Serial Number 0
9305 20:00:17.988283 Made week 0 of 2020
9306 20:00:17.991341 EDID version: 1.4
9307 20:00:17.991907 Digital display
9308 20:00:17.994509 6 bits per primary color channel
9309 20:00:17.995023 DisplayPort interface
9310 20:00:17.997734 Maximum image size: 31 cm x 17 cm
9311 20:00:18.000903 Gamma: 220%
9312 20:00:18.001313 Check DPMS levels
9313 20:00:18.004424 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9314 20:00:18.011068 First detailed timing is preferred timing
9315 20:00:18.011517 Established timings supported:
9316 20:00:18.014475 Standard timings supported:
9317 20:00:18.017671 Detailed timings
9318 20:00:18.021155 Hex of detail: 383680a07038204018303c0035ae10000019
9319 20:00:18.027761 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9320 20:00:18.030828 0780 0798 07c8 0820 hborder 0
9321 20:00:18.034255 0438 043b 0447 0458 vborder 0
9322 20:00:18.037832 -hsync -vsync
9323 20:00:18.038336 Did detailed timing
9324 20:00:18.044120 Hex of detail: 000000000000000000000000000000000000
9325 20:00:18.047770 Manufacturer-specified data, tag 0
9326 20:00:18.050527 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9327 20:00:18.054466 ASCII string: InfoVision
9328 20:00:18.057476 Hex of detail: 000000fe00523134304e574635205248200a
9329 20:00:18.060786 ASCII string: R140NWF5 RH
9330 20:00:18.061198 Checksum
9331 20:00:18.063772 Checksum: 0xfb (valid)
9332 20:00:18.067149 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9333 20:00:18.070761 DSI data_rate: 832800000 bps
9334 20:00:18.077367 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9335 20:00:18.080734 anx7625_parse_edid: pixelclock(138800).
9336 20:00:18.084069 hactive(1920), hsync(48), hfp(24), hbp(88)
9337 20:00:18.087108 vactive(1080), vsync(12), vfp(3), vbp(17)
9338 20:00:18.090660 anx7625_dsi_config: config dsi.
9339 20:00:18.096858 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9340 20:00:18.111472 anx7625_dsi_config: success to config DSI
9341 20:00:18.113739 anx7625_dp_start: MIPI phy setup OK.
9342 20:00:18.116908 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9343 20:00:18.120813 mtk_ddp_mode_set invalid vrefresh 60
9344 20:00:18.123790 main_disp_path_setup
9345 20:00:18.124303 ovl_layer_smi_id_en
9346 20:00:18.126952 ovl_layer_smi_id_en
9347 20:00:18.127482 ccorr_config
9348 20:00:18.127826 aal_config
9349 20:00:18.130684 gamma_config
9350 20:00:18.131193 postmask_config
9351 20:00:18.133629 dither_config
9352 20:00:18.137058 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9353 20:00:18.143516 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9354 20:00:18.147351 Root Device init finished in 554 msecs
9355 20:00:18.150572 CPU_CLUSTER: 0 init
9356 20:00:18.157433 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9357 20:00:18.160601 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9358 20:00:18.163805 APU_MBOX 0x190000b0 = 0x10001
9359 20:00:18.167167 APU_MBOX 0x190001b0 = 0x10001
9360 20:00:18.170047 APU_MBOX 0x190005b0 = 0x10001
9361 20:00:18.173444 APU_MBOX 0x190006b0 = 0x10001
9362 20:00:18.176533 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9363 20:00:18.189747 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9364 20:00:18.201856 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9365 20:00:18.208156 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9366 20:00:18.220024 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9367 20:00:18.229767 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9368 20:00:18.232380 CPU_CLUSTER: 0 init finished in 81 msecs
9369 20:00:18.235827 Devices initialized
9370 20:00:18.239070 Show all devs... After init.
9371 20:00:18.239526 Root Device: enabled 1
9372 20:00:18.242582 CPU_CLUSTER: 0: enabled 1
9373 20:00:18.246583 CPU: 00: enabled 1
9374 20:00:18.249254 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9375 20:00:18.253123 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9376 20:00:18.256179 ELOG: NV offset 0x57f000 size 0x1000
9377 20:00:18.262938 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9378 20:00:18.269419 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9379 20:00:18.272323 ELOG: Event(17) added with size 13 at 2023-10-28 20:00:18 UTC
9380 20:00:18.279431 out: cmd=0x121: 03 db 21 01 00 00 00 00
9381 20:00:18.282446 in-header: 03 47 00 00 2c 00 00 00
9382 20:00:18.292012 in-data: 17 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9383 20:00:18.298840 ELOG: Event(A1) added with size 10 at 2023-10-28 20:00:18 UTC
9384 20:00:18.305238 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9385 20:00:18.312182 ELOG: Event(A0) added with size 9 at 2023-10-28 20:00:18 UTC
9386 20:00:18.315820 ELOG: Event(16) added with size 11 at 2023-10-28 20:00:18 UTC
9387 20:00:18.393589 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9388 20:00:18.396997 elog_add_boot_reason: Logged dev mode boot
9389 20:00:18.403100 BS: BS_POST_DEVICE entry times (exec / console): 74 / 74 ms
9390 20:00:18.403675 Finalize devices...
9391 20:00:18.406531 Devices finalized
9392 20:00:18.409881 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9393 20:00:18.413653 Writing coreboot table at 0xffe64000
9394 20:00:18.420098 0. 000000000010a000-0000000000113fff: RAMSTAGE
9395 20:00:18.423617 1. 0000000040000000-00000000400fffff: RAM
9396 20:00:18.426569 2. 0000000040100000-000000004032afff: RAMSTAGE
9397 20:00:18.429812 3. 000000004032b000-00000000545fffff: RAM
9398 20:00:18.433254 4. 0000000054600000-000000005465ffff: BL31
9399 20:00:18.436724 5. 0000000054660000-00000000ffe63fff: RAM
9400 20:00:18.443604 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9401 20:00:18.446776 7. 0000000100000000-000000023fffffff: RAM
9402 20:00:18.450004 Passing 5 GPIOs to payload:
9403 20:00:18.452838 NAME | PORT | POLARITY | VALUE
9404 20:00:18.459758 EC in RW | 0x000000aa | low | undefined
9405 20:00:18.463255 EC interrupt | 0x00000005 | low | undefined
9406 20:00:18.466737 TPM interrupt | 0x000000ab | high | undefined
9407 20:00:18.472845 SD card detect | 0x00000011 | high | undefined
9408 20:00:18.476406 speaker enable | 0x00000093 | high | undefined
9409 20:00:18.479684 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9410 20:00:18.483845 in-header: 03 f9 00 00 02 00 00 00
9411 20:00:18.487044 in-data: 02 00
9412 20:00:18.490089 ADC[4]: Raw value=896670 ID=7
9413 20:00:18.493768 ADC[3]: Raw value=213440 ID=1
9414 20:00:18.494178 RAM Code: 0x71
9415 20:00:18.496805 ADC[6]: Raw value=74722 ID=0
9416 20:00:18.500085 ADC[5]: Raw value=212700 ID=1
9417 20:00:18.500496 SKU Code: 0x1
9418 20:00:18.507126 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 360f
9419 20:00:18.507676 coreboot table: 964 bytes.
9420 20:00:18.510105 IMD ROOT 0. 0xfffff000 0x00001000
9421 20:00:18.514017 IMD SMALL 1. 0xffffe000 0x00001000
9422 20:00:18.516900 RO MCACHE 2. 0xffffc000 0x00001104
9423 20:00:18.519897 CONSOLE 3. 0xfff7c000 0x00080000
9424 20:00:18.523648 FMAP 4. 0xfff7b000 0x00000452
9425 20:00:18.526708 TIME STAMP 5. 0xfff7a000 0x00000910
9426 20:00:18.529976 VBOOT WORK 6. 0xfff66000 0x00014000
9427 20:00:18.533546 RAMOOPS 7. 0xffe66000 0x00100000
9428 20:00:18.536435 COREBOOT 8. 0xffe64000 0x00002000
9429 20:00:18.540388 IMD small region:
9430 20:00:18.543377 IMD ROOT 0. 0xffffec00 0x00000400
9431 20:00:18.546623 VPD 1. 0xffffeb80 0x0000006c
9432 20:00:18.550124 MMC STATUS 2. 0xffffeb60 0x00000004
9433 20:00:18.552972 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9434 20:00:18.556935 Probing TPM: done!
9435 20:00:18.560291 Connected to device vid:did:rid of 1ae0:0028:00
9436 20:00:18.571366 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9437 20:00:18.574467 Initialized TPM device CR50 revision 0
9438 20:00:18.578224 Checking cr50 for pending updates
9439 20:00:18.582245 Reading cr50 TPM mode
9440 20:00:18.590447 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9441 20:00:18.597535 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9442 20:00:18.637115 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9443 20:00:18.640291 Checking segment from ROM address 0x40100000
9444 20:00:18.643994 Checking segment from ROM address 0x4010001c
9445 20:00:18.650423 Loading segment from ROM address 0x40100000
9446 20:00:18.650947 code (compression=0)
9447 20:00:18.660788 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9448 20:00:18.667363 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9449 20:00:18.667936 it's not compressed!
9450 20:00:18.673829 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9451 20:00:18.680391 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9452 20:00:18.697636 Loading segment from ROM address 0x4010001c
9453 20:00:18.698157 Entry Point 0x80000000
9454 20:00:18.701507 Loaded segments
9455 20:00:18.704395 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9456 20:00:18.710967 Jumping to boot code at 0x80000000(0xffe64000)
9457 20:00:18.718105 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9458 20:00:18.724665 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9459 20:00:18.732246 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9460 20:00:18.735519 Checking segment from ROM address 0x40100000
9461 20:00:18.738815 Checking segment from ROM address 0x4010001c
9462 20:00:18.745906 Loading segment from ROM address 0x40100000
9463 20:00:18.746434 code (compression=1)
9464 20:00:18.752310 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9465 20:00:18.762362 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9466 20:00:18.762872 using LZMA
9467 20:00:18.770419 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9468 20:00:18.777169 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9469 20:00:18.780457 Loading segment from ROM address 0x4010001c
9470 20:00:18.780975 Entry Point 0x54601000
9471 20:00:18.783338 Loaded segments
9472 20:00:18.786935 NOTICE: MT8192 bl31_setup
9473 20:00:18.794090 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9474 20:00:18.797591 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9475 20:00:18.800719 WARNING: region 0:
9476 20:00:18.804286 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 20:00:18.804877 WARNING: region 1:
9478 20:00:18.810655 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9479 20:00:18.815018 WARNING: region 2:
9480 20:00:18.817483 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9481 20:00:18.820395 WARNING: region 3:
9482 20:00:18.824927 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 20:00:18.827292 WARNING: region 4:
9484 20:00:18.834190 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 20:00:18.834723 WARNING: region 5:
9486 20:00:18.837326 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 20:00:18.841256 WARNING: region 6:
9488 20:00:18.844352 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 20:00:18.844869 WARNING: region 7:
9490 20:00:18.851244 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 20:00:18.857624 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9492 20:00:18.861096 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9493 20:00:18.864733 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9494 20:00:18.871353 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9495 20:00:18.874342 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9496 20:00:18.877704 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9497 20:00:18.884598 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9498 20:00:18.887855 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9499 20:00:18.891372 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9500 20:00:18.897720 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9501 20:00:18.900939 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9502 20:00:18.907674 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9503 20:00:18.911075 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9504 20:00:18.914419 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9505 20:00:18.920767 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9506 20:00:18.924188 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9507 20:00:18.927617 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9508 20:00:18.934275 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9509 20:00:18.937085 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9510 20:00:18.943950 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9511 20:00:18.947048 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9512 20:00:18.950438 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9513 20:00:18.957086 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9514 20:00:18.961115 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9515 20:00:18.967158 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9516 20:00:18.970504 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9517 20:00:18.974234 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9518 20:00:18.980570 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9519 20:00:18.983491 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9520 20:00:18.990683 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9521 20:00:18.994245 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9522 20:00:18.997039 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9523 20:00:19.004051 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9524 20:00:19.006865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9525 20:00:19.010411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9526 20:00:19.014296 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9527 20:00:19.020656 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9528 20:00:19.023751 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9529 20:00:19.027518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9530 20:00:19.030510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9531 20:00:19.037365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9532 20:00:19.040645 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9533 20:00:19.043701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9534 20:00:19.047358 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9535 20:00:19.053718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9536 20:00:19.057344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9537 20:00:19.060129 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9538 20:00:19.063979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9539 20:00:19.070561 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9540 20:00:19.074320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9541 20:00:19.080447 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9542 20:00:19.084099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9543 20:00:19.087639 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9544 20:00:19.094014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9545 20:00:19.097215 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9546 20:00:19.103809 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9547 20:00:19.107230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9548 20:00:19.114301 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9549 20:00:19.117233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9550 20:00:19.123764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9551 20:00:19.127230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9552 20:00:19.130910 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9553 20:00:19.137335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9554 20:00:19.140892 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9555 20:00:19.147233 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9556 20:00:19.150386 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9557 20:00:19.157300 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9558 20:00:19.160198 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9559 20:00:19.163671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9560 20:00:19.170212 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9561 20:00:19.174033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9562 20:00:19.180204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9563 20:00:19.183946 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9564 20:00:19.190623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9565 20:00:19.193956 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9566 20:00:19.197498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9567 20:00:19.204410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9568 20:00:19.207340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9569 20:00:19.214015 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9570 20:00:19.216941 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9571 20:00:19.224354 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9572 20:00:19.227663 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9573 20:00:19.230934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9574 20:00:19.237616 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9575 20:00:19.240964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9576 20:00:19.247833 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9577 20:00:19.250752 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9578 20:00:19.257883 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9579 20:00:19.261385 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9580 20:00:19.264085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9581 20:00:19.271146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9582 20:00:19.274317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9583 20:00:19.280960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9584 20:00:19.284154 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9585 20:00:19.290765 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9586 20:00:19.294024 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9587 20:00:19.297379 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9588 20:00:19.304102 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9589 20:00:19.307327 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9590 20:00:19.311050 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9591 20:00:19.314120 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9592 20:00:19.320253 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9593 20:00:19.323704 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9594 20:00:19.331143 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9595 20:00:19.333657 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9596 20:00:19.337406 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9597 20:00:19.344040 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9598 20:00:19.347031 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9599 20:00:19.353673 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9600 20:00:19.357062 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9601 20:00:19.360349 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9602 20:00:19.367275 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9603 20:00:19.370381 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9604 20:00:19.377095 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9605 20:00:19.380138 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9606 20:00:19.384173 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9607 20:00:19.386979 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9608 20:00:19.394026 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9609 20:00:19.397356 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9610 20:00:19.400217 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9611 20:00:19.406577 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9612 20:00:19.410572 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9613 20:00:19.413909 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9614 20:00:19.416706 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9615 20:00:19.423196 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9616 20:00:19.426647 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9617 20:00:19.433384 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9618 20:00:19.437075 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9619 20:00:19.439778 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9620 20:00:19.446720 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9621 20:00:19.450061 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9622 20:00:19.456712 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9623 20:00:19.460330 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9624 20:00:19.463910 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9625 20:00:19.470320 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9626 20:00:19.473371 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9627 20:00:19.480206 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9628 20:00:19.483768 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9629 20:00:19.486730 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9630 20:00:19.493229 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9631 20:00:19.496825 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9632 20:00:19.500209 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9633 20:00:19.506360 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9634 20:00:19.509924 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9635 20:00:19.516217 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9636 20:00:19.519680 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9637 20:00:19.523473 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9638 20:00:19.529663 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9639 20:00:19.533056 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9640 20:00:19.539853 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9641 20:00:19.543458 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9642 20:00:19.546844 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9643 20:00:19.552883 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9644 20:00:19.556984 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9645 20:00:19.560000 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9646 20:00:19.566560 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9647 20:00:19.570283 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9648 20:00:19.576724 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9649 20:00:19.579365 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9650 20:00:19.583243 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9651 20:00:19.590088 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9652 20:00:19.593343 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9653 20:00:19.600015 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9654 20:00:19.603541 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9655 20:00:19.606160 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9656 20:00:19.612746 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9657 20:00:19.616361 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9658 20:00:19.623181 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9659 20:00:19.626172 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9660 20:00:19.629633 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9661 20:00:19.636104 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9662 20:00:19.639648 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9663 20:00:19.643096 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9664 20:00:19.649861 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9665 20:00:19.652578 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9666 20:00:19.659944 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9667 20:00:19.663166 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9668 20:00:19.669619 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9669 20:00:19.672893 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9670 20:00:19.676060 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9671 20:00:19.682677 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9672 20:00:19.686204 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9673 20:00:19.689259 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9674 20:00:19.695949 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9675 20:00:19.699302 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9676 20:00:19.705482 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9677 20:00:19.709349 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9678 20:00:19.712064 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9679 20:00:19.719139 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9680 20:00:19.722495 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9681 20:00:19.729217 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9682 20:00:19.732414 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9683 20:00:19.739112 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9684 20:00:19.742343 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9685 20:00:19.745382 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9686 20:00:19.752247 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9687 20:00:19.755134 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9688 20:00:19.762694 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9689 20:00:19.765958 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9690 20:00:19.772034 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9691 20:00:19.775235 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9692 20:00:19.778825 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9693 20:00:19.785638 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9694 20:00:19.789113 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9695 20:00:19.795809 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9696 20:00:19.798527 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9697 20:00:19.801885 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9698 20:00:19.808829 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9699 20:00:19.812585 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9700 20:00:19.818735 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9701 20:00:19.822145 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9702 20:00:19.825826 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9703 20:00:19.831600 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9704 20:00:19.835046 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9705 20:00:19.841809 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9706 20:00:19.844908 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9707 20:00:19.852005 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9708 20:00:19.855258 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9709 20:00:19.858725 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9710 20:00:19.864898 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9711 20:00:19.868304 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9712 20:00:19.875051 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9713 20:00:19.878053 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9714 20:00:19.881552 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9715 20:00:19.888408 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9716 20:00:19.891859 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9717 20:00:19.898562 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9718 20:00:19.901589 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9719 20:00:19.908082 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9720 20:00:19.911490 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9721 20:00:19.914789 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9722 20:00:19.918147 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9723 20:00:19.921968 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9724 20:00:19.928024 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9725 20:00:19.930994 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9726 20:00:19.934616 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9727 20:00:19.941045 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9728 20:00:19.944755 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9729 20:00:19.951455 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9730 20:00:19.954935 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9731 20:00:19.957975 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9732 20:00:19.964361 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9733 20:00:19.968050 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9734 20:00:19.971337 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9735 20:00:19.977645 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9736 20:00:19.981057 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9737 20:00:19.987643 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9738 20:00:19.990991 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9739 20:00:19.994089 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9740 20:00:20.000395 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9741 20:00:20.003735 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9742 20:00:20.007296 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9743 20:00:20.013781 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9744 20:00:20.016983 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9745 20:00:20.020330 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9746 20:00:20.027082 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9747 20:00:20.030612 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9748 20:00:20.037030 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9749 20:00:20.040024 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9750 20:00:20.043423 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9751 20:00:20.049831 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9752 20:00:20.053462 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9753 20:00:20.060543 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9754 20:00:20.063223 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9755 20:00:20.066731 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9756 20:00:20.073168 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9757 20:00:20.076705 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9758 20:00:20.080330 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9759 20:00:20.086793 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9760 20:00:20.089883 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9761 20:00:20.092948 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9762 20:00:20.096588 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9763 20:00:20.103087 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9764 20:00:20.106315 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9765 20:00:20.109463 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9766 20:00:20.112886 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9767 20:00:20.119945 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9768 20:00:20.123004 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9769 20:00:20.126369 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9770 20:00:20.129535 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9771 20:00:20.136378 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9772 20:00:20.139420 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9773 20:00:20.142971 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9774 20:00:20.149191 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9775 20:00:20.152665 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9776 20:00:20.159116 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9777 20:00:20.162240 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9778 20:00:20.169291 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9779 20:00:20.172454 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9780 20:00:20.175712 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9781 20:00:20.181992 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9782 20:00:20.185453 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9783 20:00:20.191996 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9784 20:00:20.195672 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9785 20:00:20.198727 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9786 20:00:20.205059 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9787 20:00:20.208538 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9788 20:00:20.215250 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9789 20:00:20.218480 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9790 20:00:20.222278 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9791 20:00:20.228627 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9792 20:00:20.231953 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9793 20:00:20.238567 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9794 20:00:20.241480 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9795 20:00:20.248170 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9796 20:00:20.251720 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9797 20:00:20.255560 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9798 20:00:20.261927 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9799 20:00:20.265596 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9800 20:00:20.272072 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9801 20:00:20.275342 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9802 20:00:20.278140 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9803 20:00:20.285115 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9804 20:00:20.288488 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9805 20:00:20.294682 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9806 20:00:20.298227 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9807 20:00:20.301908 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9808 20:00:20.307981 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9809 20:00:20.311253 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9810 20:00:20.318016 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9811 20:00:20.321206 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9812 20:00:20.327839 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9813 20:00:20.331574 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9814 20:00:20.334570 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9815 20:00:20.341219 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9816 20:00:20.344124 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9817 20:00:20.351059 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9818 20:00:20.353989 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9819 20:00:20.360884 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9820 20:00:20.364224 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9821 20:00:20.367768 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9822 20:00:20.374377 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9823 20:00:20.377101 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9824 20:00:20.384114 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9825 20:00:20.387739 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9826 20:00:20.390724 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9827 20:00:20.397341 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9828 20:00:20.400766 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9829 20:00:20.407361 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9830 20:00:20.410748 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9831 20:00:20.413985 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9832 20:00:20.420801 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9833 20:00:20.423872 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9834 20:00:20.430566 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9835 20:00:20.433481 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9836 20:00:20.436822 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9837 20:00:20.443511 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9838 20:00:20.447151 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9839 20:00:20.454026 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9840 20:00:20.457020 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9841 20:00:20.463840 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9842 20:00:20.467001 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9843 20:00:20.469996 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9844 20:00:20.476534 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9845 20:00:20.480170 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9846 20:00:20.487258 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9847 20:00:20.490094 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9848 20:00:20.497296 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9849 20:00:20.500029 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9850 20:00:20.503751 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9851 20:00:20.509781 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9852 20:00:20.513713 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9853 20:00:20.520052 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9854 20:00:20.523541 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9855 20:00:20.529949 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9856 20:00:20.532981 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9857 20:00:20.539604 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9858 20:00:20.543146 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9859 20:00:20.546460 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9860 20:00:20.552592 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9861 20:00:20.555868 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9862 20:00:20.562395 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9863 20:00:20.566342 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9864 20:00:20.572885 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9865 20:00:20.576119 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9866 20:00:20.582402 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9867 20:00:20.585771 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9868 20:00:20.588918 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9869 20:00:20.595925 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9870 20:00:20.599103 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9871 20:00:20.605171 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9872 20:00:20.608422 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9873 20:00:20.615596 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9874 20:00:20.618690 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9875 20:00:20.625195 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9876 20:00:20.628606 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9877 20:00:20.632145 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9878 20:00:20.638576 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9879 20:00:20.642319 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9880 20:00:20.648428 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9881 20:00:20.652085 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9882 20:00:20.658712 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9883 20:00:20.661804 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9884 20:00:20.665013 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9885 20:00:20.671926 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9886 20:00:20.675526 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9887 20:00:20.681541 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9888 20:00:20.684633 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9889 20:00:20.690922 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9890 20:00:20.695013 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9891 20:00:20.701425 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9892 20:00:20.704514 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9893 20:00:20.707779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9894 20:00:20.714369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9895 20:00:20.718058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9896 20:00:20.724173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9897 20:00:20.727937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9898 20:00:20.734226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9899 20:00:20.737397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9900 20:00:20.744702 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9901 20:00:20.747594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9902 20:00:20.754553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9903 20:00:20.757407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9904 20:00:20.763936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9905 20:00:20.767886 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9906 20:00:20.774342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9907 20:00:20.777277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9908 20:00:20.780912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9909 20:00:20.786911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9910 20:00:20.790251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9911 20:00:20.797661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9912 20:00:20.800757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9913 20:00:20.806549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9914 20:00:20.810123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9915 20:00:20.816965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9916 20:00:20.820788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9917 20:00:20.827182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9918 20:00:20.833364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9919 20:00:20.836634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9920 20:00:20.843351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9921 20:00:20.846661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9922 20:00:20.853533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9923 20:00:20.856143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9924 20:00:20.863269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9925 20:00:20.866790 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9926 20:00:20.867317 INFO: [APUAPC] vio 0
9927 20:00:20.874297 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9928 20:00:20.877014 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9929 20:00:20.880478 INFO: [APUAPC] D0_APC_0: 0x400510
9930 20:00:20.883749 INFO: [APUAPC] D0_APC_1: 0x0
9931 20:00:20.887068 INFO: [APUAPC] D0_APC_2: 0x1540
9932 20:00:20.890734 INFO: [APUAPC] D0_APC_3: 0x0
9933 20:00:20.893890 INFO: [APUAPC] D1_APC_0: 0xffffffff
9934 20:00:20.897436 INFO: [APUAPC] D1_APC_1: 0xffffffff
9935 20:00:20.901048 INFO: [APUAPC] D1_APC_2: 0x3fffff
9936 20:00:20.903767 INFO: [APUAPC] D1_APC_3: 0x0
9937 20:00:20.907295 INFO: [APUAPC] D2_APC_0: 0xffffffff
9938 20:00:20.910030 INFO: [APUAPC] D2_APC_1: 0xffffffff
9939 20:00:20.913683 INFO: [APUAPC] D2_APC_2: 0x3fffff
9940 20:00:20.916608 INFO: [APUAPC] D2_APC_3: 0x0
9941 20:00:20.920704 INFO: [APUAPC] D3_APC_0: 0xffffffff
9942 20:00:20.923433 INFO: [APUAPC] D3_APC_1: 0xffffffff
9943 20:00:20.926988 INFO: [APUAPC] D3_APC_2: 0x3fffff
9944 20:00:20.930024 INFO: [APUAPC] D3_APC_3: 0x0
9945 20:00:20.933730 INFO: [APUAPC] D4_APC_0: 0xffffffff
9946 20:00:20.936424 INFO: [APUAPC] D4_APC_1: 0xffffffff
9947 20:00:20.940487 INFO: [APUAPC] D4_APC_2: 0x3fffff
9948 20:00:20.943742 INFO: [APUAPC] D4_APC_3: 0x0
9949 20:00:20.946935 INFO: [APUAPC] D5_APC_0: 0xffffffff
9950 20:00:20.950395 INFO: [APUAPC] D5_APC_1: 0xffffffff
9951 20:00:20.953392 INFO: [APUAPC] D5_APC_2: 0x3fffff
9952 20:00:20.953919 INFO: [APUAPC] D5_APC_3: 0x0
9953 20:00:20.956430 INFO: [APUAPC] D6_APC_0: 0xffffffff
9954 20:00:20.963661 INFO: [APUAPC] D6_APC_1: 0xffffffff
9955 20:00:20.966899 INFO: [APUAPC] D6_APC_2: 0x3fffff
9956 20:00:20.967456 INFO: [APUAPC] D6_APC_3: 0x0
9957 20:00:20.970045 INFO: [APUAPC] D7_APC_0: 0xffffffff
9958 20:00:20.973400 INFO: [APUAPC] D7_APC_1: 0xffffffff
9959 20:00:20.976546 INFO: [APUAPC] D7_APC_2: 0x3fffff
9960 20:00:20.980338 INFO: [APUAPC] D7_APC_3: 0x0
9961 20:00:20.983618 INFO: [APUAPC] D8_APC_0: 0xffffffff
9962 20:00:20.986350 INFO: [APUAPC] D8_APC_1: 0xffffffff
9963 20:00:20.989672 INFO: [APUAPC] D8_APC_2: 0x3fffff
9964 20:00:20.992644 INFO: [APUAPC] D8_APC_3: 0x0
9965 20:00:20.996295 INFO: [APUAPC] D9_APC_0: 0xffffffff
9966 20:00:21.000022 INFO: [APUAPC] D9_APC_1: 0xffffffff
9967 20:00:21.003512 INFO: [APUAPC] D9_APC_2: 0x3fffff
9968 20:00:21.006398 INFO: [APUAPC] D9_APC_3: 0x0
9969 20:00:21.009485 INFO: [APUAPC] D10_APC_0: 0xffffffff
9970 20:00:21.013429 INFO: [APUAPC] D10_APC_1: 0xffffffff
9971 20:00:21.016575 INFO: [APUAPC] D10_APC_2: 0x3fffff
9972 20:00:21.019693 INFO: [APUAPC] D10_APC_3: 0x0
9973 20:00:21.023142 INFO: [APUAPC] D11_APC_0: 0xffffffff
9974 20:00:21.026441 INFO: [APUAPC] D11_APC_1: 0xffffffff
9975 20:00:21.030100 INFO: [APUAPC] D11_APC_2: 0x3fffff
9976 20:00:21.032539 INFO: [APUAPC] D11_APC_3: 0x0
9977 20:00:21.036292 INFO: [APUAPC] D12_APC_0: 0xffffffff
9978 20:00:21.039849 INFO: [APUAPC] D12_APC_1: 0xffffffff
9979 20:00:21.043182 INFO: [APUAPC] D12_APC_2: 0x3fffff
9980 20:00:21.046440 INFO: [APUAPC] D12_APC_3: 0x0
9981 20:00:21.049597 INFO: [APUAPC] D13_APC_0: 0xffffffff
9982 20:00:21.052686 INFO: [APUAPC] D13_APC_1: 0xffffffff
9983 20:00:21.056388 INFO: [APUAPC] D13_APC_2: 0x3fffff
9984 20:00:21.059860 INFO: [APUAPC] D13_APC_3: 0x0
9985 20:00:21.062821 INFO: [APUAPC] D14_APC_0: 0xffffffff
9986 20:00:21.066397 INFO: [APUAPC] D14_APC_1: 0xffffffff
9987 20:00:21.069830 INFO: [APUAPC] D14_APC_2: 0x3fffff
9988 20:00:21.072751 INFO: [APUAPC] D14_APC_3: 0x0
9989 20:00:21.075942 INFO: [APUAPC] D15_APC_0: 0xffffffff
9990 20:00:21.079347 INFO: [APUAPC] D15_APC_1: 0xffffffff
9991 20:00:21.082684 INFO: [APUAPC] D15_APC_2: 0x3fffff
9992 20:00:21.086173 INFO: [APUAPC] D15_APC_3: 0x0
9993 20:00:21.089173 INFO: [APUAPC] APC_CON: 0x4
9994 20:00:21.092118 INFO: [NOCDAPC] D0_APC_0: 0x0
9995 20:00:21.095347 INFO: [NOCDAPC] D0_APC_1: 0x0
9996 20:00:21.099167 INFO: [NOCDAPC] D1_APC_0: 0x0
9997 20:00:21.102152 INFO: [NOCDAPC] D1_APC_1: 0xfff
9998 20:00:21.105909 INFO: [NOCDAPC] D2_APC_0: 0x0
9999 20:00:21.108963 INFO: [NOCDAPC] D2_APC_1: 0xfff
10000 20:00:21.109383 INFO: [NOCDAPC] D3_APC_0: 0x0
10001 20:00:21.111861 INFO: [NOCDAPC] D3_APC_1: 0xfff
10002 20:00:21.116027 INFO: [NOCDAPC] D4_APC_0: 0x0
10003 20:00:21.118780 INFO: [NOCDAPC] D4_APC_1: 0xfff
10004 20:00:21.122503 INFO: [NOCDAPC] D5_APC_0: 0x0
10005 20:00:21.125494 INFO: [NOCDAPC] D5_APC_1: 0xfff
10006 20:00:21.128559 INFO: [NOCDAPC] D6_APC_0: 0x0
10007 20:00:21.132128 INFO: [NOCDAPC] D6_APC_1: 0xfff
10008 20:00:21.135261 INFO: [NOCDAPC] D7_APC_0: 0x0
10009 20:00:21.139124 INFO: [NOCDAPC] D7_APC_1: 0xfff
10010 20:00:21.142059 INFO: [NOCDAPC] D8_APC_0: 0x0
10011 20:00:21.145342 INFO: [NOCDAPC] D8_APC_1: 0xfff
10012 20:00:21.145811 INFO: [NOCDAPC] D9_APC_0: 0x0
10013 20:00:21.148511 INFO: [NOCDAPC] D9_APC_1: 0xfff
10014 20:00:21.152158 INFO: [NOCDAPC] D10_APC_0: 0x0
10015 20:00:21.155514 INFO: [NOCDAPC] D10_APC_1: 0xfff
10016 20:00:21.158757 INFO: [NOCDAPC] D11_APC_0: 0x0
10017 20:00:21.162287 INFO: [NOCDAPC] D11_APC_1: 0xfff
10018 20:00:21.165377 INFO: [NOCDAPC] D12_APC_0: 0x0
10019 20:00:21.168631 INFO: [NOCDAPC] D12_APC_1: 0xfff
10020 20:00:21.172366 INFO: [NOCDAPC] D13_APC_0: 0x0
10021 20:00:21.175347 INFO: [NOCDAPC] D13_APC_1: 0xfff
10022 20:00:21.178797 INFO: [NOCDAPC] D14_APC_0: 0x0
10023 20:00:21.181927 INFO: [NOCDAPC] D14_APC_1: 0xfff
10024 20:00:21.185304 INFO: [NOCDAPC] D15_APC_0: 0x0
10025 20:00:21.188407 INFO: [NOCDAPC] D15_APC_1: 0xfff
10026 20:00:21.188834 INFO: [NOCDAPC] APC_CON: 0x4
10027 20:00:21.191893 INFO: [APUAPC] set_apusys_apc done
10028 20:00:21.195521 INFO: [DEVAPC] devapc_init done
10029 20:00:21.202148 INFO: GICv3 without legacy support detected.
10030 20:00:21.205189 INFO: ARM GICv3 driver initialized in EL3
10031 20:00:21.208196 INFO: Maximum SPI INTID supported: 639
10032 20:00:21.211999 INFO: BL31: Initializing runtime services
10033 20:00:21.218342 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10034 20:00:21.221737 INFO: SPM: enable CPC mode
10035 20:00:21.225157 INFO: mcdi ready for mcusys-off-idle and system suspend
10036 20:00:21.231549 INFO: BL31: Preparing for EL3 exit to normal world
10037 20:00:21.234730 INFO: Entry point address = 0x80000000
10038 20:00:21.235154 INFO: SPSR = 0x8
10039 20:00:21.242098
10040 20:00:21.242619
10041 20:00:21.242957
10042 20:00:21.245591 Starting depthcharge on Spherion...
10043 20:00:21.246010
10044 20:00:21.246340 Wipe memory regions:
10045 20:00:21.246651
10046 20:00:21.249329 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10047 20:00:21.249854 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10048 20:00:21.250259 Setting prompt string to ['asurada:']
10049 20:00:21.250638 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10050 20:00:21.251289 [0x00000040000000, 0x00000054600000)
10051 20:00:21.371562
10052 20:00:21.372079 [0x00000054660000, 0x00000080000000)
10053 20:00:21.631452
10054 20:00:21.631991 [0x000000821a7280, 0x000000ffe64000)
10055 20:00:22.376178
10056 20:00:22.376806 [0x00000100000000, 0x00000240000000)
10057 20:00:24.265138
10058 20:00:24.268021 Initializing XHCI USB controller at 0x11200000.
10059 20:00:25.306427
10060 20:00:25.308959 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10061 20:00:25.309342
10062 20:00:25.309860
10063 20:00:25.310218
10064 20:00:25.310958 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10066 20:00:25.412161 asurada: tftpboot 192.168.201.1 11899596/tftp-deploy-qe5iq69e/kernel/image.itb 11899596/tftp-deploy-qe5iq69e/kernel/cmdline
10067 20:00:25.412822 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 20:00:25.413306 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10069 20:00:25.418425 tftpboot 192.168.201.1 11899596/tftp-deploy-qe5iq69e/kernel/image.ittp-deploy-qe5iq69e/kernel/cmdline
10070 20:00:25.418940
10071 20:00:25.419265 Waiting for link
10072 20:00:25.579213
10073 20:00:25.579774 R8152: Initializing
10074 20:00:25.580108
10075 20:00:25.582295 Version 6 (ocp_data = 5c30)
10076 20:00:25.582808
10077 20:00:25.585766 R8152: Done initializing
10078 20:00:25.586286
10079 20:00:25.586618 Adding net device
10080 20:00:27.612101
10081 20:00:27.612663 done.
10082 20:00:27.612998
10083 20:00:27.613308 MAC: 00:24:32:30:78:ff
10084 20:00:27.613607
10085 20:00:27.615068 Sending DHCP discover... done.
10086 20:00:27.615596
10087 20:00:27.618296 Waiting for reply... done.
10088 20:00:27.618713
10089 20:00:27.621223 Sending DHCP request... done.
10090 20:00:27.621734
10091 20:00:27.622079 Waiting for reply... done.
10092 20:00:27.622406
10093 20:00:27.624870 My ip is 192.168.201.21
10094 20:00:27.625392
10095 20:00:27.628099 The DHCP server ip is 192.168.201.1
10096 20:00:27.628535
10097 20:00:27.631540 TFTP server IP predefined by user: 192.168.201.1
10098 20:00:27.632053
10099 20:00:27.638274 Bootfile predefined by user: 11899596/tftp-deploy-qe5iq69e/kernel/image.itb
10100 20:00:27.638867
10101 20:00:27.640880 Sending tftp read request... done.
10102 20:00:27.641461
10103 20:00:27.649700 Waiting for the transfer...
10104 20:00:27.650137
10105 20:00:28.394597 00000000 ################################################################
10106 20:00:28.395142
10107 20:00:29.137331 00080000 ################################################################
10108 20:00:29.137940
10109 20:00:29.878156 00100000 ################################################################
10110 20:00:29.878749
10111 20:00:30.629938 00180000 ################################################################
10112 20:00:30.630571
10113 20:00:31.384885 00200000 ################################################################
10114 20:00:31.385413
10115 20:00:32.141468 00280000 ################################################################
10116 20:00:32.142012
10117 20:00:32.883437 00300000 ################################################################
10118 20:00:32.884051
10119 20:00:33.628119 00380000 ################################################################
10120 20:00:33.628640
10121 20:00:34.369643 00400000 ################################################################
10122 20:00:34.370193
10123 20:00:35.110322 00480000 ################################################################
10124 20:00:35.110932
10125 20:00:35.864016 00500000 ################################################################
10126 20:00:35.864523
10127 20:00:36.621363 00580000 ################################################################
10128 20:00:36.621908
10129 20:00:37.374924 00600000 ################################################################
10130 20:00:37.375461
10131 20:00:38.123484 00680000 ################################################################
10132 20:00:38.124067
10133 20:00:38.869074 00700000 ################################################################
10134 20:00:38.869872
10135 20:00:39.622620 00780000 ################################################################
10136 20:00:39.623155
10137 20:00:40.377026 00800000 ################################################################
10138 20:00:40.377549
10139 20:00:41.135295 00880000 ################################################################
10140 20:00:41.135850
10141 20:00:41.877902 00900000 ################################################################
10142 20:00:41.878518
10143 20:00:42.617999 00980000 ################################################################
10144 20:00:42.618510
10145 20:00:43.361876 00a00000 ################################################################
10146 20:00:43.362422
10147 20:00:44.102598 00a80000 ################################################################
10148 20:00:44.103144
10149 20:00:44.837156 00b00000 ################################################################
10150 20:00:44.837653
10151 20:00:45.582061 00b80000 ################################################################
10152 20:00:45.582631
10153 20:00:46.321413 00c00000 ################################################################
10154 20:00:46.322092
10155 20:00:47.052865 00c80000 ################################################################
10156 20:00:47.053429
10157 20:00:47.784105 00d00000 ################################################################
10158 20:00:47.784630
10159 20:00:48.523049 00d80000 ################################################################
10160 20:00:48.523627
10161 20:00:49.245918 00e00000 ################################################################
10162 20:00:49.246441
10163 20:00:49.984222 00e80000 ################################################################
10164 20:00:49.984778
10165 20:00:50.721013 00f00000 ################################################################
10166 20:00:50.721560
10167 20:00:51.448781 00f80000 ################################################################
10168 20:00:51.449324
10169 20:00:52.184910 01000000 ################################################################
10170 20:00:52.185448
10171 20:00:52.909005 01080000 ################################################################
10172 20:00:52.909533
10173 20:00:53.652938 01100000 ################################################################
10174 20:00:53.653489
10175 20:00:54.401097 01180000 ################################################################
10176 20:00:54.401611
10177 20:00:55.135133 01200000 ################################################################
10178 20:00:55.135678
10179 20:00:55.874125 01280000 ################################################################
10180 20:00:55.874670
10181 20:00:56.610868 01300000 ################################################################
10182 20:00:56.611421
10183 20:00:57.353564 01380000 ################################################################
10184 20:00:57.354065
10185 20:00:58.091012 01400000 ################################################################
10186 20:00:58.091581
10187 20:00:58.841304 01480000 ################################################################
10188 20:00:58.841823
10189 20:00:59.578683 01500000 ################################################################
10190 20:00:59.579195
10191 20:01:00.327250 01580000 ################################################################
10192 20:01:00.327837
10193 20:01:01.071127 01600000 ################################################################
10194 20:01:01.071723
10195 20:01:01.808589 01680000 ################################################################
10196 20:01:01.809122
10197 20:01:02.538158 01700000 ################################################################
10198 20:01:02.538682
10199 20:01:03.280620 01780000 ################################################################
10200 20:01:03.281166
10201 20:01:04.021447 01800000 ################################################################
10202 20:01:04.022027
10203 20:01:04.765507 01880000 ################################################################
10204 20:01:04.766034
10205 20:01:05.521367 01900000 ################################################################
10206 20:01:05.521889
10207 20:01:06.259089 01980000 ################################################################
10208 20:01:06.259665
10209 20:01:07.010720 01a00000 ################################################################
10210 20:01:07.011252
10211 20:01:07.767418 01a80000 ################################################################
10212 20:01:07.767946
10213 20:01:08.510012 01b00000 ################################################################
10214 20:01:08.510514
10215 20:01:09.257531 01b80000 ################################################################
10216 20:01:09.258045
10217 20:01:10.008026 01c00000 ################################################################
10218 20:01:10.008532
10219 20:01:10.732294 01c80000 ################################################################
10220 20:01:10.732829
10221 20:01:11.476973 01d00000 ################################################################
10222 20:01:11.477520
10223 20:01:12.217033 01d80000 ################################################################
10224 20:01:12.217571
10225 20:01:12.962349 01e00000 ################################################################
10226 20:01:12.962894
10227 20:01:13.710043 01e80000 ################################################################
10228 20:01:13.710606
10229 20:01:14.459648 01f00000 ################################################################
10230 20:01:14.460231
10231 20:01:15.196444 01f80000 ################################################################
10232 20:01:15.196949
10233 20:01:15.934985 02000000 ################################################################
10234 20:01:15.935672
10235 20:01:16.693132 02080000 ################################################################
10236 20:01:16.693720
10237 20:01:17.447333 02100000 ################################################################
10238 20:01:17.447922
10239 20:01:18.205323 02180000 ################################################################
10240 20:01:18.205866
10241 20:01:18.972447 02200000 ################################################################
10242 20:01:18.973044
10243 20:01:19.715881 02280000 ################################################################
10244 20:01:19.716467
10245 20:01:20.451245 02300000 ################################################################
10246 20:01:20.451843
10247 20:01:21.204890 02380000 ################################################################
10248 20:01:21.205430
10249 20:01:21.957754 02400000 ################################################################
10250 20:01:21.958279
10251 20:01:22.707514 02480000 ################################################################
10252 20:01:22.708083
10253 20:01:23.478815 02500000 ################################################################
10254 20:01:23.479332
10255 20:01:24.231464 02580000 ################################################################
10256 20:01:24.232013
10257 20:01:24.975443 02600000 ################################################################
10258 20:01:24.975992
10259 20:01:25.719155 02680000 ################################################################
10260 20:01:25.719777
10261 20:01:26.468551 02700000 ################################################################
10262 20:01:26.469160
10263 20:01:27.206945 02780000 ################################################################
10264 20:01:27.207525
10265 20:01:27.952300 02800000 ################################################################
10266 20:01:27.952880
10267 20:01:28.689635 02880000 ################################################################
10268 20:01:28.690168
10269 20:01:29.438949 02900000 ################################################################
10270 20:01:29.439562
10271 20:01:30.179491 02980000 ################################################################
10272 20:01:30.180033
10273 20:01:30.934077 02a00000 ################################################################
10274 20:01:30.934598
10275 20:01:31.690032 02a80000 ################################################################
10276 20:01:31.690547
10277 20:01:32.435121 02b00000 ################################################################
10278 20:01:32.435670
10279 20:01:33.179936 02b80000 ################################################################
10280 20:01:33.180458
10281 20:01:33.923877 02c00000 ################################################################
10282 20:01:33.924387
10283 20:01:34.678758 02c80000 ################################################################
10284 20:01:34.679277
10285 20:01:35.427894 02d00000 ################################################################
10286 20:01:35.428434
10287 20:01:36.160201 02d80000 ################################################################
10288 20:01:36.160722
10289 20:01:36.889589 02e00000 ################################################################
10290 20:01:36.890148
10291 20:01:37.623735 02e80000 ################################################################
10292 20:01:37.624261
10293 20:01:38.360492 02f00000 ################################################################
10294 20:01:38.361007
10295 20:01:39.105329 02f80000 ################################################################
10296 20:01:39.105904
10297 20:01:39.849903 03000000 ################################################################
10298 20:01:39.850450
10299 20:01:40.608759 03080000 ################################################################
10300 20:01:40.609292
10301 20:01:41.370202 03100000 ################################################################
10302 20:01:41.370795
10303 20:01:42.115017 03180000 ################################################################
10304 20:01:42.115588
10305 20:01:42.855233 03200000 ################################################################
10306 20:01:42.855849
10307 20:01:43.578862 03280000 ################################################################
10308 20:01:43.579554
10309 20:01:44.332771 03300000 ################################################################
10310 20:01:44.333309
10311 20:01:45.075265 03380000 ################################################################
10312 20:01:45.075868
10313 20:01:45.823430 03400000 ################################################################
10314 20:01:45.823940
10315 20:01:46.576530 03480000 ################################################################
10316 20:01:46.577049
10317 20:01:47.335947 03500000 ################################################################
10318 20:01:47.336477
10319 20:01:48.074681 03580000 ################################################################
10320 20:01:48.075272
10321 20:01:48.825956 03600000 ################################################################
10322 20:01:48.826508
10323 20:01:49.569686 03680000 ################################################################
10324 20:01:49.570211
10325 20:01:50.313068 03700000 ################################################################
10326 20:01:50.313586
10327 20:01:50.903940 03780000 ################################################### done.
10328 20:01:50.904458
10329 20:01:50.907531 The bootfile was 58611090 bytes long.
10330 20:01:50.907951
10331 20:01:50.910502 Sending tftp read request... done.
10332 20:01:50.910916
10333 20:01:50.914640 Waiting for the transfer...
10334 20:01:50.915053
10335 20:01:50.915381 00000000 # done.
10336 20:01:50.915738
10337 20:01:50.921491 Command line loaded dynamically from TFTP file: 11899596/tftp-deploy-qe5iq69e/kernel/cmdline
10338 20:01:50.922014
10339 20:01:50.934530 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10340 20:01:50.935042
10341 20:01:50.937836 Loading FIT.
10342 20:01:50.938258
10343 20:01:50.941728 Image ramdisk-1 has 47514256 bytes.
10344 20:01:50.942252
10345 20:01:50.945650 Image fdt-1 has 47278 bytes.
10346 20:01:50.946171
10347 20:01:50.946603 Image kernel-1 has 11047522 bytes.
10348 20:01:50.948347
10349 20:01:50.954822 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10350 20:01:50.955330
10351 20:01:50.971547 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10352 20:01:50.974966
10353 20:01:50.978062 Choosing best match conf-1 for compat google,spherion-rev2.
10354 20:01:50.982611
10355 20:01:50.986725 Connected to device vid:did:rid of 1ae0:0028:00
10356 20:01:50.993973
10357 20:01:50.997383 tpm_get_response: command 0x17b, return code 0x0
10358 20:01:50.997906
10359 20:01:51.000054 ec_init: CrosEC protocol v3 supported (256, 248)
10360 20:01:51.004225
10361 20:01:51.007996 tpm_cleanup: add release locality here.
10362 20:01:51.008522
10363 20:01:51.008858 Shutting down all USB controllers.
10364 20:01:51.011241
10365 20:01:51.011707 Removing current net device
10366 20:01:51.012045
10367 20:01:51.018625 Exiting depthcharge with code 4 at timestamp: 119188616
10368 20:01:51.019162
10369 20:01:51.020802 LZMA decompressing kernel-1 to 0x821a6718
10370 20:01:51.021160
10371 20:01:51.023872 LZMA decompressing kernel-1 to 0x40000000
10372 20:01:52.412364
10373 20:01:52.412967 jumping to kernel
10374 20:01:52.415033 end: 2.2.4 bootloader-commands (duration 00:01:31) [common]
10375 20:01:52.415563 start: 2.2.5 auto-login-action (timeout 00:02:54) [common]
10376 20:01:52.415966 Setting prompt string to ['Linux version [0-9]']
10377 20:01:52.416325 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10378 20:01:52.416675 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10379 20:01:52.495140
10380 20:01:52.498519 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10381 20:01:52.501836 start: 2.2.5.1 login-action (timeout 00:02:54) [common]
10382 20:01:52.502293 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10383 20:01:52.502655 Setting prompt string to []
10384 20:01:52.503045 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10385 20:01:52.503440 Using line separator: #'\n'#
10386 20:01:52.503757 No login prompt set.
10387 20:01:52.504063 Parsing kernel messages
10388 20:01:52.504343 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10389 20:01:52.504860 [login-action] Waiting for messages, (timeout 00:02:54)
10390 20:01:52.521250 [ 0.000000] Linux version 6.1.59-cip8-rt4 (KernelCI@build-j84202-arm64-gcc-10-defconfig-arm64-chromebook-st8dj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023
10391 20:01:52.524613 [ 0.000000] random: crng init done
10392 20:01:52.530889 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10393 20:01:52.534265 [ 0.000000] efi: UEFI not found.
10394 20:01:52.541228 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10395 20:01:52.551080 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10396 20:01:52.561281 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10397 20:01:52.567977 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10398 20:01:52.574445 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10399 20:01:52.580653 [ 0.000000] printk: bootconsole [mtk8250] enabled
10400 20:01:52.587224 [ 0.000000] NUMA: No NUMA configuration found
10401 20:01:52.594185 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10402 20:01:52.600838 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10403 20:01:52.601358 [ 0.000000] Zone ranges:
10404 20:01:52.607534 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10405 20:01:52.611259 [ 0.000000] DMA32 empty
10406 20:01:52.616941 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10407 20:01:52.620621 [ 0.000000] Movable zone start for each node
10408 20:01:52.624267 [ 0.000000] Early memory node ranges
10409 20:01:52.630832 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10410 20:01:52.636809 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10411 20:01:52.643446 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10412 20:01:52.650273 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10413 20:01:52.657033 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10414 20:01:52.663477 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10415 20:01:52.719269 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10416 20:01:52.726176 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10417 20:01:52.732433 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10418 20:01:52.736095 [ 0.000000] psci: probing for conduit method from DT.
10419 20:01:52.742401 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10420 20:01:52.746057 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10421 20:01:52.752178 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10422 20:01:52.756038 [ 0.000000] psci: SMC Calling Convention v1.2
10423 20:01:52.762017 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10424 20:01:52.765987 [ 0.000000] Detected VIPT I-cache on CPU0
10425 20:01:52.772069 [ 0.000000] CPU features: detected: GIC system register CPU interface
10426 20:01:52.779258 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10427 20:01:52.785320 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10428 20:01:52.792313 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10429 20:01:52.798944 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10430 20:01:52.808528 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10431 20:01:52.811888 [ 0.000000] alternatives: applying boot alternatives
10432 20:01:52.818218 [ 0.000000] Fallback order for Node 0: 0
10433 20:01:52.825099 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10434 20:01:52.828832 [ 0.000000] Policy zone: Normal
10435 20:01:52.841998 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10436 20:01:52.851295 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10437 20:01:52.864155 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10438 20:01:52.874130 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10439 20:01:52.880027 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10440 20:01:52.883244 <6>[ 0.000000] software IO TLB: area num 8.
10441 20:01:52.939653 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10442 20:01:53.089345 <6>[ 0.000000] Memory: 7923024K/8385536K available (17984K kernel code, 4116K rwdata, 17476K rodata, 8448K init, 615K bss, 429744K reserved, 32768K cma-reserved)
10443 20:01:53.095966 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10444 20:01:53.101895 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10445 20:01:53.105605 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10446 20:01:53.112069 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10447 20:01:53.118736 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10448 20:01:53.121726 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10449 20:01:53.131858 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10450 20:01:53.138714 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10451 20:01:53.144942 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10452 20:01:53.151434 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10453 20:01:53.155231 <6>[ 0.000000] GICv3: 608 SPIs implemented
10454 20:01:53.158321 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10455 20:01:53.165142 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10456 20:01:53.168602 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10457 20:01:53.175104 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10458 20:01:53.188807 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10459 20:01:53.197910 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10460 20:01:53.208131 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10461 20:01:53.215460 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10462 20:01:53.229259 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10463 20:01:53.235548 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10464 20:01:53.242423 <6>[ 0.009178] Console: colour dummy device 80x25
10465 20:01:53.252151 <6>[ 0.013925] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10466 20:01:53.258415 <6>[ 0.024433] pid_max: default: 32768 minimum: 301
10467 20:01:53.261893 <6>[ 0.029304] LSM: Security Framework initializing
10468 20:01:53.268494 <6>[ 0.034241] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10469 20:01:53.278112 <6>[ 0.042056] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10470 20:01:53.288321 <6>[ 0.051517] cblist_init_generic: Setting adjustable number of callback queues.
10471 20:01:53.292236 <6>[ 0.058961] cblist_init_generic: Setting shift to 3 and lim to 1.
10472 20:01:53.301332 <6>[ 0.065298] cblist_init_generic: Setting adjustable number of callback queues.
10473 20:01:53.308407 <6>[ 0.072771] cblist_init_generic: Setting shift to 3 and lim to 1.
10474 20:01:53.311579 <6>[ 0.079250] rcu: Hierarchical SRCU implementation.
10475 20:01:53.317794 <6>[ 0.079251] rcu: Max phase no-delay instances is 1000.
10476 20:01:53.325086 <6>[ 0.079275] printk: bootconsole [mtk8250] printing thread started
10477 20:01:53.331285 <6>[ 0.097610] EFI services will not be available.
10478 20:01:53.335004 <6>[ 0.097813] smp: Bringing up secondary CPUs ...
10479 20:01:53.338259 <6>[ 0.098122] Detected VIPT I-cache on CPU1
10480 20:01:53.347767 <6>[ 0.098191] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10481 20:01:53.355110 <6>[ 0.098223] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10482 20:01:53.363863 <6>[ 0.126122] Detected VIPT I-cache on CPU2
10483 20:01:53.371215 <6>[ 0.126171] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10484 20:01:53.380989 <6>[ 0.126187] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10485 20:01:53.383510 <6>[ 0.126445] Detected VIPT I-cache on CPU3
10486 20:01:53.390558 <6>[ 0.126491] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10487 20:01:53.396903 <6>[ 0.126505] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10488 20:01:53.400039 <6>[ 0.126821] CPU features: detected: Spectre-v4
10489 20:01:53.407149 <6>[ 0.126827] CPU features: detected: Spectre-BHB
10490 20:01:53.410096 <6>[ 0.126832] Detected PIPT I-cache on CPU4
10491 20:01:53.416326 <6>[ 0.126890] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10492 20:01:53.423315 <6>[ 0.126907] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10493 20:01:53.430257 <6>[ 0.127198] Detected PIPT I-cache on CPU5
10494 20:01:53.436334 <6>[ 0.127258] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10495 20:01:53.443679 <6>[ 0.127274] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10496 20:01:53.446896 <6>[ 0.127548] Detected PIPT I-cache on CPU6
10497 20:01:53.456237 <6>[ 0.127612] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10498 20:01:53.462950 <6>[ 0.127628] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10499 20:01:53.466269 <6>[ 0.127920] Detected PIPT I-cache on CPU7
10500 20:01:53.472701 <6>[ 0.127984] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10501 20:01:53.479466 <6>[ 0.128000] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10502 20:01:53.482789 <6>[ 0.128046] smp: Brought up 1 node, 8 CPUs
10503 20:01:53.489056 <6>[ 0.128051] SMP: Total of 8 processors activated.
10504 20:01:53.496338 <6>[ 0.128054] CPU features: detected: 32-bit EL0 Support
10505 20:01:53.503033 <6>[ 0.128056] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10506 20:01:53.509073 <6>[ 0.128058] CPU features: detected: Common not Private translations
10507 20:01:53.515676 <6>[ 0.128060] CPU features: detected: CRC32 instructions
10508 20:01:53.522244 <6>[ 0.128062] CPU features: detected: RCpc load-acquire (LDAPR)
10509 20:01:53.526206 <6>[ 0.128064] CPU features: detected: LSE atomic instructions
10510 20:01:53.532473 <6>[ 0.128066] CPU features: detected: Privileged Access Never
10511 20:01:53.538666 <6>[ 0.128067] CPU features: detected: RAS Extension Support
10512 20:01:53.545673 <6>[ 0.128070] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10513 20:01:53.549178 <6>[ 0.128137] CPU: All CPU(s) started at EL2
10514 20:01:53.555411 <6>[ 0.128139] alternatives: applying system-wide alternatives
10515 20:01:53.583448 ��er�r�j��<6>[ 0.3<48622] printk: console [ttyS0] printing thread started
10516 20:01:53.587119 6>[ <6>[ 0.348675] printk: console [ttyS0] enabled
10517 20:01:53.593877 0.225631] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10518 20:01:53.602150 <6>[ 0.348680] printk: bootconsole [mtk8250] disabled
10519 20:01:53.608696 <6>[ 0.366052] printk: bootconsole [mtk8250] printing thread stopped
10520 20:01:53.612233 <6>[ 0.367386] SuperH (H)SCI(F) driver initialized
10521 20:01:53.618726 <6>[ 0.367867] msm_serial: driver initialized
10522 20:01:53.625420 <6>[ 0.372592] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10523 20:01:53.635160 <6>[ 0.372622] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10524 20:01:53.641761 <6>[ 0.372656] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10525 20:01:53.661963 <6>[ 0.372686] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10526 20:01:53.669912 <6>[ 0.372707] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10527 20:01:53.670429 <6>[ 0.372734] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10528 20:01:53.686136 <6>[ 0.372762] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10529 20:01:53.686721 <6>[ 0.372878] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10530 20:01:53.695373 <6>[ 0.372907] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10531 20:01:53.700009 <6>[ 0.384592] loop: module loaded
10532 20:01:53.704306 <6>[ 0.387275] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10533 20:01:53.711859 <4>[ 0.404169] mtk-pmic-keys: Failed to locate of_node [id: -1]
10534 20:01:53.715202 <6>[ 0.405121] megasas: 07.719.03.00-rc1
10535 20:01:53.721993 <6>[ 0.416875] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10536 20:01:53.725165 <6>[ 0.417149] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10537 20:01:53.731807 <6>[ 0.428794] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10538 20:01:53.744627 <6>[ 0.482072] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10539 20:01:55.485854 <6>[ 2.249601] Freeing initrd memory: 46400K
10540 20:01:55.492798 <6>[ 2.255645] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10541 20:01:55.495751 <6>[ 2.260258] tun: Universal TUN/TAP device driver, 1.6
10542 20:01:55.499622 <6>[ 2.261008] thunder_xcv, ver 1.0
10543 20:01:55.503120 <6>[ 2.261025] thunder_bgx, ver 1.0
10544 20:01:55.505941 <6>[ 2.261042] nicpf, ver 1.0
10545 20:01:55.512706 <6>[ 2.262140] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10546 20:01:55.519255 <6>[ 2.262143] hns3: Copyright (c) 2017 Huawei Corporation.
10547 20:01:55.522940 <6>[ 2.262168] hclge is initializing
10548 20:01:55.529123 <6>[ 2.262185] e1000: Intel(R) PRO/1000 Network Driver
10549 20:01:55.533060 <6>[ 2.262187] e1000: Copyright (c) 1999-2006 Intel Corporation.
10550 20:01:55.539571 <6>[ 2.262206] e1000e: Intel(R) PRO/1000 Network Driver
10551 20:01:55.546786 <6>[ 2.262208] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10552 20:01:55.550181 <6>[ 2.262223] igb: Intel(R) Gigabit Ethernet Network Driver
10553 20:01:55.557086 <6>[ 2.262225] igb: Copyright (c) 2007-2014 Intel Corporation.
10554 20:01:55.563855 <6>[ 2.262238] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10555 20:01:55.571009 <6>[ 2.262240] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10556 20:01:55.574272 <6>[ 2.262533] sky2: driver version 1.30
10557 20:01:55.580680 <6>[ 2.263606] VFIO - User Level meta-driver version: 0.3
10558 20:01:55.584242 <6>[ 2.266447] usbcore: registered new interface driver usb-storage
10559 20:01:55.590322 <6>[ 2.266626] usbcore: registered new device driver onboard-usb-hub
10560 20:01:55.597267 <6>[ 2.269360] mt6397-rtc mt6359-rtc: registered as rtc0
10561 20:01:55.607221 <6>[ 2.269512] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-28T20:01:55 UTC (1698523315)
10562 20:01:55.610544 <6>[ 2.270128] i2c_dev: i2c /dev entries driver
10563 20:01:55.617200 <6>[ 2.277283] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10564 20:01:55.623983 <6>[ 2.292296] cpu cpu0: EM: created perf domain
10565 20:01:55.627209 <6>[ 2.292605] cpu cpu4: EM: created perf domain
10566 20:01:55.633380 <6>[ 2.296024] sdhci: Secure Digital Host Controller Interface driver
10567 20:01:55.640103 <6>[ 2.296025] sdhci: Copyright(c) Pierre Ossman
10568 20:01:55.646486 <6>[ 2.296381] Synopsys Designware Multimedia Card Interface Driver
10569 20:01:55.650385 <6>[ 2.296773] sdhci-pltfm: SDHCI platform and OF driver helper
10570 20:01:55.653480 <6>[ 2.301347] mmc0: CQHCI version 5.10
10571 20:01:55.659977 <6>[ 2.301448] ledtrig-cpu: registered to indicate activity on CPUs
10572 20:01:55.666465 <6>[ 2.302164] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10573 20:01:55.672882 <6>[ 2.302440] usbcore: registered new interface driver usbhid
10574 20:01:55.676363 <6>[ 2.302441] usbhid: USB HID core driver
10575 20:01:55.686133 <6>[ 2.302553] spi_master spi0: will run message pump with realtime priority
10576 20:01:55.696125 <6>[ 2.331433] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10577 20:01:55.709621 <6>[ 2.333246] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10578 20:01:55.715811 <6>[ 2.335362] cros-ec-spi spi0.0: Chrome EC device registered
10579 20:01:55.725646 <6>[ 2.347666] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10580 20:01:55.732411 <6>[ 2.348635] NET: Registered PF_PACKET protocol family
10581 20:01:55.735527 <6>[ 2.348708] 9pnet: Installing 9P2000 support
10582 20:01:55.739105 <5>[ 2.348740] Key type dns_resolver registered
10583 20:01:55.745310 <6>[ 2.349036] registered taskstats version 1
10584 20:01:55.748760 <5>[ 2.349047] Loading compiled-in X.509 certificates
10585 20:01:55.758701 <4>[ 2.363612] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 20:01:55.772267 <4>[ 2.363718] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10587 20:01:55.779129 <3>[ 2.363723] debugfs: File 'uA_load' in directory '/' already present!
10588 20:01:55.785009 <3>[ 2.363729] debugfs: File 'min_uV' in directory '/' already present!
10589 20:01:55.791845 <3>[ 2.363731] debugfs: File 'max_uV' in directory '/' already present!
10590 20:01:55.798366 <3>[ 2.363732] debugfs: File 'constraint_flags' in directory '/' already present!
10591 20:01:55.805256 <3>[ 2.364906] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10592 20:01:55.811474 <6>[ 2.368201] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10593 20:01:55.818194 <6>[ 2.368652] xhci-mtk 11200000.usb: xHCI Host Controller
10594 20:01:55.825091 <6>[ 2.368681] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10595 20:01:55.835038 <6>[ 2.368953] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10596 20:01:55.841932 <6>[ 2.369019] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10597 20:01:55.848223 <6>[ 2.369194] xhci-mtk 11200000.usb: xHCI Host Controller
10598 20:01:55.854871 <6>[ 2.369209] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10599 20:01:55.861518 <6>[ 2.369222] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10600 20:01:55.865137 <6>[ 2.369863] hub 1-0:1.0: USB hub found
10601 20:01:55.871796 <6>[ 2.369898] hub 1-0:1.0: 1 port detected
10602 20:01:55.877992 <6>[ 2.370168] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10603 20:01:55.881259 <6>[ 2.370583] hub 2-0:1.0: USB hub found
10604 20:01:55.887685 <6>[ 2.370602] hub 2-0:1.0: 1 port detected
10605 20:01:55.890992 <6>[ 2.375191] mtk-msdc 11f70000.mmc: Got CD GPIO
10606 20:01:55.897705 <6>[ 2.392036] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10607 20:01:55.907660 <6>[ 2.392045] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10608 20:01:55.917331 <4>[ 2.392254] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10609 20:01:55.924205 <6>[ 2.392985] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10610 20:01:55.930781 <6>[ 2.392990] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10611 20:01:55.940794 <6>[ 2.393123] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10612 20:01:55.947278 <6>[ 2.393140] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10613 20:01:55.953921 <6>[ 2.393145] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10614 20:01:55.963676 <6>[ 2.393152] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10615 20:01:55.973865 <6>[ 2.395056] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10616 20:01:55.980334 <6>[ 2.395077] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10617 20:01:55.990509 <6>[ 2.395086] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10618 20:01:55.997016 <6>[ 2.395095] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10619 20:01:56.006980 <6>[ 2.395104] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10620 20:01:56.013062 <6>[ 2.395112] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10621 20:01:56.023368 <6>[ 2.395121] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10622 20:01:56.029924 <6>[ 2.395130] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10623 20:01:56.040071 <6>[ 2.395138] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10624 20:01:56.046389 <6>[ 2.395146] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10625 20:01:56.055974 <6>[ 2.395155] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10626 20:01:56.065941 <6>[ 2.395163] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10627 20:01:56.073054 <6>[ 2.395172] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10628 20:01:56.082706 <6>[ 2.395180] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10629 20:01:56.088796 <6>[ 2.395189] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10630 20:01:56.096034 <6>[ 2.395815] mmc0: Command Queue Engine enabled
10631 20:01:56.102515 <6>[ 2.395824] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10632 20:01:56.105767 <6>[ 2.395943] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10633 20:01:56.112228 <6>[ 2.396476] mmcblk0: mmc0:0001 DA4128 116 GiB
10634 20:01:56.119109 <6>[ 2.398004] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10635 20:01:56.125244 <6>[ 2.399059] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10636 20:01:56.131956 <6>[ 2.400080] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10637 20:01:56.138610 <6>[ 2.400083] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10638 20:01:56.145161 <6>[ 2.401135] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10639 20:01:56.149123 <6>[ 2.401147] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10640 20:01:56.155315 <6>[ 2.401800] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10641 20:01:56.165205 <6>[ 2.401841] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10642 20:01:56.172180 <6>[ 2.401859] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10643 20:01:56.181510 <6>[ 2.401868] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10644 20:01:56.191713 <6>[ 2.401875] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10645 20:01:56.201464 <6>[ 2.401882] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10646 20:01:56.211589 <6>[ 2.401892] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10647 20:01:56.220834 <6>[ 2.401901] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10648 20:01:56.227859 <6>[ 2.401908] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10649 20:01:56.237424 <6>[ 2.401914] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10650 20:01:56.248258 <6>[ 2.401921] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10651 20:01:56.258092 <6>[ 2.401927] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10652 20:01:56.264304 <6>[ 2.402065] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10653 20:01:56.273879 <6>[ 2.402380] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10654 20:01:56.281151 <6>[ 2.757857] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10655 20:01:56.283824 <6>[ 2.788706] hub 2-1:1.0: USB hub found
10656 20:01:56.287280 <6>[ 2.789063] hub 2-1:1.0: 3 ports detected
10657 20:01:56.293911 <6>[ 2.909561] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10658 20:01:56.300121 <6>[ 3.062527] hub 1-1:1.0: USB hub found
10659 20:01:56.303635 <6>[ 3.062921] hub 1-1:1.0: 4 ports detected
10660 20:01:56.377406 <6>[ 3.137973] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10661 20:01:56.613416 <6>[ 3.373775] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10662 20:01:56.738312 <6>[ 3.501770] hub 1-1.4:1.0: USB hub found
10663 20:01:56.741823 <6>[ 3.502221] hub 1-1.4:1.0: 2 ports detected
10664 20:01:57.028929 <6>[ 3.789772] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10665 20:01:57.213420 <6>[ 3.973773] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10666 20:02:07.921427 <6>[ 14.690771] ALSA device list:
10667 20:02:07.928719 <6>[ 14.690793] No soundcards found.
10668 20:02:07.931222 <6>[ 14.695232] Freeing unused kernel memory: 8448K
10669 20:02:07.934429 <6>[ 14.695376] Run /init as init process
10670 20:02:07.972731 <6>[ 14.737550] NET: Registered PF_INET6 protocol family
10671 20:02:07.975720 <6>[ 14.738714] Segment Routing with IPv6
10672 20:02:07.979599
10673 20:02:07.986396 Welcome to [1mDebian GNU/Linu<6>[ 14.738728] In-situ OAM (IOAM) with IPv6
10674 20:02:08.009006 x 11 (bullseye)<30>[ 14.751020] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10675 20:02:08.009544 [0m!
10676 20:02:08.009876
10677 20:02:08.015965 <30>[ 14.751489] systemd[1]: Detected architecture arm64.
10678 20:02:08.028425 <30>[ 14.793847] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10679 20:02:08.163845 <30>[ 14.929454] systemd[1]: Queued start job for default target Graphical Interface.
10680 20:02:08.209348 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.974516] systemd[1]: Created slice system-getty.slice.
10681 20:02:08.212782 m-getty.slice[0m.
10682 20:02:08.233942 [[0;32m OK [0m] Created slic<30>[ 14.999306] systemd[1]: Created slice system-modprobe.slice.
10683 20:02:08.237041 e [0;1;39msystem-modprobe.slice[0m.
10684 20:02:08.260275 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.022124] systemd[1]: Created slice system-serial\x2dgetty.slice.
10685 20:02:08.263358 m-serial\x2dgetty.slice[0m.
10686 20:02:08.281876 [[0;32m OK [0m] Created slic<30>[ 15.046833] systemd[1]: Created slice User and Session Slice.
10687 20:02:08.284844 e [0;1;39mUser and Session Slice[0m.
10688 20:02:08.308393 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 15.070479] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10689 20:02:08.312158 ssword …ts to Console Directory Watch[0m.
10690 20:02:08.336158 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 15.097897] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10691 20:02:08.338982 sword R…uests to Wall Directory Watch[0m.
10692 20:02:08.363255 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 15.121792] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10693 20:02:08.373472 l Encrypted Volu<30>[ 15.121973] systemd[1]: Reached target Local Encrypted Volumes.
10694 20:02:08.374006 mes[0m.
10695 20:02:08.392837 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 15.158265] systemd[1]: Reached target Paths.
10696 20:02:08.393362 s[0m.
10697 20:02:08.415377 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 15.177727] systemd[1]: Reached target Remote File Systems.
10698 20:02:08.415929 te File Systems[0m.
10699 20:02:08.432335 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 15.197716] systemd[1]: Reached target Slices.
10700 20:02:08.432861 es[0m.
10701 20:02:08.452597 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 15.217730] systemd[1]: Reached target Swap.
10702 20:02:08.453126 [0m.
10703 20:02:08.476317 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 15.238193] systemd[1]: Listening on initctl Compatibility Named Pipe.
10704 20:02:08.479669 l Compatibility Named Pipe[0m.
10705 20:02:08.498036 [[0;32m OK [0m] Listening on<30>[ 15.263150] systemd[1]: Listening on Journal Audit Socket.
10706 20:02:08.500999 [0;1;39mJournal Audit Socket[0m.
10707 20:02:08.521454 [[0;32m OK [0m] Listening on<30>[ 15.286834] systemd[1]: Listening on Journal Socket (/dev/log).
10708 20:02:08.524907 [0;1;39mJournal Socket (/dev/log)[0m.
10709 20:02:08.546130 [[0;32m OK [0m] Listening on<30>[ 15.310936] systemd[1]: Listening on Journal Socket.
10710 20:02:08.548996 [0;1;39mJournal Socket[0m.
10711 20:02:08.568129 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 15.330394] systemd[1]: Listening on Network Service Netlink Socket.
10712 20:02:08.571591 k Service Netlink Socket[0m.
10713 20:02:08.589949 [[0;32m OK [0m] Listening on<30>[ 15.354909] systemd[1]: Listening on udev Control Socket.
10714 20:02:08.592661 [0;1;39mudev Control Socket[0m.
10715 20:02:08.613549 [[0;32m OK [0m] Listening on<30>[ 15.378754] systemd[1]: Listening on udev Kernel Socket.
10716 20:02:08.616965 [0;1;39mudev Kernel Socket[0m.
10717 20:02:08.663634 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.425828] systemd[1]: Mounting Huge Pages File System...
10718 20:02:08.664151 m[0m...
10719 20:02:08.683336 Mountin<30>[ 15.448808] systemd[1]: Mounting POSIX Message Queue File System...
10720 20:02:08.686965 g [0;1;39mPOSIX Message Queue File System[0m...
10721 20:02:08.705073 <30>[ 15.473379] systemd[1]: Mounting Kernel Debug File System...
10722 20:02:08.711239 Mounting [0;1;39mKernel Debug File System[0m...
10723 20:02:08.732169 <30>[ 15.494148] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10724 20:02:08.742000 <30>[ 15.498139] systemd[1]: Starting Create list of static device nodes for the current kernel...
10725 20:02:08.748680 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10726 20:02:08.775359 Starting [0;1;39mLoad Kernel Module co<30>[ 15.537834] systemd[1]: Starting Load Kernel Module configfs...
10727 20:02:08.775912 nfigfs[0m...
10728 20:02:08.799513 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.561895] systemd[1]: Starting Load Kernel Module drm...
10729 20:02:08.800021 m[0m...
10730 20:02:08.819776 <30>[ 15.582076] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10731 20:02:08.856310 Starting [0;1;39mJournal Service[0m..<30>[ 15.622149] systemd[1]: Starting Journal Service...
10732 20:02:08.856920 .
10733 20:02:08.879354 Startin<30>[ 15.644788] systemd[1]: Starting Load Kernel Modules...
10734 20:02:08.882155 g [0;1;39mLoad Kernel Modules[0m...
10735 20:02:08.936396 Starting [0;1;39mRemount Root and Kern<30>[ 15.698486] systemd[1]: Starting Remount Root and Kernel File Systems...
10736 20:02:08.939531 el File Systems[0m...
10737 20:02:08.959151 Starting [0;1;39mColdp<30>[ 15.724097] systemd[1]: Starting Coldplug All udev Devices...
10738 20:02:08.962125 lug All udev Devices[0m...
10739 20:02:08.988866 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 15.753913] systemd[1]: Started Journal Service.
10740 20:02:08.991735 vice[0m.
10741 20:02:09.007269 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10742 20:02:09.026378 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10743 20:02:09.041996 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10744 20:02:09.062243 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10745 20:02:09.078448 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10746 20:02:09.095505 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10747 20:02:09.103063 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10748 20:02:09.123707 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10749 20:02:09.136667 See 'systemctl status systemd-remount-fs.service' for details.
10750 20:02:09.179050 Mounting [0;1;39mKernel Configuration File System[0m...
10751 20:02:09.204491 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10752 20:02:09.219773 <46>[ 15.984224] systemd-journald[188]: Received client request to flush runtime journal.
10753 20:02:09.233653 Starting [0;1;39mLoad/Save Random Seed[0m...
10754 20:02:09.257398 Starting [0;1;39mApply Kernel Variables[0m...
10755 20:02:09.281709 Starting [0;1;39mCreate System Users[0m...
10756 20:02:09.306507 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10757 20:02:09.321613 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10758 20:02:09.341923 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10759 20:02:09.354714 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10760 20:02:09.370601 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10761 20:02:09.386090 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10762 20:02:09.425040 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10763 20:02:09.449421 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10764 20:02:09.460774 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10765 20:02:09.476507 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10766 20:02:09.513084 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10767 20:02:09.540767 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10768 20:02:09.567449 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10769 20:02:09.588558 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10770 20:02:09.657069 Starting [0;1;39mNetwork Service[0m...
10771 20:02:09.682445 Starting [0;1;39mNetwork Time Synchronization[0m...
10772 20:02:09.709815 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10773 20:02:09.751298 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10774 20:02:09.767912 <6>[ 16.533194] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10775 20:02:09.774788 <3>[ 16.534491] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 20:02:09.784393 [[0;32m OK [<3>[ 16.534672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10777 20:02:09.794558 0m] Found device<3>[ 16.534683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10778 20:02:09.803995 [0;1;39m/dev/t<3>[ 16.550233] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10779 20:02:09.804505 tyS0[0m.
10780 20:02:09.814252 <3>[ 16.550278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10781 20:02:09.820759 <3>[ 16.550284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 20:02:09.827521 <3>[ 16.550295] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 20:02:09.837505 <3>[ 16.550300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 20:02:09.844332 <3>[ 16.550986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10785 20:02:09.854121 <3>[ 16.551105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10786 20:02:09.863539 [[0;32m OK [<3>[ 16.551110] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 20:02:09.873778 0m] Started [0;<3>[ 16.551114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10788 20:02:09.880406 <3>[ 16.553966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 20:02:09.886969 <3>[ 16.553999] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 20:02:09.896913 <3>[ 16.554010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 20:02:09.903658 <3>[ 16.554026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 20:02:09.913661 1;39mNetwork Tim<3>[ 16.554033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 20:02:09.920204 <6>[ 16.559627] remoteproc remoteproc0: scp is available
10794 20:02:09.923189 <6>[ 16.559742] remoteproc remoteproc0: powering up scp
10795 20:02:09.933028 <6>[ 16.559749] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10796 20:02:09.939785 e Synchronizatio<6>[ 16.559778] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10797 20:02:09.946710 <3>[ 16.559766] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 20:02:09.950033 n[0m.
10799 20:02:09.956071 <6>[ 16.645615] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10800 20:02:09.966594 <6>[ 16.645645] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10801 20:02:09.973000 <6>[ 16.645651] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10802 20:02:09.980199 <4>[ 16.681400] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10803 20:02:09.986877 <4>[ 16.681641] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10804 20:02:09.994031 <6>[ 16.685041] mc: Linux media interface: v0.10
10805 20:02:10.000503 <6>[ 16.686717] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10806 20:02:10.010343 <6>[ 16.686731] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10807 20:02:10.013670 <6>[ 16.686736] remoteproc remoteproc0: remote processor scp is now up
10808 20:02:10.024083 <6>[ 16.688936] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10809 20:02:10.030745 [[0;32m OK [<6>[ 16.729641] videodev: Linux video capture interface: v2.00
10810 20:02:10.037678 <4>[ 16.740141] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10811 20:02:10.044004 <4>[ 16.740141] Fallback method does not support PEC.
10812 20:02:10.050993 <6>[ 16.747788] usbcore: registered new interface driver r8152
10813 20:02:10.057917 <3>[ 16.755437] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10814 20:02:10.065067 0m] Finished [0<6>[ 16.769366] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10815 20:02:10.074887 ;1;39mUpdate UTM<6>[ 16.769378] pci_bus 0000:00: root bus resource [bus 00-ff]
10816 20:02:10.081453 P about System B<6>[ 16.769383] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10817 20:02:10.091592 <6>[ 16.769385] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10818 20:02:10.098343 <6>[ 16.769417] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10819 20:02:10.105101 <6>[ 16.769433] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10820 20:02:10.108661 <6>[ 16.769523] pci 0000:00:00.0: supports D1 D2
10821 20:02:10.119178 oot/Shutdown[0m<6>[ 16.769526] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10822 20:02:10.125791 <6>[ 16.775755] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10823 20:02:10.132075 <6>[ 16.780287] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10824 20:02:10.138761 <6>[ 16.780335] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10825 20:02:10.149553 <6>[ 16.780358] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10826 20:02:10.156354 <6>[ 16.780376] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10827 20:02:10.156804 .
10828 20:02:10.159839 <6>[ 16.780533] pci 0000:01:00.0: supports D1 D2
10829 20:02:10.166717 <6>[ 16.780540] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10830 20:02:10.176903 <6>[ 16.792987] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10831 20:02:10.183937 <3>[ 16.800540] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10832 20:02:10.193997 <3>[ 16.801363] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10833 20:02:10.201396 <6>[ 16.807665] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10834 20:02:10.208458 <6>[ 16.807797] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10835 20:02:10.215588 <6>[ 16.807804] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10836 20:02:10.225117 <6>[ 16.807827] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10837 20:02:10.232561 <6>[ 16.807843] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10838 20:02:10.238885 <6>[ 16.807861] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10839 20:02:10.246186 <6>[ 16.807877] pci 0000:00:00.0: PCI bridge to [bus 01]
10840 20:02:10.253188 <6>[ 16.807888] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10841 20:02:10.259296 <6>[ 16.811241] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10842 20:02:10.270169 <6>[ 16.822064] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10843 20:02:10.279908 [[0;32m OK [<6>[ 16.826052] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10844 20:02:10.287056 0m] Created slic<6>[ 16.826228] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10845 20:02:10.297694 e [0;1;39msyste<3>[ 16.836200] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10846 20:02:10.307345 m-systemd\x2dbac<4>[ 16.855344] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10847 20:02:10.318709 klight.slice[0m<4>[ 16.855359] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10848 20:02:10.319258 .
10849 20:02:10.324595 <6>[ 16.868736] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10850 20:02:10.331996 <6>[ 16.869548] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10851 20:02:10.338639 <6>[ 16.872488] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10852 20:02:10.341749 <6>[ 16.873551] Bluetooth: Core ver 2.22
10853 20:02:10.348189 <6>[ 16.873627] NET: Registered PF_BLUETOOTH protocol family
10854 20:02:10.355133 <6>[ 16.873629] Bluetooth: HCI device and connection manager initialized
10855 20:02:10.362237 <6>[ 16.873648] Bluetooth: HCI socket layer initialized
10856 20:02:10.364744 <6>[ 16.873653] Bluetooth: L2CAP socket layer initialized
10857 20:02:10.371608 <6>[ 16.873668] Bluetooth: SCO socket layer initialized
10858 20:02:10.378184 <6>[ 16.873713] usbcore: registered new interface driver cdc_ether
10859 20:02:10.384408 <6>[ 16.875642] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10860 20:02:10.391277 <6>[ 16.884606] usbcore: registered new interface driver r8153_ecm
10861 20:02:10.401260 <3>[ 16.894355] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10862 20:02:10.407514 <5>[ 16.895486] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10863 20:02:10.414345 <6>[ 16.902336] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10864 20:02:10.427527 <6>[ 16.903694] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10865 20:02:10.434875 <6>[ 16.903823] usbcore: registered new interface driver uvcvideo
10866 20:02:10.437665 <6>[ 16.905665] r8152 2-1.3:1.0 eth0: v1.12.13
10867 20:02:10.444341 <5>[ 16.912449] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10868 20:02:10.453932 <4>[ 16.912588] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10869 20:02:10.457449 <6>[ 16.912600] cfg80211: failed to load regulatory.db
10870 20:02:10.464108 <6>[ 16.914570] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10871 20:02:10.474481 <3>[ 16.932904] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 20:02:10.480722 <3>[ 16.933869] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10873 20:02:10.487549 <6>[ 16.942082] usbcore: registered new interface driver btusb
10874 20:02:10.494099 <6>[ 16.942301] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10875 20:02:10.503591 <4>[ 16.943266] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10876 20:02:10.510234 <3>[ 16.943293] Bluetooth: hci0: Failed to load firmware file (-2)
10877 20:02:10.517276 <3>[ 16.943298] Bluetooth: hci0: Failed to set up firmware (-2)
10878 20:02:10.526690 <4>[ 16.943306] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10879 20:02:10.536599 <3>[ 16.957776] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 20:02:10.543367 <3>[ 16.981578] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 20:02:10.553517 <3>[ 17.005926] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 20:02:10.560106 <6>[ 17.171941] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10883 20:02:10.566664 <6>[ 17.172065] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10884 20:02:10.573674 <6>[ 17.189605] mt7921e 0000:01:00.0: ASIC revision: 79610010
10885 20:02:10.583282 <4>[ 17.284456] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10886 20:02:10.589751 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10887 20:02:10.605005 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10888 20:02:10.631160 <4>[ 17.391492] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10889 20:02:10.637485 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10890 20:02:10.659964 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10891 20:02:10.708960 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10892 20:02:10.739063 <4>[ 17.499925] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10893 20:02:10.745709 Starting [0;1;39mNetwork Name Resolution[0m...
10894 20:02:10.766437 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10895 20:02:10.798368 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10896 20:02:10.814066 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10897 20:02:10.831817 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10898 20:02:10.851139 <4>[ 17.611884] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10899 20:02:10.857360 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10900 20:02:10.877017 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10901 20:02:10.888939 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10902 20:02:10.905328 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10903 20:02:10.959548 <4>[ 17.719915] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10904 20:02:10.966167 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10905 20:02:10.997270 Starting [0;1;39mUser Login Management[0m...
10906 20:02:11.017882 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10907 20:02:11.034540 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10908 20:02:11.052507 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10909 20:02:11.067041 <4>[ 17.828665] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10910 20:02:11.074173 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10911 20:02:11.092414 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10912 20:02:11.137615 Starting [0;1;39mPermit User Sessions[0m...
10913 20:02:11.158596 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10914 20:02:11.177254 <4>[ 17.936370] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10915 20:02:11.183999 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10916 20:02:11.234065 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10917 20:02:11.252376 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10918 20:02:11.274531 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10919 20:02:11.287096 <4>[ 18.043849] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10920 20:02:11.293719 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10921 20:02:11.309891 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10922 20:02:11.357486 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10923 20:02:11.393996 <4>[ 18.152434] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10924 20:02:11.403800 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10925 20:02:11.447489
10926 20:02:11.448004
10927 20:02:11.450912 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10928 20:02:11.451463
10929 20:02:11.454391 debian-bullseye-arm64 login: root (automatic login)
10930 20:02:11.454905
10931 20:02:11.455240
10932 20:02:11.484017 Linux debian-bullseye-arm64 6.1.59-cip8-rt4 #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023 aarch64
10933 20:02:11.484535
10934 20:02:11.490695 The programs included with the Debian GNU/Linux system are free software;
10935 20:02:11.503838 th<4>[ 18.261196] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10936 20:02:11.507056 e exact distribution terms for each program are described in the
10937 20:02:11.513999 individual files in /usr/share/doc/*/copyright.
10938 20:02:11.514536
10939 20:02:11.520141 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10940 20:02:11.520644 permitted by applicable law.
10941 20:02:11.521898 Matched prompt #10: / #
10943 20:02:11.522867 Setting prompt string to ['/ #']
10944 20:02:11.523290 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10946 20:02:11.524313 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10947 20:02:11.524791 start: 2.2.6 expect-shell-connection (timeout 00:02:35) [common]
10948 20:02:11.525138 Setting prompt string to ['/ #']
10949 20:02:11.525443 Forcing a shell prompt, looking for ['/ #']
10951 20:02:11.576239 / #
10952 20:02:11.576842 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10953 20:02:11.577240 Waiting using forced prompt support (timeout 00:02:30)
10954 20:02:11.583315
10955 20:02:11.584228 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10956 20:02:11.584724 start: 2.2.7 export-device-env (timeout 00:02:35) [common]
10957 20:02:11.585204 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10958 20:02:11.585630 end: 2.2 depthcharge-retry (duration 00:02:25) [common]
10959 20:02:11.586051 end: 2 depthcharge-action (duration 00:02:25) [common]
10960 20:02:11.586484 start: 3 lava-test-retry (timeout 00:05:00) [common]
10961 20:02:11.587031 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10962 20:02:11.587445 Using namespace: common
10964 20:02:11.688566 / # #
10965 20:02:11.689181 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10966 20:02:11.689739 <3>[ 18.369687] mt7921e 0000:01:00.0: hardware init failed
10967 20:02:11.695307 #
10968 20:02:11.696182 Using /lava-11899596
10970 20:02:11.797355 / # export SHELL=/bin/sh
10971 20:02:11.804153 export SHELL=/bin/sh
10973 20:02:11.905875 / # . /lava-11899596/environment
10974 20:02:11.906811 <6>[ 18.597201] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
10975 20:02:11.907250 <6>[ 18.607077] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10976 20:02:11.912617 . /lava-11899596/environment
10978 20:02:12.014359 / # /lava-11899596/bin/lava-test-runner /lava-11899596/0
10979 20:02:12.014970 Test shell timeout: 10s (minimum of the action and connection timeout)
10980 20:02:12.021002 /lava-11899596/bin/lava-test-runner /lava-11899596/0
10981 20:02:12.039378 + export TESTRUN_ID=0_cros-ec
10982 20:02:12.042173 + cd /lava-11899596/0/tests/0_cros-ec
10983 20:02:12.048979 + cat uuid<8>[ 18.813988] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11899596_1.5.2.3.1>
10984 20:02:12.049769 Received signal: <STARTRUN> 0_cros-ec 11899596_1.5.2.3.1
10985 20:02:12.050146 Starting test lava.0_cros-ec (11899596_1.5.2.3.1)
10986 20:02:12.050556 Skipping test definition patterns.
10987 20:02:12.052589
10988 20:02:12.053097 + UUID=11899596_1.5.2.3.1
10989 20:02:12.055950 + set +x
10990 20:02:12.058617 + python3 -m cros.runners.lava_runner -v
10991 20:02:12.411052 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
10992 20:02:12.417567 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
10993 20:02:12.421315
10994 20:02:12.427994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
10995 20:02:12.428852 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10997 20:02:12.434020 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
10998 20:02:12.440800 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
10999 20:02:12.444091
11000 20:02:12.447824 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8
11001 20:02:12.448316 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_accel_iio_data_is_<8', 'result': 'unknown'}
11002 20:02:12.454104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8>[ 19.220353] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11899596_1.5.2.3.1>
11003 20:02:12.454885 Received signal: <ENDRUN> 0_cros-ec 11899596_1.5.2.3.1
11004 20:02:12.455342 Ending use of test pattern.
11005 20:02:12.455721 Ending test lava.0_cros-ec (11899596_1.5.2.3.1), duration 0.41
11007 20:02:12.457327 valid RESULT=skip>
11008 20:02:12.461396 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11009 20:02:12.467215 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11010 20:02:12.467741
11011 20:02:12.474180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11012 20:02:12.475039 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11014 20:02:12.480816 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11015 20:02:12.487204 Checks the standard ABI for the main Embedded Controller. ... ok
11016 20:02:12.487665
11017 20:02:12.490553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11018 20:02:12.491410 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11020 20:02:12.496829 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11021 20:02:12.503845 Checks the main Embedded controller character device. ... ok
11022 20:02:12.504262
11023 20:02:12.507206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11024 20:02:12.508021 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11026 20:02:12.513449 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11027 20:02:12.520529 Checks basic comunication with the main Embedded controller. ... ok
11028 20:02:12.521041
11029 20:02:12.526996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11030 20:02:12.527827 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11032 20:02:12.530904 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11033 20:02:12.536732 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11034 20:02:12.540070
11035 20:02:12.543505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11036 20:02:12.544308 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11038 20:02:12.550479 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11039 20:02:12.556950 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11040 20:02:12.557487
11041 20:02:12.563551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11042 20:02:12.564333 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11044 20:02:12.569727 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11045 20:02:12.576435 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11046 20:02:12.576871
11047 20:02:12.582742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11048 20:02:12.583483 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11050 20:02:12.586343 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11051 20:02:12.596349 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11052 20:02:12.596878
11053 20:02:12.599704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11054 20:02:12.600379 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11056 20:02:12.606033 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11057 20:02:12.615983 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11058 20:02:12.616481
11059 20:02:12.619351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11060 20:02:12.620177 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11062 20:02:12.625767 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11063 20:02:12.632694 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11064 20:02:12.633207
11065 20:02:12.638933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11066 20:02:12.639720 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11068 20:02:12.642690 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11069 20:02:12.652835 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11070 20:02:12.653353
11071 20:02:12.659310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11072 20:02:12.660027 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11074 20:02:12.666043 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11075 20:02:12.673132 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11076 20:02:12.673647
11077 20:02:12.678721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11078 20:02:12.679518 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11080 20:02:12.685069 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11081 20:02:12.691799 Check the cros battery ABI. ... skipped 'No BAT found'
11082 20:02:12.692416
11083 20:02:12.699044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11084 20:02:12.699872 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11086 20:02:12.705286 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11087 20:02:12.711503 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11088 20:02:12.712011
11089 20:02:12.718888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11090 20:02:12.719918 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11092 20:02:12.721687 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11093 20:02:12.728026 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11094 20:02:12.728444
11095 20:02:12.735297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11096 20:02:12.736136 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11098 20:02:12.741425 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11099 20:02:12.748217 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11100 20:02:12.748637
11101 20:02:12.754854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11102 20:02:12.755423
11103 20:02:12.756043 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11105 20:02:12.761116 ----------------------------------------------------------------------
11106 20:02:12.764786 Ran 18 tests in 0.006s
11107 20:02:12.765307
11108 20:02:12.765728 OK (skipped=15)
11109 20:02:12.767824 + set +x
11110 20:02:12.768348 <LAVA_TEST_RUNNER EXIT>
11111 20:02:12.768959 ok: lava_test_shell seems to have completed
11112 20:02:12.769826 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11113 20:02:12.770299 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11114 20:02:12.770724 end: 3 lava-test-retry (duration 00:00:01) [common]
11115 20:02:12.771162 start: 4 finalize (timeout 00:07:13) [common]
11116 20:02:12.771664 start: 4.1 power-off (timeout 00:00:30) [common]
11117 20:02:12.772423 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11118 20:02:12.895909 >> Command sent successfully.
11119 20:02:12.900820 Returned 0 in 0 seconds
11120 20:02:13.001793 end: 4.1 power-off (duration 00:00:00) [common]
11122 20:02:13.003508 start: 4.2 read-feedback (timeout 00:07:13) [common]
11123 20:02:13.004778 Listened to connection for namespace 'common' for up to 1s
11124 20:02:14.005546 Finalising connection for namespace 'common'
11125 20:02:14.006202 Disconnecting from shell: Finalise
11126 20:02:14.006606 / #
11127 20:02:14.107762 end: 4.2 read-feedback (duration 00:00:01) [common]
11128 20:02:14.108443 end: 4 finalize (duration 00:00:01) [common]
11129 20:02:14.109021 Cleaning after the job
11130 20:02:14.109493 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/ramdisk
11131 20:02:14.118407 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/kernel
11132 20:02:14.126688 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/dtb
11133 20:02:14.126852 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899596/tftp-deploy-qe5iq69e/modules
11134 20:02:14.133895 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11899596
11135 20:02:14.251311 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11899596
11136 20:02:14.251667 Job finished correctly