Boot log: mt8192-asurada-spherion-r0
- Warnings: 0
- Kernel Warnings: 0
- Kernel Errors: 0
- Errors: 2
- Boot result: UNKNOWN
1 19:51:27.501777 lava-dispatcher, installed at version: 2023.08
2 19:51:27.501969 start: 0 validate
3 19:51:27.502099 Start time: 2023-10-28 19:51:27.502092+00:00 (UTC)
4 19:51:27.502219 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:51:27.502343 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 19:51:27.764368 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:51:27.765106 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:51:38.539614 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:51:38.540295 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:51:38.813184 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:51:38.813893 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:51:39.476713 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:51:39.477718 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:51:41.988183 validate duration: 14.49
16 19:51:41.988436 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:51:41.988529 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:51:41.988618 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:51:41.988742 Not decompressing ramdisk as can be used compressed.
20 19:51:41.988826 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 19:51:41.988888 saving as /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/ramdisk/initrd.cpio.gz
22 19:51:41.988956 total size: 4665395 (4 MB)
23 19:51:42.255286 progress 0 % (0 MB)
24 19:51:42.257567 progress 5 % (0 MB)
25 19:51:42.259583 progress 10 % (0 MB)
26 19:51:42.261587 progress 15 % (0 MB)
27 19:51:42.263509 progress 20 % (0 MB)
28 19:51:42.265439 progress 25 % (1 MB)
29 19:51:42.267464 progress 30 % (1 MB)
30 19:51:42.269322 progress 35 % (1 MB)
31 19:51:42.271341 progress 40 % (1 MB)
32 19:51:42.273485 progress 45 % (2 MB)
33 19:51:42.275413 progress 50 % (2 MB)
34 19:51:42.277444 progress 55 % (2 MB)
35 19:51:42.279382 progress 60 % (2 MB)
36 19:51:42.281278 progress 65 % (2 MB)
37 19:51:42.283366 progress 70 % (3 MB)
38 19:51:42.285348 progress 75 % (3 MB)
39 19:51:42.287237 progress 80 % (3 MB)
40 19:51:42.289546 progress 85 % (3 MB)
41 19:51:42.291430 progress 90 % (4 MB)
42 19:51:42.293459 progress 95 % (4 MB)
43 19:51:42.295366 progress 100 % (4 MB)
44 19:51:42.295586 4 MB downloaded in 0.31 s (14.51 MB/s)
45 19:51:42.295795 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:51:42.296159 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:51:42.296278 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:51:42.296408 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:51:42.296592 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:51:42.296695 saving as /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/kernel/Image
52 19:51:42.296780 total size: 49304064 (47 MB)
53 19:51:42.296887 No compression specified
54 19:51:42.298435 progress 0 % (0 MB)
55 19:51:42.318643 progress 5 % (2 MB)
56 19:51:42.338864 progress 10 % (4 MB)
57 19:51:42.357919 progress 15 % (7 MB)
58 19:51:42.370784 progress 20 % (9 MB)
59 19:51:42.384046 progress 25 % (11 MB)
60 19:51:42.396863 progress 30 % (14 MB)
61 19:51:42.409536 progress 35 % (16 MB)
62 19:51:42.422215 progress 40 % (18 MB)
63 19:51:42.435183 progress 45 % (21 MB)
64 19:51:42.447968 progress 50 % (23 MB)
65 19:51:42.460837 progress 55 % (25 MB)
66 19:51:42.473621 progress 60 % (28 MB)
67 19:51:42.486697 progress 65 % (30 MB)
68 19:51:42.501153 progress 70 % (32 MB)
69 19:51:42.513964 progress 75 % (35 MB)
70 19:51:42.526904 progress 80 % (37 MB)
71 19:51:42.540338 progress 85 % (39 MB)
72 19:51:42.553473 progress 90 % (42 MB)
73 19:51:42.566145 progress 95 % (44 MB)
74 19:51:42.578725 progress 100 % (47 MB)
75 19:51:42.578994 47 MB downloaded in 0.28 s (166.62 MB/s)
76 19:51:42.579233 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:51:42.579497 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:51:42.579602 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:51:42.579708 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:51:42.579867 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:51:42.579970 saving as /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/dtb/mt8192-asurada-spherion-r0.dtb
83 19:51:42.580070 total size: 47278 (0 MB)
84 19:51:42.580171 No compression specified
85 19:51:42.581877 progress 69 % (0 MB)
86 19:51:42.582191 progress 100 % (0 MB)
87 19:51:42.582386 0 MB downloaded in 0.00 s (19.49 MB/s)
88 19:51:42.582527 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:51:42.582777 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:51:42.582902 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:51:42.583026 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:51:42.583235 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 19:51:42.583336 saving as /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/nfsrootfs/full.rootfs.tar
95 19:51:42.583435 total size: 200813988 (191 MB)
96 19:51:42.583535 Using unxz to decompress xz
97 19:51:42.588116 progress 0 % (0 MB)
98 19:51:43.129582 progress 5 % (9 MB)
99 19:51:43.656866 progress 10 % (19 MB)
100 19:51:44.276935 progress 15 % (28 MB)
101 19:51:44.653123 progress 20 % (38 MB)
102 19:51:44.983053 progress 25 % (47 MB)
103 19:51:45.592297 progress 30 % (57 MB)
104 19:51:46.147355 progress 35 % (67 MB)
105 19:51:46.748348 progress 40 % (76 MB)
106 19:51:47.314358 progress 45 % (86 MB)
107 19:51:47.920963 progress 50 % (95 MB)
108 19:51:48.572496 progress 55 % (105 MB)
109 19:51:49.245894 progress 60 % (114 MB)
110 19:51:49.370480 progress 65 % (124 MB)
111 19:51:49.513205 progress 70 % (134 MB)
112 19:51:49.617513 progress 75 % (143 MB)
113 19:51:49.696976 progress 80 % (153 MB)
114 19:51:49.768688 progress 85 % (162 MB)
115 19:51:49.871844 progress 90 % (172 MB)
116 19:51:50.164569 progress 95 % (181 MB)
117 19:51:50.748336 progress 100 % (191 MB)
118 19:51:50.753732 191 MB downloaded in 8.17 s (23.44 MB/s)
119 19:51:50.754020 end: 1.4.1 http-download (duration 00:00:08) [common]
121 19:51:50.754287 end: 1.4 download-retry (duration 00:00:08) [common]
122 19:51:50.754379 start: 1.5 download-retry (timeout 00:09:51) [common]
123 19:51:50.754466 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 19:51:50.754604 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 19:51:50.754675 saving as /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/modules/modules.tar
126 19:51:50.754737 total size: 8635496 (8 MB)
127 19:51:50.754802 Using unxz to decompress xz
128 19:51:50.758998 progress 0 % (0 MB)
129 19:51:50.780734 progress 5 % (0 MB)
130 19:51:50.803043 progress 10 % (0 MB)
131 19:51:50.829164 progress 15 % (1 MB)
132 19:51:50.854291 progress 20 % (1 MB)
133 19:51:50.880106 progress 25 % (2 MB)
134 19:51:50.908328 progress 30 % (2 MB)
135 19:51:50.932958 progress 35 % (2 MB)
136 19:51:50.957701 progress 40 % (3 MB)
137 19:51:50.981785 progress 45 % (3 MB)
138 19:51:51.008355 progress 50 % (4 MB)
139 19:51:51.033287 progress 55 % (4 MB)
140 19:51:51.059524 progress 60 % (4 MB)
141 19:51:51.082325 progress 65 % (5 MB)
142 19:51:51.107360 progress 70 % (5 MB)
143 19:51:51.131024 progress 75 % (6 MB)
144 19:51:51.157012 progress 80 % (6 MB)
145 19:51:51.189280 progress 85 % (7 MB)
146 19:51:51.215120 progress 90 % (7 MB)
147 19:51:51.239187 progress 95 % (7 MB)
148 19:51:51.261882 progress 100 % (8 MB)
149 19:51:51.267403 8 MB downloaded in 0.51 s (16.06 MB/s)
150 19:51:51.267646 end: 1.5.1 http-download (duration 00:00:01) [common]
152 19:51:51.267907 end: 1.5 download-retry (duration 00:00:01) [common]
153 19:51:51.268002 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 19:51:51.268101 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 19:51:54.826997 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11899568/extract-nfsrootfs-e9matzc_
156 19:51:54.827251 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 19:51:54.827354 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 19:51:54.827528 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y
159 19:51:54.827658 makedir: /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin
160 19:51:54.827759 makedir: /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/tests
161 19:51:54.827920 makedir: /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/results
162 19:51:54.828023 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-add-keys
163 19:51:54.828169 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-add-sources
164 19:51:54.828299 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-background-process-start
165 19:51:54.828425 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-background-process-stop
166 19:51:54.828551 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-common-functions
167 19:51:54.828675 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-echo-ipv4
168 19:51:54.828800 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-install-packages
169 19:51:54.828924 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-installed-packages
170 19:51:54.829047 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-os-build
171 19:51:54.829170 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-probe-channel
172 19:51:54.829294 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-probe-ip
173 19:51:54.829417 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-target-ip
174 19:51:54.829542 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-target-mac
175 19:51:54.829665 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-target-storage
176 19:51:54.829794 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-test-case
177 19:51:54.829922 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-test-event
178 19:51:54.830046 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-test-feedback
179 19:51:54.830169 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-test-raise
180 19:51:54.830293 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-test-reference
181 19:51:54.830423 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-test-runner
182 19:51:54.830547 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-test-set
183 19:51:54.830673 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-test-shell
184 19:51:54.830798 Updating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-add-keys (debian)
185 19:51:54.830949 Updating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-add-sources (debian)
186 19:51:54.831135 Updating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-install-packages (debian)
187 19:51:54.831279 Updating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-installed-packages (debian)
188 19:51:54.831416 Updating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/bin/lava-os-build (debian)
189 19:51:54.831541 Creating /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/environment
190 19:51:54.831641 LAVA metadata
191 19:51:54.831711 - LAVA_JOB_ID=11899568
192 19:51:54.831772 - LAVA_DISPATCHER_IP=192.168.201.1
193 19:51:54.831879 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 19:51:54.831945 skipped lava-vland-overlay
195 19:51:54.832019 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 19:51:54.832097 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 19:51:54.832157 skipped lava-multinode-overlay
198 19:51:54.832229 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 19:51:54.832305 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 19:51:54.832380 Loading test definitions
201 19:51:54.832483 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 19:51:54.832553 Using /lava-11899568 at stage 0
203 19:51:54.832839 uuid=11899568_1.6.2.3.1 testdef=None
204 19:51:54.832927 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 19:51:54.833010 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 19:51:54.833462 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 19:51:54.833682 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 19:51:54.834242 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 19:51:54.834502 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 19:51:54.835054 runner path: /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/0/tests/0_timesync-off test_uuid 11899568_1.6.2.3.1
213 19:51:54.835453 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 19:51:54.835676 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 19:51:54.835748 Using /lava-11899568 at stage 0
217 19:51:54.835844 Fetching tests from https://github.com/kernelci/test-definitions.git
218 19:51:54.835921 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/0/tests/1_kselftest-rtc'
219 19:52:00.042586 Running '/usr/bin/git checkout kernelci.org
220 19:52:00.100121 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 19:52:00.101172 uuid=11899568_1.6.2.3.5 testdef=None
222 19:52:00.101389 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 19:52:00.101766 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 19:52:00.102929 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 19:52:00.103344 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 19:52:00.104931 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 19:52:00.105318 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 19:52:00.106864 runner path: /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/0/tests/1_kselftest-rtc test_uuid 11899568_1.6.2.3.5
232 19:52:00.107003 BOARD='mt8192-asurada-spherion-r0'
233 19:52:00.107139 BRANCH='cip-gitlab'
234 19:52:00.107234 SKIPFILE='/dev/null'
235 19:52:00.107325 SKIP_INSTALL='True'
236 19:52:00.107414 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 19:52:00.107505 TST_CASENAME=''
238 19:52:00.107588 TST_CMDFILES='rtc'
239 19:52:00.107786 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 19:52:00.108125 Creating lava-test-runner.conf files
242 19:52:00.108223 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899568/lava-overlay-95m6ue9y/lava-11899568/0 for stage 0
243 19:52:00.108360 - 0_timesync-off
244 19:52:00.108467 - 1_kselftest-rtc
245 19:52:00.108610 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 19:52:00.108745 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 19:52:07.643180 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 19:52:07.643339 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 19:52:07.643471 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 19:52:07.643575 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 19:52:07.643668 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 19:52:07.763696 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 19:52:07.764092 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 19:52:07.764207 extracting modules file /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899568/extract-nfsrootfs-e9matzc_
255 19:52:07.987615 extracting modules file /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899568/extract-overlay-ramdisk-rx3ahrge/ramdisk
256 19:52:08.216171 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 19:52:08.216335 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 19:52:08.216429 [common] Applying overlay to NFS
259 19:52:08.216500 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899568/compress-overlay-7_my71ek/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11899568/extract-nfsrootfs-e9matzc_
260 19:52:09.134544 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 19:52:09.134724 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 19:52:09.134819 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 19:52:09.134909 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 19:52:09.134993 Building ramdisk /var/lib/lava/dispatcher/tmp/11899568/extract-overlay-ramdisk-rx3ahrge/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11899568/extract-overlay-ramdisk-rx3ahrge/ramdisk
265 19:52:09.587963 >> 119376 blocks
266 19:52:11.491049 rename /var/lib/lava/dispatcher/tmp/11899568/extract-overlay-ramdisk-rx3ahrge/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/ramdisk/ramdisk.cpio.gz
267 19:52:11.491548 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 19:52:11.491674 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 19:52:11.491777 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 19:52:11.491890 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/kernel/Image'
271 19:52:24.321084 Returned 0 in 12 seconds
272 19:52:24.421721 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/kernel/image.itb
273 19:52:24.785663 output: FIT description: Kernel Image image with one or more FDT blobs
274 19:52:24.786044 output: Created: Sat Oct 28 20:52:24 2023
275 19:52:24.786118 output: Image 0 (kernel-1)
276 19:52:24.786182 output: Description:
277 19:52:24.786246 output: Created: Sat Oct 28 20:52:24 2023
278 19:52:24.786306 output: Type: Kernel Image
279 19:52:24.786367 output: Compression: lzma compressed
280 19:52:24.786427 output: Data Size: 11047522 Bytes = 10788.60 KiB = 10.54 MiB
281 19:52:24.786487 output: Architecture: AArch64
282 19:52:24.786547 output: OS: Linux
283 19:52:24.786604 output: Load Address: 0x00000000
284 19:52:24.786662 output: Entry Point: 0x00000000
285 19:52:24.786720 output: Hash algo: crc32
286 19:52:24.786774 output: Hash value: da40eda2
287 19:52:24.786832 output: Image 1 (fdt-1)
288 19:52:24.786887 output: Description: mt8192-asurada-spherion-r0
289 19:52:24.786940 output: Created: Sat Oct 28 20:52:24 2023
290 19:52:24.786992 output: Type: Flat Device Tree
291 19:52:24.787045 output: Compression: uncompressed
292 19:52:24.787109 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 19:52:24.787163 output: Architecture: AArch64
294 19:52:24.787216 output: Hash algo: crc32
295 19:52:24.787268 output: Hash value: cc4352de
296 19:52:24.787320 output: Image 2 (ramdisk-1)
297 19:52:24.787372 output: Description: unavailable
298 19:52:24.787424 output: Created: Sat Oct 28 20:52:24 2023
299 19:52:24.787477 output: Type: RAMDisk Image
300 19:52:24.787529 output: Compression: Unknown Compression
301 19:52:24.787582 output: Data Size: 17785558 Bytes = 17368.71 KiB = 16.96 MiB
302 19:52:24.787634 output: Architecture: AArch64
303 19:52:24.787686 output: OS: Linux
304 19:52:24.787738 output: Load Address: unavailable
305 19:52:24.787790 output: Entry Point: unavailable
306 19:52:24.787841 output: Hash algo: crc32
307 19:52:24.787893 output: Hash value: 351125b9
308 19:52:24.787945 output: Default Configuration: 'conf-1'
309 19:52:24.787997 output: Configuration 0 (conf-1)
310 19:52:24.788048 output: Description: mt8192-asurada-spherion-r0
311 19:52:24.788100 output: Kernel: kernel-1
312 19:52:24.788152 output: Init Ramdisk: ramdisk-1
313 19:52:24.788203 output: FDT: fdt-1
314 19:52:24.788255 output: Loadables: kernel-1
315 19:52:24.788306 output:
316 19:52:24.788513 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 19:52:24.788648 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 19:52:24.788789 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 19:52:24.788911 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 19:52:24.788995 No LXC device requested
321 19:52:24.789075 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 19:52:24.789164 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 19:52:24.789243 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 19:52:24.789313 Checking files for TFTP limit of 4294967296 bytes.
325 19:52:24.789819 end: 1 tftp-deploy (duration 00:00:43) [common]
326 19:52:24.789926 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 19:52:24.790018 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 19:52:24.790144 substitutions:
329 19:52:24.790210 - {DTB}: 11899568/tftp-deploy-8xh880z2/dtb/mt8192-asurada-spherion-r0.dtb
330 19:52:24.790277 - {INITRD}: 11899568/tftp-deploy-8xh880z2/ramdisk/ramdisk.cpio.gz
331 19:52:24.790336 - {KERNEL}: 11899568/tftp-deploy-8xh880z2/kernel/Image
332 19:52:24.790394 - {LAVA_MAC}: None
333 19:52:24.790450 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11899568/extract-nfsrootfs-e9matzc_
334 19:52:24.790505 - {NFS_SERVER_IP}: 192.168.201.1
335 19:52:24.790559 - {PRESEED_CONFIG}: None
336 19:52:24.790613 - {PRESEED_LOCAL}: None
337 19:52:24.790667 - {RAMDISK}: 11899568/tftp-deploy-8xh880z2/ramdisk/ramdisk.cpio.gz
338 19:52:24.790721 - {ROOT_PART}: None
339 19:52:24.790774 - {ROOT}: None
340 19:52:24.790827 - {SERVER_IP}: 192.168.201.1
341 19:52:24.790880 - {TEE}: None
342 19:52:24.790933 Parsed boot commands:
343 19:52:24.790986 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 19:52:24.791233 Parsed boot commands: tftpboot 192.168.201.1 11899568/tftp-deploy-8xh880z2/kernel/image.itb 11899568/tftp-deploy-8xh880z2/kernel/cmdline
345 19:52:24.791321 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 19:52:24.791407 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 19:52:24.791500 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 19:52:24.791581 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 19:52:24.791656 Not connected, no need to disconnect.
350 19:52:24.791729 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 19:52:24.791808 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 19:52:24.791873 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 19:52:24.795927 Setting prompt string to ['lava-test: # ']
354 19:52:24.796292 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 19:52:24.796397 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 19:52:24.796501 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 19:52:24.796594 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 19:52:24.796817 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 19:52:29.928416 >> Command sent successfully.
360 19:52:29.930895 Returned 0 in 5 seconds
361 19:52:30.031237 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 19:52:30.031554 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 19:52:30.031655 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 19:52:30.031743 Setting prompt string to 'Starting depthcharge on Spherion...'
366 19:52:30.031810 Changing prompt to 'Starting depthcharge on Spherion...'
367 19:52:30.031880 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 19:52:30.032153 [Enter `^Ec?' for help]
369 19:52:30.205608
370 19:52:30.205742
371 19:52:30.205839 F0: 102B 0000
372 19:52:30.205909
373 19:52:30.206012 F3: 1001 0000 [0200]
374 19:52:30.209175
375 19:52:30.209251 F3: 1001 0000
376 19:52:30.209315
377 19:52:30.209373 F7: 102D 0000
378 19:52:30.209431
379 19:52:30.212702 F1: 0000 0000
380 19:52:30.212790
381 19:52:30.212869 V0: 0000 0000 [0001]
382 19:52:30.212940
383 19:52:30.215533 00: 0007 8000
384 19:52:30.215630
385 19:52:30.215697 01: 0000 0000
386 19:52:30.215764
387 19:52:30.219049 BP: 0C00 0209 [0000]
388 19:52:30.219178
389 19:52:30.219257 G0: 1182 0000
390 19:52:30.219321
391 19:52:30.222529 EC: 0000 0021 [4000]
392 19:52:30.222613
393 19:52:30.222680 S7: 0000 0000 [0000]
394 19:52:30.222740
395 19:52:30.225615 CC: 0000 0000 [0001]
396 19:52:30.225705
397 19:52:30.225777 T0: 0000 0040 [010F]
398 19:52:30.225842
399 19:52:30.229238 Jump to BL
400 19:52:30.229318
401 19:52:30.253376
402 19:52:30.253526
403 19:52:30.253665
404 19:52:30.260290 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 19:52:30.263722 ARM64: Exception handlers installed.
406 19:52:30.266954 ARM64: Testing exception
407 19:52:30.270575 ARM64: Done test exception
408 19:52:30.276778 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 19:52:30.287737 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 19:52:30.294091 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 19:52:30.304316 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 19:52:30.310746 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 19:52:30.320850 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 19:52:30.330975 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 19:52:30.337736 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 19:52:30.355602 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 19:52:30.359038 WDT: Last reset was cold boot
418 19:52:30.362138 SPI1(PAD0) initialized at 2873684 Hz
419 19:52:30.365363 SPI5(PAD0) initialized at 992727 Hz
420 19:52:30.369083 VBOOT: Loading verstage.
421 19:52:30.375603 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 19:52:30.378659 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 19:52:30.382571 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 19:52:30.386001 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 19:52:30.393308 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 19:52:30.399948 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 19:52:30.411057 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 19:52:30.411150
429 19:52:30.411216
430 19:52:30.421010 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 19:52:30.424184 ARM64: Exception handlers installed.
432 19:52:30.427478 ARM64: Testing exception
433 19:52:30.427561 ARM64: Done test exception
434 19:52:30.434695 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 19:52:30.437701 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 19:52:30.451653 Probing TPM: . done!
437 19:52:30.451736 TPM ready after 0 ms
438 19:52:30.458804 Connected to device vid:did:rid of 1ae0:0028:00
439 19:52:30.465897 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 19:52:30.524011 Initialized TPM device CR50 revision 0
441 19:52:30.535925 tlcl_send_startup: Startup return code is 0
442 19:52:30.536045 TPM: setup succeeded
443 19:52:30.547728 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 19:52:30.555807 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 19:52:30.567865 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 19:52:30.577689 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 19:52:30.581731 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 19:52:30.586729 in-header: 03 07 00 00 08 00 00 00
449 19:52:30.590730 in-data: aa e4 47 04 13 02 00 00
450 19:52:30.594083 Chrome EC: UHEPI supported
451 19:52:30.601592 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 19:52:30.604841 in-header: 03 95 00 00 08 00 00 00
453 19:52:30.608327 in-data: 18 20 20 08 00 00 00 00
454 19:52:30.608427 Phase 1
455 19:52:30.612163 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 19:52:30.618977 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 19:52:30.623809 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 19:52:30.626182 Recovery requested (1009000e)
459 19:52:30.635458 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 19:52:30.641032 tlcl_extend: response is 0
461 19:52:30.650403 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 19:52:30.655878 tlcl_extend: response is 0
463 19:52:30.663384 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 19:52:30.682784 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 19:52:30.689285 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 19:52:30.689370
467 19:52:30.689437
468 19:52:30.698985 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 19:52:30.702417 ARM64: Exception handlers installed.
470 19:52:30.705562 ARM64: Testing exception
471 19:52:30.705642 ARM64: Done test exception
472 19:52:30.728095 pmic_efuse_setting: Set efuses in 11 msecs
473 19:52:30.731483 pmwrap_interface_init: Select PMIF_VLD_RDY
474 19:52:30.737886 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 19:52:30.741765 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 19:52:30.747926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 19:52:30.751959 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 19:52:30.755063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 19:52:30.762478 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 19:52:30.766902 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 19:52:30.769806 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 19:52:30.773713 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 19:52:30.781270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 19:52:30.784740 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 19:52:30.788473 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 19:52:30.792286 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 19:52:30.799984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 19:52:30.807299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 19:52:30.811607 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 19:52:30.818565 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 19:52:30.821907 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 19:52:30.829452 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 19:52:30.832703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 19:52:30.840173 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 19:52:30.844756 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 19:52:30.851413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 19:52:30.855577 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 19:52:30.862288 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 19:52:30.866606 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 19:52:30.873538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 19:52:30.877102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 19:52:30.880455 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 19:52:30.887871 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 19:52:30.891861 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 19:52:30.898770 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 19:52:30.903939 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 19:52:30.906424 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 19:52:30.913468 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 19:52:30.917764 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 19:52:30.921835 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 19:52:30.928589 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 19:52:30.932610 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 19:52:30.935753 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 19:52:30.939262 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 19:52:30.943333 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 19:52:30.950007 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 19:52:30.954190 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 19:52:30.957846 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 19:52:30.961801 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 19:52:30.965606 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 19:52:30.969032 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 19:52:30.975750 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 19:52:30.979705 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 19:52:30.983237 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 19:52:30.990662 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 19:52:30.998577 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 19:52:31.005267 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 19:52:31.012872 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 19:52:31.020293 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 19:52:31.024273 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 19:52:31.031280 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 19:52:31.035214 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 19:52:31.041467 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x20
534 19:52:31.045125 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 19:52:31.053301 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 19:52:31.056598 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 19:52:31.066469 [RTC]rtc_get_frequency_meter,154: input=15, output=854
538 19:52:31.075016 [RTC]rtc_get_frequency_meter,154: input=7, output=724
539 19:52:31.084761 [RTC]rtc_get_frequency_meter,154: input=11, output=788
540 19:52:31.094662 [RTC]rtc_get_frequency_meter,154: input=13, output=821
541 19:52:31.103945 [RTC]rtc_get_frequency_meter,154: input=12, output=805
542 19:52:31.113323 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 19:52:31.123563 [RTC]rtc_get_frequency_meter,154: input=12, output=805
544 19:52:31.126741 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 19:52:31.134517 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 19:52:31.137613 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 19:52:31.141406 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 19:52:31.144882 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 19:52:31.148895 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 19:52:31.151848 ADC[4]: Raw value=905541 ID=7
551 19:52:31.156026 ADC[3]: Raw value=213916 ID=1
552 19:52:31.156475 RAM Code: 0x71
553 19:52:31.159377 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 19:52:31.166071 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 19:52:31.173487 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 19:52:31.181027 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 19:52:31.184847 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 19:52:31.188274 in-header: 03 07 00 00 08 00 00 00
559 19:52:31.192550 in-data: aa e4 47 04 13 02 00 00
560 19:52:31.192941 Chrome EC: UHEPI supported
561 19:52:31.199709 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 19:52:31.203331 in-header: 03 95 00 00 08 00 00 00
563 19:52:31.206729 in-data: 18 20 20 08 00 00 00 00
564 19:52:31.210913 MRC: failed to locate region type 0.
565 19:52:31.217602 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 19:52:31.217904 DRAM-K: Running full calibration
567 19:52:31.224795 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 19:52:31.228607 header.status = 0x0
569 19:52:31.233107 header.version = 0x6 (expected: 0x6)
570 19:52:31.233432 header.size = 0xd00 (expected: 0xd00)
571 19:52:31.236532 header.flags = 0x0
572 19:52:31.243230 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 19:52:31.260845 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 19:52:31.267350 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 19:52:31.271039 dram_init: ddr_geometry: 2
576 19:52:31.271619 [EMI] MDL number = 2
577 19:52:31.274491 [EMI] Get MDL freq = 0
578 19:52:31.274914 dram_init: ddr_type: 0
579 19:52:31.278258 is_discrete_lpddr4: 1
580 19:52:31.282093 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 19:52:31.282620
582 19:52:31.282963
583 19:52:31.285959 [Bian_co] ETT version 0.0.0.1
584 19:52:31.289558 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 19:52:31.290086
586 19:52:31.293224 dramc_set_vcore_voltage set vcore to 650000
587 19:52:31.293723 Read voltage for 800, 4
588 19:52:31.297074 Vio18 = 0
589 19:52:31.297497 Vcore = 650000
590 19:52:31.297833 Vdram = 0
591 19:52:31.300557 Vddq = 0
592 19:52:31.300981 Vmddr = 0
593 19:52:31.301314 dram_init: config_dvfs: 1
594 19:52:31.308294 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 19:52:31.311568 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 19:52:31.314911 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 19:52:31.318810 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 19:52:31.325583 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 19:52:31.328786 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 19:52:31.329317 MEM_TYPE=3, freq_sel=18
601 19:52:31.332350 sv_algorithm_assistance_LP4_1600
602 19:52:31.336274 ============ PULL DRAM RESETB DOWN ============
603 19:52:31.339614 ========== PULL DRAM RESETB DOWN end =========
604 19:52:31.347002 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 19:52:31.350630 ===================================
606 19:52:31.351058 LPDDR4 DRAM CONFIGURATION
607 19:52:31.353723 ===================================
608 19:52:31.357272 EX_ROW_EN[0] = 0x0
609 19:52:31.357706 EX_ROW_EN[1] = 0x0
610 19:52:31.360819 LP4Y_EN = 0x0
611 19:52:31.361249 WORK_FSP = 0x0
612 19:52:31.364177 WL = 0x2
613 19:52:31.364610 RL = 0x2
614 19:52:31.367626 BL = 0x2
615 19:52:31.368096 RPST = 0x0
616 19:52:31.370868 RD_PRE = 0x0
617 19:52:31.373996 WR_PRE = 0x1
618 19:52:31.374423 WR_PST = 0x0
619 19:52:31.377371 DBI_WR = 0x0
620 19:52:31.377799 DBI_RD = 0x0
621 19:52:31.380597 OTF = 0x1
622 19:52:31.384264 ===================================
623 19:52:31.387592 ===================================
624 19:52:31.388412 ANA top config
625 19:52:31.390392 ===================================
626 19:52:31.393930 DLL_ASYNC_EN = 0
627 19:52:31.396988 ALL_SLAVE_EN = 1
628 19:52:31.397440 NEW_RANK_MODE = 1
629 19:52:31.400550 DLL_IDLE_MODE = 1
630 19:52:31.403849 LP45_APHY_COMB_EN = 1
631 19:52:31.407250 TX_ODT_DIS = 1
632 19:52:31.407713 NEW_8X_MODE = 1
633 19:52:31.410558 ===================================
634 19:52:31.414002 ===================================
635 19:52:31.416999 data_rate = 1600
636 19:52:31.420382 CKR = 1
637 19:52:31.423996 DQ_P2S_RATIO = 8
638 19:52:31.427257 ===================================
639 19:52:31.430355 CA_P2S_RATIO = 8
640 19:52:31.434265 DQ_CA_OPEN = 0
641 19:52:31.434692 DQ_SEMI_OPEN = 0
642 19:52:31.437884 CA_SEMI_OPEN = 0
643 19:52:31.441207 CA_FULL_RATE = 0
644 19:52:31.444507 DQ_CKDIV4_EN = 1
645 19:52:31.447719 CA_CKDIV4_EN = 1
646 19:52:31.448167 CA_PREDIV_EN = 0
647 19:52:31.450569 PH8_DLY = 0
648 19:52:31.453979 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 19:52:31.457510 DQ_AAMCK_DIV = 4
650 19:52:31.461308 CA_AAMCK_DIV = 4
651 19:52:31.464130 CA_ADMCK_DIV = 4
652 19:52:31.464554 DQ_TRACK_CA_EN = 0
653 19:52:31.467257 CA_PICK = 800
654 19:52:31.470821 CA_MCKIO = 800
655 19:52:31.474455 MCKIO_SEMI = 0
656 19:52:31.477992 PLL_FREQ = 3068
657 19:52:31.481857 DQ_UI_PI_RATIO = 32
658 19:52:31.482388 CA_UI_PI_RATIO = 0
659 19:52:31.485504 ===================================
660 19:52:31.489105 ===================================
661 19:52:31.492599 memory_type:LPDDR4
662 19:52:31.493097 GP_NUM : 10
663 19:52:31.496255 SRAM_EN : 1
664 19:52:31.496676 MD32_EN : 0
665 19:52:31.499895 ===================================
666 19:52:31.503569 [ANA_INIT] >>>>>>>>>>>>>>
667 19:52:31.507289 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 19:52:31.510978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 19:52:31.514454 ===================================
670 19:52:31.514950 data_rate = 1600,PCW = 0X7600
671 19:52:31.517713 ===================================
672 19:52:31.520908 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 19:52:31.528079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 19:52:31.534538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 19:52:31.537432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 19:52:31.541636 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 19:52:31.544239 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 19:52:31.547344 [ANA_INIT] flow start
679 19:52:31.550374 [ANA_INIT] PLL >>>>>>>>
680 19:52:31.550758 [ANA_INIT] PLL <<<<<<<<
681 19:52:31.553764 [ANA_INIT] MIDPI >>>>>>>>
682 19:52:31.557367 [ANA_INIT] MIDPI <<<<<<<<
683 19:52:31.558012 [ANA_INIT] DLL >>>>>>>>
684 19:52:31.560788 [ANA_INIT] flow end
685 19:52:31.564098 ============ LP4 DIFF to SE enter ============
686 19:52:31.567500 ============ LP4 DIFF to SE exit ============
687 19:52:31.570652 [ANA_INIT] <<<<<<<<<<<<<
688 19:52:31.573930 [Flow] Enable top DCM control >>>>>
689 19:52:31.577682 [Flow] Enable top DCM control <<<<<
690 19:52:31.580497 Enable DLL master slave shuffle
691 19:52:31.588031 ==============================================================
692 19:52:31.588550 Gating Mode config
693 19:52:31.594782 ==============================================================
694 19:52:31.595364 Config description:
695 19:52:31.604257 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 19:52:31.610434 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 19:52:31.617369 SELPH_MODE 0: By rank 1: By Phase
698 19:52:31.620924 ==============================================================
699 19:52:31.623764 GAT_TRACK_EN = 1
700 19:52:31.627042 RX_GATING_MODE = 2
701 19:52:31.630402 RX_GATING_TRACK_MODE = 2
702 19:52:31.634314 SELPH_MODE = 1
703 19:52:31.637302 PICG_EARLY_EN = 1
704 19:52:31.641005 VALID_LAT_VALUE = 1
705 19:52:31.647479 ==============================================================
706 19:52:31.650232 Enter into Gating configuration >>>>
707 19:52:31.653960 Exit from Gating configuration <<<<
708 19:52:31.656713 Enter into DVFS_PRE_config >>>>>
709 19:52:31.667054 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 19:52:31.670219 Exit from DVFS_PRE_config <<<<<
711 19:52:31.673626 Enter into PICG configuration >>>>
712 19:52:31.676843 Exit from PICG configuration <<<<
713 19:52:31.680465 [RX_INPUT] configuration >>>>>
714 19:52:31.680883 [RX_INPUT] configuration <<<<<
715 19:52:31.686867 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 19:52:31.693393 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 19:52:31.696247 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 19:52:31.702862 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 19:52:31.710099 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 19:52:31.716802 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 19:52:31.719947 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 19:52:31.723050 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 19:52:31.729398 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 19:52:31.732532 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 19:52:31.736478 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 19:52:31.742957 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 19:52:31.743449 ===================================
728 19:52:31.746323 LPDDR4 DRAM CONFIGURATION
729 19:52:31.749648 ===================================
730 19:52:31.753296 EX_ROW_EN[0] = 0x0
731 19:52:31.753744 EX_ROW_EN[1] = 0x0
732 19:52:31.756452 LP4Y_EN = 0x0
733 19:52:31.756876 WORK_FSP = 0x0
734 19:52:31.760239 WL = 0x2
735 19:52:31.760660 RL = 0x2
736 19:52:31.763338 BL = 0x2
737 19:52:31.763758 RPST = 0x0
738 19:52:31.767199 RD_PRE = 0x0
739 19:52:31.767628 WR_PRE = 0x1
740 19:52:31.769848 WR_PST = 0x0
741 19:52:31.773455 DBI_WR = 0x0
742 19:52:31.773753 DBI_RD = 0x0
743 19:52:31.776712 OTF = 0x1
744 19:52:31.779303 ===================================
745 19:52:31.782642 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 19:52:31.786587 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 19:52:31.789648 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 19:52:31.793021 ===================================
749 19:52:31.796074 LPDDR4 DRAM CONFIGURATION
750 19:52:31.799212 ===================================
751 19:52:31.802839 EX_ROW_EN[0] = 0x10
752 19:52:31.803021 EX_ROW_EN[1] = 0x0
753 19:52:31.806145 LP4Y_EN = 0x0
754 19:52:31.806388 WORK_FSP = 0x0
755 19:52:31.809359 WL = 0x2
756 19:52:31.809608 RL = 0x2
757 19:52:31.812507 BL = 0x2
758 19:52:31.812733 RPST = 0x0
759 19:52:31.815622 RD_PRE = 0x0
760 19:52:31.819364 WR_PRE = 0x1
761 19:52:31.819622 WR_PST = 0x0
762 19:52:31.822574 DBI_WR = 0x0
763 19:52:31.822872 DBI_RD = 0x0
764 19:52:31.825668 OTF = 0x1
765 19:52:31.829240 ===================================
766 19:52:31.832439 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 19:52:31.837796 nWR fixed to 40
768 19:52:31.841609 [ModeRegInit_LP4] CH0 RK0
769 19:52:31.842139 [ModeRegInit_LP4] CH0 RK1
770 19:52:31.844952 [ModeRegInit_LP4] CH1 RK0
771 19:52:31.847935 [ModeRegInit_LP4] CH1 RK1
772 19:52:31.848625 match AC timing 13
773 19:52:31.854463 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 19:52:31.857702 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 19:52:31.861012 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 19:52:31.867685 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 19:52:31.871103 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 19:52:31.874188 [EMI DOE] emi_dcm 0
779 19:52:31.877592 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 19:52:31.877828 ==
781 19:52:31.881311 Dram Type= 6, Freq= 0, CH_0, rank 0
782 19:52:31.884183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 19:52:31.884396 ==
784 19:52:31.890945 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 19:52:31.897462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 19:52:31.905263 [CA 0] Center 38 (7~69) winsize 63
787 19:52:31.908333 [CA 1] Center 37 (6~68) winsize 63
788 19:52:31.912078 [CA 2] Center 34 (4~65) winsize 62
789 19:52:31.915035 [CA 3] Center 35 (4~66) winsize 63
790 19:52:31.918758 [CA 4] Center 33 (3~64) winsize 62
791 19:52:31.921838 [CA 5] Center 33 (3~64) winsize 62
792 19:52:31.922066
793 19:52:31.925611 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 19:52:31.925841
795 19:52:31.928546 [CATrainingPosCal] consider 1 rank data
796 19:52:31.932222 u2DelayCellTimex100 = 270/100 ps
797 19:52:31.935101 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
798 19:52:31.938914 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 19:52:31.945421 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 19:52:31.948869 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 19:52:31.952517 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 19:52:31.955459 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 19:52:31.955931
804 19:52:31.958533 CA PerBit enable=1, Macro0, CA PI delay=33
805 19:52:31.959298
806 19:52:31.962660 [CBTSetCACLKResult] CA Dly = 33
807 19:52:31.963297 CS Dly: 5 (0~36)
808 19:52:31.965596 ==
809 19:52:31.968497 Dram Type= 6, Freq= 0, CH_0, rank 1
810 19:52:31.971864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 19:52:31.972336 ==
812 19:52:31.975151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 19:52:31.981849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 19:52:31.992073 [CA 0] Center 38 (7~69) winsize 63
815 19:52:31.995450 [CA 1] Center 37 (7~68) winsize 62
816 19:52:31.998844 [CA 2] Center 35 (4~66) winsize 63
817 19:52:32.002048 [CA 3] Center 34 (4~65) winsize 62
818 19:52:32.005821 [CA 4] Center 34 (3~65) winsize 63
819 19:52:32.008724 [CA 5] Center 33 (3~64) winsize 62
820 19:52:32.009300
821 19:52:32.012049 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 19:52:32.012626
823 19:52:32.015261 [CATrainingPosCal] consider 2 rank data
824 19:52:32.018910 u2DelayCellTimex100 = 270/100 ps
825 19:52:32.021375 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
826 19:52:32.028449 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 19:52:32.031658 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 19:52:32.034947 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 19:52:32.038070 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 19:52:32.041767 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 19:52:32.042361
832 19:52:32.044764 CA PerBit enable=1, Macro0, CA PI delay=33
833 19:52:32.045235
834 19:52:32.047741 [CBTSetCACLKResult] CA Dly = 33
835 19:52:32.048209 CS Dly: 6 (0~38)
836 19:52:32.051460
837 19:52:32.054665 ----->DramcWriteLeveling(PI) begin...
838 19:52:32.055131 ==
839 19:52:32.058826 Dram Type= 6, Freq= 0, CH_0, rank 0
840 19:52:32.061944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 19:52:32.062417 ==
842 19:52:32.065638 Write leveling (Byte 0): 31 => 31
843 19:52:32.066066 Write leveling (Byte 1): 28 => 28
844 19:52:32.069727 DramcWriteLeveling(PI) end<-----
845 19:52:32.070269
846 19:52:32.070611 ==
847 19:52:32.073336 Dram Type= 6, Freq= 0, CH_0, rank 0
848 19:52:32.076630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 19:52:32.079955 ==
850 19:52:32.080499 [Gating] SW mode calibration
851 19:52:32.087451 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 19:52:32.094409 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 19:52:32.097547 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 19:52:32.100909 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 19:52:32.107437 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 19:52:32.110886 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 19:52:32.114121 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 19:52:32.120862 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 19:52:32.123852 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 19:52:32.128043 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 19:52:32.134659 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 19:52:32.137224 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 19:52:32.140809 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 19:52:32.146898 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 19:52:32.150391 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 19:52:32.153484 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 19:52:32.160515 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 19:52:32.163435 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 19:52:32.167107 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 19:52:32.173405 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 19:52:32.177482 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 19:52:32.180428 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 19:52:32.187414 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 19:52:32.190162 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 19:52:32.193638 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 19:52:32.200136 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 19:52:32.203769 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 19:52:32.207370 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 19:52:32.210163 0 9 8 | B1->B0 | 2323 3030 | 1 0 | (1 1) (0 0)
880 19:52:32.216830 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
881 19:52:32.220336 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 19:52:32.223635 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 19:52:32.230294 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 19:52:32.233899 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 19:52:32.236826 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
886 19:52:32.243972 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
887 19:52:32.247607 0 10 8 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
888 19:52:32.251415 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
889 19:52:32.257490 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 19:52:32.260177 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 19:52:32.263639 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 19:52:32.270371 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 19:52:32.273587 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 19:52:32.276944 0 11 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
895 19:52:32.283255 0 11 8 | B1->B0 | 2929 3e3e | 0 0 | (0 0) (0 0)
896 19:52:32.287029 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
897 19:52:32.290101 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 19:52:32.296771 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 19:52:32.300223 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 19:52:32.303578 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 19:52:32.310134 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 19:52:32.313320 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 19:52:32.317279 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 19:52:32.323552 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 19:52:32.326887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 19:52:32.329907 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 19:52:32.336544 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 19:52:32.340058 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 19:52:32.343549 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 19:52:32.350076 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 19:52:32.353358 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 19:52:32.356584 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 19:52:32.359784 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 19:52:32.367435 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 19:52:32.370188 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 19:52:32.373220 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 19:52:32.379759 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 19:52:32.383345 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 19:52:32.386459 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 19:52:32.389702 Total UI for P1: 0, mck2ui 16
921 19:52:32.393315 best dqsien dly found for B0: ( 0, 14, 4)
922 19:52:32.399435 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 19:52:32.402934 Total UI for P1: 0, mck2ui 16
924 19:52:32.406262 best dqsien dly found for B1: ( 0, 14, 8)
925 19:52:32.409448 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 19:52:32.412870 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 19:52:32.413465
928 19:52:32.416584 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 19:52:32.419626 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 19:52:32.422706 [Gating] SW calibration Done
931 19:52:32.423305 ==
932 19:52:32.426746 Dram Type= 6, Freq= 0, CH_0, rank 0
933 19:52:32.429807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 19:52:32.430388 ==
935 19:52:32.433237 RX Vref Scan: 0
936 19:52:32.433803
937 19:52:32.434196 RX Vref 0 -> 0, step: 1
938 19:52:32.434548
939 19:52:32.436714 RX Delay -130 -> 252, step: 16
940 19:52:32.440694 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 19:52:32.443265 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 19:52:32.450525 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 19:52:32.453288 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 19:52:32.456580 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 19:52:32.459635 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 19:52:32.463160 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 19:52:32.470300 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 19:52:32.473192 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 19:52:32.476543 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
950 19:52:32.479687 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 19:52:32.483178 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 19:52:32.489602 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 19:52:32.493048 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 19:52:32.496708 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 19:52:32.499915 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 19:52:32.500337 ==
957 19:52:32.503215 Dram Type= 6, Freq= 0, CH_0, rank 0
958 19:52:32.509823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 19:52:32.510246 ==
960 19:52:32.510581 DQS Delay:
961 19:52:32.512923 DQS0 = 0, DQS1 = 0
962 19:52:32.513344 DQM Delay:
963 19:52:32.513681 DQM0 = 87, DQM1 = 76
964 19:52:32.516731 DQ Delay:
965 19:52:32.519868 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 19:52:32.522810 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
967 19:52:32.526428 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
968 19:52:32.529905 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 19:52:32.530345
970 19:52:32.530802
971 19:52:32.531313 ==
972 19:52:32.532907 Dram Type= 6, Freq= 0, CH_0, rank 0
973 19:52:32.536505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 19:52:32.537240 ==
975 19:52:32.537858
976 19:52:32.538336
977 19:52:32.539999 TX Vref Scan disable
978 19:52:32.543267 == TX Byte 0 ==
979 19:52:32.546332 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 19:52:32.549516 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 19:52:32.552911 == TX Byte 1 ==
982 19:52:32.556210 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 19:52:32.559597 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 19:52:32.560019 ==
985 19:52:32.562879 Dram Type= 6, Freq= 0, CH_0, rank 0
986 19:52:32.566242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 19:52:32.569528 ==
988 19:52:32.581038 TX Vref=22, minBit 0, minWin=27, winSum=440
989 19:52:32.584832 TX Vref=24, minBit 1, minWin=27, winSum=442
990 19:52:32.588054 TX Vref=26, minBit 1, minWin=27, winSum=444
991 19:52:32.591005 TX Vref=28, minBit 5, minWin=27, winSum=449
992 19:52:32.594549 TX Vref=30, minBit 1, minWin=27, winSum=450
993 19:52:32.601230 TX Vref=32, minBit 8, minWin=27, winSum=448
994 19:52:32.603761 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
995 19:52:32.604236
996 19:52:32.607405 Final TX Range 1 Vref 30
997 19:52:32.607830
998 19:52:32.608193 ==
999 19:52:32.610571 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 19:52:32.614076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 19:52:32.614610 ==
1002 19:52:32.616843
1003 19:52:32.617264
1004 19:52:32.617602 TX Vref Scan disable
1005 19:52:32.620707 == TX Byte 0 ==
1006 19:52:32.624248 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 19:52:32.627589 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 19:52:32.630573 == TX Byte 1 ==
1009 19:52:32.634100 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 19:52:32.637286 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 19:52:32.641148
1012 19:52:32.641671 [DATLAT]
1013 19:52:32.642010 Freq=800, CH0 RK0
1014 19:52:32.642335
1015 19:52:32.643912 DATLAT Default: 0xa
1016 19:52:32.644334 0, 0xFFFF, sum = 0
1017 19:52:32.647270 1, 0xFFFF, sum = 0
1018 19:52:32.647711 2, 0xFFFF, sum = 0
1019 19:52:32.650568 3, 0xFFFF, sum = 0
1020 19:52:32.651000 4, 0xFFFF, sum = 0
1021 19:52:32.654371 5, 0xFFFF, sum = 0
1022 19:52:32.657215 6, 0xFFFF, sum = 0
1023 19:52:32.657681 7, 0xFFFF, sum = 0
1024 19:52:32.660509 8, 0xFFFF, sum = 0
1025 19:52:32.660955 9, 0x0, sum = 1
1026 19:52:32.661313 10, 0x0, sum = 2
1027 19:52:32.664349 11, 0x0, sum = 3
1028 19:52:32.664990 12, 0x0, sum = 4
1029 19:52:32.666965 best_step = 10
1030 19:52:32.667467
1031 19:52:32.667828 ==
1032 19:52:32.670687 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 19:52:32.674347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 19:52:32.674870 ==
1035 19:52:32.677692 RX Vref Scan: 1
1036 19:52:32.678209
1037 19:52:32.678548 Set Vref Range= 32 -> 127
1038 19:52:32.681015
1039 19:52:32.681533 RX Vref 32 -> 127, step: 1
1040 19:52:32.681873
1041 19:52:32.684203 RX Delay -95 -> 252, step: 8
1042 19:52:32.684614
1043 19:52:32.687498 Set Vref, RX VrefLevel [Byte0]: 32
1044 19:52:32.690616 [Byte1]: 32
1045 19:52:32.691034
1046 19:52:32.693737 Set Vref, RX VrefLevel [Byte0]: 33
1047 19:52:32.696769 [Byte1]: 33
1048 19:52:32.701049
1049 19:52:32.704439 Set Vref, RX VrefLevel [Byte0]: 34
1050 19:52:32.707612 [Byte1]: 34
1051 19:52:32.708124
1052 19:52:32.710568 Set Vref, RX VrefLevel [Byte0]: 35
1053 19:52:32.714196 [Byte1]: 35
1054 19:52:32.714684
1055 19:52:32.717470 Set Vref, RX VrefLevel [Byte0]: 36
1056 19:52:32.720725 [Byte1]: 36
1057 19:52:32.721303
1058 19:52:32.724354 Set Vref, RX VrefLevel [Byte0]: 37
1059 19:52:32.728109 [Byte1]: 37
1060 19:52:32.732194
1061 19:52:32.732721 Set Vref, RX VrefLevel [Byte0]: 38
1062 19:52:32.735538 [Byte1]: 38
1063 19:52:32.739380
1064 19:52:32.739798 Set Vref, RX VrefLevel [Byte0]: 39
1065 19:52:32.743205 [Byte1]: 39
1066 19:52:32.747055
1067 19:52:32.747619 Set Vref, RX VrefLevel [Byte0]: 40
1068 19:52:32.750360 [Byte1]: 40
1069 19:52:32.754249
1070 19:52:32.754659 Set Vref, RX VrefLevel [Byte0]: 41
1071 19:52:32.757724 [Byte1]: 41
1072 19:52:32.761881
1073 19:52:32.762294 Set Vref, RX VrefLevel [Byte0]: 42
1074 19:52:32.765160 [Byte1]: 42
1075 19:52:32.769213
1076 19:52:32.769650 Set Vref, RX VrefLevel [Byte0]: 43
1077 19:52:32.772830 [Byte1]: 43
1078 19:52:32.777310
1079 19:52:32.777803 Set Vref, RX VrefLevel [Byte0]: 44
1080 19:52:32.780429 [Byte1]: 44
1081 19:52:32.785831
1082 19:52:32.786339 Set Vref, RX VrefLevel [Byte0]: 45
1083 19:52:32.787872 [Byte1]: 45
1084 19:52:32.792314
1085 19:52:32.792823 Set Vref, RX VrefLevel [Byte0]: 46
1086 19:52:32.795207 [Byte1]: 46
1087 19:52:32.799849
1088 19:52:32.800373 Set Vref, RX VrefLevel [Byte0]: 47
1089 19:52:32.803437 [Byte1]: 47
1090 19:52:32.807640
1091 19:52:32.808159 Set Vref, RX VrefLevel [Byte0]: 48
1092 19:52:32.811151 [Byte1]: 48
1093 19:52:32.815012
1094 19:52:32.815526 Set Vref, RX VrefLevel [Byte0]: 49
1095 19:52:32.818587 [Byte1]: 49
1096 19:52:32.822953
1097 19:52:32.823508 Set Vref, RX VrefLevel [Byte0]: 50
1098 19:52:32.826021 [Byte1]: 50
1099 19:52:32.830292
1100 19:52:32.830795 Set Vref, RX VrefLevel [Byte0]: 51
1101 19:52:32.833613 [Byte1]: 51
1102 19:52:32.837745
1103 19:52:32.838250 Set Vref, RX VrefLevel [Byte0]: 52
1104 19:52:32.841566 [Byte1]: 52
1105 19:52:32.845542
1106 19:52:32.845951 Set Vref, RX VrefLevel [Byte0]: 53
1107 19:52:32.849105 [Byte1]: 53
1108 19:52:32.852863
1109 19:52:32.853411 Set Vref, RX VrefLevel [Byte0]: 54
1110 19:52:32.856151 [Byte1]: 54
1111 19:52:32.860537
1112 19:52:32.860946 Set Vref, RX VrefLevel [Byte0]: 55
1113 19:52:32.863776 [Byte1]: 55
1114 19:52:32.868043
1115 19:52:32.868458 Set Vref, RX VrefLevel [Byte0]: 56
1116 19:52:32.871131 [Byte1]: 56
1117 19:52:32.875748
1118 19:52:32.876251 Set Vref, RX VrefLevel [Byte0]: 57
1119 19:52:32.879586 [Byte1]: 57
1120 19:52:32.883520
1121 19:52:32.884062 Set Vref, RX VrefLevel [Byte0]: 58
1122 19:52:32.886580 [Byte1]: 58
1123 19:52:32.890901
1124 19:52:32.891460 Set Vref, RX VrefLevel [Byte0]: 59
1125 19:52:32.893982 [Byte1]: 59
1126 19:52:32.898994
1127 19:52:32.899572 Set Vref, RX VrefLevel [Byte0]: 60
1128 19:52:32.901909 [Byte1]: 60
1129 19:52:32.906337
1130 19:52:32.906848 Set Vref, RX VrefLevel [Byte0]: 61
1131 19:52:32.909639 [Byte1]: 61
1132 19:52:32.913793
1133 19:52:32.914375 Set Vref, RX VrefLevel [Byte0]: 62
1134 19:52:32.916688 [Byte1]: 62
1135 19:52:32.921702
1136 19:52:32.922250 Set Vref, RX VrefLevel [Byte0]: 63
1137 19:52:32.924954 [Byte1]: 63
1138 19:52:32.929297
1139 19:52:32.929823 Set Vref, RX VrefLevel [Byte0]: 64
1140 19:52:32.932019 [Byte1]: 64
1141 19:52:32.936797
1142 19:52:32.937327 Set Vref, RX VrefLevel [Byte0]: 65
1143 19:52:32.939898 [Byte1]: 65
1144 19:52:32.944933
1145 19:52:32.945601 Set Vref, RX VrefLevel [Byte0]: 66
1146 19:52:32.947522 [Byte1]: 66
1147 19:52:32.951724
1148 19:52:32.952253 Set Vref, RX VrefLevel [Byte0]: 67
1149 19:52:32.954748 [Byte1]: 67
1150 19:52:32.959135
1151 19:52:32.959597 Set Vref, RX VrefLevel [Byte0]: 68
1152 19:52:32.962513 [Byte1]: 68
1153 19:52:32.967394
1154 19:52:32.967808 Set Vref, RX VrefLevel [Byte0]: 69
1155 19:52:32.969888 [Byte1]: 69
1156 19:52:32.974859
1157 19:52:32.975414 Set Vref, RX VrefLevel [Byte0]: 70
1158 19:52:32.977627 [Byte1]: 70
1159 19:52:32.981879
1160 19:52:32.982389 Set Vref, RX VrefLevel [Byte0]: 71
1161 19:52:32.986376 [Byte1]: 71
1162 19:52:32.989771
1163 19:52:32.990184 Set Vref, RX VrefLevel [Byte0]: 72
1164 19:52:32.993048 [Byte1]: 72
1165 19:52:32.997241
1166 19:52:32.997773 Set Vref, RX VrefLevel [Byte0]: 73
1167 19:52:33.000991 [Byte1]: 73
1168 19:52:33.004694
1169 19:52:33.005173 Set Vref, RX VrefLevel [Byte0]: 74
1170 19:52:33.008118 [Byte1]: 74
1171 19:52:33.012999
1172 19:52:33.013531 Set Vref, RX VrefLevel [Byte0]: 75
1173 19:52:33.015912 [Byte1]: 75
1174 19:52:33.020013
1175 19:52:33.020536 Final RX Vref Byte 0 = 55 to rank0
1176 19:52:33.023741 Final RX Vref Byte 1 = 60 to rank0
1177 19:52:33.026660 Final RX Vref Byte 0 = 55 to rank1
1178 19:52:33.030439 Final RX Vref Byte 1 = 60 to rank1==
1179 19:52:33.033248 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 19:52:33.039892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 19:52:33.040458 ==
1182 19:52:33.040820 DQS Delay:
1183 19:52:33.041201 DQS0 = 0, DQS1 = 0
1184 19:52:33.043406 DQM Delay:
1185 19:52:33.043987 DQM0 = 88, DQM1 = 76
1186 19:52:33.046482 DQ Delay:
1187 19:52:33.049691 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1188 19:52:33.052914 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1189 19:52:33.056895 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =76
1190 19:52:33.059845 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1191 19:52:33.060256
1192 19:52:33.060579
1193 19:52:33.066770 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1194 19:52:33.070334 CH0 RK0: MR19=606, MR18=2C25
1195 19:52:33.076490 CH0_RK0: MR19=0x606, MR18=0x2C25, DQSOSC=398, MR23=63, INC=93, DEC=62
1196 19:52:33.077081
1197 19:52:33.079379 ----->DramcWriteLeveling(PI) begin...
1198 19:52:33.079798 ==
1199 19:52:33.083450 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 19:52:33.086605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 19:52:33.087124 ==
1202 19:52:33.089520 Write leveling (Byte 0): 32 => 32
1203 19:52:33.093261 Write leveling (Byte 1): 28 => 28
1204 19:52:33.096417 DramcWriteLeveling(PI) end<-----
1205 19:52:33.096837
1206 19:52:33.097258 ==
1207 19:52:33.099754 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 19:52:33.103066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 19:52:33.103636 ==
1210 19:52:33.106159 [Gating] SW mode calibration
1211 19:52:33.113055 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 19:52:33.119583 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 19:52:33.163570 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 19:52:33.164458 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1215 19:52:33.164851 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 19:52:33.165426 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 19:52:33.165919 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 19:52:33.166350 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 19:52:33.166828 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 19:52:33.167454 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 19:52:33.167990 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 19:52:33.168479 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 19:52:33.206251 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 19:52:33.207107 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 19:52:33.207523 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 19:52:33.207903 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 19:52:33.208216 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 19:52:33.208607 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 19:52:33.208941 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 19:52:33.209277 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1231 19:52:33.209582 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1232 19:52:33.209930 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 19:52:33.211615 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 19:52:33.215157 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 19:52:33.218402 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 19:52:33.225086 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 19:52:33.228310 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 19:52:33.231651 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 19:52:33.238792 0 9 8 | B1->B0 | 2424 3333 | 1 0 | (1 1) (0 0)
1240 19:52:33.241646 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1241 19:52:33.245288 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 19:52:33.251797 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 19:52:33.255257 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 19:52:33.258513 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 19:52:33.265346 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 19:52:33.268268 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1247 19:52:33.271741 0 10 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
1248 19:52:33.277905 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 19:52:33.281478 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 19:52:33.285477 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 19:52:33.291243 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 19:52:33.295054 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 19:52:33.297861 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 19:52:33.304698 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
1255 19:52:33.308575 0 11 8 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
1256 19:52:33.312231 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1257 19:52:33.315462 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 19:52:33.319639 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 19:52:33.326132 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 19:52:33.329664 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 19:52:33.333694 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 19:52:33.336979 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1263 19:52:33.343704 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1264 19:52:33.347220 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 19:52:33.350239 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 19:52:33.356702 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 19:52:33.360077 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 19:52:33.364004 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 19:52:33.370307 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 19:52:33.373564 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 19:52:33.377083 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 19:52:33.383551 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 19:52:33.386597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 19:52:33.389670 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 19:52:33.396330 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 19:52:33.399522 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 19:52:33.403494 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1278 19:52:33.409796 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 19:52:33.413225 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 19:52:33.416462 Total UI for P1: 0, mck2ui 16
1281 19:52:33.419806 best dqsien dly found for B0: ( 0, 14, 6)
1282 19:52:33.422938 Total UI for P1: 0, mck2ui 16
1283 19:52:33.426260 best dqsien dly found for B1: ( 0, 14, 6)
1284 19:52:33.429478 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1285 19:52:33.433341 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1286 19:52:33.433730
1287 19:52:33.436821 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1288 19:52:33.439820 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1289 19:52:33.443270 [Gating] SW calibration Done
1290 19:52:33.443647 ==
1291 19:52:33.446251 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 19:52:33.449656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 19:52:33.452994 ==
1294 19:52:33.453407 RX Vref Scan: 0
1295 19:52:33.453737
1296 19:52:33.456979 RX Vref 0 -> 0, step: 1
1297 19:52:33.457392
1298 19:52:33.459509 RX Delay -130 -> 252, step: 16
1299 19:52:33.462789 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1300 19:52:33.466383 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1301 19:52:33.469661 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1302 19:52:33.473167 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1303 19:52:33.480401 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1304 19:52:33.483249 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1305 19:52:33.486387 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1306 19:52:33.489306 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1307 19:52:33.492840 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1308 19:52:33.499162 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1309 19:52:33.503339 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1310 19:52:33.505844 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1311 19:52:33.509147 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1312 19:52:33.512331 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1313 19:52:33.519046 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1314 19:52:33.522563 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1315 19:52:33.522944 ==
1316 19:52:33.525680 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 19:52:33.529171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 19:52:33.529559 ==
1319 19:52:33.532619 DQS Delay:
1320 19:52:33.532998 DQS0 = 0, DQS1 = 0
1321 19:52:33.533404 DQM Delay:
1322 19:52:33.535736 DQM0 = 86, DQM1 = 77
1323 19:52:33.536129 DQ Delay:
1324 19:52:33.539785 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1325 19:52:33.542224 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1326 19:52:33.545640 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1327 19:52:33.548995 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1328 19:52:33.549436
1329 19:52:33.549811
1330 19:52:33.550165 ==
1331 19:52:33.552320 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 19:52:33.559306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 19:52:33.559922 ==
1334 19:52:33.560469
1335 19:52:33.560844
1336 19:52:33.561184 TX Vref Scan disable
1337 19:52:33.563149 == TX Byte 0 ==
1338 19:52:33.565873 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1339 19:52:33.569278 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1340 19:52:33.572520 == TX Byte 1 ==
1341 19:52:33.576742 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1342 19:52:33.579366 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1343 19:52:33.582612 ==
1344 19:52:33.585718 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 19:52:33.589100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 19:52:33.589568 ==
1347 19:52:33.602313 TX Vref=22, minBit 0, minWin=27, winSum=439
1348 19:52:33.605257 TX Vref=24, minBit 1, minWin=27, winSum=443
1349 19:52:33.608599 TX Vref=26, minBit 3, minWin=27, winSum=449
1350 19:52:33.611865 TX Vref=28, minBit 1, minWin=27, winSum=451
1351 19:52:33.615570 TX Vref=30, minBit 0, minWin=28, winSum=451
1352 19:52:33.618677 TX Vref=32, minBit 1, minWin=27, winSum=450
1353 19:52:33.625691 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
1354 19:52:33.626121
1355 19:52:33.628558 Final TX Range 1 Vref 30
1356 19:52:33.628986
1357 19:52:33.629421 ==
1358 19:52:33.631646 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 19:52:33.635028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 19:52:33.635628 ==
1361 19:52:33.638436
1362 19:52:33.638945
1363 19:52:33.639460 TX Vref Scan disable
1364 19:52:33.641704 == TX Byte 0 ==
1365 19:52:33.645539 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1366 19:52:33.648624 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1367 19:52:33.652297 == TX Byte 1 ==
1368 19:52:33.655055 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1369 19:52:33.658492 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1370 19:52:33.661878
1371 19:52:33.662097 [DATLAT]
1372 19:52:33.662272 Freq=800, CH0 RK1
1373 19:52:33.662436
1374 19:52:33.664774 DATLAT Default: 0xa
1375 19:52:33.664996 0, 0xFFFF, sum = 0
1376 19:52:33.668142 1, 0xFFFF, sum = 0
1377 19:52:33.668366 2, 0xFFFF, sum = 0
1378 19:52:33.672658 3, 0xFFFF, sum = 0
1379 19:52:33.672884 4, 0xFFFF, sum = 0
1380 19:52:33.674889 5, 0xFFFF, sum = 0
1381 19:52:33.678456 6, 0xFFFF, sum = 0
1382 19:52:33.678679 7, 0xFFFF, sum = 0
1383 19:52:33.681766 8, 0xFFFF, sum = 0
1384 19:52:33.681991 9, 0x0, sum = 1
1385 19:52:33.682172 10, 0x0, sum = 2
1386 19:52:33.685055 11, 0x0, sum = 3
1387 19:52:33.685280 12, 0x0, sum = 4
1388 19:52:33.688258 best_step = 10
1389 19:52:33.688500
1390 19:52:33.688776 ==
1391 19:52:33.691721 Dram Type= 6, Freq= 0, CH_0, rank 1
1392 19:52:33.694881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 19:52:33.695130 ==
1394 19:52:33.698308 RX Vref Scan: 0
1395 19:52:33.698397
1396 19:52:33.698473 RX Vref 0 -> 0, step: 1
1397 19:52:33.698547
1398 19:52:33.701439 RX Delay -95 -> 252, step: 8
1399 19:52:33.708026 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1400 19:52:33.711750 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1401 19:52:33.714534 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1402 19:52:33.718582 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1403 19:52:33.721514 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1404 19:52:33.728015 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1405 19:52:33.731856 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1406 19:52:33.734494 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1407 19:52:33.738354 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1408 19:52:33.741615 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1409 19:52:33.748305 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1410 19:52:33.751485 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1411 19:52:33.754761 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1412 19:52:33.757842 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1413 19:52:33.764684 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1414 19:52:33.768212 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1415 19:52:33.768292 ==
1416 19:52:33.771764 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 19:52:33.774607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 19:52:33.774687 ==
1419 19:52:33.774750 DQS Delay:
1420 19:52:33.778003 DQS0 = 0, DQS1 = 0
1421 19:52:33.778104 DQM Delay:
1422 19:52:33.780951 DQM0 = 86, DQM1 = 76
1423 19:52:33.781030 DQ Delay:
1424 19:52:33.784780 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1425 19:52:33.787887 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1426 19:52:33.791082 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1427 19:52:33.794558 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1428 19:52:33.794637
1429 19:52:33.794699
1430 19:52:33.804409 [DQSOSCAuto] RK1, (LSB)MR18= 0x2622, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1431 19:52:33.804497 CH0 RK1: MR19=606, MR18=2622
1432 19:52:33.810883 CH0_RK1: MR19=0x606, MR18=0x2622, DQSOSC=400, MR23=63, INC=92, DEC=61
1433 19:52:33.814391 [RxdqsGatingPostProcess] freq 800
1434 19:52:33.821533 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1435 19:52:33.824482 Pre-setting of DQS Precalculation
1436 19:52:33.827943 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1437 19:52:33.828023 ==
1438 19:52:33.831244 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 19:52:33.837897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 19:52:33.837977 ==
1441 19:52:33.841100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1442 19:52:33.847867 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1443 19:52:33.856449 [CA 0] Center 36 (6~67) winsize 62
1444 19:52:33.860094 [CA 1] Center 36 (6~67) winsize 62
1445 19:52:33.863540 [CA 2] Center 35 (5~65) winsize 61
1446 19:52:33.866496 [CA 3] Center 34 (4~65) winsize 62
1447 19:52:33.869814 [CA 4] Center 34 (4~65) winsize 62
1448 19:52:33.873706 [CA 5] Center 34 (3~65) winsize 63
1449 19:52:33.873787
1450 19:52:33.876947 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1451 19:52:33.877019
1452 19:52:33.880155 [CATrainingPosCal] consider 1 rank data
1453 19:52:33.883360 u2DelayCellTimex100 = 270/100 ps
1454 19:52:33.886511 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1455 19:52:33.889951 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1456 19:52:33.896657 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1457 19:52:33.900203 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 19:52:33.903222 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 19:52:33.906563 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1460 19:52:33.906644
1461 19:52:33.909790 CA PerBit enable=1, Macro0, CA PI delay=34
1462 19:52:33.909870
1463 19:52:33.913285 [CBTSetCACLKResult] CA Dly = 34
1464 19:52:33.913365 CS Dly: 5 (0~36)
1465 19:52:33.916848 ==
1466 19:52:33.916931 Dram Type= 6, Freq= 0, CH_1, rank 1
1467 19:52:33.923437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1468 19:52:33.923518 ==
1469 19:52:33.926392 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1470 19:52:33.932698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1471 19:52:33.943446 [CA 0] Center 37 (6~68) winsize 63
1472 19:52:33.946191 [CA 1] Center 36 (6~67) winsize 62
1473 19:52:33.949378 [CA 2] Center 34 (4~65) winsize 62
1474 19:52:33.953119 [CA 3] Center 33 (3~64) winsize 62
1475 19:52:33.956301 [CA 4] Center 33 (3~64) winsize 62
1476 19:52:33.959845 [CA 5] Center 33 (3~64) winsize 62
1477 19:52:33.959951
1478 19:52:33.962495 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1479 19:52:33.962576
1480 19:52:33.965836 [CATrainingPosCal] consider 2 rank data
1481 19:52:33.969482 u2DelayCellTimex100 = 270/100 ps
1482 19:52:33.973152 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1483 19:52:33.976799 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1484 19:52:33.980594 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1485 19:52:33.984184 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1486 19:52:33.988145 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1487 19:52:33.991384 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1488 19:52:33.991465
1489 19:52:33.995799 CA PerBit enable=1, Macro0, CA PI delay=33
1490 19:52:33.995880
1491 19:52:33.999433 [CBTSetCACLKResult] CA Dly = 33
1492 19:52:33.999513 CS Dly: 5 (0~37)
1493 19:52:33.999576
1494 19:52:34.003198 ----->DramcWriteLeveling(PI) begin...
1495 19:52:34.003280 ==
1496 19:52:34.006557 Dram Type= 6, Freq= 0, CH_1, rank 0
1497 19:52:34.013430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1498 19:52:34.013516 ==
1499 19:52:34.016456 Write leveling (Byte 0): 25 => 25
1500 19:52:34.019828 Write leveling (Byte 1): 26 => 26
1501 19:52:34.019908 DramcWriteLeveling(PI) end<-----
1502 19:52:34.019972
1503 19:52:34.023196 ==
1504 19:52:34.026726 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 19:52:34.029801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 19:52:34.029882 ==
1507 19:52:34.033273 [Gating] SW mode calibration
1508 19:52:34.040111 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1509 19:52:34.042854 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1510 19:52:34.049486 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1511 19:52:34.053266 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1512 19:52:34.056361 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 19:52:34.063011 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 19:52:34.066303 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 19:52:34.069793 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 19:52:34.076328 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 19:52:34.079557 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 19:52:34.083005 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 19:52:34.089597 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 19:52:34.092772 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 19:52:34.096249 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 19:52:34.102850 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 19:52:34.106192 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 19:52:34.109101 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 19:52:34.116205 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 19:52:34.119410 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 19:52:34.122620 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1528 19:52:34.129264 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1529 19:52:34.132279 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 19:52:34.135759 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 19:52:34.142171 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 19:52:34.145669 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 19:52:34.148965 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 19:52:34.155542 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 19:52:34.159776 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1536 19:52:34.162818 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1537 19:52:34.165839 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 19:52:34.172294 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 19:52:34.175257 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 19:52:34.178876 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 19:52:34.185762 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 19:52:34.189147 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1543 19:52:34.192488 0 10 4 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 0)
1544 19:52:34.198948 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1545 19:52:34.202662 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 19:52:34.205840 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 19:52:34.211913 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 19:52:34.215423 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 19:52:34.218670 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 19:52:34.225091 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 19:52:34.228725 0 11 4 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
1552 19:52:34.231711 0 11 8 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
1553 19:52:34.238415 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 19:52:34.242388 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 19:52:34.245028 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 19:52:34.252293 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 19:52:34.255579 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 19:52:34.258327 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1559 19:52:34.265111 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1560 19:52:34.268682 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1561 19:52:34.271673 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 19:52:34.278717 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 19:52:34.282207 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 19:52:34.285140 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 19:52:34.291895 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 19:52:34.295118 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 19:52:34.298211 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 19:52:34.305165 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 19:52:34.308165 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 19:52:34.312342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 19:52:34.318290 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 19:52:34.321816 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 19:52:34.324739 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 19:52:34.331460 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 19:52:34.334881 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1576 19:52:34.338139 Total UI for P1: 0, mck2ui 16
1577 19:52:34.341732 best dqsien dly found for B0: ( 0, 14, 2)
1578 19:52:34.345328 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 19:52:34.348255 Total UI for P1: 0, mck2ui 16
1580 19:52:34.351251 best dqsien dly found for B1: ( 0, 14, 4)
1581 19:52:34.354994 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1582 19:52:34.357759 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1583 19:52:34.357839
1584 19:52:34.361200 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1585 19:52:34.367683 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1586 19:52:34.367765 [Gating] SW calibration Done
1587 19:52:34.367830 ==
1588 19:52:34.371410 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 19:52:34.378156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 19:52:34.378237 ==
1591 19:52:34.378302 RX Vref Scan: 0
1592 19:52:34.378361
1593 19:52:34.381365 RX Vref 0 -> 0, step: 1
1594 19:52:34.381445
1595 19:52:34.384845 RX Delay -130 -> 252, step: 16
1596 19:52:34.388155 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1597 19:52:34.391041 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1598 19:52:34.394207 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1599 19:52:34.401162 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1600 19:52:34.404561 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1601 19:52:34.407658 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1602 19:52:34.410948 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1603 19:52:34.414194 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1604 19:52:34.421020 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1605 19:52:34.424122 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1606 19:52:34.427793 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1607 19:52:34.431127 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1608 19:52:34.434394 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1609 19:52:34.440699 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1610 19:52:34.443886 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1611 19:52:34.447650 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1612 19:52:34.447731 ==
1613 19:52:34.450662 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 19:52:34.453905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 19:52:34.457215 ==
1616 19:52:34.457296 DQS Delay:
1617 19:52:34.457360 DQS0 = 0, DQS1 = 0
1618 19:52:34.460419 DQM Delay:
1619 19:52:34.460499 DQM0 = 88, DQM1 = 83
1620 19:52:34.463873 DQ Delay:
1621 19:52:34.463953 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1622 19:52:34.467068 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1623 19:52:34.470412 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1624 19:52:34.474035 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1625 19:52:34.477059
1626 19:52:34.477139
1627 19:52:34.477203 ==
1628 19:52:34.480524 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 19:52:34.483655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 19:52:34.483736 ==
1631 19:52:34.483800
1632 19:52:34.483858
1633 19:52:34.487104 TX Vref Scan disable
1634 19:52:34.487198 == TX Byte 0 ==
1635 19:52:34.493849 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1636 19:52:34.497548 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1637 19:52:34.497629 == TX Byte 1 ==
1638 19:52:34.503552 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1639 19:52:34.506953 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1640 19:52:34.507058 ==
1641 19:52:34.510037 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 19:52:34.513759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 19:52:34.513840 ==
1644 19:52:34.527201 TX Vref=22, minBit 0, minWin=27, winSum=442
1645 19:52:34.530759 TX Vref=24, minBit 2, minWin=27, winSum=447
1646 19:52:34.533701 TX Vref=26, minBit 4, minWin=27, winSum=452
1647 19:52:34.537643 TX Vref=28, minBit 4, minWin=27, winSum=454
1648 19:52:34.540607 TX Vref=30, minBit 6, minWin=27, winSum=457
1649 19:52:34.547382 TX Vref=32, minBit 0, minWin=27, winSum=453
1650 19:52:34.550553 [TxChooseVref] Worse bit 6, Min win 27, Win sum 457, Final Vref 30
1651 19:52:34.550626
1652 19:52:34.554476 Final TX Range 1 Vref 30
1653 19:52:34.554558
1654 19:52:34.554621 ==
1655 19:52:34.558089 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 19:52:34.561253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 19:52:34.561334 ==
1658 19:52:34.561398
1659 19:52:34.561457
1660 19:52:34.564494 TX Vref Scan disable
1661 19:52:34.567710 == TX Byte 0 ==
1662 19:52:34.571845 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1663 19:52:34.574400 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1664 19:52:34.577642 == TX Byte 1 ==
1665 19:52:34.581338 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1666 19:52:34.584906 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1667 19:52:34.584990
1668 19:52:34.587849 [DATLAT]
1669 19:52:34.587929 Freq=800, CH1 RK0
1670 19:52:34.587994
1671 19:52:34.591190 DATLAT Default: 0xa
1672 19:52:34.591270 0, 0xFFFF, sum = 0
1673 19:52:34.594713 1, 0xFFFF, sum = 0
1674 19:52:34.594795 2, 0xFFFF, sum = 0
1675 19:52:34.597553 3, 0xFFFF, sum = 0
1676 19:52:34.597635 4, 0xFFFF, sum = 0
1677 19:52:34.601057 5, 0xFFFF, sum = 0
1678 19:52:34.601139 6, 0xFFFF, sum = 0
1679 19:52:34.604515 7, 0xFFFF, sum = 0
1680 19:52:34.604597 8, 0xFFFF, sum = 0
1681 19:52:34.608231 9, 0x0, sum = 1
1682 19:52:34.608313 10, 0x0, sum = 2
1683 19:52:34.610816 11, 0x0, sum = 3
1684 19:52:34.610897 12, 0x0, sum = 4
1685 19:52:34.614220 best_step = 10
1686 19:52:34.614300
1687 19:52:34.614365 ==
1688 19:52:34.617522 Dram Type= 6, Freq= 0, CH_1, rank 0
1689 19:52:34.621188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1690 19:52:34.621269 ==
1691 19:52:34.624209 RX Vref Scan: 1
1692 19:52:34.624290
1693 19:52:34.624354 Set Vref Range= 32 -> 127
1694 19:52:34.624414
1695 19:52:34.628206 RX Vref 32 -> 127, step: 1
1696 19:52:34.628287
1697 19:52:34.630801 RX Delay -95 -> 252, step: 8
1698 19:52:34.630881
1699 19:52:34.634121 Set Vref, RX VrefLevel [Byte0]: 32
1700 19:52:34.637478 [Byte1]: 32
1701 19:52:34.637561
1702 19:52:34.640937 Set Vref, RX VrefLevel [Byte0]: 33
1703 19:52:34.644561 [Byte1]: 33
1704 19:52:34.648011
1705 19:52:34.648107 Set Vref, RX VrefLevel [Byte0]: 34
1706 19:52:34.651337 [Byte1]: 34
1707 19:52:34.655380
1708 19:52:34.655461 Set Vref, RX VrefLevel [Byte0]: 35
1709 19:52:34.658325 [Byte1]: 35
1710 19:52:34.662664
1711 19:52:34.662744 Set Vref, RX VrefLevel [Byte0]: 36
1712 19:52:34.665834 [Byte1]: 36
1713 19:52:34.670491
1714 19:52:34.670571 Set Vref, RX VrefLevel [Byte0]: 37
1715 19:52:34.673625 [Byte1]: 37
1716 19:52:34.678122
1717 19:52:34.678203 Set Vref, RX VrefLevel [Byte0]: 38
1718 19:52:34.681011 [Byte1]: 38
1719 19:52:34.685452
1720 19:52:34.685532 Set Vref, RX VrefLevel [Byte0]: 39
1721 19:52:34.688917 [Byte1]: 39
1722 19:52:34.693117
1723 19:52:34.693232 Set Vref, RX VrefLevel [Byte0]: 40
1724 19:52:34.696220 [Byte1]: 40
1725 19:52:34.700813
1726 19:52:34.700893 Set Vref, RX VrefLevel [Byte0]: 41
1727 19:52:34.704323 [Byte1]: 41
1728 19:52:34.708321
1729 19:52:34.708391 Set Vref, RX VrefLevel [Byte0]: 42
1730 19:52:34.711708 [Byte1]: 42
1731 19:52:34.715958
1732 19:52:34.716026 Set Vref, RX VrefLevel [Byte0]: 43
1733 19:52:34.719265 [Byte1]: 43
1734 19:52:34.723615
1735 19:52:34.723694 Set Vref, RX VrefLevel [Byte0]: 44
1736 19:52:34.726690 [Byte1]: 44
1737 19:52:34.730882
1738 19:52:34.730987 Set Vref, RX VrefLevel [Byte0]: 45
1739 19:52:34.734201 [Byte1]: 45
1740 19:52:34.738637
1741 19:52:34.738719 Set Vref, RX VrefLevel [Byte0]: 46
1742 19:52:34.742664 [Byte1]: 46
1743 19:52:34.746159
1744 19:52:34.746239 Set Vref, RX VrefLevel [Byte0]: 47
1745 19:52:34.750281 [Byte1]: 47
1746 19:52:34.753754
1747 19:52:34.753824 Set Vref, RX VrefLevel [Byte0]: 48
1748 19:52:34.757396 [Byte1]: 48
1749 19:52:34.761798
1750 19:52:34.761910 Set Vref, RX VrefLevel [Byte0]: 49
1751 19:52:34.765368 [Byte1]: 49
1752 19:52:34.769231
1753 19:52:34.769311 Set Vref, RX VrefLevel [Byte0]: 50
1754 19:52:34.772269 [Byte1]: 50
1755 19:52:34.776771
1756 19:52:34.776879 Set Vref, RX VrefLevel [Byte0]: 51
1757 19:52:34.779964 [Byte1]: 51
1758 19:52:34.784401
1759 19:52:34.784480 Set Vref, RX VrefLevel [Byte0]: 52
1760 19:52:34.787539 [Byte1]: 52
1761 19:52:34.792418
1762 19:52:34.792498 Set Vref, RX VrefLevel [Byte0]: 53
1763 19:52:34.795388 [Byte1]: 53
1764 19:52:34.799762
1765 19:52:34.799841 Set Vref, RX VrefLevel [Byte0]: 54
1766 19:52:34.802597 [Byte1]: 54
1767 19:52:34.807252
1768 19:52:34.807331 Set Vref, RX VrefLevel [Byte0]: 55
1769 19:52:34.810262 [Byte1]: 55
1770 19:52:34.814813
1771 19:52:34.814892 Set Vref, RX VrefLevel [Byte0]: 56
1772 19:52:34.818194 [Byte1]: 56
1773 19:52:34.822651
1774 19:52:34.822730 Set Vref, RX VrefLevel [Byte0]: 57
1775 19:52:34.826146 [Byte1]: 57
1776 19:52:34.830094
1777 19:52:34.830174 Set Vref, RX VrefLevel [Byte0]: 58
1778 19:52:34.833128 [Byte1]: 58
1779 19:52:34.837425
1780 19:52:34.837504 Set Vref, RX VrefLevel [Byte0]: 59
1781 19:52:34.840688 [Byte1]: 59
1782 19:52:34.845702
1783 19:52:34.845781 Set Vref, RX VrefLevel [Byte0]: 60
1784 19:52:34.848681 [Byte1]: 60
1785 19:52:34.852932
1786 19:52:34.853011 Set Vref, RX VrefLevel [Byte0]: 61
1787 19:52:34.855836 [Byte1]: 61
1788 19:52:34.860822
1789 19:52:34.860901 Set Vref, RX VrefLevel [Byte0]: 62
1790 19:52:34.863337 [Byte1]: 62
1791 19:52:34.867743
1792 19:52:34.867822 Set Vref, RX VrefLevel [Byte0]: 63
1793 19:52:34.871013 [Byte1]: 63
1794 19:52:34.875708
1795 19:52:34.875788 Set Vref, RX VrefLevel [Byte0]: 64
1796 19:52:34.878985 [Byte1]: 64
1797 19:52:34.883386
1798 19:52:34.883498 Set Vref, RX VrefLevel [Byte0]: 65
1799 19:52:34.886142 [Byte1]: 65
1800 19:52:34.890996
1801 19:52:34.891105 Set Vref, RX VrefLevel [Byte0]: 66
1802 19:52:34.894050 [Byte1]: 66
1803 19:52:34.899599
1804 19:52:34.899679 Set Vref, RX VrefLevel [Byte0]: 67
1805 19:52:34.901465 [Byte1]: 67
1806 19:52:34.905951
1807 19:52:34.906031 Set Vref, RX VrefLevel [Byte0]: 68
1808 19:52:34.909669 [Byte1]: 68
1809 19:52:34.913471
1810 19:52:34.913554 Set Vref, RX VrefLevel [Byte0]: 69
1811 19:52:34.916603 [Byte1]: 69
1812 19:52:34.920849
1813 19:52:34.920936 Set Vref, RX VrefLevel [Byte0]: 70
1814 19:52:34.924422 [Byte1]: 70
1815 19:52:34.928742
1816 19:52:34.928821 Set Vref, RX VrefLevel [Byte0]: 71
1817 19:52:34.932308 [Byte1]: 71
1818 19:52:34.936145
1819 19:52:34.936224 Set Vref, RX VrefLevel [Byte0]: 72
1820 19:52:34.939505 [Byte1]: 72
1821 19:52:34.943987
1822 19:52:34.944066 Set Vref, RX VrefLevel [Byte0]: 73
1823 19:52:34.947174 [Byte1]: 73
1824 19:52:34.952091
1825 19:52:34.952173 Set Vref, RX VrefLevel [Byte0]: 74
1826 19:52:34.954555 [Byte1]: 74
1827 19:52:34.959265
1828 19:52:34.959349 Set Vref, RX VrefLevel [Byte0]: 75
1829 19:52:34.962274 [Byte1]: 75
1830 19:52:34.966839
1831 19:52:34.966915 Final RX Vref Byte 0 = 54 to rank0
1832 19:52:34.969995 Final RX Vref Byte 1 = 53 to rank0
1833 19:52:34.973471 Final RX Vref Byte 0 = 54 to rank1
1834 19:52:34.976629 Final RX Vref Byte 1 = 53 to rank1==
1835 19:52:34.979750 Dram Type= 6, Freq= 0, CH_1, rank 0
1836 19:52:34.986397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1837 19:52:34.986480 ==
1838 19:52:34.986565 DQS Delay:
1839 19:52:34.990100 DQS0 = 0, DQS1 = 0
1840 19:52:34.990183 DQM Delay:
1841 19:52:34.990267 DQM0 = 85, DQM1 = 80
1842 19:52:34.993707 DQ Delay:
1843 19:52:34.996790 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1844 19:52:34.999725 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1845 19:52:35.003480 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1846 19:52:35.006428 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1847 19:52:35.006511
1848 19:52:35.006595
1849 19:52:35.013227 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f33, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
1850 19:52:35.016344 CH1 RK0: MR19=606, MR18=1F33
1851 19:52:35.022994 CH1_RK0: MR19=0x606, MR18=0x1F33, DQSOSC=396, MR23=63, INC=94, DEC=62
1852 19:52:35.023083
1853 19:52:35.026304 ----->DramcWriteLeveling(PI) begin...
1854 19:52:35.026389 ==
1855 19:52:35.029725 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 19:52:35.032865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 19:52:35.032939 ==
1858 19:52:35.036523 Write leveling (Byte 0): 26 => 26
1859 19:52:35.039649 Write leveling (Byte 1): 28 => 28
1860 19:52:35.043066 DramcWriteLeveling(PI) end<-----
1861 19:52:35.043185
1862 19:52:35.043249 ==
1863 19:52:35.046313 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 19:52:35.049406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 19:52:35.049481 ==
1866 19:52:35.052847 [Gating] SW mode calibration
1867 19:52:35.059640 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1868 19:52:35.066409 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1869 19:52:35.069602 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1870 19:52:35.072981 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1871 19:52:35.079908 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 19:52:35.082647 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 19:52:35.086380 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 19:52:35.092967 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 19:52:35.096172 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 19:52:35.099594 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 19:52:35.106218 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 19:52:35.109325 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 19:52:35.112601 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 19:52:35.119487 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 19:52:35.122604 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 19:52:35.126390 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 19:52:35.132494 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 19:52:35.135952 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 19:52:35.138994 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1886 19:52:35.145703 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1887 19:52:35.148930 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 19:52:35.152723 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 19:52:35.159248 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 19:52:35.162372 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 19:52:35.165795 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 19:52:35.171989 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 19:52:35.176032 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 19:52:35.178848 0 9 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1895 19:52:35.185796 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1896 19:52:35.189085 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 19:52:35.191999 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 19:52:35.198734 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 19:52:35.202391 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 19:52:35.205646 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 19:52:35.212033 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 19:52:35.216021 0 10 4 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
1903 19:52:35.218663 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1904 19:52:35.225644 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 19:52:35.228810 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 19:52:35.231740 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 19:52:35.238563 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 19:52:35.242044 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 19:52:35.244978 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 19:52:35.248534 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
1911 19:52:35.255004 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1912 19:52:35.258354 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 19:52:35.261828 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 19:52:35.268358 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 19:52:35.271929 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 19:52:35.274988 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 19:52:35.281587 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 19:52:35.285743 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1919 19:52:35.288369 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 19:52:35.295187 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 19:52:35.298467 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 19:52:35.301693 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 19:52:35.308076 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 19:52:35.311424 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 19:52:35.314700 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 19:52:35.321367 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 19:52:35.325141 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 19:52:35.328879 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 19:52:35.335192 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 19:52:35.338507 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 19:52:35.342018 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 19:52:35.348261 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 19:52:35.351376 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1934 19:52:35.354616 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1935 19:52:35.358115 Total UI for P1: 0, mck2ui 16
1936 19:52:35.362159 best dqsien dly found for B0: ( 0, 14, 0)
1937 19:52:35.367957 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1938 19:52:35.371445 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 19:52:35.374676 Total UI for P1: 0, mck2ui 16
1940 19:52:35.378313 best dqsien dly found for B1: ( 0, 14, 6)
1941 19:52:35.381417 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1942 19:52:35.384454 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1943 19:52:35.384523
1944 19:52:35.388166 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1945 19:52:35.391356 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1946 19:52:35.394477 [Gating] SW calibration Done
1947 19:52:35.394544 ==
1948 19:52:35.397736 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 19:52:35.400882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 19:52:35.400948 ==
1951 19:52:35.404609 RX Vref Scan: 0
1952 19:52:35.404675
1953 19:52:35.407852 RX Vref 0 -> 0, step: 1
1954 19:52:35.407921
1955 19:52:35.407984 RX Delay -130 -> 252, step: 16
1956 19:52:35.414637 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1957 19:52:35.417816 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1958 19:52:35.420962 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1959 19:52:35.424579 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1960 19:52:35.427771 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1961 19:52:35.434619 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1962 19:52:35.437729 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1963 19:52:35.440501 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1964 19:52:35.443820 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1965 19:52:35.447574 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1966 19:52:35.454198 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1967 19:52:35.457225 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1968 19:52:35.460929 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1969 19:52:35.464106 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1970 19:52:35.470597 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1971 19:52:35.474291 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1972 19:52:35.474371 ==
1973 19:52:35.477032 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 19:52:35.480874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 19:52:35.480947 ==
1976 19:52:35.483773 DQS Delay:
1977 19:52:35.483842 DQS0 = 0, DQS1 = 0
1978 19:52:35.483904 DQM Delay:
1979 19:52:35.486951 DQM0 = 79, DQM1 = 79
1980 19:52:35.487047 DQ Delay:
1981 19:52:35.490676 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1982 19:52:35.493786 DQ4 =77, DQ5 =85, DQ6 =85, DQ7 =77
1983 19:52:35.497226 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1984 19:52:35.500359 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1985 19:52:35.500426
1986 19:52:35.500488
1987 19:52:35.500546 ==
1988 19:52:35.503949 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 19:52:35.509951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 19:52:35.510026 ==
1991 19:52:35.510088
1992 19:52:35.510144
1993 19:52:35.510198 TX Vref Scan disable
1994 19:52:35.513713 == TX Byte 0 ==
1995 19:52:35.517262 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1996 19:52:35.520262 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1997 19:52:35.523822 == TX Byte 1 ==
1998 19:52:35.526870 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1999 19:52:35.533626 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2000 19:52:35.533703 ==
2001 19:52:35.537773 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 19:52:35.540265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 19:52:35.540345 ==
2004 19:52:35.553020 TX Vref=22, minBit 1, minWin=27, winSum=448
2005 19:52:35.556271 TX Vref=24, minBit 1, minWin=27, winSum=450
2006 19:52:35.559651 TX Vref=26, minBit 0, minWin=28, winSum=453
2007 19:52:35.562776 TX Vref=28, minBit 1, minWin=27, winSum=453
2008 19:52:35.566637 TX Vref=30, minBit 0, minWin=28, winSum=456
2009 19:52:35.569603 TX Vref=32, minBit 5, minWin=27, winSum=454
2010 19:52:35.576508 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
2011 19:52:35.576593
2012 19:52:35.579605 Final TX Range 1 Vref 30
2013 19:52:35.579686
2014 19:52:35.579749 ==
2015 19:52:35.583753 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 19:52:35.586363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 19:52:35.586446 ==
2018 19:52:35.589580
2019 19:52:35.589684
2020 19:52:35.589775 TX Vref Scan disable
2021 19:52:35.592788 == TX Byte 0 ==
2022 19:52:35.596521 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2023 19:52:35.602968 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2024 19:52:35.603082 == TX Byte 1 ==
2025 19:52:35.605883 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2026 19:52:35.612566 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2027 19:52:35.612670
2028 19:52:35.612748 [DATLAT]
2029 19:52:35.612841 Freq=800, CH1 RK1
2030 19:52:35.612908
2031 19:52:35.615851 DATLAT Default: 0xa
2032 19:52:35.615945 0, 0xFFFF, sum = 0
2033 19:52:35.619211 1, 0xFFFF, sum = 0
2034 19:52:35.619324 2, 0xFFFF, sum = 0
2035 19:52:35.622711 3, 0xFFFF, sum = 0
2036 19:52:35.625927 4, 0xFFFF, sum = 0
2037 19:52:35.626026 5, 0xFFFF, sum = 0
2038 19:52:35.629164 6, 0xFFFF, sum = 0
2039 19:52:35.629259 7, 0xFFFF, sum = 0
2040 19:52:35.632693 8, 0xFFFF, sum = 0
2041 19:52:35.632798 9, 0x0, sum = 1
2042 19:52:35.636039 10, 0x0, sum = 2
2043 19:52:35.636121 11, 0x0, sum = 3
2044 19:52:35.636198 12, 0x0, sum = 4
2045 19:52:35.639440 best_step = 10
2046 19:52:35.639510
2047 19:52:35.639570 ==
2048 19:52:35.642407 Dram Type= 6, Freq= 0, CH_1, rank 1
2049 19:52:35.646208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2050 19:52:35.646347 ==
2051 19:52:35.649206 RX Vref Scan: 0
2052 19:52:35.649281
2053 19:52:35.649343 RX Vref 0 -> 0, step: 1
2054 19:52:35.652743
2055 19:52:35.652817 RX Delay -95 -> 252, step: 8
2056 19:52:35.659312 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2057 19:52:35.662859 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2058 19:52:35.666206 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2059 19:52:35.669438 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2060 19:52:35.672807 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2061 19:52:35.679632 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2062 19:52:35.682895 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2063 19:52:35.686027 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2064 19:52:35.689363 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2065 19:52:35.692516 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2066 19:52:35.700090 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2067 19:52:35.702934 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2068 19:52:35.705774 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2069 19:52:35.708891 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2070 19:52:35.716368 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2071 19:52:35.718937 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2072 19:52:35.719042 ==
2073 19:52:35.722951 Dram Type= 6, Freq= 0, CH_1, rank 1
2074 19:52:35.725657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2075 19:52:35.725759 ==
2076 19:52:35.728988 DQS Delay:
2077 19:52:35.729083 DQS0 = 0, DQS1 = 0
2078 19:52:35.729171 DQM Delay:
2079 19:52:35.732517 DQM0 = 86, DQM1 = 81
2080 19:52:35.732587 DQ Delay:
2081 19:52:35.735612 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2082 19:52:35.739632 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2083 19:52:35.742270 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2084 19:52:35.745550 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2085 19:52:35.745647
2086 19:52:35.745734
2087 19:52:35.755752 [DQSOSCAuto] RK1, (LSB)MR18= 0x223e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2088 19:52:35.755867 CH1 RK1: MR19=606, MR18=223E
2089 19:52:35.762480 CH1_RK1: MR19=0x606, MR18=0x223E, DQSOSC=394, MR23=63, INC=95, DEC=63
2090 19:52:35.765839 [RxdqsGatingPostProcess] freq 800
2091 19:52:35.772290 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2092 19:52:35.775873 Pre-setting of DQS Precalculation
2093 19:52:35.778980 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2094 19:52:35.785543 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2095 19:52:35.795526 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2096 19:52:35.795608
2097 19:52:35.795671
2098 19:52:35.798731 [Calibration Summary] 1600 Mbps
2099 19:52:35.798817 CH 0, Rank 0
2100 19:52:35.802072 SW Impedance : PASS
2101 19:52:35.802153 DUTY Scan : NO K
2102 19:52:35.806526 ZQ Calibration : PASS
2103 19:52:35.806607 Jitter Meter : NO K
2104 19:52:35.809519 CBT Training : PASS
2105 19:52:35.811945 Write leveling : PASS
2106 19:52:35.812026 RX DQS gating : PASS
2107 19:52:35.815480 RX DQ/DQS(RDDQC) : PASS
2108 19:52:35.818757 TX DQ/DQS : PASS
2109 19:52:35.818865 RX DATLAT : PASS
2110 19:52:35.822678 RX DQ/DQS(Engine): PASS
2111 19:52:35.825307 TX OE : NO K
2112 19:52:35.825388 All Pass.
2113 19:52:35.825453
2114 19:52:35.825512 CH 0, Rank 1
2115 19:52:35.829049 SW Impedance : PASS
2116 19:52:35.832208 DUTY Scan : NO K
2117 19:52:35.832289 ZQ Calibration : PASS
2118 19:52:35.835286 Jitter Meter : NO K
2119 19:52:35.838744 CBT Training : PASS
2120 19:52:35.838825 Write leveling : PASS
2121 19:52:35.842548 RX DQS gating : PASS
2122 19:52:35.845126 RX DQ/DQS(RDDQC) : PASS
2123 19:52:35.845207 TX DQ/DQS : PASS
2124 19:52:35.848628 RX DATLAT : PASS
2125 19:52:35.848734 RX DQ/DQS(Engine): PASS
2126 19:52:35.852228 TX OE : NO K
2127 19:52:35.852309 All Pass.
2128 19:52:35.852373
2129 19:52:35.855889 CH 1, Rank 0
2130 19:52:35.855969 SW Impedance : PASS
2131 19:52:35.858566 DUTY Scan : NO K
2132 19:52:35.861952 ZQ Calibration : PASS
2133 19:52:35.862033 Jitter Meter : NO K
2134 19:52:35.865260 CBT Training : PASS
2135 19:52:35.869166 Write leveling : PASS
2136 19:52:35.869246 RX DQS gating : PASS
2137 19:52:35.871660 RX DQ/DQS(RDDQC) : PASS
2138 19:52:35.875192 TX DQ/DQS : PASS
2139 19:52:35.875274 RX DATLAT : PASS
2140 19:52:35.878445 RX DQ/DQS(Engine): PASS
2141 19:52:35.881998 TX OE : NO K
2142 19:52:35.882079 All Pass.
2143 19:52:35.882143
2144 19:52:35.882202 CH 1, Rank 1
2145 19:52:35.885431 SW Impedance : PASS
2146 19:52:35.888689 DUTY Scan : NO K
2147 19:52:35.888770 ZQ Calibration : PASS
2148 19:52:35.891729 Jitter Meter : NO K
2149 19:52:35.894991 CBT Training : PASS
2150 19:52:35.895133 Write leveling : PASS
2151 19:52:35.898424 RX DQS gating : PASS
2152 19:52:35.901821 RX DQ/DQS(RDDQC) : PASS
2153 19:52:35.901918 TX DQ/DQS : PASS
2154 19:52:35.905038 RX DATLAT : PASS
2155 19:52:35.905110 RX DQ/DQS(Engine): PASS
2156 19:52:35.908618 TX OE : NO K
2157 19:52:35.908759 All Pass.
2158 19:52:35.908839
2159 19:52:35.911633 DramC Write-DBI off
2160 19:52:35.915039 PER_BANK_REFRESH: Hybrid Mode
2161 19:52:35.915128 TX_TRACKING: ON
2162 19:52:35.918728 [GetDramInforAfterCalByMRR] Vendor 6.
2163 19:52:35.921745 [GetDramInforAfterCalByMRR] Revision 606.
2164 19:52:35.928507 [GetDramInforAfterCalByMRR] Revision 2 0.
2165 19:52:35.928584 MR0 0x3b3b
2166 19:52:35.928664 MR8 0x5151
2167 19:52:35.932226 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 19:52:35.932295
2169 19:52:35.934955 MR0 0x3b3b
2170 19:52:35.935050 MR8 0x5151
2171 19:52:35.938280 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2172 19:52:35.938378
2173 19:52:35.948404 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2174 19:52:35.951334 [FAST_K] Save calibration result to emmc
2175 19:52:35.954843 [FAST_K] Save calibration result to emmc
2176 19:52:35.958105 dram_init: config_dvfs: 1
2177 19:52:35.961794 dramc_set_vcore_voltage set vcore to 662500
2178 19:52:35.961883 Read voltage for 1200, 2
2179 19:52:35.964917 Vio18 = 0
2180 19:52:35.964989 Vcore = 662500
2181 19:52:35.965050 Vdram = 0
2182 19:52:35.968127 Vddq = 0
2183 19:52:35.968197 Vmddr = 0
2184 19:52:35.971522 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2185 19:52:35.978429 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2186 19:52:35.981502 MEM_TYPE=3, freq_sel=15
2187 19:52:35.985392 sv_algorithm_assistance_LP4_1600
2188 19:52:35.988095 ============ PULL DRAM RESETB DOWN ============
2189 19:52:35.991459 ========== PULL DRAM RESETB DOWN end =========
2190 19:52:35.998093 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2191 19:52:36.001495 ===================================
2192 19:52:36.001566 LPDDR4 DRAM CONFIGURATION
2193 19:52:36.004729 ===================================
2194 19:52:36.008317 EX_ROW_EN[0] = 0x0
2195 19:52:36.008398 EX_ROW_EN[1] = 0x0
2196 19:52:36.011257 LP4Y_EN = 0x0
2197 19:52:36.014832 WORK_FSP = 0x0
2198 19:52:36.014932 WL = 0x4
2199 19:52:36.017897 RL = 0x4
2200 19:52:36.017994 BL = 0x2
2201 19:52:36.021324 RPST = 0x0
2202 19:52:36.021422 RD_PRE = 0x0
2203 19:52:36.024722 WR_PRE = 0x1
2204 19:52:36.024788 WR_PST = 0x0
2205 19:52:36.028423 DBI_WR = 0x0
2206 19:52:36.028517 DBI_RD = 0x0
2207 19:52:36.031808 OTF = 0x1
2208 19:52:36.034717 ===================================
2209 19:52:36.037723 ===================================
2210 19:52:36.037810 ANA top config
2211 19:52:36.041430 ===================================
2212 19:52:36.044353 DLL_ASYNC_EN = 0
2213 19:52:36.047603 ALL_SLAVE_EN = 0
2214 19:52:36.047713 NEW_RANK_MODE = 1
2215 19:52:36.050820 DLL_IDLE_MODE = 1
2216 19:52:36.054292 LP45_APHY_COMB_EN = 1
2217 19:52:36.057761 TX_ODT_DIS = 1
2218 19:52:36.060854 NEW_8X_MODE = 1
2219 19:52:36.064242 ===================================
2220 19:52:36.067722 ===================================
2221 19:52:36.067795 data_rate = 2400
2222 19:52:36.071033 CKR = 1
2223 19:52:36.074359 DQ_P2S_RATIO = 8
2224 19:52:36.077348 ===================================
2225 19:52:36.081259 CA_P2S_RATIO = 8
2226 19:52:36.084095 DQ_CA_OPEN = 0
2227 19:52:36.087606 DQ_SEMI_OPEN = 0
2228 19:52:36.087677 CA_SEMI_OPEN = 0
2229 19:52:36.090941 CA_FULL_RATE = 0
2230 19:52:36.094176 DQ_CKDIV4_EN = 0
2231 19:52:36.097525 CA_CKDIV4_EN = 0
2232 19:52:36.100556 CA_PREDIV_EN = 0
2233 19:52:36.103911 PH8_DLY = 17
2234 19:52:36.104009 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2235 19:52:36.107297 DQ_AAMCK_DIV = 4
2236 19:52:36.110726 CA_AAMCK_DIV = 4
2237 19:52:36.114610 CA_ADMCK_DIV = 4
2238 19:52:36.117722 DQ_TRACK_CA_EN = 0
2239 19:52:36.120570 CA_PICK = 1200
2240 19:52:36.123963 CA_MCKIO = 1200
2241 19:52:36.124063 MCKIO_SEMI = 0
2242 19:52:36.127523 PLL_FREQ = 2366
2243 19:52:36.130865 DQ_UI_PI_RATIO = 32
2244 19:52:36.134105 CA_UI_PI_RATIO = 0
2245 19:52:36.137469 ===================================
2246 19:52:36.140705 ===================================
2247 19:52:36.143944 memory_type:LPDDR4
2248 19:52:36.144024 GP_NUM : 10
2249 19:52:36.147651 SRAM_EN : 1
2250 19:52:36.147734 MD32_EN : 0
2251 19:52:36.150812 ===================================
2252 19:52:36.154087 [ANA_INIT] >>>>>>>>>>>>>>
2253 19:52:36.157458 <<<<<< [CONFIGURE PHASE]: ANA_TX
2254 19:52:36.160676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2255 19:52:36.164293 ===================================
2256 19:52:36.167682 data_rate = 2400,PCW = 0X5b00
2257 19:52:36.171023 ===================================
2258 19:52:36.174286 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2259 19:52:36.180898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2260 19:52:36.184246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 19:52:36.191251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2262 19:52:36.194965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2263 19:52:36.197481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2264 19:52:36.197565 [ANA_INIT] flow start
2265 19:52:36.200763 [ANA_INIT] PLL >>>>>>>>
2266 19:52:36.204859 [ANA_INIT] PLL <<<<<<<<
2267 19:52:36.204942 [ANA_INIT] MIDPI >>>>>>>>
2268 19:52:36.207557 [ANA_INIT] MIDPI <<<<<<<<
2269 19:52:36.210695 [ANA_INIT] DLL >>>>>>>>
2270 19:52:36.210778 [ANA_INIT] DLL <<<<<<<<
2271 19:52:36.214415 [ANA_INIT] flow end
2272 19:52:36.217295 ============ LP4 DIFF to SE enter ============
2273 19:52:36.223799 ============ LP4 DIFF to SE exit ============
2274 19:52:36.223883 [ANA_INIT] <<<<<<<<<<<<<
2275 19:52:36.227022 [Flow] Enable top DCM control >>>>>
2276 19:52:36.230135 [Flow] Enable top DCM control <<<<<
2277 19:52:36.233722 Enable DLL master slave shuffle
2278 19:52:36.240543 ==============================================================
2279 19:52:36.240627 Gating Mode config
2280 19:52:36.246843 ==============================================================
2281 19:52:36.250378 Config description:
2282 19:52:36.256905 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2283 19:52:36.264009 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2284 19:52:36.270684 SELPH_MODE 0: By rank 1: By Phase
2285 19:52:36.274023 ==============================================================
2286 19:52:36.277029 GAT_TRACK_EN = 1
2287 19:52:36.280424 RX_GATING_MODE = 2
2288 19:52:36.284173 RX_GATING_TRACK_MODE = 2
2289 19:52:36.287060 SELPH_MODE = 1
2290 19:52:36.290373 PICG_EARLY_EN = 1
2291 19:52:36.293823 VALID_LAT_VALUE = 1
2292 19:52:36.300382 ==============================================================
2293 19:52:36.304187 Enter into Gating configuration >>>>
2294 19:52:36.307297 Exit from Gating configuration <<<<
2295 19:52:36.310351 Enter into DVFS_PRE_config >>>>>
2296 19:52:36.320629 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2297 19:52:36.323636 Exit from DVFS_PRE_config <<<<<
2298 19:52:36.326924 Enter into PICG configuration >>>>
2299 19:52:36.330417 Exit from PICG configuration <<<<
2300 19:52:36.333906 [RX_INPUT] configuration >>>>>
2301 19:52:36.333989 [RX_INPUT] configuration <<<<<
2302 19:52:36.340552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2303 19:52:36.346815 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2304 19:52:36.350660 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 19:52:36.357028 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 19:52:36.363502 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 19:52:36.370313 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 19:52:36.373867 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2309 19:52:36.377146 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2310 19:52:36.383667 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2311 19:52:36.386991 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2312 19:52:36.390015 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2313 19:52:36.396557 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2314 19:52:36.399917 ===================================
2315 19:52:36.399986 LPDDR4 DRAM CONFIGURATION
2316 19:52:36.403269 ===================================
2317 19:52:36.406646 EX_ROW_EN[0] = 0x0
2318 19:52:36.406739 EX_ROW_EN[1] = 0x0
2319 19:52:36.409824 LP4Y_EN = 0x0
2320 19:52:36.409919 WORK_FSP = 0x0
2321 19:52:36.413533 WL = 0x4
2322 19:52:36.413603 RL = 0x4
2323 19:52:36.417087 BL = 0x2
2324 19:52:36.420024 RPST = 0x0
2325 19:52:36.420092 RD_PRE = 0x0
2326 19:52:36.423108 WR_PRE = 0x1
2327 19:52:36.423204 WR_PST = 0x0
2328 19:52:36.426803 DBI_WR = 0x0
2329 19:52:36.426898 DBI_RD = 0x0
2330 19:52:36.430044 OTF = 0x1
2331 19:52:36.433168 ===================================
2332 19:52:36.436407 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2333 19:52:36.440172 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2334 19:52:36.443231 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2335 19:52:36.446617 ===================================
2336 19:52:36.450078 LPDDR4 DRAM CONFIGURATION
2337 19:52:36.453812 ===================================
2338 19:52:36.456278 EX_ROW_EN[0] = 0x10
2339 19:52:36.456348 EX_ROW_EN[1] = 0x0
2340 19:52:36.459794 LP4Y_EN = 0x0
2341 19:52:36.459869 WORK_FSP = 0x0
2342 19:52:36.463166 WL = 0x4
2343 19:52:36.463264 RL = 0x4
2344 19:52:36.466704 BL = 0x2
2345 19:52:36.466801 RPST = 0x0
2346 19:52:36.469592 RD_PRE = 0x0
2347 19:52:36.469690 WR_PRE = 0x1
2348 19:52:36.474101 WR_PST = 0x0
2349 19:52:36.476384 DBI_WR = 0x0
2350 19:52:36.476484 DBI_RD = 0x0
2351 19:52:36.479621 OTF = 0x1
2352 19:52:36.483220 ===================================
2353 19:52:36.486397 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2354 19:52:36.486467 ==
2355 19:52:36.489402 Dram Type= 6, Freq= 0, CH_0, rank 0
2356 19:52:36.496286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 19:52:36.496387 ==
2358 19:52:36.499649 [Duty_Offset_Calibration]
2359 19:52:36.499718 B0:2 B1:0 CA:4
2360 19:52:36.499780
2361 19:52:36.502869 [DutyScan_Calibration_Flow] k_type=0
2362 19:52:36.512136
2363 19:52:36.512216 ==CLK 0==
2364 19:52:36.515233 Final CLK duty delay cell = 0
2365 19:52:36.518777 [0] MAX Duty = 5156%(X100), DQS PI = 14
2366 19:52:36.522033 [0] MIN Duty = 5000%(X100), DQS PI = 8
2367 19:52:36.522115 [0] AVG Duty = 5078%(X100)
2368 19:52:36.525290
2369 19:52:36.528533 CH0 CLK Duty spec in!! Max-Min= 156%
2370 19:52:36.531720 [DutyScan_Calibration_Flow] ====Done====
2371 19:52:36.531800
2372 19:52:36.535255 [DutyScan_Calibration_Flow] k_type=1
2373 19:52:36.551538
2374 19:52:36.551620 ==DQS 0 ==
2375 19:52:36.555190 Final DQS duty delay cell = 0
2376 19:52:36.557924 [0] MAX Duty = 5156%(X100), DQS PI = 14
2377 19:52:36.561687 [0] MIN Duty = 5093%(X100), DQS PI = 44
2378 19:52:36.564771 [0] AVG Duty = 5124%(X100)
2379 19:52:36.564849
2380 19:52:36.564913 ==DQS 1 ==
2381 19:52:36.567886 Final DQS duty delay cell = 0
2382 19:52:36.571775 [0] MAX Duty = 5125%(X100), DQS PI = 48
2383 19:52:36.575183 [0] MIN Duty = 4969%(X100), DQS PI = 62
2384 19:52:36.577833 [0] AVG Duty = 5047%(X100)
2385 19:52:36.577930
2386 19:52:36.581261 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2387 19:52:36.581354
2388 19:52:36.584506 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2389 19:52:36.588161 [DutyScan_Calibration_Flow] ====Done====
2390 19:52:36.588252
2391 19:52:36.590996 [DutyScan_Calibration_Flow] k_type=3
2392 19:52:36.608404
2393 19:52:36.608503 ==DQM 0 ==
2394 19:52:36.611633 Final DQM duty delay cell = 0
2395 19:52:36.614993 [0] MAX Duty = 5125%(X100), DQS PI = 20
2396 19:52:36.617966 [0] MIN Duty = 4844%(X100), DQS PI = 56
2397 19:52:36.618058 [0] AVG Duty = 4984%(X100)
2398 19:52:36.621114
2399 19:52:36.621183 ==DQM 1 ==
2400 19:52:36.624687 Final DQM duty delay cell = 0
2401 19:52:36.627931 [0] MAX Duty = 4969%(X100), DQS PI = 0
2402 19:52:36.631283 [0] MIN Duty = 4875%(X100), DQS PI = 20
2403 19:52:36.634498 [0] AVG Duty = 4922%(X100)
2404 19:52:36.634589
2405 19:52:36.638094 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2406 19:52:36.638165
2407 19:52:36.641330 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2408 19:52:36.644560 [DutyScan_Calibration_Flow] ====Done====
2409 19:52:36.644650
2410 19:52:36.647721 [DutyScan_Calibration_Flow] k_type=2
2411 19:52:36.664560
2412 19:52:36.664636 ==DQ 0 ==
2413 19:52:36.668121 Final DQ duty delay cell = 0
2414 19:52:36.671054 [0] MAX Duty = 5125%(X100), DQS PI = 18
2415 19:52:36.674155 [0] MIN Duty = 5000%(X100), DQS PI = 8
2416 19:52:36.674250 [0] AVG Duty = 5062%(X100)
2417 19:52:36.678194
2418 19:52:36.678265 ==DQ 1 ==
2419 19:52:36.681073 Final DQ duty delay cell = 0
2420 19:52:36.684741 [0] MAX Duty = 5156%(X100), DQS PI = 4
2421 19:52:36.687907 [0] MIN Duty = 4938%(X100), DQS PI = 16
2422 19:52:36.687975 [0] AVG Duty = 5047%(X100)
2423 19:52:36.688034
2424 19:52:36.690881 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2425 19:52:36.694662
2426 19:52:36.697788 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2427 19:52:36.700739 [DutyScan_Calibration_Flow] ====Done====
2428 19:52:36.700807 ==
2429 19:52:36.703808 Dram Type= 6, Freq= 0, CH_1, rank 0
2430 19:52:36.707238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2431 19:52:36.707335 ==
2432 19:52:36.710776 [Duty_Offset_Calibration]
2433 19:52:36.710846 B0:0 B1:-1 CA:3
2434 19:52:36.710914
2435 19:52:36.714191 [DutyScan_Calibration_Flow] k_type=0
2436 19:52:36.723401
2437 19:52:36.723483 ==CLK 0==
2438 19:52:36.727642 Final CLK duty delay cell = -4
2439 19:52:36.730221 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2440 19:52:36.733504 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2441 19:52:36.736925 [-4] AVG Duty = 4938%(X100)
2442 19:52:36.737006
2443 19:52:36.740210 CH1 CLK Duty spec in!! Max-Min= 124%
2444 19:52:36.743395 [DutyScan_Calibration_Flow] ====Done====
2445 19:52:36.743476
2446 19:52:36.746974 [DutyScan_Calibration_Flow] k_type=1
2447 19:52:36.762709
2448 19:52:36.762789 ==DQS 0 ==
2449 19:52:36.765494 Final DQS duty delay cell = 0
2450 19:52:36.769121 [0] MAX Duty = 5156%(X100), DQS PI = 18
2451 19:52:36.772309 [0] MIN Duty = 4907%(X100), DQS PI = 38
2452 19:52:36.775448 [0] AVG Duty = 5031%(X100)
2453 19:52:36.775529
2454 19:52:36.775593 ==DQS 1 ==
2455 19:52:36.778706 Final DQS duty delay cell = -4
2456 19:52:36.782248 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2457 19:52:36.785328 [-4] MIN Duty = 4875%(X100), DQS PI = 20
2458 19:52:36.788702 [-4] AVG Duty = 4953%(X100)
2459 19:52:36.788782
2460 19:52:36.792003 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2461 19:52:36.792084
2462 19:52:36.795449 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2463 19:52:36.798646 [DutyScan_Calibration_Flow] ====Done====
2464 19:52:36.798726
2465 19:52:36.802032 [DutyScan_Calibration_Flow] k_type=3
2466 19:52:36.819098
2467 19:52:36.819180 ==DQM 0 ==
2468 19:52:36.822423 Final DQM duty delay cell = 0
2469 19:52:36.825829 [0] MAX Duty = 5031%(X100), DQS PI = 26
2470 19:52:36.828797 [0] MIN Duty = 4813%(X100), DQS PI = 38
2471 19:52:36.832295 [0] AVG Duty = 4922%(X100)
2472 19:52:36.832376
2473 19:52:36.832440 ==DQM 1 ==
2474 19:52:36.835748 Final DQM duty delay cell = 0
2475 19:52:36.839326 [0] MAX Duty = 5000%(X100), DQS PI = 34
2476 19:52:36.842334 [0] MIN Duty = 4844%(X100), DQS PI = 0
2477 19:52:36.845201 [0] AVG Duty = 4922%(X100)
2478 19:52:36.845282
2479 19:52:36.849032 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2480 19:52:36.849114
2481 19:52:36.852370 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2482 19:52:36.856027 [DutyScan_Calibration_Flow] ====Done====
2483 19:52:36.856109
2484 19:52:36.858748 [DutyScan_Calibration_Flow] k_type=2
2485 19:52:36.874594
2486 19:52:36.874710 ==DQ 0 ==
2487 19:52:36.878094 Final DQ duty delay cell = -4
2488 19:52:36.881119 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2489 19:52:36.884527 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2490 19:52:36.888227 [-4] AVG Duty = 4922%(X100)
2491 19:52:36.888301
2492 19:52:36.888363 ==DQ 1 ==
2493 19:52:36.891243 Final DQ duty delay cell = 0
2494 19:52:36.894629 [0] MAX Duty = 5031%(X100), DQS PI = 32
2495 19:52:36.898087 [0] MIN Duty = 4844%(X100), DQS PI = 62
2496 19:52:36.901336 [0] AVG Duty = 4937%(X100)
2497 19:52:36.901434
2498 19:52:36.904349 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2499 19:52:36.904419
2500 19:52:36.907847 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2501 19:52:36.911605 [DutyScan_Calibration_Flow] ====Done====
2502 19:52:36.914665 nWR fixed to 30
2503 19:52:36.914764 [ModeRegInit_LP4] CH0 RK0
2504 19:52:36.918143 [ModeRegInit_LP4] CH0 RK1
2505 19:52:36.921246 [ModeRegInit_LP4] CH1 RK0
2506 19:52:36.924685 [ModeRegInit_LP4] CH1 RK1
2507 19:52:36.924756 match AC timing 7
2508 19:52:36.930857 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2509 19:52:36.934181 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2510 19:52:36.937524 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2511 19:52:36.944237 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2512 19:52:36.947658 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2513 19:52:36.947756 ==
2514 19:52:36.951590 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 19:52:36.954362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 19:52:36.954461 ==
2517 19:52:36.960834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2518 19:52:36.967340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2519 19:52:36.975301 [CA 0] Center 39 (9~70) winsize 62
2520 19:52:36.978405 [CA 1] Center 39 (9~69) winsize 61
2521 19:52:36.981737 [CA 2] Center 35 (5~66) winsize 62
2522 19:52:36.984817 [CA 3] Center 35 (5~66) winsize 62
2523 19:52:36.988398 [CA 4] Center 33 (3~64) winsize 62
2524 19:52:36.991496 [CA 5] Center 33 (3~63) winsize 61
2525 19:52:36.991567
2526 19:52:36.994839 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2527 19:52:36.994937
2528 19:52:36.997994 [CATrainingPosCal] consider 1 rank data
2529 19:52:37.001548 u2DelayCellTimex100 = 270/100 ps
2530 19:52:37.005183 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2531 19:52:37.011734 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2532 19:52:37.014681 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2533 19:52:37.018305 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2534 19:52:37.021412 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2535 19:52:37.024427 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2536 19:52:37.024511
2537 19:52:37.027937 CA PerBit enable=1, Macro0, CA PI delay=33
2538 19:52:37.028021
2539 19:52:37.031260 [CBTSetCACLKResult] CA Dly = 33
2540 19:52:37.031344 CS Dly: 7 (0~38)
2541 19:52:37.034698 ==
2542 19:52:37.037782 Dram Type= 6, Freq= 0, CH_0, rank 1
2543 19:52:37.041280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2544 19:52:37.041364 ==
2545 19:52:37.044876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2546 19:52:37.051265 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2547 19:52:37.060957 [CA 0] Center 39 (9~70) winsize 62
2548 19:52:37.063852 [CA 1] Center 39 (9~70) winsize 62
2549 19:52:37.067137 [CA 2] Center 35 (5~66) winsize 62
2550 19:52:37.071150 [CA 3] Center 35 (5~66) winsize 62
2551 19:52:37.073991 [CA 4] Center 34 (4~65) winsize 62
2552 19:52:37.077378 [CA 5] Center 33 (3~64) winsize 62
2553 19:52:37.077462
2554 19:52:37.080710 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2555 19:52:37.080794
2556 19:52:37.084343 [CATrainingPosCal] consider 2 rank data
2557 19:52:37.087048 u2DelayCellTimex100 = 270/100 ps
2558 19:52:37.090936 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2559 19:52:37.097679 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2560 19:52:37.100724 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2561 19:52:37.104204 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2562 19:52:37.107041 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2563 19:52:37.110181 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2564 19:52:37.110284
2565 19:52:37.113808 CA PerBit enable=1, Macro0, CA PI delay=33
2566 19:52:37.113894
2567 19:52:37.117197 [CBTSetCACLKResult] CA Dly = 33
2568 19:52:37.120113 CS Dly: 8 (0~41)
2569 19:52:37.120224
2570 19:52:37.123621 ----->DramcWriteLeveling(PI) begin...
2571 19:52:37.123706 ==
2572 19:52:37.126675 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 19:52:37.130178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 19:52:37.130263 ==
2575 19:52:37.133387 Write leveling (Byte 0): 32 => 32
2576 19:52:37.136699 Write leveling (Byte 1): 28 => 28
2577 19:52:37.140487 DramcWriteLeveling(PI) end<-----
2578 19:52:37.140572
2579 19:52:37.140657 ==
2580 19:52:37.143691 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 19:52:37.147008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 19:52:37.147151 ==
2583 19:52:37.149997 [Gating] SW mode calibration
2584 19:52:37.156711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2585 19:52:37.163801 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2586 19:52:37.167383 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2587 19:52:37.170306 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2588 19:52:37.176832 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 19:52:37.180341 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 19:52:37.184467 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 19:52:37.190491 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 19:52:37.193323 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2593 19:52:37.196829 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
2594 19:52:37.203649 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2595 19:52:37.206960 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 19:52:37.210146 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 19:52:37.217182 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 19:52:37.220240 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 19:52:37.223215 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 19:52:37.226411 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2601 19:52:37.233512 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2602 19:52:37.236769 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2603 19:52:37.240197 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 19:52:37.246769 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 19:52:37.249916 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 19:52:37.253168 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 19:52:37.260482 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 19:52:37.263636 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2609 19:52:37.266571 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2610 19:52:37.273081 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2611 19:52:37.276558 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 19:52:37.280068 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 19:52:37.286974 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 19:52:37.290207 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 19:52:37.293066 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 19:52:37.299639 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 19:52:37.303615 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 19:52:37.306303 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 19:52:37.312701 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 19:52:37.316147 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 19:52:37.319261 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 19:52:37.326025 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 19:52:37.329584 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 19:52:37.332699 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2625 19:52:37.339367 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2626 19:52:37.339448 Total UI for P1: 0, mck2ui 16
2627 19:52:37.345978 best dqsien dly found for B0: ( 1, 3, 24)
2628 19:52:37.349558 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2629 19:52:37.352776 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 19:52:37.355862 Total UI for P1: 0, mck2ui 16
2631 19:52:37.358995 best dqsien dly found for B1: ( 1, 4, 0)
2632 19:52:37.362863 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2633 19:52:37.366173 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2634 19:52:37.366253
2635 19:52:37.369522 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2636 19:52:37.375564 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2637 19:52:37.375674 [Gating] SW calibration Done
2638 19:52:37.375778 ==
2639 19:52:37.379492 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 19:52:37.386095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 19:52:37.386176 ==
2642 19:52:37.386258 RX Vref Scan: 0
2643 19:52:37.386425
2644 19:52:37.389217 RX Vref 0 -> 0, step: 1
2645 19:52:37.389298
2646 19:52:37.392269 RX Delay -40 -> 252, step: 8
2647 19:52:37.396104 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2648 19:52:37.399263 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2649 19:52:37.402671 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2650 19:52:37.409338 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2651 19:52:37.412392 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2652 19:52:37.415834 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2653 19:52:37.419450 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2654 19:52:37.422314 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2655 19:52:37.428873 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2656 19:52:37.432407 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2657 19:52:37.435819 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2658 19:52:37.438849 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2659 19:52:37.442208 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2660 19:52:37.449717 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2661 19:52:37.452057 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2662 19:52:37.455784 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2663 19:52:37.455866 ==
2664 19:52:37.458768 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 19:52:37.462021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 19:52:37.462102 ==
2667 19:52:37.465852 DQS Delay:
2668 19:52:37.465933 DQS0 = 0, DQS1 = 0
2669 19:52:37.468745 DQM Delay:
2670 19:52:37.468825 DQM0 = 119, DQM1 = 107
2671 19:52:37.468888 DQ Delay:
2672 19:52:37.475615 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2673 19:52:37.479007 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2674 19:52:37.482335 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2675 19:52:37.485575 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =111
2676 19:52:37.485656
2677 19:52:37.485720
2678 19:52:37.485778 ==
2679 19:52:37.488793 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 19:52:37.491745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 19:52:37.491826 ==
2682 19:52:37.491889
2683 19:52:37.491948
2684 19:52:37.495066 TX Vref Scan disable
2685 19:52:37.498526 == TX Byte 0 ==
2686 19:52:37.501947 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2687 19:52:37.506241 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2688 19:52:37.508797 == TX Byte 1 ==
2689 19:52:37.511664 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2690 19:52:37.515085 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2691 19:52:37.515166 ==
2692 19:52:37.518569 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 19:52:37.522133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 19:52:37.525443 ==
2695 19:52:37.535257 TX Vref=22, minBit 1, minWin=25, winSum=417
2696 19:52:37.538513 TX Vref=24, minBit 1, minWin=26, winSum=424
2697 19:52:37.541903 TX Vref=26, minBit 3, minWin=26, winSum=429
2698 19:52:37.545625 TX Vref=28, minBit 0, minWin=26, winSum=430
2699 19:52:37.548524 TX Vref=30, minBit 5, minWin=26, winSum=430
2700 19:52:37.551865 TX Vref=32, minBit 5, minWin=26, winSum=427
2701 19:52:37.559650 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
2702 19:52:37.559731
2703 19:52:37.562028 Final TX Range 1 Vref 28
2704 19:52:37.562107
2705 19:52:37.562170 ==
2706 19:52:37.565252 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 19:52:37.568820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 19:52:37.568901 ==
2709 19:52:37.571922
2710 19:52:37.572005
2711 19:52:37.572089 TX Vref Scan disable
2712 19:52:37.575346 == TX Byte 0 ==
2713 19:52:37.578810 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2714 19:52:37.585223 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2715 19:52:37.585303 == TX Byte 1 ==
2716 19:52:37.588489 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2717 19:52:37.594870 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2718 19:52:37.594950
2719 19:52:37.595014 [DATLAT]
2720 19:52:37.595079 Freq=1200, CH0 RK0
2721 19:52:37.595167
2722 19:52:37.598270 DATLAT Default: 0xd
2723 19:52:37.598351 0, 0xFFFF, sum = 0
2724 19:52:37.601607 1, 0xFFFF, sum = 0
2725 19:52:37.605079 2, 0xFFFF, sum = 0
2726 19:52:37.605160 3, 0xFFFF, sum = 0
2727 19:52:37.608286 4, 0xFFFF, sum = 0
2728 19:52:37.608378 5, 0xFFFF, sum = 0
2729 19:52:37.611535 6, 0xFFFF, sum = 0
2730 19:52:37.611616 7, 0xFFFF, sum = 0
2731 19:52:37.615710 8, 0xFFFF, sum = 0
2732 19:52:37.615792 9, 0xFFFF, sum = 0
2733 19:52:37.618480 10, 0xFFFF, sum = 0
2734 19:52:37.618639 11, 0xFFFF, sum = 0
2735 19:52:37.622374 12, 0x0, sum = 1
2736 19:52:37.622459 13, 0x0, sum = 2
2737 19:52:37.625355 14, 0x0, sum = 3
2738 19:52:37.625440 15, 0x0, sum = 4
2739 19:52:37.628370 best_step = 13
2740 19:52:37.628452
2741 19:52:37.628536 ==
2742 19:52:37.631344 Dram Type= 6, Freq= 0, CH_0, rank 0
2743 19:52:37.634598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2744 19:52:37.634681 ==
2745 19:52:37.634766 RX Vref Scan: 1
2746 19:52:37.634845
2747 19:52:37.638001 Set Vref Range= 32 -> 127
2748 19:52:37.638084
2749 19:52:37.641327 RX Vref 32 -> 127, step: 1
2750 19:52:37.641410
2751 19:52:37.645119 RX Delay -21 -> 252, step: 4
2752 19:52:37.645203
2753 19:52:37.647991 Set Vref, RX VrefLevel [Byte0]: 32
2754 19:52:37.651755 [Byte1]: 32
2755 19:52:37.651838
2756 19:52:37.654936 Set Vref, RX VrefLevel [Byte0]: 33
2757 19:52:37.658544 [Byte1]: 33
2758 19:52:37.661568
2759 19:52:37.661651 Set Vref, RX VrefLevel [Byte0]: 34
2760 19:52:37.664528 [Byte1]: 34
2761 19:52:37.669332
2762 19:52:37.669415 Set Vref, RX VrefLevel [Byte0]: 35
2763 19:52:37.672752 [Byte1]: 35
2764 19:52:37.677648
2765 19:52:37.677731 Set Vref, RX VrefLevel [Byte0]: 36
2766 19:52:37.680692 [Byte1]: 36
2767 19:52:37.685420
2768 19:52:37.685502 Set Vref, RX VrefLevel [Byte0]: 37
2769 19:52:37.688865 [Byte1]: 37
2770 19:52:37.693263
2771 19:52:37.693346 Set Vref, RX VrefLevel [Byte0]: 38
2772 19:52:37.696580 [Byte1]: 38
2773 19:52:37.701634
2774 19:52:37.701716 Set Vref, RX VrefLevel [Byte0]: 39
2775 19:52:37.704590 [Byte1]: 39
2776 19:52:37.709488
2777 19:52:37.709570 Set Vref, RX VrefLevel [Byte0]: 40
2778 19:52:37.712410 [Byte1]: 40
2779 19:52:37.716984
2780 19:52:37.717067 Set Vref, RX VrefLevel [Byte0]: 41
2781 19:52:37.720490 [Byte1]: 41
2782 19:52:37.724817
2783 19:52:37.724900 Set Vref, RX VrefLevel [Byte0]: 42
2784 19:52:37.728379 [Byte1]: 42
2785 19:52:37.733277
2786 19:52:37.733360 Set Vref, RX VrefLevel [Byte0]: 43
2787 19:52:37.735991 [Byte1]: 43
2788 19:52:37.740604
2789 19:52:37.740691 Set Vref, RX VrefLevel [Byte0]: 44
2790 19:52:37.743995 [Byte1]: 44
2791 19:52:37.749031
2792 19:52:37.749113 Set Vref, RX VrefLevel [Byte0]: 45
2793 19:52:37.752058 [Byte1]: 45
2794 19:52:37.756713
2795 19:52:37.756796 Set Vref, RX VrefLevel [Byte0]: 46
2796 19:52:37.759854 [Byte1]: 46
2797 19:52:37.764335
2798 19:52:37.764418 Set Vref, RX VrefLevel [Byte0]: 47
2799 19:52:37.768026 [Byte1]: 47
2800 19:52:37.772297
2801 19:52:37.772380 Set Vref, RX VrefLevel [Byte0]: 48
2802 19:52:37.775718 [Byte1]: 48
2803 19:52:37.780538
2804 19:52:37.780621 Set Vref, RX VrefLevel [Byte0]: 49
2805 19:52:37.783745 [Byte1]: 49
2806 19:52:37.788541
2807 19:52:37.788624 Set Vref, RX VrefLevel [Byte0]: 50
2808 19:52:37.791547 [Byte1]: 50
2809 19:52:37.796595
2810 19:52:37.796677 Set Vref, RX VrefLevel [Byte0]: 51
2811 19:52:37.800002 [Byte1]: 51
2812 19:52:37.804057
2813 19:52:37.804141 Set Vref, RX VrefLevel [Byte0]: 52
2814 19:52:37.807246 [Byte1]: 52
2815 19:52:37.812577
2816 19:52:37.812659 Set Vref, RX VrefLevel [Byte0]: 53
2817 19:52:37.815303 [Byte1]: 53
2818 19:52:37.820148
2819 19:52:37.820231 Set Vref, RX VrefLevel [Byte0]: 54
2820 19:52:37.823278 [Byte1]: 54
2821 19:52:37.828587
2822 19:52:37.828670 Set Vref, RX VrefLevel [Byte0]: 55
2823 19:52:37.831016 [Byte1]: 55
2824 19:52:37.836066
2825 19:52:37.836149 Set Vref, RX VrefLevel [Byte0]: 56
2826 19:52:37.839801 [Byte1]: 56
2827 19:52:37.843948
2828 19:52:37.844031 Set Vref, RX VrefLevel [Byte0]: 57
2829 19:52:37.847103 [Byte1]: 57
2830 19:52:37.851484
2831 19:52:37.851567 Set Vref, RX VrefLevel [Byte0]: 58
2832 19:52:37.855358 [Byte1]: 58
2833 19:52:37.859998
2834 19:52:37.860081 Set Vref, RX VrefLevel [Byte0]: 59
2835 19:52:37.862835 [Byte1]: 59
2836 19:52:37.867441
2837 19:52:37.867524 Set Vref, RX VrefLevel [Byte0]: 60
2838 19:52:37.871130 [Byte1]: 60
2839 19:52:37.875889
2840 19:52:37.875971 Set Vref, RX VrefLevel [Byte0]: 61
2841 19:52:37.879490 [Byte1]: 61
2842 19:52:37.883949
2843 19:52:37.884029 Set Vref, RX VrefLevel [Byte0]: 62
2844 19:52:37.886623 [Byte1]: 62
2845 19:52:37.891340
2846 19:52:37.891419 Set Vref, RX VrefLevel [Byte0]: 63
2847 19:52:37.894448 [Byte1]: 63
2848 19:52:37.899267
2849 19:52:37.899348 Set Vref, RX VrefLevel [Byte0]: 64
2850 19:52:37.902468 [Byte1]: 64
2851 19:52:37.907084
2852 19:52:37.907182 Set Vref, RX VrefLevel [Byte0]: 65
2853 19:52:37.910457 [Byte1]: 65
2854 19:52:37.914907
2855 19:52:37.915005 Set Vref, RX VrefLevel [Byte0]: 66
2856 19:52:37.918418 [Byte1]: 66
2857 19:52:37.923430
2858 19:52:37.923510 Set Vref, RX VrefLevel [Byte0]: 67
2859 19:52:37.926278 [Byte1]: 67
2860 19:52:37.931334
2861 19:52:37.931414 Final RX Vref Byte 0 = 57 to rank0
2862 19:52:37.934347 Final RX Vref Byte 1 = 49 to rank0
2863 19:52:37.938248 Final RX Vref Byte 0 = 57 to rank1
2864 19:52:37.941412 Final RX Vref Byte 1 = 49 to rank1==
2865 19:52:37.943985 Dram Type= 6, Freq= 0, CH_0, rank 0
2866 19:52:37.950519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2867 19:52:37.950601 ==
2868 19:52:37.950665 DQS Delay:
2869 19:52:37.953841 DQS0 = 0, DQS1 = 0
2870 19:52:37.953922 DQM Delay:
2871 19:52:37.953986 DQM0 = 119, DQM1 = 105
2872 19:52:37.957193 DQ Delay:
2873 19:52:37.960707 DQ0 =120, DQ1 =118, DQ2 =116, DQ3 =116
2874 19:52:37.963932 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2875 19:52:37.967247 DQ8 =94, DQ9 =92, DQ10 =104, DQ11 =100
2876 19:52:37.970743 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =114
2877 19:52:37.970824
2878 19:52:37.970888
2879 19:52:37.980751 [DQSOSCAuto] RK0, (LSB)MR18= 0xfb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2880 19:52:37.980833 CH0 RK0: MR19=403, MR18=FB
2881 19:52:37.987509 CH0_RK0: MR19=0x403, MR18=0xFB, DQSOSC=410, MR23=63, INC=39, DEC=26
2882 19:52:37.987591
2883 19:52:37.990349 ----->DramcWriteLeveling(PI) begin...
2884 19:52:37.990431 ==
2885 19:52:37.993983 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 19:52:37.997553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 19:52:38.000104 ==
2888 19:52:38.000185 Write leveling (Byte 0): 31 => 31
2889 19:52:38.003845 Write leveling (Byte 1): 27 => 27
2890 19:52:38.007364 DramcWriteLeveling(PI) end<-----
2891 19:52:38.007445
2892 19:52:38.007508 ==
2893 19:52:38.010070 Dram Type= 6, Freq= 0, CH_0, rank 1
2894 19:52:38.016737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 19:52:38.016833 ==
2896 19:52:38.016899 [Gating] SW mode calibration
2897 19:52:38.027207 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2898 19:52:38.030234 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2899 19:52:38.033784 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2900 19:52:38.040402 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2901 19:52:38.043843 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 19:52:38.046867 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 19:52:38.053980 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 19:52:38.057040 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2905 19:52:38.060338 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2906 19:52:38.066894 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2907 19:52:38.070802 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
2908 19:52:38.073977 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 19:52:38.080323 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 19:52:38.083784 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 19:52:38.086887 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 19:52:38.093386 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 19:52:38.097015 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2914 19:52:38.100597 1 0 28 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
2915 19:52:38.106762 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
2916 19:52:38.110085 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 19:52:38.113781 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 19:52:38.120211 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 19:52:38.123038 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 19:52:38.127071 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 19:52:38.133412 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2922 19:52:38.136323 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2923 19:52:38.139941 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2924 19:52:38.146671 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 19:52:38.149903 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 19:52:38.153274 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 19:52:38.159652 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 19:52:38.163134 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 19:52:38.166467 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 19:52:38.172921 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 19:52:38.176315 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 19:52:38.179586 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 19:52:38.186265 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 19:52:38.189547 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 19:52:38.192765 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 19:52:38.199652 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 19:52:38.202545 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2938 19:52:38.205946 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2939 19:52:38.209288 Total UI for P1: 0, mck2ui 16
2940 19:52:38.212744 best dqsien dly found for B0: ( 1, 3, 24)
2941 19:52:38.216254 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2942 19:52:38.222698 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 19:52:38.226123 Total UI for P1: 0, mck2ui 16
2944 19:52:38.229719 best dqsien dly found for B1: ( 1, 3, 30)
2945 19:52:38.232418 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2946 19:52:38.235701 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2947 19:52:38.235782
2948 19:52:38.239317 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2949 19:52:38.242997 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2950 19:52:38.246093 [Gating] SW calibration Done
2951 19:52:38.246185 ==
2952 19:52:38.249144 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 19:52:38.252448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 19:52:38.252550 ==
2955 19:52:38.255970 RX Vref Scan: 0
2956 19:52:38.256074
2957 19:52:38.259266 RX Vref 0 -> 0, step: 1
2958 19:52:38.259373
2959 19:52:38.259484 RX Delay -40 -> 252, step: 8
2960 19:52:38.266611 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2961 19:52:38.268890 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2962 19:52:38.272324 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2963 19:52:38.275860 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2964 19:52:38.278983 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2965 19:52:38.286493 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2966 19:52:38.289170 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2967 19:52:38.292679 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2968 19:52:38.296075 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2969 19:52:38.299277 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2970 19:52:38.306009 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2971 19:52:38.309122 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2972 19:52:38.312250 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2973 19:52:38.315767 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2974 19:52:38.319341 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2975 19:52:38.326076 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2976 19:52:38.326492 ==
2977 19:52:38.329910 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 19:52:38.332198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 19:52:38.332752 ==
2980 19:52:38.333146 DQS Delay:
2981 19:52:38.335654 DQS0 = 0, DQS1 = 0
2982 19:52:38.336066 DQM Delay:
2983 19:52:38.339405 DQM0 = 119, DQM1 = 106
2984 19:52:38.339823 DQ Delay:
2985 19:52:38.342642 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2986 19:52:38.346015 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2987 19:52:38.349227 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2988 19:52:38.352627 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2989 19:52:38.353042
2990 19:52:38.353365
2991 19:52:38.356045 ==
2992 19:52:38.356460 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 19:52:38.362340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 19:52:38.362757 ==
2995 19:52:38.363124
2996 19:52:38.363445
2997 19:52:38.365671 TX Vref Scan disable
2998 19:52:38.366212 == TX Byte 0 ==
2999 19:52:38.368982 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3000 19:52:38.375756 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3001 19:52:38.376173 == TX Byte 1 ==
3002 19:52:38.378752 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3003 19:52:38.385609 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3004 19:52:38.386060 ==
3005 19:52:38.388635 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 19:52:38.392141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 19:52:38.392573 ==
3008 19:52:38.404666 TX Vref=22, minBit 3, minWin=25, winSum=415
3009 19:52:38.407792 TX Vref=24, minBit 2, minWin=25, winSum=418
3010 19:52:38.411006 TX Vref=26, minBit 1, minWin=26, winSum=425
3011 19:52:38.414698 TX Vref=28, minBit 5, minWin=25, winSum=423
3012 19:52:38.418484 TX Vref=30, minBit 1, minWin=26, winSum=424
3013 19:52:38.424688 TX Vref=32, minBit 0, minWin=26, winSum=424
3014 19:52:38.427678 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 26
3015 19:52:38.428108
3016 19:52:38.430917 Final TX Range 1 Vref 26
3017 19:52:38.431377
3018 19:52:38.431813 ==
3019 19:52:38.434282 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 19:52:38.437831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 19:52:38.438254 ==
3022 19:52:38.438612
3023 19:52:38.441091
3024 19:52:38.441482 TX Vref Scan disable
3025 19:52:38.444212 == TX Byte 0 ==
3026 19:52:38.447786 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3027 19:52:38.450715 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3028 19:52:38.454540 == TX Byte 1 ==
3029 19:52:38.457556 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3030 19:52:38.460724 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3031 19:52:38.464201
3032 19:52:38.464578 [DATLAT]
3033 19:52:38.464919 Freq=1200, CH0 RK1
3034 19:52:38.465249
3035 19:52:38.467610 DATLAT Default: 0xd
3036 19:52:38.468014 0, 0xFFFF, sum = 0
3037 19:52:38.470836 1, 0xFFFF, sum = 0
3038 19:52:38.471309 2, 0xFFFF, sum = 0
3039 19:52:38.474126 3, 0xFFFF, sum = 0
3040 19:52:38.477972 4, 0xFFFF, sum = 0
3041 19:52:38.478584 5, 0xFFFF, sum = 0
3042 19:52:38.480776 6, 0xFFFF, sum = 0
3043 19:52:38.481200 7, 0xFFFF, sum = 0
3044 19:52:38.484631 8, 0xFFFF, sum = 0
3045 19:52:38.485071 9, 0xFFFF, sum = 0
3046 19:52:38.487475 10, 0xFFFF, sum = 0
3047 19:52:38.487910 11, 0xFFFF, sum = 0
3048 19:52:38.490506 12, 0x0, sum = 1
3049 19:52:38.490939 13, 0x0, sum = 2
3050 19:52:38.494088 14, 0x0, sum = 3
3051 19:52:38.494521 15, 0x0, sum = 4
3052 19:52:38.494958 best_step = 13
3053 19:52:38.497365
3054 19:52:38.497789 ==
3055 19:52:38.501037 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 19:52:38.503853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 19:52:38.504284 ==
3058 19:52:38.504720 RX Vref Scan: 0
3059 19:52:38.505133
3060 19:52:38.507187 RX Vref 0 -> 0, step: 1
3061 19:52:38.507614
3062 19:52:38.510415 RX Delay -21 -> 252, step: 4
3063 19:52:38.513873 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3064 19:52:38.520731 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3065 19:52:38.523893 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3066 19:52:38.527125 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3067 19:52:38.530995 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3068 19:52:38.534741 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3069 19:52:38.540542 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3070 19:52:38.543719 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3071 19:52:38.547035 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3072 19:52:38.551364 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3073 19:52:38.553862 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3074 19:52:38.560947 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3075 19:52:38.564030 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3076 19:52:38.567015 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3077 19:52:38.570504 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3078 19:52:38.574031 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3079 19:52:38.577246 ==
3080 19:52:38.577840 Dram Type= 6, Freq= 0, CH_0, rank 1
3081 19:52:38.583966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 19:52:38.584465 ==
3083 19:52:38.584834 DQS Delay:
3084 19:52:38.586891 DQS0 = 0, DQS1 = 0
3085 19:52:38.587397 DQM Delay:
3086 19:52:38.590286 DQM0 = 118, DQM1 = 106
3087 19:52:38.590700 DQ Delay:
3088 19:52:38.593769 DQ0 =116, DQ1 =118, DQ2 =114, DQ3 =114
3089 19:52:38.596943 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =124
3090 19:52:38.600534 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3091 19:52:38.603679 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =114
3092 19:52:38.604108
3093 19:52:38.604539
3094 19:52:38.613731 [DQSOSCAuto] RK1, (LSB)MR18= 0xfdfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3095 19:52:38.614165 CH0 RK1: MR19=303, MR18=FDFA
3096 19:52:38.620491 CH0_RK1: MR19=0x303, MR18=0xFDFA, DQSOSC=411, MR23=63, INC=38, DEC=25
3097 19:52:38.624201 [RxdqsGatingPostProcess] freq 1200
3098 19:52:38.630288 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3099 19:52:38.633642 best DQS0 dly(2T, 0.5T) = (0, 11)
3100 19:52:38.636737 best DQS1 dly(2T, 0.5T) = (0, 12)
3101 19:52:38.639695 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3102 19:52:38.643746 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3103 19:52:38.646780 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 19:52:38.649760 best DQS1 dly(2T, 0.5T) = (0, 11)
3105 19:52:38.650193 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 19:52:38.653362 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3107 19:52:38.656597 Pre-setting of DQS Precalculation
3108 19:52:38.663554 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3109 19:52:38.664101 ==
3110 19:52:38.666571 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 19:52:38.669988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 19:52:38.670406 ==
3113 19:52:38.676152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3114 19:52:38.682770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3115 19:52:38.690079 [CA 0] Center 38 (8~68) winsize 61
3116 19:52:38.693435 [CA 1] Center 37 (7~68) winsize 62
3117 19:52:38.697068 [CA 2] Center 35 (6~65) winsize 60
3118 19:52:38.700247 [CA 3] Center 34 (4~64) winsize 61
3119 19:52:38.703528 [CA 4] Center 34 (4~65) winsize 62
3120 19:52:38.706837 [CA 5] Center 33 (3~63) winsize 61
3121 19:52:38.706917
3122 19:52:38.710481 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3123 19:52:38.710562
3124 19:52:38.713044 [CATrainingPosCal] consider 1 rank data
3125 19:52:38.716453 u2DelayCellTimex100 = 270/100 ps
3126 19:52:38.719762 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3127 19:52:38.726557 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3128 19:52:38.729667 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3129 19:52:38.733559 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3130 19:52:38.736698 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3131 19:52:38.740120 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3132 19:52:38.740198
3133 19:52:38.743472 CA PerBit enable=1, Macro0, CA PI delay=33
3134 19:52:38.743543
3135 19:52:38.747001 [CBTSetCACLKResult] CA Dly = 33
3136 19:52:38.747070 CS Dly: 5 (0~36)
3137 19:52:38.747140 ==
3138 19:52:38.750231 Dram Type= 6, Freq= 0, CH_1, rank 1
3139 19:52:38.756865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 19:52:38.756943 ==
3141 19:52:38.759859 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3142 19:52:38.766405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3143 19:52:38.775976 [CA 0] Center 38 (8~68) winsize 61
3144 19:52:38.779275 [CA 1] Center 37 (7~68) winsize 62
3145 19:52:38.782422 [CA 2] Center 34 (4~65) winsize 62
3146 19:52:38.786214 [CA 3] Center 34 (4~64) winsize 61
3147 19:52:38.788791 [CA 4] Center 34 (4~64) winsize 61
3148 19:52:38.793240 [CA 5] Center 33 (3~63) winsize 61
3149 19:52:38.793312
3150 19:52:38.795766 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3151 19:52:38.795835
3152 19:52:38.799085 [CATrainingPosCal] consider 2 rank data
3153 19:52:38.802439 u2DelayCellTimex100 = 270/100 ps
3154 19:52:38.805736 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3155 19:52:38.809251 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3156 19:52:38.815623 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3157 19:52:38.818730 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3158 19:52:38.822348 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 19:52:38.826241 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3160 19:52:38.826312
3161 19:52:38.829085 CA PerBit enable=1, Macro0, CA PI delay=33
3162 19:52:38.829157
3163 19:52:38.832309 [CBTSetCACLKResult] CA Dly = 33
3164 19:52:38.832378 CS Dly: 6 (0~38)
3165 19:52:38.832437
3166 19:52:38.835453 ----->DramcWriteLeveling(PI) begin...
3167 19:52:38.838894 ==
3168 19:52:38.842627 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 19:52:38.845670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 19:52:38.845741 ==
3171 19:52:38.848830 Write leveling (Byte 0): 28 => 28
3172 19:52:38.852507 Write leveling (Byte 1): 26 => 26
3173 19:52:38.855551 DramcWriteLeveling(PI) end<-----
3174 19:52:38.855629
3175 19:52:38.855691 ==
3176 19:52:38.858950 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 19:52:38.862033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 19:52:38.862113 ==
3179 19:52:38.865680 [Gating] SW mode calibration
3180 19:52:38.872038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3181 19:52:38.878777 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3182 19:52:38.882596 0 15 0 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
3183 19:52:38.885344 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 19:52:38.891826 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 19:52:38.894984 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 19:52:38.898700 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 19:52:38.901921 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 19:52:38.908790 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 1)
3189 19:52:38.912110 0 15 28 | B1->B0 | 2727 2525 | 0 0 | (0 0) (1 0)
3190 19:52:38.915514 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 19:52:38.922162 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 19:52:38.925145 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 19:52:38.928456 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 19:52:38.935028 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 19:52:38.938425 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 19:52:38.941751 1 0 24 | B1->B0 | 2424 3131 | 0 0 | (0 0) (1 1)
3197 19:52:38.948604 1 0 28 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
3198 19:52:38.951736 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 19:52:38.955215 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 19:52:38.961434 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 19:52:38.965347 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 19:52:38.968056 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 19:52:38.975178 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 19:52:38.978426 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3205 19:52:38.981765 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3206 19:52:38.987959 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 19:52:38.991131 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 19:52:38.995221 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 19:52:39.001292 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 19:52:39.004596 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 19:52:39.008152 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 19:52:39.014560 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 19:52:39.018025 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 19:52:39.021430 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 19:52:39.027784 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 19:52:39.031318 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 19:52:39.034379 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 19:52:39.041100 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 19:52:39.044637 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 19:52:39.047739 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 19:52:39.054377 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3222 19:52:39.058018 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 19:52:39.061200 Total UI for P1: 0, mck2ui 16
3224 19:52:39.064417 best dqsien dly found for B0: ( 1, 3, 28)
3225 19:52:39.067404 Total UI for P1: 0, mck2ui 16
3226 19:52:39.070895 best dqsien dly found for B1: ( 1, 3, 28)
3227 19:52:39.074023 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3228 19:52:39.077207 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3229 19:52:39.077287
3230 19:52:39.081078 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3231 19:52:39.084237 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3232 19:52:39.087609 [Gating] SW calibration Done
3233 19:52:39.087689 ==
3234 19:52:39.091232 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 19:52:39.094028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 19:52:39.094109 ==
3237 19:52:39.097171 RX Vref Scan: 0
3238 19:52:39.097251
3239 19:52:39.100540 RX Vref 0 -> 0, step: 1
3240 19:52:39.100620
3241 19:52:39.100682 RX Delay -40 -> 252, step: 8
3242 19:52:39.107800 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3243 19:52:39.110744 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3244 19:52:39.113883 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3245 19:52:39.117115 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3246 19:52:39.120707 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3247 19:52:39.127243 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3248 19:52:39.131051 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3249 19:52:39.134329 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3250 19:52:39.137207 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3251 19:52:39.140206 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3252 19:52:39.146785 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3253 19:52:39.150726 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3254 19:52:39.153586 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3255 19:52:39.156905 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3256 19:52:39.164477 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3257 19:52:39.167417 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3258 19:52:39.167497 ==
3259 19:52:39.170208 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 19:52:39.173548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 19:52:39.173629 ==
3262 19:52:39.176750 DQS Delay:
3263 19:52:39.176831 DQS0 = 0, DQS1 = 0
3264 19:52:39.176895 DQM Delay:
3265 19:52:39.180192 DQM0 = 117, DQM1 = 112
3266 19:52:39.180273 DQ Delay:
3267 19:52:39.183315 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3268 19:52:39.186667 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3269 19:52:39.190310 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3270 19:52:39.196552 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3271 19:52:39.196633
3272 19:52:39.196696
3273 19:52:39.196756 ==
3274 19:52:39.199986 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 19:52:39.203386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 19:52:39.203467 ==
3277 19:52:39.203532
3278 19:52:39.203591
3279 19:52:39.206597 TX Vref Scan disable
3280 19:52:39.206677 == TX Byte 0 ==
3281 19:52:39.213153 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3282 19:52:39.216686 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3283 19:52:39.216768 == TX Byte 1 ==
3284 19:52:39.222998 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3285 19:52:39.226899 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3286 19:52:39.226980 ==
3287 19:52:39.229879 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 19:52:39.233742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 19:52:39.233823 ==
3290 19:52:39.245655 TX Vref=22, minBit 8, minWin=24, winSum=404
3292 19:57:25.033046 end: 2.2.3 depthcharge-start (duration 00:04:55) [common]
3294 19:57:25.034077 depthcharge-retry failed: 1 of 1 attempts. 'depthcharge-start timed out after 295 seconds'
3296 19:57:25.034972 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
3299 19:57:25.036484 end: 2 depthcharge-action (duration 00:05:00) [common]
3301 19:57:25.037265 Cleaning after the job
3302 19:57:25.037352 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/ramdisk
3303 19:57:25.039990 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/kernel
3304 19:57:25.052389 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/dtb
3305 19:57:25.052557 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/nfsrootfs
3306 19:57:25.142038 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899568/tftp-deploy-8xh880z2/modules
3307 19:57:25.149009 start: 4.1 power-off (timeout 00:00:30) [common]
3308 19:57:25.149180 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
3309 19:57:25.227694 >> Command sent successfully.
3310 19:57:25.232721 Returned 0 in 0 seconds
3311 19:57:25.333806 end: 4.1 power-off (duration 00:00:00) [common]
3313 19:57:25.335318 start: 4.2 read-feedback (timeout 00:10:00) [common]
3314 19:57:25.336717 Listened to connection for namespace 'common' for up to 1s
3315 19:57:26.337234 Finalising connection for namespace 'common'
3316 19:57:26.337947 Disconnecting from shell: Finalise
3317 19:57:26.338398 TX Vref=24, minBit 8, minWin=24,
3318 19:57:26.439468 end: 4.2 read-feedback (duration 00:00:01) [common]
3319 19:57:26.440079 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11899568
3320 19:57:27.097140 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11899568
3321 19:57:27.097337 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.