Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 42
- Errors: 0
- Boot result: PASS
1 19:54:35.442706 lava-dispatcher, installed at version: 2023.08
2 19:54:35.442910 start: 0 validate
3 19:54:35.443043 Start time: 2023-10-28 19:54:35.443031+00:00 (UTC)
4 19:54:35.443161 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:54:35.443289 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 19:54:35.714233 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:54:35.714961 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:54:35.985502 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:54:35.986311 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:54:36.256827 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:54:36.257623 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:54:36.528383 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:54:36.529151 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:54:36.807449 validate duration: 1.36
16 19:54:36.808731 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:54:36.809307 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:54:36.809780 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:54:36.810395 Not decompressing ramdisk as can be used compressed.
20 19:54:36.810898 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 19:54:36.811254 saving as /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/ramdisk/initrd.cpio.gz
22 19:54:36.811604 total size: 4665398 (4 MB)
23 19:54:36.816901 progress 0 % (0 MB)
24 19:54:36.825189 progress 5 % (0 MB)
25 19:54:36.832176 progress 10 % (0 MB)
26 19:54:36.836823 progress 15 % (0 MB)
27 19:54:36.840403 progress 20 % (0 MB)
28 19:54:36.843430 progress 25 % (1 MB)
29 19:54:36.846313 progress 30 % (1 MB)
30 19:54:36.848743 progress 35 % (1 MB)
31 19:54:36.851132 progress 40 % (1 MB)
32 19:54:36.853420 progress 45 % (2 MB)
33 19:54:36.855510 progress 50 % (2 MB)
34 19:54:36.857409 progress 55 % (2 MB)
35 19:54:36.859185 progress 60 % (2 MB)
36 19:54:36.860960 progress 65 % (2 MB)
37 19:54:36.862542 progress 70 % (3 MB)
38 19:54:36.864111 progress 75 % (3 MB)
39 19:54:36.865674 progress 80 % (3 MB)
40 19:54:36.867379 progress 85 % (3 MB)
41 19:54:36.868808 progress 90 % (4 MB)
42 19:54:36.870227 progress 95 % (4 MB)
43 19:54:36.871618 progress 100 % (4 MB)
44 19:54:36.871793 4 MB downloaded in 0.06 s (73.89 MB/s)
45 19:54:36.871944 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:54:36.872186 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:54:36.872274 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:54:36.872363 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:54:36.872499 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:54:36.872573 saving as /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/kernel/Image
52 19:54:36.872636 total size: 49304064 (47 MB)
53 19:54:36.872698 No compression specified
54 19:54:36.873814 progress 0 % (0 MB)
55 19:54:36.886609 progress 5 % (2 MB)
56 19:54:36.899348 progress 10 % (4 MB)
57 19:54:36.912145 progress 15 % (7 MB)
58 19:54:36.924861 progress 20 % (9 MB)
59 19:54:36.937940 progress 25 % (11 MB)
60 19:54:36.950581 progress 30 % (14 MB)
61 19:54:36.963317 progress 35 % (16 MB)
62 19:54:36.976370 progress 40 % (18 MB)
63 19:54:36.989509 progress 45 % (21 MB)
64 19:54:37.002139 progress 50 % (23 MB)
65 19:54:37.014683 progress 55 % (25 MB)
66 19:54:37.027532 progress 60 % (28 MB)
67 19:54:37.040058 progress 65 % (30 MB)
68 19:54:37.052713 progress 70 % (32 MB)
69 19:54:37.065259 progress 75 % (35 MB)
70 19:54:37.077897 progress 80 % (37 MB)
71 19:54:37.090848 progress 85 % (39 MB)
72 19:54:37.103629 progress 90 % (42 MB)
73 19:54:37.115969 progress 95 % (44 MB)
74 19:54:37.128399 progress 100 % (47 MB)
75 19:54:37.128625 47 MB downloaded in 0.26 s (183.68 MB/s)
76 19:54:37.128814 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:54:37.129173 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:54:37.129286 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:54:37.129396 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:54:37.129562 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:54:37.129661 saving as /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/dtb/mt8192-asurada-spherion-r0.dtb
83 19:54:37.129749 total size: 47278 (0 MB)
84 19:54:37.129835 No compression specified
85 19:54:37.131535 progress 69 % (0 MB)
86 19:54:37.131876 progress 100 % (0 MB)
87 19:54:37.132057 0 MB downloaded in 0.00 s (19.55 MB/s)
88 19:54:37.132218 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:54:37.132563 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:54:37.132672 start: 1.4 download-retry (timeout 00:10:00) [common]
92 19:54:37.132781 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 19:54:37.132920 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 19:54:37.133012 saving as /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/nfsrootfs/full.rootfs.tar
95 19:54:37.133097 total size: 89451516 (85 MB)
96 19:54:37.133185 Using unxz to decompress xz
97 19:54:37.137207 progress 0 % (0 MB)
98 19:54:37.347607 progress 5 % (4 MB)
99 19:54:37.561076 progress 10 % (8 MB)
100 19:54:37.810637 progress 15 % (12 MB)
101 19:54:38.000420 progress 20 % (17 MB)
102 19:54:38.093508 progress 25 % (21 MB)
103 19:54:38.338785 progress 30 % (25 MB)
104 19:54:38.620174 progress 35 % (29 MB)
105 19:54:38.877062 progress 40 % (34 MB)
106 19:54:39.136124 progress 45 % (38 MB)
107 19:54:39.379032 progress 50 % (42 MB)
108 19:54:39.643986 progress 55 % (46 MB)
109 19:54:39.889526 progress 60 % (51 MB)
110 19:54:40.150819 progress 65 % (55 MB)
111 19:54:40.436815 progress 70 % (59 MB)
112 19:54:40.738212 progress 75 % (64 MB)
113 19:54:41.027102 progress 80 % (68 MB)
114 19:54:41.277244 progress 85 % (72 MB)
115 19:54:41.500404 progress 90 % (76 MB)
116 19:54:41.760181 progress 95 % (81 MB)
117 19:54:42.017860 progress 100 % (85 MB)
118 19:54:42.023937 85 MB downloaded in 4.89 s (17.44 MB/s)
119 19:54:42.024185 end: 1.4.1 http-download (duration 00:00:05) [common]
121 19:54:42.024442 end: 1.4 download-retry (duration 00:00:05) [common]
122 19:54:42.024529 start: 1.5 download-retry (timeout 00:09:55) [common]
123 19:54:42.024614 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 19:54:42.024764 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 19:54:42.024834 saving as /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/modules/modules.tar
126 19:54:42.024893 total size: 8635496 (8 MB)
127 19:54:42.024956 Using unxz to decompress xz
128 19:54:42.029155 progress 0 % (0 MB)
129 19:54:42.050305 progress 5 % (0 MB)
130 19:54:42.071989 progress 10 % (0 MB)
131 19:54:42.097865 progress 15 % (1 MB)
132 19:54:42.123222 progress 20 % (1 MB)
133 19:54:42.148480 progress 25 % (2 MB)
134 19:54:42.176045 progress 30 % (2 MB)
135 19:54:42.200493 progress 35 % (2 MB)
136 19:54:42.225078 progress 40 % (3 MB)
137 19:54:42.248805 progress 45 % (3 MB)
138 19:54:42.274391 progress 50 % (4 MB)
139 19:54:42.299160 progress 55 % (4 MB)
140 19:54:42.325046 progress 60 % (4 MB)
141 19:54:42.347504 progress 65 % (5 MB)
142 19:54:42.371984 progress 70 % (5 MB)
143 19:54:42.395414 progress 75 % (6 MB)
144 19:54:42.421314 progress 80 % (6 MB)
145 19:54:42.453015 progress 85 % (7 MB)
146 19:54:42.478103 progress 90 % (7 MB)
147 19:54:42.502395 progress 95 % (7 MB)
148 19:54:42.525137 progress 100 % (8 MB)
149 19:54:42.530570 8 MB downloaded in 0.51 s (16.29 MB/s)
150 19:54:42.530802 end: 1.5.1 http-download (duration 00:00:01) [common]
152 19:54:42.531057 end: 1.5 download-retry (duration 00:00:01) [common]
153 19:54:42.531148 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 19:54:42.531243 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 19:54:44.256003 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11899579/extract-nfsrootfs-g6gngi29
156 19:54:44.256205 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 19:54:44.256306 start: 1.6.2 lava-overlay (timeout 00:09:53) [common]
158 19:54:44.256470 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_
159 19:54:44.256604 makedir: /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin
160 19:54:44.256733 makedir: /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/tests
161 19:54:44.256847 makedir: /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/results
162 19:54:44.256949 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-add-keys
163 19:54:44.257092 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-add-sources
164 19:54:44.257224 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-background-process-start
165 19:54:44.257353 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-background-process-stop
166 19:54:44.257479 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-common-functions
167 19:54:44.257603 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-echo-ipv4
168 19:54:44.257746 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-install-packages
169 19:54:44.257884 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-installed-packages
170 19:54:44.258007 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-os-build
171 19:54:44.258207 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-probe-channel
172 19:54:44.258343 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-probe-ip
173 19:54:44.258466 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-target-ip
174 19:54:44.258590 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-target-mac
175 19:54:44.258714 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-target-storage
176 19:54:44.258840 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-test-case
177 19:54:44.258964 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-test-event
178 19:54:44.259086 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-test-feedback
179 19:54:44.259209 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-test-raise
180 19:54:44.259333 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-test-reference
181 19:54:44.259457 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-test-runner
182 19:54:44.259582 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-test-set
183 19:54:44.259706 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-test-shell
184 19:54:44.260032 Updating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-install-packages (oe)
185 19:54:44.260185 Updating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/bin/lava-installed-packages (oe)
186 19:54:44.260307 Creating /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/environment
187 19:54:44.260405 LAVA metadata
188 19:54:44.260475 - LAVA_JOB_ID=11899579
189 19:54:44.260537 - LAVA_DISPATCHER_IP=192.168.201.1
190 19:54:44.260638 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:53) [common]
191 19:54:44.260703 skipped lava-vland-overlay
192 19:54:44.260775 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 19:54:44.260853 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
194 19:54:44.260914 skipped lava-multinode-overlay
195 19:54:44.260984 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 19:54:44.261060 start: 1.6.2.3 test-definition (timeout 00:09:53) [common]
197 19:54:44.261132 Loading test definitions
198 19:54:44.261219 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:53) [common]
199 19:54:44.261289 Using /lava-11899579 at stage 0
200 19:54:44.261596 uuid=11899579_1.6.2.3.1 testdef=None
201 19:54:44.261684 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 19:54:44.261767 start: 1.6.2.3.2 test-overlay (timeout 00:09:53) [common]
203 19:54:44.262250 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 19:54:44.262463 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:53) [common]
206 19:54:44.263065 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 19:54:44.263287 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
209 19:54:44.263920 runner path: /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/0/tests/0_lc-compliance test_uuid 11899579_1.6.2.3.1
210 19:54:44.264105 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 19:54:44.264304 Creating lava-test-runner.conf files
213 19:54:44.264367 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899579/lava-overlay-kd4fvte_/lava-11899579/0 for stage 0
214 19:54:44.264456 - 0_lc-compliance
215 19:54:44.264553 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 19:54:44.264637 start: 1.6.2.4 compress-overlay (timeout 00:09:53) [common]
217 19:54:44.270653 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 19:54:44.270752 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
219 19:54:44.270835 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 19:54:44.270918 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 19:54:44.271001 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
222 19:54:44.389996 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 19:54:44.390378 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 19:54:44.390497 extracting modules file /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899579/extract-nfsrootfs-g6gngi29
225 19:54:44.614015 extracting modules file /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899579/extract-overlay-ramdisk-1v2wm74q/ramdisk
226 19:54:44.841443 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 19:54:44.841617 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 19:54:44.841713 [common] Applying overlay to NFS
229 19:54:44.841782 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899579/compress-overlay-sopufrgf/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11899579/extract-nfsrootfs-g6gngi29
230 19:54:44.848521 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 19:54:44.848631 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 19:54:44.848721 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 19:54:44.848809 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 19:54:44.848888 Building ramdisk /var/lib/lava/dispatcher/tmp/11899579/extract-overlay-ramdisk-1v2wm74q/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11899579/extract-overlay-ramdisk-1v2wm74q/ramdisk
235 19:54:45.185200 >> 119376 blocks
236 19:54:47.100421 rename /var/lib/lava/dispatcher/tmp/11899579/extract-overlay-ramdisk-1v2wm74q/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/ramdisk/ramdisk.cpio.gz
237 19:54:47.100893 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 19:54:47.101030 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 19:54:47.101127 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 19:54:47.101239 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/kernel/Image'
241 19:54:59.041255 Returned 0 in 11 seconds
242 19:54:59.141904 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/kernel/image.itb
243 19:54:59.498279 output: FIT description: Kernel Image image with one or more FDT blobs
244 19:54:59.498657 output: Created: Sat Oct 28 20:54:59 2023
245 19:54:59.498734 output: Image 0 (kernel-1)
246 19:54:59.498800 output: Description:
247 19:54:59.498864 output: Created: Sat Oct 28 20:54:59 2023
248 19:54:59.498929 output: Type: Kernel Image
249 19:54:59.498992 output: Compression: lzma compressed
250 19:54:59.499054 output: Data Size: 11047522 Bytes = 10788.60 KiB = 10.54 MiB
251 19:54:59.499114 output: Architecture: AArch64
252 19:54:59.499173 output: OS: Linux
253 19:54:59.499230 output: Load Address: 0x00000000
254 19:54:59.499288 output: Entry Point: 0x00000000
255 19:54:59.499346 output: Hash algo: crc32
256 19:54:59.499404 output: Hash value: da40eda2
257 19:54:59.499461 output: Image 1 (fdt-1)
258 19:54:59.499516 output: Description: mt8192-asurada-spherion-r0
259 19:54:59.499570 output: Created: Sat Oct 28 20:54:59 2023
260 19:54:59.499624 output: Type: Flat Device Tree
261 19:54:59.499677 output: Compression: uncompressed
262 19:54:59.499739 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 19:54:59.499795 output: Architecture: AArch64
264 19:54:59.499848 output: Hash algo: crc32
265 19:54:59.499902 output: Hash value: cc4352de
266 19:54:59.499955 output: Image 2 (ramdisk-1)
267 19:54:59.500008 output: Description: unavailable
268 19:54:59.500061 output: Created: Sat Oct 28 20:54:59 2023
269 19:54:59.500115 output: Type: RAMDisk Image
270 19:54:59.500168 output: Compression: Unknown Compression
271 19:54:59.500222 output: Data Size: 17794634 Bytes = 17377.57 KiB = 16.97 MiB
272 19:54:59.500275 output: Architecture: AArch64
273 19:54:59.500329 output: OS: Linux
274 19:54:59.500382 output: Load Address: unavailable
275 19:54:59.500435 output: Entry Point: unavailable
276 19:54:59.500489 output: Hash algo: crc32
277 19:54:59.500541 output: Hash value: 0c198338
278 19:54:59.500594 output: Default Configuration: 'conf-1'
279 19:54:59.500647 output: Configuration 0 (conf-1)
280 19:54:59.500701 output: Description: mt8192-asurada-spherion-r0
281 19:54:59.500754 output: Kernel: kernel-1
282 19:54:59.500807 output: Init Ramdisk: ramdisk-1
283 19:54:59.500860 output: FDT: fdt-1
284 19:54:59.500913 output: Loadables: kernel-1
285 19:54:59.500967 output:
286 19:54:59.501177 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
287 19:54:59.501281 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
288 19:54:59.501387 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
289 19:54:59.501479 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 19:54:59.501559 No LXC device requested
291 19:54:59.501639 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 19:54:59.501726 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 19:54:59.501801 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 19:54:59.501867 Checking files for TFTP limit of 4294967296 bytes.
295 19:54:59.502377 end: 1 tftp-deploy (duration 00:00:23) [common]
296 19:54:59.502479 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 19:54:59.502569 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 19:54:59.502701 substitutions:
299 19:54:59.502770 - {DTB}: 11899579/tftp-deploy-2vc2u5r_/dtb/mt8192-asurada-spherion-r0.dtb
300 19:54:59.502835 - {INITRD}: 11899579/tftp-deploy-2vc2u5r_/ramdisk/ramdisk.cpio.gz
301 19:54:59.502895 - {KERNEL}: 11899579/tftp-deploy-2vc2u5r_/kernel/Image
302 19:54:59.502953 - {LAVA_MAC}: None
303 19:54:59.503010 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11899579/extract-nfsrootfs-g6gngi29
304 19:54:59.503067 - {NFS_SERVER_IP}: 192.168.201.1
305 19:54:59.503123 - {PRESEED_CONFIG}: None
306 19:54:59.503178 - {PRESEED_LOCAL}: None
307 19:54:59.503232 - {RAMDISK}: 11899579/tftp-deploy-2vc2u5r_/ramdisk/ramdisk.cpio.gz
308 19:54:59.503287 - {ROOT_PART}: None
309 19:54:59.503342 - {ROOT}: None
310 19:54:59.503396 - {SERVER_IP}: 192.168.201.1
311 19:54:59.503449 - {TEE}: None
312 19:54:59.503503 Parsed boot commands:
313 19:54:59.503556 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 19:54:59.503780 Parsed boot commands: tftpboot 192.168.201.1 11899579/tftp-deploy-2vc2u5r_/kernel/image.itb 11899579/tftp-deploy-2vc2u5r_/kernel/cmdline
315 19:54:59.503883 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 19:54:59.503966 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 19:54:59.504060 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 19:54:59.504149 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 19:54:59.504224 Not connected, no need to disconnect.
320 19:54:59.504300 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 19:54:59.504380 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 19:54:59.504450 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
323 19:54:59.508509 Setting prompt string to ['lava-test: # ']
324 19:54:59.508914 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 19:54:59.509025 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 19:54:59.509126 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 19:54:59.509216 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 19:54:59.509450 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
329 19:55:04.643063 >> Command sent successfully.
330 19:55:04.645562 Returned 0 in 5 seconds
331 19:55:04.746001 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 19:55:04.746353 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 19:55:04.746455 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 19:55:04.746542 Setting prompt string to 'Starting depthcharge on Spherion...'
336 19:55:04.746611 Changing prompt to 'Starting depthcharge on Spherion...'
337 19:55:04.746680 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 19:55:04.746945 [Enter `^Ec?' for help]
339 19:55:04.922787
340 19:55:04.922953
341 19:55:04.923030 F0: 102B 0000
342 19:55:04.923100
343 19:55:04.923161 F3: 1001 0000 [0200]
344 19:55:04.923220
345 19:55:04.926040 F3: 1001 0000
346 19:55:04.926131
347 19:55:04.926199 F7: 102D 0000
348 19:55:04.926261
349 19:55:04.926321 F1: 0000 0000
350 19:55:04.926382
351 19:55:04.929917 V0: 0000 0000 [0001]
352 19:55:04.930005
353 19:55:04.930072 00: 0007 8000
354 19:55:04.930140
355 19:55:04.933604 01: 0000 0000
356 19:55:04.933700
357 19:55:04.933768 BP: 0C00 0209 [0000]
358 19:55:04.933830
359 19:55:04.937433 G0: 1182 0000
360 19:55:04.937530
361 19:55:04.937598 EC: 0000 0021 [4000]
362 19:55:04.937660
363 19:55:04.941172 S7: 0000 0000 [0000]
364 19:55:04.941276
365 19:55:04.941356 CC: 0000 0000 [0001]
366 19:55:04.941420
367 19:55:04.945002 T0: 0000 0040 [010F]
368 19:55:04.945112
369 19:55:04.945181 Jump to BL
370 19:55:04.945244
371 19:55:04.969120
372 19:55:04.969280
373 19:55:04.969348
374 19:55:04.976270 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 19:55:04.980157 ARM64: Exception handlers installed.
376 19:55:04.982456 ARM64: Testing exception
377 19:55:04.986161 ARM64: Done test exception
378 19:55:04.993517 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 19:55:05.004137 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 19:55:05.011383 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 19:55:05.022274 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 19:55:05.028442 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 19:55:05.035962 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 19:55:05.045956 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 19:55:05.051975 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 19:55:05.072537 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 19:55:05.075183 WDT: Last reset was cold boot
388 19:55:05.078694 SPI1(PAD0) initialized at 2873684 Hz
389 19:55:05.081814 SPI5(PAD0) initialized at 992727 Hz
390 19:55:05.085169 VBOOT: Loading verstage.
391 19:55:05.091958 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 19:55:05.095116 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 19:55:05.098940 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 19:55:05.101565 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 19:55:05.109668 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 19:55:05.116090 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 19:55:05.126796 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 19:55:05.126933
399 19:55:05.127003
400 19:55:05.137688 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 19:55:05.140072 ARM64: Exception handlers installed.
402 19:55:05.143412 ARM64: Testing exception
403 19:55:05.143532 ARM64: Done test exception
404 19:55:05.149993 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 19:55:05.153281 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 19:55:05.168082 Probing TPM: . done!
407 19:55:05.168234 TPM ready after 0 ms
408 19:55:05.174553 Connected to device vid:did:rid of 1ae0:0028:00
409 19:55:05.184211 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
410 19:55:05.222782 Initialized TPM device CR50 revision 0
411 19:55:05.234965 tlcl_send_startup: Startup return code is 0
412 19:55:05.235117 TPM: setup succeeded
413 19:55:05.246432 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 19:55:05.254974 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 19:55:05.261710 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 19:55:05.273989 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 19:55:05.277178 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 19:55:05.280213 in-header: 03 07 00 00 08 00 00 00
419 19:55:05.283623 in-data: aa e4 47 04 13 02 00 00
420 19:55:05.286968 Chrome EC: UHEPI supported
421 19:55:05.293616 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 19:55:05.297497 in-header: 03 ad 00 00 08 00 00 00
423 19:55:05.300387 in-data: 00 20 20 08 00 00 00 00
424 19:55:05.300473 Phase 1
425 19:55:05.306702 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 19:55:05.310875 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 19:55:05.316823 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 19:55:05.320128 Recovery requested (1009000e)
429 19:55:05.324731 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 19:55:05.333133 tlcl_extend: response is 0
431 19:55:05.343158 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 19:55:05.347060 tlcl_extend: response is 0
433 19:55:05.353330 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 19:55:05.373607 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 19:55:05.380418 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 19:55:05.380533
437 19:55:05.380602
438 19:55:05.391251 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 19:55:05.394545 ARM64: Exception handlers installed.
440 19:55:05.394644 ARM64: Testing exception
441 19:55:05.397772 ARM64: Done test exception
442 19:55:05.419473 pmic_efuse_setting: Set efuses in 11 msecs
443 19:55:05.422763 pmwrap_interface_init: Select PMIF_VLD_RDY
444 19:55:05.430144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 19:55:05.433634 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 19:55:05.436602 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 19:55:05.443289 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 19:55:05.447376 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 19:55:05.454165 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 19:55:05.456905 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 19:55:05.463642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 19:55:05.466802 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 19:55:05.470008 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 19:55:05.476920 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 19:55:05.480540 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 19:55:05.483496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 19:55:05.491156 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 19:55:05.497327 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 19:55:05.503899 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 19:55:05.507133 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 19:55:05.514200 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 19:55:05.520712 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 19:55:05.524035 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 19:55:05.531060 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 19:55:05.537792 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 19:55:05.541296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 19:55:05.548787 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 19:55:05.552177 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 19:55:05.558917 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 19:55:05.562392 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 19:55:05.569179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 19:55:05.572535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 19:55:05.580107 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 19:55:05.583758 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 19:55:05.587965 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 19:55:05.594387 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 19:55:05.597929 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 19:55:05.604036 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 19:55:05.607545 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 19:55:05.614288 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 19:55:05.617405 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 19:55:05.622336 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 19:55:05.627920 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 19:55:05.632314 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 19:55:05.635196 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 19:55:05.638703 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 19:55:05.644982 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 19:55:05.648584 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 19:55:05.651680 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 19:55:05.658264 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 19:55:05.661426 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 19:55:05.664649 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 19:55:05.671837 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 19:55:05.675064 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 19:55:05.681703 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 19:55:05.691300 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 19:55:05.694461 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 19:55:05.704546 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 19:55:05.711341 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 19:55:05.717597 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 19:55:05.720862 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 19:55:05.723945 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 19:55:05.732182 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2a
504 19:55:05.738259 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 19:55:05.741605 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
506 19:55:05.748311 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 19:55:05.756898 [RTC]rtc_get_frequency_meter,154: input=15, output=835
508 19:55:05.765766 [RTC]rtc_get_frequency_meter,154: input=7, output=708
509 19:55:05.775656 [RTC]rtc_get_frequency_meter,154: input=11, output=772
510 19:55:05.784881 [RTC]rtc_get_frequency_meter,154: input=13, output=804
511 19:55:05.794513 [RTC]rtc_get_frequency_meter,154: input=12, output=789
512 19:55:05.803696 [RTC]rtc_get_frequency_meter,154: input=12, output=788
513 19:55:05.813696 [RTC]rtc_get_frequency_meter,154: input=13, output=804
514 19:55:05.816989 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
515 19:55:05.824421 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
516 19:55:05.827622 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 19:55:05.830600 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 19:55:05.837115 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 19:55:05.840476 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 19:55:05.843892 ADC[4]: Raw value=903031 ID=7
521 19:55:05.843999 ADC[3]: Raw value=213652 ID=1
522 19:55:05.847006 RAM Code: 0x71
523 19:55:05.850461 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 19:55:05.857522 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 19:55:05.863364 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 19:55:05.870306 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 19:55:05.874302 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 19:55:05.877647 in-header: 03 07 00 00 08 00 00 00
529 19:55:05.880432 in-data: aa e4 47 04 13 02 00 00
530 19:55:05.883326 Chrome EC: UHEPI supported
531 19:55:05.890222 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 19:55:05.893310 in-header: 03 dd 00 00 08 00 00 00
533 19:55:05.896837 in-data: 90 20 60 08 00 00 00 00
534 19:55:05.899923 MRC: failed to locate region type 0.
535 19:55:05.907094 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 19:55:05.909801 DRAM-K: Running full calibration
537 19:55:05.916496 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 19:55:05.916602 header.status = 0x0
539 19:55:05.919845 header.version = 0x6 (expected: 0x6)
540 19:55:05.923142 header.size = 0xd00 (expected: 0xd00)
541 19:55:05.926895 header.flags = 0x0
542 19:55:05.933003 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 19:55:05.950373 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
544 19:55:05.956845 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 19:55:05.960100 dram_init: ddr_geometry: 2
546 19:55:05.963366 [EMI] MDL number = 2
547 19:55:05.963458 [EMI] Get MDL freq = 0
548 19:55:05.967085 dram_init: ddr_type: 0
549 19:55:05.967174 is_discrete_lpddr4: 1
550 19:55:05.970045 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 19:55:05.970132
552 19:55:05.970198
553 19:55:05.973189 [Bian_co] ETT version 0.0.0.1
554 19:55:05.980043 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 19:55:05.980143
556 19:55:05.983176 dramc_set_vcore_voltage set vcore to 650000
557 19:55:05.986613 Read voltage for 800, 4
558 19:55:05.986704 Vio18 = 0
559 19:55:05.986772 Vcore = 650000
560 19:55:05.989930 Vdram = 0
561 19:55:05.990020 Vddq = 0
562 19:55:05.990088 Vmddr = 0
563 19:55:05.993228 dram_init: config_dvfs: 1
564 19:55:05.996342 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 19:55:06.003543 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 19:55:06.006543 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
567 19:55:06.009855 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
568 19:55:06.013781 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
569 19:55:06.019550 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
570 19:55:06.019653 MEM_TYPE=3, freq_sel=18
571 19:55:06.023037 sv_algorithm_assistance_LP4_1600
572 19:55:06.026316 ============ PULL DRAM RESETB DOWN ============
573 19:55:06.033135 ========== PULL DRAM RESETB DOWN end =========
574 19:55:06.036037 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 19:55:06.039372 ===================================
576 19:55:06.042694 LPDDR4 DRAM CONFIGURATION
577 19:55:06.046180 ===================================
578 19:55:06.046277 EX_ROW_EN[0] = 0x0
579 19:55:06.049441 EX_ROW_EN[1] = 0x0
580 19:55:06.049529 LP4Y_EN = 0x0
581 19:55:06.053271 WORK_FSP = 0x0
582 19:55:06.053360 WL = 0x2
583 19:55:06.056475 RL = 0x2
584 19:55:06.056563 BL = 0x2
585 19:55:06.059835 RPST = 0x0
586 19:55:06.062820 RD_PRE = 0x0
587 19:55:06.062907 WR_PRE = 0x1
588 19:55:06.066124 WR_PST = 0x0
589 19:55:06.066212 DBI_WR = 0x0
590 19:55:06.069485 DBI_RD = 0x0
591 19:55:06.069571 OTF = 0x1
592 19:55:06.072720 ===================================
593 19:55:06.076058 ===================================
594 19:55:06.079177 ANA top config
595 19:55:06.082788 ===================================
596 19:55:06.082878 DLL_ASYNC_EN = 0
597 19:55:06.086383 ALL_SLAVE_EN = 1
598 19:55:06.089241 NEW_RANK_MODE = 1
599 19:55:06.092392 DLL_IDLE_MODE = 1
600 19:55:06.092481 LP45_APHY_COMB_EN = 1
601 19:55:06.095718 TX_ODT_DIS = 1
602 19:55:06.099151 NEW_8X_MODE = 1
603 19:55:06.102473 ===================================
604 19:55:06.105612 ===================================
605 19:55:06.109442 data_rate = 1600
606 19:55:06.112337 CKR = 1
607 19:55:06.115535 DQ_P2S_RATIO = 8
608 19:55:06.118847 ===================================
609 19:55:06.118936 CA_P2S_RATIO = 8
610 19:55:06.123085 DQ_CA_OPEN = 0
611 19:55:06.125934 DQ_SEMI_OPEN = 0
612 19:55:06.129115 CA_SEMI_OPEN = 0
613 19:55:06.132596 CA_FULL_RATE = 0
614 19:55:06.136179 DQ_CKDIV4_EN = 1
615 19:55:06.136277 CA_CKDIV4_EN = 1
616 19:55:06.138983 CA_PREDIV_EN = 0
617 19:55:06.142263 PH8_DLY = 0
618 19:55:06.145596 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 19:55:06.149307 DQ_AAMCK_DIV = 4
620 19:55:06.152168 CA_AAMCK_DIV = 4
621 19:55:06.152259 CA_ADMCK_DIV = 4
622 19:55:06.155605 DQ_TRACK_CA_EN = 0
623 19:55:06.159307 CA_PICK = 800
624 19:55:06.162092 CA_MCKIO = 800
625 19:55:06.165347 MCKIO_SEMI = 0
626 19:55:06.168588 PLL_FREQ = 3068
627 19:55:06.171735 DQ_UI_PI_RATIO = 32
628 19:55:06.171829 CA_UI_PI_RATIO = 0
629 19:55:06.175297 ===================================
630 19:55:06.178858 ===================================
631 19:55:06.181789 memory_type:LPDDR4
632 19:55:06.185190 GP_NUM : 10
633 19:55:06.185277 SRAM_EN : 1
634 19:55:06.188364 MD32_EN : 0
635 19:55:06.192106 ===================================
636 19:55:06.195256 [ANA_INIT] >>>>>>>>>>>>>>
637 19:55:06.198625 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 19:55:06.201907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 19:55:06.205034 ===================================
640 19:55:06.205124 data_rate = 1600,PCW = 0X7600
641 19:55:06.208552 ===================================
642 19:55:06.211839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 19:55:06.218107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 19:55:06.225064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 19:55:06.228546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 19:55:06.231248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 19:55:06.234568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 19:55:06.238549 [ANA_INIT] flow start
649 19:55:06.241545 [ANA_INIT] PLL >>>>>>>>
650 19:55:06.241640 [ANA_INIT] PLL <<<<<<<<
651 19:55:06.244703 [ANA_INIT] MIDPI >>>>>>>>
652 19:55:06.248152 [ANA_INIT] MIDPI <<<<<<<<
653 19:55:06.248243 [ANA_INIT] DLL >>>>>>>>
654 19:55:06.251326 [ANA_INIT] flow end
655 19:55:06.255202 ============ LP4 DIFF to SE enter ============
656 19:55:06.258295 ============ LP4 DIFF to SE exit ============
657 19:55:06.261389 [ANA_INIT] <<<<<<<<<<<<<
658 19:55:06.265029 [Flow] Enable top DCM control >>>>>
659 19:55:06.267984 [Flow] Enable top DCM control <<<<<
660 19:55:06.271514 Enable DLL master slave shuffle
661 19:55:06.278115 ==============================================================
662 19:55:06.278220 Gating Mode config
663 19:55:06.284901 ==============================================================
664 19:55:06.285004 Config description:
665 19:55:06.294760 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 19:55:06.301248 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 19:55:06.308699 SELPH_MODE 0: By rank 1: By Phase
668 19:55:06.311818 ==============================================================
669 19:55:06.314938 GAT_TRACK_EN = 1
670 19:55:06.318323 RX_GATING_MODE = 2
671 19:55:06.321607 RX_GATING_TRACK_MODE = 2
672 19:55:06.324979 SELPH_MODE = 1
673 19:55:06.328213 PICG_EARLY_EN = 1
674 19:55:06.331689 VALID_LAT_VALUE = 1
675 19:55:06.335016 ==============================================================
676 19:55:06.338017 Enter into Gating configuration >>>>
677 19:55:06.341423 Exit from Gating configuration <<<<
678 19:55:06.345248 Enter into DVFS_PRE_config >>>>>
679 19:55:06.357993 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 19:55:06.361100 Exit from DVFS_PRE_config <<<<<
681 19:55:06.364710 Enter into PICG configuration >>>>
682 19:55:06.368416 Exit from PICG configuration <<<<
683 19:55:06.368509 [RX_INPUT] configuration >>>>>
684 19:55:06.371052 [RX_INPUT] configuration <<<<<
685 19:55:06.377866 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 19:55:06.381472 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 19:55:06.388103 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 19:55:06.395716 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 19:55:06.402399 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 19:55:06.406229 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 19:55:06.409595 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 19:55:06.416389 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 19:55:06.420396 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 19:55:06.424432 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 19:55:06.427718 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 19:55:06.431485 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 19:55:06.435210 ===================================
698 19:55:06.438726 LPDDR4 DRAM CONFIGURATION
699 19:55:06.442797 ===================================
700 19:55:06.442914 EX_ROW_EN[0] = 0x0
701 19:55:06.445833 EX_ROW_EN[1] = 0x0
702 19:55:06.445926 LP4Y_EN = 0x0
703 19:55:06.448992 WORK_FSP = 0x0
704 19:55:06.449086 WL = 0x2
705 19:55:06.452773 RL = 0x2
706 19:55:06.452865 BL = 0x2
707 19:55:06.456391 RPST = 0x0
708 19:55:06.456482 RD_PRE = 0x0
709 19:55:06.460307 WR_PRE = 0x1
710 19:55:06.460400 WR_PST = 0x0
711 19:55:06.463914 DBI_WR = 0x0
712 19:55:06.464004 DBI_RD = 0x0
713 19:55:06.467898 OTF = 0x1
714 19:55:06.467991 ===================================
715 19:55:06.471375 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 19:55:06.478889 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 19:55:06.482008 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 19:55:06.485777 ===================================
719 19:55:06.485875 LPDDR4 DRAM CONFIGURATION
720 19:55:06.489507 ===================================
721 19:55:06.493437 EX_ROW_EN[0] = 0x10
722 19:55:06.493538 EX_ROW_EN[1] = 0x0
723 19:55:06.496807 LP4Y_EN = 0x0
724 19:55:06.496912 WORK_FSP = 0x0
725 19:55:06.501147 WL = 0x2
726 19:55:06.501243 RL = 0x2
727 19:55:06.504352 BL = 0x2
728 19:55:06.504442 RPST = 0x0
729 19:55:06.507866 RD_PRE = 0x0
730 19:55:06.507955 WR_PRE = 0x1
731 19:55:06.511328 WR_PST = 0x0
732 19:55:06.511417 DBI_WR = 0x0
733 19:55:06.515129 DBI_RD = 0x0
734 19:55:06.515220 OTF = 0x1
735 19:55:06.518767 ===================================
736 19:55:06.525570 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 19:55:06.529568 nWR fixed to 40
738 19:55:06.529672 [ModeRegInit_LP4] CH0 RK0
739 19:55:06.533378 [ModeRegInit_LP4] CH0 RK1
740 19:55:06.536394 [ModeRegInit_LP4] CH1 RK0
741 19:55:06.536493 [ModeRegInit_LP4] CH1 RK1
742 19:55:06.539592 match AC timing 13
743 19:55:06.543362 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 19:55:06.546478 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 19:55:06.553695 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 19:55:06.557324 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 19:55:06.560263 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 19:55:06.563492 [EMI DOE] emi_dcm 0
749 19:55:06.567040 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 19:55:06.567140 ==
751 19:55:06.570209 Dram Type= 6, Freq= 0, CH_0, rank 0
752 19:55:06.577484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 19:55:06.577595 ==
754 19:55:06.580805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 19:55:06.587571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 19:55:06.596227 [CA 0] Center 37 (6~68) winsize 63
757 19:55:06.599540 [CA 1] Center 36 (6~67) winsize 62
758 19:55:06.602643 [CA 2] Center 34 (4~65) winsize 62
759 19:55:06.606196 [CA 3] Center 34 (4~65) winsize 62
760 19:55:06.609608 [CA 4] Center 33 (3~64) winsize 62
761 19:55:06.612775 [CA 5] Center 33 (3~64) winsize 62
762 19:55:06.612865
763 19:55:06.616580 [CmdBusTrainingLP45] Vref(ca) range 1: 32
764 19:55:06.616674
765 19:55:06.620364 [CATrainingPosCal] consider 1 rank data
766 19:55:06.623289 u2DelayCellTimex100 = 270/100 ps
767 19:55:06.627041 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
768 19:55:06.629642 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
769 19:55:06.633290 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
770 19:55:06.639718 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
771 19:55:06.642879 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
772 19:55:06.646435 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 19:55:06.646534
774 19:55:06.649449 CA PerBit enable=1, Macro0, CA PI delay=33
775 19:55:06.649536
776 19:55:06.652686 [CBTSetCACLKResult] CA Dly = 33
777 19:55:06.652774 CS Dly: 6 (0~37)
778 19:55:06.652841 ==
779 19:55:06.656305 Dram Type= 6, Freq= 0, CH_0, rank 1
780 19:55:06.662916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 19:55:06.663017 ==
782 19:55:06.665961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 19:55:06.672538 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 19:55:06.682122 [CA 0] Center 37 (7~68) winsize 62
785 19:55:06.685384 [CA 1] Center 37 (7~68) winsize 62
786 19:55:06.688690 [CA 2] Center 34 (4~65) winsize 62
787 19:55:06.692230 [CA 3] Center 34 (4~65) winsize 62
788 19:55:06.695417 [CA 4] Center 33 (3~64) winsize 62
789 19:55:06.698496 [CA 5] Center 33 (2~64) winsize 63
790 19:55:06.698584
791 19:55:06.702208 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 19:55:06.702293
793 19:55:06.705263 [CATrainingPosCal] consider 2 rank data
794 19:55:06.708417 u2DelayCellTimex100 = 270/100 ps
795 19:55:06.711760 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 19:55:06.718917 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
797 19:55:06.722763 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 19:55:06.725761 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 19:55:06.729926 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 19:55:06.733103 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 19:55:06.733195
802 19:55:06.737149 CA PerBit enable=1, Macro0, CA PI delay=33
803 19:55:06.737277
804 19:55:06.740277 [CBTSetCACLKResult] CA Dly = 33
805 19:55:06.740392 CS Dly: 6 (0~38)
806 19:55:06.740493
807 19:55:06.743551 ----->DramcWriteLeveling(PI) begin...
808 19:55:06.743638 ==
809 19:55:06.747348 Dram Type= 6, Freq= 0, CH_0, rank 0
810 19:55:06.750954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 19:55:06.751047 ==
812 19:55:06.754437 Write leveling (Byte 0): 32 => 32
813 19:55:06.758043 Write leveling (Byte 1): 29 => 29
814 19:55:06.760844 DramcWriteLeveling(PI) end<-----
815 19:55:06.760930
816 19:55:06.760997 ==
817 19:55:06.764111 Dram Type= 6, Freq= 0, CH_0, rank 0
818 19:55:06.767356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 19:55:06.767441 ==
820 19:55:06.770606 [Gating] SW mode calibration
821 19:55:06.777475 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 19:55:06.784393 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 19:55:06.787452 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 19:55:06.791215 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 19:55:06.797635 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 19:55:06.800472 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
827 19:55:06.805357 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 19:55:06.810719 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 19:55:06.813798 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 19:55:06.817198 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 19:55:06.823933 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 19:55:06.827260 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 19:55:06.830544 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 19:55:06.837238 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 19:55:06.840461 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 19:55:06.843634 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 19:55:06.850570 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 19:55:06.853835 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 19:55:06.857481 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 19:55:06.864226 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 19:55:06.867018 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
842 19:55:06.870262 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 19:55:06.877254 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 19:55:06.880158 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 19:55:06.883369 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 19:55:06.890343 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 19:55:06.893561 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 19:55:06.896711 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 19:55:06.903420 0 9 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
850 19:55:06.906601 0 9 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
851 19:55:06.910310 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 19:55:06.916462 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 19:55:06.919847 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 19:55:06.923215 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 19:55:06.929987 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 19:55:06.933349 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
857 19:55:06.936509 0 10 8 | B1->B0 | 3232 2e2e | 0 1 | (0 1) (1 0)
858 19:55:06.943441 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
859 19:55:06.946681 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 19:55:06.949751 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 19:55:06.956500 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 19:55:06.959914 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 19:55:06.963051 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 19:55:06.970598 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 19:55:06.973254 0 11 8 | B1->B0 | 2525 3a3a | 1 0 | (0 0) (0 0)
866 19:55:06.976534 0 11 12 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
867 19:55:06.982718 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 19:55:06.986079 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 19:55:06.989857 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 19:55:06.995955 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 19:55:06.999836 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 19:55:07.002853 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 19:55:07.006363 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
874 19:55:07.013134 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
875 19:55:07.016156 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 19:55:07.019314 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 19:55:07.026103 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 19:55:07.029135 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 19:55:07.032969 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 19:55:07.039325 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 19:55:07.042623 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 19:55:07.045961 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 19:55:07.052639 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 19:55:07.056097 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 19:55:07.059056 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 19:55:07.065884 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 19:55:07.069314 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 19:55:07.072532 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 19:55:07.078946 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
890 19:55:07.082325 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 19:55:07.085490 Total UI for P1: 0, mck2ui 16
892 19:55:07.089338 best dqsien dly found for B0: ( 0, 14, 8)
893 19:55:07.092290 Total UI for P1: 0, mck2ui 16
894 19:55:07.095624 best dqsien dly found for B1: ( 0, 14, 8)
895 19:55:07.099303 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
896 19:55:07.102264 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
897 19:55:07.102353
898 19:55:07.105453 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 19:55:07.109107 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
900 19:55:07.112160 [Gating] SW calibration Done
901 19:55:07.112249 ==
902 19:55:07.115863 Dram Type= 6, Freq= 0, CH_0, rank 0
903 19:55:07.119383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 19:55:07.119477 ==
905 19:55:07.123374 RX Vref Scan: 0
906 19:55:07.123464
907 19:55:07.123531 RX Vref 0 -> 0, step: 1
908 19:55:07.123593
909 19:55:07.126246 RX Delay -130 -> 252, step: 16
910 19:55:07.129893 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 19:55:07.136794 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 19:55:07.140293 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
913 19:55:07.144100 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
914 19:55:07.147173 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
915 19:55:07.150972 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
916 19:55:07.154081 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
917 19:55:07.161650 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
918 19:55:07.164721 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
919 19:55:07.168259 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
920 19:55:07.171883 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 19:55:07.176199 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 19:55:07.179362 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
923 19:55:07.182498 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
924 19:55:07.186453 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 19:55:07.189895 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
926 19:55:07.193529 ==
927 19:55:07.193625 Dram Type= 6, Freq= 0, CH_0, rank 0
928 19:55:07.200962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 19:55:07.201077 ==
930 19:55:07.201149 DQS Delay:
931 19:55:07.201210 DQS0 = 0, DQS1 = 0
932 19:55:07.204487 DQM Delay:
933 19:55:07.204577 DQM0 = 85, DQM1 = 71
934 19:55:07.204643 DQ Delay:
935 19:55:07.208249 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
936 19:55:07.211878 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
937 19:55:07.215157 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
938 19:55:07.219852 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
939 19:55:07.219990
940 19:55:07.220091
941 19:55:07.220181 ==
942 19:55:07.223105 Dram Type= 6, Freq= 0, CH_0, rank 0
943 19:55:07.227307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 19:55:07.227426 ==
945 19:55:07.227522
946 19:55:07.227612
947 19:55:07.230448 TX Vref Scan disable
948 19:55:07.230556 == TX Byte 0 ==
949 19:55:07.237881 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
950 19:55:07.241480 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
951 19:55:07.241589 == TX Byte 1 ==
952 19:55:07.244628 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
953 19:55:07.251492 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
954 19:55:07.251610 ==
955 19:55:07.255606 Dram Type= 6, Freq= 0, CH_0, rank 0
956 19:55:07.258749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 19:55:07.258844 ==
958 19:55:07.272982 TX Vref=22, minBit 4, minWin=27, winSum=440
959 19:55:07.276192 TX Vref=24, minBit 5, minWin=27, winSum=442
960 19:55:07.279062 TX Vref=26, minBit 5, minWin=27, winSum=445
961 19:55:07.282579 TX Vref=28, minBit 8, minWin=27, winSum=448
962 19:55:07.286265 TX Vref=30, minBit 8, minWin=27, winSum=450
963 19:55:07.289388 TX Vref=32, minBit 4, minWin=27, winSum=445
964 19:55:07.296422 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 30
965 19:55:07.296532
966 19:55:07.299700 Final TX Range 1 Vref 30
967 19:55:07.299798
968 19:55:07.299864 ==
969 19:55:07.302742 Dram Type= 6, Freq= 0, CH_0, rank 0
970 19:55:07.306054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 19:55:07.306143 ==
972 19:55:07.306209
973 19:55:07.306269
974 19:55:07.309357 TX Vref Scan disable
975 19:55:07.309442 == TX Byte 0 ==
976 19:55:07.316251 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
977 19:55:07.319191 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
978 19:55:07.323114 == TX Byte 1 ==
979 19:55:07.326386 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
980 19:55:07.329568 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
981 19:55:07.329661
982 19:55:07.329728 [DATLAT]
983 19:55:07.332429 Freq=800, CH0 RK0
984 19:55:07.332515
985 19:55:07.336271 DATLAT Default: 0xa
986 19:55:07.336358 0, 0xFFFF, sum = 0
987 19:55:07.339181 1, 0xFFFF, sum = 0
988 19:55:07.339271 2, 0xFFFF, sum = 0
989 19:55:07.342488 3, 0xFFFF, sum = 0
990 19:55:07.342577 4, 0xFFFF, sum = 0
991 19:55:07.345585 5, 0xFFFF, sum = 0
992 19:55:07.345682 6, 0xFFFF, sum = 0
993 19:55:07.348877 7, 0xFFFF, sum = 0
994 19:55:07.348966 8, 0xFFFF, sum = 0
995 19:55:07.352253 9, 0x0, sum = 1
996 19:55:07.352341 10, 0x0, sum = 2
997 19:55:07.355631 11, 0x0, sum = 3
998 19:55:07.355718 12, 0x0, sum = 4
999 19:55:07.359425 best_step = 10
1000 19:55:07.359510
1001 19:55:07.359576 ==
1002 19:55:07.362174 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 19:55:07.365432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 19:55:07.365519 ==
1005 19:55:07.365586 RX Vref Scan: 1
1006 19:55:07.365647
1007 19:55:07.369154 Set Vref Range= 32 -> 127
1008 19:55:07.369270
1009 19:55:07.372491 RX Vref 32 -> 127, step: 1
1010 19:55:07.372600
1011 19:55:07.375609 RX Delay -111 -> 252, step: 8
1012 19:55:07.375717
1013 19:55:07.378557 Set Vref, RX VrefLevel [Byte0]: 32
1014 19:55:07.382559 [Byte1]: 32
1015 19:55:07.382668
1016 19:55:07.385298 Set Vref, RX VrefLevel [Byte0]: 33
1017 19:55:07.388826 [Byte1]: 33
1018 19:55:07.388934
1019 19:55:07.392060 Set Vref, RX VrefLevel [Byte0]: 34
1020 19:55:07.395138 [Byte1]: 34
1021 19:55:07.399594
1022 19:55:07.399728 Set Vref, RX VrefLevel [Byte0]: 35
1023 19:55:07.402632 [Byte1]: 35
1024 19:55:07.407378
1025 19:55:07.407499 Set Vref, RX VrefLevel [Byte0]: 36
1026 19:55:07.410196 [Byte1]: 36
1027 19:55:07.415116
1028 19:55:07.415229 Set Vref, RX VrefLevel [Byte0]: 37
1029 19:55:07.418419 [Byte1]: 37
1030 19:55:07.422502
1031 19:55:07.422615 Set Vref, RX VrefLevel [Byte0]: 38
1032 19:55:07.426006 [Byte1]: 38
1033 19:55:07.430382
1034 19:55:07.430492 Set Vref, RX VrefLevel [Byte0]: 39
1035 19:55:07.433589 [Byte1]: 39
1036 19:55:07.438359
1037 19:55:07.438478 Set Vref, RX VrefLevel [Byte0]: 40
1038 19:55:07.440889 [Byte1]: 40
1039 19:55:07.445037
1040 19:55:07.448445 Set Vref, RX VrefLevel [Byte0]: 41
1041 19:55:07.451622 [Byte1]: 41
1042 19:55:07.451758
1043 19:55:07.455173 Set Vref, RX VrefLevel [Byte0]: 42
1044 19:55:07.458211 [Byte1]: 42
1045 19:55:07.458322
1046 19:55:07.461503 Set Vref, RX VrefLevel [Byte0]: 43
1047 19:55:07.464998 [Byte1]: 43
1048 19:55:07.468366
1049 19:55:07.468475 Set Vref, RX VrefLevel [Byte0]: 44
1050 19:55:07.472147 [Byte1]: 44
1051 19:55:07.475688
1052 19:55:07.475806 Set Vref, RX VrefLevel [Byte0]: 45
1053 19:55:07.479178 [Byte1]: 45
1054 19:55:07.484320
1055 19:55:07.484439 Set Vref, RX VrefLevel [Byte0]: 46
1056 19:55:07.486795 [Byte1]: 46
1057 19:55:07.491010
1058 19:55:07.491117 Set Vref, RX VrefLevel [Byte0]: 47
1059 19:55:07.494386 [Byte1]: 47
1060 19:55:07.498698
1061 19:55:07.498807 Set Vref, RX VrefLevel [Byte0]: 48
1062 19:55:07.501865 [Byte1]: 48
1063 19:55:07.506942
1064 19:55:07.507050 Set Vref, RX VrefLevel [Byte0]: 49
1065 19:55:07.510772 [Byte1]: 49
1066 19:55:07.514395
1067 19:55:07.514505 Set Vref, RX VrefLevel [Byte0]: 50
1068 19:55:07.518231 [Byte1]: 50
1069 19:55:07.521839
1070 19:55:07.525480 Set Vref, RX VrefLevel [Byte0]: 51
1071 19:55:07.525595 [Byte1]: 51
1072 19:55:07.529591
1073 19:55:07.529699 Set Vref, RX VrefLevel [Byte0]: 52
1074 19:55:07.532981 [Byte1]: 52
1075 19:55:07.537411
1076 19:55:07.537527 Set Vref, RX VrefLevel [Byte0]: 53
1077 19:55:07.540392 [Byte1]: 53
1078 19:55:07.545328
1079 19:55:07.545454 Set Vref, RX VrefLevel [Byte0]: 54
1080 19:55:07.548038 [Byte1]: 54
1081 19:55:07.552684
1082 19:55:07.552801 Set Vref, RX VrefLevel [Byte0]: 55
1083 19:55:07.555839 [Byte1]: 55
1084 19:55:07.560361
1085 19:55:07.560477 Set Vref, RX VrefLevel [Byte0]: 56
1086 19:55:07.563977 [Byte1]: 56
1087 19:55:07.568074
1088 19:55:07.568188 Set Vref, RX VrefLevel [Byte0]: 57
1089 19:55:07.571052 [Byte1]: 57
1090 19:55:07.575236
1091 19:55:07.575352 Set Vref, RX VrefLevel [Byte0]: 58
1092 19:55:07.578524 [Byte1]: 58
1093 19:55:07.582619
1094 19:55:07.582733 Set Vref, RX VrefLevel [Byte0]: 59
1095 19:55:07.586258 [Byte1]: 59
1096 19:55:07.590405
1097 19:55:07.590516 Set Vref, RX VrefLevel [Byte0]: 60
1098 19:55:07.593917 [Byte1]: 60
1099 19:55:07.598043
1100 19:55:07.598158 Set Vref, RX VrefLevel [Byte0]: 61
1101 19:55:07.601372 [Byte1]: 61
1102 19:55:07.606304
1103 19:55:07.606416 Set Vref, RX VrefLevel [Byte0]: 62
1104 19:55:07.609021 [Byte1]: 62
1105 19:55:07.613403
1106 19:55:07.613518 Set Vref, RX VrefLevel [Byte0]: 63
1107 19:55:07.616949 [Byte1]: 63
1108 19:55:07.621127
1109 19:55:07.621242 Set Vref, RX VrefLevel [Byte0]: 64
1110 19:55:07.624761 [Byte1]: 64
1111 19:55:07.629009
1112 19:55:07.629123 Set Vref, RX VrefLevel [Byte0]: 65
1113 19:55:07.632263 [Byte1]: 65
1114 19:55:07.636475
1115 19:55:07.636588 Set Vref, RX VrefLevel [Byte0]: 66
1116 19:55:07.639903 [Byte1]: 66
1117 19:55:07.644233
1118 19:55:07.644350 Set Vref, RX VrefLevel [Byte0]: 67
1119 19:55:07.648082 [Byte1]: 67
1120 19:55:07.651464
1121 19:55:07.651576 Set Vref, RX VrefLevel [Byte0]: 68
1122 19:55:07.655244 [Byte1]: 68
1123 19:55:07.659818
1124 19:55:07.659932 Set Vref, RX VrefLevel [Byte0]: 69
1125 19:55:07.662398 [Byte1]: 69
1126 19:55:07.667679
1127 19:55:07.667835 Set Vref, RX VrefLevel [Byte0]: 70
1128 19:55:07.670817 [Byte1]: 70
1129 19:55:07.674861
1130 19:55:07.677787 Set Vref, RX VrefLevel [Byte0]: 71
1131 19:55:07.681007 [Byte1]: 71
1132 19:55:07.681119
1133 19:55:07.684185 Set Vref, RX VrefLevel [Byte0]: 72
1134 19:55:07.687543 [Byte1]: 72
1135 19:55:07.687651
1136 19:55:07.691240 Set Vref, RX VrefLevel [Byte0]: 73
1137 19:55:07.694230 [Byte1]: 73
1138 19:55:07.697990
1139 19:55:07.698100 Set Vref, RX VrefLevel [Byte0]: 74
1140 19:55:07.700813 [Byte1]: 74
1141 19:55:07.705488
1142 19:55:07.705600 Set Vref, RX VrefLevel [Byte0]: 75
1143 19:55:07.708382 [Byte1]: 75
1144 19:55:07.712527
1145 19:55:07.712637 Set Vref, RX VrefLevel [Byte0]: 76
1146 19:55:07.715916 [Byte1]: 76
1147 19:55:07.720780
1148 19:55:07.720894 Set Vref, RX VrefLevel [Byte0]: 77
1149 19:55:07.724254 [Byte1]: 77
1150 19:55:07.727862
1151 19:55:07.727972 Set Vref, RX VrefLevel [Byte0]: 78
1152 19:55:07.731433 [Byte1]: 78
1153 19:55:07.735577
1154 19:55:07.735684 Set Vref, RX VrefLevel [Byte0]: 79
1155 19:55:07.738878 [Byte1]: 79
1156 19:55:07.743262
1157 19:55:07.743379 Set Vref, RX VrefLevel [Byte0]: 80
1158 19:55:07.746799 [Byte1]: 80
1159 19:55:07.751030
1160 19:55:07.751124 Set Vref, RX VrefLevel [Byte0]: 81
1161 19:55:07.754243 [Byte1]: 81
1162 19:55:07.758755
1163 19:55:07.758840 Final RX Vref Byte 0 = 64 to rank0
1164 19:55:07.761985 Final RX Vref Byte 1 = 60 to rank0
1165 19:55:07.765216 Final RX Vref Byte 0 = 64 to rank1
1166 19:55:07.768701 Final RX Vref Byte 1 = 60 to rank1==
1167 19:55:07.771906 Dram Type= 6, Freq= 0, CH_0, rank 0
1168 19:55:07.778619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1169 19:55:07.778724 ==
1170 19:55:07.778790 DQS Delay:
1171 19:55:07.778849 DQS0 = 0, DQS1 = 0
1172 19:55:07.782301 DQM Delay:
1173 19:55:07.782383 DQM0 = 86, DQM1 = 76
1174 19:55:07.785385 DQ Delay:
1175 19:55:07.788885 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1176 19:55:07.788969 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1177 19:55:07.792277 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =72
1178 19:55:07.798682 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1179 19:55:07.798777
1180 19:55:07.798842
1181 19:55:07.805678 [DQSOSCAuto] RK0, (LSB)MR18= 0x482a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1182 19:55:07.808546 CH0 RK0: MR19=606, MR18=482A
1183 19:55:07.815371 CH0_RK0: MR19=0x606, MR18=0x482A, DQSOSC=391, MR23=63, INC=96, DEC=64
1184 19:55:07.815502
1185 19:55:07.818633 ----->DramcWriteLeveling(PI) begin...
1186 19:55:07.818743 ==
1187 19:55:07.821755 Dram Type= 6, Freq= 0, CH_0, rank 1
1188 19:55:07.825170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 19:55:07.825280 ==
1190 19:55:07.828367 Write leveling (Byte 0): 35 => 35
1191 19:55:07.831754 Write leveling (Byte 1): 30 => 30
1192 19:55:07.835065 DramcWriteLeveling(PI) end<-----
1193 19:55:07.835174
1194 19:55:07.835266 ==
1195 19:55:07.839009 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 19:55:07.841957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1197 19:55:07.842070 ==
1198 19:55:07.886122 [Gating] SW mode calibration
1199 19:55:07.886533 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1200 19:55:07.886649 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1201 19:55:07.886756 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1202 19:55:07.887048 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1203 19:55:07.887147 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1204 19:55:07.887436 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 19:55:07.887550 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 19:55:07.887839 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 19:55:07.901654 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 19:55:07.901842 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 19:55:07.902148 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 19:55:07.905322 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 19:55:07.908061 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 19:55:07.911244 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 19:55:07.914694 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 19:55:07.918240 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 19:55:07.924546 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 19:55:07.927920 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 19:55:07.931123 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 19:55:07.937739 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 19:55:07.941318 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1220 19:55:07.944436 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1221 19:55:07.951241 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 19:55:07.954277 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 19:55:07.957639 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 19:55:07.964132 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 19:55:07.967695 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 19:55:07.970921 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 19:55:07.977344 0 9 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
1228 19:55:07.980715 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1229 19:55:07.984350 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 19:55:07.990740 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 19:55:07.994634 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 19:55:07.997308 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 19:55:08.004321 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 19:55:08.007426 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1235 19:55:08.010882 0 10 8 | B1->B0 | 3131 2626 | 0 0 | (0 1) (1 0)
1236 19:55:08.017404 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1237 19:55:08.020824 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 19:55:08.024133 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 19:55:08.030344 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 19:55:08.034242 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 19:55:08.037225 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 19:55:08.040454 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1243 19:55:08.047074 0 11 8 | B1->B0 | 2e2e 3f3f | 0 0 | (0 0) (0 0)
1244 19:55:08.051058 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1245 19:55:08.053836 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 19:55:08.060636 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 19:55:08.063946 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 19:55:08.067488 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 19:55:08.073884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 19:55:08.077450 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 19:55:08.081097 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1252 19:55:08.087433 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1253 19:55:08.091702 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 19:55:08.093872 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 19:55:08.100156 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 19:55:08.104161 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 19:55:08.107747 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 19:55:08.111293 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 19:55:08.118549 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 19:55:08.121956 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 19:55:08.125866 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 19:55:08.129374 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 19:55:08.132899 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 19:55:08.139710 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 19:55:08.143854 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 19:55:08.147527 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 19:55:08.151330 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1268 19:55:08.158258 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 19:55:08.158409 Total UI for P1: 0, mck2ui 16
1270 19:55:08.161868 best dqsien dly found for B0: ( 0, 14, 8)
1271 19:55:08.165404 Total UI for P1: 0, mck2ui 16
1272 19:55:08.168963 best dqsien dly found for B1: ( 0, 14, 8)
1273 19:55:08.172745 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1274 19:55:08.176383 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1275 19:55:08.176496
1276 19:55:08.179899 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1277 19:55:08.183684 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1278 19:55:08.186882 [Gating] SW calibration Done
1279 19:55:08.186994 ==
1280 19:55:08.190775 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 19:55:08.194260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 19:55:08.194374 ==
1283 19:55:08.197994 RX Vref Scan: 0
1284 19:55:08.198104
1285 19:55:08.198197 RX Vref 0 -> 0, step: 1
1286 19:55:08.198286
1287 19:55:08.201157 RX Delay -130 -> 252, step: 16
1288 19:55:08.205294 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1289 19:55:08.208844 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1290 19:55:08.212410 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1291 19:55:08.216223 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1292 19:55:08.219522 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1293 19:55:08.226681 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1294 19:55:08.230503 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1295 19:55:08.234191 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1296 19:55:08.238390 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1297 19:55:08.241485 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1298 19:55:08.245243 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1299 19:55:08.249135 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1300 19:55:08.252431 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1301 19:55:08.256325 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1302 19:55:08.260157 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1303 19:55:08.267480 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1304 19:55:08.267624 ==
1305 19:55:08.271074 Dram Type= 6, Freq= 0, CH_0, rank 1
1306 19:55:08.274568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1307 19:55:08.274691 ==
1308 19:55:08.274785 DQS Delay:
1309 19:55:08.278225 DQS0 = 0, DQS1 = 0
1310 19:55:08.278332 DQM Delay:
1311 19:55:08.278424 DQM0 = 84, DQM1 = 75
1312 19:55:08.281937 DQ Delay:
1313 19:55:08.282045 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1314 19:55:08.286046 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1315 19:55:08.289319 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
1316 19:55:08.293165 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1317 19:55:08.293280
1318 19:55:08.293374
1319 19:55:08.293462 ==
1320 19:55:08.296148 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 19:55:08.300680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 19:55:08.300797 ==
1323 19:55:08.300890
1324 19:55:08.300979
1325 19:55:08.304025 TX Vref Scan disable
1326 19:55:08.307025 == TX Byte 0 ==
1327 19:55:08.310533 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1328 19:55:08.314281 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1329 19:55:08.314396 == TX Byte 1 ==
1330 19:55:08.321460 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1331 19:55:08.324869 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1332 19:55:08.324999 ==
1333 19:55:08.328859 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 19:55:08.331967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 19:55:08.332080 ==
1336 19:55:08.346041 TX Vref=22, minBit 5, minWin=27, winSum=441
1337 19:55:08.349674 TX Vref=24, minBit 7, minWin=27, winSum=445
1338 19:55:08.353617 TX Vref=26, minBit 4, minWin=27, winSum=447
1339 19:55:08.357251 TX Vref=28, minBit 3, minWin=27, winSum=448
1340 19:55:08.361519 TX Vref=30, minBit 9, minWin=27, winSum=447
1341 19:55:08.364401 TX Vref=32, minBit 4, minWin=27, winSum=442
1342 19:55:08.368052 [TxChooseVref] Worse bit 3, Min win 27, Win sum 448, Final Vref 28
1343 19:55:08.372021
1344 19:55:08.372148 Final TX Range 1 Vref 28
1345 19:55:08.372244
1346 19:55:08.372333 ==
1347 19:55:08.375573 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 19:55:08.378686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 19:55:08.378798 ==
1350 19:55:08.378891
1351 19:55:08.382528
1352 19:55:08.382634 TX Vref Scan disable
1353 19:55:08.386125 == TX Byte 0 ==
1354 19:55:08.389715 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1355 19:55:08.393734 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1356 19:55:08.397098 == TX Byte 1 ==
1357 19:55:08.401284 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1358 19:55:08.404983 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1359 19:55:08.405102
1360 19:55:08.405195 [DATLAT]
1361 19:55:08.408452 Freq=800, CH0 RK1
1362 19:55:08.408559
1363 19:55:08.408650 DATLAT Default: 0xa
1364 19:55:08.412932 0, 0xFFFF, sum = 0
1365 19:55:08.413048 1, 0xFFFF, sum = 0
1366 19:55:08.413142 2, 0xFFFF, sum = 0
1367 19:55:08.416283 3, 0xFFFF, sum = 0
1368 19:55:08.416391 4, 0xFFFF, sum = 0
1369 19:55:08.420193 5, 0xFFFF, sum = 0
1370 19:55:08.420303 6, 0xFFFF, sum = 0
1371 19:55:08.423468 7, 0xFFFF, sum = 0
1372 19:55:08.423579 8, 0xFFFF, sum = 0
1373 19:55:08.427086 9, 0x0, sum = 1
1374 19:55:08.427197 10, 0x0, sum = 2
1375 19:55:08.427291 11, 0x0, sum = 3
1376 19:55:08.431082 12, 0x0, sum = 4
1377 19:55:08.431196 best_step = 10
1378 19:55:08.431289
1379 19:55:08.431377 ==
1380 19:55:08.434760 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 19:55:08.438823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 19:55:08.438943 ==
1383 19:55:08.442285 RX Vref Scan: 0
1384 19:55:08.442403
1385 19:55:08.442496 RX Vref 0 -> 0, step: 1
1386 19:55:08.442584
1387 19:55:08.445357 RX Delay -111 -> 252, step: 8
1388 19:55:08.452048 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1389 19:55:08.455366 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1390 19:55:08.458767 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1391 19:55:08.462583 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1392 19:55:08.468782 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1393 19:55:08.472470 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1394 19:55:08.475095 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1395 19:55:08.478683 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1396 19:55:08.482022 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1397 19:55:08.488534 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1398 19:55:08.491888 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1399 19:55:08.495202 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1400 19:55:08.498727 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1401 19:55:08.501640 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1402 19:55:08.508564 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1403 19:55:08.511845 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1404 19:55:08.511963 ==
1405 19:55:08.515168 Dram Type= 6, Freq= 0, CH_0, rank 1
1406 19:55:08.518815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 19:55:08.518900 ==
1408 19:55:08.522172 DQS Delay:
1409 19:55:08.522255 DQS0 = 0, DQS1 = 0
1410 19:55:08.522318 DQM Delay:
1411 19:55:08.525440 DQM0 = 86, DQM1 = 77
1412 19:55:08.525522 DQ Delay:
1413 19:55:08.528584 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1414 19:55:08.531741 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1415 19:55:08.535190 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1416 19:55:08.538159 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =84
1417 19:55:08.538242
1418 19:55:08.538305
1419 19:55:08.548078 [DQSOSCAuto] RK1, (LSB)MR18= 0x450b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
1420 19:55:08.548216 CH0 RK1: MR19=606, MR18=450B
1421 19:55:08.554918 CH0_RK1: MR19=0x606, MR18=0x450B, DQSOSC=392, MR23=63, INC=96, DEC=64
1422 19:55:08.558151 [RxdqsGatingPostProcess] freq 800
1423 19:55:08.564759 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1424 19:55:08.568595 Pre-setting of DQS Precalculation
1425 19:55:08.571296 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1426 19:55:08.571406 ==
1427 19:55:08.574589 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 19:55:08.581758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 19:55:08.581895 ==
1430 19:55:08.584572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1431 19:55:08.591149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1432 19:55:08.600851 [CA 0] Center 36 (6~67) winsize 62
1433 19:55:08.603674 [CA 1] Center 36 (6~67) winsize 62
1434 19:55:08.607033 [CA 2] Center 34 (4~65) winsize 62
1435 19:55:08.610606 [CA 3] Center 34 (3~65) winsize 63
1436 19:55:08.613679 [CA 4] Center 34 (4~65) winsize 62
1437 19:55:08.617115 [CA 5] Center 34 (3~65) winsize 63
1438 19:55:08.617202
1439 19:55:08.620290 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1440 19:55:08.620382
1441 19:55:08.623595 [CATrainingPosCal] consider 1 rank data
1442 19:55:08.627165 u2DelayCellTimex100 = 270/100 ps
1443 19:55:08.630526 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1444 19:55:08.636736 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1445 19:55:08.640371 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1446 19:55:08.643898 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1447 19:55:08.646735 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1448 19:55:08.649965 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1449 19:55:08.650080
1450 19:55:08.653501 CA PerBit enable=1, Macro0, CA PI delay=34
1451 19:55:08.653615
1452 19:55:08.656506 [CBTSetCACLKResult] CA Dly = 34
1453 19:55:08.660069 CS Dly: 5 (0~36)
1454 19:55:08.660178 ==
1455 19:55:08.663365 Dram Type= 6, Freq= 0, CH_1, rank 1
1456 19:55:08.666695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 19:55:08.666804 ==
1458 19:55:08.670301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1459 19:55:08.677112 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1460 19:55:08.686830 [CA 0] Center 36 (6~67) winsize 62
1461 19:55:08.690089 [CA 1] Center 36 (6~67) winsize 62
1462 19:55:08.693308 [CA 2] Center 34 (4~65) winsize 62
1463 19:55:08.696594 [CA 3] Center 34 (3~65) winsize 63
1464 19:55:08.699918 [CA 4] Center 34 (4~65) winsize 62
1465 19:55:08.703003 [CA 5] Center 34 (3~65) winsize 63
1466 19:55:08.703112
1467 19:55:08.706434 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1468 19:55:08.706543
1469 19:55:08.710175 [CATrainingPosCal] consider 2 rank data
1470 19:55:08.713205 u2DelayCellTimex100 = 270/100 ps
1471 19:55:08.716631 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 19:55:08.723151 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1473 19:55:08.727080 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 19:55:08.730347 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1475 19:55:08.733700 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 19:55:08.736594 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1477 19:55:08.736707
1478 19:55:08.739702 CA PerBit enable=1, Macro0, CA PI delay=34
1479 19:55:08.739817
1480 19:55:08.743253 [CBTSetCACLKResult] CA Dly = 34
1481 19:55:08.743371 CS Dly: 6 (0~38)
1482 19:55:08.746225
1483 19:55:08.749781 ----->DramcWriteLeveling(PI) begin...
1484 19:55:08.749896 ==
1485 19:55:08.753649 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 19:55:08.756266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1487 19:55:08.756375 ==
1488 19:55:08.759412 Write leveling (Byte 0): 27 => 27
1489 19:55:08.762998 Write leveling (Byte 1): 27 => 27
1490 19:55:08.766402 DramcWriteLeveling(PI) end<-----
1491 19:55:08.766516
1492 19:55:08.766609 ==
1493 19:55:08.769735 Dram Type= 6, Freq= 0, CH_1, rank 0
1494 19:55:08.772874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1495 19:55:08.772986 ==
1496 19:55:08.776386 [Gating] SW mode calibration
1497 19:55:08.782689 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1498 19:55:08.789295 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1499 19:55:08.792814 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1500 19:55:08.796209 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1501 19:55:08.802591 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 19:55:08.806180 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 19:55:08.809475 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 19:55:08.815974 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 19:55:08.819229 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 19:55:08.822313 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 19:55:08.829569 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 19:55:08.833164 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 19:55:08.835573 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 19:55:08.842197 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 19:55:08.845470 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 19:55:08.849169 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 19:55:08.855554 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 19:55:08.858737 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 19:55:08.861898 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1516 19:55:08.869239 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1517 19:55:08.871825 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 19:55:08.875151 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 19:55:08.882384 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 19:55:08.885537 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 19:55:08.888703 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 19:55:08.895802 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 19:55:08.898723 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 19:55:08.901936 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1525 19:55:08.905444 0 9 8 | B1->B0 | 2c2c 3231 | 0 1 | (0 0) (0 0)
1526 19:55:08.911693 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 19:55:08.915365 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 19:55:08.918402 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 19:55:08.925342 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 19:55:08.928721 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 19:55:08.931611 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 19:55:08.938083 0 10 4 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
1533 19:55:08.941721 0 10 8 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
1534 19:55:08.944749 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 19:55:08.951491 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 19:55:08.955051 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 19:55:08.958191 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 19:55:08.964842 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 19:55:08.968259 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 19:55:08.971542 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1541 19:55:08.977946 0 11 8 | B1->B0 | 3b3b 4040 | 0 0 | (0 0) (0 0)
1542 19:55:08.981748 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 19:55:08.984639 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 19:55:08.991029 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 19:55:08.994878 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 19:55:08.998158 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 19:55:09.004379 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 19:55:09.008327 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1549 19:55:09.011350 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 19:55:09.017695 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 19:55:09.020969 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 19:55:09.024520 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 19:55:09.030871 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 19:55:09.034265 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 19:55:09.037596 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 19:55:09.044107 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 19:55:09.047543 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 19:55:09.050967 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 19:55:09.057921 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 19:55:09.060845 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 19:55:09.064341 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 19:55:09.071294 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 19:55:09.074124 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 19:55:09.077489 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1565 19:55:09.084089 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 19:55:09.084198 Total UI for P1: 0, mck2ui 16
1567 19:55:09.090691 best dqsien dly found for B0: ( 0, 14, 4)
1568 19:55:09.090790 Total UI for P1: 0, mck2ui 16
1569 19:55:09.093749 best dqsien dly found for B1: ( 0, 14, 4)
1570 19:55:09.100563 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1571 19:55:09.103922 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1572 19:55:09.104013
1573 19:55:09.107042 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1574 19:55:09.110584 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1575 19:55:09.113866 [Gating] SW calibration Done
1576 19:55:09.113952 ==
1577 19:55:09.117369 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 19:55:09.120678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 19:55:09.120766 ==
1580 19:55:09.123975 RX Vref Scan: 0
1581 19:55:09.124060
1582 19:55:09.124124 RX Vref 0 -> 0, step: 1
1583 19:55:09.124184
1584 19:55:09.127160 RX Delay -130 -> 252, step: 16
1585 19:55:09.130425 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1586 19:55:09.137091 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1587 19:55:09.140264 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1588 19:55:09.143677 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1589 19:55:09.146946 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1590 19:55:09.151177 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1591 19:55:09.157324 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1592 19:55:09.160393 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1593 19:55:09.163554 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1594 19:55:09.166969 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1595 19:55:09.170054 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1596 19:55:09.176703 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1597 19:55:09.180085 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1598 19:55:09.184063 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1599 19:55:09.187055 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1600 19:55:09.191018 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1601 19:55:09.193465 ==
1602 19:55:09.197217 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 19:55:09.200016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 19:55:09.200144 ==
1605 19:55:09.200210 DQS Delay:
1606 19:55:09.203333 DQS0 = 0, DQS1 = 0
1607 19:55:09.203417 DQM Delay:
1608 19:55:09.206775 DQM0 = 89, DQM1 = 78
1609 19:55:09.206860 DQ Delay:
1610 19:55:09.210308 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1611 19:55:09.213626 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1612 19:55:09.216614 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1613 19:55:09.220193 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1614 19:55:09.220278
1615 19:55:09.220343
1616 19:55:09.220403 ==
1617 19:55:09.223645 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 19:55:09.226770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 19:55:09.226855 ==
1620 19:55:09.226920
1621 19:55:09.226979
1622 19:55:09.229781 TX Vref Scan disable
1623 19:55:09.232998 == TX Byte 0 ==
1624 19:55:09.236489 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1625 19:55:09.240147 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1626 19:55:09.243657 == TX Byte 1 ==
1627 19:55:09.246520 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1628 19:55:09.250183 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1629 19:55:09.250277 ==
1630 19:55:09.252993 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 19:55:09.259424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 19:55:09.259525 ==
1633 19:55:09.271042 TX Vref=22, minBit 10, minWin=26, winSum=445
1634 19:55:09.274852 TX Vref=24, minBit 8, minWin=27, winSum=446
1635 19:55:09.278011 TX Vref=26, minBit 9, minWin=27, winSum=449
1636 19:55:09.281714 TX Vref=28, minBit 1, minWin=28, winSum=454
1637 19:55:09.284413 TX Vref=30, minBit 9, minWin=27, winSum=448
1638 19:55:09.291467 TX Vref=32, minBit 0, minWin=27, winSum=444
1639 19:55:09.294854 [TxChooseVref] Worse bit 1, Min win 28, Win sum 454, Final Vref 28
1640 19:55:09.294948
1641 19:55:09.297896 Final TX Range 1 Vref 28
1642 19:55:09.297980
1643 19:55:09.298045 ==
1644 19:55:09.301120 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 19:55:09.304951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 19:55:09.305051 ==
1647 19:55:09.307914
1648 19:55:09.307996
1649 19:55:09.308061 TX Vref Scan disable
1650 19:55:09.311342 == TX Byte 0 ==
1651 19:55:09.314698 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1652 19:55:09.317998 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1653 19:55:09.321485 == TX Byte 1 ==
1654 19:55:09.324289 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1655 19:55:09.330947 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1656 19:55:09.331045
1657 19:55:09.331111 [DATLAT]
1658 19:55:09.331172 Freq=800, CH1 RK0
1659 19:55:09.331229
1660 19:55:09.334320 DATLAT Default: 0xa
1661 19:55:09.334402 0, 0xFFFF, sum = 0
1662 19:55:09.337780 1, 0xFFFF, sum = 0
1663 19:55:09.337866 2, 0xFFFF, sum = 0
1664 19:55:09.341193 3, 0xFFFF, sum = 0
1665 19:55:09.344744 4, 0xFFFF, sum = 0
1666 19:55:09.344837 5, 0xFFFF, sum = 0
1667 19:55:09.348467 6, 0xFFFF, sum = 0
1668 19:55:09.348553 7, 0xFFFF, sum = 0
1669 19:55:09.350843 8, 0xFFFF, sum = 0
1670 19:55:09.350928 9, 0x0, sum = 1
1671 19:55:09.354358 10, 0x0, sum = 2
1672 19:55:09.354443 11, 0x0, sum = 3
1673 19:55:09.354508 12, 0x0, sum = 4
1674 19:55:09.357505 best_step = 10
1675 19:55:09.357588
1676 19:55:09.357653 ==
1677 19:55:09.361098 Dram Type= 6, Freq= 0, CH_1, rank 0
1678 19:55:09.364125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1679 19:55:09.364210 ==
1680 19:55:09.367605 RX Vref Scan: 1
1681 19:55:09.367689
1682 19:55:09.371055 Set Vref Range= 32 -> 127
1683 19:55:09.371138
1684 19:55:09.371203 RX Vref 32 -> 127, step: 1
1685 19:55:09.371263
1686 19:55:09.374434 RX Delay -95 -> 252, step: 8
1687 19:55:09.374518
1688 19:55:09.378145 Set Vref, RX VrefLevel [Byte0]: 32
1689 19:55:09.380699 [Byte1]: 32
1690 19:55:09.380785
1691 19:55:09.383977 Set Vref, RX VrefLevel [Byte0]: 33
1692 19:55:09.387308 [Byte1]: 33
1693 19:55:09.391530
1694 19:55:09.391617 Set Vref, RX VrefLevel [Byte0]: 34
1695 19:55:09.396155 [Byte1]: 34
1696 19:55:09.399075
1697 19:55:09.399197 Set Vref, RX VrefLevel [Byte0]: 35
1698 19:55:09.402667 [Byte1]: 35
1699 19:55:09.406846
1700 19:55:09.406934 Set Vref, RX VrefLevel [Byte0]: 36
1701 19:55:09.409882 [Byte1]: 36
1702 19:55:09.414405
1703 19:55:09.414493 Set Vref, RX VrefLevel [Byte0]: 37
1704 19:55:09.417794 [Byte1]: 37
1705 19:55:09.422246
1706 19:55:09.422333 Set Vref, RX VrefLevel [Byte0]: 38
1707 19:55:09.425269 [Byte1]: 38
1708 19:55:09.429710
1709 19:55:09.429799 Set Vref, RX VrefLevel [Byte0]: 39
1710 19:55:09.432809 [Byte1]: 39
1711 19:55:09.437210
1712 19:55:09.437297 Set Vref, RX VrefLevel [Byte0]: 40
1713 19:55:09.440535 [Byte1]: 40
1714 19:55:09.445131
1715 19:55:09.445231 Set Vref, RX VrefLevel [Byte0]: 41
1716 19:55:09.447885 [Byte1]: 41
1717 19:55:09.452595
1718 19:55:09.452693 Set Vref, RX VrefLevel [Byte0]: 42
1719 19:55:09.456071 [Byte1]: 42
1720 19:55:09.460140
1721 19:55:09.460228 Set Vref, RX VrefLevel [Byte0]: 43
1722 19:55:09.463470 [Byte1]: 43
1723 19:55:09.467376
1724 19:55:09.467462 Set Vref, RX VrefLevel [Byte0]: 44
1725 19:55:09.471015 [Byte1]: 44
1726 19:55:09.475033
1727 19:55:09.475120 Set Vref, RX VrefLevel [Byte0]: 45
1728 19:55:09.478320 [Byte1]: 45
1729 19:55:09.482621
1730 19:55:09.482711 Set Vref, RX VrefLevel [Byte0]: 46
1731 19:55:09.486383 [Byte1]: 46
1732 19:55:09.490348
1733 19:55:09.490436 Set Vref, RX VrefLevel [Byte0]: 47
1734 19:55:09.493787 [Byte1]: 47
1735 19:55:09.498181
1736 19:55:09.498268 Set Vref, RX VrefLevel [Byte0]: 48
1737 19:55:09.501031 [Byte1]: 48
1738 19:55:09.505572
1739 19:55:09.505662 Set Vref, RX VrefLevel [Byte0]: 49
1740 19:55:09.509014 [Byte1]: 49
1741 19:55:09.513580
1742 19:55:09.513670 Set Vref, RX VrefLevel [Byte0]: 50
1743 19:55:09.516644 [Byte1]: 50
1744 19:55:09.520609
1745 19:55:09.520700 Set Vref, RX VrefLevel [Byte0]: 51
1746 19:55:09.524497 [Byte1]: 51
1747 19:55:09.528711
1748 19:55:09.528798 Set Vref, RX VrefLevel [Byte0]: 52
1749 19:55:09.531601 [Byte1]: 52
1750 19:55:09.535835
1751 19:55:09.535921 Set Vref, RX VrefLevel [Byte0]: 53
1752 19:55:09.539331 [Byte1]: 53
1753 19:55:09.543663
1754 19:55:09.543801 Set Vref, RX VrefLevel [Byte0]: 54
1755 19:55:09.546643 [Byte1]: 54
1756 19:55:09.551702
1757 19:55:09.551822 Set Vref, RX VrefLevel [Byte0]: 55
1758 19:55:09.554659 [Byte1]: 55
1759 19:55:09.558606
1760 19:55:09.558686 Set Vref, RX VrefLevel [Byte0]: 56
1761 19:55:09.561962 [Byte1]: 56
1762 19:55:09.566224
1763 19:55:09.566304 Set Vref, RX VrefLevel [Byte0]: 57
1764 19:55:09.569604 [Byte1]: 57
1765 19:55:09.573927
1766 19:55:09.574008 Set Vref, RX VrefLevel [Byte0]: 58
1767 19:55:09.577311 [Byte1]: 58
1768 19:55:09.581441
1769 19:55:09.581522 Set Vref, RX VrefLevel [Byte0]: 59
1770 19:55:09.585047 [Byte1]: 59
1771 19:55:09.589064
1772 19:55:09.589145 Set Vref, RX VrefLevel [Byte0]: 60
1773 19:55:09.592412 [Byte1]: 60
1774 19:55:09.596606
1775 19:55:09.596687 Set Vref, RX VrefLevel [Byte0]: 61
1776 19:55:09.599677 [Byte1]: 61
1777 19:55:09.604064
1778 19:55:09.604147 Set Vref, RX VrefLevel [Byte0]: 62
1779 19:55:09.607361 [Byte1]: 62
1780 19:55:09.611851
1781 19:55:09.611931 Set Vref, RX VrefLevel [Byte0]: 63
1782 19:55:09.615251 [Byte1]: 63
1783 19:55:09.619401
1784 19:55:09.619502 Set Vref, RX VrefLevel [Byte0]: 64
1785 19:55:09.622838 [Byte1]: 64
1786 19:55:09.627347
1787 19:55:09.627427 Set Vref, RX VrefLevel [Byte0]: 65
1788 19:55:09.630365 [Byte1]: 65
1789 19:55:09.634782
1790 19:55:09.634861 Set Vref, RX VrefLevel [Byte0]: 66
1791 19:55:09.637761 [Byte1]: 66
1792 19:55:09.642288
1793 19:55:09.642368 Set Vref, RX VrefLevel [Byte0]: 67
1794 19:55:09.645848 [Byte1]: 67
1795 19:55:09.650211
1796 19:55:09.650292 Set Vref, RX VrefLevel [Byte0]: 68
1797 19:55:09.653014 [Byte1]: 68
1798 19:55:09.657538
1799 19:55:09.657619 Set Vref, RX VrefLevel [Byte0]: 69
1800 19:55:09.660635 [Byte1]: 69
1801 19:55:09.665279
1802 19:55:09.665360 Set Vref, RX VrefLevel [Byte0]: 70
1803 19:55:09.668192 [Byte1]: 70
1804 19:55:09.672578
1805 19:55:09.672659 Set Vref, RX VrefLevel [Byte0]: 71
1806 19:55:09.676304 [Byte1]: 71
1807 19:55:09.680208
1808 19:55:09.680287 Set Vref, RX VrefLevel [Byte0]: 72
1809 19:55:09.683545 [Byte1]: 72
1810 19:55:09.687846
1811 19:55:09.687926 Set Vref, RX VrefLevel [Byte0]: 73
1812 19:55:09.691654 [Byte1]: 73
1813 19:55:09.695563
1814 19:55:09.695643 Set Vref, RX VrefLevel [Byte0]: 74
1815 19:55:09.698744 [Byte1]: 74
1816 19:55:09.703060
1817 19:55:09.703140 Set Vref, RX VrefLevel [Byte0]: 75
1818 19:55:09.706369 [Byte1]: 75
1819 19:55:09.710668
1820 19:55:09.710775 Set Vref, RX VrefLevel [Byte0]: 76
1821 19:55:09.713813 [Byte1]: 76
1822 19:55:09.718162
1823 19:55:09.718242 Final RX Vref Byte 0 = 57 to rank0
1824 19:55:09.721438 Final RX Vref Byte 1 = 63 to rank0
1825 19:55:09.724493 Final RX Vref Byte 0 = 57 to rank1
1826 19:55:09.727976 Final RX Vref Byte 1 = 63 to rank1==
1827 19:55:09.731704 Dram Type= 6, Freq= 0, CH_1, rank 0
1828 19:55:09.737934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1829 19:55:09.738015 ==
1830 19:55:09.738081 DQS Delay:
1831 19:55:09.741254 DQS0 = 0, DQS1 = 0
1832 19:55:09.741335 DQM Delay:
1833 19:55:09.741398 DQM0 = 86, DQM1 = 78
1834 19:55:09.744757 DQ Delay:
1835 19:55:09.748144 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1836 19:55:09.751175 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1837 19:55:09.754445 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1838 19:55:09.757702 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
1839 19:55:09.757784
1840 19:55:09.757848
1841 19:55:09.764538 [DQSOSCAuto] RK0, (LSB)MR18= 0x3420, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1842 19:55:09.767637 CH1 RK0: MR19=606, MR18=3420
1843 19:55:09.774329 CH1_RK0: MR19=0x606, MR18=0x3420, DQSOSC=396, MR23=63, INC=94, DEC=62
1844 19:55:09.774412
1845 19:55:09.777850 ----->DramcWriteLeveling(PI) begin...
1846 19:55:09.777938 ==
1847 19:55:09.780841 Dram Type= 6, Freq= 0, CH_1, rank 1
1848 19:55:09.784263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 19:55:09.784345 ==
1850 19:55:09.787583 Write leveling (Byte 0): 28 => 28
1851 19:55:09.791134 Write leveling (Byte 1): 29 => 29
1852 19:55:09.794394 DramcWriteLeveling(PI) end<-----
1853 19:55:09.794474
1854 19:55:09.794537 ==
1855 19:55:09.797633 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 19:55:09.800927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 19:55:09.801008 ==
1858 19:55:09.804843 [Gating] SW mode calibration
1859 19:55:09.810811 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1860 19:55:09.817344 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1861 19:55:09.820776 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1862 19:55:09.827398 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1863 19:55:09.830654 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 19:55:09.833847 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 19:55:09.840905 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 19:55:09.844459 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 19:55:09.847753 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 19:55:09.853851 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 19:55:09.857045 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 19:55:09.860843 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 19:55:09.867391 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 19:55:09.870365 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 19:55:09.873619 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 19:55:09.880226 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 19:55:09.883520 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 19:55:09.886828 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 19:55:09.893413 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1878 19:55:09.896806 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1879 19:55:09.899756 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 19:55:09.906472 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 19:55:09.909704 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 19:55:09.913408 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 19:55:09.919842 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 19:55:09.924078 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 19:55:09.926157 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 19:55:09.933034 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 19:55:09.936063 0 9 8 | B1->B0 | 3434 2626 | 0 1 | (0 0) (1 1)
1888 19:55:09.939472 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 19:55:09.946167 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 19:55:09.949602 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 19:55:09.952803 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 19:55:09.959437 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 19:55:09.962443 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 19:55:09.965860 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
1895 19:55:09.972541 0 10 8 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
1896 19:55:09.976055 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 19:55:09.979112 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 19:55:09.986116 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 19:55:09.989333 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 19:55:09.992456 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 19:55:09.995764 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 19:55:10.002787 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1903 19:55:10.005961 0 11 8 | B1->B0 | 4444 3838 | 0 0 | (0 0) (0 0)
1904 19:55:10.009183 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 19:55:10.015962 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 19:55:10.020042 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 19:55:10.022470 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 19:55:10.029613 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 19:55:10.033776 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 19:55:10.035833 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 19:55:10.042387 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 19:55:10.045826 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 19:55:10.049243 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 19:55:10.055768 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 19:55:10.059100 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 19:55:10.062026 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 19:55:10.068699 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 19:55:10.072377 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 19:55:10.075862 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 19:55:10.082261 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 19:55:10.085459 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 19:55:10.089189 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 19:55:10.095663 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 19:55:10.098483 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 19:55:10.102153 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 19:55:10.108761 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1927 19:55:10.112277 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1928 19:55:10.115655 Total UI for P1: 0, mck2ui 16
1929 19:55:10.118475 best dqsien dly found for B1: ( 0, 14, 4)
1930 19:55:10.121869 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 19:55:10.124966 Total UI for P1: 0, mck2ui 16
1932 19:55:10.128096 best dqsien dly found for B0: ( 0, 14, 6)
1933 19:55:10.131837 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1934 19:55:10.135023 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1935 19:55:10.135103
1936 19:55:10.141751 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1937 19:55:10.144957 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1938 19:55:10.145038 [Gating] SW calibration Done
1939 19:55:10.148829 ==
1940 19:55:10.151917 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 19:55:10.155019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 19:55:10.155101 ==
1943 19:55:10.155165 RX Vref Scan: 0
1944 19:55:10.155225
1945 19:55:10.157838 RX Vref 0 -> 0, step: 1
1946 19:55:10.157918
1947 19:55:10.161638 RX Delay -130 -> 252, step: 16
1948 19:55:10.164853 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1949 19:55:10.168170 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1950 19:55:10.174470 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1951 19:55:10.177822 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1952 19:55:10.181696 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1953 19:55:10.184460 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1954 19:55:10.187612 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1955 19:55:10.194285 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1956 19:55:10.197820 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1957 19:55:10.201225 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1958 19:55:10.204017 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1959 19:55:10.207423 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1960 19:55:10.214174 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1961 19:55:10.217593 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1962 19:55:10.220813 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1963 19:55:10.224550 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1964 19:55:10.224646 ==
1965 19:55:10.227345 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 19:55:10.233881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 19:55:10.233967 ==
1968 19:55:10.234033 DQS Delay:
1969 19:55:10.237446 DQS0 = 0, DQS1 = 0
1970 19:55:10.237529 DQM Delay:
1971 19:55:10.237594 DQM0 = 86, DQM1 = 78
1972 19:55:10.240937 DQ Delay:
1973 19:55:10.244159 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1974 19:55:10.247268 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1975 19:55:10.250545 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1976 19:55:10.253954 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1977 19:55:10.254044
1978 19:55:10.254129
1979 19:55:10.254210 ==
1980 19:55:10.257270 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 19:55:10.260617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 19:55:10.260704 ==
1983 19:55:10.260789
1984 19:55:10.260885
1985 19:55:10.263657 TX Vref Scan disable
1986 19:55:10.267008 == TX Byte 0 ==
1987 19:55:10.270600 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1988 19:55:10.273811 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1989 19:55:10.277044 == TX Byte 1 ==
1990 19:55:10.280559 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1991 19:55:10.283625 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1992 19:55:10.283708 ==
1993 19:55:10.287200 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 19:55:10.290065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 19:55:10.294003 ==
1996 19:55:10.304909 TX Vref=22, minBit 8, minWin=27, winSum=445
1997 19:55:10.308309 TX Vref=24, minBit 8, minWin=27, winSum=449
1998 19:55:10.311324 TX Vref=26, minBit 8, minWin=27, winSum=451
1999 19:55:10.314735 TX Vref=28, minBit 15, minWin=27, winSum=451
2000 19:55:10.318149 TX Vref=30, minBit 8, minWin=27, winSum=448
2001 19:55:10.325258 TX Vref=32, minBit 8, minWin=27, winSum=448
2002 19:55:10.328441 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 26
2003 19:55:10.328527
2004 19:55:10.331525 Final TX Range 1 Vref 26
2005 19:55:10.331607
2006 19:55:10.331672 ==
2007 19:55:10.334901 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 19:55:10.338006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 19:55:10.338089 ==
2010 19:55:10.341299
2011 19:55:10.341380
2012 19:55:10.341445 TX Vref Scan disable
2013 19:55:10.344768 == TX Byte 0 ==
2014 19:55:10.348221 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2015 19:55:10.354574 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2016 19:55:10.354674 == TX Byte 1 ==
2017 19:55:10.358466 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2018 19:55:10.365092 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2019 19:55:10.365190
2020 19:55:10.365256 [DATLAT]
2021 19:55:10.365316 Freq=800, CH1 RK1
2022 19:55:10.365373
2023 19:55:10.368115 DATLAT Default: 0xa
2024 19:55:10.368197 0, 0xFFFF, sum = 0
2025 19:55:10.371324 1, 0xFFFF, sum = 0
2026 19:55:10.371406 2, 0xFFFF, sum = 0
2027 19:55:10.374773 3, 0xFFFF, sum = 0
2028 19:55:10.378462 4, 0xFFFF, sum = 0
2029 19:55:10.378547 5, 0xFFFF, sum = 0
2030 19:55:10.381637 6, 0xFFFF, sum = 0
2031 19:55:10.381720 7, 0xFFFF, sum = 0
2032 19:55:10.384844 8, 0xFFFF, sum = 0
2033 19:55:10.384926 9, 0x0, sum = 1
2034 19:55:10.388439 10, 0x0, sum = 2
2035 19:55:10.388521 11, 0x0, sum = 3
2036 19:55:10.388586 12, 0x0, sum = 4
2037 19:55:10.391291 best_step = 10
2038 19:55:10.391371
2039 19:55:10.391435 ==
2040 19:55:10.394829 Dram Type= 6, Freq= 0, CH_1, rank 1
2041 19:55:10.398156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2042 19:55:10.398247 ==
2043 19:55:10.401101 RX Vref Scan: 0
2044 19:55:10.401186
2045 19:55:10.404417 RX Vref 0 -> 0, step: 1
2046 19:55:10.404505
2047 19:55:10.404571 RX Delay -95 -> 252, step: 8
2048 19:55:10.411455 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2049 19:55:10.414772 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2050 19:55:10.418403 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2051 19:55:10.421498 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2052 19:55:10.424770 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2053 19:55:10.431422 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2054 19:55:10.434969 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2055 19:55:10.438340 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2056 19:55:10.441235 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2057 19:55:10.448318 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2058 19:55:10.451094 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2059 19:55:10.454353 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2060 19:55:10.457865 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2061 19:55:10.461571 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2062 19:55:10.468176 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2063 19:55:10.471696 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2064 19:55:10.471844 ==
2065 19:55:10.474600 Dram Type= 6, Freq= 0, CH_1, rank 1
2066 19:55:10.478985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2067 19:55:10.479098 ==
2068 19:55:10.481555 DQS Delay:
2069 19:55:10.481637 DQS0 = 0, DQS1 = 0
2070 19:55:10.481703 DQM Delay:
2071 19:55:10.484631 DQM0 = 87, DQM1 = 79
2072 19:55:10.484717 DQ Delay:
2073 19:55:10.487552 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2074 19:55:10.491073 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2075 19:55:10.494293 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =72
2076 19:55:10.497528 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2077 19:55:10.497611
2078 19:55:10.497675
2079 19:55:10.507470 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2080 19:55:10.510992 CH1 RK1: MR19=606, MR18=1A12
2081 19:55:10.514722 CH1_RK1: MR19=0x606, MR18=0x1A12, DQSOSC=403, MR23=63, INC=90, DEC=60
2082 19:55:10.518034 [RxdqsGatingPostProcess] freq 800
2083 19:55:10.524267 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2084 19:55:10.527472 Pre-setting of DQS Precalculation
2085 19:55:10.530841 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2086 19:55:10.537477 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2087 19:55:10.547371 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2088 19:55:10.547472
2089 19:55:10.547538
2090 19:55:10.551441 [Calibration Summary] 1600 Mbps
2091 19:55:10.551526 CH 0, Rank 0
2092 19:55:10.553948 SW Impedance : PASS
2093 19:55:10.554031 DUTY Scan : NO K
2094 19:55:10.557391 ZQ Calibration : PASS
2095 19:55:10.560597 Jitter Meter : NO K
2096 19:55:10.560680 CBT Training : PASS
2097 19:55:10.564056 Write leveling : PASS
2098 19:55:10.567058 RX DQS gating : PASS
2099 19:55:10.567141 RX DQ/DQS(RDDQC) : PASS
2100 19:55:10.571123 TX DQ/DQS : PASS
2101 19:55:10.574433 RX DATLAT : PASS
2102 19:55:10.574515 RX DQ/DQS(Engine): PASS
2103 19:55:10.577952 TX OE : NO K
2104 19:55:10.578035 All Pass.
2105 19:55:10.578099
2106 19:55:10.580773 CH 0, Rank 1
2107 19:55:10.580855 SW Impedance : PASS
2108 19:55:10.583688 DUTY Scan : NO K
2109 19:55:10.583787 ZQ Calibration : PASS
2110 19:55:10.587027 Jitter Meter : NO K
2111 19:55:10.590155 CBT Training : PASS
2112 19:55:10.590237 Write leveling : PASS
2113 19:55:10.594205 RX DQS gating : PASS
2114 19:55:10.596986 RX DQ/DQS(RDDQC) : PASS
2115 19:55:10.597068 TX DQ/DQS : PASS
2116 19:55:10.600468 RX DATLAT : PASS
2117 19:55:10.603807 RX DQ/DQS(Engine): PASS
2118 19:55:10.603889 TX OE : NO K
2119 19:55:10.607180 All Pass.
2120 19:55:10.607262
2121 19:55:10.607327 CH 1, Rank 0
2122 19:55:10.610241 SW Impedance : PASS
2123 19:55:10.610323 DUTY Scan : NO K
2124 19:55:10.613595 ZQ Calibration : PASS
2125 19:55:10.617073 Jitter Meter : NO K
2126 19:55:10.617154 CBT Training : PASS
2127 19:55:10.620218 Write leveling : PASS
2128 19:55:10.623462 RX DQS gating : PASS
2129 19:55:10.623543 RX DQ/DQS(RDDQC) : PASS
2130 19:55:10.626959 TX DQ/DQS : PASS
2131 19:55:10.630488 RX DATLAT : PASS
2132 19:55:10.630569 RX DQ/DQS(Engine): PASS
2133 19:55:10.633597 TX OE : NO K
2134 19:55:10.633677 All Pass.
2135 19:55:10.633742
2136 19:55:10.637280 CH 1, Rank 1
2137 19:55:10.637360 SW Impedance : PASS
2138 19:55:10.640078 DUTY Scan : NO K
2139 19:55:10.640160 ZQ Calibration : PASS
2140 19:55:10.643334 Jitter Meter : NO K
2141 19:55:10.647162 CBT Training : PASS
2142 19:55:10.647243 Write leveling : PASS
2143 19:55:10.650090 RX DQS gating : PASS
2144 19:55:10.653179 RX DQ/DQS(RDDQC) : PASS
2145 19:55:10.653261 TX DQ/DQS : PASS
2146 19:55:10.656915 RX DATLAT : PASS
2147 19:55:10.660084 RX DQ/DQS(Engine): PASS
2148 19:55:10.660166 TX OE : NO K
2149 19:55:10.663234 All Pass.
2150 19:55:10.663314
2151 19:55:10.663379 DramC Write-DBI off
2152 19:55:10.667004 PER_BANK_REFRESH: Hybrid Mode
2153 19:55:10.667086 TX_TRACKING: ON
2154 19:55:10.673221 [GetDramInforAfterCalByMRR] Vendor 6.
2155 19:55:10.676592 [GetDramInforAfterCalByMRR] Revision 606.
2156 19:55:10.679932 [GetDramInforAfterCalByMRR] Revision 2 0.
2157 19:55:10.680014 MR0 0x3b3b
2158 19:55:10.680079 MR8 0x5151
2159 19:55:10.683146 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2160 19:55:10.686329
2161 19:55:10.686410 MR0 0x3b3b
2162 19:55:10.686474 MR8 0x5151
2163 19:55:10.690236 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 19:55:10.690318
2165 19:55:10.699891 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2166 19:55:10.702908 [FAST_K] Save calibration result to emmc
2167 19:55:10.706398 [FAST_K] Save calibration result to emmc
2168 19:55:10.710026 dram_init: config_dvfs: 1
2169 19:55:10.713283 dramc_set_vcore_voltage set vcore to 662500
2170 19:55:10.716252 Read voltage for 1200, 2
2171 19:55:10.716334 Vio18 = 0
2172 19:55:10.716398 Vcore = 662500
2173 19:55:10.719731 Vdram = 0
2174 19:55:10.719813 Vddq = 0
2175 19:55:10.719878 Vmddr = 0
2176 19:55:10.726416 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2177 19:55:10.729649 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2178 19:55:10.733169 MEM_TYPE=3, freq_sel=15
2179 19:55:10.736380 sv_algorithm_assistance_LP4_1600
2180 19:55:10.739619 ============ PULL DRAM RESETB DOWN ============
2181 19:55:10.742930 ========== PULL DRAM RESETB DOWN end =========
2182 19:55:10.749760 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2183 19:55:10.752889 ===================================
2184 19:55:10.756123 LPDDR4 DRAM CONFIGURATION
2185 19:55:10.759578 ===================================
2186 19:55:10.759690 EX_ROW_EN[0] = 0x0
2187 19:55:10.763122 EX_ROW_EN[1] = 0x0
2188 19:55:10.763203 LP4Y_EN = 0x0
2189 19:55:10.765915 WORK_FSP = 0x0
2190 19:55:10.765997 WL = 0x4
2191 19:55:10.769592 RL = 0x4
2192 19:55:10.769674 BL = 0x2
2193 19:55:10.773535 RPST = 0x0
2194 19:55:10.773617 RD_PRE = 0x0
2195 19:55:10.776155 WR_PRE = 0x1
2196 19:55:10.776237 WR_PST = 0x0
2197 19:55:10.779180 DBI_WR = 0x0
2198 19:55:10.779286 DBI_RD = 0x0
2199 19:55:10.782867 OTF = 0x1
2200 19:55:10.785786 ===================================
2201 19:55:10.789564 ===================================
2202 19:55:10.789650 ANA top config
2203 19:55:10.792459 ===================================
2204 19:55:10.795995 DLL_ASYNC_EN = 0
2205 19:55:10.799031 ALL_SLAVE_EN = 0
2206 19:55:10.802318 NEW_RANK_MODE = 1
2207 19:55:10.805961 DLL_IDLE_MODE = 1
2208 19:55:10.806042 LP45_APHY_COMB_EN = 1
2209 19:55:10.809655 TX_ODT_DIS = 1
2210 19:55:10.812571 NEW_8X_MODE = 1
2211 19:55:10.816382 ===================================
2212 19:55:10.818789 ===================================
2213 19:55:10.822062 data_rate = 2400
2214 19:55:10.826241 CKR = 1
2215 19:55:10.826323 DQ_P2S_RATIO = 8
2216 19:55:10.829431 ===================================
2217 19:55:10.832593 CA_P2S_RATIO = 8
2218 19:55:10.835612 DQ_CA_OPEN = 0
2219 19:55:10.839019 DQ_SEMI_OPEN = 0
2220 19:55:10.842852 CA_SEMI_OPEN = 0
2221 19:55:10.846034 CA_FULL_RATE = 0
2222 19:55:10.846116 DQ_CKDIV4_EN = 0
2223 19:55:10.848784 CA_CKDIV4_EN = 0
2224 19:55:10.852142 CA_PREDIV_EN = 0
2225 19:55:10.855668 PH8_DLY = 17
2226 19:55:10.858977 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2227 19:55:10.862121 DQ_AAMCK_DIV = 4
2228 19:55:10.862202 CA_AAMCK_DIV = 4
2229 19:55:10.865493 CA_ADMCK_DIV = 4
2230 19:55:10.868964 DQ_TRACK_CA_EN = 0
2231 19:55:10.872231 CA_PICK = 1200
2232 19:55:10.875306 CA_MCKIO = 1200
2233 19:55:10.879104 MCKIO_SEMI = 0
2234 19:55:10.882046 PLL_FREQ = 2366
2235 19:55:10.882127 DQ_UI_PI_RATIO = 32
2236 19:55:10.885288 CA_UI_PI_RATIO = 0
2237 19:55:10.888491 ===================================
2238 19:55:10.892213 ===================================
2239 19:55:10.895282 memory_type:LPDDR4
2240 19:55:10.898402 GP_NUM : 10
2241 19:55:10.898485 SRAM_EN : 1
2242 19:55:10.902020 MD32_EN : 0
2243 19:55:10.905380 ===================================
2244 19:55:10.908858 [ANA_INIT] >>>>>>>>>>>>>>
2245 19:55:10.908941 <<<<<< [CONFIGURE PHASE]: ANA_TX
2246 19:55:10.911598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2247 19:55:10.915210 ===================================
2248 19:55:10.918450 data_rate = 2400,PCW = 0X5b00
2249 19:55:10.922122 ===================================
2250 19:55:10.924827 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2251 19:55:10.931677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 19:55:10.938650 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2253 19:55:10.941721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2254 19:55:10.944915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2255 19:55:10.948333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2256 19:55:10.951596 [ANA_INIT] flow start
2257 19:55:10.951680 [ANA_INIT] PLL >>>>>>>>
2258 19:55:10.954905 [ANA_INIT] PLL <<<<<<<<
2259 19:55:10.958075 [ANA_INIT] MIDPI >>>>>>>>
2260 19:55:10.961960 [ANA_INIT] MIDPI <<<<<<<<
2261 19:55:10.962043 [ANA_INIT] DLL >>>>>>>>
2262 19:55:10.965224 [ANA_INIT] DLL <<<<<<<<
2263 19:55:10.965305 [ANA_INIT] flow end
2264 19:55:10.971365 ============ LP4 DIFF to SE enter ============
2265 19:55:10.975340 ============ LP4 DIFF to SE exit ============
2266 19:55:10.978592 [ANA_INIT] <<<<<<<<<<<<<
2267 19:55:10.981102 [Flow] Enable top DCM control >>>>>
2268 19:55:10.984593 [Flow] Enable top DCM control <<<<<
2269 19:55:10.987922 Enable DLL master slave shuffle
2270 19:55:10.991261 ==============================================================
2271 19:55:10.994517 Gating Mode config
2272 19:55:10.997801 ==============================================================
2273 19:55:11.001790 Config description:
2274 19:55:11.011636 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2275 19:55:11.017536 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2276 19:55:11.021108 SELPH_MODE 0: By rank 1: By Phase
2277 19:55:11.027538 ==============================================================
2278 19:55:11.030871 GAT_TRACK_EN = 1
2279 19:55:11.034147 RX_GATING_MODE = 2
2280 19:55:11.037607 RX_GATING_TRACK_MODE = 2
2281 19:55:11.040737 SELPH_MODE = 1
2282 19:55:11.045097 PICG_EARLY_EN = 1
2283 19:55:11.045210 VALID_LAT_VALUE = 1
2284 19:55:11.051573 ==============================================================
2285 19:55:11.054140 Enter into Gating configuration >>>>
2286 19:55:11.057637 Exit from Gating configuration <<<<
2287 19:55:11.061326 Enter into DVFS_PRE_config >>>>>
2288 19:55:11.070851 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2289 19:55:11.074646 Exit from DVFS_PRE_config <<<<<
2290 19:55:11.077783 Enter into PICG configuration >>>>
2291 19:55:11.080858 Exit from PICG configuration <<<<
2292 19:55:11.084250 [RX_INPUT] configuration >>>>>
2293 19:55:11.087299 [RX_INPUT] configuration <<<<<
2294 19:55:11.090892 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2295 19:55:11.097364 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2296 19:55:11.103886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 19:55:11.110556 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 19:55:11.117799 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2299 19:55:11.123702 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2300 19:55:11.127008 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2301 19:55:11.130257 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2302 19:55:11.134438 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2303 19:55:11.140324 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2304 19:55:11.144093 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2305 19:55:11.147121 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2306 19:55:11.150170 ===================================
2307 19:55:11.153659 LPDDR4 DRAM CONFIGURATION
2308 19:55:11.156813 ===================================
2309 19:55:11.156900 EX_ROW_EN[0] = 0x0
2310 19:55:11.160288 EX_ROW_EN[1] = 0x0
2311 19:55:11.163346 LP4Y_EN = 0x0
2312 19:55:11.163428 WORK_FSP = 0x0
2313 19:55:11.166831 WL = 0x4
2314 19:55:11.166919 RL = 0x4
2315 19:55:11.170149 BL = 0x2
2316 19:55:11.170236 RPST = 0x0
2317 19:55:11.173697 RD_PRE = 0x0
2318 19:55:11.173779 WR_PRE = 0x1
2319 19:55:11.176839 WR_PST = 0x0
2320 19:55:11.176922 DBI_WR = 0x0
2321 19:55:11.180117 DBI_RD = 0x0
2322 19:55:11.180202 OTF = 0x1
2323 19:55:11.184235 ===================================
2324 19:55:11.186791 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2325 19:55:11.193682 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2326 19:55:11.196449 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2327 19:55:11.199785 ===================================
2328 19:55:11.203584 LPDDR4 DRAM CONFIGURATION
2329 19:55:11.206578 ===================================
2330 19:55:11.206660 EX_ROW_EN[0] = 0x10
2331 19:55:11.209742 EX_ROW_EN[1] = 0x0
2332 19:55:11.209825 LP4Y_EN = 0x0
2333 19:55:11.213217 WORK_FSP = 0x0
2334 19:55:11.216551 WL = 0x4
2335 19:55:11.216631 RL = 0x4
2336 19:55:11.219677 BL = 0x2
2337 19:55:11.219779 RPST = 0x0
2338 19:55:11.223001 RD_PRE = 0x0
2339 19:55:11.223079 WR_PRE = 0x1
2340 19:55:11.226513 WR_PST = 0x0
2341 19:55:11.226594 DBI_WR = 0x0
2342 19:55:11.229422 DBI_RD = 0x0
2343 19:55:11.229501 OTF = 0x1
2344 19:55:11.233085 ===================================
2345 19:55:11.240155 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2346 19:55:11.240245 ==
2347 19:55:11.242990 Dram Type= 6, Freq= 0, CH_0, rank 0
2348 19:55:11.246098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2349 19:55:11.246180 ==
2350 19:55:11.249484 [Duty_Offset_Calibration]
2351 19:55:11.252913 B0:1 B1:-1 CA:0
2352 19:55:11.253046
2353 19:55:11.256069 [DutyScan_Calibration_Flow] k_type=0
2354 19:55:11.264455
2355 19:55:11.264652 ==CLK 0==
2356 19:55:11.267628 Final CLK duty delay cell = 0
2357 19:55:11.270964 [0] MAX Duty = 5125%(X100), DQS PI = 24
2358 19:55:11.274656 [0] MIN Duty = 4907%(X100), DQS PI = 6
2359 19:55:11.274760 [0] AVG Duty = 5016%(X100)
2360 19:55:11.278112
2361 19:55:11.281054 CH0 CLK Duty spec in!! Max-Min= 218%
2362 19:55:11.284519 [DutyScan_Calibration_Flow] ====Done====
2363 19:55:11.284650
2364 19:55:11.287915 [DutyScan_Calibration_Flow] k_type=1
2365 19:55:11.302427
2366 19:55:11.302611 ==DQS 0 ==
2367 19:55:11.305678 Final DQS duty delay cell = -4
2368 19:55:11.308809 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2369 19:55:11.312059 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2370 19:55:11.315497 [-4] AVG Duty = 4968%(X100)
2371 19:55:11.315587
2372 19:55:11.315651 ==DQS 1 ==
2373 19:55:11.318662 Final DQS duty delay cell = -4
2374 19:55:11.321895 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2375 19:55:11.325383 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2376 19:55:11.328370 [-4] AVG Duty = 4938%(X100)
2377 19:55:11.328471
2378 19:55:11.331668 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2379 19:55:11.331793
2380 19:55:11.335509 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2381 19:55:11.338883 [DutyScan_Calibration_Flow] ====Done====
2382 19:55:11.338971
2383 19:55:11.341755 [DutyScan_Calibration_Flow] k_type=3
2384 19:55:11.360293
2385 19:55:11.360425 ==DQM 0 ==
2386 19:55:11.363476 Final DQM duty delay cell = 0
2387 19:55:11.366663 [0] MAX Duty = 5062%(X100), DQS PI = 24
2388 19:55:11.370006 [0] MIN Duty = 4875%(X100), DQS PI = 8
2389 19:55:11.370088 [0] AVG Duty = 4968%(X100)
2390 19:55:11.373635
2391 19:55:11.373717 ==DQM 1 ==
2392 19:55:11.376823 Final DQM duty delay cell = 4
2393 19:55:11.380133 [4] MAX Duty = 5187%(X100), DQS PI = 14
2394 19:55:11.383770 [4] MIN Duty = 4969%(X100), DQS PI = 26
2395 19:55:11.387009 [4] AVG Duty = 5078%(X100)
2396 19:55:11.387096
2397 19:55:11.390158 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2398 19:55:11.390241
2399 19:55:11.393881 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2400 19:55:11.396555 [DutyScan_Calibration_Flow] ====Done====
2401 19:55:11.396637
2402 19:55:11.400178 [DutyScan_Calibration_Flow] k_type=2
2403 19:55:11.416127
2404 19:55:11.416246 ==DQ 0 ==
2405 19:55:11.419495 Final DQ duty delay cell = -4
2406 19:55:11.422707 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2407 19:55:11.425632 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2408 19:55:11.429461 [-4] AVG Duty = 4969%(X100)
2409 19:55:11.429543
2410 19:55:11.429608 ==DQ 1 ==
2411 19:55:11.433055 Final DQ duty delay cell = 0
2412 19:55:11.436336 [0] MAX Duty = 5093%(X100), DQS PI = 2
2413 19:55:11.439483 [0] MIN Duty = 4969%(X100), DQS PI = 42
2414 19:55:11.442368 [0] AVG Duty = 5031%(X100)
2415 19:55:11.442451
2416 19:55:11.445601 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2417 19:55:11.445707
2418 19:55:11.449180 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2419 19:55:11.452353 [DutyScan_Calibration_Flow] ====Done====
2420 19:55:11.452437 ==
2421 19:55:11.455620 Dram Type= 6, Freq= 0, CH_1, rank 0
2422 19:55:11.459135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2423 19:55:11.459219 ==
2424 19:55:11.462261 [Duty_Offset_Calibration]
2425 19:55:11.462343 B0:-1 B1:1 CA:2
2426 19:55:11.462408
2427 19:55:11.465865 [DutyScan_Calibration_Flow] k_type=0
2428 19:55:11.476372
2429 19:55:11.476472 ==CLK 0==
2430 19:55:11.480354 Final CLK duty delay cell = 0
2431 19:55:11.482689 [0] MAX Duty = 5156%(X100), DQS PI = 22
2432 19:55:11.486358 [0] MIN Duty = 4969%(X100), DQS PI = 62
2433 19:55:11.489291 [0] AVG Duty = 5062%(X100)
2434 19:55:11.489374
2435 19:55:11.492624 CH1 CLK Duty spec in!! Max-Min= 187%
2436 19:55:11.495940 [DutyScan_Calibration_Flow] ====Done====
2437 19:55:11.496024
2438 19:55:11.499394 [DutyScan_Calibration_Flow] k_type=1
2439 19:55:11.515936
2440 19:55:11.516058 ==DQS 0 ==
2441 19:55:11.518674 Final DQS duty delay cell = 0
2442 19:55:11.522212 [0] MAX Duty = 5156%(X100), DQS PI = 48
2443 19:55:11.525380 [0] MIN Duty = 4938%(X100), DQS PI = 6
2444 19:55:11.529076 [0] AVG Duty = 5047%(X100)
2445 19:55:11.529160
2446 19:55:11.529226 ==DQS 1 ==
2447 19:55:11.532443 Final DQS duty delay cell = 0
2448 19:55:11.535265 [0] MAX Duty = 5094%(X100), DQS PI = 12
2449 19:55:11.538710 [0] MIN Duty = 4969%(X100), DQS PI = 58
2450 19:55:11.541956 [0] AVG Duty = 5031%(X100)
2451 19:55:11.542039
2452 19:55:11.545239 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2453 19:55:11.545322
2454 19:55:11.548752 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2455 19:55:11.552278 [DutyScan_Calibration_Flow] ====Done====
2456 19:55:11.552365
2457 19:55:11.555172 [DutyScan_Calibration_Flow] k_type=3
2458 19:55:11.571088
2459 19:55:11.571199 ==DQM 0 ==
2460 19:55:11.575033 Final DQM duty delay cell = -4
2461 19:55:11.578220 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2462 19:55:11.581380 [-4] MIN Duty = 4876%(X100), DQS PI = 8
2463 19:55:11.584598 [-4] AVG Duty = 4969%(X100)
2464 19:55:11.584681
2465 19:55:11.584746 ==DQM 1 ==
2466 19:55:11.587926 Final DQM duty delay cell = 0
2467 19:55:11.591270 [0] MAX Duty = 5156%(X100), DQS PI = 4
2468 19:55:11.594462 [0] MIN Duty = 5000%(X100), DQS PI = 28
2469 19:55:11.597772 [0] AVG Duty = 5078%(X100)
2470 19:55:11.597854
2471 19:55:11.601296 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2472 19:55:11.601378
2473 19:55:11.604551 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2474 19:55:11.607888 [DutyScan_Calibration_Flow] ====Done====
2475 19:55:11.607970
2476 19:55:11.610991 [DutyScan_Calibration_Flow] k_type=2
2477 19:55:11.627958
2478 19:55:11.628069 ==DQ 0 ==
2479 19:55:11.631244 Final DQ duty delay cell = 0
2480 19:55:11.634271 [0] MAX Duty = 5156%(X100), DQS PI = 28
2481 19:55:11.637986 [0] MIN Duty = 4907%(X100), DQS PI = 6
2482 19:55:11.638069 [0] AVG Duty = 5031%(X100)
2483 19:55:11.641208
2484 19:55:11.641288 ==DQ 1 ==
2485 19:55:11.644805 Final DQ duty delay cell = 0
2486 19:55:11.648518 [0] MAX Duty = 5124%(X100), DQS PI = 10
2487 19:55:11.652117 [0] MIN Duty = 4969%(X100), DQS PI = 0
2488 19:55:11.652200 [0] AVG Duty = 5046%(X100)
2489 19:55:11.652281
2490 19:55:11.654375 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2491 19:55:11.654457
2492 19:55:11.661234 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2493 19:55:11.664457 [DutyScan_Calibration_Flow] ====Done====
2494 19:55:11.667871 nWR fixed to 30
2495 19:55:11.667954 [ModeRegInit_LP4] CH0 RK0
2496 19:55:11.670884 [ModeRegInit_LP4] CH0 RK1
2497 19:55:11.674374 [ModeRegInit_LP4] CH1 RK0
2498 19:55:11.674456 [ModeRegInit_LP4] CH1 RK1
2499 19:55:11.677710 match AC timing 7
2500 19:55:11.681348 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2501 19:55:11.687309 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2502 19:55:11.690945 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2503 19:55:11.697219 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2504 19:55:11.700709 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2505 19:55:11.700793 ==
2506 19:55:11.704031 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 19:55:11.707620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 19:55:11.707703 ==
2509 19:55:11.714098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2510 19:55:11.720465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2511 19:55:11.727551 [CA 0] Center 39 (9~70) winsize 62
2512 19:55:11.730968 [CA 1] Center 39 (9~69) winsize 61
2513 19:55:11.734150 [CA 2] Center 35 (5~66) winsize 62
2514 19:55:11.737430 [CA 3] Center 35 (5~66) winsize 62
2515 19:55:11.741278 [CA 4] Center 33 (4~63) winsize 60
2516 19:55:11.743940 [CA 5] Center 33 (3~63) winsize 61
2517 19:55:11.744023
2518 19:55:11.747634 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2519 19:55:11.747718
2520 19:55:11.750965 [CATrainingPosCal] consider 1 rank data
2521 19:55:11.754416 u2DelayCellTimex100 = 270/100 ps
2522 19:55:11.757435 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2523 19:55:11.764055 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2524 19:55:11.767318 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2525 19:55:11.770854 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2526 19:55:11.774138 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2527 19:55:11.777293 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2528 19:55:11.777378
2529 19:55:11.780495 CA PerBit enable=1, Macro0, CA PI delay=33
2530 19:55:11.780579
2531 19:55:11.784358 [CBTSetCACLKResult] CA Dly = 33
2532 19:55:11.784443 CS Dly: 8 (0~39)
2533 19:55:11.787345 ==
2534 19:55:11.790537 Dram Type= 6, Freq= 0, CH_0, rank 1
2535 19:55:11.794135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 19:55:11.794220 ==
2537 19:55:11.797460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2538 19:55:11.803706 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2539 19:55:11.813580 [CA 0] Center 39 (8~70) winsize 63
2540 19:55:11.817203 [CA 1] Center 39 (9~70) winsize 62
2541 19:55:11.820074 [CA 2] Center 35 (5~66) winsize 62
2542 19:55:11.823471 [CA 3] Center 34 (4~65) winsize 62
2543 19:55:11.826893 [CA 4] Center 33 (3~64) winsize 62
2544 19:55:11.830026 [CA 5] Center 33 (3~63) winsize 61
2545 19:55:11.830112
2546 19:55:11.833357 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2547 19:55:11.833443
2548 19:55:11.836516 [CATrainingPosCal] consider 2 rank data
2549 19:55:11.839869 u2DelayCellTimex100 = 270/100 ps
2550 19:55:11.843362 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2551 19:55:11.850067 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2552 19:55:11.853166 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2553 19:55:11.856465 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2554 19:55:11.859734 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2555 19:55:11.862989 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2556 19:55:11.863076
2557 19:55:11.866507 CA PerBit enable=1, Macro0, CA PI delay=33
2558 19:55:11.866591
2559 19:55:11.869859 [CBTSetCACLKResult] CA Dly = 33
2560 19:55:11.869949 CS Dly: 9 (0~41)
2561 19:55:11.870034
2562 19:55:11.873290 ----->DramcWriteLeveling(PI) begin...
2563 19:55:11.876412 ==
2564 19:55:11.879643 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 19:55:11.883868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 19:55:11.883954 ==
2567 19:55:11.886415 Write leveling (Byte 0): 32 => 32
2568 19:55:11.889730 Write leveling (Byte 1): 29 => 29
2569 19:55:11.893195 DramcWriteLeveling(PI) end<-----
2570 19:55:11.893287
2571 19:55:11.893373 ==
2572 19:55:11.896519 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 19:55:11.899919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 19:55:11.900019 ==
2575 19:55:11.902958 [Gating] SW mode calibration
2576 19:55:11.909341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2577 19:55:11.916423 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2578 19:55:11.919981 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2579 19:55:11.922700 0 15 4 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
2580 19:55:11.929132 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 19:55:11.933101 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 19:55:11.935943 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 19:55:11.942621 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 19:55:11.946059 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2585 19:55:11.949352 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
2586 19:55:11.955638 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2587 19:55:11.959347 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 19:55:11.962391 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 19:55:11.969350 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 19:55:11.972391 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 19:55:11.975759 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 19:55:11.982517 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 19:55:11.985544 1 0 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
2594 19:55:11.989109 1 1 0 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
2595 19:55:11.992451 1 1 4 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
2596 19:55:11.999063 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 19:55:12.002454 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 19:55:12.005730 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 19:55:12.012270 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 19:55:12.015716 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 19:55:12.018950 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2602 19:55:12.025399 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2603 19:55:12.028852 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 19:55:12.032147 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 19:55:12.039316 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 19:55:12.042263 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 19:55:12.045680 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 19:55:12.052636 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 19:55:12.055730 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 19:55:12.058726 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 19:55:12.065614 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 19:55:12.068537 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 19:55:12.071842 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 19:55:12.078396 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 19:55:12.082042 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 19:55:12.085320 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 19:55:12.091671 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2618 19:55:12.095041 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2619 19:55:12.098356 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 19:55:12.101830 Total UI for P1: 0, mck2ui 16
2621 19:55:12.105163 best dqsien dly found for B0: ( 1, 3, 30)
2622 19:55:12.108647 Total UI for P1: 0, mck2ui 16
2623 19:55:12.112552 best dqsien dly found for B1: ( 1, 4, 0)
2624 19:55:12.116019 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2625 19:55:12.118111 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2626 19:55:12.118195
2627 19:55:12.124754 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2628 19:55:12.128449 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2629 19:55:12.128532 [Gating] SW calibration Done
2630 19:55:12.132020 ==
2631 19:55:12.134875 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 19:55:12.138239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 19:55:12.138322 ==
2634 19:55:12.138387 RX Vref Scan: 0
2635 19:55:12.138449
2636 19:55:12.141545 RX Vref 0 -> 0, step: 1
2637 19:55:12.141628
2638 19:55:12.144665 RX Delay -40 -> 252, step: 8
2639 19:55:12.148099 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2640 19:55:12.151263 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2641 19:55:12.155731 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2642 19:55:12.161666 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2643 19:55:12.164641 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2644 19:55:12.167849 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2645 19:55:12.171351 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2646 19:55:12.174377 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2647 19:55:12.181736 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2648 19:55:12.184883 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2649 19:55:12.187843 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2650 19:55:12.190958 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2651 19:55:12.195083 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2652 19:55:12.201569 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2653 19:55:12.205070 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2654 19:55:12.208353 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2655 19:55:12.208436 ==
2656 19:55:12.211063 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 19:55:12.214067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 19:55:12.217335 ==
2659 19:55:12.217417 DQS Delay:
2660 19:55:12.217482 DQS0 = 0, DQS1 = 0
2661 19:55:12.220898 DQM Delay:
2662 19:55:12.220980 DQM0 = 119, DQM1 = 106
2663 19:55:12.224710 DQ Delay:
2664 19:55:12.227703 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2665 19:55:12.230860 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2666 19:55:12.234243 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2667 19:55:12.237312 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2668 19:55:12.237394
2669 19:55:12.237458
2670 19:55:12.237518 ==
2671 19:55:12.240925 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 19:55:12.244168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 19:55:12.244251 ==
2674 19:55:12.244316
2675 19:55:12.244376
2676 19:55:12.247523 TX Vref Scan disable
2677 19:55:12.250761 == TX Byte 0 ==
2678 19:55:12.254018 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2679 19:55:12.257423 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2680 19:55:12.260723 == TX Byte 1 ==
2681 19:55:12.263969 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2682 19:55:12.267983 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2683 19:55:12.268067 ==
2684 19:55:12.270692 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 19:55:12.277303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 19:55:12.277388 ==
2687 19:55:12.287595 TX Vref=22, minBit 5, minWin=25, winSum=416
2688 19:55:12.291380 TX Vref=24, minBit 0, minWin=26, winSum=427
2689 19:55:12.294488 TX Vref=26, minBit 1, minWin=26, winSum=426
2690 19:55:12.297818 TX Vref=28, minBit 4, minWin=26, winSum=429
2691 19:55:12.300842 TX Vref=30, minBit 1, minWin=26, winSum=429
2692 19:55:12.307651 TX Vref=32, minBit 4, minWin=26, winSum=427
2693 19:55:12.311145 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 28
2694 19:55:12.311228
2695 19:55:12.314048 Final TX Range 1 Vref 28
2696 19:55:12.314131
2697 19:55:12.314195 ==
2698 19:55:12.317367 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 19:55:12.320463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 19:55:12.324190 ==
2701 19:55:12.324272
2702 19:55:12.324336
2703 19:55:12.324395 TX Vref Scan disable
2704 19:55:12.327484 == TX Byte 0 ==
2705 19:55:12.330892 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2706 19:55:12.337803 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2707 19:55:12.337888 == TX Byte 1 ==
2708 19:55:12.340919 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2709 19:55:12.347256 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2710 19:55:12.347363
2711 19:55:12.347456 [DATLAT]
2712 19:55:12.347576 Freq=1200, CH0 RK0
2713 19:55:12.347676
2714 19:55:12.350795 DATLAT Default: 0xd
2715 19:55:12.350877 0, 0xFFFF, sum = 0
2716 19:55:12.353940 1, 0xFFFF, sum = 0
2717 19:55:12.357529 2, 0xFFFF, sum = 0
2718 19:55:12.357612 3, 0xFFFF, sum = 0
2719 19:55:12.360968 4, 0xFFFF, sum = 0
2720 19:55:12.361052 5, 0xFFFF, sum = 0
2721 19:55:12.363986 6, 0xFFFF, sum = 0
2722 19:55:12.364069 7, 0xFFFF, sum = 0
2723 19:55:12.367497 8, 0xFFFF, sum = 0
2724 19:55:12.367581 9, 0xFFFF, sum = 0
2725 19:55:12.370562 10, 0xFFFF, sum = 0
2726 19:55:12.370645 11, 0xFFFF, sum = 0
2727 19:55:12.373655 12, 0x0, sum = 1
2728 19:55:12.373736 13, 0x0, sum = 2
2729 19:55:12.377166 14, 0x0, sum = 3
2730 19:55:12.377251 15, 0x0, sum = 4
2731 19:55:12.380779 best_step = 13
2732 19:55:12.380862
2733 19:55:12.380946 ==
2734 19:55:12.383935 Dram Type= 6, Freq= 0, CH_0, rank 0
2735 19:55:12.387252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2736 19:55:12.387336 ==
2737 19:55:12.387421 RX Vref Scan: 1
2738 19:55:12.390884
2739 19:55:12.390968 Set Vref Range= 32 -> 127
2740 19:55:12.391053
2741 19:55:12.393730 RX Vref 32 -> 127, step: 1
2742 19:55:12.393813
2743 19:55:12.397300 RX Delay -21 -> 252, step: 4
2744 19:55:12.397381
2745 19:55:12.400557 Set Vref, RX VrefLevel [Byte0]: 32
2746 19:55:12.403422 [Byte1]: 32
2747 19:55:12.403538
2748 19:55:12.406956 Set Vref, RX VrefLevel [Byte0]: 33
2749 19:55:12.409970 [Byte1]: 33
2750 19:55:12.414135
2751 19:55:12.414214 Set Vref, RX VrefLevel [Byte0]: 34
2752 19:55:12.417590 [Byte1]: 34
2753 19:55:12.422054
2754 19:55:12.422149 Set Vref, RX VrefLevel [Byte0]: 35
2755 19:55:12.425362 [Byte1]: 35
2756 19:55:12.429834
2757 19:55:12.429915 Set Vref, RX VrefLevel [Byte0]: 36
2758 19:55:12.433358 [Byte1]: 36
2759 19:55:12.437642
2760 19:55:12.437722 Set Vref, RX VrefLevel [Byte0]: 37
2761 19:55:12.441309 [Byte1]: 37
2762 19:55:12.445701
2763 19:55:12.445781 Set Vref, RX VrefLevel [Byte0]: 38
2764 19:55:12.449296 [Byte1]: 38
2765 19:55:12.453642
2766 19:55:12.453767 Set Vref, RX VrefLevel [Byte0]: 39
2767 19:55:12.456894 [Byte1]: 39
2768 19:55:12.461502
2769 19:55:12.461585 Set Vref, RX VrefLevel [Byte0]: 40
2770 19:55:12.465158 [Byte1]: 40
2771 19:55:12.469133
2772 19:55:12.472787 Set Vref, RX VrefLevel [Byte0]: 41
2773 19:55:12.476049 [Byte1]: 41
2774 19:55:12.476131
2775 19:55:12.479716 Set Vref, RX VrefLevel [Byte0]: 42
2776 19:55:12.482530 [Byte1]: 42
2777 19:55:12.482636
2778 19:55:12.485907 Set Vref, RX VrefLevel [Byte0]: 43
2779 19:55:12.489030 [Byte1]: 43
2780 19:55:12.493787
2781 19:55:12.493868 Set Vref, RX VrefLevel [Byte0]: 44
2782 19:55:12.496497 [Byte1]: 44
2783 19:55:12.501424
2784 19:55:12.501505 Set Vref, RX VrefLevel [Byte0]: 45
2785 19:55:12.504660 [Byte1]: 45
2786 19:55:12.509100
2787 19:55:12.509181 Set Vref, RX VrefLevel [Byte0]: 46
2788 19:55:12.512497 [Byte1]: 46
2789 19:55:12.516887
2790 19:55:12.516971 Set Vref, RX VrefLevel [Byte0]: 47
2791 19:55:12.520374 [Byte1]: 47
2792 19:55:12.525174
2793 19:55:12.525258 Set Vref, RX VrefLevel [Byte0]: 48
2794 19:55:12.528102 [Byte1]: 48
2795 19:55:12.533012
2796 19:55:12.533096 Set Vref, RX VrefLevel [Byte0]: 49
2797 19:55:12.536419 [Byte1]: 49
2798 19:55:12.540863
2799 19:55:12.540947 Set Vref, RX VrefLevel [Byte0]: 50
2800 19:55:12.544285 [Byte1]: 50
2801 19:55:12.549298
2802 19:55:12.549383 Set Vref, RX VrefLevel [Byte0]: 51
2803 19:55:12.552244 [Byte1]: 51
2804 19:55:12.556638
2805 19:55:12.556723 Set Vref, RX VrefLevel [Byte0]: 52
2806 19:55:12.560216 [Byte1]: 52
2807 19:55:12.564672
2808 19:55:12.564759 Set Vref, RX VrefLevel [Byte0]: 53
2809 19:55:12.567843 [Byte1]: 53
2810 19:55:12.572592
2811 19:55:12.572676 Set Vref, RX VrefLevel [Byte0]: 54
2812 19:55:12.576014 [Byte1]: 54
2813 19:55:12.580645
2814 19:55:12.580729 Set Vref, RX VrefLevel [Byte0]: 55
2815 19:55:12.584294 [Byte1]: 55
2816 19:55:12.588637
2817 19:55:12.588721 Set Vref, RX VrefLevel [Byte0]: 56
2818 19:55:12.592271 [Byte1]: 56
2819 19:55:12.596848
2820 19:55:12.596952 Set Vref, RX VrefLevel [Byte0]: 57
2821 19:55:12.600074 [Byte1]: 57
2822 19:55:12.604293
2823 19:55:12.604374 Set Vref, RX VrefLevel [Byte0]: 58
2824 19:55:12.607882 [Byte1]: 58
2825 19:55:12.612351
2826 19:55:12.612433 Set Vref, RX VrefLevel [Byte0]: 59
2827 19:55:12.616093 [Byte1]: 59
2828 19:55:12.620616
2829 19:55:12.620697 Set Vref, RX VrefLevel [Byte0]: 60
2830 19:55:12.623286 [Byte1]: 60
2831 19:55:12.628342
2832 19:55:12.628423 Set Vref, RX VrefLevel [Byte0]: 61
2833 19:55:12.631466 [Byte1]: 61
2834 19:55:12.635831
2835 19:55:12.635913 Set Vref, RX VrefLevel [Byte0]: 62
2836 19:55:12.639201 [Byte1]: 62
2837 19:55:12.643835
2838 19:55:12.643916 Set Vref, RX VrefLevel [Byte0]: 63
2839 19:55:12.647221 [Byte1]: 63
2840 19:55:12.652574
2841 19:55:12.652657 Set Vref, RX VrefLevel [Byte0]: 64
2842 19:55:12.655304 [Byte1]: 64
2843 19:55:12.660119
2844 19:55:12.660201 Set Vref, RX VrefLevel [Byte0]: 65
2845 19:55:12.663072 [Byte1]: 65
2846 19:55:12.667914
2847 19:55:12.670885 Set Vref, RX VrefLevel [Byte0]: 66
2848 19:55:12.670966 [Byte1]: 66
2849 19:55:12.675656
2850 19:55:12.675780 Set Vref, RX VrefLevel [Byte0]: 67
2851 19:55:12.678939 [Byte1]: 67
2852 19:55:12.683634
2853 19:55:12.683715 Set Vref, RX VrefLevel [Byte0]: 68
2854 19:55:12.686796 [Byte1]: 68
2855 19:55:12.691488
2856 19:55:12.691569 Set Vref, RX VrefLevel [Byte0]: 69
2857 19:55:12.694936 [Byte1]: 69
2858 19:55:12.700017
2859 19:55:12.700098 Set Vref, RX VrefLevel [Byte0]: 70
2860 19:55:12.702790 [Byte1]: 70
2861 19:55:12.707440
2862 19:55:12.707521 Set Vref, RX VrefLevel [Byte0]: 71
2863 19:55:12.710837 [Byte1]: 71
2864 19:55:12.715075
2865 19:55:12.715157 Set Vref, RX VrefLevel [Byte0]: 72
2866 19:55:12.718395 [Byte1]: 72
2867 19:55:12.723717
2868 19:55:12.723804 Set Vref, RX VrefLevel [Byte0]: 73
2869 19:55:12.726629 [Byte1]: 73
2870 19:55:12.730940
2871 19:55:12.731021 Set Vref, RX VrefLevel [Byte0]: 74
2872 19:55:12.734401 [Byte1]: 74
2873 19:55:12.739018
2874 19:55:12.739099 Set Vref, RX VrefLevel [Byte0]: 75
2875 19:55:12.742244 [Byte1]: 75
2876 19:55:12.747329
2877 19:55:12.747435 Set Vref, RX VrefLevel [Byte0]: 76
2878 19:55:12.750350 [Byte1]: 76
2879 19:55:12.755363
2880 19:55:12.755445 Set Vref, RX VrefLevel [Byte0]: 77
2881 19:55:12.758325 [Byte1]: 77
2882 19:55:12.763071
2883 19:55:12.763152 Set Vref, RX VrefLevel [Byte0]: 78
2884 19:55:12.765895 [Byte1]: 78
2885 19:55:12.771086
2886 19:55:12.771170 Final RX Vref Byte 0 = 58 to rank0
2887 19:55:12.774279 Final RX Vref Byte 1 = 48 to rank0
2888 19:55:12.777405 Final RX Vref Byte 0 = 58 to rank1
2889 19:55:12.780527 Final RX Vref Byte 1 = 48 to rank1==
2890 19:55:12.784052 Dram Type= 6, Freq= 0, CH_0, rank 0
2891 19:55:12.790739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 19:55:12.790846 ==
2893 19:55:12.790940 DQS Delay:
2894 19:55:12.793772 DQS0 = 0, DQS1 = 0
2895 19:55:12.793854 DQM Delay:
2896 19:55:12.793919 DQM0 = 118, DQM1 = 106
2897 19:55:12.797327 DQ Delay:
2898 19:55:12.800386 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =116
2899 19:55:12.803766 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =124
2900 19:55:12.807006 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
2901 19:55:12.810611 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2902 19:55:12.810693
2903 19:55:12.810757
2904 19:55:12.820273 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 402 ps
2905 19:55:12.820358 CH0 RK0: MR19=403, MR18=13FF
2906 19:55:12.827102 CH0_RK0: MR19=0x403, MR18=0x13FF, DQSOSC=402, MR23=63, INC=40, DEC=27
2907 19:55:12.827184
2908 19:55:12.830465 ----->DramcWriteLeveling(PI) begin...
2909 19:55:12.830547 ==
2910 19:55:12.833456 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 19:55:12.840091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 19:55:12.840174 ==
2913 19:55:12.843480 Write leveling (Byte 0): 32 => 32
2914 19:55:12.843561 Write leveling (Byte 1): 29 => 29
2915 19:55:12.846847 DramcWriteLeveling(PI) end<-----
2916 19:55:12.846928
2917 19:55:12.850141 ==
2918 19:55:12.850224 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 19:55:12.856718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 19:55:12.856802 ==
2921 19:55:12.860271 [Gating] SW mode calibration
2922 19:55:12.866789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2923 19:55:12.870255 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2924 19:55:12.876613 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2925 19:55:12.880135 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2926 19:55:12.883243 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 19:55:12.890444 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 19:55:12.893222 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 19:55:12.896579 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 19:55:12.903469 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 19:55:12.906435 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2932 19:55:12.910136 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2933 19:55:12.916458 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 19:55:12.919740 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 19:55:12.922989 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 19:55:12.929540 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 19:55:12.933000 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 19:55:12.936519 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 19:55:12.939834 1 0 28 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
2940 19:55:12.946634 1 1 0 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
2941 19:55:12.949552 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 19:55:12.953147 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 19:55:12.959896 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 19:55:12.963166 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 19:55:12.966609 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 19:55:12.973241 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 19:55:12.976132 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2948 19:55:12.979663 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2949 19:55:12.985839 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 19:55:12.989396 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 19:55:12.992429 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 19:55:12.999105 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 19:55:13.002610 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 19:55:13.005925 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 19:55:13.012541 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 19:55:13.016241 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 19:55:13.018989 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 19:55:13.026202 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 19:55:13.029147 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 19:55:13.032599 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 19:55:13.038816 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 19:55:13.042186 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2963 19:55:13.045437 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2964 19:55:13.051901 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2965 19:55:13.055503 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 19:55:13.058926 Total UI for P1: 0, mck2ui 16
2967 19:55:13.062057 best dqsien dly found for B0: ( 1, 3, 28)
2968 19:55:13.065260 Total UI for P1: 0, mck2ui 16
2969 19:55:13.068482 best dqsien dly found for B1: ( 1, 4, 0)
2970 19:55:13.072022 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2971 19:55:13.075338 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2972 19:55:13.075419
2973 19:55:13.078383 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2974 19:55:13.081925 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2975 19:55:13.086014 [Gating] SW calibration Done
2976 19:55:13.086096 ==
2977 19:55:13.088433 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 19:55:13.095162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 19:55:13.095244 ==
2980 19:55:13.095310 RX Vref Scan: 0
2981 19:55:13.095370
2982 19:55:13.098729 RX Vref 0 -> 0, step: 1
2983 19:55:13.098810
2984 19:55:13.102202 RX Delay -40 -> 252, step: 8
2985 19:55:13.104893 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2986 19:55:13.109080 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2987 19:55:13.111564 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2988 19:55:13.114853 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2989 19:55:13.121507 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2990 19:55:13.125002 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2991 19:55:13.128394 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2992 19:55:13.131640 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2993 19:55:13.135132 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2994 19:55:13.141576 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2995 19:55:13.144673 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2996 19:55:13.148460 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2997 19:55:13.151487 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2998 19:55:13.155265 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2999 19:55:13.162490 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3000 19:55:13.164688 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3001 19:55:13.164771 ==
3002 19:55:13.168396 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 19:55:13.171985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 19:55:13.172067 ==
3005 19:55:13.174528 DQS Delay:
3006 19:55:13.174609 DQS0 = 0, DQS1 = 0
3007 19:55:13.174674 DQM Delay:
3008 19:55:13.177866 DQM0 = 117, DQM1 = 108
3009 19:55:13.177948 DQ Delay:
3010 19:55:13.181386 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3011 19:55:13.184619 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
3012 19:55:13.187810 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3013 19:55:13.194749 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3014 19:55:13.194831
3015 19:55:13.194896
3016 19:55:13.194956 ==
3017 19:55:13.197899 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 19:55:13.201811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 19:55:13.201897 ==
3020 19:55:13.201963
3021 19:55:13.202024
3022 19:55:13.204430 TX Vref Scan disable
3023 19:55:13.204511 == TX Byte 0 ==
3024 19:55:13.211206 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3025 19:55:13.214971 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3026 19:55:13.215053 == TX Byte 1 ==
3027 19:55:13.221270 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3028 19:55:13.224614 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3029 19:55:13.224695 ==
3030 19:55:13.228229 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 19:55:13.231293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 19:55:13.231375 ==
3033 19:55:13.244168 TX Vref=22, minBit 10, minWin=25, winSum=419
3034 19:55:13.247840 TX Vref=24, minBit 13, minWin=25, winSum=420
3035 19:55:13.251051 TX Vref=26, minBit 10, minWin=25, winSum=421
3036 19:55:13.254327 TX Vref=28, minBit 13, minWin=25, winSum=426
3037 19:55:13.260549 TX Vref=30, minBit 12, minWin=25, winSum=425
3038 19:55:13.263974 TX Vref=32, minBit 12, minWin=25, winSum=425
3039 19:55:13.270778 [TxChooseVref] Worse bit 13, Min win 25, Win sum 426, Final Vref 28
3040 19:55:13.270862
3041 19:55:13.270927 Final TX Range 1 Vref 28
3042 19:55:13.270987
3043 19:55:13.271045 ==
3044 19:55:13.273645 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 19:55:13.280161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 19:55:13.280342 ==
3047 19:55:13.280464
3048 19:55:13.280526
3049 19:55:13.280585 TX Vref Scan disable
3050 19:55:13.284835 == TX Byte 0 ==
3051 19:55:13.287946 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3052 19:55:13.294391 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3053 19:55:13.294472 == TX Byte 1 ==
3054 19:55:13.298160 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3055 19:55:13.304297 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3056 19:55:13.304379
3057 19:55:13.304444 [DATLAT]
3058 19:55:13.304504 Freq=1200, CH0 RK1
3059 19:55:13.304562
3060 19:55:13.307954 DATLAT Default: 0xd
3061 19:55:13.311158 0, 0xFFFF, sum = 0
3062 19:55:13.311240 1, 0xFFFF, sum = 0
3063 19:55:13.314608 2, 0xFFFF, sum = 0
3064 19:55:13.314690 3, 0xFFFF, sum = 0
3065 19:55:13.317766 4, 0xFFFF, sum = 0
3066 19:55:13.317849 5, 0xFFFF, sum = 0
3067 19:55:13.320866 6, 0xFFFF, sum = 0
3068 19:55:13.320949 7, 0xFFFF, sum = 0
3069 19:55:13.324454 8, 0xFFFF, sum = 0
3070 19:55:13.324537 9, 0xFFFF, sum = 0
3071 19:55:13.327219 10, 0xFFFF, sum = 0
3072 19:55:13.327301 11, 0xFFFF, sum = 0
3073 19:55:13.330549 12, 0x0, sum = 1
3074 19:55:13.330631 13, 0x0, sum = 2
3075 19:55:13.334272 14, 0x0, sum = 3
3076 19:55:13.334355 15, 0x0, sum = 4
3077 19:55:13.337426 best_step = 13
3078 19:55:13.337507
3079 19:55:13.337571 ==
3080 19:55:13.340598 Dram Type= 6, Freq= 0, CH_0, rank 1
3081 19:55:13.344042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 19:55:13.344125 ==
3083 19:55:13.347580 RX Vref Scan: 0
3084 19:55:13.347686
3085 19:55:13.347826 RX Vref 0 -> 0, step: 1
3086 19:55:13.347915
3087 19:55:13.350854 RX Delay -21 -> 252, step: 4
3088 19:55:13.357296 iDelay=199, Bit 0, Center 114 (51 ~ 178) 128
3089 19:55:13.361003 iDelay=199, Bit 1, Center 120 (51 ~ 190) 140
3090 19:55:13.364194 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3091 19:55:13.367421 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3092 19:55:13.370626 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3093 19:55:13.377085 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3094 19:55:13.380384 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3095 19:55:13.383658 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3096 19:55:13.386871 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3097 19:55:13.390516 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3098 19:55:13.397689 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3099 19:55:13.400412 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3100 19:55:13.403695 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3101 19:55:13.407064 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3102 19:55:13.410396 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3103 19:55:13.416742 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3104 19:55:13.416824 ==
3105 19:55:13.420650 Dram Type= 6, Freq= 0, CH_0, rank 1
3106 19:55:13.424120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 19:55:13.424228 ==
3108 19:55:13.424325 DQS Delay:
3109 19:55:13.426733 DQS0 = 0, DQS1 = 0
3110 19:55:13.426814 DQM Delay:
3111 19:55:13.430103 DQM0 = 116, DQM1 = 107
3112 19:55:13.430184 DQ Delay:
3113 19:55:13.433468 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =112
3114 19:55:13.436988 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3115 19:55:13.440290 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3116 19:55:13.443656 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3117 19:55:13.443798
3118 19:55:13.443865
3119 19:55:13.453327 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 403 ps
3120 19:55:13.456534 CH0 RK1: MR19=403, MR18=10EA
3121 19:55:13.463441 CH0_RK1: MR19=0x403, MR18=0x10EA, DQSOSC=403, MR23=63, INC=40, DEC=26
3122 19:55:13.463553 [RxdqsGatingPostProcess] freq 1200
3123 19:55:13.469916 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3124 19:55:13.473330 best DQS0 dly(2T, 0.5T) = (0, 11)
3125 19:55:13.476499 best DQS1 dly(2T, 0.5T) = (0, 12)
3126 19:55:13.479614 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3127 19:55:13.483233 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3128 19:55:13.486531 best DQS0 dly(2T, 0.5T) = (0, 11)
3129 19:55:13.490083 best DQS1 dly(2T, 0.5T) = (0, 12)
3130 19:55:13.493462 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3131 19:55:13.497363 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3132 19:55:13.499808 Pre-setting of DQS Precalculation
3133 19:55:13.503175 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3134 19:55:13.503256 ==
3135 19:55:13.507325 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 19:55:13.509807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 19:55:13.509913 ==
3138 19:55:13.516944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3139 19:55:13.522795 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3140 19:55:13.531124 [CA 0] Center 37 (7~68) winsize 62
3141 19:55:13.534607 [CA 1] Center 37 (7~68) winsize 62
3142 19:55:13.537688 [CA 2] Center 34 (4~64) winsize 61
3143 19:55:13.540881 [CA 3] Center 33 (3~64) winsize 62
3144 19:55:13.543954 [CA 4] Center 34 (4~64) winsize 61
3145 19:55:13.547379 [CA 5] Center 33 (3~64) winsize 62
3146 19:55:13.547461
3147 19:55:13.550771 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3148 19:55:13.550877
3149 19:55:13.554102 [CATrainingPosCal] consider 1 rank data
3150 19:55:13.557613 u2DelayCellTimex100 = 270/100 ps
3151 19:55:13.561423 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3152 19:55:13.568273 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3153 19:55:13.570695 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3154 19:55:13.574751 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3155 19:55:13.577299 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 19:55:13.580869 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3157 19:55:13.580951
3158 19:55:13.584601 CA PerBit enable=1, Macro0, CA PI delay=33
3159 19:55:13.584684
3160 19:55:13.587254 [CBTSetCACLKResult] CA Dly = 33
3161 19:55:13.587335 CS Dly: 6 (0~37)
3162 19:55:13.590601 ==
3163 19:55:13.594084 Dram Type= 6, Freq= 0, CH_1, rank 1
3164 19:55:13.597460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 19:55:13.597542 ==
3166 19:55:13.600492 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3167 19:55:13.607390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3168 19:55:13.616526 [CA 0] Center 37 (7~68) winsize 62
3169 19:55:13.619916 [CA 1] Center 38 (8~68) winsize 61
3170 19:55:13.623117 [CA 2] Center 34 (4~65) winsize 62
3171 19:55:13.626737 [CA 3] Center 33 (3~64) winsize 62
3172 19:55:13.630051 [CA 4] Center 34 (3~65) winsize 63
3173 19:55:13.633487 [CA 5] Center 33 (3~64) winsize 62
3174 19:55:13.633566
3175 19:55:13.637182 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3176 19:55:13.637262
3177 19:55:13.640142 [CATrainingPosCal] consider 2 rank data
3178 19:55:13.643551 u2DelayCellTimex100 = 270/100 ps
3179 19:55:13.646485 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3180 19:55:13.649770 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3181 19:55:13.656715 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3182 19:55:13.660326 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3183 19:55:13.663022 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3184 19:55:13.666480 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3185 19:55:13.666563
3186 19:55:13.670355 CA PerBit enable=1, Macro0, CA PI delay=33
3187 19:55:13.670438
3188 19:55:13.673291 [CBTSetCACLKResult] CA Dly = 33
3189 19:55:13.673373 CS Dly: 7 (0~40)
3190 19:55:13.673438
3191 19:55:13.676512 ----->DramcWriteLeveling(PI) begin...
3192 19:55:13.679844 ==
3193 19:55:13.683009 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 19:55:13.686696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 19:55:13.686779 ==
3196 19:55:13.689993 Write leveling (Byte 0): 24 => 24
3197 19:55:13.692882 Write leveling (Byte 1): 27 => 27
3198 19:55:13.696141 DramcWriteLeveling(PI) end<-----
3199 19:55:13.696223
3200 19:55:13.696287 ==
3201 19:55:13.699552 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 19:55:13.702892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 19:55:13.702976 ==
3204 19:55:13.706593 [Gating] SW mode calibration
3205 19:55:13.712652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3206 19:55:13.719844 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3207 19:55:13.723205 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3208 19:55:13.726277 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 19:55:13.732567 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 19:55:13.735887 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 19:55:13.739224 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 19:55:13.745969 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 19:55:13.749447 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
3214 19:55:13.753373 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3215 19:55:13.756591 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 19:55:13.762510 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 19:55:13.766289 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 19:55:13.769299 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 19:55:13.775687 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 19:55:13.779524 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 19:55:13.782726 1 0 24 | B1->B0 | 2929 3535 | 0 1 | (0 0) (0 0)
3222 19:55:13.789273 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3223 19:55:13.792788 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 19:55:13.795925 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 19:55:13.802788 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 19:55:13.805704 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 19:55:13.808686 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 19:55:13.815887 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 19:55:13.818953 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3230 19:55:13.821910 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3231 19:55:13.828714 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 19:55:13.832253 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 19:55:13.835437 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 19:55:13.842007 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 19:55:13.845570 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 19:55:13.848724 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 19:55:13.855343 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 19:55:13.858530 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 19:55:13.861926 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 19:55:13.868477 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 19:55:13.872256 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 19:55:13.875543 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 19:55:13.882360 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 19:55:13.885499 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 19:55:13.888343 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3246 19:55:13.895655 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 19:55:13.895746 Total UI for P1: 0, mck2ui 16
3248 19:55:13.901708 best dqsien dly found for B0: ( 1, 3, 24)
3249 19:55:13.901790 Total UI for P1: 0, mck2ui 16
3250 19:55:13.908263 best dqsien dly found for B1: ( 1, 3, 24)
3251 19:55:13.911987 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3252 19:55:13.914992 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3253 19:55:13.915072
3254 19:55:13.918143 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3255 19:55:13.921566 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3256 19:55:13.924743 [Gating] SW calibration Done
3257 19:55:13.924823 ==
3258 19:55:13.928236 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 19:55:13.931537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 19:55:13.931633 ==
3261 19:55:13.935059 RX Vref Scan: 0
3262 19:55:13.935139
3263 19:55:13.935202 RX Vref 0 -> 0, step: 1
3264 19:55:13.935260
3265 19:55:13.937964 RX Delay -40 -> 252, step: 8
3266 19:55:13.941245 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3267 19:55:13.948412 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3268 19:55:13.951585 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3269 19:55:13.954635 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3270 19:55:13.957799 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3271 19:55:13.961271 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3272 19:55:13.968274 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3273 19:55:13.971036 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3274 19:55:13.974353 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3275 19:55:13.978296 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3276 19:55:13.980974 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3277 19:55:13.988812 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3278 19:55:13.991357 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3279 19:55:13.995051 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3280 19:55:13.997807 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3281 19:55:14.001502 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3282 19:55:14.004245 ==
3283 19:55:14.007894 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 19:55:14.011380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 19:55:14.011463 ==
3286 19:55:14.011528 DQS Delay:
3287 19:55:14.014832 DQS0 = 0, DQS1 = 0
3288 19:55:14.014914 DQM Delay:
3289 19:55:14.017390 DQM0 = 117, DQM1 = 109
3290 19:55:14.017471 DQ Delay:
3291 19:55:14.020726 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3292 19:55:14.024658 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3293 19:55:14.027893 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3294 19:55:14.030901 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3295 19:55:14.030982
3296 19:55:14.031047
3297 19:55:14.031107 ==
3298 19:55:14.034622 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 19:55:14.040653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 19:55:14.040735 ==
3301 19:55:14.040801
3302 19:55:14.040860
3303 19:55:14.040917 TX Vref Scan disable
3304 19:55:14.044184 == TX Byte 0 ==
3305 19:55:14.047638 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3306 19:55:14.051332 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3307 19:55:14.054041 == TX Byte 1 ==
3308 19:55:14.057259 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3309 19:55:14.060788 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3310 19:55:14.064139 ==
3311 19:55:14.067657 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 19:55:14.070633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 19:55:14.070715 ==
3314 19:55:14.081998 TX Vref=22, minBit 10, minWin=24, winSum=410
3315 19:55:14.085557 TX Vref=24, minBit 8, minWin=25, winSum=422
3316 19:55:14.088589 TX Vref=26, minBit 9, minWin=25, winSum=425
3317 19:55:14.092175 TX Vref=28, minBit 9, minWin=25, winSum=429
3318 19:55:14.095625 TX Vref=30, minBit 9, minWin=25, winSum=430
3319 19:55:14.102059 TX Vref=32, minBit 9, minWin=25, winSum=427
3320 19:55:14.105674 [TxChooseVref] Worse bit 9, Min win 25, Win sum 430, Final Vref 30
3321 19:55:14.105755
3322 19:55:14.108504 Final TX Range 1 Vref 30
3323 19:55:14.108585
3324 19:55:14.108648 ==
3325 19:55:14.112310 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 19:55:14.115625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 19:55:14.115720 ==
3328 19:55:14.119087
3329 19:55:14.119166
3330 19:55:14.119229 TX Vref Scan disable
3331 19:55:14.122233 == TX Byte 0 ==
3332 19:55:14.125314 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3333 19:55:14.129058 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3334 19:55:14.131677 == TX Byte 1 ==
3335 19:55:14.135339 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3336 19:55:14.138479 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3337 19:55:14.141779
3338 19:55:14.141858 [DATLAT]
3339 19:55:14.141921 Freq=1200, CH1 RK0
3340 19:55:14.141980
3341 19:55:14.145223 DATLAT Default: 0xd
3342 19:55:14.145303 0, 0xFFFF, sum = 0
3343 19:55:14.148502 1, 0xFFFF, sum = 0
3344 19:55:14.148582 2, 0xFFFF, sum = 0
3345 19:55:14.151635 3, 0xFFFF, sum = 0
3346 19:55:14.151798 4, 0xFFFF, sum = 0
3347 19:55:14.155299 5, 0xFFFF, sum = 0
3348 19:55:14.158907 6, 0xFFFF, sum = 0
3349 19:55:14.158989 7, 0xFFFF, sum = 0
3350 19:55:14.161743 8, 0xFFFF, sum = 0
3351 19:55:14.161824 9, 0xFFFF, sum = 0
3352 19:55:14.165104 10, 0xFFFF, sum = 0
3353 19:55:14.165184 11, 0xFFFF, sum = 0
3354 19:55:14.168230 12, 0x0, sum = 1
3355 19:55:14.168310 13, 0x0, sum = 2
3356 19:55:14.172435 14, 0x0, sum = 3
3357 19:55:14.172517 15, 0x0, sum = 4
3358 19:55:14.172582 best_step = 13
3359 19:55:14.174796
3360 19:55:14.174876 ==
3361 19:55:14.178707 Dram Type= 6, Freq= 0, CH_1, rank 0
3362 19:55:14.181977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3363 19:55:14.182058 ==
3364 19:55:14.182123 RX Vref Scan: 1
3365 19:55:14.182183
3366 19:55:14.185030 Set Vref Range= 32 -> 127
3367 19:55:14.185111
3368 19:55:14.188156 RX Vref 32 -> 127, step: 1
3369 19:55:14.188237
3370 19:55:14.191770 RX Delay -21 -> 252, step: 4
3371 19:55:14.191850
3372 19:55:14.195396 Set Vref, RX VrefLevel [Byte0]: 32
3373 19:55:14.198219 [Byte1]: 32
3374 19:55:14.198301
3375 19:55:14.201968 Set Vref, RX VrefLevel [Byte0]: 33
3376 19:55:14.204715 [Byte1]: 33
3377 19:55:14.208268
3378 19:55:14.208348 Set Vref, RX VrefLevel [Byte0]: 34
3379 19:55:14.211802 [Byte1]: 34
3380 19:55:14.215967
3381 19:55:14.216048 Set Vref, RX VrefLevel [Byte0]: 35
3382 19:55:14.219260 [Byte1]: 35
3383 19:55:14.224224
3384 19:55:14.224305 Set Vref, RX VrefLevel [Byte0]: 36
3385 19:55:14.227622 [Byte1]: 36
3386 19:55:14.231830
3387 19:55:14.231911 Set Vref, RX VrefLevel [Byte0]: 37
3388 19:55:14.235109 [Byte1]: 37
3389 19:55:14.239829
3390 19:55:14.239910 Set Vref, RX VrefLevel [Byte0]: 38
3391 19:55:14.243063 [Byte1]: 38
3392 19:55:14.247758
3393 19:55:14.247853 Set Vref, RX VrefLevel [Byte0]: 39
3394 19:55:14.251010 [Byte1]: 39
3395 19:55:14.255883
3396 19:55:14.255973 Set Vref, RX VrefLevel [Byte0]: 40
3397 19:55:14.259879 [Byte1]: 40
3398 19:55:14.263487
3399 19:55:14.263604 Set Vref, RX VrefLevel [Byte0]: 41
3400 19:55:14.266930 [Byte1]: 41
3401 19:55:14.271512
3402 19:55:14.271593 Set Vref, RX VrefLevel [Byte0]: 42
3403 19:55:14.274896 [Byte1]: 42
3404 19:55:14.279856
3405 19:55:14.279937 Set Vref, RX VrefLevel [Byte0]: 43
3406 19:55:14.282837 [Byte1]: 43
3407 19:55:14.287637
3408 19:55:14.287718 Set Vref, RX VrefLevel [Byte0]: 44
3409 19:55:14.291175 [Byte1]: 44
3410 19:55:14.295148
3411 19:55:14.295229 Set Vref, RX VrefLevel [Byte0]: 45
3412 19:55:14.298775 [Byte1]: 45
3413 19:55:14.303836
3414 19:55:14.303916 Set Vref, RX VrefLevel [Byte0]: 46
3415 19:55:14.306756 [Byte1]: 46
3416 19:55:14.311330
3417 19:55:14.311411 Set Vref, RX VrefLevel [Byte0]: 47
3418 19:55:14.314502 [Byte1]: 47
3419 19:55:14.319567
3420 19:55:14.319648 Set Vref, RX VrefLevel [Byte0]: 48
3421 19:55:14.322574 [Byte1]: 48
3422 19:55:14.327397
3423 19:55:14.327477 Set Vref, RX VrefLevel [Byte0]: 49
3424 19:55:14.330291 [Byte1]: 49
3425 19:55:14.335107
3426 19:55:14.335187 Set Vref, RX VrefLevel [Byte0]: 50
3427 19:55:14.338070 [Byte1]: 50
3428 19:55:14.343324
3429 19:55:14.343404 Set Vref, RX VrefLevel [Byte0]: 51
3430 19:55:14.346458 [Byte1]: 51
3431 19:55:14.350751
3432 19:55:14.350831 Set Vref, RX VrefLevel [Byte0]: 52
3433 19:55:14.353785 [Byte1]: 52
3434 19:55:14.358458
3435 19:55:14.358540 Set Vref, RX VrefLevel [Byte0]: 53
3436 19:55:14.362062 [Byte1]: 53
3437 19:55:14.366651
3438 19:55:14.366732 Set Vref, RX VrefLevel [Byte0]: 54
3439 19:55:14.369730 [Byte1]: 54
3440 19:55:14.374255
3441 19:55:14.374335 Set Vref, RX VrefLevel [Byte0]: 55
3442 19:55:14.377632 [Byte1]: 55
3443 19:55:14.382218
3444 19:55:14.382299 Set Vref, RX VrefLevel [Byte0]: 56
3445 19:55:14.385613 [Byte1]: 56
3446 19:55:14.390442
3447 19:55:14.390523 Set Vref, RX VrefLevel [Byte0]: 57
3448 19:55:14.393432 [Byte1]: 57
3449 19:55:14.398042
3450 19:55:14.398123 Set Vref, RX VrefLevel [Byte0]: 58
3451 19:55:14.401656 [Byte1]: 58
3452 19:55:14.406308
3453 19:55:14.406388 Set Vref, RX VrefLevel [Byte0]: 59
3454 19:55:14.409286 [Byte1]: 59
3455 19:55:14.414108
3456 19:55:14.414188 Set Vref, RX VrefLevel [Byte0]: 60
3457 19:55:14.417335 [Byte1]: 60
3458 19:55:14.421858
3459 19:55:14.421938 Set Vref, RX VrefLevel [Byte0]: 61
3460 19:55:14.425363 [Byte1]: 61
3461 19:55:14.429839
3462 19:55:14.429919 Set Vref, RX VrefLevel [Byte0]: 62
3463 19:55:14.433265 [Byte1]: 62
3464 19:55:14.437778
3465 19:55:14.437859 Set Vref, RX VrefLevel [Byte0]: 63
3466 19:55:14.441131 [Byte1]: 63
3467 19:55:14.445823
3468 19:55:14.445904 Set Vref, RX VrefLevel [Byte0]: 64
3469 19:55:14.448966 [Byte1]: 64
3470 19:55:14.453819
3471 19:55:14.453901 Set Vref, RX VrefLevel [Byte0]: 65
3472 19:55:14.457412 [Byte1]: 65
3473 19:55:14.461496
3474 19:55:14.461578 Set Vref, RX VrefLevel [Byte0]: 66
3475 19:55:14.465072 [Byte1]: 66
3476 19:55:14.469449
3477 19:55:14.469532 Set Vref, RX VrefLevel [Byte0]: 67
3478 19:55:14.472791 [Byte1]: 67
3479 19:55:14.477375
3480 19:55:14.477454 Set Vref, RX VrefLevel [Byte0]: 68
3481 19:55:14.480546 [Byte1]: 68
3482 19:55:14.486202
3483 19:55:14.486282 Final RX Vref Byte 0 = 48 to rank0
3484 19:55:14.488475 Final RX Vref Byte 1 = 58 to rank0
3485 19:55:14.491709 Final RX Vref Byte 0 = 48 to rank1
3486 19:55:14.495131 Final RX Vref Byte 1 = 58 to rank1==
3487 19:55:14.498569 Dram Type= 6, Freq= 0, CH_1, rank 0
3488 19:55:14.506054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 19:55:14.506136 ==
3490 19:55:14.506200 DQS Delay:
3491 19:55:14.506259 DQS0 = 0, DQS1 = 0
3492 19:55:14.508857 DQM Delay:
3493 19:55:14.508936 DQM0 = 115, DQM1 = 110
3494 19:55:14.511698 DQ Delay:
3495 19:55:14.515236 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3496 19:55:14.518859 DQ4 =112, DQ5 =126, DQ6 =124, DQ7 =114
3497 19:55:14.521976 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =100
3498 19:55:14.525544 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3499 19:55:14.525623
3500 19:55:14.525686
3501 19:55:14.535041 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 408 ps
3502 19:55:14.535127 CH1 RK0: MR19=403, MR18=5F9
3503 19:55:14.541821 CH1_RK0: MR19=0x403, MR18=0x5F9, DQSOSC=408, MR23=63, INC=39, DEC=26
3504 19:55:14.541902
3505 19:55:14.544948 ----->DramcWriteLeveling(PI) begin...
3506 19:55:14.545033 ==
3507 19:55:14.548649 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 19:55:14.551629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 19:55:14.555134 ==
3510 19:55:14.555215 Write leveling (Byte 0): 25 => 25
3511 19:55:14.558260 Write leveling (Byte 1): 28 => 28
3512 19:55:14.561545 DramcWriteLeveling(PI) end<-----
3513 19:55:14.561625
3514 19:55:14.561687 ==
3515 19:55:14.565096 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 19:55:14.571758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 19:55:14.571870 ==
3518 19:55:14.575020 [Gating] SW mode calibration
3519 19:55:14.581153 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3520 19:55:14.584689 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3521 19:55:14.590962 0 15 0 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
3522 19:55:14.594540 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 19:55:14.597718 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 19:55:14.604305 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 19:55:14.607485 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 19:55:14.611470 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 19:55:14.617515 0 15 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
3528 19:55:14.620739 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3529 19:55:14.624267 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 19:55:14.630798 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 19:55:14.634337 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 19:55:14.637450 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 19:55:14.644046 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 19:55:14.647233 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 19:55:14.650949 1 0 24 | B1->B0 | 3c3c 2726 | 0 1 | (0 0) (0 0)
3536 19:55:14.657134 1 0 28 | B1->B0 | 4545 4343 | 1 0 | (0 0) (0 0)
3537 19:55:14.660485 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 19:55:14.664073 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 19:55:14.670499 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 19:55:14.673679 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 19:55:14.677049 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 19:55:14.683493 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 19:55:14.687295 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3544 19:55:14.690582 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3545 19:55:14.697755 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 19:55:14.700737 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 19:55:14.703690 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 19:55:14.709955 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 19:55:14.713911 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 19:55:14.716915 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 19:55:14.723170 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 19:55:14.726827 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 19:55:14.730376 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 19:55:14.733423 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 19:55:14.740915 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 19:55:14.743018 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 19:55:14.750128 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 19:55:14.753021 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 19:55:14.756474 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3560 19:55:14.762749 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3561 19:55:14.766163 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3562 19:55:14.769877 Total UI for P1: 0, mck2ui 16
3563 19:55:14.773060 best dqsien dly found for B0: ( 1, 3, 28)
3564 19:55:14.776031 Total UI for P1: 0, mck2ui 16
3565 19:55:14.779085 best dqsien dly found for B1: ( 1, 3, 26)
3566 19:55:14.782319 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3567 19:55:14.785529 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3568 19:55:14.785609
3569 19:55:14.788920 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3570 19:55:14.792434 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3571 19:55:14.795605 [Gating] SW calibration Done
3572 19:55:14.795711 ==
3573 19:55:14.798957 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 19:55:14.802478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 19:55:14.805653 ==
3576 19:55:14.805733 RX Vref Scan: 0
3577 19:55:14.805798
3578 19:55:14.808705 RX Vref 0 -> 0, step: 1
3579 19:55:14.808785
3580 19:55:14.811997 RX Delay -40 -> 252, step: 8
3581 19:55:14.815478 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3582 19:55:14.818797 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3583 19:55:14.821822 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3584 19:55:14.826071 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3585 19:55:14.832288 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3586 19:55:14.835303 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3587 19:55:14.838448 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3588 19:55:14.841915 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3589 19:55:14.845236 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3590 19:55:14.851515 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3591 19:55:14.855268 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3592 19:55:14.858890 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3593 19:55:14.861807 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3594 19:55:14.865233 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3595 19:55:14.871512 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3596 19:55:14.875276 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3597 19:55:14.875357 ==
3598 19:55:14.878023 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 19:55:14.881640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 19:55:14.881722 ==
3601 19:55:14.884818 DQS Delay:
3602 19:55:14.884898 DQS0 = 0, DQS1 = 0
3603 19:55:14.884963 DQM Delay:
3604 19:55:14.888241 DQM0 = 116, DQM1 = 110
3605 19:55:14.888322 DQ Delay:
3606 19:55:14.891476 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3607 19:55:14.894872 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3608 19:55:14.901306 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3609 19:55:14.904436 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3610 19:55:14.904517
3611 19:55:14.904582
3612 19:55:14.904641 ==
3613 19:55:14.907901 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 19:55:14.910978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 19:55:14.911059 ==
3616 19:55:14.911123
3617 19:55:14.911182
3618 19:55:14.914535 TX Vref Scan disable
3619 19:55:14.917589 == TX Byte 0 ==
3620 19:55:14.921964 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3621 19:55:14.924120 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3622 19:55:14.927673 == TX Byte 1 ==
3623 19:55:14.930832 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3624 19:55:14.934419 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3625 19:55:14.934501 ==
3626 19:55:14.937389 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 19:55:14.940628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 19:55:14.944043 ==
3629 19:55:14.954253 TX Vref=22, minBit 9, minWin=25, winSum=423
3630 19:55:14.957312 TX Vref=24, minBit 8, minWin=25, winSum=424
3631 19:55:14.960660 TX Vref=26, minBit 8, minWin=26, winSum=431
3632 19:55:14.963896 TX Vref=28, minBit 9, minWin=26, winSum=431
3633 19:55:14.967353 TX Vref=30, minBit 8, minWin=26, winSum=433
3634 19:55:14.974197 TX Vref=32, minBit 8, minWin=26, winSum=431
3635 19:55:14.977785 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
3636 19:55:14.977866
3637 19:55:14.980899 Final TX Range 1 Vref 30
3638 19:55:14.981008
3639 19:55:14.981083 ==
3640 19:55:14.983889 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 19:55:14.987029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 19:55:14.991312 ==
3643 19:55:14.991417
3644 19:55:14.991508
3645 19:55:14.991596 TX Vref Scan disable
3646 19:55:14.994297 == TX Byte 0 ==
3647 19:55:14.997005 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3648 19:55:15.003692 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3649 19:55:15.003817 == TX Byte 1 ==
3650 19:55:15.006978 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3651 19:55:15.013587 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3652 19:55:15.013670
3653 19:55:15.013734 [DATLAT]
3654 19:55:15.013794 Freq=1200, CH1 RK1
3655 19:55:15.013851
3656 19:55:15.017063 DATLAT Default: 0xd
3657 19:55:15.017144 0, 0xFFFF, sum = 0
3658 19:55:15.020324 1, 0xFFFF, sum = 0
3659 19:55:15.023453 2, 0xFFFF, sum = 0
3660 19:55:15.023535 3, 0xFFFF, sum = 0
3661 19:55:15.026863 4, 0xFFFF, sum = 0
3662 19:55:15.026947 5, 0xFFFF, sum = 0
3663 19:55:15.031082 6, 0xFFFF, sum = 0
3664 19:55:15.031243 7, 0xFFFF, sum = 0
3665 19:55:15.033891 8, 0xFFFF, sum = 0
3666 19:55:15.034054 9, 0xFFFF, sum = 0
3667 19:55:15.037211 10, 0xFFFF, sum = 0
3668 19:55:15.037375 11, 0xFFFF, sum = 0
3669 19:55:15.040566 12, 0x0, sum = 1
3670 19:55:15.040728 13, 0x0, sum = 2
3671 19:55:15.043496 14, 0x0, sum = 3
3672 19:55:15.043665 15, 0x0, sum = 4
3673 19:55:15.047169 best_step = 13
3674 19:55:15.047329
3675 19:55:15.047402 ==
3676 19:55:15.050366 Dram Type= 6, Freq= 0, CH_1, rank 1
3677 19:55:15.053083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3678 19:55:15.053240 ==
3679 19:55:15.056484 RX Vref Scan: 0
3680 19:55:15.056623
3681 19:55:15.056697 RX Vref 0 -> 0, step: 1
3682 19:55:15.056764
3683 19:55:15.059874 RX Delay -21 -> 252, step: 4
3684 19:55:15.066996 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3685 19:55:15.070207 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3686 19:55:15.073097 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3687 19:55:15.076261 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3688 19:55:15.080324 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3689 19:55:15.086655 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3690 19:55:15.089754 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3691 19:55:15.093169 iDelay=199, Bit 7, Center 112 (47 ~ 178) 132
3692 19:55:15.096524 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3693 19:55:15.099436 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3694 19:55:15.106125 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3695 19:55:15.109636 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3696 19:55:15.112826 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3697 19:55:15.116123 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3698 19:55:15.122933 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3699 19:55:15.126516 iDelay=199, Bit 15, Center 122 (55 ~ 190) 136
3700 19:55:15.127103 ==
3701 19:55:15.129632 Dram Type= 6, Freq= 0, CH_1, rank 1
3702 19:55:15.132665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3703 19:55:15.133041 ==
3704 19:55:15.135568 DQS Delay:
3705 19:55:15.135657 DQS0 = 0, DQS1 = 0
3706 19:55:15.135784 DQM Delay:
3707 19:55:15.139441 DQM0 = 116, DQM1 = 112
3708 19:55:15.139624 DQ Delay:
3709 19:55:15.142772 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =112
3710 19:55:15.145745 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =112
3711 19:55:15.152226 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =102
3712 19:55:15.155584 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =122
3713 19:55:15.155706
3714 19:55:15.155818
3715 19:55:15.161933 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5f1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3716 19:55:15.165521 CH1 RK1: MR19=303, MR18=F5F1
3717 19:55:15.171957 CH1_RK1: MR19=0x303, MR18=0xF5F1, DQSOSC=414, MR23=63, INC=38, DEC=25
3718 19:55:15.175986 [RxdqsGatingPostProcess] freq 1200
3719 19:55:15.179033 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3720 19:55:15.181836 best DQS0 dly(2T, 0.5T) = (0, 11)
3721 19:55:15.185327 best DQS1 dly(2T, 0.5T) = (0, 11)
3722 19:55:15.188606 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3723 19:55:15.191770 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3724 19:55:15.195001 best DQS0 dly(2T, 0.5T) = (0, 11)
3725 19:55:15.198929 best DQS1 dly(2T, 0.5T) = (0, 11)
3726 19:55:15.201446 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3727 19:55:15.204787 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3728 19:55:15.208606 Pre-setting of DQS Precalculation
3729 19:55:15.214586 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3730 19:55:15.221401 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3731 19:55:15.227646 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3732 19:55:15.227788
3733 19:55:15.227855
3734 19:55:15.231833 [Calibration Summary] 2400 Mbps
3735 19:55:15.232161 CH 0, Rank 0
3736 19:55:15.234579 SW Impedance : PASS
3737 19:55:15.238043 DUTY Scan : NO K
3738 19:55:15.238282 ZQ Calibration : PASS
3739 19:55:15.241154 Jitter Meter : NO K
3740 19:55:15.244566 CBT Training : PASS
3741 19:55:15.244756 Write leveling : PASS
3742 19:55:15.247930 RX DQS gating : PASS
3743 19:55:15.251465 RX DQ/DQS(RDDQC) : PASS
3744 19:55:15.251599 TX DQ/DQS : PASS
3745 19:55:15.254740 RX DATLAT : PASS
3746 19:55:15.254881 RX DQ/DQS(Engine): PASS
3747 19:55:15.257355 TX OE : NO K
3748 19:55:15.257516 All Pass.
3749 19:55:15.257648
3750 19:55:15.261161 CH 0, Rank 1
3751 19:55:15.261313 SW Impedance : PASS
3752 19:55:15.264032 DUTY Scan : NO K
3753 19:55:15.267204 ZQ Calibration : PASS
3754 19:55:15.267307 Jitter Meter : NO K
3755 19:55:15.270798 CBT Training : PASS
3756 19:55:15.274060 Write leveling : PASS
3757 19:55:15.274154 RX DQS gating : PASS
3758 19:55:15.277225 RX DQ/DQS(RDDQC) : PASS
3759 19:55:15.280746 TX DQ/DQS : PASS
3760 19:55:15.280831 RX DATLAT : PASS
3761 19:55:15.284093 RX DQ/DQS(Engine): PASS
3762 19:55:15.287009 TX OE : NO K
3763 19:55:15.287089 All Pass.
3764 19:55:15.287152
3765 19:55:15.287211 CH 1, Rank 0
3766 19:55:15.291054 SW Impedance : PASS
3767 19:55:15.293776 DUTY Scan : NO K
3768 19:55:15.293856 ZQ Calibration : PASS
3769 19:55:15.297178 Jitter Meter : NO K
3770 19:55:15.300725 CBT Training : PASS
3771 19:55:15.300808 Write leveling : PASS
3772 19:55:15.303860 RX DQS gating : PASS
3773 19:55:15.307087 RX DQ/DQS(RDDQC) : PASS
3774 19:55:15.307166 TX DQ/DQS : PASS
3775 19:55:15.310568 RX DATLAT : PASS
3776 19:55:15.313862 RX DQ/DQS(Engine): PASS
3777 19:55:15.313943 TX OE : NO K
3778 19:55:15.314006 All Pass.
3779 19:55:15.317332
3780 19:55:15.317412 CH 1, Rank 1
3781 19:55:15.320301 SW Impedance : PASS
3782 19:55:15.320381 DUTY Scan : NO K
3783 19:55:15.323603 ZQ Calibration : PASS
3784 19:55:15.326789 Jitter Meter : NO K
3785 19:55:15.326870 CBT Training : PASS
3786 19:55:15.330714 Write leveling : PASS
3787 19:55:15.330795 RX DQS gating : PASS
3788 19:55:15.333767 RX DQ/DQS(RDDQC) : PASS
3789 19:55:15.336653 TX DQ/DQS : PASS
3790 19:55:15.336734 RX DATLAT : PASS
3791 19:55:15.340387 RX DQ/DQS(Engine): PASS
3792 19:55:15.343229 TX OE : NO K
3793 19:55:15.343310 All Pass.
3794 19:55:15.343373
3795 19:55:15.346823 DramC Write-DBI off
3796 19:55:15.346904 PER_BANK_REFRESH: Hybrid Mode
3797 19:55:15.349892 TX_TRACKING: ON
3798 19:55:15.359693 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3799 19:55:15.362928 [FAST_K] Save calibration result to emmc
3800 19:55:15.366546 dramc_set_vcore_voltage set vcore to 650000
3801 19:55:15.369776 Read voltage for 600, 5
3802 19:55:15.369857 Vio18 = 0
3803 19:55:15.369922 Vcore = 650000
3804 19:55:15.372996 Vdram = 0
3805 19:55:15.373077 Vddq = 0
3806 19:55:15.373141 Vmddr = 0
3807 19:55:15.379608 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3808 19:55:15.382889 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3809 19:55:15.386310 MEM_TYPE=3, freq_sel=19
3810 19:55:15.389507 sv_algorithm_assistance_LP4_1600
3811 19:55:15.393175 ============ PULL DRAM RESETB DOWN ============
3812 19:55:15.396053 ========== PULL DRAM RESETB DOWN end =========
3813 19:55:15.402657 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3814 19:55:15.405686 ===================================
3815 19:55:15.405767 LPDDR4 DRAM CONFIGURATION
3816 19:55:15.409200 ===================================
3817 19:55:15.413058 EX_ROW_EN[0] = 0x0
3818 19:55:15.416157 EX_ROW_EN[1] = 0x0
3819 19:55:15.416237 LP4Y_EN = 0x0
3820 19:55:15.419045 WORK_FSP = 0x0
3821 19:55:15.419125 WL = 0x2
3822 19:55:15.422661 RL = 0x2
3823 19:55:15.422742 BL = 0x2
3824 19:55:15.425970 RPST = 0x0
3825 19:55:15.426051 RD_PRE = 0x0
3826 19:55:15.428679 WR_PRE = 0x1
3827 19:55:15.428760 WR_PST = 0x0
3828 19:55:15.432924 DBI_WR = 0x0
3829 19:55:15.433004 DBI_RD = 0x0
3830 19:55:15.435380 OTF = 0x1
3831 19:55:15.438911 ===================================
3832 19:55:15.442009 ===================================
3833 19:55:15.442090 ANA top config
3834 19:55:15.445206 ===================================
3835 19:55:15.448665 DLL_ASYNC_EN = 0
3836 19:55:15.452806 ALL_SLAVE_EN = 1
3837 19:55:15.455647 NEW_RANK_MODE = 1
3838 19:55:15.455787 DLL_IDLE_MODE = 1
3839 19:55:15.458499 LP45_APHY_COMB_EN = 1
3840 19:55:15.461736 TX_ODT_DIS = 1
3841 19:55:15.465670 NEW_8X_MODE = 1
3842 19:55:15.468526 ===================================
3843 19:55:15.471938 ===================================
3844 19:55:15.474884 data_rate = 1200
3845 19:55:15.478186 CKR = 1
3846 19:55:15.478267 DQ_P2S_RATIO = 8
3847 19:55:15.481543 ===================================
3848 19:55:15.484902 CA_P2S_RATIO = 8
3849 19:55:15.488027 DQ_CA_OPEN = 0
3850 19:55:15.491340 DQ_SEMI_OPEN = 0
3851 19:55:15.494815 CA_SEMI_OPEN = 0
3852 19:55:15.498538 CA_FULL_RATE = 0
3853 19:55:15.498619 DQ_CKDIV4_EN = 1
3854 19:55:15.501102 CA_CKDIV4_EN = 1
3855 19:55:15.504917 CA_PREDIV_EN = 0
3856 19:55:15.508389 PH8_DLY = 0
3857 19:55:15.511516 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3858 19:55:15.514840 DQ_AAMCK_DIV = 4
3859 19:55:15.514921 CA_AAMCK_DIV = 4
3860 19:55:15.517847 CA_ADMCK_DIV = 4
3861 19:55:15.521898 DQ_TRACK_CA_EN = 0
3862 19:55:15.524335 CA_PICK = 600
3863 19:55:15.528263 CA_MCKIO = 600
3864 19:55:15.531106 MCKIO_SEMI = 0
3865 19:55:15.535200 PLL_FREQ = 2288
3866 19:55:15.535281 DQ_UI_PI_RATIO = 32
3867 19:55:15.537799 CA_UI_PI_RATIO = 0
3868 19:55:15.541002 ===================================
3869 19:55:15.544770 ===================================
3870 19:55:15.548057 memory_type:LPDDR4
3871 19:55:15.551049 GP_NUM : 10
3872 19:55:15.551129 SRAM_EN : 1
3873 19:55:15.554551 MD32_EN : 0
3874 19:55:15.557325 ===================================
3875 19:55:15.561299 [ANA_INIT] >>>>>>>>>>>>>>
3876 19:55:15.563783 <<<<<< [CONFIGURE PHASE]: ANA_TX
3877 19:55:15.568077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3878 19:55:15.570455 ===================================
3879 19:55:15.570535 data_rate = 1200,PCW = 0X5800
3880 19:55:15.574417 ===================================
3881 19:55:15.577181 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3882 19:55:15.583439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3883 19:55:15.590546 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3884 19:55:15.593453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3885 19:55:15.596897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3886 19:55:15.600064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3887 19:55:15.603043 [ANA_INIT] flow start
3888 19:55:15.606657 [ANA_INIT] PLL >>>>>>>>
3889 19:55:15.606740 [ANA_INIT] PLL <<<<<<<<
3890 19:55:15.610145 [ANA_INIT] MIDPI >>>>>>>>
3891 19:55:15.612926 [ANA_INIT] MIDPI <<<<<<<<
3892 19:55:15.613010 [ANA_INIT] DLL >>>>>>>>
3893 19:55:15.616621 [ANA_INIT] flow end
3894 19:55:15.619593 ============ LP4 DIFF to SE enter ============
3895 19:55:15.626200 ============ LP4 DIFF to SE exit ============
3896 19:55:15.626286 [ANA_INIT] <<<<<<<<<<<<<
3897 19:55:15.630075 [Flow] Enable top DCM control >>>>>
3898 19:55:15.633256 [Flow] Enable top DCM control <<<<<
3899 19:55:15.636283 Enable DLL master slave shuffle
3900 19:55:15.643336 ==============================================================
3901 19:55:15.643424 Gating Mode config
3902 19:55:15.649730 ==============================================================
3903 19:55:15.652681 Config description:
3904 19:55:15.662982 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3905 19:55:15.669395 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3906 19:55:15.672569 SELPH_MODE 0: By rank 1: By Phase
3907 19:55:15.678840 ==============================================================
3908 19:55:15.682542 GAT_TRACK_EN = 1
3909 19:55:15.686091 RX_GATING_MODE = 2
3910 19:55:15.686178 RX_GATING_TRACK_MODE = 2
3911 19:55:15.688897 SELPH_MODE = 1
3912 19:55:15.692194 PICG_EARLY_EN = 1
3913 19:55:15.695228 VALID_LAT_VALUE = 1
3914 19:55:15.702015 ==============================================================
3915 19:55:15.706112 Enter into Gating configuration >>>>
3916 19:55:15.708373 Exit from Gating configuration <<<<
3917 19:55:15.711798 Enter into DVFS_PRE_config >>>>>
3918 19:55:15.722054 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3919 19:55:15.724949 Exit from DVFS_PRE_config <<<<<
3920 19:55:15.728312 Enter into PICG configuration >>>>
3921 19:55:15.731642 Exit from PICG configuration <<<<
3922 19:55:15.735048 [RX_INPUT] configuration >>>>>
3923 19:55:15.738265 [RX_INPUT] configuration <<<<<
3924 19:55:15.741891 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3925 19:55:15.748763 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3926 19:55:15.755255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3927 19:55:15.761364 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3928 19:55:15.768178 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3929 19:55:15.772000 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3930 19:55:15.778256 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3931 19:55:15.781128 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3932 19:55:15.784608 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3933 19:55:15.787557 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3934 19:55:15.794395 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3935 19:55:15.797881 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3936 19:55:15.800997 ===================================
3937 19:55:15.804172 LPDDR4 DRAM CONFIGURATION
3938 19:55:15.807884 ===================================
3939 19:55:15.808043 EX_ROW_EN[0] = 0x0
3940 19:55:15.811641 EX_ROW_EN[1] = 0x0
3941 19:55:15.811821 LP4Y_EN = 0x0
3942 19:55:15.814397 WORK_FSP = 0x0
3943 19:55:15.814521 WL = 0x2
3944 19:55:15.817355 RL = 0x2
3945 19:55:15.820928 BL = 0x2
3946 19:55:15.821118 RPST = 0x0
3947 19:55:15.824267 RD_PRE = 0x0
3948 19:55:15.824444 WR_PRE = 0x1
3949 19:55:15.827600 WR_PST = 0x0
3950 19:55:15.827799 DBI_WR = 0x0
3951 19:55:15.830716 DBI_RD = 0x0
3952 19:55:15.830900 OTF = 0x1
3953 19:55:15.834733 ===================================
3954 19:55:15.837457 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3955 19:55:15.843965 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3956 19:55:15.848108 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3957 19:55:15.850651 ===================================
3958 19:55:15.854012 LPDDR4 DRAM CONFIGURATION
3959 19:55:15.857194 ===================================
3960 19:55:15.857574 EX_ROW_EN[0] = 0x10
3961 19:55:15.860717 EX_ROW_EN[1] = 0x0
3962 19:55:15.861079 LP4Y_EN = 0x0
3963 19:55:15.863815 WORK_FSP = 0x0
3964 19:55:15.864178 WL = 0x2
3965 19:55:15.867157 RL = 0x2
3966 19:55:15.870393 BL = 0x2
3967 19:55:15.870751 RPST = 0x0
3968 19:55:15.873632 RD_PRE = 0x0
3969 19:55:15.873988 WR_PRE = 0x1
3970 19:55:15.877321 WR_PST = 0x0
3971 19:55:15.877772 DBI_WR = 0x0
3972 19:55:15.880761 DBI_RD = 0x0
3973 19:55:15.881113 OTF = 0x1
3974 19:55:15.883877 ===================================
3975 19:55:15.890378 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3976 19:55:15.895086 nWR fixed to 30
3977 19:55:15.898052 [ModeRegInit_LP4] CH0 RK0
3978 19:55:15.898506 [ModeRegInit_LP4] CH0 RK1
3979 19:55:15.901175 [ModeRegInit_LP4] CH1 RK0
3980 19:55:15.904423 [ModeRegInit_LP4] CH1 RK1
3981 19:55:15.904809 match AC timing 17
3982 19:55:15.911482 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3983 19:55:15.914300 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3984 19:55:15.917426 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3985 19:55:15.924519 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3986 19:55:15.927835 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3987 19:55:15.928309 ==
3988 19:55:15.930915 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 19:55:15.934978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 19:55:15.935430 ==
3991 19:55:15.940742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3992 19:55:15.947232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3993 19:55:15.950238 [CA 0] Center 36 (6~66) winsize 61
3994 19:55:15.953694 [CA 1] Center 36 (6~66) winsize 61
3995 19:55:15.957079 [CA 2] Center 34 (4~65) winsize 62
3996 19:55:15.960253 [CA 3] Center 34 (4~65) winsize 62
3997 19:55:15.964326 [CA 4] Center 33 (3~64) winsize 62
3998 19:55:15.967777 [CA 5] Center 33 (3~64) winsize 62
3999 19:55:15.968165
4000 19:55:15.970640 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4001 19:55:15.971118
4002 19:55:15.974001 [CATrainingPosCal] consider 1 rank data
4003 19:55:15.977082 u2DelayCellTimex100 = 270/100 ps
4004 19:55:15.980648 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4005 19:55:15.983598 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4006 19:55:15.987060 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4007 19:55:15.990442 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4008 19:55:15.996956 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4009 19:55:16.000675 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4010 19:55:16.001151
4011 19:55:16.003658 CA PerBit enable=1, Macro0, CA PI delay=33
4012 19:55:16.004089
4013 19:55:16.006739 [CBTSetCACLKResult] CA Dly = 33
4014 19:55:16.007219 CS Dly: 5 (0~36)
4015 19:55:16.007529 ==
4016 19:55:16.009940 Dram Type= 6, Freq= 0, CH_0, rank 1
4017 19:55:16.016850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 19:55:16.017332 ==
4019 19:55:16.020371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4020 19:55:16.026713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4021 19:55:16.029771 [CA 0] Center 36 (6~66) winsize 61
4022 19:55:16.033467 [CA 1] Center 36 (6~66) winsize 61
4023 19:55:16.036911 [CA 2] Center 33 (3~64) winsize 62
4024 19:55:16.039999 [CA 3] Center 33 (3~64) winsize 62
4025 19:55:16.043278 [CA 4] Center 33 (2~64) winsize 63
4026 19:55:16.046453 [CA 5] Center 33 (2~64) winsize 63
4027 19:55:16.046943
4028 19:55:16.049778 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4029 19:55:16.050268
4030 19:55:16.052921 [CATrainingPosCal] consider 2 rank data
4031 19:55:16.056192 u2DelayCellTimex100 = 270/100 ps
4032 19:55:16.059849 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4033 19:55:16.063492 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4034 19:55:16.069989 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4035 19:55:16.073133 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4036 19:55:16.076231 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4037 19:55:16.079778 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4038 19:55:16.080303
4039 19:55:16.083097 CA PerBit enable=1, Macro0, CA PI delay=33
4040 19:55:16.083472
4041 19:55:16.086247 [CBTSetCACLKResult] CA Dly = 33
4042 19:55:16.086727 CS Dly: 5 (0~37)
4043 19:55:16.089135
4044 19:55:16.092503 ----->DramcWriteLeveling(PI) begin...
4045 19:55:16.092898 ==
4046 19:55:16.096208 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 19:55:16.099405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 19:55:16.099930 ==
4049 19:55:16.102606 Write leveling (Byte 0): 33 => 33
4050 19:55:16.106384 Write leveling (Byte 1): 32 => 32
4051 19:55:16.109718 DramcWriteLeveling(PI) end<-----
4052 19:55:16.110194
4053 19:55:16.110499 ==
4054 19:55:16.112542 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 19:55:16.115607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 19:55:16.116008 ==
4057 19:55:16.118975 [Gating] SW mode calibration
4058 19:55:16.125840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4059 19:55:16.132554 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4060 19:55:16.136100 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4061 19:55:16.139139 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4062 19:55:16.145642 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4063 19:55:16.148767 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4064 19:55:16.152231 0 9 16 | B1->B0 | 2f2f 2828 | 1 0 | (0 0) (0 0)
4065 19:55:16.158675 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 19:55:16.161758 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 19:55:16.165529 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 19:55:16.171656 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 19:55:16.175328 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 19:55:16.178529 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 19:55:16.184831 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4072 19:55:16.188383 0 10 16 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
4073 19:55:16.191668 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 19:55:16.198623 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 19:55:16.201799 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 19:55:16.205280 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 19:55:16.211505 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 19:55:16.214762 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 19:55:16.218069 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4080 19:55:16.224749 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 19:55:16.228384 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 19:55:16.231146 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 19:55:16.238483 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 19:55:16.241045 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 19:55:16.244192 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 19:55:16.250991 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 19:55:16.254560 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 19:55:16.257649 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 19:55:16.264125 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 19:55:16.267622 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 19:55:16.270320 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 19:55:16.277791 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 19:55:16.280153 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 19:55:16.283496 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 19:55:16.290502 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4096 19:55:16.293439 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4097 19:55:16.297669 Total UI for P1: 0, mck2ui 16
4098 19:55:16.300393 best dqsien dly found for B0: ( 0, 13, 12)
4099 19:55:16.303094 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 19:55:16.306900 Total UI for P1: 0, mck2ui 16
4101 19:55:16.310024 best dqsien dly found for B1: ( 0, 13, 16)
4102 19:55:16.313179 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4103 19:55:16.319956 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4104 19:55:16.320470
4105 19:55:16.323320 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4106 19:55:16.326514 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4107 19:55:16.329938 [Gating] SW calibration Done
4108 19:55:16.330463 ==
4109 19:55:16.333475 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 19:55:16.336601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 19:55:16.337115 ==
4112 19:55:16.339945 RX Vref Scan: 0
4113 19:55:16.340455
4114 19:55:16.340788 RX Vref 0 -> 0, step: 1
4115 19:55:16.341096
4116 19:55:16.343251 RX Delay -230 -> 252, step: 16
4117 19:55:16.346355 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4118 19:55:16.352713 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4119 19:55:16.356181 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4120 19:55:16.359400 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4121 19:55:16.362468 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4122 19:55:16.369403 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4123 19:55:16.372587 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4124 19:55:16.376172 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4125 19:55:16.379404 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4126 19:55:16.383127 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4127 19:55:16.389043 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4128 19:55:16.392345 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4129 19:55:16.395809 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4130 19:55:16.402383 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4131 19:55:16.406021 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4132 19:55:16.408622 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4133 19:55:16.409136 ==
4134 19:55:16.412199 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 19:55:16.415609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 19:55:16.416218 ==
4137 19:55:16.418719 DQS Delay:
4138 19:55:16.419133 DQS0 = 0, DQS1 = 0
4139 19:55:16.422109 DQM Delay:
4140 19:55:16.422692 DQM0 = 43, DQM1 = 36
4141 19:55:16.423039 DQ Delay:
4142 19:55:16.425598 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4143 19:55:16.428545 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4144 19:55:16.432114 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4145 19:55:16.436101 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4146 19:55:16.436623
4147 19:55:16.436963
4148 19:55:16.439289 ==
4149 19:55:16.441787 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 19:55:16.445218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 19:55:16.445644 ==
4152 19:55:16.445977
4153 19:55:16.446287
4154 19:55:16.448711 TX Vref Scan disable
4155 19:55:16.449128 == TX Byte 0 ==
4156 19:55:16.455199 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4157 19:55:16.458272 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4158 19:55:16.458940 == TX Byte 1 ==
4159 19:55:16.464337 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4160 19:55:16.467836 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4161 19:55:16.468525 ==
4162 19:55:16.471794 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 19:55:16.474550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 19:55:16.475000 ==
4165 19:55:16.475265
4166 19:55:16.475683
4167 19:55:16.477988 TX Vref Scan disable
4168 19:55:16.480776 == TX Byte 0 ==
4169 19:55:16.484264 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4170 19:55:16.487447 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4171 19:55:16.491090 == TX Byte 1 ==
4172 19:55:16.494285 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4173 19:55:16.497035 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4174 19:55:16.500743
4175 19:55:16.500861 [DATLAT]
4176 19:55:16.500953 Freq=600, CH0 RK0
4177 19:55:16.501039
4178 19:55:16.504047 DATLAT Default: 0x9
4179 19:55:16.504157 0, 0xFFFF, sum = 0
4180 19:55:16.507093 1, 0xFFFF, sum = 0
4181 19:55:16.507185 2, 0xFFFF, sum = 0
4182 19:55:16.510409 3, 0xFFFF, sum = 0
4183 19:55:16.513868 4, 0xFFFF, sum = 0
4184 19:55:16.513958 5, 0xFFFF, sum = 0
4185 19:55:16.517049 6, 0xFFFF, sum = 0
4186 19:55:16.517136 7, 0xFFFF, sum = 0
4187 19:55:16.520360 8, 0x0, sum = 1
4188 19:55:16.520445 9, 0x0, sum = 2
4189 19:55:16.520511 10, 0x0, sum = 3
4190 19:55:16.523861 11, 0x0, sum = 4
4191 19:55:16.523943 best_step = 9
4192 19:55:16.524007
4193 19:55:16.524066 ==
4194 19:55:16.526970 Dram Type= 6, Freq= 0, CH_0, rank 0
4195 19:55:16.533502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 19:55:16.533584 ==
4197 19:55:16.533648 RX Vref Scan: 1
4198 19:55:16.533708
4199 19:55:16.536877 RX Vref 0 -> 0, step: 1
4200 19:55:16.536957
4201 19:55:16.540213 RX Delay -179 -> 252, step: 8
4202 19:55:16.540293
4203 19:55:16.543412 Set Vref, RX VrefLevel [Byte0]: 58
4204 19:55:16.546786 [Byte1]: 48
4205 19:55:16.546866
4206 19:55:16.550332 Final RX Vref Byte 0 = 58 to rank0
4207 19:55:16.553506 Final RX Vref Byte 1 = 48 to rank0
4208 19:55:16.556516 Final RX Vref Byte 0 = 58 to rank1
4209 19:55:16.559859 Final RX Vref Byte 1 = 48 to rank1==
4210 19:55:16.563568 Dram Type= 6, Freq= 0, CH_0, rank 0
4211 19:55:16.566626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 19:55:16.566707 ==
4213 19:55:16.569849 DQS Delay:
4214 19:55:16.569928 DQS0 = 0, DQS1 = 0
4215 19:55:16.572979 DQM Delay:
4216 19:55:16.573059 DQM0 = 43, DQM1 = 32
4217 19:55:16.573123 DQ Delay:
4218 19:55:16.576379 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =44
4219 19:55:16.579439 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4220 19:55:16.582958 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4221 19:55:16.586179 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4222 19:55:16.586259
4223 19:55:16.589733
4224 19:55:16.595926 [DQSOSCAuto] RK0, (LSB)MR18= 0x6b43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4225 19:55:16.599528 CH0 RK0: MR19=808, MR18=6B43
4226 19:55:16.605783 CH0_RK0: MR19=0x808, MR18=0x6B43, DQSOSC=389, MR23=63, INC=173, DEC=115
4227 19:55:16.605865
4228 19:55:16.609420 ----->DramcWriteLeveling(PI) begin...
4229 19:55:16.609503 ==
4230 19:55:16.612377 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 19:55:16.615370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 19:55:16.615450 ==
4233 19:55:16.619169 Write leveling (Byte 0): 33 => 33
4234 19:55:16.622550 Write leveling (Byte 1): 29 => 29
4235 19:55:16.625665 DramcWriteLeveling(PI) end<-----
4236 19:55:16.625746
4237 19:55:16.625809 ==
4238 19:55:16.629046 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 19:55:16.632047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 19:55:16.634960 ==
4241 19:55:16.635042 [Gating] SW mode calibration
4242 19:55:16.644850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4243 19:55:16.648291 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4244 19:55:16.651487 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 19:55:16.658180 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4246 19:55:16.661850 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4247 19:55:16.664989 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4248 19:55:16.671300 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
4249 19:55:16.674602 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 19:55:16.678267 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 19:55:16.685083 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 19:55:16.688427 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 19:55:16.691457 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 19:55:16.698493 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 19:55:16.701299 0 10 12 | B1->B0 | 2727 2727 | 0 0 | (0 0) (0 0)
4256 19:55:16.705284 0 10 16 | B1->B0 | 3333 4242 | 0 0 | (1 1) (0 0)
4257 19:55:16.711527 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 19:55:16.714201 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 19:55:16.717656 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 19:55:16.724998 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 19:55:16.727787 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 19:55:16.730873 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 19:55:16.737662 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 19:55:16.740791 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 19:55:16.743783 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 19:55:16.750644 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 19:55:16.753572 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 19:55:16.757349 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 19:55:16.764186 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 19:55:16.767204 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 19:55:16.770433 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 19:55:16.777714 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 19:55:16.780338 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 19:55:16.783522 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 19:55:16.790204 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 19:55:16.793386 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 19:55:16.796976 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 19:55:16.803280 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 19:55:16.806473 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4280 19:55:16.810014 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 19:55:16.813473 Total UI for P1: 0, mck2ui 16
4282 19:55:16.816789 best dqsien dly found for B0: ( 0, 13, 12)
4283 19:55:16.819631 Total UI for P1: 0, mck2ui 16
4284 19:55:16.822852 best dqsien dly found for B1: ( 0, 13, 12)
4285 19:55:16.826444 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4286 19:55:16.829479 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4287 19:55:16.832872
4288 19:55:16.836101 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4289 19:55:16.839922 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4290 19:55:16.842695 [Gating] SW calibration Done
4291 19:55:16.842796 ==
4292 19:55:16.845949 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 19:55:16.849388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 19:55:16.849524 ==
4295 19:55:16.849644 RX Vref Scan: 0
4296 19:55:16.853018
4297 19:55:16.853103 RX Vref 0 -> 0, step: 1
4298 19:55:16.853182
4299 19:55:16.856616 RX Delay -230 -> 252, step: 16
4300 19:55:16.859911 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4301 19:55:16.866224 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4302 19:55:16.869926 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4303 19:55:16.872849 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4304 19:55:16.876316 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4305 19:55:16.882579 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4306 19:55:16.886065 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4307 19:55:16.889649 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4308 19:55:16.892604 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4309 19:55:16.895881 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4310 19:55:16.902595 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4311 19:55:16.906170 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4312 19:55:16.909155 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4313 19:55:16.912362 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4314 19:55:16.919035 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4315 19:55:16.922709 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4316 19:55:16.923048 ==
4317 19:55:16.925905 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 19:55:16.929793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 19:55:16.930191 ==
4320 19:55:16.932152 DQS Delay:
4321 19:55:16.932545 DQS0 = 0, DQS1 = 0
4322 19:55:16.932850 DQM Delay:
4323 19:55:16.935384 DQM0 = 42, DQM1 = 36
4324 19:55:16.935948 DQ Delay:
4325 19:55:16.939070 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4326 19:55:16.942033 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4327 19:55:16.945994 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4328 19:55:16.948998 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4329 19:55:16.949521
4330 19:55:16.949851
4331 19:55:16.951914 ==
4332 19:55:16.952326 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 19:55:16.958685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 19:55:16.958766 ==
4335 19:55:16.958829
4336 19:55:16.958902
4337 19:55:16.961491 TX Vref Scan disable
4338 19:55:16.961572 == TX Byte 0 ==
4339 19:55:16.968288 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4340 19:55:16.971943 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4341 19:55:16.972123 == TX Byte 1 ==
4342 19:55:16.979223 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4343 19:55:16.981465 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4344 19:55:16.981653 ==
4345 19:55:16.985213 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 19:55:16.988374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 19:55:16.988590 ==
4348 19:55:16.988712
4349 19:55:16.988816
4350 19:55:16.991762 TX Vref Scan disable
4351 19:55:16.994585 == TX Byte 0 ==
4352 19:55:16.998269 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4353 19:55:17.001328 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4354 19:55:17.005352 == TX Byte 1 ==
4355 19:55:17.008178 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4356 19:55:17.011871 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4357 19:55:17.012279
4358 19:55:17.014738 [DATLAT]
4359 19:55:17.015129 Freq=600, CH0 RK1
4360 19:55:17.015371
4361 19:55:17.018350 DATLAT Default: 0x9
4362 19:55:17.018839 0, 0xFFFF, sum = 0
4363 19:55:17.021545 1, 0xFFFF, sum = 0
4364 19:55:17.022060 2, 0xFFFF, sum = 0
4365 19:55:17.025189 3, 0xFFFF, sum = 0
4366 19:55:17.025714 4, 0xFFFF, sum = 0
4367 19:55:17.028465 5, 0xFFFF, sum = 0
4368 19:55:17.028987 6, 0xFFFF, sum = 0
4369 19:55:17.031907 7, 0xFFFF, sum = 0
4370 19:55:17.032434 8, 0x0, sum = 1
4371 19:55:17.034712 9, 0x0, sum = 2
4372 19:55:17.035228 10, 0x0, sum = 3
4373 19:55:17.038288 11, 0x0, sum = 4
4374 19:55:17.038821 best_step = 9
4375 19:55:17.039153
4376 19:55:17.039458 ==
4377 19:55:17.040911 Dram Type= 6, Freq= 0, CH_0, rank 1
4378 19:55:17.048077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 19:55:17.048597 ==
4380 19:55:17.048928 RX Vref Scan: 0
4381 19:55:17.049234
4382 19:55:17.051318 RX Vref 0 -> 0, step: 1
4383 19:55:17.051874
4384 19:55:17.054826 RX Delay -179 -> 252, step: 8
4385 19:55:17.057825 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4386 19:55:17.064295 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4387 19:55:17.067677 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4388 19:55:17.071178 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4389 19:55:17.074243 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4390 19:55:17.081131 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4391 19:55:17.084775 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4392 19:55:17.087947 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4393 19:55:17.091268 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4394 19:55:17.094412 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4395 19:55:17.100991 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4396 19:55:17.104046 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4397 19:55:17.107495 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4398 19:55:17.111115 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4399 19:55:17.117292 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4400 19:55:17.121181 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4401 19:55:17.121690 ==
4402 19:55:17.124073 Dram Type= 6, Freq= 0, CH_0, rank 1
4403 19:55:17.127327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 19:55:17.127875 ==
4405 19:55:17.130578 DQS Delay:
4406 19:55:17.131078 DQS0 = 0, DQS1 = 0
4407 19:55:17.131412 DQM Delay:
4408 19:55:17.133648 DQM0 = 42, DQM1 = 37
4409 19:55:17.134154 DQ Delay:
4410 19:55:17.136711 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4411 19:55:17.140717 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4412 19:55:17.143600 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4413 19:55:17.147196 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4414 19:55:17.147707
4415 19:55:17.148085
4416 19:55:17.156778 [DQSOSCAuto] RK1, (LSB)MR18= 0x6417, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4417 19:55:17.160404 CH0 RK1: MR19=808, MR18=6417
4418 19:55:17.163373 CH0_RK1: MR19=0x808, MR18=0x6417, DQSOSC=391, MR23=63, INC=171, DEC=114
4419 19:55:17.166652 [RxdqsGatingPostProcess] freq 600
4420 19:55:17.173548 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4421 19:55:17.176904 Pre-setting of DQS Precalculation
4422 19:55:17.180020 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4423 19:55:17.183404 ==
4424 19:55:17.183962 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 19:55:17.190267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 19:55:17.190785 ==
4427 19:55:17.193328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4428 19:55:17.199846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4429 19:55:17.203827 [CA 0] Center 35 (5~66) winsize 62
4430 19:55:17.206328 [CA 1] Center 35 (5~66) winsize 62
4431 19:55:17.210274 [CA 2] Center 34 (4~65) winsize 62
4432 19:55:17.214464 [CA 3] Center 33 (3~64) winsize 62
4433 19:55:17.217099 [CA 4] Center 34 (4~64) winsize 61
4434 19:55:17.219970 [CA 5] Center 33 (3~64) winsize 62
4435 19:55:17.220488
4436 19:55:17.223482 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4437 19:55:17.224119
4438 19:55:17.226849 [CATrainingPosCal] consider 1 rank data
4439 19:55:17.229842 u2DelayCellTimex100 = 270/100 ps
4440 19:55:17.233144 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4441 19:55:17.239759 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4442 19:55:17.243380 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 19:55:17.246589 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 19:55:17.249878 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4445 19:55:17.252754 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4446 19:55:17.253269
4447 19:55:17.256288 CA PerBit enable=1, Macro0, CA PI delay=33
4448 19:55:17.256707
4449 19:55:17.259076 [CBTSetCACLKResult] CA Dly = 33
4450 19:55:17.262749 CS Dly: 3 (0~34)
4451 19:55:17.263165 ==
4452 19:55:17.265984 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 19:55:17.269421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 19:55:17.269924 ==
4455 19:55:17.276160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4456 19:55:17.279227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4457 19:55:17.283860 [CA 0] Center 35 (5~66) winsize 62
4458 19:55:17.287214 [CA 1] Center 36 (6~66) winsize 61
4459 19:55:17.290570 [CA 2] Center 34 (4~65) winsize 62
4460 19:55:17.293796 [CA 3] Center 34 (3~65) winsize 63
4461 19:55:17.296482 [CA 4] Center 34 (4~65) winsize 62
4462 19:55:17.299782 [CA 5] Center 34 (3~65) winsize 63
4463 19:55:17.300273
4464 19:55:17.303092 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4465 19:55:17.303509
4466 19:55:17.306449 [CATrainingPosCal] consider 2 rank data
4467 19:55:17.310291 u2DelayCellTimex100 = 270/100 ps
4468 19:55:17.313159 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4469 19:55:17.320115 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4470 19:55:17.323484 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4471 19:55:17.326514 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4472 19:55:17.329708 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4473 19:55:17.333428 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4474 19:55:17.333943
4475 19:55:17.336676 CA PerBit enable=1, Macro0, CA PI delay=33
4476 19:55:17.337195
4477 19:55:17.339885 [CBTSetCACLKResult] CA Dly = 33
4478 19:55:17.343157 CS Dly: 4 (0~37)
4479 19:55:17.343673
4480 19:55:17.346466 ----->DramcWriteLeveling(PI) begin...
4481 19:55:17.346988 ==
4482 19:55:17.349998 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 19:55:17.353182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 19:55:17.353702 ==
4485 19:55:17.355693 Write leveling (Byte 0): 30 => 30
4486 19:55:17.358994 Write leveling (Byte 1): 31 => 31
4487 19:55:17.362585 DramcWriteLeveling(PI) end<-----
4488 19:55:17.363143
4489 19:55:17.363614 ==
4490 19:55:17.365578 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 19:55:17.369804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 19:55:17.370331 ==
4493 19:55:17.372578 [Gating] SW mode calibration
4494 19:55:17.379238 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4495 19:55:17.385461 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4496 19:55:17.389150 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4497 19:55:17.392664 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4498 19:55:17.399026 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4499 19:55:17.402256 0 9 12 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
4500 19:55:17.405453 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4501 19:55:17.412198 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 19:55:17.415275 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 19:55:17.418825 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 19:55:17.424787 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 19:55:17.428377 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 19:55:17.431776 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4507 19:55:17.438520 0 10 12 | B1->B0 | 2e2e 3434 | 0 0 | (0 0) (0 0)
4508 19:55:17.441603 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 19:55:17.444735 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 19:55:17.451647 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 19:55:17.454660 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 19:55:17.461591 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 19:55:17.464977 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 19:55:17.467848 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 19:55:17.474505 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4516 19:55:17.477779 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 19:55:17.481022 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 19:55:17.487378 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 19:55:17.491149 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 19:55:17.494132 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 19:55:17.500765 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 19:55:17.504156 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 19:55:17.507694 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 19:55:17.514268 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 19:55:17.517159 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 19:55:17.520406 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 19:55:17.527762 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 19:55:17.530595 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 19:55:17.533996 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 19:55:17.540503 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 19:55:17.543596 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4532 19:55:17.547168 Total UI for P1: 0, mck2ui 16
4533 19:55:17.550586 best dqsien dly found for B1: ( 0, 13, 10)
4534 19:55:17.553846 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4535 19:55:17.556969 Total UI for P1: 0, mck2ui 16
4536 19:55:17.560640 best dqsien dly found for B0: ( 0, 13, 12)
4537 19:55:17.563490 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4538 19:55:17.566828 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4539 19:55:17.567333
4540 19:55:17.573918 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4541 19:55:17.576379 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4542 19:55:17.576802 [Gating] SW calibration Done
4543 19:55:17.579641 ==
4544 19:55:17.583060 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 19:55:17.586710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 19:55:17.587224 ==
4547 19:55:17.587559 RX Vref Scan: 0
4548 19:55:17.587959
4549 19:55:17.589475 RX Vref 0 -> 0, step: 1
4550 19:55:17.589943
4551 19:55:17.593340 RX Delay -230 -> 252, step: 16
4552 19:55:17.596574 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4553 19:55:17.599628 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4554 19:55:17.606271 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4555 19:55:17.609876 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4556 19:55:17.613356 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4557 19:55:17.616090 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4558 19:55:17.622881 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4559 19:55:17.626160 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4560 19:55:17.629090 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4561 19:55:17.632918 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4562 19:55:17.639528 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4563 19:55:17.642221 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4564 19:55:17.645955 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4565 19:55:17.649463 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4566 19:55:17.655523 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4567 19:55:17.659241 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4568 19:55:17.659782 ==
4569 19:55:17.661874 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 19:55:17.665227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 19:55:17.665647 ==
4572 19:55:17.668929 DQS Delay:
4573 19:55:17.669345 DQS0 = 0, DQS1 = 0
4574 19:55:17.669873 DQM Delay:
4575 19:55:17.672226 DQM0 = 49, DQM1 = 39
4576 19:55:17.672642 DQ Delay:
4577 19:55:17.675397 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =41
4578 19:55:17.678921 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =49
4579 19:55:17.682227 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4580 19:55:17.685590 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =57
4581 19:55:17.686107
4582 19:55:17.686440
4583 19:55:17.686747 ==
4584 19:55:17.688600 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 19:55:17.695175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 19:55:17.695686 ==
4587 19:55:17.696076
4588 19:55:17.696389
4589 19:55:17.696685 TX Vref Scan disable
4590 19:55:17.699261 == TX Byte 0 ==
4591 19:55:17.701889 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4592 19:55:17.709012 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4593 19:55:17.709528 == TX Byte 1 ==
4594 19:55:17.712118 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4595 19:55:17.718901 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4596 19:55:17.719417 ==
4597 19:55:17.721861 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 19:55:17.725478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 19:55:17.725992 ==
4600 19:55:17.726326
4601 19:55:17.726633
4602 19:55:17.728190 TX Vref Scan disable
4603 19:55:17.731909 == TX Byte 0 ==
4604 19:55:17.735068 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4605 19:55:17.738258 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4606 19:55:17.741533 == TX Byte 1 ==
4607 19:55:17.745535 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4608 19:55:17.748730 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4609 19:55:17.749245
4610 19:55:17.749577 [DATLAT]
4611 19:55:17.751438 Freq=600, CH1 RK0
4612 19:55:17.751978
4613 19:55:17.754602 DATLAT Default: 0x9
4614 19:55:17.755107 0, 0xFFFF, sum = 0
4615 19:55:17.759466 1, 0xFFFF, sum = 0
4616 19:55:17.760050 2, 0xFFFF, sum = 0
4617 19:55:17.761453 3, 0xFFFF, sum = 0
4618 19:55:17.761880 4, 0xFFFF, sum = 0
4619 19:55:17.764491 5, 0xFFFF, sum = 0
4620 19:55:17.764919 6, 0xFFFF, sum = 0
4621 19:55:17.767801 7, 0xFFFF, sum = 0
4622 19:55:17.768224 8, 0x0, sum = 1
4623 19:55:17.771346 9, 0x0, sum = 2
4624 19:55:17.771926 10, 0x0, sum = 3
4625 19:55:17.774336 11, 0x0, sum = 4
4626 19:55:17.774753 best_step = 9
4627 19:55:17.775082
4628 19:55:17.775389 ==
4629 19:55:17.777670 Dram Type= 6, Freq= 0, CH_1, rank 0
4630 19:55:17.780785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 19:55:17.781214 ==
4632 19:55:17.784193 RX Vref Scan: 1
4633 19:55:17.784632
4634 19:55:17.787606 RX Vref 0 -> 0, step: 1
4635 19:55:17.788066
4636 19:55:17.790979 RX Delay -195 -> 252, step: 8
4637 19:55:17.791460
4638 19:55:17.794142 Set Vref, RX VrefLevel [Byte0]: 48
4639 19:55:17.794556 [Byte1]: 58
4640 19:55:17.799451
4641 19:55:17.799904 Final RX Vref Byte 0 = 48 to rank0
4642 19:55:17.802703 Final RX Vref Byte 1 = 58 to rank0
4643 19:55:17.806236 Final RX Vref Byte 0 = 48 to rank1
4644 19:55:17.809231 Final RX Vref Byte 1 = 58 to rank1==
4645 19:55:17.812435 Dram Type= 6, Freq= 0, CH_1, rank 0
4646 19:55:17.819675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 19:55:17.820264 ==
4648 19:55:17.820604 DQS Delay:
4649 19:55:17.820925 DQS0 = 0, DQS1 = 0
4650 19:55:17.822316 DQM Delay:
4651 19:55:17.822796 DQM0 = 49, DQM1 = 38
4652 19:55:17.826128 DQ Delay:
4653 19:55:17.829400 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4654 19:55:17.832636 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4655 19:55:17.836100 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4656 19:55:17.841095 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4657 19:55:17.841515
4658 19:55:17.841843
4659 19:55:17.845738 [DQSOSCAuto] RK0, (LSB)MR18= 0x5035, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4660 19:55:17.848822 CH1 RK0: MR19=808, MR18=5035
4661 19:55:17.855279 CH1_RK0: MR19=0x808, MR18=0x5035, DQSOSC=394, MR23=63, INC=168, DEC=112
4662 19:55:17.855695
4663 19:55:17.858611 ----->DramcWriteLeveling(PI) begin...
4664 19:55:17.859030 ==
4665 19:55:17.861989 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 19:55:17.865422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 19:55:17.865843 ==
4668 19:55:17.869074 Write leveling (Byte 0): 28 => 28
4669 19:55:17.871926 Write leveling (Byte 1): 31 => 31
4670 19:55:17.875144 DramcWriteLeveling(PI) end<-----
4671 19:55:17.875574
4672 19:55:17.876040 ==
4673 19:55:17.878683 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 19:55:17.882067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 19:55:17.884847 ==
4676 19:55:17.885278 [Gating] SW mode calibration
4677 19:55:17.894760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4678 19:55:17.898426 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4679 19:55:17.901409 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4680 19:55:17.907836 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4681 19:55:17.911557 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4682 19:55:17.914974 0 9 12 | B1->B0 | 3131 3232 | 1 1 | (0 0) (1 0)
4683 19:55:17.921315 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4684 19:55:17.924647 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 19:55:17.927940 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 19:55:17.934771 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 19:55:17.938353 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 19:55:17.941328 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 19:55:17.947763 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 19:55:17.951293 0 10 12 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
4691 19:55:17.954837 0 10 16 | B1->B0 | 4444 4242 | 0 1 | (0 0) (0 0)
4692 19:55:17.960872 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 19:55:17.964225 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 19:55:17.967452 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 19:55:17.974528 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 19:55:17.977804 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 19:55:17.981243 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 19:55:17.987347 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4699 19:55:17.991281 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 19:55:17.994087 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 19:55:18.000697 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 19:55:18.003858 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 19:55:18.007089 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 19:55:18.013724 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 19:55:18.017251 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 19:55:18.020319 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 19:55:18.026917 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 19:55:18.030486 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 19:55:18.033700 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 19:55:18.040140 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 19:55:18.043951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 19:55:18.046809 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 19:55:18.053368 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4714 19:55:18.056489 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 19:55:18.060108 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 19:55:18.062926 Total UI for P1: 0, mck2ui 16
4717 19:55:18.066340 best dqsien dly found for B0: ( 0, 13, 14)
4718 19:55:18.070109 Total UI for P1: 0, mck2ui 16
4719 19:55:18.073313 best dqsien dly found for B1: ( 0, 13, 14)
4720 19:55:18.076095 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4721 19:55:18.079868 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4722 19:55:18.080373
4723 19:55:18.086147 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4724 19:55:18.089742 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4725 19:55:18.092956 [Gating] SW calibration Done
4726 19:55:18.093377 ==
4727 19:55:18.096080 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 19:55:18.099506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 19:55:18.100073 ==
4730 19:55:18.100416 RX Vref Scan: 0
4731 19:55:18.102695
4732 19:55:18.103201 RX Vref 0 -> 0, step: 1
4733 19:55:18.103536
4734 19:55:18.106506 RX Delay -230 -> 252, step: 16
4735 19:55:18.109707 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4736 19:55:18.115881 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4737 19:55:18.119450 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4738 19:55:18.122556 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4739 19:55:18.125714 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4740 19:55:18.129563 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4741 19:55:18.135919 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4742 19:55:18.139862 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4743 19:55:18.142368 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4744 19:55:18.145841 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4745 19:55:18.152644 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4746 19:55:18.155574 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4747 19:55:18.158606 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4748 19:55:18.162535 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4749 19:55:18.168644 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4750 19:55:18.171922 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4751 19:55:18.172339 ==
4752 19:55:18.175342 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 19:55:18.178766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 19:55:18.179286 ==
4755 19:55:18.182031 DQS Delay:
4756 19:55:18.182444 DQS0 = 0, DQS1 = 0
4757 19:55:18.182776 DQM Delay:
4758 19:55:18.185576 DQM0 = 44, DQM1 = 37
4759 19:55:18.186120 DQ Delay:
4760 19:55:18.188392 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4761 19:55:18.191798 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4762 19:55:18.195222 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4763 19:55:18.198423 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4764 19:55:18.198951
4765 19:55:18.199281
4766 19:55:18.199588 ==
4767 19:55:18.202424 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 19:55:18.208981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 19:55:18.209502 ==
4770 19:55:18.209836
4771 19:55:18.210143
4772 19:55:18.210435 TX Vref Scan disable
4773 19:55:18.212091 == TX Byte 0 ==
4774 19:55:18.215790 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4775 19:55:18.222189 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4776 19:55:18.222703 == TX Byte 1 ==
4777 19:55:18.225552 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4778 19:55:18.232676 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4779 19:55:18.233191 ==
4780 19:55:18.235347 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 19:55:18.239048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 19:55:18.239566 ==
4783 19:55:18.239944
4784 19:55:18.240252
4785 19:55:18.242056 TX Vref Scan disable
4786 19:55:18.245873 == TX Byte 0 ==
4787 19:55:18.248969 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4788 19:55:18.251967 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4789 19:55:18.255347 == TX Byte 1 ==
4790 19:55:18.258383 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4791 19:55:18.261965 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4792 19:55:18.262381
4793 19:55:18.262737 [DATLAT]
4794 19:55:18.265293 Freq=600, CH1 RK1
4795 19:55:18.265709
4796 19:55:18.268361 DATLAT Default: 0x9
4797 19:55:18.268797 0, 0xFFFF, sum = 0
4798 19:55:18.271601 1, 0xFFFF, sum = 0
4799 19:55:18.272058 2, 0xFFFF, sum = 0
4800 19:55:18.275021 3, 0xFFFF, sum = 0
4801 19:55:18.275545 4, 0xFFFF, sum = 0
4802 19:55:18.278988 5, 0xFFFF, sum = 0
4803 19:55:18.279531 6, 0xFFFF, sum = 0
4804 19:55:18.282051 7, 0xFFFF, sum = 0
4805 19:55:18.282580 8, 0x0, sum = 1
4806 19:55:18.285208 9, 0x0, sum = 2
4807 19:55:18.285765 10, 0x0, sum = 3
4808 19:55:18.288121 11, 0x0, sum = 4
4809 19:55:18.288561 best_step = 9
4810 19:55:18.288910
4811 19:55:18.289364 ==
4812 19:55:18.291524 Dram Type= 6, Freq= 0, CH_1, rank 1
4813 19:55:18.294939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4814 19:55:18.295461 ==
4815 19:55:18.298520 RX Vref Scan: 0
4816 19:55:18.299037
4817 19:55:18.301918 RX Vref 0 -> 0, step: 1
4818 19:55:18.302436
4819 19:55:18.302839 RX Delay -195 -> 252, step: 8
4820 19:55:18.309519 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4821 19:55:18.312707 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4822 19:55:18.315930 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4823 19:55:18.319330 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4824 19:55:18.326189 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4825 19:55:18.329308 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4826 19:55:18.332939 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4827 19:55:18.336171 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4828 19:55:18.339180 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4829 19:55:18.345902 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4830 19:55:18.349021 iDelay=213, Bit 10, Center 40 (-115 ~ 196) 312
4831 19:55:18.352416 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4832 19:55:18.356342 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4833 19:55:18.362220 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4834 19:55:18.365581 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4835 19:55:18.368720 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4836 19:55:18.369181 ==
4837 19:55:18.372057 Dram Type= 6, Freq= 0, CH_1, rank 1
4838 19:55:18.379242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4839 19:55:18.379816 ==
4840 19:55:18.380171 DQS Delay:
4841 19:55:18.380489 DQS0 = 0, DQS1 = 0
4842 19:55:18.381840 DQM Delay:
4843 19:55:18.382255 DQM0 = 45, DQM1 = 37
4844 19:55:18.385085 DQ Delay:
4845 19:55:18.388662 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4846 19:55:18.392119 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4847 19:55:18.392645 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4848 19:55:18.398665 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4849 19:55:18.399188
4850 19:55:18.399634
4851 19:55:18.405344 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
4852 19:55:18.408600 CH1 RK1: MR19=808, MR18=2F24
4853 19:55:18.415313 CH1_RK1: MR19=0x808, MR18=0x2F24, DQSOSC=400, MR23=63, INC=163, DEC=109
4854 19:55:18.418797 [RxdqsGatingPostProcess] freq 600
4855 19:55:18.421923 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4856 19:55:18.425368 Pre-setting of DQS Precalculation
4857 19:55:18.431785 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4858 19:55:18.438737 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4859 19:55:18.445354 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4860 19:55:18.445918
4861 19:55:18.446287
4862 19:55:18.448546 [Calibration Summary] 1200 Mbps
4863 19:55:18.449006 CH 0, Rank 0
4864 19:55:18.451831 SW Impedance : PASS
4865 19:55:18.454723 DUTY Scan : NO K
4866 19:55:18.455140 ZQ Calibration : PASS
4867 19:55:18.458165 Jitter Meter : NO K
4868 19:55:18.461869 CBT Training : PASS
4869 19:55:18.462291 Write leveling : PASS
4870 19:55:18.464241 RX DQS gating : PASS
4871 19:55:18.467889 RX DQ/DQS(RDDQC) : PASS
4872 19:55:18.468548 TX DQ/DQS : PASS
4873 19:55:18.471129 RX DATLAT : PASS
4874 19:55:18.474411 RX DQ/DQS(Engine): PASS
4875 19:55:18.474939 TX OE : NO K
4876 19:55:18.477651 All Pass.
4877 19:55:18.478171
4878 19:55:18.478507 CH 0, Rank 1
4879 19:55:18.480990 SW Impedance : PASS
4880 19:55:18.481411 DUTY Scan : NO K
4881 19:55:18.485001 ZQ Calibration : PASS
4882 19:55:18.487611 Jitter Meter : NO K
4883 19:55:18.488074 CBT Training : PASS
4884 19:55:18.491109 Write leveling : PASS
4885 19:55:18.494440 RX DQS gating : PASS
4886 19:55:18.494961 RX DQ/DQS(RDDQC) : PASS
4887 19:55:18.498117 TX DQ/DQS : PASS
4888 19:55:18.498642 RX DATLAT : PASS
4889 19:55:18.500901 RX DQ/DQS(Engine): PASS
4890 19:55:18.504648 TX OE : NO K
4891 19:55:18.505162 All Pass.
4892 19:55:18.505502
4893 19:55:18.505811 CH 1, Rank 0
4894 19:55:18.507545 SW Impedance : PASS
4895 19:55:18.510835 DUTY Scan : NO K
4896 19:55:18.511348 ZQ Calibration : PASS
4897 19:55:18.514549 Jitter Meter : NO K
4898 19:55:18.517252 CBT Training : PASS
4899 19:55:18.517771 Write leveling : PASS
4900 19:55:18.520675 RX DQS gating : PASS
4901 19:55:18.524185 RX DQ/DQS(RDDQC) : PASS
4902 19:55:18.524703 TX DQ/DQS : PASS
4903 19:55:18.527264 RX DATLAT : PASS
4904 19:55:18.531136 RX DQ/DQS(Engine): PASS
4905 19:55:18.531558 TX OE : NO K
4906 19:55:18.534053 All Pass.
4907 19:55:18.534597
4908 19:55:18.534939 CH 1, Rank 1
4909 19:55:18.537069 SW Impedance : PASS
4910 19:55:18.537592 DUTY Scan : NO K
4911 19:55:18.540577 ZQ Calibration : PASS
4912 19:55:18.543697 Jitter Meter : NO K
4913 19:55:18.544258 CBT Training : PASS
4914 19:55:18.547184 Write leveling : PASS
4915 19:55:18.550564 RX DQS gating : PASS
4916 19:55:18.551080 RX DQ/DQS(RDDQC) : PASS
4917 19:55:18.554108 TX DQ/DQS : PASS
4918 19:55:18.556658 RX DATLAT : PASS
4919 19:55:18.557082 RX DQ/DQS(Engine): PASS
4920 19:55:18.560437 TX OE : NO K
4921 19:55:18.560858 All Pass.
4922 19:55:18.561190
4923 19:55:18.563205 DramC Write-DBI off
4924 19:55:18.566763 PER_BANK_REFRESH: Hybrid Mode
4925 19:55:18.567183 TX_TRACKING: ON
4926 19:55:18.576717 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4927 19:55:18.580025 [FAST_K] Save calibration result to emmc
4928 19:55:18.583318 dramc_set_vcore_voltage set vcore to 662500
4929 19:55:18.586687 Read voltage for 933, 3
4930 19:55:18.587242 Vio18 = 0
4931 19:55:18.587607 Vcore = 662500
4932 19:55:18.589930 Vdram = 0
4933 19:55:18.590340 Vddq = 0
4934 19:55:18.590667 Vmddr = 0
4935 19:55:18.596866 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4936 19:55:18.599958 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4937 19:55:18.602879 MEM_TYPE=3, freq_sel=17
4938 19:55:18.606203 sv_algorithm_assistance_LP4_1600
4939 19:55:18.609476 ============ PULL DRAM RESETB DOWN ============
4940 19:55:18.612848 ========== PULL DRAM RESETB DOWN end =========
4941 19:55:18.619768 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4942 19:55:18.622744 ===================================
4943 19:55:18.626097 LPDDR4 DRAM CONFIGURATION
4944 19:55:18.629133 ===================================
4945 19:55:18.629610 EX_ROW_EN[0] = 0x0
4946 19:55:18.632927 EX_ROW_EN[1] = 0x0
4947 19:55:18.633438 LP4Y_EN = 0x0
4948 19:55:18.635900 WORK_FSP = 0x0
4949 19:55:18.636407 WL = 0x3
4950 19:55:18.639332 RL = 0x3
4951 19:55:18.639777 BL = 0x2
4952 19:55:18.642646 RPST = 0x0
4953 19:55:18.643157 RD_PRE = 0x0
4954 19:55:18.645916 WR_PRE = 0x1
4955 19:55:18.646426 WR_PST = 0x0
4956 19:55:18.649009 DBI_WR = 0x0
4957 19:55:18.653037 DBI_RD = 0x0
4958 19:55:18.653545 OTF = 0x1
4959 19:55:18.655559 ===================================
4960 19:55:18.659142 ===================================
4961 19:55:18.659679 ANA top config
4962 19:55:18.662211 ===================================
4963 19:55:18.665901 DLL_ASYNC_EN = 0
4964 19:55:18.668734 ALL_SLAVE_EN = 1
4965 19:55:18.672205 NEW_RANK_MODE = 1
4966 19:55:18.675969 DLL_IDLE_MODE = 1
4967 19:55:18.676480 LP45_APHY_COMB_EN = 1
4968 19:55:18.679072 TX_ODT_DIS = 1
4969 19:55:18.682616 NEW_8X_MODE = 1
4970 19:55:18.685927 ===================================
4971 19:55:18.689150 ===================================
4972 19:55:18.692927 data_rate = 1866
4973 19:55:18.695334 CKR = 1
4974 19:55:18.695897 DQ_P2S_RATIO = 8
4975 19:55:18.698673 ===================================
4976 19:55:18.702579 CA_P2S_RATIO = 8
4977 19:55:18.705833 DQ_CA_OPEN = 0
4978 19:55:18.708957 DQ_SEMI_OPEN = 0
4979 19:55:18.712112 CA_SEMI_OPEN = 0
4980 19:55:18.715303 CA_FULL_RATE = 0
4981 19:55:18.715752 DQ_CKDIV4_EN = 1
4982 19:55:18.718750 CA_CKDIV4_EN = 1
4983 19:55:18.722759 CA_PREDIV_EN = 0
4984 19:55:18.725138 PH8_DLY = 0
4985 19:55:18.728548 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4986 19:55:18.732172 DQ_AAMCK_DIV = 4
4987 19:55:18.732685 CA_AAMCK_DIV = 4
4988 19:55:18.734953 CA_ADMCK_DIV = 4
4989 19:55:18.738550 DQ_TRACK_CA_EN = 0
4990 19:55:18.742153 CA_PICK = 933
4991 19:55:18.744830 CA_MCKIO = 933
4992 19:55:18.748899 MCKIO_SEMI = 0
4993 19:55:18.751950 PLL_FREQ = 3732
4994 19:55:18.754827 DQ_UI_PI_RATIO = 32
4995 19:55:18.755352 CA_UI_PI_RATIO = 0
4996 19:55:18.757876 ===================================
4997 19:55:18.761042 ===================================
4998 19:55:18.764763 memory_type:LPDDR4
4999 19:55:18.768143 GP_NUM : 10
5000 19:55:18.768768 SRAM_EN : 1
5001 19:55:18.770916 MD32_EN : 0
5002 19:55:18.774579 ===================================
5003 19:55:18.778091 [ANA_INIT] >>>>>>>>>>>>>>
5004 19:55:18.780940 <<<<<< [CONFIGURE PHASE]: ANA_TX
5005 19:55:18.784273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5006 19:55:18.787564 ===================================
5007 19:55:18.788143 data_rate = 1866,PCW = 0X8f00
5008 19:55:18.791237 ===================================
5009 19:55:18.794359 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5010 19:55:18.800913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5011 19:55:18.807611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5012 19:55:18.811374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5013 19:55:18.814761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5014 19:55:18.817263 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5015 19:55:18.820670 [ANA_INIT] flow start
5016 19:55:18.823976 [ANA_INIT] PLL >>>>>>>>
5017 19:55:18.824487 [ANA_INIT] PLL <<<<<<<<
5018 19:55:18.827275 [ANA_INIT] MIDPI >>>>>>>>
5019 19:55:18.830710 [ANA_INIT] MIDPI <<<<<<<<
5020 19:55:18.831226 [ANA_INIT] DLL >>>>>>>>
5021 19:55:18.834046 [ANA_INIT] flow end
5022 19:55:18.837027 ============ LP4 DIFF to SE enter ============
5023 19:55:18.843776 ============ LP4 DIFF to SE exit ============
5024 19:55:18.844287 [ANA_INIT] <<<<<<<<<<<<<
5025 19:55:18.846873 [Flow] Enable top DCM control >>>>>
5026 19:55:18.850177 [Flow] Enable top DCM control <<<<<
5027 19:55:18.853846 Enable DLL master slave shuffle
5028 19:55:18.860135 ==============================================================
5029 19:55:18.860670 Gating Mode config
5030 19:55:18.866490 ==============================================================
5031 19:55:18.870375 Config description:
5032 19:55:18.879636 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5033 19:55:18.886723 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5034 19:55:18.889774 SELPH_MODE 0: By rank 1: By Phase
5035 19:55:18.896599 ==============================================================
5036 19:55:18.899639 GAT_TRACK_EN = 1
5037 19:55:18.900244 RX_GATING_MODE = 2
5038 19:55:18.903075 RX_GATING_TRACK_MODE = 2
5039 19:55:18.906422 SELPH_MODE = 1
5040 19:55:18.909463 PICG_EARLY_EN = 1
5041 19:55:18.913000 VALID_LAT_VALUE = 1
5042 19:55:18.919871 ==============================================================
5043 19:55:18.922836 Enter into Gating configuration >>>>
5044 19:55:18.926580 Exit from Gating configuration <<<<
5045 19:55:18.929292 Enter into DVFS_PRE_config >>>>>
5046 19:55:18.938875 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5047 19:55:18.942487 Exit from DVFS_PRE_config <<<<<
5048 19:55:18.945367 Enter into PICG configuration >>>>
5049 19:55:18.948782 Exit from PICG configuration <<<<
5050 19:55:18.951920 [RX_INPUT] configuration >>>>>
5051 19:55:18.955766 [RX_INPUT] configuration <<<<<
5052 19:55:18.958598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5053 19:55:18.965234 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5054 19:55:18.972087 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5055 19:55:18.978515 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5056 19:55:18.985436 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5057 19:55:18.988621 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5058 19:55:18.995141 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5059 19:55:18.998395 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5060 19:55:19.001987 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5061 19:55:19.005239 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5062 19:55:19.011923 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5063 19:55:19.015017 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5064 19:55:19.018001 ===================================
5065 19:55:19.021573 LPDDR4 DRAM CONFIGURATION
5066 19:55:19.024642 ===================================
5067 19:55:19.025054 EX_ROW_EN[0] = 0x0
5068 19:55:19.028544 EX_ROW_EN[1] = 0x0
5069 19:55:19.028952 LP4Y_EN = 0x0
5070 19:55:19.031656 WORK_FSP = 0x0
5071 19:55:19.032213 WL = 0x3
5072 19:55:19.034806 RL = 0x3
5073 19:55:19.035316 BL = 0x2
5074 19:55:19.038149 RPST = 0x0
5075 19:55:19.038663 RD_PRE = 0x0
5076 19:55:19.041419 WR_PRE = 0x1
5077 19:55:19.045102 WR_PST = 0x0
5078 19:55:19.045613 DBI_WR = 0x0
5079 19:55:19.048439 DBI_RD = 0x0
5080 19:55:19.048964 OTF = 0x1
5081 19:55:19.051292 ===================================
5082 19:55:19.054903 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5083 19:55:19.060982 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5084 19:55:19.064274 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5085 19:55:19.067654 ===================================
5086 19:55:19.071449 LPDDR4 DRAM CONFIGURATION
5087 19:55:19.074371 ===================================
5088 19:55:19.074790 EX_ROW_EN[0] = 0x10
5089 19:55:19.077762 EX_ROW_EN[1] = 0x0
5090 19:55:19.078177 LP4Y_EN = 0x0
5091 19:55:19.081170 WORK_FSP = 0x0
5092 19:55:19.081587 WL = 0x3
5093 19:55:19.084393 RL = 0x3
5094 19:55:19.084807 BL = 0x2
5095 19:55:19.088004 RPST = 0x0
5096 19:55:19.090883 RD_PRE = 0x0
5097 19:55:19.091334 WR_PRE = 0x1
5098 19:55:19.093813 WR_PST = 0x0
5099 19:55:19.094533 DBI_WR = 0x0
5100 19:55:19.097723 DBI_RD = 0x0
5101 19:55:19.098230 OTF = 0x1
5102 19:55:19.100550 ===================================
5103 19:55:19.107130 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5104 19:55:19.111066 nWR fixed to 30
5105 19:55:19.114232 [ModeRegInit_LP4] CH0 RK0
5106 19:55:19.114652 [ModeRegInit_LP4] CH0 RK1
5107 19:55:19.117599 [ModeRegInit_LP4] CH1 RK0
5108 19:55:19.121122 [ModeRegInit_LP4] CH1 RK1
5109 19:55:19.121834 match AC timing 9
5110 19:55:19.127937 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5111 19:55:19.131041 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5112 19:55:19.134742 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5113 19:55:19.140940 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5114 19:55:19.143899 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5115 19:55:19.144322 ==
5116 19:55:19.147520 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 19:55:19.150505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 19:55:19.150922 ==
5119 19:55:19.156977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5120 19:55:19.164147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5121 19:55:19.166862 [CA 0] Center 37 (7~68) winsize 62
5122 19:55:19.170569 [CA 1] Center 37 (7~68) winsize 62
5123 19:55:19.173757 [CA 2] Center 34 (4~65) winsize 62
5124 19:55:19.176941 [CA 3] Center 34 (4~65) winsize 62
5125 19:55:19.180291 [CA 4] Center 33 (3~64) winsize 62
5126 19:55:19.183425 [CA 5] Center 33 (3~63) winsize 61
5127 19:55:19.183970
5128 19:55:19.187081 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5129 19:55:19.187592
5130 19:55:19.189869 [CATrainingPosCal] consider 1 rank data
5131 19:55:19.193710 u2DelayCellTimex100 = 270/100 ps
5132 19:55:19.196542 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5133 19:55:19.200301 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5134 19:55:19.203637 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5135 19:55:19.209978 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5136 19:55:19.213056 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5137 19:55:19.216895 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5138 19:55:19.217465
5139 19:55:19.219645 CA PerBit enable=1, Macro0, CA PI delay=33
5140 19:55:19.220142
5141 19:55:19.223016 [CBTSetCACLKResult] CA Dly = 33
5142 19:55:19.223427 CS Dly: 7 (0~38)
5143 19:55:19.223794 ==
5144 19:55:19.226286 Dram Type= 6, Freq= 0, CH_0, rank 1
5145 19:55:19.233748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 19:55:19.234260 ==
5147 19:55:19.236221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5148 19:55:19.242842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5149 19:55:19.246701 [CA 0] Center 37 (7~68) winsize 62
5150 19:55:19.249795 [CA 1] Center 37 (7~68) winsize 62
5151 19:55:19.252714 [CA 2] Center 34 (4~65) winsize 62
5152 19:55:19.255958 [CA 3] Center 35 (5~65) winsize 61
5153 19:55:19.259608 [CA 4] Center 33 (3~64) winsize 62
5154 19:55:19.262387 [CA 5] Center 33 (3~63) winsize 61
5155 19:55:19.262929
5156 19:55:19.266210 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5157 19:55:19.266751
5158 19:55:19.269147 [CATrainingPosCal] consider 2 rank data
5159 19:55:19.272654 u2DelayCellTimex100 = 270/100 ps
5160 19:55:19.276272 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5161 19:55:19.282516 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5162 19:55:19.285944 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5163 19:55:19.289654 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5164 19:55:19.292421 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5165 19:55:19.296275 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5166 19:55:19.296785
5167 19:55:19.299134 CA PerBit enable=1, Macro0, CA PI delay=33
5168 19:55:19.299640
5169 19:55:19.302528 [CBTSetCACLKResult] CA Dly = 33
5170 19:55:19.306421 CS Dly: 7 (0~39)
5171 19:55:19.306935
5172 19:55:19.308656 ----->DramcWriteLeveling(PI) begin...
5173 19:55:19.309082 ==
5174 19:55:19.312737 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 19:55:19.315899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 19:55:19.316410 ==
5177 19:55:19.318915 Write leveling (Byte 0): 35 => 35
5178 19:55:19.322396 Write leveling (Byte 1): 29 => 29
5179 19:55:19.325542 DramcWriteLeveling(PI) end<-----
5180 19:55:19.326052
5181 19:55:19.326383 ==
5182 19:55:19.328565 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 19:55:19.332200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 19:55:19.332711 ==
5185 19:55:19.335324 [Gating] SW mode calibration
5186 19:55:19.342411 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5187 19:55:19.348498 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5188 19:55:19.351822 0 14 0 | B1->B0 | 2322 3030 | 1 0 | (0 0) (0 0)
5189 19:55:19.355255 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5190 19:55:19.361686 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 19:55:19.364930 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 19:55:19.368540 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 19:55:19.374913 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 19:55:19.378353 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 19:55:19.381357 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
5196 19:55:19.388061 0 15 0 | B1->B0 | 3131 2424 | 0 0 | (0 0) (1 0)
5197 19:55:19.391561 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5198 19:55:19.394800 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 19:55:19.401832 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 19:55:19.404836 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 19:55:19.407852 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 19:55:19.414298 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 19:55:19.417983 0 15 28 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
5204 19:55:19.420942 1 0 0 | B1->B0 | 3131 4141 | 0 0 | (1 1) (0 0)
5205 19:55:19.427699 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 19:55:19.430514 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 19:55:19.434463 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 19:55:19.440753 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 19:55:19.443861 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 19:55:19.447289 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 19:55:19.454057 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5212 19:55:19.457400 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5213 19:55:19.460285 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 19:55:19.466890 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 19:55:19.470521 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 19:55:19.473705 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 19:55:19.480058 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 19:55:19.483916 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 19:55:19.487041 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 19:55:19.494090 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 19:55:19.496721 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 19:55:19.500051 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 19:55:19.506842 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 19:55:19.510112 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 19:55:19.513406 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 19:55:19.520128 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 19:55:19.523528 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5228 19:55:19.526533 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5229 19:55:19.533479 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5230 19:55:19.536086 Total UI for P1: 0, mck2ui 16
5231 19:55:19.539641 best dqsien dly found for B0: ( 1, 2, 30)
5232 19:55:19.543077 Total UI for P1: 0, mck2ui 16
5233 19:55:19.546370 best dqsien dly found for B1: ( 1, 3, 0)
5234 19:55:19.549226 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5235 19:55:19.552815 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5236 19:55:19.553366
5237 19:55:19.556171 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5238 19:55:19.559178 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5239 19:55:19.562448 [Gating] SW calibration Done
5240 19:55:19.563086 ==
5241 19:55:19.565767 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 19:55:19.569094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 19:55:19.569556 ==
5244 19:55:19.573066 RX Vref Scan: 0
5245 19:55:19.573523
5246 19:55:19.575767 RX Vref 0 -> 0, step: 1
5247 19:55:19.576227
5248 19:55:19.576591 RX Delay -80 -> 252, step: 8
5249 19:55:19.582613 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5250 19:55:19.585791 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5251 19:55:19.588797 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5252 19:55:19.592656 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5253 19:55:19.596643 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5254 19:55:19.599375 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5255 19:55:19.605514 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5256 19:55:19.608656 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5257 19:55:19.612662 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5258 19:55:19.615980 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5259 19:55:19.619012 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5260 19:55:19.625725 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5261 19:55:19.628691 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5262 19:55:19.632241 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5263 19:55:19.635416 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5264 19:55:19.638851 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5265 19:55:19.642083 ==
5266 19:55:19.645228 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 19:55:19.648288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 19:55:19.648846 ==
5269 19:55:19.649214 DQS Delay:
5270 19:55:19.651640 DQS0 = 0, DQS1 = 0
5271 19:55:19.652233 DQM Delay:
5272 19:55:19.655133 DQM0 = 96, DQM1 = 85
5273 19:55:19.655679 DQ Delay:
5274 19:55:19.658537 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5275 19:55:19.661666 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5276 19:55:19.664890 DQ8 =79, DQ9 =79, DQ10 =83, DQ11 =79
5277 19:55:19.667950 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5278 19:55:19.668508
5279 19:55:19.668873
5280 19:55:19.669215 ==
5281 19:55:19.671245 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 19:55:19.674487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 19:55:19.674952 ==
5284 19:55:19.675315
5285 19:55:19.677917
5286 19:55:19.678460 TX Vref Scan disable
5287 19:55:19.680993 == TX Byte 0 ==
5288 19:55:19.684440 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5289 19:55:19.687921 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5290 19:55:19.691226 == TX Byte 1 ==
5291 19:55:19.695404 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5292 19:55:19.697805 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5293 19:55:19.698246 ==
5294 19:55:19.701654 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 19:55:19.708273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 19:55:19.708787 ==
5297 19:55:19.709122
5298 19:55:19.709427
5299 19:55:19.710896 TX Vref Scan disable
5300 19:55:19.711307 == TX Byte 0 ==
5301 19:55:19.717839 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5302 19:55:19.721111 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5303 19:55:19.721623 == TX Byte 1 ==
5304 19:55:19.727631 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5305 19:55:19.731040 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5306 19:55:19.731546
5307 19:55:19.731916 [DATLAT]
5308 19:55:19.734702 Freq=933, CH0 RK0
5309 19:55:19.735210
5310 19:55:19.735539 DATLAT Default: 0xd
5311 19:55:19.737792 0, 0xFFFF, sum = 0
5312 19:55:19.738309 1, 0xFFFF, sum = 0
5313 19:55:19.740498 2, 0xFFFF, sum = 0
5314 19:55:19.740929 3, 0xFFFF, sum = 0
5315 19:55:19.744561 4, 0xFFFF, sum = 0
5316 19:55:19.745074 5, 0xFFFF, sum = 0
5317 19:55:19.747497 6, 0xFFFF, sum = 0
5318 19:55:19.750741 7, 0xFFFF, sum = 0
5319 19:55:19.751257 8, 0xFFFF, sum = 0
5320 19:55:19.754308 9, 0xFFFF, sum = 0
5321 19:55:19.754825 10, 0x0, sum = 1
5322 19:55:19.755163 11, 0x0, sum = 2
5323 19:55:19.757212 12, 0x0, sum = 3
5324 19:55:19.757631 13, 0x0, sum = 4
5325 19:55:19.760265 best_step = 11
5326 19:55:19.760676
5327 19:55:19.761000 ==
5328 19:55:19.763782 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 19:55:19.767160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 19:55:19.767572 ==
5331 19:55:19.769958 RX Vref Scan: 1
5332 19:55:19.770365
5333 19:55:19.770685 RX Vref 0 -> 0, step: 1
5334 19:55:19.773231
5335 19:55:19.773637 RX Delay -61 -> 252, step: 4
5336 19:55:19.773961
5337 19:55:19.776641 Set Vref, RX VrefLevel [Byte0]: 58
5338 19:55:19.779809 [Byte1]: 48
5339 19:55:19.784541
5340 19:55:19.784950 Final RX Vref Byte 0 = 58 to rank0
5341 19:55:19.787819 Final RX Vref Byte 1 = 48 to rank0
5342 19:55:19.790997 Final RX Vref Byte 0 = 58 to rank1
5343 19:55:19.794510 Final RX Vref Byte 1 = 48 to rank1==
5344 19:55:19.797435 Dram Type= 6, Freq= 0, CH_0, rank 0
5345 19:55:19.805141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 19:55:19.805652 ==
5347 19:55:19.805984 DQS Delay:
5348 19:55:19.807543 DQS0 = 0, DQS1 = 0
5349 19:55:19.808014 DQM Delay:
5350 19:55:19.808427 DQM0 = 97, DQM1 = 85
5351 19:55:19.810747 DQ Delay:
5352 19:55:19.814312 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5353 19:55:19.817589 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =106
5354 19:55:19.820704 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =80
5355 19:55:19.824314 DQ12 =88, DQ13 =88, DQ14 =98, DQ15 =92
5356 19:55:19.824726
5357 19:55:19.825048
5358 19:55:19.831017 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5359 19:55:19.834394 CH0 RK0: MR19=505, MR18=2D14
5360 19:55:19.840986 CH0_RK0: MR19=0x505, MR18=0x2D14, DQSOSC=407, MR23=63, INC=65, DEC=43
5361 19:55:19.841496
5362 19:55:19.844125 ----->DramcWriteLeveling(PI) begin...
5363 19:55:19.844633 ==
5364 19:55:19.847433 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 19:55:19.850118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 19:55:19.850534 ==
5367 19:55:19.853695 Write leveling (Byte 0): 32 => 32
5368 19:55:19.856953 Write leveling (Byte 1): 30 => 30
5369 19:55:19.860584 DramcWriteLeveling(PI) end<-----
5370 19:55:19.861090
5371 19:55:19.861470 ==
5372 19:55:19.863569 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 19:55:19.870304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 19:55:19.870811 ==
5375 19:55:19.871141 [Gating] SW mode calibration
5376 19:55:19.880307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5377 19:55:19.883460 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5378 19:55:19.886814 0 14 0 | B1->B0 | 2c2b 3333 | 1 1 | (1 1) (1 1)
5379 19:55:19.893670 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 19:55:19.897001 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 19:55:19.899766 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 19:55:19.906832 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 19:55:19.910082 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 19:55:19.913645 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5385 19:55:19.919956 0 14 28 | B1->B0 | 3232 2f2f | 0 1 | (0 1) (1 1)
5386 19:55:19.923210 0 15 0 | B1->B0 | 2f2f 2c2c | 1 1 | (1 0) (1 0)
5387 19:55:19.926400 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 19:55:19.933050 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 19:55:19.936717 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 19:55:19.939541 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 19:55:19.946310 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 19:55:19.949744 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 19:55:19.953064 0 15 28 | B1->B0 | 2828 3535 | 0 0 | (0 0) (0 0)
5394 19:55:19.959698 1 0 0 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
5395 19:55:19.962810 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 19:55:19.965554 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 19:55:19.972358 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 19:55:19.975651 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 19:55:19.979324 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 19:55:19.985546 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 19:55:19.988614 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 19:55:19.992177 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 19:55:19.999115 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 19:55:20.002457 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 19:55:20.005338 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 19:55:20.012862 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 19:55:20.015489 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 19:55:20.018994 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 19:55:20.025018 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 19:55:20.028385 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 19:55:20.031669 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 19:55:20.039242 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 19:55:20.042158 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 19:55:20.045071 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 19:55:20.051719 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 19:55:20.054895 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 19:55:20.058461 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5418 19:55:20.065202 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 19:55:20.068421 Total UI for P1: 0, mck2ui 16
5420 19:55:20.071835 best dqsien dly found for B0: ( 1, 2, 28)
5421 19:55:20.072255 Total UI for P1: 0, mck2ui 16
5422 19:55:20.078239 best dqsien dly found for B1: ( 1, 2, 28)
5423 19:55:20.081465 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5424 19:55:20.085290 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5425 19:55:20.085804
5426 19:55:20.088302 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5427 19:55:20.091327 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5428 19:55:20.094470 [Gating] SW calibration Done
5429 19:55:20.094883 ==
5430 19:55:20.097876 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 19:55:20.100925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 19:55:20.101342 ==
5433 19:55:20.104185 RX Vref Scan: 0
5434 19:55:20.104791
5435 19:55:20.105128 RX Vref 0 -> 0, step: 1
5436 19:55:20.107838
5437 19:55:20.108252 RX Delay -80 -> 252, step: 8
5438 19:55:20.114414 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5439 19:55:20.118101 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5440 19:55:20.121257 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5441 19:55:20.124222 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5442 19:55:20.129069 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5443 19:55:20.130704 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5444 19:55:20.137537 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5445 19:55:20.140736 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5446 19:55:20.145416 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5447 19:55:20.147825 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5448 19:55:20.150923 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5449 19:55:20.157635 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5450 19:55:20.161126 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5451 19:55:20.163908 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5452 19:55:20.166983 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5453 19:55:20.170240 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5454 19:55:20.170835 ==
5455 19:55:20.173742 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 19:55:20.180330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 19:55:20.180752 ==
5458 19:55:20.181087 DQS Delay:
5459 19:55:20.183647 DQS0 = 0, DQS1 = 0
5460 19:55:20.184113 DQM Delay:
5461 19:55:20.184450 DQM0 = 96, DQM1 = 88
5462 19:55:20.187087 DQ Delay:
5463 19:55:20.190475 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5464 19:55:20.193228 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5465 19:55:20.196992 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5466 19:55:20.200475 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5467 19:55:20.200985
5468 19:55:20.201319
5469 19:55:20.201626 ==
5470 19:55:20.203699 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 19:55:20.207194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 19:55:20.207800 ==
5473 19:55:20.208203
5474 19:55:20.208544
5475 19:55:20.210454 TX Vref Scan disable
5476 19:55:20.213488 == TX Byte 0 ==
5477 19:55:20.216800 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5478 19:55:20.220031 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5479 19:55:20.223501 == TX Byte 1 ==
5480 19:55:20.226671 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5481 19:55:20.230166 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5482 19:55:20.230719 ==
5483 19:55:20.234093 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 19:55:20.236821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 19:55:20.240155 ==
5486 19:55:20.240701
5487 19:55:20.241064
5488 19:55:20.241399 TX Vref Scan disable
5489 19:55:20.243872 == TX Byte 0 ==
5490 19:55:20.247283 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5491 19:55:20.253615 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5492 19:55:20.254171 == TX Byte 1 ==
5493 19:55:20.256953 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5494 19:55:20.263382 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5495 19:55:20.263899
5496 19:55:20.264271 [DATLAT]
5497 19:55:20.264626 Freq=933, CH0 RK1
5498 19:55:20.264956
5499 19:55:20.266638 DATLAT Default: 0xb
5500 19:55:20.267095 0, 0xFFFF, sum = 0
5501 19:55:20.269925 1, 0xFFFF, sum = 0
5502 19:55:20.270389 2, 0xFFFF, sum = 0
5503 19:55:20.273245 3, 0xFFFF, sum = 0
5504 19:55:20.277049 4, 0xFFFF, sum = 0
5505 19:55:20.277679 5, 0xFFFF, sum = 0
5506 19:55:20.279827 6, 0xFFFF, sum = 0
5507 19:55:20.280292 7, 0xFFFF, sum = 0
5508 19:55:20.283028 8, 0xFFFF, sum = 0
5509 19:55:20.283490 9, 0xFFFF, sum = 0
5510 19:55:20.286935 10, 0x0, sum = 1
5511 19:55:20.287492 11, 0x0, sum = 2
5512 19:55:20.289911 12, 0x0, sum = 3
5513 19:55:20.290468 13, 0x0, sum = 4
5514 19:55:20.290861 best_step = 11
5515 19:55:20.291202
5516 19:55:20.293182 ==
5517 19:55:20.296534 Dram Type= 6, Freq= 0, CH_0, rank 1
5518 19:55:20.300033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 19:55:20.300607 ==
5520 19:55:20.300972 RX Vref Scan: 0
5521 19:55:20.301315
5522 19:55:20.302950 RX Vref 0 -> 0, step: 1
5523 19:55:20.303405
5524 19:55:20.307453 RX Delay -61 -> 252, step: 4
5525 19:55:20.312962 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5526 19:55:20.316576 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5527 19:55:20.319618 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5528 19:55:20.323298 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5529 19:55:20.326034 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5530 19:55:20.329709 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5531 19:55:20.336323 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5532 19:55:20.339157 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5533 19:55:20.342678 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5534 19:55:20.346041 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5535 19:55:20.349084 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5536 19:55:20.356100 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5537 19:55:20.359295 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5538 19:55:20.362367 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5539 19:55:20.365566 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5540 19:55:20.368844 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5541 19:55:20.372458 ==
5542 19:55:20.375388 Dram Type= 6, Freq= 0, CH_0, rank 1
5543 19:55:20.378478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 19:55:20.378966 ==
5545 19:55:20.379332 DQS Delay:
5546 19:55:20.381905 DQS0 = 0, DQS1 = 0
5547 19:55:20.382363 DQM Delay:
5548 19:55:20.385180 DQM0 = 95, DQM1 = 85
5549 19:55:20.385635 DQ Delay:
5550 19:55:20.388919 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5551 19:55:20.391485 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5552 19:55:20.395242 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5553 19:55:20.398093 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5554 19:55:20.398503
5555 19:55:20.398829
5556 19:55:20.405563 [DQSOSCAuto] RK1, (LSB)MR18= 0x28f8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5557 19:55:20.408046 CH0 RK1: MR19=504, MR18=28F8
5558 19:55:20.415524 CH0_RK1: MR19=0x504, MR18=0x28F8, DQSOSC=409, MR23=63, INC=64, DEC=43
5559 19:55:20.418284 [RxdqsGatingPostProcess] freq 933
5560 19:55:20.424677 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5561 19:55:20.428411 best DQS0 dly(2T, 0.5T) = (0, 10)
5562 19:55:20.431522 best DQS1 dly(2T, 0.5T) = (0, 11)
5563 19:55:20.435122 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5564 19:55:20.435635 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5565 19:55:20.437910 best DQS0 dly(2T, 0.5T) = (0, 10)
5566 19:55:20.441195 best DQS1 dly(2T, 0.5T) = (0, 10)
5567 19:55:20.444874 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5568 19:55:20.447989 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5569 19:55:20.451120 Pre-setting of DQS Precalculation
5570 19:55:20.457728 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5571 19:55:20.458237 ==
5572 19:55:20.461333 Dram Type= 6, Freq= 0, CH_1, rank 0
5573 19:55:20.464204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 19:55:20.464717 ==
5575 19:55:20.471270 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5576 19:55:20.477684 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5577 19:55:20.480623 [CA 0] Center 36 (6~67) winsize 62
5578 19:55:20.484195 [CA 1] Center 37 (6~68) winsize 63
5579 19:55:20.487859 [CA 2] Center 34 (4~65) winsize 62
5580 19:55:20.490606 [CA 3] Center 33 (3~64) winsize 62
5581 19:55:20.493893 [CA 4] Center 34 (4~64) winsize 61
5582 19:55:20.497491 [CA 5] Center 33 (3~64) winsize 62
5583 19:55:20.498001
5584 19:55:20.500805 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5585 19:55:20.501221
5586 19:55:20.504194 [CATrainingPosCal] consider 1 rank data
5587 19:55:20.507490 u2DelayCellTimex100 = 270/100 ps
5588 19:55:20.510341 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5589 19:55:20.514367 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5590 19:55:20.517950 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5591 19:55:20.521016 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5592 19:55:20.524187 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5593 19:55:20.527658 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5594 19:55:20.528219
5595 19:55:20.530685 CA PerBit enable=1, Macro0, CA PI delay=33
5596 19:55:20.533973
5597 19:55:20.534488 [CBTSetCACLKResult] CA Dly = 33
5598 19:55:20.537499 CS Dly: 6 (0~37)
5599 19:55:20.538005 ==
5600 19:55:20.540358 Dram Type= 6, Freq= 0, CH_1, rank 1
5601 19:55:20.543862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 19:55:20.544382 ==
5603 19:55:20.550374 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5604 19:55:20.556963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5605 19:55:20.560201 [CA 0] Center 36 (6~67) winsize 62
5606 19:55:20.563676 [CA 1] Center 37 (7~67) winsize 61
5607 19:55:20.566694 [CA 2] Center 34 (4~65) winsize 62
5608 19:55:20.569811 [CA 3] Center 33 (3~64) winsize 62
5609 19:55:20.573406 [CA 4] Center 34 (3~65) winsize 63
5610 19:55:20.576880 [CA 5] Center 33 (3~64) winsize 62
5611 19:55:20.577391
5612 19:55:20.580022 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5613 19:55:20.580438
5614 19:55:20.583550 [CATrainingPosCal] consider 2 rank data
5615 19:55:20.587024 u2DelayCellTimex100 = 270/100 ps
5616 19:55:20.590146 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5617 19:55:20.593210 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5618 19:55:20.596403 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5619 19:55:20.599701 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5620 19:55:20.603229 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5621 19:55:20.609629 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5622 19:55:20.610134
5623 19:55:20.613422 CA PerBit enable=1, Macro0, CA PI delay=33
5624 19:55:20.613939
5625 19:55:20.616155 [CBTSetCACLKResult] CA Dly = 33
5626 19:55:20.616660 CS Dly: 7 (0~39)
5627 19:55:20.616998
5628 19:55:20.620146 ----->DramcWriteLeveling(PI) begin...
5629 19:55:20.620654 ==
5630 19:55:20.623065 Dram Type= 6, Freq= 0, CH_1, rank 0
5631 19:55:20.629565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 19:55:20.630074 ==
5633 19:55:20.633098 Write leveling (Byte 0): 27 => 27
5634 19:55:20.633605 Write leveling (Byte 1): 28 => 28
5635 19:55:20.636302 DramcWriteLeveling(PI) end<-----
5636 19:55:20.636808
5637 19:55:20.637144 ==
5638 19:55:20.639357 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 19:55:20.646029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 19:55:20.646539 ==
5641 19:55:20.649625 [Gating] SW mode calibration
5642 19:55:20.655969 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5643 19:55:20.659538 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5644 19:55:20.665635 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5645 19:55:20.668804 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 19:55:20.672211 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 19:55:20.679077 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 19:55:20.682144 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 19:55:20.685468 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 19:55:20.692299 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5651 19:55:20.695653 0 14 28 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (0 0)
5652 19:55:20.698862 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 19:55:20.705283 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 19:55:20.708876 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 19:55:20.712097 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 19:55:20.718849 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 19:55:20.722037 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 19:55:20.725042 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5659 19:55:20.732282 0 15 28 | B1->B0 | 3939 3a3a | 0 0 | (0 0) (0 0)
5660 19:55:20.735412 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 19:55:20.738518 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 19:55:20.745473 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 19:55:20.748593 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 19:55:20.751676 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 19:55:20.758383 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5666 19:55:20.761950 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5667 19:55:20.764415 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5668 19:55:20.771366 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 19:55:20.774671 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 19:55:20.777191 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 19:55:20.784061 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 19:55:20.787149 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 19:55:20.790466 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 19:55:20.797279 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 19:55:20.800261 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 19:55:20.803744 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 19:55:20.810816 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 19:55:20.813655 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 19:55:20.816565 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 19:55:20.823336 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 19:55:20.826546 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 19:55:20.829797 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5683 19:55:20.836687 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5684 19:55:20.839826 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5685 19:55:20.843222 Total UI for P1: 0, mck2ui 16
5686 19:55:20.846984 best dqsien dly found for B0: ( 1, 2, 26)
5687 19:55:20.850253 Total UI for P1: 0, mck2ui 16
5688 19:55:20.853221 best dqsien dly found for B1: ( 1, 2, 28)
5689 19:55:20.856244 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5690 19:55:20.860266 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5691 19:55:20.860772
5692 19:55:20.862867 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5693 19:55:20.869991 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5694 19:55:20.870498 [Gating] SW calibration Done
5695 19:55:20.870888 ==
5696 19:55:20.872881 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 19:55:20.879622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 19:55:20.880107 ==
5699 19:55:20.880675 RX Vref Scan: 0
5700 19:55:20.881057
5701 19:55:20.882490 RX Vref 0 -> 0, step: 1
5702 19:55:20.883071
5703 19:55:20.886156 RX Delay -80 -> 252, step: 8
5704 19:55:20.889863 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5705 19:55:20.892669 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5706 19:55:20.896264 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5707 19:55:20.899140 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5708 19:55:20.906535 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5709 19:55:20.909278 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5710 19:55:20.912708 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5711 19:55:20.916341 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5712 19:55:20.919453 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5713 19:55:20.925781 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5714 19:55:20.929396 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5715 19:55:20.932472 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5716 19:55:20.936217 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5717 19:55:20.939443 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5718 19:55:20.942714 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5719 19:55:20.949726 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5720 19:55:20.950267 ==
5721 19:55:20.952426 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 19:55:20.955797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 19:55:20.956345 ==
5724 19:55:20.956714 DQS Delay:
5725 19:55:20.958947 DQS0 = 0, DQS1 = 0
5726 19:55:20.959489 DQM Delay:
5727 19:55:20.962270 DQM0 = 100, DQM1 = 91
5728 19:55:20.962726 DQ Delay:
5729 19:55:20.965336 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =95
5730 19:55:20.968810 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5731 19:55:20.972327 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =83
5732 19:55:20.975958 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5733 19:55:20.976501
5734 19:55:20.976864
5735 19:55:20.977198 ==
5736 19:55:20.979005 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 19:55:20.981872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 19:55:20.985451 ==
5739 19:55:20.985994
5740 19:55:20.986361
5741 19:55:20.986700 TX Vref Scan disable
5742 19:55:20.988861 == TX Byte 0 ==
5743 19:55:20.991919 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5744 19:55:20.995561 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5745 19:55:20.998761 == TX Byte 1 ==
5746 19:55:21.002095 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5747 19:55:21.005737 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5748 19:55:21.008834 ==
5749 19:55:21.012302 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 19:55:21.015038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 19:55:21.015589 ==
5752 19:55:21.016001
5753 19:55:21.016335
5754 19:55:21.018675 TX Vref Scan disable
5755 19:55:21.019233 == TX Byte 0 ==
5756 19:55:21.025167 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5757 19:55:21.028262 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5758 19:55:21.028817 == TX Byte 1 ==
5759 19:55:21.034737 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5760 19:55:21.038314 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5761 19:55:21.038874
5762 19:55:21.039240 [DATLAT]
5763 19:55:21.041769 Freq=933, CH1 RK0
5764 19:55:21.042357
5765 19:55:21.042732 DATLAT Default: 0xd
5766 19:55:21.044446 0, 0xFFFF, sum = 0
5767 19:55:21.044913 1, 0xFFFF, sum = 0
5768 19:55:21.048117 2, 0xFFFF, sum = 0
5769 19:55:21.051456 3, 0xFFFF, sum = 0
5770 19:55:21.052062 4, 0xFFFF, sum = 0
5771 19:55:21.054606 5, 0xFFFF, sum = 0
5772 19:55:21.055153 6, 0xFFFF, sum = 0
5773 19:55:21.057820 7, 0xFFFF, sum = 0
5774 19:55:21.058413 8, 0xFFFF, sum = 0
5775 19:55:21.061359 9, 0xFFFF, sum = 0
5776 19:55:21.061824 10, 0x0, sum = 1
5777 19:55:21.064292 11, 0x0, sum = 2
5778 19:55:21.064757 12, 0x0, sum = 3
5779 19:55:21.067526 13, 0x0, sum = 4
5780 19:55:21.068033 best_step = 11
5781 19:55:21.068400
5782 19:55:21.068735 ==
5783 19:55:21.070879 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 19:55:21.074586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 19:55:21.075050 ==
5786 19:55:21.077923 RX Vref Scan: 1
5787 19:55:21.078470
5788 19:55:21.080883 RX Vref 0 -> 0, step: 1
5789 19:55:21.081357
5790 19:55:21.081722 RX Delay -61 -> 252, step: 4
5791 19:55:21.082065
5792 19:55:21.084710 Set Vref, RX VrefLevel [Byte0]: 48
5793 19:55:21.087992 [Byte1]: 58
5794 19:55:21.092508
5795 19:55:21.093056 Final RX Vref Byte 0 = 48 to rank0
5796 19:55:21.095679 Final RX Vref Byte 1 = 58 to rank0
5797 19:55:21.099213 Final RX Vref Byte 0 = 48 to rank1
5798 19:55:21.102667 Final RX Vref Byte 1 = 58 to rank1==
5799 19:55:21.105526 Dram Type= 6, Freq= 0, CH_1, rank 0
5800 19:55:21.112879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 19:55:21.113416 ==
5802 19:55:21.113786 DQS Delay:
5803 19:55:21.115079 DQS0 = 0, DQS1 = 0
5804 19:55:21.115533 DQM Delay:
5805 19:55:21.115925 DQM0 = 100, DQM1 = 93
5806 19:55:21.118739 DQ Delay:
5807 19:55:21.122167 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5808 19:55:21.125362 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5809 19:55:21.128795 DQ8 =82, DQ9 =86, DQ10 =92, DQ11 =84
5810 19:55:21.131885 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5811 19:55:21.132435
5812 19:55:21.132800
5813 19:55:21.138576 [DQSOSCAuto] RK0, (LSB)MR18= 0x2010, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 411 ps
5814 19:55:21.141710 CH1 RK0: MR19=505, MR18=2010
5815 19:55:21.148673 CH1_RK0: MR19=0x505, MR18=0x2010, DQSOSC=411, MR23=63, INC=64, DEC=42
5816 19:55:21.149235
5817 19:55:21.151871 ----->DramcWriteLeveling(PI) begin...
5818 19:55:21.152442 ==
5819 19:55:21.155773 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 19:55:21.158465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 19:55:21.161313 ==
5822 19:55:21.161796 Write leveling (Byte 0): 25 => 25
5823 19:55:21.164717 Write leveling (Byte 1): 31 => 31
5824 19:55:21.168078 DramcWriteLeveling(PI) end<-----
5825 19:55:21.168622
5826 19:55:21.168986 ==
5827 19:55:21.171862 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 19:55:21.179088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 19:55:21.179638 ==
5830 19:55:21.181340 [Gating] SW mode calibration
5831 19:55:21.188422 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5832 19:55:21.191547 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5833 19:55:21.197824 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
5834 19:55:21.200722 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 19:55:21.204437 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 19:55:21.211028 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 19:55:21.213997 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 19:55:21.217195 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 19:55:21.224241 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5840 19:55:21.227159 0 14 28 | B1->B0 | 2828 2c2c | 0 0 | (0 0) (1 0)
5841 19:55:21.231447 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 19:55:21.237426 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 19:55:21.241236 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 19:55:21.243719 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 19:55:21.250614 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 19:55:21.254058 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 19:55:21.257614 0 15 24 | B1->B0 | 2c2c 2525 | 1 0 | (1 1) (0 0)
5848 19:55:21.263657 0 15 28 | B1->B0 | 3a3a 2e2e | 0 1 | (0 0) (0 0)
5849 19:55:21.267528 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5850 19:55:21.270953 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 19:55:21.277162 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 19:55:21.280097 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 19:55:21.283389 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 19:55:21.289977 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 19:55:21.293439 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 19:55:21.296810 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5857 19:55:21.303263 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 19:55:21.306399 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 19:55:21.310047 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 19:55:21.316377 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 19:55:21.319715 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 19:55:21.323119 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 19:55:21.330158 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 19:55:21.333193 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 19:55:21.336384 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 19:55:21.342952 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 19:55:21.346760 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 19:55:21.350040 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 19:55:21.356441 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 19:55:21.359325 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 19:55:21.362671 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5872 19:55:21.369843 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5873 19:55:21.372373 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5874 19:55:21.375861 Total UI for P1: 0, mck2ui 16
5875 19:55:21.379306 best dqsien dly found for B1: ( 1, 2, 26)
5876 19:55:21.382912 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5877 19:55:21.385619 Total UI for P1: 0, mck2ui 16
5878 19:55:21.389099 best dqsien dly found for B0: ( 1, 2, 30)
5879 19:55:21.392501 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5880 19:55:21.395434 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5881 19:55:21.396138
5882 19:55:21.402165 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5883 19:55:21.405723 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5884 19:55:21.406290 [Gating] SW calibration Done
5885 19:55:21.409513 ==
5886 19:55:21.412637 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 19:55:21.415339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 19:55:21.415950 ==
5889 19:55:21.416327 RX Vref Scan: 0
5890 19:55:21.416669
5891 19:55:21.418752 RX Vref 0 -> 0, step: 1
5892 19:55:21.419315
5893 19:55:21.421933 RX Delay -80 -> 252, step: 8
5894 19:55:21.425394 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5895 19:55:21.428308 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5896 19:55:21.432404 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5897 19:55:21.438755 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5898 19:55:21.442526 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5899 19:55:21.445136 iDelay=208, Bit 5, Center 103 (8 ~ 199) 192
5900 19:55:21.448426 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5901 19:55:21.451393 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5902 19:55:21.455240 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5903 19:55:21.461220 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5904 19:55:21.465020 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5905 19:55:21.468356 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5906 19:55:21.471369 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5907 19:55:21.475010 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5908 19:55:21.481786 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5909 19:55:21.485115 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5910 19:55:21.485579 ==
5911 19:55:21.487544 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 19:55:21.491781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 19:55:21.492245 ==
5914 19:55:21.494351 DQS Delay:
5915 19:55:21.494809 DQS0 = 0, DQS1 = 0
5916 19:55:21.495173 DQM Delay:
5917 19:55:21.497474 DQM0 = 99, DQM1 = 92
5918 19:55:21.497934 DQ Delay:
5919 19:55:21.501391 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5920 19:55:21.504243 DQ4 =95, DQ5 =103, DQ6 =111, DQ7 =99
5921 19:55:21.507779 DQ8 =75, DQ9 =83, DQ10 =95, DQ11 =83
5922 19:55:21.511576 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5923 19:55:21.512173
5924 19:55:21.512513
5925 19:55:21.513981 ==
5926 19:55:21.517642 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 19:55:21.520495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 19:55:21.520915 ==
5929 19:55:21.521249
5930 19:55:21.521559
5931 19:55:21.524096 TX Vref Scan disable
5932 19:55:21.524512 == TX Byte 0 ==
5933 19:55:21.530647 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5934 19:55:21.534706 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5935 19:55:21.535231 == TX Byte 1 ==
5936 19:55:21.540332 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5937 19:55:21.543713 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5938 19:55:21.544260 ==
5939 19:55:21.547137 Dram Type= 6, Freq= 0, CH_1, rank 1
5940 19:55:21.550471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 19:55:21.550996 ==
5942 19:55:21.551331
5943 19:55:21.551641
5944 19:55:21.553841 TX Vref Scan disable
5945 19:55:21.556987 == TX Byte 0 ==
5946 19:55:21.560470 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5947 19:55:21.563315 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5948 19:55:21.567181 == TX Byte 1 ==
5949 19:55:21.570109 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5950 19:55:21.573141 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5951 19:55:21.573668
5952 19:55:21.577550 [DATLAT]
5953 19:55:21.578063 Freq=933, CH1 RK1
5954 19:55:21.578399
5955 19:55:21.580098 DATLAT Default: 0xb
5956 19:55:21.580513 0, 0xFFFF, sum = 0
5957 19:55:21.583886 1, 0xFFFF, sum = 0
5958 19:55:21.584468 2, 0xFFFF, sum = 0
5959 19:55:21.587124 3, 0xFFFF, sum = 0
5960 19:55:21.587688 4, 0xFFFF, sum = 0
5961 19:55:21.589650 5, 0xFFFF, sum = 0
5962 19:55:21.590116 6, 0xFFFF, sum = 0
5963 19:55:21.593420 7, 0xFFFF, sum = 0
5964 19:55:21.596509 8, 0xFFFF, sum = 0
5965 19:55:21.597016 9, 0xFFFF, sum = 0
5966 19:55:21.600373 10, 0x0, sum = 1
5967 19:55:21.600943 11, 0x0, sum = 2
5968 19:55:21.601330 12, 0x0, sum = 3
5969 19:55:21.603779 13, 0x0, sum = 4
5970 19:55:21.604244 best_step = 11
5971 19:55:21.604609
5972 19:55:21.604947 ==
5973 19:55:21.606242 Dram Type= 6, Freq= 0, CH_1, rank 1
5974 19:55:21.612938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5975 19:55:21.613512 ==
5976 19:55:21.613989 RX Vref Scan: 0
5977 19:55:21.614391
5978 19:55:21.616224 RX Vref 0 -> 0, step: 1
5979 19:55:21.616685
5980 19:55:21.619649 RX Delay -69 -> 252, step: 4
5981 19:55:21.623470 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5982 19:55:21.629323 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5983 19:55:21.633160 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5984 19:55:21.636291 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5985 19:55:21.639422 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5986 19:55:21.642835 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5987 19:55:21.646792 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5988 19:55:21.652396 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5989 19:55:21.655893 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5990 19:55:21.659613 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5991 19:55:21.662584 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5992 19:55:21.665918 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5993 19:55:21.672521 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5994 19:55:21.676127 iDelay=207, Bit 13, Center 104 (15 ~ 194) 180
5995 19:55:21.678843 iDelay=207, Bit 14, Center 100 (7 ~ 194) 188
5996 19:55:21.682438 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
5997 19:55:21.683002 ==
5998 19:55:21.685363 Dram Type= 6, Freq= 0, CH_1, rank 1
5999 19:55:21.692065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6000 19:55:21.692531 ==
6001 19:55:21.692900 DQS Delay:
6002 19:55:21.693242 DQS0 = 0, DQS1 = 0
6003 19:55:21.695716 DQM Delay:
6004 19:55:21.696217 DQM0 = 101, DQM1 = 94
6005 19:55:21.698694 DQ Delay:
6006 19:55:21.702645 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
6007 19:55:21.706366 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =98
6008 19:55:21.709112 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
6009 19:55:21.712512 DQ12 =104, DQ13 =104, DQ14 =100, DQ15 =104
6010 19:55:21.713155
6011 19:55:21.713533
6012 19:55:21.718874 [DQSOSCAuto] RK1, (LSB)MR18= 0x902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6013 19:55:21.722020 CH1 RK1: MR19=505, MR18=902
6014 19:55:21.728625 CH1_RK1: MR19=0x505, MR18=0x902, DQSOSC=419, MR23=63, INC=61, DEC=41
6015 19:55:21.731771 [RxdqsGatingPostProcess] freq 933
6016 19:55:21.738648 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6017 19:55:21.739406 best DQS0 dly(2T, 0.5T) = (0, 10)
6018 19:55:21.742565 best DQS1 dly(2T, 0.5T) = (0, 10)
6019 19:55:21.744909 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6020 19:55:21.748283 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6021 19:55:21.751308 best DQS0 dly(2T, 0.5T) = (0, 10)
6022 19:55:21.754819 best DQS1 dly(2T, 0.5T) = (0, 10)
6023 19:55:21.758227 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6024 19:55:21.761543 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6025 19:55:21.764411 Pre-setting of DQS Precalculation
6026 19:55:21.771072 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6027 19:55:21.778224 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6028 19:55:21.784491 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6029 19:55:21.785052
6030 19:55:21.785422
6031 19:55:21.787897 [Calibration Summary] 1866 Mbps
6032 19:55:21.788463 CH 0, Rank 0
6033 19:55:21.790933 SW Impedance : PASS
6034 19:55:21.794510 DUTY Scan : NO K
6035 19:55:21.795065 ZQ Calibration : PASS
6036 19:55:21.797239 Jitter Meter : NO K
6037 19:55:21.801000 CBT Training : PASS
6038 19:55:21.801464 Write leveling : PASS
6039 19:55:21.804472 RX DQS gating : PASS
6040 19:55:21.807771 RX DQ/DQS(RDDQC) : PASS
6041 19:55:21.808359 TX DQ/DQS : PASS
6042 19:55:21.811072 RX DATLAT : PASS
6043 19:55:21.814126 RX DQ/DQS(Engine): PASS
6044 19:55:21.814682 TX OE : NO K
6045 19:55:21.815055 All Pass.
6046 19:55:21.815397
6047 19:55:21.817617 CH 0, Rank 1
6048 19:55:21.821652 SW Impedance : PASS
6049 19:55:21.822207 DUTY Scan : NO K
6050 19:55:21.824146 ZQ Calibration : PASS
6051 19:55:21.824606 Jitter Meter : NO K
6052 19:55:21.827460 CBT Training : PASS
6053 19:55:21.830867 Write leveling : PASS
6054 19:55:21.831324 RX DQS gating : PASS
6055 19:55:21.834644 RX DQ/DQS(RDDQC) : PASS
6056 19:55:21.837936 TX DQ/DQS : PASS
6057 19:55:21.838493 RX DATLAT : PASS
6058 19:55:21.841030 RX DQ/DQS(Engine): PASS
6059 19:55:21.844813 TX OE : NO K
6060 19:55:21.845368 All Pass.
6061 19:55:21.845734
6062 19:55:21.846073 CH 1, Rank 0
6063 19:55:21.847500 SW Impedance : PASS
6064 19:55:21.850512 DUTY Scan : NO K
6065 19:55:21.851170 ZQ Calibration : PASS
6066 19:55:21.853763 Jitter Meter : NO K
6067 19:55:21.857101 CBT Training : PASS
6068 19:55:21.857649 Write leveling : PASS
6069 19:55:21.860437 RX DQS gating : PASS
6070 19:55:21.863339 RX DQ/DQS(RDDQC) : PASS
6071 19:55:21.863877 TX DQ/DQS : PASS
6072 19:55:21.867383 RX DATLAT : PASS
6073 19:55:21.870166 RX DQ/DQS(Engine): PASS
6074 19:55:21.870682 TX OE : NO K
6075 19:55:21.873647 All Pass.
6076 19:55:21.874107
6077 19:55:21.874471 CH 1, Rank 1
6078 19:55:21.876918 SW Impedance : PASS
6079 19:55:21.877379 DUTY Scan : NO K
6080 19:55:21.880340 ZQ Calibration : PASS
6081 19:55:21.883368 Jitter Meter : NO K
6082 19:55:21.883978 CBT Training : PASS
6083 19:55:21.887392 Write leveling : PASS
6084 19:55:21.890237 RX DQS gating : PASS
6085 19:55:21.890785 RX DQ/DQS(RDDQC) : PASS
6086 19:55:21.893007 TX DQ/DQS : PASS
6087 19:55:21.896757 RX DATLAT : PASS
6088 19:55:21.897335 RX DQ/DQS(Engine): PASS
6089 19:55:21.899810 TX OE : NO K
6090 19:55:21.900364 All Pass.
6091 19:55:21.900730
6092 19:55:21.902917 DramC Write-DBI off
6093 19:55:21.906446 PER_BANK_REFRESH: Hybrid Mode
6094 19:55:21.907064 TX_TRACKING: ON
6095 19:55:21.916194 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6096 19:55:21.919480 [FAST_K] Save calibration result to emmc
6097 19:55:21.922609 dramc_set_vcore_voltage set vcore to 650000
6098 19:55:21.926301 Read voltage for 400, 6
6099 19:55:21.926850 Vio18 = 0
6100 19:55:21.927201 Vcore = 650000
6101 19:55:21.928916 Vdram = 0
6102 19:55:21.929442 Vddq = 0
6103 19:55:21.929856 Vmddr = 0
6104 19:55:21.935951 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6105 19:55:21.939054 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6106 19:55:21.942741 MEM_TYPE=3, freq_sel=20
6107 19:55:21.945919 sv_algorithm_assistance_LP4_800
6108 19:55:21.948879 ============ PULL DRAM RESETB DOWN ============
6109 19:55:21.952457 ========== PULL DRAM RESETB DOWN end =========
6110 19:55:21.959897 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6111 19:55:21.962349 ===================================
6112 19:55:21.962770 LPDDR4 DRAM CONFIGURATION
6113 19:55:21.965676 ===================================
6114 19:55:21.968629 EX_ROW_EN[0] = 0x0
6115 19:55:21.971785 EX_ROW_EN[1] = 0x0
6116 19:55:21.972214 LP4Y_EN = 0x0
6117 19:55:21.975273 WORK_FSP = 0x0
6118 19:55:21.975875 WL = 0x2
6119 19:55:21.978699 RL = 0x2
6120 19:55:21.979288 BL = 0x2
6121 19:55:21.982086 RPST = 0x0
6122 19:55:21.982628 RD_PRE = 0x0
6123 19:55:21.985279 WR_PRE = 0x1
6124 19:55:21.985835 WR_PST = 0x0
6125 19:55:21.988699 DBI_WR = 0x0
6126 19:55:21.989118 DBI_RD = 0x0
6127 19:55:21.991696 OTF = 0x1
6128 19:55:21.995117 ===================================
6129 19:55:21.998284 ===================================
6130 19:55:21.998758 ANA top config
6131 19:55:22.002170 ===================================
6132 19:55:22.005026 DLL_ASYNC_EN = 0
6133 19:55:22.008520 ALL_SLAVE_EN = 1
6134 19:55:22.011964 NEW_RANK_MODE = 1
6135 19:55:22.012519 DLL_IDLE_MODE = 1
6136 19:55:22.015126 LP45_APHY_COMB_EN = 1
6137 19:55:22.018541 TX_ODT_DIS = 1
6138 19:55:22.021768 NEW_8X_MODE = 1
6139 19:55:22.024780 ===================================
6140 19:55:22.027989 ===================================
6141 19:55:22.031182 data_rate = 800
6142 19:55:22.034529 CKR = 1
6143 19:55:22.035077 DQ_P2S_RATIO = 4
6144 19:55:22.038547 ===================================
6145 19:55:22.041439 CA_P2S_RATIO = 4
6146 19:55:22.044591 DQ_CA_OPEN = 0
6147 19:55:22.047835 DQ_SEMI_OPEN = 1
6148 19:55:22.051464 CA_SEMI_OPEN = 1
6149 19:55:22.054531 CA_FULL_RATE = 0
6150 19:55:22.054946 DQ_CKDIV4_EN = 0
6151 19:55:22.057738 CA_CKDIV4_EN = 1
6152 19:55:22.061105 CA_PREDIV_EN = 0
6153 19:55:22.064138 PH8_DLY = 0
6154 19:55:22.068054 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6155 19:55:22.070645 DQ_AAMCK_DIV = 0
6156 19:55:22.071058 CA_AAMCK_DIV = 0
6157 19:55:22.074035 CA_ADMCK_DIV = 4
6158 19:55:22.077534 DQ_TRACK_CA_EN = 0
6159 19:55:22.080729 CA_PICK = 800
6160 19:55:22.084265 CA_MCKIO = 400
6161 19:55:22.087584 MCKIO_SEMI = 400
6162 19:55:22.091141 PLL_FREQ = 3016
6163 19:55:22.093982 DQ_UI_PI_RATIO = 32
6164 19:55:22.094398 CA_UI_PI_RATIO = 32
6165 19:55:22.097504 ===================================
6166 19:55:22.100350 ===================================
6167 19:55:22.104164 memory_type:LPDDR4
6168 19:55:22.107876 GP_NUM : 10
6169 19:55:22.108386 SRAM_EN : 1
6170 19:55:22.110973 MD32_EN : 0
6171 19:55:22.113686 ===================================
6172 19:55:22.116734 [ANA_INIT] >>>>>>>>>>>>>>
6173 19:55:22.120016 <<<<<< [CONFIGURE PHASE]: ANA_TX
6174 19:55:22.123560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6175 19:55:22.126878 ===================================
6176 19:55:22.127293 data_rate = 800,PCW = 0X7400
6177 19:55:22.130013 ===================================
6178 19:55:22.136985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6179 19:55:22.140454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6180 19:55:22.153943 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6181 19:55:22.157137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6182 19:55:22.160274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6183 19:55:22.163664 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6184 19:55:22.168062 [ANA_INIT] flow start
6185 19:55:22.168609 [ANA_INIT] PLL >>>>>>>>
6186 19:55:22.170018 [ANA_INIT] PLL <<<<<<<<
6187 19:55:22.173333 [ANA_INIT] MIDPI >>>>>>>>
6188 19:55:22.176597 [ANA_INIT] MIDPI <<<<<<<<
6189 19:55:22.177057 [ANA_INIT] DLL >>>>>>>>
6190 19:55:22.180200 [ANA_INIT] flow end
6191 19:55:22.183256 ============ LP4 DIFF to SE enter ============
6192 19:55:22.186784 ============ LP4 DIFF to SE exit ============
6193 19:55:22.190168 [ANA_INIT] <<<<<<<<<<<<<
6194 19:55:22.193353 [Flow] Enable top DCM control >>>>>
6195 19:55:22.196933 [Flow] Enable top DCM control <<<<<
6196 19:55:22.199761 Enable DLL master slave shuffle
6197 19:55:22.206662 ==============================================================
6198 19:55:22.207221 Gating Mode config
6199 19:55:22.213576 ==============================================================
6200 19:55:22.214129 Config description:
6201 19:55:22.223029 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6202 19:55:22.229714 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6203 19:55:22.236071 SELPH_MODE 0: By rank 1: By Phase
6204 19:55:22.239609 ==============================================================
6205 19:55:22.242896 GAT_TRACK_EN = 0
6206 19:55:22.246091 RX_GATING_MODE = 2
6207 19:55:22.249546 RX_GATING_TRACK_MODE = 2
6208 19:55:22.253099 SELPH_MODE = 1
6209 19:55:22.256159 PICG_EARLY_EN = 1
6210 19:55:22.259101 VALID_LAT_VALUE = 1
6211 19:55:22.265638 ==============================================================
6212 19:55:22.268919 Enter into Gating configuration >>>>
6213 19:55:22.272487 Exit from Gating configuration <<<<
6214 19:55:22.272947 Enter into DVFS_PRE_config >>>>>
6215 19:55:22.285845 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6216 19:55:22.289081 Exit from DVFS_PRE_config <<<<<
6217 19:55:22.292261 Enter into PICG configuration >>>>
6218 19:55:22.295475 Exit from PICG configuration <<<<
6219 19:55:22.295934 [RX_INPUT] configuration >>>>>
6220 19:55:22.299272 [RX_INPUT] configuration <<<<<
6221 19:55:22.305623 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6222 19:55:22.311976 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6223 19:55:22.316121 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6224 19:55:22.322090 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6225 19:55:22.328818 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6226 19:55:22.335574 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6227 19:55:22.338526 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6228 19:55:22.341859 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6229 19:55:22.348361 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6230 19:55:22.351318 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6231 19:55:22.354611 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6232 19:55:22.361490 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6233 19:55:22.364680 ===================================
6234 19:55:22.365098 LPDDR4 DRAM CONFIGURATION
6235 19:55:22.368015 ===================================
6236 19:55:22.371114 EX_ROW_EN[0] = 0x0
6237 19:55:22.374915 EX_ROW_EN[1] = 0x0
6238 19:55:22.375334 LP4Y_EN = 0x0
6239 19:55:22.378085 WORK_FSP = 0x0
6240 19:55:22.378499 WL = 0x2
6241 19:55:22.381467 RL = 0x2
6242 19:55:22.381878 BL = 0x2
6243 19:55:22.384225 RPST = 0x0
6244 19:55:22.384308 RD_PRE = 0x0
6245 19:55:22.387278 WR_PRE = 0x1
6246 19:55:22.387360 WR_PST = 0x0
6247 19:55:22.390994 DBI_WR = 0x0
6248 19:55:22.391078 DBI_RD = 0x0
6249 19:55:22.393902 OTF = 0x1
6250 19:55:22.397740 ===================================
6251 19:55:22.400451 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6252 19:55:22.403926 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6253 19:55:22.410758 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6254 19:55:22.414129 ===================================
6255 19:55:22.414211 LPDDR4 DRAM CONFIGURATION
6256 19:55:22.417322 ===================================
6257 19:55:22.420396 EX_ROW_EN[0] = 0x10
6258 19:55:22.423622 EX_ROW_EN[1] = 0x0
6259 19:55:22.423704 LP4Y_EN = 0x0
6260 19:55:22.427188 WORK_FSP = 0x0
6261 19:55:22.427270 WL = 0x2
6262 19:55:22.430677 RL = 0x2
6263 19:55:22.430760 BL = 0x2
6264 19:55:22.433982 RPST = 0x0
6265 19:55:22.434070 RD_PRE = 0x0
6266 19:55:22.436996 WR_PRE = 0x1
6267 19:55:22.437091 WR_PST = 0x0
6268 19:55:22.440430 DBI_WR = 0x0
6269 19:55:22.440525 DBI_RD = 0x0
6270 19:55:22.443640 OTF = 0x1
6271 19:55:22.447179 ===================================
6272 19:55:22.453708 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6273 19:55:22.456978 nWR fixed to 30
6274 19:55:22.457117 [ModeRegInit_LP4] CH0 RK0
6275 19:55:22.460608 [ModeRegInit_LP4] CH0 RK1
6276 19:55:22.464261 [ModeRegInit_LP4] CH1 RK0
6277 19:55:22.467027 [ModeRegInit_LP4] CH1 RK1
6278 19:55:22.467250 match AC timing 19
6279 19:55:22.473586 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6280 19:55:22.477260 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6281 19:55:22.480412 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6282 19:55:22.487234 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6283 19:55:22.490650 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6284 19:55:22.491071 ==
6285 19:55:22.493596 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 19:55:22.497333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 19:55:22.497750 ==
6288 19:55:22.503543 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6289 19:55:22.509940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6290 19:55:22.513186 [CA 0] Center 36 (8~64) winsize 57
6291 19:55:22.516314 [CA 1] Center 36 (8~64) winsize 57
6292 19:55:22.516877 [CA 2] Center 36 (8~64) winsize 57
6293 19:55:22.519750 [CA 3] Center 36 (8~64) winsize 57
6294 19:55:22.523543 [CA 4] Center 36 (8~64) winsize 57
6295 19:55:22.526371 [CA 5] Center 36 (8~64) winsize 57
6296 19:55:22.526784
6297 19:55:22.533373 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6298 19:55:22.533877
6299 19:55:22.536655 [CATrainingPosCal] consider 1 rank data
6300 19:55:22.539536 u2DelayCellTimex100 = 270/100 ps
6301 19:55:22.542738 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 19:55:22.546452 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 19:55:22.549966 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 19:55:22.552850 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 19:55:22.556250 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 19:55:22.559858 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 19:55:22.560408
6308 19:55:22.563009 CA PerBit enable=1, Macro0, CA PI delay=36
6309 19:55:22.563555
6310 19:55:22.566127 [CBTSetCACLKResult] CA Dly = 36
6311 19:55:22.569280 CS Dly: 1 (0~32)
6312 19:55:22.569734 ==
6313 19:55:22.572843 Dram Type= 6, Freq= 0, CH_0, rank 1
6314 19:55:22.576348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 19:55:22.576812 ==
6316 19:55:22.582835 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6317 19:55:22.589294 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6318 19:55:22.592093 [CA 0] Center 36 (8~64) winsize 57
6319 19:55:22.592572 [CA 1] Center 36 (8~64) winsize 57
6320 19:55:22.595481 [CA 2] Center 36 (8~64) winsize 57
6321 19:55:22.598674 [CA 3] Center 36 (8~64) winsize 57
6322 19:55:22.602628 [CA 4] Center 36 (8~64) winsize 57
6323 19:55:22.605474 [CA 5] Center 36 (8~64) winsize 57
6324 19:55:22.605946
6325 19:55:22.608968 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6326 19:55:22.609397
6327 19:55:22.615308 [CATrainingPosCal] consider 2 rank data
6328 19:55:22.615783 u2DelayCellTimex100 = 270/100 ps
6329 19:55:22.621835 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 19:55:22.625284 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 19:55:22.628820 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 19:55:22.631900 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 19:55:22.635591 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 19:55:22.638621 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 19:55:22.638989
6336 19:55:22.641669 CA PerBit enable=1, Macro0, CA PI delay=36
6337 19:55:22.641983
6338 19:55:22.644943 [CBTSetCACLKResult] CA Dly = 36
6339 19:55:22.648653 CS Dly: 1 (0~32)
6340 19:55:22.648871
6341 19:55:22.651322 ----->DramcWriteLeveling(PI) begin...
6342 19:55:22.651542 ==
6343 19:55:22.654968 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 19:55:22.658732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 19:55:22.659040 ==
6346 19:55:22.661563 Write leveling (Byte 0): 40 => 8
6347 19:55:22.665217 Write leveling (Byte 1): 32 => 0
6348 19:55:22.668392 DramcWriteLeveling(PI) end<-----
6349 19:55:22.668610
6350 19:55:22.668785 ==
6351 19:55:22.671251 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 19:55:22.674473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 19:55:22.674763 ==
6354 19:55:22.678072 [Gating] SW mode calibration
6355 19:55:22.684557 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6356 19:55:22.690892 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6357 19:55:22.694103 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6358 19:55:22.697651 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6359 19:55:22.704213 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6360 19:55:22.707714 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 19:55:22.711376 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 19:55:22.717992 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 19:55:22.721517 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 19:55:22.725034 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6365 19:55:22.731830 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6366 19:55:22.734130 Total UI for P1: 0, mck2ui 16
6367 19:55:22.737824 best dqsien dly found for B0: ( 0, 14, 24)
6368 19:55:22.740734 Total UI for P1: 0, mck2ui 16
6369 19:55:22.744035 best dqsien dly found for B1: ( 0, 14, 24)
6370 19:55:22.747477 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6371 19:55:22.750809 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6372 19:55:22.751358
6373 19:55:22.754202 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6374 19:55:22.758030 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6375 19:55:22.760638 [Gating] SW calibration Done
6376 19:55:22.761095 ==
6377 19:55:22.764371 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 19:55:22.767355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 19:55:22.767968 ==
6380 19:55:22.770843 RX Vref Scan: 0
6381 19:55:22.771392
6382 19:55:22.773824 RX Vref 0 -> 0, step: 1
6383 19:55:22.774279
6384 19:55:22.774636 RX Delay -410 -> 252, step: 16
6385 19:55:22.780676 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6386 19:55:22.784119 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6387 19:55:22.787324 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6388 19:55:22.793620 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6389 19:55:22.796887 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6390 19:55:22.800543 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6391 19:55:22.804061 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6392 19:55:22.810801 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6393 19:55:22.813634 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6394 19:55:22.816864 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6395 19:55:22.820134 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6396 19:55:22.826792 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6397 19:55:22.829934 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6398 19:55:22.833579 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6399 19:55:22.836823 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6400 19:55:22.843116 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6401 19:55:22.843765 ==
6402 19:55:22.846385 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 19:55:22.850303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 19:55:22.850854 ==
6405 19:55:22.851216 DQS Delay:
6406 19:55:22.853382 DQS0 = 43, DQS1 = 59
6407 19:55:22.853929 DQM Delay:
6408 19:55:22.857089 DQM0 = 9, DQM1 = 12
6409 19:55:22.857658 DQ Delay:
6410 19:55:22.859818 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6411 19:55:22.863131 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6412 19:55:22.866287 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6413 19:55:22.869492 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6414 19:55:22.869948
6415 19:55:22.870308
6416 19:55:22.870659 ==
6417 19:55:22.873109 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 19:55:22.876323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 19:55:22.876797 ==
6420 19:55:22.877158
6421 19:55:22.877504
6422 19:55:22.879945 TX Vref Scan disable
6423 19:55:22.882881 == TX Byte 0 ==
6424 19:55:22.886290 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 19:55:22.889206 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 19:55:22.892711 == TX Byte 1 ==
6427 19:55:22.896230 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6428 19:55:22.899033 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6429 19:55:22.899450 ==
6430 19:55:22.902593 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 19:55:22.906281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 19:55:22.909454 ==
6433 19:55:22.909867
6434 19:55:22.910195
6435 19:55:22.910498 TX Vref Scan disable
6436 19:55:22.912093 == TX Byte 0 ==
6437 19:55:22.915660 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6438 19:55:22.919049 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6439 19:55:22.922370 == TX Byte 1 ==
6440 19:55:22.925520 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6441 19:55:22.929111 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6442 19:55:22.929521
6443 19:55:22.932793 [DATLAT]
6444 19:55:22.933240 Freq=400, CH0 RK0
6445 19:55:22.933600
6446 19:55:22.935843 DATLAT Default: 0xf
6447 19:55:22.936280 0, 0xFFFF, sum = 0
6448 19:55:22.938763 1, 0xFFFF, sum = 0
6449 19:55:22.939372 2, 0xFFFF, sum = 0
6450 19:55:22.942707 3, 0xFFFF, sum = 0
6451 19:55:22.943253 4, 0xFFFF, sum = 0
6452 19:55:22.945443 5, 0xFFFF, sum = 0
6453 19:55:22.945861 6, 0xFFFF, sum = 0
6454 19:55:22.948774 7, 0xFFFF, sum = 0
6455 19:55:22.949352 8, 0xFFFF, sum = 0
6456 19:55:22.951573 9, 0xFFFF, sum = 0
6457 19:55:22.951680 10, 0xFFFF, sum = 0
6458 19:55:22.954781 11, 0xFFFF, sum = 0
6459 19:55:22.959163 12, 0xFFFF, sum = 0
6460 19:55:22.959244 13, 0x0, sum = 1
6461 19:55:22.961545 14, 0x0, sum = 2
6462 19:55:22.961660 15, 0x0, sum = 3
6463 19:55:22.961762 16, 0x0, sum = 4
6464 19:55:22.965221 best_step = 14
6465 19:55:22.965304
6466 19:55:22.965368 ==
6467 19:55:22.968411 Dram Type= 6, Freq= 0, CH_0, rank 0
6468 19:55:22.971407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 19:55:22.971514 ==
6470 19:55:22.974395 RX Vref Scan: 1
6471 19:55:22.974500
6472 19:55:22.977769 RX Vref 0 -> 0, step: 1
6473 19:55:22.977877
6474 19:55:22.977971 RX Delay -359 -> 252, step: 8
6475 19:55:22.978064
6476 19:55:22.981207 Set Vref, RX VrefLevel [Byte0]: 58
6477 19:55:22.984522 [Byte1]: 48
6478 19:55:22.989829
6479 19:55:22.989909 Final RX Vref Byte 0 = 58 to rank0
6480 19:55:22.993369 Final RX Vref Byte 1 = 48 to rank0
6481 19:55:22.996656 Final RX Vref Byte 0 = 58 to rank1
6482 19:55:23.000006 Final RX Vref Byte 1 = 48 to rank1==
6483 19:55:23.003477 Dram Type= 6, Freq= 0, CH_0, rank 0
6484 19:55:23.010184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 19:55:23.010298 ==
6486 19:55:23.010396 DQS Delay:
6487 19:55:23.013115 DQS0 = 48, DQS1 = 60
6488 19:55:23.013222 DQM Delay:
6489 19:55:23.013319 DQM0 = 11, DQM1 = 12
6490 19:55:23.016725 DQ Delay:
6491 19:55:23.020021 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6492 19:55:23.023103 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6493 19:55:23.023183 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6494 19:55:23.029886 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6495 19:55:23.030045
6496 19:55:23.030124
6497 19:55:23.036271 [DQSOSCAuto] RK0, (LSB)MR18= 0xc387, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6498 19:55:23.039452 CH0 RK0: MR19=C0C, MR18=C387
6499 19:55:23.046615 CH0_RK0: MR19=0xC0C, MR18=0xC387, DQSOSC=385, MR23=63, INC=398, DEC=265
6500 19:55:23.046810 ==
6501 19:55:23.049390 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 19:55:23.052644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 19:55:23.052827 ==
6504 19:55:23.055863 [Gating] SW mode calibration
6505 19:55:23.062654 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6506 19:55:23.069628 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6507 19:55:23.072631 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6508 19:55:23.075860 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6509 19:55:23.082511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6510 19:55:23.085857 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 19:55:23.089386 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 19:55:23.095765 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 19:55:23.099219 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 19:55:23.102416 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 19:55:23.109490 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6516 19:55:23.112259 Total UI for P1: 0, mck2ui 16
6517 19:55:23.115860 best dqsien dly found for B0: ( 0, 14, 24)
6518 19:55:23.116300 Total UI for P1: 0, mck2ui 16
6519 19:55:23.122347 best dqsien dly found for B1: ( 0, 14, 24)
6520 19:55:23.125970 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6521 19:55:23.128573 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6522 19:55:23.128935
6523 19:55:23.132561 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6524 19:55:23.135088 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6525 19:55:23.138672 [Gating] SW calibration Done
6526 19:55:23.138775 ==
6527 19:55:23.141658 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 19:55:23.145283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 19:55:23.145367 ==
6530 19:55:23.148468 RX Vref Scan: 0
6531 19:55:23.148550
6532 19:55:23.151639 RX Vref 0 -> 0, step: 1
6533 19:55:23.151719
6534 19:55:23.151825 RX Delay -410 -> 252, step: 16
6535 19:55:23.158959 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6536 19:55:23.161760 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6537 19:55:23.165120 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6538 19:55:23.168487 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6539 19:55:23.175337 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6540 19:55:23.178259 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6541 19:55:23.181697 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6542 19:55:23.184733 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6543 19:55:23.191896 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6544 19:55:23.194730 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6545 19:55:23.197830 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6546 19:55:23.204566 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6547 19:55:23.207935 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6548 19:55:23.211488 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6549 19:55:23.214155 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6550 19:55:23.221048 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6551 19:55:23.221129 ==
6552 19:55:23.224151 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 19:55:23.227339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 19:55:23.227420 ==
6555 19:55:23.227498 DQS Delay:
6556 19:55:23.230587 DQS0 = 43, DQS1 = 59
6557 19:55:23.230668 DQM Delay:
6558 19:55:23.234198 DQM0 = 11, DQM1 = 16
6559 19:55:23.234281 DQ Delay:
6560 19:55:23.237444 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6561 19:55:23.240634 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6562 19:55:23.243878 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6563 19:55:23.248484 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6564 19:55:23.248900
6565 19:55:23.249229
6566 19:55:23.249534 ==
6567 19:55:23.251251 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 19:55:23.254119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 19:55:23.254540 ==
6570 19:55:23.258138
6571 19:55:23.258646
6572 19:55:23.258974 TX Vref Scan disable
6573 19:55:23.261413 == TX Byte 0 ==
6574 19:55:23.264517 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6575 19:55:23.267500 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6576 19:55:23.271035 == TX Byte 1 ==
6577 19:55:23.273842 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6578 19:55:23.277456 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6579 19:55:23.277918 ==
6580 19:55:23.281232 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 19:55:23.284286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 19:55:23.287392 ==
6583 19:55:23.288153
6584 19:55:23.288576
6585 19:55:23.288939 TX Vref Scan disable
6586 19:55:23.290819 == TX Byte 0 ==
6587 19:55:23.294040 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6588 19:55:23.297248 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6589 19:55:23.300501 == TX Byte 1 ==
6590 19:55:23.304154 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6591 19:55:23.307267 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6592 19:55:23.307761
6593 19:55:23.310835 [DATLAT]
6594 19:55:23.311385 Freq=400, CH0 RK1
6595 19:55:23.311807
6596 19:55:23.313621 DATLAT Default: 0xe
6597 19:55:23.314221 0, 0xFFFF, sum = 0
6598 19:55:23.316889 1, 0xFFFF, sum = 0
6599 19:55:23.317351 2, 0xFFFF, sum = 0
6600 19:55:23.320347 3, 0xFFFF, sum = 0
6601 19:55:23.320816 4, 0xFFFF, sum = 0
6602 19:55:23.323622 5, 0xFFFF, sum = 0
6603 19:55:23.324129 6, 0xFFFF, sum = 0
6604 19:55:23.327242 7, 0xFFFF, sum = 0
6605 19:55:23.327908 8, 0xFFFF, sum = 0
6606 19:55:23.329954 9, 0xFFFF, sum = 0
6607 19:55:23.330428 10, 0xFFFF, sum = 0
6608 19:55:23.333725 11, 0xFFFF, sum = 0
6609 19:55:23.334213 12, 0xFFFF, sum = 0
6610 19:55:23.336582 13, 0x0, sum = 1
6611 19:55:23.337046 14, 0x0, sum = 2
6612 19:55:23.339886 15, 0x0, sum = 3
6613 19:55:23.340355 16, 0x0, sum = 4
6614 19:55:23.343125 best_step = 14
6615 19:55:23.343585
6616 19:55:23.344042 ==
6617 19:55:23.347048 Dram Type= 6, Freq= 0, CH_0, rank 1
6618 19:55:23.350210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 19:55:23.350767 ==
6620 19:55:23.353387 RX Vref Scan: 0
6621 19:55:23.353943
6622 19:55:23.354312 RX Vref 0 -> 0, step: 1
6623 19:55:23.356332
6624 19:55:23.356791 RX Delay -359 -> 252, step: 8
6625 19:55:23.365198 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6626 19:55:23.368073 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6627 19:55:23.371694 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6628 19:55:23.378144 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6629 19:55:23.381469 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6630 19:55:23.385283 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6631 19:55:23.388147 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6632 19:55:23.394542 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6633 19:55:23.398583 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6634 19:55:23.401257 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6635 19:55:23.404295 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6636 19:55:23.411176 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6637 19:55:23.414435 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6638 19:55:23.417464 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6639 19:55:23.420953 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6640 19:55:23.427939 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6641 19:55:23.428493 ==
6642 19:55:23.430614 Dram Type= 6, Freq= 0, CH_0, rank 1
6643 19:55:23.434836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 19:55:23.435395 ==
6645 19:55:23.435803 DQS Delay:
6646 19:55:23.437610 DQS0 = 44, DQS1 = 60
6647 19:55:23.438163 DQM Delay:
6648 19:55:23.441263 DQM0 = 9, DQM1 = 15
6649 19:55:23.441813 DQ Delay:
6650 19:55:23.444114 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6651 19:55:23.447494 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6652 19:55:23.450887 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6653 19:55:23.453863 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6654 19:55:23.454331
6655 19:55:23.454909
6656 19:55:23.460527 [DQSOSCAuto] RK1, (LSB)MR18= 0xba45, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6657 19:55:23.464227 CH0 RK1: MR19=C0C, MR18=BA45
6658 19:55:23.470506 CH0_RK1: MR19=0xC0C, MR18=0xBA45, DQSOSC=386, MR23=63, INC=396, DEC=264
6659 19:55:23.473658 [RxdqsGatingPostProcess] freq 400
6660 19:55:23.480597 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6661 19:55:23.484005 best DQS0 dly(2T, 0.5T) = (0, 10)
6662 19:55:23.486935 best DQS1 dly(2T, 0.5T) = (0, 10)
6663 19:55:23.490180 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6664 19:55:23.493707 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6665 19:55:23.494363 best DQS0 dly(2T, 0.5T) = (0, 10)
6666 19:55:23.497253 best DQS1 dly(2T, 0.5T) = (0, 10)
6667 19:55:23.500193 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6668 19:55:23.503374 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6669 19:55:23.506748 Pre-setting of DQS Precalculation
6670 19:55:23.513668 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6671 19:55:23.514196 ==
6672 19:55:23.516549 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 19:55:23.519851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 19:55:23.520272 ==
6675 19:55:23.527097 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6676 19:55:23.533633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6677 19:55:23.536618 [CA 0] Center 36 (8~64) winsize 57
6678 19:55:23.537170 [CA 1] Center 36 (8~64) winsize 57
6679 19:55:23.540046 [CA 2] Center 36 (8~64) winsize 57
6680 19:55:23.543448 [CA 3] Center 36 (8~64) winsize 57
6681 19:55:23.546816 [CA 4] Center 36 (8~64) winsize 57
6682 19:55:23.549842 [CA 5] Center 36 (8~64) winsize 57
6683 19:55:23.550392
6684 19:55:23.553364 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6685 19:55:23.553915
6686 19:55:23.559865 [CATrainingPosCal] consider 1 rank data
6687 19:55:23.560417 u2DelayCellTimex100 = 270/100 ps
6688 19:55:23.566660 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 19:55:23.569575 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 19:55:23.572976 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 19:55:23.576126 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 19:55:23.579333 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 19:55:23.582980 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 19:55:23.583439
6695 19:55:23.585809 CA PerBit enable=1, Macro0, CA PI delay=36
6696 19:55:23.586270
6697 19:55:23.589003 [CBTSetCACLKResult] CA Dly = 36
6698 19:55:23.591966 CS Dly: 1 (0~32)
6699 19:55:23.592061 ==
6700 19:55:23.595543 Dram Type= 6, Freq= 0, CH_1, rank 1
6701 19:55:23.598923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 19:55:23.599010 ==
6703 19:55:23.605966 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6704 19:55:23.611845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6705 19:55:23.611963 [CA 0] Center 36 (8~64) winsize 57
6706 19:55:23.615310 [CA 1] Center 36 (8~64) winsize 57
6707 19:55:23.618531 [CA 2] Center 36 (8~64) winsize 57
6708 19:55:23.621869 [CA 3] Center 36 (8~64) winsize 57
6709 19:55:23.625132 [CA 4] Center 36 (8~64) winsize 57
6710 19:55:23.628499 [CA 5] Center 36 (8~64) winsize 57
6711 19:55:23.628649
6712 19:55:23.632360 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6713 19:55:23.632531
6714 19:55:23.638357 [CATrainingPosCal] consider 2 rank data
6715 19:55:23.638556 u2DelayCellTimex100 = 270/100 ps
6716 19:55:23.644696 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 19:55:23.648004 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 19:55:23.651668 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 19:55:23.654650 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 19:55:23.658035 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 19:55:23.661435 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 19:55:23.661727
6723 19:55:23.664865 CA PerBit enable=1, Macro0, CA PI delay=36
6724 19:55:23.665161
6725 19:55:23.668105 [CBTSetCACLKResult] CA Dly = 36
6726 19:55:23.671206 CS Dly: 1 (0~32)
6727 19:55:23.671501
6728 19:55:23.674652 ----->DramcWriteLeveling(PI) begin...
6729 19:55:23.674951 ==
6730 19:55:23.677652 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 19:55:23.681205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 19:55:23.681573 ==
6733 19:55:23.684909 Write leveling (Byte 0): 40 => 8
6734 19:55:23.687720 Write leveling (Byte 1): 32 => 0
6735 19:55:23.691382 DramcWriteLeveling(PI) end<-----
6736 19:55:23.691757
6737 19:55:23.692122 ==
6738 19:55:23.694691 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 19:55:23.697884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 19:55:23.698260 ==
6741 19:55:23.700886 [Gating] SW mode calibration
6742 19:55:23.707589 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6743 19:55:23.714039 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6744 19:55:23.717838 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6745 19:55:23.720627 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6746 19:55:23.727328 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6747 19:55:23.730775 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 19:55:23.734221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 19:55:23.740631 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 19:55:23.743718 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 19:55:23.747133 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6752 19:55:23.753348 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6753 19:55:23.757020 Total UI for P1: 0, mck2ui 16
6754 19:55:23.761206 best dqsien dly found for B0: ( 0, 14, 24)
6755 19:55:23.763628 Total UI for P1: 0, mck2ui 16
6756 19:55:23.766776 best dqsien dly found for B1: ( 0, 14, 24)
6757 19:55:23.770080 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6758 19:55:23.773426 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6759 19:55:23.773724
6760 19:55:23.776731 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6761 19:55:23.779902 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6762 19:55:23.783055 [Gating] SW calibration Done
6763 19:55:23.783353 ==
6764 19:55:23.786327 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 19:55:23.789789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 19:55:23.790087 ==
6767 19:55:23.793582 RX Vref Scan: 0
6768 19:55:23.794014
6769 19:55:23.796244 RX Vref 0 -> 0, step: 1
6770 19:55:23.796557
6771 19:55:23.796858 RX Delay -410 -> 252, step: 16
6772 19:55:23.803393 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6773 19:55:23.806367 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6774 19:55:23.809827 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6775 19:55:23.816388 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6776 19:55:23.820124 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6777 19:55:23.823071 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6778 19:55:23.826677 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6779 19:55:23.833187 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6780 19:55:23.836209 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6781 19:55:23.839626 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6782 19:55:23.842849 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6783 19:55:23.849569 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6784 19:55:23.852551 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6785 19:55:23.856911 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6786 19:55:23.859008 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6787 19:55:23.865671 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6788 19:55:23.865765 ==
6789 19:55:23.869261 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 19:55:23.872429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 19:55:23.872509 ==
6792 19:55:23.872571 DQS Delay:
6793 19:55:23.875686 DQS0 = 43, DQS1 = 51
6794 19:55:23.875789 DQM Delay:
6795 19:55:23.878866 DQM0 = 12, DQM1 = 14
6796 19:55:23.878943 DQ Delay:
6797 19:55:23.882253 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6798 19:55:23.885446 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6799 19:55:23.888801 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6800 19:55:23.892036 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6801 19:55:23.892127
6802 19:55:23.892197
6803 19:55:23.892264 ==
6804 19:55:23.895638 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 19:55:23.898778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 19:55:23.898873 ==
6807 19:55:23.898996
6808 19:55:23.899103
6809 19:55:23.902129 TX Vref Scan disable
6810 19:55:23.905380 == TX Byte 0 ==
6811 19:55:23.909287 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 19:55:23.912474 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 19:55:23.916085 == TX Byte 1 ==
6814 19:55:23.918731 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6815 19:55:23.922119 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6816 19:55:23.922219 ==
6817 19:55:23.925663 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 19:55:23.928930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 19:55:23.932342 ==
6820 19:55:23.932447
6821 19:55:23.932528
6822 19:55:23.932602 TX Vref Scan disable
6823 19:55:23.936047 == TX Byte 0 ==
6824 19:55:23.938501 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6825 19:55:23.942519 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6826 19:55:23.945735 == TX Byte 1 ==
6827 19:55:23.949277 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6828 19:55:23.952366 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6829 19:55:23.952595
6830 19:55:23.955454 [DATLAT]
6831 19:55:23.955684 Freq=400, CH1 RK0
6832 19:55:23.955866
6833 19:55:23.958730 DATLAT Default: 0xf
6834 19:55:23.958984 0, 0xFFFF, sum = 0
6835 19:55:23.962041 1, 0xFFFF, sum = 0
6836 19:55:23.962328 2, 0xFFFF, sum = 0
6837 19:55:23.965370 3, 0xFFFF, sum = 0
6838 19:55:23.965665 4, 0xFFFF, sum = 0
6839 19:55:23.968310 5, 0xFFFF, sum = 0
6840 19:55:23.968575 6, 0xFFFF, sum = 0
6841 19:55:23.972310 7, 0xFFFF, sum = 0
6842 19:55:23.972743 8, 0xFFFF, sum = 0
6843 19:55:23.974702 9, 0xFFFF, sum = 0
6844 19:55:23.975117 10, 0xFFFF, sum = 0
6845 19:55:23.978215 11, 0xFFFF, sum = 0
6846 19:55:23.981741 12, 0xFFFF, sum = 0
6847 19:55:23.982249 13, 0x0, sum = 1
6848 19:55:23.984830 14, 0x0, sum = 2
6849 19:55:23.985085 15, 0x0, sum = 3
6850 19:55:23.985155 16, 0x0, sum = 4
6851 19:55:23.988009 best_step = 14
6852 19:55:23.988088
6853 19:55:23.988153 ==
6854 19:55:23.991467 Dram Type= 6, Freq= 0, CH_1, rank 0
6855 19:55:23.994497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 19:55:23.994584 ==
6857 19:55:23.997979 RX Vref Scan: 1
6858 19:55:23.998080
6859 19:55:24.001156 RX Vref 0 -> 0, step: 1
6860 19:55:24.001244
6861 19:55:24.001316 RX Delay -343 -> 252, step: 8
6862 19:55:24.001384
6863 19:55:24.004268 Set Vref, RX VrefLevel [Byte0]: 48
6864 19:55:24.007504 [Byte1]: 58
6865 19:55:24.013142
6866 19:55:24.013262 Final RX Vref Byte 0 = 48 to rank0
6867 19:55:24.016449 Final RX Vref Byte 1 = 58 to rank0
6868 19:55:24.019677 Final RX Vref Byte 0 = 48 to rank1
6869 19:55:24.023167 Final RX Vref Byte 1 = 58 to rank1==
6870 19:55:24.026545 Dram Type= 6, Freq= 0, CH_1, rank 0
6871 19:55:24.032766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 19:55:24.033093 ==
6873 19:55:24.033371 DQS Delay:
6874 19:55:24.036190 DQS0 = 44, DQS1 = 56
6875 19:55:24.036388 DQM Delay:
6876 19:55:24.036546 DQM0 = 8, DQM1 = 12
6877 19:55:24.039964 DQ Delay:
6878 19:55:24.042813 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6879 19:55:24.043164 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6880 19:55:24.046372 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6881 19:55:24.049469 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6882 19:55:24.052659
6883 19:55:24.052978
6884 19:55:24.059278 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6885 19:55:24.062383 CH1 RK0: MR19=C0C, MR18=9B71
6886 19:55:24.069392 CH1_RK0: MR19=0xC0C, MR18=0x9B71, DQSOSC=390, MR23=63, INC=388, DEC=258
6887 19:55:24.069757 ==
6888 19:55:24.072806 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 19:55:24.075972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 19:55:24.076357 ==
6891 19:55:24.078901 [Gating] SW mode calibration
6892 19:55:24.085537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6893 19:55:24.092146 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6894 19:55:24.095374 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6895 19:55:24.099241 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6896 19:55:24.105314 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6897 19:55:24.108413 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 19:55:24.111441 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 19:55:24.119074 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 19:55:24.121368 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 19:55:24.125163 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6902 19:55:24.131682 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6903 19:55:24.134908 Total UI for P1: 0, mck2ui 16
6904 19:55:24.138804 best dqsien dly found for B0: ( 0, 14, 24)
6905 19:55:24.138991 Total UI for P1: 0, mck2ui 16
6906 19:55:24.144995 best dqsien dly found for B1: ( 0, 14, 24)
6907 19:55:24.148199 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6908 19:55:24.151537 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6909 19:55:24.151766
6910 19:55:24.155251 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6911 19:55:24.158362 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6912 19:55:24.161530 [Gating] SW calibration Done
6913 19:55:24.161787 ==
6914 19:55:24.164981 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 19:55:24.168356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 19:55:24.168678 ==
6917 19:55:24.171450 RX Vref Scan: 0
6918 19:55:24.171810
6919 19:55:24.174922 RX Vref 0 -> 0, step: 1
6920 19:55:24.175218
6921 19:55:24.175452 RX Delay -410 -> 252, step: 16
6922 19:55:24.181580 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6923 19:55:24.184797 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6924 19:55:24.187848 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6925 19:55:24.191855 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6926 19:55:24.197614 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6927 19:55:24.200730 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6928 19:55:24.204103 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6929 19:55:24.211023 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6930 19:55:24.214213 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6931 19:55:24.217391 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6932 19:55:24.220263 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6933 19:55:24.227214 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6934 19:55:24.230265 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6935 19:55:24.233783 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6936 19:55:24.240224 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6937 19:55:24.243536 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6938 19:55:24.243793 ==
6939 19:55:24.246847 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 19:55:24.250561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 19:55:24.250950 ==
6942 19:55:24.253953 DQS Delay:
6943 19:55:24.254429 DQS0 = 51, DQS1 = 59
6944 19:55:24.254735 DQM Delay:
6945 19:55:24.257011 DQM0 = 20, DQM1 = 22
6946 19:55:24.257571 DQ Delay:
6947 19:55:24.260723 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6948 19:55:24.263611 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6949 19:55:24.267247 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6950 19:55:24.270327 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6951 19:55:24.270878
6952 19:55:24.271244
6953 19:55:24.271582 ==
6954 19:55:24.273245 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 19:55:24.279876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 19:55:24.280342 ==
6957 19:55:24.280710
6958 19:55:24.281048
6959 19:55:24.281371 TX Vref Scan disable
6960 19:55:24.283780 == TX Byte 0 ==
6961 19:55:24.286743 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6962 19:55:24.290338 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6963 19:55:24.293111 == TX Byte 1 ==
6964 19:55:24.296729 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6965 19:55:24.299661 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6966 19:55:24.303223 ==
6967 19:55:24.303678 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 19:55:24.309956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 19:55:24.310499 ==
6970 19:55:24.310869
6971 19:55:24.311208
6972 19:55:24.313098 TX Vref Scan disable
6973 19:55:24.313647 == TX Byte 0 ==
6974 19:55:24.316636 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6975 19:55:24.322862 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6976 19:55:24.323415 == TX Byte 1 ==
6977 19:55:24.326046 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6978 19:55:24.332678 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6979 19:55:24.333224
6980 19:55:24.333592 [DATLAT]
6981 19:55:24.333931 Freq=400, CH1 RK1
6982 19:55:24.334258
6983 19:55:24.336061 DATLAT Default: 0xe
6984 19:55:24.336514 0, 0xFFFF, sum = 0
6985 19:55:24.339805 1, 0xFFFF, sum = 0
6986 19:55:24.342581 2, 0xFFFF, sum = 0
6987 19:55:24.343047 3, 0xFFFF, sum = 0
6988 19:55:24.345564 4, 0xFFFF, sum = 0
6989 19:55:24.346024 5, 0xFFFF, sum = 0
6990 19:55:24.349491 6, 0xFFFF, sum = 0
6991 19:55:24.350064 7, 0xFFFF, sum = 0
6992 19:55:24.352582 8, 0xFFFF, sum = 0
6993 19:55:24.353061 9, 0xFFFF, sum = 0
6994 19:55:24.355796 10, 0xFFFF, sum = 0
6995 19:55:24.356294 11, 0xFFFF, sum = 0
6996 19:55:24.359120 12, 0xFFFF, sum = 0
6997 19:55:24.359679 13, 0x0, sum = 1
6998 19:55:24.362580 14, 0x0, sum = 2
6999 19:55:24.363174 15, 0x0, sum = 3
7000 19:55:24.365859 16, 0x0, sum = 4
7001 19:55:24.366424 best_step = 14
7002 19:55:24.366787
7003 19:55:24.367118 ==
7004 19:55:24.368966 Dram Type= 6, Freq= 0, CH_1, rank 1
7005 19:55:24.372327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7006 19:55:24.375574 ==
7007 19:55:24.376213 RX Vref Scan: 0
7008 19:55:24.376584
7009 19:55:24.378789 RX Vref 0 -> 0, step: 1
7010 19:55:24.379254
7011 19:55:24.381724 RX Delay -359 -> 252, step: 8
7012 19:55:24.389214 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7013 19:55:24.392044 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7014 19:55:24.395609 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7015 19:55:24.398224 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7016 19:55:24.405194 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7017 19:55:24.408177 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7018 19:55:24.412011 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7019 19:55:24.415083 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7020 19:55:24.422015 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
7021 19:55:24.425345 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7022 19:55:24.427989 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7023 19:55:24.431951 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7024 19:55:24.439403 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7025 19:55:24.442320 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7026 19:55:24.444856 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7027 19:55:24.451597 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7028 19:55:24.452222 ==
7029 19:55:24.454952 Dram Type= 6, Freq= 0, CH_1, rank 1
7030 19:55:24.457825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7031 19:55:24.458384 ==
7032 19:55:24.458756 DQS Delay:
7033 19:55:24.461258 DQS0 = 48, DQS1 = 60
7034 19:55:24.461962 DQM Delay:
7035 19:55:24.464412 DQM0 = 12, DQM1 = 14
7036 19:55:24.464963 DQ Delay:
7037 19:55:24.467981 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7038 19:55:24.471120 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
7039 19:55:24.474578 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7040 19:55:24.477721 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7041 19:55:24.478185
7042 19:55:24.478625
7043 19:55:24.484503 [DQSOSCAuto] RK1, (LSB)MR18= 0x6857, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7044 19:55:24.488038 CH1 RK1: MR19=C0C, MR18=6857
7045 19:55:24.494397 CH1_RK1: MR19=0xC0C, MR18=0x6857, DQSOSC=396, MR23=63, INC=376, DEC=251
7046 19:55:24.497891 [RxdqsGatingPostProcess] freq 400
7047 19:55:24.504542 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7048 19:55:24.507778 best DQS0 dly(2T, 0.5T) = (0, 10)
7049 19:55:24.508339 best DQS1 dly(2T, 0.5T) = (0, 10)
7050 19:55:24.510851 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7051 19:55:24.514848 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7052 19:55:24.517638 best DQS0 dly(2T, 0.5T) = (0, 10)
7053 19:55:24.520734 best DQS1 dly(2T, 0.5T) = (0, 10)
7054 19:55:24.524082 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7055 19:55:24.527108 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7056 19:55:24.530775 Pre-setting of DQS Precalculation
7057 19:55:24.537741 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7058 19:55:24.543903 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7059 19:55:24.550756 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7060 19:55:24.551176
7061 19:55:24.551508
7062 19:55:24.554020 [Calibration Summary] 800 Mbps
7063 19:55:24.554542 CH 0, Rank 0
7064 19:55:24.557313 SW Impedance : PASS
7065 19:55:24.560318 DUTY Scan : NO K
7066 19:55:24.560780 ZQ Calibration : PASS
7067 19:55:24.563529 Jitter Meter : NO K
7068 19:55:24.566783 CBT Training : PASS
7069 19:55:24.567201 Write leveling : PASS
7070 19:55:24.570088 RX DQS gating : PASS
7071 19:55:24.573862 RX DQ/DQS(RDDQC) : PASS
7072 19:55:24.574279 TX DQ/DQS : PASS
7073 19:55:24.576576 RX DATLAT : PASS
7074 19:55:24.580337 RX DQ/DQS(Engine): PASS
7075 19:55:24.580755 TX OE : NO K
7076 19:55:24.581091 All Pass.
7077 19:55:24.583384
7078 19:55:24.583834 CH 0, Rank 1
7079 19:55:24.586499 SW Impedance : PASS
7080 19:55:24.587015 DUTY Scan : NO K
7081 19:55:24.590173 ZQ Calibration : PASS
7082 19:55:24.590677 Jitter Meter : NO K
7083 19:55:24.593298 CBT Training : PASS
7084 19:55:24.596521 Write leveling : NO K
7085 19:55:24.596942 RX DQS gating : PASS
7086 19:55:24.599575 RX DQ/DQS(RDDQC) : PASS
7087 19:55:24.602960 TX DQ/DQS : PASS
7088 19:55:24.603560 RX DATLAT : PASS
7089 19:55:24.606112 RX DQ/DQS(Engine): PASS
7090 19:55:24.609572 TX OE : NO K
7091 19:55:24.609992 All Pass.
7092 19:55:24.610367
7093 19:55:24.610857 CH 1, Rank 0
7094 19:55:24.612906 SW Impedance : PASS
7095 19:55:24.616540 DUTY Scan : NO K
7096 19:55:24.616960 ZQ Calibration : PASS
7097 19:55:24.619169 Jitter Meter : NO K
7098 19:55:24.622792 CBT Training : PASS
7099 19:55:24.623208 Write leveling : PASS
7100 19:55:24.626281 RX DQS gating : PASS
7101 19:55:24.629820 RX DQ/DQS(RDDQC) : PASS
7102 19:55:24.630332 TX DQ/DQS : PASS
7103 19:55:24.632588 RX DATLAT : PASS
7104 19:55:24.635872 RX DQ/DQS(Engine): PASS
7105 19:55:24.636293 TX OE : NO K
7106 19:55:24.639618 All Pass.
7107 19:55:24.640177
7108 19:55:24.640515 CH 1, Rank 1
7109 19:55:24.643358 SW Impedance : PASS
7110 19:55:24.643921 DUTY Scan : NO K
7111 19:55:24.646063 ZQ Calibration : PASS
7112 19:55:24.649024 Jitter Meter : NO K
7113 19:55:24.649443 CBT Training : PASS
7114 19:55:24.652180 Write leveling : NO K
7115 19:55:24.655526 RX DQS gating : PASS
7116 19:55:24.656071 RX DQ/DQS(RDDQC) : PASS
7117 19:55:24.659286 TX DQ/DQS : PASS
7118 19:55:24.662561 RX DATLAT : PASS
7119 19:55:24.663071 RX DQ/DQS(Engine): PASS
7120 19:55:24.666023 TX OE : NO K
7121 19:55:24.666537 All Pass.
7122 19:55:24.666872
7123 19:55:24.669411 DramC Write-DBI off
7124 19:55:24.672117 PER_BANK_REFRESH: Hybrid Mode
7125 19:55:24.672539 TX_TRACKING: ON
7126 19:55:24.682462 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7127 19:55:24.685710 [FAST_K] Save calibration result to emmc
7128 19:55:24.689547 dramc_set_vcore_voltage set vcore to 725000
7129 19:55:24.692296 Read voltage for 1600, 0
7130 19:55:24.692808 Vio18 = 0
7131 19:55:24.693143 Vcore = 725000
7132 19:55:24.695471 Vdram = 0
7133 19:55:24.696019 Vddq = 0
7134 19:55:24.696357 Vmddr = 0
7135 19:55:24.702218 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7136 19:55:24.705937 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7137 19:55:24.708877 MEM_TYPE=3, freq_sel=13
7138 19:55:24.712433 sv_algorithm_assistance_LP4_3733
7139 19:55:24.715595 ============ PULL DRAM RESETB DOWN ============
7140 19:55:24.718271 ========== PULL DRAM RESETB DOWN end =========
7141 19:55:24.725430 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7142 19:55:24.728456 ===================================
7143 19:55:24.731794 LPDDR4 DRAM CONFIGURATION
7144 19:55:24.734878 ===================================
7145 19:55:24.735344 EX_ROW_EN[0] = 0x0
7146 19:55:24.738265 EX_ROW_EN[1] = 0x0
7147 19:55:24.738816 LP4Y_EN = 0x0
7148 19:55:24.741819 WORK_FSP = 0x1
7149 19:55:24.742377 WL = 0x5
7150 19:55:24.745084 RL = 0x5
7151 19:55:24.745638 BL = 0x2
7152 19:55:24.748799 RPST = 0x0
7153 19:55:24.749365 RD_PRE = 0x0
7154 19:55:24.751950 WR_PRE = 0x1
7155 19:55:24.752519 WR_PST = 0x1
7156 19:55:24.755083 DBI_WR = 0x0
7157 19:55:24.755649 DBI_RD = 0x0
7158 19:55:24.758521 OTF = 0x1
7159 19:55:24.761657 ===================================
7160 19:55:24.764680 ===================================
7161 19:55:24.765240 ANA top config
7162 19:55:24.768886 ===================================
7163 19:55:24.771661 DLL_ASYNC_EN = 0
7164 19:55:24.774752 ALL_SLAVE_EN = 0
7165 19:55:24.778037 NEW_RANK_MODE = 1
7166 19:55:24.778509 DLL_IDLE_MODE = 1
7167 19:55:24.781311 LP45_APHY_COMB_EN = 1
7168 19:55:24.785171 TX_ODT_DIS = 0
7169 19:55:24.788338 NEW_8X_MODE = 1
7170 19:55:24.791437 ===================================
7171 19:55:24.794728 ===================================
7172 19:55:24.798622 data_rate = 3200
7173 19:55:24.801606 CKR = 1
7174 19:55:24.802176 DQ_P2S_RATIO = 8
7175 19:55:24.804735 ===================================
7176 19:55:24.807955 CA_P2S_RATIO = 8
7177 19:55:24.811363 DQ_CA_OPEN = 0
7178 19:55:24.814613 DQ_SEMI_OPEN = 0
7179 19:55:24.818111 CA_SEMI_OPEN = 0
7180 19:55:24.821143 CA_FULL_RATE = 0
7181 19:55:24.821717 DQ_CKDIV4_EN = 0
7182 19:55:24.824122 CA_CKDIV4_EN = 0
7183 19:55:24.828050 CA_PREDIV_EN = 0
7184 19:55:24.831102 PH8_DLY = 12
7185 19:55:24.834331 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7186 19:55:24.837459 DQ_AAMCK_DIV = 4
7187 19:55:24.838028 CA_AAMCK_DIV = 4
7188 19:55:24.841521 CA_ADMCK_DIV = 4
7189 19:55:24.844202 DQ_TRACK_CA_EN = 0
7190 19:55:24.847931 CA_PICK = 1600
7191 19:55:24.850560 CA_MCKIO = 1600
7192 19:55:24.854673 MCKIO_SEMI = 0
7193 19:55:24.857081 PLL_FREQ = 3068
7194 19:55:24.860614 DQ_UI_PI_RATIO = 32
7195 19:55:24.861175 CA_UI_PI_RATIO = 0
7196 19:55:24.863820 ===================================
7197 19:55:24.867326 ===================================
7198 19:55:24.871645 memory_type:LPDDR4
7199 19:55:24.873602 GP_NUM : 10
7200 19:55:24.874067 SRAM_EN : 1
7201 19:55:24.877254 MD32_EN : 0
7202 19:55:24.880393 ===================================
7203 19:55:24.884073 [ANA_INIT] >>>>>>>>>>>>>>
7204 19:55:24.887159 <<<<<< [CONFIGURE PHASE]: ANA_TX
7205 19:55:24.890648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7206 19:55:24.894369 ===================================
7207 19:55:24.894942 data_rate = 3200,PCW = 0X7600
7208 19:55:24.896675 ===================================
7209 19:55:24.900321 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7210 19:55:24.906744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7211 19:55:24.913237 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7212 19:55:24.916691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7213 19:55:24.920051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7214 19:55:24.923488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7215 19:55:24.926575 [ANA_INIT] flow start
7216 19:55:24.929931 [ANA_INIT] PLL >>>>>>>>
7217 19:55:24.930496 [ANA_INIT] PLL <<<<<<<<
7218 19:55:24.933141 [ANA_INIT] MIDPI >>>>>>>>
7219 19:55:24.936615 [ANA_INIT] MIDPI <<<<<<<<
7220 19:55:24.937178 [ANA_INIT] DLL >>>>>>>>
7221 19:55:24.940290 [ANA_INIT] DLL <<<<<<<<
7222 19:55:24.942701 [ANA_INIT] flow end
7223 19:55:24.946472 ============ LP4 DIFF to SE enter ============
7224 19:55:24.949452 ============ LP4 DIFF to SE exit ============
7225 19:55:24.952780 [ANA_INIT] <<<<<<<<<<<<<
7226 19:55:24.956484 [Flow] Enable top DCM control >>>>>
7227 19:55:24.959626 [Flow] Enable top DCM control <<<<<
7228 19:55:24.962854 Enable DLL master slave shuffle
7229 19:55:24.966127 ==============================================================
7230 19:55:24.969224 Gating Mode config
7231 19:55:24.975974 ==============================================================
7232 19:55:24.976577 Config description:
7233 19:55:24.986037 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7234 19:55:24.992411 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7235 19:55:24.999276 SELPH_MODE 0: By rank 1: By Phase
7236 19:55:25.002654 ==============================================================
7237 19:55:25.005581 GAT_TRACK_EN = 1
7238 19:55:25.008911 RX_GATING_MODE = 2
7239 19:55:25.012455 RX_GATING_TRACK_MODE = 2
7240 19:55:25.015663 SELPH_MODE = 1
7241 19:55:25.019186 PICG_EARLY_EN = 1
7242 19:55:25.022769 VALID_LAT_VALUE = 1
7243 19:55:25.025763 ==============================================================
7244 19:55:25.029248 Enter into Gating configuration >>>>
7245 19:55:25.032610 Exit from Gating configuration <<<<
7246 19:55:25.035480 Enter into DVFS_PRE_config >>>>>
7247 19:55:25.048476 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7248 19:55:25.052103 Exit from DVFS_PRE_config <<<<<
7249 19:55:25.055265 Enter into PICG configuration >>>>
7250 19:55:25.058501 Exit from PICG configuration <<<<
7251 19:55:25.059064 [RX_INPUT] configuration >>>>>
7252 19:55:25.062108 [RX_INPUT] configuration <<<<<
7253 19:55:25.068685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7254 19:55:25.071632 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7255 19:55:25.078270 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7256 19:55:25.085085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7257 19:55:25.091901 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7258 19:55:25.098496 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7259 19:55:25.101286 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7260 19:55:25.104851 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7261 19:55:25.111574 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7262 19:55:25.114562 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7263 19:55:25.118449 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7264 19:55:25.121693 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7265 19:55:25.124530 ===================================
7266 19:55:25.128069 LPDDR4 DRAM CONFIGURATION
7267 19:55:25.131081 ===================================
7268 19:55:25.134244 EX_ROW_EN[0] = 0x0
7269 19:55:25.134702 EX_ROW_EN[1] = 0x0
7270 19:55:25.137846 LP4Y_EN = 0x0
7271 19:55:25.138305 WORK_FSP = 0x1
7272 19:55:25.140931 WL = 0x5
7273 19:55:25.141389 RL = 0x5
7274 19:55:25.145153 BL = 0x2
7275 19:55:25.148103 RPST = 0x0
7276 19:55:25.148662 RD_PRE = 0x0
7277 19:55:25.151353 WR_PRE = 0x1
7278 19:55:25.151848 WR_PST = 0x1
7279 19:55:25.154535 DBI_WR = 0x0
7280 19:55:25.155093 DBI_RD = 0x0
7281 19:55:25.157469 OTF = 0x1
7282 19:55:25.161067 ===================================
7283 19:55:25.164329 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7284 19:55:25.168275 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7285 19:55:25.170790 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7286 19:55:25.174621 ===================================
7287 19:55:25.177608 LPDDR4 DRAM CONFIGURATION
7288 19:55:25.180610 ===================================
7289 19:55:25.184090 EX_ROW_EN[0] = 0x10
7290 19:55:25.184651 EX_ROW_EN[1] = 0x0
7291 19:55:25.187323 LP4Y_EN = 0x0
7292 19:55:25.187908 WORK_FSP = 0x1
7293 19:55:25.190538 WL = 0x5
7294 19:55:25.194188 RL = 0x5
7295 19:55:25.194746 BL = 0x2
7296 19:55:25.197729 RPST = 0x0
7297 19:55:25.198287 RD_PRE = 0x0
7298 19:55:25.200372 WR_PRE = 0x1
7299 19:55:25.200935 WR_PST = 0x1
7300 19:55:25.203358 DBI_WR = 0x0
7301 19:55:25.203864 DBI_RD = 0x0
7302 19:55:25.206806 OTF = 0x1
7303 19:55:25.210200 ===================================
7304 19:55:25.216742 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7305 19:55:25.217310 ==
7306 19:55:25.220019 Dram Type= 6, Freq= 0, CH_0, rank 0
7307 19:55:25.223894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7308 19:55:25.224453 ==
7309 19:55:25.226924 [Duty_Offset_Calibration]
7310 19:55:25.227486 B0:1 B1:-1 CA:0
7311 19:55:25.227949
7312 19:55:25.229835 [DutyScan_Calibration_Flow] k_type=0
7313 19:55:25.240590
7314 19:55:25.241217 ==CLK 0==
7315 19:55:25.243918 Final CLK duty delay cell = 0
7316 19:55:25.247111 [0] MAX Duty = 5156%(X100), DQS PI = 22
7317 19:55:25.250784 [0] MIN Duty = 4875%(X100), DQS PI = 10
7318 19:55:25.253992 [0] AVG Duty = 5015%(X100)
7319 19:55:25.254551
7320 19:55:25.256947 CH0 CLK Duty spec in!! Max-Min= 281%
7321 19:55:25.260356 [DutyScan_Calibration_Flow] ====Done====
7322 19:55:25.260918
7323 19:55:25.263499 [DutyScan_Calibration_Flow] k_type=1
7324 19:55:25.280329
7325 19:55:25.280879 ==DQS 0 ==
7326 19:55:25.283491 Final DQS duty delay cell = -4
7327 19:55:25.286763 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7328 19:55:25.289751 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7329 19:55:25.293127 [-4] AVG Duty = 4922%(X100)
7330 19:55:25.293585
7331 19:55:25.293947 ==DQS 1 ==
7332 19:55:25.296295 Final DQS duty delay cell = 0
7333 19:55:25.299698 [0] MAX Duty = 5187%(X100), DQS PI = 4
7334 19:55:25.302950 [0] MIN Duty = 5031%(X100), DQS PI = 16
7335 19:55:25.305942 [0] AVG Duty = 5109%(X100)
7336 19:55:25.306397
7337 19:55:25.309137 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7338 19:55:25.309592
7339 19:55:25.312787 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7340 19:55:25.316116 [DutyScan_Calibration_Flow] ====Done====
7341 19:55:25.316574
7342 19:55:25.319690 [DutyScan_Calibration_Flow] k_type=3
7343 19:55:25.337569
7344 19:55:25.338116 ==DQM 0 ==
7345 19:55:25.340417 Final DQM duty delay cell = 0
7346 19:55:25.343392 [0] MAX Duty = 5124%(X100), DQS PI = 24
7347 19:55:25.347422 [0] MIN Duty = 4907%(X100), DQS PI = 8
7348 19:55:25.350913 [0] AVG Duty = 5015%(X100)
7349 19:55:25.351458
7350 19:55:25.351886 ==DQM 1 ==
7351 19:55:25.353977 Final DQM duty delay cell = 0
7352 19:55:25.356904 [0] MAX Duty = 5031%(X100), DQS PI = 52
7353 19:55:25.360659 [0] MIN Duty = 4813%(X100), DQS PI = 18
7354 19:55:25.363192 [0] AVG Duty = 4922%(X100)
7355 19:55:25.363647
7356 19:55:25.367319 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7357 19:55:25.368080
7358 19:55:25.370528 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7359 19:55:25.373277 [DutyScan_Calibration_Flow] ====Done====
7360 19:55:25.373733
7361 19:55:25.377133 [DutyScan_Calibration_Flow] k_type=2
7362 19:55:25.393886
7363 19:55:25.394429 ==DQ 0 ==
7364 19:55:25.396736 Final DQ duty delay cell = -4
7365 19:55:25.400342 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7366 19:55:25.403774 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7367 19:55:25.407102 [-4] AVG Duty = 4953%(X100)
7368 19:55:25.407558
7369 19:55:25.408009 ==DQ 1 ==
7370 19:55:25.409871 Final DQ duty delay cell = 0
7371 19:55:25.413414 [0] MAX Duty = 5125%(X100), DQS PI = 2
7372 19:55:25.417261 [0] MIN Duty = 5000%(X100), DQS PI = 34
7373 19:55:25.419973 [0] AVG Duty = 5062%(X100)
7374 19:55:25.420440
7375 19:55:25.423481 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7376 19:55:25.424073
7377 19:55:25.426866 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7378 19:55:25.430070 [DutyScan_Calibration_Flow] ====Done====
7379 19:55:25.430615 ==
7380 19:55:25.433450 Dram Type= 6, Freq= 0, CH_1, rank 0
7381 19:55:25.436613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7382 19:55:25.437068 ==
7383 19:55:25.439926 [Duty_Offset_Calibration]
7384 19:55:25.440373 B0:-1 B1:1 CA:2
7385 19:55:25.440728
7386 19:55:25.443377 [DutyScan_Calibration_Flow] k_type=0
7387 19:55:25.454525
7388 19:55:25.455068 ==CLK 0==
7389 19:55:25.457390 Final CLK duty delay cell = 0
7390 19:55:25.460660 [0] MAX Duty = 5218%(X100), DQS PI = 24
7391 19:55:25.463710 [0] MIN Duty = 4969%(X100), DQS PI = 0
7392 19:55:25.467340 [0] AVG Duty = 5093%(X100)
7393 19:55:25.468025
7394 19:55:25.471123 CH1 CLK Duty spec in!! Max-Min= 249%
7395 19:55:25.473625 [DutyScan_Calibration_Flow] ====Done====
7396 19:55:25.474094
7397 19:55:25.477018 [DutyScan_Calibration_Flow] k_type=1
7398 19:55:25.493590
7399 19:55:25.494194 ==DQS 0 ==
7400 19:55:25.496979 Final DQS duty delay cell = 0
7401 19:55:25.500575 [0] MAX Duty = 5124%(X100), DQS PI = 18
7402 19:55:25.503903 [0] MIN Duty = 4907%(X100), DQS PI = 8
7403 19:55:25.506888 [0] AVG Duty = 5015%(X100)
7404 19:55:25.507347
7405 19:55:25.507712 ==DQS 1 ==
7406 19:55:25.510316 Final DQS duty delay cell = 0
7407 19:55:25.513681 [0] MAX Duty = 5093%(X100), DQS PI = 24
7408 19:55:25.516897 [0] MIN Duty = 4969%(X100), DQS PI = 56
7409 19:55:25.520068 [0] AVG Duty = 5031%(X100)
7410 19:55:25.520528
7411 19:55:25.523441 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7412 19:55:25.523945
7413 19:55:25.527961 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7414 19:55:25.530152 [DutyScan_Calibration_Flow] ====Done====
7415 19:55:25.530727
7416 19:55:25.533367 [DutyScan_Calibration_Flow] k_type=3
7417 19:55:25.551024
7418 19:55:25.551570 ==DQM 0 ==
7419 19:55:25.554132 Final DQM duty delay cell = 0
7420 19:55:25.557274 [0] MAX Duty = 5218%(X100), DQS PI = 18
7421 19:55:25.560956 [0] MIN Duty = 5031%(X100), DQS PI = 8
7422 19:55:25.564443 [0] AVG Duty = 5124%(X100)
7423 19:55:25.565042
7424 19:55:25.565412 ==DQM 1 ==
7425 19:55:25.567508 Final DQM duty delay cell = 0
7426 19:55:25.570872 [0] MAX Duty = 5156%(X100), DQS PI = 2
7427 19:55:25.573804 [0] MIN Duty = 4969%(X100), DQS PI = 34
7428 19:55:25.577009 [0] AVG Duty = 5062%(X100)
7429 19:55:25.577471
7430 19:55:25.579964 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7431 19:55:25.580437
7432 19:55:25.583349 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7433 19:55:25.586753 [DutyScan_Calibration_Flow] ====Done====
7434 19:55:25.587324
7435 19:55:25.590360 [DutyScan_Calibration_Flow] k_type=2
7436 19:55:25.607774
7437 19:55:25.608345 ==DQ 0 ==
7438 19:55:25.610570 Final DQ duty delay cell = 0
7439 19:55:25.613882 [0] MAX Duty = 5156%(X100), DQS PI = 28
7440 19:55:25.617100 [0] MIN Duty = 4906%(X100), DQS PI = 8
7441 19:55:25.617569 [0] AVG Duty = 5031%(X100)
7442 19:55:25.620540
7443 19:55:25.621290 ==DQ 1 ==
7444 19:55:25.623681 Final DQ duty delay cell = 0
7445 19:55:25.627241 [0] MAX Duty = 5156%(X100), DQS PI = 8
7446 19:55:25.630169 [0] MIN Duty = 4969%(X100), DQS PI = 56
7447 19:55:25.630626 [0] AVG Duty = 5062%(X100)
7448 19:55:25.630986
7449 19:55:25.633584 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7450 19:55:25.637048
7451 19:55:25.640635 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7452 19:55:25.643847 [DutyScan_Calibration_Flow] ====Done====
7453 19:55:25.647258 nWR fixed to 30
7454 19:55:25.648225 [ModeRegInit_LP4] CH0 RK0
7455 19:55:25.650462 [ModeRegInit_LP4] CH0 RK1
7456 19:55:25.653505 [ModeRegInit_LP4] CH1 RK0
7457 19:55:25.657221 [ModeRegInit_LP4] CH1 RK1
7458 19:55:25.657699 match AC timing 5
7459 19:55:25.660289 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7460 19:55:25.667115 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7461 19:55:25.670051 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7462 19:55:25.677043 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7463 19:55:25.680035 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7464 19:55:25.680494 [MiockJmeterHQA]
7465 19:55:25.680856
7466 19:55:25.682956 [DramcMiockJmeter] u1RxGatingPI = 0
7467 19:55:25.686504 0 : 4252, 4027
7468 19:55:25.686932 4 : 4253, 4026
7469 19:55:25.689596 8 : 4363, 4137
7470 19:55:25.690037 12 : 4252, 4027
7471 19:55:25.690413 16 : 4363, 4138
7472 19:55:25.693144 20 : 4255, 4029
7473 19:55:25.693566 24 : 4363, 4137
7474 19:55:25.696048 28 : 4252, 4027
7475 19:55:25.696473 32 : 4253, 4026
7476 19:55:25.699918 36 : 4250, 4027
7477 19:55:25.700350 40 : 4360, 4137
7478 19:55:25.703082 44 : 4361, 4137
7479 19:55:25.703504 48 : 4250, 4027
7480 19:55:25.703890 52 : 4250, 4026
7481 19:55:25.706222 56 : 4252, 4027
7482 19:55:25.706643 60 : 4250, 4027
7483 19:55:25.709509 64 : 4253, 4029
7484 19:55:25.709928 68 : 4361, 4138
7485 19:55:25.712985 72 : 4250, 4026
7486 19:55:25.713506 76 : 4250, 4027
7487 19:55:25.715872 80 : 4250, 4027
7488 19:55:25.716300 84 : 4253, 4029
7489 19:55:25.716638 88 : 4250, 4026
7490 19:55:25.719519 92 : 4360, 405
7491 19:55:25.720017 96 : 4250, 0
7492 19:55:25.723128 100 : 4363, 0
7493 19:55:25.723658 104 : 4361, 0
7494 19:55:25.724082 108 : 4361, 0
7495 19:55:25.726123 112 : 4363, 0
7496 19:55:25.726546 116 : 4250, 0
7497 19:55:25.729804 120 : 4250, 0
7498 19:55:25.730321 124 : 4250, 0
7499 19:55:25.730661 128 : 4252, 0
7500 19:55:25.732890 132 : 4250, 0
7501 19:55:25.733446 136 : 4250, 0
7502 19:55:25.736147 140 : 4253, 0
7503 19:55:25.736718 144 : 4360, 0
7504 19:55:25.737062 148 : 4361, 0
7505 19:55:25.739046 152 : 4250, 0
7506 19:55:25.739468 156 : 4250, 0
7507 19:55:25.742452 160 : 4250, 0
7508 19:55:25.742965 164 : 4250, 0
7509 19:55:25.743339 168 : 4250, 0
7510 19:55:25.745545 172 : 4250, 0
7511 19:55:25.745970 176 : 4250, 0
7512 19:55:25.746309 180 : 4253, 0
7513 19:55:25.749251 184 : 4250, 0
7514 19:55:25.749821 188 : 4250, 0
7515 19:55:25.752223 192 : 4252, 0
7516 19:55:25.752648 196 : 4360, 0
7517 19:55:25.752989 200 : 4361, 0
7518 19:55:25.755589 204 : 4363, 0
7519 19:55:25.756047 208 : 4250, 0
7520 19:55:25.759633 212 : 4250, 0
7521 19:55:25.760221 216 : 4250, 0
7522 19:55:25.760568 220 : 4250, 0
7523 19:55:25.762689 224 : 4250, 379
7524 19:55:25.763206 228 : 4253, 3280
7525 19:55:25.765867 232 : 4361, 4137
7526 19:55:25.766294 236 : 4363, 4140
7527 19:55:25.768904 240 : 4250, 4027
7528 19:55:25.769330 244 : 4250, 4026
7529 19:55:25.772226 248 : 4363, 4140
7530 19:55:25.772650 252 : 4250, 4027
7531 19:55:25.775752 256 : 4250, 4027
7532 19:55:25.776182 260 : 4253, 4026
7533 19:55:25.779015 264 : 4253, 4029
7534 19:55:25.779437 268 : 4250, 4027
7535 19:55:25.782362 272 : 4250, 4027
7536 19:55:25.782785 276 : 4360, 4137
7537 19:55:25.783123 280 : 4250, 4027
7538 19:55:25.786007 284 : 4361, 4137
7539 19:55:25.786525 288 : 4361, 4137
7540 19:55:25.788522 292 : 4250, 4027
7541 19:55:25.788947 296 : 4250, 4026
7542 19:55:25.792498 300 : 4363, 4140
7543 19:55:25.793019 304 : 4250, 4027
7544 19:55:25.795537 308 : 4250, 4027
7545 19:55:25.796122 312 : 4250, 4026
7546 19:55:25.798658 316 : 4253, 4029
7547 19:55:25.799175 320 : 4250, 4027
7548 19:55:25.802608 324 : 4249, 4027
7549 19:55:25.803126 328 : 4360, 4137
7550 19:55:25.805441 332 : 4250, 4027
7551 19:55:25.805867 336 : 4250, 3621
7552 19:55:25.808661 340 : 4361, 1968
7553 19:55:25.809083
7554 19:55:25.809413 MIOCK jitter meter ch=0
7555 19:55:25.809724
7556 19:55:25.811655 1T = (340-92) = 248 dly cells
7557 19:55:25.818265 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7558 19:55:25.818781 ==
7559 19:55:25.821725 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 19:55:25.825582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 19:55:25.826096 ==
7562 19:55:25.831917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7563 19:55:25.835849 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7564 19:55:25.838641 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7565 19:55:25.844835 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7566 19:55:25.854473 [CA 0] Center 43 (12~74) winsize 63
7567 19:55:25.857775 [CA 1] Center 42 (12~73) winsize 62
7568 19:55:25.861025 [CA 2] Center 38 (9~68) winsize 60
7569 19:55:25.864005 [CA 3] Center 38 (8~68) winsize 61
7570 19:55:25.867817 [CA 4] Center 36 (7~66) winsize 60
7571 19:55:25.870539 [CA 5] Center 35 (6~65) winsize 60
7572 19:55:25.871073
7573 19:55:25.873926 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7574 19:55:25.874387
7575 19:55:25.880343 [CATrainingPosCal] consider 1 rank data
7576 19:55:25.880823 u2DelayCellTimex100 = 262/100 ps
7577 19:55:25.887256 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7578 19:55:25.890594 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7579 19:55:25.893902 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7580 19:55:25.897432 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7581 19:55:25.900447 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7582 19:55:25.903650 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7583 19:55:25.904293
7584 19:55:25.906906 CA PerBit enable=1, Macro0, CA PI delay=35
7585 19:55:25.907369
7586 19:55:25.909894 [CBTSetCACLKResult] CA Dly = 35
7587 19:55:25.913829 CS Dly: 11 (0~42)
7588 19:55:25.916687 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7589 19:55:25.919695 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7590 19:55:25.923055 ==
7591 19:55:25.923606 Dram Type= 6, Freq= 0, CH_0, rank 1
7592 19:55:25.930324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 19:55:25.930883 ==
7594 19:55:25.933231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7595 19:55:25.939839 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7596 19:55:25.943333 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7597 19:55:25.950040 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7598 19:55:25.958043 [CA 0] Center 42 (12~73) winsize 62
7599 19:55:25.961597 [CA 1] Center 43 (13~73) winsize 61
7600 19:55:25.965093 [CA 2] Center 37 (8~67) winsize 60
7601 19:55:25.967786 [CA 3] Center 37 (7~67) winsize 61
7602 19:55:25.971018 [CA 4] Center 35 (6~65) winsize 60
7603 19:55:25.974390 [CA 5] Center 35 (5~65) winsize 61
7604 19:55:25.975009
7605 19:55:25.977499 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7606 19:55:25.977998
7607 19:55:25.980688 [CATrainingPosCal] consider 2 rank data
7608 19:55:25.984077 u2DelayCellTimex100 = 262/100 ps
7609 19:55:25.990677 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7610 19:55:25.993845 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7611 19:55:25.997502 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7612 19:55:26.000468 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7613 19:55:26.003662 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7614 19:55:26.007139 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7615 19:55:26.007703
7616 19:55:26.010367 CA PerBit enable=1, Macro0, CA PI delay=35
7617 19:55:26.011009
7618 19:55:26.014612 [CBTSetCACLKResult] CA Dly = 35
7619 19:55:26.017239 CS Dly: 12 (0~44)
7620 19:55:26.020512 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7621 19:55:26.023626 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7622 19:55:26.024297
7623 19:55:26.026908 ----->DramcWriteLeveling(PI) begin...
7624 19:55:26.027495 ==
7625 19:55:26.029997 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 19:55:26.037064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 19:55:26.037694 ==
7628 19:55:26.040423 Write leveling (Byte 0): 36 => 36
7629 19:55:26.043637 Write leveling (Byte 1): 27 => 27
7630 19:55:26.044351 DramcWriteLeveling(PI) end<-----
7631 19:55:26.046911
7632 19:55:26.047432 ==
7633 19:55:26.049806 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 19:55:26.053264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 19:55:26.053827 ==
7636 19:55:26.057170 [Gating] SW mode calibration
7637 19:55:26.063676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7638 19:55:26.069617 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7639 19:55:26.073049 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 19:55:26.076867 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 19:55:26.082714 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 19:55:26.086122 1 4 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
7643 19:55:26.089460 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7644 19:55:26.096462 1 4 20 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7645 19:55:26.099445 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7646 19:55:26.102482 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7647 19:55:26.109431 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7648 19:55:26.112350 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7649 19:55:26.115750 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7650 19:55:26.122181 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7651 19:55:26.125805 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7652 19:55:26.128856 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
7653 19:55:26.135669 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7654 19:55:26.138792 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 19:55:26.142303 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 19:55:26.149257 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 19:55:26.152563 1 6 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7658 19:55:26.155661 1 6 12 | B1->B0 | 2323 3e3e | 0 1 | (0 0) (0 0)
7659 19:55:26.161995 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7660 19:55:26.165254 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7661 19:55:26.168311 1 6 24 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
7662 19:55:26.174997 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 19:55:26.177946 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 19:55:26.182073 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 19:55:26.184891 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 19:55:26.191660 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7667 19:55:26.194444 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7668 19:55:26.198318 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7669 19:55:26.205115 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 19:55:26.208096 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 19:55:26.211020 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 19:55:26.217797 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 19:55:26.220842 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 19:55:26.224667 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 19:55:26.231124 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 19:55:26.234506 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 19:55:26.237606 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 19:55:26.244392 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 19:55:26.247596 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 19:55:26.250958 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 19:55:26.257482 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7682 19:55:26.260629 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7683 19:55:26.264323 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7684 19:55:26.267023 Total UI for P1: 0, mck2ui 16
7685 19:55:26.270597 best dqsien dly found for B0: ( 1, 9, 10)
7686 19:55:26.277830 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7687 19:55:26.280630 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7688 19:55:26.283559 Total UI for P1: 0, mck2ui 16
7689 19:55:26.286947 best dqsien dly found for B1: ( 1, 9, 18)
7690 19:55:26.289977 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7691 19:55:26.293768 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7692 19:55:26.293869
7693 19:55:26.296650 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7694 19:55:26.303153 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7695 19:55:26.303254 [Gating] SW calibration Done
7696 19:55:26.306724 ==
7697 19:55:26.306826 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 19:55:26.313039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 19:55:26.313140 ==
7700 19:55:26.313234 RX Vref Scan: 0
7701 19:55:26.313323
7702 19:55:26.316462 RX Vref 0 -> 0, step: 1
7703 19:55:26.316561
7704 19:55:26.320141 RX Delay 0 -> 252, step: 8
7705 19:55:26.323160 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7706 19:55:26.326692 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7707 19:55:26.329700 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7708 19:55:26.336696 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7709 19:55:26.339867 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7710 19:55:26.343212 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7711 19:55:26.346252 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7712 19:55:26.349706 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7713 19:55:26.356087 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7714 19:55:26.359306 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7715 19:55:26.363238 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7716 19:55:26.366221 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7717 19:55:26.369069 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7718 19:55:26.375878 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7719 19:55:26.379143 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7720 19:55:26.383007 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7721 19:55:26.383108 ==
7722 19:55:26.385864 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 19:55:26.388931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 19:55:26.392662 ==
7725 19:55:26.392763 DQS Delay:
7726 19:55:26.392854 DQS0 = 0, DQS1 = 0
7727 19:55:26.395877 DQM Delay:
7728 19:55:26.395951 DQM0 = 136, DQM1 = 126
7729 19:55:26.399026 DQ Delay:
7730 19:55:26.402343 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7731 19:55:26.405498 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7732 19:55:26.409264 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7733 19:55:26.412430 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7734 19:55:26.412530
7735 19:55:26.412620
7736 19:55:26.412705 ==
7737 19:55:26.415665 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 19:55:26.419006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 19:55:26.422214 ==
7740 19:55:26.422314
7741 19:55:26.422407
7742 19:55:26.422495 TX Vref Scan disable
7743 19:55:26.425510 == TX Byte 0 ==
7744 19:55:26.428935 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7745 19:55:26.432016 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7746 19:55:26.435160 == TX Byte 1 ==
7747 19:55:26.438795 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7748 19:55:26.442224 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7749 19:55:26.445449 ==
7750 19:55:26.445549 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 19:55:26.451998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 19:55:26.452072 ==
7753 19:55:26.464498
7754 19:55:26.468172 TX Vref early break, caculate TX vref
7755 19:55:26.471975 TX Vref=16, minBit 1, minWin=22, winSum=367
7756 19:55:26.475234 TX Vref=18, minBit 0, minWin=23, winSum=379
7757 19:55:26.478455 TX Vref=20, minBit 1, minWin=23, winSum=388
7758 19:55:26.480894 TX Vref=22, minBit 1, minWin=24, winSum=403
7759 19:55:26.484217 TX Vref=24, minBit 0, minWin=25, winSum=411
7760 19:55:26.491050 TX Vref=26, minBit 2, minWin=25, winSum=413
7761 19:55:26.494630 TX Vref=28, minBit 4, minWin=25, winSum=415
7762 19:55:26.497670 TX Vref=30, minBit 0, minWin=25, winSum=412
7763 19:55:26.501111 TX Vref=32, minBit 0, minWin=24, winSum=402
7764 19:55:26.504139 TX Vref=34, minBit 0, minWin=24, winSum=392
7765 19:55:26.510798 [TxChooseVref] Worse bit 4, Min win 25, Win sum 415, Final Vref 28
7766 19:55:26.510881
7767 19:55:26.514198 Final TX Range 0 Vref 28
7768 19:55:26.514299
7769 19:55:26.514390 ==
7770 19:55:26.517796 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 19:55:26.520789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 19:55:26.520888 ==
7773 19:55:26.520978
7774 19:55:26.521063
7775 19:55:26.524298 TX Vref Scan disable
7776 19:55:26.530610 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7777 19:55:26.530713 == TX Byte 0 ==
7778 19:55:26.533717 u2DelayCellOfst[0]=18 cells (5 PI)
7779 19:55:26.537026 u2DelayCellOfst[1]=18 cells (5 PI)
7780 19:55:26.540571 u2DelayCellOfst[2]=14 cells (4 PI)
7781 19:55:26.543958 u2DelayCellOfst[3]=14 cells (4 PI)
7782 19:55:26.546873 u2DelayCellOfst[4]=11 cells (3 PI)
7783 19:55:26.550472 u2DelayCellOfst[5]=0 cells (0 PI)
7784 19:55:26.554024 u2DelayCellOfst[6]=18 cells (5 PI)
7785 19:55:26.557119 u2DelayCellOfst[7]=22 cells (6 PI)
7786 19:55:26.560430 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7787 19:55:26.563637 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7788 19:55:26.566668 == TX Byte 1 ==
7789 19:55:26.570294 u2DelayCellOfst[8]=0 cells (0 PI)
7790 19:55:26.573409 u2DelayCellOfst[9]=0 cells (0 PI)
7791 19:55:26.577248 u2DelayCellOfst[10]=3 cells (1 PI)
7792 19:55:26.577347 u2DelayCellOfst[11]=0 cells (0 PI)
7793 19:55:26.580347 u2DelayCellOfst[12]=11 cells (3 PI)
7794 19:55:26.583634 u2DelayCellOfst[13]=7 cells (2 PI)
7795 19:55:26.587074 u2DelayCellOfst[14]=11 cells (3 PI)
7796 19:55:26.590108 u2DelayCellOfst[15]=11 cells (3 PI)
7797 19:55:26.596331 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7798 19:55:26.599640 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7799 19:55:26.599749 DramC Write-DBI on
7800 19:55:26.603132 ==
7801 19:55:26.603231 Dram Type= 6, Freq= 0, CH_0, rank 0
7802 19:55:26.609975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7803 19:55:26.610080 ==
7804 19:55:26.610180
7805 19:55:26.610268
7806 19:55:26.613173 TX Vref Scan disable
7807 19:55:26.613278 == TX Byte 0 ==
7808 19:55:26.619656 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7809 19:55:26.619797 == TX Byte 1 ==
7810 19:55:26.623133 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7811 19:55:26.626483 DramC Write-DBI off
7812 19:55:26.626586
7813 19:55:26.626676 [DATLAT]
7814 19:55:26.629855 Freq=1600, CH0 RK0
7815 19:55:26.629953
7816 19:55:26.630053 DATLAT Default: 0xf
7817 19:55:26.633047 0, 0xFFFF, sum = 0
7818 19:55:26.633147 1, 0xFFFF, sum = 0
7819 19:55:26.636019 2, 0xFFFF, sum = 0
7820 19:55:26.636120 3, 0xFFFF, sum = 0
7821 19:55:26.639290 4, 0xFFFF, sum = 0
7822 19:55:26.639400 5, 0xFFFF, sum = 0
7823 19:55:26.642840 6, 0xFFFF, sum = 0
7824 19:55:26.645981 7, 0xFFFF, sum = 0
7825 19:55:26.646088 8, 0xFFFF, sum = 0
7826 19:55:26.649334 9, 0xFFFF, sum = 0
7827 19:55:26.649441 10, 0xFFFF, sum = 0
7828 19:55:26.652683 11, 0xFFFF, sum = 0
7829 19:55:26.652758 12, 0xFFFF, sum = 0
7830 19:55:26.655731 13, 0xFFFF, sum = 0
7831 19:55:26.655808 14, 0x0, sum = 1
7832 19:55:26.658979 15, 0x0, sum = 2
7833 19:55:26.659088 16, 0x0, sum = 3
7834 19:55:26.662808 17, 0x0, sum = 4
7835 19:55:26.662907 best_step = 15
7836 19:55:26.663006
7837 19:55:26.663094 ==
7838 19:55:26.665987 Dram Type= 6, Freq= 0, CH_0, rank 0
7839 19:55:26.672123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7840 19:55:26.672198 ==
7841 19:55:26.672260 RX Vref Scan: 1
7842 19:55:26.672329
7843 19:55:26.675345 Set Vref Range= 24 -> 127
7844 19:55:26.675442
7845 19:55:26.678616 RX Vref 24 -> 127, step: 1
7846 19:55:26.678715
7847 19:55:26.678815 RX Delay 19 -> 252, step: 4
7848 19:55:26.678905
7849 19:55:26.681834 Set Vref, RX VrefLevel [Byte0]: 24
7850 19:55:26.685453 [Byte1]: 24
7851 19:55:26.689518
7852 19:55:26.689626 Set Vref, RX VrefLevel [Byte0]: 25
7853 19:55:26.692480 [Byte1]: 25
7854 19:55:26.696801
7855 19:55:26.696899 Set Vref, RX VrefLevel [Byte0]: 26
7856 19:55:26.700183 [Byte1]: 26
7857 19:55:26.704566
7858 19:55:26.704682 Set Vref, RX VrefLevel [Byte0]: 27
7859 19:55:26.707691 [Byte1]: 27
7860 19:55:26.711929
7861 19:55:26.712005 Set Vref, RX VrefLevel [Byte0]: 28
7862 19:55:26.715207 [Byte1]: 28
7863 19:55:26.719503
7864 19:55:26.719604 Set Vref, RX VrefLevel [Byte0]: 29
7865 19:55:26.722901 [Byte1]: 29
7866 19:55:26.726923
7867 19:55:26.727025 Set Vref, RX VrefLevel [Byte0]: 30
7868 19:55:26.730205 [Byte1]: 30
7869 19:55:26.734681
7870 19:55:26.734817 Set Vref, RX VrefLevel [Byte0]: 31
7871 19:55:26.737821 [Byte1]: 31
7872 19:55:26.742416
7873 19:55:26.742524 Set Vref, RX VrefLevel [Byte0]: 32
7874 19:55:26.745824 [Byte1]: 32
7875 19:55:26.749824
7876 19:55:26.749924 Set Vref, RX VrefLevel [Byte0]: 33
7877 19:55:26.753039 [Byte1]: 33
7878 19:55:26.757998
7879 19:55:26.758101 Set Vref, RX VrefLevel [Byte0]: 34
7880 19:55:26.763766 [Byte1]: 34
7881 19:55:26.763864
7882 19:55:26.767549 Set Vref, RX VrefLevel [Byte0]: 35
7883 19:55:26.770935 [Byte1]: 35
7884 19:55:26.771034
7885 19:55:26.774765 Set Vref, RX VrefLevel [Byte0]: 36
7886 19:55:26.777661 [Byte1]: 36
7887 19:55:26.777759
7888 19:55:26.780532 Set Vref, RX VrefLevel [Byte0]: 37
7889 19:55:26.783590 [Byte1]: 37
7890 19:55:26.787732
7891 19:55:26.787835 Set Vref, RX VrefLevel [Byte0]: 38
7892 19:55:26.791364 [Byte1]: 38
7893 19:55:26.795691
7894 19:55:26.795798 Set Vref, RX VrefLevel [Byte0]: 39
7895 19:55:26.798657 [Byte1]: 39
7896 19:55:26.803465
7897 19:55:26.803564 Set Vref, RX VrefLevel [Byte0]: 40
7898 19:55:26.806049 [Byte1]: 40
7899 19:55:26.810652
7900 19:55:26.810756 Set Vref, RX VrefLevel [Byte0]: 41
7901 19:55:26.813732 [Byte1]: 41
7902 19:55:26.817937
7903 19:55:26.818036 Set Vref, RX VrefLevel [Byte0]: 42
7904 19:55:26.822031 [Byte1]: 42
7905 19:55:26.825845
7906 19:55:26.825944 Set Vref, RX VrefLevel [Byte0]: 43
7907 19:55:26.828878 [Byte1]: 43
7908 19:55:26.833265
7909 19:55:26.833361 Set Vref, RX VrefLevel [Byte0]: 44
7910 19:55:26.836951 [Byte1]: 44
7911 19:55:26.841063
7912 19:55:26.841161 Set Vref, RX VrefLevel [Byte0]: 45
7913 19:55:26.843846 [Byte1]: 45
7914 19:55:26.848355
7915 19:55:26.848430 Set Vref, RX VrefLevel [Byte0]: 46
7916 19:55:26.852127 [Byte1]: 46
7917 19:55:26.855668
7918 19:55:26.855775 Set Vref, RX VrefLevel [Byte0]: 47
7919 19:55:26.859413 [Byte1]: 47
7920 19:55:26.863677
7921 19:55:26.863783 Set Vref, RX VrefLevel [Byte0]: 48
7922 19:55:26.866931 [Byte1]: 48
7923 19:55:26.871459
7924 19:55:26.871556 Set Vref, RX VrefLevel [Byte0]: 49
7925 19:55:26.874306 [Byte1]: 49
7926 19:55:26.878723
7927 19:55:26.878818 Set Vref, RX VrefLevel [Byte0]: 50
7928 19:55:26.882036 [Byte1]: 50
7929 19:55:26.886421
7930 19:55:26.886521 Set Vref, RX VrefLevel [Byte0]: 51
7931 19:55:26.889832 [Byte1]: 51
7932 19:55:26.893800
7933 19:55:26.893899 Set Vref, RX VrefLevel [Byte0]: 52
7934 19:55:26.896931 [Byte1]: 52
7935 19:55:26.901605
7936 19:55:26.901705 Set Vref, RX VrefLevel [Byte0]: 53
7937 19:55:26.905285 [Byte1]: 53
7938 19:55:26.908689
7939 19:55:26.908792 Set Vref, RX VrefLevel [Byte0]: 54
7940 19:55:26.912491 [Byte1]: 54
7941 19:55:26.916344
7942 19:55:26.916443 Set Vref, RX VrefLevel [Byte0]: 55
7943 19:55:26.920067 [Byte1]: 55
7944 19:55:26.924353
7945 19:55:26.924454 Set Vref, RX VrefLevel [Byte0]: 56
7946 19:55:26.927347 [Byte1]: 56
7947 19:55:26.931499
7948 19:55:26.931599 Set Vref, RX VrefLevel [Byte0]: 57
7949 19:55:26.934793 [Byte1]: 57
7950 19:55:26.939447
7951 19:55:26.939546 Set Vref, RX VrefLevel [Byte0]: 58
7952 19:55:26.942408 [Byte1]: 58
7953 19:55:26.947274
7954 19:55:26.947375 Set Vref, RX VrefLevel [Byte0]: 59
7955 19:55:26.950549 [Byte1]: 59
7956 19:55:26.954545
7957 19:55:26.954643 Set Vref, RX VrefLevel [Byte0]: 60
7958 19:55:26.957643 [Byte1]: 60
7959 19:55:26.961889
7960 19:55:26.961988 Set Vref, RX VrefLevel [Byte0]: 61
7961 19:55:26.965129 [Byte1]: 61
7962 19:55:26.969677
7963 19:55:26.969786 Set Vref, RX VrefLevel [Byte0]: 62
7964 19:55:26.972678 [Byte1]: 62
7965 19:55:26.977147
7966 19:55:26.977258 Set Vref, RX VrefLevel [Byte0]: 63
7967 19:55:26.980438 [Byte1]: 63
7968 19:55:26.984454
7969 19:55:26.984562 Set Vref, RX VrefLevel [Byte0]: 64
7970 19:55:26.987789 [Byte1]: 64
7971 19:55:26.992248
7972 19:55:26.995439 Set Vref, RX VrefLevel [Byte0]: 65
7973 19:55:26.998620 [Byte1]: 65
7974 19:55:26.998725
7975 19:55:27.002200 Set Vref, RX VrefLevel [Byte0]: 66
7976 19:55:27.005328 [Byte1]: 66
7977 19:55:27.005433
7978 19:55:27.008509 Set Vref, RX VrefLevel [Byte0]: 67
7979 19:55:27.012222 [Byte1]: 67
7980 19:55:27.012330
7981 19:55:27.015337 Set Vref, RX VrefLevel [Byte0]: 68
7982 19:55:27.018944 [Byte1]: 68
7983 19:55:27.022388
7984 19:55:27.022486 Set Vref, RX VrefLevel [Byte0]: 69
7985 19:55:27.025548 [Byte1]: 69
7986 19:55:27.030000
7987 19:55:27.030098 Set Vref, RX VrefLevel [Byte0]: 70
7988 19:55:27.033093 [Byte1]: 70
7989 19:55:27.037764
7990 19:55:27.037855 Set Vref, RX VrefLevel [Byte0]: 71
7991 19:55:27.041262 [Byte1]: 71
7992 19:55:27.044978
7993 19:55:27.045075 Set Vref, RX VrefLevel [Byte0]: 72
7994 19:55:27.048868 [Byte1]: 72
7995 19:55:27.052997
7996 19:55:27.053100 Set Vref, RX VrefLevel [Byte0]: 73
7997 19:55:27.055997 [Byte1]: 73
7998 19:55:27.060456
7999 19:55:27.060558 Set Vref, RX VrefLevel [Byte0]: 74
8000 19:55:27.063516 [Byte1]: 74
8001 19:55:27.068321
8002 19:55:27.068416 Set Vref, RX VrefLevel [Byte0]: 75
8003 19:55:27.071144 [Byte1]: 75
8004 19:55:27.075597
8005 19:55:27.075698 Set Vref, RX VrefLevel [Byte0]: 76
8006 19:55:27.078807 [Byte1]: 76
8007 19:55:27.083177
8008 19:55:27.083274 Set Vref, RX VrefLevel [Byte0]: 77
8009 19:55:27.086532 [Byte1]: 77
8010 19:55:27.090450
8011 19:55:27.090559 Final RX Vref Byte 0 = 68 to rank0
8012 19:55:27.094368 Final RX Vref Byte 1 = 57 to rank0
8013 19:55:27.097163 Final RX Vref Byte 0 = 68 to rank1
8014 19:55:27.100484 Final RX Vref Byte 1 = 57 to rank1==
8015 19:55:27.104042 Dram Type= 6, Freq= 0, CH_0, rank 0
8016 19:55:27.110495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 19:55:27.110605 ==
8018 19:55:27.110700 DQS Delay:
8019 19:55:27.110787 DQS0 = 0, DQS1 = 0
8020 19:55:27.113981 DQM Delay:
8021 19:55:27.114086 DQM0 = 134, DQM1 = 123
8022 19:55:27.117233 DQ Delay:
8023 19:55:27.120309 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =134
8024 19:55:27.123844 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =144
8025 19:55:27.127457 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =118
8026 19:55:27.130690 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
8027 19:55:27.130790
8028 19:55:27.130880
8029 19:55:27.130965
8030 19:55:27.133613 [DramC_TX_OE_Calibration] TA2
8031 19:55:27.136984 Original DQ_B0 (3 6) =30, OEN = 27
8032 19:55:27.140371 Original DQ_B1 (3 6) =30, OEN = 27
8033 19:55:27.143601 24, 0x0, End_B0=24 End_B1=24
8034 19:55:27.143700 25, 0x0, End_B0=25 End_B1=25
8035 19:55:27.147646 26, 0x0, End_B0=26 End_B1=26
8036 19:55:27.150489 27, 0x0, End_B0=27 End_B1=27
8037 19:55:27.153928 28, 0x0, End_B0=28 End_B1=28
8038 19:55:27.157012 29, 0x0, End_B0=29 End_B1=29
8039 19:55:27.157100 30, 0x0, End_B0=30 End_B1=30
8040 19:55:27.160164 31, 0x4141, End_B0=30 End_B1=30
8041 19:55:27.163638 Byte0 end_step=30 best_step=27
8042 19:55:27.166600 Byte1 end_step=30 best_step=27
8043 19:55:27.170461 Byte0 TX OE(2T, 0.5T) = (3, 3)
8044 19:55:27.173562 Byte1 TX OE(2T, 0.5T) = (3, 3)
8045 19:55:27.173642
8046 19:55:27.173706
8047 19:55:27.179655 [DQSOSCAuto] RK0, (LSB)MR18= 0x2113, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8048 19:55:27.183327 CH0 RK0: MR19=303, MR18=2113
8049 19:55:27.189780 CH0_RK0: MR19=0x303, MR18=0x2113, DQSOSC=393, MR23=63, INC=23, DEC=15
8050 19:55:27.189861
8051 19:55:27.192886 ----->DramcWriteLeveling(PI) begin...
8052 19:55:27.192968 ==
8053 19:55:27.196624 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 19:55:27.199614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 19:55:27.199742 ==
8056 19:55:27.202939 Write leveling (Byte 0): 35 => 35
8057 19:55:27.206173 Write leveling (Byte 1): 27 => 27
8058 19:55:27.209830 DramcWriteLeveling(PI) end<-----
8059 19:55:27.209917
8060 19:55:27.209980 ==
8061 19:55:27.212967 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 19:55:27.216096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 19:55:27.219482 ==
8064 19:55:27.219588 [Gating] SW mode calibration
8065 19:55:27.226094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8066 19:55:27.232534 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8067 19:55:27.235889 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 19:55:27.242596 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 19:55:27.246105 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 19:55:27.249289 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 19:55:27.255578 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
8072 19:55:27.258838 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8073 19:55:27.262265 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 19:55:27.268659 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 19:55:27.271788 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8076 19:55:27.275547 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8077 19:55:27.281835 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8078 19:55:27.285649 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
8079 19:55:27.288565 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8080 19:55:27.294903 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8081 19:55:27.298297 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 19:55:27.301673 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 19:55:27.308346 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 19:55:27.311324 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 19:55:27.314811 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 19:55:27.321381 1 6 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8087 19:55:27.324584 1 6 16 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
8088 19:55:27.328057 1 6 20 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
8089 19:55:27.334828 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 19:55:27.337820 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 19:55:27.341190 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 19:55:27.347580 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 19:55:27.351549 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8094 19:55:27.354512 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8095 19:55:27.360937 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8096 19:55:27.364140 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 19:55:27.367792 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8098 19:55:27.374492 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 19:55:27.377574 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 19:55:27.380955 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 19:55:27.387648 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 19:55:27.390738 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 19:55:27.394152 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 19:55:27.401035 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 19:55:27.403984 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 19:55:27.407359 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 19:55:27.413917 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 19:55:27.417216 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 19:55:27.420481 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8110 19:55:27.428907 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8111 19:55:27.430561 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8112 19:55:27.433582 Total UI for P1: 0, mck2ui 16
8113 19:55:27.436876 best dqsien dly found for B0: ( 1, 9, 10)
8114 19:55:27.440322 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8115 19:55:27.446693 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 19:55:27.446793 Total UI for P1: 0, mck2ui 16
8117 19:55:27.453599 best dqsien dly found for B1: ( 1, 9, 18)
8118 19:55:27.456907 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8119 19:55:27.460445 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8120 19:55:27.460518
8121 19:55:27.463525 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8122 19:55:27.466922 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8123 19:55:27.469954 [Gating] SW calibration Done
8124 19:55:27.470052 ==
8125 19:55:27.473021 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 19:55:27.476334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 19:55:27.476433 ==
8128 19:55:27.479947 RX Vref Scan: 0
8129 19:55:27.480021
8130 19:55:27.483344 RX Vref 0 -> 0, step: 1
8131 19:55:27.483440
8132 19:55:27.483532 RX Delay 0 -> 252, step: 8
8133 19:55:27.489838 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8134 19:55:27.493443 iDelay=208, Bit 1, Center 139 (80 ~ 199) 120
8135 19:55:27.496369 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8136 19:55:27.499519 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
8137 19:55:27.502809 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8138 19:55:27.510249 iDelay=208, Bit 5, Center 123 (64 ~ 183) 120
8139 19:55:27.512733 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
8140 19:55:27.516060 iDelay=208, Bit 7, Center 147 (88 ~ 207) 120
8141 19:55:27.519929 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8142 19:55:27.522872 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8143 19:55:27.529351 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8144 19:55:27.532477 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8145 19:55:27.536127 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8146 19:55:27.539092 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8147 19:55:27.545706 iDelay=208, Bit 14, Center 143 (88 ~ 199) 112
8148 19:55:27.549286 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8149 19:55:27.549386 ==
8150 19:55:27.552079 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 19:55:27.555604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 19:55:27.555700 ==
8153 19:55:27.559234 DQS Delay:
8154 19:55:27.559332 DQS0 = 0, DQS1 = 0
8155 19:55:27.559420 DQM Delay:
8156 19:55:27.562021 DQM0 = 134, DQM1 = 129
8157 19:55:27.562118 DQ Delay:
8158 19:55:27.565812 DQ0 =135, DQ1 =139, DQ2 =127, DQ3 =127
8159 19:55:27.568745 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
8160 19:55:27.572361 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =127
8161 19:55:27.578740 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8162 19:55:27.578842
8163 19:55:27.578933
8164 19:55:27.579019 ==
8165 19:55:27.582140 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 19:55:27.585323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 19:55:27.585422 ==
8168 19:55:27.585513
8169 19:55:27.585601
8170 19:55:27.588525 TX Vref Scan disable
8171 19:55:27.588619 == TX Byte 0 ==
8172 19:55:27.594941 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8173 19:55:27.598546 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8174 19:55:27.601894 == TX Byte 1 ==
8175 19:55:27.604950 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8176 19:55:27.608672 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8177 19:55:27.608774 ==
8178 19:55:27.611590 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 19:55:27.614570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 19:55:27.617967 ==
8181 19:55:27.629684
8182 19:55:27.633184 TX Vref early break, caculate TX vref
8183 19:55:27.636304 TX Vref=16, minBit 1, minWin=22, winSum=375
8184 19:55:27.639690 TX Vref=18, minBit 0, minWin=23, winSum=389
8185 19:55:27.643144 TX Vref=20, minBit 0, minWin=23, winSum=390
8186 19:55:27.646628 TX Vref=22, minBit 1, minWin=22, winSum=396
8187 19:55:27.649707 TX Vref=24, minBit 1, minWin=24, winSum=407
8188 19:55:27.656524 TX Vref=26, minBit 1, minWin=24, winSum=415
8189 19:55:27.659665 TX Vref=28, minBit 0, minWin=24, winSum=411
8190 19:55:27.663175 TX Vref=30, minBit 0, minWin=24, winSum=404
8191 19:55:27.666274 TX Vref=32, minBit 7, minWin=23, winSum=394
8192 19:55:27.669538 TX Vref=34, minBit 0, minWin=23, winSum=383
8193 19:55:27.676095 [TxChooseVref] Worse bit 1, Min win 24, Win sum 415, Final Vref 26
8194 19:55:27.676197
8195 19:55:27.679384 Final TX Range 0 Vref 26
8196 19:55:27.679484
8197 19:55:27.679583 ==
8198 19:55:27.682528 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 19:55:27.685763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 19:55:27.685866 ==
8201 19:55:27.685958
8202 19:55:27.686047
8203 19:55:27.689078 TX Vref Scan disable
8204 19:55:27.696003 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8205 19:55:27.696103 == TX Byte 0 ==
8206 19:55:27.698838 u2DelayCellOfst[0]=11 cells (3 PI)
8207 19:55:27.702203 u2DelayCellOfst[1]=14 cells (4 PI)
8208 19:55:27.706053 u2DelayCellOfst[2]=11 cells (3 PI)
8209 19:55:27.708752 u2DelayCellOfst[3]=11 cells (3 PI)
8210 19:55:27.712073 u2DelayCellOfst[4]=7 cells (2 PI)
8211 19:55:27.715556 u2DelayCellOfst[5]=0 cells (0 PI)
8212 19:55:27.718870 u2DelayCellOfst[6]=14 cells (4 PI)
8213 19:55:27.722395 u2DelayCellOfst[7]=18 cells (5 PI)
8214 19:55:27.725392 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8215 19:55:27.728713 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8216 19:55:27.731674 == TX Byte 1 ==
8217 19:55:27.735408 u2DelayCellOfst[8]=0 cells (0 PI)
8218 19:55:27.738908 u2DelayCellOfst[9]=0 cells (0 PI)
8219 19:55:27.741645 u2DelayCellOfst[10]=7 cells (2 PI)
8220 19:55:27.741746 u2DelayCellOfst[11]=3 cells (1 PI)
8221 19:55:27.744951 u2DelayCellOfst[12]=11 cells (3 PI)
8222 19:55:27.748480 u2DelayCellOfst[13]=11 cells (3 PI)
8223 19:55:27.751747 u2DelayCellOfst[14]=14 cells (4 PI)
8224 19:55:27.754910 u2DelayCellOfst[15]=11 cells (3 PI)
8225 19:55:27.761489 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8226 19:55:27.764865 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8227 19:55:27.764963 DramC Write-DBI on
8228 19:55:27.768241 ==
8229 19:55:27.768313 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 19:55:27.774720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 19:55:27.774823 ==
8232 19:55:27.774898
8233 19:55:27.774986
8234 19:55:27.778029 TX Vref Scan disable
8235 19:55:27.778136 == TX Byte 0 ==
8236 19:55:27.785007 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8237 19:55:27.785106 == TX Byte 1 ==
8238 19:55:27.788376 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8239 19:55:27.791438 DramC Write-DBI off
8240 19:55:27.791536
8241 19:55:27.791628 [DATLAT]
8242 19:55:27.794895 Freq=1600, CH0 RK1
8243 19:55:27.794997
8244 19:55:27.795087 DATLAT Default: 0xf
8245 19:55:27.798024 0, 0xFFFF, sum = 0
8246 19:55:27.798124 1, 0xFFFF, sum = 0
8247 19:55:27.801213 2, 0xFFFF, sum = 0
8248 19:55:27.801311 3, 0xFFFF, sum = 0
8249 19:55:27.804769 4, 0xFFFF, sum = 0
8250 19:55:27.804873 5, 0xFFFF, sum = 0
8251 19:55:27.807972 6, 0xFFFF, sum = 0
8252 19:55:27.808045 7, 0xFFFF, sum = 0
8253 19:55:27.811278 8, 0xFFFF, sum = 0
8254 19:55:27.814504 9, 0xFFFF, sum = 0
8255 19:55:27.814626 10, 0xFFFF, sum = 0
8256 19:55:27.817610 11, 0xFFFF, sum = 0
8257 19:55:27.817715 12, 0xFFFF, sum = 0
8258 19:55:27.821032 13, 0xFFFF, sum = 0
8259 19:55:27.821136 14, 0x0, sum = 1
8260 19:55:27.824472 15, 0x0, sum = 2
8261 19:55:27.824593 16, 0x0, sum = 3
8262 19:55:27.828119 17, 0x0, sum = 4
8263 19:55:27.828222 best_step = 15
8264 19:55:27.828311
8265 19:55:27.828400 ==
8266 19:55:27.830858 Dram Type= 6, Freq= 0, CH_0, rank 1
8267 19:55:27.834010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 19:55:27.837658 ==
8269 19:55:27.837759 RX Vref Scan: 0
8270 19:55:27.837848
8271 19:55:27.840827 RX Vref 0 -> 0, step: 1
8272 19:55:27.840928
8273 19:55:27.841020 RX Delay 11 -> 252, step: 4
8274 19:55:27.848560 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8275 19:55:27.851672 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8276 19:55:27.854732 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8277 19:55:27.858212 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8278 19:55:27.864801 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8279 19:55:27.867898 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8280 19:55:27.870936 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8281 19:55:27.874368 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8282 19:55:27.878323 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8283 19:55:27.884435 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8284 19:55:27.887744 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8285 19:55:27.891120 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8286 19:55:27.895313 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8287 19:55:27.897525 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8288 19:55:27.904087 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8289 19:55:27.907514 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8290 19:55:27.907612 ==
8291 19:55:27.910690 Dram Type= 6, Freq= 0, CH_0, rank 1
8292 19:55:27.914140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 19:55:27.914239 ==
8294 19:55:27.916908 DQS Delay:
8295 19:55:27.917005 DQS0 = 0, DQS1 = 0
8296 19:55:27.920680 DQM Delay:
8297 19:55:27.920775 DQM0 = 130, DQM1 = 125
8298 19:55:27.920863 DQ Delay:
8299 19:55:27.927112 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8300 19:55:27.930177 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =140
8301 19:55:27.933722 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8302 19:55:27.937294 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8303 19:55:27.937390
8304 19:55:27.937477
8305 19:55:27.937566
8306 19:55:27.940085 [DramC_TX_OE_Calibration] TA2
8307 19:55:27.943502 Original DQ_B0 (3 6) =30, OEN = 27
8308 19:55:27.946696 Original DQ_B1 (3 6) =30, OEN = 27
8309 19:55:27.946805 24, 0x0, End_B0=24 End_B1=24
8310 19:55:27.950315 25, 0x0, End_B0=25 End_B1=25
8311 19:55:27.953311 26, 0x0, End_B0=26 End_B1=26
8312 19:55:27.956925 27, 0x0, End_B0=27 End_B1=27
8313 19:55:27.959939 28, 0x0, End_B0=28 End_B1=28
8314 19:55:27.960037 29, 0x0, End_B0=29 End_B1=29
8315 19:55:27.963556 30, 0x0, End_B0=30 End_B1=30
8316 19:55:27.967009 31, 0x4545, End_B0=30 End_B1=30
8317 19:55:27.969930 Byte0 end_step=30 best_step=27
8318 19:55:27.973380 Byte1 end_step=30 best_step=27
8319 19:55:27.976576 Byte0 TX OE(2T, 0.5T) = (3, 3)
8320 19:55:27.976647 Byte1 TX OE(2T, 0.5T) = (3, 3)
8321 19:55:27.976708
8322 19:55:27.976771
8323 19:55:27.986918 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8324 19:55:27.989930 CH0 RK1: MR19=303, MR18=2104
8325 19:55:27.996744 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8326 19:55:27.999897 [RxdqsGatingPostProcess] freq 1600
8327 19:55:28.003390 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8328 19:55:28.007514 best DQS0 dly(2T, 0.5T) = (1, 1)
8329 19:55:28.009705 best DQS1 dly(2T, 0.5T) = (1, 1)
8330 19:55:28.012991 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8331 19:55:28.016169 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8332 19:55:28.019362 best DQS0 dly(2T, 0.5T) = (1, 1)
8333 19:55:28.022978 best DQS1 dly(2T, 0.5T) = (1, 1)
8334 19:55:28.026122 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8335 19:55:28.029248 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8336 19:55:28.033067 Pre-setting of DQS Precalculation
8337 19:55:28.036684 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8338 19:55:28.036758 ==
8339 19:55:28.039366 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 19:55:28.042665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 19:55:28.042763 ==
8342 19:55:28.049044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8343 19:55:28.052634 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8344 19:55:28.059271 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8345 19:55:28.062599 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8346 19:55:28.072544 [CA 0] Center 42 (13~72) winsize 60
8347 19:55:28.076071 [CA 1] Center 42 (13~72) winsize 60
8348 19:55:28.079035 [CA 2] Center 38 (9~67) winsize 59
8349 19:55:28.082471 [CA 3] Center 37 (8~66) winsize 59
8350 19:55:28.085452 [CA 4] Center 37 (8~67) winsize 60
8351 19:55:28.089205 [CA 5] Center 37 (8~67) winsize 60
8352 19:55:28.089303
8353 19:55:28.092416 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8354 19:55:28.092509
8355 19:55:28.098478 [CATrainingPosCal] consider 1 rank data
8356 19:55:28.098575 u2DelayCellTimex100 = 262/100 ps
8357 19:55:28.105110 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8358 19:55:28.108435 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8359 19:55:28.112087 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8360 19:55:28.115283 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8361 19:55:28.118519 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8362 19:55:28.121959 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8363 19:55:28.122054
8364 19:55:28.124933 CA PerBit enable=1, Macro0, CA PI delay=37
8365 19:55:28.125029
8366 19:55:28.128198 [CBTSetCACLKResult] CA Dly = 37
8367 19:55:28.132149 CS Dly: 9 (0~40)
8368 19:55:28.135412 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8369 19:55:28.138588 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8370 19:55:28.138684 ==
8371 19:55:28.142065 Dram Type= 6, Freq= 0, CH_1, rank 1
8372 19:55:28.148370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 19:55:28.148440 ==
8374 19:55:28.151644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8375 19:55:28.158050 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8376 19:55:28.161218 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8377 19:55:28.167964 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8378 19:55:28.175778 [CA 0] Center 43 (14~72) winsize 59
8379 19:55:28.178946 [CA 1] Center 42 (13~72) winsize 60
8380 19:55:28.182621 [CA 2] Center 37 (8~67) winsize 60
8381 19:55:28.185323 [CA 3] Center 37 (8~67) winsize 60
8382 19:55:28.189345 [CA 4] Center 38 (9~67) winsize 59
8383 19:55:28.192163 [CA 5] Center 37 (8~67) winsize 60
8384 19:55:28.192255
8385 19:55:28.195464 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8386 19:55:28.195559
8387 19:55:28.199324 [CATrainingPosCal] consider 2 rank data
8388 19:55:28.202386 u2DelayCellTimex100 = 262/100 ps
8389 19:55:28.208585 CA0 delay=43 (14~72),Diff = 6 PI (22 cell)
8390 19:55:28.211829 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8391 19:55:28.215323 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8392 19:55:28.218807 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8393 19:55:28.222130 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8394 19:55:28.225067 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8395 19:55:28.225163
8396 19:55:28.228388 CA PerBit enable=1, Macro0, CA PI delay=37
8397 19:55:28.228471
8398 19:55:28.231885 [CBTSetCACLKResult] CA Dly = 37
8399 19:55:28.235208 CS Dly: 11 (0~44)
8400 19:55:28.238545 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8401 19:55:28.241434 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8402 19:55:28.241533
8403 19:55:28.244813 ----->DramcWriteLeveling(PI) begin...
8404 19:55:28.244901 ==
8405 19:55:28.248076 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 19:55:28.254578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 19:55:28.254677 ==
8408 19:55:28.257704 Write leveling (Byte 0): 24 => 24
8409 19:55:28.261677 Write leveling (Byte 1): 27 => 27
8410 19:55:28.264517 DramcWriteLeveling(PI) end<-----
8411 19:55:28.264610
8412 19:55:28.264696 ==
8413 19:55:28.267819 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 19:55:28.270929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 19:55:28.271023 ==
8416 19:55:28.274154 [Gating] SW mode calibration
8417 19:55:28.281117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8418 19:55:28.287470 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8419 19:55:28.291000 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 19:55:28.294215 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 19:55:28.301013 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8422 19:55:28.304531 1 4 12 | B1->B0 | 2c2c 3232 | 0 0 | (0 0) (0 0)
8423 19:55:28.307490 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 19:55:28.314035 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 19:55:28.317770 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 19:55:28.320839 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 19:55:28.323975 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 19:55:28.330818 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 19:55:28.333737 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 19:55:28.337494 1 5 12 | B1->B0 | 3131 2626 | 0 0 | (0 0) (0 0)
8431 19:55:28.343750 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8432 19:55:28.347372 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 19:55:28.350355 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 19:55:28.356895 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 19:55:28.360580 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 19:55:28.363616 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 19:55:28.369849 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 19:55:28.373304 1 6 12 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
8439 19:55:28.377226 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 19:55:28.383460 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 19:55:28.386729 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 19:55:28.390858 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 19:55:28.396260 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 19:55:28.399806 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 19:55:28.402988 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 19:55:28.409533 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8447 19:55:28.413010 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8448 19:55:28.416182 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 19:55:28.423008 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 19:55:28.426749 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 19:55:28.429565 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 19:55:28.436240 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 19:55:28.439374 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 19:55:28.442684 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 19:55:28.449131 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 19:55:28.452464 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 19:55:28.456300 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 19:55:28.462795 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 19:55:28.466159 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 19:55:28.468891 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 19:55:28.475486 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8462 19:55:28.478858 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8463 19:55:28.482590 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 19:55:28.486095 Total UI for P1: 0, mck2ui 16
8465 19:55:28.489042 best dqsien dly found for B0: ( 1, 9, 10)
8466 19:55:28.492082 Total UI for P1: 0, mck2ui 16
8467 19:55:28.495690 best dqsien dly found for B1: ( 1, 9, 10)
8468 19:55:28.499056 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8469 19:55:28.505235 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8470 19:55:28.505315
8471 19:55:28.508681 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8472 19:55:28.511931 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8473 19:55:28.515462 [Gating] SW calibration Done
8474 19:55:28.515541 ==
8475 19:55:28.519100 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 19:55:28.521839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 19:55:28.521920 ==
8478 19:55:28.525472 RX Vref Scan: 0
8479 19:55:28.525553
8480 19:55:28.525616 RX Vref 0 -> 0, step: 1
8481 19:55:28.525675
8482 19:55:28.528296 RX Delay 0 -> 252, step: 8
8483 19:55:28.531524 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8484 19:55:28.538121 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8485 19:55:28.541589 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8486 19:55:28.545446 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8487 19:55:28.548276 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8488 19:55:28.551388 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8489 19:55:28.558144 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8490 19:55:28.561502 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8491 19:55:28.564873 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8492 19:55:28.567861 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8493 19:55:28.571417 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8494 19:55:28.577794 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8495 19:55:28.581133 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8496 19:55:28.584885 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8497 19:55:28.587682 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8498 19:55:28.591438 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8499 19:55:28.594268 ==
8500 19:55:28.597726 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 19:55:28.600998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 19:55:28.601079 ==
8503 19:55:28.601143 DQS Delay:
8504 19:55:28.604156 DQS0 = 0, DQS1 = 0
8505 19:55:28.604236 DQM Delay:
8506 19:55:28.607699 DQM0 = 138, DQM1 = 130
8507 19:55:28.607790 DQ Delay:
8508 19:55:28.610929 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8509 19:55:28.614187 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8510 19:55:28.617986 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8511 19:55:28.620797 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =143
8512 19:55:28.620877
8513 19:55:28.620939
8514 19:55:28.624014 ==
8515 19:55:28.627324 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 19:55:28.630463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 19:55:28.630544 ==
8518 19:55:28.630608
8519 19:55:28.630666
8520 19:55:28.634010 TX Vref Scan disable
8521 19:55:28.634090 == TX Byte 0 ==
8522 19:55:28.637330 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8523 19:55:28.643613 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8524 19:55:28.643719 == TX Byte 1 ==
8525 19:55:28.650588 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8526 19:55:28.653814 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8527 19:55:28.653895 ==
8528 19:55:28.656947 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 19:55:28.660222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 19:55:28.660302 ==
8531 19:55:28.673723
8532 19:55:28.676799 TX Vref early break, caculate TX vref
8533 19:55:28.679872 TX Vref=16, minBit 5, minWin=21, winSum=374
8534 19:55:28.683492 TX Vref=18, minBit 0, minWin=22, winSum=384
8535 19:55:28.686918 TX Vref=20, minBit 0, minWin=22, winSum=389
8536 19:55:28.689933 TX Vref=22, minBit 0, minWin=24, winSum=404
8537 19:55:28.693347 TX Vref=24, minBit 0, minWin=24, winSum=414
8538 19:55:28.699816 TX Vref=26, minBit 5, minWin=24, winSum=416
8539 19:55:28.703060 TX Vref=28, minBit 1, minWin=24, winSum=419
8540 19:55:28.706793 TX Vref=30, minBit 1, minWin=24, winSum=413
8541 19:55:28.710064 TX Vref=32, minBit 0, minWin=24, winSum=405
8542 19:55:28.713291 TX Vref=34, minBit 0, minWin=23, winSum=394
8543 19:55:28.720314 [TxChooseVref] Worse bit 1, Min win 24, Win sum 419, Final Vref 28
8544 19:55:28.720395
8545 19:55:28.723085 Final TX Range 0 Vref 28
8546 19:55:28.723165
8547 19:55:28.723229 ==
8548 19:55:28.726646 Dram Type= 6, Freq= 0, CH_1, rank 0
8549 19:55:28.730032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8550 19:55:28.730113 ==
8551 19:55:28.730177
8552 19:55:28.730236
8553 19:55:28.733052 TX Vref Scan disable
8554 19:55:28.739625 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8555 19:55:28.739706 == TX Byte 0 ==
8556 19:55:28.742707 u2DelayCellOfst[0]=18 cells (5 PI)
8557 19:55:28.746164 u2DelayCellOfst[1]=11 cells (3 PI)
8558 19:55:28.749488 u2DelayCellOfst[2]=0 cells (0 PI)
8559 19:55:28.752681 u2DelayCellOfst[3]=7 cells (2 PI)
8560 19:55:28.755897 u2DelayCellOfst[4]=7 cells (2 PI)
8561 19:55:28.759342 u2DelayCellOfst[5]=18 cells (5 PI)
8562 19:55:28.763083 u2DelayCellOfst[6]=18 cells (5 PI)
8563 19:55:28.766422 u2DelayCellOfst[7]=7 cells (2 PI)
8564 19:55:28.769511 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8565 19:55:28.772942 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8566 19:55:28.776175 == TX Byte 1 ==
8567 19:55:28.776255 u2DelayCellOfst[8]=0 cells (0 PI)
8568 19:55:28.779153 u2DelayCellOfst[9]=3 cells (1 PI)
8569 19:55:28.782684 u2DelayCellOfst[10]=11 cells (3 PI)
8570 19:55:28.785979 u2DelayCellOfst[11]=3 cells (1 PI)
8571 19:55:28.788915 u2DelayCellOfst[12]=14 cells (4 PI)
8572 19:55:28.792079 u2DelayCellOfst[13]=18 cells (5 PI)
8573 19:55:28.796207 u2DelayCellOfst[14]=18 cells (5 PI)
8574 19:55:28.799156 u2DelayCellOfst[15]=18 cells (5 PI)
8575 19:55:28.802343 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8576 19:55:28.808989 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8577 19:55:28.809092 DramC Write-DBI on
8578 19:55:28.809194 ==
8579 19:55:28.812440 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 19:55:28.818672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 19:55:28.818754 ==
8582 19:55:28.818819
8583 19:55:28.818879
8584 19:55:28.818936 TX Vref Scan disable
8585 19:55:28.822905 == TX Byte 0 ==
8586 19:55:28.825869 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8587 19:55:28.829206 == TX Byte 1 ==
8588 19:55:28.832944 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8589 19:55:28.836053 DramC Write-DBI off
8590 19:55:28.836133
8591 19:55:28.836197 [DATLAT]
8592 19:55:28.836256 Freq=1600, CH1 RK0
8593 19:55:28.836313
8594 19:55:28.839053 DATLAT Default: 0xf
8595 19:55:28.839133 0, 0xFFFF, sum = 0
8596 19:55:28.842958 1, 0xFFFF, sum = 0
8597 19:55:28.845709 2, 0xFFFF, sum = 0
8598 19:55:28.845790 3, 0xFFFF, sum = 0
8599 19:55:28.849070 4, 0xFFFF, sum = 0
8600 19:55:28.849152 5, 0xFFFF, sum = 0
8601 19:55:28.852632 6, 0xFFFF, sum = 0
8602 19:55:28.852714 7, 0xFFFF, sum = 0
8603 19:55:28.855702 8, 0xFFFF, sum = 0
8604 19:55:28.855819 9, 0xFFFF, sum = 0
8605 19:55:28.859350 10, 0xFFFF, sum = 0
8606 19:55:28.859431 11, 0xFFFF, sum = 0
8607 19:55:28.862762 12, 0xFFFF, sum = 0
8608 19:55:28.862843 13, 0xFFFF, sum = 0
8609 19:55:28.865810 14, 0x0, sum = 1
8610 19:55:28.865892 15, 0x0, sum = 2
8611 19:55:28.869122 16, 0x0, sum = 3
8612 19:55:28.869203 17, 0x0, sum = 4
8613 19:55:28.872632 best_step = 15
8614 19:55:28.872712
8615 19:55:28.872776 ==
8616 19:55:28.875879 Dram Type= 6, Freq= 0, CH_1, rank 0
8617 19:55:28.879062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8618 19:55:28.879143 ==
8619 19:55:28.882578 RX Vref Scan: 1
8620 19:55:28.882658
8621 19:55:28.882721 Set Vref Range= 24 -> 127
8622 19:55:28.882780
8623 19:55:28.885678 RX Vref 24 -> 127, step: 1
8624 19:55:28.885759
8625 19:55:28.888791 RX Delay 11 -> 252, step: 4
8626 19:55:28.888875
8627 19:55:28.892033 Set Vref, RX VrefLevel [Byte0]: 24
8628 19:55:28.895368 [Byte1]: 24
8629 19:55:28.895448
8630 19:55:28.898640 Set Vref, RX VrefLevel [Byte0]: 25
8631 19:55:28.902114 [Byte1]: 25
8632 19:55:28.905468
8633 19:55:28.905547 Set Vref, RX VrefLevel [Byte0]: 26
8634 19:55:28.909007 [Byte1]: 26
8635 19:55:28.913273
8636 19:55:28.913354 Set Vref, RX VrefLevel [Byte0]: 27
8637 19:55:28.916266 [Byte1]: 27
8638 19:55:28.920925
8639 19:55:28.921031 Set Vref, RX VrefLevel [Byte0]: 28
8640 19:55:28.924070 [Byte1]: 28
8641 19:55:28.928604
8642 19:55:28.928683 Set Vref, RX VrefLevel [Byte0]: 29
8643 19:55:28.931583 [Byte1]: 29
8644 19:55:28.935677
8645 19:55:28.935810 Set Vref, RX VrefLevel [Byte0]: 30
8646 19:55:28.939259 [Byte1]: 30
8647 19:55:28.943664
8648 19:55:28.943787 Set Vref, RX VrefLevel [Byte0]: 31
8649 19:55:28.946775 [Byte1]: 31
8650 19:55:28.950939
8651 19:55:28.951034 Set Vref, RX VrefLevel [Byte0]: 32
8652 19:55:28.954248 [Byte1]: 32
8653 19:55:28.958945
8654 19:55:28.959025 Set Vref, RX VrefLevel [Byte0]: 33
8655 19:55:28.962143 [Byte1]: 33
8656 19:55:28.966351
8657 19:55:28.966431 Set Vref, RX VrefLevel [Byte0]: 34
8658 19:55:28.969868 [Byte1]: 34
8659 19:55:28.974025
8660 19:55:28.974105 Set Vref, RX VrefLevel [Byte0]: 35
8661 19:55:28.977005 [Byte1]: 35
8662 19:55:28.981854
8663 19:55:28.981934 Set Vref, RX VrefLevel [Byte0]: 36
8664 19:55:28.984919 [Byte1]: 36
8665 19:55:28.988975
8666 19:55:28.989055 Set Vref, RX VrefLevel [Byte0]: 37
8667 19:55:28.993051 [Byte1]: 37
8668 19:55:28.996686
8669 19:55:28.996765 Set Vref, RX VrefLevel [Byte0]: 38
8670 19:55:29.000114 [Byte1]: 38
8671 19:55:29.004212
8672 19:55:29.004291 Set Vref, RX VrefLevel [Byte0]: 39
8673 19:55:29.007681 [Byte1]: 39
8674 19:55:29.012043
8675 19:55:29.012123 Set Vref, RX VrefLevel [Byte0]: 40
8676 19:55:29.015895 [Byte1]: 40
8677 19:55:29.019621
8678 19:55:29.019731 Set Vref, RX VrefLevel [Byte0]: 41
8679 19:55:29.023312 [Byte1]: 41
8680 19:55:29.027491
8681 19:55:29.027597 Set Vref, RX VrefLevel [Byte0]: 42
8682 19:55:29.030522 [Byte1]: 42
8683 19:55:29.034769
8684 19:55:29.034849 Set Vref, RX VrefLevel [Byte0]: 43
8685 19:55:29.038076 [Byte1]: 43
8686 19:55:29.042718
8687 19:55:29.042797 Set Vref, RX VrefLevel [Byte0]: 44
8688 19:55:29.045697 [Byte1]: 44
8689 19:55:29.050348
8690 19:55:29.050428 Set Vref, RX VrefLevel [Byte0]: 45
8691 19:55:29.053508 [Byte1]: 45
8692 19:55:29.057960
8693 19:55:29.058039 Set Vref, RX VrefLevel [Byte0]: 46
8694 19:55:29.060958 [Byte1]: 46
8695 19:55:29.065583
8696 19:55:29.065663 Set Vref, RX VrefLevel [Byte0]: 47
8697 19:55:29.068450 [Byte1]: 47
8698 19:55:29.072862
8699 19:55:29.072942 Set Vref, RX VrefLevel [Byte0]: 48
8700 19:55:29.076563 [Byte1]: 48
8701 19:55:29.080600
8702 19:55:29.080679 Set Vref, RX VrefLevel [Byte0]: 49
8703 19:55:29.084409 [Byte1]: 49
8704 19:55:29.088443
8705 19:55:29.088523 Set Vref, RX VrefLevel [Byte0]: 50
8706 19:55:29.091658 [Byte1]: 50
8707 19:55:29.095848
8708 19:55:29.095932 Set Vref, RX VrefLevel [Byte0]: 51
8709 19:55:29.099477 [Byte1]: 51
8710 19:55:29.103911
8711 19:55:29.103991 Set Vref, RX VrefLevel [Byte0]: 52
8712 19:55:29.107008 [Byte1]: 52
8713 19:55:29.110921
8714 19:55:29.111001 Set Vref, RX VrefLevel [Byte0]: 53
8715 19:55:29.114351 [Byte1]: 53
8716 19:55:29.118744
8717 19:55:29.118824 Set Vref, RX VrefLevel [Byte0]: 54
8718 19:55:29.122175 [Byte1]: 54
8719 19:55:29.126369
8720 19:55:29.126449 Set Vref, RX VrefLevel [Byte0]: 55
8721 19:55:29.129750 [Byte1]: 55
8722 19:55:29.134000
8723 19:55:29.134079 Set Vref, RX VrefLevel [Byte0]: 56
8724 19:55:29.137241 [Byte1]: 56
8725 19:55:29.141383
8726 19:55:29.141463 Set Vref, RX VrefLevel [Byte0]: 57
8727 19:55:29.144835 [Byte1]: 57
8728 19:55:29.149141
8729 19:55:29.149221 Set Vref, RX VrefLevel [Byte0]: 58
8730 19:55:29.152579 [Byte1]: 58
8731 19:55:29.156796
8732 19:55:29.156876 Set Vref, RX VrefLevel [Byte0]: 59
8733 19:55:29.159918 [Byte1]: 59
8734 19:55:29.164709
8735 19:55:29.164789 Set Vref, RX VrefLevel [Byte0]: 60
8736 19:55:29.167483 [Byte1]: 60
8737 19:55:29.172019
8738 19:55:29.172099 Set Vref, RX VrefLevel [Byte0]: 61
8739 19:55:29.175423 [Byte1]: 61
8740 19:55:29.179697
8741 19:55:29.179790 Set Vref, RX VrefLevel [Byte0]: 62
8742 19:55:29.183319 [Byte1]: 62
8743 19:55:29.186902
8744 19:55:29.186981 Set Vref, RX VrefLevel [Byte0]: 63
8745 19:55:29.190583 [Byte1]: 63
8746 19:55:29.195253
8747 19:55:29.195333 Set Vref, RX VrefLevel [Byte0]: 64
8748 19:55:29.198465 [Byte1]: 64
8749 19:55:29.202380
8750 19:55:29.202460 Set Vref, RX VrefLevel [Byte0]: 65
8751 19:55:29.205901 [Byte1]: 65
8752 19:55:29.210841
8753 19:55:29.210921 Set Vref, RX VrefLevel [Byte0]: 66
8754 19:55:29.213227 [Byte1]: 66
8755 19:55:29.217820
8756 19:55:29.217900 Set Vref, RX VrefLevel [Byte0]: 67
8757 19:55:29.220812 [Byte1]: 67
8758 19:55:29.224998
8759 19:55:29.225077 Set Vref, RX VrefLevel [Byte0]: 68
8760 19:55:29.228369 [Byte1]: 68
8761 19:55:29.232651
8762 19:55:29.232731 Set Vref, RX VrefLevel [Byte0]: 69
8763 19:55:29.239615 [Byte1]: 69
8764 19:55:29.239695
8765 19:55:29.242582 Set Vref, RX VrefLevel [Byte0]: 70
8766 19:55:29.245739 [Byte1]: 70
8767 19:55:29.245819
8768 19:55:29.249302 Set Vref, RX VrefLevel [Byte0]: 71
8769 19:55:29.252582 [Byte1]: 71
8770 19:55:29.255716
8771 19:55:29.255835 Set Vref, RX VrefLevel [Byte0]: 72
8772 19:55:29.259104 [Byte1]: 72
8773 19:55:29.263389
8774 19:55:29.263496 Set Vref, RX VrefLevel [Byte0]: 73
8775 19:55:29.266494 [Byte1]: 73
8776 19:55:29.271412
8777 19:55:29.271492 Set Vref, RX VrefLevel [Byte0]: 74
8778 19:55:29.274035 [Byte1]: 74
8779 19:55:29.278705
8780 19:55:29.278784 Final RX Vref Byte 0 = 52 to rank0
8781 19:55:29.282006 Final RX Vref Byte 1 = 60 to rank0
8782 19:55:29.284961 Final RX Vref Byte 0 = 52 to rank1
8783 19:55:29.288171 Final RX Vref Byte 1 = 60 to rank1==
8784 19:55:29.291637 Dram Type= 6, Freq= 0, CH_1, rank 0
8785 19:55:29.298275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 19:55:29.298356 ==
8787 19:55:29.298420 DQS Delay:
8788 19:55:29.301691 DQS0 = 0, DQS1 = 0
8789 19:55:29.301771 DQM Delay:
8790 19:55:29.301835 DQM0 = 134, DQM1 = 129
8791 19:55:29.305263 DQ Delay:
8792 19:55:29.308408 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =130
8793 19:55:29.311441 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8794 19:55:29.314683 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =118
8795 19:55:29.318432 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8796 19:55:29.318512
8797 19:55:29.318576
8798 19:55:29.318635
8799 19:55:29.321627 [DramC_TX_OE_Calibration] TA2
8800 19:55:29.324473 Original DQ_B0 (3 6) =30, OEN = 27
8801 19:55:29.327945 Original DQ_B1 (3 6) =30, OEN = 27
8802 19:55:29.330905 24, 0x0, End_B0=24 End_B1=24
8803 19:55:29.334347 25, 0x0, End_B0=25 End_B1=25
8804 19:55:29.334428 26, 0x0, End_B0=26 End_B1=26
8805 19:55:29.338001 27, 0x0, End_B0=27 End_B1=27
8806 19:55:29.341131 28, 0x0, End_B0=28 End_B1=28
8807 19:55:29.344251 29, 0x0, End_B0=29 End_B1=29
8808 19:55:29.344333 30, 0x0, End_B0=30 End_B1=30
8809 19:55:29.347605 31, 0x4141, End_B0=30 End_B1=30
8810 19:55:29.350897 Byte0 end_step=30 best_step=27
8811 19:55:29.354164 Byte1 end_step=30 best_step=27
8812 19:55:29.357831 Byte0 TX OE(2T, 0.5T) = (3, 3)
8813 19:55:29.360767 Byte1 TX OE(2T, 0.5T) = (3, 3)
8814 19:55:29.360847
8815 19:55:29.360910
8816 19:55:29.367527 [DQSOSCAuto] RK0, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8817 19:55:29.371206 CH1 RK0: MR19=303, MR18=190F
8818 19:55:29.377487 CH1_RK0: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8819 19:55:29.377590
8820 19:55:29.380345 ----->DramcWriteLeveling(PI) begin...
8821 19:55:29.380426 ==
8822 19:55:29.383705 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 19:55:29.387237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 19:55:29.387337 ==
8825 19:55:29.390593 Write leveling (Byte 0): 25 => 25
8826 19:55:29.393385 Write leveling (Byte 1): 28 => 28
8827 19:55:29.397128 DramcWriteLeveling(PI) end<-----
8828 19:55:29.397231
8829 19:55:29.397329 ==
8830 19:55:29.400186 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 19:55:29.407087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 19:55:29.407187 ==
8833 19:55:29.407285 [Gating] SW mode calibration
8834 19:55:29.416778 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8835 19:55:29.420365 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8836 19:55:29.423587 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 19:55:29.429999 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 19:55:29.433153 1 4 8 | B1->B0 | 2625 2323 | 1 0 | (0 0) (0 0)
8839 19:55:29.437112 1 4 12 | B1->B0 | 3333 2323 | 0 0 | (1 1) (0 0)
8840 19:55:29.442989 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8841 19:55:29.446221 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 19:55:29.449524 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8843 19:55:29.456236 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8844 19:55:29.459646 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8845 19:55:29.466560 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8846 19:55:29.469595 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8847 19:55:29.472673 1 5 12 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8848 19:55:29.478998 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 19:55:29.482509 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 19:55:29.485690 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 19:55:29.492396 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 19:55:29.495807 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 19:55:29.499025 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8854 19:55:29.505807 1 6 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8855 19:55:29.508797 1 6 12 | B1->B0 | 4545 2323 | 0 0 | (0 0) (0 0)
8856 19:55:29.512380 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8857 19:55:29.518695 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 19:55:29.522227 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 19:55:29.525724 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 19:55:29.528550 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 19:55:29.535446 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 19:55:29.538976 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8863 19:55:29.542335 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8864 19:55:29.548643 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8865 19:55:29.551771 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8866 19:55:29.555026 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 19:55:29.561959 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 19:55:29.565285 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 19:55:29.568658 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 19:55:29.575349 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 19:55:29.578618 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 19:55:29.581513 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 19:55:29.588591 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 19:55:29.591791 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 19:55:29.595475 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 19:55:29.601960 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 19:55:29.605523 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 19:55:29.608090 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8879 19:55:29.615136 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8880 19:55:29.618196 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8881 19:55:29.621473 Total UI for P1: 0, mck2ui 16
8882 19:55:29.624625 best dqsien dly found for B0: ( 1, 9, 10)
8883 19:55:29.628028 Total UI for P1: 0, mck2ui 16
8884 19:55:29.631180 best dqsien dly found for B1: ( 1, 9, 10)
8885 19:55:29.634759 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8886 19:55:29.637848 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8887 19:55:29.637940
8888 19:55:29.641077 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8889 19:55:29.647700 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8890 19:55:29.647809 [Gating] SW calibration Done
8891 19:55:29.647915 ==
8892 19:55:29.651120 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 19:55:29.658322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 19:55:29.658422 ==
8895 19:55:29.658506 RX Vref Scan: 0
8896 19:55:29.658585
8897 19:55:29.661254 RX Vref 0 -> 0, step: 1
8898 19:55:29.661326
8899 19:55:29.664327 RX Delay 0 -> 252, step: 8
8900 19:55:29.667462 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8901 19:55:29.671112 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8902 19:55:29.674156 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8903 19:55:29.677733 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8904 19:55:29.684599 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8905 19:55:29.687284 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8906 19:55:29.690767 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8907 19:55:29.694114 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8908 19:55:29.700677 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8909 19:55:29.703674 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8910 19:55:29.707883 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8911 19:55:29.710476 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8912 19:55:29.713805 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8913 19:55:29.720563 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8914 19:55:29.723536 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8915 19:55:29.727497 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8916 19:55:29.727600 ==
8917 19:55:29.730338 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 19:55:29.733552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 19:55:29.733625 ==
8920 19:55:29.736726 DQS Delay:
8921 19:55:29.736814 DQS0 = 0, DQS1 = 0
8922 19:55:29.739980 DQM Delay:
8923 19:55:29.740052 DQM0 = 136, DQM1 = 129
8924 19:55:29.743488 DQ Delay:
8925 19:55:29.746593 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8926 19:55:29.749830 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8927 19:55:29.753117 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8928 19:55:29.756645 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8929 19:55:29.756749
8930 19:55:29.756848
8931 19:55:29.756952 ==
8932 19:55:29.760191 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 19:55:29.763146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 19:55:29.763243 ==
8935 19:55:29.763351
8936 19:55:29.767060
8937 19:55:29.767156 TX Vref Scan disable
8938 19:55:29.770059 == TX Byte 0 ==
8939 19:55:29.773229 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8940 19:55:29.776391 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8941 19:55:29.780036 == TX Byte 1 ==
8942 19:55:29.782767 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8943 19:55:29.786336 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8944 19:55:29.786436 ==
8945 19:55:29.789966 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 19:55:29.796506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 19:55:29.796581 ==
8948 19:55:29.808232
8949 19:55:29.811538 TX Vref early break, caculate TX vref
8950 19:55:29.815051 TX Vref=16, minBit 8, minWin=22, winSum=387
8951 19:55:29.817870 TX Vref=18, minBit 8, minWin=23, winSum=395
8952 19:55:29.821142 TX Vref=20, minBit 9, minWin=23, winSum=402
8953 19:55:29.824504 TX Vref=22, minBit 8, minWin=24, winSum=410
8954 19:55:29.827845 TX Vref=24, minBit 9, minWin=25, winSum=418
8955 19:55:29.834495 TX Vref=26, minBit 1, minWin=25, winSum=424
8956 19:55:29.837787 TX Vref=28, minBit 0, minWin=25, winSum=424
8957 19:55:29.841024 TX Vref=30, minBit 0, minWin=25, winSum=419
8958 19:55:29.844408 TX Vref=32, minBit 9, minWin=24, winSum=405
8959 19:55:29.848296 TX Vref=34, minBit 0, minWin=23, winSum=397
8960 19:55:29.854181 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 26
8961 19:55:29.854284
8962 19:55:29.857496 Final TX Range 0 Vref 26
8963 19:55:29.857605
8964 19:55:29.857703 ==
8965 19:55:29.861044 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 19:55:29.864503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 19:55:29.864576 ==
8968 19:55:29.864660
8969 19:55:29.864737
8970 19:55:29.867221 TX Vref Scan disable
8971 19:55:29.873874 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8972 19:55:29.873976 == TX Byte 0 ==
8973 19:55:29.877418 u2DelayCellOfst[0]=18 cells (5 PI)
8974 19:55:29.880414 u2DelayCellOfst[1]=14 cells (4 PI)
8975 19:55:29.883868 u2DelayCellOfst[2]=0 cells (0 PI)
8976 19:55:29.887314 u2DelayCellOfst[3]=7 cells (2 PI)
8977 19:55:29.890551 u2DelayCellOfst[4]=11 cells (3 PI)
8978 19:55:29.893689 u2DelayCellOfst[5]=22 cells (6 PI)
8979 19:55:29.896896 u2DelayCellOfst[6]=22 cells (6 PI)
8980 19:55:29.900549 u2DelayCellOfst[7]=7 cells (2 PI)
8981 19:55:29.903498 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8982 19:55:29.907318 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8983 19:55:29.910570 == TX Byte 1 ==
8984 19:55:29.913503 u2DelayCellOfst[8]=0 cells (0 PI)
8985 19:55:29.916676 u2DelayCellOfst[9]=7 cells (2 PI)
8986 19:55:29.920190 u2DelayCellOfst[10]=14 cells (4 PI)
8987 19:55:29.920290 u2DelayCellOfst[11]=7 cells (2 PI)
8988 19:55:29.923411 u2DelayCellOfst[12]=14 cells (4 PI)
8989 19:55:29.927025 u2DelayCellOfst[13]=18 cells (5 PI)
8990 19:55:29.929900 u2DelayCellOfst[14]=18 cells (5 PI)
8991 19:55:29.933456 u2DelayCellOfst[15]=18 cells (5 PI)
8992 19:55:29.940163 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8993 19:55:29.943147 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8994 19:55:29.943222 DramC Write-DBI on
8995 19:55:29.943313 ==
8996 19:55:29.947049 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 19:55:29.953272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 19:55:29.953374 ==
8999 19:55:29.953472
9000 19:55:29.953572
9001 19:55:29.956701 TX Vref Scan disable
9002 19:55:29.956805 == TX Byte 0 ==
9003 19:55:29.963247 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9004 19:55:29.963348 == TX Byte 1 ==
9005 19:55:29.965998 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9006 19:55:29.969423 DramC Write-DBI off
9007 19:55:29.969522
9008 19:55:29.969619 [DATLAT]
9009 19:55:29.972925 Freq=1600, CH1 RK1
9010 19:55:29.973022
9011 19:55:29.973119 DATLAT Default: 0xf
9012 19:55:29.976071 0, 0xFFFF, sum = 0
9013 19:55:29.976152 1, 0xFFFF, sum = 0
9014 19:55:29.979266 2, 0xFFFF, sum = 0
9015 19:55:29.979365 3, 0xFFFF, sum = 0
9016 19:55:29.982583 4, 0xFFFF, sum = 0
9017 19:55:29.982684 5, 0xFFFF, sum = 0
9018 19:55:29.986031 6, 0xFFFF, sum = 0
9019 19:55:29.986183 7, 0xFFFF, sum = 0
9020 19:55:29.989492 8, 0xFFFF, sum = 0
9021 19:55:29.992290 9, 0xFFFF, sum = 0
9022 19:55:29.992397 10, 0xFFFF, sum = 0
9023 19:55:29.995837 11, 0xFFFF, sum = 0
9024 19:55:29.995919 12, 0xFFFF, sum = 0
9025 19:55:29.999196 13, 0xFFFF, sum = 0
9026 19:55:29.999295 14, 0x0, sum = 1
9027 19:55:30.002473 15, 0x0, sum = 2
9028 19:55:30.002573 16, 0x0, sum = 3
9029 19:55:30.006166 17, 0x0, sum = 4
9030 19:55:30.006265 best_step = 15
9031 19:55:30.006362
9032 19:55:30.006458 ==
9033 19:55:30.009412 Dram Type= 6, Freq= 0, CH_1, rank 1
9034 19:55:30.012414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9035 19:55:30.015605 ==
9036 19:55:30.015713 RX Vref Scan: 0
9037 19:55:30.015834
9038 19:55:30.018974 RX Vref 0 -> 0, step: 1
9039 19:55:30.019071
9040 19:55:30.019170 RX Delay 11 -> 252, step: 4
9041 19:55:30.026070 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9042 19:55:30.029525 iDelay=203, Bit 1, Center 126 (75 ~ 178) 104
9043 19:55:30.032732 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9044 19:55:30.036678 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9045 19:55:30.042887 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9046 19:55:30.045929 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9047 19:55:30.049449 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9048 19:55:30.052824 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9049 19:55:30.056085 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9050 19:55:30.062862 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9051 19:55:30.065958 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9052 19:55:30.069017 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9053 19:55:30.072462 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9054 19:55:30.075636 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9055 19:55:30.082434 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9056 19:55:30.085680 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9057 19:55:30.085760 ==
9058 19:55:30.088765 Dram Type= 6, Freq= 0, CH_1, rank 1
9059 19:55:30.092329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9060 19:55:30.092435 ==
9061 19:55:30.095321 DQS Delay:
9062 19:55:30.095416 DQS0 = 0, DQS1 = 0
9063 19:55:30.095504 DQM Delay:
9064 19:55:30.099064 DQM0 = 133, DQM1 = 127
9065 19:55:30.099145 DQ Delay:
9066 19:55:30.102488 DQ0 =138, DQ1 =126, DQ2 =122, DQ3 =130
9067 19:55:30.105217 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9068 19:55:30.111964 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =118
9069 19:55:30.115155 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =138
9070 19:55:30.115236
9071 19:55:30.115299
9072 19:55:30.115357
9073 19:55:30.118725 [DramC_TX_OE_Calibration] TA2
9074 19:55:30.121855 Original DQ_B0 (3 6) =30, OEN = 27
9075 19:55:30.125273 Original DQ_B1 (3 6) =30, OEN = 27
9076 19:55:30.125354 24, 0x0, End_B0=24 End_B1=24
9077 19:55:30.128425 25, 0x0, End_B0=25 End_B1=25
9078 19:55:30.131663 26, 0x0, End_B0=26 End_B1=26
9079 19:55:30.135422 27, 0x0, End_B0=27 End_B1=27
9080 19:55:30.138243 28, 0x0, End_B0=28 End_B1=28
9081 19:55:30.138325 29, 0x0, End_B0=29 End_B1=29
9082 19:55:30.141215 30, 0x0, End_B0=30 End_B1=30
9083 19:55:30.144704 31, 0x4141, End_B0=30 End_B1=30
9084 19:55:30.148216 Byte0 end_step=30 best_step=27
9085 19:55:30.151391 Byte1 end_step=30 best_step=27
9086 19:55:30.154809 Byte0 TX OE(2T, 0.5T) = (3, 3)
9087 19:55:30.154889 Byte1 TX OE(2T, 0.5T) = (3, 3)
9088 19:55:30.154953
9089 19:55:30.157690
9090 19:55:30.165214 [DQSOSCAuto] RK1, (LSB)MR18= 0xd08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9091 19:55:30.167841 CH1 RK1: MR19=303, MR18=D08
9092 19:55:30.174688 CH1_RK1: MR19=0x303, MR18=0xD08, DQSOSC=403, MR23=63, INC=22, DEC=15
9093 19:55:30.174769 [RxdqsGatingPostProcess] freq 1600
9094 19:55:30.181097 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9095 19:55:30.184309 best DQS0 dly(2T, 0.5T) = (1, 1)
9096 19:55:30.187695 best DQS1 dly(2T, 0.5T) = (1, 1)
9097 19:55:30.190978 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9098 19:55:30.194347 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9099 19:55:30.197395 best DQS0 dly(2T, 0.5T) = (1, 1)
9100 19:55:30.200972 best DQS1 dly(2T, 0.5T) = (1, 1)
9101 19:55:30.204152 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9102 19:55:30.207670 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9103 19:55:30.207787 Pre-setting of DQS Precalculation
9104 19:55:30.214098 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9105 19:55:30.220818 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9106 19:55:30.227164 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 19:55:30.227267
9108 19:55:30.227333
9109 19:55:30.230966 [Calibration Summary] 3200 Mbps
9110 19:55:30.233790 CH 0, Rank 0
9111 19:55:30.233870 SW Impedance : PASS
9112 19:55:30.237232 DUTY Scan : NO K
9113 19:55:30.240712 ZQ Calibration : PASS
9114 19:55:30.240792 Jitter Meter : NO K
9115 19:55:30.243846 CBT Training : PASS
9116 19:55:30.246996 Write leveling : PASS
9117 19:55:30.247077 RX DQS gating : PASS
9118 19:55:30.250410 RX DQ/DQS(RDDQC) : PASS
9119 19:55:30.253484 TX DQ/DQS : PASS
9120 19:55:30.253565 RX DATLAT : PASS
9121 19:55:30.256767 RX DQ/DQS(Engine): PASS
9122 19:55:30.260237 TX OE : PASS
9123 19:55:30.260317 All Pass.
9124 19:55:30.260381
9125 19:55:30.260440 CH 0, Rank 1
9126 19:55:30.263588 SW Impedance : PASS
9127 19:55:30.266860 DUTY Scan : NO K
9128 19:55:30.266939 ZQ Calibration : PASS
9129 19:55:30.270004 Jitter Meter : NO K
9130 19:55:30.273394 CBT Training : PASS
9131 19:55:30.273474 Write leveling : PASS
9132 19:55:30.276873 RX DQS gating : PASS
9133 19:55:30.280204 RX DQ/DQS(RDDQC) : PASS
9134 19:55:30.280284 TX DQ/DQS : PASS
9135 19:55:30.283089 RX DATLAT : PASS
9136 19:55:30.283169 RX DQ/DQS(Engine): PASS
9137 19:55:30.286621 TX OE : PASS
9138 19:55:30.286702 All Pass.
9139 19:55:30.286766
9140 19:55:30.290237 CH 1, Rank 0
9141 19:55:30.290317 SW Impedance : PASS
9142 19:55:30.293202 DUTY Scan : NO K
9143 19:55:30.296368 ZQ Calibration : PASS
9144 19:55:30.296448 Jitter Meter : NO K
9145 19:55:30.299858 CBT Training : PASS
9146 19:55:30.302892 Write leveling : PASS
9147 19:55:30.302973 RX DQS gating : PASS
9148 19:55:30.306004 RX DQ/DQS(RDDQC) : PASS
9149 19:55:30.309571 TX DQ/DQS : PASS
9150 19:55:30.309651 RX DATLAT : PASS
9151 19:55:30.312673 RX DQ/DQS(Engine): PASS
9152 19:55:30.316442 TX OE : PASS
9153 19:55:30.316530 All Pass.
9154 19:55:30.316594
9155 19:55:30.316654 CH 1, Rank 1
9156 19:55:30.319143 SW Impedance : PASS
9157 19:55:30.322829 DUTY Scan : NO K
9158 19:55:30.322909 ZQ Calibration : PASS
9159 19:55:30.325815 Jitter Meter : NO K
9160 19:55:30.329165 CBT Training : PASS
9161 19:55:30.329245 Write leveling : PASS
9162 19:55:30.332722 RX DQS gating : PASS
9163 19:55:30.335856 RX DQ/DQS(RDDQC) : PASS
9164 19:55:30.335956 TX DQ/DQS : PASS
9165 19:55:30.339202 RX DATLAT : PASS
9166 19:55:30.342213 RX DQ/DQS(Engine): PASS
9167 19:55:30.342294 TX OE : PASS
9168 19:55:30.345914 All Pass.
9169 19:55:30.345994
9170 19:55:30.346058 DramC Write-DBI on
9171 19:55:30.349178 PER_BANK_REFRESH: Hybrid Mode
9172 19:55:30.349258 TX_TRACKING: ON
9173 19:55:30.359018 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9174 19:55:30.368805 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9175 19:55:30.375217 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9176 19:55:30.378639 [FAST_K] Save calibration result to emmc
9177 19:55:30.381625 sync common calibartion params.
9178 19:55:30.381706 sync cbt_mode0:1, 1:1
9179 19:55:30.384995 dram_init: ddr_geometry: 2
9180 19:55:30.389065 dram_init: ddr_geometry: 2
9181 19:55:30.389145 dram_init: ddr_geometry: 2
9182 19:55:30.391983 0:dram_rank_size:100000000
9183 19:55:30.394932 1:dram_rank_size:100000000
9184 19:55:30.402222 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9185 19:55:30.402304 DFS_SHUFFLE_HW_MODE: ON
9186 19:55:30.405195 dramc_set_vcore_voltage set vcore to 725000
9187 19:55:30.407996 Read voltage for 1600, 0
9188 19:55:30.408076 Vio18 = 0
9189 19:55:30.411392 Vcore = 725000
9190 19:55:30.411473 Vdram = 0
9191 19:55:30.411536 Vddq = 0
9192 19:55:30.415033 Vmddr = 0
9193 19:55:30.415114 switch to 3200 Mbps bootup
9194 19:55:30.418933 [DramcRunTimeConfig]
9195 19:55:30.419014 PHYPLL
9196 19:55:30.421484 DPM_CONTROL_AFTERK: ON
9197 19:55:30.421564 PER_BANK_REFRESH: ON
9198 19:55:30.424975 REFRESH_OVERHEAD_REDUCTION: ON
9199 19:55:30.428040 CMD_PICG_NEW_MODE: OFF
9200 19:55:30.428120 XRTWTW_NEW_MODE: ON
9201 19:55:30.431883 XRTRTR_NEW_MODE: ON
9202 19:55:30.431964 TX_TRACKING: ON
9203 19:55:30.434447 RDSEL_TRACKING: OFF
9204 19:55:30.438277 DQS Precalculation for DVFS: ON
9205 19:55:30.438357 RX_TRACKING: OFF
9206 19:55:30.441536 HW_GATING DBG: ON
9207 19:55:30.441616 ZQCS_ENABLE_LP4: ON
9208 19:55:30.444396 RX_PICG_NEW_MODE: ON
9209 19:55:30.444476 TX_PICG_NEW_MODE: ON
9210 19:55:30.447819 ENABLE_RX_DCM_DPHY: ON
9211 19:55:30.451231 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9212 19:55:30.455056 DUMMY_READ_FOR_TRACKING: OFF
9213 19:55:30.457690 !!! SPM_CONTROL_AFTERK: OFF
9214 19:55:30.457782 !!! SPM could not control APHY
9215 19:55:30.460981 IMPEDANCE_TRACKING: ON
9216 19:55:30.461054 TEMP_SENSOR: ON
9217 19:55:30.464477 HW_SAVE_FOR_SR: OFF
9218 19:55:30.468231 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9219 19:55:30.471166 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9220 19:55:30.474469 Read ODT Tracking: ON
9221 19:55:30.474563 Refresh Rate DeBounce: ON
9222 19:55:30.477469 DFS_NO_QUEUE_FLUSH: ON
9223 19:55:30.480568 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9224 19:55:30.484393 ENABLE_DFS_RUNTIME_MRW: OFF
9225 19:55:30.484489 DDR_RESERVE_NEW_MODE: ON
9226 19:55:30.487901 MR_CBT_SWITCH_FREQ: ON
9227 19:55:30.490633 =========================
9228 19:55:30.509075 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9229 19:55:30.512148 dram_init: ddr_geometry: 2
9230 19:55:30.530550 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9231 19:55:30.533374 dram_init: dram init end (result: 0)
9232 19:55:30.540609 DRAM-K: Full calibration passed in 24618 msecs
9233 19:55:30.543378 MRC: failed to locate region type 0.
9234 19:55:30.543475 DRAM rank0 size:0x100000000,
9235 19:55:30.547081 DRAM rank1 size=0x100000000
9236 19:55:30.556948 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9237 19:55:30.563241 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9238 19:55:30.569738 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9239 19:55:30.576476 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9240 19:55:30.580494 DRAM rank0 size:0x100000000,
9241 19:55:30.583285 DRAM rank1 size=0x100000000
9242 19:55:30.583365 CBMEM:
9243 19:55:30.586555 IMD: root @ 0xfffff000 254 entries.
9244 19:55:30.589783 IMD: root @ 0xffffec00 62 entries.
9245 19:55:30.592735 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9246 19:55:30.599478 WARNING: RO_VPD is uninitialized or empty.
9247 19:55:30.603243 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9248 19:55:30.610535 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9249 19:55:30.623230 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9250 19:55:30.634409 BS: romstage times (exec / console): total (unknown) / 24109 ms
9251 19:55:30.634491
9252 19:55:30.634554
9253 19:55:30.644315 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9254 19:55:30.647519 ARM64: Exception handlers installed.
9255 19:55:30.650771 ARM64: Testing exception
9256 19:55:30.654257 ARM64: Done test exception
9257 19:55:30.654338 Enumerating buses...
9258 19:55:30.657701 Show all devs... Before device enumeration.
9259 19:55:30.660512 Root Device: enabled 1
9260 19:55:30.663795 CPU_CLUSTER: 0: enabled 1
9261 19:55:30.663876 CPU: 00: enabled 1
9262 19:55:30.667104 Compare with tree...
9263 19:55:30.667184 Root Device: enabled 1
9264 19:55:30.670308 CPU_CLUSTER: 0: enabled 1
9265 19:55:30.673680 CPU: 00: enabled 1
9266 19:55:30.673761 Root Device scanning...
9267 19:55:30.676937 scan_static_bus for Root Device
9268 19:55:30.680177 CPU_CLUSTER: 0 enabled
9269 19:55:30.684399 scan_static_bus for Root Device done
9270 19:55:30.687244 scan_bus: bus Root Device finished in 8 msecs
9271 19:55:30.687325 done
9272 19:55:30.693584 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9273 19:55:30.696850 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9274 19:55:30.703205 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9275 19:55:30.710108 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9276 19:55:30.710189 Allocating resources...
9277 19:55:30.713239 Reading resources...
9278 19:55:30.716491 Root Device read_resources bus 0 link: 0
9279 19:55:30.720305 DRAM rank0 size:0x100000000,
9280 19:55:30.720385 DRAM rank1 size=0x100000000
9281 19:55:30.726830 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9282 19:55:30.726911 CPU: 00 missing read_resources
9283 19:55:30.733192 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9284 19:55:30.736373 Root Device read_resources bus 0 link: 0 done
9285 19:55:30.739695 Done reading resources.
9286 19:55:30.743096 Show resources in subtree (Root Device)...After reading.
9287 19:55:30.746313 Root Device child on link 0 CPU_CLUSTER: 0
9288 19:55:30.749706 CPU_CLUSTER: 0 child on link 0 CPU: 00
9289 19:55:30.759775 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9290 19:55:30.759857 CPU: 00
9291 19:55:30.766072 Root Device assign_resources, bus 0 link: 0
9292 19:55:30.769697 CPU_CLUSTER: 0 missing set_resources
9293 19:55:30.772741 Root Device assign_resources, bus 0 link: 0 done
9294 19:55:30.772822 Done setting resources.
9295 19:55:30.779416 Show resources in subtree (Root Device)...After assigning values.
9296 19:55:30.782548 Root Device child on link 0 CPU_CLUSTER: 0
9297 19:55:30.789634 CPU_CLUSTER: 0 child on link 0 CPU: 00
9298 19:55:30.795776 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9299 19:55:30.799098 CPU: 00
9300 19:55:30.799179 Done allocating resources.
9301 19:55:30.805967 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9302 19:55:30.806049 Enabling resources...
9303 19:55:30.809088 done.
9304 19:55:30.812105 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9305 19:55:30.815919 Initializing devices...
9306 19:55:30.816018 Root Device init
9307 19:55:30.819469 init hardware done!
9308 19:55:30.819575 0x00000018: ctrlr->caps
9309 19:55:30.822489 52.000 MHz: ctrlr->f_max
9310 19:55:30.825582 0.400 MHz: ctrlr->f_min
9311 19:55:30.825665 0x40ff8080: ctrlr->voltages
9312 19:55:30.829380 sclk: 390625
9313 19:55:30.829460 Bus Width = 1
9314 19:55:30.832249 sclk: 390625
9315 19:55:30.832329 Bus Width = 1
9316 19:55:30.835630 Early init status = 3
9317 19:55:30.839271 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9318 19:55:30.843719 in-header: 03 fc 00 00 01 00 00 00
9319 19:55:30.846861 in-data: 00
9320 19:55:30.849854 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9321 19:55:30.854607 in-header: 03 fd 00 00 00 00 00 00
9322 19:55:30.858286 in-data:
9323 19:55:30.861541 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9324 19:55:30.864811 in-header: 03 fc 00 00 01 00 00 00
9325 19:55:30.868546 in-data: 00
9326 19:55:30.871532 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9327 19:55:30.878218 in-header: 03 fd 00 00 00 00 00 00
9328 19:55:30.881338 in-data:
9329 19:55:30.884649 [SSUSB] Setting up USB HOST controller...
9330 19:55:30.888114 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9331 19:55:30.891688 [SSUSB] phy power-on done.
9332 19:55:30.894676 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9333 19:55:30.901132 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9334 19:55:30.905131 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9335 19:55:30.910912 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9336 19:55:30.917986 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9337 19:55:30.924454 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9338 19:55:30.931014 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9339 19:55:30.937548 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9340 19:55:30.941164 SPM: binary array size = 0x9dc
9341 19:55:30.944260 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9342 19:55:30.951237 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9343 19:55:30.957630 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9344 19:55:30.963837 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9345 19:55:30.967212 configure_display: Starting display init
9346 19:55:31.001588 anx7625_power_on_init: Init interface.
9347 19:55:31.004930 anx7625_disable_pd_protocol: Disabled PD feature.
9348 19:55:31.007953 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9349 19:55:31.036307 anx7625_start_dp_work: Secure OCM version=00
9350 19:55:31.039033 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9351 19:55:31.054788 sp_tx_get_edid_block: EDID Block = 1
9352 19:55:31.156595 Extracted contents:
9353 19:55:31.159869 header: 00 ff ff ff ff ff ff 00
9354 19:55:31.163035 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9355 19:55:31.166389 version: 01 04
9356 19:55:31.169537 basic params: 95 1f 11 78 0a
9357 19:55:31.173010 chroma info: 76 90 94 55 54 90 27 21 50 54
9358 19:55:31.176065 established: 00 00 00
9359 19:55:31.183011 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9360 19:55:31.186238 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9361 19:55:31.192752 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9362 19:55:31.199619 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9363 19:55:31.205778 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9364 19:55:31.209319 extensions: 00
9365 19:55:31.209425 checksum: fb
9366 19:55:31.209517
9367 19:55:31.215900 Manufacturer: IVO Model 57d Serial Number 0
9368 19:55:31.215984 Made week 0 of 2020
9369 19:55:31.218935 EDID version: 1.4
9370 19:55:31.219016 Digital display
9371 19:55:31.222482 6 bits per primary color channel
9372 19:55:31.222563 DisplayPort interface
9373 19:55:31.226084 Maximum image size: 31 cm x 17 cm
9374 19:55:31.228773 Gamma: 220%
9375 19:55:31.228854 Check DPMS levels
9376 19:55:31.235551 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9377 19:55:31.238943 First detailed timing is preferred timing
9378 19:55:31.239024 Established timings supported:
9379 19:55:31.242134 Standard timings supported:
9380 19:55:31.245399 Detailed timings
9381 19:55:31.249245 Hex of detail: 383680a07038204018303c0035ae10000019
9382 19:55:31.255426 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9383 19:55:31.258845 0780 0798 07c8 0820 hborder 0
9384 19:55:31.261979 0438 043b 0447 0458 vborder 0
9385 19:55:31.264965 -hsync -vsync
9386 19:55:31.265046 Did detailed timing
9387 19:55:31.272139 Hex of detail: 000000000000000000000000000000000000
9388 19:55:31.275349 Manufacturer-specified data, tag 0
9389 19:55:31.278809 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9390 19:55:31.282208 ASCII string: InfoVision
9391 19:55:31.284826 Hex of detail: 000000fe00523134304e574635205248200a
9392 19:55:31.288379 ASCII string: R140NWF5 RH
9393 19:55:31.288459 Checksum
9394 19:55:31.291708 Checksum: 0xfb (valid)
9395 19:55:31.295109 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9396 19:55:31.298102 DSI data_rate: 832800000 bps
9397 19:55:31.304898 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9398 19:55:31.308128 anx7625_parse_edid: pixelclock(138800).
9399 19:55:31.311566 hactive(1920), hsync(48), hfp(24), hbp(88)
9400 19:55:31.314739 vactive(1080), vsync(12), vfp(3), vbp(17)
9401 19:55:31.317920 anx7625_dsi_config: config dsi.
9402 19:55:31.324565 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9403 19:55:31.338752 anx7625_dsi_config: success to config DSI
9404 19:55:31.341891 anx7625_dp_start: MIPI phy setup OK.
9405 19:55:31.345289 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9406 19:55:31.348293 mtk_ddp_mode_set invalid vrefresh 60
9407 19:55:31.351704 main_disp_path_setup
9408 19:55:31.351794 ovl_layer_smi_id_en
9409 19:55:31.355338 ovl_layer_smi_id_en
9410 19:55:31.355418 ccorr_config
9411 19:55:31.355482 aal_config
9412 19:55:31.358399 gamma_config
9413 19:55:31.358479 postmask_config
9414 19:55:31.361747 dither_config
9415 19:55:31.365275 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9416 19:55:31.371503 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9417 19:55:31.375213 Root Device init finished in 555 msecs
9418 19:55:31.379071 CPU_CLUSTER: 0 init
9419 19:55:31.384862 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9420 19:55:31.391451 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9421 19:55:31.391531 APU_MBOX 0x190000b0 = 0x10001
9422 19:55:31.394497 APU_MBOX 0x190001b0 = 0x10001
9423 19:55:31.398112 APU_MBOX 0x190005b0 = 0x10001
9424 19:55:31.401406 APU_MBOX 0x190006b0 = 0x10001
9425 19:55:31.407606 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9426 19:55:31.417509 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9427 19:55:31.430108 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9428 19:55:31.436734 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9429 19:55:31.448605 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9430 19:55:31.457646 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9431 19:55:31.460944 CPU_CLUSTER: 0 init finished in 81 msecs
9432 19:55:31.464034 Devices initialized
9433 19:55:31.467289 Show all devs... After init.
9434 19:55:31.467370 Root Device: enabled 1
9435 19:55:31.470928 CPU_CLUSTER: 0: enabled 1
9436 19:55:31.474396 CPU: 00: enabled 1
9437 19:55:31.476938 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9438 19:55:31.480533 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9439 19:55:31.483499 ELOG: NV offset 0x57f000 size 0x1000
9440 19:55:31.490728 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9441 19:55:31.497219 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9442 19:55:31.500324 ELOG: Event(17) added with size 13 at 2023-10-28 19:55:32 UTC
9443 19:55:31.506750 out: cmd=0x121: 03 db 21 01 00 00 00 00
9444 19:55:31.510097 in-header: 03 cb 00 00 2c 00 00 00
9445 19:55:31.519703 in-data: 94 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9446 19:55:31.526650 ELOG: Event(A1) added with size 10 at 2023-10-28 19:55:32 UTC
9447 19:55:31.533408 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9448 19:55:31.539877 ELOG: Event(A0) added with size 9 at 2023-10-28 19:55:32 UTC
9449 19:55:31.543184 elog_add_boot_reason: Logged dev mode boot
9450 19:55:31.549671 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9451 19:55:31.549752 Finalize devices...
9452 19:55:31.552774 Devices finalized
9453 19:55:31.556149 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9454 19:55:31.559649 Writing coreboot table at 0xffe64000
9455 19:55:31.562986 0. 000000000010a000-0000000000113fff: RAMSTAGE
9456 19:55:31.569584 1. 0000000040000000-00000000400fffff: RAM
9457 19:55:31.572777 2. 0000000040100000-000000004032afff: RAMSTAGE
9458 19:55:31.575941 3. 000000004032b000-00000000545fffff: RAM
9459 19:55:31.579247 4. 0000000054600000-000000005465ffff: BL31
9460 19:55:31.582666 5. 0000000054660000-00000000ffe63fff: RAM
9461 19:55:31.589346 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9462 19:55:31.592657 7. 0000000100000000-000000023fffffff: RAM
9463 19:55:31.595923 Passing 5 GPIOs to payload:
9464 19:55:31.599475 NAME | PORT | POLARITY | VALUE
9465 19:55:31.606609 EC in RW | 0x000000aa | low | undefined
9466 19:55:31.609136 EC interrupt | 0x00000005 | low | undefined
9467 19:55:31.615641 TPM interrupt | 0x000000ab | high | undefined
9468 19:55:31.619897 SD card detect | 0x00000011 | high | undefined
9469 19:55:31.622569 speaker enable | 0x00000093 | high | undefined
9470 19:55:31.625205 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9471 19:55:31.629123 in-header: 03 f9 00 00 02 00 00 00
9472 19:55:31.632362 in-data: 02 00
9473 19:55:31.635932 ADC[4]: Raw value=904139 ID=7
9474 19:55:31.639100 ADC[3]: Raw value=214021 ID=1
9475 19:55:31.639181 RAM Code: 0x71
9476 19:55:31.642262 ADC[6]: Raw value=75406 ID=0
9477 19:55:31.645828 ADC[5]: Raw value=212912 ID=1
9478 19:55:31.645908 SKU Code: 0x1
9479 19:55:31.652218 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a16d
9480 19:55:31.652311 coreboot table: 964 bytes.
9481 19:55:31.655677 IMD ROOT 0. 0xfffff000 0x00001000
9482 19:55:31.658840 IMD SMALL 1. 0xffffe000 0x00001000
9483 19:55:31.662507 RO MCACHE 2. 0xffffc000 0x00001104
9484 19:55:31.665164 CONSOLE 3. 0xfff7c000 0x00080000
9485 19:55:31.668702 FMAP 4. 0xfff7b000 0x00000452
9486 19:55:31.671694 TIME STAMP 5. 0xfff7a000 0x00000910
9487 19:55:31.675186 VBOOT WORK 6. 0xfff66000 0x00014000
9488 19:55:31.678503 RAMOOPS 7. 0xffe66000 0x00100000
9489 19:55:31.681797 COREBOOT 8. 0xffe64000 0x00002000
9490 19:55:31.685007 IMD small region:
9491 19:55:31.688582 IMD ROOT 0. 0xffffec00 0x00000400
9492 19:55:31.691705 VPD 1. 0xffffeb80 0x0000006c
9493 19:55:31.695144 MMC STATUS 2. 0xffffeb60 0x00000004
9494 19:55:31.701931 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9495 19:55:31.702034 Probing TPM: done!
9496 19:55:31.705249 Connected to device vid:did:rid of 1ae0:0028:00
9497 19:55:31.716643 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9498 19:55:31.720100 Initialized TPM device CR50 revision 0
9499 19:55:31.723486 Checking cr50 for pending updates
9500 19:55:31.727337 Reading cr50 TPM mode
9501 19:55:31.735719 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9502 19:55:31.742033 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9503 19:55:31.782693 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9504 19:55:31.785729 Checking segment from ROM address 0x40100000
9505 19:55:31.789017 Checking segment from ROM address 0x4010001c
9506 19:55:31.795667 Loading segment from ROM address 0x40100000
9507 19:55:31.795783 code (compression=0)
9508 19:55:31.805590 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9509 19:55:31.811971 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9510 19:55:31.812078 it's not compressed!
9511 19:55:31.819253 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9512 19:55:31.825493 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9513 19:55:31.843181 Loading segment from ROM address 0x4010001c
9514 19:55:31.843283 Entry Point 0x80000000
9515 19:55:31.846301 Loaded segments
9516 19:55:31.849355 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9517 19:55:31.856246 Jumping to boot code at 0x80000000(0xffe64000)
9518 19:55:31.862775 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9519 19:55:31.869586 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9520 19:55:31.877000 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9521 19:55:31.880844 Checking segment from ROM address 0x40100000
9522 19:55:31.884145 Checking segment from ROM address 0x4010001c
9523 19:55:31.890607 Loading segment from ROM address 0x40100000
9524 19:55:31.890711 code (compression=1)
9525 19:55:31.897151 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9526 19:55:31.907245 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9527 19:55:31.907349 using LZMA
9528 19:55:31.915905 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9529 19:55:31.922370 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9530 19:55:31.925765 Loading segment from ROM address 0x4010001c
9531 19:55:31.925870 Entry Point 0x54601000
9532 19:55:31.929138 Loaded segments
9533 19:55:31.932555 NOTICE: MT8192 bl31_setup
9534 19:55:31.939049 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9535 19:55:31.942642 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9536 19:55:31.945909 WARNING: region 0:
9537 19:55:31.949234 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 19:55:31.949312 WARNING: region 1:
9539 19:55:31.955867 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9540 19:55:31.959320 WARNING: region 2:
9541 19:55:31.962756 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9542 19:55:31.966195 WARNING: region 3:
9543 19:55:31.969145 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9544 19:55:31.972318 WARNING: region 4:
9545 19:55:31.979141 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9546 19:55:31.979247 WARNING: region 5:
9547 19:55:31.982374 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 19:55:31.985555 WARNING: region 6:
9549 19:55:31.988838 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 19:55:31.992416 WARNING: region 7:
9551 19:55:31.995650 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9552 19:55:32.001990 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9553 19:55:32.005403 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9554 19:55:32.008650 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9555 19:55:32.015501 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9556 19:55:32.018497 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9557 19:55:32.025849 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9558 19:55:32.028768 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9559 19:55:32.031836 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9560 19:55:32.038517 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9561 19:55:32.041721 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9562 19:55:32.045243 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9563 19:55:32.052101 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9564 19:55:32.055250 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9565 19:55:32.062033 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9566 19:55:32.064931 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9567 19:55:32.068319 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9568 19:55:32.075339 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9569 19:55:32.078332 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9570 19:55:32.081711 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9571 19:55:32.088509 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9572 19:55:32.091605 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9573 19:55:32.099416 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9574 19:55:32.101579 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9575 19:55:32.104871 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9576 19:55:32.111531 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9577 19:55:32.114921 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9578 19:55:32.121338 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9579 19:55:32.124779 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9580 19:55:32.128205 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9581 19:55:32.134766 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9582 19:55:32.138694 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9583 19:55:32.144720 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9584 19:55:32.147972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9585 19:55:32.151668 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9586 19:55:32.155074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9587 19:55:32.162116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9588 19:55:32.164992 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9589 19:55:32.168183 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9590 19:55:32.171382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9591 19:55:32.177669 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9592 19:55:32.181207 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9593 19:55:32.184671 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9594 19:55:32.187712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9595 19:55:32.194383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9596 19:55:32.198116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9597 19:55:32.201053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9598 19:55:32.204618 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9599 19:55:32.211071 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9600 19:55:32.214736 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9601 19:55:32.221350 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9602 19:55:32.224547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9603 19:55:32.228315 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9604 19:55:32.234418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9605 19:55:32.237990 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9606 19:55:32.244646 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9607 19:55:32.247713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9608 19:55:32.254164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9609 19:55:32.257487 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9610 19:55:32.261431 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9611 19:55:32.267424 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9612 19:55:32.271037 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9613 19:55:32.277656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9614 19:55:32.281152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9615 19:55:32.287265 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9616 19:55:32.290812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9617 19:55:32.297390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9618 19:55:32.301145 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9619 19:55:32.303895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9620 19:55:32.310785 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9621 19:55:32.313950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9622 19:55:32.320342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9623 19:55:32.323951 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9624 19:55:32.330427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9625 19:55:32.333756 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9626 19:55:32.336928 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9627 19:55:32.343573 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9628 19:55:32.347279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9629 19:55:32.353680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9630 19:55:32.357235 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9631 19:55:32.363647 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9632 19:55:32.367014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9633 19:55:32.373575 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9634 19:55:32.377027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9635 19:55:32.380416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9636 19:55:32.386928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9637 19:55:32.390034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9638 19:55:32.397100 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9639 19:55:32.400581 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9640 19:55:32.406855 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9641 19:55:32.410053 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9642 19:55:32.416771 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9643 19:55:32.420113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9644 19:55:32.423139 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9645 19:55:32.429654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9646 19:55:32.433151 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9647 19:55:32.439884 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9648 19:55:32.443591 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9649 19:55:32.446344 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9650 19:55:32.453264 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9651 19:55:32.456391 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9652 19:55:32.460351 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9653 19:55:32.463019 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9654 19:55:32.469416 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9655 19:55:32.473482 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9656 19:55:32.480056 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9657 19:55:32.482871 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9658 19:55:32.489537 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9659 19:55:32.492605 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9660 19:55:32.495869 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9661 19:55:32.503031 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9662 19:55:32.506180 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9663 19:55:32.512816 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9664 19:55:32.516433 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9665 19:55:32.519880 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9666 19:55:32.525887 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9667 19:55:32.529220 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9668 19:55:32.532832 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9669 19:55:32.539210 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9670 19:55:32.543256 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9671 19:55:32.546425 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9672 19:55:32.549590 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9673 19:55:32.556120 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9674 19:55:32.559354 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9675 19:55:32.562858 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9676 19:55:32.569922 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9677 19:55:32.572773 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9678 19:55:32.575892 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9679 19:55:32.582364 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9680 19:55:32.585636 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9681 19:55:32.592031 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9682 19:55:32.595969 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9683 19:55:32.598717 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9684 19:55:32.605476 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9685 19:55:32.608672 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9686 19:55:32.615163 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9687 19:55:32.618732 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9688 19:55:32.621902 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9689 19:55:32.628989 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9690 19:55:32.631878 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9691 19:55:32.638629 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9692 19:55:32.642292 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9693 19:55:32.645124 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9694 19:55:32.652072 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9695 19:55:32.655247 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9696 19:55:32.661684 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9697 19:55:32.665517 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9698 19:55:32.668291 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9699 19:55:32.674965 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9700 19:55:32.679121 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9701 19:55:32.685427 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9702 19:55:32.688074 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9703 19:55:32.691696 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9704 19:55:32.698165 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9705 19:55:32.701577 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9706 19:55:32.708304 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9707 19:55:32.711658 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9708 19:55:32.714911 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9709 19:55:32.721398 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9710 19:55:32.724600 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9711 19:55:32.728010 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9712 19:55:32.734570 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9713 19:55:32.737829 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9714 19:55:32.744472 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9715 19:55:32.747506 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9716 19:55:32.754616 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9717 19:55:32.757751 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9718 19:55:32.760659 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9719 19:55:32.767604 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9720 19:55:32.770681 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9721 19:55:32.777413 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9722 19:55:32.781080 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9723 19:55:32.783905 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9724 19:55:32.790268 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9725 19:55:32.793701 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9726 19:55:32.800285 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9727 19:55:32.803979 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9728 19:55:32.807418 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9729 19:55:32.813710 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9730 19:55:32.817256 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9731 19:55:32.820659 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9732 19:55:32.827051 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9733 19:55:32.830397 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9734 19:55:32.837082 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9735 19:55:32.840232 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9736 19:55:32.843476 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9737 19:55:32.850703 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9738 19:55:32.853450 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9739 19:55:32.860067 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9740 19:55:32.863572 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9741 19:55:32.870100 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9742 19:55:32.873382 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9743 19:55:32.876994 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9744 19:55:32.883243 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9745 19:55:32.886579 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9746 19:55:32.893074 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9747 19:55:32.896173 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9748 19:55:32.899660 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9749 19:55:32.906390 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9750 19:55:32.909714 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9751 19:55:32.916156 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9752 19:55:32.919608 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9753 19:55:32.925988 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9754 19:55:32.929488 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9755 19:55:32.932965 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9756 19:55:32.939149 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9757 19:55:32.942614 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9758 19:55:32.949371 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9759 19:55:32.952662 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9760 19:55:32.959026 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9761 19:55:32.963061 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9762 19:55:32.965887 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9763 19:55:32.972367 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9764 19:55:32.976063 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9765 19:55:32.981990 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9766 19:55:32.985280 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9767 19:55:32.991836 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9768 19:55:32.995128 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9769 19:55:32.998727 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9770 19:55:33.005343 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9771 19:55:33.008733 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9772 19:55:33.014918 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9773 19:55:33.018995 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9774 19:55:33.025068 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9775 19:55:33.028336 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9776 19:55:33.031340 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9777 19:55:33.038347 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9778 19:55:33.041613 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9779 19:55:33.047935 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9780 19:55:33.051538 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9781 19:55:33.055058 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9782 19:55:33.058563 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9783 19:55:33.064514 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9784 19:55:33.068414 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9785 19:55:33.071302 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9786 19:55:33.078022 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9787 19:55:33.081618 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9788 19:55:33.084677 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9789 19:55:33.091171 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9790 19:55:33.094378 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9791 19:55:33.097683 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9792 19:55:33.104375 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9793 19:55:33.107787 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9794 19:55:33.114388 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9795 19:55:33.117960 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9796 19:55:33.120596 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9797 19:55:33.127596 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9798 19:55:33.130625 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9799 19:55:33.137251 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9800 19:55:33.140589 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9801 19:55:33.143819 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9802 19:55:33.150386 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9803 19:55:33.153835 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9804 19:55:33.157551 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9805 19:55:33.163770 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9806 19:55:33.167259 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9807 19:55:33.170490 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9808 19:55:33.177618 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9809 19:55:33.180074 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9810 19:55:33.183919 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9811 19:55:33.190214 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9812 19:55:33.193419 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9813 19:55:33.200206 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9814 19:55:33.203317 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9815 19:55:33.206348 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9816 19:55:33.213115 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9817 19:55:33.217003 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9818 19:55:33.223024 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9819 19:55:33.226339 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9820 19:55:33.229631 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9821 19:55:33.233131 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9822 19:55:33.239897 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9823 19:55:33.242743 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9824 19:55:33.246330 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9825 19:55:33.249351 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9826 19:55:33.256241 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9827 19:55:33.259521 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9828 19:55:33.262603 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9829 19:55:33.265810 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9830 19:55:33.272642 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9831 19:55:33.275880 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9832 19:55:33.278918 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9833 19:55:33.285687 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9834 19:55:33.288753 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9835 19:55:33.295831 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9836 19:55:33.299107 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9837 19:55:33.301988 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9838 19:55:33.309054 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9839 19:55:33.312244 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9840 19:55:33.318775 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9841 19:55:33.321805 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9842 19:55:33.325168 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9843 19:55:33.331963 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9844 19:55:33.335146 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9845 19:55:33.341732 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9846 19:55:33.345031 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9847 19:55:33.351676 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9848 19:55:33.354992 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9849 19:55:33.358473 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9850 19:55:33.364954 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9851 19:55:33.368609 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9852 19:55:33.375121 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9853 19:55:33.378510 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9854 19:55:33.381352 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9855 19:55:33.387863 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9856 19:55:33.392120 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9857 19:55:33.398026 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9858 19:55:33.401477 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9859 19:55:33.404855 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9860 19:55:33.411266 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9861 19:55:33.414219 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9862 19:55:33.420949 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9863 19:55:33.424087 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9864 19:55:33.431018 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9865 19:55:33.434217 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9866 19:55:33.437192 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9867 19:55:33.443994 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9868 19:55:33.447400 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9869 19:55:33.454517 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9870 19:55:33.457130 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9871 19:55:33.463568 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9872 19:55:33.467073 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9873 19:55:33.470963 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9874 19:55:33.476777 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9875 19:55:33.480056 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9876 19:55:33.486661 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9877 19:55:33.490351 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9878 19:55:33.493592 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9879 19:55:33.500149 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9880 19:55:33.503674 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9881 19:55:33.509775 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9882 19:55:33.513350 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9883 19:55:33.519916 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9884 19:55:33.523315 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9885 19:55:33.527079 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9886 19:55:33.533303 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9887 19:55:33.536430 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9888 19:55:33.542705 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9889 19:55:33.545975 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9890 19:55:33.549510 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9891 19:55:33.555967 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9892 19:55:33.559135 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9893 19:55:33.565842 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9894 19:55:33.569207 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9895 19:55:33.575591 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9896 19:55:33.579408 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9897 19:55:33.582625 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9898 19:55:33.588832 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9899 19:55:33.592510 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9900 19:55:33.598932 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9901 19:55:33.601975 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9902 19:55:33.608698 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9903 19:55:33.611902 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9904 19:55:33.615176 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9905 19:55:33.621873 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9906 19:55:33.625234 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9907 19:55:33.632128 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9908 19:55:33.635536 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9909 19:55:33.641662 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9910 19:55:33.645140 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9911 19:55:33.648552 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9912 19:55:33.654978 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9913 19:55:33.658236 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9914 19:55:33.665390 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9915 19:55:33.668932 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9916 19:55:33.674834 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9917 19:55:33.678235 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9918 19:55:33.685040 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9919 19:55:33.688024 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9920 19:55:33.691661 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9921 19:55:33.697827 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9922 19:55:33.701130 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9923 19:55:33.707956 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9924 19:55:33.711521 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9925 19:55:33.717571 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9926 19:55:33.720942 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9927 19:55:33.724497 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9928 19:55:33.731479 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9929 19:55:33.734529 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9930 19:55:33.741040 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9931 19:55:33.744241 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9932 19:55:33.750782 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9933 19:55:33.754308 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9934 19:55:33.760837 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9935 19:55:33.764201 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9936 19:55:33.767196 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9937 19:55:33.774386 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9938 19:55:33.777025 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9939 19:55:33.783910 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9940 19:55:33.787010 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9941 19:55:33.793735 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9942 19:55:33.797364 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9943 19:55:33.803855 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9944 19:55:33.806979 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9945 19:55:33.809999 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9946 19:55:33.816877 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9947 19:55:33.819979 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9948 19:55:33.826725 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9949 19:55:33.830506 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9950 19:55:33.836899 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9951 19:55:33.840091 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9952 19:55:33.846633 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9953 19:55:33.850352 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9954 19:55:33.853415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9955 19:55:33.859913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9956 19:55:33.863160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9957 19:55:33.870075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9958 19:55:33.873439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9959 19:55:33.879858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9960 19:55:33.883002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9961 19:55:33.890440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9962 19:55:33.893114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9963 19:55:33.899382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9964 19:55:33.902548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9965 19:55:33.909309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9966 19:55:33.912746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9967 19:55:33.919288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9968 19:55:33.922353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9969 19:55:33.929215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9970 19:55:33.932148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9971 19:55:33.935569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9972 19:55:33.942346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9973 19:55:33.945341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9974 19:55:33.952472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9975 19:55:33.955664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9976 19:55:33.962228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9977 19:55:33.966088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9978 19:55:33.971802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9979 19:55:33.979185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9980 19:55:33.982019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9981 19:55:33.988346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9982 19:55:33.991938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9983 19:55:33.998386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9984 19:55:34.001640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9985 19:55:34.008157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9986 19:55:34.011429 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9987 19:55:34.011510 INFO: [APUAPC] vio 0
9988 19:55:34.018968 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9989 19:55:34.022179 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9990 19:55:34.025517 INFO: [APUAPC] D0_APC_0: 0x400510
9991 19:55:34.029059 INFO: [APUAPC] D0_APC_1: 0x0
9992 19:55:34.032287 INFO: [APUAPC] D0_APC_2: 0x1540
9993 19:55:34.035380 INFO: [APUAPC] D0_APC_3: 0x0
9994 19:55:34.038737 INFO: [APUAPC] D1_APC_0: 0xffffffff
9995 19:55:34.042625 INFO: [APUAPC] D1_APC_1: 0xffffffff
9996 19:55:34.045589 INFO: [APUAPC] D1_APC_2: 0x3fffff
9997 19:55:34.048952 INFO: [APUAPC] D1_APC_3: 0x0
9998 19:55:34.052134 INFO: [APUAPC] D2_APC_0: 0xffffffff
9999 19:55:34.055687 INFO: [APUAPC] D2_APC_1: 0xffffffff
10000 19:55:34.058564 INFO: [APUAPC] D2_APC_2: 0x3fffff
10001 19:55:34.062048 INFO: [APUAPC] D2_APC_3: 0x0
10002 19:55:34.065457 INFO: [APUAPC] D3_APC_0: 0xffffffff
10003 19:55:34.068634 INFO: [APUAPC] D3_APC_1: 0xffffffff
10004 19:55:34.072422 INFO: [APUAPC] D3_APC_2: 0x3fffff
10005 19:55:34.075158 INFO: [APUAPC] D3_APC_3: 0x0
10006 19:55:34.078738 INFO: [APUAPC] D4_APC_0: 0xffffffff
10007 19:55:34.081668 INFO: [APUAPC] D4_APC_1: 0xffffffff
10008 19:55:34.085134 INFO: [APUAPC] D4_APC_2: 0x3fffff
10009 19:55:34.088250 INFO: [APUAPC] D4_APC_3: 0x0
10010 19:55:34.091634 INFO: [APUAPC] D5_APC_0: 0xffffffff
10011 19:55:34.094752 INFO: [APUAPC] D5_APC_1: 0xffffffff
10012 19:55:34.098241 INFO: [APUAPC] D5_APC_2: 0x3fffff
10013 19:55:34.101315 INFO: [APUAPC] D5_APC_3: 0x0
10014 19:55:34.104741 INFO: [APUAPC] D6_APC_0: 0xffffffff
10015 19:55:34.108173 INFO: [APUAPC] D6_APC_1: 0xffffffff
10016 19:55:34.111402 INFO: [APUAPC] D6_APC_2: 0x3fffff
10017 19:55:34.111482 INFO: [APUAPC] D6_APC_3: 0x0
10018 19:55:34.117961 INFO: [APUAPC] D7_APC_0: 0xffffffff
10019 19:55:34.121264 INFO: [APUAPC] D7_APC_1: 0xffffffff
10020 19:55:34.124561 INFO: [APUAPC] D7_APC_2: 0x3fffff
10021 19:55:34.124642 INFO: [APUAPC] D7_APC_3: 0x0
10022 19:55:34.127757 INFO: [APUAPC] D8_APC_0: 0xffffffff
10023 19:55:34.131194 INFO: [APUAPC] D8_APC_1: 0xffffffff
10024 19:55:34.135221 INFO: [APUAPC] D8_APC_2: 0x3fffff
10025 19:55:34.137928 INFO: [APUAPC] D8_APC_3: 0x0
10026 19:55:34.141405 INFO: [APUAPC] D9_APC_0: 0xffffffff
10027 19:55:34.144538 INFO: [APUAPC] D9_APC_1: 0xffffffff
10028 19:55:34.147981 INFO: [APUAPC] D9_APC_2: 0x3fffff
10029 19:55:34.151208 INFO: [APUAPC] D9_APC_3: 0x0
10030 19:55:34.154634 INFO: [APUAPC] D10_APC_0: 0xffffffff
10031 19:55:34.157458 INFO: [APUAPC] D10_APC_1: 0xffffffff
10032 19:55:34.160854 INFO: [APUAPC] D10_APC_2: 0x3fffff
10033 19:55:34.164389 INFO: [APUAPC] D10_APC_3: 0x0
10034 19:55:34.167681 INFO: [APUAPC] D11_APC_0: 0xffffffff
10035 19:55:34.170967 INFO: [APUAPC] D11_APC_1: 0xffffffff
10036 19:55:34.173969 INFO: [APUAPC] D11_APC_2: 0x3fffff
10037 19:55:34.177755 INFO: [APUAPC] D11_APC_3: 0x0
10038 19:55:34.180517 INFO: [APUAPC] D12_APC_0: 0xffffffff
10039 19:55:34.187271 INFO: [APUAPC] D12_APC_1: 0xffffffff
10040 19:55:34.190579 INFO: [APUAPC] D12_APC_2: 0x3fffff
10041 19:55:34.190660 INFO: [APUAPC] D12_APC_3: 0x0
10042 19:55:34.193905 INFO: [APUAPC] D13_APC_0: 0xffffffff
10043 19:55:34.200387 INFO: [APUAPC] D13_APC_1: 0xffffffff
10044 19:55:34.203847 INFO: [APUAPC] D13_APC_2: 0x3fffff
10045 19:55:34.203949 INFO: [APUAPC] D13_APC_3: 0x0
10046 19:55:34.210644 INFO: [APUAPC] D14_APC_0: 0xffffffff
10047 19:55:34.213987 INFO: [APUAPC] D14_APC_1: 0xffffffff
10048 19:55:34.217223 INFO: [APUAPC] D14_APC_2: 0x3fffff
10049 19:55:34.217305 INFO: [APUAPC] D14_APC_3: 0x0
10050 19:55:34.223491 INFO: [APUAPC] D15_APC_0: 0xffffffff
10051 19:55:34.227262 INFO: [APUAPC] D15_APC_1: 0xffffffff
10052 19:55:34.230347 INFO: [APUAPC] D15_APC_2: 0x3fffff
10053 19:55:34.233706 INFO: [APUAPC] D15_APC_3: 0x0
10054 19:55:34.233801 INFO: [APUAPC] APC_CON: 0x4
10055 19:55:34.236577 INFO: [NOCDAPC] D0_APC_0: 0x0
10056 19:55:34.240082 INFO: [NOCDAPC] D0_APC_1: 0x0
10057 19:55:34.243557 INFO: [NOCDAPC] D1_APC_0: 0x0
10058 19:55:34.246398 INFO: [NOCDAPC] D1_APC_1: 0xfff
10059 19:55:34.249664 INFO: [NOCDAPC] D2_APC_0: 0x0
10060 19:55:34.253407 INFO: [NOCDAPC] D2_APC_1: 0xfff
10061 19:55:34.257239 INFO: [NOCDAPC] D3_APC_0: 0x0
10062 19:55:34.259671 INFO: [NOCDAPC] D3_APC_1: 0xfff
10063 19:55:34.263049 INFO: [NOCDAPC] D4_APC_0: 0x0
10064 19:55:34.266833 INFO: [NOCDAPC] D4_APC_1: 0xfff
10065 19:55:34.266914 INFO: [NOCDAPC] D5_APC_0: 0x0
10066 19:55:34.269425 INFO: [NOCDAPC] D5_APC_1: 0xfff
10067 19:55:34.273283 INFO: [NOCDAPC] D6_APC_0: 0x0
10068 19:55:34.276596 INFO: [NOCDAPC] D6_APC_1: 0xfff
10069 19:55:34.279563 INFO: [NOCDAPC] D7_APC_0: 0x0
10070 19:55:34.282609 INFO: [NOCDAPC] D7_APC_1: 0xfff
10071 19:55:34.286094 INFO: [NOCDAPC] D8_APC_0: 0x0
10072 19:55:34.289251 INFO: [NOCDAPC] D8_APC_1: 0xfff
10073 19:55:34.292400 INFO: [NOCDAPC] D9_APC_0: 0x0
10074 19:55:34.295741 INFO: [NOCDAPC] D9_APC_1: 0xfff
10075 19:55:34.298984 INFO: [NOCDAPC] D10_APC_0: 0x0
10076 19:55:34.302538 INFO: [NOCDAPC] D10_APC_1: 0xfff
10077 19:55:34.305523 INFO: [NOCDAPC] D11_APC_0: 0x0
10078 19:55:34.309119 INFO: [NOCDAPC] D11_APC_1: 0xfff
10079 19:55:34.309200 INFO: [NOCDAPC] D12_APC_0: 0x0
10080 19:55:34.312412 INFO: [NOCDAPC] D12_APC_1: 0xfff
10081 19:55:34.316007 INFO: [NOCDAPC] D13_APC_0: 0x0
10082 19:55:34.318705 INFO: [NOCDAPC] D13_APC_1: 0xfff
10083 19:55:34.321896 INFO: [NOCDAPC] D14_APC_0: 0x0
10084 19:55:34.325201 INFO: [NOCDAPC] D14_APC_1: 0xfff
10085 19:55:34.328958 INFO: [NOCDAPC] D15_APC_0: 0x0
10086 19:55:34.331922 INFO: [NOCDAPC] D15_APC_1: 0xfff
10087 19:55:34.335400 INFO: [NOCDAPC] APC_CON: 0x4
10088 19:55:34.338560 INFO: [APUAPC] set_apusys_apc done
10089 19:55:34.342152 INFO: [DEVAPC] devapc_init done
10090 19:55:34.345665 INFO: GICv3 without legacy support detected.
10091 19:55:34.348544 INFO: ARM GICv3 driver initialized in EL3
10092 19:55:34.352090 INFO: Maximum SPI INTID supported: 639
10093 19:55:34.358537 INFO: BL31: Initializing runtime services
10094 19:55:34.361789 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10095 19:55:34.365179 INFO: SPM: enable CPC mode
10096 19:55:34.371902 INFO: mcdi ready for mcusys-off-idle and system suspend
10097 19:55:34.374775 INFO: BL31: Preparing for EL3 exit to normal world
10098 19:55:34.378276 INFO: Entry point address = 0x80000000
10099 19:55:34.381571 INFO: SPSR = 0x8
10100 19:55:34.387460
10101 19:55:34.387541
10102 19:55:34.387604
10103 19:55:34.390542 Starting depthcharge on Spherion...
10104 19:55:34.390622
10105 19:55:34.390687 Wipe memory regions:
10106 19:55:34.390746
10107 19:55:34.391430 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10108 19:55:34.391530 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10109 19:55:34.391612 Setting prompt string to ['asurada:']
10110 19:55:34.391695 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10111 19:55:34.393700 [0x00000040000000, 0x00000054600000)
10112 19:55:34.516111
10113 19:55:34.516255 [0x00000054660000, 0x00000080000000)
10114 19:55:34.776606
10115 19:55:34.776740 [0x000000821a7280, 0x000000ffe64000)
10116 19:55:35.521681
10117 19:55:35.521816 [0x00000100000000, 0x00000240000000)
10118 19:55:37.411860
10119 19:55:37.415283 Initializing XHCI USB controller at 0x11200000.
10120 19:55:38.396392
10121 19:55:38.396526 R8152: Initializing
10122 19:55:38.396593
10123 19:55:38.399586 Version 9 (ocp_data = 6010)
10124 19:55:38.399667
10125 19:55:38.403091 R8152: Done initializing
10126 19:55:38.403172
10127 19:55:38.403235 Adding net device
10128 19:55:38.924490
10129 19:55:38.928024 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10130 19:55:38.928112
10131 19:55:38.928179
10132 19:55:38.928239
10133 19:55:38.928549 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10135 19:55:39.028895 asurada: tftpboot 192.168.201.1 11899579/tftp-deploy-2vc2u5r_/kernel/image.itb 11899579/tftp-deploy-2vc2u5r_/kernel/cmdline
10136 19:55:39.029038 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10137 19:55:39.029121 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10138 19:55:39.033625 tftpboot 192.168.201.1 11899579/tftp-deploy-2vc2u5r_/kernel/image.itp-deploy-2vc2u5r_/kernel/cmdline
10139 19:55:39.033709
10140 19:55:39.033773 Waiting for link
10141 19:55:39.236183
10142 19:55:39.236314 done.
10143 19:55:39.236379
10144 19:55:39.236438 MAC: f4:f5:e8:50:de:0a
10145 19:55:39.236496
10146 19:55:39.239460 Sending DHCP discover... done.
10147 19:55:39.239566
10148 19:55:39.242569 Waiting for reply... done.
10149 19:55:39.242651
10150 19:55:39.245677 Sending DHCP request... done.
10151 19:55:39.245756
10152 19:55:39.245820 Waiting for reply... done.
10153 19:55:39.245880
10154 19:55:39.249035 My ip is 192.168.201.14
10155 19:55:39.249141
10156 19:55:39.252385 The DHCP server ip is 192.168.201.1
10157 19:55:39.252466
10158 19:55:39.255718 TFTP server IP predefined by user: 192.168.201.1
10159 19:55:39.255834
10160 19:55:39.262344 Bootfile predefined by user: 11899579/tftp-deploy-2vc2u5r_/kernel/image.itb
10161 19:55:39.262425
10162 19:55:39.265714 Sending tftp read request... done.
10163 19:55:39.265794
10164 19:55:39.268766 Waiting for the transfer...
10165 19:55:39.268846
10166 19:55:39.514899 00000000 ################################################################
10167 19:55:39.515033
10168 19:55:39.743023 00080000 ################################################################
10169 19:55:39.743151
10170 19:55:39.971690 00100000 ################################################################
10171 19:55:39.971876
10172 19:55:40.196835 00180000 ################################################################
10173 19:55:40.196967
10174 19:55:40.440130 00200000 ################################################################
10175 19:55:40.440261
10176 19:55:40.671153 00280000 ################################################################
10177 19:55:40.671293
10178 19:55:40.896014 00300000 ################################################################
10179 19:55:40.896160
10180 19:55:41.120110 00380000 ################################################################
10181 19:55:41.120273
10182 19:55:41.346906 00400000 ################################################################
10183 19:55:41.347054
10184 19:55:41.573954 00480000 ################################################################
10185 19:55:41.574097
10186 19:55:41.802040 00500000 ################################################################
10187 19:55:41.802180
10188 19:55:42.025058 00580000 ################################################################
10189 19:55:42.025204
10190 19:55:42.257694 00600000 ################################################################
10191 19:55:42.257831
10192 19:55:42.484984 00680000 ################################################################
10193 19:55:42.485124
10194 19:55:42.712715 00700000 ################################################################
10195 19:55:42.712850
10196 19:55:42.939874 00780000 ################################################################
10197 19:55:42.940006
10198 19:55:43.178567 00800000 ################################################################
10199 19:55:43.178697
10200 19:55:43.410398 00880000 ################################################################
10201 19:55:43.410557
10202 19:55:43.642607 00900000 ################################################################
10203 19:55:43.642751
10204 19:55:43.869869 00980000 ################################################################
10205 19:55:43.870009
10206 19:55:44.099606 00a00000 ################################################################
10207 19:55:44.099784
10208 19:55:44.325767 00a80000 ################################################################
10209 19:55:44.325911
10210 19:55:44.549633 00b00000 ################################################################
10211 19:55:44.549780
10212 19:55:44.786122 00b80000 ################################################################
10213 19:55:44.786263
10214 19:55:45.018579 00c00000 ################################################################
10215 19:55:45.018720
10216 19:55:45.246398 00c80000 ################################################################
10217 19:55:45.246540
10218 19:55:45.474512 00d00000 ################################################################
10219 19:55:45.474649
10220 19:55:45.703647 00d80000 ################################################################
10221 19:55:45.703829
10222 19:55:45.929285 00e00000 ################################################################
10223 19:55:45.929423
10224 19:55:46.159256 00e80000 ################################################################
10225 19:55:46.159422
10226 19:55:46.391070 00f00000 ################################################################
10227 19:55:46.391205
10228 19:55:46.618105 00f80000 ################################################################
10229 19:55:46.618244
10230 19:55:46.853734 01000000 ################################################################
10231 19:55:46.853911
10232 19:55:47.085373 01080000 ################################################################
10233 19:55:47.085531
10234 19:55:47.312493 01100000 ################################################################
10235 19:55:47.312641
10236 19:55:47.540850 01180000 ################################################################
10237 19:55:47.540978
10238 19:55:47.764994 01200000 ################################################################
10239 19:55:47.765147
10240 19:55:47.998249 01280000 ################################################################
10241 19:55:47.998456
10242 19:55:48.230174 01300000 ################################################################
10243 19:55:48.230317
10244 19:55:48.467577 01380000 ################################################################
10245 19:55:48.467717
10246 19:55:48.695663 01400000 ################################################################
10247 19:55:48.695818
10248 19:55:48.923935 01480000 ################################################################
10249 19:55:48.924067
10250 19:55:49.153807 01500000 ################################################################
10251 19:55:49.153941
10252 19:55:49.392170 01580000 ################################################################
10253 19:55:49.392312
10254 19:55:49.618639 01600000 ################################################################
10255 19:55:49.618783
10256 19:55:49.859262 01680000 ################################################################
10257 19:55:49.859404
10258 19:55:50.090533 01700000 ################################################################
10259 19:55:50.090678
10260 19:55:50.320012 01780000 ################################################################
10261 19:55:50.320154
10262 19:55:50.555702 01800000 ################################################################
10263 19:55:50.555865
10264 19:55:50.802802 01880000 ################################################################
10265 19:55:50.802944
10266 19:55:51.027144 01900000 ################################################################
10267 19:55:51.027278
10268 19:55:51.262747 01980000 ################################################################
10269 19:55:51.262880
10270 19:55:51.498886 01a00000 ################################################################
10271 19:55:51.499025
10272 19:55:51.767033 01a80000 ################################################################
10273 19:55:51.767171
10274 19:55:52.016954 01b00000 ################################################################
10275 19:55:52.017089
10276 19:55:52.039290 01b80000 ####### done.
10277 19:55:52.042248
10278 19:55:52.042332 The bootfile was 28891470 bytes long.
10279 19:55:52.045533
10280 19:55:52.045634 Sending tftp read request... done.
10281 19:55:52.045704
10282 19:55:52.048550 Waiting for the transfer...
10283 19:55:52.048643
10284 19:55:52.052007 00000000 # done.
10285 19:55:52.052108
10286 19:55:52.058626 Command line loaded dynamically from TFTP file: 11899579/tftp-deploy-2vc2u5r_/kernel/cmdline
10287 19:55:52.058735
10288 19:55:52.082061 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11899579/extract-nfsrootfs-g6gngi29,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10289 19:55:52.082340
10290 19:55:52.082502 Loading FIT.
10291 19:55:52.082647
10292 19:55:52.085412 Image ramdisk-1 has 17794634 bytes.
10293 19:55:52.085684
10294 19:55:52.088815 Image fdt-1 has 47278 bytes.
10295 19:55:52.089127
10296 19:55:52.092288 Image kernel-1 has 11047522 bytes.
10297 19:55:52.092654
10298 19:55:52.102438 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10299 19:55:52.102993
10300 19:55:52.118577 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10301 19:55:52.119138
10302 19:55:52.121850 Choosing best match conf-1 for compat google,spherion-rev2.
10303 19:55:52.127676
10304 19:55:52.131856 Connected to device vid:did:rid of 1ae0:0028:00
10305 19:55:52.139560
10306 19:55:52.143013 tpm_get_response: command 0x17b, return code 0x0
10307 19:55:52.143618
10308 19:55:52.145580 ec_init: CrosEC protocol v3 supported (256, 248)
10309 19:55:52.148858
10310 19:55:52.152442 tpm_cleanup: add release locality here.
10311 19:55:52.152902
10312 19:55:52.155445 Shutting down all USB controllers.
10313 19:55:52.155938
10314 19:55:52.158686 Removing current net device
10315 19:55:52.159140
10316 19:55:52.162245 Exiting depthcharge with code 4 at timestamp: 47190058
10317 19:55:52.162703
10318 19:55:52.165771 LZMA decompressing kernel-1 to 0x821a6718
10319 19:55:52.166327
10320 19:55:52.168603 LZMA decompressing kernel-1 to 0x40000000
10321 19:55:53.557933
10322 19:55:53.558069 jumping to kernel
10323 19:55:53.558516 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
10324 19:55:53.558612 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10325 19:55:53.558688 Setting prompt string to ['Linux version [0-9]']
10326 19:55:53.558760 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10327 19:55:53.558849 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10328 19:55:53.640366
10329 19:55:53.643361 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10330 19:55:53.646788 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10331 19:55:53.646956 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10332 19:55:53.647104 Setting prompt string to []
10333 19:55:53.647254 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10334 19:55:53.647382 Using line separator: #'\n'#
10335 19:55:53.647490 No login prompt set.
10336 19:55:53.647605 Parsing kernel messages
10337 19:55:53.647706 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10338 19:55:53.647909 [login-action] Waiting for messages, (timeout 00:04:06)
10339 19:55:53.666542 [ 0.000000] Linux version 6.1.59-cip8-rt4 (KernelCI@build-j84202-arm64-gcc-10-defconfig-arm64-chromebook-st8dj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023
10340 19:55:53.669974 [ 0.000000] random: crng init done
10341 19:55:53.677094 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10342 19:55:53.679665 [ 0.000000] efi: UEFI not found.
10343 19:55:53.686505 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10344 19:55:53.696023 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10345 19:55:53.703414 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10346 19:55:53.712661 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10347 19:55:53.719234 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10348 19:55:53.725693 [ 0.000000] printk: bootconsole [mtk8250] enabled
10349 19:55:53.732379 [ 0.000000] NUMA: No NUMA configuration found
10350 19:55:53.739622 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10351 19:55:53.745405 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10352 19:55:53.745487 [ 0.000000] Zone ranges:
10353 19:55:53.752029 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10354 19:55:53.755420 [ 0.000000] DMA32 empty
10355 19:55:53.761812 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10356 19:55:53.765455 [ 0.000000] Movable zone start for each node
10357 19:55:53.768466 [ 0.000000] Early memory node ranges
10358 19:55:53.775438 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10359 19:55:53.781873 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10360 19:55:53.788573 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10361 19:55:53.795026 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10362 19:55:53.801284 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10363 19:55:53.808224 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10364 19:55:53.864544 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10365 19:55:53.871090 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10366 19:55:53.878035 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10367 19:55:53.880956 [ 0.000000] psci: probing for conduit method from DT.
10368 19:55:53.887749 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10369 19:55:53.890943 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10370 19:55:53.897321 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10371 19:55:53.901110 [ 0.000000] psci: SMC Calling Convention v1.2
10372 19:55:53.907210 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10373 19:55:53.910511 [ 0.000000] Detected VIPT I-cache on CPU0
10374 19:55:53.917186 [ 0.000000] CPU features: detected: GIC system register CPU interface
10375 19:55:53.924063 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10376 19:55:53.930326 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10377 19:55:53.937013 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10378 19:55:53.947675 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10379 19:55:53.953526 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10380 19:55:53.956445 [ 0.000000] alternatives: applying boot alternatives
10381 19:55:53.963604 [ 0.000000] Fallback order for Node 0: 0
10382 19:55:53.970234 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10383 19:55:53.973448 [ 0.000000] Policy zone: Normal
10384 19:55:53.996608 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11899579/extract-nfsrootfs-g6gngi29,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10385 19:55:54.006405 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10386 19:55:54.017126 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10387 19:55:54.027826 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10388 19:55:54.033521 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10389 19:55:54.037470 <6>[ 0.000000] software IO TLB: area num 8.
10390 19:55:54.093593 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10391 19:55:54.243102 <6>[ 0.000000] Memory: 7952048K/8385536K available (17984K kernel code, 4116K rwdata, 17476K rodata, 8448K init, 615K bss, 400720K reserved, 32768K cma-reserved)
10392 19:55:54.249538 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10393 19:55:54.256590 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10394 19:55:54.259366 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10395 19:55:54.266089 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10396 19:55:54.272476 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10397 19:55:54.279390 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10398 19:55:54.285561 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10399 19:55:54.292105 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10400 19:55:54.299169 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10401 19:55:54.305423 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10402 19:55:54.309084 <6>[ 0.000000] GICv3: 608 SPIs implemented
10403 19:55:54.312103 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10404 19:55:54.318572 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10405 19:55:54.321898 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10406 19:55:54.328812 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10407 19:55:54.342362 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10408 19:55:54.355314 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10409 19:55:54.361796 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10410 19:55:54.370099 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10411 19:55:54.383115 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10412 19:55:54.389677 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10413 19:55:54.396218 <6>[ 0.009176] Console: colour dummy device 80x25
10414 19:55:54.406146 <6>[ 0.013896] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10415 19:55:54.413528 <6>[ 0.024404] pid_max: default: 32768 minimum: 301
10416 19:55:54.416469 <6>[ 0.029276] LSM: Security Framework initializing
10417 19:55:54.422765 <6>[ 0.034245] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10418 19:55:54.432546 <6>[ 0.042026] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10419 19:55:54.442491 <6>[ 0.051487] cblist_init_generic: Setting adjustable number of callback queues.
10420 19:55:54.445825 <6>[ 0.058928] cblist_init_generic: Setting shift to 3 and lim to 1.
10421 19:55:54.455970 <6>[ 0.065304] cblist_init_generic: Setting adjustable number of callback queues.
10422 19:55:54.462816 <6>[ 0.072731] cblist_init_generic: Setting shift to 3 and lim to 1.
10423 19:55:54.465614 <6>[ 0.079173] rcu: Hierarchical SRCU implementation.
10424 19:55:54.472109 <6>[ 0.079175] rcu: Max phase no-delay instances is 1000.
10425 19:55:54.479099 <6>[ 0.079199] printk: bootconsole [mtk8250] printing thread started
10426 19:55:54.485456 <6>[ 0.097504] EFI services will not be available.
10427 19:55:54.488949 <6>[ 0.097708] smp: Bringing up secondary CPUs ...
10428 19:55:54.495618 <6>[ 0.098017] Detected VIPT I-cache on CPU1
10429 19:55:54.502370 <6>[ 0.098084] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10430 19:55:54.508675 <6>[ 0.098117] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10431 19:55:54.517969 <6>[ 0.125947] Detected VIPT I-cache on CPU2
10432 19:55:54.524907 <6>[ 0.125993] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10433 19:55:54.534895 <6>[ 0.126009] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10434 19:55:54.538119 <6>[ 0.126268] Detected VIPT I-cache on CPU3
10435 19:55:54.544418 <6>[ 0.126315] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10436 19:55:54.550838 <6>[ 0.126329] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10437 19:55:54.557672 <6>[ 0.126638] CPU features: detected: Spectre-v4
10438 19:55:54.561942 <6>[ 0.126644] CPU features: detected: Spectre-BHB
10439 19:55:54.564177 <6>[ 0.126649] Detected PIPT I-cache on CPU4
10440 19:55:54.570989 <6>[ 0.126708] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10441 19:55:54.580711 <6>[ 0.126725] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10442 19:55:54.583996 <6>[ 0.127019] Detected PIPT I-cache on CPU5
10443 19:55:54.590803 <6>[ 0.127079] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10444 19:55:54.597206 <6>[ 0.127095] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10445 19:55:54.600602 <6>[ 0.127369] Detected PIPT I-cache on CPU6
10446 19:55:54.610081 <6>[ 0.127433] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10447 19:55:54.617053 <6>[ 0.127450] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10448 19:55:54.620692 <6>[ 0.127740] Detected PIPT I-cache on CPU7
10449 19:55:54.626763 <6>[ 0.127805] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10450 19:55:54.633820 <6>[ 0.127821] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10451 19:55:54.640356 <6>[ 0.127866] smp: Brought up 1 node, 8 CPUs
10452 19:55:54.644307 <6>[ 0.127871] SMP: Total of 8 processors activated.
10453 19:55:54.649464 <6>[ 0.127874] CPU features: detected: 32-bit EL0 Support
10454 19:55:54.656357 <6>[ 0.127876] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10455 19:55:54.663261 <6>[ 0.127878] CPU features: detected: Common not Private translations
10456 19:55:54.670091 <6>[ 0.127880] CPU features: detected: CRC32 instructions
10457 19:55:54.676609 <6>[ 0.127883] CPU features: detected: RCpc load-acquire (LDAPR)
10458 19:55:54.683404 <6>[ 0.127884] CPU features: detected: LSE atomic instructions
10459 19:55:54.686903 <6>[ 0.127886] CPU features: detected: Privileged Access Never
10460 19:55:54.693615 <6>[ 0.127888] CPU features: detected: RAS Extension Support
10461 19:55:54.699993 <6>[ 0.127891] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10462 19:55:54.706720 <6>[ 0.127961] CPU: All CPU(s) started at EL2
10463 19:55:54.709966 <6>[ 0.127962] alternatives: applying system-wide alternatives
10464 19:55:54.712632 <6>[ 0.141070] devtmpfs: initialized
10465 19:55:54.722383 <6>[ 0.147287] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10466 19:55:54.752478 ���U���ѕɕ��C}%9Q��ɽѽ����������5R�<6>[ < 0.364895] printk: console [ttyS0] printing thread started
10467 19:55:54.758956 6>[<6>[ 0.364931] printk: console [ttyS0] enabled
10468 19:55:54.765654 0.228685] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10469 19:55:54.772624 <6>[ 0.364934] printk: bootconsole [mtk8250] disabled
10470 19:55:54.779449 <6>[ 0.383010] printk: bootconsole [mtk8250] printing thread stopped
10471 19:55:54.783111 <6>[ 0.384306] SuperH (H)SCI(F) driver initialized
10472 19:55:54.789947 <6>[ 0.384784] msm_serial: driver initialized
10473 19:55:54.796423 <6>[ 0.389492] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10474 19:55:54.805737 <6>[ 0.389523] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10475 19:55:54.812518 <6>[ 0.389555] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10476 19:55:54.822467 <6>[ 0.389585] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10477 19:55:54.832163 <6>[ 0.389606] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10478 19:55:54.844956 <6>[ 0.389633] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10479 19:55:54.860523 <6>[ 0.389661] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10480 19:55:54.861305 <6>[ 0.389770] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10481 19:55:54.865565 <6>[ 0.389800] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10482 19:55:54.870625 <6>[ 0.400414] loop: module loaded
10483 19:55:54.876864 <6>[ 0.402959] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10484 19:55:54.882379 <4>[ 0.419769] mtk-pmic-keys: Failed to locate of_node [id: -1]
10485 19:55:54.885601 <6>[ 0.420670] megasas: 07.719.03.00-rc1
10486 19:55:54.892202 <6>[ 0.432821] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10487 19:55:54.895570 <6>[ 0.432966] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10488 19:55:54.902416 <6>[ 0.444612] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10489 19:55:54.915405 <6>[ 0.503053] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10490 19:55:55.360180 <6>[ 0.970805] Freeing initrd memory: 17376K
10491 19:55:55.366451 <6>[ 0.977037] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10492 19:55:55.369945 <6>[ 0.981502] tun: Universal TUN/TAP device driver, 1.6
10493 19:55:55.373403 <6>[ 0.982265] thunder_xcv, ver 1.0
10494 19:55:55.376626 <6>[ 0.982283] thunder_bgx, ver 1.0
10495 19:55:55.380105 <6>[ 0.982300] nicpf, ver 1.0
10496 19:55:55.389853 <6>[ 0.983363] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10497 19:55:55.393332 <6>[ 0.983366] hns3: Copyright (c) 2017 Huawei Corporation.
10498 19:55:55.396330 <6>[ 0.983392] hclge is initializing
10499 19:55:55.403310 <6>[ 0.983414] e1000: Intel(R) PRO/1000 Network Driver
10500 19:55:55.409497 <6>[ 0.983416] e1000: Copyright (c) 1999-2006 Intel Corporation.
10501 19:55:55.413228 <6>[ 0.983436] e1000e: Intel(R) PRO/1000 Network Driver
10502 19:55:55.420520 <6>[ 0.983438] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10503 19:55:55.427684 <6>[ 0.983454] igb: Intel(R) Gigabit Ethernet Network Driver
10504 19:55:55.430809 <6>[ 0.983456] igb: Copyright (c) 2007-2014 Intel Corporation.
10505 19:55:55.437202 <6>[ 0.983471] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10506 19:55:55.444370 <6>[ 0.983473] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10507 19:55:55.447930 <6>[ 0.983768] sky2: driver version 1.30
10508 19:55:55.455010 <6>[ 0.984844] VFIO - User Level meta-driver version: 0.3
10509 19:55:55.461494 <6>[ 0.987757] usbcore: registered new interface driver usb-storage
10510 19:55:55.464818 <6>[ 0.987936] usbcore: registered new device driver onboard-usb-hub
10511 19:55:55.471665 <6>[ 0.990754] mt6397-rtc mt6359-rtc: registered as rtc0
10512 19:55:55.481786 <6>[ 0.990905] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-28T19:55:55 UTC (1698522955)
10513 19:55:55.485207 <6>[ 0.991523] i2c_dev: i2c /dev entries driver
10514 19:55:55.494809 <6>[ 0.998798] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10515 19:55:55.498056 <6>[ 1.013777] cpu cpu0: EM: created perf domain
10516 19:55:55.501059 <6>[ 1.014005] cpu cpu4: EM: created perf domain
10517 19:55:55.507937 <6>[ 1.015894] sdhci: Secure Digital Host Controller Interface driver
10518 19:55:55.514291 <6>[ 1.015896] sdhci: Copyright(c) Pierre Ossman
10519 19:55:55.520881 <6>[ 1.016249] Synopsys Designware Multimedia Card Interface Driver
10520 19:55:55.525264 <6>[ 1.016611] sdhci-pltfm: SDHCI platform and OF driver helper
10521 19:55:55.530922 <6>[ 1.021243] mmc0: CQHCI version 5.10
10522 19:55:55.534138 <6>[ 1.027046] ledtrig-cpu: registered to indicate activity on CPUs
10523 19:55:55.541103 <6>[ 1.027987] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10524 19:55:55.547395 <6>[ 1.028278] usbcore: registered new interface driver usbhid
10525 19:55:55.550743 <6>[ 1.028280] usbhid: USB HID core driver
10526 19:55:55.560563 <6>[ 1.028398] spi_master spi0: will run message pump with realtime priority
10527 19:55:55.570400 <6>[ 1.060265] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10528 19:55:55.583283 <6>[ 1.062638] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10529 19:55:55.589801 <6>[ 1.063906] cros-ec-spi spi0.0: Chrome EC device registered
10530 19:55:55.599853 <6>[ 1.075176] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10531 19:55:55.606437 <6>[ 1.076141] NET: Registered PF_PACKET protocol family
10532 19:55:55.610012 <6>[ 1.076225] 9pnet: Installing 9P2000 support
10533 19:55:55.613049 <5>[ 1.076258] Key type dns_resolver registered
10534 19:55:55.619960 <6>[ 1.076572] registered taskstats version 1
10535 19:55:55.622800 <5>[ 1.076585] Loading compiled-in X.509 certificates
10536 19:55:55.633009 <4>[ 1.093856] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10537 19:55:55.646134 <4>[ 1.094114] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10538 19:55:55.653057 <3>[ 1.094134] debugfs: File 'uA_load' in directory '/' already present!
10539 19:55:55.659333 <3>[ 1.094146] debugfs: File 'min_uV' in directory '/' already present!
10540 19:55:55.666266 <3>[ 1.094153] debugfs: File 'max_uV' in directory '/' already present!
10541 19:55:55.672846 <3>[ 1.094159] debugfs: File 'constraint_flags' in directory '/' already present!
10542 19:55:55.679616 <3>[ 1.097219] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10543 19:55:55.686489 <6>[ 1.105556] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10544 19:55:55.693067 <6>[ 1.106189] xhci-mtk 11200000.usb: xHCI Host Controller
10545 19:55:55.699710 <6>[ 1.106203] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10546 19:55:55.709668 <6>[ 1.106411] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10547 19:55:55.716553 <6>[ 1.106454] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10548 19:55:55.723276 <6>[ 1.106544] xhci-mtk 11200000.usb: xHCI Host Controller
10549 19:55:55.729226 <6>[ 1.106551] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10550 19:55:55.736014 <6>[ 1.106557] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10551 19:55:55.739326 <6>[ 1.106998] hub 1-0:1.0: USB hub found
10552 19:55:55.745763 <6>[ 1.107026] hub 1-0:1.0: 1 port detected
10553 19:55:55.752940 <6>[ 1.107244] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10554 19:55:55.756153 <6>[ 1.107499] hub 2-0:1.0: USB hub found
10555 19:55:55.759646 <6>[ 1.107589] hub 2-0:1.0: 1 port detected
10556 19:55:55.765883 <6>[ 1.110130] mtk-msdc 11f70000.mmc: Got CD GPIO
10557 19:55:55.769580 <6>[ 1.115798] mmc0: Command Queue Engine enabled
10558 19:55:55.776311 <6>[ 1.115840] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10559 19:55:55.782717 <6>[ 1.116603] mmcblk0: mmc0:0001 DA4128 116 GiB
10560 19:55:55.789114 <6>[ 1.118791] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10561 19:55:55.795709 <6>[ 1.118799] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10562 19:55:55.805871 <4>[ 1.118877] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10563 19:55:55.816087 <6>[ 1.119365] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10564 19:55:55.822794 <6>[ 1.119366] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10565 19:55:55.828894 <6>[ 1.119654] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10566 19:55:55.839002 <6>[ 1.119674] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10567 19:55:55.845632 <6>[ 1.119677] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10568 19:55:55.855431 <6>[ 1.119682] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10569 19:55:55.862085 <6>[ 1.120617] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10570 19:55:55.868860 <6>[ 1.121688] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10571 19:55:55.879368 <6>[ 1.121710] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10572 19:55:55.885344 <6>[ 1.121717] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10573 19:55:55.895639 <6>[ 1.121724] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10574 19:55:55.902023 <6>[ 1.121731] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10575 19:55:55.911632 <6>[ 1.121739] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10576 19:55:55.918517 <6>[ 1.121747] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10577 19:55:55.928037 <6>[ 1.121755] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10578 19:55:55.934856 <6>[ 1.121762] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10579 19:55:55.944433 <6>[ 1.121769] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10580 19:55:55.951097 <6>[ 1.121776] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10581 19:55:55.960607 <6>[ 1.121782] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10582 19:55:55.967350 <6>[ 1.121789] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10583 19:55:55.977138 <6>[ 1.121795] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10584 19:55:55.987424 <6>[ 1.121801] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10585 19:55:55.990692 <6>[ 1.121833] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10586 19:55:55.998215 <6>[ 1.122592] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10587 19:55:56.004211 <6>[ 1.122658] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10588 19:55:56.010935 <6>[ 1.123243] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10589 19:55:56.017052 <6>[ 1.123877] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10590 19:55:56.023703 <6>[ 1.124604] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10591 19:55:56.030414 <6>[ 1.125322] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10592 19:55:56.036777 <6>[ 1.126086] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10593 19:55:56.043298 <6>[ 1.126310] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10594 19:55:56.053531 <6>[ 1.126324] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10595 19:55:56.063401 <6>[ 1.126329] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10596 19:55:56.073288 <6>[ 1.126335] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10597 19:55:56.083460 <6>[ 1.126340] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10598 19:55:56.089846 <6>[ 1.126351] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10599 19:55:56.099685 <6>[ 1.126358] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10600 19:55:56.109575 <6>[ 1.126363] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10601 19:55:56.119561 <6>[ 1.126367] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10602 19:55:56.129573 <6>[ 1.126374] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10603 19:55:56.139435 <6>[ 1.126379] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10604 19:55:56.148883 <6>[ 1.127026] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10605 19:55:56.152417 <6>[ 1.144757] Trying to probe devices needed for running init ...
10606 19:55:56.162325 <6>[ 1.493768] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10607 19:55:56.165297 <6>[ 1.528438] hub 2-1:1.0: USB hub found
10608 19:55:56.168685 <6>[ 1.528866] hub 2-1:1.0: 3 ports detected
10609 19:55:56.175025 <6>[ 1.649537] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10610 19:55:56.188197 <6>[ 1.797866] hub 1-1:1.0: USB hub found
10611 19:55:56.191376 <6>[ 1.798235] hub 1-1:1.0: 4 ports detected
10612 19:55:56.503640 <6>[ 2.109707] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10613 19:55:56.624249 <6>[ 2.235873] hub 1-1.1:1.0: USB hub found
10614 19:55:56.627857 <6>[ 2.236003] hub 1-1.1:1.0: 4 ports detected
10615 19:55:56.736070 <6>[ 2.341694] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10616 19:55:56.856661 <6>[ 2.469059] hub 1-1.4:1.0: USB hub found
10617 19:55:56.859799 <6>[ 2.469443] hub 1-1.4:1.0: 2 ports detected
10618 19:55:56.939577 <6>[ 2.545674] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10619 19:55:57.120497 <6>[ 2.725677] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10620 19:55:57.196512 <3>[ 2.805877] usb 1-1.1.4: device descriptor read/64, error -32
10621 19:55:57.384588 <3>[ 2.993890] usb 1-1.1.4: device descriptor read/64, error -32
10622 19:55:57.575886 <6>[ 3.181694] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10623 19:55:57.755990 <6>[ 3.361695] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10624 19:55:57.832813 <3>[ 3.441884] usb 1-1.1.4: device descriptor read/64, error -32
10625 19:55:58.020697 <3>[ 3.629900] usb 1-1.1.4: device descriptor read/64, error -32
10626 19:55:58.128651 <6>[ 3.738265] usb 1-1.1-port4: attempt power cycle
10627 19:55:58.211975 <6>[ 3.817731] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10628 19:55:58.735823 <6>[ 4.341695] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10629 19:55:58.742208 <4>[ 4.341946] usb 1-1.1.4: Device not responding to setup address.
10630 19:55:58.940347 <4>[ 4.549916] usb 1-1.1.4: Device not responding to setup address.
10631 19:55:59.148487 <3>[ 4.757684] usb 1-1.1.4: device not accepting address 10, error -71
10632 19:55:59.231772 <6>[ 4.837531] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10633 19:55:59.238640 <4>[ 4.837776] usb 1-1.1.4: Device not responding to setup address.
10634 19:55:59.436034 <4>[ 5.045961] usb 1-1.1.4: Device not responding to setup address.
10635 19:55:59.644365 <3>[ 5.253558] usb 1-1.1.4: device not accepting address 11, error -71
10636 19:55:59.650913 <3>[ 5.254058] usb 1-1.1-port4: unable to enumerate USB device
10637 19:56:07.830206 <6>[ 13.442698] ALSA device list:
10638 19:56:07.837049 <6>[ 13.442719] No soundcards found.
10639 19:56:07.839949 <6>[ 13.447119] Freeing unused kernel memory: 8448K
10640 19:56:07.847110 Loading, please <6>[ 13.447293] Run /init as init process
10641 19:56:07.847673 wait...
10642 19:56:07.861784 Starting version 247.3-7+deb11u2
10643 19:56:08.098995 <6>[ 13.706740] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10644 19:56:08.101754 <6>[ 13.711355] remoteproc remoteproc0: scp is available
10645 19:56:08.108484 <6>[ 13.711475] remoteproc remoteproc0: powering up scp
10646 19:56:08.115217 <6>[ 13.711481] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10647 19:56:08.121759 <6>[ 13.711509] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10648 19:56:08.187176 <3>[ 13.795022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10649 19:56:08.193126 <3>[ 13.795043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10650 19:56:08.203169 <3>[ 13.795047] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10651 19:56:08.210100 <3>[ 13.801457] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10652 19:56:08.219944 <3>[ 13.801483] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10653 19:56:08.226349 <3>[ 13.801491] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 19:56:08.236165 <3>[ 13.801559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 19:56:08.242455 <3>[ 13.801570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 19:56:08.249449 <4>[ 13.811219] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10657 19:56:08.258963 <6>[ 13.812297] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10658 19:56:08.265928 <6>[ 13.812336] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10659 19:56:08.276279 <6>[ 13.812343] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10660 19:56:08.285402 <3>[ 13.820842] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 19:56:08.292539 <4>[ 13.820975] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10662 19:56:08.299162 <3>[ 13.825142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10663 19:56:08.309847 <3>[ 13.825159] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10664 19:56:08.316378 <3>[ 13.825162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10665 19:56:08.323339 <6>[ 13.827121] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10666 19:56:08.330049 <6>[ 13.828222] mc: Linux media interface: v0.10
10667 19:56:08.336208 <3>[ 13.828646] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10668 19:56:08.346171 <3>[ 13.828701] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 19:56:08.352519 <3>[ 13.828714] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10670 19:56:08.362370 <3>[ 13.828729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 19:56:08.369119 <3>[ 13.828740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 19:56:08.378982 <3>[ 13.832296] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10673 19:56:08.385218 <6>[ 13.839631] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10674 19:56:08.392706 <6>[ 13.839631] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10675 19:56:08.399101 <6>[ 13.839652] remoteproc remoteproc0: remote processor scp is now up
10676 19:56:08.405518 <6>[ 13.847301] videodev: Linux video capture interface: v2.00
10677 19:56:08.412103 <6>[ 13.848017] usbcore: registered new interface driver r8152
10678 19:56:08.419496 <4>[ 13.852310] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10679 19:56:08.425672 <4>[ 13.852310] Fallback method does not support PEC.
10680 19:56:08.432206 <6>[ 13.879514] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10681 19:56:08.441671 <6>[ 13.881030] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10682 19:56:08.451491 <3>[ 13.916564] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10683 19:56:08.458377 <6>[ 13.934861] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10684 19:56:08.461586 <6>[ 13.934870] pci_bus 0000:00: root bus resource [bus 00-ff]
10685 19:56:08.468438 <6>[ 13.934875] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10686 19:56:08.478124 <6>[ 13.934878] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10687 19:56:08.484524 <6>[ 13.934909] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10688 19:56:08.494454 <6>[ 13.934922] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10689 19:56:08.497878 <6>[ 13.934997] pci 0000:00:00.0: supports D1 D2
10690 19:56:08.504419 <6>[ 13.934999] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10691 19:56:08.514184 <6>[ 13.935966] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10692 19:56:08.517697 <6>[ 13.936036] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10693 19:56:08.527596 <6>[ 13.936059] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10694 19:56:08.534099 <6>[ 13.936074] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10695 19:56:08.540835 <6>[ 13.936089] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10696 19:56:08.547021 <6>[ 13.936190] pci 0000:01:00.0: supports D1 D2
10697 19:56:08.553913 <6>[ 13.936192] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10698 19:56:08.564095 <6>[ 13.937777] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10699 19:56:08.570225 <3>[ 13.938101] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10700 19:56:08.576975 <6>[ 13.945486] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10701 19:56:08.586910 <6>[ 13.945515] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10702 19:56:08.593849 <6>[ 13.945518] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10703 19:56:08.603247 <6>[ 13.945526] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10704 19:56:08.610088 <6>[ 13.945538] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10705 19:56:08.616632 <6>[ 13.945551] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10706 19:56:08.622971 <6>[ 13.945562] pci 0000:00:00.0: PCI bridge to [bus 01]
10707 19:56:08.630074 <6>[ 13.945567] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10708 19:56:08.636022 <6>[ 13.945676] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10709 19:56:08.646094 <6>[ 13.946067] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10710 19:56:08.652667 <6>[ 13.946140] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10711 19:56:08.659576 <6>[ 13.946417] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10712 19:56:08.669130 <6>[ 13.946568] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10713 19:56:08.675578 <6>[ 13.947395] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10714 19:56:08.682400 <6>[ 13.965803] usbcore: registered new interface driver cdc_ether
10715 19:56:08.688876 <5>[ 13.970550] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10716 19:56:08.695639 <5>[ 13.977428] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10717 19:56:08.705753 <4>[ 13.977537] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10718 19:56:08.709036 <6>[ 13.977545] cfg80211: failed to load regulatory.db
10719 19:56:08.715369 <6>[ 13.981508] Bluetooth: Core ver 2.22
10720 19:56:08.718774 <6>[ 13.981596] NET: Registered PF_BLUETOOTH protocol family
10721 19:56:08.725315 <6>[ 13.981599] Bluetooth: HCI device and connection manager initialized
10722 19:56:08.731958 <6>[ 13.981623] Bluetooth: HCI socket layer initialized
10723 19:56:08.735231 <6>[ 13.981632] Bluetooth: L2CAP socket layer initialized
10724 19:56:08.742415 <6>[ 13.981646] Bluetooth: SCO socket layer initialized
10725 19:56:08.748581 <6>[ 13.981710] usbcore: registered new interface driver r8153_ecm
10726 19:56:08.755232 <6>[ 14.054329] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10727 19:56:08.768562 <6>[ 14.056486] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10728 19:56:08.774947 <6>[ 14.056786] usbcore: registered new interface driver uvcvideo
10729 19:56:08.778926 <6>[ 14.062652] usbcore: registered new interface driver btusb
10730 19:56:08.791256 <4>[ 14.063681] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10731 19:56:08.795161 <3>[ 14.063702] Bluetooth: hci0: Failed to load firmware file (-2)
10732 19:56:08.801747 <3>[ 14.063706] Bluetooth: hci0: Failed to set up firmware (-2)
10733 19:56:08.811666 <4>[ 14.063710] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10734 19:56:08.821106 <4>[ 14.065702] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10735 19:56:08.831479 <4>[ 14.065716] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10736 19:56:08.837627 <6>[ 14.073469] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10737 19:56:08.845019 <6>[ 14.073567] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10738 19:56:08.851527 <6>[ 14.076714] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10739 19:56:08.854239 <6>[ 14.093550] mt7921e 0000:01:00.0: ASIC revision: 79610010
10740 19:56:08.860517 <6>[ 14.117686] r8152 1-1.1.1:1.0 eth0: v1.12.13
10741 19:56:08.867224 <6>[ 14.126684] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10742 19:56:08.877318 <4>[ 14.188599] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10743 19:56:08.887702 <4>[ 14.295262] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10744 19:56:08.900682 <4>[ 14.398892] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10745 19:56:08.910318 <4>[ 14.503306] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10746 19:56:08.917020 Begin: Loading essential drivers ... done.
10747 19:56:08.920337 Begin: Running /scripts/init-premount ... done.
10748 19:56:08.926838 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10749 19:56:08.937060 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10750 19:56:08.939840 Device /sys/class/net/enxf4f5e850de0a found
10751 19:56:08.940300 done.
10752 19:56:09.001927 <4>[ 14.607710] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10753 19:56:09.019101 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10754 19:56:09.109816 <4>[ 14.715018] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10755 19:56:09.213874 <4>[ 14.818654] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10756 19:56:09.318153 <4>[ 14.922472] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10757 19:56:09.421933 <4>[ 15.026343] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10758 19:56:09.525872 <4>[ 15.130346] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10759 19:56:09.619685 <3>[ 15.232221] mt7921e 0000:01:00.0: hardware init failed
10760 19:56:10.170896 <6>[ 15.784114] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10761 19:56:10.876341 IP-Config: no response after 2 secs - giving up
10762 19:56:10.918069 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10763 19:56:10.921320 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10764 19:56:10.931088 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10765 19:56:10.938086 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10766 19:56:10.944479 host : mt8192-asurada-spherion-r0-cbg-9
10767 19:56:10.951440 domain : lava-rack
10768 19:56:10.953952 rootserver: 192.168.201.1 rootpath:
10769 19:56:10.954066 filename :
10770 19:56:11.002795 done.
10771 19:56:11.010202 Begin: Running /scripts/nfs-bottom ... done.
10772 19:56:11.027253 Begin: Running /scripts/init-bottom ... done.
10773 19:56:12.231040 <6>[ 17.844285] NET: Registered PF_INET6 protocol family
10774 19:56:12.238617 <6>[ 17.851069] Segment Routing with IPv6
10775 19:56:12.243698 <6>[ 17.851104] In-situ OAM (IOAM) with IPv6
10776 19:56:12.351180 <30>[ 17.942400] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10777 19:56:12.353648 <30>[ 17.943395] systemd[1]: Detected architecture arm64.
10778 19:56:12.354134
10779 19:56:12.360298 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10780 19:56:12.360832
10781 19:56:12.382713 <30>[ 17.996467] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10782 19:56:13.177694 <30>[ 18.787346] systemd[1]: Queued start job for default target Graphical Interface.
10783 19:56:13.200744 [[0;32m OK [<30>[ 18.812018] systemd[1]: Created slice system-getty.slice.
10784 19:56:13.203824 0m] Created slice [0;1;39msystem-getty.slice[0m.
10785 19:56:13.223745 [[0;32m OK [0m] Created slic<30>[ 18.835009] systemd[1]: Created slice system-modprobe.slice.
10786 19:56:13.226632 e [0;1;39msystem-modprobe.slice[0m.
10787 19:56:13.247681 [[0;32m OK [0m] Created slic<30>[ 18.858912] systemd[1]: Created slice system-serial\x2dgetty.slice.
10788 19:56:13.254437 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10789 19:56:13.271995 [[0;32m OK [0m] Created slic<30>[ 18.883506] systemd[1]: Created slice User and Session Slice.
10790 19:56:13.275683 e [0;1;39mUser and Session Slice[0m.
10791 19:56:13.298589 [[0;32m OK [0m] Started [0;<30>[ 18.906515] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10792 19:56:13.301884 1;39mDispatch Password …ts to Console Directory Watch[0m.
10793 19:56:13.325786 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 18.933924] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10794 19:56:13.329116 sword R…uests to Wall Directory Watch[0m.
10795 19:56:13.353199 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 18.957844] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10796 19:56:13.359585 <30>[ 18.958058] systemd[1]: Reached target Local Encrypted Volumes.
10797 19:56:13.363149 l Encrypted Volumes[0m.
10798 19:56:13.382983 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 18.993936] systemd[1]: Reached target Paths.
10799 19:56:13.383501 s[0m.
10800 19:56:13.405371 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.013666] systemd[1]: Reached target Remote File Systems.
10801 19:56:13.405876 te File Systems[0m.
10802 19:56:13.426445 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.037635] systemd[1]: Reached target Slices.
10803 19:56:13.427005 es[0m.
10804 19:56:13.446298 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.057672] systemd[1]: Reached target Swap.
10805 19:56:13.446756 [0m.
10806 19:56:13.470015 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.078062] systemd[1]: Listening on initctl Compatibility Named Pipe.
10807 19:56:13.473037 l Compatibility Named Pipe[0m.
10808 19:56:13.483141 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.094126] systemd[1]: Listening on Journal Audit Socket.
10809 19:56:13.486404 l Audit Socket[0m.
10810 19:56:13.508395 [[0;32m OK [0m] Listening on<30>[ 19.119816] systemd[1]: Listening on Journal Socket (/dev/log).
10811 19:56:13.512167 [0;1;39mJournal Socket (/dev/log)[0m.
10812 19:56:13.531572 [[0;32m OK [0m] Listening on<30>[ 19.142860] systemd[1]: Listening on Journal Socket.
10813 19:56:13.534969 [0;1;39mJournal Socket[0m.
10814 19:56:13.552353 [[0;32m OK [0m] Listening on<30>[ 19.163604] systemd[1]: Listening on Network Service Netlink Socket.
10815 19:56:13.558926 [0;1;39mNetwork Service Netlink Socket[0m.
10816 19:56:13.577238 [[0;32m OK [<30>[ 19.188475] systemd[1]: Listening on udev Control Socket.
10817 19:56:13.580334 0m] Listening on [0;1;39mudev Control Socket[0m.
10818 19:56:13.599879 [[0;32m OK [0m] Listening on<30>[ 19.210799] systemd[1]: Listening on udev Kernel Socket.
10819 19:56:13.602963 [0;1;39mudev Kernel Socket[0m.
10820 19:56:13.665270 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.273834] systemd[1]: Mounting Huge Pages File System...
10821 19:56:13.665869 m[0m...
10822 19:56:13.689341 Mounting [0;1;39mPOSIX Message Queue F<30>[ 19.297978] systemd[1]: Mounting POSIX Message Queue File System...
10823 19:56:13.689433 ile System[0m...
10824 19:56:13.717193 Mounting [0;1;39mKernel Debug File Sys<30>[ 19.325894] systemd[1]: Mounting Kernel Debug File System...
10825 19:56:13.717305 tem[0m...
10826 19:56:13.737528 <30>[ 19.346183] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10827 19:56:13.747012 <30>[ 19.351838] systemd[1]: Starting Create list of static device nodes for the current kernel...
10828 19:56:13.753515 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10829 19:56:13.781557 Starting [0;1;39mLoad Kernel Module co<30>[ 19.390045] systemd[1]: Starting Load Kernel Module configfs...
10830 19:56:13.781746 nfigfs[0m...
10831 19:56:13.803545 Starting [0;1;39mLoad <30>[ 19.414699] systemd[1]: Starting Load Kernel Module drm...
10832 19:56:13.806179 Kernel Module drm[0m...
10833 19:56:13.830327 Starting [0;1;39mLoad Kernel Module fu<30>[ 19.438378] systemd[1]: Starting Load Kernel Module fuse...
10834 19:56:13.830899 se[0m...
10835 19:56:13.853299 <30>[ 19.463491] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10836 19:56:13.867208 Starting [0;1;39mJourn<30>[ 19.478845] systemd[1]: Starting Journal Service...
10837 19:56:13.867311 al Service[0m...
10838 19:56:13.874370 <6>[ 19.487828] fuse: init (API version 7.37)
10839 19:56:13.893132 Startin<30>[ 19.504583] systemd[1]: Starting Load Kernel Modules...
10840 19:56:13.895901 g [0;1;39mLoad Kernel Modules[0m...
10841 19:56:13.938132 Starting [0;1;39mRemount Root and Kern<30>[ 19.546273] systemd[1]: Starting Remount Root and Kernel File Systems...
10842 19:56:13.941443 el File Systems[0m...
10843 19:56:13.963142 Starting [0;1;39mColdp<30>[ 19.574510] systemd[1]: Starting Coldplug All udev Devices...
10844 19:56:13.966556 lug All udev Devices[0m...
10845 19:56:13.988687 [[0;32m OK [<30>[ 19.600276] systemd[1]: Mounted Huge Pages File System.
10846 19:56:13.991649 0m] Mounted [0;1;39mHuge Pages File System[0m.
10847 19:56:14.011982 [[0;32m OK [0m] Mounted [0;<30>[ 19.623038] systemd[1]: Mounted POSIX Message Queue File System.
10848 19:56:14.014735 1;39mPOSIX Message Queue File System[0m.
10849 19:56:14.029732 <3>[ 19.638669] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10850 19:56:14.039813 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 19.650658] systemd[1]: Mounted Kernel Debug File System.
10851 19:56:14.042743 g File System[0m.
10852 19:56:14.066626 [[0;32m OK [0m] Finished [0;1;39mCreate lis<30>[ 19.674500] systemd[1]: Finished Create list of static device nodes for the current kernel.
10853 19:56:14.076266 t of st… nodes<3>[ 19.675983] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10854 19:56:14.079592 for the current kernel[0m.
10855 19:56:14.101147 [[0;32m OK [0m] Finished [0<30>[ 19.710940] systemd[1]: modprobe@configfs.service: Succeeded.
10856 19:56:14.107780 <30>[ 19.711909] systemd[1]: Finished Load Kernel Module configfs.
10857 19:56:14.117753 ;1;39mLoad Kerne<3>[ 19.725737] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10858 19:56:14.120849 l Module configfs[0m.
10859 19:56:14.138237 <3>[ 19.746362] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 19:56:14.148440 [[0;32m OK [<30>[ 19.759301] systemd[1]: modprobe@drm.service: Succeeded.
10861 19:56:14.155078 0m] Finished [0<30>[ 19.759985] systemd[1]: Finished Load Kernel Module drm.
10862 19:56:14.158239 ;1;39mLoad Kernel Module drm[0m.
10863 19:56:14.170174 <3>[ 19.780512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10864 19:56:14.181513 [[0;32m OK [<30>[ 19.791842] systemd[1]: modprobe@fuse.service: Succeeded.
10865 19:56:14.188113 0m] Finished [0<30>[ 19.792730] systemd[1]: Finished Load Kernel Module fuse.
10866 19:56:14.198181 ;1;39mLoad Kernel Module fuse[0<3>[ 19.808641] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10867 19:56:14.198599 m.
10868 19:56:14.222956 [[0;32m OK [0m] Finished [0<3>[ 19.830263] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 19:56:14.229409 ;1;39mLoad Kerne<30>[ 19.831172] systemd[1]: Finished Load Kernel Modules.
10870 19:56:14.229979 l Modules[0m.
10871 19:56:14.249588 <3>[ 19.859226] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 19:56:14.256635 <30>[ 19.862860] systemd[1]: Finished Remount Root and Kernel File Systems.
10873 19:56:14.263138 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10874 19:56:14.273873 <3>[ 19.883539] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 19:56:14.293880 <3>[ 19.904975] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 19:56:14.327406 Mounting [0;1;39mFUSE <30>[ 19.938593] systemd[1]: Mounting FUSE Control File System...
10877 19:56:14.330733 Control File System[0m...
10878 19:56:14.383201 Mounting [0;1;39mKerne<30>[ 19.994427] systemd[1]: Mounting Kernel Configuration File System...
10879 19:56:14.386391 l Configuration File System[0m...
10880 19:56:14.414379 <30>[ 20.023082] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10881 19:56:14.423004 <30>[ 20.023406] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10882 19:56:14.430571 Startin<30>[ 20.027564] systemd[1]: Starting Load/Save Random Seed...
10883 19:56:14.433876 g [0;1;39mLoad/Save Random Seed[0m...
10884 19:56:14.456735 Startin<30>[ 20.068739] systemd[1]: Starting Apply Kernel Variables...
10885 19:56:14.460139 g [0;1;39mApply Kernel Variables[0m...
10886 19:56:14.498180 Starting [0;1;39mCreate System Users[<4>[ 20.098084] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10887 19:56:14.499702 0m...
10888 19:56:14.507222 <3>[ 20.098153] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10889 19:56:14.510950 <30>[ 20.098273] systemd[1]: Starting Create System Users...
10890 19:56:14.517394 <30>[ 20.131161] systemd[1]: Started Journal Service.
10891 19:56:14.523601 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10892 19:56:14.546910 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10893 19:56:14.558447 See 'systemctl status systemd-udev-trigger.service' for details.
10894 19:56:14.574726 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10895 19:56:14.590990 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10896 19:56:14.608283 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10897 19:56:14.623715 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10898 19:56:14.640309 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10899 19:56:14.679832 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10900 19:56:14.697238 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10901 19:56:14.733498 <46>[ 20.343071] systemd-journald[304]: Received client request to flush runtime journal.
10902 19:56:15.482579 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10903 19:56:15.499508 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10904 19:56:15.514290 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10905 19:56:15.578539 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10906 19:56:16.124316 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10907 19:56:16.179284 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10908 19:56:16.219100 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10909 19:56:16.271493 Starting [0;1;39mNetwork Service[0m...
10910 19:56:16.556621 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10911 19:56:16.579374 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10912 19:56:16.614648 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10913 19:56:16.953611 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10914 19:56:16.966487 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10915 19:56:16.985650 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10916 19:56:16.999626 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10917 19:56:17.018758 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10918 19:56:17.087530 Starting [0;1;39mNetwork Name Resolution[0m...
10919 19:56:17.107710 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10920 19:56:17.135679 Starting [0;1;39mNetwork Time Synchronization[0m...
10921 19:56:17.159432 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10922 19:56:17.175597 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10923 19:56:17.245869 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10924 19:56:17.382934 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10925 19:56:17.399031 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10926 19:56:17.417111 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10927 19:56:17.430274 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10928 19:56:17.446193 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10929 19:56:17.569732 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10930 19:56:17.614901 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10931 19:56:17.639568 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10932 19:56:17.671529 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10933 19:56:17.686894 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10934 19:56:17.708455 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10935 19:56:17.722374 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10936 19:56:17.738840 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10937 19:56:17.795315 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10938 19:56:17.871339 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10939 19:56:18.018227 Starting [0;1;39mUser Login Management[0m...
10940 19:56:18.036255 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10941 19:56:18.053960 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10942 19:56:18.073142 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10943 19:56:18.106643 Starting [0;1;39mPermit User Sessions[0m...
10944 19:56:18.185589 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10945 19:56:18.206182 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10946 19:56:18.248671 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10947 19:56:18.268348 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10948 19:56:18.289694 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10949 19:56:18.307385 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10950 19:56:18.327875 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10951 19:56:18.347046 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10952 19:56:18.396237 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10953 19:56:18.446114 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10954 19:56:18.532100
10955 19:56:18.532313
10956 19:56:18.535559 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10957 19:56:18.535699
10958 19:56:18.538461 debian-bullseye-arm64 login: root (automatic login)
10959 19:56:18.538615
10960 19:56:18.538771
10961 19:56:18.853732 Linux debian-bullseye-arm64 6.1.59-cip8-rt4 #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023 aarch64
10962 19:56:18.854252
10963 19:56:18.860572 The programs included with the Debian GNU/Linux system are free software;
10964 19:56:18.867402 the exact distribution terms for each program are described in the
10965 19:56:18.870298 individual files in /usr/share/doc/*/copyright.
10966 19:56:18.870726
10967 19:56:18.877205 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10968 19:56:18.880083 permitted by applicable law.
10969 19:56:18.956510 Matched prompt #10: / #
10971 19:56:18.957834 Setting prompt string to ['/ #']
10972 19:56:18.958284 end: 2.2.5.1 login-action (duration 00:00:25) [common]
10974 19:56:18.959255 end: 2.2.5 auto-login-action (duration 00:00:25) [common]
10975 19:56:18.959864 start: 2.2.6 expect-shell-connection (timeout 00:03:41) [common]
10976 19:56:18.960290 Setting prompt string to ['/ #']
10977 19:56:18.960682 Forcing a shell prompt, looking for ['/ #']
10979 19:56:19.011812 / #
10980 19:56:19.012514 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10981 19:56:19.013152 Waiting using forced prompt support (timeout 00:02:30)
10982 19:56:19.018738
10983 19:56:19.019802 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10984 19:56:19.020393 start: 2.2.7 export-device-env (timeout 00:03:40) [common]
10986 19:56:19.121784 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11899579/extract-nfsrootfs-g6gngi29'
10987 19:56:19.128625 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11899579/extract-nfsrootfs-g6gngi29'
10989 19:56:19.230328 / # export NFS_SERVER_IP='192.168.201.1'
10990 19:56:19.236738 export NFS_SERVER_IP='192.168.201.1'
10991 19:56:19.237796 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10992 19:56:19.238346 end: 2.2 depthcharge-retry (duration 00:01:20) [common]
10993 19:56:19.238834 end: 2 depthcharge-action (duration 00:01:20) [common]
10994 19:56:19.239328 start: 3 lava-test-retry (timeout 00:30:00) [common]
10995 19:56:19.239840 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10996 19:56:19.240246 Using namespace: common
10998 19:56:19.341535 / # #
10999 19:56:19.342190 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11000 19:56:19.348116 #
11001 19:56:19.349194 Using /lava-11899579
11003 19:56:19.450337 / # export SHELL=/bin/sh
11004 19:56:19.456879 export SHELL=/bin/sh
11006 19:56:19.558806 / # . /lava-11899579/environment
11007 19:56:19.565328 . /lava-11899579/environment
11009 19:56:19.672738 / # /lava-11899579/bin/lava-test-runner /lava-11899579/0
11010 19:56:19.672925 Test shell timeout: 10s (minimum of the action and connection timeout)
11011 19:56:19.677838 /lava-11899579/bin/lava-test-runner /lava-11899579/0
11012 19:56:19.905297 + export TESTRUN_ID=0_lc-compliance
11013 19:56:19.911793 + cd /lava-11899579/0/tests/0_lc-compliance
11014 19:56:19.912312 + cat uuid
11015 19:56:19.917362 + UUID=11899579_1.6.2.3.1
11016 19:56:19.917849 + set +x
11017 19:56:19.924056 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 11899579_1.6.2.3.1>
11018 19:56:19.924761 Received signal: <STARTRUN> 0_lc-compliance 11899579_1.6.2.3.1
11019 19:56:19.925178 Starting test lava.0_lc-compliance (11899579_1.6.2.3.1)
11020 19:56:19.925639 Skipping test definition patterns.
11021 19:56:19.927394 + /usr/bin/lc-compliance-parser.sh
11022 19:56:21.156280 [0:00:26.680728959] [414] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
11023 19:56:21.159772 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11024 19:56:21.174276 [0:00:26.699077013] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11025 19:56:21.230037 [0:00:26.754439396] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11026 19:56:21.237825 [==========] Running 120 tests from 1 test suite.
11027 19:56:21.284569 [0:00:26.808244987] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11028 19:56:21.312309 [----------] Global test environment set-up.
11029 19:56:21.338482 [0:00:26.862189491] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11030 19:56:21.375848 [----------] 120 tests from CaptureTests/SingleStream
11031 19:56:21.446421 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11032 19:56:21.507640 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11033 19:56:21.508505 Received signal: <TESTSET> START CaptureTests/SingleStream
11034 19:56:21.508887 Starting test_set CaptureTests/SingleStream
11035 19:56:21.511015 Camera needs 4 requests, can't test only 1
11036 19:56:21.590499 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11037 19:56:21.661375
11038 19:56:21.740996 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (56 ms)
11039 19:56:21.800560 [0:00:27.318598715] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11040 19:56:21.837085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11041 19:56:21.837785 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11043 19:56:21.854573 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11044 19:56:21.912264 Camera needs 4 requests, can't test only 2
11045 19:56:21.988678 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11046 19:56:22.064284
11047 19:56:22.146212 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (54 ms)
11048 19:56:22.239049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11049 19:56:22.239692 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11051 19:56:22.254541 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11052 19:56:22.306158 Camera needs 4 requests, can't test only 3
11053 19:56:22.362071 [0:00:27.874659941] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11054 19:56:22.396985 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11055 19:56:22.481262
11056 19:56:22.562049 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (54 ms)
11057 19:56:22.646545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11058 19:56:22.646869 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11060 19:56:22.662477 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11061 19:56:22.713591 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (456 ms)
11062 19:56:22.807563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11063 19:56:22.808329 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11065 19:56:22.824875 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11066 19:56:22.877994 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (556 ms)
11067 19:56:22.966784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11068 19:56:22.967485 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11070 19:56:22.982577 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11071 19:56:23.049973 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (689 ms)
11072 19:56:23.060006 [0:00:28.563813324] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11073 19:56:23.149279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11074 19:56:23.150028 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11076 19:56:23.165071 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11077 19:56:23.946133 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (888 ms)
11078 19:56:23.956425 [0:00:29.453080261] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11079 19:56:24.048171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11080 19:56:24.048925 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11082 19:56:24.066628 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11083 19:56:25.341088 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1386 ms)
11084 19:56:25.350940 [0:00:30.840604340] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11085 19:56:25.432523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11086 19:56:25.432881 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11088 19:56:25.448763 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11089 19:56:27.437200 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2083 ms)
11090 19:56:27.446491 [0:00:32.924206299] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11091 19:56:27.527025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11092 19:56:27.527443 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11094 19:56:27.540183 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11095 19:56:30.602962 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3153 ms)
11096 19:56:30.612657 [0:00:36.076154709] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11097 19:56:30.666585 [0:00:36.130858385] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11098 19:56:30.702559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11099 19:56:30.703394 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11101 19:56:30.719215 [0:00:36.182948909] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11102 19:56:30.722147 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11103 19:56:30.770303 [0:00:36.234420032] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11104 19:56:30.773812 Camera needs 4 requests, can't test only 1
11105 19:56:30.860702 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11106 19:56:30.942023
11107 19:56:31.022656 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (55 ms)
11108 19:56:31.115954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11109 19:56:31.116693 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11111 19:56:31.132278 [0:00:36.595220966] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11112 19:56:31.135881 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11113 19:56:31.193883 Camera needs 4 requests, can't test only 2
11114 19:56:31.280565 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11115 19:56:31.363074
11116 19:56:31.451545 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (53 ms)
11117 19:56:31.548100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11118 19:56:31.549021 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11120 19:56:31.566356 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11121 19:56:31.596017 [0:00:37.057579412] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11122 19:56:31.628071 Camera needs 4 requests, can't test only 3
11123 19:56:31.702095 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11124 19:56:31.776528
11125 19:56:31.861857 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (51 ms)
11126 19:56:31.955557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11127 19:56:31.956315 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11129 19:56:31.973203 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11130 19:56:32.030725 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (361 ms)
11131 19:56:32.129912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11132 19:56:32.130615 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11134 19:56:32.146646 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11135 19:56:32.205312 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (463 ms)
11136 19:56:32.288969 [0:00:37.749015677] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11137 19:56:32.297317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11138 19:56:32.297991 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11140 19:56:32.313477 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11141 19:56:32.372953 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (691 ms)
11142 19:56:32.472324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11143 19:56:32.473055 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11145 19:56:32.489278 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11146 19:56:33.276216 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (992 ms)
11147 19:56:33.288721 [0:00:38.742610412] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11148 19:56:33.374031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11149 19:56:33.374748 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11151 19:56:33.389710 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11152 19:56:34.670368 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1392 ms)
11153 19:56:34.683291 [0:00:40.134436753] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11154 19:56:34.763995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11155 19:56:34.764744 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11157 19:56:34.780780 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11158 19:56:36.765126 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2091 ms)
11159 19:56:36.777877 [0:00:42.224879658] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11160 19:56:36.867893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11161 19:56:36.868687 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11163 19:56:36.885604 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11164 19:56:38.540980 <6>[ 44.158022] vpu: disabling
11165 19:56:38.544221 <6>[ 44.158140] vproc2: disabling
11166 19:56:38.551405 <6>[ 44.158270] vproc1: disabling
11167 19:56:38.554929 <6>[ 44.158325] vaud18: disabling
11168 19:56:38.558113 <6>[ 44.158580] vsram_others: disabling
11169 19:56:38.561256 <6>[ 44.158765] va09: disabling
11170 19:56:38.564284 <6>[ 44.158845] vsram_md: disabling
11171 19:56:38.568319 <6>[ 44.158976] Vgpu: disabling
11172 19:56:39.991816 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3224 ms)
11173 19:56:40.004349 [0:00:45.449251193] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11174 19:56:40.054277 [0:00:45.502166375] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11175 19:56:40.091608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11176 19:56:40.092445 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11178 19:56:40.107849 [0:00:45.555153108] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11179 19:56:40.110608 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11180 19:56:40.159463 [0:00:45.607520611] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11181 19:56:40.167891 Camera needs 4 requests, can't test only 1
11182 19:56:40.249064 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11183 19:56:40.325446
11184 19:56:40.413311 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (54 ms)
11185 19:56:40.508399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11186 19:56:40.509332 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11188 19:56:40.522703 [0:00:45.970316435] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11189 19:56:40.529129 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11190 19:56:40.584071 Camera needs 4 requests, can't test only 2
11191 19:56:40.664463 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11192 19:56:40.739441
11193 19:56:40.826040 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (52 ms)
11194 19:56:40.919215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11195 19:56:40.919933 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11197 19:56:40.936712 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11198 19:56:40.985186 [0:00:46.432595082] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11199 19:56:40.993586 Camera needs 4 requests, can't test only 3
11200 19:56:41.074258 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11201 19:56:41.150471
11202 19:56:41.234286 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (53 ms)
11203 19:56:41.328696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11204 19:56:41.328995 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11206 19:56:41.343052 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11207 19:56:41.393604 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (362 ms)
11208 19:56:41.479695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11209 19:56:41.480008 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11211 19:56:41.492433 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11212 19:56:41.539371 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (463 ms)
11213 19:56:41.631228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11214 19:56:41.632024 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11216 19:56:41.646443 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11217 19:56:41.678414 [0:00:47.125135296] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11218 19:56:41.702152 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (692 ms)
11219 19:56:41.793413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11220 19:56:41.794207 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11222 19:56:41.809475 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11223 19:56:42.565372 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (895 ms)
11224 19:56:42.578552 [0:00:48.019576068] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11225 19:56:42.658809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11226 19:56:42.659137 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11228 19:56:42.674119 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11229 19:56:43.959004 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1392 ms)
11230 19:56:43.971451 [0:00:49.412610884] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11231 19:56:44.042809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11232 19:56:44.043093 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11234 19:56:44.056583 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11235 19:56:46.052092 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2092 ms)
11236 19:56:46.064992 [0:00:51.504760968] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11237 19:56:46.142053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11238 19:56:46.142852 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11240 19:56:46.157392 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11241 19:56:49.214427 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3162 ms)
11242 19:56:49.227475 [0:00:54.666737536] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11243 19:56:49.275461 [0:00:54.719709022] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11244 19:56:49.314688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11245 19:56:49.315043 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11247 19:56:49.329733 [0:00:54.774143509] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11248 19:56:49.333125 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11249 19:56:49.382789 [0:00:54.827292410] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11250 19:56:49.386018 Camera needs 4 requests, can't test only 1
11251 19:56:49.455233 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11252 19:56:49.531052
11253 19:56:49.607364 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (52 ms)
11254 19:56:49.694157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11255 19:56:49.694939 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11257 19:56:49.712321 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11258 19:56:49.761874 Camera needs 4 requests, can't test only 2
11259 19:56:49.810508 [0:00:55.254642824] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11260 19:56:49.851655 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11261 19:56:49.927623
11262 19:56:49.997889 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (54 ms)
11263 19:56:50.091945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11264 19:56:50.092679 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11266 19:56:50.107627 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11267 19:56:50.160632 Camera needs 4 requests, can't test only 3
11268 19:56:50.242062 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11269 19:56:50.273318 [0:00:55.717163331] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11270 19:56:50.321194
11271 19:56:50.404938 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (54 ms)
11272 19:56:50.503126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11273 19:56:50.503879 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11275 19:56:50.521032 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11276 19:56:50.575323 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (428 ms)
11277 19:56:50.665424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11278 19:56:50.666186 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11280 19:56:50.681112 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11281 19:56:50.734680 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (462 ms)
11282 19:56:50.831562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11283 19:56:50.832394 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11285 19:56:50.848504 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11286 19:56:50.959422 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (694 ms)
11287 19:56:50.972673 [0:00:56.411475969] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11288 19:56:51.057828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11289 19:56:51.058539 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11291 19:56:51.076199 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11292 19:56:51.855447 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (896 ms)
11293 19:56:51.867938 [0:00:57.306887129] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11294 19:56:51.955546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11295 19:56:51.956317 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11297 19:56:51.971873 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11298 19:56:53.248395 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1392 ms)
11299 19:56:53.261281 [0:00:58.699856705] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11300 19:56:53.348443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11301 19:56:53.349203 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11303 19:56:53.366833 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11304 19:56:55.341509 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2092 ms)
11305 19:56:55.353714 [0:01:00.792287451] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11306 19:56:55.425889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11307 19:56:55.426169 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11309 19:56:55.438465 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11310 19:56:58.566886 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3225 ms)
11311 19:56:58.579778 [0:01:04.017959879] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11312 19:56:58.626580 [0:01:04.069453275] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11313 19:56:58.661598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11314 19:56:58.662319 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11316 19:56:58.679982 [0:01:04.122593012] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11317 19:56:58.683240 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11318 19:56:58.732003 [0:01:04.174553616] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11319 19:56:58.735215 Camera needs 4 requests, can't test only 1
11320 19:56:58.818088 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11321 19:56:58.895962
11322 19:56:58.983588 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (52 ms)
11323 19:56:59.078819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11324 19:56:59.079544 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11326 19:56:59.096415 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11327 19:56:59.151852 Camera needs 4 requests, can't test only 2
11328 19:56:59.230061 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11329 19:56:59.308595
11330 19:56:59.394595 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (53 ms)
11331 19:56:59.487895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11332 19:56:59.488616 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11334 19:56:59.503257 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11335 19:56:59.559407 Camera needs 4 requests, can't test only 3
11336 19:56:59.640522 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11337 19:56:59.720642
11338 19:56:59.802847 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (53 ms)
11339 19:56:59.879487 [0:01:05.321859373] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11340 19:56:59.899377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11341 19:56:59.900121 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11343 19:56:59.916152 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11344 19:56:59.970916 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1147 ms)
11345 19:57:00.058459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11346 19:57:00.059178 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11348 19:57:00.074664 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11349 19:57:01.258764 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1387 ms)
11350 19:57:01.271997 [0:01:06.709355472] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11351 19:57:01.345988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11352 19:57:01.346690 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11354 19:57:01.363870 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11355 19:57:03.368581 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2110 ms)
11356 19:57:03.381504 [0:01:08.819515037] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11357 19:57:03.470859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11358 19:57:03.471578 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11360 19:57:03.486848 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11361 19:57:06.050175 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2681 ms)
11362 19:57:06.063074 [0:01:11.500475088] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11363 19:57:06.145319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11364 19:57:06.146052 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11366 19:57:06.160708 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11367 19:57:10.259311 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4208 ms)
11368 19:57:10.270890 [0:01:15.708475787] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11369 19:57:10.350408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11370 19:57:10.351214 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11372 19:57:10.366401 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11373 19:57:16.535311 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6277 ms)
11374 19:57:16.548270 [0:01:21.986027774] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11375 19:57:16.636407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11376 19:57:16.637134 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11378 19:57:16.653755 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11379 19:57:26.145057 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9610 ms)
11380 19:57:26.158582 [0:01:31.595918782] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11381 19:57:26.204717 [0:01:31.647405465] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11382 19:57:26.247852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11383 19:57:26.248543 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11385 19:57:26.261459 [0:01:31.701649736] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11386 19:57:26.267782 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11387 19:57:26.312496 [0:01:31.755345274] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11388 19:57:26.321907 Camera needs 4 requests, can't test only 1
11389 19:57:26.401852 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11390 19:57:26.482502
11391 19:57:26.571768 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (51 ms)
11392 19:57:26.667050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11393 19:57:26.667804 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11395 19:57:26.685703 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11396 19:57:26.740659 Camera needs 4 requests, can't test only 2
11397 19:57:26.823660 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11398 19:57:26.892638
11399 19:57:26.984747 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (53 ms)
11400 19:57:27.082200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11401 19:57:27.082918 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11403 19:57:27.097724 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11404 19:57:27.150725 Camera needs 4 requests, can't test only 3
11405 19:57:27.222915 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11406 19:57:27.295603
11407 19:57:27.379858 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (54 ms)
11408 19:57:27.458708 [0:01:32.901401232] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11409 19:57:27.471345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11410 19:57:27.471612 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11412 19:57:27.483347 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11413 19:57:27.536571 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1146 ms)
11414 19:57:27.622852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11415 19:57:27.623170 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11417 19:57:27.634344 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11418 19:57:28.836880 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1383 ms)
11419 19:57:28.846372 [0:01:34.283776714] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11420 19:57:28.934079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11421 19:57:28.934430 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11423 19:57:28.943992 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11424 19:57:30.913228 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2077 ms)
11425 19:57:30.923161 [0:01:36.360802168] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11426 19:57:31.012248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11427 19:57:31.013064 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11429 19:57:31.026802 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11430 19:57:33.593808 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2680 ms)
11431 19:57:33.604676 [0:01:39.042115824] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11432 19:57:33.688012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11433 19:57:33.688764 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11435 19:57:33.701191 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11436 19:57:37.802911 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4209 ms)
11437 19:57:37.812609 [0:01:43.251284039] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11438 19:57:37.901417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11439 19:57:37.902116 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11441 19:57:37.914681 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11442 19:57:44.111796 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6308 ms)
11443 19:57:44.121040 [0:01:49.559858498] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11444 19:57:44.205079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11445 19:57:44.205809 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11447 19:57:44.217430 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11448 19:57:53.720451 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9609 ms)
11449 19:57:53.730695 [0:01:59.169845980] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11450 19:57:53.776544 [0:01:59.220613309] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11451 19:57:53.827223 [0:01:59.271569552] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11452 19:57:53.833984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11453 19:57:53.834672 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11455 19:57:53.844378 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11456 19:57:53.879386 [0:01:59.323456910] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11457 19:57:53.903817 Camera needs 4 requests, can't test only 1
11458 19:57:53.989693 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11459 19:57:54.071916
11460 19:57:54.161480 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (52 ms)
11461 19:57:54.253694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11462 19:57:54.254470 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11464 19:57:54.267201 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11465 19:57:54.324263 Camera needs 4 requests, can't test only 2
11466 19:57:54.408265 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11467 19:57:54.480903
11468 19:57:54.572893 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (51 ms)
11469 19:57:54.668661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11470 19:57:54.669439 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11472 19:57:54.682929 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11473 19:57:54.738057 Camera needs 4 requests, can't test only 3
11474 19:57:54.818430 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11475 19:57:54.897257
11476 19:57:54.989417 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (51 ms)
11477 19:57:55.086968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11478 19:57:55.087707 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11480 19:57:55.096574 [0:02:00.535726034] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11481 19:57:55.103403 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11482 19:57:55.162038 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1213 ms)
11483 19:57:55.254849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11484 19:57:55.255676 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11486 19:57:55.266101 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11487 19:57:56.468841 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1382 ms)
11488 19:57:56.478902 [0:02:01.918032952] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11489 19:57:56.567641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11490 19:57:56.568500 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11492 19:57:56.579769 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11493 19:57:58.514641 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2045 ms)
11494 19:57:58.524159 [0:02:03.963435245] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11495 19:57:58.615701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11496 19:57:58.616451 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11498 19:57:58.630403 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11499 19:58:01.195130 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2680 ms)
11500 19:58:01.204707 [0:02:06.643622604] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11501 19:58:01.287648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11502 19:58:01.288390 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11504 19:58:01.299851 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11505 19:58:05.371638 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4175 ms)
11506 19:58:05.381573 [0:02:10.819862838] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11507 19:58:05.469298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11508 19:58:05.470195 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11510 19:58:05.482499 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11511 19:58:11.646014 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6274 ms)
11512 19:58:11.655702 [0:02:17.094102513] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11513 19:58:11.743299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11514 19:58:11.744052 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11516 19:58:11.756595 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11517 19:58:21.255289 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9610 ms)
11518 19:58:21.265528 [0:02:26.703575413] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11519 19:58:21.312596 [0:02:26.755470685] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11520 19:58:21.349928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11521 19:58:21.350816 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11523 19:58:21.365497 [0:02:26.808804556] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11524 19:58:21.371952 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11525 19:58:21.418660 [0:02:26.861503425] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11526 19:58:21.421706 Camera needs 4 requests, can't test only 1
11527 19:58:21.489424 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11528 19:58:21.572998
11529 19:58:21.666749 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (52 ms)
11530 19:58:21.767317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11531 19:58:21.768156 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11533 19:58:21.782447 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11534 19:58:21.842441 Camera needs 4 requests, can't test only 2
11535 19:58:21.920649 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11536 19:58:21.992678
11537 19:58:22.073616 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (54 ms)
11538 19:58:22.164982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11539 19:58:22.165756 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11541 19:58:22.178624 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11542 19:58:22.235549 Camera needs 4 requests, can't test only 3
11543 19:58:22.310861 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11544 19:58:22.381426
11545 19:58:22.469062 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (52 ms)
11546 19:58:22.551179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11547 19:58:22.551531 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11549 19:58:22.566170 [0:02:28.009450170] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11550 19:58:22.572644 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11551 19:58:22.619971 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1147 ms)
11552 19:58:22.716241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11553 19:58:22.717170 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11555 19:58:22.728151 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11556 19:58:23.949457 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1388 ms)
11557 19:58:23.959301 [0:02:29.397713443] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11558 19:58:24.049567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11559 19:58:24.050465 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11561 19:58:24.061320 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11562 19:58:25.996526 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2047 ms)
11563 19:58:26.006404 [0:02:31.444455643] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11564 19:58:26.091093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11565 19:58:26.091379 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11567 19:58:26.102496 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11568 19:58:28.677446 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2681 ms)
11569 19:58:28.686672 [0:02:34.125262613] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11570 19:58:28.776720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11571 19:58:28.777516 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11573 19:58:28.789547 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11574 19:58:32.853281 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4176 ms)
11575 19:58:32.863025 [0:02:38.301492369] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11576 19:58:32.952073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11577 19:58:32.952818 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11579 19:58:32.967573 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11580 19:58:39.128624 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6275 ms)
11581 19:58:39.138441 [0:02:44.576682186] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11582 19:58:39.224372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11583 19:58:39.225131 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11585 19:58:39.237537 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11586 19:58:48.835099 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9707 ms)
11587 19:58:48.844213 [0:02:54.283366186] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11588 19:58:48.930963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11589 19:58:48.931681 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11591 19:58:48.942038 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11592 19:58:49.062786 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (232 ms)
11593 19:58:49.075841 [0:02:54.514979380] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11594 19:58:49.161222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11595 19:58:49.161982 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11597 19:58:49.178334 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11598 19:58:49.327835 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (265 ms)
11599 19:58:49.340721 [0:02:54.779655028] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11600 19:58:49.425838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11601 19:58:49.426547 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11603 19:58:49.443067 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11604 19:58:49.622008 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (294 ms)
11605 19:58:49.635000 [0:02:55.073581213] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11606 19:58:49.719626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11607 19:58:49.720370 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11609 19:58:49.733526 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11610 19:58:50.049192 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (427 ms)
11611 19:58:50.062196 [0:02:55.501239068] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11612 19:58:50.145633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11613 19:58:50.145920 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11615 19:58:50.160511 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11616 19:58:50.545386 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (496 ms)
11617 19:58:50.558431 [0:02:55.997205725] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 19:58:50.647525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11619 19:58:50.648347 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11621 19:58:50.661507 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11622 19:58:51.240141 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (694 ms)
11623 19:58:51.252675 [0:02:56.691921061] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 19:58:51.339021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11625 19:58:51.339828 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11627 19:58:51.355864 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11628 19:58:52.135989 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (895 ms)
11629 19:58:52.149177 [0:02:57.587522425] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11630 19:58:52.229835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11631 19:58:52.230537 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11633 19:58:52.245171 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11634 19:58:53.529590 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1393 ms)
11635 19:58:53.541973 [0:02:58.981595778] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 19:58:53.609673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11637 19:58:53.609947 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11639 19:58:53.624459 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11640 19:58:55.622563 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2094 ms)
11641 19:58:55.636116 [0:03:01.075219075] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 19:58:55.733867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11643 19:58:55.734764 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11645 19:58:55.750415 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11646 19:58:58.786409 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3163 ms)
11647 19:58:58.798984 [0:03:04.238822490] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11648 19:58:58.886273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11649 19:58:58.886994 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11651 19:58:58.902255 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11652 19:58:59.117259 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (328 ms)
11653 19:58:59.127260 [0:03:04.566209926] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11654 19:58:59.212191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11655 19:58:59.212972 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11657 19:58:59.224041 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11658 19:58:59.477991 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (361 ms)
11659 19:58:59.487604 [0:03:04.926912941] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11660 19:58:59.572884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11661 19:58:59.573752 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11663 19:58:59.584896 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11664 19:58:59.775686 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (298 ms)
11665 19:58:59.785666 [0:03:05.224645333] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11666 19:58:59.867878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11667 19:58:59.868616 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11669 19:58:59.879784 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11670 19:59:00.203782 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (427 ms)
11671 19:59:00.213410 [0:03:05.652538929] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11672 19:59:00.297126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11673 19:59:00.297880 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11675 19:59:00.309779 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11676 19:59:00.666122 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (463 ms)
11677 19:59:00.676140 [0:03:06.115441312] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11678 19:59:00.760201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11679 19:59:00.760923 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11681 19:59:00.771409 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11682 19:59:01.361385 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (695 ms)
11683 19:59:01.370938 [0:03:06.810257787] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11684 19:59:01.454599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11685 19:59:01.455318 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11687 19:59:01.468188 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11688 19:59:02.256624 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (895 ms)
11689 19:59:02.266427 [0:03:07.706070579] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11690 19:59:02.353389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11691 19:59:02.354148 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11693 19:59:02.365796 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11694 19:59:03.650631 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1393 ms)
11695 19:59:03.660468 [0:03:09.099834141] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11696 19:59:03.741256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11697 19:59:03.741947 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11699 19:59:03.753860 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11700 19:59:05.744183 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2093 ms)
11701 19:59:05.753588 [0:03:11.193467866] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11702 19:59:05.842145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11703 19:59:05.842901 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11705 19:59:05.856463 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11706 19:59:08.970505 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3226 ms)
11707 19:59:08.980481 [0:03:14.419810452] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11708 19:59:09.061901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11709 19:59:09.062249 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11711 19:59:09.070997 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11712 19:59:09.264750 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (295 ms)
11713 19:59:09.274791 [0:03:14.714510436] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11714 19:59:09.364610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11715 19:59:09.365327 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11717 19:59:09.377548 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11718 19:59:09.593906 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (328 ms)
11719 19:59:09.602742 [0:03:15.042673428] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11720 19:59:09.694294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11721 19:59:09.695021 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11723 19:59:09.707673 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11724 19:59:09.890715 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (297 ms)
11725 19:59:09.899915 [0:03:15.339280526] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11726 19:59:09.978400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11727 19:59:09.978721 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11729 19:59:09.987901 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11730 19:59:10.350443 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (461 ms)
11731 19:59:10.359848 [0:03:15.799876046] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11732 19:59:10.435744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11733 19:59:10.436068 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11735 19:59:10.444961 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11736 19:59:10.911330 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (560 ms)
11737 19:59:10.920714 [0:03:16.360433207] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11738 19:59:11.008556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11739 19:59:11.009346 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11741 19:59:11.021079 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11742 19:59:11.604947 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (694 ms)
11743 19:59:11.615295 [0:03:17.055027562] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11744 19:59:11.701344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11745 19:59:11.702215 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11747 19:59:11.713605 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11748 19:59:12.502066 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (897 ms)
11749 19:59:12.511578 [0:03:17.951180159] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11750 19:59:12.591108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11751 19:59:12.591423 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11753 19:59:12.601454 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11754 19:59:13.896034 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1394 ms)
11755 19:59:13.905222 [0:03:19.345249000] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11756 19:59:13.993071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11757 19:59:13.993775 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11759 19:59:14.003845 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11760 19:59:15.989403 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2093 ms)
11761 19:59:15.999786 [0:03:21.439161230] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11762 19:59:16.086041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11763 19:59:16.086909 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11765 19:59:16.098612 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11766 19:59:19.152155 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3163 ms)
11767 19:59:19.162213 [0:03:24.602357932] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11768 19:59:19.249478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11769 19:59:19.250387 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11771 19:59:19.260628 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11772 19:59:19.479686 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (327 ms)
11773 19:59:19.489638 [0:03:24.929925363] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11774 19:59:19.575324 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11776 19:59:19.577778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11777 19:59:19.591069 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11778 19:59:19.841202 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (361 ms)
11779 19:59:19.850841 [0:03:25.290633780] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11780 19:59:19.934711 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11782 19:59:19.938111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11783 19:59:19.947399 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11784 19:59:20.138388 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (298 ms)
11785 19:59:20.148404 [0:03:25.588420200] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11786 19:59:20.238849 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11788 19:59:20.242078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11789 19:59:20.254516 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11790 19:59:20.566080 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (428 ms)
11791 19:59:20.576290 [0:03:26.016305438] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11792 19:59:20.662634 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11794 19:59:20.665783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11795 19:59:20.677986 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11796 19:59:21.029428 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (463 ms)
11797 19:59:21.039075 [0:03:26.479232864] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11798 19:59:21.119178 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11800 19:59:21.122370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11801 19:59:21.133689 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11802 19:59:21.724229 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (694 ms)
11803 19:59:21.734410 [0:03:27.173962186] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11804 19:59:21.815965 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11806 19:59:21.818353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11807 19:59:21.832616 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11808 19:59:22.718956 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (994 ms)
11809 19:59:22.728300 [0:03:28.167848732] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11810 19:59:22.812151 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11812 19:59:22.815361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11813 19:59:22.828865 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11814 19:59:24.145595 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1426 ms)
11815 19:59:24.154678 [0:03:29.594849967] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11816 19:59:24.236710 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11818 19:59:24.239473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11819 19:59:24.251779 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11820 19:59:26.238035 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2094 ms)
11821 19:59:26.247850 [0:03:31.688287231] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11822 19:59:26.336859 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11824 19:59:26.339827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11825 19:59:26.353208 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11826 19:59:29.402008 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3164 ms)
11827 19:59:29.487981 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11829 19:59:29.490600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11830 19:59:29.502776 [----------] 120 tests from CaptureTests/SingleStream (188154 ms total)
11831 19:59:29.584272
11832 19:59:29.667850 [----------] Global test environment tear-down
11833 19:59:29.751617 [==========] 120 tests from 1 test suite ran. (188154 ms total)
11834 19:59:29.839054 <LAVA_SIGNAL_TESTSET STOP>
11835 19:59:29.839976 Received signal: <TESTSET> STOP
11836 19:59:29.840461 Closing test_set CaptureTests/SingleStream
11837 19:59:29.848341 + set +x
11838 19:59:29.851919 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 11899579_1.6.2.3.1>
11839 19:59:29.852594 Received signal: <ENDRUN> 0_lc-compliance 11899579_1.6.2.3.1
11840 19:59:29.853043 Ending use of test pattern.
11841 19:59:29.853365 Ending test lava.0_lc-compliance (11899579_1.6.2.3.1), duration 189.93
11843 19:59:29.855047 <LAVA_TEST_RUNNER EXIT>
11844 19:59:29.855717 ok: lava_test_shell seems to have completed
11845 19:59:29.865186 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11846 19:59:29.866050 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11847 19:59:29.866508 end: 3 lava-test-retry (duration 00:03:11) [common]
11848 19:59:29.866949 start: 4 finalize (timeout 00:10:00) [common]
11849 19:59:29.867389 start: 4.1 power-off (timeout 00:00:30) [common]
11850 19:59:29.868153 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11851 19:59:29.989178 >> Command sent successfully.
11852 19:59:29.993438 Returned 0 in 0 seconds
11853 19:59:30.094477 end: 4.1 power-off (duration 00:00:00) [common]
11855 19:59:30.096127 start: 4.2 read-feedback (timeout 00:10:00) [common]
11856 19:59:30.097431 Listened to connection for namespace 'common' for up to 1s
11857 19:59:31.097717 Finalising connection for namespace 'common'
11858 19:59:31.098447 Disconnecting from shell: Finalise
11859 19:59:31.098945 / #
11860 19:59:31.200117 end: 4.2 read-feedback (duration 00:00:01) [common]
11861 19:59:31.200954 end: 4 finalize (duration 00:00:01) [common]
11862 19:59:31.201699 Cleaning after the job
11863 19:59:31.202279 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/ramdisk
11864 19:59:31.215264 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/kernel
11865 19:59:31.251694 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/dtb
11866 19:59:31.252072 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/nfsrootfs
11867 19:59:31.314431 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899579/tftp-deploy-2vc2u5r_/modules
11868 19:59:31.321832 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11899579
11869 19:59:31.636356 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11899579
11870 19:59:31.636538 Job finished correctly