Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 26
- Kernel Errors: 37
- Errors: 1
- Boot result: PASS
1 19:51:35.118309 lava-dispatcher, installed at version: 2023.08
2 19:51:35.118520 start: 0 validate
3 19:51:35.118642 Start time: 2023-10-28 19:51:35.118635+00:00 (UTC)
4 19:51:35.118755 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:51:35.118882 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 19:51:35.386726 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:51:35.386933 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:51:35.654440 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:51:35.655289 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:52:05.893675 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:52:05.894397 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:52:06.430443 validate duration: 31.31
14 19:52:06.431810 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:52:06.432366 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:52:06.432871 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:52:06.433529 Not decompressing ramdisk as can be used compressed.
18 19:52:06.434007 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 19:52:06.434385 saving as /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/ramdisk/rootfs.cpio.gz
20 19:52:06.434755 total size: 26246609 (25 MB)
21 19:52:09.232377 progress 0 % (0 MB)
22 19:52:09.242472 progress 5 % (1 MB)
23 19:52:09.249223 progress 10 % (2 MB)
24 19:52:09.256054 progress 15 % (3 MB)
25 19:52:09.262954 progress 20 % (5 MB)
26 19:52:09.269950 progress 25 % (6 MB)
27 19:52:09.276910 progress 30 % (7 MB)
28 19:52:09.283734 progress 35 % (8 MB)
29 19:52:09.290643 progress 40 % (10 MB)
30 19:52:09.297507 progress 45 % (11 MB)
31 19:52:09.304387 progress 50 % (12 MB)
32 19:52:09.311198 progress 55 % (13 MB)
33 19:52:09.318046 progress 60 % (15 MB)
34 19:52:09.324922 progress 65 % (16 MB)
35 19:52:09.331952 progress 70 % (17 MB)
36 19:52:09.338802 progress 75 % (18 MB)
37 19:52:09.345668 progress 80 % (20 MB)
38 19:52:09.352487 progress 85 % (21 MB)
39 19:52:09.359198 progress 90 % (22 MB)
40 19:52:09.366019 progress 95 % (23 MB)
41 19:52:09.372745 progress 100 % (25 MB)
42 19:52:09.372990 25 MB downloaded in 2.94 s (8.52 MB/s)
43 19:52:09.373144 end: 1.1.1 http-download (duration 00:00:03) [common]
45 19:52:09.373454 end: 1.1 download-retry (duration 00:00:03) [common]
46 19:52:09.373541 start: 1.2 download-retry (timeout 00:09:57) [common]
47 19:52:09.373624 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 19:52:09.373757 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:52:09.373829 saving as /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/kernel/Image
50 19:52:09.373890 total size: 49304064 (47 MB)
51 19:52:09.373949 No compression specified
52 19:52:09.375025 progress 0 % (0 MB)
53 19:52:09.388044 progress 5 % (2 MB)
54 19:52:09.400543 progress 10 % (4 MB)
55 19:52:09.412910 progress 15 % (7 MB)
56 19:52:09.425298 progress 20 % (9 MB)
57 19:52:09.438068 progress 25 % (11 MB)
58 19:52:09.450767 progress 30 % (14 MB)
59 19:52:09.463661 progress 35 % (16 MB)
60 19:52:09.476534 progress 40 % (18 MB)
61 19:52:09.489386 progress 45 % (21 MB)
62 19:52:09.501963 progress 50 % (23 MB)
63 19:52:09.514441 progress 55 % (25 MB)
64 19:52:09.526931 progress 60 % (28 MB)
65 19:52:09.539550 progress 65 % (30 MB)
66 19:52:09.552193 progress 70 % (32 MB)
67 19:52:09.565751 progress 75 % (35 MB)
68 19:52:09.579635 progress 80 % (37 MB)
69 19:52:09.593367 progress 85 % (39 MB)
70 19:52:09.608276 progress 90 % (42 MB)
71 19:52:09.621355 progress 95 % (44 MB)
72 19:52:09.634676 progress 100 % (47 MB)
73 19:52:09.634912 47 MB downloaded in 0.26 s (180.14 MB/s)
74 19:52:09.635067 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:52:09.635301 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:52:09.635389 start: 1.3 download-retry (timeout 00:09:57) [common]
78 19:52:09.635483 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 19:52:09.635621 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:52:09.635691 saving as /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/dtb/mt8192-asurada-spherion-r0.dtb
81 19:52:09.635767 total size: 47278 (0 MB)
82 19:52:09.635831 No compression specified
83 19:52:09.636906 progress 69 % (0 MB)
84 19:52:09.637178 progress 100 % (0 MB)
85 19:52:09.637334 0 MB downloaded in 0.00 s (28.82 MB/s)
86 19:52:09.637456 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:52:09.637677 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:52:09.637762 start: 1.4 download-retry (timeout 00:09:57) [common]
90 19:52:09.637845 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 19:52:09.637958 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:52:09.638026 saving as /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/modules/modules.tar
93 19:52:09.638086 total size: 8635496 (8 MB)
94 19:52:09.638146 Using unxz to decompress xz
95 19:52:09.642620 progress 0 % (0 MB)
96 19:52:09.664203 progress 5 % (0 MB)
97 19:52:09.686537 progress 10 % (0 MB)
98 19:52:09.712721 progress 15 % (1 MB)
99 19:52:09.737900 progress 20 % (1 MB)
100 19:52:09.763083 progress 25 % (2 MB)
101 19:52:09.791349 progress 30 % (2 MB)
102 19:52:09.816401 progress 35 % (2 MB)
103 19:52:09.841310 progress 40 % (3 MB)
104 19:52:09.865080 progress 45 % (3 MB)
105 19:52:09.891434 progress 50 % (4 MB)
106 19:52:09.916621 progress 55 % (4 MB)
107 19:52:09.943171 progress 60 % (4 MB)
108 19:52:09.965790 progress 65 % (5 MB)
109 19:52:09.990764 progress 70 % (5 MB)
110 19:52:10.014992 progress 75 % (6 MB)
111 19:52:10.041282 progress 80 % (6 MB)
112 19:52:10.073447 progress 85 % (7 MB)
113 19:52:10.099291 progress 90 % (7 MB)
114 19:52:10.123867 progress 95 % (7 MB)
115 19:52:10.147656 progress 100 % (8 MB)
116 19:52:10.153468 8 MB downloaded in 0.52 s (15.98 MB/s)
117 19:52:10.153726 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:52:10.154017 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:52:10.154126 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 19:52:10.154238 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 19:52:10.154342 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:52:10.154466 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 19:52:10.154747 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d
125 19:52:10.154925 makedir: /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin
126 19:52:10.155071 makedir: /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/tests
127 19:52:10.155187 makedir: /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/results
128 19:52:10.155318 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-add-keys
129 19:52:10.155482 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-add-sources
130 19:52:10.155634 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-background-process-start
131 19:52:10.155849 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-background-process-stop
132 19:52:10.155996 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-common-functions
133 19:52:10.156166 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-echo-ipv4
134 19:52:10.156334 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-install-packages
135 19:52:10.156477 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-installed-packages
136 19:52:10.156620 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-os-build
137 19:52:10.156763 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-probe-channel
138 19:52:10.156909 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-probe-ip
139 19:52:10.157079 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-target-ip
140 19:52:10.157248 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-target-mac
141 19:52:10.157416 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-target-storage
142 19:52:10.157589 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-test-case
143 19:52:10.157756 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-test-event
144 19:52:10.157897 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-test-feedback
145 19:52:10.158039 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-test-raise
146 19:52:10.158183 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-test-reference
147 19:52:10.158326 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-test-runner
148 19:52:10.158476 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-test-set
149 19:52:10.158645 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-test-shell
150 19:52:10.158795 Updating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-install-packages (oe)
151 19:52:10.158996 Updating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/bin/lava-installed-packages (oe)
152 19:52:10.159159 Creating /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/environment
153 19:52:10.159275 LAVA metadata
154 19:52:10.159384 - LAVA_JOB_ID=11899576
155 19:52:10.159486 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:52:10.159635 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 19:52:10.159760 skipped lava-vland-overlay
158 19:52:10.159875 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:52:10.159977 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 19:52:10.160074 skipped lava-multinode-overlay
161 19:52:10.160196 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:52:10.160333 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 19:52:10.160445 Loading test definitions
164 19:52:10.160560 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 19:52:10.160648 Using /lava-11899576 at stage 0
166 19:52:10.161045 uuid=11899576_1.5.2.3.1 testdef=None
167 19:52:10.161169 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 19:52:10.161271 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 19:52:10.161970 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 19:52:10.162329 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 19:52:10.162958 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 19:52:10.163215 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 19:52:10.163864 runner path: /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11899576_1.5.2.3.1
176 19:52:10.164029 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 19:52:10.164253 Creating lava-test-runner.conf files
179 19:52:10.164336 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899576/lava-overlay-8ycihv3d/lava-11899576/0 for stage 0
180 19:52:10.164456 - 0_v4l2-compliance-mtk-vcodec-enc
181 19:52:10.164592 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 19:52:10.164692 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
183 19:52:10.172677 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 19:52:10.172791 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
185 19:52:10.172892 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 19:52:10.172994 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 19:52:10.173098 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
188 19:52:10.893293 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 19:52:10.893685 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
190 19:52:10.893819 extracting modules file /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899576/extract-overlay-ramdisk-k0sxsifp/ramdisk
191 19:52:11.124707 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 19:52:11.124877 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
193 19:52:11.124982 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899576/compress-overlay-54bd24ju/overlay-1.5.2.4.tar.gz to ramdisk
194 19:52:11.125053 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899576/compress-overlay-54bd24ju/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11899576/extract-overlay-ramdisk-k0sxsifp/ramdisk
195 19:52:11.131702 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 19:52:11.131896 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
197 19:52:11.131986 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 19:52:11.132075 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
199 19:52:11.132154 Building ramdisk /var/lib/lava/dispatcher/tmp/11899576/extract-overlay-ramdisk-k0sxsifp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11899576/extract-overlay-ramdisk-k0sxsifp/ramdisk
200 19:52:11.750891 >> 228405 blocks
201 19:52:15.615557 rename /var/lib/lava/dispatcher/tmp/11899576/extract-overlay-ramdisk-k0sxsifp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/ramdisk/ramdisk.cpio.gz
202 19:52:15.616044 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 19:52:15.616192 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 19:52:15.616310 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 19:52:15.616437 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/kernel/Image'
206 19:52:28.191963 Returned 0 in 12 seconds
207 19:52:28.292958 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/kernel/image.itb
208 19:52:28.928903 output: FIT description: Kernel Image image with one or more FDT blobs
209 19:52:28.929286 output: Created: Sat Oct 28 20:52:28 2023
210 19:52:28.929387 output: Image 0 (kernel-1)
211 19:52:28.929471 output: Description:
212 19:52:28.929552 output: Created: Sat Oct 28 20:52:28 2023
213 19:52:28.929635 output: Type: Kernel Image
214 19:52:28.929714 output: Compression: lzma compressed
215 19:52:28.929793 output: Data Size: 11047522 Bytes = 10788.60 KiB = 10.54 MiB
216 19:52:28.929892 output: Architecture: AArch64
217 19:52:28.929991 output: OS: Linux
218 19:52:28.930086 output: Load Address: 0x00000000
219 19:52:28.930182 output: Entry Point: 0x00000000
220 19:52:28.930277 output: Hash algo: crc32
221 19:52:28.930374 output: Hash value: da40eda2
222 19:52:28.930466 output: Image 1 (fdt-1)
223 19:52:28.930563 output: Description: mt8192-asurada-spherion-r0
224 19:52:28.930656 output: Created: Sat Oct 28 20:52:28 2023
225 19:52:28.930747 output: Type: Flat Device Tree
226 19:52:28.930838 output: Compression: uncompressed
227 19:52:28.930928 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 19:52:28.931018 output: Architecture: AArch64
229 19:52:28.931108 output: Hash algo: crc32
230 19:52:28.931199 output: Hash value: cc4352de
231 19:52:28.931289 output: Image 2 (ramdisk-1)
232 19:52:28.931378 output: Description: unavailable
233 19:52:28.931468 output: Created: Sat Oct 28 20:52:28 2023
234 19:52:28.931557 output: Type: RAMDisk Image
235 19:52:28.931646 output: Compression: Unknown Compression
236 19:52:28.931740 output: Data Size: 39367638 Bytes = 38444.96 KiB = 37.54 MiB
237 19:52:28.931884 output: Architecture: AArch64
238 19:52:28.931974 output: OS: Linux
239 19:52:28.932063 output: Load Address: unavailable
240 19:52:28.932153 output: Entry Point: unavailable
241 19:52:28.932242 output: Hash algo: crc32
242 19:52:28.932331 output: Hash value: c6178e73
243 19:52:28.932420 output: Default Configuration: 'conf-1'
244 19:52:28.932509 output: Configuration 0 (conf-1)
245 19:52:28.932597 output: Description: mt8192-asurada-spherion-r0
246 19:52:28.932687 output: Kernel: kernel-1
247 19:52:28.932776 output: Init Ramdisk: ramdisk-1
248 19:52:28.932865 output: FDT: fdt-1
249 19:52:28.932953 output: Loadables: kernel-1
250 19:52:28.933042 output:
251 19:52:28.933284 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 19:52:28.933423 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 19:52:28.933575 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 19:52:28.933712 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 19:52:28.933823 No LXC device requested
256 19:52:28.933922 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 19:52:28.934050 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 19:52:28.934167 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 19:52:28.934273 Checking files for TFTP limit of 4294967296 bytes.
260 19:52:28.934942 end: 1 tftp-deploy (duration 00:00:23) [common]
261 19:52:28.935080 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 19:52:28.935218 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 19:52:28.935387 substitutions:
264 19:52:28.935483 - {DTB}: 11899576/tftp-deploy-nqnatrmr/dtb/mt8192-asurada-spherion-r0.dtb
265 19:52:28.935583 - {INITRD}: 11899576/tftp-deploy-nqnatrmr/ramdisk/ramdisk.cpio.gz
266 19:52:28.935678 - {KERNEL}: 11899576/tftp-deploy-nqnatrmr/kernel/Image
267 19:52:28.935836 - {LAVA_MAC}: None
268 19:52:28.935932 - {PRESEED_CONFIG}: None
269 19:52:28.936026 - {PRESEED_LOCAL}: None
270 19:52:28.936119 - {RAMDISK}: 11899576/tftp-deploy-nqnatrmr/ramdisk/ramdisk.cpio.gz
271 19:52:28.936211 - {ROOT_PART}: None
272 19:52:28.936304 - {ROOT}: None
273 19:52:28.936395 - {SERVER_IP}: 192.168.201.1
274 19:52:28.936487 - {TEE}: None
275 19:52:28.936578 Parsed boot commands:
276 19:52:28.936668 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 19:52:28.936899 Parsed boot commands: tftpboot 192.168.201.1 11899576/tftp-deploy-nqnatrmr/kernel/image.itb 11899576/tftp-deploy-nqnatrmr/kernel/cmdline
278 19:52:28.937022 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 19:52:28.937149 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 19:52:28.937284 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 19:52:28.937407 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 19:52:28.937515 Not connected, no need to disconnect.
283 19:52:28.937631 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 19:52:28.937750 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 19:52:28.937854 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 19:52:28.941883 Setting prompt string to ['lava-test: # ']
287 19:52:28.942271 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 19:52:28.942409 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 19:52:28.942520 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 19:52:28.942642 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 19:52:28.942920 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 19:52:34.087424 >> Command sent successfully.
293 19:52:34.090465 Returned 0 in 5 seconds
294 19:52:34.191293 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 19:52:34.193209 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 19:52:34.193761 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 19:52:34.194404 Setting prompt string to 'Starting depthcharge on Spherion...'
299 19:52:34.195048 Changing prompt to 'Starting depthcharge on Spherion...'
300 19:52:34.195468 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 19:52:34.196801 [Enter `^Ec?' for help]
302 19:52:34.364514
303 19:52:34.365198
304 19:52:34.365562 F0: 102B 0000
305 19:52:34.365936
306 19:52:34.366295 F3: 1001 0000 [0200]
307 19:52:34.367979
308 19:52:34.368521 F3: 1001 0000
309 19:52:34.369144
310 19:52:34.369573 F7: 102D 0000
311 19:52:34.369922
312 19:52:34.371859 F1: 0000 0000
313 19:52:34.372450
314 19:52:34.373073 V0: 0000 0000 [0001]
315 19:52:34.373427
316 19:52:34.373741 00: 0007 8000
317 19:52:34.374052
318 19:52:34.375601 01: 0000 0000
319 19:52:34.376309
320 19:52:34.376882 BP: 0C00 0209 [0000]
321 19:52:34.377214
322 19:52:34.379493 G0: 1182 0000
323 19:52:34.380073
324 19:52:34.380425 EC: 0000 0021 [4000]
325 19:52:34.380747
326 19:52:34.383289 S7: 0000 0000 [0000]
327 19:52:34.383863
328 19:52:34.384219 CC: 0000 0000 [0001]
329 19:52:34.384535
330 19:52:34.386687 T0: 0000 0040 [010F]
331 19:52:34.387154
332 19:52:34.387527 Jump to BL
333 19:52:34.387919
334 19:52:34.410686
335 19:52:34.411220
336 19:52:34.411596
337 19:52:34.418049 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 19:52:34.421317 ARM64: Exception handlers installed.
339 19:52:34.424750 ARM64: Testing exception
340 19:52:34.428363 ARM64: Done test exception
341 19:52:34.435618 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 19:52:34.445973 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 19:52:34.453796 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 19:52:34.461332 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 19:52:34.471183 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 19:52:34.477834 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 19:52:34.487418 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 19:52:34.494180 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 19:52:34.513623 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 19:52:34.517099 WDT: Last reset was cold boot
351 19:52:34.520560 SPI1(PAD0) initialized at 2873684 Hz
352 19:52:34.523615 SPI5(PAD0) initialized at 992727 Hz
353 19:52:34.526767 VBOOT: Loading verstage.
354 19:52:34.533598 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 19:52:34.537241 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 19:52:34.540148 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 19:52:34.543213 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 19:52:34.551016 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 19:52:34.557929 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 19:52:34.568982 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 19:52:34.569407
362 19:52:34.569742
363 19:52:34.578798 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 19:52:34.582009 ARM64: Exception handlers installed.
365 19:52:34.585576 ARM64: Testing exception
366 19:52:34.585998 ARM64: Done test exception
367 19:52:34.592246 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 19:52:34.595763 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 19:52:34.610104 Probing TPM: . done!
370 19:52:34.610740 TPM ready after 0 ms
371 19:52:34.616390 Connected to device vid:did:rid of 1ae0:0028:00
372 19:52:34.626590 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 19:52:34.664166 Initialized TPM device CR50 revision 0
374 19:52:34.676698 tlcl_send_startup: Startup return code is 0
375 19:52:34.677052 TPM: setup succeeded
376 19:52:34.687691 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 19:52:34.696122 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 19:52:34.703498 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 19:52:34.715655 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 19:52:34.718749 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 19:52:34.722158 in-header: 03 07 00 00 08 00 00 00
382 19:52:34.725275 in-data: aa e4 47 04 13 02 00 00
383 19:52:34.729004 Chrome EC: UHEPI supported
384 19:52:34.735753 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 19:52:34.738963 in-header: 03 ad 00 00 08 00 00 00
386 19:52:34.742414 in-data: 00 20 20 08 00 00 00 00
387 19:52:34.742537 Phase 1
388 19:52:34.745807 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 19:52:34.752220 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 19:52:34.759031 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 19:52:34.762324 Recovery requested (1009000e)
392 19:52:34.766107 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 19:52:34.775175 tlcl_extend: response is 0
394 19:52:34.783127 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 19:52:34.788470 tlcl_extend: response is 0
396 19:52:34.794615 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 19:52:34.815088 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 19:52:34.822120 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 19:52:34.822721
400 19:52:34.823278
401 19:52:34.832605 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 19:52:34.835650 ARM64: Exception handlers installed.
403 19:52:34.838943 ARM64: Testing exception
404 19:52:34.839361 ARM64: Done test exception
405 19:52:34.861400 pmic_efuse_setting: Set efuses in 11 msecs
406 19:52:34.864916 pmwrap_interface_init: Select PMIF_VLD_RDY
407 19:52:34.868626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 19:52:34.875388 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 19:52:34.878537 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 19:52:34.885528 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 19:52:34.888678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 19:52:34.896479 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 19:52:34.898892 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 19:52:34.902618 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 19:52:34.909238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 19:52:34.912111 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 19:52:34.918912 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 19:52:34.921823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 19:52:34.925476 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 19:52:34.932392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 19:52:34.938869 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 19:52:34.945714 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 19:52:34.949567 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 19:52:34.955480 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 19:52:34.962508 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 19:52:34.965584 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 19:52:34.972305 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 19:52:34.979479 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 19:52:34.982890 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 19:52:34.990666 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 19:52:34.993800 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 19:52:35.000542 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 19:52:35.004301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 19:52:35.010711 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 19:52:35.014081 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 19:52:35.021023 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 19:52:35.024427 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 19:52:35.032415 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 19:52:35.035575 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 19:52:35.038821 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 19:52:35.046009 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 19:52:35.049116 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 19:52:35.055830 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 19:52:35.058958 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 19:52:35.065846 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 19:52:35.069249 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 19:52:35.073222 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 19:52:35.077290 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 19:52:35.080447 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 19:52:35.087441 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 19:52:35.090502 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 19:52:35.093849 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 19:52:35.100034 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 19:52:35.103759 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 19:52:35.107009 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 19:52:35.110319 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 19:52:35.117318 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 19:52:35.123885 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 19:52:35.133240 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 19:52:35.137206 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 19:52:35.143245 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 19:52:35.153357 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 19:52:35.156826 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 19:52:35.163367 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 19:52:35.166744 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 19:52:35.173953 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2a
467 19:52:35.180301 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 19:52:35.184184 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 19:52:35.187049 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 19:52:35.198457 [RTC]rtc_get_frequency_meter,154: input=15, output=835
471 19:52:35.207937 [RTC]rtc_get_frequency_meter,154: input=7, output=710
472 19:52:35.217072 [RTC]rtc_get_frequency_meter,154: input=11, output=773
473 19:52:35.226734 [RTC]rtc_get_frequency_meter,154: input=13, output=803
474 19:52:35.235991 [RTC]rtc_get_frequency_meter,154: input=12, output=789
475 19:52:35.246005 [RTC]rtc_get_frequency_meter,154: input=12, output=788
476 19:52:35.255191 [RTC]rtc_get_frequency_meter,154: input=13, output=805
477 19:52:35.258163 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 19:52:35.265545 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 19:52:35.269563 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 19:52:35.272136 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 19:52:35.278748 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 19:52:35.282100 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 19:52:35.285565 ADC[4]: Raw value=906357 ID=7
484 19:52:35.286032 ADC[3]: Raw value=213282 ID=1
485 19:52:35.288824 RAM Code: 0x71
486 19:52:35.292266 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 19:52:35.298893 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 19:52:35.305414 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 19:52:35.312106 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 19:52:35.315063 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 19:52:35.318823 in-header: 03 07 00 00 08 00 00 00
492 19:52:35.322370 in-data: aa e4 47 04 13 02 00 00
493 19:52:35.325349 Chrome EC: UHEPI supported
494 19:52:35.331718 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 19:52:35.335524 in-header: 03 dd 00 00 08 00 00 00
496 19:52:35.338747 in-data: 90 20 60 08 00 00 00 00
497 19:52:35.341726 MRC: failed to locate region type 0.
498 19:52:35.348152 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 19:52:35.352373 DRAM-K: Running full calibration
500 19:52:35.358673 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 19:52:35.359266 header.status = 0x0
502 19:52:35.361616 header.version = 0x6 (expected: 0x6)
503 19:52:35.365246 header.size = 0xd00 (expected: 0xd00)
504 19:52:35.368401 header.flags = 0x0
505 19:52:35.375198 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 19:52:35.392173 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 19:52:35.398876 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 19:52:35.402320 dram_init: ddr_geometry: 2
509 19:52:35.405470 [EMI] MDL number = 2
510 19:52:35.406047 [EMI] Get MDL freq = 0
511 19:52:35.408496 dram_init: ddr_type: 0
512 19:52:35.408971 is_discrete_lpddr4: 1
513 19:52:35.412342 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 19:52:35.412816
515 19:52:35.414860
516 19:52:35.415330 [Bian_co] ETT version 0.0.0.1
517 19:52:35.422016 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 19:52:35.422598
519 19:52:35.425185 dramc_set_vcore_voltage set vcore to 650000
520 19:52:35.428508 Read voltage for 800, 4
521 19:52:35.429086 Vio18 = 0
522 19:52:35.429468 Vcore = 650000
523 19:52:35.431448 Vdram = 0
524 19:52:35.431946 Vddq = 0
525 19:52:35.432342 Vmddr = 0
526 19:52:35.435063 dram_init: config_dvfs: 1
527 19:52:35.438422 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 19:52:35.444818 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 19:52:35.448088 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 19:52:35.451683 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 19:52:35.455132 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 19:52:35.461318 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 19:52:35.461888 MEM_TYPE=3, freq_sel=18
534 19:52:35.464419 sv_algorithm_assistance_LP4_1600
535 19:52:35.467932 ============ PULL DRAM RESETB DOWN ============
536 19:52:35.474801 ========== PULL DRAM RESETB DOWN end =========
537 19:52:35.477809 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 19:52:35.480815 ===================================
539 19:52:35.484385 LPDDR4 DRAM CONFIGURATION
540 19:52:35.487887 ===================================
541 19:52:35.488424 EX_ROW_EN[0] = 0x0
542 19:52:35.491014 EX_ROW_EN[1] = 0x0
543 19:52:35.494519 LP4Y_EN = 0x0
544 19:52:35.494949 WORK_FSP = 0x0
545 19:52:35.497809 WL = 0x2
546 19:52:35.498342 RL = 0x2
547 19:52:35.500809 BL = 0x2
548 19:52:35.501236 RPST = 0x0
549 19:52:35.504430 RD_PRE = 0x0
550 19:52:35.504969 WR_PRE = 0x1
551 19:52:35.507674 WR_PST = 0x0
552 19:52:35.508240 DBI_WR = 0x0
553 19:52:35.510997 DBI_RD = 0x0
554 19:52:35.511534 OTF = 0x1
555 19:52:35.514419 ===================================
556 19:52:35.518033 ===================================
557 19:52:35.520851 ANA top config
558 19:52:35.524703 ===================================
559 19:52:35.525239 DLL_ASYNC_EN = 0
560 19:52:35.527643 ALL_SLAVE_EN = 1
561 19:52:35.530729 NEW_RANK_MODE = 1
562 19:52:35.533647 DLL_IDLE_MODE = 1
563 19:52:35.537915 LP45_APHY_COMB_EN = 1
564 19:52:35.538345 TX_ODT_DIS = 1
565 19:52:35.540402 NEW_8X_MODE = 1
566 19:52:35.544028 ===================================
567 19:52:35.547282 ===================================
568 19:52:35.550453 data_rate = 1600
569 19:52:35.553975 CKR = 1
570 19:52:35.557210 DQ_P2S_RATIO = 8
571 19:52:35.560243 ===================================
572 19:52:35.563807 CA_P2S_RATIO = 8
573 19:52:35.564236 DQ_CA_OPEN = 0
574 19:52:35.567562 DQ_SEMI_OPEN = 0
575 19:52:35.570112 CA_SEMI_OPEN = 0
576 19:52:35.574290 CA_FULL_RATE = 0
577 19:52:35.577083 DQ_CKDIV4_EN = 1
578 19:52:35.580248 CA_CKDIV4_EN = 1
579 19:52:35.580732 CA_PREDIV_EN = 0
580 19:52:35.583663 PH8_DLY = 0
581 19:52:35.587417 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 19:52:35.590147 DQ_AAMCK_DIV = 4
583 19:52:35.594029 CA_AAMCK_DIV = 4
584 19:52:35.596561 CA_ADMCK_DIV = 4
585 19:52:35.597032 DQ_TRACK_CA_EN = 0
586 19:52:35.599807 CA_PICK = 800
587 19:52:35.603821 CA_MCKIO = 800
588 19:52:35.606594 MCKIO_SEMI = 0
589 19:52:35.610676 PLL_FREQ = 3068
590 19:52:35.613073 DQ_UI_PI_RATIO = 32
591 19:52:35.616669 CA_UI_PI_RATIO = 0
592 19:52:35.620089 ===================================
593 19:52:35.623355 ===================================
594 19:52:35.623974 memory_type:LPDDR4
595 19:52:35.626641 GP_NUM : 10
596 19:52:35.629507 SRAM_EN : 1
597 19:52:35.630121 MD32_EN : 0
598 19:52:35.633013 ===================================
599 19:52:35.636664 [ANA_INIT] >>>>>>>>>>>>>>
600 19:52:35.640247 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 19:52:35.642810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 19:52:35.646493 ===================================
603 19:52:35.649501 data_rate = 1600,PCW = 0X7600
604 19:52:35.652944 ===================================
605 19:52:35.655999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 19:52:35.659776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 19:52:35.666170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 19:52:35.669384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 19:52:35.673214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 19:52:35.676346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 19:52:35.679384 [ANA_INIT] flow start
612 19:52:35.682696 [ANA_INIT] PLL >>>>>>>>
613 19:52:35.683293 [ANA_INIT] PLL <<<<<<<<
614 19:52:35.686217 [ANA_INIT] MIDPI >>>>>>>>
615 19:52:35.689597 [ANA_INIT] MIDPI <<<<<<<<
616 19:52:35.690193 [ANA_INIT] DLL >>>>>>>>
617 19:52:35.692706 [ANA_INIT] flow end
618 19:52:35.695960 ============ LP4 DIFF to SE enter ============
619 19:52:35.703029 ============ LP4 DIFF to SE exit ============
620 19:52:35.703613 [ANA_INIT] <<<<<<<<<<<<<
621 19:52:35.705994 [Flow] Enable top DCM control >>>>>
622 19:52:35.709321 [Flow] Enable top DCM control <<<<<
623 19:52:35.713277 Enable DLL master slave shuffle
624 19:52:35.720022 ==============================================================
625 19:52:35.720675 Gating Mode config
626 19:52:35.725837 ==============================================================
627 19:52:35.729550 Config description:
628 19:52:35.735752 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 19:52:35.742610 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 19:52:35.749364 SELPH_MODE 0: By rank 1: By Phase
631 19:52:35.755716 ==============================================================
632 19:52:35.756204 GAT_TRACK_EN = 1
633 19:52:35.759175 RX_GATING_MODE = 2
634 19:52:35.762397 RX_GATING_TRACK_MODE = 2
635 19:52:35.765543 SELPH_MODE = 1
636 19:52:35.768810 PICG_EARLY_EN = 1
637 19:52:35.772166 VALID_LAT_VALUE = 1
638 19:52:35.778842 ==============================================================
639 19:52:35.782136 Enter into Gating configuration >>>>
640 19:52:35.785588 Exit from Gating configuration <<<<
641 19:52:35.789222 Enter into DVFS_PRE_config >>>>>
642 19:52:35.799322 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 19:52:35.802202 Exit from DVFS_PRE_config <<<<<
644 19:52:35.805796 Enter into PICG configuration >>>>
645 19:52:35.808863 Exit from PICG configuration <<<<
646 19:52:35.811955 [RX_INPUT] configuration >>>>>
647 19:52:35.815199 [RX_INPUT] configuration <<<<<
648 19:52:35.819420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 19:52:35.825623 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 19:52:35.829469 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 19:52:35.837064 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 19:52:35.843657 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 19:52:35.851024 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 19:52:35.854482 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 19:52:35.858429 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 19:52:35.861453 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 19:52:35.864984 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 19:52:35.869018 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 19:52:35.875794 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 19:52:35.876365 ===================================
661 19:52:35.879684 LPDDR4 DRAM CONFIGURATION
662 19:52:35.883360 ===================================
663 19:52:35.887050 EX_ROW_EN[0] = 0x0
664 19:52:35.887656 EX_ROW_EN[1] = 0x0
665 19:52:35.890551 LP4Y_EN = 0x0
666 19:52:35.891154 WORK_FSP = 0x0
667 19:52:35.894305 WL = 0x2
668 19:52:35.894913 RL = 0x2
669 19:52:35.895288 BL = 0x2
670 19:52:35.898534 RPST = 0x0
671 19:52:35.899114 RD_PRE = 0x0
672 19:52:35.901717 WR_PRE = 0x1
673 19:52:35.902318 WR_PST = 0x0
674 19:52:35.905663 DBI_WR = 0x0
675 19:52:35.906321 DBI_RD = 0x0
676 19:52:35.909139 OTF = 0x1
677 19:52:35.912989 ===================================
678 19:52:35.916700 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 19:52:35.920206 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 19:52:35.924005 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 19:52:35.927588 ===================================
682 19:52:35.931164 LPDDR4 DRAM CONFIGURATION
683 19:52:35.931931 ===================================
684 19:52:35.934435 EX_ROW_EN[0] = 0x10
685 19:52:35.938486 EX_ROW_EN[1] = 0x0
686 19:52:35.938976 LP4Y_EN = 0x0
687 19:52:35.941586 WORK_FSP = 0x0
688 19:52:35.942060 WL = 0x2
689 19:52:35.942436 RL = 0x2
690 19:52:35.945296 BL = 0x2
691 19:52:35.945768 RPST = 0x0
692 19:52:35.949365 RD_PRE = 0x0
693 19:52:35.949839 WR_PRE = 0x1
694 19:52:35.953725 WR_PST = 0x0
695 19:52:35.954312 DBI_WR = 0x0
696 19:52:35.956560 DBI_RD = 0x0
697 19:52:35.957051 OTF = 0x1
698 19:52:35.960304 ===================================
699 19:52:35.967254 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 19:52:35.970866 nWR fixed to 40
701 19:52:35.971345 [ModeRegInit_LP4] CH0 RK0
702 19:52:35.974731 [ModeRegInit_LP4] CH0 RK1
703 19:52:35.979264 [ModeRegInit_LP4] CH1 RK0
704 19:52:35.979882 [ModeRegInit_LP4] CH1 RK1
705 19:52:35.982660 match AC timing 13
706 19:52:35.986179 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 19:52:35.989057 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 19:52:35.996160 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 19:52:35.999074 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 19:52:36.002812 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 19:52:36.006013 [EMI DOE] emi_dcm 0
712 19:52:36.009084 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 19:52:36.009661 ==
714 19:52:36.012657 Dram Type= 6, Freq= 0, CH_0, rank 0
715 19:52:36.015506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 19:52:36.018896 ==
717 19:52:36.022469 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 19:52:36.029243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 19:52:36.038020 [CA 0] Center 37 (6~68) winsize 63
720 19:52:36.041652 [CA 1] Center 36 (6~67) winsize 62
721 19:52:36.044890 [CA 2] Center 34 (4~65) winsize 62
722 19:52:36.048183 [CA 3] Center 34 (4~65) winsize 62
723 19:52:36.051632 [CA 4] Center 33 (3~64) winsize 62
724 19:52:36.055435 [CA 5] Center 33 (3~64) winsize 62
725 19:52:36.056051
726 19:52:36.058675 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 19:52:36.059239
728 19:52:36.061598 [CATrainingPosCal] consider 1 rank data
729 19:52:36.065091 u2DelayCellTimex100 = 270/100 ps
730 19:52:36.068123 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 19:52:36.071497 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
732 19:52:36.075209 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 19:52:36.081743 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 19:52:36.085167 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 19:52:36.088368 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 19:52:36.088962
737 19:52:36.091618 CA PerBit enable=1, Macro0, CA PI delay=33
738 19:52:36.092262
739 19:52:36.095264 [CBTSetCACLKResult] CA Dly = 33
740 19:52:36.095904 CS Dly: 6 (0~37)
741 19:52:36.096410 ==
742 19:52:36.098301 Dram Type= 6, Freq= 0, CH_0, rank 1
743 19:52:36.104823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 19:52:36.105422 ==
745 19:52:36.108306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 19:52:36.114330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 19:52:36.124322 [CA 0] Center 36 (6~67) winsize 62
748 19:52:36.128113 [CA 1] Center 37 (7~68) winsize 62
749 19:52:36.131074 [CA 2] Center 34 (4~65) winsize 62
750 19:52:36.134032 [CA 3] Center 34 (4~65) winsize 62
751 19:52:36.137326 [CA 4] Center 33 (3~64) winsize 62
752 19:52:36.140398 [CA 5] Center 33 (2~64) winsize 63
753 19:52:36.140909
754 19:52:36.143959 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 19:52:36.144550
756 19:52:36.147056 [CATrainingPosCal] consider 2 rank data
757 19:52:36.150827 u2DelayCellTimex100 = 270/100 ps
758 19:52:36.154160 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
759 19:52:36.160696 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
760 19:52:36.164168 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 19:52:36.167770 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 19:52:36.171439 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 19:52:36.175288 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 19:52:36.175909
765 19:52:36.179228 CA PerBit enable=1, Macro0, CA PI delay=33
766 19:52:36.179694
767 19:52:36.180112 [CBTSetCACLKResult] CA Dly = 33
768 19:52:36.182168 CS Dly: 6 (0~38)
769 19:52:36.182631
770 19:52:36.185536 ----->DramcWriteLeveling(PI) begin...
771 19:52:36.186007 ==
772 19:52:36.188996 Dram Type= 6, Freq= 0, CH_0, rank 0
773 19:52:36.192253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 19:52:36.192772 ==
775 19:52:36.195657 Write leveling (Byte 0): 31 => 31
776 19:52:36.199200 Write leveling (Byte 1): 29 => 29
777 19:52:36.202974 DramcWriteLeveling(PI) end<-----
778 19:52:36.203494
779 19:52:36.203870 ==
780 19:52:36.206124 Dram Type= 6, Freq= 0, CH_0, rank 0
781 19:52:36.209216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 19:52:36.209738 ==
783 19:52:36.212787 [Gating] SW mode calibration
784 19:52:36.219510 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 19:52:36.225979 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 19:52:36.229904 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 19:52:36.235793 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 19:52:36.239355 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 19:52:36.242354 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 19:52:36.245963 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 19:52:36.252287 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 19:52:36.256007 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 19:52:36.259244 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 19:52:36.265929 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:52:36.269489 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:52:36.272561 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 19:52:36.279292 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 19:52:36.282670 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 19:52:36.285576 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 19:52:36.292456 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 19:52:36.295680 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 19:52:36.299050 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 19:52:36.305452 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 19:52:36.308519 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 19:52:36.312005 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 19:52:36.318538 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 19:52:36.321946 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 19:52:36.325704 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 19:52:36.332316 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 19:52:36.335278 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 19:52:36.338543 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 19:52:36.345168 0 9 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
813 19:52:36.348247 0 9 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
814 19:52:36.351898 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 19:52:36.358496 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 19:52:36.362289 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 19:52:36.365374 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 19:52:36.371822 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 19:52:36.375297 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
820 19:52:36.378780 0 10 8 | B1->B0 | 3333 2a2a | 0 0 | (0 0) (0 0)
821 19:52:36.384975 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
822 19:52:36.388434 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 19:52:36.392127 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 19:52:36.398732 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 19:52:36.402081 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 19:52:36.404732 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 19:52:36.411676 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 19:52:36.414634 0 11 8 | B1->B0 | 2323 3838 | 0 1 | (0 0) (1 1)
829 19:52:36.418064 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
830 19:52:36.421592 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 19:52:36.428531 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 19:52:36.431373 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 19:52:36.435092 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 19:52:36.441712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 19:52:36.445062 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 19:52:36.447909 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 19:52:36.454783 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 19:52:36.458335 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 19:52:36.461826 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 19:52:36.468241 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 19:52:36.472012 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 19:52:36.475679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 19:52:36.479149 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 19:52:36.487365 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 19:52:36.490673 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 19:52:36.494163 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 19:52:36.497391 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 19:52:36.501325 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 19:52:36.508197 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 19:52:36.511700 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 19:52:36.515580 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 19:52:36.519645 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 19:52:36.523427 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 19:52:36.527377 Total UI for P1: 0, mck2ui 16
855 19:52:36.530038 best dqsien dly found for B0: ( 0, 14, 6)
856 19:52:36.533413 Total UI for P1: 0, mck2ui 16
857 19:52:36.536946 best dqsien dly found for B1: ( 0, 14, 10)
858 19:52:36.539891 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 19:52:36.543043 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 19:52:36.543508
861 19:52:36.546548 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 19:52:36.553264 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 19:52:36.553818 [Gating] SW calibration Done
864 19:52:36.554193 ==
865 19:52:36.557299 Dram Type= 6, Freq= 0, CH_0, rank 0
866 19:52:36.564094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 19:52:36.564695 ==
868 19:52:36.565080 RX Vref Scan: 0
869 19:52:36.565427
870 19:52:36.566995 RX Vref 0 -> 0, step: 1
871 19:52:36.567457
872 19:52:36.570415 RX Delay -130 -> 252, step: 16
873 19:52:36.573717 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 19:52:36.578001 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 19:52:36.581235 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 19:52:36.584504 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 19:52:36.587773 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 19:52:36.591653 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 19:52:36.599235 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 19:52:36.602347 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
881 19:52:36.606431 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 19:52:36.609547 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 19:52:36.612737 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 19:52:36.616366 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 19:52:36.622790 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
886 19:52:36.626757 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
887 19:52:36.629466 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 19:52:36.632622 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
889 19:52:36.633191 ==
890 19:52:36.636509 Dram Type= 6, Freq= 0, CH_0, rank 0
891 19:52:36.642403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 19:52:36.643184 ==
893 19:52:36.643585 DQS Delay:
894 19:52:36.644000 DQS0 = 0, DQS1 = 0
895 19:52:36.646174 DQM Delay:
896 19:52:36.646636 DQM0 = 85, DQM1 = 74
897 19:52:36.649379 DQ Delay:
898 19:52:36.652652 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 19:52:36.653138 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
900 19:52:36.655767 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
901 19:52:36.659314 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
902 19:52:36.663262
903 19:52:36.663877
904 19:52:36.664259 ==
905 19:52:36.665818 Dram Type= 6, Freq= 0, CH_0, rank 0
906 19:52:36.669119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 19:52:36.669587 ==
908 19:52:36.669960
909 19:52:36.670300
910 19:52:36.672504 TX Vref Scan disable
911 19:52:36.672973 == TX Byte 0 ==
912 19:52:36.679151 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 19:52:36.682904 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 19:52:36.683466 == TX Byte 1 ==
915 19:52:36.690383 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 19:52:36.693007 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 19:52:36.693572 ==
918 19:52:36.696352 Dram Type= 6, Freq= 0, CH_0, rank 0
919 19:52:36.699385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 19:52:36.699992 ==
921 19:52:36.713406 TX Vref=22, minBit 1, minWin=27, winSum=436
922 19:52:36.716098 TX Vref=24, minBit 13, minWin=26, winSum=438
923 19:52:36.719524 TX Vref=26, minBit 8, minWin=27, winSum=444
924 19:52:36.723799 TX Vref=28, minBit 8, minWin=27, winSum=447
925 19:52:36.726153 TX Vref=30, minBit 8, minWin=27, winSum=444
926 19:52:36.732693 TX Vref=32, minBit 4, minWin=27, winSum=443
927 19:52:36.736233 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 28
928 19:52:36.736698
929 19:52:36.739984 Final TX Range 1 Vref 28
930 19:52:36.740549
931 19:52:36.740925 ==
932 19:52:36.742783 Dram Type= 6, Freq= 0, CH_0, rank 0
933 19:52:36.746266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 19:52:36.746733 ==
935 19:52:36.749548
936 19:52:36.750011
937 19:52:36.750382 TX Vref Scan disable
938 19:52:36.753052 == TX Byte 0 ==
939 19:52:36.755807 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 19:52:36.762734 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 19:52:36.763300 == TX Byte 1 ==
942 19:52:36.765854 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 19:52:36.772924 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 19:52:36.773497
945 19:52:36.773868 [DATLAT]
946 19:52:36.774211 Freq=800, CH0 RK0
947 19:52:36.774537
948 19:52:36.775875 DATLAT Default: 0xa
949 19:52:36.779278 0, 0xFFFF, sum = 0
950 19:52:36.779900 1, 0xFFFF, sum = 0
951 19:52:36.782756 2, 0xFFFF, sum = 0
952 19:52:36.783321 3, 0xFFFF, sum = 0
953 19:52:36.785374 4, 0xFFFF, sum = 0
954 19:52:36.785843 5, 0xFFFF, sum = 0
955 19:52:36.789187 6, 0xFFFF, sum = 0
956 19:52:36.789939 7, 0xFFFF, sum = 0
957 19:52:36.792290 8, 0xFFFF, sum = 0
958 19:52:36.792758 9, 0x0, sum = 1
959 19:52:36.795908 10, 0x0, sum = 2
960 19:52:36.796377 11, 0x0, sum = 3
961 19:52:36.799777 12, 0x0, sum = 4
962 19:52:36.800251 best_step = 10
963 19:52:36.800619
964 19:52:36.800967 ==
965 19:52:36.802382 Dram Type= 6, Freq= 0, CH_0, rank 0
966 19:52:36.805804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 19:52:36.806224 ==
968 19:52:36.808793 RX Vref Scan: 1
969 19:52:36.809319
970 19:52:36.812221 Set Vref Range= 32 -> 127
971 19:52:36.812831
972 19:52:36.813182 RX Vref 32 -> 127, step: 1
973 19:52:36.813586
974 19:52:36.815427 RX Delay -95 -> 252, step: 8
975 19:52:36.815960
976 19:52:36.819036 Set Vref, RX VrefLevel [Byte0]: 32
977 19:52:36.821842 [Byte1]: 32
978 19:52:36.825367
979 19:52:36.825781 Set Vref, RX VrefLevel [Byte0]: 33
980 19:52:36.829188 [Byte1]: 33
981 19:52:36.832764
982 19:52:36.833364 Set Vref, RX VrefLevel [Byte0]: 34
983 19:52:36.836811 [Byte1]: 34
984 19:52:36.840624
985 19:52:36.841049 Set Vref, RX VrefLevel [Byte0]: 35
986 19:52:36.843618 [Byte1]: 35
987 19:52:36.848188
988 19:52:36.848617 Set Vref, RX VrefLevel [Byte0]: 36
989 19:52:36.851285 [Byte1]: 36
990 19:52:36.855948
991 19:52:36.856430 Set Vref, RX VrefLevel [Byte0]: 37
992 19:52:36.859853 [Byte1]: 37
993 19:52:36.863626
994 19:52:36.864228 Set Vref, RX VrefLevel [Byte0]: 38
995 19:52:36.866547 [Byte1]: 38
996 19:52:36.871160
997 19:52:36.871589 Set Vref, RX VrefLevel [Byte0]: 39
998 19:52:36.874318 [Byte1]: 39
999 19:52:36.878627
1000 19:52:36.879054 Set Vref, RX VrefLevel [Byte0]: 40
1001 19:52:36.881710 [Byte1]: 40
1002 19:52:36.886504
1003 19:52:36.886930 Set Vref, RX VrefLevel [Byte0]: 41
1004 19:52:36.889375 [Byte1]: 41
1005 19:52:36.893701
1006 19:52:36.894125 Set Vref, RX VrefLevel [Byte0]: 42
1007 19:52:36.897196 [Byte1]: 42
1008 19:52:36.901127
1009 19:52:36.901552 Set Vref, RX VrefLevel [Byte0]: 43
1010 19:52:36.904854 [Byte1]: 43
1011 19:52:36.908954
1012 19:52:36.909380 Set Vref, RX VrefLevel [Byte0]: 44
1013 19:52:36.912236 [Byte1]: 44
1014 19:52:36.917002
1015 19:52:36.917468 Set Vref, RX VrefLevel [Byte0]: 45
1016 19:52:36.919870 [Byte1]: 45
1017 19:52:36.923916
1018 19:52:36.923998 Set Vref, RX VrefLevel [Byte0]: 46
1019 19:52:36.926929 [Byte1]: 46
1020 19:52:36.931221
1021 19:52:36.931306 Set Vref, RX VrefLevel [Byte0]: 47
1022 19:52:36.934851 [Byte1]: 47
1023 19:52:36.938786
1024 19:52:36.938868 Set Vref, RX VrefLevel [Byte0]: 48
1025 19:52:36.942713 [Byte1]: 48
1026 19:52:36.946716
1027 19:52:36.946799 Set Vref, RX VrefLevel [Byte0]: 49
1028 19:52:36.950006 [Byte1]: 49
1029 19:52:36.954121
1030 19:52:36.954203 Set Vref, RX VrefLevel [Byte0]: 50
1031 19:52:36.957394 [Byte1]: 50
1032 19:52:36.961803
1033 19:52:36.961884 Set Vref, RX VrefLevel [Byte0]: 51
1034 19:52:36.964892 [Byte1]: 51
1035 19:52:36.969768
1036 19:52:36.969849 Set Vref, RX VrefLevel [Byte0]: 52
1037 19:52:36.972990 [Byte1]: 52
1038 19:52:36.977347
1039 19:52:36.977428 Set Vref, RX VrefLevel [Byte0]: 53
1040 19:52:36.980240 [Byte1]: 53
1041 19:52:36.984304
1042 19:52:36.984384 Set Vref, RX VrefLevel [Byte0]: 54
1043 19:52:36.987623 [Byte1]: 54
1044 19:52:36.991894
1045 19:52:36.991974 Set Vref, RX VrefLevel [Byte0]: 55
1046 19:52:36.995404 [Byte1]: 55
1047 19:52:36.999759
1048 19:52:36.999852 Set Vref, RX VrefLevel [Byte0]: 56
1049 19:52:37.003426 [Byte1]: 56
1050 19:52:37.007375
1051 19:52:37.007455 Set Vref, RX VrefLevel [Byte0]: 57
1052 19:52:37.010881 [Byte1]: 57
1053 19:52:37.015349
1054 19:52:37.015430 Set Vref, RX VrefLevel [Byte0]: 58
1055 19:52:37.018198 [Byte1]: 58
1056 19:52:37.022622
1057 19:52:37.022703 Set Vref, RX VrefLevel [Byte0]: 59
1058 19:52:37.026156 [Byte1]: 59
1059 19:52:37.030285
1060 19:52:37.030366 Set Vref, RX VrefLevel [Byte0]: 60
1061 19:52:37.034154 [Byte1]: 60
1062 19:52:37.037798
1063 19:52:37.037878 Set Vref, RX VrefLevel [Byte0]: 61
1064 19:52:37.041352 [Byte1]: 61
1065 19:52:37.045273
1066 19:52:37.045354 Set Vref, RX VrefLevel [Byte0]: 62
1067 19:52:37.049197 [Byte1]: 62
1068 19:52:37.053554
1069 19:52:37.053635 Set Vref, RX VrefLevel [Byte0]: 63
1070 19:52:37.056575 [Byte1]: 63
1071 19:52:37.060516
1072 19:52:37.063773 Set Vref, RX VrefLevel [Byte0]: 64
1073 19:52:37.063854 [Byte1]: 64
1074 19:52:37.068278
1075 19:52:37.068360 Set Vref, RX VrefLevel [Byte0]: 65
1076 19:52:37.071690 [Byte1]: 65
1077 19:52:37.076354
1078 19:52:37.076434 Set Vref, RX VrefLevel [Byte0]: 66
1079 19:52:37.079636 [Byte1]: 66
1080 19:52:37.083602
1081 19:52:37.083683 Set Vref, RX VrefLevel [Byte0]: 67
1082 19:52:37.087111 [Byte1]: 67
1083 19:52:37.090565
1084 19:52:37.094069 Set Vref, RX VrefLevel [Byte0]: 68
1085 19:52:37.094151 [Byte1]: 68
1086 19:52:37.098178
1087 19:52:37.098259 Set Vref, RX VrefLevel [Byte0]: 69
1088 19:52:37.101693 [Byte1]: 69
1089 19:52:37.106173
1090 19:52:37.106253 Set Vref, RX VrefLevel [Byte0]: 70
1091 19:52:37.109235 [Byte1]: 70
1092 19:52:37.113989
1093 19:52:37.114064 Set Vref, RX VrefLevel [Byte0]: 71
1094 19:52:37.116995 [Byte1]: 71
1095 19:52:37.121449
1096 19:52:37.121521 Set Vref, RX VrefLevel [Byte0]: 72
1097 19:52:37.124710 [Byte1]: 72
1098 19:52:37.129255
1099 19:52:37.129328 Set Vref, RX VrefLevel [Byte0]: 73
1100 19:52:37.132747 [Byte1]: 73
1101 19:52:37.136654
1102 19:52:37.136732 Set Vref, RX VrefLevel [Byte0]: 74
1103 19:52:37.140526 [Byte1]: 74
1104 19:52:37.144605
1105 19:52:37.144695 Set Vref, RX VrefLevel [Byte0]: 75
1106 19:52:37.148130 [Byte1]: 75
1107 19:52:37.151975
1108 19:52:37.152055 Set Vref, RX VrefLevel [Byte0]: 76
1109 19:52:37.155005 [Byte1]: 76
1110 19:52:37.159369
1111 19:52:37.159450 Set Vref, RX VrefLevel [Byte0]: 77
1112 19:52:37.162487 [Byte1]: 77
1113 19:52:37.166782
1114 19:52:37.170044 Set Vref, RX VrefLevel [Byte0]: 78
1115 19:52:37.173363 [Byte1]: 78
1116 19:52:37.173445
1117 19:52:37.176572 Set Vref, RX VrefLevel [Byte0]: 79
1118 19:52:37.180060 [Byte1]: 79
1119 19:52:37.180134
1120 19:52:37.183915 Set Vref, RX VrefLevel [Byte0]: 80
1121 19:52:37.187373 [Byte1]: 80
1122 19:52:37.187447
1123 19:52:37.190726 Final RX Vref Byte 0 = 62 to rank0
1124 19:52:37.194646 Final RX Vref Byte 1 = 49 to rank0
1125 19:52:37.197778 Final RX Vref Byte 0 = 62 to rank1
1126 19:52:37.201480 Final RX Vref Byte 1 = 49 to rank1==
1127 19:52:37.205195 Dram Type= 6, Freq= 0, CH_0, rank 0
1128 19:52:37.208351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1129 19:52:37.208427 ==
1130 19:52:37.208496 DQS Delay:
1131 19:52:37.212254 DQS0 = 0, DQS1 = 0
1132 19:52:37.212328 DQM Delay:
1133 19:52:37.216261 DQM0 = 87, DQM1 = 76
1134 19:52:37.216360 DQ Delay:
1135 19:52:37.219586 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1136 19:52:37.223072 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1137 19:52:37.223156 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1138 19:52:37.226829 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1139 19:52:37.226906
1140 19:52:37.226967
1141 19:52:37.237287 [DQSOSCAuto] RK0, (LSB)MR18= 0x4223, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1142 19:52:37.237364 CH0 RK0: MR19=606, MR18=4223
1143 19:52:37.245003 CH0_RK0: MR19=0x606, MR18=0x4223, DQSOSC=393, MR23=63, INC=95, DEC=63
1144 19:52:37.245103
1145 19:52:37.248144 ----->DramcWriteLeveling(PI) begin...
1146 19:52:37.248216 ==
1147 19:52:37.251583 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 19:52:37.255637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 19:52:37.255783 ==
1150 19:52:37.259050 Write leveling (Byte 0): 32 => 32
1151 19:52:37.262627 Write leveling (Byte 1): 32 => 32
1152 19:52:37.266287 DramcWriteLeveling(PI) end<-----
1153 19:52:37.266369
1154 19:52:37.266433 ==
1155 19:52:37.270432 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 19:52:37.274031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 19:52:37.274104 ==
1158 19:52:37.277806 [Gating] SW mode calibration
1159 19:52:37.285279 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1160 19:52:37.329356 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1161 19:52:37.329994 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1162 19:52:37.330067 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1163 19:52:37.330312 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1164 19:52:37.330568 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1165 19:52:37.330823 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 19:52:37.331139 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 19:52:37.331205 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 19:52:37.331520 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 19:52:37.332015 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 19:52:37.373175 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 19:52:37.373302 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 19:52:37.373369 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 19:52:37.373614 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 19:52:37.373862 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 19:52:37.374432 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 19:52:37.374682 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 19:52:37.374782 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 19:52:37.374851 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1179 19:52:37.375092 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1180 19:52:37.417304 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 19:52:37.417575 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 19:52:37.417646 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 19:52:37.417708 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 19:52:37.418061 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 19:52:37.418573 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 19:52:37.419114 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 19:52:37.419178 0 9 8 | B1->B0 | 2323 2d2d | 1 0 | (1 1) (0 0)
1188 19:52:37.419580 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 19:52:37.419863 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 19:52:37.422538 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 19:52:37.425773 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 19:52:37.429123 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 19:52:37.433067 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 19:52:37.436907 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1195 19:52:37.443532 0 10 8 | B1->B0 | 3030 2727 | 1 0 | (1 1) (0 0)
1196 19:52:37.447633 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 19:52:37.451104 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 19:52:37.455037 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 19:52:37.458490 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 19:52:37.466712 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 19:52:37.469342 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 19:52:37.473067 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1203 19:52:37.476869 0 11 8 | B1->B0 | 2e2e 3838 | 1 0 | (0 0) (0 0)
1204 19:52:37.480778 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1205 19:52:37.488121 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 19:52:37.491430 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 19:52:37.495273 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 19:52:37.499291 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 19:52:37.505407 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 19:52:37.508520 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 19:52:37.512029 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1212 19:52:37.515433 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 19:52:37.522593 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 19:52:37.525625 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 19:52:37.528642 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 19:52:37.535228 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 19:52:37.538312 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 19:52:37.541687 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 19:52:37.548601 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 19:52:37.552058 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 19:52:37.554898 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 19:52:37.561902 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 19:52:37.565040 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 19:52:37.568213 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 19:52:37.575018 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 19:52:37.578240 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 19:52:37.581321 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1228 19:52:37.588074 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 19:52:37.591371 Total UI for P1: 0, mck2ui 16
1230 19:52:37.594962 best dqsien dly found for B0: ( 0, 14, 8)
1231 19:52:37.595043 Total UI for P1: 0, mck2ui 16
1232 19:52:37.601674 best dqsien dly found for B1: ( 0, 14, 10)
1233 19:52:37.605065 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1234 19:52:37.608041 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1235 19:52:37.608121
1236 19:52:37.611413 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1237 19:52:37.614696 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1238 19:52:37.618065 [Gating] SW calibration Done
1239 19:52:37.618145 ==
1240 19:52:37.621485 Dram Type= 6, Freq= 0, CH_0, rank 1
1241 19:52:37.624871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1242 19:52:37.624951 ==
1243 19:52:37.628007 RX Vref Scan: 0
1244 19:52:37.628087
1245 19:52:37.628151 RX Vref 0 -> 0, step: 1
1246 19:52:37.628211
1247 19:52:37.631456 RX Delay -130 -> 252, step: 16
1248 19:52:37.638176 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1249 19:52:37.641579 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1250 19:52:37.644618 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1251 19:52:37.647958 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1252 19:52:37.651020 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1253 19:52:37.657929 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1254 19:52:37.661349 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1255 19:52:37.664766 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1256 19:52:37.667449 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1257 19:52:37.671195 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1258 19:52:37.678052 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1259 19:52:37.681549 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1260 19:52:37.684468 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1261 19:52:37.687468 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1262 19:52:37.690773 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1263 19:52:37.697326 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1264 19:52:37.697396 ==
1265 19:52:37.700889 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 19:52:37.704326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 19:52:37.704396 ==
1268 19:52:37.704456 DQS Delay:
1269 19:52:37.707232 DQS0 = 0, DQS1 = 0
1270 19:52:37.707303 DQM Delay:
1271 19:52:37.710291 DQM0 = 83, DQM1 = 77
1272 19:52:37.710392 DQ Delay:
1273 19:52:37.713645 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1274 19:52:37.717530 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1275 19:52:37.720260 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1276 19:52:37.724242 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1277 19:52:37.724314
1278 19:52:37.724375
1279 19:52:37.724439 ==
1280 19:52:37.726727 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 19:52:37.730367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 19:52:37.734020 ==
1283 19:52:37.734102
1284 19:52:37.734165
1285 19:52:37.734223 TX Vref Scan disable
1286 19:52:37.737100 == TX Byte 0 ==
1287 19:52:37.740440 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1288 19:52:37.743400 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1289 19:52:37.747048 == TX Byte 1 ==
1290 19:52:37.750358 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1291 19:52:37.757061 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1292 19:52:37.757141 ==
1293 19:52:37.760312 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 19:52:37.763485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 19:52:37.763560 ==
1296 19:52:37.775705 TX Vref=22, minBit 8, minWin=27, winSum=445
1297 19:52:37.779326 TX Vref=24, minBit 13, minWin=27, winSum=447
1298 19:52:37.782526 TX Vref=26, minBit 12, minWin=27, winSum=449
1299 19:52:37.785631 TX Vref=28, minBit 9, minWin=27, winSum=447
1300 19:52:37.789174 TX Vref=30, minBit 9, minWin=27, winSum=447
1301 19:52:37.796004 TX Vref=32, minBit 4, minWin=27, winSum=445
1302 19:52:37.799079 [TxChooseVref] Worse bit 12, Min win 27, Win sum 449, Final Vref 26
1303 19:52:37.799146
1304 19:52:37.802173 Final TX Range 1 Vref 26
1305 19:52:37.802240
1306 19:52:37.802299 ==
1307 19:52:37.805502 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 19:52:37.808763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 19:52:37.812360 ==
1310 19:52:37.812428
1311 19:52:37.812487
1312 19:52:37.812542 TX Vref Scan disable
1313 19:52:37.815650 == TX Byte 0 ==
1314 19:52:37.819004 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1315 19:52:37.825693 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1316 19:52:37.825766 == TX Byte 1 ==
1317 19:52:37.829334 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1318 19:52:37.835507 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1319 19:52:37.835581
1320 19:52:37.835642 [DATLAT]
1321 19:52:37.835708 Freq=800, CH0 RK1
1322 19:52:37.835809
1323 19:52:37.839352 DATLAT Default: 0xa
1324 19:52:37.839426 0, 0xFFFF, sum = 0
1325 19:52:37.842649 1, 0xFFFF, sum = 0
1326 19:52:37.842718 2, 0xFFFF, sum = 0
1327 19:52:37.846186 3, 0xFFFF, sum = 0
1328 19:52:37.849094 4, 0xFFFF, sum = 0
1329 19:52:37.849169 5, 0xFFFF, sum = 0
1330 19:52:37.852236 6, 0xFFFF, sum = 0
1331 19:52:37.852315 7, 0xFFFF, sum = 0
1332 19:52:37.855803 8, 0xFFFF, sum = 0
1333 19:52:37.855878 9, 0x0, sum = 1
1334 19:52:37.858955 10, 0x0, sum = 2
1335 19:52:37.859020 11, 0x0, sum = 3
1336 19:52:37.859088 12, 0x0, sum = 4
1337 19:52:37.862364 best_step = 10
1338 19:52:37.862431
1339 19:52:37.862489 ==
1340 19:52:37.865672 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 19:52:37.868844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 19:52:37.868916 ==
1343 19:52:37.872335 RX Vref Scan: 0
1344 19:52:37.872402
1345 19:52:37.872461 RX Vref 0 -> 0, step: 1
1346 19:52:37.875706
1347 19:52:37.875817 RX Delay -111 -> 252, step: 8
1348 19:52:37.882709 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1349 19:52:37.885781 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1350 19:52:37.889608 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1351 19:52:37.892492 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1352 19:52:37.898906 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1353 19:52:37.902254 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1354 19:52:37.905701 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1355 19:52:37.909177 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1356 19:52:37.912180 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1357 19:52:37.919196 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1358 19:52:37.922307 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1359 19:52:37.925657 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1360 19:52:37.928768 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1361 19:52:37.932117 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1362 19:52:37.938588 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1363 19:52:37.941925 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1364 19:52:37.942005 ==
1365 19:52:37.945151 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 19:52:37.948864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 19:52:37.948950 ==
1368 19:52:37.952239 DQS Delay:
1369 19:52:37.952319 DQS0 = 0, DQS1 = 0
1370 19:52:37.952382 DQM Delay:
1371 19:52:37.955630 DQM0 = 85, DQM1 = 76
1372 19:52:37.955778 DQ Delay:
1373 19:52:37.959378 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1374 19:52:37.961914 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1375 19:52:37.965177 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1376 19:52:37.968673 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1377 19:52:37.968745
1378 19:52:37.968805
1379 19:52:37.978774 [DQSOSCAuto] RK1, (LSB)MR18= 0x460d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
1380 19:52:37.981950 CH0 RK1: MR19=606, MR18=460D
1381 19:52:37.985291 CH0_RK1: MR19=0x606, MR18=0x460D, DQSOSC=392, MR23=63, INC=96, DEC=64
1382 19:52:37.988182 [RxdqsGatingPostProcess] freq 800
1383 19:52:37.995087 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1384 19:52:37.998289 Pre-setting of DQS Precalculation
1385 19:52:38.001631 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1386 19:52:38.001704 ==
1387 19:52:38.004786 Dram Type= 6, Freq= 0, CH_1, rank 0
1388 19:52:38.011500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 19:52:38.011575 ==
1390 19:52:38.014657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1391 19:52:38.021278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1392 19:52:38.030925 [CA 0] Center 36 (6~67) winsize 62
1393 19:52:38.034508 [CA 1] Center 36 (6~67) winsize 62
1394 19:52:38.037738 [CA 2] Center 34 (4~65) winsize 62
1395 19:52:38.041011 [CA 3] Center 34 (3~65) winsize 63
1396 19:52:38.044133 [CA 4] Center 34 (4~65) winsize 62
1397 19:52:38.048002 [CA 5] Center 34 (3~65) winsize 63
1398 19:52:38.048083
1399 19:52:38.051186 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1400 19:52:38.051261
1401 19:52:38.054128 [CATrainingPosCal] consider 1 rank data
1402 19:52:38.057842 u2DelayCellTimex100 = 270/100 ps
1403 19:52:38.061339 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1404 19:52:38.064466 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1405 19:52:38.070856 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1406 19:52:38.074427 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1407 19:52:38.077644 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1408 19:52:38.081222 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1409 19:52:38.081292
1410 19:52:38.084616 CA PerBit enable=1, Macro0, CA PI delay=34
1411 19:52:38.084685
1412 19:52:38.087459 [CBTSetCACLKResult] CA Dly = 34
1413 19:52:38.087526 CS Dly: 5 (0~36)
1414 19:52:38.090498 ==
1415 19:52:38.090566 Dram Type= 6, Freq= 0, CH_1, rank 1
1416 19:52:38.097614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 19:52:38.097693 ==
1418 19:52:38.100826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1419 19:52:38.107303 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1420 19:52:38.117187 [CA 0] Center 36 (6~67) winsize 62
1421 19:52:38.120222 [CA 1] Center 37 (6~68) winsize 63
1422 19:52:38.123621 [CA 2] Center 34 (4~65) winsize 62
1423 19:52:38.127377 [CA 3] Center 34 (3~65) winsize 63
1424 19:52:38.130490 [CA 4] Center 34 (4~65) winsize 62
1425 19:52:38.133611 [CA 5] Center 33 (3~64) winsize 62
1426 19:52:38.133684
1427 19:52:38.137097 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1428 19:52:38.137192
1429 19:52:38.140221 [CATrainingPosCal] consider 2 rank data
1430 19:52:38.143484 u2DelayCellTimex100 = 270/100 ps
1431 19:52:38.146755 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1432 19:52:38.150343 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1433 19:52:38.157033 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1434 19:52:38.160072 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1435 19:52:38.163305 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1436 19:52:38.166856 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1437 19:52:38.166927
1438 19:52:38.169950 CA PerBit enable=1, Macro0, CA PI delay=33
1439 19:52:38.170023
1440 19:52:38.173215 [CBTSetCACLKResult] CA Dly = 33
1441 19:52:38.173285 CS Dly: 5 (0~37)
1442 19:52:38.177289
1443 19:52:38.179869 ----->DramcWriteLeveling(PI) begin...
1444 19:52:38.179951 ==
1445 19:52:38.183438 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 19:52:38.186785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 19:52:38.186863 ==
1448 19:52:38.189674 Write leveling (Byte 0): 27 => 27
1449 19:52:38.193393 Write leveling (Byte 1): 28 => 28
1450 19:52:38.196390 DramcWriteLeveling(PI) end<-----
1451 19:52:38.196459
1452 19:52:38.196518 ==
1453 19:52:38.199798 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 19:52:38.203246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 19:52:38.203315 ==
1456 19:52:38.206632 [Gating] SW mode calibration
1457 19:52:38.213524 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1458 19:52:38.219501 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1459 19:52:38.223084 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1460 19:52:38.226336 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1461 19:52:38.232793 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1462 19:52:38.236029 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 19:52:38.239307 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 19:52:38.245771 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 19:52:38.249063 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 19:52:38.252564 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 19:52:38.259397 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 19:52:38.262532 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 19:52:38.265842 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 19:52:38.272652 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 19:52:38.275737 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 19:52:38.278859 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 19:52:38.285531 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 19:52:38.288872 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 19:52:38.292262 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1476 19:52:38.298785 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1477 19:52:38.302645 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1478 19:52:38.305692 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 19:52:38.312160 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 19:52:38.315378 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 19:52:38.318736 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 19:52:38.325500 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 19:52:38.328537 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 19:52:38.331979 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 19:52:38.338608 0 9 8 | B1->B0 | 3131 2f2f | 1 0 | (1 1) (0 0)
1486 19:52:38.341831 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 19:52:38.345062 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 19:52:38.351882 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 19:52:38.355331 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 19:52:38.358959 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 19:52:38.365002 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1492 19:52:38.368620 0 10 4 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 1)
1493 19:52:38.371475 0 10 8 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (0 0)
1494 19:52:38.378405 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 19:52:38.381375 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 19:52:38.384804 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 19:52:38.388490 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 19:52:38.394722 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 19:52:38.398350 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 19:52:38.401399 0 11 4 | B1->B0 | 2727 2b2b | 1 0 | (0 0) (0 0)
1501 19:52:38.408070 0 11 8 | B1->B0 | 3939 4444 | 1 1 | (0 0) (0 0)
1502 19:52:38.411386 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 19:52:38.414898 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 19:52:38.421723 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 19:52:38.425634 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 19:52:38.427894 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 19:52:38.434862 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1508 19:52:38.437891 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1509 19:52:38.441527 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 19:52:38.447797 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 19:52:38.451072 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 19:52:38.454609 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 19:52:38.461424 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 19:52:38.464508 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 19:52:38.468035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 19:52:38.474273 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 19:52:38.477468 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 19:52:38.480916 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 19:52:38.487518 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 19:52:38.490927 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 19:52:38.493886 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 19:52:38.500774 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 19:52:38.503938 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 19:52:38.507604 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1525 19:52:38.514214 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 19:52:38.514294 Total UI for P1: 0, mck2ui 16
1527 19:52:38.521353 best dqsien dly found for B0: ( 0, 14, 4)
1528 19:52:38.521432 Total UI for P1: 0, mck2ui 16
1529 19:52:38.527167 best dqsien dly found for B1: ( 0, 14, 6)
1530 19:52:38.530572 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1531 19:52:38.534080 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1532 19:52:38.534160
1533 19:52:38.537474 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1534 19:52:38.540744 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1535 19:52:38.544287 [Gating] SW calibration Done
1536 19:52:38.544366 ==
1537 19:52:38.547357 Dram Type= 6, Freq= 0, CH_1, rank 0
1538 19:52:38.550573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1539 19:52:38.550654 ==
1540 19:52:38.553899 RX Vref Scan: 0
1541 19:52:38.553979
1542 19:52:38.554042 RX Vref 0 -> 0, step: 1
1543 19:52:38.554101
1544 19:52:38.557205 RX Delay -130 -> 252, step: 16
1545 19:52:38.560771 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1546 19:52:38.567232 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1547 19:52:38.570482 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1548 19:52:38.574136 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1549 19:52:38.577018 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1550 19:52:38.580464 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1551 19:52:38.587127 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1552 19:52:38.590021 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1553 19:52:38.593539 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1554 19:52:38.597035 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1555 19:52:38.600439 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1556 19:52:38.606738 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1557 19:52:38.610160 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1558 19:52:38.613596 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1559 19:52:38.616624 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1560 19:52:38.623281 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1561 19:52:38.623361 ==
1562 19:52:38.626687 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 19:52:38.630157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 19:52:38.630238 ==
1565 19:52:38.630301 DQS Delay:
1566 19:52:38.633436 DQS0 = 0, DQS1 = 0
1567 19:52:38.633516 DQM Delay:
1568 19:52:38.636576 DQM0 = 89, DQM1 = 78
1569 19:52:38.636655 DQ Delay:
1570 19:52:38.639647 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1571 19:52:38.644051 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1572 19:52:38.646591 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1573 19:52:38.649549 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1574 19:52:38.649626
1575 19:52:38.649688
1576 19:52:38.649745 ==
1577 19:52:38.653402 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 19:52:38.656421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 19:52:38.659993 ==
1580 19:52:38.660066
1581 19:52:38.660128
1582 19:52:38.660186 TX Vref Scan disable
1583 19:52:38.663258 == TX Byte 0 ==
1584 19:52:38.666629 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1585 19:52:38.669490 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1586 19:52:38.672926 == TX Byte 1 ==
1587 19:52:38.676670 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1588 19:52:38.679419 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1589 19:52:38.683096 ==
1590 19:52:38.683167 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 19:52:38.689238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 19:52:38.689316 ==
1593 19:52:38.701656 TX Vref=22, minBit 10, minWin=26, winSum=442
1594 19:52:38.705172 TX Vref=24, minBit 10, minWin=27, winSum=450
1595 19:52:38.708300 TX Vref=26, minBit 9, minWin=27, winSum=452
1596 19:52:38.711396 TX Vref=28, minBit 15, minWin=27, winSum=452
1597 19:52:38.715339 TX Vref=30, minBit 11, minWin=27, winSum=451
1598 19:52:38.721441 TX Vref=32, minBit 0, minWin=27, winSum=446
1599 19:52:38.724682 [TxChooseVref] Worse bit 9, Min win 27, Win sum 452, Final Vref 26
1600 19:52:38.724759
1601 19:52:38.728329 Final TX Range 1 Vref 26
1602 19:52:38.728436
1603 19:52:38.728513 ==
1604 19:52:38.731786 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 19:52:38.735334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 19:52:38.738025 ==
1607 19:52:38.738099
1608 19:52:38.738161
1609 19:52:38.738225 TX Vref Scan disable
1610 19:52:38.742125 == TX Byte 0 ==
1611 19:52:38.745371 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1612 19:52:38.751884 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1613 19:52:38.751966 == TX Byte 1 ==
1614 19:52:38.755304 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1615 19:52:38.761884 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1616 19:52:38.761956
1617 19:52:38.762018 [DATLAT]
1618 19:52:38.762075 Freq=800, CH1 RK0
1619 19:52:38.762132
1620 19:52:38.765212 DATLAT Default: 0xa
1621 19:52:38.765279 0, 0xFFFF, sum = 0
1622 19:52:38.768545 1, 0xFFFF, sum = 0
1623 19:52:38.768619 2, 0xFFFF, sum = 0
1624 19:52:38.771653 3, 0xFFFF, sum = 0
1625 19:52:38.775019 4, 0xFFFF, sum = 0
1626 19:52:38.775125 5, 0xFFFF, sum = 0
1627 19:52:38.778669 6, 0xFFFF, sum = 0
1628 19:52:38.778739 7, 0xFFFF, sum = 0
1629 19:52:38.781609 8, 0xFFFF, sum = 0
1630 19:52:38.781683 9, 0x0, sum = 1
1631 19:52:38.784861 10, 0x0, sum = 2
1632 19:52:38.784935 11, 0x0, sum = 3
1633 19:52:38.784995 12, 0x0, sum = 4
1634 19:52:38.788669 best_step = 10
1635 19:52:38.788740
1636 19:52:38.788800 ==
1637 19:52:38.791750 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 19:52:38.794813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 19:52:38.794880 ==
1640 19:52:38.798152 RX Vref Scan: 1
1641 19:52:38.798219
1642 19:52:38.801888 Set Vref Range= 32 -> 127
1643 19:52:38.801955
1644 19:52:38.802013 RX Vref 32 -> 127, step: 1
1645 19:52:38.802069
1646 19:52:38.805030 RX Delay -95 -> 252, step: 8
1647 19:52:38.805095
1648 19:52:38.808426 Set Vref, RX VrefLevel [Byte0]: 32
1649 19:52:38.811405 [Byte1]: 32
1650 19:52:38.814917
1651 19:52:38.814993 Set Vref, RX VrefLevel [Byte0]: 33
1652 19:52:38.817835 [Byte1]: 33
1653 19:52:38.822260
1654 19:52:38.822329 Set Vref, RX VrefLevel [Byte0]: 34
1655 19:52:38.825624 [Byte1]: 34
1656 19:52:38.829627
1657 19:52:38.829695 Set Vref, RX VrefLevel [Byte0]: 35
1658 19:52:38.833003 [Byte1]: 35
1659 19:52:38.837245
1660 19:52:38.837313 Set Vref, RX VrefLevel [Byte0]: 36
1661 19:52:38.840498 [Byte1]: 36
1662 19:52:38.844661
1663 19:52:38.847818 Set Vref, RX VrefLevel [Byte0]: 37
1664 19:52:38.851163 [Byte1]: 37
1665 19:52:38.851238
1666 19:52:38.854443 Set Vref, RX VrefLevel [Byte0]: 38
1667 19:52:38.858055 [Byte1]: 38
1668 19:52:38.858128
1669 19:52:38.861380 Set Vref, RX VrefLevel [Byte0]: 39
1670 19:52:38.864733 [Byte1]: 39
1671 19:52:38.867967
1672 19:52:38.868041 Set Vref, RX VrefLevel [Byte0]: 40
1673 19:52:38.871427 [Byte1]: 40
1674 19:52:38.875434
1675 19:52:38.875531 Set Vref, RX VrefLevel [Byte0]: 41
1676 19:52:38.882249 [Byte1]: 41
1677 19:52:38.882321
1678 19:52:38.885095 Set Vref, RX VrefLevel [Byte0]: 42
1679 19:52:38.888278 [Byte1]: 42
1680 19:52:38.888346
1681 19:52:38.892153 Set Vref, RX VrefLevel [Byte0]: 43
1682 19:52:38.895056 [Byte1]: 43
1683 19:52:38.895130
1684 19:52:38.898882 Set Vref, RX VrefLevel [Byte0]: 44
1685 19:52:38.901837 [Byte1]: 44
1686 19:52:38.905746
1687 19:52:38.905822 Set Vref, RX VrefLevel [Byte0]: 45
1688 19:52:38.908796 [Byte1]: 45
1689 19:52:38.913492
1690 19:52:38.913561 Set Vref, RX VrefLevel [Byte0]: 46
1691 19:52:38.916629 [Byte1]: 46
1692 19:52:38.921477
1693 19:52:38.921548 Set Vref, RX VrefLevel [Byte0]: 47
1694 19:52:38.924373 [Byte1]: 47
1695 19:52:38.928458
1696 19:52:38.928526 Set Vref, RX VrefLevel [Byte0]: 48
1697 19:52:38.931663 [Byte1]: 48
1698 19:52:38.936631
1699 19:52:38.936704 Set Vref, RX VrefLevel [Byte0]: 49
1700 19:52:38.939398 [Byte1]: 49
1701 19:52:38.943916
1702 19:52:38.943983 Set Vref, RX VrefLevel [Byte0]: 50
1703 19:52:38.947190 [Byte1]: 50
1704 19:52:38.951204
1705 19:52:38.951277 Set Vref, RX VrefLevel [Byte0]: 51
1706 19:52:38.954662 [Byte1]: 51
1707 19:52:38.958790
1708 19:52:38.958866 Set Vref, RX VrefLevel [Byte0]: 52
1709 19:52:38.962706 [Byte1]: 52
1710 19:52:38.966578
1711 19:52:38.966654 Set Vref, RX VrefLevel [Byte0]: 53
1712 19:52:38.969484 [Byte1]: 53
1713 19:52:38.974158
1714 19:52:38.974263 Set Vref, RX VrefLevel [Byte0]: 54
1715 19:52:38.977875 [Byte1]: 54
1716 19:52:38.981767
1717 19:52:38.981847 Set Vref, RX VrefLevel [Byte0]: 55
1718 19:52:38.985088 [Byte1]: 55
1719 19:52:38.989056
1720 19:52:38.989140 Set Vref, RX VrefLevel [Byte0]: 56
1721 19:52:38.992566 [Byte1]: 56
1722 19:52:38.997465
1723 19:52:38.997545 Set Vref, RX VrefLevel [Byte0]: 57
1724 19:52:39.000097 [Byte1]: 57
1725 19:52:39.004679
1726 19:52:39.004760 Set Vref, RX VrefLevel [Byte0]: 58
1727 19:52:39.007584 [Byte1]: 58
1728 19:52:39.012288
1729 19:52:39.012367 Set Vref, RX VrefLevel [Byte0]: 59
1730 19:52:39.015360 [Byte1]: 59
1731 19:52:39.019760
1732 19:52:39.019854 Set Vref, RX VrefLevel [Byte0]: 60
1733 19:52:39.023039 [Byte1]: 60
1734 19:52:39.027269
1735 19:52:39.027399 Set Vref, RX VrefLevel [Byte0]: 61
1736 19:52:39.030652 [Byte1]: 61
1737 19:52:39.034767
1738 19:52:39.034841 Set Vref, RX VrefLevel [Byte0]: 62
1739 19:52:39.038485 [Byte1]: 62
1740 19:52:39.042761
1741 19:52:39.042839 Set Vref, RX VrefLevel [Byte0]: 63
1742 19:52:39.046163 [Byte1]: 63
1743 19:52:39.049948
1744 19:52:39.050028 Set Vref, RX VrefLevel [Byte0]: 64
1745 19:52:39.053515 [Byte1]: 64
1746 19:52:39.057865
1747 19:52:39.057941 Set Vref, RX VrefLevel [Byte0]: 65
1748 19:52:39.060955 [Byte1]: 65
1749 19:52:39.064982
1750 19:52:39.065053 Set Vref, RX VrefLevel [Byte0]: 66
1751 19:52:39.068534 [Byte1]: 66
1752 19:52:39.072893
1753 19:52:39.072999 Set Vref, RX VrefLevel [Byte0]: 67
1754 19:52:39.079180 [Byte1]: 67
1755 19:52:39.079260
1756 19:52:39.082689 Set Vref, RX VrefLevel [Byte0]: 68
1757 19:52:39.086257 [Byte1]: 68
1758 19:52:39.086337
1759 19:52:39.089399 Set Vref, RX VrefLevel [Byte0]: 69
1760 19:52:39.092462 [Byte1]: 69
1761 19:52:39.092545
1762 19:52:39.096108 Set Vref, RX VrefLevel [Byte0]: 70
1763 19:52:39.099193 [Byte1]: 70
1764 19:52:39.103350
1765 19:52:39.103429 Set Vref, RX VrefLevel [Byte0]: 71
1766 19:52:39.106709 [Byte1]: 71
1767 19:52:39.110571
1768 19:52:39.110677 Set Vref, RX VrefLevel [Byte0]: 72
1769 19:52:39.114201 [Byte1]: 72
1770 19:52:39.118706
1771 19:52:39.118786 Set Vref, RX VrefLevel [Byte0]: 73
1772 19:52:39.121533 [Byte1]: 73
1773 19:52:39.126096
1774 19:52:39.126175 Set Vref, RX VrefLevel [Byte0]: 74
1775 19:52:39.129414 [Byte1]: 74
1776 19:52:39.133763
1777 19:52:39.133842 Set Vref, RX VrefLevel [Byte0]: 75
1778 19:52:39.137015 [Byte1]: 75
1779 19:52:39.141828
1780 19:52:39.141908 Final RX Vref Byte 0 = 55 to rank0
1781 19:52:39.144322 Final RX Vref Byte 1 = 62 to rank0
1782 19:52:39.147648 Final RX Vref Byte 0 = 55 to rank1
1783 19:52:39.151293 Final RX Vref Byte 1 = 62 to rank1==
1784 19:52:39.154258 Dram Type= 6, Freq= 0, CH_1, rank 0
1785 19:52:39.161126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 19:52:39.161207 ==
1787 19:52:39.161272 DQS Delay:
1788 19:52:39.164834 DQS0 = 0, DQS1 = 0
1789 19:52:39.164913 DQM Delay:
1790 19:52:39.164977 DQM0 = 86, DQM1 = 80
1791 19:52:39.167669 DQ Delay:
1792 19:52:39.171267 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1793 19:52:39.174016 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1794 19:52:39.177913 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1795 19:52:39.180519 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =92
1796 19:52:39.180599
1797 19:52:39.180663
1798 19:52:39.187628 [DQSOSCAuto] RK0, (LSB)MR18= 0x321e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1799 19:52:39.190950 CH1 RK0: MR19=606, MR18=321E
1800 19:52:39.197519 CH1_RK0: MR19=0x606, MR18=0x321E, DQSOSC=397, MR23=63, INC=93, DEC=62
1801 19:52:39.197600
1802 19:52:39.200685 ----->DramcWriteLeveling(PI) begin...
1803 19:52:39.200766 ==
1804 19:52:39.203641 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 19:52:39.207380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 19:52:39.207460 ==
1807 19:52:39.210948 Write leveling (Byte 0): 28 => 28
1808 19:52:39.214199 Write leveling (Byte 1): 30 => 30
1809 19:52:39.217134 DramcWriteLeveling(PI) end<-----
1810 19:52:39.217214
1811 19:52:39.217276 ==
1812 19:52:39.220976 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 19:52:39.224102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 19:52:39.227221 ==
1815 19:52:39.227301 [Gating] SW mode calibration
1816 19:52:39.233589 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1817 19:52:39.240246 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1818 19:52:39.243852 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1819 19:52:39.250361 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1820 19:52:39.253648 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1821 19:52:39.257133 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 19:52:39.263405 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 19:52:39.266790 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 19:52:39.269958 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 19:52:39.276938 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 19:52:39.279727 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 19:52:39.283192 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 19:52:39.289955 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 19:52:39.294102 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 19:52:39.296387 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 19:52:39.303362 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 19:52:39.306448 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 19:52:39.309955 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 19:52:39.316335 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 19:52:39.319926 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1836 19:52:39.323200 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1837 19:52:39.330139 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 19:52:39.333545 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 19:52:39.336407 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 19:52:39.343198 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 19:52:39.346307 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 19:52:39.349642 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 19:52:39.356208 0 9 4 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1844 19:52:39.359763 0 9 8 | B1->B0 | 3333 2c2c | 1 0 | (1 1) (0 0)
1845 19:52:39.362769 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 19:52:39.365782 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 19:52:39.372921 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 19:52:39.376017 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 19:52:39.379470 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 19:52:39.385744 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 19:52:39.389248 0 10 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1852 19:52:39.392724 0 10 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1853 19:52:39.399051 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 19:52:39.402259 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 19:52:39.405632 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 19:52:39.412281 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 19:52:39.415717 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 19:52:39.418713 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 19:52:39.425512 0 11 4 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
1860 19:52:39.428890 0 11 8 | B1->B0 | 3d3d 3434 | 0 0 | (0 0) (0 0)
1861 19:52:39.432814 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 19:52:39.439149 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 19:52:39.442182 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 19:52:39.445618 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 19:52:39.452393 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 19:52:39.455677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 19:52:39.458940 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 19:52:39.465373 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1869 19:52:39.468813 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 19:52:39.472681 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 19:52:39.479117 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 19:52:39.482010 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 19:52:39.485539 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 19:52:39.492066 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 19:52:39.495518 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 19:52:39.498763 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 19:52:39.505863 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 19:52:39.508822 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 19:52:39.512061 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 19:52:39.518589 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 19:52:39.521700 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 19:52:39.525382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 19:52:39.532042 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1884 19:52:39.535115 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1885 19:52:39.538970 Total UI for P1: 0, mck2ui 16
1886 19:52:39.541946 best dqsien dly found for B1: ( 0, 14, 4)
1887 19:52:39.545100 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 19:52:39.548186 Total UI for P1: 0, mck2ui 16
1889 19:52:39.551913 best dqsien dly found for B0: ( 0, 14, 8)
1890 19:52:39.555205 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1891 19:52:39.558597 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1892 19:52:39.558678
1893 19:52:39.561555 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1894 19:52:39.564714 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1895 19:52:39.568116 [Gating] SW calibration Done
1896 19:52:39.568196 ==
1897 19:52:39.571515 Dram Type= 6, Freq= 0, CH_1, rank 1
1898 19:52:39.578707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1899 19:52:39.578789 ==
1900 19:52:39.578854 RX Vref Scan: 0
1901 19:52:39.578914
1902 19:52:39.581679 RX Vref 0 -> 0, step: 1
1903 19:52:39.581759
1904 19:52:39.584768 RX Delay -130 -> 252, step: 16
1905 19:52:39.588224 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1906 19:52:39.591324 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1907 19:52:39.594745 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1908 19:52:39.601250 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1909 19:52:39.604867 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1910 19:52:39.607862 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1911 19:52:39.611235 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1912 19:52:39.614890 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1913 19:52:39.621173 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1914 19:52:39.624761 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1915 19:52:39.627881 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1916 19:52:39.631606 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1917 19:52:39.634940 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1918 19:52:39.641621 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1919 19:52:39.644424 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1920 19:52:39.647892 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1921 19:52:39.647973 ==
1922 19:52:39.651104 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 19:52:39.654525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 19:52:39.657741 ==
1925 19:52:39.657822 DQS Delay:
1926 19:52:39.657887 DQS0 = 0, DQS1 = 0
1927 19:52:39.661017 DQM Delay:
1928 19:52:39.661098 DQM0 = 87, DQM1 = 79
1929 19:52:39.664603 DQ Delay:
1930 19:52:39.664683 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1931 19:52:39.667920 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1932 19:52:39.671028 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1933 19:52:39.674131 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1934 19:52:39.677806
1935 19:52:39.677887
1936 19:52:39.677951 ==
1937 19:52:39.680962 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 19:52:39.684167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 19:52:39.684248 ==
1940 19:52:39.684312
1941 19:52:39.684372
1942 19:52:39.687525 TX Vref Scan disable
1943 19:52:39.687606 == TX Byte 0 ==
1944 19:52:39.694194 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1945 19:52:39.697321 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1946 19:52:39.697402 == TX Byte 1 ==
1947 19:52:39.703759 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1948 19:52:39.707188 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1949 19:52:39.707268 ==
1950 19:52:39.710421 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 19:52:39.714255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 19:52:39.714335 ==
1953 19:52:39.727849 TX Vref=22, minBit 8, minWin=27, winSum=445
1954 19:52:39.731612 TX Vref=24, minBit 8, minWin=27, winSum=446
1955 19:52:39.734785 TX Vref=26, minBit 8, minWin=27, winSum=449
1956 19:52:39.737775 TX Vref=28, minBit 1, minWin=27, winSum=449
1957 19:52:39.741386 TX Vref=30, minBit 15, minWin=27, winSum=450
1958 19:52:39.748178 TX Vref=32, minBit 8, minWin=27, winSum=448
1959 19:52:39.750823 [TxChooseVref] Worse bit 15, Min win 27, Win sum 450, Final Vref 30
1960 19:52:39.750919
1961 19:52:39.754479 Final TX Range 1 Vref 30
1962 19:52:39.754560
1963 19:52:39.754624 ==
1964 19:52:39.757610 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 19:52:39.760865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 19:52:39.764615 ==
1967 19:52:39.764695
1968 19:52:39.764759
1969 19:52:39.764819 TX Vref Scan disable
1970 19:52:39.767929 == TX Byte 0 ==
1971 19:52:39.771710 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1972 19:52:39.775295 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1973 19:52:39.777957 == TX Byte 1 ==
1974 19:52:39.781430 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1975 19:52:39.788167 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1976 19:52:39.788247
1977 19:52:39.788312 [DATLAT]
1978 19:52:39.788372 Freq=800, CH1 RK1
1979 19:52:39.788432
1980 19:52:39.791425 DATLAT Default: 0xa
1981 19:52:39.791528 0, 0xFFFF, sum = 0
1982 19:52:39.795310 1, 0xFFFF, sum = 0
1983 19:52:39.795421 2, 0xFFFF, sum = 0
1984 19:52:39.798354 3, 0xFFFF, sum = 0
1985 19:52:39.798435 4, 0xFFFF, sum = 0
1986 19:52:39.801355 5, 0xFFFF, sum = 0
1987 19:52:39.805011 6, 0xFFFF, sum = 0
1988 19:52:39.805092 7, 0xFFFF, sum = 0
1989 19:52:39.808953 8, 0xFFFF, sum = 0
1990 19:52:39.809034 9, 0x0, sum = 1
1991 19:52:39.809100 10, 0x0, sum = 2
1992 19:52:39.811241 11, 0x0, sum = 3
1993 19:52:39.811350 12, 0x0, sum = 4
1994 19:52:39.814842 best_step = 10
1995 19:52:39.814923
1996 19:52:39.814986 ==
1997 19:52:39.818250 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 19:52:39.821231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 19:52:39.821312 ==
2000 19:52:39.824737 RX Vref Scan: 0
2001 19:52:39.824843
2002 19:52:39.824937 RX Vref 0 -> 0, step: 1
2003 19:52:39.825010
2004 19:52:39.828416 RX Delay -95 -> 252, step: 8
2005 19:52:39.834485 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2006 19:52:39.837966 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2007 19:52:39.841430 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2008 19:52:39.844783 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2009 19:52:39.847860 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2010 19:52:39.854516 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2011 19:52:39.858123 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2012 19:52:39.861428 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2013 19:52:39.864842 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2014 19:52:39.868073 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2015 19:52:39.874535 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2016 19:52:39.878017 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2017 19:52:39.881303 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2018 19:52:39.884941 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2019 19:52:39.891180 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
2020 19:52:39.894765 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2021 19:52:39.894845 ==
2022 19:52:39.897673 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 19:52:39.901062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 19:52:39.901149 ==
2025 19:52:39.901214 DQS Delay:
2026 19:52:39.904527 DQS0 = 0, DQS1 = 0
2027 19:52:39.904607 DQM Delay:
2028 19:52:39.907645 DQM0 = 87, DQM1 = 79
2029 19:52:39.907784 DQ Delay:
2030 19:52:39.910937 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2031 19:52:39.914356 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2032 19:52:39.917575 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2033 19:52:39.920756 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
2034 19:52:39.920835
2035 19:52:39.920899
2036 19:52:39.931449 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2037 19:52:39.931531 CH1 RK1: MR19=606, MR18=1C14
2038 19:52:39.937460 CH1_RK1: MR19=0x606, MR18=0x1C14, DQSOSC=402, MR23=63, INC=91, DEC=60
2039 19:52:39.940837 [RxdqsGatingPostProcess] freq 800
2040 19:52:39.947837 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2041 19:52:39.951062 Pre-setting of DQS Precalculation
2042 19:52:39.954125 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2043 19:52:39.960652 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2044 19:52:39.970620 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2045 19:52:39.970701
2046 19:52:39.970764
2047 19:52:39.974502 [Calibration Summary] 1600 Mbps
2048 19:52:39.974610 CH 0, Rank 0
2049 19:52:39.977265 SW Impedance : PASS
2050 19:52:39.977345 DUTY Scan : NO K
2051 19:52:39.980487 ZQ Calibration : PASS
2052 19:52:39.984080 Jitter Meter : NO K
2053 19:52:39.984160 CBT Training : PASS
2054 19:52:39.987137 Write leveling : PASS
2055 19:52:39.987216 RX DQS gating : PASS
2056 19:52:39.990794 RX DQ/DQS(RDDQC) : PASS
2057 19:52:39.994041 TX DQ/DQS : PASS
2058 19:52:39.994121 RX DATLAT : PASS
2059 19:52:39.997365 RX DQ/DQS(Engine): PASS
2060 19:52:40.000687 TX OE : NO K
2061 19:52:40.000768 All Pass.
2062 19:52:40.000831
2063 19:52:40.000891 CH 0, Rank 1
2064 19:52:40.003713 SW Impedance : PASS
2065 19:52:40.007239 DUTY Scan : NO K
2066 19:52:40.007318 ZQ Calibration : PASS
2067 19:52:40.010716 Jitter Meter : NO K
2068 19:52:40.013728 CBT Training : PASS
2069 19:52:40.013830 Write leveling : PASS
2070 19:52:40.016815 RX DQS gating : PASS
2071 19:52:40.020106 RX DQ/DQS(RDDQC) : PASS
2072 19:52:40.020185 TX DQ/DQS : PASS
2073 19:52:40.023698 RX DATLAT : PASS
2074 19:52:40.026720 RX DQ/DQS(Engine): PASS
2075 19:52:40.026801 TX OE : NO K
2076 19:52:40.030018 All Pass.
2077 19:52:40.030098
2078 19:52:40.030162 CH 1, Rank 0
2079 19:52:40.033942 SW Impedance : PASS
2080 19:52:40.034021 DUTY Scan : NO K
2081 19:52:40.036764 ZQ Calibration : PASS
2082 19:52:40.040409 Jitter Meter : NO K
2083 19:52:40.040489 CBT Training : PASS
2084 19:52:40.043701 Write leveling : PASS
2085 19:52:40.046946 RX DQS gating : PASS
2086 19:52:40.047025 RX DQ/DQS(RDDQC) : PASS
2087 19:52:40.050202 TX DQ/DQS : PASS
2088 19:52:40.050282 RX DATLAT : PASS
2089 19:52:40.053715 RX DQ/DQS(Engine): PASS
2090 19:52:40.057005 TX OE : NO K
2091 19:52:40.057084 All Pass.
2092 19:52:40.057148
2093 19:52:40.057206 CH 1, Rank 1
2094 19:52:40.060576 SW Impedance : PASS
2095 19:52:40.063612 DUTY Scan : NO K
2096 19:52:40.063750 ZQ Calibration : PASS
2097 19:52:40.066759 Jitter Meter : NO K
2098 19:52:40.070213 CBT Training : PASS
2099 19:52:40.070292 Write leveling : PASS
2100 19:52:40.073950 RX DQS gating : PASS
2101 19:52:40.077107 RX DQ/DQS(RDDQC) : PASS
2102 19:52:40.077186 TX DQ/DQS : PASS
2103 19:52:40.080129 RX DATLAT : PASS
2104 19:52:40.083378 RX DQ/DQS(Engine): PASS
2105 19:52:40.083484 TX OE : NO K
2106 19:52:40.086623 All Pass.
2107 19:52:40.086702
2108 19:52:40.086766 DramC Write-DBI off
2109 19:52:40.089948 PER_BANK_REFRESH: Hybrid Mode
2110 19:52:40.090028 TX_TRACKING: ON
2111 19:52:40.093586 [GetDramInforAfterCalByMRR] Vendor 6.
2112 19:52:40.100172 [GetDramInforAfterCalByMRR] Revision 606.
2113 19:52:40.103324 [GetDramInforAfterCalByMRR] Revision 2 0.
2114 19:52:40.103430 MR0 0x3b3b
2115 19:52:40.103521 MR8 0x5151
2116 19:52:40.106790 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 19:52:40.106870
2118 19:52:40.109915 MR0 0x3b3b
2119 19:52:40.109995 MR8 0x5151
2120 19:52:40.113271 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 19:52:40.113351
2122 19:52:40.123891 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2123 19:52:40.126645 [FAST_K] Save calibration result to emmc
2124 19:52:40.129692 [FAST_K] Save calibration result to emmc
2125 19:52:40.132927 dram_init: config_dvfs: 1
2126 19:52:40.136705 dramc_set_vcore_voltage set vcore to 662500
2127 19:52:40.139594 Read voltage for 1200, 2
2128 19:52:40.139676 Vio18 = 0
2129 19:52:40.139781 Vcore = 662500
2130 19:52:40.143262 Vdram = 0
2131 19:52:40.143343 Vddq = 0
2132 19:52:40.143407 Vmddr = 0
2133 19:52:40.149681 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2134 19:52:40.152990 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2135 19:52:40.156706 MEM_TYPE=3, freq_sel=15
2136 19:52:40.159846 sv_algorithm_assistance_LP4_1600
2137 19:52:40.162890 ============ PULL DRAM RESETB DOWN ============
2138 19:52:40.166509 ========== PULL DRAM RESETB DOWN end =========
2139 19:52:40.173071 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2140 19:52:40.176572 ===================================
2141 19:52:40.176655 LPDDR4 DRAM CONFIGURATION
2142 19:52:40.179469 ===================================
2143 19:52:40.182938 EX_ROW_EN[0] = 0x0
2144 19:52:40.186408 EX_ROW_EN[1] = 0x0
2145 19:52:40.186490 LP4Y_EN = 0x0
2146 19:52:40.189649 WORK_FSP = 0x0
2147 19:52:40.189730 WL = 0x4
2148 19:52:40.192937 RL = 0x4
2149 19:52:40.193018 BL = 0x2
2150 19:52:40.195920 RPST = 0x0
2151 19:52:40.196053 RD_PRE = 0x0
2152 19:52:40.199623 WR_PRE = 0x1
2153 19:52:40.199705 WR_PST = 0x0
2154 19:52:40.202966 DBI_WR = 0x0
2155 19:52:40.203048 DBI_RD = 0x0
2156 19:52:40.206196 OTF = 0x1
2157 19:52:40.209226 ===================================
2158 19:52:40.212457 ===================================
2159 19:52:40.212538 ANA top config
2160 19:52:40.215660 ===================================
2161 19:52:40.220002 DLL_ASYNC_EN = 0
2162 19:52:40.223015 ALL_SLAVE_EN = 0
2163 19:52:40.225845 NEW_RANK_MODE = 1
2164 19:52:40.225928 DLL_IDLE_MODE = 1
2165 19:52:40.229289 LP45_APHY_COMB_EN = 1
2166 19:52:40.232436 TX_ODT_DIS = 1
2167 19:52:40.235986 NEW_8X_MODE = 1
2168 19:52:40.239372 ===================================
2169 19:52:40.242472 ===================================
2170 19:52:40.245964 data_rate = 2400
2171 19:52:40.246046 CKR = 1
2172 19:52:40.249303 DQ_P2S_RATIO = 8
2173 19:52:40.252343 ===================================
2174 19:52:40.255929 CA_P2S_RATIO = 8
2175 19:52:40.259110 DQ_CA_OPEN = 0
2176 19:52:40.262711 DQ_SEMI_OPEN = 0
2177 19:52:40.265610 CA_SEMI_OPEN = 0
2178 19:52:40.265692 CA_FULL_RATE = 0
2179 19:52:40.269095 DQ_CKDIV4_EN = 0
2180 19:52:40.272439 CA_CKDIV4_EN = 0
2181 19:52:40.275482 CA_PREDIV_EN = 0
2182 19:52:40.278881 PH8_DLY = 17
2183 19:52:40.282482 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2184 19:52:40.282563 DQ_AAMCK_DIV = 4
2185 19:52:40.285821 CA_AAMCK_DIV = 4
2186 19:52:40.288757 CA_ADMCK_DIV = 4
2187 19:52:40.292160 DQ_TRACK_CA_EN = 0
2188 19:52:40.295662 CA_PICK = 1200
2189 19:52:40.299232 CA_MCKIO = 1200
2190 19:52:40.302157 MCKIO_SEMI = 0
2191 19:52:40.302276 PLL_FREQ = 2366
2192 19:52:40.305854 DQ_UI_PI_RATIO = 32
2193 19:52:40.308673 CA_UI_PI_RATIO = 0
2194 19:52:40.312412 ===================================
2195 19:52:40.315151 ===================================
2196 19:52:40.318375 memory_type:LPDDR4
2197 19:52:40.321999 GP_NUM : 10
2198 19:52:40.322080 SRAM_EN : 1
2199 19:52:40.325278 MD32_EN : 0
2200 19:52:40.328707 ===================================
2201 19:52:40.331640 [ANA_INIT] >>>>>>>>>>>>>>
2202 19:52:40.331745 <<<<<< [CONFIGURE PHASE]: ANA_TX
2203 19:52:40.335244 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2204 19:52:40.338761 ===================================
2205 19:52:40.341850 data_rate = 2400,PCW = 0X5b00
2206 19:52:40.345164 ===================================
2207 19:52:40.349254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2208 19:52:40.354946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 19:52:40.361607 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 19:52:40.365021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2211 19:52:40.368763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2212 19:52:40.372257 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2213 19:52:40.375346 [ANA_INIT] flow start
2214 19:52:40.375427 [ANA_INIT] PLL >>>>>>>>
2215 19:52:40.378171 [ANA_INIT] PLL <<<<<<<<
2216 19:52:40.381571 [ANA_INIT] MIDPI >>>>>>>>
2217 19:52:40.381653 [ANA_INIT] MIDPI <<<<<<<<
2218 19:52:40.384809 [ANA_INIT] DLL >>>>>>>>
2219 19:52:40.388067 [ANA_INIT] DLL <<<<<<<<
2220 19:52:40.388148 [ANA_INIT] flow end
2221 19:52:40.394709 ============ LP4 DIFF to SE enter ============
2222 19:52:40.398419 ============ LP4 DIFF to SE exit ============
2223 19:52:40.401399 [ANA_INIT] <<<<<<<<<<<<<
2224 19:52:40.404792 [Flow] Enable top DCM control >>>>>
2225 19:52:40.407970 [Flow] Enable top DCM control <<<<<
2226 19:52:40.408055 Enable DLL master slave shuffle
2227 19:52:40.414674 ==============================================================
2228 19:52:40.418215 Gating Mode config
2229 19:52:40.421222 ==============================================================
2230 19:52:40.425149 Config description:
2231 19:52:40.434754 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2232 19:52:40.441201 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2233 19:52:40.444530 SELPH_MODE 0: By rank 1: By Phase
2234 19:52:40.451911 ==============================================================
2235 19:52:40.454589 GAT_TRACK_EN = 1
2236 19:52:40.457704 RX_GATING_MODE = 2
2237 19:52:40.461538 RX_GATING_TRACK_MODE = 2
2238 19:52:40.464675 SELPH_MODE = 1
2239 19:52:40.464774 PICG_EARLY_EN = 1
2240 19:52:40.467861 VALID_LAT_VALUE = 1
2241 19:52:40.474561 ==============================================================
2242 19:52:40.477551 Enter into Gating configuration >>>>
2243 19:52:40.481386 Exit from Gating configuration <<<<
2244 19:52:40.484559 Enter into DVFS_PRE_config >>>>>
2245 19:52:40.494670 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2246 19:52:40.497510 Exit from DVFS_PRE_config <<<<<
2247 19:52:40.501051 Enter into PICG configuration >>>>
2248 19:52:40.504189 Exit from PICG configuration <<<<
2249 19:52:40.507656 [RX_INPUT] configuration >>>>>
2250 19:52:40.510710 [RX_INPUT] configuration <<<<<
2251 19:52:40.514273 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2252 19:52:40.520891 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2253 19:52:40.527574 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 19:52:40.533946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 19:52:40.540691 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 19:52:40.547252 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 19:52:40.551178 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2258 19:52:40.553925 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2259 19:52:40.557428 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2260 19:52:40.560852 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2261 19:52:40.567625 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2262 19:52:40.570633 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2263 19:52:40.573845 ===================================
2264 19:52:40.576982 LPDDR4 DRAM CONFIGURATION
2265 19:52:40.580628 ===================================
2266 19:52:40.580710 EX_ROW_EN[0] = 0x0
2267 19:52:40.583975 EX_ROW_EN[1] = 0x0
2268 19:52:40.584056 LP4Y_EN = 0x0
2269 19:52:40.586999 WORK_FSP = 0x0
2270 19:52:40.587080 WL = 0x4
2271 19:52:40.590442 RL = 0x4
2272 19:52:40.593342 BL = 0x2
2273 19:52:40.593424 RPST = 0x0
2274 19:52:40.596871 RD_PRE = 0x0
2275 19:52:40.596952 WR_PRE = 0x1
2276 19:52:40.600381 WR_PST = 0x0
2277 19:52:40.600462 DBI_WR = 0x0
2278 19:52:40.603364 DBI_RD = 0x0
2279 19:52:40.603445 OTF = 0x1
2280 19:52:40.606840 ===================================
2281 19:52:40.610004 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2282 19:52:40.616706 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2283 19:52:40.620296 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2284 19:52:40.623331 ===================================
2285 19:52:40.626433 LPDDR4 DRAM CONFIGURATION
2286 19:52:40.630268 ===================================
2287 19:52:40.630350 EX_ROW_EN[0] = 0x10
2288 19:52:40.633429 EX_ROW_EN[1] = 0x0
2289 19:52:40.633510 LP4Y_EN = 0x0
2290 19:52:40.636812 WORK_FSP = 0x0
2291 19:52:40.636893 WL = 0x4
2292 19:52:40.639923 RL = 0x4
2293 19:52:40.640003 BL = 0x2
2294 19:52:40.643285 RPST = 0x0
2295 19:52:40.646750 RD_PRE = 0x0
2296 19:52:40.646831 WR_PRE = 0x1
2297 19:52:40.649961 WR_PST = 0x0
2298 19:52:40.650059 DBI_WR = 0x0
2299 19:52:40.652942 DBI_RD = 0x0
2300 19:52:40.653022 OTF = 0x1
2301 19:52:40.656735 ===================================
2302 19:52:40.663423 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2303 19:52:40.663507 ==
2304 19:52:40.666780 Dram Type= 6, Freq= 0, CH_0, rank 0
2305 19:52:40.669929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2306 19:52:40.670010 ==
2307 19:52:40.673661 [Duty_Offset_Calibration]
2308 19:52:40.676660 B0:1 B1:-1 CA:0
2309 19:52:40.676741
2310 19:52:40.679991 [DutyScan_Calibration_Flow] k_type=0
2311 19:52:40.687641
2312 19:52:40.687730 ==CLK 0==
2313 19:52:40.691164 Final CLK duty delay cell = 0
2314 19:52:40.694450 [0] MAX Duty = 5094%(X100), DQS PI = 16
2315 19:52:40.697451 [0] MIN Duty = 4875%(X100), DQS PI = 10
2316 19:52:40.697532 [0] AVG Duty = 4984%(X100)
2317 19:52:40.700857
2318 19:52:40.704274 CH0 CLK Duty spec in!! Max-Min= 219%
2319 19:52:40.707693 [DutyScan_Calibration_Flow] ====Done====
2320 19:52:40.707816
2321 19:52:40.710654 [DutyScan_Calibration_Flow] k_type=1
2322 19:52:40.725315
2323 19:52:40.725395 ==DQS 0 ==
2324 19:52:40.728848 Final DQS duty delay cell = -4
2325 19:52:40.732265 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2326 19:52:40.735267 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2327 19:52:40.739001 [-4] AVG Duty = 4968%(X100)
2328 19:52:40.739081
2329 19:52:40.739146 ==DQS 1 ==
2330 19:52:40.742088 Final DQS duty delay cell = -4
2331 19:52:40.745550 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2332 19:52:40.748891 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2333 19:52:40.751823 [-4] AVG Duty = 4938%(X100)
2334 19:52:40.751904
2335 19:52:40.755062 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2336 19:52:40.755144
2337 19:52:40.758780 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2338 19:52:40.761918 [DutyScan_Calibration_Flow] ====Done====
2339 19:52:40.761999
2340 19:52:40.765492 [DutyScan_Calibration_Flow] k_type=3
2341 19:52:40.783664
2342 19:52:40.783798 ==DQM 0 ==
2343 19:52:40.786810 Final DQM duty delay cell = 0
2344 19:52:40.790401 [0] MAX Duty = 5062%(X100), DQS PI = 20
2345 19:52:40.793672 [0] MIN Duty = 4875%(X100), DQS PI = 10
2346 19:52:40.793753 [0] AVG Duty = 4968%(X100)
2347 19:52:40.796883
2348 19:52:40.796963 ==DQM 1 ==
2349 19:52:40.800143 Final DQM duty delay cell = 4
2350 19:52:40.803671 [4] MAX Duty = 5187%(X100), DQS PI = 14
2351 19:52:40.806641 [4] MIN Duty = 5000%(X100), DQS PI = 24
2352 19:52:40.809950 [4] AVG Duty = 5093%(X100)
2353 19:52:40.810031
2354 19:52:40.813315 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2355 19:52:40.813396
2356 19:52:40.817185 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2357 19:52:40.819939 [DutyScan_Calibration_Flow] ====Done====
2358 19:52:40.820046
2359 19:52:40.823325 [DutyScan_Calibration_Flow] k_type=2
2360 19:52:40.838953
2361 19:52:40.839033 ==DQ 0 ==
2362 19:52:40.841737 Final DQ duty delay cell = -4
2363 19:52:40.845535 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2364 19:52:40.848572 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2365 19:52:40.851544 [-4] AVG Duty = 4969%(X100)
2366 19:52:40.851624
2367 19:52:40.851688 ==DQ 1 ==
2368 19:52:40.855118 Final DQ duty delay cell = -4
2369 19:52:40.858819 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2370 19:52:40.861452 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2371 19:52:40.864605 [-4] AVG Duty = 4938%(X100)
2372 19:52:40.864685
2373 19:52:40.868455 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2374 19:52:40.868535
2375 19:52:40.871564 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2376 19:52:40.874924 [DutyScan_Calibration_Flow] ====Done====
2377 19:52:40.875005 ==
2378 19:52:40.878248 Dram Type= 6, Freq= 0, CH_1, rank 0
2379 19:52:40.881535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2380 19:52:40.881616 ==
2381 19:52:40.884957 [Duty_Offset_Calibration]
2382 19:52:40.885036 B0:-1 B1:1 CA:2
2383 19:52:40.888131
2384 19:52:40.891047 [DutyScan_Calibration_Flow] k_type=0
2385 19:52:40.898972
2386 19:52:40.899052 ==CLK 0==
2387 19:52:40.902652 Final CLK duty delay cell = 0
2388 19:52:40.906073 [0] MAX Duty = 5156%(X100), DQS PI = 22
2389 19:52:40.909192 [0] MIN Duty = 4969%(X100), DQS PI = 62
2390 19:52:40.909272 [0] AVG Duty = 5062%(X100)
2391 19:52:40.912681
2392 19:52:40.915843 CH1 CLK Duty spec in!! Max-Min= 187%
2393 19:52:40.919178 [DutyScan_Calibration_Flow] ====Done====
2394 19:52:40.919257
2395 19:52:40.922122 [DutyScan_Calibration_Flow] k_type=1
2396 19:52:40.938817
2397 19:52:40.938903 ==DQS 0 ==
2398 19:52:40.942074 Final DQS duty delay cell = 0
2399 19:52:40.944924 [0] MAX Duty = 5156%(X100), DQS PI = 48
2400 19:52:40.948443 [0] MIN Duty = 4875%(X100), DQS PI = 8
2401 19:52:40.952288 [0] AVG Duty = 5015%(X100)
2402 19:52:40.952368
2403 19:52:40.952431 ==DQS 1 ==
2404 19:52:40.955078 Final DQS duty delay cell = 0
2405 19:52:40.958118 [0] MAX Duty = 5094%(X100), DQS PI = 10
2406 19:52:40.961398 [0] MIN Duty = 4969%(X100), DQS PI = 58
2407 19:52:40.965140 [0] AVG Duty = 5031%(X100)
2408 19:52:40.965220
2409 19:52:40.968049 CH1 DQS 0 Duty spec in!! Max-Min= 281%
2410 19:52:40.968128
2411 19:52:40.971514 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2412 19:52:40.974770 [DutyScan_Calibration_Flow] ====Done====
2413 19:52:40.974850
2414 19:52:40.977918 [DutyScan_Calibration_Flow] k_type=3
2415 19:52:40.994317
2416 19:52:40.994396 ==DQM 0 ==
2417 19:52:40.997301 Final DQM duty delay cell = -4
2418 19:52:41.000510 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2419 19:52:41.003923 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2420 19:52:41.007383 [-4] AVG Duty = 4937%(X100)
2421 19:52:41.007463
2422 19:52:41.007525 ==DQM 1 ==
2423 19:52:41.010852 Final DQM duty delay cell = 0
2424 19:52:41.013883 [0] MAX Duty = 5187%(X100), DQS PI = 4
2425 19:52:41.017107 [0] MIN Duty = 5000%(X100), DQS PI = 28
2426 19:52:41.020552 [0] AVG Duty = 5093%(X100)
2427 19:52:41.020632
2428 19:52:41.024413 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2429 19:52:41.024494
2430 19:52:41.027243 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2431 19:52:41.030514 [DutyScan_Calibration_Flow] ====Done====
2432 19:52:41.030593
2433 19:52:41.034270 [DutyScan_Calibration_Flow] k_type=2
2434 19:52:41.051020
2435 19:52:41.051107 ==DQ 0 ==
2436 19:52:41.054476 Final DQ duty delay cell = 0
2437 19:52:41.057960 [0] MAX Duty = 5187%(X100), DQS PI = 32
2438 19:52:41.060685 [0] MIN Duty = 4907%(X100), DQS PI = 6
2439 19:52:41.060765 [0] AVG Duty = 5047%(X100)
2440 19:52:41.060829
2441 19:52:41.064027 ==DQ 1 ==
2442 19:52:41.067469 Final DQ duty delay cell = 0
2443 19:52:41.070608 [0] MAX Duty = 5124%(X100), DQS PI = 10
2444 19:52:41.074356 [0] MIN Duty = 4969%(X100), DQS PI = 0
2445 19:52:41.074436 [0] AVG Duty = 5046%(X100)
2446 19:52:41.074499
2447 19:52:41.077434 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2448 19:52:41.080829
2449 19:52:41.084333 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2450 19:52:41.087489 [DutyScan_Calibration_Flow] ====Done====
2451 19:52:41.090578 nWR fixed to 30
2452 19:52:41.090685 [ModeRegInit_LP4] CH0 RK0
2453 19:52:41.093691 [ModeRegInit_LP4] CH0 RK1
2454 19:52:41.097217 [ModeRegInit_LP4] CH1 RK0
2455 19:52:41.100790 [ModeRegInit_LP4] CH1 RK1
2456 19:52:41.100869 match AC timing 7
2457 19:52:41.104013 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2458 19:52:41.110381 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2459 19:52:41.114008 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2460 19:52:41.117109 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2461 19:52:41.123851 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2462 19:52:41.123957 ==
2463 19:52:41.127647 Dram Type= 6, Freq= 0, CH_0, rank 0
2464 19:52:41.130720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2465 19:52:41.130800 ==
2466 19:52:41.137119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2467 19:52:41.143596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2468 19:52:41.150516 [CA 0] Center 39 (9~70) winsize 62
2469 19:52:41.153901 [CA 1] Center 39 (9~70) winsize 62
2470 19:52:41.157222 [CA 2] Center 35 (5~66) winsize 62
2471 19:52:41.160833 [CA 3] Center 35 (5~65) winsize 61
2472 19:52:41.163879 [CA 4] Center 33 (3~64) winsize 62
2473 19:52:41.168024 [CA 5] Center 33 (4~63) winsize 60
2474 19:52:41.168103
2475 19:52:41.170747 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2476 19:52:41.170827
2477 19:52:41.174015 [CATrainingPosCal] consider 1 rank data
2478 19:52:41.177424 u2DelayCellTimex100 = 270/100 ps
2479 19:52:41.180798 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2480 19:52:41.187364 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2481 19:52:41.190664 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2482 19:52:41.193836 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2483 19:52:41.196769 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2484 19:52:41.200766 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2485 19:52:41.200846
2486 19:52:41.203587 CA PerBit enable=1, Macro0, CA PI delay=33
2487 19:52:41.203697
2488 19:52:41.207219 [CBTSetCACLKResult] CA Dly = 33
2489 19:52:41.207299 CS Dly: 8 (0~39)
2490 19:52:41.210220 ==
2491 19:52:41.213723 Dram Type= 6, Freq= 0, CH_0, rank 1
2492 19:52:41.217289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2493 19:52:41.217366 ==
2494 19:52:41.220079 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2495 19:52:41.226943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2496 19:52:41.236141 [CA 0] Center 39 (8~70) winsize 63
2497 19:52:41.239835 [CA 1] Center 39 (9~70) winsize 62
2498 19:52:41.243090 [CA 2] Center 35 (5~66) winsize 62
2499 19:52:41.246282 [CA 3] Center 34 (4~65) winsize 62
2500 19:52:41.249493 [CA 4] Center 33 (3~64) winsize 62
2501 19:52:41.253207 [CA 5] Center 33 (3~63) winsize 61
2502 19:52:41.253287
2503 19:52:41.256214 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2504 19:52:41.256294
2505 19:52:41.259905 [CATrainingPosCal] consider 2 rank data
2506 19:52:41.263651 u2DelayCellTimex100 = 270/100 ps
2507 19:52:41.266321 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2508 19:52:41.269738 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2509 19:52:41.276231 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2510 19:52:41.279384 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2511 19:52:41.283174 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2512 19:52:41.286477 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2513 19:52:41.286558
2514 19:52:41.289779 CA PerBit enable=1, Macro0, CA PI delay=33
2515 19:52:41.289860
2516 19:52:41.292944 [CBTSetCACLKResult] CA Dly = 33
2517 19:52:41.293025 CS Dly: 8 (0~40)
2518 19:52:41.293090
2519 19:52:41.296422 ----->DramcWriteLeveling(PI) begin...
2520 19:52:41.300165 ==
2521 19:52:41.300245 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 19:52:41.306461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 19:52:41.306541 ==
2524 19:52:41.309738 Write leveling (Byte 0): 33 => 33
2525 19:52:41.313164 Write leveling (Byte 1): 29 => 29
2526 19:52:41.316716 DramcWriteLeveling(PI) end<-----
2527 19:52:41.316796
2528 19:52:41.316859 ==
2529 19:52:41.319896 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 19:52:41.322948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 19:52:41.323028 ==
2532 19:52:41.326767 [Gating] SW mode calibration
2533 19:52:41.332654 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2534 19:52:41.339511 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2535 19:52:41.342581 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2536 19:52:41.346281 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2537 19:52:41.349408 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 19:52:41.356548 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 19:52:41.359660 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 19:52:41.363030 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 19:52:41.369449 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2542 19:52:41.372639 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
2543 19:52:41.376070 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
2544 19:52:41.383131 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2545 19:52:41.386411 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 19:52:41.389408 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 19:52:41.396240 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 19:52:41.399650 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 19:52:41.403205 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 19:52:41.409766 1 0 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
2551 19:52:41.412750 1 1 0 | B1->B0 | 2424 4444 | 1 0 | (0 0) (0 0)
2552 19:52:41.416046 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2553 19:52:41.423620 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 19:52:41.426019 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 19:52:41.429302 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 19:52:41.435925 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 19:52:41.439469 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 19:52:41.442870 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2559 19:52:41.449324 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2560 19:52:41.452470 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 19:52:41.455481 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 19:52:41.462420 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 19:52:41.465750 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 19:52:41.469124 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 19:52:41.475410 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 19:52:41.479088 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 19:52:41.482326 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 19:52:41.485709 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 19:52:41.492117 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 19:52:41.495572 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 19:52:41.498895 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 19:52:41.505538 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 19:52:41.509200 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 19:52:41.512018 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2575 19:52:41.518846 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2576 19:52:41.522164 Total UI for P1: 0, mck2ui 16
2577 19:52:41.525419 best dqsien dly found for B0: ( 1, 3, 28)
2578 19:52:41.529019 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 19:52:41.532164 Total UI for P1: 0, mck2ui 16
2580 19:52:41.535155 best dqsien dly found for B1: ( 1, 4, 0)
2581 19:52:41.538737 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2582 19:52:41.542101 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2583 19:52:41.542181
2584 19:52:41.545514 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2585 19:52:41.549111 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2586 19:52:41.552052 [Gating] SW calibration Done
2587 19:52:41.552132 ==
2588 19:52:41.555610 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 19:52:41.558346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 19:52:41.562210 ==
2591 19:52:41.562290 RX Vref Scan: 0
2592 19:52:41.562354
2593 19:52:41.565908 RX Vref 0 -> 0, step: 1
2594 19:52:41.565987
2595 19:52:41.568712 RX Delay -40 -> 252, step: 8
2596 19:52:41.572031 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2597 19:52:41.574824 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2598 19:52:41.578441 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2599 19:52:41.581832 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2600 19:52:41.588877 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2601 19:52:41.591518 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2602 19:52:41.594595 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2603 19:52:41.598391 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2604 19:52:41.601644 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2605 19:52:41.608130 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2606 19:52:41.611823 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2607 19:52:41.614881 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2608 19:52:41.618530 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2609 19:52:41.621258 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2610 19:52:41.628077 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2611 19:52:41.631986 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2612 19:52:41.632066 ==
2613 19:52:41.634962 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 19:52:41.638297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 19:52:41.638378 ==
2616 19:52:41.641230 DQS Delay:
2617 19:52:41.641310 DQS0 = 0, DQS1 = 0
2618 19:52:41.641374 DQM Delay:
2619 19:52:41.644364 DQM0 = 119, DQM1 = 106
2620 19:52:41.644448 DQ Delay:
2621 19:52:41.648455 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2622 19:52:41.651563 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2623 19:52:41.654974 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2624 19:52:41.661510 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2625 19:52:41.661590
2626 19:52:41.661656
2627 19:52:41.661719 ==
2628 19:52:41.664540 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 19:52:41.668062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 19:52:41.668145 ==
2631 19:52:41.668209
2632 19:52:41.668268
2633 19:52:41.671118 TX Vref Scan disable
2634 19:52:41.671197 == TX Byte 0 ==
2635 19:52:41.677448 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2636 19:52:41.681049 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2637 19:52:41.684189 == TX Byte 1 ==
2638 19:52:41.688036 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2639 19:52:41.690916 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2640 19:52:41.690995 ==
2641 19:52:41.694157 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 19:52:41.698666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 19:52:41.698746 ==
2644 19:52:41.710933 TX Vref=22, minBit 5, minWin=25, winSum=417
2645 19:52:41.714250 TX Vref=24, minBit 8, minWin=25, winSum=424
2646 19:52:41.717688 TX Vref=26, minBit 14, minWin=25, winSum=430
2647 19:52:41.720425 TX Vref=28, minBit 8, minWin=26, winSum=434
2648 19:52:41.724217 TX Vref=30, minBit 4, minWin=26, winSum=434
2649 19:52:41.730613 TX Vref=32, minBit 10, minWin=26, winSum=432
2650 19:52:41.733809 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
2651 19:52:41.733890
2652 19:52:41.737827 Final TX Range 1 Vref 28
2653 19:52:41.737973
2654 19:52:41.738038 ==
2655 19:52:41.740968 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 19:52:41.743789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 19:52:41.746932 ==
2658 19:52:41.747012
2659 19:52:41.747075
2660 19:52:41.747134 TX Vref Scan disable
2661 19:52:41.750642 == TX Byte 0 ==
2662 19:52:41.754305 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2663 19:52:41.760448 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2664 19:52:41.760528 == TX Byte 1 ==
2665 19:52:41.763566 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2666 19:52:41.770821 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2667 19:52:41.770902
2668 19:52:41.770966 [DATLAT]
2669 19:52:41.771025 Freq=1200, CH0 RK0
2670 19:52:41.773804
2671 19:52:41.773884 DATLAT Default: 0xd
2672 19:52:41.776849 0, 0xFFFF, sum = 0
2673 19:52:41.776931 1, 0xFFFF, sum = 0
2674 19:52:41.780526 2, 0xFFFF, sum = 0
2675 19:52:41.780607 3, 0xFFFF, sum = 0
2676 19:52:41.784021 4, 0xFFFF, sum = 0
2677 19:52:41.784132 5, 0xFFFF, sum = 0
2678 19:52:41.786977 6, 0xFFFF, sum = 0
2679 19:52:41.787057 7, 0xFFFF, sum = 0
2680 19:52:41.790222 8, 0xFFFF, sum = 0
2681 19:52:41.790303 9, 0xFFFF, sum = 0
2682 19:52:41.793680 10, 0xFFFF, sum = 0
2683 19:52:41.793761 11, 0xFFFF, sum = 0
2684 19:52:41.796663 12, 0x0, sum = 1
2685 19:52:41.796743 13, 0x0, sum = 2
2686 19:52:41.800271 14, 0x0, sum = 3
2687 19:52:41.800352 15, 0x0, sum = 4
2688 19:52:41.803882 best_step = 13
2689 19:52:41.803962
2690 19:52:41.804024 ==
2691 19:52:41.806947 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 19:52:41.810038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 19:52:41.810145 ==
2694 19:52:41.813700 RX Vref Scan: 1
2695 19:52:41.813782
2696 19:52:41.813862 Set Vref Range= 32 -> 127
2697 19:52:41.813924
2698 19:52:41.816680 RX Vref 32 -> 127, step: 1
2699 19:52:41.816759
2700 19:52:41.820077 RX Delay -21 -> 252, step: 4
2701 19:52:41.820183
2702 19:52:41.823719 Set Vref, RX VrefLevel [Byte0]: 32
2703 19:52:41.826873 [Byte1]: 32
2704 19:52:41.826952
2705 19:52:41.830182 Set Vref, RX VrefLevel [Byte0]: 33
2706 19:52:41.833408 [Byte1]: 33
2707 19:52:41.837160
2708 19:52:41.837241 Set Vref, RX VrefLevel [Byte0]: 34
2709 19:52:41.840912 [Byte1]: 34
2710 19:52:41.845386
2711 19:52:41.845466 Set Vref, RX VrefLevel [Byte0]: 35
2712 19:52:41.848820 [Byte1]: 35
2713 19:52:41.853157
2714 19:52:41.853238 Set Vref, RX VrefLevel [Byte0]: 36
2715 19:52:41.856343 [Byte1]: 36
2716 19:52:41.861099
2717 19:52:41.861176 Set Vref, RX VrefLevel [Byte0]: 37
2718 19:52:41.864293 [Byte1]: 37
2719 19:52:41.869113
2720 19:52:41.869192 Set Vref, RX VrefLevel [Byte0]: 38
2721 19:52:41.872280 [Byte1]: 38
2722 19:52:41.877132
2723 19:52:41.877237 Set Vref, RX VrefLevel [Byte0]: 39
2724 19:52:41.879999 [Byte1]: 39
2725 19:52:41.885200
2726 19:52:41.885279 Set Vref, RX VrefLevel [Byte0]: 40
2727 19:52:41.888316 [Byte1]: 40
2728 19:52:41.892858
2729 19:52:41.892937 Set Vref, RX VrefLevel [Byte0]: 41
2730 19:52:41.896356 [Byte1]: 41
2731 19:52:41.900572
2732 19:52:41.900652 Set Vref, RX VrefLevel [Byte0]: 42
2733 19:52:41.903730 [Byte1]: 42
2734 19:52:41.909104
2735 19:52:41.909183 Set Vref, RX VrefLevel [Byte0]: 43
2736 19:52:41.912207 [Byte1]: 43
2737 19:52:41.917284
2738 19:52:41.917363 Set Vref, RX VrefLevel [Byte0]: 44
2739 19:52:41.922991 [Byte1]: 44
2740 19:52:41.923083
2741 19:52:41.926426 Set Vref, RX VrefLevel [Byte0]: 45
2742 19:52:41.929695 [Byte1]: 45
2743 19:52:41.929775
2744 19:52:41.933036 Set Vref, RX VrefLevel [Byte0]: 46
2745 19:52:41.936270 [Byte1]: 46
2746 19:52:41.940321
2747 19:52:41.940401 Set Vref, RX VrefLevel [Byte0]: 47
2748 19:52:41.943605 [Byte1]: 47
2749 19:52:41.948091
2750 19:52:41.948170 Set Vref, RX VrefLevel [Byte0]: 48
2751 19:52:41.951973 [Byte1]: 48
2752 19:52:41.956208
2753 19:52:41.956287 Set Vref, RX VrefLevel [Byte0]: 49
2754 19:52:41.959785 [Byte1]: 49
2755 19:52:41.964361
2756 19:52:41.964440 Set Vref, RX VrefLevel [Byte0]: 50
2757 19:52:41.967445 [Byte1]: 50
2758 19:52:41.972006
2759 19:52:41.972085 Set Vref, RX VrefLevel [Byte0]: 51
2760 19:52:41.975501 [Byte1]: 51
2761 19:52:41.980219
2762 19:52:41.980320 Set Vref, RX VrefLevel [Byte0]: 52
2763 19:52:41.983195 [Byte1]: 52
2764 19:52:41.988211
2765 19:52:41.988292 Set Vref, RX VrefLevel [Byte0]: 53
2766 19:52:41.990877 [Byte1]: 53
2767 19:52:41.995869
2768 19:52:41.995949 Set Vref, RX VrefLevel [Byte0]: 54
2769 19:52:41.999485 [Byte1]: 54
2770 19:52:42.003669
2771 19:52:42.003774 Set Vref, RX VrefLevel [Byte0]: 55
2772 19:52:42.007363 [Byte1]: 55
2773 19:52:42.011935
2774 19:52:42.012014 Set Vref, RX VrefLevel [Byte0]: 56
2775 19:52:42.015014 [Byte1]: 56
2776 19:52:42.020086
2777 19:52:42.020165 Set Vref, RX VrefLevel [Byte0]: 57
2778 19:52:42.023104 [Byte1]: 57
2779 19:52:42.027684
2780 19:52:42.027782 Set Vref, RX VrefLevel [Byte0]: 58
2781 19:52:42.030683 [Byte1]: 58
2782 19:52:42.035376
2783 19:52:42.035455 Set Vref, RX VrefLevel [Byte0]: 59
2784 19:52:42.038770 [Byte1]: 59
2785 19:52:42.043092
2786 19:52:42.043170 Set Vref, RX VrefLevel [Byte0]: 60
2787 19:52:42.046489 [Byte1]: 60
2788 19:52:42.051128
2789 19:52:42.051208 Set Vref, RX VrefLevel [Byte0]: 61
2790 19:52:42.054371 [Byte1]: 61
2791 19:52:42.059060
2792 19:52:42.059139 Set Vref, RX VrefLevel [Byte0]: 62
2793 19:52:42.062562 [Byte1]: 62
2794 19:52:42.067576
2795 19:52:42.067683 Set Vref, RX VrefLevel [Byte0]: 63
2796 19:52:42.070310 [Byte1]: 63
2797 19:52:42.075030
2798 19:52:42.075110 Set Vref, RX VrefLevel [Byte0]: 64
2799 19:52:42.078204 [Byte1]: 64
2800 19:52:42.082919
2801 19:52:42.082999 Set Vref, RX VrefLevel [Byte0]: 65
2802 19:52:42.086345 [Byte1]: 65
2803 19:52:42.090822
2804 19:52:42.090902 Set Vref, RX VrefLevel [Byte0]: 66
2805 19:52:42.094186 [Byte1]: 66
2806 19:52:42.098532
2807 19:52:42.098611 Set Vref, RX VrefLevel [Byte0]: 67
2808 19:52:42.102155 [Byte1]: 67
2809 19:52:42.106989
2810 19:52:42.107068 Set Vref, RX VrefLevel [Byte0]: 68
2811 19:52:42.109892 [Byte1]: 68
2812 19:52:42.114605
2813 19:52:42.114684 Set Vref, RX VrefLevel [Byte0]: 69
2814 19:52:42.121244 [Byte1]: 69
2815 19:52:42.121324
2816 19:52:42.124880 Set Vref, RX VrefLevel [Byte0]: 70
2817 19:52:42.127870 [Byte1]: 70
2818 19:52:42.127961
2819 19:52:42.131102 Set Vref, RX VrefLevel [Byte0]: 71
2820 19:52:42.134462 [Byte1]: 71
2821 19:52:42.138630
2822 19:52:42.138709 Set Vref, RX VrefLevel [Byte0]: 72
2823 19:52:42.142025 [Byte1]: 72
2824 19:52:42.146445
2825 19:52:42.146524 Set Vref, RX VrefLevel [Byte0]: 73
2826 19:52:42.149968 [Byte1]: 73
2827 19:52:42.154750
2828 19:52:42.154829 Set Vref, RX VrefLevel [Byte0]: 74
2829 19:52:42.157440 [Byte1]: 74
2830 19:52:42.162410
2831 19:52:42.162516 Set Vref, RX VrefLevel [Byte0]: 75
2832 19:52:42.165492 [Byte1]: 75
2833 19:52:42.170290
2834 19:52:42.170369 Set Vref, RX VrefLevel [Byte0]: 76
2835 19:52:42.173367 [Byte1]: 76
2836 19:52:42.178127
2837 19:52:42.178237 Set Vref, RX VrefLevel [Byte0]: 77
2838 19:52:42.181358 [Byte1]: 77
2839 19:52:42.185711
2840 19:52:42.185790 Final RX Vref Byte 0 = 59 to rank0
2841 19:52:42.189167 Final RX Vref Byte 1 = 59 to rank0
2842 19:52:42.193238 Final RX Vref Byte 0 = 59 to rank1
2843 19:52:42.195734 Final RX Vref Byte 1 = 59 to rank1==
2844 19:52:42.199135 Dram Type= 6, Freq= 0, CH_0, rank 0
2845 19:52:42.205832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 19:52:42.205912 ==
2847 19:52:42.205977 DQS Delay:
2848 19:52:42.209195 DQS0 = 0, DQS1 = 0
2849 19:52:42.209275 DQM Delay:
2850 19:52:42.209338 DQM0 = 119, DQM1 = 108
2851 19:52:42.212735 DQ Delay:
2852 19:52:42.216011 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2853 19:52:42.218855 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2854 19:52:42.222757 DQ8 =96, DQ9 =94, DQ10 =112, DQ11 =102
2855 19:52:42.225624 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2856 19:52:42.225733
2857 19:52:42.225807
2858 19:52:42.235555 [DQSOSCAuto] RK0, (LSB)MR18= 0xefa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2859 19:52:42.235662 CH0 RK0: MR19=403, MR18=EFA
2860 19:52:42.242278 CH0_RK0: MR19=0x403, MR18=0xEFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2861 19:52:42.242390
2862 19:52:42.245718 ----->DramcWriteLeveling(PI) begin...
2863 19:52:42.245799 ==
2864 19:52:42.249039 Dram Type= 6, Freq= 0, CH_0, rank 1
2865 19:52:42.252105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2866 19:52:42.255932 ==
2867 19:52:42.256012 Write leveling (Byte 0): 33 => 33
2868 19:52:42.258752 Write leveling (Byte 1): 29 => 29
2869 19:52:42.262211 DramcWriteLeveling(PI) end<-----
2870 19:52:42.262291
2871 19:52:42.262354 ==
2872 19:52:42.265522 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 19:52:42.272121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 19:52:42.272201 ==
2875 19:52:42.275176 [Gating] SW mode calibration
2876 19:52:42.282355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2877 19:52:42.285506 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2878 19:52:42.291693 0 15 0 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
2879 19:52:42.295281 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 19:52:42.299144 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 19:52:42.305245 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 19:52:42.308653 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 19:52:42.311690 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 19:52:42.318601 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2885 19:52:42.321653 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2886 19:52:42.325495 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2887 19:52:42.328502 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 19:52:42.335127 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 19:52:42.338388 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 19:52:42.341758 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 19:52:42.348319 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 19:52:42.351515 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 19:52:42.354809 1 0 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
2894 19:52:42.361747 1 1 0 | B1->B0 | 3b3a 4646 | 1 0 | (0 0) (0 0)
2895 19:52:42.364792 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 19:52:42.367814 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 19:52:42.374517 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 19:52:42.378013 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 19:52:42.381399 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 19:52:42.387943 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 19:52:42.391417 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2902 19:52:42.394438 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2903 19:52:42.400901 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 19:52:42.404231 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 19:52:42.407542 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 19:52:42.414502 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 19:52:42.417932 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 19:52:42.420984 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 19:52:42.428329 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 19:52:42.431474 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 19:52:42.434527 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 19:52:42.441289 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 19:52:42.444881 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 19:52:42.447984 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 19:52:42.454559 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 19:52:42.457697 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 19:52:42.461372 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2918 19:52:42.467545 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2919 19:52:42.470907 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 19:52:42.474630 Total UI for P1: 0, mck2ui 16
2921 19:52:42.477540 best dqsien dly found for B0: ( 1, 3, 30)
2922 19:52:42.480755 Total UI for P1: 0, mck2ui 16
2923 19:52:42.484643 best dqsien dly found for B1: ( 1, 4, 0)
2924 19:52:42.487371 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2925 19:52:42.490643 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2926 19:52:42.490737
2927 19:52:42.494257 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2928 19:52:42.497265 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2929 19:52:42.501245 [Gating] SW calibration Done
2930 19:52:42.501343 ==
2931 19:52:42.504000 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 19:52:42.507835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 19:52:42.507907 ==
2934 19:52:42.511076 RX Vref Scan: 0
2935 19:52:42.511184
2936 19:52:42.513847 RX Vref 0 -> 0, step: 1
2937 19:52:42.513943
2938 19:52:42.514034 RX Delay -40 -> 252, step: 8
2939 19:52:42.520660 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2940 19:52:42.524111 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2941 19:52:42.527068 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2942 19:52:42.530308 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2943 19:52:42.534268 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2944 19:52:42.540629 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2945 19:52:42.543918 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2946 19:52:42.547061 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2947 19:52:42.550470 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2948 19:52:42.553942 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2949 19:52:42.560183 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2950 19:52:42.563664 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2951 19:52:42.566725 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
2952 19:52:42.570152 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2953 19:52:42.577129 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2954 19:52:42.580187 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2955 19:52:42.580265 ==
2956 19:52:42.583813 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 19:52:42.586945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 19:52:42.587018 ==
2959 19:52:42.587090 DQS Delay:
2960 19:52:42.590337 DQS0 = 0, DQS1 = 0
2961 19:52:42.590429 DQM Delay:
2962 19:52:42.593631 DQM0 = 116, DQM1 = 109
2963 19:52:42.593723 DQ Delay:
2964 19:52:42.597040 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2965 19:52:42.600081 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2966 19:52:42.603618 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2967 19:52:42.606656 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2968 19:52:42.606727
2969 19:52:42.610284
2970 19:52:42.610352 ==
2971 19:52:42.614020 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 19:52:42.617126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 19:52:42.617219 ==
2974 19:52:42.617306
2975 19:52:42.617392
2976 19:52:42.619817 TX Vref Scan disable
2977 19:52:42.619907 == TX Byte 0 ==
2978 19:52:42.626656 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2979 19:52:42.629789 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2980 19:52:42.629884 == TX Byte 1 ==
2981 19:52:42.636610 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2982 19:52:42.640067 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2983 19:52:42.640168 ==
2984 19:52:42.643035 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 19:52:42.646269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 19:52:42.646364 ==
2987 19:52:42.659150 TX Vref=22, minBit 8, minWin=25, winSum=416
2988 19:52:42.662637 TX Vref=24, minBit 1, minWin=26, winSum=427
2989 19:52:42.665811 TX Vref=26, minBit 13, minWin=26, winSum=430
2990 19:52:42.669344 TX Vref=28, minBit 1, minWin=26, winSum=428
2991 19:52:42.672554 TX Vref=30, minBit 10, minWin=26, winSum=432
2992 19:52:42.679218 TX Vref=32, minBit 10, minWin=26, winSum=434
2993 19:52:42.682309 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 32
2994 19:52:42.682440
2995 19:52:42.685800 Final TX Range 1 Vref 32
2996 19:52:42.685902
2997 19:52:42.685993 ==
2998 19:52:42.689365 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 19:52:42.695750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 19:52:42.695837 ==
3001 19:52:42.695898
3002 19:52:42.695956
3003 19:52:42.696011 TX Vref Scan disable
3004 19:52:42.699490 == TX Byte 0 ==
3005 19:52:42.702628 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3006 19:52:42.709523 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3007 19:52:42.709619 == TX Byte 1 ==
3008 19:52:42.712861 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3009 19:52:42.719082 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3010 19:52:42.719183
3011 19:52:42.719275 [DATLAT]
3012 19:52:42.719362 Freq=1200, CH0 RK1
3013 19:52:42.719449
3014 19:52:42.722377 DATLAT Default: 0xd
3015 19:52:42.726164 0, 0xFFFF, sum = 0
3016 19:52:42.726263 1, 0xFFFF, sum = 0
3017 19:52:42.728809 2, 0xFFFF, sum = 0
3018 19:52:42.728904 3, 0xFFFF, sum = 0
3019 19:52:42.732284 4, 0xFFFF, sum = 0
3020 19:52:42.732351 5, 0xFFFF, sum = 0
3021 19:52:42.735374 6, 0xFFFF, sum = 0
3022 19:52:42.735440 7, 0xFFFF, sum = 0
3023 19:52:42.739002 8, 0xFFFF, sum = 0
3024 19:52:42.739097 9, 0xFFFF, sum = 0
3025 19:52:42.742846 10, 0xFFFF, sum = 0
3026 19:52:42.742942 11, 0xFFFF, sum = 0
3027 19:52:42.745506 12, 0x0, sum = 1
3028 19:52:42.745578 13, 0x0, sum = 2
3029 19:52:42.748911 14, 0x0, sum = 3
3030 19:52:42.749009 15, 0x0, sum = 4
3031 19:52:42.752067 best_step = 13
3032 19:52:42.752134
3033 19:52:42.752192 ==
3034 19:52:42.755191 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 19:52:42.759017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 19:52:42.759089 ==
3037 19:52:42.762078 RX Vref Scan: 0
3038 19:52:42.762145
3039 19:52:42.762204 RX Vref 0 -> 0, step: 1
3040 19:52:42.762263
3041 19:52:42.765521 RX Delay -21 -> 252, step: 4
3042 19:52:42.772408 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3043 19:52:42.775396 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3044 19:52:42.778781 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3045 19:52:42.781891 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3046 19:52:42.785181 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3047 19:52:42.792272 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3048 19:52:42.795464 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3049 19:52:42.798466 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3050 19:52:42.801928 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3051 19:52:42.805969 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3052 19:52:42.811975 iDelay=199, Bit 10, Center 112 (43 ~ 182) 140
3053 19:52:42.814997 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3054 19:52:42.818892 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3055 19:52:42.822012 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3056 19:52:42.825165 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3057 19:52:42.831661 iDelay=199, Bit 15, Center 118 (55 ~ 182) 128
3058 19:52:42.831811 ==
3059 19:52:42.835061 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 19:52:42.838373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 19:52:42.838448 ==
3062 19:52:42.838507 DQS Delay:
3063 19:52:42.841802 DQS0 = 0, DQS1 = 0
3064 19:52:42.841869 DQM Delay:
3065 19:52:42.844837 DQM0 = 116, DQM1 = 109
3066 19:52:42.844905 DQ Delay:
3067 19:52:42.848677 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3068 19:52:42.852177 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3069 19:52:42.855116 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =104
3070 19:52:42.858260 DQ12 =116, DQ13 =114, DQ14 =120, DQ15 =118
3071 19:52:42.858335
3072 19:52:42.858396
3073 19:52:42.868462 [DQSOSCAuto] RK1, (LSB)MR18= 0xde7, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3074 19:52:42.871491 CH0 RK1: MR19=403, MR18=DE7
3075 19:52:42.875040 CH0_RK1: MR19=0x403, MR18=0xDE7, DQSOSC=405, MR23=63, INC=39, DEC=26
3076 19:52:42.878264 [RxdqsGatingPostProcess] freq 1200
3077 19:52:42.884615 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3078 19:52:42.888394 best DQS0 dly(2T, 0.5T) = (0, 11)
3079 19:52:42.891031 best DQS1 dly(2T, 0.5T) = (0, 12)
3080 19:52:42.894350 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3081 19:52:42.898513 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3082 19:52:42.900921 best DQS0 dly(2T, 0.5T) = (0, 11)
3083 19:52:42.904644 best DQS1 dly(2T, 0.5T) = (0, 12)
3084 19:52:42.907694 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3085 19:52:42.911250 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3086 19:52:42.914265 Pre-setting of DQS Precalculation
3087 19:52:42.918131 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3088 19:52:42.918205 ==
3089 19:52:42.921288 Dram Type= 6, Freq= 0, CH_1, rank 0
3090 19:52:42.924277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 19:52:42.924347 ==
3092 19:52:42.930825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3093 19:52:42.937650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3094 19:52:42.945598 [CA 0] Center 37 (7~68) winsize 62
3095 19:52:42.949021 [CA 1] Center 38 (8~68) winsize 61
3096 19:52:42.952095 [CA 2] Center 34 (4~64) winsize 61
3097 19:52:42.955151 [CA 3] Center 33 (3~64) winsize 62
3098 19:52:42.958988 [CA 4] Center 34 (4~64) winsize 61
3099 19:52:42.962381 [CA 5] Center 33 (3~64) winsize 62
3100 19:52:42.962457
3101 19:52:42.965382 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3102 19:52:42.965451
3103 19:52:42.968671 [CATrainingPosCal] consider 1 rank data
3104 19:52:42.971754 u2DelayCellTimex100 = 270/100 ps
3105 19:52:42.975123 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3106 19:52:42.981732 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3107 19:52:42.985287 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 19:52:42.988489 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3109 19:52:42.991714 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3110 19:52:42.995451 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3111 19:52:42.995525
3112 19:52:42.998596 CA PerBit enable=1, Macro0, CA PI delay=33
3113 19:52:42.998664
3114 19:52:43.001701 [CBTSetCACLKResult] CA Dly = 33
3115 19:52:43.001773 CS Dly: 5 (0~36)
3116 19:52:43.005228 ==
3117 19:52:43.008193 Dram Type= 6, Freq= 0, CH_1, rank 1
3118 19:52:43.011719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 19:52:43.011833 ==
3120 19:52:43.014922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3121 19:52:43.021776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3122 19:52:43.031238 [CA 0] Center 37 (7~68) winsize 62
3123 19:52:43.034203 [CA 1] Center 38 (8~68) winsize 61
3124 19:52:43.038181 [CA 2] Center 34 (4~65) winsize 62
3125 19:52:43.040894 [CA 3] Center 33 (3~64) winsize 62
3126 19:52:43.044552 [CA 4] Center 34 (3~65) winsize 63
3127 19:52:43.047960 [CA 5] Center 33 (3~64) winsize 62
3128 19:52:43.048036
3129 19:52:43.050864 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3130 19:52:43.050933
3131 19:52:43.054403 [CATrainingPosCal] consider 2 rank data
3132 19:52:43.057443 u2DelayCellTimex100 = 270/100 ps
3133 19:52:43.060899 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3134 19:52:43.067301 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3135 19:52:43.070675 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3136 19:52:43.073970 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3137 19:52:43.077384 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3138 19:52:43.081330 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3139 19:52:43.081410
3140 19:52:43.083937 CA PerBit enable=1, Macro0, CA PI delay=33
3141 19:52:43.084034
3142 19:52:43.087352 [CBTSetCACLKResult] CA Dly = 33
3143 19:52:43.087422 CS Dly: 7 (0~40)
3144 19:52:43.087481
3145 19:52:43.094413 ----->DramcWriteLeveling(PI) begin...
3146 19:52:43.094493 ==
3147 19:52:43.097315 Dram Type= 6, Freq= 0, CH_1, rank 0
3148 19:52:43.100522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3149 19:52:43.100592 ==
3150 19:52:43.104006 Write leveling (Byte 0): 25 => 25
3151 19:52:43.107770 Write leveling (Byte 1): 28 => 28
3152 19:52:43.110857 DramcWriteLeveling(PI) end<-----
3153 19:52:43.110928
3154 19:52:43.110987 ==
3155 19:52:43.114092 Dram Type= 6, Freq= 0, CH_1, rank 0
3156 19:52:43.117182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 19:52:43.117254 ==
3158 19:52:43.120829 [Gating] SW mode calibration
3159 19:52:43.127382 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3160 19:52:43.134309 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3161 19:52:43.137807 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3162 19:52:43.140613 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 19:52:43.147624 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 19:52:43.150562 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 19:52:43.153631 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 19:52:43.160269 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 19:52:43.164100 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
3168 19:52:43.167159 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
3169 19:52:43.170383 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 19:52:43.177288 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 19:52:43.180698 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 19:52:43.184317 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 19:52:43.190560 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 19:52:43.193655 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 19:52:43.196939 1 0 24 | B1->B0 | 2928 3a3a | 1 0 | (0 0) (0 0)
3176 19:52:43.203951 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 19:52:43.207311 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 19:52:43.210507 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 19:52:43.217187 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 19:52:43.220815 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 19:52:43.223831 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 19:52:43.230785 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 19:52:43.233728 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3184 19:52:43.236769 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3185 19:52:43.243540 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 19:52:43.246963 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 19:52:43.249875 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 19:52:43.256829 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 19:52:43.259947 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 19:52:43.263064 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 19:52:43.269584 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 19:52:43.273128 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 19:52:43.276253 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 19:52:43.283152 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 19:52:43.286531 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 19:52:43.289967 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 19:52:43.296257 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 19:52:43.299634 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 19:52:43.302855 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3200 19:52:43.309642 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3201 19:52:43.313354 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 19:52:43.316193 Total UI for P1: 0, mck2ui 16
3203 19:52:43.319897 best dqsien dly found for B0: ( 1, 3, 26)
3204 19:52:43.322778 Total UI for P1: 0, mck2ui 16
3205 19:52:43.326388 best dqsien dly found for B1: ( 1, 3, 28)
3206 19:52:43.329642 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3207 19:52:43.333098 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3208 19:52:43.333170
3209 19:52:43.336383 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3210 19:52:43.339612 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3211 19:52:43.342767 [Gating] SW calibration Done
3212 19:52:43.342834 ==
3213 19:52:43.346619 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 19:52:43.349826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 19:52:43.349925 ==
3216 19:52:43.353002 RX Vref Scan: 0
3217 19:52:43.353106
3218 19:52:43.356597 RX Vref 0 -> 0, step: 1
3219 19:52:43.356700
3220 19:52:43.356792 RX Delay -40 -> 252, step: 8
3221 19:52:43.362858 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3222 19:52:43.366368 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3223 19:52:43.369283 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3224 19:52:43.372821 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3225 19:52:43.376066 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3226 19:52:43.382744 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3227 19:52:43.386420 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3228 19:52:43.389468 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3229 19:52:43.392574 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3230 19:52:43.396040 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3231 19:52:43.402959 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3232 19:52:43.405634 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3233 19:52:43.408898 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3234 19:52:43.412681 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3235 19:52:43.415629 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3236 19:52:43.422299 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3237 19:52:43.422395 ==
3238 19:52:43.425985 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 19:52:43.428980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 19:52:43.429053 ==
3241 19:52:43.429121 DQS Delay:
3242 19:52:43.432739 DQS0 = 0, DQS1 = 0
3243 19:52:43.432815 DQM Delay:
3244 19:52:43.435664 DQM0 = 117, DQM1 = 109
3245 19:52:43.435758 DQ Delay:
3246 19:52:43.439212 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3247 19:52:43.442911 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3248 19:52:43.446020 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3249 19:52:43.449521 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3250 19:52:43.449593
3251 19:52:43.449653
3252 19:52:43.452572 ==
3253 19:52:43.455705 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 19:52:43.458887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 19:52:43.458959 ==
3256 19:52:43.459019
3257 19:52:43.459077
3258 19:52:43.462074 TX Vref Scan disable
3259 19:52:43.462146 == TX Byte 0 ==
3260 19:52:43.465903 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3261 19:52:43.472305 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3262 19:52:43.472378 == TX Byte 1 ==
3263 19:52:43.478902 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3264 19:52:43.481813 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3265 19:52:43.481888 ==
3266 19:52:43.485277 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 19:52:43.488752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 19:52:43.488832 ==
3269 19:52:43.500910 TX Vref=22, minBit 10, minWin=24, winSum=414
3270 19:52:43.504241 TX Vref=24, minBit 11, minWin=24, winSum=417
3271 19:52:43.507887 TX Vref=26, minBit 9, minWin=25, winSum=426
3272 19:52:43.511139 TX Vref=28, minBit 9, minWin=25, winSum=428
3273 19:52:43.514538 TX Vref=30, minBit 11, minWin=25, winSum=427
3274 19:52:43.520970 TX Vref=32, minBit 9, minWin=25, winSum=422
3275 19:52:43.524165 [TxChooseVref] Worse bit 9, Min win 25, Win sum 428, Final Vref 28
3276 19:52:43.524238
3277 19:52:43.527312 Final TX Range 1 Vref 28
3278 19:52:43.527381
3279 19:52:43.527446 ==
3280 19:52:43.530659 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 19:52:43.534145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 19:52:43.537221 ==
3283 19:52:43.537291
3284 19:52:43.537353
3285 19:52:43.537410 TX Vref Scan disable
3286 19:52:43.541075 == TX Byte 0 ==
3287 19:52:43.544443 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3288 19:52:43.550646 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3289 19:52:43.550718 == TX Byte 1 ==
3290 19:52:43.554234 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3291 19:52:43.560735 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3292 19:52:43.560817
3293 19:52:43.560880 [DATLAT]
3294 19:52:43.560938 Freq=1200, CH1 RK0
3295 19:52:43.560995
3296 19:52:43.564103 DATLAT Default: 0xd
3297 19:52:43.567375 0, 0xFFFF, sum = 0
3298 19:52:43.567446 1, 0xFFFF, sum = 0
3299 19:52:43.570614 2, 0xFFFF, sum = 0
3300 19:52:43.570683 3, 0xFFFF, sum = 0
3301 19:52:43.573859 4, 0xFFFF, sum = 0
3302 19:52:43.573932 5, 0xFFFF, sum = 0
3303 19:52:43.577257 6, 0xFFFF, sum = 0
3304 19:52:43.577330 7, 0xFFFF, sum = 0
3305 19:52:43.580800 8, 0xFFFF, sum = 0
3306 19:52:43.580873 9, 0xFFFF, sum = 0
3307 19:52:43.583919 10, 0xFFFF, sum = 0
3308 19:52:43.583989 11, 0xFFFF, sum = 0
3309 19:52:43.587173 12, 0x0, sum = 1
3310 19:52:43.587242 13, 0x0, sum = 2
3311 19:52:43.590649 14, 0x0, sum = 3
3312 19:52:43.590757 15, 0x0, sum = 4
3313 19:52:43.593780 best_step = 13
3314 19:52:43.593849
3315 19:52:43.593907 ==
3316 19:52:43.597411 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 19:52:43.600305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 19:52:43.600374 ==
3319 19:52:43.604233 RX Vref Scan: 1
3320 19:52:43.604338
3321 19:52:43.604400 Set Vref Range= 32 -> 127
3322 19:52:43.604457
3323 19:52:43.606954 RX Vref 32 -> 127, step: 1
3324 19:52:43.607027
3325 19:52:43.610382 RX Delay -21 -> 252, step: 4
3326 19:52:43.610458
3327 19:52:43.613747 Set Vref, RX VrefLevel [Byte0]: 32
3328 19:52:43.617073 [Byte1]: 32
3329 19:52:43.617142
3330 19:52:43.621141 Set Vref, RX VrefLevel [Byte0]: 33
3331 19:52:43.623962 [Byte1]: 33
3332 19:52:43.627573
3333 19:52:43.627681 Set Vref, RX VrefLevel [Byte0]: 34
3334 19:52:43.630750 [Byte1]: 34
3335 19:52:43.635461
3336 19:52:43.635538 Set Vref, RX VrefLevel [Byte0]: 35
3337 19:52:43.638384 [Byte1]: 35
3338 19:52:43.643150
3339 19:52:43.643219 Set Vref, RX VrefLevel [Byte0]: 36
3340 19:52:43.647063 [Byte1]: 36
3341 19:52:43.651311
3342 19:52:43.651385 Set Vref, RX VrefLevel [Byte0]: 37
3343 19:52:43.654295 [Byte1]: 37
3344 19:52:43.659199
3345 19:52:43.659274 Set Vref, RX VrefLevel [Byte0]: 38
3346 19:52:43.662750 [Byte1]: 38
3347 19:52:43.667085
3348 19:52:43.667157 Set Vref, RX VrefLevel [Byte0]: 39
3349 19:52:43.670393 [Byte1]: 39
3350 19:52:43.675404
3351 19:52:43.675480 Set Vref, RX VrefLevel [Byte0]: 40
3352 19:52:43.678676 [Byte1]: 40
3353 19:52:43.682603
3354 19:52:43.682707 Set Vref, RX VrefLevel [Byte0]: 41
3355 19:52:43.686055 [Byte1]: 41
3356 19:52:43.690748
3357 19:52:43.690825 Set Vref, RX VrefLevel [Byte0]: 42
3358 19:52:43.693884 [Byte1]: 42
3359 19:52:43.698572
3360 19:52:43.698665 Set Vref, RX VrefLevel [Byte0]: 43
3361 19:52:43.701885 [Byte1]: 43
3362 19:52:43.706597
3363 19:52:43.706695 Set Vref, RX VrefLevel [Byte0]: 44
3364 19:52:43.709669 [Byte1]: 44
3365 19:52:43.714499
3366 19:52:43.714593 Set Vref, RX VrefLevel [Byte0]: 45
3367 19:52:43.718156 [Byte1]: 45
3368 19:52:43.722178
3369 19:52:43.722243 Set Vref, RX VrefLevel [Byte0]: 46
3370 19:52:43.725640 [Byte1]: 46
3371 19:52:43.730012
3372 19:52:43.730084 Set Vref, RX VrefLevel [Byte0]: 47
3373 19:52:43.733784 [Byte1]: 47
3374 19:52:43.738027
3375 19:52:43.738096 Set Vref, RX VrefLevel [Byte0]: 48
3376 19:52:43.741909 [Byte1]: 48
3377 19:52:43.746254
3378 19:52:43.746325 Set Vref, RX VrefLevel [Byte0]: 49
3379 19:52:43.749333 [Byte1]: 49
3380 19:52:43.754075
3381 19:52:43.754144 Set Vref, RX VrefLevel [Byte0]: 50
3382 19:52:43.757626 [Byte1]: 50
3383 19:52:43.762046
3384 19:52:43.762145 Set Vref, RX VrefLevel [Byte0]: 51
3385 19:52:43.765069 [Byte1]: 51
3386 19:52:43.769801
3387 19:52:43.769898 Set Vref, RX VrefLevel [Byte0]: 52
3388 19:52:43.773052 [Byte1]: 52
3389 19:52:43.777922
3390 19:52:43.778019 Set Vref, RX VrefLevel [Byte0]: 53
3391 19:52:43.781044 [Byte1]: 53
3392 19:52:43.785609
3393 19:52:43.785681 Set Vref, RX VrefLevel [Byte0]: 54
3394 19:52:43.788759 [Byte1]: 54
3395 19:52:43.794140
3396 19:52:43.794241 Set Vref, RX VrefLevel [Byte0]: 55
3397 19:52:43.798290 [Byte1]: 55
3398 19:52:43.801399
3399 19:52:43.801478 Set Vref, RX VrefLevel [Byte0]: 56
3400 19:52:43.804893 [Byte1]: 56
3401 19:52:43.809490
3402 19:52:43.809562 Set Vref, RX VrefLevel [Byte0]: 57
3403 19:52:43.812515 [Byte1]: 57
3404 19:52:43.817367
3405 19:52:43.817439 Set Vref, RX VrefLevel [Byte0]: 58
3406 19:52:43.820630 [Byte1]: 58
3407 19:52:43.825365
3408 19:52:43.825435 Set Vref, RX VrefLevel [Byte0]: 59
3409 19:52:43.828399 [Byte1]: 59
3410 19:52:43.832974
3411 19:52:43.833050 Set Vref, RX VrefLevel [Byte0]: 60
3412 19:52:43.839458 [Byte1]: 60
3413 19:52:43.839533
3414 19:52:43.843284 Set Vref, RX VrefLevel [Byte0]: 61
3415 19:52:43.846665 [Byte1]: 61
3416 19:52:43.846742
3417 19:52:43.849830 Set Vref, RX VrefLevel [Byte0]: 62
3418 19:52:43.853100 [Byte1]: 62
3419 19:52:43.857257
3420 19:52:43.857337 Set Vref, RX VrefLevel [Byte0]: 63
3421 19:52:43.860467 [Byte1]: 63
3422 19:52:43.864728
3423 19:52:43.864802 Set Vref, RX VrefLevel [Byte0]: 64
3424 19:52:43.868205 [Byte1]: 64
3425 19:52:43.872915
3426 19:52:43.872983 Set Vref, RX VrefLevel [Byte0]: 65
3427 19:52:43.876760 [Byte1]: 65
3428 19:52:43.881283
3429 19:52:43.881388 Set Vref, RX VrefLevel [Byte0]: 66
3430 19:52:43.883979 [Byte1]: 66
3431 19:52:43.888804
3432 19:52:43.888900 Set Vref, RX VrefLevel [Byte0]: 67
3433 19:52:43.891902 [Byte1]: 67
3434 19:52:43.896705
3435 19:52:43.896814 Set Vref, RX VrefLevel [Byte0]: 68
3436 19:52:43.899638 [Byte1]: 68
3437 19:52:43.904420
3438 19:52:43.904524 Final RX Vref Byte 0 = 50 to rank0
3439 19:52:43.907978 Final RX Vref Byte 1 = 53 to rank0
3440 19:52:43.911004 Final RX Vref Byte 0 = 50 to rank1
3441 19:52:43.914452 Final RX Vref Byte 1 = 53 to rank1==
3442 19:52:43.917875 Dram Type= 6, Freq= 0, CH_1, rank 0
3443 19:52:43.924377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3444 19:52:43.924577 ==
3445 19:52:43.924733 DQS Delay:
3446 19:52:43.924889 DQS0 = 0, DQS1 = 0
3447 19:52:43.927895 DQM Delay:
3448 19:52:43.928098 DQM0 = 115, DQM1 = 110
3449 19:52:43.931092 DQ Delay:
3450 19:52:43.934801 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =110
3451 19:52:43.937819 DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =112
3452 19:52:43.941868 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3453 19:52:43.944898 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3454 19:52:43.945294
3455 19:52:43.945644
3456 19:52:43.951508 [DQSOSCAuto] RK0, (LSB)MR18= 0x7fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3457 19:52:43.954536 CH1 RK0: MR19=403, MR18=7FB
3458 19:52:43.961054 CH1_RK0: MR19=0x403, MR18=0x7FB, DQSOSC=407, MR23=63, INC=39, DEC=26
3459 19:52:43.961483
3460 19:52:43.965108 ----->DramcWriteLeveling(PI) begin...
3461 19:52:43.965507 ==
3462 19:52:43.967950 Dram Type= 6, Freq= 0, CH_1, rank 1
3463 19:52:43.971208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3464 19:52:43.974726 ==
3465 19:52:43.975171 Write leveling (Byte 0): 27 => 27
3466 19:52:43.977911 Write leveling (Byte 1): 28 => 28
3467 19:52:43.981493 DramcWriteLeveling(PI) end<-----
3468 19:52:43.982055
3469 19:52:43.982418 ==
3470 19:52:43.984558 Dram Type= 6, Freq= 0, CH_1, rank 1
3471 19:52:43.991049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3472 19:52:43.991480 ==
3473 19:52:43.994451 [Gating] SW mode calibration
3474 19:52:44.000976 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3475 19:52:44.004161 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3476 19:52:44.011091 0 15 0 | B1->B0 | 3333 3232 | 1 0 | (1 1) (0 0)
3477 19:52:44.014276 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 19:52:44.017323 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 19:52:44.024481 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 19:52:44.027487 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 19:52:44.030961 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 19:52:44.037354 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3483 19:52:44.040571 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 0)
3484 19:52:44.043809 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 19:52:44.050500 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 19:52:44.053687 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 19:52:44.057406 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 19:52:44.063673 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 19:52:44.067377 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 19:52:44.070184 1 0 24 | B1->B0 | 3939 2929 | 1 0 | (1 1) (0 0)
3491 19:52:44.076978 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3492 19:52:44.080873 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 19:52:44.083835 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 19:52:44.090645 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 19:52:44.093394 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 19:52:44.096827 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 19:52:44.100250 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 19:52:44.106894 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3499 19:52:44.110508 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3500 19:52:44.113244 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 19:52:44.119874 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 19:52:44.123232 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 19:52:44.126788 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 19:52:44.133301 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 19:52:44.136902 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 19:52:44.139869 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 19:52:44.147079 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 19:52:44.149724 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 19:52:44.153033 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 19:52:44.160104 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 19:52:44.162930 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 19:52:44.166085 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 19:52:44.172701 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 19:52:44.176316 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3515 19:52:44.179467 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3516 19:52:44.186235 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 19:52:44.189625 Total UI for P1: 0, mck2ui 16
3518 19:52:44.192456 best dqsien dly found for B0: ( 1, 3, 28)
3519 19:52:44.195953 Total UI for P1: 0, mck2ui 16
3520 19:52:44.199174 best dqsien dly found for B1: ( 1, 3, 26)
3521 19:52:44.203015 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3522 19:52:44.205719 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3523 19:52:44.206277
3524 19:52:44.209408 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3525 19:52:44.212292 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3526 19:52:44.215863 [Gating] SW calibration Done
3527 19:52:44.216307 ==
3528 19:52:44.219355 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 19:52:44.222655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 19:52:44.223083 ==
3531 19:52:44.225998 RX Vref Scan: 0
3532 19:52:44.226439
3533 19:52:44.228956 RX Vref 0 -> 0, step: 1
3534 19:52:44.229397
3535 19:52:44.229763 RX Delay -40 -> 252, step: 8
3536 19:52:44.235370 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3537 19:52:44.238919 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3538 19:52:44.241982 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3539 19:52:44.245362 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3540 19:52:44.248475 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3541 19:52:44.255464 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3542 19:52:44.258525 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3543 19:52:44.261605 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3544 19:52:44.264956 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3545 19:52:44.268404 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3546 19:52:44.274828 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3547 19:52:44.278300 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3548 19:52:44.281871 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3549 19:52:44.284898 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3550 19:52:44.291312 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3551 19:52:44.294732 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3552 19:52:44.295272 ==
3553 19:52:44.297929 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 19:52:44.301304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 19:52:44.301749 ==
3556 19:52:44.304443 DQS Delay:
3557 19:52:44.304882 DQS0 = 0, DQS1 = 0
3558 19:52:44.305252 DQM Delay:
3559 19:52:44.308058 DQM0 = 115, DQM1 = 110
3560 19:52:44.308490 DQ Delay:
3561 19:52:44.311193 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3562 19:52:44.314570 DQ4 =115, DQ5 =123, DQ6 =127, DQ7 =115
3563 19:52:44.317881 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3564 19:52:44.324310 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3565 19:52:44.324788
3566 19:52:44.325127
3567 19:52:44.325464 ==
3568 19:52:44.327676 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 19:52:44.331542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 19:52:44.332007 ==
3571 19:52:44.332361
3572 19:52:44.332691
3573 19:52:44.334657 TX Vref Scan disable
3574 19:52:44.335097 == TX Byte 0 ==
3575 19:52:44.340829 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3576 19:52:44.344091 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3577 19:52:44.344526 == TX Byte 1 ==
3578 19:52:44.350872 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3579 19:52:44.354223 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3580 19:52:44.354656 ==
3581 19:52:44.357628 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 19:52:44.360752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 19:52:44.361193 ==
3584 19:52:44.373760 TX Vref=22, minBit 0, minWin=26, winSum=420
3585 19:52:44.376675 TX Vref=24, minBit 9, minWin=25, winSum=430
3586 19:52:44.380496 TX Vref=26, minBit 9, minWin=26, winSum=430
3587 19:52:44.383436 TX Vref=28, minBit 9, minWin=26, winSum=427
3588 19:52:44.386810 TX Vref=30, minBit 9, minWin=26, winSum=433
3589 19:52:44.393882 TX Vref=32, minBit 9, minWin=26, winSum=433
3590 19:52:44.396403 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3591 19:52:44.396837
3592 19:52:44.400071 Final TX Range 1 Vref 30
3593 19:52:44.400511
3594 19:52:44.400909 ==
3595 19:52:44.403084 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 19:52:44.406541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 19:52:44.410354 ==
3598 19:52:44.410811
3599 19:52:44.411242
3600 19:52:44.411774 TX Vref Scan disable
3601 19:52:44.413565 == TX Byte 0 ==
3602 19:52:44.416916 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3603 19:52:44.423348 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3604 19:52:44.423862 == TX Byte 1 ==
3605 19:52:44.426521 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3606 19:52:44.433070 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3607 19:52:44.433503
3608 19:52:44.433849 [DATLAT]
3609 19:52:44.434185 Freq=1200, CH1 RK1
3610 19:52:44.434508
3611 19:52:44.436422 DATLAT Default: 0xd
3612 19:52:44.439946 0, 0xFFFF, sum = 0
3613 19:52:44.440450 1, 0xFFFF, sum = 0
3614 19:52:44.443111 2, 0xFFFF, sum = 0
3615 19:52:44.443710 3, 0xFFFF, sum = 0
3616 19:52:44.446422 4, 0xFFFF, sum = 0
3617 19:52:44.446978 5, 0xFFFF, sum = 0
3618 19:52:44.449736 6, 0xFFFF, sum = 0
3619 19:52:44.450305 7, 0xFFFF, sum = 0
3620 19:52:44.452945 8, 0xFFFF, sum = 0
3621 19:52:44.453412 9, 0xFFFF, sum = 0
3622 19:52:44.455880 10, 0xFFFF, sum = 0
3623 19:52:44.456313 11, 0xFFFF, sum = 0
3624 19:52:44.459566 12, 0x0, sum = 1
3625 19:52:44.460098 13, 0x0, sum = 2
3626 19:52:44.462685 14, 0x0, sum = 3
3627 19:52:44.463144 15, 0x0, sum = 4
3628 19:52:44.465846 best_step = 13
3629 19:52:44.466553
3630 19:52:44.467118 ==
3631 19:52:44.469279 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 19:52:44.472464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 19:52:44.473060 ==
3634 19:52:44.476012 RX Vref Scan: 0
3635 19:52:44.476405
3636 19:52:44.476783 RX Vref 0 -> 0, step: 1
3637 19:52:44.477174
3638 19:52:44.479014 RX Delay -21 -> 252, step: 4
3639 19:52:44.485510 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3640 19:52:44.489002 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3641 19:52:44.492219 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3642 19:52:44.495977 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3643 19:52:44.498779 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3644 19:52:44.505411 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3645 19:52:44.509165 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3646 19:52:44.512390 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3647 19:52:44.515136 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3648 19:52:44.519085 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3649 19:52:44.525411 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3650 19:52:44.528499 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3651 19:52:44.531661 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3652 19:52:44.534816 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3653 19:52:44.541645 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3654 19:52:44.544924 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3655 19:52:44.545361 ==
3656 19:52:44.548196 Dram Type= 6, Freq= 0, CH_1, rank 1
3657 19:52:44.551202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3658 19:52:44.551639 ==
3659 19:52:44.554604 DQS Delay:
3660 19:52:44.555038 DQS0 = 0, DQS1 = 0
3661 19:52:44.555404 DQM Delay:
3662 19:52:44.558087 DQM0 = 117, DQM1 = 110
3663 19:52:44.558711 DQ Delay:
3664 19:52:44.561753 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3665 19:52:44.564461 DQ4 =116, DQ5 =128, DQ6 =130, DQ7 =116
3666 19:52:44.571098 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3667 19:52:44.574715 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3668 19:52:44.575223
3669 19:52:44.575580
3670 19:52:44.581287 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8f3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
3671 19:52:44.584747 CH1 RK1: MR19=303, MR18=F8F3
3672 19:52:44.590890 CH1_RK1: MR19=0x303, MR18=0xF8F3, DQSOSC=413, MR23=63, INC=38, DEC=25
3673 19:52:44.594563 [RxdqsGatingPostProcess] freq 1200
3674 19:52:44.600804 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3675 19:52:44.601238 best DQS0 dly(2T, 0.5T) = (0, 11)
3676 19:52:44.604125 best DQS1 dly(2T, 0.5T) = (0, 11)
3677 19:52:44.607234 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3678 19:52:44.610826 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3679 19:52:44.614133 best DQS0 dly(2T, 0.5T) = (0, 11)
3680 19:52:44.617400 best DQS1 dly(2T, 0.5T) = (0, 11)
3681 19:52:44.620881 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3682 19:52:44.623797 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3683 19:52:44.627389 Pre-setting of DQS Precalculation
3684 19:52:44.634704 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3685 19:52:44.640528 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3686 19:52:44.647223 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3687 19:52:44.647820
3688 19:52:44.648348
3689 19:52:44.650046 [Calibration Summary] 2400 Mbps
3690 19:52:44.650474 CH 0, Rank 0
3691 19:52:44.653309 SW Impedance : PASS
3692 19:52:44.657569 DUTY Scan : NO K
3693 19:52:44.658016 ZQ Calibration : PASS
3694 19:52:44.660317 Jitter Meter : NO K
3695 19:52:44.663283 CBT Training : PASS
3696 19:52:44.663767 Write leveling : PASS
3697 19:52:44.666754 RX DQS gating : PASS
3698 19:52:44.670166 RX DQ/DQS(RDDQC) : PASS
3699 19:52:44.670727 TX DQ/DQS : PASS
3700 19:52:44.673297 RX DATLAT : PASS
3701 19:52:44.677039 RX DQ/DQS(Engine): PASS
3702 19:52:44.677463 TX OE : NO K
3703 19:52:44.677818 All Pass.
3704 19:52:44.680353
3705 19:52:44.680800 CH 0, Rank 1
3706 19:52:44.683004 SW Impedance : PASS
3707 19:52:44.683453 DUTY Scan : NO K
3708 19:52:44.686450 ZQ Calibration : PASS
3709 19:52:44.686877 Jitter Meter : NO K
3710 19:52:44.689771 CBT Training : PASS
3711 19:52:44.693260 Write leveling : PASS
3712 19:52:44.693686 RX DQS gating : PASS
3713 19:52:44.696557 RX DQ/DQS(RDDQC) : PASS
3714 19:52:44.699780 TX DQ/DQS : PASS
3715 19:52:44.700227 RX DATLAT : PASS
3716 19:52:44.703217 RX DQ/DQS(Engine): PASS
3717 19:52:44.706706 TX OE : NO K
3718 19:52:44.707267 All Pass.
3719 19:52:44.707612
3720 19:52:44.708149 CH 1, Rank 0
3721 19:52:44.709572 SW Impedance : PASS
3722 19:52:44.712676 DUTY Scan : NO K
3723 19:52:44.713199 ZQ Calibration : PASS
3724 19:52:44.716609 Jitter Meter : NO K
3725 19:52:44.719754 CBT Training : PASS
3726 19:52:44.720197 Write leveling : PASS
3727 19:52:44.722756 RX DQS gating : PASS
3728 19:52:44.726139 RX DQ/DQS(RDDQC) : PASS
3729 19:52:44.726565 TX DQ/DQS : PASS
3730 19:52:44.729862 RX DATLAT : PASS
3731 19:52:44.732739 RX DQ/DQS(Engine): PASS
3732 19:52:44.733183 TX OE : NO K
3733 19:52:44.736037 All Pass.
3734 19:52:44.736568
3735 19:52:44.736930 CH 1, Rank 1
3736 19:52:44.739303 SW Impedance : PASS
3737 19:52:44.739775 DUTY Scan : NO K
3738 19:52:44.742578 ZQ Calibration : PASS
3739 19:52:44.745810 Jitter Meter : NO K
3740 19:52:44.746252 CBT Training : PASS
3741 19:52:44.749580 Write leveling : PASS
3742 19:52:44.752619 RX DQS gating : PASS
3743 19:52:44.753042 RX DQ/DQS(RDDQC) : PASS
3744 19:52:44.755940 TX DQ/DQS : PASS
3745 19:52:44.756501 RX DATLAT : PASS
3746 19:52:44.759116 RX DQ/DQS(Engine): PASS
3747 19:52:44.763126 TX OE : NO K
3748 19:52:44.763559 All Pass.
3749 19:52:44.764018
3750 19:52:44.765715 DramC Write-DBI off
3751 19:52:44.768941 PER_BANK_REFRESH: Hybrid Mode
3752 19:52:44.769368 TX_TRACKING: ON
3753 19:52:44.779012 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3754 19:52:44.782178 [FAST_K] Save calibration result to emmc
3755 19:52:44.785295 dramc_set_vcore_voltage set vcore to 650000
3756 19:52:44.789614 Read voltage for 600, 5
3757 19:52:44.790041 Vio18 = 0
3758 19:52:44.790394 Vcore = 650000
3759 19:52:44.792107 Vdram = 0
3760 19:52:44.792538 Vddq = 0
3761 19:52:44.792895 Vmddr = 0
3762 19:52:44.798488 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3763 19:52:44.801640 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3764 19:52:44.805141 MEM_TYPE=3, freq_sel=19
3765 19:52:44.808527 sv_algorithm_assistance_LP4_1600
3766 19:52:44.812074 ============ PULL DRAM RESETB DOWN ============
3767 19:52:44.815610 ========== PULL DRAM RESETB DOWN end =========
3768 19:52:44.821847 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3769 19:52:44.824912 ===================================
3770 19:52:44.828048 LPDDR4 DRAM CONFIGURATION
3771 19:52:44.831478 ===================================
3772 19:52:44.832073 EX_ROW_EN[0] = 0x0
3773 19:52:44.834905 EX_ROW_EN[1] = 0x0
3774 19:52:44.835328 LP4Y_EN = 0x0
3775 19:52:44.838276 WORK_FSP = 0x0
3776 19:52:44.838766 WL = 0x2
3777 19:52:44.841480 RL = 0x2
3778 19:52:44.842010 BL = 0x2
3779 19:52:44.844751 RPST = 0x0
3780 19:52:44.845359 RD_PRE = 0x0
3781 19:52:44.848142 WR_PRE = 0x1
3782 19:52:44.848570 WR_PST = 0x0
3783 19:52:44.851137 DBI_WR = 0x0
3784 19:52:44.851563 DBI_RD = 0x0
3785 19:52:44.854929 OTF = 0x1
3786 19:52:44.858211 ===================================
3787 19:52:44.861056 ===================================
3788 19:52:44.861498 ANA top config
3789 19:52:44.864598 ===================================
3790 19:52:44.867839 DLL_ASYNC_EN = 0
3791 19:52:44.870719 ALL_SLAVE_EN = 1
3792 19:52:44.874268 NEW_RANK_MODE = 1
3793 19:52:44.874375 DLL_IDLE_MODE = 1
3794 19:52:44.877924 LP45_APHY_COMB_EN = 1
3795 19:52:44.880571 TX_ODT_DIS = 1
3796 19:52:44.883869 NEW_8X_MODE = 1
3797 19:52:44.887450 ===================================
3798 19:52:44.890782 ===================================
3799 19:52:44.893801 data_rate = 1200
3800 19:52:44.897272 CKR = 1
3801 19:52:44.897343 DQ_P2S_RATIO = 8
3802 19:52:44.900297 ===================================
3803 19:52:44.903521 CA_P2S_RATIO = 8
3804 19:52:44.907375 DQ_CA_OPEN = 0
3805 19:52:44.910289 DQ_SEMI_OPEN = 0
3806 19:52:44.913747 CA_SEMI_OPEN = 0
3807 19:52:44.917057 CA_FULL_RATE = 0
3808 19:52:44.917154 DQ_CKDIV4_EN = 1
3809 19:52:44.920383 CA_CKDIV4_EN = 1
3810 19:52:44.923642 CA_PREDIV_EN = 0
3811 19:52:44.926790 PH8_DLY = 0
3812 19:52:44.930044 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3813 19:52:44.933473 DQ_AAMCK_DIV = 4
3814 19:52:44.933543 CA_AAMCK_DIV = 4
3815 19:52:44.937138 CA_ADMCK_DIV = 4
3816 19:52:44.940460 DQ_TRACK_CA_EN = 0
3817 19:52:44.943114 CA_PICK = 600
3818 19:52:44.946884 CA_MCKIO = 600
3819 19:52:44.949823 MCKIO_SEMI = 0
3820 19:52:44.952899 PLL_FREQ = 2288
3821 19:52:44.956524 DQ_UI_PI_RATIO = 32
3822 19:52:44.956595 CA_UI_PI_RATIO = 0
3823 19:52:44.959505 ===================================
3824 19:52:44.962944 ===================================
3825 19:52:44.966353 memory_type:LPDDR4
3826 19:52:44.969517 GP_NUM : 10
3827 19:52:44.969615 SRAM_EN : 1
3828 19:52:44.972757 MD32_EN : 0
3829 19:52:44.976018 ===================================
3830 19:52:44.979396 [ANA_INIT] >>>>>>>>>>>>>>
3831 19:52:44.982600 <<<<<< [CONFIGURE PHASE]: ANA_TX
3832 19:52:44.986291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3833 19:52:44.989806 ===================================
3834 19:52:44.989906 data_rate = 1200,PCW = 0X5800
3835 19:52:44.992848 ===================================
3836 19:52:44.996041 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3837 19:52:45.003276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3838 19:52:45.009169 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3839 19:52:45.012370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3840 19:52:45.016076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3841 19:52:45.019615 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3842 19:52:45.022420 [ANA_INIT] flow start
3843 19:52:45.025865 [ANA_INIT] PLL >>>>>>>>
3844 19:52:45.025965 [ANA_INIT] PLL <<<<<<<<
3845 19:52:45.029836 [ANA_INIT] MIDPI >>>>>>>>
3846 19:52:45.032404 [ANA_INIT] MIDPI <<<<<<<<
3847 19:52:45.032474 [ANA_INIT] DLL >>>>>>>>
3848 19:52:45.035856 [ANA_INIT] flow end
3849 19:52:45.038999 ============ LP4 DIFF to SE enter ============
3850 19:52:45.043015 ============ LP4 DIFF to SE exit ============
3851 19:52:45.045524 [ANA_INIT] <<<<<<<<<<<<<
3852 19:52:45.048955 [Flow] Enable top DCM control >>>>>
3853 19:52:45.052252 [Flow] Enable top DCM control <<<<<
3854 19:52:45.056164 Enable DLL master slave shuffle
3855 19:52:45.061952 ==============================================================
3856 19:52:45.062054 Gating Mode config
3857 19:52:45.069272 ==============================================================
3858 19:52:45.069365 Config description:
3859 19:52:45.078909 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3860 19:52:45.085276 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3861 19:52:45.092004 SELPH_MODE 0: By rank 1: By Phase
3862 19:52:45.098368 ==============================================================
3863 19:52:45.098469 GAT_TRACK_EN = 1
3864 19:52:45.101864 RX_GATING_MODE = 2
3865 19:52:45.104805 RX_GATING_TRACK_MODE = 2
3866 19:52:45.108349 SELPH_MODE = 1
3867 19:52:45.111637 PICG_EARLY_EN = 1
3868 19:52:45.114996 VALID_LAT_VALUE = 1
3869 19:52:45.121442 ==============================================================
3870 19:52:45.124582 Enter into Gating configuration >>>>
3871 19:52:45.127704 Exit from Gating configuration <<<<
3872 19:52:45.131654 Enter into DVFS_PRE_config >>>>>
3873 19:52:45.141318 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3874 19:52:45.144928 Exit from DVFS_PRE_config <<<<<
3875 19:52:45.147649 Enter into PICG configuration >>>>
3876 19:52:45.150989 Exit from PICG configuration <<<<
3877 19:52:45.154240 [RX_INPUT] configuration >>>>>
3878 19:52:45.157557 [RX_INPUT] configuration <<<<<
3879 19:52:45.161067 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3880 19:52:45.167990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3881 19:52:45.174246 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3882 19:52:45.180628 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3883 19:52:45.183884 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3884 19:52:45.190724 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3885 19:52:45.193800 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3886 19:52:45.200587 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3887 19:52:45.203971 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3888 19:52:45.207147 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3889 19:52:45.210601 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3890 19:52:45.217780 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3891 19:52:45.220584 ===================================
3892 19:52:45.223650 LPDDR4 DRAM CONFIGURATION
3893 19:52:45.226940 ===================================
3894 19:52:45.227033 EX_ROW_EN[0] = 0x0
3895 19:52:45.230316 EX_ROW_EN[1] = 0x0
3896 19:52:45.230386 LP4Y_EN = 0x0
3897 19:52:45.233702 WORK_FSP = 0x0
3898 19:52:45.233807 WL = 0x2
3899 19:52:45.236681 RL = 0x2
3900 19:52:45.236777 BL = 0x2
3901 19:52:45.240265 RPST = 0x0
3902 19:52:45.240335 RD_PRE = 0x0
3903 19:52:45.243474 WR_PRE = 0x1
3904 19:52:45.243541 WR_PST = 0x0
3905 19:52:45.246713 DBI_WR = 0x0
3906 19:52:45.246782 DBI_RD = 0x0
3907 19:52:45.250427 OTF = 0x1
3908 19:52:45.253860 ===================================
3909 19:52:45.256952 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3910 19:52:45.260181 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3911 19:52:45.267023 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3912 19:52:45.269772 ===================================
3913 19:52:45.269872 LPDDR4 DRAM CONFIGURATION
3914 19:52:45.273339 ===================================
3915 19:52:45.276359 EX_ROW_EN[0] = 0x10
3916 19:52:45.279693 EX_ROW_EN[1] = 0x0
3917 19:52:45.279827 LP4Y_EN = 0x0
3918 19:52:45.282787 WORK_FSP = 0x0
3919 19:52:45.282857 WL = 0x2
3920 19:52:45.286262 RL = 0x2
3921 19:52:45.286335 BL = 0x2
3922 19:52:45.289921 RPST = 0x0
3923 19:52:45.290017 RD_PRE = 0x0
3924 19:52:45.292718 WR_PRE = 0x1
3925 19:52:45.292792 WR_PST = 0x0
3926 19:52:45.296140 DBI_WR = 0x0
3927 19:52:45.296209 DBI_RD = 0x0
3928 19:52:45.299231 OTF = 0x1
3929 19:52:45.303017 ===================================
3930 19:52:45.309512 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3931 19:52:45.312874 nWR fixed to 30
3932 19:52:45.316302 [ModeRegInit_LP4] CH0 RK0
3933 19:52:45.316379 [ModeRegInit_LP4] CH0 RK1
3934 19:52:45.319633 [ModeRegInit_LP4] CH1 RK0
3935 19:52:45.322670 [ModeRegInit_LP4] CH1 RK1
3936 19:52:45.322766 match AC timing 17
3937 19:52:45.329389 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3938 19:52:45.332703 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3939 19:52:45.335745 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3940 19:52:45.343215 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3941 19:52:45.346070 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3942 19:52:45.346168 ==
3943 19:52:45.349413 Dram Type= 6, Freq= 0, CH_0, rank 0
3944 19:52:45.352477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3945 19:52:45.352575 ==
3946 19:52:45.358944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3947 19:52:45.365907 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3948 19:52:45.369274 [CA 0] Center 36 (6~66) winsize 61
3949 19:52:45.372424 [CA 1] Center 36 (6~66) winsize 61
3950 19:52:45.375538 [CA 2] Center 34 (3~65) winsize 63
3951 19:52:45.378846 [CA 3] Center 34 (3~65) winsize 63
3952 19:52:45.381904 [CA 4] Center 33 (3~64) winsize 62
3953 19:52:45.386258 [CA 5] Center 33 (3~64) winsize 62
3954 19:52:45.386357
3955 19:52:45.388902 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3956 19:52:45.388978
3957 19:52:45.391978 [CATrainingPosCal] consider 1 rank data
3958 19:52:45.395472 u2DelayCellTimex100 = 270/100 ps
3959 19:52:45.398499 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3960 19:52:45.402204 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3961 19:52:45.405428 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3962 19:52:45.408720 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3963 19:52:45.415625 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3964 19:52:45.418711 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3965 19:52:45.418783
3966 19:52:45.421530 CA PerBit enable=1, Macro0, CA PI delay=33
3967 19:52:45.421600
3968 19:52:45.425153 [CBTSetCACLKResult] CA Dly = 33
3969 19:52:45.425251 CS Dly: 5 (0~36)
3970 19:52:45.425362 ==
3971 19:52:45.428502 Dram Type= 6, Freq= 0, CH_0, rank 1
3972 19:52:45.434988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 19:52:45.435063 ==
3974 19:52:45.438125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3975 19:52:45.444724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3976 19:52:45.448786 [CA 0] Center 36 (6~66) winsize 61
3977 19:52:45.451583 [CA 1] Center 36 (6~66) winsize 61
3978 19:52:45.454804 [CA 2] Center 33 (3~64) winsize 62
3979 19:52:45.458410 [CA 3] Center 33 (3~64) winsize 62
3980 19:52:45.461336 [CA 4] Center 33 (3~64) winsize 62
3981 19:52:45.464507 [CA 5] Center 33 (2~64) winsize 63
3982 19:52:45.464578
3983 19:52:45.467711 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3984 19:52:45.467820
3985 19:52:45.471482 [CATrainingPosCal] consider 2 rank data
3986 19:52:45.474538 u2DelayCellTimex100 = 270/100 ps
3987 19:52:45.477961 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3988 19:52:45.484215 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3989 19:52:45.487879 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 19:52:45.491626 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3991 19:52:45.494513 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3992 19:52:45.497787 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3993 19:52:45.497860
3994 19:52:45.500952 CA PerBit enable=1, Macro0, CA PI delay=33
3995 19:52:45.501023
3996 19:52:45.504033 [CBTSetCACLKResult] CA Dly = 33
3997 19:52:45.507537 CS Dly: 5 (0~36)
3998 19:52:45.507608
3999 19:52:45.511079 ----->DramcWriteLeveling(PI) begin...
4000 19:52:45.511175 ==
4001 19:52:45.514038 Dram Type= 6, Freq= 0, CH_0, rank 0
4002 19:52:45.517546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 19:52:45.517643 ==
4004 19:52:45.520946 Write leveling (Byte 0): 35 => 35
4005 19:52:45.523960 Write leveling (Byte 1): 31 => 31
4006 19:52:45.527318 DramcWriteLeveling(PI) end<-----
4007 19:52:45.527403
4008 19:52:45.527464 ==
4009 19:52:45.530580 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 19:52:45.534271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 19:52:45.534345 ==
4012 19:52:45.537281 [Gating] SW mode calibration
4013 19:52:45.544075 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4014 19:52:45.550240 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4015 19:52:45.553713 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4016 19:52:45.557108 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4017 19:52:45.563487 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4018 19:52:45.566866 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4019 19:52:45.570280 0 9 16 | B1->B0 | 3030 2929 | 1 0 | (1 0) (1 1)
4020 19:52:45.577414 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 19:52:45.580263 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 19:52:45.583576 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 19:52:45.589917 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 19:52:45.593218 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 19:52:45.597186 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 19:52:45.603010 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
4027 19:52:45.606539 0 10 16 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
4028 19:52:45.609662 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 19:52:45.616291 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 19:52:45.619761 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 19:52:45.623021 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 19:52:45.629281 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 19:52:45.632839 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 19:52:45.636212 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 19:52:45.642961 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4036 19:52:45.646028 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 19:52:45.649262 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 19:52:45.656224 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 19:52:45.659027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 19:52:45.662441 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 19:52:45.668967 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 19:52:45.672654 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 19:52:45.675231 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 19:52:45.682096 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 19:52:45.685416 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 19:52:45.688754 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 19:52:45.695304 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 19:52:45.698319 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 19:52:45.701892 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 19:52:45.708067 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4051 19:52:45.711967 Total UI for P1: 0, mck2ui 16
4052 19:52:45.715325 best dqsien dly found for B0: ( 0, 13, 10)
4053 19:52:45.718048 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4054 19:52:45.721351 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 19:52:45.724794 Total UI for P1: 0, mck2ui 16
4056 19:52:45.728084 best dqsien dly found for B1: ( 0, 13, 14)
4057 19:52:45.734648 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4058 19:52:45.738586 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4059 19:52:45.738683
4060 19:52:45.741559 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4061 19:52:45.744811 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4062 19:52:45.748300 [Gating] SW calibration Done
4063 19:52:45.748375 ==
4064 19:52:45.751091 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 19:52:45.754532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 19:52:45.754637 ==
4067 19:52:45.757929 RX Vref Scan: 0
4068 19:52:45.758029
4069 19:52:45.758128 RX Vref 0 -> 0, step: 1
4070 19:52:45.758215
4071 19:52:45.761046 RX Delay -230 -> 252, step: 16
4072 19:52:45.764710 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4073 19:52:45.771247 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4074 19:52:45.774463 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4075 19:52:45.778217 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4076 19:52:45.780941 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4077 19:52:45.787715 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4078 19:52:45.791083 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4079 19:52:45.794089 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4080 19:52:45.797482 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4081 19:52:45.800715 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4082 19:52:45.807263 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4083 19:52:45.810559 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4084 19:52:45.813899 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4085 19:52:45.820832 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4086 19:52:45.823835 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4087 19:52:45.827030 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4088 19:52:45.827104 ==
4089 19:52:45.830667 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 19:52:45.833704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 19:52:45.833804 ==
4092 19:52:45.837028 DQS Delay:
4093 19:52:45.837097 DQS0 = 0, DQS1 = 0
4094 19:52:45.840410 DQM Delay:
4095 19:52:45.840505 DQM0 = 42, DQM1 = 31
4096 19:52:45.840594 DQ Delay:
4097 19:52:45.844331 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4098 19:52:45.847180 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4099 19:52:45.850352 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4100 19:52:45.853584 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4101 19:52:45.853662
4102 19:52:45.856942
4103 19:52:45.857036 ==
4104 19:52:45.860171 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 19:52:45.863841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 19:52:45.863916 ==
4107 19:52:45.863979
4108 19:52:45.864042
4109 19:52:45.866522 TX Vref Scan disable
4110 19:52:45.866617 == TX Byte 0 ==
4111 19:52:45.873210 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4112 19:52:45.876715 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4113 19:52:45.876787 == TX Byte 1 ==
4114 19:52:45.883182 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4115 19:52:45.886541 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4116 19:52:45.886639 ==
4117 19:52:45.889973 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 19:52:45.893278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 19:52:45.893350 ==
4120 19:52:45.893411
4121 19:52:45.893467
4122 19:52:45.896319 TX Vref Scan disable
4123 19:52:45.899477 == TX Byte 0 ==
4124 19:52:45.903129 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4125 19:52:45.909458 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4126 19:52:45.909558 == TX Byte 1 ==
4127 19:52:45.912837 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4128 19:52:45.919408 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4129 19:52:45.919481
4130 19:52:45.919541 [DATLAT]
4131 19:52:45.919599 Freq=600, CH0 RK0
4132 19:52:45.919674
4133 19:52:45.922805 DATLAT Default: 0x9
4134 19:52:45.922901 0, 0xFFFF, sum = 0
4135 19:52:45.925894 1, 0xFFFF, sum = 0
4136 19:52:45.929359 2, 0xFFFF, sum = 0
4137 19:52:45.929431 3, 0xFFFF, sum = 0
4138 19:52:45.933028 4, 0xFFFF, sum = 0
4139 19:52:45.933102 5, 0xFFFF, sum = 0
4140 19:52:45.936362 6, 0xFFFF, sum = 0
4141 19:52:45.936436 7, 0xFFFF, sum = 0
4142 19:52:45.939629 8, 0x0, sum = 1
4143 19:52:45.939734 9, 0x0, sum = 2
4144 19:52:45.939824 10, 0x0, sum = 3
4145 19:52:45.942700 11, 0x0, sum = 4
4146 19:52:45.942771 best_step = 9
4147 19:52:45.942828
4148 19:52:45.942898 ==
4149 19:52:45.945864 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 19:52:45.952873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 19:52:45.952947 ==
4152 19:52:45.953008 RX Vref Scan: 1
4153 19:52:45.953065
4154 19:52:45.955951 RX Vref 0 -> 0, step: 1
4155 19:52:45.956019
4156 19:52:45.959047 RX Delay -195 -> 252, step: 8
4157 19:52:45.959141
4158 19:52:45.962322 Set Vref, RX VrefLevel [Byte0]: 59
4159 19:52:45.965976 [Byte1]: 59
4160 19:52:45.966075
4161 19:52:45.968973 Final RX Vref Byte 0 = 59 to rank0
4162 19:52:45.972512 Final RX Vref Byte 1 = 59 to rank0
4163 19:52:45.975460 Final RX Vref Byte 0 = 59 to rank1
4164 19:52:45.978728 Final RX Vref Byte 1 = 59 to rank1==
4165 19:52:45.981973 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 19:52:45.985393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 19:52:45.988571 ==
4168 19:52:45.988642 DQS Delay:
4169 19:52:45.988702 DQS0 = 0, DQS1 = 0
4170 19:52:45.992036 DQM Delay:
4171 19:52:45.992106 DQM0 = 43, DQM1 = 33
4172 19:52:45.995205 DQ Delay:
4173 19:52:45.995276 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4174 19:52:45.998607 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =48
4175 19:52:46.002002 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4176 19:52:46.005305 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4177 19:52:46.005375
4178 19:52:46.008631
4179 19:52:46.015345 [DQSOSCAuto] RK0, (LSB)MR18= 0x6740, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4180 19:52:46.018886 CH0 RK0: MR19=808, MR18=6740
4181 19:52:46.025181 CH0_RK0: MR19=0x808, MR18=0x6740, DQSOSC=390, MR23=63, INC=172, DEC=114
4182 19:52:46.025256
4183 19:52:46.028431 ----->DramcWriteLeveling(PI) begin...
4184 19:52:46.028506 ==
4185 19:52:46.031906 Dram Type= 6, Freq= 0, CH_0, rank 1
4186 19:52:46.035282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 19:52:46.035381 ==
4188 19:52:46.038460 Write leveling (Byte 0): 33 => 33
4189 19:52:46.041449 Write leveling (Byte 1): 31 => 31
4190 19:52:46.045113 DramcWriteLeveling(PI) end<-----
4191 19:52:46.045186
4192 19:52:46.045247 ==
4193 19:52:46.048372 Dram Type= 6, Freq= 0, CH_0, rank 1
4194 19:52:46.051761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 19:52:46.051846 ==
4196 19:52:46.054860 [Gating] SW mode calibration
4197 19:52:46.061537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4198 19:52:46.067907 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4199 19:52:46.071644 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4200 19:52:46.077843 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4201 19:52:46.081192 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4202 19:52:46.084650 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
4203 19:52:46.092098 0 9 16 | B1->B0 | 3030 2c2c | 0 0 | (0 1) (0 0)
4204 19:52:46.094408 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 19:52:46.097663 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 19:52:46.104192 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 19:52:46.107681 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 19:52:46.110850 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 19:52:46.117769 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 19:52:46.120653 0 10 12 | B1->B0 | 2727 2b2b | 0 0 | (0 0) (0 0)
4211 19:52:46.123946 0 10 16 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
4212 19:52:46.130756 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 19:52:46.134201 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 19:52:46.137144 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 19:52:46.143689 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 19:52:46.147165 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 19:52:46.150133 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 19:52:46.156974 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4219 19:52:46.160034 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 19:52:46.163363 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 19:52:46.170332 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 19:52:46.173456 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 19:52:46.177208 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 19:52:46.183343 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 19:52:46.186285 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 19:52:46.189811 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 19:52:46.196420 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 19:52:46.200152 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 19:52:46.203309 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 19:52:46.209848 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 19:52:46.213119 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 19:52:46.216021 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 19:52:46.222636 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 19:52:46.226007 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4235 19:52:46.229525 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 19:52:46.232683 Total UI for P1: 0, mck2ui 16
4237 19:52:46.236505 best dqsien dly found for B0: ( 0, 13, 12)
4238 19:52:46.239527 Total UI for P1: 0, mck2ui 16
4239 19:52:46.242507 best dqsien dly found for B1: ( 0, 13, 12)
4240 19:52:46.246227 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4241 19:52:46.249228 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4242 19:52:46.249299
4243 19:52:46.255597 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4244 19:52:46.258840 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4245 19:52:46.262013 [Gating] SW calibration Done
4246 19:52:46.262116 ==
4247 19:52:46.265735 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 19:52:46.268939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 19:52:46.269011 ==
4250 19:52:46.269072 RX Vref Scan: 0
4251 19:52:46.269129
4252 19:52:46.272000 RX Vref 0 -> 0, step: 1
4253 19:52:46.272068
4254 19:52:46.275144 RX Delay -230 -> 252, step: 16
4255 19:52:46.278901 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4256 19:52:46.285527 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4257 19:52:46.289233 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4258 19:52:46.292143 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4259 19:52:46.295194 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4260 19:52:46.298474 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4261 19:52:46.305312 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4262 19:52:46.308661 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4263 19:52:46.311391 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4264 19:52:46.314802 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4265 19:52:46.321985 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4266 19:52:46.324776 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4267 19:52:46.327923 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4268 19:52:46.331485 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4269 19:52:46.337954 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4270 19:52:46.341225 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4271 19:52:46.341298 ==
4272 19:52:46.344846 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 19:52:46.347697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 19:52:46.347832 ==
4275 19:52:46.351474 DQS Delay:
4276 19:52:46.351550 DQS0 = 0, DQS1 = 0
4277 19:52:46.351611 DQM Delay:
4278 19:52:46.354452 DQM0 = 46, DQM1 = 38
4279 19:52:46.354549 DQ Delay:
4280 19:52:46.357857 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4281 19:52:46.361146 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4282 19:52:46.364175 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4283 19:52:46.367803 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4284 19:52:46.367876
4285 19:52:46.367943
4286 19:52:46.368001 ==
4287 19:52:46.371242 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 19:52:46.377680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 19:52:46.377753 ==
4290 19:52:46.377813
4291 19:52:46.377870
4292 19:52:46.377925 TX Vref Scan disable
4293 19:52:46.381398 == TX Byte 0 ==
4294 19:52:46.384496 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4295 19:52:46.391371 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4296 19:52:46.391483 == TX Byte 1 ==
4297 19:52:46.394930 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4298 19:52:46.401447 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4299 19:52:46.401547 ==
4300 19:52:46.404711 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 19:52:46.408425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 19:52:46.408522 ==
4303 19:52:46.408611
4304 19:52:46.408706
4305 19:52:46.411429 TX Vref Scan disable
4306 19:52:46.414507 == TX Byte 0 ==
4307 19:52:46.418280 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4308 19:52:46.421102 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4309 19:52:46.424613 == TX Byte 1 ==
4310 19:52:46.427503 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4311 19:52:46.431128 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4312 19:52:46.431225
4313 19:52:46.431314 [DATLAT]
4314 19:52:46.434192 Freq=600, CH0 RK1
4315 19:52:46.434298
4316 19:52:46.437501 DATLAT Default: 0x9
4317 19:52:46.437595 0, 0xFFFF, sum = 0
4318 19:52:46.440995 1, 0xFFFF, sum = 0
4319 19:52:46.441105 2, 0xFFFF, sum = 0
4320 19:52:46.444592 3, 0xFFFF, sum = 0
4321 19:52:46.444693 4, 0xFFFF, sum = 0
4322 19:52:46.447459 5, 0xFFFF, sum = 0
4323 19:52:46.447557 6, 0xFFFF, sum = 0
4324 19:52:46.450829 7, 0xFFFF, sum = 0
4325 19:52:46.450904 8, 0x0, sum = 1
4326 19:52:46.454234 9, 0x0, sum = 2
4327 19:52:46.454334 10, 0x0, sum = 3
4328 19:52:46.457529 11, 0x0, sum = 4
4329 19:52:46.457600 best_step = 9
4330 19:52:46.457672
4331 19:52:46.457731 ==
4332 19:52:46.460795 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 19:52:46.464010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 19:52:46.464089 ==
4335 19:52:46.467546 RX Vref Scan: 0
4336 19:52:46.467644
4337 19:52:46.470651 RX Vref 0 -> 0, step: 1
4338 19:52:46.470749
4339 19:52:46.470845 RX Delay -179 -> 252, step: 8
4340 19:52:46.478520 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4341 19:52:46.481741 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4342 19:52:46.485017 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4343 19:52:46.488613 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4344 19:52:46.494816 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4345 19:52:46.498374 iDelay=205, Bit 5, Center 36 (-115 ~ 188) 304
4346 19:52:46.501643 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4347 19:52:46.504943 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4348 19:52:46.511478 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4349 19:52:46.514553 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4350 19:52:46.518460 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4351 19:52:46.521125 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4352 19:52:46.527902 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4353 19:52:46.531218 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4354 19:52:46.534886 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4355 19:52:46.537984 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4356 19:52:46.538080 ==
4357 19:52:46.541370 Dram Type= 6, Freq= 0, CH_0, rank 1
4358 19:52:46.547682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 19:52:46.547817 ==
4360 19:52:46.547907 DQS Delay:
4361 19:52:46.551316 DQS0 = 0, DQS1 = 0
4362 19:52:46.551385 DQM Delay:
4363 19:52:46.551443 DQM0 = 41, DQM1 = 37
4364 19:52:46.554475 DQ Delay:
4365 19:52:46.557984 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4366 19:52:46.560732 DQ4 =44, DQ5 =36, DQ6 =48, DQ7 =48
4367 19:52:46.564441 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4368 19:52:46.567661 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4369 19:52:46.567760
4370 19:52:46.567826
4371 19:52:46.574240 [DQSOSCAuto] RK1, (LSB)MR18= 0x6417, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4372 19:52:46.578160 CH0 RK1: MR19=808, MR18=6417
4373 19:52:46.584017 CH0_RK1: MR19=0x808, MR18=0x6417, DQSOSC=391, MR23=63, INC=171, DEC=114
4374 19:52:46.587416 [RxdqsGatingPostProcess] freq 600
4375 19:52:46.593932 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4376 19:52:46.594005 Pre-setting of DQS Precalculation
4377 19:52:46.600420 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4378 19:52:46.600497 ==
4379 19:52:46.604462 Dram Type= 6, Freq= 0, CH_1, rank 0
4380 19:52:46.607122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 19:52:46.607231 ==
4382 19:52:46.613459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4383 19:52:46.620040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4384 19:52:46.623194 [CA 0] Center 35 (5~66) winsize 62
4385 19:52:46.626584 [CA 1] Center 35 (5~66) winsize 62
4386 19:52:46.630271 [CA 2] Center 34 (4~65) winsize 62
4387 19:52:46.633117 [CA 3] Center 33 (3~64) winsize 62
4388 19:52:46.636601 [CA 4] Center 34 (4~65) winsize 62
4389 19:52:46.639601 [CA 5] Center 33 (3~64) winsize 62
4390 19:52:46.639701
4391 19:52:46.643139 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4392 19:52:46.643239
4393 19:52:46.646407 [CATrainingPosCal] consider 1 rank data
4394 19:52:46.649763 u2DelayCellTimex100 = 270/100 ps
4395 19:52:46.653155 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4396 19:52:46.656075 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4397 19:52:46.659874 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 19:52:46.663202 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 19:52:46.666196 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 19:52:46.672695 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4401 19:52:46.672809
4402 19:52:46.676235 CA PerBit enable=1, Macro0, CA PI delay=33
4403 19:52:46.676336
4404 19:52:46.679944 [CBTSetCACLKResult] CA Dly = 33
4405 19:52:46.680017 CS Dly: 5 (0~36)
4406 19:52:46.680079 ==
4407 19:52:46.682731 Dram Type= 6, Freq= 0, CH_1, rank 1
4408 19:52:46.686120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 19:52:46.689652 ==
4410 19:52:46.692604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4411 19:52:46.699146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4412 19:52:46.702712 [CA 0] Center 35 (5~66) winsize 62
4413 19:52:46.705757 [CA 1] Center 36 (6~66) winsize 61
4414 19:52:46.709472 [CA 2] Center 34 (4~65) winsize 62
4415 19:52:46.712270 [CA 3] Center 34 (4~65) winsize 62
4416 19:52:46.715903 [CA 4] Center 34 (4~65) winsize 62
4417 19:52:46.719273 [CA 5] Center 34 (3~65) winsize 63
4418 19:52:46.719367
4419 19:52:46.722019 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4420 19:52:46.722113
4421 19:52:46.725666 [CATrainingPosCal] consider 2 rank data
4422 19:52:46.728630 u2DelayCellTimex100 = 270/100 ps
4423 19:52:46.732338 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4424 19:52:46.735278 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4425 19:52:46.742090 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4426 19:52:46.745241 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4427 19:52:46.748873 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4428 19:52:46.751895 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4429 19:52:46.751967
4430 19:52:46.755162 CA PerBit enable=1, Macro0, CA PI delay=33
4431 19:52:46.755260
4432 19:52:46.758721 [CBTSetCACLKResult] CA Dly = 33
4433 19:52:46.758820 CS Dly: 5 (0~37)
4434 19:52:46.758907
4435 19:52:46.765276 ----->DramcWriteLeveling(PI) begin...
4436 19:52:46.765352 ==
4437 19:52:46.768382 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 19:52:46.771707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 19:52:46.771827 ==
4440 19:52:46.774793 Write leveling (Byte 0): 31 => 31
4441 19:52:46.778156 Write leveling (Byte 1): 29 => 29
4442 19:52:46.781689 DramcWriteLeveling(PI) end<-----
4443 19:52:46.781788
4444 19:52:46.781880 ==
4445 19:52:46.784856 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 19:52:46.788560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 19:52:46.788663 ==
4448 19:52:46.792305 [Gating] SW mode calibration
4449 19:52:46.798095 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4450 19:52:46.804760 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4451 19:52:46.808105 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4452 19:52:46.811335 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4453 19:52:46.817927 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4454 19:52:46.821114 0 9 12 | B1->B0 | 3030 3030 | 1 1 | (1 1) (1 0)
4455 19:52:46.825026 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4456 19:52:46.831321 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 19:52:46.834712 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 19:52:46.838056 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 19:52:46.845105 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 19:52:46.847929 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 19:52:46.851017 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4462 19:52:46.857917 0 10 12 | B1->B0 | 2d2d 3838 | 0 0 | (0 0) (0 0)
4463 19:52:46.861343 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 19:52:46.864108 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 19:52:46.871245 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 19:52:46.874803 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 19:52:46.877917 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 19:52:46.884119 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 19:52:46.887441 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 19:52:46.890891 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4471 19:52:46.897557 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 19:52:46.900931 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 19:52:46.903879 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 19:52:46.910345 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 19:52:46.913795 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 19:52:46.917412 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 19:52:46.923747 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 19:52:46.927501 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 19:52:46.930297 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 19:52:46.933594 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 19:52:46.940284 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 19:52:46.943647 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 19:52:46.947006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 19:52:46.953700 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 19:52:46.956657 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 19:52:46.959914 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4487 19:52:46.967253 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 19:52:46.970170 Total UI for P1: 0, mck2ui 16
4489 19:52:46.973461 best dqsien dly found for B0: ( 0, 13, 12)
4490 19:52:46.976545 Total UI for P1: 0, mck2ui 16
4491 19:52:46.980223 best dqsien dly found for B1: ( 0, 13, 14)
4492 19:52:46.983192 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4493 19:52:46.986434 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4494 19:52:46.986534
4495 19:52:46.990234 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4496 19:52:46.993346 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4497 19:52:46.996359 [Gating] SW calibration Done
4498 19:52:46.996429 ==
4499 19:52:47.000507 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 19:52:47.003456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 19:52:47.003552 ==
4502 19:52:47.006234 RX Vref Scan: 0
4503 19:52:47.006307
4504 19:52:47.010228 RX Vref 0 -> 0, step: 1
4505 19:52:47.010323
4506 19:52:47.010411 RX Delay -230 -> 252, step: 16
4507 19:52:47.016362 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4508 19:52:47.019818 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4509 19:52:47.023298 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4510 19:52:47.026501 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4511 19:52:47.033843 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4512 19:52:47.036388 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4513 19:52:47.039369 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4514 19:52:47.042699 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4515 19:52:47.049274 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4516 19:52:47.052800 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4517 19:52:47.056133 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4518 19:52:47.059066 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4519 19:52:47.066291 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4520 19:52:47.069217 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4521 19:52:47.072536 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4522 19:52:47.075854 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4523 19:52:47.075951 ==
4524 19:52:47.079002 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 19:52:47.085710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 19:52:47.085811 ==
4527 19:52:47.085906 DQS Delay:
4528 19:52:47.088839 DQS0 = 0, DQS1 = 0
4529 19:52:47.088909 DQM Delay:
4530 19:52:47.088968 DQM0 = 46, DQM1 = 36
4531 19:52:47.092368 DQ Delay:
4532 19:52:47.095255 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4533 19:52:47.098742 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4534 19:52:47.102106 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4535 19:52:47.105059 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4536 19:52:47.105129
4537 19:52:47.105189
4538 19:52:47.105252 ==
4539 19:52:47.108477 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 19:52:47.111977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 19:52:47.112052 ==
4542 19:52:47.112113
4543 19:52:47.112170
4544 19:52:47.115131 TX Vref Scan disable
4545 19:52:47.118685 == TX Byte 0 ==
4546 19:52:47.121832 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4547 19:52:47.124914 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4548 19:52:47.128624 == TX Byte 1 ==
4549 19:52:47.131987 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4550 19:52:47.135084 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4551 19:52:47.135183 ==
4552 19:52:47.138484 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 19:52:47.144967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 19:52:47.145043 ==
4555 19:52:47.145106
4556 19:52:47.145164
4557 19:52:47.145241 TX Vref Scan disable
4558 19:52:47.149345 == TX Byte 0 ==
4559 19:52:47.152703 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4560 19:52:47.158957 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4561 19:52:47.159058 == TX Byte 1 ==
4562 19:52:47.162363 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4563 19:52:47.168931 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4564 19:52:47.169012
4565 19:52:47.169077 [DATLAT]
4566 19:52:47.169136 Freq=600, CH1 RK0
4567 19:52:47.169193
4568 19:52:47.172086 DATLAT Default: 0x9
4569 19:52:47.172155 0, 0xFFFF, sum = 0
4570 19:52:47.175656 1, 0xFFFF, sum = 0
4571 19:52:47.178994 2, 0xFFFF, sum = 0
4572 19:52:47.179070 3, 0xFFFF, sum = 0
4573 19:52:47.182377 4, 0xFFFF, sum = 0
4574 19:52:47.182475 5, 0xFFFF, sum = 0
4575 19:52:47.185728 6, 0xFFFF, sum = 0
4576 19:52:47.185828 7, 0xFFFF, sum = 0
4577 19:52:47.188760 8, 0x0, sum = 1
4578 19:52:47.188832 9, 0x0, sum = 2
4579 19:52:47.192109 10, 0x0, sum = 3
4580 19:52:47.192190 11, 0x0, sum = 4
4581 19:52:47.192253 best_step = 9
4582 19:52:47.192310
4583 19:52:47.195466 ==
4584 19:52:47.195536 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 19:52:47.202156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 19:52:47.202255 ==
4587 19:52:47.202323 RX Vref Scan: 1
4588 19:52:47.202381
4589 19:52:47.205426 RX Vref 0 -> 0, step: 1
4590 19:52:47.205501
4591 19:52:47.208637 RX Delay -195 -> 252, step: 8
4592 19:52:47.208706
4593 19:52:47.211892 Set Vref, RX VrefLevel [Byte0]: 50
4594 19:52:47.215241 [Byte1]: 53
4595 19:52:47.215314
4596 19:52:47.218952 Final RX Vref Byte 0 = 50 to rank0
4597 19:52:47.221794 Final RX Vref Byte 1 = 53 to rank0
4598 19:52:47.225205 Final RX Vref Byte 0 = 50 to rank1
4599 19:52:47.228605 Final RX Vref Byte 1 = 53 to rank1==
4600 19:52:47.231884 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 19:52:47.234836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 19:52:47.238096 ==
4603 19:52:47.238168 DQS Delay:
4604 19:52:47.238228 DQS0 = 0, DQS1 = 0
4605 19:52:47.241382 DQM Delay:
4606 19:52:47.241468 DQM0 = 46, DQM1 = 37
4607 19:52:47.244899 DQ Delay:
4608 19:52:47.244998 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =40
4609 19:52:47.248060 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4610 19:52:47.251946 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4611 19:52:47.254841 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =48
4612 19:52:47.254913
4613 19:52:47.258450
4614 19:52:47.264796 [DQSOSCAuto] RK0, (LSB)MR18= 0x553a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 393 ps
4615 19:52:47.268345 CH1 RK0: MR19=808, MR18=553A
4616 19:52:47.274737 CH1_RK0: MR19=0x808, MR18=0x553A, DQSOSC=393, MR23=63, INC=169, DEC=113
4617 19:52:47.274813
4618 19:52:47.277950 ----->DramcWriteLeveling(PI) begin...
4619 19:52:47.278052 ==
4620 19:52:47.281474 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 19:52:47.284207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 19:52:47.284279 ==
4623 19:52:47.288930 Write leveling (Byte 0): 33 => 33
4624 19:52:47.291700 Write leveling (Byte 1): 30 => 30
4625 19:52:47.294527 DramcWriteLeveling(PI) end<-----
4626 19:52:47.294628
4627 19:52:47.294718 ==
4628 19:52:47.297973 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 19:52:47.301400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 19:52:47.301471 ==
4631 19:52:47.304601 [Gating] SW mode calibration
4632 19:52:47.311287 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4633 19:52:47.317634 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4634 19:52:47.320788 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4635 19:52:47.327481 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4636 19:52:47.330812 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4637 19:52:47.333965 0 9 12 | B1->B0 | 3030 3333 | 1 1 | (0 1) (0 1)
4638 19:52:47.340798 0 9 16 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4639 19:52:47.343994 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 19:52:47.347064 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 19:52:47.353805 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 19:52:47.356936 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 19:52:47.360400 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 19:52:47.367375 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 19:52:47.370561 0 10 12 | B1->B0 | 3333 2a2a | 0 0 | (0 0) (0 0)
4646 19:52:47.373342 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4647 19:52:47.380434 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 19:52:47.383333 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 19:52:47.386958 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 19:52:47.393319 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 19:52:47.396729 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 19:52:47.400472 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 19:52:47.406308 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4654 19:52:47.410081 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4655 19:52:47.413294 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 19:52:47.419877 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 19:52:47.423401 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 19:52:47.426534 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 19:52:47.432726 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 19:52:47.436377 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 19:52:47.439552 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 19:52:47.446455 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 19:52:47.449293 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 19:52:47.452941 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 19:52:47.455928 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 19:52:47.462764 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 19:52:47.465802 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 19:52:47.469077 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 19:52:47.475982 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4670 19:52:47.478927 Total UI for P1: 0, mck2ui 16
4671 19:52:47.482173 best dqsien dly found for B1: ( 0, 13, 10)
4672 19:52:47.485819 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 19:52:47.488963 Total UI for P1: 0, mck2ui 16
4674 19:52:47.492298 best dqsien dly found for B0: ( 0, 13, 12)
4675 19:52:47.495576 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4676 19:52:47.499005 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4677 19:52:47.499090
4678 19:52:47.502582 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4679 19:52:47.508868 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4680 19:52:47.508941 [Gating] SW calibration Done
4681 19:52:47.512139 ==
4682 19:52:47.512214 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 19:52:47.518684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 19:52:47.518756 ==
4685 19:52:47.518817 RX Vref Scan: 0
4686 19:52:47.518875
4687 19:52:47.522250 RX Vref 0 -> 0, step: 1
4688 19:52:47.522316
4689 19:52:47.525747 RX Delay -230 -> 252, step: 16
4690 19:52:47.528758 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4691 19:52:47.532460 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4692 19:52:47.538985 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4693 19:52:47.542104 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4694 19:52:47.545583 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4695 19:52:47.549019 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4696 19:52:47.552346 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4697 19:52:47.558206 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4698 19:52:47.561915 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4699 19:52:47.565224 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4700 19:52:47.568332 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4701 19:52:47.575321 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4702 19:52:47.578604 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4703 19:52:47.581929 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4704 19:52:47.584857 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4705 19:52:47.591708 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4706 19:52:47.591825 ==
4707 19:52:47.594822 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 19:52:47.598138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 19:52:47.598208 ==
4710 19:52:47.598274 DQS Delay:
4711 19:52:47.601884 DQS0 = 0, DQS1 = 0
4712 19:52:47.601968 DQM Delay:
4713 19:52:47.604940 DQM0 = 42, DQM1 = 36
4714 19:52:47.605007 DQ Delay:
4715 19:52:47.608251 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4716 19:52:47.611526 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4717 19:52:47.614969 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4718 19:52:47.618429 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4719 19:52:47.618496
4720 19:52:47.618560
4721 19:52:47.618645 ==
4722 19:52:47.621551 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 19:52:47.624491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 19:52:47.628175 ==
4725 19:52:47.628271
4726 19:52:47.628359
4727 19:52:47.628446 TX Vref Scan disable
4728 19:52:47.631382 == TX Byte 0 ==
4729 19:52:47.634403 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4730 19:52:47.638324 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4731 19:52:47.640932 == TX Byte 1 ==
4732 19:52:47.644258 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4733 19:52:47.651453 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4734 19:52:47.651552 ==
4735 19:52:47.654312 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 19:52:47.657610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 19:52:47.657681 ==
4738 19:52:47.657762
4739 19:52:47.657851
4740 19:52:47.660714 TX Vref Scan disable
4741 19:52:47.664274 == TX Byte 0 ==
4742 19:52:47.667248 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4743 19:52:47.671308 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4744 19:52:47.674383 == TX Byte 1 ==
4745 19:52:47.677233 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4746 19:52:47.680687 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4747 19:52:47.680764
4748 19:52:47.680864 [DATLAT]
4749 19:52:47.684157 Freq=600, CH1 RK1
4750 19:52:47.684232
4751 19:52:47.687256 DATLAT Default: 0x9
4752 19:52:47.687354 0, 0xFFFF, sum = 0
4753 19:52:47.690553 1, 0xFFFF, sum = 0
4754 19:52:47.690655 2, 0xFFFF, sum = 0
4755 19:52:47.693646 3, 0xFFFF, sum = 0
4756 19:52:47.693757 4, 0xFFFF, sum = 0
4757 19:52:47.697241 5, 0xFFFF, sum = 0
4758 19:52:47.697396 6, 0xFFFF, sum = 0
4759 19:52:47.700166 7, 0xFFFF, sum = 0
4760 19:52:47.700239 8, 0x0, sum = 1
4761 19:52:47.703467 9, 0x0, sum = 2
4762 19:52:47.703568 10, 0x0, sum = 3
4763 19:52:47.706957 11, 0x0, sum = 4
4764 19:52:47.707056 best_step = 9
4765 19:52:47.707144
4766 19:52:47.707229 ==
4767 19:52:47.710205 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 19:52:47.713690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 19:52:47.713794 ==
4770 19:52:47.716937 RX Vref Scan: 0
4771 19:52:47.717048
4772 19:52:47.720138 RX Vref 0 -> 0, step: 1
4773 19:52:47.720209
4774 19:52:47.720269 RX Delay -195 -> 252, step: 8
4775 19:52:47.728239 iDelay=213, Bit 0, Center 52 (-99 ~ 204) 304
4776 19:52:47.731298 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4777 19:52:47.734942 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4778 19:52:47.737891 iDelay=213, Bit 3, Center 44 (-99 ~ 188) 288
4779 19:52:47.744483 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4780 19:52:47.748337 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4781 19:52:47.751204 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4782 19:52:47.755101 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4783 19:52:47.757646 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4784 19:52:47.764280 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4785 19:52:47.767903 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4786 19:52:47.771115 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4787 19:52:47.774532 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4788 19:52:47.780757 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4789 19:52:47.784287 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4790 19:52:47.787575 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4791 19:52:47.787671 ==
4792 19:52:47.791041 Dram Type= 6, Freq= 0, CH_1, rank 1
4793 19:52:47.797760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4794 19:52:47.797854 ==
4795 19:52:47.797943 DQS Delay:
4796 19:52:47.798029 DQS0 = 0, DQS1 = 0
4797 19:52:47.801030 DQM Delay:
4798 19:52:47.801096 DQM0 = 46, DQM1 = 36
4799 19:52:47.804045 DQ Delay:
4800 19:52:47.807312 DQ0 =52, DQ1 =40, DQ2 =32, DQ3 =44
4801 19:52:47.810358 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =40
4802 19:52:47.813655 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4803 19:52:47.816915 DQ12 =48, DQ13 =44, DQ14 =40, DQ15 =48
4804 19:52:47.816985
4805 19:52:47.817044
4806 19:52:47.823695 [DQSOSCAuto] RK1, (LSB)MR18= 0x3429, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4807 19:52:47.827108 CH1 RK1: MR19=808, MR18=3429
4808 19:52:47.833765 CH1_RK1: MR19=0x808, MR18=0x3429, DQSOSC=400, MR23=63, INC=163, DEC=109
4809 19:52:47.837699 [RxdqsGatingPostProcess] freq 600
4810 19:52:47.840389 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4811 19:52:47.843548 Pre-setting of DQS Precalculation
4812 19:52:47.850363 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4813 19:52:47.857196 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4814 19:52:47.863528 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4815 19:52:47.863603
4816 19:52:47.863665
4817 19:52:47.867303 [Calibration Summary] 1200 Mbps
4818 19:52:47.867372 CH 0, Rank 0
4819 19:52:47.870222 SW Impedance : PASS
4820 19:52:47.873301 DUTY Scan : NO K
4821 19:52:47.873404 ZQ Calibration : PASS
4822 19:52:47.876862 Jitter Meter : NO K
4823 19:52:47.879910 CBT Training : PASS
4824 19:52:47.879983 Write leveling : PASS
4825 19:52:47.883563 RX DQS gating : PASS
4826 19:52:47.886302 RX DQ/DQS(RDDQC) : PASS
4827 19:52:47.886409 TX DQ/DQS : PASS
4828 19:52:47.889687 RX DATLAT : PASS
4829 19:52:47.892999 RX DQ/DQS(Engine): PASS
4830 19:52:47.893090 TX OE : NO K
4831 19:52:47.896118 All Pass.
4832 19:52:47.896219
4833 19:52:47.896316 CH 0, Rank 1
4834 19:52:47.899519 SW Impedance : PASS
4835 19:52:47.899617 DUTY Scan : NO K
4836 19:52:47.902751 ZQ Calibration : PASS
4837 19:52:47.906098 Jitter Meter : NO K
4838 19:52:47.906168 CBT Training : PASS
4839 19:52:47.909223 Write leveling : PASS
4840 19:52:47.912724 RX DQS gating : PASS
4841 19:52:47.912796 RX DQ/DQS(RDDQC) : PASS
4842 19:52:47.915930 TX DQ/DQS : PASS
4843 19:52:47.919182 RX DATLAT : PASS
4844 19:52:47.919290 RX DQ/DQS(Engine): PASS
4845 19:52:47.922425 TX OE : NO K
4846 19:52:47.922528 All Pass.
4847 19:52:47.922618
4848 19:52:47.925882 CH 1, Rank 0
4849 19:52:47.925954 SW Impedance : PASS
4850 19:52:47.929286 DUTY Scan : NO K
4851 19:52:47.932265 ZQ Calibration : PASS
4852 19:52:47.932342 Jitter Meter : NO K
4853 19:52:47.935439 CBT Training : PASS
4854 19:52:47.939195 Write leveling : PASS
4855 19:52:47.939284 RX DQS gating : PASS
4856 19:52:47.942146 RX DQ/DQS(RDDQC) : PASS
4857 19:52:47.945331 TX DQ/DQS : PASS
4858 19:52:47.945403 RX DATLAT : PASS
4859 19:52:47.948730 RX DQ/DQS(Engine): PASS
4860 19:52:47.948827 TX OE : NO K
4861 19:52:47.952098 All Pass.
4862 19:52:47.952172
4863 19:52:47.952233 CH 1, Rank 1
4864 19:52:47.955620 SW Impedance : PASS
4865 19:52:47.955717 DUTY Scan : NO K
4866 19:52:47.958452 ZQ Calibration : PASS
4867 19:52:47.961626 Jitter Meter : NO K
4868 19:52:47.961697 CBT Training : PASS
4869 19:52:47.965304 Write leveling : PASS
4870 19:52:47.968264 RX DQS gating : PASS
4871 19:52:47.968367 RX DQ/DQS(RDDQC) : PASS
4872 19:52:47.971898 TX DQ/DQS : PASS
4873 19:52:47.975081 RX DATLAT : PASS
4874 19:52:47.975179 RX DQ/DQS(Engine): PASS
4875 19:52:47.978446 TX OE : NO K
4876 19:52:47.978555 All Pass.
4877 19:52:47.978647
4878 19:52:47.981746 DramC Write-DBI off
4879 19:52:47.985118 PER_BANK_REFRESH: Hybrid Mode
4880 19:52:47.985192 TX_TRACKING: ON
4881 19:52:47.995218 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4882 19:52:47.998160 [FAST_K] Save calibration result to emmc
4883 19:52:48.001714 dramc_set_vcore_voltage set vcore to 662500
4884 19:52:48.004944 Read voltage for 933, 3
4885 19:52:48.005018 Vio18 = 0
4886 19:52:48.005096 Vcore = 662500
4887 19:52:48.007954 Vdram = 0
4888 19:52:48.008038 Vddq = 0
4889 19:52:48.008100 Vmddr = 0
4890 19:52:48.014749 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4891 19:52:48.018011 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4892 19:52:48.021257 MEM_TYPE=3, freq_sel=17
4893 19:52:48.024373 sv_algorithm_assistance_LP4_1600
4894 19:52:48.027691 ============ PULL DRAM RESETB DOWN ============
4895 19:52:48.034335 ========== PULL DRAM RESETB DOWN end =========
4896 19:52:48.037903 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4897 19:52:48.041000 ===================================
4898 19:52:48.044775 LPDDR4 DRAM CONFIGURATION
4899 19:52:48.048005 ===================================
4900 19:52:48.048110 EX_ROW_EN[0] = 0x0
4901 19:52:48.050849 EX_ROW_EN[1] = 0x0
4902 19:52:48.050958 LP4Y_EN = 0x0
4903 19:52:48.054353 WORK_FSP = 0x0
4904 19:52:48.054452 WL = 0x3
4905 19:52:48.057397 RL = 0x3
4906 19:52:48.061034 BL = 0x2
4907 19:52:48.061133 RPST = 0x0
4908 19:52:48.063842 RD_PRE = 0x0
4909 19:52:48.063948 WR_PRE = 0x1
4910 19:52:48.067156 WR_PST = 0x0
4911 19:52:48.067230 DBI_WR = 0x0
4912 19:52:48.070621 DBI_RD = 0x0
4913 19:52:48.070722 OTF = 0x1
4914 19:52:48.073806 ===================================
4915 19:52:48.077481 ===================================
4916 19:52:48.080931 ANA top config
4917 19:52:48.083866 ===================================
4918 19:52:48.083938 DLL_ASYNC_EN = 0
4919 19:52:48.087131 ALL_SLAVE_EN = 1
4920 19:52:48.090340 NEW_RANK_MODE = 1
4921 19:52:48.093672 DLL_IDLE_MODE = 1
4922 19:52:48.093773 LP45_APHY_COMB_EN = 1
4923 19:52:48.097053 TX_ODT_DIS = 1
4924 19:52:48.100194 NEW_8X_MODE = 1
4925 19:52:48.103680 ===================================
4926 19:52:48.107192 ===================================
4927 19:52:48.109967 data_rate = 1866
4928 19:52:48.113541 CKR = 1
4929 19:52:48.117157 DQ_P2S_RATIO = 8
4930 19:52:48.119826 ===================================
4931 19:52:48.119900 CA_P2S_RATIO = 8
4932 19:52:48.123382 DQ_CA_OPEN = 0
4933 19:52:48.126735 DQ_SEMI_OPEN = 0
4934 19:52:48.130211 CA_SEMI_OPEN = 0
4935 19:52:48.132875 CA_FULL_RATE = 0
4936 19:52:48.136463 DQ_CKDIV4_EN = 1
4937 19:52:48.139964 CA_CKDIV4_EN = 1
4938 19:52:48.140037 CA_PREDIV_EN = 0
4939 19:52:48.143136 PH8_DLY = 0
4940 19:52:48.146608 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4941 19:52:48.149825 DQ_AAMCK_DIV = 4
4942 19:52:48.152597 CA_AAMCK_DIV = 4
4943 19:52:48.155918 CA_ADMCK_DIV = 4
4944 19:52:48.155991 DQ_TRACK_CA_EN = 0
4945 19:52:48.159393 CA_PICK = 933
4946 19:52:48.162403 CA_MCKIO = 933
4947 19:52:48.166230 MCKIO_SEMI = 0
4948 19:52:48.169253 PLL_FREQ = 3732
4949 19:52:48.172622 DQ_UI_PI_RATIO = 32
4950 19:52:48.175883 CA_UI_PI_RATIO = 0
4951 19:52:48.179346 ===================================
4952 19:52:48.182560 ===================================
4953 19:52:48.182666 memory_type:LPDDR4
4954 19:52:48.185537 GP_NUM : 10
4955 19:52:48.189028 SRAM_EN : 1
4956 19:52:48.189129 MD32_EN : 0
4957 19:52:48.191992 ===================================
4958 19:52:48.195989 [ANA_INIT] >>>>>>>>>>>>>>
4959 19:52:48.198852 <<<<<< [CONFIGURE PHASE]: ANA_TX
4960 19:52:48.202344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4961 19:52:48.205679 ===================================
4962 19:52:48.208693 data_rate = 1866,PCW = 0X8f00
4963 19:52:48.212077 ===================================
4964 19:52:48.215188 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4965 19:52:48.218425 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4966 19:52:48.224968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4967 19:52:48.231466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4968 19:52:48.235035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4969 19:52:48.238419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4970 19:52:48.238526 [ANA_INIT] flow start
4971 19:52:48.241716 [ANA_INIT] PLL >>>>>>>>
4972 19:52:48.244747 [ANA_INIT] PLL <<<<<<<<
4973 19:52:48.244836 [ANA_INIT] MIDPI >>>>>>>>
4974 19:52:48.248198 [ANA_INIT] MIDPI <<<<<<<<
4975 19:52:48.251524 [ANA_INIT] DLL >>>>>>>>
4976 19:52:48.251599 [ANA_INIT] flow end
4977 19:52:48.258017 ============ LP4 DIFF to SE enter ============
4978 19:52:48.261335 ============ LP4 DIFF to SE exit ============
4979 19:52:48.261409 [ANA_INIT] <<<<<<<<<<<<<
4980 19:52:48.264459 [Flow] Enable top DCM control >>>>>
4981 19:52:48.267752 [Flow] Enable top DCM control <<<<<
4982 19:52:48.271327 Enable DLL master slave shuffle
4983 19:52:48.277698 ==============================================================
4984 19:52:48.281042 Gating Mode config
4985 19:52:48.284473 ==============================================================
4986 19:52:48.287688 Config description:
4987 19:52:48.297749 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4988 19:52:48.303940 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4989 19:52:48.307617 SELPH_MODE 0: By rank 1: By Phase
4990 19:52:48.314202 ==============================================================
4991 19:52:48.317839 GAT_TRACK_EN = 1
4992 19:52:48.320803 RX_GATING_MODE = 2
4993 19:52:48.323948 RX_GATING_TRACK_MODE = 2
4994 19:52:48.327075 SELPH_MODE = 1
4995 19:52:48.327172 PICG_EARLY_EN = 1
4996 19:52:48.330458 VALID_LAT_VALUE = 1
4997 19:52:48.337659 ==============================================================
4998 19:52:48.340816 Enter into Gating configuration >>>>
4999 19:52:48.343979 Exit from Gating configuration <<<<
5000 19:52:48.347063 Enter into DVFS_PRE_config >>>>>
5001 19:52:48.357261 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5002 19:52:48.360368 Exit from DVFS_PRE_config <<<<<
5003 19:52:48.363949 Enter into PICG configuration >>>>
5004 19:52:48.367028 Exit from PICG configuration <<<<
5005 19:52:48.370170 [RX_INPUT] configuration >>>>>
5006 19:52:48.373436 [RX_INPUT] configuration <<<<<
5007 19:52:48.379880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5008 19:52:48.383553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5009 19:52:48.389680 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5010 19:52:48.396751 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5011 19:52:48.403628 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5012 19:52:48.409727 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5013 19:52:48.413405 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5014 19:52:48.416698 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5015 19:52:48.419505 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5016 19:52:48.425888 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5017 19:52:48.429904 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5018 19:52:48.432835 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5019 19:52:48.436614 ===================================
5020 19:52:48.439292 LPDDR4 DRAM CONFIGURATION
5021 19:52:48.442826 ===================================
5022 19:52:48.446432 EX_ROW_EN[0] = 0x0
5023 19:52:48.446539 EX_ROW_EN[1] = 0x0
5024 19:52:48.449829 LP4Y_EN = 0x0
5025 19:52:48.449936 WORK_FSP = 0x0
5026 19:52:48.452860 WL = 0x3
5027 19:52:48.452939 RL = 0x3
5028 19:52:48.456348 BL = 0x2
5029 19:52:48.456419 RPST = 0x0
5030 19:52:48.459403 RD_PRE = 0x0
5031 19:52:48.459504 WR_PRE = 0x1
5032 19:52:48.462382 WR_PST = 0x0
5033 19:52:48.462487 DBI_WR = 0x0
5034 19:52:48.466177 DBI_RD = 0x0
5035 19:52:48.466277 OTF = 0x1
5036 19:52:48.469291 ===================================
5037 19:52:48.475460 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5038 19:52:48.478945 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5039 19:52:48.482213 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5040 19:52:48.485782 ===================================
5041 19:52:48.488898 LPDDR4 DRAM CONFIGURATION
5042 19:52:48.492233 ===================================
5043 19:52:48.495615 EX_ROW_EN[0] = 0x10
5044 19:52:48.495712 EX_ROW_EN[1] = 0x0
5045 19:52:48.499011 LP4Y_EN = 0x0
5046 19:52:48.499105 WORK_FSP = 0x0
5047 19:52:48.502128 WL = 0x3
5048 19:52:48.502220 RL = 0x3
5049 19:52:48.505403 BL = 0x2
5050 19:52:48.505475 RPST = 0x0
5051 19:52:48.508830 RD_PRE = 0x0
5052 19:52:48.508934 WR_PRE = 0x1
5053 19:52:48.512180 WR_PST = 0x0
5054 19:52:48.512252 DBI_WR = 0x0
5055 19:52:48.515548 DBI_RD = 0x0
5056 19:52:48.515649 OTF = 0x1
5057 19:52:48.519162 ===================================
5058 19:52:48.525243 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5059 19:52:48.530532 nWR fixed to 30
5060 19:52:48.533087 [ModeRegInit_LP4] CH0 RK0
5061 19:52:48.533156 [ModeRegInit_LP4] CH0 RK1
5062 19:52:48.537055 [ModeRegInit_LP4] CH1 RK0
5063 19:52:48.539629 [ModeRegInit_LP4] CH1 RK1
5064 19:52:48.539728 match AC timing 9
5065 19:52:48.546680 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5066 19:52:48.549472 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5067 19:52:48.552748 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5068 19:52:48.559489 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5069 19:52:48.562847 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5070 19:52:48.562944 ==
5071 19:52:48.565845 Dram Type= 6, Freq= 0, CH_0, rank 0
5072 19:52:48.569641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5073 19:52:48.572406 ==
5074 19:52:48.576115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5075 19:52:48.582574 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5076 19:52:48.585966 [CA 0] Center 37 (7~68) winsize 62
5077 19:52:48.588819 [CA 1] Center 37 (7~68) winsize 62
5078 19:52:48.592339 [CA 2] Center 34 (4~65) winsize 62
5079 19:52:48.595809 [CA 3] Center 35 (5~65) winsize 61
5080 19:52:48.599144 [CA 4] Center 33 (3~64) winsize 62
5081 19:52:48.601864 [CA 5] Center 33 (3~63) winsize 61
5082 19:52:48.601930
5083 19:52:48.605302 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5084 19:52:48.605370
5085 19:52:48.608418 [CATrainingPosCal] consider 1 rank data
5086 19:52:48.611486 u2DelayCellTimex100 = 270/100 ps
5087 19:52:48.614972 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5088 19:52:48.618998 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5089 19:52:48.624954 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5090 19:52:48.628293 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5091 19:52:48.631399 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5092 19:52:48.634753 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5093 19:52:48.634848
5094 19:52:48.638125 CA PerBit enable=1, Macro0, CA PI delay=33
5095 19:52:48.638219
5096 19:52:48.641138 [CBTSetCACLKResult] CA Dly = 33
5097 19:52:48.641214 CS Dly: 7 (0~38)
5098 19:52:48.644563 ==
5099 19:52:48.647769 Dram Type= 6, Freq= 0, CH_0, rank 1
5100 19:52:48.651417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 19:52:48.651521 ==
5102 19:52:48.654485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5103 19:52:48.661130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5104 19:52:48.664757 [CA 0] Center 37 (7~68) winsize 62
5105 19:52:48.668881 [CA 1] Center 37 (7~68) winsize 62
5106 19:52:48.671956 [CA 2] Center 34 (4~65) winsize 62
5107 19:52:48.674608 [CA 3] Center 34 (4~65) winsize 62
5108 19:52:48.677906 [CA 4] Center 33 (3~64) winsize 62
5109 19:52:48.681555 [CA 5] Center 33 (3~63) winsize 61
5110 19:52:48.681628
5111 19:52:48.684605 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5112 19:52:48.684675
5113 19:52:48.687747 [CATrainingPosCal] consider 2 rank data
5114 19:52:48.691578 u2DelayCellTimex100 = 270/100 ps
5115 19:52:48.694665 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5116 19:52:48.701495 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5117 19:52:48.704442 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5118 19:52:48.707995 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5119 19:52:48.710903 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5120 19:52:48.714717 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5121 19:52:48.714813
5122 19:52:48.717695 CA PerBit enable=1, Macro0, CA PI delay=33
5123 19:52:48.717767
5124 19:52:48.721321 [CBTSetCACLKResult] CA Dly = 33
5125 19:52:48.724344 CS Dly: 7 (0~39)
5126 19:52:48.724414
5127 19:52:48.727870 ----->DramcWriteLeveling(PI) begin...
5128 19:52:48.727970 ==
5129 19:52:48.731411 Dram Type= 6, Freq= 0, CH_0, rank 0
5130 19:52:48.734400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 19:52:48.734497 ==
5132 19:52:48.737585 Write leveling (Byte 0): 32 => 32
5133 19:52:48.741035 Write leveling (Byte 1): 27 => 27
5134 19:52:48.744396 DramcWriteLeveling(PI) end<-----
5135 19:52:48.744466
5136 19:52:48.744526 ==
5137 19:52:48.747364 Dram Type= 6, Freq= 0, CH_0, rank 0
5138 19:52:48.750649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5139 19:52:48.750743 ==
5140 19:52:48.754160 [Gating] SW mode calibration
5141 19:52:48.760639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5142 19:52:48.767684 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5143 19:52:48.771189 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5144 19:52:48.774253 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5145 19:52:48.780449 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 19:52:48.783862 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 19:52:48.787246 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 19:52:48.793784 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 19:52:48.797424 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 19:52:48.800486 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5151 19:52:48.807587 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5152 19:52:48.810283 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5153 19:52:48.813498 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 19:52:48.820078 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 19:52:48.823458 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 19:52:48.826814 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 19:52:48.833570 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 19:52:48.836720 0 15 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
5159 19:52:48.840102 1 0 0 | B1->B0 | 3131 4141 | 0 0 | (0 0) (0 0)
5160 19:52:48.847005 1 0 4 | B1->B0 | 403f 4646 | 1 0 | (0 0) (0 0)
5161 19:52:48.849891 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 19:52:48.853494 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 19:52:48.860394 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 19:52:48.863426 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 19:52:48.866465 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 19:52:48.873237 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5167 19:52:48.876224 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5168 19:52:48.879618 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 19:52:48.886296 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 19:52:48.890212 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 19:52:48.893016 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 19:52:48.900076 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 19:52:48.902729 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 19:52:48.905824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 19:52:48.912544 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 19:52:48.916174 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 19:52:48.919209 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 19:52:48.926213 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 19:52:48.928883 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 19:52:48.932362 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 19:52:48.939607 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 19:52:48.942250 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5183 19:52:48.945415 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5184 19:52:48.951892 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 19:52:48.955233 Total UI for P1: 0, mck2ui 16
5186 19:52:48.958563 best dqsien dly found for B0: ( 1, 2, 30)
5187 19:52:48.958663 Total UI for P1: 0, mck2ui 16
5188 19:52:48.965484 best dqsien dly found for B1: ( 1, 3, 0)
5189 19:52:48.968396 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5190 19:52:48.972117 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5191 19:52:48.972196
5192 19:52:48.975314 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5193 19:52:48.979297 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5194 19:52:48.981710 [Gating] SW calibration Done
5195 19:52:48.981783 ==
5196 19:52:48.985463 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 19:52:48.988270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 19:52:48.988368 ==
5199 19:52:48.992372 RX Vref Scan: 0
5200 19:52:48.992446
5201 19:52:48.992508 RX Vref 0 -> 0, step: 1
5202 19:52:48.992583
5203 19:52:48.995277 RX Delay -80 -> 252, step: 8
5204 19:52:48.998079 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5205 19:52:49.005255 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5206 19:52:49.008144 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5207 19:52:49.012143 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5208 19:52:49.014760 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5209 19:52:49.018207 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5210 19:52:49.021180 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5211 19:52:49.028011 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5212 19:52:49.031067 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5213 19:52:49.034377 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5214 19:52:49.038308 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5215 19:52:49.041146 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5216 19:52:49.047716 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5217 19:52:49.051087 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5218 19:52:49.054620 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5219 19:52:49.057576 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5220 19:52:49.057647 ==
5221 19:52:49.061312 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 19:52:49.067555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 19:52:49.067665 ==
5224 19:52:49.067798 DQS Delay:
5225 19:52:49.067882 DQS0 = 0, DQS1 = 0
5226 19:52:49.070888 DQM Delay:
5227 19:52:49.070984 DQM0 = 97, DQM1 = 86
5228 19:52:49.074718 DQ Delay:
5229 19:52:49.077618 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5230 19:52:49.080686 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5231 19:52:49.084143 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5232 19:52:49.087670 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5233 19:52:49.087805
5234 19:52:49.087871
5235 19:52:49.087938 ==
5236 19:52:49.091065 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 19:52:49.093894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 19:52:49.093995 ==
5239 19:52:49.094097
5240 19:52:49.094174
5241 19:52:49.097533 TX Vref Scan disable
5242 19:52:49.100312 == TX Byte 0 ==
5243 19:52:49.103802 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5244 19:52:49.107174 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5245 19:52:49.110546 == TX Byte 1 ==
5246 19:52:49.113771 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5247 19:52:49.116948 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5248 19:52:49.117027 ==
5249 19:52:49.120325 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 19:52:49.123674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 19:52:49.126802 ==
5252 19:52:49.126878
5253 19:52:49.126958
5254 19:52:49.127058 TX Vref Scan disable
5255 19:52:49.130274 == TX Byte 0 ==
5256 19:52:49.133818 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5257 19:52:49.140380 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5258 19:52:49.140462 == TX Byte 1 ==
5259 19:52:49.144210 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5260 19:52:49.150384 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5261 19:52:49.150486
5262 19:52:49.150587 [DATLAT]
5263 19:52:49.150684 Freq=933, CH0 RK0
5264 19:52:49.150780
5265 19:52:49.153850 DATLAT Default: 0xd
5266 19:52:49.153929 0, 0xFFFF, sum = 0
5267 19:52:49.157063 1, 0xFFFF, sum = 0
5268 19:52:49.157166 2, 0xFFFF, sum = 0
5269 19:52:49.160227 3, 0xFFFF, sum = 0
5270 19:52:49.163749 4, 0xFFFF, sum = 0
5271 19:52:49.163863 5, 0xFFFF, sum = 0
5272 19:52:49.167130 6, 0xFFFF, sum = 0
5273 19:52:49.167240 7, 0xFFFF, sum = 0
5274 19:52:49.170195 8, 0xFFFF, sum = 0
5275 19:52:49.170269 9, 0xFFFF, sum = 0
5276 19:52:49.173522 10, 0x0, sum = 1
5277 19:52:49.173603 11, 0x0, sum = 2
5278 19:52:49.176657 12, 0x0, sum = 3
5279 19:52:49.176757 13, 0x0, sum = 4
5280 19:52:49.176848 best_step = 11
5281 19:52:49.179938
5282 19:52:49.180007 ==
5283 19:52:49.183351 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 19:52:49.187089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 19:52:49.187160 ==
5286 19:52:49.187219 RX Vref Scan: 1
5287 19:52:49.187295
5288 19:52:49.190072 RX Vref 0 -> 0, step: 1
5289 19:52:49.190179
5290 19:52:49.193720 RX Delay -69 -> 252, step: 4
5291 19:52:49.193791
5292 19:52:49.196628 Set Vref, RX VrefLevel [Byte0]: 59
5293 19:52:49.199875 [Byte1]: 59
5294 19:52:49.203162
5295 19:52:49.203249 Final RX Vref Byte 0 = 59 to rank0
5296 19:52:49.206941 Final RX Vref Byte 1 = 59 to rank0
5297 19:52:49.209938 Final RX Vref Byte 0 = 59 to rank1
5298 19:52:49.213272 Final RX Vref Byte 1 = 59 to rank1==
5299 19:52:49.216899 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 19:52:49.223060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 19:52:49.223132 ==
5302 19:52:49.223192 DQS Delay:
5303 19:52:49.223249 DQS0 = 0, DQS1 = 0
5304 19:52:49.226611 DQM Delay:
5305 19:52:49.226705 DQM0 = 97, DQM1 = 87
5306 19:52:49.229805 DQ Delay:
5307 19:52:49.233000 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5308 19:52:49.236882 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =106
5309 19:52:49.239591 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =82
5310 19:52:49.243427 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =94
5311 19:52:49.243530
5312 19:52:49.243618
5313 19:52:49.249574 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5314 19:52:49.252653 CH0 RK0: MR19=505, MR18=2E15
5315 19:52:49.259609 CH0_RK0: MR19=0x505, MR18=0x2E15, DQSOSC=407, MR23=63, INC=65, DEC=43
5316 19:52:49.259686
5317 19:52:49.263321 ----->DramcWriteLeveling(PI) begin...
5318 19:52:49.263401 ==
5319 19:52:49.265990 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 19:52:49.269136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 19:52:49.269216 ==
5322 19:52:49.272880 Write leveling (Byte 0): 33 => 33
5323 19:52:49.276056 Write leveling (Byte 1): 30 => 30
5324 19:52:49.279648 DramcWriteLeveling(PI) end<-----
5325 19:52:49.279751
5326 19:52:49.279830 ==
5327 19:52:49.282568 Dram Type= 6, Freq= 0, CH_0, rank 1
5328 19:52:49.285927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 19:52:49.286034 ==
5330 19:52:49.289063 [Gating] SW mode calibration
5331 19:52:49.295834 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5332 19:52:49.302518 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5333 19:52:49.306165 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
5334 19:52:49.312328 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 19:52:49.315466 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 19:52:49.319641 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 19:52:49.325774 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 19:52:49.328956 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 19:52:49.332555 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 19:52:49.338878 0 14 28 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 1)
5341 19:52:49.342467 0 15 0 | B1->B0 | 2e2e 2525 | 1 0 | (1 0) (1 0)
5342 19:52:49.345599 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 19:52:49.352296 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 19:52:49.355682 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 19:52:49.359121 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 19:52:49.365295 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 19:52:49.369512 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 19:52:49.372110 0 15 28 | B1->B0 | 2828 3838 | 1 0 | (0 0) (0 0)
5349 19:52:49.378853 1 0 0 | B1->B0 | 3a3a 4545 | 1 0 | (0 0) (0 0)
5350 19:52:49.381998 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 19:52:49.385002 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 19:52:49.391978 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 19:52:49.395018 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 19:52:49.398267 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 19:52:49.405168 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5356 19:52:49.408269 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5357 19:52:49.411649 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5358 19:52:49.414774 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 19:52:49.421807 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 19:52:49.424555 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 19:52:49.428516 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 19:52:49.434723 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 19:52:49.438219 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 19:52:49.441441 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 19:52:49.448020 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 19:52:49.451571 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 19:52:49.457853 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 19:52:49.461313 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 19:52:49.464437 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 19:52:49.467953 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 19:52:49.474211 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 19:52:49.478203 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5373 19:52:49.480779 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 19:52:49.484388 Total UI for P1: 0, mck2ui 16
5375 19:52:49.487920 best dqsien dly found for B0: ( 1, 2, 28)
5376 19:52:49.490866 Total UI for P1: 0, mck2ui 16
5377 19:52:49.494721 best dqsien dly found for B1: ( 1, 2, 30)
5378 19:52:49.497861 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5379 19:52:49.504131 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5380 19:52:49.504209
5381 19:52:49.507335 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5382 19:52:49.510737 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5383 19:52:49.513955 [Gating] SW calibration Done
5384 19:52:49.514029 ==
5385 19:52:49.517260 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 19:52:49.520576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 19:52:49.520654 ==
5388 19:52:49.524320 RX Vref Scan: 0
5389 19:52:49.524407
5390 19:52:49.524487 RX Vref 0 -> 0, step: 1
5391 19:52:49.524564
5392 19:52:49.527297 RX Delay -80 -> 252, step: 8
5393 19:52:49.530551 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5394 19:52:49.533669 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5395 19:52:49.540525 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5396 19:52:49.543615 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5397 19:52:49.547052 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5398 19:52:49.551010 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5399 19:52:49.553720 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5400 19:52:49.556872 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5401 19:52:49.563678 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5402 19:52:49.567408 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5403 19:52:49.569982 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5404 19:52:49.573576 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5405 19:52:49.576531 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5406 19:52:49.583855 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5407 19:52:49.586608 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5408 19:52:49.590219 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5409 19:52:49.590322 ==
5410 19:52:49.593218 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 19:52:49.596519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 19:52:49.596593 ==
5413 19:52:49.599892 DQS Delay:
5414 19:52:49.599998 DQS0 = 0, DQS1 = 0
5415 19:52:49.603236 DQM Delay:
5416 19:52:49.603334 DQM0 = 96, DQM1 = 90
5417 19:52:49.603433 DQ Delay:
5418 19:52:49.606374 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5419 19:52:49.609667 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5420 19:52:49.613358 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5421 19:52:49.616361 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5422 19:52:49.616464
5423 19:52:49.616553
5424 19:52:49.620014 ==
5425 19:52:49.623087 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 19:52:49.626290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 19:52:49.626388 ==
5428 19:52:49.626486
5429 19:52:49.626575
5430 19:52:49.629578 TX Vref Scan disable
5431 19:52:49.629682 == TX Byte 0 ==
5432 19:52:49.636134 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5433 19:52:49.639292 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5434 19:52:49.639391 == TX Byte 1 ==
5435 19:52:49.646194 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5436 19:52:49.649791 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5437 19:52:49.649889 ==
5438 19:52:49.652936 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 19:52:49.655802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 19:52:49.655893 ==
5441 19:52:49.655957
5442 19:52:49.656016
5443 19:52:49.659184 TX Vref Scan disable
5444 19:52:49.662882 == TX Byte 0 ==
5445 19:52:49.665734 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5446 19:52:49.669043 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5447 19:52:49.672734 == TX Byte 1 ==
5448 19:52:49.675947 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5449 19:52:49.678904 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5450 19:52:49.679011
5451 19:52:49.682625 [DATLAT]
5452 19:52:49.682724 Freq=933, CH0 RK1
5453 19:52:49.682815
5454 19:52:49.685486 DATLAT Default: 0xb
5455 19:52:49.685569 0, 0xFFFF, sum = 0
5456 19:52:49.688998 1, 0xFFFF, sum = 0
5457 19:52:49.689082 2, 0xFFFF, sum = 0
5458 19:52:49.692136 3, 0xFFFF, sum = 0
5459 19:52:49.692217 4, 0xFFFF, sum = 0
5460 19:52:49.695252 5, 0xFFFF, sum = 0
5461 19:52:49.695333 6, 0xFFFF, sum = 0
5462 19:52:49.698678 7, 0xFFFF, sum = 0
5463 19:52:49.698760 8, 0xFFFF, sum = 0
5464 19:52:49.702787 9, 0xFFFF, sum = 0
5465 19:52:49.702869 10, 0x0, sum = 1
5466 19:52:49.705642 11, 0x0, sum = 2
5467 19:52:49.705724 12, 0x0, sum = 3
5468 19:52:49.708739 13, 0x0, sum = 4
5469 19:52:49.708820 best_step = 11
5470 19:52:49.708883
5471 19:52:49.708943 ==
5472 19:52:49.712472 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 19:52:49.718913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 19:52:49.718994 ==
5475 19:52:49.719059 RX Vref Scan: 0
5476 19:52:49.719119
5477 19:52:49.721724 RX Vref 0 -> 0, step: 1
5478 19:52:49.721804
5479 19:52:49.725510 RX Delay -61 -> 252, step: 4
5480 19:52:49.728448 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5481 19:52:49.735687 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5482 19:52:49.738662 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5483 19:52:49.741439 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5484 19:52:49.744928 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5485 19:52:49.748616 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5486 19:52:49.751518 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5487 19:52:49.758314 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5488 19:52:49.761356 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5489 19:52:49.764953 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5490 19:52:49.768388 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5491 19:52:49.771277 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5492 19:52:49.778082 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5493 19:52:49.781555 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5494 19:52:49.785005 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5495 19:52:49.788161 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5496 19:52:49.788263 ==
5497 19:52:49.791481 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 19:52:49.798118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 19:52:49.798219 ==
5500 19:52:49.798319 DQS Delay:
5501 19:52:49.801030 DQS0 = 0, DQS1 = 0
5502 19:52:49.801098 DQM Delay:
5503 19:52:49.801157 DQM0 = 95, DQM1 = 87
5504 19:52:49.804260 DQ Delay:
5505 19:52:49.807445 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5506 19:52:49.810729 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5507 19:52:49.814470 DQ8 =82, DQ9 =78, DQ10 =90, DQ11 =82
5508 19:52:49.817395 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5509 19:52:49.817490
5510 19:52:49.817570
5511 19:52:49.824220 [DQSOSCAuto] RK1, (LSB)MR18= 0x28f8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5512 19:52:49.827886 CH0 RK1: MR19=504, MR18=28F8
5513 19:52:49.833908 CH0_RK1: MR19=0x504, MR18=0x28F8, DQSOSC=409, MR23=63, INC=64, DEC=43
5514 19:52:49.837144 [RxdqsGatingPostProcess] freq 933
5515 19:52:49.840790 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5516 19:52:49.844144 best DQS0 dly(2T, 0.5T) = (0, 10)
5517 19:52:49.847293 best DQS1 dly(2T, 0.5T) = (0, 11)
5518 19:52:49.850547 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5519 19:52:49.853948 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5520 19:52:49.856979 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 19:52:49.860560 best DQS1 dly(2T, 0.5T) = (0, 10)
5522 19:52:49.863742 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 19:52:49.867564 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5524 19:52:49.870101 Pre-setting of DQS Precalculation
5525 19:52:49.876937 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5526 19:52:49.877039 ==
5527 19:52:49.880355 Dram Type= 6, Freq= 0, CH_1, rank 0
5528 19:52:49.883518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 19:52:49.883615 ==
5530 19:52:49.890002 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 19:52:49.893802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5532 19:52:49.897594 [CA 0] Center 36 (6~67) winsize 62
5533 19:52:49.900554 [CA 1] Center 37 (6~68) winsize 63
5534 19:52:49.904321 [CA 2] Center 34 (4~64) winsize 61
5535 19:52:49.907554 [CA 3] Center 33 (3~64) winsize 62
5536 19:52:49.910246 [CA 4] Center 34 (4~64) winsize 61
5537 19:52:49.913625 [CA 5] Center 33 (3~64) winsize 62
5538 19:52:49.913713
5539 19:52:49.916856 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5540 19:52:49.916953
5541 19:52:49.920168 [CATrainingPosCal] consider 1 rank data
5542 19:52:49.923281 u2DelayCellTimex100 = 270/100 ps
5543 19:52:49.930059 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5544 19:52:49.933583 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5545 19:52:49.936688 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5546 19:52:49.940474 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5547 19:52:49.943620 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5548 19:52:49.946680 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5549 19:52:49.946783
5550 19:52:49.950399 CA PerBit enable=1, Macro0, CA PI delay=33
5551 19:52:49.950497
5552 19:52:49.953279 [CBTSetCACLKResult] CA Dly = 33
5553 19:52:49.956631 CS Dly: 5 (0~36)
5554 19:52:49.956702 ==
5555 19:52:49.959686 Dram Type= 6, Freq= 0, CH_1, rank 1
5556 19:52:49.963197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 19:52:49.963294 ==
5558 19:52:49.969619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5559 19:52:49.973061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5560 19:52:49.976987 [CA 0] Center 36 (6~67) winsize 62
5561 19:52:49.980514 [CA 1] Center 36 (6~67) winsize 62
5562 19:52:49.984081 [CA 2] Center 34 (4~65) winsize 62
5563 19:52:49.987207 [CA 3] Center 33 (3~64) winsize 62
5564 19:52:49.990401 [CA 4] Center 34 (3~65) winsize 63
5565 19:52:49.994403 [CA 5] Center 33 (3~64) winsize 62
5566 19:52:49.994503
5567 19:52:49.997401 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5568 19:52:49.997481
5569 19:52:50.000273 [CATrainingPosCal] consider 2 rank data
5570 19:52:50.004111 u2DelayCellTimex100 = 270/100 ps
5571 19:52:50.006931 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5572 19:52:50.013551 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5573 19:52:50.016693 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5574 19:52:50.020126 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5575 19:52:50.023100 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5576 19:52:50.026563 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5577 19:52:50.026635
5578 19:52:50.029784 CA PerBit enable=1, Macro0, CA PI delay=33
5579 19:52:50.029891
5580 19:52:50.033190 [CBTSetCACLKResult] CA Dly = 33
5581 19:52:50.036871 CS Dly: 6 (0~39)
5582 19:52:50.036939
5583 19:52:50.040366 ----->DramcWriteLeveling(PI) begin...
5584 19:52:50.040461 ==
5585 19:52:50.042609 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 19:52:50.046088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 19:52:50.046154 ==
5588 19:52:50.049885 Write leveling (Byte 0): 25 => 25
5589 19:52:50.052626 Write leveling (Byte 1): 27 => 27
5590 19:52:50.056322 DramcWriteLeveling(PI) end<-----
5591 19:52:50.056398
5592 19:52:50.056460 ==
5593 19:52:50.059296 Dram Type= 6, Freq= 0, CH_1, rank 0
5594 19:52:50.063329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 19:52:50.063434 ==
5596 19:52:50.066475 [Gating] SW mode calibration
5597 19:52:50.072844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5598 19:52:50.079884 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5599 19:52:50.082812 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5600 19:52:50.089016 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 19:52:50.092207 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 19:52:50.095477 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 19:52:50.102289 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 19:52:50.105336 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 19:52:50.108868 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
5606 19:52:50.115298 0 14 28 | B1->B0 | 2a2a 2b2b | 0 0 | (1 1) (1 1)
5607 19:52:50.119494 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 19:52:50.122067 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 19:52:50.128657 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 19:52:50.132122 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 19:52:50.135064 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 19:52:50.139119 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 19:52:50.145067 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5614 19:52:50.148591 0 15 28 | B1->B0 | 3333 3939 | 0 1 | (1 1) (0 0)
5615 19:52:50.155061 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
5616 19:52:50.158415 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 19:52:50.161902 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 19:52:50.165244 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 19:52:50.171393 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 19:52:50.175079 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 19:52:50.178337 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5622 19:52:50.185456 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5623 19:52:50.188636 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 19:52:50.191307 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 19:52:50.198086 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 19:52:50.201349 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 19:52:50.204656 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 19:52:50.210906 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 19:52:50.214064 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 19:52:50.220737 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 19:52:50.224342 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 19:52:50.227538 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 19:52:50.234425 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 19:52:50.237203 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 19:52:50.240517 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 19:52:50.247328 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 19:52:50.250316 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5638 19:52:50.254001 Total UI for P1: 0, mck2ui 16
5639 19:52:50.257322 best dqsien dly found for B0: ( 1, 2, 22)
5640 19:52:50.260521 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5641 19:52:50.266866 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 19:52:50.266967 Total UI for P1: 0, mck2ui 16
5643 19:52:50.270364 best dqsien dly found for B1: ( 1, 2, 26)
5644 19:52:50.274102 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5645 19:52:50.280340 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5646 19:52:50.280424
5647 19:52:50.283374 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5648 19:52:50.286824 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5649 19:52:50.289850 [Gating] SW calibration Done
5650 19:52:50.289932 ==
5651 19:52:50.293607 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 19:52:50.296728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 19:52:50.296810 ==
5654 19:52:50.299957 RX Vref Scan: 0
5655 19:52:50.300038
5656 19:52:50.300102 RX Vref 0 -> 0, step: 1
5657 19:52:50.300162
5658 19:52:50.303374 RX Delay -80 -> 252, step: 8
5659 19:52:50.306529 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5660 19:52:50.313500 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5661 19:52:50.316608 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5662 19:52:50.320033 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5663 19:52:50.323186 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5664 19:52:50.326586 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5665 19:52:50.329665 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5666 19:52:50.336203 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5667 19:52:50.339440 iDelay=208, Bit 8, Center 79 (-24 ~ 183) 208
5668 19:52:50.342786 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5669 19:52:50.346160 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5670 19:52:50.349503 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5671 19:52:50.355932 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5672 19:52:50.359446 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5673 19:52:50.362553 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5674 19:52:50.365846 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5675 19:52:50.365927 ==
5676 19:52:50.369333 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 19:52:50.373115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 19:52:50.375936 ==
5679 19:52:50.376017 DQS Delay:
5680 19:52:50.376080 DQS0 = 0, DQS1 = 0
5681 19:52:50.379272 DQM Delay:
5682 19:52:50.379352 DQM0 = 101, DQM1 = 91
5683 19:52:50.382671 DQ Delay:
5684 19:52:50.385758 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5685 19:52:50.389112 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5686 19:52:50.393401 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5687 19:52:50.395677 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5688 19:52:50.395801
5689 19:52:50.395865
5690 19:52:50.395924 ==
5691 19:52:50.399137 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 19:52:50.402931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 19:52:50.403001 ==
5694 19:52:50.403064
5695 19:52:50.403122
5696 19:52:50.405766 TX Vref Scan disable
5697 19:52:50.405830 == TX Byte 0 ==
5698 19:52:50.412134 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5699 19:52:50.415684 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5700 19:52:50.415823 == TX Byte 1 ==
5701 19:52:50.422232 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5702 19:52:50.425484 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5703 19:52:50.425557 ==
5704 19:52:50.429392 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 19:52:50.432155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 19:52:50.432233 ==
5707 19:52:50.432295
5708 19:52:50.432353
5709 19:52:50.435315 TX Vref Scan disable
5710 19:52:50.438734 == TX Byte 0 ==
5711 19:52:50.441985 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5712 19:52:50.445358 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5713 19:52:50.448585 == TX Byte 1 ==
5714 19:52:50.452099 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5715 19:52:50.455860 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5716 19:52:50.458540
5717 19:52:50.458633 [DATLAT]
5718 19:52:50.458720 Freq=933, CH1 RK0
5719 19:52:50.458813
5720 19:52:50.461838 DATLAT Default: 0xd
5721 19:52:50.461910 0, 0xFFFF, sum = 0
5722 19:52:50.464791 1, 0xFFFF, sum = 0
5723 19:52:50.464889 2, 0xFFFF, sum = 0
5724 19:52:50.468627 3, 0xFFFF, sum = 0
5725 19:52:50.471910 4, 0xFFFF, sum = 0
5726 19:52:50.471983 5, 0xFFFF, sum = 0
5727 19:52:50.475049 6, 0xFFFF, sum = 0
5728 19:52:50.475145 7, 0xFFFF, sum = 0
5729 19:52:50.478081 8, 0xFFFF, sum = 0
5730 19:52:50.478182 9, 0xFFFF, sum = 0
5731 19:52:50.481565 10, 0x0, sum = 1
5732 19:52:50.481664 11, 0x0, sum = 2
5733 19:52:50.484797 12, 0x0, sum = 3
5734 19:52:50.484895 13, 0x0, sum = 4
5735 19:52:50.484994 best_step = 11
5736 19:52:50.485088
5737 19:52:50.488551 ==
5738 19:52:50.491588 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 19:52:50.494888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 19:52:50.494962 ==
5741 19:52:50.495042 RX Vref Scan: 1
5742 19:52:50.495123
5743 19:52:50.498456 RX Vref 0 -> 0, step: 1
5744 19:52:50.498527
5745 19:52:50.501350 RX Delay -69 -> 252, step: 4
5746 19:52:50.501431
5747 19:52:50.504881 Set Vref, RX VrefLevel [Byte0]: 50
5748 19:52:50.508013 [Byte1]: 53
5749 19:52:50.508085
5750 19:52:50.511463 Final RX Vref Byte 0 = 50 to rank0
5751 19:52:50.514805 Final RX Vref Byte 1 = 53 to rank0
5752 19:52:50.517983 Final RX Vref Byte 0 = 50 to rank1
5753 19:52:50.521277 Final RX Vref Byte 1 = 53 to rank1==
5754 19:52:50.524342 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 19:52:50.530712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 19:52:50.530817 ==
5757 19:52:50.530918 DQS Delay:
5758 19:52:50.530996 DQS0 = 0, DQS1 = 0
5759 19:52:50.534183 DQM Delay:
5760 19:52:50.534284 DQM0 = 100, DQM1 = 94
5761 19:52:50.537523 DQ Delay:
5762 19:52:50.540963 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5763 19:52:50.544127 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =96
5764 19:52:50.547231 DQ8 =82, DQ9 =82, DQ10 =96, DQ11 =86
5765 19:52:50.550740 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5766 19:52:50.550837
5767 19:52:50.550936
5768 19:52:50.557518 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5769 19:52:50.560478 CH1 RK0: MR19=505, MR18=1B0A
5770 19:52:50.567318 CH1_RK0: MR19=0x505, MR18=0x1B0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5771 19:52:50.567421
5772 19:52:50.570306 ----->DramcWriteLeveling(PI) begin...
5773 19:52:50.570407 ==
5774 19:52:50.574087 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 19:52:50.577363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 19:52:50.577466 ==
5777 19:52:50.580467 Write leveling (Byte 0): 25 => 25
5778 19:52:50.583607 Write leveling (Byte 1): 26 => 26
5779 19:52:50.587600 DramcWriteLeveling(PI) end<-----
5780 19:52:50.587697
5781 19:52:50.587822 ==
5782 19:52:50.590237 Dram Type= 6, Freq= 0, CH_1, rank 1
5783 19:52:50.597305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 19:52:50.597380 ==
5785 19:52:50.597464 [Gating] SW mode calibration
5786 19:52:50.606815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5787 19:52:50.610220 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5788 19:52:50.616594 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 19:52:50.620173 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 19:52:50.623573 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 19:52:50.630019 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 19:52:50.633376 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 19:52:50.637250 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5794 19:52:50.643361 0 14 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 0)
5795 19:52:50.646550 0 14 28 | B1->B0 | 2727 2f2f | 0 1 | (0 0) (1 0)
5796 19:52:50.649830 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
5797 19:52:50.656409 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 19:52:50.659515 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 19:52:50.662766 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 19:52:50.669759 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 19:52:50.672801 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 19:52:50.675843 0 15 24 | B1->B0 | 2f2f 2626 | 0 0 | (1 1) (0 0)
5803 19:52:50.683878 0 15 28 | B1->B0 | 3a3a 3737 | 0 0 | (0 0) (0 0)
5804 19:52:50.685769 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 19:52:50.689276 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 19:52:50.695971 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 19:52:50.699265 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 19:52:50.702875 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 19:52:50.708745 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 19:52:50.712382 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5811 19:52:50.715623 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 19:52:50.722075 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 19:52:50.725268 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 19:52:50.728760 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 19:52:50.735520 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 19:52:50.738469 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 19:52:50.742447 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 19:52:50.745231 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 19:52:50.751768 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 19:52:50.755507 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 19:52:50.758559 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 19:52:50.765053 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 19:52:50.768744 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 19:52:50.772080 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 19:52:50.778356 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 19:52:50.781717 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5827 19:52:50.788489 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5828 19:52:50.791368 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 19:52:50.795026 Total UI for P1: 0, mck2ui 16
5830 19:52:50.797997 best dqsien dly found for B0: ( 1, 2, 28)
5831 19:52:50.801410 Total UI for P1: 0, mck2ui 16
5832 19:52:50.805023 best dqsien dly found for B1: ( 1, 2, 26)
5833 19:52:50.807880 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5834 19:52:50.811662 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5835 19:52:50.811795
5836 19:52:50.814968 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5837 19:52:50.818118 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5838 19:52:50.821142 [Gating] SW calibration Done
5839 19:52:50.821216 ==
5840 19:52:50.824473 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 19:52:50.827646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 19:52:50.827778 ==
5843 19:52:50.830843 RX Vref Scan: 0
5844 19:52:50.830939
5845 19:52:50.834087 RX Vref 0 -> 0, step: 1
5846 19:52:50.834164
5847 19:52:50.834247 RX Delay -80 -> 252, step: 8
5848 19:52:50.840891 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5849 19:52:50.844453 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5850 19:52:50.847910 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5851 19:52:50.851013 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5852 19:52:50.854314 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5853 19:52:50.857384 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5854 19:52:50.863910 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5855 19:52:50.867297 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5856 19:52:50.871310 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5857 19:52:50.873900 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5858 19:52:50.877187 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5859 19:52:50.883701 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5860 19:52:50.886923 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5861 19:52:50.890305 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5862 19:52:50.893744 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5863 19:52:50.897249 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5864 19:52:50.897324 ==
5865 19:52:50.900183 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 19:52:50.906996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 19:52:50.907097 ==
5868 19:52:50.907194 DQS Delay:
5869 19:52:50.910702 DQS0 = 0, DQS1 = 0
5870 19:52:50.910775 DQM Delay:
5871 19:52:50.913687 DQM0 = 99, DQM1 = 90
5872 19:52:50.913768 DQ Delay:
5873 19:52:50.917036 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =95
5874 19:52:50.920136 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5875 19:52:50.923571 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =83
5876 19:52:50.926693 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5877 19:52:50.926792
5878 19:52:50.926890
5879 19:52:50.926968 ==
5880 19:52:50.930035 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 19:52:50.933332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 19:52:50.933432 ==
5883 19:52:50.933533
5884 19:52:50.933630
5885 19:52:50.936503 TX Vref Scan disable
5886 19:52:50.939842 == TX Byte 0 ==
5887 19:52:50.943232 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5888 19:52:50.946319 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5889 19:52:50.949968 == TX Byte 1 ==
5890 19:52:50.952881 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5891 19:52:50.956571 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5892 19:52:50.956651 ==
5893 19:52:50.959820 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 19:52:50.966766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 19:52:50.966871 ==
5896 19:52:50.966971
5897 19:52:50.967068
5898 19:52:50.967163 TX Vref Scan disable
5899 19:52:50.970328 == TX Byte 0 ==
5900 19:52:50.973439 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5901 19:52:50.980465 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5902 19:52:50.980549 == TX Byte 1 ==
5903 19:52:50.983986 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5904 19:52:50.990202 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5905 19:52:50.990310
5906 19:52:50.990412 [DATLAT]
5907 19:52:50.990502 Freq=933, CH1 RK1
5908 19:52:50.990599
5909 19:52:50.993330 DATLAT Default: 0xb
5910 19:52:50.993430 0, 0xFFFF, sum = 0
5911 19:52:50.996925 1, 0xFFFF, sum = 0
5912 19:52:50.999967 2, 0xFFFF, sum = 0
5913 19:52:51.000039 3, 0xFFFF, sum = 0
5914 19:52:51.003505 4, 0xFFFF, sum = 0
5915 19:52:51.003616 5, 0xFFFF, sum = 0
5916 19:52:51.006856 6, 0xFFFF, sum = 0
5917 19:52:51.006954 7, 0xFFFF, sum = 0
5918 19:52:51.010114 8, 0xFFFF, sum = 0
5919 19:52:51.010208 9, 0xFFFF, sum = 0
5920 19:52:51.013428 10, 0x0, sum = 1
5921 19:52:51.013522 11, 0x0, sum = 2
5922 19:52:51.016462 12, 0x0, sum = 3
5923 19:52:51.016529 13, 0x0, sum = 4
5924 19:52:51.016588 best_step = 11
5925 19:52:51.016644
5926 19:52:51.019714 ==
5927 19:52:51.023244 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 19:52:51.026579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 19:52:51.026651 ==
5930 19:52:51.026712 RX Vref Scan: 0
5931 19:52:51.026769
5932 19:52:51.030161 RX Vref 0 -> 0, step: 1
5933 19:52:51.030257
5934 19:52:51.032846 RX Delay -69 -> 252, step: 4
5935 19:52:51.040295 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5936 19:52:51.042673 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
5937 19:52:51.046141 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5938 19:52:51.049648 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5939 19:52:51.052525 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5940 19:52:51.056059 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5941 19:52:51.062548 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5942 19:52:51.065801 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
5943 19:52:51.069562 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5944 19:52:51.072855 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
5945 19:52:51.076207 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
5946 19:52:51.082571 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5947 19:52:51.085786 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5948 19:52:51.089151 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
5949 19:52:51.093305 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5950 19:52:51.095494 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5951 19:52:51.098887 ==
5952 19:52:51.102296 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 19:52:51.105672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 19:52:51.105745 ==
5955 19:52:51.105833 DQS Delay:
5956 19:52:51.108714 DQS0 = 0, DQS1 = 0
5957 19:52:51.108790 DQM Delay:
5958 19:52:51.112171 DQM0 = 101, DQM1 = 93
5959 19:52:51.112239 DQ Delay:
5960 19:52:51.115598 DQ0 =106, DQ1 =96, DQ2 =90, DQ3 =98
5961 19:52:51.119176 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =96
5962 19:52:51.122022 DQ8 =82, DQ9 =82, DQ10 =92, DQ11 =84
5963 19:52:51.125281 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5964 19:52:51.125375
5965 19:52:51.125472
5966 19:52:51.134858 [DQSOSCAuto] RK1, (LSB)MR18= 0xd06, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 417 ps
5967 19:52:51.134958 CH1 RK1: MR19=505, MR18=D06
5968 19:52:51.141527 CH1_RK1: MR19=0x505, MR18=0xD06, DQSOSC=417, MR23=63, INC=62, DEC=41
5969 19:52:51.145095 [RxdqsGatingPostProcess] freq 933
5970 19:52:51.151864 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5971 19:52:51.155489 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 19:52:51.158278 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 19:52:51.161562 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 19:52:51.164721 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 19:52:51.167951 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 19:52:51.168024 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 19:52:51.171621 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 19:52:51.174594 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 19:52:51.178065 Pre-setting of DQS Precalculation
5980 19:52:51.184715 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5981 19:52:51.191492 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5982 19:52:51.197673 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5983 19:52:51.197747
5984 19:52:51.197813
5985 19:52:51.201153 [Calibration Summary] 1866 Mbps
5986 19:52:51.204404 CH 0, Rank 0
5987 19:52:51.204477 SW Impedance : PASS
5988 19:52:51.207609 DUTY Scan : NO K
5989 19:52:51.210950 ZQ Calibration : PASS
5990 19:52:51.211043 Jitter Meter : NO K
5991 19:52:51.214735 CBT Training : PASS
5992 19:52:51.214802 Write leveling : PASS
5993 19:52:51.217382 RX DQS gating : PASS
5994 19:52:51.220762 RX DQ/DQS(RDDQC) : PASS
5995 19:52:51.220827 TX DQ/DQS : PASS
5996 19:52:51.224404 RX DATLAT : PASS
5997 19:52:51.227385 RX DQ/DQS(Engine): PASS
5998 19:52:51.227455 TX OE : NO K
5999 19:52:51.230769 All Pass.
6000 19:52:51.230862
6001 19:52:51.230948 CH 0, Rank 1
6002 19:52:51.233772 SW Impedance : PASS
6003 19:52:51.233839 DUTY Scan : NO K
6004 19:52:51.237406 ZQ Calibration : PASS
6005 19:52:51.240432 Jitter Meter : NO K
6006 19:52:51.240498 CBT Training : PASS
6007 19:52:51.244091 Write leveling : PASS
6008 19:52:51.247222 RX DQS gating : PASS
6009 19:52:51.247313 RX DQ/DQS(RDDQC) : PASS
6010 19:52:51.250459 TX DQ/DQS : PASS
6011 19:52:51.253533 RX DATLAT : PASS
6012 19:52:51.253627 RX DQ/DQS(Engine): PASS
6013 19:52:51.257100 TX OE : NO K
6014 19:52:51.257200 All Pass.
6015 19:52:51.257290
6016 19:52:51.260743 CH 1, Rank 0
6017 19:52:51.260814 SW Impedance : PASS
6018 19:52:51.263924 DUTY Scan : NO K
6019 19:52:51.266934 ZQ Calibration : PASS
6020 19:52:51.267029 Jitter Meter : NO K
6021 19:52:51.270212 CBT Training : PASS
6022 19:52:51.273780 Write leveling : PASS
6023 19:52:51.273875 RX DQS gating : PASS
6024 19:52:51.276969 RX DQ/DQS(RDDQC) : PASS
6025 19:52:51.280545 TX DQ/DQS : PASS
6026 19:52:51.280615 RX DATLAT : PASS
6027 19:52:51.283257 RX DQ/DQS(Engine): PASS
6028 19:52:51.286657 TX OE : NO K
6029 19:52:51.286753 All Pass.
6030 19:52:51.286840
6031 19:52:51.286925 CH 1, Rank 1
6032 19:52:51.290170 SW Impedance : PASS
6033 19:52:51.293268 DUTY Scan : NO K
6034 19:52:51.293362 ZQ Calibration : PASS
6035 19:52:51.296644 Jitter Meter : NO K
6036 19:52:51.296710 CBT Training : PASS
6037 19:52:51.300127 Write leveling : PASS
6038 19:52:51.303304 RX DQS gating : PASS
6039 19:52:51.303404 RX DQ/DQS(RDDQC) : PASS
6040 19:52:51.306810 TX DQ/DQS : PASS
6041 19:52:51.310101 RX DATLAT : PASS
6042 19:52:51.310168 RX DQ/DQS(Engine): PASS
6043 19:52:51.313103 TX OE : NO K
6044 19:52:51.313197 All Pass.
6045 19:52:51.313284
6046 19:52:51.316452 DramC Write-DBI off
6047 19:52:51.320040 PER_BANK_REFRESH: Hybrid Mode
6048 19:52:51.320133 TX_TRACKING: ON
6049 19:52:51.329616 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6050 19:52:51.333133 [FAST_K] Save calibration result to emmc
6051 19:52:51.336206 dramc_set_vcore_voltage set vcore to 650000
6052 19:52:51.339659 Read voltage for 400, 6
6053 19:52:51.339764 Vio18 = 0
6054 19:52:51.339855 Vcore = 650000
6055 19:52:51.342710 Vdram = 0
6056 19:52:51.342803 Vddq = 0
6057 19:52:51.342901 Vmddr = 0
6058 19:52:51.349621 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6059 19:52:51.352796 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6060 19:52:51.356306 MEM_TYPE=3, freq_sel=20
6061 19:52:51.359459 sv_algorithm_assistance_LP4_800
6062 19:52:51.362932 ============ PULL DRAM RESETB DOWN ============
6063 19:52:51.369581 ========== PULL DRAM RESETB DOWN end =========
6064 19:52:51.372432 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6065 19:52:51.375867 ===================================
6066 19:52:51.379388 LPDDR4 DRAM CONFIGURATION
6067 19:52:51.382676 ===================================
6068 19:52:51.382774 EX_ROW_EN[0] = 0x0
6069 19:52:51.386069 EX_ROW_EN[1] = 0x0
6070 19:52:51.386161 LP4Y_EN = 0x0
6071 19:52:51.389341 WORK_FSP = 0x0
6072 19:52:51.389408 WL = 0x2
6073 19:52:51.392935 RL = 0x2
6074 19:52:51.393000 BL = 0x2
6075 19:52:51.395594 RPST = 0x0
6076 19:52:51.395658 RD_PRE = 0x0
6077 19:52:51.399219 WR_PRE = 0x1
6078 19:52:51.402207 WR_PST = 0x0
6079 19:52:51.402300 DBI_WR = 0x0
6080 19:52:51.405862 DBI_RD = 0x0
6081 19:52:51.405956 OTF = 0x1
6082 19:52:51.409059 ===================================
6083 19:52:51.412264 ===================================
6084 19:52:51.415542 ANA top config
6085 19:52:51.415646 ===================================
6086 19:52:51.419218 DLL_ASYNC_EN = 0
6087 19:52:51.422446 ALL_SLAVE_EN = 1
6088 19:52:51.425684 NEW_RANK_MODE = 1
6089 19:52:51.428732 DLL_IDLE_MODE = 1
6090 19:52:51.428801 LP45_APHY_COMB_EN = 1
6091 19:52:51.432639 TX_ODT_DIS = 1
6092 19:52:51.435530 NEW_8X_MODE = 1
6093 19:52:51.439348 ===================================
6094 19:52:51.441940 ===================================
6095 19:52:51.445754 data_rate = 800
6096 19:52:51.448678 CKR = 1
6097 19:52:51.452423 DQ_P2S_RATIO = 4
6098 19:52:51.455840 ===================================
6099 19:52:51.455913 CA_P2S_RATIO = 4
6100 19:52:51.458449 DQ_CA_OPEN = 0
6101 19:52:51.461796 DQ_SEMI_OPEN = 1
6102 19:52:51.465527 CA_SEMI_OPEN = 1
6103 19:52:51.468087 CA_FULL_RATE = 0
6104 19:52:51.471995 DQ_CKDIV4_EN = 0
6105 19:52:51.472071 CA_CKDIV4_EN = 1
6106 19:52:51.474956 CA_PREDIV_EN = 0
6107 19:52:51.478520 PH8_DLY = 0
6108 19:52:51.481422 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6109 19:52:51.484782 DQ_AAMCK_DIV = 0
6110 19:52:51.488252 CA_AAMCK_DIV = 0
6111 19:52:51.488327 CA_ADMCK_DIV = 4
6112 19:52:51.491915 DQ_TRACK_CA_EN = 0
6113 19:52:51.495162 CA_PICK = 800
6114 19:52:51.497831 CA_MCKIO = 400
6115 19:52:51.501243 MCKIO_SEMI = 400
6116 19:52:51.504521 PLL_FREQ = 3016
6117 19:52:51.507811 DQ_UI_PI_RATIO = 32
6118 19:52:51.511393 CA_UI_PI_RATIO = 32
6119 19:52:51.514670 ===================================
6120 19:52:51.517918 ===================================
6121 19:52:51.517989 memory_type:LPDDR4
6122 19:52:51.521005 GP_NUM : 10
6123 19:52:51.524261 SRAM_EN : 1
6124 19:52:51.524333 MD32_EN : 0
6125 19:52:51.528247 ===================================
6126 19:52:51.531166 [ANA_INIT] >>>>>>>>>>>>>>
6127 19:52:51.534200 <<<<<< [CONFIGURE PHASE]: ANA_TX
6128 19:52:51.537747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6129 19:52:51.541086 ===================================
6130 19:52:51.544226 data_rate = 800,PCW = 0X7400
6131 19:52:51.548509 ===================================
6132 19:52:51.550862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6133 19:52:51.554428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6134 19:52:51.567622 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6135 19:52:51.570306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6136 19:52:51.573675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6137 19:52:51.576966 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6138 19:52:51.580987 [ANA_INIT] flow start
6139 19:52:51.583705 [ANA_INIT] PLL >>>>>>>>
6140 19:52:51.583817 [ANA_INIT] PLL <<<<<<<<
6141 19:52:51.587069 [ANA_INIT] MIDPI >>>>>>>>
6142 19:52:51.590359 [ANA_INIT] MIDPI <<<<<<<<
6143 19:52:51.590455 [ANA_INIT] DLL >>>>>>>>
6144 19:52:51.593615 [ANA_INIT] flow end
6145 19:52:51.596836 ============ LP4 DIFF to SE enter ============
6146 19:52:51.600018 ============ LP4 DIFF to SE exit ============
6147 19:52:51.604534 [ANA_INIT] <<<<<<<<<<<<<
6148 19:52:51.606635 [Flow] Enable top DCM control >>>>>
6149 19:52:51.610058 [Flow] Enable top DCM control <<<<<
6150 19:52:51.613146 Enable DLL master slave shuffle
6151 19:52:51.620339 ==============================================================
6152 19:52:51.620439 Gating Mode config
6153 19:52:51.627000 ==============================================================
6154 19:52:51.630000 Config description:
6155 19:52:51.636273 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6156 19:52:51.643311 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6157 19:52:51.649915 SELPH_MODE 0: By rank 1: By Phase
6158 19:52:51.656705 ==============================================================
6159 19:52:51.656783 GAT_TRACK_EN = 0
6160 19:52:51.659412 RX_GATING_MODE = 2
6161 19:52:51.662985 RX_GATING_TRACK_MODE = 2
6162 19:52:51.666188 SELPH_MODE = 1
6163 19:52:51.669358 PICG_EARLY_EN = 1
6164 19:52:51.673372 VALID_LAT_VALUE = 1
6165 19:52:51.679208 ==============================================================
6166 19:52:51.683153 Enter into Gating configuration >>>>
6167 19:52:51.685932 Exit from Gating configuration <<<<
6168 19:52:51.690068 Enter into DVFS_PRE_config >>>>>
6169 19:52:51.699330 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6170 19:52:51.702476 Exit from DVFS_PRE_config <<<<<
6171 19:52:51.705813 Enter into PICG configuration >>>>
6172 19:52:51.710039 Exit from PICG configuration <<<<
6173 19:52:51.712795 [RX_INPUT] configuration >>>>>
6174 19:52:51.715699 [RX_INPUT] configuration <<<<<
6175 19:52:51.718999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6176 19:52:51.726002 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6177 19:52:51.732176 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6178 19:52:51.738765 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6179 19:52:51.742012 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6180 19:52:51.748517 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6181 19:52:51.752002 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6182 19:52:51.758936 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6183 19:52:51.761876 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6184 19:52:51.765173 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6185 19:52:51.768725 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6186 19:52:51.775343 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6187 19:52:51.778508 ===================================
6188 19:52:51.781659 LPDDR4 DRAM CONFIGURATION
6189 19:52:51.781758 ===================================
6190 19:52:51.784891 EX_ROW_EN[0] = 0x0
6191 19:52:51.788391 EX_ROW_EN[1] = 0x0
6192 19:52:51.788489 LP4Y_EN = 0x0
6193 19:52:51.791492 WORK_FSP = 0x0
6194 19:52:51.791590 WL = 0x2
6195 19:52:51.794983 RL = 0x2
6196 19:52:51.795059 BL = 0x2
6197 19:52:51.798560 RPST = 0x0
6198 19:52:51.798658 RD_PRE = 0x0
6199 19:52:51.801594 WR_PRE = 0x1
6200 19:52:51.801674 WR_PST = 0x0
6201 19:52:51.805056 DBI_WR = 0x0
6202 19:52:51.805132 DBI_RD = 0x0
6203 19:52:51.808583 OTF = 0x1
6204 19:52:51.811340 ===================================
6205 19:52:51.814939 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6206 19:52:51.818275 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6207 19:52:51.824783 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6208 19:52:51.828032 ===================================
6209 19:52:51.828132 LPDDR4 DRAM CONFIGURATION
6210 19:52:51.830974 ===================================
6211 19:52:51.834757 EX_ROW_EN[0] = 0x10
6212 19:52:51.838112 EX_ROW_EN[1] = 0x0
6213 19:52:51.838210 LP4Y_EN = 0x0
6214 19:52:51.842404 WORK_FSP = 0x0
6215 19:52:51.842511 WL = 0x2
6216 19:52:51.844596 RL = 0x2
6217 19:52:51.844685 BL = 0x2
6218 19:52:51.847592 RPST = 0x0
6219 19:52:51.847689 RD_PRE = 0x0
6220 19:52:51.851134 WR_PRE = 0x1
6221 19:52:51.851239 WR_PST = 0x0
6222 19:52:51.854444 DBI_WR = 0x0
6223 19:52:51.854541 DBI_RD = 0x0
6224 19:52:51.858260 OTF = 0x1
6225 19:52:51.860870 ===================================
6226 19:52:51.867417 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6227 19:52:51.870931 nWR fixed to 30
6228 19:52:51.874219 [ModeRegInit_LP4] CH0 RK0
6229 19:52:51.874318 [ModeRegInit_LP4] CH0 RK1
6230 19:52:51.877724 [ModeRegInit_LP4] CH1 RK0
6231 19:52:51.880852 [ModeRegInit_LP4] CH1 RK1
6232 19:52:51.880951 match AC timing 19
6233 19:52:51.887636 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6234 19:52:51.890958 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6235 19:52:51.894073 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6236 19:52:51.900360 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6237 19:52:51.903827 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6238 19:52:51.903903 ==
6239 19:52:51.907490 Dram Type= 6, Freq= 0, CH_0, rank 0
6240 19:52:51.910317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 19:52:51.910419 ==
6242 19:52:51.917190 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 19:52:51.923424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6244 19:52:51.926681 [CA 0] Center 36 (8~64) winsize 57
6245 19:52:51.930600 [CA 1] Center 36 (8~64) winsize 57
6246 19:52:51.933397 [CA 2] Center 36 (8~64) winsize 57
6247 19:52:51.936836 [CA 3] Center 36 (8~64) winsize 57
6248 19:52:51.939867 [CA 4] Center 36 (8~64) winsize 57
6249 19:52:51.943295 [CA 5] Center 36 (8~64) winsize 57
6250 19:52:51.943368
6251 19:52:51.946890 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6252 19:52:51.946999
6253 19:52:51.950252 [CATrainingPosCal] consider 1 rank data
6254 19:52:51.953105 u2DelayCellTimex100 = 270/100 ps
6255 19:52:51.956467 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 19:52:51.959576 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 19:52:51.963295 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 19:52:51.966170 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 19:52:51.969531 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 19:52:51.973238 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 19:52:51.973342
6262 19:52:51.979439 CA PerBit enable=1, Macro0, CA PI delay=36
6263 19:52:51.979542
6264 19:52:51.979641 [CBTSetCACLKResult] CA Dly = 36
6265 19:52:51.982820 CS Dly: 1 (0~32)
6266 19:52:51.982922 ==
6267 19:52:51.986066 Dram Type= 6, Freq= 0, CH_0, rank 1
6268 19:52:51.989840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 19:52:51.989946 ==
6270 19:52:51.996129 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6271 19:52:52.002288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6272 19:52:52.005785 [CA 0] Center 36 (8~64) winsize 57
6273 19:52:52.009158 [CA 1] Center 36 (8~64) winsize 57
6274 19:52:52.012728 [CA 2] Center 36 (8~64) winsize 57
6275 19:52:52.015624 [CA 3] Center 36 (8~64) winsize 57
6276 19:52:52.018900 [CA 4] Center 36 (8~64) winsize 57
6277 19:52:52.019003 [CA 5] Center 36 (8~64) winsize 57
6278 19:52:52.022479
6279 19:52:52.025629 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6280 19:52:52.025738
6281 19:52:52.029185 [CATrainingPosCal] consider 2 rank data
6282 19:52:52.032306 u2DelayCellTimex100 = 270/100 ps
6283 19:52:52.035285 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 19:52:52.038925 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 19:52:52.042161 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 19:52:52.045485 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 19:52:52.048453 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 19:52:52.052182 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 19:52:52.052261
6290 19:52:52.055334 CA PerBit enable=1, Macro0, CA PI delay=36
6291 19:52:52.058829
6292 19:52:52.058938 [CBTSetCACLKResult] CA Dly = 36
6293 19:52:52.062582 CS Dly: 1 (0~32)
6294 19:52:52.062686
6295 19:52:52.064961 ----->DramcWriteLeveling(PI) begin...
6296 19:52:52.065126 ==
6297 19:52:52.068589 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 19:52:52.071701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 19:52:52.071830 ==
6300 19:52:52.075358 Write leveling (Byte 0): 40 => 8
6301 19:52:52.078492 Write leveling (Byte 1): 32 => 0
6302 19:52:52.081737 DramcWriteLeveling(PI) end<-----
6303 19:52:52.081816
6304 19:52:52.081897 ==
6305 19:52:52.085166 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 19:52:52.088202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 19:52:52.088275 ==
6308 19:52:52.092291 [Gating] SW mode calibration
6309 19:52:52.098046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6310 19:52:52.105073 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6311 19:52:52.108482 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6312 19:52:52.114837 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6313 19:52:52.118234 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 19:52:52.121317 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6315 19:52:52.128275 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 19:52:52.131196 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 19:52:52.134605 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6318 19:52:52.141498 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 19:52:52.144442 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 19:52:52.147530 Total UI for P1: 0, mck2ui 16
6321 19:52:52.150894 best dqsien dly found for B0: ( 0, 14, 24)
6322 19:52:52.154034 Total UI for P1: 0, mck2ui 16
6323 19:52:52.157529 best dqsien dly found for B1: ( 0, 14, 24)
6324 19:52:52.161032 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6325 19:52:52.164260 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6326 19:52:52.164367
6327 19:52:52.167652 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6328 19:52:52.170733 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6329 19:52:52.174258 [Gating] SW calibration Done
6330 19:52:52.174365 ==
6331 19:52:52.177848 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 19:52:52.183715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 19:52:52.183843 ==
6334 19:52:52.183906 RX Vref Scan: 0
6335 19:52:52.183965
6336 19:52:52.187178 RX Vref 0 -> 0, step: 1
6337 19:52:52.187274
6338 19:52:52.191306 RX Delay -410 -> 252, step: 16
6339 19:52:52.193854 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6340 19:52:52.197472 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6341 19:52:52.203570 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6342 19:52:52.206846 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6343 19:52:52.210296 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6344 19:52:52.213834 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6345 19:52:52.220319 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6346 19:52:52.223431 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6347 19:52:52.226963 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6348 19:52:52.230381 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6349 19:52:52.237194 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6350 19:52:52.240171 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6351 19:52:52.243294 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6352 19:52:52.246859 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6353 19:52:52.253507 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6354 19:52:52.256603 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6355 19:52:52.256708 ==
6356 19:52:52.259689 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 19:52:52.263357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 19:52:52.263432 ==
6359 19:52:52.267301 DQS Delay:
6360 19:52:52.267399 DQS0 = 43, DQS1 = 59
6361 19:52:52.270497 DQM Delay:
6362 19:52:52.270597 DQM0 = 9, DQM1 = 12
6363 19:52:52.270695 DQ Delay:
6364 19:52:52.273180 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6365 19:52:52.276614 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6366 19:52:52.279715 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6367 19:52:52.283229 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6368 19:52:52.283303
6369 19:52:52.283400
6370 19:52:52.283498 ==
6371 19:52:52.286369 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 19:52:52.292823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 19:52:52.292926 ==
6374 19:52:52.293025
6375 19:52:52.293103
6376 19:52:52.293179 TX Vref Scan disable
6377 19:52:52.296436 == TX Byte 0 ==
6378 19:52:52.300191 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 19:52:52.302857 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 19:52:52.306470 == TX Byte 1 ==
6381 19:52:52.309708 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6382 19:52:52.313024 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6383 19:52:52.313098 ==
6384 19:52:52.316176 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 19:52:52.322709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 19:52:52.322810 ==
6387 19:52:52.322908
6388 19:52:52.323004
6389 19:52:52.326220 TX Vref Scan disable
6390 19:52:52.326293 == TX Byte 0 ==
6391 19:52:52.329524 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 19:52:52.335950 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 19:52:52.336029 == TX Byte 1 ==
6394 19:52:52.339103 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6395 19:52:52.345561 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6396 19:52:52.345645
6397 19:52:52.345743 [DATLAT]
6398 19:52:52.345841 Freq=400, CH0 RK0
6399 19:52:52.345940
6400 19:52:52.349015 DATLAT Default: 0xf
6401 19:52:52.352412 0, 0xFFFF, sum = 0
6402 19:52:52.352488 1, 0xFFFF, sum = 0
6403 19:52:52.355654 2, 0xFFFF, sum = 0
6404 19:52:52.355793 3, 0xFFFF, sum = 0
6405 19:52:52.359172 4, 0xFFFF, sum = 0
6406 19:52:52.359256 5, 0xFFFF, sum = 0
6407 19:52:52.362144 6, 0xFFFF, sum = 0
6408 19:52:52.362243 7, 0xFFFF, sum = 0
6409 19:52:52.365782 8, 0xFFFF, sum = 0
6410 19:52:52.365885 9, 0xFFFF, sum = 0
6411 19:52:52.368661 10, 0xFFFF, sum = 0
6412 19:52:52.368733 11, 0xFFFF, sum = 0
6413 19:52:52.372095 12, 0xFFFF, sum = 0
6414 19:52:52.372166 13, 0x0, sum = 1
6415 19:52:52.375649 14, 0x0, sum = 2
6416 19:52:52.375787 15, 0x0, sum = 3
6417 19:52:52.378760 16, 0x0, sum = 4
6418 19:52:52.378834 best_step = 14
6419 19:52:52.378911
6420 19:52:52.378970 ==
6421 19:52:52.382184 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 19:52:52.388516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 19:52:52.388622 ==
6424 19:52:52.388712 RX Vref Scan: 1
6425 19:52:52.388798
6426 19:52:52.392091 RX Vref 0 -> 0, step: 1
6427 19:52:52.392170
6428 19:52:52.395102 RX Delay -359 -> 252, step: 8
6429 19:52:52.395182
6430 19:52:52.398601 Set Vref, RX VrefLevel [Byte0]: 59
6431 19:52:52.402287 [Byte1]: 59
6432 19:52:52.402389
6433 19:52:52.405037 Final RX Vref Byte 0 = 59 to rank0
6434 19:52:52.408522 Final RX Vref Byte 1 = 59 to rank0
6435 19:52:52.411834 Final RX Vref Byte 0 = 59 to rank1
6436 19:52:52.415109 Final RX Vref Byte 1 = 59 to rank1==
6437 19:52:52.418615 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 19:52:52.421624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 19:52:52.424905 ==
6440 19:52:52.424994 DQS Delay:
6441 19:52:52.425074 DQS0 = 48, DQS1 = 56
6442 19:52:52.428403 DQM Delay:
6443 19:52:52.428487 DQM0 = 12, DQM1 = 8
6444 19:52:52.431353 DQ Delay:
6445 19:52:52.431453 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6446 19:52:52.434675 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6447 19:52:52.438698 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6448 19:52:52.441685 DQ12 =12, DQ13 =12, DQ14 =16, DQ15 =16
6449 19:52:52.441763
6450 19:52:52.441842
6451 19:52:52.451325 [DQSOSCAuto] RK0, (LSB)MR18= 0xbf84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6452 19:52:52.454598 CH0 RK0: MR19=C0C, MR18=BF84
6453 19:52:52.461255 CH0_RK0: MR19=0xC0C, MR18=0xBF84, DQSOSC=386, MR23=63, INC=396, DEC=264
6454 19:52:52.461334 ==
6455 19:52:52.464710 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 19:52:52.468505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 19:52:52.468609 ==
6458 19:52:52.471244 [Gating] SW mode calibration
6459 19:52:52.477777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6460 19:52:52.484894 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6461 19:52:52.487877 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6462 19:52:52.490982 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6463 19:52:52.497243 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 19:52:52.500636 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6465 19:52:52.504290 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 19:52:52.510862 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 19:52:52.514479 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 19:52:52.517422 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 19:52:52.523673 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 19:52:52.523804 Total UI for P1: 0, mck2ui 16
6471 19:52:52.527630 best dqsien dly found for B0: ( 0, 14, 24)
6472 19:52:52.530233 Total UI for P1: 0, mck2ui 16
6473 19:52:52.533741 best dqsien dly found for B1: ( 0, 14, 24)
6474 19:52:52.540112 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6475 19:52:52.543760 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6476 19:52:52.543872
6477 19:52:52.546775 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6478 19:52:52.550193 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6479 19:52:52.553275 [Gating] SW calibration Done
6480 19:52:52.553373 ==
6481 19:52:52.556967 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 19:52:52.560414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 19:52:52.560491 ==
6484 19:52:52.563253 RX Vref Scan: 0
6485 19:52:52.563331
6486 19:52:52.563413 RX Vref 0 -> 0, step: 1
6487 19:52:52.563490
6488 19:52:52.566615 RX Delay -410 -> 252, step: 16
6489 19:52:52.573323 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6490 19:52:52.576631 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6491 19:52:52.579604 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6492 19:52:52.583172 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6493 19:52:52.589757 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6494 19:52:52.593111 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6495 19:52:52.596326 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6496 19:52:52.600032 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6497 19:52:52.606296 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6498 19:52:52.609569 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6499 19:52:52.612903 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6500 19:52:52.615998 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6501 19:52:52.622556 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6502 19:52:52.625966 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6503 19:52:52.629642 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6504 19:52:52.635874 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6505 19:52:52.635977 ==
6506 19:52:52.639381 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 19:52:52.642756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 19:52:52.642836 ==
6509 19:52:52.642916 DQS Delay:
6510 19:52:52.645864 DQS0 = 43, DQS1 = 59
6511 19:52:52.645962 DQM Delay:
6512 19:52:52.649065 DQM0 = 13, DQM1 = 17
6513 19:52:52.649142 DQ Delay:
6514 19:52:52.653065 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6515 19:52:52.656005 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6516 19:52:52.658913 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6517 19:52:52.662452 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =24
6518 19:52:52.662553
6519 19:52:52.662633
6520 19:52:52.662710 ==
6521 19:52:52.665686 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 19:52:52.668990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 19:52:52.669093 ==
6524 19:52:52.669190
6525 19:52:52.669292
6526 19:52:52.671965 TX Vref Scan disable
6527 19:52:52.675627 == TX Byte 0 ==
6528 19:52:52.678909 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6529 19:52:52.681909 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6530 19:52:52.685113 == TX Byte 1 ==
6531 19:52:52.688836 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6532 19:52:52.692268 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6533 19:52:52.692346 ==
6534 19:52:52.695354 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 19:52:52.698430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 19:52:52.698506 ==
6537 19:52:52.698602
6538 19:52:52.701673
6539 19:52:52.701746 TX Vref Scan disable
6540 19:52:52.705216 == TX Byte 0 ==
6541 19:52:52.708199 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6542 19:52:52.711429 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6543 19:52:52.715343 == TX Byte 1 ==
6544 19:52:52.718534 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6545 19:52:52.721863 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6546 19:52:52.721961
6547 19:52:52.722068 [DATLAT]
6548 19:52:52.725099 Freq=400, CH0 RK1
6549 19:52:52.725169
6550 19:52:52.728186 DATLAT Default: 0xe
6551 19:52:52.728256 0, 0xFFFF, sum = 0
6552 19:52:52.731401 1, 0xFFFF, sum = 0
6553 19:52:52.731501 2, 0xFFFF, sum = 0
6554 19:52:52.735050 3, 0xFFFF, sum = 0
6555 19:52:52.735122 4, 0xFFFF, sum = 0
6556 19:52:52.738021 5, 0xFFFF, sum = 0
6557 19:52:52.738095 6, 0xFFFF, sum = 0
6558 19:52:52.741342 7, 0xFFFF, sum = 0
6559 19:52:52.741418 8, 0xFFFF, sum = 0
6560 19:52:52.744719 9, 0xFFFF, sum = 0
6561 19:52:52.744790 10, 0xFFFF, sum = 0
6562 19:52:52.748093 11, 0xFFFF, sum = 0
6563 19:52:52.748163 12, 0xFFFF, sum = 0
6564 19:52:52.751559 13, 0x0, sum = 1
6565 19:52:52.751657 14, 0x0, sum = 2
6566 19:52:52.754256 15, 0x0, sum = 3
6567 19:52:52.754353 16, 0x0, sum = 4
6568 19:52:52.757909 best_step = 14
6569 19:52:52.757985
6570 19:52:52.758046 ==
6571 19:52:52.761029 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 19:52:52.764509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 19:52:52.764581 ==
6574 19:52:52.767503 RX Vref Scan: 0
6575 19:52:52.767571
6576 19:52:52.767628 RX Vref 0 -> 0, step: 1
6577 19:52:52.767684
6578 19:52:52.770783 RX Delay -359 -> 252, step: 8
6579 19:52:52.779387 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6580 19:52:52.782640 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6581 19:52:52.785497 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6582 19:52:52.792254 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6583 19:52:52.795855 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6584 19:52:52.799335 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6585 19:52:52.802288 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6586 19:52:52.809003 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6587 19:52:52.811946 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6588 19:52:52.815490 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6589 19:52:52.818537 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6590 19:52:52.825611 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6591 19:52:52.828431 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6592 19:52:52.831976 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6593 19:52:52.835144 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6594 19:52:52.841655 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6595 19:52:52.841729 ==
6596 19:52:52.845034 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 19:52:52.848363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 19:52:52.848435 ==
6599 19:52:52.848495 DQS Delay:
6600 19:52:52.851938 DQS0 = 44, DQS1 = 56
6601 19:52:52.852008 DQM Delay:
6602 19:52:52.855137 DQM0 = 7, DQM1 = 11
6603 19:52:52.855236 DQ Delay:
6604 19:52:52.858327 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6605 19:52:52.861691 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6606 19:52:52.864749 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6607 19:52:52.868029 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6608 19:52:52.868125
6609 19:52:52.868213
6610 19:52:52.874752 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe49, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6611 19:52:52.877904 CH0 RK1: MR19=C0C, MR18=BE49
6612 19:52:52.884510 CH0_RK1: MR19=0xC0C, MR18=0xBE49, DQSOSC=386, MR23=63, INC=396, DEC=264
6613 19:52:52.887709 [RxdqsGatingPostProcess] freq 400
6614 19:52:52.895445 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6615 19:52:52.897537 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 19:52:52.900805 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 19:52:52.904199 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 19:52:52.907644 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 19:52:52.910615 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 19:52:52.910713 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 19:52:52.914128 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 19:52:52.917442 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 19:52:52.920482 Pre-setting of DQS Precalculation
6624 19:52:52.927674 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6625 19:52:52.927788 ==
6626 19:52:52.930820 Dram Type= 6, Freq= 0, CH_1, rank 0
6627 19:52:52.933754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 19:52:52.933840 ==
6629 19:52:52.940155 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 19:52:52.947118 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6631 19:52:52.950800 [CA 0] Center 36 (8~64) winsize 57
6632 19:52:52.953558 [CA 1] Center 36 (8~64) winsize 57
6633 19:52:52.956917 [CA 2] Center 36 (8~64) winsize 57
6634 19:52:52.957015 [CA 3] Center 36 (8~64) winsize 57
6635 19:52:52.960333 [CA 4] Center 36 (8~64) winsize 57
6636 19:52:52.964144 [CA 5] Center 36 (8~64) winsize 57
6637 19:52:52.964215
6638 19:52:52.969910 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6639 19:52:52.970007
6640 19:52:52.973347 [CATrainingPosCal] consider 1 rank data
6641 19:52:52.976691 u2DelayCellTimex100 = 270/100 ps
6642 19:52:52.979998 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 19:52:52.983435 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 19:52:52.986433 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 19:52:52.989655 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 19:52:52.993110 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 19:52:52.996374 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 19:52:52.996454
6649 19:52:52.999980 CA PerBit enable=1, Macro0, CA PI delay=36
6650 19:52:53.000060
6651 19:52:53.002902 [CBTSetCACLKResult] CA Dly = 36
6652 19:52:53.006593 CS Dly: 1 (0~32)
6653 19:52:53.006672 ==
6654 19:52:53.009986 Dram Type= 6, Freq= 0, CH_1, rank 1
6655 19:52:53.013360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 19:52:53.013441 ==
6657 19:52:53.019679 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6658 19:52:53.023046 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6659 19:52:53.026625 [CA 0] Center 36 (8~64) winsize 57
6660 19:52:53.029723 [CA 1] Center 36 (8~64) winsize 57
6661 19:52:53.033368 [CA 2] Center 36 (8~64) winsize 57
6662 19:52:53.036222 [CA 3] Center 36 (8~64) winsize 57
6663 19:52:53.039568 [CA 4] Center 36 (8~64) winsize 57
6664 19:52:53.042891 [CA 5] Center 36 (8~64) winsize 57
6665 19:52:53.042963
6666 19:52:53.045943 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6667 19:52:53.046046
6668 19:52:53.052488 [CATrainingPosCal] consider 2 rank data
6669 19:52:53.052564 u2DelayCellTimex100 = 270/100 ps
6670 19:52:53.055920 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 19:52:53.062466 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 19:52:53.065828 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 19:52:53.069371 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 19:52:53.072617 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 19:52:53.076065 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 19:52:53.076145
6677 19:52:53.079111 CA PerBit enable=1, Macro0, CA PI delay=36
6678 19:52:53.079191
6679 19:52:53.082301 [CBTSetCACLKResult] CA Dly = 36
6680 19:52:53.085356 CS Dly: 1 (0~32)
6681 19:52:53.085436
6682 19:52:53.089255 ----->DramcWriteLeveling(PI) begin...
6683 19:52:53.089336 ==
6684 19:52:53.092789 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 19:52:53.095083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 19:52:53.095164 ==
6687 19:52:53.098468 Write leveling (Byte 0): 40 => 8
6688 19:52:53.102430 Write leveling (Byte 1): 40 => 8
6689 19:52:53.105365 DramcWriteLeveling(PI) end<-----
6690 19:52:53.105445
6691 19:52:53.105507 ==
6692 19:52:53.108917 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 19:52:53.111637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 19:52:53.111734 ==
6695 19:52:53.114718 [Gating] SW mode calibration
6696 19:52:53.121518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6697 19:52:53.127987 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6698 19:52:53.131613 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6699 19:52:53.137688 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6700 19:52:53.141242 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 19:52:53.144367 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6702 19:52:53.151614 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 19:52:53.154725 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 19:52:53.157831 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6705 19:52:53.164605 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 19:52:53.167579 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 19:52:53.171048 Total UI for P1: 0, mck2ui 16
6708 19:52:53.174171 best dqsien dly found for B0: ( 0, 14, 24)
6709 19:52:53.177255 Total UI for P1: 0, mck2ui 16
6710 19:52:53.181003 best dqsien dly found for B1: ( 0, 14, 24)
6711 19:52:53.184283 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6712 19:52:53.187496 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6713 19:52:53.187573
6714 19:52:53.190517 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6715 19:52:53.194991 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6716 19:52:53.197189 [Gating] SW calibration Done
6717 19:52:53.197276 ==
6718 19:52:53.201021 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 19:52:53.204025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 19:52:53.207216 ==
6721 19:52:53.207315 RX Vref Scan: 0
6722 19:52:53.207404
6723 19:52:53.210352 RX Vref 0 -> 0, step: 1
6724 19:52:53.210448
6725 19:52:53.213611 RX Delay -410 -> 252, step: 16
6726 19:52:53.217274 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6727 19:52:53.221111 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6728 19:52:53.223936 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6729 19:52:53.230150 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6730 19:52:53.233821 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6731 19:52:53.237106 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6732 19:52:53.240035 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6733 19:52:53.247252 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6734 19:52:53.249855 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6735 19:52:53.253323 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6736 19:52:53.256774 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6737 19:52:53.263193 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6738 19:52:53.266633 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6739 19:52:53.269705 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6740 19:52:53.276846 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6741 19:52:53.279481 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6742 19:52:53.279580 ==
6743 19:52:53.282922 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 19:52:53.286318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 19:52:53.286425 ==
6746 19:52:53.289690 DQS Delay:
6747 19:52:53.289789 DQS0 = 43, DQS1 = 51
6748 19:52:53.289886 DQM Delay:
6749 19:52:53.292748 DQM0 = 12, DQM1 = 14
6750 19:52:53.292833 DQ Delay:
6751 19:52:53.296102 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6752 19:52:53.299314 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6753 19:52:53.302550 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6754 19:52:53.306016 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6755 19:52:53.306099
6756 19:52:53.306162
6757 19:52:53.306220 ==
6758 19:52:53.309482 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 19:52:53.312616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 19:52:53.315810 ==
6761 19:52:53.315915
6762 19:52:53.315980
6763 19:52:53.316038 TX Vref Scan disable
6764 19:52:53.319506 == TX Byte 0 ==
6765 19:52:53.322395 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 19:52:53.326052 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 19:52:53.329150 == TX Byte 1 ==
6768 19:52:53.332662 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 19:52:53.335558 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 19:52:53.335656 ==
6771 19:52:53.338856 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 19:52:53.345618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 19:52:53.345698 ==
6774 19:52:53.345761
6775 19:52:53.345820
6776 19:52:53.345879 TX Vref Scan disable
6777 19:52:53.348863 == TX Byte 0 ==
6778 19:52:53.352421 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 19:52:53.355137 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 19:52:53.358884 == TX Byte 1 ==
6781 19:52:53.361748 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 19:52:53.365432 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 19:52:53.368570
6784 19:52:53.368645 [DATLAT]
6785 19:52:53.368708 Freq=400, CH1 RK0
6786 19:52:53.368774
6787 19:52:53.371636 DATLAT Default: 0xf
6788 19:52:53.371739 0, 0xFFFF, sum = 0
6789 19:52:53.375319 1, 0xFFFF, sum = 0
6790 19:52:53.375419 2, 0xFFFF, sum = 0
6791 19:52:53.378172 3, 0xFFFF, sum = 0
6792 19:52:53.378284 4, 0xFFFF, sum = 0
6793 19:52:53.381706 5, 0xFFFF, sum = 0
6794 19:52:53.384964 6, 0xFFFF, sum = 0
6795 19:52:53.385036 7, 0xFFFF, sum = 0
6796 19:52:53.389006 8, 0xFFFF, sum = 0
6797 19:52:53.389076 9, 0xFFFF, sum = 0
6798 19:52:53.391647 10, 0xFFFF, sum = 0
6799 19:52:53.391778 11, 0xFFFF, sum = 0
6800 19:52:53.394801 12, 0xFFFF, sum = 0
6801 19:52:53.394898 13, 0x0, sum = 1
6802 19:52:53.397880 14, 0x0, sum = 2
6803 19:52:53.397980 15, 0x0, sum = 3
6804 19:52:53.401353 16, 0x0, sum = 4
6805 19:52:53.401422 best_step = 14
6806 19:52:53.401481
6807 19:52:53.401542 ==
6808 19:52:53.404615 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 19:52:53.407900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 19:52:53.411363 ==
6811 19:52:53.411455 RX Vref Scan: 1
6812 19:52:53.411516
6813 19:52:53.414605 RX Vref 0 -> 0, step: 1
6814 19:52:53.414682
6815 19:52:53.418243 RX Delay -343 -> 252, step: 8
6816 19:52:53.418339
6817 19:52:53.421305 Set Vref, RX VrefLevel [Byte0]: 50
6818 19:52:53.424465 [Byte1]: 53
6819 19:52:53.424536
6820 19:52:53.427887 Final RX Vref Byte 0 = 50 to rank0
6821 19:52:53.431521 Final RX Vref Byte 1 = 53 to rank0
6822 19:52:53.434509 Final RX Vref Byte 0 = 50 to rank1
6823 19:52:53.437968 Final RX Vref Byte 1 = 53 to rank1==
6824 19:52:53.440864 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 19:52:53.444266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 19:52:53.444341 ==
6827 19:52:53.447643 DQS Delay:
6828 19:52:53.447775 DQS0 = 44, DQS1 = 56
6829 19:52:53.451066 DQM Delay:
6830 19:52:53.451137 DQM0 = 7, DQM1 = 12
6831 19:52:53.451198 DQ Delay:
6832 19:52:53.454459 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
6833 19:52:53.458129 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6834 19:52:53.461732 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6835 19:52:53.464341 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6836 19:52:53.464437
6837 19:52:53.464502
6838 19:52:53.473959 [DQSOSCAuto] RK0, (LSB)MR18= 0x976e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6839 19:52:53.477351 CH1 RK0: MR19=C0C, MR18=976E
6840 19:52:53.480543 CH1_RK0: MR19=0xC0C, MR18=0x976E, DQSOSC=390, MR23=63, INC=388, DEC=258
6841 19:52:53.484216 ==
6842 19:52:53.487060 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 19:52:53.490534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 19:52:53.490609 ==
6845 19:52:53.493714 [Gating] SW mode calibration
6846 19:52:53.500911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6847 19:52:53.503569 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6848 19:52:53.510372 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6849 19:52:53.513687 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6850 19:52:53.516888 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 19:52:53.523251 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6852 19:52:53.526864 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 19:52:53.530057 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 19:52:53.537009 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6855 19:52:53.539967 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 19:52:53.543012 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 19:52:53.546633 Total UI for P1: 0, mck2ui 16
6858 19:52:53.549894 best dqsien dly found for B0: ( 0, 14, 24)
6859 19:52:53.552931 Total UI for P1: 0, mck2ui 16
6860 19:52:53.556776 best dqsien dly found for B1: ( 0, 14, 24)
6861 19:52:53.559784 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6862 19:52:53.563496 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6863 19:52:53.566547
6864 19:52:53.569641 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6865 19:52:53.572699 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6866 19:52:53.576161 [Gating] SW calibration Done
6867 19:52:53.576233 ==
6868 19:52:53.579924 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 19:52:53.582991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 19:52:53.583064 ==
6871 19:52:53.585955 RX Vref Scan: 0
6872 19:52:53.586053
6873 19:52:53.586141 RX Vref 0 -> 0, step: 1
6874 19:52:53.586225
6875 19:52:53.589077 RX Delay -410 -> 252, step: 16
6876 19:52:53.592630 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6877 19:52:53.598992 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6878 19:52:53.602584 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6879 19:52:53.605540 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6880 19:52:53.609004 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6881 19:52:53.615733 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6882 19:52:53.619229 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6883 19:52:53.622373 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6884 19:52:53.625654 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6885 19:52:53.632376 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6886 19:52:53.635376 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6887 19:52:53.638671 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6888 19:52:53.645489 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6889 19:52:53.648867 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6890 19:52:53.651709 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6891 19:52:53.655366 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6892 19:52:53.658418 ==
6893 19:52:53.661624 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 19:52:53.665115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 19:52:53.665199 ==
6896 19:52:53.665262 DQS Delay:
6897 19:52:53.668193 DQS0 = 51, DQS1 = 51
6898 19:52:53.668261 DQM Delay:
6899 19:52:53.671641 DQM0 = 19, DQM1 = 15
6900 19:52:53.671776 DQ Delay:
6901 19:52:53.674998 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6902 19:52:53.678214 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6903 19:52:53.681363 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6904 19:52:53.684855 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6905 19:52:53.684936
6906 19:52:53.684999
6907 19:52:53.685055 ==
6908 19:52:53.687943 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 19:52:53.691561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 19:52:53.691655 ==
6911 19:52:53.691792
6912 19:52:53.691859
6913 19:52:53.694917 TX Vref Scan disable
6914 19:52:53.695017 == TX Byte 0 ==
6915 19:52:53.701787 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6916 19:52:53.704483 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6917 19:52:53.704555 == TX Byte 1 ==
6918 19:52:53.710969 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6919 19:52:53.714188 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6920 19:52:53.714257 ==
6921 19:52:53.717718 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 19:52:53.721143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 19:52:53.721252 ==
6924 19:52:53.721343
6925 19:52:53.721429
6926 19:52:53.724486 TX Vref Scan disable
6927 19:52:53.727590 == TX Byte 0 ==
6928 19:52:53.731355 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6929 19:52:53.733981 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6930 19:52:53.737305 == TX Byte 1 ==
6931 19:52:53.740852 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6932 19:52:53.743955 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6933 19:52:53.744028
6934 19:52:53.744109 [DATLAT]
6935 19:52:53.747661 Freq=400, CH1 RK1
6936 19:52:53.747773
6937 19:52:53.747838 DATLAT Default: 0xe
6938 19:52:53.750716 0, 0xFFFF, sum = 0
6939 19:52:53.754080 1, 0xFFFF, sum = 0
6940 19:52:53.754190 2, 0xFFFF, sum = 0
6941 19:52:53.757272 3, 0xFFFF, sum = 0
6942 19:52:53.757381 4, 0xFFFF, sum = 0
6943 19:52:53.760550 5, 0xFFFF, sum = 0
6944 19:52:53.760627 6, 0xFFFF, sum = 0
6945 19:52:53.763761 7, 0xFFFF, sum = 0
6946 19:52:53.763853 8, 0xFFFF, sum = 0
6947 19:52:53.767254 9, 0xFFFF, sum = 0
6948 19:52:53.767327 10, 0xFFFF, sum = 0
6949 19:52:53.770229 11, 0xFFFF, sum = 0
6950 19:52:53.770336 12, 0xFFFF, sum = 0
6951 19:52:53.773722 13, 0x0, sum = 1
6952 19:52:53.773832 14, 0x0, sum = 2
6953 19:52:53.777031 15, 0x0, sum = 3
6954 19:52:53.777131 16, 0x0, sum = 4
6955 19:52:53.780851 best_step = 14
6956 19:52:53.780928
6957 19:52:53.780988 ==
6958 19:52:53.783926 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 19:52:53.787143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 19:52:53.787245 ==
6961 19:52:53.790220 RX Vref Scan: 0
6962 19:52:53.790324
6963 19:52:53.790412 RX Vref 0 -> 0, step: 1
6964 19:52:53.790506
6965 19:52:53.793900 RX Delay -343 -> 252, step: 8
6966 19:52:53.801672 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6967 19:52:53.805003 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6968 19:52:53.807963 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6969 19:52:53.814709 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6970 19:52:53.817976 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6971 19:52:53.821357 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6972 19:52:53.824346 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6973 19:52:53.831128 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6974 19:52:53.834452 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6975 19:52:53.838819 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6976 19:52:53.840925 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6977 19:52:53.847335 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6978 19:52:53.850607 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6979 19:52:53.854066 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6980 19:52:53.857590 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6981 19:52:53.864019 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
6982 19:52:53.864092 ==
6983 19:52:53.867369 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 19:52:53.870752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 19:52:53.870853 ==
6986 19:52:53.870942 DQS Delay:
6987 19:52:53.874175 DQS0 = 48, DQS1 = 56
6988 19:52:53.874275 DQM Delay:
6989 19:52:53.877540 DQM0 = 12, DQM1 = 11
6990 19:52:53.877636 DQ Delay:
6991 19:52:53.880570 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
6992 19:52:53.883983 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6993 19:52:53.887053 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6994 19:52:53.890994 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6995 19:52:53.891104
6996 19:52:53.891196
6997 19:52:53.897147 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
6998 19:52:53.900855 CH1 RK1: MR19=C0C, MR18=6B5B
6999 19:52:53.907041 CH1_RK1: MR19=0xC0C, MR18=0x6B5B, DQSOSC=396, MR23=63, INC=376, DEC=251
7000 19:52:53.910871 [RxdqsGatingPostProcess] freq 400
7001 19:52:53.917433 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7002 19:52:53.920302 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 19:52:53.923504 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 19:52:53.926897 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 19:52:53.930480 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 19:52:53.930579 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 19:52:53.933440 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 19:52:53.936663 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 19:52:53.940286 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 19:52:53.943311 Pre-setting of DQS Precalculation
7011 19:52:53.949990 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7012 19:52:53.956901 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7013 19:52:53.963412 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7014 19:52:53.963511
7015 19:52:53.963611
7016 19:52:53.966485 [Calibration Summary] 800 Mbps
7017 19:52:53.966568 CH 0, Rank 0
7018 19:52:53.970259 SW Impedance : PASS
7019 19:52:53.972988 DUTY Scan : NO K
7020 19:52:53.973063 ZQ Calibration : PASS
7021 19:52:53.976582 Jitter Meter : NO K
7022 19:52:53.979918 CBT Training : PASS
7023 19:52:53.979992 Write leveling : PASS
7024 19:52:53.983117 RX DQS gating : PASS
7025 19:52:53.986699 RX DQ/DQS(RDDQC) : PASS
7026 19:52:53.986792 TX DQ/DQS : PASS
7027 19:52:53.989573 RX DATLAT : PASS
7028 19:52:53.992733 RX DQ/DQS(Engine): PASS
7029 19:52:53.992804 TX OE : NO K
7030 19:52:53.996554 All Pass.
7031 19:52:53.996626
7032 19:52:53.996686 CH 0, Rank 1
7033 19:52:53.999660 SW Impedance : PASS
7034 19:52:53.999760 DUTY Scan : NO K
7035 19:52:54.002943 ZQ Calibration : PASS
7036 19:52:54.006034 Jitter Meter : NO K
7037 19:52:54.006133 CBT Training : PASS
7038 19:52:54.010221 Write leveling : NO K
7039 19:52:54.012932 RX DQS gating : PASS
7040 19:52:54.013008 RX DQ/DQS(RDDQC) : PASS
7041 19:52:54.016026 TX DQ/DQS : PASS
7042 19:52:54.019214 RX DATLAT : PASS
7043 19:52:54.019311 RX DQ/DQS(Engine): PASS
7044 19:52:54.023081 TX OE : NO K
7045 19:52:54.023181 All Pass.
7046 19:52:54.023270
7047 19:52:54.025904 CH 1, Rank 0
7048 19:52:54.026000 SW Impedance : PASS
7049 19:52:54.029369 DUTY Scan : NO K
7050 19:52:54.032284 ZQ Calibration : PASS
7051 19:52:54.032356 Jitter Meter : NO K
7052 19:52:54.036131 CBT Training : PASS
7053 19:52:54.036230 Write leveling : PASS
7054 19:52:54.039131 RX DQS gating : PASS
7055 19:52:54.042688 RX DQ/DQS(RDDQC) : PASS
7056 19:52:54.042771 TX DQ/DQS : PASS
7057 19:52:54.045667 RX DATLAT : PASS
7058 19:52:54.049273 RX DQ/DQS(Engine): PASS
7059 19:52:54.049348 TX OE : NO K
7060 19:52:54.051952 All Pass.
7061 19:52:54.052027
7062 19:52:54.052089 CH 1, Rank 1
7063 19:52:54.055310 SW Impedance : PASS
7064 19:52:54.055384 DUTY Scan : NO K
7065 19:52:54.058883 ZQ Calibration : PASS
7066 19:52:54.062483 Jitter Meter : NO K
7067 19:52:54.062584 CBT Training : PASS
7068 19:52:54.065465 Write leveling : NO K
7069 19:52:54.068952 RX DQS gating : PASS
7070 19:52:54.069049 RX DQ/DQS(RDDQC) : PASS
7071 19:52:54.072038 TX DQ/DQS : PASS
7072 19:52:54.075180 RX DATLAT : PASS
7073 19:52:54.075253 RX DQ/DQS(Engine): PASS
7074 19:52:54.078886 TX OE : NO K
7075 19:52:54.078959 All Pass.
7076 19:52:54.079026
7077 19:52:54.081803 DramC Write-DBI off
7078 19:52:54.085480 PER_BANK_REFRESH: Hybrid Mode
7079 19:52:54.085588 TX_TRACKING: ON
7080 19:52:54.094993 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7081 19:52:54.098225 [FAST_K] Save calibration result to emmc
7082 19:52:54.102035 dramc_set_vcore_voltage set vcore to 725000
7083 19:52:54.105135 Read voltage for 1600, 0
7084 19:52:54.105214 Vio18 = 0
7085 19:52:54.105280 Vcore = 725000
7086 19:52:54.107928 Vdram = 0
7087 19:52:54.108003 Vddq = 0
7088 19:52:54.108063 Vmddr = 0
7089 19:52:54.114690 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7090 19:52:54.118087 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7091 19:52:54.121331 MEM_TYPE=3, freq_sel=13
7092 19:52:54.124668 sv_algorithm_assistance_LP4_3733
7093 19:52:54.127899 ============ PULL DRAM RESETB DOWN ============
7094 19:52:54.134567 ========== PULL DRAM RESETB DOWN end =========
7095 19:52:54.137635 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7096 19:52:54.140987 ===================================
7097 19:52:54.144572 LPDDR4 DRAM CONFIGURATION
7098 19:52:54.148110 ===================================
7099 19:52:54.148210 EX_ROW_EN[0] = 0x0
7100 19:52:54.151449 EX_ROW_EN[1] = 0x0
7101 19:52:54.151545 LP4Y_EN = 0x0
7102 19:52:54.154399 WORK_FSP = 0x1
7103 19:52:54.154470 WL = 0x5
7104 19:52:54.157449 RL = 0x5
7105 19:52:54.157526 BL = 0x2
7106 19:52:54.160829 RPST = 0x0
7107 19:52:54.164205 RD_PRE = 0x0
7108 19:52:54.164311 WR_PRE = 0x1
7109 19:52:54.167241 WR_PST = 0x1
7110 19:52:54.167380 DBI_WR = 0x0
7111 19:52:54.171047 DBI_RD = 0x0
7112 19:52:54.171143 OTF = 0x1
7113 19:52:54.174182 ===================================
7114 19:52:54.177327 ===================================
7115 19:52:54.180678 ANA top config
7116 19:52:54.183881 ===================================
7117 19:52:54.183953 DLL_ASYNC_EN = 0
7118 19:52:54.187019 ALL_SLAVE_EN = 0
7119 19:52:54.190571 NEW_RANK_MODE = 1
7120 19:52:54.193796 DLL_IDLE_MODE = 1
7121 19:52:54.197000 LP45_APHY_COMB_EN = 1
7122 19:52:54.197079 TX_ODT_DIS = 0
7123 19:52:54.200640 NEW_8X_MODE = 1
7124 19:52:54.204006 ===================================
7125 19:52:54.206972 ===================================
7126 19:52:54.210061 data_rate = 3200
7127 19:52:54.213497 CKR = 1
7128 19:52:54.216823 DQ_P2S_RATIO = 8
7129 19:52:54.220606 ===================================
7130 19:52:54.223698 CA_P2S_RATIO = 8
7131 19:52:54.223840 DQ_CA_OPEN = 0
7132 19:52:54.226610 DQ_SEMI_OPEN = 0
7133 19:52:54.230001 CA_SEMI_OPEN = 0
7134 19:52:54.233483 CA_FULL_RATE = 0
7135 19:52:54.236373 DQ_CKDIV4_EN = 0
7136 19:52:54.240076 CA_CKDIV4_EN = 0
7137 19:52:54.240150 CA_PREDIV_EN = 0
7138 19:52:54.242880 PH8_DLY = 12
7139 19:52:54.246287 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7140 19:52:54.249949 DQ_AAMCK_DIV = 4
7141 19:52:54.252920 CA_AAMCK_DIV = 4
7142 19:52:54.256554 CA_ADMCK_DIV = 4
7143 19:52:54.256626 DQ_TRACK_CA_EN = 0
7144 19:52:54.259345 CA_PICK = 1600
7145 19:52:54.262588 CA_MCKIO = 1600
7146 19:52:54.265986 MCKIO_SEMI = 0
7147 19:52:54.269776 PLL_FREQ = 3068
7148 19:52:54.272556 DQ_UI_PI_RATIO = 32
7149 19:52:54.275841 CA_UI_PI_RATIO = 0
7150 19:52:54.279666 ===================================
7151 19:52:54.282845 ===================================
7152 19:52:54.282967 memory_type:LPDDR4
7153 19:52:54.286708 GP_NUM : 10
7154 19:52:54.289244 SRAM_EN : 1
7155 19:52:54.289324 MD32_EN : 0
7156 19:52:54.292895 ===================================
7157 19:52:54.295797 [ANA_INIT] >>>>>>>>>>>>>>
7158 19:52:54.300040 <<<<<< [CONFIGURE PHASE]: ANA_TX
7159 19:52:54.302843 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7160 19:52:54.306167 ===================================
7161 19:52:54.308973 data_rate = 3200,PCW = 0X7600
7162 19:52:54.312363 ===================================
7163 19:52:54.315988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7164 19:52:54.319607 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7165 19:52:54.325795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7166 19:52:54.328953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7167 19:52:54.332537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7168 19:52:54.339393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7169 19:52:54.339474 [ANA_INIT] flow start
7170 19:52:54.342192 [ANA_INIT] PLL >>>>>>>>
7171 19:52:54.342272 [ANA_INIT] PLL <<<<<<<<
7172 19:52:54.345762 [ANA_INIT] MIDPI >>>>>>>>
7173 19:52:54.348826 [ANA_INIT] MIDPI <<<<<<<<
7174 19:52:54.352199 [ANA_INIT] DLL >>>>>>>>
7175 19:52:54.352278 [ANA_INIT] DLL <<<<<<<<
7176 19:52:54.355410 [ANA_INIT] flow end
7177 19:52:54.358726 ============ LP4 DIFF to SE enter ============
7178 19:52:54.361998 ============ LP4 DIFF to SE exit ============
7179 19:52:54.366125 [ANA_INIT] <<<<<<<<<<<<<
7180 19:52:54.369051 [Flow] Enable top DCM control >>>>>
7181 19:52:54.372485 [Flow] Enable top DCM control <<<<<
7182 19:52:54.375471 Enable DLL master slave shuffle
7183 19:52:54.382500 ==============================================================
7184 19:52:54.382662 Gating Mode config
7185 19:52:54.388772 ==============================================================
7186 19:52:54.388930 Config description:
7187 19:52:54.398596 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7188 19:52:54.405656 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7189 19:52:54.411967 SELPH_MODE 0: By rank 1: By Phase
7190 19:52:54.415095 ==============================================================
7191 19:52:54.418557 GAT_TRACK_EN = 1
7192 19:52:54.421987 RX_GATING_MODE = 2
7193 19:52:54.425256 RX_GATING_TRACK_MODE = 2
7194 19:52:54.429016 SELPH_MODE = 1
7195 19:52:54.431754 PICG_EARLY_EN = 1
7196 19:52:54.435476 VALID_LAT_VALUE = 1
7197 19:52:54.441955 ==============================================================
7198 19:52:54.445385 Enter into Gating configuration >>>>
7199 19:52:54.448692 Exit from Gating configuration <<<<
7200 19:52:54.451882 Enter into DVFS_PRE_config >>>>>
7201 19:52:54.462168 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7202 19:52:54.465250 Exit from DVFS_PRE_config <<<<<
7203 19:52:54.468263 Enter into PICG configuration >>>>
7204 19:52:54.471797 Exit from PICG configuration <<<<
7205 19:52:54.475077 [RX_INPUT] configuration >>>>>
7206 19:52:54.475573 [RX_INPUT] configuration <<<<<
7207 19:52:54.481417 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7208 19:52:54.488272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7209 19:52:54.495017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7210 19:52:54.498007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7211 19:52:54.504886 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7212 19:52:54.512182 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7213 19:52:54.514989 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7214 19:52:54.521626 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7215 19:52:54.525036 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7216 19:52:54.527666 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7217 19:52:54.531111 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7218 19:52:54.537652 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7219 19:52:54.540808 ===================================
7220 19:52:54.541361 LPDDR4 DRAM CONFIGURATION
7221 19:52:54.544529 ===================================
7222 19:52:54.547437 EX_ROW_EN[0] = 0x0
7223 19:52:54.551672 EX_ROW_EN[1] = 0x0
7224 19:52:54.552264 LP4Y_EN = 0x0
7225 19:52:54.554037 WORK_FSP = 0x1
7226 19:52:54.554590 WL = 0x5
7227 19:52:54.557550 RL = 0x5
7228 19:52:54.558099 BL = 0x2
7229 19:52:54.560717 RPST = 0x0
7230 19:52:54.561169 RD_PRE = 0x0
7231 19:52:54.564137 WR_PRE = 0x1
7232 19:52:54.564587 WR_PST = 0x1
7233 19:52:54.567716 DBI_WR = 0x0
7234 19:52:54.568323 DBI_RD = 0x0
7235 19:52:54.570842 OTF = 0x1
7236 19:52:54.574391 ===================================
7237 19:52:54.577429 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7238 19:52:54.580289 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7239 19:52:54.586749 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7240 19:52:54.590353 ===================================
7241 19:52:54.590905 LPDDR4 DRAM CONFIGURATION
7242 19:52:54.593640 ===================================
7243 19:52:54.597416 EX_ROW_EN[0] = 0x10
7244 19:52:54.600126 EX_ROW_EN[1] = 0x0
7245 19:52:54.600577 LP4Y_EN = 0x0
7246 19:52:54.603785 WORK_FSP = 0x1
7247 19:52:54.604245 WL = 0x5
7248 19:52:54.606868 RL = 0x5
7249 19:52:54.607422 BL = 0x2
7250 19:52:54.610323 RPST = 0x0
7251 19:52:54.610774 RD_PRE = 0x0
7252 19:52:54.614086 WR_PRE = 0x1
7253 19:52:54.614637 WR_PST = 0x1
7254 19:52:54.616799 DBI_WR = 0x0
7255 19:52:54.617353 DBI_RD = 0x0
7256 19:52:54.620263 OTF = 0x1
7257 19:52:54.623460 ===================================
7258 19:52:54.630215 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7259 19:52:54.630669 ==
7260 19:52:54.633723 Dram Type= 6, Freq= 0, CH_0, rank 0
7261 19:52:54.636641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7262 19:52:54.637099 ==
7263 19:52:54.639959 [Duty_Offset_Calibration]
7264 19:52:54.640459 B0:1 B1:-1 CA:0
7265 19:52:54.640826
7266 19:52:54.643445 [DutyScan_Calibration_Flow] k_type=0
7267 19:52:54.654447
7268 19:52:54.654991 ==CLK 0==
7269 19:52:54.658322 Final CLK duty delay cell = 0
7270 19:52:54.661198 [0] MAX Duty = 5125%(X100), DQS PI = 20
7271 19:52:54.663954 [0] MIN Duty = 4907%(X100), DQS PI = 6
7272 19:52:54.667373 [0] AVG Duty = 5016%(X100)
7273 19:52:54.667979
7274 19:52:54.670898 CH0 CLK Duty spec in!! Max-Min= 218%
7275 19:52:54.674402 [DutyScan_Calibration_Flow] ====Done====
7276 19:52:54.675075
7277 19:52:54.677637 [DutyScan_Calibration_Flow] k_type=1
7278 19:52:54.693409
7279 19:52:54.693961 ==DQS 0 ==
7280 19:52:54.696470 Final DQS duty delay cell = -4
7281 19:52:54.699625 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7282 19:52:54.702902 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7283 19:52:54.706660 [-4] AVG Duty = 4922%(X100)
7284 19:52:54.707213
7285 19:52:54.707572 ==DQS 1 ==
7286 19:52:54.710075 Final DQS duty delay cell = 0
7287 19:52:54.713131 [0] MAX Duty = 5156%(X100), DQS PI = 0
7288 19:52:54.716354 [0] MIN Duty = 5031%(X100), DQS PI = 18
7289 19:52:54.719524 [0] AVG Duty = 5093%(X100)
7290 19:52:54.720049
7291 19:52:54.723047 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7292 19:52:54.723498
7293 19:52:54.726197 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7294 19:52:54.729579 [DutyScan_Calibration_Flow] ====Done====
7295 19:52:54.730029
7296 19:52:54.732672 [DutyScan_Calibration_Flow] k_type=3
7297 19:52:54.750834
7298 19:52:54.751375 ==DQM 0 ==
7299 19:52:54.754992 Final DQM duty delay cell = 0
7300 19:52:54.757640 [0] MAX Duty = 5124%(X100), DQS PI = 22
7301 19:52:54.760928 [0] MIN Duty = 4907%(X100), DQS PI = 10
7302 19:52:54.763830 [0] AVG Duty = 5015%(X100)
7303 19:52:54.764238
7304 19:52:54.764561 ==DQM 1 ==
7305 19:52:54.767508 Final DQM duty delay cell = 0
7306 19:52:54.770838 [0] MAX Duty = 5000%(X100), DQS PI = 4
7307 19:52:54.773816 [0] MIN Duty = 4813%(X100), DQS PI = 20
7308 19:52:54.777204 [0] AVG Duty = 4906%(X100)
7309 19:52:54.777704
7310 19:52:54.780249 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7311 19:52:54.780657
7312 19:52:54.783551 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7313 19:52:54.786635 [DutyScan_Calibration_Flow] ====Done====
7314 19:52:54.787039
7315 19:52:54.790440 [DutyScan_Calibration_Flow] k_type=2
7316 19:52:54.806880
7317 19:52:54.807420 ==DQ 0 ==
7318 19:52:54.809562 Final DQ duty delay cell = -4
7319 19:52:54.812920 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7320 19:52:54.816396 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7321 19:52:54.819845 [-4] AVG Duty = 4953%(X100)
7322 19:52:54.820390
7323 19:52:54.820749 ==DQ 1 ==
7324 19:52:54.823008 Final DQ duty delay cell = -4
7325 19:52:54.826419 [-4] MAX Duty = 4969%(X100), DQS PI = 50
7326 19:52:54.829252 [-4] MIN Duty = 4875%(X100), DQS PI = 10
7327 19:52:54.832474 [-4] AVG Duty = 4922%(X100)
7328 19:52:54.832925
7329 19:52:54.836345 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7330 19:52:54.836792
7331 19:52:54.839355 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7332 19:52:54.842600 [DutyScan_Calibration_Flow] ====Done====
7333 19:52:54.843153 ==
7334 19:52:54.846017 Dram Type= 6, Freq= 0, CH_1, rank 0
7335 19:52:54.848927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7336 19:52:54.849383 ==
7337 19:52:54.852350 [Duty_Offset_Calibration]
7338 19:52:54.856014 B0:-1 B1:1 CA:1
7339 19:52:54.856550
7340 19:52:54.859015 [DutyScan_Calibration_Flow] k_type=0
7341 19:52:54.867598
7342 19:52:54.868222 ==CLK 0==
7343 19:52:54.870774 Final CLK duty delay cell = 0
7344 19:52:54.874320 [0] MAX Duty = 5187%(X100), DQS PI = 24
7345 19:52:54.878586 [0] MIN Duty = 5000%(X100), DQS PI = 0
7346 19:52:54.879131 [0] AVG Duty = 5093%(X100)
7347 19:52:54.880352
7348 19:52:54.884379 CH1 CLK Duty spec in!! Max-Min= 187%
7349 19:52:54.887458 [DutyScan_Calibration_Flow] ====Done====
7350 19:52:54.887913
7351 19:52:54.890812 [DutyScan_Calibration_Flow] k_type=1
7352 19:52:54.907330
7353 19:52:54.907918 ==DQS 0 ==
7354 19:52:54.910862 Final DQS duty delay cell = 0
7355 19:52:54.913802 [0] MAX Duty = 5124%(X100), DQS PI = 18
7356 19:52:54.916694 [0] MIN Duty = 4907%(X100), DQS PI = 10
7357 19:52:54.920316 [0] AVG Duty = 5015%(X100)
7358 19:52:54.920859
7359 19:52:54.921218 ==DQS 1 ==
7360 19:52:54.923591 Final DQS duty delay cell = 0
7361 19:52:54.927194 [0] MAX Duty = 5093%(X100), DQS PI = 24
7362 19:52:54.929748 [0] MIN Duty = 4969%(X100), DQS PI = 56
7363 19:52:54.933766 [0] AVG Duty = 5031%(X100)
7364 19:52:54.934314
7365 19:52:54.936795 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7366 19:52:54.937380
7367 19:52:54.939781 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7368 19:52:54.943333 [DutyScan_Calibration_Flow] ====Done====
7369 19:52:54.943935
7370 19:52:54.946634 [DutyScan_Calibration_Flow] k_type=3
7371 19:52:54.964107
7372 19:52:54.964651 ==DQM 0 ==
7373 19:52:54.967364 Final DQM duty delay cell = 0
7374 19:52:54.970354 [0] MAX Duty = 5218%(X100), DQS PI = 18
7375 19:52:54.973745 [0] MIN Duty = 5031%(X100), DQS PI = 8
7376 19:52:54.974195 [0] AVG Duty = 5124%(X100)
7377 19:52:54.977322
7378 19:52:54.977867 ==DQM 1 ==
7379 19:52:54.980385 Final DQM duty delay cell = 0
7380 19:52:54.984117 [0] MAX Duty = 5156%(X100), DQS PI = 2
7381 19:52:54.987178 [0] MIN Duty = 4969%(X100), DQS PI = 34
7382 19:52:54.991165 [0] AVG Duty = 5062%(X100)
7383 19:52:54.991817
7384 19:52:54.993231 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7385 19:52:54.993682
7386 19:52:54.996682 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7387 19:52:55.000094 [DutyScan_Calibration_Flow] ====Done====
7388 19:52:55.000543
7389 19:52:55.003556 [DutyScan_Calibration_Flow] k_type=2
7390 19:52:55.020694
7391 19:52:55.021238 ==DQ 0 ==
7392 19:52:55.024219 Final DQ duty delay cell = 0
7393 19:52:55.027134 [0] MAX Duty = 5156%(X100), DQS PI = 30
7394 19:52:55.030526 [0] MIN Duty = 4906%(X100), DQS PI = 8
7395 19:52:55.030980 [0] AVG Duty = 5031%(X100)
7396 19:52:55.033899
7397 19:52:55.034444 ==DQ 1 ==
7398 19:52:55.036980 Final DQ duty delay cell = 0
7399 19:52:55.040269 [0] MAX Duty = 5156%(X100), DQS PI = 8
7400 19:52:55.043934 [0] MIN Duty = 4969%(X100), DQS PI = 54
7401 19:52:55.044485 [0] AVG Duty = 5062%(X100)
7402 19:52:55.047221
7403 19:52:55.050131 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7404 19:52:55.050671
7405 19:52:55.053975 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7406 19:52:55.057184 [DutyScan_Calibration_Flow] ====Done====
7407 19:52:55.060377 nWR fixed to 30
7408 19:52:55.060928 [ModeRegInit_LP4] CH0 RK0
7409 19:52:55.063498 [ModeRegInit_LP4] CH0 RK1
7410 19:52:55.067159 [ModeRegInit_LP4] CH1 RK0
7411 19:52:55.069908 [ModeRegInit_LP4] CH1 RK1
7412 19:52:55.070356 match AC timing 5
7413 19:52:55.076632 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7414 19:52:55.080528 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7415 19:52:55.083714 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7416 19:52:55.089689 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7417 19:52:55.092858 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7418 19:52:55.093340 [MiockJmeterHQA]
7419 19:52:55.093707
7420 19:52:55.096195 [DramcMiockJmeter] u1RxGatingPI = 0
7421 19:52:55.099567 0 : 4253, 4026
7422 19:52:55.100069 4 : 4252, 4026
7423 19:52:55.103412 8 : 4363, 4138
7424 19:52:55.104172 12 : 4252, 4026
7425 19:52:55.106582 16 : 4363, 4137
7426 19:52:55.107137 20 : 4252, 4027
7427 19:52:55.107507 24 : 4252, 4027
7428 19:52:55.109728 28 : 4253, 4027
7429 19:52:55.110349 32 : 4255, 4029
7430 19:52:55.113359 36 : 4252, 4027
7431 19:52:55.113911 40 : 4363, 4140
7432 19:52:55.116064 44 : 4363, 4137
7433 19:52:55.116520 48 : 4250, 4027
7434 19:52:55.120187 52 : 4252, 4027
7435 19:52:55.120744 56 : 4252, 4027
7436 19:52:55.121117 60 : 4250, 4027
7437 19:52:55.122561 64 : 4253, 4029
7438 19:52:55.123016 68 : 4360, 4138
7439 19:52:55.126188 72 : 4250, 4027
7440 19:52:55.126735 76 : 4250, 4027
7441 19:52:55.129487 80 : 4250, 4027
7442 19:52:55.129941 84 : 4253, 4029
7443 19:52:55.132513 88 : 4250, 4024
7444 19:52:55.133063 92 : 4361, 271
7445 19:52:55.133433 96 : 4250, 0
7446 19:52:55.136169 100 : 4250, 0
7447 19:52:55.136631 104 : 4360, 0
7448 19:52:55.139191 108 : 4249, 0
7449 19:52:55.139603 112 : 4250, 0
7450 19:52:55.139988 116 : 4250, 0
7451 19:52:55.142479 120 : 4250, 0
7452 19:52:55.143034 124 : 4250, 0
7453 19:52:55.143401 128 : 4253, 0
7454 19:52:55.145971 132 : 4250, 0
7455 19:52:55.146389 136 : 4250, 0
7456 19:52:55.149197 140 : 4252, 0
7457 19:52:55.149656 144 : 4360, 0
7458 19:52:55.150023 148 : 4360, 0
7459 19:52:55.152280 152 : 4363, 0
7460 19:52:55.152691 156 : 4361, 0
7461 19:52:55.156660 160 : 4361, 0
7462 19:52:55.157227 164 : 4250, 0
7463 19:52:55.157567 168 : 4250, 0
7464 19:52:55.158835 172 : 4250, 0
7465 19:52:55.159250 176 : 4250, 0
7466 19:52:55.162305 180 : 4253, 0
7467 19:52:55.162726 184 : 4250, 0
7468 19:52:55.163059 188 : 4250, 0
7469 19:52:55.165658 192 : 4253, 0
7470 19:52:55.166071 196 : 4361, 0
7471 19:52:55.169089 200 : 4360, 0
7472 19:52:55.169504 204 : 4363, 0
7473 19:52:55.169841 208 : 4250, 0
7474 19:52:55.172290 212 : 4249, 0
7475 19:52:55.172708 216 : 4250, 0
7476 19:52:55.173046 220 : 4250, 0
7477 19:52:55.175115 224 : 4250, 295
7478 19:52:55.175531 228 : 4253, 3548
7479 19:52:55.179131 232 : 4361, 4137
7480 19:52:55.179647 236 : 4360, 4138
7481 19:52:55.181671 240 : 4250, 4027
7482 19:52:55.182104 244 : 4250, 4026
7483 19:52:55.185014 248 : 4363, 4140
7484 19:52:55.185430 252 : 4250, 4027
7485 19:52:55.189107 256 : 4250, 4027
7486 19:52:55.189624 260 : 4250, 4027
7487 19:52:55.192004 264 : 4253, 4029
7488 19:52:55.192419 268 : 4250, 4027
7489 19:52:55.195078 272 : 4249, 4027
7490 19:52:55.195495 276 : 4361, 4137
7491 19:52:55.198506 280 : 4250, 4026
7492 19:52:55.199016 284 : 4250, 4027
7493 19:52:55.199353 288 : 4360, 4138
7494 19:52:55.202227 292 : 4252, 4027
7495 19:52:55.202748 296 : 4250, 4026
7496 19:52:55.205077 300 : 4363, 4140
7497 19:52:55.205497 304 : 4250, 4027
7498 19:52:55.208326 308 : 4250, 4027
7499 19:52:55.208740 312 : 4250, 4027
7500 19:52:55.211526 316 : 4253, 4029
7501 19:52:55.211987 320 : 4250, 4027
7502 19:52:55.215285 324 : 4250, 4027
7503 19:52:55.215847 328 : 4362, 4137
7504 19:52:55.218605 332 : 4250, 4026
7505 19:52:55.219124 336 : 4250, 3698
7506 19:52:55.221746 340 : 4360, 1660
7507 19:52:55.222280
7508 19:52:55.222621 MIOCK jitter meter ch=0
7509 19:52:55.222931
7510 19:52:55.224938 1T = (340-92) = 248 dly cells
7511 19:52:55.231623 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7512 19:52:55.232170 ==
7513 19:52:55.235085 Dram Type= 6, Freq= 0, CH_0, rank 0
7514 19:52:55.237861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7515 19:52:55.238283 ==
7516 19:52:55.244811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7517 19:52:55.248307 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7518 19:52:55.251369 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7519 19:52:55.258163 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7520 19:52:55.268377 [CA 0] Center 43 (13~74) winsize 62
7521 19:52:55.270955 [CA 1] Center 43 (13~74) winsize 62
7522 19:52:55.274313 [CA 2] Center 39 (10~69) winsize 60
7523 19:52:55.277886 [CA 3] Center 39 (10~68) winsize 59
7524 19:52:55.281316 [CA 4] Center 37 (8~66) winsize 59
7525 19:52:55.284208 [CA 5] Center 36 (7~66) winsize 60
7526 19:52:55.284621
7527 19:52:55.287399 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7528 19:52:55.287844
7529 19:52:55.293955 [CATrainingPosCal] consider 1 rank data
7530 19:52:55.294451 u2DelayCellTimex100 = 262/100 ps
7531 19:52:55.300609 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7532 19:52:55.304320 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7533 19:52:55.307468 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7534 19:52:55.310747 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7535 19:52:55.313954 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7536 19:52:55.317232 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7537 19:52:55.317742
7538 19:52:55.320543 CA PerBit enable=1, Macro0, CA PI delay=36
7539 19:52:55.320953
7540 19:52:55.323765 [CBTSetCACLKResult] CA Dly = 36
7541 19:52:55.326952 CS Dly: 11 (0~42)
7542 19:52:55.330640 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7543 19:52:55.334053 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7544 19:52:55.334519 ==
7545 19:52:55.336889 Dram Type= 6, Freq= 0, CH_0, rank 1
7546 19:52:55.343685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 19:52:55.344422 ==
7548 19:52:55.346795 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7549 19:52:55.353408 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7550 19:52:55.356908 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7551 19:52:55.364167 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7552 19:52:55.371313 [CA 0] Center 42 (12~73) winsize 62
7553 19:52:55.374532 [CA 1] Center 43 (13~73) winsize 61
7554 19:52:55.378041 [CA 2] Center 37 (8~67) winsize 60
7555 19:52:55.381295 [CA 3] Center 37 (7~67) winsize 61
7556 19:52:55.384833 [CA 4] Center 35 (6~65) winsize 60
7557 19:52:55.388150 [CA 5] Center 35 (5~65) winsize 61
7558 19:52:55.388560
7559 19:52:55.391241 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7560 19:52:55.391650
7561 19:52:55.394910 [CATrainingPosCal] consider 2 rank data
7562 19:52:55.397815 u2DelayCellTimex100 = 262/100 ps
7563 19:52:55.401375 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7564 19:52:55.408086 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7565 19:52:55.411423 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7566 19:52:55.414535 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7567 19:52:55.418481 CA4 delay=36 (8~65),Diff = 0 PI (0 cell)
7568 19:52:55.421265 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7569 19:52:55.421918
7570 19:52:55.424453 CA PerBit enable=1, Macro0, CA PI delay=36
7571 19:52:55.424867
7572 19:52:55.428365 [CBTSetCACLKResult] CA Dly = 36
7573 19:52:55.431394 CS Dly: 11 (0~43)
7574 19:52:55.434703 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7575 19:52:55.437595 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7576 19:52:55.438007
7577 19:52:55.440772 ----->DramcWriteLeveling(PI) begin...
7578 19:52:55.441190 ==
7579 19:52:55.444163 Dram Type= 6, Freq= 0, CH_0, rank 0
7580 19:52:55.451259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 19:52:55.451831 ==
7582 19:52:55.454112 Write leveling (Byte 0): 37 => 37
7583 19:52:55.457970 Write leveling (Byte 1): 26 => 26
7584 19:52:55.458380 DramcWriteLeveling(PI) end<-----
7585 19:52:55.458711
7586 19:52:55.460944 ==
7587 19:52:55.464471 Dram Type= 6, Freq= 0, CH_0, rank 0
7588 19:52:55.467578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 19:52:55.468021 ==
7590 19:52:55.470615 [Gating] SW mode calibration
7591 19:52:55.478410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7592 19:52:55.480529 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7593 19:52:55.487961 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 19:52:55.490506 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 19:52:55.493879 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 19:52:55.500450 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7597 19:52:55.503990 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7598 19:52:55.506870 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
7599 19:52:55.513655 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 19:52:55.517090 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 19:52:55.520548 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 19:52:55.526871 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 19:52:55.530178 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7604 19:52:55.533442 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7605 19:52:55.540340 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7606 19:52:55.543821 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7607 19:52:55.546495 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7608 19:52:55.553564 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 19:52:55.556283 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 19:52:55.559873 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 19:52:55.566501 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 19:52:55.569919 1 6 12 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
7613 19:52:55.572887 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7614 19:52:55.579546 1 6 20 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
7615 19:52:55.582509 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 19:52:55.586586 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 19:52:55.592747 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 19:52:55.595999 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 19:52:55.599078 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 19:52:55.606327 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7621 19:52:55.609208 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7622 19:52:55.612419 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7623 19:52:55.619160 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7624 19:52:55.622562 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 19:52:55.625711 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 19:52:55.632518 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 19:52:55.635519 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 19:52:55.638854 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 19:52:55.645145 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 19:52:55.648499 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 19:52:55.652309 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 19:52:55.658711 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 19:52:55.661942 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 19:52:55.665046 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 19:52:55.671887 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7636 19:52:55.675152 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7637 19:52:55.678723 Total UI for P1: 0, mck2ui 16
7638 19:52:55.682297 best dqsien dly found for B0: ( 1, 9, 8)
7639 19:52:55.685232 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7640 19:52:55.691685 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7641 19:52:55.694973 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7642 19:52:55.699148 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 19:52:55.701559 Total UI for P1: 0, mck2ui 16
7644 19:52:55.704904 best dqsien dly found for B1: ( 1, 9, 20)
7645 19:52:55.708421 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7646 19:52:55.712101 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7647 19:52:55.715183
7648 19:52:55.717967 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7649 19:52:55.721843 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7650 19:52:55.724815 [Gating] SW calibration Done
7651 19:52:55.725366 ==
7652 19:52:55.727888 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 19:52:55.731476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 19:52:55.732078 ==
7655 19:52:55.732452 RX Vref Scan: 0
7656 19:52:55.734339
7657 19:52:55.734889 RX Vref 0 -> 0, step: 1
7658 19:52:55.735255
7659 19:52:55.737701 RX Delay 0 -> 252, step: 8
7660 19:52:55.741048 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7661 19:52:55.744879 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7662 19:52:55.750890 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7663 19:52:55.754205 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7664 19:52:55.757704 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7665 19:52:55.760948 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7666 19:52:55.764278 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7667 19:52:55.770989 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7668 19:52:55.774241 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7669 19:52:55.777752 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7670 19:52:55.780646 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7671 19:52:55.784124 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7672 19:52:55.790379 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7673 19:52:55.794799 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7674 19:52:55.797030 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7675 19:52:55.800633 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7676 19:52:55.801088 ==
7677 19:52:55.804215 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 19:52:55.810455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 19:52:55.811019 ==
7680 19:52:55.811393 DQS Delay:
7681 19:52:55.813731 DQS0 = 0, DQS1 = 0
7682 19:52:55.814190 DQM Delay:
7683 19:52:55.817601 DQM0 = 137, DQM1 = 126
7684 19:52:55.818158 DQ Delay:
7685 19:52:55.820122 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7686 19:52:55.823632 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7687 19:52:55.827490 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7688 19:52:55.830383 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7689 19:52:55.830946
7690 19:52:55.831313
7691 19:52:55.831653 ==
7692 19:52:55.834247 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 19:52:55.839941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 19:52:55.840509 ==
7695 19:52:55.840885
7696 19:52:55.841228
7697 19:52:55.841580 TX Vref Scan disable
7698 19:52:55.843781 == TX Byte 0 ==
7699 19:52:55.847011 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7700 19:52:55.854066 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7701 19:52:55.854653 == TX Byte 1 ==
7702 19:52:55.856875 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7703 19:52:55.863556 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7704 19:52:55.864147 ==
7705 19:52:55.866891 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 19:52:55.870367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 19:52:55.870918 ==
7708 19:52:55.883565
7709 19:52:55.886839 TX Vref early break, caculate TX vref
7710 19:52:55.890411 TX Vref=16, minBit 8, minWin=21, winSum=360
7711 19:52:55.893624 TX Vref=18, minBit 9, minWin=22, winSum=372
7712 19:52:55.896419 TX Vref=20, minBit 9, minWin=22, winSum=381
7713 19:52:55.900455 TX Vref=22, minBit 8, minWin=23, winSum=394
7714 19:52:55.903495 TX Vref=24, minBit 7, minWin=24, winSum=400
7715 19:52:55.910016 TX Vref=26, minBit 2, minWin=25, winSum=408
7716 19:52:55.913142 TX Vref=28, minBit 10, minWin=24, winSum=411
7717 19:52:55.916543 TX Vref=30, minBit 8, minWin=23, winSum=403
7718 19:52:55.919708 TX Vref=32, minBit 0, minWin=24, winSum=397
7719 19:52:55.923355 TX Vref=34, minBit 4, minWin=22, winSum=386
7720 19:52:55.929646 [TxChooseVref] Worse bit 2, Min win 25, Win sum 408, Final Vref 26
7721 19:52:55.930203
7722 19:52:55.933082 Final TX Range 0 Vref 26
7723 19:52:55.933637
7724 19:52:55.933998 ==
7725 19:52:55.936544 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 19:52:55.939554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 19:52:55.940057 ==
7728 19:52:55.940424
7729 19:52:55.940758
7730 19:52:55.942716 TX Vref Scan disable
7731 19:52:55.949613 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7732 19:52:55.950160 == TX Byte 0 ==
7733 19:52:55.952641 u2DelayCellOfst[0]=14 cells (4 PI)
7734 19:52:55.956159 u2DelayCellOfst[1]=18 cells (5 PI)
7735 19:52:55.959615 u2DelayCellOfst[2]=14 cells (4 PI)
7736 19:52:55.962894 u2DelayCellOfst[3]=14 cells (4 PI)
7737 19:52:55.965933 u2DelayCellOfst[4]=14 cells (4 PI)
7738 19:52:55.969359 u2DelayCellOfst[5]=0 cells (0 PI)
7739 19:52:55.972450 u2DelayCellOfst[6]=22 cells (6 PI)
7740 19:52:55.976185 u2DelayCellOfst[7]=18 cells (5 PI)
7741 19:52:55.979231 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7742 19:52:55.982186 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7743 19:52:55.985517 == TX Byte 1 ==
7744 19:52:55.988930 u2DelayCellOfst[8]=0 cells (0 PI)
7745 19:52:55.992300 u2DelayCellOfst[9]=0 cells (0 PI)
7746 19:52:55.995717 u2DelayCellOfst[10]=7 cells (2 PI)
7747 19:52:55.998892 u2DelayCellOfst[11]=3 cells (1 PI)
7748 19:52:55.999348 u2DelayCellOfst[12]=11 cells (3 PI)
7749 19:52:56.002009 u2DelayCellOfst[13]=11 cells (3 PI)
7750 19:52:56.005456 u2DelayCellOfst[14]=14 cells (4 PI)
7751 19:52:56.008590 u2DelayCellOfst[15]=11 cells (3 PI)
7752 19:52:56.016152 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7753 19:52:56.019401 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7754 19:52:56.019945 DramC Write-DBI on
7755 19:52:56.022191 ==
7756 19:52:56.022700 Dram Type= 6, Freq= 0, CH_0, rank 0
7757 19:52:56.029285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7758 19:52:56.029797 ==
7759 19:52:56.030130
7760 19:52:56.030437
7761 19:52:56.032390 TX Vref Scan disable
7762 19:52:56.032805 == TX Byte 0 ==
7763 19:52:56.038671 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7764 19:52:56.039320 == TX Byte 1 ==
7765 19:52:56.042044 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7766 19:52:56.045284 DramC Write-DBI off
7767 19:52:56.045794
7768 19:52:56.046129 [DATLAT]
7769 19:52:56.048895 Freq=1600, CH0 RK0
7770 19:52:56.049406
7771 19:52:56.049743 DATLAT Default: 0xf
7772 19:52:56.051565 0, 0xFFFF, sum = 0
7773 19:52:56.052016 1, 0xFFFF, sum = 0
7774 19:52:56.055083 2, 0xFFFF, sum = 0
7775 19:52:56.055602 3, 0xFFFF, sum = 0
7776 19:52:56.058738 4, 0xFFFF, sum = 0
7777 19:52:56.059255 5, 0xFFFF, sum = 0
7778 19:52:56.061755 6, 0xFFFF, sum = 0
7779 19:52:56.064676 7, 0xFFFF, sum = 0
7780 19:52:56.065093 8, 0xFFFF, sum = 0
7781 19:52:56.068886 9, 0xFFFF, sum = 0
7782 19:52:56.069437 10, 0xFFFF, sum = 0
7783 19:52:56.071375 11, 0xFFFF, sum = 0
7784 19:52:56.071819 12, 0xFFFF, sum = 0
7785 19:52:56.074803 13, 0xFFFF, sum = 0
7786 19:52:56.075222 14, 0x0, sum = 1
7787 19:52:56.078432 15, 0x0, sum = 2
7788 19:52:56.078944 16, 0x0, sum = 3
7789 19:52:56.081611 17, 0x0, sum = 4
7790 19:52:56.082124 best_step = 15
7791 19:52:56.082458
7792 19:52:56.082759 ==
7793 19:52:56.084612 Dram Type= 6, Freq= 0, CH_0, rank 0
7794 19:52:56.088025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7795 19:52:56.091204 ==
7796 19:52:56.091614 RX Vref Scan: 1
7797 19:52:56.091993
7798 19:52:56.094937 Set Vref Range= 24 -> 127
7799 19:52:56.095346
7800 19:52:56.097564 RX Vref 24 -> 127, step: 1
7801 19:52:56.097974
7802 19:52:56.098302 RX Delay 19 -> 252, step: 4
7803 19:52:56.098612
7804 19:52:56.101289 Set Vref, RX VrefLevel [Byte0]: 24
7805 19:52:56.104442 [Byte1]: 24
7806 19:52:56.108725
7807 19:52:56.109399 Set Vref, RX VrefLevel [Byte0]: 25
7808 19:52:56.111818 [Byte1]: 25
7809 19:52:56.116174
7810 19:52:56.116682 Set Vref, RX VrefLevel [Byte0]: 26
7811 19:52:56.119557 [Byte1]: 26
7812 19:52:56.123806
7813 19:52:56.124321 Set Vref, RX VrefLevel [Byte0]: 27
7814 19:52:56.126679 [Byte1]: 27
7815 19:52:56.131400
7816 19:52:56.131947 Set Vref, RX VrefLevel [Byte0]: 28
7817 19:52:56.135017 [Byte1]: 28
7818 19:52:56.138955
7819 19:52:56.139494 Set Vref, RX VrefLevel [Byte0]: 29
7820 19:52:56.141729 [Byte1]: 29
7821 19:52:56.146316
7822 19:52:56.146823 Set Vref, RX VrefLevel [Byte0]: 30
7823 19:52:56.149875 [Byte1]: 30
7824 19:52:56.153991
7825 19:52:56.154521 Set Vref, RX VrefLevel [Byte0]: 31
7826 19:52:56.156914 [Byte1]: 31
7827 19:52:56.161396
7828 19:52:56.161901 Set Vref, RX VrefLevel [Byte0]: 32
7829 19:52:56.164702 [Byte1]: 32
7830 19:52:56.169388
7831 19:52:56.169929 Set Vref, RX VrefLevel [Byte0]: 33
7832 19:52:56.172327 [Byte1]: 33
7833 19:52:56.176569
7834 19:52:56.177080 Set Vref, RX VrefLevel [Byte0]: 34
7835 19:52:56.180252 [Byte1]: 34
7836 19:52:56.184179
7837 19:52:56.184568 Set Vref, RX VrefLevel [Byte0]: 35
7838 19:52:56.188060 [Byte1]: 35
7839 19:52:56.192450
7840 19:52:56.192988 Set Vref, RX VrefLevel [Byte0]: 36
7841 19:52:56.194782 [Byte1]: 36
7842 19:52:56.198868
7843 19:52:56.199276 Set Vref, RX VrefLevel [Byte0]: 37
7844 19:52:56.203018 [Byte1]: 37
7845 19:52:56.206955
7846 19:52:56.207368 Set Vref, RX VrefLevel [Byte0]: 38
7847 19:52:56.210402 [Byte1]: 38
7848 19:52:56.214539
7849 19:52:56.215064 Set Vref, RX VrefLevel [Byte0]: 39
7850 19:52:56.217638 [Byte1]: 39
7851 19:52:56.222258
7852 19:52:56.222800 Set Vref, RX VrefLevel [Byte0]: 40
7853 19:52:56.225308 [Byte1]: 40
7854 19:52:56.229227
7855 19:52:56.229690 Set Vref, RX VrefLevel [Byte0]: 41
7856 19:52:56.233023 [Byte1]: 41
7857 19:52:56.237493
7858 19:52:56.238041 Set Vref, RX VrefLevel [Byte0]: 42
7859 19:52:56.240691 [Byte1]: 42
7860 19:52:56.244620
7861 19:52:56.245175 Set Vref, RX VrefLevel [Byte0]: 43
7862 19:52:56.251408 [Byte1]: 43
7863 19:52:56.251996
7864 19:52:56.254802 Set Vref, RX VrefLevel [Byte0]: 44
7865 19:52:56.257595 [Byte1]: 44
7866 19:52:56.258149
7867 19:52:56.262113 Set Vref, RX VrefLevel [Byte0]: 45
7868 19:52:56.264484 [Byte1]: 45
7869 19:52:56.265095
7870 19:52:56.267665 Set Vref, RX VrefLevel [Byte0]: 46
7871 19:52:56.270895 [Byte1]: 46
7872 19:52:56.275195
7873 19:52:56.275651 Set Vref, RX VrefLevel [Byte0]: 47
7874 19:52:56.278517 [Byte1]: 47
7875 19:52:56.282630
7876 19:52:56.283225 Set Vref, RX VrefLevel [Byte0]: 48
7877 19:52:56.285841 [Byte1]: 48
7878 19:52:56.290324
7879 19:52:56.290866 Set Vref, RX VrefLevel [Byte0]: 49
7880 19:52:56.293366 [Byte1]: 49
7881 19:52:56.297666
7882 19:52:56.298117 Set Vref, RX VrefLevel [Byte0]: 50
7883 19:52:56.300852 [Byte1]: 50
7884 19:52:56.306194
7885 19:52:56.306745 Set Vref, RX VrefLevel [Byte0]: 51
7886 19:52:56.308738 [Byte1]: 51
7887 19:52:56.312965
7888 19:52:56.313516 Set Vref, RX VrefLevel [Byte0]: 52
7889 19:52:56.316150 [Byte1]: 52
7890 19:52:56.321151
7891 19:52:56.321696 Set Vref, RX VrefLevel [Byte0]: 53
7892 19:52:56.324170 [Byte1]: 53
7893 19:52:56.328348
7894 19:52:56.328884 Set Vref, RX VrefLevel [Byte0]: 54
7895 19:52:56.331651 [Byte1]: 54
7896 19:52:56.335587
7897 19:52:56.336094 Set Vref, RX VrefLevel [Byte0]: 55
7898 19:52:56.339176 [Byte1]: 55
7899 19:52:56.343268
7900 19:52:56.343855 Set Vref, RX VrefLevel [Byte0]: 56
7901 19:52:56.346147 [Byte1]: 56
7902 19:52:56.350853
7903 19:52:56.351315 Set Vref, RX VrefLevel [Byte0]: 57
7904 19:52:56.353836 [Byte1]: 57
7905 19:52:56.358791
7906 19:52:56.359210 Set Vref, RX VrefLevel [Byte0]: 58
7907 19:52:56.361970 [Byte1]: 58
7908 19:52:56.365418
7909 19:52:56.365835 Set Vref, RX VrefLevel [Byte0]: 59
7910 19:52:56.368951 [Byte1]: 59
7911 19:52:56.373731
7912 19:52:56.374149 Set Vref, RX VrefLevel [Byte0]: 60
7913 19:52:56.376392 [Byte1]: 60
7914 19:52:56.381161
7915 19:52:56.381671 Set Vref, RX VrefLevel [Byte0]: 61
7916 19:52:56.383890 [Byte1]: 61
7917 19:52:56.388644
7918 19:52:56.389061 Set Vref, RX VrefLevel [Byte0]: 62
7919 19:52:56.391878 [Byte1]: 62
7920 19:52:56.396053
7921 19:52:56.396469 Set Vref, RX VrefLevel [Byte0]: 63
7922 19:52:56.399271 [Byte1]: 63
7923 19:52:56.403618
7924 19:52:56.404071 Set Vref, RX VrefLevel [Byte0]: 64
7925 19:52:56.406706 [Byte1]: 64
7926 19:52:56.411601
7927 19:52:56.412068 Set Vref, RX VrefLevel [Byte0]: 65
7928 19:52:56.414421 [Byte1]: 65
7929 19:52:56.418790
7930 19:52:56.419208 Set Vref, RX VrefLevel [Byte0]: 66
7931 19:52:56.422286 [Byte1]: 66
7932 19:52:56.426545
7933 19:52:56.426966 Set Vref, RX VrefLevel [Byte0]: 67
7934 19:52:56.429644 [Byte1]: 67
7935 19:52:56.433770
7936 19:52:56.434189 Set Vref, RX VrefLevel [Byte0]: 68
7937 19:52:56.437302 [Byte1]: 68
7938 19:52:56.441662
7939 19:52:56.442075 Set Vref, RX VrefLevel [Byte0]: 69
7940 19:52:56.444766 [Byte1]: 69
7941 19:52:56.448897
7942 19:52:56.449306 Set Vref, RX VrefLevel [Byte0]: 70
7943 19:52:56.452437 [Byte1]: 70
7944 19:52:56.456472
7945 19:52:56.456885 Set Vref, RX VrefLevel [Byte0]: 71
7946 19:52:56.459824 [Byte1]: 71
7947 19:52:56.463890
7948 19:52:56.464461 Set Vref, RX VrefLevel [Byte0]: 72
7949 19:52:56.467562 [Byte1]: 72
7950 19:52:56.471349
7951 19:52:56.471817 Set Vref, RX VrefLevel [Byte0]: 73
7952 19:52:56.474909 [Byte1]: 73
7953 19:52:56.478964
7954 19:52:56.479404 Set Vref, RX VrefLevel [Byte0]: 74
7955 19:52:56.482371 [Byte1]: 74
7956 19:52:56.486859
7957 19:52:56.487278 Set Vref, RX VrefLevel [Byte0]: 75
7958 19:52:56.490197 [Byte1]: 75
7959 19:52:56.494490
7960 19:52:56.494904 Set Vref, RX VrefLevel [Byte0]: 76
7961 19:52:56.497592 [Byte1]: 76
7962 19:52:56.501897
7963 19:52:56.502312 Set Vref, RX VrefLevel [Byte0]: 77
7964 19:52:56.505390 [Byte1]: 77
7965 19:52:56.509461
7966 19:52:56.509896 Set Vref, RX VrefLevel [Byte0]: 78
7967 19:52:56.512585 [Byte1]: 78
7968 19:52:56.517222
7969 19:52:56.517657 Set Vref, RX VrefLevel [Byte0]: 79
7970 19:52:56.520232 [Byte1]: 79
7971 19:52:56.524623
7972 19:52:56.525032 Final RX Vref Byte 0 = 68 to rank0
7973 19:52:56.528167 Final RX Vref Byte 1 = 57 to rank0
7974 19:52:56.531201 Final RX Vref Byte 0 = 68 to rank1
7975 19:52:56.534511 Final RX Vref Byte 1 = 57 to rank1==
7976 19:52:56.537914 Dram Type= 6, Freq= 0, CH_0, rank 0
7977 19:52:56.544191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 19:52:56.544736 ==
7979 19:52:56.545078 DQS Delay:
7980 19:52:56.547481 DQS0 = 0, DQS1 = 0
7981 19:52:56.547932 DQM Delay:
7982 19:52:56.551295 DQM0 = 133, DQM1 = 122
7983 19:52:56.551935 DQ Delay:
7984 19:52:56.554264 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =132
7985 19:52:56.557509 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
7986 19:52:56.560435 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =116
7987 19:52:56.564284 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
7988 19:52:56.564901
7989 19:52:56.565383
7990 19:52:56.565926
7991 19:52:56.567226 [DramC_TX_OE_Calibration] TA2
7992 19:52:56.570846 Original DQ_B0 (3 6) =30, OEN = 27
7993 19:52:56.574227 Original DQ_B1 (3 6) =30, OEN = 27
7994 19:52:56.577366 24, 0x0, End_B0=24 End_B1=24
7995 19:52:56.580831 25, 0x0, End_B0=25 End_B1=25
7996 19:52:56.581259 26, 0x0, End_B0=26 End_B1=26
7997 19:52:56.583843 27, 0x0, End_B0=27 End_B1=27
7998 19:52:56.586864 28, 0x0, End_B0=28 End_B1=28
7999 19:52:56.590297 29, 0x0, End_B0=29 End_B1=29
8000 19:52:56.590602 30, 0x0, End_B0=30 End_B1=30
8001 19:52:56.593397 31, 0x4141, End_B0=30 End_B1=30
8002 19:52:56.596562 Byte0 end_step=30 best_step=27
8003 19:52:56.600470 Byte1 end_step=30 best_step=27
8004 19:52:56.603108 Byte0 TX OE(2T, 0.5T) = (3, 3)
8005 19:52:56.607211 Byte1 TX OE(2T, 0.5T) = (3, 3)
8006 19:52:56.607457
8007 19:52:56.607661
8008 19:52:56.612921 [DQSOSCAuto] RK0, (LSB)MR18= 0x2113, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8009 19:52:56.616175 CH0 RK0: MR19=303, MR18=2113
8010 19:52:56.623051 CH0_RK0: MR19=0x303, MR18=0x2113, DQSOSC=393, MR23=63, INC=23, DEC=15
8011 19:52:56.623157
8012 19:52:56.626024 ----->DramcWriteLeveling(PI) begin...
8013 19:52:56.626134 ==
8014 19:52:56.629512 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 19:52:56.633272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 19:52:56.633385 ==
8017 19:52:56.636077 Write leveling (Byte 0): 37 => 37
8018 19:52:56.639904 Write leveling (Byte 1): 28 => 28
8019 19:52:56.642684 DramcWriteLeveling(PI) end<-----
8020 19:52:56.642763
8021 19:52:56.642826 ==
8022 19:52:56.646389 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 19:52:56.652640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 19:52:56.652726 ==
8025 19:52:56.652796 [Gating] SW mode calibration
8026 19:52:56.662442 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8027 19:52:56.665895 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8028 19:52:56.669309 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 19:52:56.675875 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 19:52:56.679170 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 19:52:56.682505 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8032 19:52:56.689093 1 4 16 | B1->B0 | 2323 3333 | 1 1 | (0 0) (1 1)
8033 19:52:56.692743 1 4 20 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
8034 19:52:56.696022 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 19:52:56.703278 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 19:52:56.705850 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 19:52:56.709246 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 19:52:56.715515 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8039 19:52:56.719189 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8040 19:52:56.725477 1 5 16 | B1->B0 | 3434 2626 | 0 0 | (0 0) (1 0)
8041 19:52:56.728879 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
8042 19:52:56.732334 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 19:52:56.738731 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 19:52:56.742270 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 19:52:56.745557 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 19:52:56.751997 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 19:52:56.755143 1 6 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8048 19:52:56.758319 1 6 16 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
8049 19:52:56.764823 1 6 20 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
8050 19:52:56.768024 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 19:52:56.771459 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 19:52:56.778203 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 19:52:56.781498 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 19:52:56.785044 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 19:52:56.791483 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8056 19:52:56.794785 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8057 19:52:56.798136 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8058 19:52:56.804851 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 19:52:56.808261 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 19:52:56.810960 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 19:52:56.817773 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 19:52:56.821156 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 19:52:56.824886 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 19:52:56.828255 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 19:52:56.834504 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 19:52:56.837929 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 19:52:56.842008 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 19:52:56.847653 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 19:52:56.850809 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 19:52:56.857781 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8071 19:52:56.860468 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8072 19:52:56.863925 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8073 19:52:56.867471 Total UI for P1: 0, mck2ui 16
8074 19:52:56.870272 best dqsien dly found for B0: ( 1, 9, 10)
8075 19:52:56.874135 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 19:52:56.877570 Total UI for P1: 0, mck2ui 16
8077 19:52:56.880538 best dqsien dly found for B1: ( 1, 9, 14)
8078 19:52:56.886608 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8079 19:52:56.890219 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8080 19:52:56.890349
8081 19:52:56.893141 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8082 19:52:56.896671 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8083 19:52:56.900211 [Gating] SW calibration Done
8084 19:52:56.900673 ==
8085 19:52:56.903630 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 19:52:56.906811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 19:52:56.907257 ==
8088 19:52:56.910606 RX Vref Scan: 0
8089 19:52:56.911197
8090 19:52:56.911618 RX Vref 0 -> 0, step: 1
8091 19:52:56.912034
8092 19:52:56.913386 RX Delay 0 -> 252, step: 8
8093 19:52:56.917459 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8094 19:52:56.923259 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8095 19:52:56.926763 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8096 19:52:56.929769 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8097 19:52:56.932865 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8098 19:52:56.936195 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8099 19:52:56.942655 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8100 19:52:56.946381 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8101 19:52:56.949463 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8102 19:52:56.952877 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8103 19:52:56.956052 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8104 19:52:56.962475 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8105 19:52:56.965735 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8106 19:52:56.969160 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8107 19:52:56.972298 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8108 19:52:56.978982 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8109 19:52:56.979057 ==
8110 19:52:56.982066 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 19:52:56.985839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 19:52:56.985920 ==
8113 19:52:56.985985 DQS Delay:
8114 19:52:56.988557 DQS0 = 0, DQS1 = 0
8115 19:52:56.988638 DQM Delay:
8116 19:52:56.992293 DQM0 = 134, DQM1 = 129
8117 19:52:56.992373 DQ Delay:
8118 19:52:56.995478 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =127
8119 19:52:56.998680 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8120 19:52:57.001947 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8121 19:52:57.005121 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8122 19:52:57.005202
8123 19:52:57.008783
8124 19:52:57.008863 ==
8125 19:52:57.011668 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 19:52:57.015195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 19:52:57.015276 ==
8128 19:52:57.015340
8129 19:52:57.015400
8130 19:52:57.018220 TX Vref Scan disable
8131 19:52:57.018301 == TX Byte 0 ==
8132 19:52:57.025081 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8133 19:52:57.028158 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8134 19:52:57.028239 == TX Byte 1 ==
8135 19:52:57.035187 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8136 19:52:57.038101 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8137 19:52:57.038182 ==
8138 19:52:57.041748 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 19:52:57.044532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 19:52:57.044613 ==
8141 19:52:57.059213
8142 19:52:57.062719 TX Vref early break, caculate TX vref
8143 19:52:57.065794 TX Vref=16, minBit 8, minWin=22, winSum=376
8144 19:52:57.069259 TX Vref=18, minBit 0, minWin=23, winSum=380
8145 19:52:57.072298 TX Vref=20, minBit 2, minWin=23, winSum=389
8146 19:52:57.075821 TX Vref=22, minBit 0, minWin=24, winSum=393
8147 19:52:57.078831 TX Vref=24, minBit 1, minWin=24, winSum=404
8148 19:52:57.085847 TX Vref=26, minBit 4, minWin=24, winSum=413
8149 19:52:57.088916 TX Vref=28, minBit 0, minWin=25, winSum=413
8150 19:52:57.092558 TX Vref=30, minBit 0, minWin=24, winSum=406
8151 19:52:57.095563 TX Vref=32, minBit 5, minWin=23, winSum=398
8152 19:52:57.098861 TX Vref=34, minBit 1, minWin=23, winSum=389
8153 19:52:57.105799 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8154 19:52:57.105880
8155 19:52:57.108457 Final TX Range 0 Vref 28
8156 19:52:57.108539
8157 19:52:57.108604 ==
8158 19:52:57.112427 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 19:52:57.115614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 19:52:57.115696 ==
8161 19:52:57.115772
8162 19:52:57.115832
8163 19:52:57.118396 TX Vref Scan disable
8164 19:52:57.125477 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8165 19:52:57.125557 == TX Byte 0 ==
8166 19:52:57.128438 u2DelayCellOfst[0]=11 cells (3 PI)
8167 19:52:57.131804 u2DelayCellOfst[1]=14 cells (4 PI)
8168 19:52:57.135507 u2DelayCellOfst[2]=11 cells (3 PI)
8169 19:52:57.138333 u2DelayCellOfst[3]=11 cells (3 PI)
8170 19:52:57.142067 u2DelayCellOfst[4]=7 cells (2 PI)
8171 19:52:57.145496 u2DelayCellOfst[5]=0 cells (0 PI)
8172 19:52:57.148245 u2DelayCellOfst[6]=14 cells (4 PI)
8173 19:52:57.151606 u2DelayCellOfst[7]=18 cells (5 PI)
8174 19:52:57.154856 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8175 19:52:57.158175 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8176 19:52:57.163087 == TX Byte 1 ==
8177 19:52:57.164647 u2DelayCellOfst[8]=0 cells (0 PI)
8178 19:52:57.168015 u2DelayCellOfst[9]=3 cells (1 PI)
8179 19:52:57.171373 u2DelayCellOfst[10]=7 cells (2 PI)
8180 19:52:57.171500 u2DelayCellOfst[11]=3 cells (1 PI)
8181 19:52:57.174835 u2DelayCellOfst[12]=11 cells (3 PI)
8182 19:52:57.177719 u2DelayCellOfst[13]=11 cells (3 PI)
8183 19:52:57.181354 u2DelayCellOfst[14]=18 cells (5 PI)
8184 19:52:57.184730 u2DelayCellOfst[15]=11 cells (3 PI)
8185 19:52:57.191138 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8186 19:52:57.194959 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8187 19:52:57.195160 DramC Write-DBI on
8188 19:52:57.195320 ==
8189 19:52:57.198094 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 19:52:57.205163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 19:52:57.205368 ==
8192 19:52:57.205532
8193 19:52:57.205683
8194 19:52:57.207775 TX Vref Scan disable
8195 19:52:57.207979 == TX Byte 0 ==
8196 19:52:57.214573 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8197 19:52:57.214777 == TX Byte 1 ==
8198 19:52:57.217562 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8199 19:52:57.221204 DramC Write-DBI off
8200 19:52:57.221404
8201 19:52:57.221565 [DATLAT]
8202 19:52:57.224665 Freq=1600, CH0 RK1
8203 19:52:57.224866
8204 19:52:57.225026 DATLAT Default: 0xf
8205 19:52:57.227892 0, 0xFFFF, sum = 0
8206 19:52:57.228095 1, 0xFFFF, sum = 0
8207 19:52:57.231358 2, 0xFFFF, sum = 0
8208 19:52:57.231561 3, 0xFFFF, sum = 0
8209 19:52:57.234126 4, 0xFFFF, sum = 0
8210 19:52:57.234328 5, 0xFFFF, sum = 0
8211 19:52:57.237599 6, 0xFFFF, sum = 0
8212 19:52:57.237802 7, 0xFFFF, sum = 0
8213 19:52:57.240765 8, 0xFFFF, sum = 0
8214 19:52:57.244204 9, 0xFFFF, sum = 0
8215 19:52:57.244372 10, 0xFFFF, sum = 0
8216 19:52:57.247470 11, 0xFFFF, sum = 0
8217 19:52:57.247612 12, 0xFFFF, sum = 0
8218 19:52:57.251187 13, 0xFFFF, sum = 0
8219 19:52:57.251329 14, 0x0, sum = 1
8220 19:52:57.254491 15, 0x0, sum = 2
8221 19:52:57.254632 16, 0x0, sum = 3
8222 19:52:57.257592 17, 0x0, sum = 4
8223 19:52:57.257736 best_step = 15
8224 19:52:57.257848
8225 19:52:57.257954 ==
8226 19:52:57.260803 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 19:52:57.264555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 19:52:57.264776 ==
8229 19:52:57.267515 RX Vref Scan: 0
8230 19:52:57.267710
8231 19:52:57.271078 RX Vref 0 -> 0, step: 1
8232 19:52:57.271225
8233 19:52:57.271337 RX Delay 11 -> 252, step: 4
8234 19:52:57.277496 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8235 19:52:57.280962 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8236 19:52:57.284709 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8237 19:52:57.287750 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8238 19:52:57.291303 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8239 19:52:57.297946 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8240 19:52:57.301138 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8241 19:52:57.304052 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8242 19:52:57.307295 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8243 19:52:57.310770 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8244 19:52:57.317462 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8245 19:52:57.320788 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8246 19:52:57.323705 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8247 19:52:57.327585 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8248 19:52:57.333637 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8249 19:52:57.337432 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8250 19:52:57.337515 ==
8251 19:52:57.340546 Dram Type= 6, Freq= 0, CH_0, rank 1
8252 19:52:57.343358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 19:52:57.343440 ==
8254 19:52:57.347052 DQS Delay:
8255 19:52:57.347134 DQS0 = 0, DQS1 = 0
8256 19:52:57.347200 DQM Delay:
8257 19:52:57.350291 DQM0 = 130, DQM1 = 125
8258 19:52:57.350372 DQ Delay:
8259 19:52:57.353449 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =126
8260 19:52:57.356659 DQ4 =132, DQ5 =120, DQ6 =140, DQ7 =140
8261 19:52:57.363468 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8262 19:52:57.367156 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8263 19:52:57.367238
8264 19:52:57.367303
8265 19:52:57.367363
8266 19:52:57.370852 [DramC_TX_OE_Calibration] TA2
8267 19:52:57.373512 Original DQ_B0 (3 6) =30, OEN = 27
8268 19:52:57.376887 Original DQ_B1 (3 6) =30, OEN = 27
8269 19:52:57.377029 24, 0x0, End_B0=24 End_B1=24
8270 19:52:57.381515 25, 0x0, End_B0=25 End_B1=25
8271 19:52:57.383871 26, 0x0, End_B0=26 End_B1=26
8272 19:52:57.387479 27, 0x0, End_B0=27 End_B1=27
8273 19:52:57.387668 28, 0x0, End_B0=28 End_B1=28
8274 19:52:57.390059 29, 0x0, End_B0=29 End_B1=29
8275 19:52:57.393482 30, 0x0, End_B0=30 End_B1=30
8276 19:52:57.396551 31, 0x4141, End_B0=30 End_B1=30
8277 19:52:57.399975 Byte0 end_step=30 best_step=27
8278 19:52:57.403396 Byte1 end_step=30 best_step=27
8279 19:52:57.403630 Byte0 TX OE(2T, 0.5T) = (3, 3)
8280 19:52:57.407002 Byte1 TX OE(2T, 0.5T) = (3, 3)
8281 19:52:57.407265
8282 19:52:57.407421
8283 19:52:57.416774 [DQSOSCAuto] RK1, (LSB)MR18= 0x2205, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
8284 19:52:57.419847 CH0 RK1: MR19=303, MR18=2205
8285 19:52:57.422996 CH0_RK1: MR19=0x303, MR18=0x2205, DQSOSC=392, MR23=63, INC=24, DEC=16
8286 19:52:57.427228 [RxdqsGatingPostProcess] freq 1600
8287 19:52:57.433277 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8288 19:52:57.436560 best DQS0 dly(2T, 0.5T) = (1, 1)
8289 19:52:57.440107 best DQS1 dly(2T, 0.5T) = (1, 1)
8290 19:52:57.443474 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8291 19:52:57.446820 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8292 19:52:57.449965 best DQS0 dly(2T, 0.5T) = (1, 1)
8293 19:52:57.452846 best DQS1 dly(2T, 0.5T) = (1, 1)
8294 19:52:57.456160 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8295 19:52:57.459631 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8296 19:52:57.460083 Pre-setting of DQS Precalculation
8297 19:52:57.466165 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8298 19:52:57.466583 ==
8299 19:52:57.469170 Dram Type= 6, Freq= 0, CH_1, rank 0
8300 19:52:57.472414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 19:52:57.472834 ==
8302 19:52:57.479272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8303 19:52:57.482766 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8304 19:52:57.489180 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8305 19:52:57.492537 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8306 19:52:57.502978 [CA 0] Center 41 (12~71) winsize 60
8307 19:52:57.506212 [CA 1] Center 42 (13~71) winsize 59
8308 19:52:57.509388 [CA 2] Center 37 (8~66) winsize 59
8309 19:52:57.512585 [CA 3] Center 36 (7~65) winsize 59
8310 19:52:57.515413 [CA 4] Center 37 (7~67) winsize 61
8311 19:52:57.519323 [CA 5] Center 36 (7~65) winsize 59
8312 19:52:57.519778
8313 19:52:57.522217 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8314 19:52:57.522629
8315 19:52:57.526441 [CATrainingPosCal] consider 1 rank data
8316 19:52:57.528788 u2DelayCellTimex100 = 262/100 ps
8317 19:52:57.535035 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8318 19:52:57.538771 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8319 19:52:57.542612 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8320 19:52:57.545185 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8321 19:52:57.548293 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8322 19:52:57.551526 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8323 19:52:57.551991
8324 19:52:57.555119 CA PerBit enable=1, Macro0, CA PI delay=36
8325 19:52:57.555536
8326 19:52:57.558173 [CBTSetCACLKResult] CA Dly = 36
8327 19:52:57.561603 CS Dly: 9 (0~40)
8328 19:52:57.564914 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8329 19:52:57.568339 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8330 19:52:57.568754 ==
8331 19:52:57.571816 Dram Type= 6, Freq= 0, CH_1, rank 1
8332 19:52:57.578359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 19:52:57.578778 ==
8334 19:52:57.581411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8335 19:52:57.588623 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8336 19:52:57.591473 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8337 19:52:57.598360 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8338 19:52:57.605667 [CA 0] Center 42 (13~72) winsize 60
8339 19:52:57.608936 [CA 1] Center 42 (13~72) winsize 60
8340 19:52:57.612121 [CA 2] Center 38 (9~67) winsize 59
8341 19:52:57.616225 [CA 3] Center 37 (7~67) winsize 61
8342 19:52:57.619004 [CA 4] Center 37 (8~67) winsize 60
8343 19:52:57.622560 [CA 5] Center 37 (8~66) winsize 59
8344 19:52:57.623120
8345 19:52:57.625859 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8346 19:52:57.626418
8347 19:52:57.629985 [CATrainingPosCal] consider 2 rank data
8348 19:52:57.633162 u2DelayCellTimex100 = 262/100 ps
8349 19:52:57.635907 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8350 19:52:57.642282 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8351 19:52:57.645477 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8352 19:52:57.648622 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8353 19:52:57.652184 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8354 19:52:57.655361 CA5 delay=36 (8~65),Diff = 0 PI (0 cell)
8355 19:52:57.656027
8356 19:52:57.658657 CA PerBit enable=1, Macro0, CA PI delay=36
8357 19:52:57.659116
8358 19:52:57.661660 [CBTSetCACLKResult] CA Dly = 36
8359 19:52:57.665211 CS Dly: 10 (0~43)
8360 19:52:57.668360 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8361 19:52:57.671885 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8362 19:52:57.672436
8363 19:52:57.674890 ----->DramcWriteLeveling(PI) begin...
8364 19:52:57.675355 ==
8365 19:52:57.678213 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 19:52:57.685099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 19:52:57.685665 ==
8368 19:52:57.688461 Write leveling (Byte 0): 23 => 23
8369 19:52:57.688923 Write leveling (Byte 1): 26 => 26
8370 19:52:57.691650 DramcWriteLeveling(PI) end<-----
8371 19:52:57.692259
8372 19:52:57.694689 ==
8373 19:52:57.695147 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 19:52:57.701355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 19:52:57.701960 ==
8376 19:52:57.705261 [Gating] SW mode calibration
8377 19:52:57.711894 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8378 19:52:57.714966 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8379 19:52:57.721467 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 19:52:57.724709 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 19:52:57.728252 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 19:52:57.734446 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
8383 19:52:57.737907 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 19:52:57.741339 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 19:52:57.747766 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 19:52:57.751289 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 19:52:57.754062 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 19:52:57.761203 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 19:52:57.764715 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8390 19:52:57.767347 1 5 12 | B1->B0 | 3030 2c2c | 0 0 | (0 1) (0 1)
8391 19:52:57.773893 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 19:52:57.777189 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 19:52:57.780725 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 19:52:57.787639 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 19:52:57.790508 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 19:52:57.793994 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 19:52:57.800395 1 6 8 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
8398 19:52:57.803824 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8399 19:52:57.807450 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 19:52:57.813622 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 19:52:57.816926 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 19:52:57.820612 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 19:52:57.827380 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 19:52:57.830372 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 19:52:57.833757 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8406 19:52:57.840279 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8407 19:52:57.843392 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8408 19:52:57.846669 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 19:52:57.853335 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 19:52:57.857100 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 19:52:57.860306 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 19:52:57.866680 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 19:52:57.870238 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 19:52:57.872829 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 19:52:57.879337 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 19:52:57.882887 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 19:52:57.886130 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 19:52:57.892703 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 19:52:57.895704 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 19:52:57.899393 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 19:52:57.905799 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8422 19:52:57.909333 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8423 19:52:57.911961 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 19:52:57.915521 Total UI for P1: 0, mck2ui 16
8425 19:52:57.919159 best dqsien dly found for B0: ( 1, 9, 10)
8426 19:52:57.922361 Total UI for P1: 0, mck2ui 16
8427 19:52:57.925254 best dqsien dly found for B1: ( 1, 9, 12)
8428 19:52:57.929243 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8429 19:52:57.931782 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8430 19:52:57.931964
8431 19:52:57.938504 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8432 19:52:57.941692 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8433 19:52:57.945636 [Gating] SW calibration Done
8434 19:52:57.945817 ==
8435 19:52:57.948408 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 19:52:57.952599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 19:52:57.952770 ==
8438 19:52:57.952894 RX Vref Scan: 0
8439 19:52:57.953009
8440 19:52:57.955234 RX Vref 0 -> 0, step: 1
8441 19:52:57.955363
8442 19:52:57.958376 RX Delay 0 -> 252, step: 8
8443 19:52:57.961894 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8444 19:52:57.965226 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8445 19:52:57.971343 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8446 19:52:57.974816 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8447 19:52:57.978139 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8448 19:52:57.981272 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8449 19:52:57.984996 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8450 19:52:57.991363 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8451 19:52:57.994603 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8452 19:52:57.998080 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8453 19:52:58.001174 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8454 19:52:58.004362 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8455 19:52:58.010839 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8456 19:52:58.014212 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8457 19:52:58.017432 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8458 19:52:58.021816 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8459 19:52:58.021892 ==
8460 19:52:58.024366 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 19:52:58.031634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 19:52:58.031716 ==
8463 19:52:58.031822 DQS Delay:
8464 19:52:58.034084 DQS0 = 0, DQS1 = 0
8465 19:52:58.034165 DQM Delay:
8466 19:52:58.037258 DQM0 = 137, DQM1 = 128
8467 19:52:58.037347 DQ Delay:
8468 19:52:58.041091 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8469 19:52:58.044060 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8470 19:52:58.047258 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8471 19:52:58.051009 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8472 19:52:58.051120
8473 19:52:58.051186
8474 19:52:58.051246 ==
8475 19:52:58.054557 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 19:52:58.060880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 19:52:58.060963 ==
8478 19:52:58.061027
8479 19:52:58.061088
8480 19:52:58.061146 TX Vref Scan disable
8481 19:52:58.063911 == TX Byte 0 ==
8482 19:52:58.067111 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8483 19:52:58.073695 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8484 19:52:58.073780 == TX Byte 1 ==
8485 19:52:58.077257 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8486 19:52:58.083396 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8487 19:52:58.083478 ==
8488 19:52:58.086960 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 19:52:58.090233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 19:52:58.090315 ==
8491 19:52:58.102873
8492 19:52:58.106197 TX Vref early break, caculate TX vref
8493 19:52:58.109337 TX Vref=16, minBit 0, minWin=21, winSum=376
8494 19:52:58.112462 TX Vref=18, minBit 5, minWin=22, winSum=381
8495 19:52:58.116425 TX Vref=20, minBit 5, minWin=22, winSum=391
8496 19:52:58.119071 TX Vref=22, minBit 0, minWin=23, winSum=398
8497 19:52:58.122466 TX Vref=24, minBit 5, minWin=23, winSum=409
8498 19:52:58.129669 TX Vref=26, minBit 0, minWin=24, winSum=416
8499 19:52:58.132414 TX Vref=28, minBit 0, minWin=24, winSum=413
8500 19:52:58.135700 TX Vref=30, minBit 0, minWin=24, winSum=410
8501 19:52:58.139053 TX Vref=32, minBit 0, minWin=23, winSum=399
8502 19:52:58.142295 TX Vref=34, minBit 5, minWin=22, winSum=392
8503 19:52:58.148800 [TxChooseVref] Worse bit 0, Min win 24, Win sum 416, Final Vref 26
8504 19:52:58.148883
8505 19:52:58.152035 Final TX Range 0 Vref 26
8506 19:52:58.152117
8507 19:52:58.152182 ==
8508 19:52:58.155202 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 19:52:58.158518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 19:52:58.158600 ==
8511 19:52:58.158667
8512 19:52:58.158739
8513 19:52:58.161855 TX Vref Scan disable
8514 19:52:58.168279 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8515 19:52:58.168366 == TX Byte 0 ==
8516 19:52:58.171769 u2DelayCellOfst[0]=18 cells (5 PI)
8517 19:52:58.175174 u2DelayCellOfst[1]=14 cells (4 PI)
8518 19:52:58.178572 u2DelayCellOfst[2]=0 cells (0 PI)
8519 19:52:58.181487 u2DelayCellOfst[3]=7 cells (2 PI)
8520 19:52:58.185315 u2DelayCellOfst[4]=11 cells (3 PI)
8521 19:52:58.188097 u2DelayCellOfst[5]=22 cells (6 PI)
8522 19:52:58.191515 u2DelayCellOfst[6]=22 cells (6 PI)
8523 19:52:58.194667 u2DelayCellOfst[7]=7 cells (2 PI)
8524 19:52:58.198442 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8525 19:52:58.201440 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8526 19:52:58.205568 == TX Byte 1 ==
8527 19:52:58.208267 u2DelayCellOfst[8]=0 cells (0 PI)
8528 19:52:58.211562 u2DelayCellOfst[9]=3 cells (1 PI)
8529 19:52:58.214626 u2DelayCellOfst[10]=11 cells (3 PI)
8530 19:52:58.214788 u2DelayCellOfst[11]=3 cells (1 PI)
8531 19:52:58.218312 u2DelayCellOfst[12]=14 cells (4 PI)
8532 19:52:58.222167 u2DelayCellOfst[13]=14 cells (4 PI)
8533 19:52:58.225568 u2DelayCellOfst[14]=18 cells (5 PI)
8534 19:52:58.228401 u2DelayCellOfst[15]=18 cells (5 PI)
8535 19:52:58.235018 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8536 19:52:58.238656 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8537 19:52:58.238911 DramC Write-DBI on
8538 19:52:58.241448 ==
8539 19:52:58.241730 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 19:52:58.248360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 19:52:58.248686 ==
8542 19:52:58.248892
8543 19:52:58.249076
8544 19:52:58.252035 TX Vref Scan disable
8545 19:52:58.252424 == TX Byte 0 ==
8546 19:52:58.258199 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8547 19:52:58.258678 == TX Byte 1 ==
8548 19:52:58.261899 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8549 19:52:58.264756 DramC Write-DBI off
8550 19:52:58.265305
8551 19:52:58.265709 [DATLAT]
8552 19:52:58.268421 Freq=1600, CH1 RK0
8553 19:52:58.269109
8554 19:52:58.269524 DATLAT Default: 0xf
8555 19:52:58.271263 0, 0xFFFF, sum = 0
8556 19:52:58.271757 1, 0xFFFF, sum = 0
8557 19:52:58.274607 2, 0xFFFF, sum = 0
8558 19:52:58.275158 3, 0xFFFF, sum = 0
8559 19:52:58.277920 4, 0xFFFF, sum = 0
8560 19:52:58.278386 5, 0xFFFF, sum = 0
8561 19:52:58.281623 6, 0xFFFF, sum = 0
8562 19:52:58.282178 7, 0xFFFF, sum = 0
8563 19:52:58.284469 8, 0xFFFF, sum = 0
8564 19:52:58.284936 9, 0xFFFF, sum = 0
8565 19:52:58.288479 10, 0xFFFF, sum = 0
8566 19:52:58.291410 11, 0xFFFF, sum = 0
8567 19:52:58.292031 12, 0xFFFF, sum = 0
8568 19:52:58.294262 13, 0xFFFF, sum = 0
8569 19:52:58.294727 14, 0x0, sum = 1
8570 19:52:58.297636 15, 0x0, sum = 2
8571 19:52:58.298106 16, 0x0, sum = 3
8572 19:52:58.301163 17, 0x0, sum = 4
8573 19:52:58.301649 best_step = 15
8574 19:52:58.302017
8575 19:52:58.302363 ==
8576 19:52:58.304351 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 19:52:58.307816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 19:52:58.308376 ==
8579 19:52:58.311107 RX Vref Scan: 1
8580 19:52:58.311656
8581 19:52:58.314578 Set Vref Range= 24 -> 127
8582 19:52:58.315141
8583 19:52:58.315517 RX Vref 24 -> 127, step: 1
8584 19:52:58.315905
8585 19:52:58.317922 RX Delay 11 -> 252, step: 4
8586 19:52:58.318492
8587 19:52:58.321058 Set Vref, RX VrefLevel [Byte0]: 24
8588 19:52:58.324328 [Byte1]: 24
8589 19:52:58.327636
8590 19:52:58.328122 Set Vref, RX VrefLevel [Byte0]: 25
8591 19:52:58.331413 [Byte1]: 25
8592 19:52:58.335421
8593 19:52:58.336018 Set Vref, RX VrefLevel [Byte0]: 26
8594 19:52:58.339009 [Byte1]: 26
8595 19:52:58.343156
8596 19:52:58.343710 Set Vref, RX VrefLevel [Byte0]: 27
8597 19:52:58.346164 [Byte1]: 27
8598 19:52:58.350668
8599 19:52:58.351222 Set Vref, RX VrefLevel [Byte0]: 28
8600 19:52:58.354024 [Byte1]: 28
8601 19:52:58.358731
8602 19:52:58.359279 Set Vref, RX VrefLevel [Byte0]: 29
8603 19:52:58.361811 [Byte1]: 29
8604 19:52:58.366647
8605 19:52:58.367198 Set Vref, RX VrefLevel [Byte0]: 30
8606 19:52:58.369067 [Byte1]: 30
8607 19:52:58.373810
8608 19:52:58.374364 Set Vref, RX VrefLevel [Byte0]: 31
8609 19:52:58.376566 [Byte1]: 31
8610 19:52:58.381173
8611 19:52:58.381724 Set Vref, RX VrefLevel [Byte0]: 32
8612 19:52:58.384541 [Byte1]: 32
8613 19:52:58.388599
8614 19:52:58.389331 Set Vref, RX VrefLevel [Byte0]: 33
8615 19:52:58.392009 [Byte1]: 33
8616 19:52:58.396038
8617 19:52:58.396719 Set Vref, RX VrefLevel [Byte0]: 34
8618 19:52:58.399261 [Byte1]: 34
8619 19:52:58.403818
8620 19:52:58.404446 Set Vref, RX VrefLevel [Byte0]: 35
8621 19:52:58.406817 [Byte1]: 35
8622 19:52:58.411622
8623 19:52:58.412133 Set Vref, RX VrefLevel [Byte0]: 36
8624 19:52:58.414437 [Byte1]: 36
8625 19:52:58.418921
8626 19:52:58.419218 Set Vref, RX VrefLevel [Byte0]: 37
8627 19:52:58.422143 [Byte1]: 37
8628 19:52:58.426415
8629 19:52:58.426596 Set Vref, RX VrefLevel [Byte0]: 38
8630 19:52:58.430015 [Byte1]: 38
8631 19:52:58.434637
8632 19:52:58.434902 Set Vref, RX VrefLevel [Byte0]: 39
8633 19:52:58.437753 [Byte1]: 39
8634 19:52:58.441566
8635 19:52:58.441748 Set Vref, RX VrefLevel [Byte0]: 40
8636 19:52:58.444897 [Byte1]: 40
8637 19:52:58.449143
8638 19:52:58.449323 Set Vref, RX VrefLevel [Byte0]: 41
8639 19:52:58.453158 [Byte1]: 41
8640 19:52:58.457041
8641 19:52:58.457430 Set Vref, RX VrefLevel [Byte0]: 42
8642 19:52:58.459924 [Byte1]: 42
8643 19:52:58.464791
8644 19:52:58.465174 Set Vref, RX VrefLevel [Byte0]: 43
8645 19:52:58.467925 [Byte1]: 43
8646 19:52:58.472429
8647 19:52:58.472941 Set Vref, RX VrefLevel [Byte0]: 44
8648 19:52:58.475783 [Byte1]: 44
8649 19:52:58.480126
8650 19:52:58.480677 Set Vref, RX VrefLevel [Byte0]: 45
8651 19:52:58.483378 [Byte1]: 45
8652 19:52:58.488148
8653 19:52:58.488738 Set Vref, RX VrefLevel [Byte0]: 46
8654 19:52:58.491016 [Byte1]: 46
8655 19:52:58.495036
8656 19:52:58.495614 Set Vref, RX VrefLevel [Byte0]: 47
8657 19:52:58.498375 [Byte1]: 47
8658 19:52:58.503105
8659 19:52:58.503646 Set Vref, RX VrefLevel [Byte0]: 48
8660 19:52:58.506118 [Byte1]: 48
8661 19:52:58.510122
8662 19:52:58.510538 Set Vref, RX VrefLevel [Byte0]: 49
8663 19:52:58.513539 [Byte1]: 49
8664 19:52:58.517909
8665 19:52:58.518326 Set Vref, RX VrefLevel [Byte0]: 50
8666 19:52:58.522095 [Byte1]: 50
8667 19:52:58.525556
8668 19:52:58.526070 Set Vref, RX VrefLevel [Byte0]: 51
8669 19:52:58.528974 [Byte1]: 51
8670 19:52:58.533275
8671 19:52:58.533695 Set Vref, RX VrefLevel [Byte0]: 52
8672 19:52:58.536396 [Byte1]: 52
8673 19:52:58.540653
8674 19:52:58.541204 Set Vref, RX VrefLevel [Byte0]: 53
8675 19:52:58.543900 [Byte1]: 53
8676 19:52:58.548420
8677 19:52:58.548929 Set Vref, RX VrefLevel [Byte0]: 54
8678 19:52:58.551700 [Byte1]: 54
8679 19:52:58.555671
8680 19:52:58.556104 Set Vref, RX VrefLevel [Byte0]: 55
8681 19:52:58.558861 [Byte1]: 55
8682 19:52:58.563430
8683 19:52:58.563708 Set Vref, RX VrefLevel [Byte0]: 56
8684 19:52:58.566872 [Byte1]: 56
8685 19:52:58.571025
8686 19:52:58.571249 Set Vref, RX VrefLevel [Byte0]: 57
8687 19:52:58.574672 [Byte1]: 57
8688 19:52:58.578338
8689 19:52:58.578562 Set Vref, RX VrefLevel [Byte0]: 58
8690 19:52:58.581953 [Byte1]: 58
8691 19:52:58.585998
8692 19:52:58.586222 Set Vref, RX VrefLevel [Byte0]: 59
8693 19:52:58.589240 [Byte1]: 59
8694 19:52:58.593750
8695 19:52:58.594008 Set Vref, RX VrefLevel [Byte0]: 60
8696 19:52:58.597184 [Byte1]: 60
8697 19:52:58.601387
8698 19:52:58.601627 Set Vref, RX VrefLevel [Byte0]: 61
8699 19:52:58.604657 [Byte1]: 61
8700 19:52:58.609010
8701 19:52:58.609190 Set Vref, RX VrefLevel [Byte0]: 62
8702 19:52:58.612097 [Byte1]: 62
8703 19:52:58.616636
8704 19:52:58.616776 Set Vref, RX VrefLevel [Byte0]: 63
8705 19:52:58.619858 [Byte1]: 63
8706 19:52:58.624312
8707 19:52:58.624485 Set Vref, RX VrefLevel [Byte0]: 64
8708 19:52:58.627616 [Byte1]: 64
8709 19:52:58.631995
8710 19:52:58.632124 Set Vref, RX VrefLevel [Byte0]: 65
8711 19:52:58.635329 [Byte1]: 65
8712 19:52:58.639398
8713 19:52:58.639565 Set Vref, RX VrefLevel [Byte0]: 66
8714 19:52:58.642725 [Byte1]: 66
8715 19:52:58.647113
8716 19:52:58.647236 Set Vref, RX VrefLevel [Byte0]: 67
8717 19:52:58.650376 [Byte1]: 67
8718 19:52:58.654419
8719 19:52:58.654549 Set Vref, RX VrefLevel [Byte0]: 68
8720 19:52:58.657540 [Byte1]: 68
8721 19:52:58.662490
8722 19:52:58.662572 Set Vref, RX VrefLevel [Byte0]: 69
8723 19:52:58.665417 [Byte1]: 69
8724 19:52:58.669692
8725 19:52:58.669803 Set Vref, RX VrefLevel [Byte0]: 70
8726 19:52:58.672900 [Byte1]: 70
8727 19:52:58.677845
8728 19:52:58.677926 Set Vref, RX VrefLevel [Byte0]: 71
8729 19:52:58.680934 [Byte1]: 71
8730 19:52:58.684865
8731 19:52:58.684946 Set Vref, RX VrefLevel [Byte0]: 72
8732 19:52:58.689132 [Byte1]: 72
8733 19:52:58.693113
8734 19:52:58.693196 Set Vref, RX VrefLevel [Byte0]: 73
8735 19:52:58.696085 [Byte1]: 73
8736 19:52:58.699959
8737 19:52:58.700070 Final RX Vref Byte 0 = 51 to rank0
8738 19:52:58.703324 Final RX Vref Byte 1 = 59 to rank0
8739 19:52:58.706787 Final RX Vref Byte 0 = 51 to rank1
8740 19:52:58.710713 Final RX Vref Byte 1 = 59 to rank1==
8741 19:52:58.713428 Dram Type= 6, Freq= 0, CH_1, rank 0
8742 19:52:58.720374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 19:52:58.720482 ==
8744 19:52:58.720571 DQS Delay:
8745 19:52:58.720667 DQS0 = 0, DQS1 = 0
8746 19:52:58.723400 DQM Delay:
8747 19:52:58.723509 DQM0 = 133, DQM1 = 128
8748 19:52:58.726688 DQ Delay:
8749 19:52:58.730030 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =128
8750 19:52:58.733193 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8751 19:52:58.736441 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8752 19:52:58.739998 DQ12 =136, DQ13 =138, DQ14 =136, DQ15 =138
8753 19:52:58.740077
8754 19:52:58.740170
8755 19:52:58.740256
8756 19:52:58.743495 [DramC_TX_OE_Calibration] TA2
8757 19:52:58.746363 Original DQ_B0 (3 6) =30, OEN = 27
8758 19:52:58.749797 Original DQ_B1 (3 6) =30, OEN = 27
8759 19:52:58.753153 24, 0x0, End_B0=24 End_B1=24
8760 19:52:58.756272 25, 0x0, End_B0=25 End_B1=25
8761 19:52:58.756355 26, 0x0, End_B0=26 End_B1=26
8762 19:52:58.759920 27, 0x0, End_B0=27 End_B1=27
8763 19:52:58.762600 28, 0x0, End_B0=28 End_B1=28
8764 19:52:58.766326 29, 0x0, End_B0=29 End_B1=29
8765 19:52:58.766436 30, 0x0, End_B0=30 End_B1=30
8766 19:52:58.769518 31, 0x4141, End_B0=30 End_B1=30
8767 19:52:58.772491 Byte0 end_step=30 best_step=27
8768 19:52:58.775840 Byte1 end_step=30 best_step=27
8769 19:52:58.779316 Byte0 TX OE(2T, 0.5T) = (3, 3)
8770 19:52:58.782534 Byte1 TX OE(2T, 0.5T) = (3, 3)
8771 19:52:58.782616
8772 19:52:58.782681
8773 19:52:58.789404 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8774 19:52:58.793109 CH1 RK0: MR19=303, MR18=1B11
8775 19:52:58.799079 CH1_RK0: MR19=0x303, MR18=0x1B11, DQSOSC=396, MR23=63, INC=23, DEC=15
8776 19:52:58.799161
8777 19:52:58.802619 ----->DramcWriteLeveling(PI) begin...
8778 19:52:58.802701 ==
8779 19:52:58.805692 Dram Type= 6, Freq= 0, CH_1, rank 1
8780 19:52:58.808816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 19:52:58.808897 ==
8782 19:52:58.812273 Write leveling (Byte 0): 23 => 23
8783 19:52:58.815886 Write leveling (Byte 1): 26 => 26
8784 19:52:58.819102 DramcWriteLeveling(PI) end<-----
8785 19:52:58.819181
8786 19:52:58.819245 ==
8787 19:52:58.822301 Dram Type= 6, Freq= 0, CH_1, rank 1
8788 19:52:58.825574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 19:52:58.829886 ==
8790 19:52:58.829966 [Gating] SW mode calibration
8791 19:52:58.838956 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8792 19:52:58.842166 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8793 19:52:58.845241 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 19:52:58.851604 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 19:52:58.854984 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8796 19:52:58.858116 1 4 12 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8797 19:52:58.865423 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8798 19:52:58.868615 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 19:52:58.871695 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 19:52:58.878213 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 19:52:58.881341 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 19:52:58.884909 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 19:52:58.891542 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
8804 19:52:58.894925 1 5 12 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)
8805 19:52:58.898212 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 19:52:58.904889 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 19:52:58.908226 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 19:52:58.911543 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 19:52:58.917711 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 19:52:58.921441 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 19:52:58.924830 1 6 8 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
8812 19:52:58.931362 1 6 12 | B1->B0 | 4646 2525 | 0 1 | (0 0) (0 0)
8813 19:52:58.934631 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 19:52:58.937893 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 19:52:58.944402 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 19:52:58.947716 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 19:52:58.950784 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 19:52:58.957981 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 19:52:58.960991 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8820 19:52:58.964400 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8821 19:52:58.971072 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8822 19:52:58.974290 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 19:52:58.977286 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 19:52:58.984132 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 19:52:58.987227 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 19:52:58.990747 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 19:52:58.997422 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 19:52:59.000679 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 19:52:59.003866 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 19:52:59.011263 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 19:52:59.014415 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 19:52:59.017157 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 19:52:59.024569 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 19:52:59.027322 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 19:52:59.030849 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8836 19:52:59.037393 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8837 19:52:59.040469 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8838 19:52:59.044122 Total UI for P1: 0, mck2ui 16
8839 19:52:59.047468 best dqsien dly found for B1: ( 1, 9, 10)
8840 19:52:59.050462 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 19:52:59.054153 Total UI for P1: 0, mck2ui 16
8842 19:52:59.057046 best dqsien dly found for B0: ( 1, 9, 12)
8843 19:52:59.060965 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8844 19:52:59.064123 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8845 19:52:59.064597
8846 19:52:59.070001 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8847 19:52:59.073775 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8848 19:52:59.077266 [Gating] SW calibration Done
8849 19:52:59.077781 ==
8850 19:52:59.080003 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 19:52:59.083642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 19:52:59.084098 ==
8853 19:52:59.084542 RX Vref Scan: 0
8854 19:52:59.085033
8855 19:52:59.087191 RX Vref 0 -> 0, step: 1
8856 19:52:59.087611
8857 19:52:59.089999 RX Delay 0 -> 252, step: 8
8858 19:52:59.093970 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8859 19:52:59.096813 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8860 19:52:59.103324 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8861 19:52:59.106987 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8862 19:52:59.110161 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8863 19:52:59.113328 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8864 19:52:59.116690 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8865 19:52:59.123282 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8866 19:52:59.126847 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8867 19:52:59.129904 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8868 19:52:59.133228 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8869 19:52:59.136358 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8870 19:52:59.143456 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8871 19:52:59.146264 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8872 19:52:59.149398 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8873 19:52:59.152650 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8874 19:52:59.153155 ==
8875 19:52:59.156135 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 19:52:59.162875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 19:52:59.163427 ==
8878 19:52:59.163830 DQS Delay:
8879 19:52:59.166012 DQS0 = 0, DQS1 = 0
8880 19:52:59.166560 DQM Delay:
8881 19:52:59.169584 DQM0 = 137, DQM1 = 129
8882 19:52:59.170111 DQ Delay:
8883 19:52:59.172238 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8884 19:52:59.175613 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8885 19:52:59.179068 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8886 19:52:59.182256 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8887 19:52:59.182713
8888 19:52:59.183075
8889 19:52:59.183406 ==
8890 19:52:59.185635 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 19:52:59.192149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 19:52:59.192606 ==
8893 19:52:59.192971
8894 19:52:59.193348
8895 19:52:59.193699 TX Vref Scan disable
8896 19:52:59.196273 == TX Byte 0 ==
8897 19:52:59.199464 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8898 19:52:59.206301 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8899 19:52:59.206857 == TX Byte 1 ==
8900 19:52:59.209573 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8901 19:52:59.216032 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8902 19:52:59.216588 ==
8903 19:52:59.219579 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 19:52:59.222060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 19:52:59.222620 ==
8906 19:52:59.234485
8907 19:52:59.238475 TX Vref early break, caculate TX vref
8908 19:52:59.241346 TX Vref=16, minBit 0, minWin=22, winSum=384
8909 19:52:59.244739 TX Vref=18, minBit 6, minWin=22, winSum=390
8910 19:52:59.248088 TX Vref=20, minBit 0, minWin=23, winSum=399
8911 19:52:59.251542 TX Vref=22, minBit 1, minWin=23, winSum=404
8912 19:52:59.254745 TX Vref=24, minBit 0, minWin=25, winSum=417
8913 19:52:59.260941 TX Vref=26, minBit 5, minWin=24, winSum=421
8914 19:52:59.264456 TX Vref=28, minBit 0, minWin=23, winSum=419
8915 19:52:59.268090 TX Vref=30, minBit 0, minWin=23, winSum=413
8916 19:52:59.271316 TX Vref=32, minBit 0, minWin=23, winSum=404
8917 19:52:59.274689 TX Vref=34, minBit 0, minWin=22, winSum=393
8918 19:52:59.280740 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 24
8919 19:52:59.281292
8920 19:52:59.284265 Final TX Range 0 Vref 24
8921 19:52:59.284813
8922 19:52:59.285174 ==
8923 19:52:59.287516 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 19:52:59.290892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 19:52:59.291349 ==
8926 19:52:59.291789
8927 19:52:59.292145
8928 19:52:59.294099 TX Vref Scan disable
8929 19:52:59.300527 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8930 19:52:59.300982 == TX Byte 0 ==
8931 19:52:59.304352 u2DelayCellOfst[0]=22 cells (6 PI)
8932 19:52:59.307548 u2DelayCellOfst[1]=14 cells (4 PI)
8933 19:52:59.311014 u2DelayCellOfst[2]=0 cells (0 PI)
8934 19:52:59.314124 u2DelayCellOfst[3]=7 cells (2 PI)
8935 19:52:59.317522 u2DelayCellOfst[4]=11 cells (3 PI)
8936 19:52:59.320205 u2DelayCellOfst[5]=22 cells (6 PI)
8937 19:52:59.323606 u2DelayCellOfst[6]=22 cells (6 PI)
8938 19:52:59.327156 u2DelayCellOfst[7]=7 cells (2 PI)
8939 19:52:59.329985 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8940 19:52:59.334362 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8941 19:52:59.336759 == TX Byte 1 ==
8942 19:52:59.340523 u2DelayCellOfst[8]=0 cells (0 PI)
8943 19:52:59.343896 u2DelayCellOfst[9]=3 cells (1 PI)
8944 19:52:59.346990 u2DelayCellOfst[10]=14 cells (4 PI)
8945 19:52:59.347472 u2DelayCellOfst[11]=7 cells (2 PI)
8946 19:52:59.349974 u2DelayCellOfst[12]=14 cells (4 PI)
8947 19:52:59.353723 u2DelayCellOfst[13]=14 cells (4 PI)
8948 19:52:59.356923 u2DelayCellOfst[14]=18 cells (5 PI)
8949 19:52:59.360317 u2DelayCellOfst[15]=18 cells (5 PI)
8950 19:52:59.366590 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8951 19:52:59.369817 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8952 19:52:59.370405 DramC Write-DBI on
8953 19:52:59.373283 ==
8954 19:52:59.373833 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 19:52:59.379870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 19:52:59.380427 ==
8957 19:52:59.380799
8958 19:52:59.381138
8959 19:52:59.383042 TX Vref Scan disable
8960 19:52:59.383593 == TX Byte 0 ==
8961 19:52:59.389830 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8962 19:52:59.390392 == TX Byte 1 ==
8963 19:52:59.393727 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8964 19:52:59.396471 DramC Write-DBI off
8965 19:52:59.397026
8966 19:52:59.397400 [DATLAT]
8967 19:52:59.399837 Freq=1600, CH1 RK1
8968 19:52:59.400401
8969 19:52:59.400776 DATLAT Default: 0xf
8970 19:52:59.403083 0, 0xFFFF, sum = 0
8971 19:52:59.403546 1, 0xFFFF, sum = 0
8972 19:52:59.406492 2, 0xFFFF, sum = 0
8973 19:52:59.407048 3, 0xFFFF, sum = 0
8974 19:52:59.409430 4, 0xFFFF, sum = 0
8975 19:52:59.409923 5, 0xFFFF, sum = 0
8976 19:52:59.412669 6, 0xFFFF, sum = 0
8977 19:52:59.413201 7, 0xFFFF, sum = 0
8978 19:52:59.415976 8, 0xFFFF, sum = 0
8979 19:52:59.416451 9, 0xFFFF, sum = 0
8980 19:52:59.419622 10, 0xFFFF, sum = 0
8981 19:52:59.422913 11, 0xFFFF, sum = 0
8982 19:52:59.423468 12, 0xFFFF, sum = 0
8983 19:52:59.426427 13, 0xFFFF, sum = 0
8984 19:52:59.427082 14, 0x0, sum = 1
8985 19:52:59.429849 15, 0x0, sum = 2
8986 19:52:59.430427 16, 0x0, sum = 3
8987 19:52:59.432971 17, 0x0, sum = 4
8988 19:52:59.433545 best_step = 15
8989 19:52:59.433911
8990 19:52:59.434248 ==
8991 19:52:59.436943 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 19:52:59.439660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 19:52:59.440268 ==
8994 19:52:59.443552 RX Vref Scan: 0
8995 19:52:59.444181
8996 19:52:59.445879 RX Vref 0 -> 0, step: 1
8997 19:52:59.446333
8998 19:52:59.446695 RX Delay 11 -> 252, step: 4
8999 19:52:59.453153 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9000 19:52:59.456427 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9001 19:52:59.459950 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9002 19:52:59.463037 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9003 19:52:59.466353 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9004 19:52:59.473023 iDelay=203, Bit 5, Center 142 (91 ~ 194) 104
9005 19:52:59.476680 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9006 19:52:59.479602 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9007 19:52:59.482733 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9008 19:52:59.486873 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9009 19:52:59.493095 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9010 19:52:59.496721 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9011 19:52:59.498997 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9012 19:52:59.502639 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9013 19:52:59.509694 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9014 19:52:59.512417 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9015 19:52:59.512882 ==
9016 19:52:59.516121 Dram Type= 6, Freq= 0, CH_1, rank 1
9017 19:52:59.519047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9018 19:52:59.519647 ==
9019 19:52:59.522600 DQS Delay:
9020 19:52:59.523151 DQS0 = 0, DQS1 = 0
9021 19:52:59.523522 DQM Delay:
9022 19:52:59.525778 DQM0 = 133, DQM1 = 127
9023 19:52:59.526239 DQ Delay:
9024 19:52:59.529205 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9025 19:52:59.532559 DQ4 =132, DQ5 =142, DQ6 =146, DQ7 =130
9026 19:52:59.539219 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =118
9027 19:52:59.542233 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9028 19:52:59.542840
9029 19:52:59.543361
9030 19:52:59.543876
9031 19:52:59.545422 [DramC_TX_OE_Calibration] TA2
9032 19:52:59.548680 Original DQ_B0 (3 6) =30, OEN = 27
9033 19:52:59.552117 Original DQ_B1 (3 6) =30, OEN = 27
9034 19:52:59.552672 24, 0x0, End_B0=24 End_B1=24
9035 19:52:59.555059 25, 0x0, End_B0=25 End_B1=25
9036 19:52:59.558461 26, 0x0, End_B0=26 End_B1=26
9037 19:52:59.562180 27, 0x0, End_B0=27 End_B1=27
9038 19:52:59.562738 28, 0x0, End_B0=28 End_B1=28
9039 19:52:59.565479 29, 0x0, End_B0=29 End_B1=29
9040 19:52:59.568462 30, 0x0, End_B0=30 End_B1=30
9041 19:52:59.571783 31, 0x4141, End_B0=30 End_B1=30
9042 19:52:59.575521 Byte0 end_step=30 best_step=27
9043 19:52:59.578336 Byte1 end_step=30 best_step=27
9044 19:52:59.578801 Byte0 TX OE(2T, 0.5T) = (3, 3)
9045 19:52:59.581792 Byte1 TX OE(2T, 0.5T) = (3, 3)
9046 19:52:59.582257
9047 19:52:59.582627
9048 19:52:59.591309 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 402 ps
9049 19:52:59.594688 CH1 RK1: MR19=303, MR18=F0C
9050 19:52:59.598062 CH1_RK1: MR19=0x303, MR18=0xF0C, DQSOSC=402, MR23=63, INC=22, DEC=15
9051 19:52:59.601358 [RxdqsGatingPostProcess] freq 1600
9052 19:52:59.608009 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9053 19:52:59.611341 best DQS0 dly(2T, 0.5T) = (1, 1)
9054 19:52:59.614458 best DQS1 dly(2T, 0.5T) = (1, 1)
9055 19:52:59.618074 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9056 19:52:59.620972 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9057 19:52:59.624284 best DQS0 dly(2T, 0.5T) = (1, 1)
9058 19:52:59.627985 best DQS1 dly(2T, 0.5T) = (1, 1)
9059 19:52:59.628588 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9060 19:52:59.631117 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9061 19:52:59.634951 Pre-setting of DQS Precalculation
9062 19:52:59.640864 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9063 19:52:59.647270 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9064 19:52:59.653974 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9065 19:52:59.654434
9066 19:52:59.654879
9067 19:52:59.657516 [Calibration Summary] 3200 Mbps
9068 19:52:59.660713 CH 0, Rank 0
9069 19:52:59.661167 SW Impedance : PASS
9070 19:52:59.664417 DUTY Scan : NO K
9071 19:52:59.667719 ZQ Calibration : PASS
9072 19:52:59.668384 Jitter Meter : NO K
9073 19:52:59.670501 CBT Training : PASS
9074 19:52:59.674354 Write leveling : PASS
9075 19:52:59.675016 RX DQS gating : PASS
9076 19:52:59.677086 RX DQ/DQS(RDDQC) : PASS
9077 19:52:59.677552 TX DQ/DQS : PASS
9078 19:52:59.681062 RX DATLAT : PASS
9079 19:52:59.683781 RX DQ/DQS(Engine): PASS
9080 19:52:59.684238 TX OE : PASS
9081 19:52:59.687891 All Pass.
9082 19:52:59.688309
9083 19:52:59.688645 CH 0, Rank 1
9084 19:52:59.690186 SW Impedance : PASS
9085 19:52:59.690702 DUTY Scan : NO K
9086 19:52:59.693766 ZQ Calibration : PASS
9087 19:52:59.697344 Jitter Meter : NO K
9088 19:52:59.697755 CBT Training : PASS
9089 19:52:59.700805 Write leveling : PASS
9090 19:52:59.703377 RX DQS gating : PASS
9091 19:52:59.703840 RX DQ/DQS(RDDQC) : PASS
9092 19:52:59.706936 TX DQ/DQS : PASS
9093 19:52:59.710529 RX DATLAT : PASS
9094 19:52:59.711051 RX DQ/DQS(Engine): PASS
9095 19:52:59.713708 TX OE : PASS
9096 19:52:59.714130 All Pass.
9097 19:52:59.714469
9098 19:52:59.716895 CH 1, Rank 0
9099 19:52:59.717313 SW Impedance : PASS
9100 19:52:59.720181 DUTY Scan : NO K
9101 19:52:59.723632 ZQ Calibration : PASS
9102 19:52:59.724075 Jitter Meter : NO K
9103 19:52:59.727083 CBT Training : PASS
9104 19:52:59.730024 Write leveling : PASS
9105 19:52:59.730482 RX DQS gating : PASS
9106 19:52:59.733294 RX DQ/DQS(RDDQC) : PASS
9107 19:52:59.737017 TX DQ/DQS : PASS
9108 19:52:59.737440 RX DATLAT : PASS
9109 19:52:59.740199 RX DQ/DQS(Engine): PASS
9110 19:52:59.740674 TX OE : PASS
9111 19:52:59.743313 All Pass.
9112 19:52:59.743766
9113 19:52:59.744116 CH 1, Rank 1
9114 19:52:59.747047 SW Impedance : PASS
9115 19:52:59.747479 DUTY Scan : NO K
9116 19:52:59.749650 ZQ Calibration : PASS
9117 19:52:59.753141 Jitter Meter : NO K
9118 19:52:59.753560 CBT Training : PASS
9119 19:52:59.756932 Write leveling : PASS
9120 19:52:59.759834 RX DQS gating : PASS
9121 19:52:59.760255 RX DQ/DQS(RDDQC) : PASS
9122 19:52:59.763720 TX DQ/DQS : PASS
9123 19:52:59.766618 RX DATLAT : PASS
9124 19:52:59.767122 RX DQ/DQS(Engine): PASS
9125 19:52:59.769992 TX OE : PASS
9126 19:52:59.770516 All Pass.
9127 19:52:59.770860
9128 19:52:59.773324 DramC Write-DBI on
9129 19:52:59.776314 PER_BANK_REFRESH: Hybrid Mode
9130 19:52:59.776739 TX_TRACKING: ON
9131 19:52:59.786078 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9132 19:52:59.793141 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9133 19:52:59.799799 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9134 19:52:59.806334 [FAST_K] Save calibration result to emmc
9135 19:52:59.806912 sync common calibartion params.
9136 19:52:59.810429 sync cbt_mode0:1, 1:1
9137 19:52:59.813036 dram_init: ddr_geometry: 2
9138 19:52:59.813586 dram_init: ddr_geometry: 2
9139 19:52:59.816104 dram_init: ddr_geometry: 2
9140 19:52:59.819460 0:dram_rank_size:100000000
9141 19:52:59.823046 1:dram_rank_size:100000000
9142 19:52:59.826047 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9143 19:52:59.829735 DFS_SHUFFLE_HW_MODE: ON
9144 19:52:59.833131 dramc_set_vcore_voltage set vcore to 725000
9145 19:52:59.835951 Read voltage for 1600, 0
9146 19:52:59.836405 Vio18 = 0
9147 19:52:59.839390 Vcore = 725000
9148 19:52:59.839986 Vdram = 0
9149 19:52:59.840361 Vddq = 0
9150 19:52:59.840725 Vmddr = 0
9151 19:52:59.842436 switch to 3200 Mbps bootup
9152 19:52:59.845717 [DramcRunTimeConfig]
9153 19:52:59.846209 PHYPLL
9154 19:52:59.848957 DPM_CONTROL_AFTERK: ON
9155 19:52:59.849455 PER_BANK_REFRESH: ON
9156 19:52:59.852258 REFRESH_OVERHEAD_REDUCTION: ON
9157 19:52:59.855495 CMD_PICG_NEW_MODE: OFF
9158 19:52:59.856034 XRTWTW_NEW_MODE: ON
9159 19:52:59.859140 XRTRTR_NEW_MODE: ON
9160 19:52:59.859684 TX_TRACKING: ON
9161 19:52:59.862552 RDSEL_TRACKING: OFF
9162 19:52:59.865492 DQS Precalculation for DVFS: ON
9163 19:52:59.865933 RX_TRACKING: OFF
9164 19:52:59.866275 HW_GATING DBG: ON
9165 19:52:59.868891 ZQCS_ENABLE_LP4: ON
9166 19:52:59.872264 RX_PICG_NEW_MODE: ON
9167 19:52:59.872698 TX_PICG_NEW_MODE: ON
9168 19:52:59.875542 ENABLE_RX_DCM_DPHY: ON
9169 19:52:59.878823 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9170 19:52:59.882444 DUMMY_READ_FOR_TRACKING: OFF
9171 19:52:59.882959 !!! SPM_CONTROL_AFTERK: OFF
9172 19:52:59.885729 !!! SPM could not control APHY
9173 19:52:59.888759 IMPEDANCE_TRACKING: ON
9174 19:52:59.889260 TEMP_SENSOR: ON
9175 19:52:59.892267 HW_SAVE_FOR_SR: OFF
9176 19:52:59.895365 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9177 19:52:59.898572 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9178 19:52:59.898988 Read ODT Tracking: ON
9179 19:52:59.901905 Refresh Rate DeBounce: ON
9180 19:52:59.905580 DFS_NO_QUEUE_FLUSH: ON
9181 19:52:59.909085 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9182 19:52:59.909598 ENABLE_DFS_RUNTIME_MRW: OFF
9183 19:52:59.911650 DDR_RESERVE_NEW_MODE: ON
9184 19:52:59.915161 MR_CBT_SWITCH_FREQ: ON
9185 19:52:59.915715 =========================
9186 19:52:59.935488 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9187 19:52:59.938765 dram_init: ddr_geometry: 2
9188 19:52:59.956917 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9189 19:52:59.960303 dram_init: dram init end (result: 0)
9190 19:52:59.967120 DRAM-K: Full calibration passed in 24603 msecs
9191 19:52:59.970212 MRC: failed to locate region type 0.
9192 19:52:59.970776 DRAM rank0 size:0x100000000,
9193 19:52:59.973470 DRAM rank1 size=0x100000000
9194 19:52:59.983894 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9195 19:52:59.990407 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9196 19:52:59.999938 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9197 19:53:00.005939 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9198 19:53:00.006586 DRAM rank0 size:0x100000000,
9199 19:53:00.009697 DRAM rank1 size=0x100000000
9200 19:53:00.010156 CBMEM:
9201 19:53:00.012500 IMD: root @ 0xfffff000 254 entries.
9202 19:53:00.016169 IMD: root @ 0xffffec00 62 entries.
9203 19:53:00.022548 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9204 19:53:00.025655 WARNING: RO_VPD is uninitialized or empty.
9205 19:53:00.029493 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9206 19:53:00.037015 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9207 19:53:00.050235 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9208 19:53:00.062030 BS: romstage times (exec / console): total (unknown) / 24101 ms
9209 19:53:00.062590
9210 19:53:00.062961
9211 19:53:00.071113 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9212 19:53:00.074588 ARM64: Exception handlers installed.
9213 19:53:00.077835 ARM64: Testing exception
9214 19:53:00.080883 ARM64: Done test exception
9215 19:53:00.081375 Enumerating buses...
9216 19:53:00.084251 Show all devs... Before device enumeration.
9217 19:53:00.087486 Root Device: enabled 1
9218 19:53:00.091446 CPU_CLUSTER: 0: enabled 1
9219 19:53:00.092059 CPU: 00: enabled 1
9220 19:53:00.094524 Compare with tree...
9221 19:53:00.095144 Root Device: enabled 1
9222 19:53:00.097399 CPU_CLUSTER: 0: enabled 1
9223 19:53:00.101016 CPU: 00: enabled 1
9224 19:53:00.101476 Root Device scanning...
9225 19:53:00.103889 scan_static_bus for Root Device
9226 19:53:00.107925 CPU_CLUSTER: 0 enabled
9227 19:53:00.110947 scan_static_bus for Root Device done
9228 19:53:00.114017 scan_bus: bus Root Device finished in 8 msecs
9229 19:53:00.114573 done
9230 19:53:00.120454 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9231 19:53:00.123806 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9232 19:53:00.130345 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9233 19:53:00.134224 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9234 19:53:00.136672 Allocating resources...
9235 19:53:00.140221 Reading resources...
9236 19:53:00.143457 Root Device read_resources bus 0 link: 0
9237 19:53:00.146572 DRAM rank0 size:0x100000000,
9238 19:53:00.147048 DRAM rank1 size=0x100000000
9239 19:53:00.153431 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9240 19:53:00.153997 CPU: 00 missing read_resources
9241 19:53:00.160089 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9242 19:53:00.163224 Root Device read_resources bus 0 link: 0 done
9243 19:53:00.166638 Done reading resources.
9244 19:53:00.170309 Show resources in subtree (Root Device)...After reading.
9245 19:53:00.173016 Root Device child on link 0 CPU_CLUSTER: 0
9246 19:53:00.176441 CPU_CLUSTER: 0 child on link 0 CPU: 00
9247 19:53:00.187073 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9248 19:53:00.187589 CPU: 00
9249 19:53:00.192997 Root Device assign_resources, bus 0 link: 0
9250 19:53:00.196199 CPU_CLUSTER: 0 missing set_resources
9251 19:53:00.199548 Root Device assign_resources, bus 0 link: 0 done
9252 19:53:00.200080 Done setting resources.
9253 19:53:00.206348 Show resources in subtree (Root Device)...After assigning values.
9254 19:53:00.209686 Root Device child on link 0 CPU_CLUSTER: 0
9255 19:53:00.216147 CPU_CLUSTER: 0 child on link 0 CPU: 00
9256 19:53:00.222900 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9257 19:53:00.225908 CPU: 00
9258 19:53:00.226484 Done allocating resources.
9259 19:53:00.232715 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9260 19:53:00.233287 Enabling resources...
9261 19:53:00.235866 done.
9262 19:53:00.238892 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9263 19:53:00.242427 Initializing devices...
9264 19:53:00.242854 Root Device init
9265 19:53:00.245246 init hardware done!
9266 19:53:00.245676 0x00000018: ctrlr->caps
9267 19:53:00.248372 52.000 MHz: ctrlr->f_max
9268 19:53:00.251954 0.400 MHz: ctrlr->f_min
9269 19:53:00.255154 0x40ff8080: ctrlr->voltages
9270 19:53:00.255611 sclk: 390625
9271 19:53:00.256086 Bus Width = 1
9272 19:53:00.258850 sclk: 390625
9273 19:53:00.259377 Bus Width = 1
9274 19:53:00.262177 Early init status = 3
9275 19:53:00.265790 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9276 19:53:00.268734 in-header: 03 fc 00 00 01 00 00 00
9277 19:53:00.272350 in-data: 00
9278 19:53:00.275038 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9279 19:53:00.281436 in-header: 03 fd 00 00 00 00 00 00
9280 19:53:00.285254 in-data:
9281 19:53:00.288172 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9282 19:53:00.292025 in-header: 03 fc 00 00 01 00 00 00
9283 19:53:00.295421 in-data: 00
9284 19:53:00.298678 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9285 19:53:00.303521 in-header: 03 fd 00 00 00 00 00 00
9286 19:53:00.307090 in-data:
9287 19:53:00.310779 [SSUSB] Setting up USB HOST controller...
9288 19:53:00.313369 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9289 19:53:00.317981 [SSUSB] phy power-on done.
9290 19:53:00.320112 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9291 19:53:00.327248 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9292 19:53:00.330564 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9293 19:53:00.336935 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9294 19:53:00.343478 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9295 19:53:00.349816 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9296 19:53:00.356523 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9297 19:53:00.363000 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9298 19:53:00.366649 SPM: binary array size = 0x9dc
9299 19:53:00.369677 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9300 19:53:00.376681 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9301 19:53:00.382611 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9302 19:53:00.389621 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9303 19:53:00.392546 configure_display: Starting display init
9304 19:53:00.427679 anx7625_power_on_init: Init interface.
9305 19:53:00.430656 anx7625_disable_pd_protocol: Disabled PD feature.
9306 19:53:00.433767 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9307 19:53:00.461727 anx7625_start_dp_work: Secure OCM version=00
9308 19:53:00.464672 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9309 19:53:00.480538 sp_tx_get_edid_block: EDID Block = 1
9310 19:53:00.582185 Extracted contents:
9311 19:53:00.585189 header: 00 ff ff ff ff ff ff 00
9312 19:53:00.589069 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9313 19:53:00.591850 version: 01 04
9314 19:53:00.595921 basic params: 95 1f 11 78 0a
9315 19:53:00.598773 chroma info: 76 90 94 55 54 90 27 21 50 54
9316 19:53:00.602362 established: 00 00 00
9317 19:53:00.608231 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9318 19:53:00.615332 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9319 19:53:00.618061 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9320 19:53:00.624732 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9321 19:53:00.631608 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9322 19:53:00.635198 extensions: 00
9323 19:53:00.635807 checksum: fb
9324 19:53:00.636301
9325 19:53:00.638692 Manufacturer: IVO Model 57d Serial Number 0
9326 19:53:00.641953 Made week 0 of 2020
9327 19:53:00.644911 EDID version: 1.4
9328 19:53:00.645475 Digital display
9329 19:53:00.648348 6 bits per primary color channel
9330 19:53:00.648916 DisplayPort interface
9331 19:53:00.651997 Maximum image size: 31 cm x 17 cm
9332 19:53:00.654744 Gamma: 220%
9333 19:53:00.655306 Check DPMS levels
9334 19:53:00.660989 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9335 19:53:00.664672 First detailed timing is preferred timing
9336 19:53:00.665279 Established timings supported:
9337 19:53:00.667806 Standard timings supported:
9338 19:53:00.671167 Detailed timings
9339 19:53:00.674269 Hex of detail: 383680a07038204018303c0035ae10000019
9340 19:53:00.680834 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9341 19:53:00.684641 0780 0798 07c8 0820 hborder 0
9342 19:53:00.687786 0438 043b 0447 0458 vborder 0
9343 19:53:00.690927 -hsync -vsync
9344 19:53:00.691400 Did detailed timing
9345 19:53:00.697429 Hex of detail: 000000000000000000000000000000000000
9346 19:53:00.700859 Manufacturer-specified data, tag 0
9347 19:53:00.704466 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9348 19:53:00.707328 ASCII string: InfoVision
9349 19:53:00.710616 Hex of detail: 000000fe00523134304e574635205248200a
9350 19:53:00.714096 ASCII string: R140NWF5 RH
9351 19:53:00.714560 Checksum
9352 19:53:00.717179 Checksum: 0xfb (valid)
9353 19:53:00.720474 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9354 19:53:00.723339 DSI data_rate: 832800000 bps
9355 19:53:00.730257 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9356 19:53:00.733700 anx7625_parse_edid: pixelclock(138800).
9357 19:53:00.736906 hactive(1920), hsync(48), hfp(24), hbp(88)
9358 19:53:00.740047 vactive(1080), vsync(12), vfp(3), vbp(17)
9359 19:53:00.743691 anx7625_dsi_config: config dsi.
9360 19:53:00.750256 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9361 19:53:00.764294 anx7625_dsi_config: success to config DSI
9362 19:53:00.767243 anx7625_dp_start: MIPI phy setup OK.
9363 19:53:00.770743 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9364 19:53:00.773645 mtk_ddp_mode_set invalid vrefresh 60
9365 19:53:00.777578 main_disp_path_setup
9366 19:53:00.778106 ovl_layer_smi_id_en
9367 19:53:00.780638 ovl_layer_smi_id_en
9368 19:53:00.781051 ccorr_config
9369 19:53:00.781382 aal_config
9370 19:53:00.783918 gamma_config
9371 19:53:00.784338 postmask_config
9372 19:53:00.787552 dither_config
9373 19:53:00.790298 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9374 19:53:00.796782 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9375 19:53:00.800092 Root Device init finished in 554 msecs
9376 19:53:00.803260 CPU_CLUSTER: 0 init
9377 19:53:00.809914 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9378 19:53:00.816297 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9379 19:53:00.816716 APU_MBOX 0x190000b0 = 0x10001
9380 19:53:00.819761 APU_MBOX 0x190001b0 = 0x10001
9381 19:53:00.823265 APU_MBOX 0x190005b0 = 0x10001
9382 19:53:00.826503 APU_MBOX 0x190006b0 = 0x10001
9383 19:53:00.833308 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9384 19:53:00.843163 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9385 19:53:00.856022 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9386 19:53:00.862384 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9387 19:53:00.873791 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9388 19:53:00.882851 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9389 19:53:00.886326 CPU_CLUSTER: 0 init finished in 81 msecs
9390 19:53:00.889441 Devices initialized
9391 19:53:00.892955 Show all devs... After init.
9392 19:53:00.893510 Root Device: enabled 1
9393 19:53:00.895952 CPU_CLUSTER: 0: enabled 1
9394 19:53:00.899887 CPU: 00: enabled 1
9395 19:53:00.902999 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9396 19:53:00.906020 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9397 19:53:00.908866 ELOG: NV offset 0x57f000 size 0x1000
9398 19:53:00.916250 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9399 19:53:00.922580 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9400 19:53:00.925707 ELOG: Event(17) added with size 13 at 2023-10-28 19:53:01 UTC
9401 19:53:00.932506 out: cmd=0x121: 03 db 21 01 00 00 00 00
9402 19:53:00.935990 in-header: 03 dd 00 00 2c 00 00 00
9403 19:53:00.948538 in-data: 82 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9404 19:53:00.951833 ELOG: Event(A1) added with size 10 at 2023-10-28 19:53:01 UTC
9405 19:53:00.959313 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9406 19:53:00.965190 ELOG: Event(A0) added with size 9 at 2023-10-28 19:53:01 UTC
9407 19:53:00.968949 elog_add_boot_reason: Logged dev mode boot
9408 19:53:00.974960 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9409 19:53:00.975521 Finalize devices...
9410 19:53:00.978439 Devices finalized
9411 19:53:00.981950 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9412 19:53:00.985202 Writing coreboot table at 0xffe64000
9413 19:53:00.988512 0. 000000000010a000-0000000000113fff: RAMSTAGE
9414 19:53:00.995116 1. 0000000040000000-00000000400fffff: RAM
9415 19:53:00.998195 2. 0000000040100000-000000004032afff: RAMSTAGE
9416 19:53:01.001463 3. 000000004032b000-00000000545fffff: RAM
9417 19:53:01.005339 4. 0000000054600000-000000005465ffff: BL31
9418 19:53:01.008125 5. 0000000054660000-00000000ffe63fff: RAM
9419 19:53:01.014745 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9420 19:53:01.018313 7. 0000000100000000-000000023fffffff: RAM
9421 19:53:01.021192 Passing 5 GPIOs to payload:
9422 19:53:01.024443 NAME | PORT | POLARITY | VALUE
9423 19:53:01.031146 EC in RW | 0x000000aa | low | undefined
9424 19:53:01.034600 EC interrupt | 0x00000005 | low | undefined
9425 19:53:01.041073 TPM interrupt | 0x000000ab | high | undefined
9426 19:53:01.044268 SD card detect | 0x00000011 | high | undefined
9427 19:53:01.048529 speaker enable | 0x00000093 | high | undefined
9428 19:53:01.051462 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9429 19:53:01.054523 in-header: 03 f9 00 00 02 00 00 00
9430 19:53:01.057383 in-data: 02 00
9431 19:53:01.060920 ADC[4]: Raw value=903031 ID=7
9432 19:53:01.064125 ADC[3]: Raw value=213282 ID=1
9433 19:53:01.064600 RAM Code: 0x71
9434 19:53:01.067941 ADC[6]: Raw value=75036 ID=0
9435 19:53:01.070728 ADC[5]: Raw value=213652 ID=1
9436 19:53:01.071293 SKU Code: 0x1
9437 19:53:01.077130 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a16d
9438 19:53:01.077698 coreboot table: 964 bytes.
9439 19:53:01.080915 IMD ROOT 0. 0xfffff000 0x00001000
9440 19:53:01.083899 IMD SMALL 1. 0xffffe000 0x00001000
9441 19:53:01.087356 RO MCACHE 2. 0xffffc000 0x00001104
9442 19:53:01.090465 CONSOLE 3. 0xfff7c000 0x00080000
9443 19:53:01.093738 FMAP 4. 0xfff7b000 0x00000452
9444 19:53:01.096833 TIME STAMP 5. 0xfff7a000 0x00000910
9445 19:53:01.100666 VBOOT WORK 6. 0xfff66000 0x00014000
9446 19:53:01.103600 RAMOOPS 7. 0xffe66000 0x00100000
9447 19:53:01.107116 COREBOOT 8. 0xffe64000 0x00002000
9448 19:53:01.110089 IMD small region:
9449 19:53:01.114171 IMD ROOT 0. 0xffffec00 0x00000400
9450 19:53:01.116939 VPD 1. 0xffffeb80 0x0000006c
9451 19:53:01.120113 MMC STATUS 2. 0xffffeb60 0x00000004
9452 19:53:01.127056 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9453 19:53:01.127640 Probing TPM: done!
9454 19:53:01.133453 Connected to device vid:did:rid of 1ae0:0028:00
9455 19:53:01.139901 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9456 19:53:01.143286 Initialized TPM device CR50 revision 0
9457 19:53:01.147409 Checking cr50 for pending updates
9458 19:53:01.152578 Reading cr50 TPM mode
9459 19:53:01.162152 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9460 19:53:01.168100 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9461 19:53:01.207862 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9462 19:53:01.212045 Checking segment from ROM address 0x40100000
9463 19:53:01.214971 Checking segment from ROM address 0x4010001c
9464 19:53:01.221516 Loading segment from ROM address 0x40100000
9465 19:53:01.222088 code (compression=0)
9466 19:53:01.230783 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9467 19:53:01.238000 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9468 19:53:01.238571 it's not compressed!
9469 19:53:01.244432 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9470 19:53:01.250598 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9471 19:53:01.268048 Loading segment from ROM address 0x4010001c
9472 19:53:01.268604 Entry Point 0x80000000
9473 19:53:01.271715 Loaded segments
9474 19:53:01.275112 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9475 19:53:01.281776 Jumping to boot code at 0x80000000(0xffe64000)
9476 19:53:01.288316 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9477 19:53:01.294622 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9478 19:53:01.303234 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9479 19:53:01.306111 Checking segment from ROM address 0x40100000
9480 19:53:01.310363 Checking segment from ROM address 0x4010001c
9481 19:53:01.315978 Loading segment from ROM address 0x40100000
9482 19:53:01.316517 code (compression=1)
9483 19:53:01.323026 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9484 19:53:01.332978 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9485 19:53:01.333537 using LZMA
9486 19:53:01.340811 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9487 19:53:01.348098 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9488 19:53:01.350825 Loading segment from ROM address 0x4010001c
9489 19:53:01.354176 Entry Point 0x54601000
9490 19:53:01.354746 Loaded segments
9491 19:53:01.357507 NOTICE: MT8192 bl31_setup
9492 19:53:01.364783 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9493 19:53:01.368431 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9494 19:53:01.371167 WARNING: region 0:
9495 19:53:01.375198 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 19:53:01.375811 WARNING: region 1:
9497 19:53:01.381432 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9498 19:53:01.384861 WARNING: region 2:
9499 19:53:01.388069 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9500 19:53:01.391289 WARNING: region 3:
9501 19:53:01.394592 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9502 19:53:01.398131 WARNING: region 4:
9503 19:53:01.404527 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9504 19:53:01.405081 WARNING: region 5:
9505 19:53:01.407718 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 19:53:01.410693 WARNING: region 6:
9507 19:53:01.414330 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 19:53:01.417437 WARNING: region 7:
9509 19:53:01.421011 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 19:53:01.427583 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9511 19:53:01.430973 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9512 19:53:01.437280 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9513 19:53:01.440995 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9514 19:53:01.444418 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9515 19:53:01.450696 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9516 19:53:01.454286 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9517 19:53:01.457400 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9518 19:53:01.464049 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9519 19:53:01.467046 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9520 19:53:01.473909 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9521 19:53:01.476845 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9522 19:53:01.480581 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9523 19:53:01.487181 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9524 19:53:01.490474 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9525 19:53:01.493774 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9526 19:53:01.500520 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9527 19:53:01.504014 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9528 19:53:01.510215 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9529 19:53:01.513783 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9530 19:53:01.517080 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9531 19:53:01.523849 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9532 19:53:01.527166 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9533 19:53:01.530141 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9534 19:53:01.537030 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9535 19:53:01.540696 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9536 19:53:01.547178 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9537 19:53:01.550890 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9538 19:53:01.553564 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9539 19:53:01.561151 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9540 19:53:01.563983 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9541 19:53:01.570693 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9542 19:53:01.573602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9543 19:53:01.577565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9544 19:53:01.579999 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9545 19:53:01.586859 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9546 19:53:01.590327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9547 19:53:01.593334 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9548 19:53:01.597124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9549 19:53:01.603425 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9550 19:53:01.606712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9551 19:53:01.610138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9552 19:53:01.613275 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9553 19:53:01.620325 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9554 19:53:01.623336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9555 19:53:01.627062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9556 19:53:01.630097 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9557 19:53:01.636526 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9558 19:53:01.639896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9559 19:53:01.646912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9560 19:53:01.650250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9561 19:53:01.653484 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9562 19:53:01.659907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9563 19:53:01.663296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9564 19:53:01.670285 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9565 19:53:01.673599 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9566 19:53:01.679904 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9567 19:53:01.683411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9568 19:53:01.686380 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9569 19:53:01.693125 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9570 19:53:01.696411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9571 19:53:01.703029 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9572 19:53:01.706577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9573 19:53:01.713020 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9574 19:53:01.716024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9575 19:53:01.723264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9576 19:53:01.726528 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9577 19:53:01.729779 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9578 19:53:01.736442 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9579 19:53:01.740131 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9580 19:53:01.746383 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9581 19:53:01.749391 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9582 19:53:01.756111 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9583 19:53:01.759880 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9584 19:53:01.763265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9585 19:53:01.769913 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9586 19:53:01.772445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9587 19:53:01.779655 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9588 19:53:01.782564 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9589 19:53:01.789805 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9590 19:53:01.792444 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9591 19:53:01.799525 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9592 19:53:01.802721 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9593 19:53:01.805653 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9594 19:53:01.812708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9595 19:53:01.815826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9596 19:53:01.822255 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9597 19:53:01.825671 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9598 19:53:01.832261 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9599 19:53:01.835791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9600 19:53:01.838849 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9601 19:53:01.845504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9602 19:53:01.849008 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9603 19:53:01.855875 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9604 19:53:01.858793 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9605 19:53:01.865635 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9606 19:53:01.868790 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9607 19:53:01.872685 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9608 19:53:01.875595 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9609 19:53:01.882071 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9610 19:53:01.885431 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9611 19:53:01.888415 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9612 19:53:01.895386 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9613 19:53:01.898585 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9614 19:53:01.905700 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9615 19:53:01.908971 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9616 19:53:01.912122 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9617 19:53:01.918654 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9618 19:53:01.922139 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9619 19:53:01.928850 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9620 19:53:01.932700 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9621 19:53:01.935248 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9622 19:53:01.941782 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9623 19:53:01.944908 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9624 19:53:01.951670 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9625 19:53:01.954996 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9626 19:53:01.958826 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9627 19:53:01.965011 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9628 19:53:01.968407 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9629 19:53:01.971712 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9630 19:53:01.975170 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9631 19:53:01.981661 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9632 19:53:01.985407 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9633 19:53:01.988319 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9634 19:53:01.994757 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9635 19:53:01.998189 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9636 19:53:02.001305 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9637 19:53:02.008029 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9638 19:53:02.011560 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9639 19:53:02.018659 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9640 19:53:02.021542 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9641 19:53:02.024983 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9642 19:53:02.031388 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9643 19:53:02.034439 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9644 19:53:02.041357 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9645 19:53:02.044710 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9646 19:53:02.048039 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9647 19:53:02.054218 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9648 19:53:02.058562 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9649 19:53:02.064681 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9650 19:53:02.067692 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9651 19:53:02.071053 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9652 19:53:02.077936 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9653 19:53:02.081263 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9654 19:53:02.084318 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9655 19:53:02.091072 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9656 19:53:02.094510 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9657 19:53:02.101063 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9658 19:53:02.104434 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9659 19:53:02.107840 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9660 19:53:02.114130 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9661 19:53:02.118055 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9662 19:53:02.124186 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9663 19:53:02.127778 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9664 19:53:02.131612 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9665 19:53:02.137625 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9666 19:53:02.140809 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9667 19:53:02.147925 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9668 19:53:02.150901 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9669 19:53:02.153952 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9670 19:53:02.160694 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9671 19:53:02.164352 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9672 19:53:02.170750 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9673 19:53:02.173784 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9674 19:53:02.177069 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9675 19:53:02.183437 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9676 19:53:02.186899 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9677 19:53:02.193563 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9678 19:53:02.196982 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9679 19:53:02.200117 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9680 19:53:02.206500 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9681 19:53:02.210282 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9682 19:53:02.216534 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9683 19:53:02.219773 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9684 19:53:02.222912 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9685 19:53:02.229686 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9686 19:53:02.232876 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9687 19:53:02.239469 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9688 19:53:02.242967 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9689 19:53:02.246256 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9690 19:53:02.253016 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9691 19:53:02.256029 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9692 19:53:02.262353 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9693 19:53:02.266144 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9694 19:53:02.269322 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9695 19:53:02.275626 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9696 19:53:02.279500 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9697 19:53:02.285678 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9698 19:53:02.289108 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9699 19:53:02.292590 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9700 19:53:02.299268 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9701 19:53:02.302290 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9702 19:53:02.309219 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9703 19:53:02.312159 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9704 19:53:02.318845 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9705 19:53:02.322248 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9706 19:53:02.325583 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9707 19:53:02.331777 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9708 19:53:02.335527 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9709 19:53:02.342613 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9710 19:53:02.345291 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9711 19:53:02.352364 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9712 19:53:02.355017 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9713 19:53:02.358094 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9714 19:53:02.365488 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9715 19:53:02.368657 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9716 19:53:02.375438 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9717 19:53:02.378393 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9718 19:53:02.381665 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9719 19:53:02.388266 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9720 19:53:02.391474 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9721 19:53:02.398220 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9722 19:53:02.401162 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9723 19:53:02.408333 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9724 19:53:02.411829 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9725 19:53:02.414268 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9726 19:53:02.420800 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9727 19:53:02.424310 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9728 19:53:02.430845 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9729 19:53:02.434637 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9730 19:53:02.440785 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9731 19:53:02.443875 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9732 19:53:02.447986 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9733 19:53:02.453907 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9734 19:53:02.457004 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9735 19:53:02.463903 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9736 19:53:02.467445 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9737 19:53:02.473769 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9738 19:53:02.477091 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9739 19:53:02.480073 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9740 19:53:02.486925 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9741 19:53:02.490396 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9742 19:53:02.493899 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9743 19:53:02.496624 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9744 19:53:02.503400 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9745 19:53:02.506832 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9746 19:53:02.509665 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9747 19:53:02.516718 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9748 19:53:02.519709 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9749 19:53:02.523273 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9750 19:53:02.529965 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9751 19:53:02.533073 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9752 19:53:02.539491 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9753 19:53:02.542883 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9754 19:53:02.546115 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9755 19:53:02.552712 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9756 19:53:02.555833 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9757 19:53:02.562375 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9758 19:53:02.566029 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9759 19:53:02.569309 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9760 19:53:02.575603 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9761 19:53:02.578889 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9762 19:53:02.585732 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9763 19:53:02.589118 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9764 19:53:02.592936 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9765 19:53:02.599402 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9766 19:53:02.602668 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9767 19:53:02.605720 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9768 19:53:02.612303 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9769 19:53:02.615563 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9770 19:53:02.618725 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9771 19:53:02.625618 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9772 19:53:02.628301 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9773 19:53:02.632075 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9774 19:53:02.638496 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9775 19:53:02.641863 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9776 19:53:02.648225 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9777 19:53:02.651502 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9778 19:53:02.654546 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9779 19:53:02.661273 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9780 19:53:02.664725 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9781 19:53:02.668247 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9782 19:53:02.671522 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9783 19:53:02.675153 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9784 19:53:02.682004 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9785 19:53:02.684720 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9786 19:53:02.688419 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9787 19:53:02.694710 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9788 19:53:02.697777 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9789 19:53:02.701062 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9790 19:53:02.704717 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9791 19:53:02.711150 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9792 19:53:02.714739 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9793 19:53:02.720993 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9794 19:53:02.724704 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9795 19:53:02.728042 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9796 19:53:02.734450 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9797 19:53:02.737593 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9798 19:53:02.744246 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9799 19:53:02.747824 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9800 19:53:02.750544 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9801 19:53:02.757287 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9802 19:53:02.760483 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9803 19:53:02.767261 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9804 19:53:02.770744 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9805 19:53:02.777058 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9806 19:53:02.780644 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9807 19:53:02.783818 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9808 19:53:02.790649 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9809 19:53:02.793670 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9810 19:53:02.800742 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9811 19:53:02.804391 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9812 19:53:02.806858 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9813 19:53:02.813971 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9814 19:53:02.816619 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9815 19:53:02.823246 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9816 19:53:02.826481 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9817 19:53:02.830213 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9818 19:53:02.836473 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9819 19:53:02.839682 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9820 19:53:02.846445 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9821 19:53:02.849843 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9822 19:53:02.856601 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9823 19:53:02.859777 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9824 19:53:02.862688 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9825 19:53:02.869954 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9826 19:53:02.872891 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9827 19:53:02.879453 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9828 19:53:02.883141 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9829 19:53:02.889414 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9830 19:53:02.892633 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9831 19:53:02.896287 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9832 19:53:02.903895 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9833 19:53:02.906007 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9834 19:53:02.912215 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9835 19:53:02.916091 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9836 19:53:02.919287 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9837 19:53:02.925495 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9838 19:53:02.928807 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9839 19:53:02.935409 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9840 19:53:02.938934 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9841 19:53:02.941762 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9842 19:53:02.948744 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9843 19:53:02.951707 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9844 19:53:02.958403 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9845 19:53:02.961788 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9846 19:53:02.968574 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9847 19:53:02.971462 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9848 19:53:02.974844 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9849 19:53:02.981535 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9850 19:53:02.985030 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9851 19:53:02.991155 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9852 19:53:02.994722 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9853 19:53:03.001892 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9854 19:53:03.004435 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9855 19:53:03.008242 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9856 19:53:03.014764 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9857 19:53:03.017668 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9858 19:53:03.024493 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9859 19:53:03.027912 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9860 19:53:03.034510 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9861 19:53:03.037961 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9862 19:53:03.040772 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9863 19:53:03.047674 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9864 19:53:03.051321 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9865 19:53:03.057465 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9866 19:53:03.061259 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9867 19:53:03.067130 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9868 19:53:03.070620 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9869 19:53:03.073917 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9870 19:53:03.080834 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9871 19:53:03.083976 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9872 19:53:03.089746 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9873 19:53:03.094306 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9874 19:53:03.099797 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9875 19:53:03.103656 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9876 19:53:03.109878 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9877 19:53:03.113410 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9878 19:53:03.116380 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9879 19:53:03.123143 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9880 19:53:03.126464 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9881 19:53:03.133381 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9882 19:53:03.136461 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9883 19:53:03.144198 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9884 19:53:03.146518 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9885 19:53:03.153189 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9886 19:53:03.156632 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9887 19:53:03.160041 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9888 19:53:03.166553 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9889 19:53:03.169891 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9890 19:53:03.176208 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9891 19:53:03.179386 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9892 19:53:03.186696 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9893 19:53:03.189874 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9894 19:53:03.192769 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9895 19:53:03.199488 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9896 19:53:03.202598 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9897 19:53:03.209225 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9898 19:53:03.212792 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9899 19:53:03.219463 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9900 19:53:03.222729 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9901 19:53:03.226239 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9902 19:53:03.232868 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9903 19:53:03.236039 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9904 19:53:03.243178 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9905 19:53:03.246209 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9906 19:53:03.252453 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9907 19:53:03.255845 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9908 19:53:03.259318 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9909 19:53:03.266068 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9910 19:53:03.269395 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9911 19:53:03.276027 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9912 19:53:03.279542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9913 19:53:03.282732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9914 19:53:03.289562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9915 19:53:03.292445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9916 19:53:03.299243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9917 19:53:03.302109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9918 19:53:03.308899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9919 19:53:03.312437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9920 19:53:03.318880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9921 19:53:03.321805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9922 19:53:03.328569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9923 19:53:03.332356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9924 19:53:03.338841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9925 19:53:03.341663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9926 19:53:03.348172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9927 19:53:03.351816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9928 19:53:03.358618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9929 19:53:03.362081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9930 19:53:03.369096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9931 19:53:03.371666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9932 19:53:03.378350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9933 19:53:03.382058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9934 19:53:03.388616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9935 19:53:03.392082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9936 19:53:03.398457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9937 19:53:03.401574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9938 19:53:03.408122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9939 19:53:03.411179 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9940 19:53:03.418686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9941 19:53:03.421075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9942 19:53:03.427934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9943 19:53:03.431081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9944 19:53:03.437707 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9945 19:53:03.438363 INFO: [APUAPC] vio 0
9946 19:53:03.444801 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9947 19:53:03.447971 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9948 19:53:03.451074 INFO: [APUAPC] D0_APC_0: 0x400510
9949 19:53:03.454219 INFO: [APUAPC] D0_APC_1: 0x0
9950 19:53:03.457688 INFO: [APUAPC] D0_APC_2: 0x1540
9951 19:53:03.461332 INFO: [APUAPC] D0_APC_3: 0x0
9952 19:53:03.464652 INFO: [APUAPC] D1_APC_0: 0xffffffff
9953 19:53:03.467751 INFO: [APUAPC] D1_APC_1: 0xffffffff
9954 19:53:03.471010 INFO: [APUAPC] D1_APC_2: 0x3fffff
9955 19:53:03.474183 INFO: [APUAPC] D1_APC_3: 0x0
9956 19:53:03.477443 INFO: [APUAPC] D2_APC_0: 0xffffffff
9957 19:53:03.480984 INFO: [APUAPC] D2_APC_1: 0xffffffff
9958 19:53:03.484687 INFO: [APUAPC] D2_APC_2: 0x3fffff
9959 19:53:03.487793 INFO: [APUAPC] D2_APC_3: 0x0
9960 19:53:03.491087 INFO: [APUAPC] D3_APC_0: 0xffffffff
9961 19:53:03.493964 INFO: [APUAPC] D3_APC_1: 0xffffffff
9962 19:53:03.497274 INFO: [APUAPC] D3_APC_2: 0x3fffff
9963 19:53:03.501185 INFO: [APUAPC] D3_APC_3: 0x0
9964 19:53:03.504176 INFO: [APUAPC] D4_APC_0: 0xffffffff
9965 19:53:03.507376 INFO: [APUAPC] D4_APC_1: 0xffffffff
9966 19:53:03.510541 INFO: [APUAPC] D4_APC_2: 0x3fffff
9967 19:53:03.513829 INFO: [APUAPC] D4_APC_3: 0x0
9968 19:53:03.517164 INFO: [APUAPC] D5_APC_0: 0xffffffff
9969 19:53:03.520267 INFO: [APUAPC] D5_APC_1: 0xffffffff
9970 19:53:03.523575 INFO: [APUAPC] D5_APC_2: 0x3fffff
9971 19:53:03.527002 INFO: [APUAPC] D5_APC_3: 0x0
9972 19:53:03.530089 INFO: [APUAPC] D6_APC_0: 0xffffffff
9973 19:53:03.533637 INFO: [APUAPC] D6_APC_1: 0xffffffff
9974 19:53:03.536885 INFO: [APUAPC] D6_APC_2: 0x3fffff
9975 19:53:03.537349 INFO: [APUAPC] D6_APC_3: 0x0
9976 19:53:03.540153 INFO: [APUAPC] D7_APC_0: 0xffffffff
9977 19:53:03.546868 INFO: [APUAPC] D7_APC_1: 0xffffffff
9978 19:53:03.549852 INFO: [APUAPC] D7_APC_2: 0x3fffff
9979 19:53:03.550346 INFO: [APUAPC] D7_APC_3: 0x0
9980 19:53:03.553330 INFO: [APUAPC] D8_APC_0: 0xffffffff
9981 19:53:03.559838 INFO: [APUAPC] D8_APC_1: 0xffffffff
9982 19:53:03.563320 INFO: [APUAPC] D8_APC_2: 0x3fffff
9983 19:53:03.563968 INFO: [APUAPC] D8_APC_3: 0x0
9984 19:53:03.566927 INFO: [APUAPC] D9_APC_0: 0xffffffff
9985 19:53:03.569980 INFO: [APUAPC] D9_APC_1: 0xffffffff
9986 19:53:03.572977 INFO: [APUAPC] D9_APC_2: 0x3fffff
9987 19:53:03.576497 INFO: [APUAPC] D9_APC_3: 0x0
9988 19:53:03.580171 INFO: [APUAPC] D10_APC_0: 0xffffffff
9989 19:53:03.582664 INFO: [APUAPC] D10_APC_1: 0xffffffff
9990 19:53:03.586072 INFO: [APUAPC] D10_APC_2: 0x3fffff
9991 19:53:03.590010 INFO: [APUAPC] D10_APC_3: 0x0
9992 19:53:03.592838 INFO: [APUAPC] D11_APC_0: 0xffffffff
9993 19:53:03.599652 INFO: [APUAPC] D11_APC_1: 0xffffffff
9994 19:53:03.603182 INFO: [APUAPC] D11_APC_2: 0x3fffff
9995 19:53:03.603788 INFO: [APUAPC] D11_APC_3: 0x0
9996 19:53:03.606512 INFO: [APUAPC] D12_APC_0: 0xffffffff
9997 19:53:03.612969 INFO: [APUAPC] D12_APC_1: 0xffffffff
9998 19:53:03.616273 INFO: [APUAPC] D12_APC_2: 0x3fffff
9999 19:53:03.616880 INFO: [APUAPC] D12_APC_3: 0x0
10000 19:53:03.622511 INFO: [APUAPC] D13_APC_0: 0xffffffff
10001 19:53:03.625810 INFO: [APUAPC] D13_APC_1: 0xffffffff
10002 19:53:03.629076 INFO: [APUAPC] D13_APC_2: 0x3fffff
10003 19:53:03.632430 INFO: [APUAPC] D13_APC_3: 0x0
10004 19:53:03.635622 INFO: [APUAPC] D14_APC_0: 0xffffffff
10005 19:53:03.638758 INFO: [APUAPC] D14_APC_1: 0xffffffff
10006 19:53:03.642726 INFO: [APUAPC] D14_APC_2: 0x3fffff
10007 19:53:03.645702 INFO: [APUAPC] D14_APC_3: 0x0
10008 19:53:03.649045 INFO: [APUAPC] D15_APC_0: 0xffffffff
10009 19:53:03.651868 INFO: [APUAPC] D15_APC_1: 0xffffffff
10010 19:53:03.655516 INFO: [APUAPC] D15_APC_2: 0x3fffff
10011 19:53:03.658762 INFO: [APUAPC] D15_APC_3: 0x0
10012 19:53:03.659221 INFO: [APUAPC] APC_CON: 0x4
10013 19:53:03.662362 INFO: [NOCDAPC] D0_APC_0: 0x0
10014 19:53:03.665198 INFO: [NOCDAPC] D0_APC_1: 0x0
10015 19:53:03.668606 INFO: [NOCDAPC] D1_APC_0: 0x0
10016 19:53:03.672151 INFO: [NOCDAPC] D1_APC_1: 0xfff
10017 19:53:03.675350 INFO: [NOCDAPC] D2_APC_0: 0x0
10018 19:53:03.678729 INFO: [NOCDAPC] D2_APC_1: 0xfff
10019 19:53:03.681888 INFO: [NOCDAPC] D3_APC_0: 0x0
10020 19:53:03.685545 INFO: [NOCDAPC] D3_APC_1: 0xfff
10021 19:53:03.688714 INFO: [NOCDAPC] D4_APC_0: 0x0
10022 19:53:03.692103 INFO: [NOCDAPC] D4_APC_1: 0xfff
10023 19:53:03.692666 INFO: [NOCDAPC] D5_APC_0: 0x0
10024 19:53:03.695230 INFO: [NOCDAPC] D5_APC_1: 0xfff
10025 19:53:03.698845 INFO: [NOCDAPC] D6_APC_0: 0x0
10026 19:53:03.702210 INFO: [NOCDAPC] D6_APC_1: 0xfff
10027 19:53:03.705204 INFO: [NOCDAPC] D7_APC_0: 0x0
10028 19:53:03.708347 INFO: [NOCDAPC] D7_APC_1: 0xfff
10029 19:53:03.711801 INFO: [NOCDAPC] D8_APC_0: 0x0
10030 19:53:03.715544 INFO: [NOCDAPC] D8_APC_1: 0xfff
10031 19:53:03.717976 INFO: [NOCDAPC] D9_APC_0: 0x0
10032 19:53:03.721888 INFO: [NOCDAPC] D9_APC_1: 0xfff
10033 19:53:03.724793 INFO: [NOCDAPC] D10_APC_0: 0x0
10034 19:53:03.728268 INFO: [NOCDAPC] D10_APC_1: 0xfff
10035 19:53:03.728728 INFO: [NOCDAPC] D11_APC_0: 0x0
10036 19:53:03.731609 INFO: [NOCDAPC] D11_APC_1: 0xfff
10037 19:53:03.734913 INFO: [NOCDAPC] D12_APC_0: 0x0
10038 19:53:03.738768 INFO: [NOCDAPC] D12_APC_1: 0xfff
10039 19:53:03.741896 INFO: [NOCDAPC] D13_APC_0: 0x0
10040 19:53:03.744441 INFO: [NOCDAPC] D13_APC_1: 0xfff
10041 19:53:03.748159 INFO: [NOCDAPC] D14_APC_0: 0x0
10042 19:53:03.751014 INFO: [NOCDAPC] D14_APC_1: 0xfff
10043 19:53:03.754799 INFO: [NOCDAPC] D15_APC_0: 0x0
10044 19:53:03.758034 INFO: [NOCDAPC] D15_APC_1: 0xfff
10045 19:53:03.761061 INFO: [NOCDAPC] APC_CON: 0x4
10046 19:53:03.764462 INFO: [APUAPC] set_apusys_apc done
10047 19:53:03.767586 INFO: [DEVAPC] devapc_init done
10048 19:53:03.771423 INFO: GICv3 without legacy support detected.
10049 19:53:03.774611 INFO: ARM GICv3 driver initialized in EL3
10050 19:53:03.778138 INFO: Maximum SPI INTID supported: 639
10051 19:53:03.784419 INFO: BL31: Initializing runtime services
10052 19:53:03.787613 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10053 19:53:03.791064 INFO: SPM: enable CPC mode
10054 19:53:03.797507 INFO: mcdi ready for mcusys-off-idle and system suspend
10055 19:53:03.800741 INFO: BL31: Preparing for EL3 exit to normal world
10056 19:53:03.803920 INFO: Entry point address = 0x80000000
10057 19:53:03.807769 INFO: SPSR = 0x8
10058 19:53:03.813023
10059 19:53:03.813576
10060 19:53:03.813944
10061 19:53:03.816062 Starting depthcharge on Spherion...
10062 19:53:03.816623
10063 19:53:03.816993 Wipe memory regions:
10064 19:53:03.817330
10065 19:53:03.820082 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10066 19:53:03.820710 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10067 19:53:03.821163 Setting prompt string to ['asurada:']
10068 19:53:03.821593 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10069 19:53:03.822313 [0x00000040000000, 0x00000054600000)
10070 19:53:03.941531
10071 19:53:03.942087 [0x00000054660000, 0x00000080000000)
10072 19:53:04.202264
10073 19:53:04.202826 [0x000000821a7280, 0x000000ffe64000)
10074 19:53:04.947290
10075 19:53:04.947891 [0x00000100000000, 0x00000240000000)
10076 19:53:06.838908
10077 19:53:06.840663 Initializing XHCI USB controller at 0x11200000.
10078 19:53:07.822560
10079 19:53:07.823116 R8152: Initializing
10080 19:53:07.823486
10081 19:53:07.826204 Version 9 (ocp_data = 6010)
10082 19:53:07.826763
10083 19:53:07.829261 R8152: Done initializing
10084 19:53:07.829817
10085 19:53:07.830185 Adding net device
10086 19:53:08.351499
10087 19:53:08.353966 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10088 19:53:08.354434
10089 19:53:08.354803
10090 19:53:08.355147
10091 19:53:08.355975 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10093 19:53:08.457267 asurada: tftpboot 192.168.201.1 11899576/tftp-deploy-nqnatrmr/kernel/image.itb 11899576/tftp-deploy-nqnatrmr/kernel/cmdline
10094 19:53:08.458071 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10095 19:53:08.458600 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10096 19:53:08.462508 tftpboot 192.168.201.1 11899576/tftp-deploy-nqnatrmr/kernel/image.itp-deploy-nqnatrmr/kernel/cmdline
10097 19:53:08.462591
10098 19:53:08.462656 Waiting for link
10099 19:53:08.665510
10100 19:53:08.666173 done.
10101 19:53:08.666619
10102 19:53:08.666974 MAC: f4:f5:e8:50:de:0a
10103 19:53:08.667306
10104 19:53:08.668693 Sending DHCP discover... done.
10105 19:53:08.669171
10106 19:53:08.671444 Waiting for reply... done.
10107 19:53:08.671964
10108 19:53:08.674937 Sending DHCP request... done.
10109 19:53:08.675415
10110 19:53:08.680925 Waiting for reply... done.
10111 19:53:08.681482
10112 19:53:08.681859 My ip is 192.168.201.14
10113 19:53:08.682205
10114 19:53:08.683561 The DHCP server ip is 192.168.201.1
10115 19:53:08.684091
10116 19:53:08.690804 TFTP server IP predefined by user: 192.168.201.1
10117 19:53:08.691362
10118 19:53:08.696724 Bootfile predefined by user: 11899576/tftp-deploy-nqnatrmr/kernel/image.itb
10119 19:53:08.697289
10120 19:53:08.700157 Sending tftp read request... done.
10121 19:53:08.700623
10122 19:53:08.706892 Waiting for the transfer...
10123 19:53:08.707356
10124 19:53:08.964692 00000000 ################################################################
10125 19:53:08.964870
10126 19:53:09.209383 00080000 ################################################################
10127 19:53:09.209550
10128 19:53:09.456811 00100000 ################################################################
10129 19:53:09.456953
10130 19:53:09.712712 00180000 ################################################################
10131 19:53:09.712858
10132 19:53:09.952699 00200000 ################################################################
10133 19:53:09.952836
10134 19:53:10.181437 00280000 ################################################################
10135 19:53:10.181573
10136 19:53:10.441054 00300000 ################################################################
10137 19:53:10.441190
10138 19:53:10.688721 00380000 ################################################################
10139 19:53:10.688866
10140 19:53:10.941769 00400000 ################################################################
10141 19:53:10.941910
10142 19:53:11.206524 00480000 ################################################################
10143 19:53:11.206665
10144 19:53:11.477505 00500000 ################################################################
10145 19:53:11.477650
10146 19:53:11.721084 00580000 ################################################################
10147 19:53:11.721230
10148 19:53:11.971542 00600000 ################################################################
10149 19:53:11.971713
10150 19:53:12.232752 00680000 ################################################################
10151 19:53:12.232882
10152 19:53:12.464165 00700000 ################################################################
10153 19:53:12.464300
10154 19:53:12.700778 00780000 ################################################################
10155 19:53:12.700915
10156 19:53:12.939522 00800000 ################################################################
10157 19:53:12.939669
10158 19:53:13.189845 00880000 ################################################################
10159 19:53:13.189984
10160 19:53:13.439693 00900000 ################################################################
10161 19:53:13.439839
10162 19:53:13.679570 00980000 ################################################################
10163 19:53:13.679776
10164 19:53:13.936967 00a00000 ################################################################
10165 19:53:13.937139
10166 19:53:14.201193 00a80000 ################################################################
10167 19:53:14.201334
10168 19:53:14.457486 00b00000 ################################################################
10169 19:53:14.457620
10170 19:53:14.694996 00b80000 ################################################################
10171 19:53:14.695127
10172 19:53:14.942332 00c00000 ################################################################
10173 19:53:14.942494
10174 19:53:15.180894 00c80000 ################################################################
10175 19:53:15.181036
10176 19:53:15.419514 00d00000 ################################################################
10177 19:53:15.419647
10178 19:53:15.669489 00d80000 ################################################################
10179 19:53:15.669632
10180 19:53:15.918986 00e00000 ################################################################
10181 19:53:15.919115
10182 19:53:16.156108 00e80000 ################################################################
10183 19:53:16.156244
10184 19:53:16.408398 00f00000 ################################################################
10185 19:53:16.408535
10186 19:53:16.640491 00f80000 ################################################################
10187 19:53:16.640625
10188 19:53:16.892419 01000000 ################################################################
10189 19:53:16.892549
10190 19:53:17.161978 01080000 ################################################################
10191 19:53:17.162124
10192 19:53:17.423941 01100000 ################################################################
10193 19:53:17.424088
10194 19:53:17.686209 01180000 ################################################################
10195 19:53:17.686351
10196 19:53:17.955345 01200000 ################################################################
10197 19:53:17.955483
10198 19:53:18.227759 01280000 ################################################################
10199 19:53:18.227897
10200 19:53:18.493835 01300000 ################################################################
10201 19:53:18.493991
10202 19:53:18.738145 01380000 ################################################################
10203 19:53:18.738287
10204 19:53:18.996333 01400000 ################################################################
10205 19:53:18.996473
10206 19:53:19.268828 01480000 ################################################################
10207 19:53:19.268966
10208 19:53:19.515827 01500000 ################################################################
10209 19:53:19.515974
10210 19:53:19.784709 01580000 ################################################################
10211 19:53:19.784856
10212 19:53:20.037853 01600000 ################################################################
10213 19:53:20.037991
10214 19:53:20.278697 01680000 ################################################################
10215 19:53:20.278836
10216 19:53:20.535006 01700000 ################################################################
10217 19:53:20.535150
10218 19:53:20.781133 01780000 ################################################################
10219 19:53:20.781274
10220 19:53:21.034065 01800000 ################################################################
10221 19:53:21.034202
10222 19:53:21.292052 01880000 ################################################################
10223 19:53:21.292189
10224 19:53:21.556222 01900000 ################################################################
10225 19:53:21.556362
10226 19:53:21.824063 01980000 ################################################################
10227 19:53:21.824209
10228 19:53:22.095954 01a00000 ################################################################
10229 19:53:22.096093
10230 19:53:22.364993 01a80000 ################################################################
10231 19:53:22.365158
10232 19:53:22.608203 01b00000 ################################################################
10233 19:53:22.608359
10234 19:53:22.853704 01b80000 ################################################################
10235 19:53:22.853844
10236 19:53:23.106969 01c00000 ################################################################
10237 19:53:23.107101
10238 19:53:23.361420 01c80000 ################################################################
10239 19:53:23.361560
10240 19:53:23.633302 01d00000 ################################################################
10241 19:53:23.633444
10242 19:53:23.900254 01d80000 ################################################################
10243 19:53:23.900392
10244 19:53:24.140539 01e00000 ################################################################
10245 19:53:24.140682
10246 19:53:24.405758 01e80000 ################################################################
10247 19:53:24.405900
10248 19:53:24.676507 01f00000 ################################################################
10249 19:53:24.676646
10250 19:53:24.918777 01f80000 ################################################################
10251 19:53:24.918921
10252 19:53:25.145773 02000000 ################################################################
10253 19:53:25.145910
10254 19:53:25.395481 02080000 ################################################################
10255 19:53:25.395616
10256 19:53:25.651726 02100000 ################################################################
10257 19:53:25.651898
10258 19:53:25.903770 02180000 ################################################################
10259 19:53:25.903924
10260 19:53:26.143293 02200000 ################################################################
10261 19:53:26.143431
10262 19:53:26.394964 02280000 ################################################################
10263 19:53:26.395106
10264 19:53:26.664395 02300000 ################################################################
10265 19:53:26.664535
10266 19:53:26.925876 02380000 ################################################################
10267 19:53:26.926013
10268 19:53:27.165880 02400000 ################################################################
10269 19:53:27.166026
10270 19:53:27.403428 02480000 ################################################################
10271 19:53:27.403556
10272 19:53:27.646431 02500000 ################################################################
10273 19:53:27.646594
10274 19:53:27.900803 02580000 ################################################################
10275 19:53:27.900941
10276 19:53:28.152224 02600000 ################################################################
10277 19:53:28.152366
10278 19:53:28.413162 02680000 ################################################################
10279 19:53:28.413306
10280 19:53:28.640478 02700000 ################################################################
10281 19:53:28.640617
10282 19:53:28.875130 02780000 ################################################################
10283 19:53:28.875266
10284 19:53:29.109206 02800000 ################################################################
10285 19:53:29.109339
10286 19:53:29.349623 02880000 ################################################################
10287 19:53:29.349767
10288 19:53:29.588165 02900000 ################################################################
10289 19:53:29.588301
10290 19:53:29.840938 02980000 ################################################################
10291 19:53:29.841075
10292 19:53:30.100566 02a00000 ################################################################
10293 19:53:30.100704
10294 19:53:30.349118 02a80000 ################################################################
10295 19:53:30.349258
10296 19:53:30.610702 02b00000 ################################################################
10297 19:53:30.610847
10298 19:53:30.868079 02b80000 ################################################################
10299 19:53:30.868218
10300 19:53:31.106064 02c00000 ################################################################
10301 19:53:31.106201
10302 19:53:31.372949 02c80000 ################################################################
10303 19:53:31.373115
10304 19:53:31.644818 02d00000 ################################################################
10305 19:53:31.644961
10306 19:53:31.890946 02d80000 ################################################################
10307 19:53:31.891115
10308 19:53:32.133754 02e00000 ################################################################
10309 19:53:32.133918
10310 19:53:32.371105 02e80000 ################################################################
10311 19:53:32.371263
10312 19:53:32.606738 02f00000 ################################################################
10313 19:53:32.606882
10314 19:53:32.840814 02f80000 ################################################################
10315 19:53:32.840956
10316 19:53:32.909779 03000000 ################# done.
10317 19:53:32.909884
10318 19:53:32.912859 The bootfile was 50464474 bytes long.
10319 19:53:32.912947
10320 19:53:32.916543 Sending tftp read request... done.
10321 19:53:32.916713
10322 19:53:32.919762 Waiting for the transfer...
10323 19:53:32.919880
10324 19:53:32.919968 00000000 # done.
10325 19:53:32.920046
10326 19:53:32.929820 Command line loaded dynamically from TFTP file: 11899576/tftp-deploy-nqnatrmr/kernel/cmdline
10327 19:53:32.930029
10328 19:53:32.942747 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10329 19:53:32.942989
10330 19:53:32.943167 Loading FIT.
10331 19:53:32.943326
10332 19:53:32.946573 Image ramdisk-1 has 39367638 bytes.
10333 19:53:32.946831
10334 19:53:32.949252 Image fdt-1 has 47278 bytes.
10335 19:53:32.949434
10336 19:53:32.952877 Image kernel-1 has 11047522 bytes.
10337 19:53:32.953169
10338 19:53:32.960180 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10339 19:53:32.960581
10340 19:53:32.979664 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10341 19:53:32.980298
10342 19:53:32.982670 Choosing best match conf-1 for compat google,spherion-rev2.
10343 19:53:32.988215
10344 19:53:32.992359 Connected to device vid:did:rid of 1ae0:0028:00
10345 19:53:33.000085
10346 19:53:33.002953 tpm_get_response: command 0x17b, return code 0x0
10347 19:53:33.003430
10348 19:53:33.006357 ec_init: CrosEC protocol v3 supported (256, 248)
10349 19:53:33.010889
10350 19:53:33.013534 tpm_cleanup: add release locality here.
10351 19:53:33.014015
10352 19:53:33.014500 Shutting down all USB controllers.
10353 19:53:33.017379
10354 19:53:33.017853 Removing current net device
10355 19:53:33.018336
10356 19:53:33.023554 Exiting depthcharge with code 4 at timestamp: 58608643
10357 19:53:33.024080
10358 19:53:33.026898 LZMA decompressing kernel-1 to 0x821a6718
10359 19:53:33.027377
10360 19:53:33.029998 LZMA decompressing kernel-1 to 0x40000000
10361 19:53:34.418786
10362 19:53:34.419351 jumping to kernel
10363 19:53:34.421557 end: 2.2.4 bootloader-commands (duration 00:00:31) [common]
10364 19:53:34.422171 start: 2.2.5 auto-login-action (timeout 00:03:55) [common]
10365 19:53:34.422639 Setting prompt string to ['Linux version [0-9]']
10366 19:53:34.423128 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10367 19:53:34.423604 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10368 19:53:34.500864
10369 19:53:34.503935 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10370 19:53:34.508002 start: 2.2.5.1 login-action (timeout 00:03:54) [common]
10371 19:53:34.508610 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10372 19:53:34.509110 Setting prompt string to []
10373 19:53:34.509678 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10374 19:53:34.510161 Using line separator: #'\n'#
10375 19:53:34.510589 No login prompt set.
10376 19:53:34.511075 Parsing kernel messages
10377 19:53:34.511485 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10378 19:53:34.512510 [login-action] Waiting for messages, (timeout 00:03:54)
10379 19:53:34.526992 [ 0.000000] Linux version 6.1.59-cip8-rt4 (KernelCI@build-j84202-arm64-gcc-10-defconfig-arm64-chromebook-st8dj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023
10380 19:53:34.530236 [ 0.000000] random: crng init done
10381 19:53:34.537028 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10382 19:53:34.540589 [ 0.000000] efi: UEFI not found.
10383 19:53:34.546453 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10384 19:53:34.556490 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10385 19:53:34.566645 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10386 19:53:34.572912 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10387 19:53:34.579431 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10388 19:53:34.586100 [ 0.000000] printk: bootconsole [mtk8250] enabled
10389 19:53:34.592815 [ 0.000000] NUMA: No NUMA configuration found
10390 19:53:34.599409 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10391 19:53:34.606383 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10392 19:53:34.606970 [ 0.000000] Zone ranges:
10393 19:53:34.612354 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10394 19:53:34.615712 [ 0.000000] DMA32 empty
10395 19:53:34.622315 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10396 19:53:34.625940 [ 0.000000] Movable zone start for each node
10397 19:53:34.629191 [ 0.000000] Early memory node ranges
10398 19:53:34.635370 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10399 19:53:34.642813 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10400 19:53:34.648676 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10401 19:53:34.655343 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10402 19:53:34.662442 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10403 19:53:34.668698 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10404 19:53:34.725183 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10405 19:53:34.731982 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10406 19:53:34.738724 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10407 19:53:34.741950 [ 0.000000] psci: probing for conduit method from DT.
10408 19:53:34.748367 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10409 19:53:34.751593 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10410 19:53:34.757936 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10411 19:53:34.761869 [ 0.000000] psci: SMC Calling Convention v1.2
10412 19:53:34.768080 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10413 19:53:34.771709 [ 0.000000] Detected VIPT I-cache on CPU0
10414 19:53:34.777866 [ 0.000000] CPU features: detected: GIC system register CPU interface
10415 19:53:34.784732 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10416 19:53:34.791687 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10417 19:53:34.797572 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10418 19:53:34.807946 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10419 19:53:34.813998 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10420 19:53:34.817640 [ 0.000000] alternatives: applying boot alternatives
10421 19:53:34.824534 [ 0.000000] Fallback order for Node 0: 0
10422 19:53:34.831461 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10423 19:53:34.834518 [ 0.000000] Policy zone: Normal
10424 19:53:34.847410 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10425 19:53:34.857424 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10426 19:53:34.868842 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10427 19:53:34.878332 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10428 19:53:34.884618 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10429 19:53:34.888043 <6>[ 0.000000] software IO TLB: area num 8.
10430 19:53:34.945141 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10431 19:53:35.094770 <6>[ 0.000000] Memory: 7930980K/8385536K available (17984K kernel code, 4116K rwdata, 17476K rodata, 8448K init, 615K bss, 421788K reserved, 32768K cma-reserved)
10432 19:53:35.101153 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10433 19:53:35.107597 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10434 19:53:35.110555 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10435 19:53:35.117500 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10436 19:53:35.124687 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10437 19:53:35.127148 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10438 19:53:35.137703 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10439 19:53:35.144473 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10440 19:53:35.150976 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10441 19:53:35.157173 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10442 19:53:35.160456 <6>[ 0.000000] GICv3: 608 SPIs implemented
10443 19:53:35.163702 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10444 19:53:35.170697 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10445 19:53:35.173765 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10446 19:53:35.180655 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10447 19:53:35.193559 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10448 19:53:35.206892 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10449 19:53:35.212979 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10450 19:53:35.220760 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10451 19:53:35.233945 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10452 19:53:35.240594 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10453 19:53:35.247653 <6>[ 0.009234] Console: colour dummy device 80x25
10454 19:53:35.257901 <6>[ 0.013957] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10455 19:53:35.264228 <6>[ 0.024400] pid_max: default: 32768 minimum: 301
10456 19:53:35.267344 <6>[ 0.029271] LSM: Security Framework initializing
10457 19:53:35.273666 <6>[ 0.034238] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10458 19:53:35.284005 <6>[ 0.042099] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10459 19:53:35.294028 <6>[ 0.051521] cblist_init_generic: Setting adjustable number of callback queues.
10460 19:53:35.300429 <6>[ 0.059011] cblist_init_generic: Setting shift to 3 and lim to 1.
10461 19:53:35.306598 <6>[ 0.065348] cblist_init_generic: Setting adjustable number of callback queues.
10462 19:53:35.313406 <6>[ 0.072776] cblist_init_generic: Setting shift to 3 and lim to 1.
10463 19:53:35.316506 <6>[ 0.079216] rcu: Hierarchical SRCU implementation.
10464 19:53:35.323015 <6>[ 0.079218] rcu: Max phase no-delay instances is 1000.
10465 19:53:35.329649 <6>[ 0.079242] printk: bootconsole [mtk8250] printing thread started
10466 19:53:35.336425 <6>[ 0.097574] EFI services will not be available.
10467 19:53:35.339334 <6>[ 0.097775] smp: Bringing up secondary CPUs ...
10468 19:53:35.345911 <6>[ 0.098088] Detected VIPT I-cache on CPU1
10469 19:53:35.352624 <6>[ 0.098157] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10470 19:53:35.359759 <6>[ 0.098188] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10471 19:53:35.369627 <6>[ 0.126019] Detected VIPT I-cache on CPU2
10472 19:53:35.376069 <6>[ 0.126071] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10473 19:53:35.385835 <6>[ 0.126089] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10474 19:53:35.388553 <6>[ 0.126347] Detected VIPT I-cache on CPU3
10475 19:53:35.395554 <6>[ 0.126393] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10476 19:53:35.402046 <6>[ 0.126406] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10477 19:53:35.408883 <6>[ 0.126718] CPU features: detected: Spectre-v4
10478 19:53:35.412089 <6>[ 0.126725] CPU features: detected: Spectre-BHB
10479 19:53:35.415884 <6>[ 0.126730] Detected PIPT I-cache on CPU4
10480 19:53:35.422247 <6>[ 0.126789] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10481 19:53:35.428581 <6>[ 0.126805] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10482 19:53:35.435664 <6>[ 0.127098] Detected PIPT I-cache on CPU5
10483 19:53:35.441797 <6>[ 0.127158] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10484 19:53:35.448463 <6>[ 0.127175] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10485 19:53:35.451958 <6>[ 0.127450] Detected PIPT I-cache on CPU6
10486 19:53:35.461952 <6>[ 0.127516] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10487 19:53:35.468515 <6>[ 0.127532] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10488 19:53:35.471974 <6>[ 0.127819] Detected PIPT I-cache on CPU7
10489 19:53:35.478833 <6>[ 0.127877] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10490 19:53:35.485145 <6>[ 0.127893] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10491 19:53:35.488339 <6>[ 0.127940] smp: Brought up 1 node, 8 CPUs
10492 19:53:35.494545 <6>[ 0.127944] SMP: Total of 8 processors activated.
10493 19:53:35.501013 <6>[ 0.127947] CPU features: detected: 32-bit EL0 Support
10494 19:53:35.507942 <6>[ 0.127949] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10495 19:53:35.514714 <6>[ 0.127951] CPU features: detected: Common not Private translations
10496 19:53:35.521425 <6>[ 0.127953] CPU features: detected: CRC32 instructions
10497 19:53:35.527613 <6>[ 0.127956] CPU features: detected: RCpc load-acquire (LDAPR)
10498 19:53:35.530918 <6>[ 0.127957] CPU features: detected: LSE atomic instructions
10499 19:53:35.537600 <6>[ 0.127959] CPU features: detected: Privileged Access Never
10500 19:53:35.543998 <6>[ 0.127960] CPU features: detected: RAS Extension Support
10501 19:53:35.551078 <6>[ 0.127963] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10502 19:53:35.553975 <6>[ 0.128020] CPU: All CPU(s) started at EL2
10503 19:53:35.561282 <6>[ 0.128022] alternatives: applying system-wide alternatives
10504 19:53:35.586442 �n��<6>[ 0.348054]< printk: console [ttyS0] printing thread started
10505 19:53:35.593107 6<6>[ 0.348080] printk: console [ttyS0] enabled
10506 19:53:35.599155 >[ 0.225578] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10507 19:53:35.607480 <6>[ 0.348084] printk: bootconsole [mtk8250] disabled
10508 19:53:35.614810 <6>[ 0.365466] printk: bootconsole [mtk8250] printing thread stopped
10509 19:53:35.617658 <6>[ 0.366775] SuperH (H)SCI(F) driver initialized
10510 19:53:35.624465 <6>[ 0.367261] msm_serial: driver initialized
10511 19:53:35.631093 <6>[ 0.371918] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10512 19:53:35.640824 <6>[ 0.371947] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10513 19:53:35.647060 <6>[ 0.371976] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10514 19:53:35.656884 <6>[ 0.372005] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10515 19:53:35.674832 <6>[ 0.372026] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10516 19:53:35.676068 <6>[ 0.372053] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10517 19:53:35.696116 <6>[ 0.372083] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10518 19:53:35.696615 <6>[ 0.372196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10519 19:53:35.703493 <6>[ 0.372225] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10520 19:53:35.710578 <6>[ 0.384494] loop: module loaded
10521 19:53:35.713841 <6>[ 0.387137] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10522 19:53:35.718247 <4>[ 0.403886] mtk-pmic-keys: Failed to locate of_node [id: -1]
10523 19:53:35.721697 <6>[ 0.404698] megasas: 07.719.03.00-rc1
10524 19:53:35.728375 <6>[ 0.416807] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10525 19:53:35.731862 <6>[ 0.416967] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10526 19:53:35.737975 <6>[ 0.428479] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10527 19:53:35.748380 <6>[ 0.486450] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10528 19:53:37.047638 <6>[ 1.806973] Freeing initrd memory: 38444K
10529 19:53:37.054398 <6>[ 1.813133] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10530 19:53:37.057313 <6>[ 1.817865] tun: Universal TUN/TAP device driver, 1.6
10531 19:53:37.060458 <6>[ 1.818618] thunder_xcv, ver 1.0
10532 19:53:37.064289 <6>[ 1.818637] thunder_bgx, ver 1.0
10533 19:53:37.067317 <6>[ 1.818651] nicpf, ver 1.0
10534 19:53:37.077190 <6>[ 1.819700] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10535 19:53:37.080655 <6>[ 1.819703] hns3: Copyright (c) 2017 Huawei Corporation.
10536 19:53:37.083856 <6>[ 1.819728] hclge is initializing
10537 19:53:37.090558 <6>[ 1.819742] e1000: Intel(R) PRO/1000 Network Driver
10538 19:53:37.097975 <6>[ 1.819744] e1000: Copyright (c) 1999-2006 Intel Corporation.
10539 19:53:37.101397 <6>[ 1.819760] e1000e: Intel(R) PRO/1000 Network Driver
10540 19:53:37.108626 <6>[ 1.819761] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10541 19:53:37.111600 <6>[ 1.819779] igb: Intel(R) Gigabit Ethernet Network Driver
10542 19:53:37.119212 <6>[ 1.819783] igb: Copyright (c) 2007-2014 Intel Corporation.
10543 19:53:37.125302 <6>[ 1.819796] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10544 19:53:37.131352 <6>[ 1.819798] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10545 19:53:37.134622 <6>[ 1.820090] sky2: driver version 1.30
10546 19:53:37.141273 <6>[ 1.821155] VFIO - User Level meta-driver version: 0.3
10547 19:53:37.148133 <6>[ 1.824015] usbcore: registered new interface driver usb-storage
10548 19:53:37.155901 <6>[ 1.824192] usbcore: registered new device driver onboard-usb-hub
10549 19:53:37.158072 <6>[ 1.826957] mt6397-rtc mt6359-rtc: registered as rtc0
10550 19:53:37.167774 <6>[ 1.827108] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-28T19:53:37 UTC (1698522817)
10551 19:53:37.171156 <6>[ 1.827720] i2c_dev: i2c /dev entries driver
10552 19:53:37.180863 <6>[ 1.834880] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10553 19:53:37.184729 <6>[ 1.849863] cpu cpu0: EM: created perf domain
10554 19:53:37.191765 <6>[ 1.850184] cpu cpu4: EM: created perf domain
10555 19:53:37.194374 <6>[ 1.851958] sdhci: Secure Digital Host Controller Interface driver
10556 19:53:37.200992 <6>[ 1.851959] sdhci: Copyright(c) Pierre Ossman
10557 19:53:37.207268 <6>[ 1.852322] Synopsys Designware Multimedia Card Interface Driver
10558 19:53:37.214003 <6>[ 1.852707] sdhci-pltfm: SDHCI platform and OF driver helper
10559 19:53:37.217140 <6>[ 1.856933] ledtrig-cpu: registered to indicate activity on CPUs
10560 19:53:37.223671 <6>[ 1.857533] mmc0: CQHCI version 5.10
10561 19:53:37.230542 <6>[ 1.857596] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10562 19:53:37.233553 <6>[ 1.857919] usbcore: registered new interface driver usbhid
10563 19:53:37.240337 <6>[ 1.857920] usbhid: USB HID core driver
10564 19:53:37.246957 <6>[ 1.858079] spi_master spi0: will run message pump with realtime priority
10565 19:53:37.260666 <6>[ 1.890012] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10566 19:53:37.273809 <6>[ 1.892183] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10567 19:53:37.276527 <6>[ 1.893037] cros-ec-spi spi0.0: Chrome EC device registered
10568 19:53:37.287041 <6>[ 1.904311] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10569 19:53:37.293583 <6>[ 1.905239] NET: Registered PF_PACKET protocol family
10570 19:53:37.296534 <6>[ 1.905309] 9pnet: Installing 9P2000 support
10571 19:53:37.303242 <5>[ 1.905341] Key type dns_resolver registered
10572 19:53:37.306894 <6>[ 1.905821] registered taskstats version 1
10573 19:53:37.309591 <5>[ 1.905836] Loading compiled-in X.509 certificates
10574 19:53:37.323041 <4>[ 1.920311] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10575 19:53:37.332572 <4>[ 1.920706] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10576 19:53:37.339186 <3>[ 1.920734] debugfs: File 'uA_load' in directory '/' already present!
10577 19:53:37.346072 <3>[ 1.920746] debugfs: File 'min_uV' in directory '/' already present!
10578 19:53:37.352509 <3>[ 1.920753] debugfs: File 'max_uV' in directory '/' already present!
10579 19:53:37.359155 <3>[ 1.920760] debugfs: File 'constraint_flags' in directory '/' already present!
10580 19:53:37.369842 <3>[ 1.922438] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10581 19:53:37.375835 <6>[ 1.925897] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10582 19:53:37.378983 <6>[ 1.926430] xhci-mtk 11200000.usb: xHCI Host Controller
10583 19:53:37.388906 <6>[ 1.926449] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10584 19:53:37.395975 <6>[ 1.926664] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10585 19:53:37.402227 <6>[ 1.926718] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10586 19:53:37.408625 <6>[ 1.926797] xhci-mtk 11200000.usb: xHCI Host Controller
10587 19:53:37.415455 <6>[ 1.926802] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10588 19:53:37.422371 <6>[ 1.926808] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10589 19:53:37.429119 <6>[ 1.927358] hub 1-0:1.0: USB hub found
10590 19:53:37.432258 <6>[ 1.927373] hub 1-0:1.0: 1 port detected
10591 19:53:37.438702 <6>[ 1.927507] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10592 19:53:37.444900 <6>[ 1.927660] hub 2-0:1.0: USB hub found
10593 19:53:37.448421 <6>[ 1.927670] hub 2-0:1.0: 1 port detected
10594 19:53:37.451639 <6>[ 1.930676] mtk-msdc 11f70000.mmc: Got CD GPIO
10595 19:53:37.461952 <6>[ 1.941653] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10596 19:53:37.468245 <6>[ 1.941663] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10597 19:53:37.478422 <4>[ 1.941738] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10598 19:53:37.485025 <6>[ 1.942229] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10599 19:53:37.495099 <6>[ 1.942231] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10600 19:53:37.501177 <6>[ 1.942390] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10601 19:53:37.507640 <6>[ 1.942402] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10602 19:53:37.517958 <6>[ 1.942405] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10603 19:53:37.524759 <6>[ 1.942408] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10604 19:53:37.534466 <6>[ 1.943572] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10605 19:53:37.544123 <6>[ 1.943587] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10606 19:53:37.551095 <6>[ 1.943590] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10607 19:53:37.560380 <6>[ 1.943593] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10608 19:53:37.567251 <6>[ 1.943597] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10609 19:53:37.577391 <6>[ 1.943600] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10610 19:53:37.584064 <6>[ 1.943603] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10611 19:53:37.594169 <6>[ 1.943607] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10612 19:53:37.600449 <6>[ 1.943610] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10613 19:53:37.610252 <6>[ 1.943613] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10614 19:53:37.616843 <6>[ 1.943616] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10615 19:53:37.626934 <6>[ 1.943620] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10616 19:53:37.634046 <6>[ 1.943623] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10617 19:53:37.643089 <6>[ 1.943627] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10618 19:53:37.649975 <6>[ 1.943630] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10619 19:53:37.656901 <6>[ 1.944018] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10620 19:53:37.663356 <6>[ 1.944609] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10621 19:53:37.669822 <6>[ 1.944830] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10622 19:53:37.676625 <6>[ 1.945073] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10623 19:53:37.682960 <6>[ 1.945319] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10624 19:53:37.692768 <6>[ 1.945517] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10625 19:53:37.702700 <6>[ 1.945528] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10626 19:53:37.712428 <6>[ 1.945530] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10627 19:53:37.722151 <6>[ 1.945532] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10628 19:53:37.729317 <6>[ 1.945536] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10629 19:53:37.739176 <6>[ 1.945547] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10630 19:53:37.749197 <6>[ 1.945552] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10631 19:53:37.759059 <6>[ 1.945555] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10632 19:53:37.768894 <6>[ 1.945557] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10633 19:53:37.778714 <6>[ 1.945564] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10634 19:53:37.788724 <6>[ 1.945568] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10635 19:53:37.794951 <6>[ 1.946805] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10636 19:53:37.801485 <6>[ 1.956450] mmc0: Command Queue Engine enabled
10637 19:53:37.808052 <6>[ 1.956461] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10638 19:53:37.811510 <6>[ 1.957107] mmcblk0: mmc0:0001 DA4128 116 GiB
10639 19:53:37.817929 <6>[ 1.961376] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10640 19:53:37.824567 <6>[ 1.963009] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10641 19:53:37.827831 <6>[ 1.963667] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10642 19:53:37.834633 <6>[ 1.964176] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10643 19:53:37.841220 <6>[ 2.313816] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10644 19:53:37.844713 <6>[ 2.340672] hub 2-1:1.0: USB hub found
10645 19:53:37.851081 <6>[ 2.341037] hub 2-1:1.0: 3 ports detected
10646 19:53:37.857365 <6>[ 2.461567] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10647 19:53:37.861194 <6>[ 2.614449] hub 1-1:1.0: USB hub found
10648 19:53:37.864119 <6>[ 2.614830] hub 1-1:1.0: 4 ports detected
10649 19:53:38.170746 <6>[ 2.925803] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10650 19:53:38.291563 <6>[ 3.051377] hub 1-1.1:1.0: USB hub found
10651 19:53:38.294622 <6>[ 3.051445] hub 1-1.1:1.0: 4 ports detected
10652 19:53:38.402733 <6>[ 3.157536] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10653 19:53:38.523437 <6>[ 3.284321] hub 1-1.4:1.0: USB hub found
10654 19:53:38.526841 <6>[ 3.284671] hub 1-1.4:1.0: 2 ports detected
10655 19:53:38.607468 <6>[ 3.361693] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10656 19:53:38.787214 <6>[ 3.541735] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10657 19:53:38.863516 <3>[ 3.621791] usb 1-1.1.4: device descriptor read/64, error -32
10658 19:53:39.052000 <3>[ 3.809839] usb 1-1.1.4: device descriptor read/64, error -32
10659 19:53:39.243041 <6>[ 3.997787] usb 1-1.1.4: new full-speed USB device number 7 using xhci-mtk
10660 19:53:39.319415 <3>[ 4.077829] usb 1-1.1.4: device descriptor read/64, error -32
10661 19:53:39.507540 <3>[ 4.265789] usb 1-1.1.4: device descriptor read/64, error -32
10662 19:53:39.615556 <6>[ 4.374017] usb 1-1.1-port4: attempt power cycle
10663 19:53:39.699173 <6>[ 4.453766] usb 1-1.4.1: new high-speed USB device number 8 using xhci-mtk
10664 19:53:39.882610 <6>[ 4.637751] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10665 19:53:40.270882 <6>[ 5.025785] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10666 19:53:40.277136 <4>[ 5.025994] usb 1-1.1.4: Device not responding to setup address.
10667 19:53:40.475429 <4>[ 5.233871] usb 1-1.1.4: Device not responding to setup address.
10668 19:53:40.683325 <3>[ 5.441747] usb 1-1.1.4: device not accepting address 10, error -71
10669 19:53:40.766312 <6>[ 5.521752] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10670 19:53:40.772828 <4>[ 5.521906] usb 1-1.1.4: Device not responding to setup address.
10671 19:53:40.971262 <4>[ 5.729849] usb 1-1.1.4: Device not responding to setup address.
10672 19:53:41.179060 <3>[ 5.937758] usb 1-1.1.4: device not accepting address 11, error -71
10673 19:53:41.185534 <3>[ 5.938090] usb 1-1.1-port4: unable to enumerate USB device
10674 19:53:49.479643 <6>[ 14.242726] ALSA device list:
10675 19:53:49.485802 <6>[ 14.242747] No soundcards found.
10676 19:53:49.488875 <6>[ 14.247183] Freeing unused kernel memory: 8448K
10677 19:53:49.492079 <6>[ 14.247350] Run /init as init process
10678 19:53:49.526985 <6>[ 14.288365] NET: Registered PF_INET6 protocol family
10679 19:53:49.529700 <6>[ 14.289323] Segment Routing with IPv6
10680 19:53:49.535647 <6>[ 14.289334] In-situ OAM (IOAM) with IPv6
10681 19:53:49.540340
10682 19:53:49.566366 Welcome to [1mDebian GNU/Linux 11 (bullseye)<30>[ 14.305653] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10683 19:53:49.567053 [0m!
10684 19:53:49.567548
10685 19:53:49.572351 <30>[ 14.306057] systemd[1]: Detected architecture arm64.
10686 19:53:49.579472 <30>[ 14.339966] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10687 19:53:49.705722 <30>[ 14.463676] systemd[1]: Queued start job for default target Graphical Interface.
10688 19:53:49.742666 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.502456] systemd[1]: Created slice system-getty.slice.
10689 19:53:49.746399 m-getty.slice[0m.
10690 19:53:49.770400 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.526499] systemd[1]: Created slice system-modprobe.slice.
10691 19:53:49.770999 m-modprobe.slice[0m.
10692 19:53:49.791377 [[0;32m OK [0m] Created slic<30>[ 14.550923] systemd[1]: Created slice system-serial\x2dgetty.slice.
10693 19:53:49.797585 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10694 19:53:49.817206 [[0;32m OK [0m] Created slice [0;1;39mUser <30>[ 14.573965] systemd[1]: Created slice User and Session Slice.
10695 19:53:49.817775 and Session Slice[0m.
10696 19:53:49.841797 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 14.598238] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10697 19:53:49.845064 ssword …ts to Console Directory Watch[0m.
10698 19:53:49.869055 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 14.625714] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10699 19:53:49.872705 sword R…uests to Wall Directory Watch[0m.
10700 19:53:49.896441 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 14.649776] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10701 19:53:49.903132 <30>[ 14.649953] systemd[1]: Reached target Local Encrypted Volumes.
10702 19:53:49.906391 l Encrypted Volumes[0m.
10703 19:53:49.925932 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 14.685829] systemd[1]: Reached target Paths.
10704 19:53:49.926469 s[0m.
10705 19:53:49.949487 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 14.705679] systemd[1]: Reached target Remote File Systems.
10706 19:53:49.950060 te File Systems[0m.
10707 19:53:49.965833 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 14.725664] systemd[1]: Reached target Slices.
10708 19:53:49.966424 es[0m.
10709 19:53:49.986074 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 14.745721] systemd[1]: Reached target Swap.
10710 19:53:49.986698 [0m.
10711 19:53:50.010295 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 14.766079] systemd[1]: Listening on initctl Compatibility Named Pipe.
10712 19:53:50.012847 l Compatibility Named Pipe[0m.
10713 19:53:50.031662 [[0;32m OK [0m] Listening on<30>[ 14.791044] systemd[1]: Listening on Journal Audit Socket.
10714 19:53:50.034453 [0;1;39mJournal Audit Socket[0m.
10715 19:53:50.055453 [[0;32m OK [0m] Listening on<30>[ 14.814804] systemd[1]: Listening on Journal Socket (/dev/log).
10716 19:53:50.058487 [0;1;39mJournal Socket (/dev/log)[0m.
10717 19:53:50.079152 [[0;32m OK [0m] Listening on<30>[ 14.838868] systemd[1]: Listening on Journal Socket.
10718 19:53:50.082385 [0;1;39mJournal Socket[0m.
10719 19:53:50.101914 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 14.858365] systemd[1]: Listening on Network Service Netlink Socket.
10720 19:53:50.105497 k Service Netlink Socket[0m.
10721 19:53:50.123177 [[0;32m OK [0m] Listening on<30>[ 14.882906] systemd[1]: Listening on udev Control Socket.
10722 19:53:50.126751 [0;1;39mudev Control Socket[0m.
10723 19:53:50.147105 [[0;32m OK [0m] Listening on<30>[ 14.906719] systemd[1]: Listening on udev Kernel Socket.
10724 19:53:50.150405 [0;1;39mudev Kernel Socket[0m.
10725 19:53:50.206152 Mounting [0;1;39mHuge Pages File Syste<30>[ 14.962360] systemd[1]: Mounting Huge Pages File System...
10726 19:53:50.206722 m[0m...
10727 19:53:50.229521 Mounting [0;1;39mPOSIX Message Queue F<30>[ 14.985969] systemd[1]: Mounting POSIX Message Queue File System...
10728 19:53:50.230090 ile System[0m...
10729 19:53:50.257936 Mounting [0;1;39mKernel Debug File Sys<30>[ 15.014117] systemd[1]: Mounting Kernel Debug File System...
10730 19:53:50.258503 tem[0m...
10731 19:53:50.277903 <30>[ 15.034319] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10732 19:53:50.309677 Starting [0;1;39mCreat<30>[ 15.066496] systemd[1]: Starting Create list of static device nodes for the current kernel...
10733 19:53:50.313176 e list of st…odes for the current kernel[0m...
10734 19:53:50.338605 Starting [0;1;39mLoad <30>[ 15.098442] systemd[1]: Starting Load Kernel Module configfs...
10735 19:53:50.342070 Kernel Module configfs[0m...
10736 19:53:50.365933 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.122126] systemd[1]: Starting Load Kernel Module drm...
10737 19:53:50.366503 m[0m...
10738 19:53:50.385854 <30>[ 15.142181] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10739 19:53:50.399669 Starting [0;1;39mJourn<30>[ 15.158901] systemd[1]: Starting Journal Service...
10740 19:53:50.400299 al Service[0m...
10741 19:53:50.423127 Starting [0;1;39mLoad <30>[ 15.182596] systemd[1]: Starting Load Kernel Modules...
10742 19:53:50.425845 Kernel Modules[0m...
10743 19:53:50.450307 Starting [0;1;39mRemount Root and Kern<30>[ 15.206333] systemd[1]: Starting Remount Root and Kernel File Systems...
10744 19:53:50.452886 el File Systems[0m...
10745 19:53:50.472669 Startin<30>[ 15.232533] systemd[1]: Starting Coldplug All udev Devices...
10746 19:53:50.475654 g [0;1;39mColdplug All udev Devices[0m...
10747 19:53:50.493074 [[0;32m OK [<30>[ 15.256314] systemd[1]: Started Journal Service.
10748 19:53:50.499467 0m] Started [0;1;39mJournal Service[0m.
10749 19:53:50.516348 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10750 19:53:50.535920 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10751 19:53:50.551095 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10752 19:53:50.572219 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10753 19:53:50.588402 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10754 19:53:50.608451 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10755 19:53:50.628318 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10756 19:53:50.652628 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10757 19:53:50.667101 See 'systemctl status systemd-remount-fs.service' for details.
10758 19:53:50.719923 Mounting [0;1;39mKernel Configuration File System[0m...
10759 19:53:50.741016 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10760 19:53:50.757674 <46>[ 15.514133] systemd-journald[193]: Received client request to flush runtime journal.
10761 19:53:50.770201 Starting [0;1;39mLoad/Save Random Seed[0m...
10762 19:53:50.794942 Starting [0;1;39mApply Kernel Variables[0m...
10763 19:53:50.820355 Starting [0;1;39mCreate System Users[0m...
10764 19:53:50.843916 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10765 19:53:50.862179 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10766 19:53:50.883530 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10767 19:53:50.896461 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10768 19:53:50.912604 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10769 19:53:50.927830 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10770 19:53:50.967247 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10771 19:53:50.986880 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10772 19:53:50.998301 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10773 19:53:51.014471 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10774 19:53:51.051047 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10775 19:53:51.077894 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10776 19:53:51.096490 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10777 19:53:51.115971 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10778 19:53:51.188340 Starting [0;1;39mNetwork Service[0m...
10779 19:53:51.215874 Starting [0;1;39mNetwork Time Synchronization[0m...
10780 19:53:51.233232 <6>[ 15.991908] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10781 19:53:51.244193 <6>[ 15.991922] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10782 19:53:51.253600 <6>[ 15.991961] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10783 19:53:51.263391 Startin<6>[ 15.991972] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10784 19:53:51.270031 g [0;1;39mUpdat<6>[ 15.994808] remoteproc remoteproc0: scp is available
10785 19:53:51.276662 e UTMP about Sys<6>[ 15.995340] remoteproc remoteproc0: powering up scp
10786 19:53:51.286918 tem Boot/Shutdow<6>[ 15.995347] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10787 19:53:51.287478 n[0m...
10788 19:53:51.290096 <6>[ 15.995368] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10789 19:53:51.299895 <4>[ 16.036318] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10790 19:53:51.306723 <4>[ 16.036502] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10791 19:53:51.318327 <6>[ 16.078602] mc: Linux media interface: v0.10
10792 19:53:51.324544 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10793 19:53:51.353489 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10794 19:53:51.360108 <3>[ 16.121147] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 19:53:51.370332 <3>[ 16.121169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10796 19:53:51.376544 <3>[ 16.121172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10797 19:53:51.386540 <6>[ 16.122397] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10798 19:53:51.393438 <6>[ 16.122407] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10799 19:53:51.402930 [[0;32m OK [0m] Started [0;1;39mNetwork Tim<6>[ 16.122415] remoteproc remoteproc0: remote processor scp is now up
10800 19:53:51.413277 e Synchronizatio<3>[ 16.125083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10801 19:53:51.413835 n[0m.
10802 19:53:51.423099 <3>[ 16.125102] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10803 19:53:51.429786 <3>[ 16.125111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10804 19:53:51.439187 <3>[ 16.125120] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10805 19:53:51.446198 <3>[ 16.125127] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10806 19:53:51.456372 <3>[ 16.126335] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10807 19:53:51.462703 <3>[ 16.127040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10808 19:53:51.472754 [[0;32m OK [<3>[ 16.127045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10809 19:53:51.482181 0m] Finished [0<3>[ 16.127048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10810 19:53:51.488855 <3>[ 16.127474] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10811 19:53:51.498565 <3>[ 16.127480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10812 19:53:51.505413 <3>[ 16.127483] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10813 19:53:51.515939 <3>[ 16.127487] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10814 19:53:51.522938 <3>[ 16.127489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10815 19:53:51.532329 ;1;39mUpdate UTM<3>[ 16.128598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10816 19:53:51.539830 P about System B<6>[ 16.128711] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10817 19:53:51.546283 <6>[ 16.128720] pci_bus 0000:00: root bus resource [bus 00-ff]
10818 19:53:51.552874 <6>[ 16.128729] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10819 19:53:51.563255 <6>[ 16.128734] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10820 19:53:51.569850 oot/Shutdown[0m<6>[ 16.128801] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10821 19:53:51.579636 <6>[ 16.128826] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10822 19:53:51.582895 <6>[ 16.128946] pci 0000:00:00.0: supports D1 D2
10823 19:53:51.583357 .
10824 19:53:51.589725 <6>[ 16.128950] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10825 19:53:51.599007 <6>[ 16.149504] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10826 19:53:51.605889 <6>[ 16.155629] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10827 19:53:51.612493 <6>[ 16.155947] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10828 19:53:51.622463 <6>[ 16.155983] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10829 19:53:51.629249 <6>[ 16.156027] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10830 19:53:51.636096 <6>[ 16.156046] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10831 19:53:51.642676 <6>[ 16.157279] pci 0000:01:00.0: supports D1 D2
10832 19:53:51.648773 <6>[ 16.157285] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10833 19:53:51.659311 <6>[ 16.163697] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10834 19:53:51.666578 <6>[ 16.164968] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10835 19:53:51.676547 [[0;32m OK [0m] Created slic<6>[ 16.198104] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10836 19:53:51.683025 e [0;1;39msyste<6>[ 16.198136] videodev: Linux video capture interface: v2.00
10837 19:53:51.692827 m-systemd\x2dbac<6>[ 16.198203] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10838 19:53:51.699402 <6>[ 16.198210] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10839 19:53:51.711085 klight.slice[0m<6>[ 16.198226] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10840 19:53:51.716986 <6>[ 16.198243] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10841 19:53:51.727119 <6>[ 16.198260] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10842 19:53:51.727677 .
10843 19:53:51.730616 <6>[ 16.198276] pci 0000:00:00.0: PCI bridge to [bus 01]
10844 19:53:51.740976 <6>[ 16.198285] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10845 19:53:51.747556 <6>[ 16.198797] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10846 19:53:51.754442 <6>[ 16.201314] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10847 19:53:51.757010 <6>[ 16.202860] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10848 19:53:51.761011 <6>[ 16.217047] Bluetooth: Core ver 2.22
10849 19:53:51.771060 <6>[ 16.217088] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10850 19:53:51.777528 [[0;32m OK [<6>[ 16.217158] NET: Registered PF_BLUETOOTH protocol family
10851 19:53:51.784014 0m] Reached targ<6>[ 16.217160] Bluetooth: HCI device and connection manager initialized
10852 19:53:51.790583 et [0;1;39mBlue<6>[ 16.217581] Bluetooth: HCI socket layer initialized
10853 19:53:51.791086 tooth[0m.
10854 19:53:51.797824 <6>[ 16.217594] Bluetooth: L2CAP socket layer initialized
10855 19:53:51.804055 <6>[ 16.217624] Bluetooth: SCO socket layer initialized
10856 19:53:51.807793 <6>[ 16.230542] usbcore: registered new interface driver r8152
10857 19:53:51.817964 <4>[ 16.253553] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10858 19:53:51.821382 <4>[ 16.253553] Fallback method does not support PEC.
10859 19:53:51.831665 <3>[ 16.282176] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 19:53:51.838171 <6>[ 16.302553] usbcore: registered new interface driver cdc_ether
10861 19:53:51.845297 <3>[ 16.304415] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10862 19:53:51.855150 <3>[ 16.329512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10863 19:53:51.861589 [[0;32m OK [<6>[ 16.340241] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10864 19:53:51.872404 0m] Reached targ<6>[ 16.345891] usbcore: registered new interface driver r8153_ecm
10865 19:53:51.878499 <6>[ 16.367171] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10866 19:53:51.888658 <4>[ 16.379554] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10867 19:53:51.895691 <3>[ 16.379569] Bluetooth: hci0: Failed to load firmware file (-2)
10868 19:53:51.902018 et [0;1;39mSyst<3>[ 16.379570] Bluetooth: hci0: Failed to set up firmware (-2)
10869 19:53:51.912106 <4>[ 16.379573] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10870 19:53:51.918655 <5>[ 16.381393] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10871 19:53:51.928644 em Time Set[0m.<6>[ 16.391350] usbcore: registered new interface driver btusb
10872 19:53:51.938558 <6>[ 16.393024] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10873 19:53:51.944929 <6>[ 16.393285] usbcore: registered new interface driver uvcvideo
10874 19:53:51.954921 <6>[ 16.393614] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10875 19:53:51.961861 <6>[ 16.400723] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10876 19:53:51.967833 <6>[ 16.402239] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10877 19:53:51.975504 <5>[ 16.403086] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10878 19:53:51.984322 <4>[ 16.403285] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10879 19:53:51.987945 <6>[ 16.403298] cfg80211: failed to load regulatory.db
10880 19:53:51.998239 <3>[ 16.442421] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10881 19:53:52.007881 <3>[ 16.450370] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 19:53:52.014298 <3>[ 16.451183] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10883 19:53:52.024528 <4>[ 16.454298] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10884 19:53:52.034810 <4>[ 16.454320] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10885 19:53:52.037710 <6>[ 16.473531] r8152 1-1.1.1:1.0 eth0: v1.12.13
10886 19:53:52.047411 <3>[ 16.479626] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 19:53:52.053951 <6>[ 16.490897] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10888 19:53:52.061065 <3>[ 16.506613] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 19:53:52.067418 <6>[ 16.514021] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10890 19:53:52.073577 <6>[ 16.514122] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10891 19:53:52.083804 <3>[ 16.528125] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 19:53:52.090457 <6>[ 16.533570] mt7921e 0000:01:00.0: ASIC revision: 79610010
10893 19:53:52.097024 <3>[ 16.553862] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 19:53:52.109808 <4>[ 16.636973] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10895 19:53:52.119801 <4>[ 16.743351] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10896 19:53:52.133031 <4>[ 16.847739] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10897 19:53:52.133729
10898 19:53:52.146702 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10899 19:53:52.165675 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10900 19:53:52.197183 <4>[ 16.951828] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10901 19:53:52.226662 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10902 19:53:52.248745 Starting [0;1;39mNetwork Name Resolution[0m...
10903 19:53:52.272050 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10904 19:53:52.304591 <4>[ 17.060557] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10905 19:53:52.314236 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10906 19:53:52.335241 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10907 19:53:52.353516 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10908 19:53:52.370751 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10909 19:53:52.395362 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10910 19:53:52.412498 <4>[ 17.168271] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10911 19:53:52.419078 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10912 19:53:52.438645 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10913 19:53:52.494870 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10914 19:53:52.524680 <4>[ 17.277593] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10915 19:53:52.539124 Starting [0;1;39mUser Login Management[0m...
10916 19:53:52.558799 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10917 19:53:52.575691 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10918 19:53:52.587600 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10919 19:53:52.602544 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10920 19:53:52.628597 [[0;32m OK [0m] Reached target [0;1;39mHost<4>[ 17.383886] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10921 19:53:52.632401 and Network Name Lookups[0m.
10922 19:53:52.679560 Starting [0;1;39mPermit User Sessions[0m...
10923 19:53:52.696724 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10924 19:53:52.716238 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10925 19:53:52.737133 <4>[ 17.492915] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10926 19:53:52.743076 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10927 19:53:52.764306 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10928 19:53:52.783208 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10929 19:53:52.799041 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10930 19:53:52.814976 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10931 19:53:52.844487 <4>[ 17.600734] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10932 19:53:52.879352 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10933 19:53:52.917912 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10934 19:53:52.940502
10935 19:53:52.941052
10936 19:53:52.947001 Debian GNU/Linux 11 debian-bu<3>[ 17.709243] mt7921e 0000:01:00.0: hardware init failed
10937 19:53:52.949886 llseye-arm64 ttyS0
10938 19:53:52.950434
10939 19:53:52.953025 debian-bullseye-arm64 login: root (automatic login)
10940 19:53:52.953480
10941 19:53:52.953835
10942 19:53:52.967012 Linux debian-bullseye-arm64 6.1.59-cip8-rt4 #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023 aarch64
10943 19:53:52.967555
10944 19:53:52.974181 The programs included with the Debian GNU/Linux system are free software;
10945 19:53:52.980130 the exact distribution terms for each program are described in the
10946 19:53:52.983386 individual files in /usr/share/doc/*/copyright.
10947 19:53:52.983950
10948 19:53:52.990345 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10949 19:53:52.993813 permitted by applicable law.
10950 19:53:52.995306 Matched prompt #10: / #
10952 19:53:52.996458 Setting prompt string to ['/ #']
10953 19:53:52.996935 end: 2.2.5.1 login-action (duration 00:00:18) [common]
10955 19:53:52.997982 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10956 19:53:52.998455 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
10957 19:53:52.998842 Setting prompt string to ['/ #']
10958 19:53:52.999185 Forcing a shell prompt, looking for ['/ #']
10960 19:53:53.050233 / #
10961 19:53:53.050883 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10962 19:53:53.051346 Waiting using forced prompt support (timeout 00:02:30)
10963 19:53:53.056977
10964 19:53:53.057907 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10965 19:53:53.058419 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
10966 19:53:53.058926 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10967 19:53:53.059398 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
10968 19:53:53.059906 end: 2 depthcharge-action (duration 00:01:24) [common]
10969 19:53:53.060389 start: 3 lava-test-retry (timeout 00:08:13) [common]
10970 19:53:53.060865 start: 3.1 lava-test-shell (timeout 00:08:13) [common]
10971 19:53:53.061277 Using namespace: common
10973 19:53:53.162506 / # #
10974 19:53:53.163154 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10975 19:53:53.168852 #
10976 19:53:53.169731 Using /lava-11899576
10978 19:53:53.270916 / # export SHELL=/bin/sh
10979 19:53:53.277698 export SHELL=/bin/sh
10981 19:53:53.379308 / # . /lava-11899576/environment
10982 19:53:53.386722 . /lava-11899576/environment
10984 19:53:53.488606 / # /lava-11899576/bin/lava-test-runner /lava-11899576/0
10985 19:53:53.489234 Test shell timeout: 10s (minimum of the action and connection timeout)
10986 19:53:53.490894 <6>[ 18.172799] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
10987 19:53:53.491327 <6>[ 18.173333] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10988 19:53:53.536324 /lava-11899576/bin/lava-test-runner /lava-11899576/0
10989 19:53:53.536882 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10990 19:53:53.537265 + cd /lava-11899576/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10991 19:53:53.537614 + cat uuid
10992 19:53:53.537945 + UUID=11899576_1.5.2.3.1
10993 19:53:53.538271 + set +x
10994 19:53:53.538900 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11899576_1.5.2.3.1>
10995 19:53:53.539541 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11899576_1.5.2.3.1
10996 19:53:53.539993 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11899576_1.5.2.3.1)
10997 19:53:53.540429 Skipping test definition patterns.
10998 19:53:53.540944 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
10999 19:53:53.546923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11000 19:53:53.547787 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11002 19:53:53.553534 dev<4>[ 18.313062] use of bytesused == 0 is deprecated and will be removed in the future,
11003 19:53:53.560984 ice: /dev/video2<4>[ 18.313069] use the actual size instead.
11004 19:53:53.561566
11005 19:53:53.563330 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11006 19:53:53.575673 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11007 19:53:53.583317
11008 19:53:53.595858 Compliance test for mtk-vcodec-enc device /dev/video2:
11009 19:53:53.603585
11010 19:53:53.614601 Driver Info:
11011 19:53:53.624375 Driver name : mtk-vcodec-enc
11012 19:53:53.638872 Card type : MT8192 video encoder
11013 19:53:53.649446 Bus info : platform:17020000.vcodec
11014 19:53:53.656115 Driver version : 6.1.59
11015 19:53:53.666598 Capabilities : 0x84204000
11016 19:53:53.675882 Video Memory-to-Memory Multiplanar
11017 19:53:53.686387 Streaming
11018 19:53:53.702578 Extended Pix Format
11019 19:53:53.715365 Device Capabilities
11020 19:53:53.724683 Device Caps : 0x04204000
11021 19:53:53.737188 Video Memory-to-Memory Multiplanar
11022 19:53:53.747871 Streaming
11023 19:53:53.763870 Extended Pix Format
11024 19:53:53.775643 Detected Stateful Encoder
11025 19:53:53.789450
11026 19:53:53.799880 Required ioctls:
11027 19:53:53.814888 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11028 19:53:53.815428 test VIDIOC_QUERYCAP: OK
11029 19:53:53.816127 Received signal: <TESTSET> START Required-ioctls
11030 19:53:53.816519 Starting test_set Required-ioctls
11031 19:53:53.838755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11032 19:53:53.839583 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11034 19:53:53.841842 test invalid ioctls: OK
11035 19:53:53.863296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11036 19:53:53.863891
11037 19:53:53.864532 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11039 19:53:53.876103 Allow for multiple opens:
11040 19:53:53.883372 <LAVA_SIGNAL_TESTSET STOP>
11041 19:53:53.884253 Received signal: <TESTSET> STOP
11042 19:53:53.884655 Closing test_set Required-ioctls
11043 19:53:53.894241 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11044 19:53:53.895050 Received signal: <TESTSET> START Allow-for-multiple-opens
11045 19:53:53.895512 Starting test_set Allow-for-multiple-opens
11046 19:53:53.896170 test second /dev/video2 open: OK
11047 19:53:53.918918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11048 19:53:53.919782 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11050 19:53:53.921874 test VIDIOC_QUERYCAP: OK
11051 19:53:53.943144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11052 19:53:53.943970 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11054 19:53:53.946308 test VIDIOC_G/S_PRIORITY: OK
11055 19:53:53.968184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11056 19:53:53.969014 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11058 19:53:53.971709 test for unlimited opens: OK
11059 19:53:53.996257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11060 19:53:53.996863
11061 19:53:53.997521 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11063 19:53:54.007363 Debug ioctls:
11064 19:53:54.014884 <LAVA_SIGNAL_TESTSET STOP>
11065 19:53:54.015716 Received signal: <TESTSET> STOP
11066 19:53:54.016163 Closing test_set Allow-for-multiple-opens
11067 19:53:54.026239 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11068 19:53:54.027070 Received signal: <TESTSET> START Debug-ioctls
11069 19:53:54.027461 Starting test_set Debug-ioctls
11070 19:53:54.029163 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11071 19:53:54.051340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11072 19:53:54.052396 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11074 19:53:54.057997 test VIDIOC_LOG_STATUS: OK (Not Supported)
11075 19:53:54.079425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11076 19:53:54.080020
11077 19:53:54.080663 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11079 19:53:54.091186 Input ioctls:
11080 19:53:54.102663 <LAVA_SIGNAL_TESTSET STOP>
11081 19:53:54.103526 Received signal: <TESTSET> STOP
11082 19:53:54.103966 Closing test_set Debug-ioctls
11083 19:53:54.113047 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11084 19:53:54.113873 Received signal: <TESTSET> START Input-ioctls
11085 19:53:54.114266 Starting test_set Input-ioctls
11086 19:53:54.115981 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11087 19:53:54.144187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11088 19:53:54.145045 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11090 19:53:54.147251 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11091 19:53:54.164494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11092 19:53:54.165325 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11094 19:53:54.170887 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11095 19:53:54.191687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11096 19:53:54.192666 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11098 19:53:54.197915 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11099 19:53:54.216109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11100 19:53:54.216937 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11102 19:53:54.219464 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11103 19:53:54.240604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11104 19:53:54.241435 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11106 19:53:54.243134 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11107 19:53:54.264986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11108 19:53:54.265854 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11110 19:53:54.268244 Inputs: 0 Audio Inputs: 0 Tuners: 0
11111 19:53:54.275945
11112 19:53:54.292170 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11113 19:53:54.313404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11114 19:53:54.314224 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11116 19:53:54.319965 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11117 19:53:54.336926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11118 19:53:54.337676 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11120 19:53:54.343614 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11121 19:53:54.361565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11122 19:53:54.362282 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11124 19:53:54.367905 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11125 19:53:54.385818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11126 19:53:54.386625 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11128 19:53:54.392385 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11129 19:53:54.411840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11130 19:53:54.412385
11131 19:53:54.413017 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11133 19:53:54.433355 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11134 19:53:54.462465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11135 19:53:54.463294 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11137 19:53:54.468945 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11138 19:53:54.495499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11139 19:53:54.496340 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11141 19:53:54.498904 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11142 19:53:54.518112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11143 19:53:54.518936 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11145 19:53:54.521117 test VIDIOC_G/S_EDID: OK (Not Supported)
11146 19:53:54.547254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11147 19:53:54.547837
11148 19:53:54.548476 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11150 19:53:54.560071 Control ioctls:
11151 19:53:54.567767 <LAVA_SIGNAL_TESTSET STOP>
11152 19:53:54.568585 Received signal: <TESTSET> STOP
11153 19:53:54.568966 Closing test_set Input-ioctls
11154 19:53:54.577321 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11155 19:53:54.578146 Received signal: <TESTSET> START Control-ioctls
11156 19:53:54.578535 Starting test_set Control-ioctls
11157 19:53:54.581100 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11158 19:53:54.610960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11159 19:53:54.611505 test VIDIOC_QUERYCTRL: OK
11160 19:53:54.612203 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11162 19:53:54.635555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11163 19:53:54.636439 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11165 19:53:54.637905 test VIDIOC_G/S_CTRL: OK
11166 19:53:54.659833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11167 19:53:54.660658 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11169 19:53:54.663246 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11170 19:53:54.685733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11171 19:53:54.686580 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11173 19:53:54.695202 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11174 19:53:54.698144 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11175 19:53:54.724692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11176 19:53:54.725525 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11178 19:53:54.727205 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11179 19:53:54.746706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11180 19:53:54.747570 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11182 19:53:54.750102 Standard Controls: 16 Private Controls: 0
11183 19:53:54.758084
11184 19:53:54.769240 Format ioctls:
11185 19:53:54.776005 <LAVA_SIGNAL_TESTSET STOP>
11186 19:53:54.777031 Received signal: <TESTSET> STOP
11187 19:53:54.777438 Closing test_set Control-ioctls
11188 19:53:54.785586 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11189 19:53:54.786415 Received signal: <TESTSET> START Format-ioctls
11190 19:53:54.786800 Starting test_set Format-ioctls
11191 19:53:54.788412 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11192 19:53:54.814879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11193 19:53:54.815711 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11195 19:53:54.818326 test VIDIOC_G/S_PARM: OK
11196 19:53:54.836190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11197 19:53:54.837019 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11199 19:53:54.839052 test VIDIOC_G_FBUF: OK (Not Supported)
11200 19:53:54.860886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11201 19:53:54.861718 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11203 19:53:54.864172 test VIDIOC_G_FMT: OK
11204 19:53:54.885381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11205 19:53:54.886207 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11207 19:53:54.888414 test VIDIOC_TRY_FMT: OK
11208 19:53:54.910513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11209 19:53:54.911340 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11211 19:53:54.919929 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11212 19:53:54.920582 test VIDIOC_S_FMT: FAIL
11213 19:53:54.948088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11214 19:53:54.948894 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11216 19:53:54.951498 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11217 19:53:54.972886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11218 19:53:54.973717 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11220 19:53:54.976244 test Cropping: OK
11221 19:53:54.997228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11222 19:53:54.998070 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11224 19:53:55.000388 test Composing: OK (Not Supported)
11225 19:53:55.022687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11226 19:53:55.023509 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11228 19:53:55.025543 test Scaling: OK (Not Supported)
11229 19:53:55.047043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11230 19:53:55.047642
11231 19:53:55.048343 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11233 19:53:55.057086 Codec ioctls:
11234 19:53:55.063984 <LAVA_SIGNAL_TESTSET STOP>
11235 19:53:55.064803 Received signal: <TESTSET> STOP
11236 19:53:55.065185 Closing test_set Format-ioctls
11237 19:53:55.073069 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11238 19:53:55.073881 Received signal: <TESTSET> START Codec-ioctls
11239 19:53:55.074266 Starting test_set Codec-ioctls
11240 19:53:55.076472 test VIDIOC_(TRY_)ENCODER_CMD: OK
11241 19:53:55.097078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11242 19:53:55.097883 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11244 19:53:55.104176 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11245 19:53:55.123602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11246 19:53:55.124513 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11248 19:53:55.129632 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11249 19:53:55.147131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11250 19:53:55.147705
11251 19:53:55.148405 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11253 19:53:55.163191 Buffer ioctls:
11254 19:53:55.169983 <LAVA_SIGNAL_TESTSET STOP>
11255 19:53:55.170811 Received signal: <TESTSET> STOP
11256 19:53:55.171194 Closing test_set Codec-ioctls
11257 19:53:55.179213 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11258 19:53:55.180076 Received signal: <TESTSET> START Buffer-ioctls
11259 19:53:55.180476 Starting test_set Buffer-ioctls
11260 19:53:55.182138 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11261 19:53:55.206366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11262 19:53:55.206906 test VIDIOC_EXPBUF: OK
11263 19:53:55.207534 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11265 19:53:55.228108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11266 19:53:55.228948 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11268 19:53:55.230595 test Requests: OK (Not Supported)
11269 19:53:55.252808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11270 19:53:55.253345
11271 19:53:55.253970 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11273 19:53:55.264291 Test input 0:
11274 19:53:55.275875
11275 19:53:55.291855 Streaming ioctls:
11276 19:53:55.303552 <LAVA_SIGNAL_TESTSET STOP>
11277 19:53:55.304349 Received signal: <TESTSET> STOP
11278 19:53:55.304743 Closing test_set Buffer-ioctls
11279 19:53:55.313336 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11280 19:53:55.314166 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11281 19:53:55.314557 Starting test_set Streaming-ioctls_Test-input-0
11282 19:53:55.316463 test read/write: OK (Not Supported)
11283 19:53:55.334335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11284 19:53:55.335161 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11286 19:53:55.340707 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11287 19:53:55.364248 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11288 19:53:55.368620 test blocking wait: FAIL
11289 19:53:55.396461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11290 19:53:55.397222 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11292 19:53:55.405949 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11293 19:53:55.406547 test MMAP (select): FAIL
11294 19:53:55.428753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11295 19:53:55.429524 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11297 19:53:55.435182 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11298 19:53:55.441825 test MMAP (epoll): FAIL
11299 19:53:55.464442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11300 19:53:55.465198 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11302 19:53:55.474452 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11303 19:53:55.485034 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11304 19:53:55.488679 test USERPTR (select): FAIL
11305 19:53:55.512423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11306 19:53:55.513271 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11308 19:53:55.518971 test DMABUF: Cannot test, specify --expbuf-device
11309 19:53:55.523520
11310 19:53:55.539766 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11311 19:53:55.543269 <LAVA_TEST_RUNNER EXIT>
11312 19:53:55.544178 ok: lava_test_shell seems to have completed
11313 19:53:55.544629 Marking unfinished test run as failed
11315 19:53:55.549553 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11316 19:53:55.550193 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11317 19:53:55.550668 end: 3 lava-test-retry (duration 00:00:02) [common]
11318 19:53:55.551131 start: 4 finalize (timeout 00:08:11) [common]
11319 19:53:55.551619 start: 4.1 power-off (timeout 00:00:30) [common]
11320 19:53:55.552497 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11321 19:53:55.672337 >> Command sent successfully.
11322 19:53:55.676339 Returned 0 in 0 seconds
11323 19:53:55.777413 end: 4.1 power-off (duration 00:00:00) [common]
11325 19:53:55.779042 start: 4.2 read-feedback (timeout 00:08:11) [common]
11326 19:53:55.780500 Listened to connection for namespace 'common' for up to 1s
11327 19:53:56.779991 Finalising connection for namespace 'common'
11328 19:53:56.780673 Disconnecting from shell: Finalise
11329 19:53:56.781066 / #
11330 19:53:56.882094 end: 4.2 read-feedback (duration 00:00:01) [common]
11331 19:53:56.882853 end: 4 finalize (duration 00:00:01) [common]
11332 19:53:56.883470 Cleaning after the job
11333 19:53:56.884058 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/ramdisk
11334 19:53:56.909804 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/kernel
11335 19:53:56.928983 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/dtb
11336 19:53:56.929273 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899576/tftp-deploy-nqnatrmr/modules
11337 19:53:56.939456 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11899576
11338 19:53:57.008258 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11899576
11339 19:53:57.008440 Job finished correctly