Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 18
- Kernel Errors: 33
- Errors: 1
- Boot result: PASS
1 19:56:25.030322 lava-dispatcher, installed at version: 2023.08
2 19:56:25.030521 start: 0 validate
3 19:56:25.030650 Start time: 2023-10-28 19:56:25.030643+00:00 (UTC)
4 19:56:25.030797 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:56:25.030928 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 19:56:25.293532 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:56:25.294280 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:56:25.565112 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:56:25.566033 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:56:25.836577 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:56:25.837352 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:56:26.113077 validate duration: 1.08
14 19:56:26.113356 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:56:26.113453 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:56:26.113540 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:56:26.113667 Not decompressing ramdisk as can be used compressed.
18 19:56:26.113752 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 19:56:26.113818 saving as /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/ramdisk/rootfs.cpio.gz
20 19:56:26.113881 total size: 26246609 (25 MB)
21 19:56:26.114940 progress 0 % (0 MB)
22 19:56:26.122687 progress 5 % (1 MB)
23 19:56:26.130173 progress 10 % (2 MB)
24 19:56:26.137609 progress 15 % (3 MB)
25 19:56:26.144764 progress 20 % (5 MB)
26 19:56:26.151574 progress 25 % (6 MB)
27 19:56:26.158306 progress 30 % (7 MB)
28 19:56:26.165190 progress 35 % (8 MB)
29 19:56:26.171978 progress 40 % (10 MB)
30 19:56:26.178787 progress 45 % (11 MB)
31 19:56:26.185642 progress 50 % (12 MB)
32 19:56:26.192449 progress 55 % (13 MB)
33 19:56:26.199248 progress 60 % (15 MB)
34 19:56:26.206002 progress 65 % (16 MB)
35 19:56:26.212785 progress 70 % (17 MB)
36 19:56:26.219559 progress 75 % (18 MB)
37 19:56:26.226361 progress 80 % (20 MB)
38 19:56:26.233251 progress 85 % (21 MB)
39 19:56:26.239895 progress 90 % (22 MB)
40 19:56:26.246482 progress 95 % (23 MB)
41 19:56:26.253133 progress 100 % (25 MB)
42 19:56:26.253377 25 MB downloaded in 0.14 s (179.44 MB/s)
43 19:56:26.253534 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:56:26.253772 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:56:26.253858 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:56:26.253942 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:56:26.254077 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:56:26.254150 saving as /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/kernel/Image
50 19:56:26.254212 total size: 49304064 (47 MB)
51 19:56:26.254273 No compression specified
52 19:56:26.255417 progress 0 % (0 MB)
53 19:56:26.268248 progress 5 % (2 MB)
54 19:56:26.280849 progress 10 % (4 MB)
55 19:56:26.293398 progress 15 % (7 MB)
56 19:56:26.306096 progress 20 % (9 MB)
57 19:56:26.318921 progress 25 % (11 MB)
58 19:56:26.331535 progress 30 % (14 MB)
59 19:56:26.344161 progress 35 % (16 MB)
60 19:56:26.357129 progress 40 % (18 MB)
61 19:56:26.369893 progress 45 % (21 MB)
62 19:56:26.382791 progress 50 % (23 MB)
63 19:56:26.395442 progress 55 % (25 MB)
64 19:56:26.408155 progress 60 % (28 MB)
65 19:56:26.421183 progress 65 % (30 MB)
66 19:56:26.434001 progress 70 % (32 MB)
67 19:56:26.446898 progress 75 % (35 MB)
68 19:56:26.459691 progress 80 % (37 MB)
69 19:56:26.472594 progress 85 % (39 MB)
70 19:56:26.485421 progress 90 % (42 MB)
71 19:56:26.497881 progress 95 % (44 MB)
72 19:56:26.510207 progress 100 % (47 MB)
73 19:56:26.510410 47 MB downloaded in 0.26 s (183.53 MB/s)
74 19:56:26.510575 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:56:26.510807 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:56:26.510894 start: 1.3 download-retry (timeout 00:10:00) [common]
78 19:56:26.510987 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 19:56:26.511130 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:56:26.511200 saving as /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/dtb/mt8192-asurada-spherion-r0.dtb
81 19:56:26.511262 total size: 47278 (0 MB)
82 19:56:26.511323 No compression specified
83 19:56:26.512519 progress 69 % (0 MB)
84 19:56:26.512794 progress 100 % (0 MB)
85 19:56:26.512952 0 MB downloaded in 0.00 s (26.71 MB/s)
86 19:56:26.513075 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:56:26.513296 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:56:26.513380 start: 1.4 download-retry (timeout 00:10:00) [common]
90 19:56:26.513462 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 19:56:26.513574 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:56:26.513642 saving as /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/modules/modules.tar
93 19:56:26.513703 total size: 8635496 (8 MB)
94 19:56:26.513764 Using unxz to decompress xz
95 19:56:26.517823 progress 0 % (0 MB)
96 19:56:26.539204 progress 5 % (0 MB)
97 19:56:26.561282 progress 10 % (0 MB)
98 19:56:26.587320 progress 15 % (1 MB)
99 19:56:26.612235 progress 20 % (1 MB)
100 19:56:26.637420 progress 25 % (2 MB)
101 19:56:26.664974 progress 30 % (2 MB)
102 19:56:26.689614 progress 35 % (2 MB)
103 19:56:26.714460 progress 40 % (3 MB)
104 19:56:26.738266 progress 45 % (3 MB)
105 19:56:26.763985 progress 50 % (4 MB)
106 19:56:26.788708 progress 55 % (4 MB)
107 19:56:26.814661 progress 60 % (4 MB)
108 19:56:26.837289 progress 65 % (5 MB)
109 19:56:26.861866 progress 70 % (5 MB)
110 19:56:26.885641 progress 75 % (6 MB)
111 19:56:26.911456 progress 80 % (6 MB)
112 19:56:26.943338 progress 85 % (7 MB)
113 19:56:26.968880 progress 90 % (7 MB)
114 19:56:26.992692 progress 95 % (7 MB)
115 19:56:27.015213 progress 100 % (8 MB)
116 19:56:27.020759 8 MB downloaded in 0.51 s (16.24 MB/s)
117 19:56:27.020994 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:56:27.021250 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:56:27.021342 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 19:56:27.021437 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 19:56:27.021517 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:56:27.021602 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 19:56:27.021828 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku
125 19:56:27.021965 makedir: /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin
126 19:56:27.022071 makedir: /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/tests
127 19:56:27.022171 makedir: /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/results
128 19:56:27.022291 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-add-keys
129 19:56:27.022448 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-add-sources
130 19:56:27.022581 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-background-process-start
131 19:56:27.022712 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-background-process-stop
132 19:56:27.022839 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-common-functions
133 19:56:27.022966 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-echo-ipv4
134 19:56:27.023091 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-install-packages
135 19:56:27.023217 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-installed-packages
136 19:56:27.023342 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-os-build
137 19:56:27.023527 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-probe-channel
138 19:56:27.023652 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-probe-ip
139 19:56:27.023779 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-target-ip
140 19:56:27.023904 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-target-mac
141 19:56:27.024028 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-target-storage
142 19:56:27.024157 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-test-case
143 19:56:27.024283 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-test-event
144 19:56:27.024406 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-test-feedback
145 19:56:27.024532 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-test-raise
146 19:56:27.024660 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-test-reference
147 19:56:27.024786 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-test-runner
148 19:56:27.024935 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-test-set
149 19:56:27.025065 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-test-shell
150 19:56:27.025195 Updating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-install-packages (oe)
151 19:56:27.025351 Updating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/bin/lava-installed-packages (oe)
152 19:56:27.025473 Creating /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/environment
153 19:56:27.025572 LAVA metadata
154 19:56:27.025647 - LAVA_JOB_ID=11899582
155 19:56:27.025712 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:56:27.025817 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 19:56:27.025882 skipped lava-vland-overlay
158 19:56:27.025957 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:56:27.026037 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 19:56:27.026100 skipped lava-multinode-overlay
161 19:56:27.026179 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:56:27.026262 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 19:56:27.026334 Loading test definitions
164 19:56:27.026425 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 19:56:27.026499 Using /lava-11899582 at stage 0
166 19:56:27.026807 uuid=11899582_1.5.2.3.1 testdef=None
167 19:56:27.026895 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 19:56:27.026981 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 19:56:27.027527 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 19:56:27.027743 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 19:56:27.028355 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 19:56:27.028586 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 19:56:27.029172 runner path: /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/0/tests/0_v4l2-compliance-uvc test_uuid 11899582_1.5.2.3.1
176 19:56:27.029330 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 19:56:27.029534 Creating lava-test-runner.conf files
179 19:56:27.029596 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899582/lava-overlay-bxnqt5ku/lava-11899582/0 for stage 0
180 19:56:27.029686 - 0_v4l2-compliance-uvc
181 19:56:27.029780 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 19:56:27.029864 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 19:56:27.036506 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 19:56:27.036609 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 19:56:27.036694 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 19:56:27.036777 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 19:56:27.036865 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 19:56:27.744905 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 19:56:27.745289 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 19:56:27.745404 extracting modules file /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899582/extract-overlay-ramdisk-8efwiqcx/ramdisk
191 19:56:27.973925 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 19:56:27.974090 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 19:56:27.974183 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899582/compress-overlay-q_b2xk5k/overlay-1.5.2.4.tar.gz to ramdisk
194 19:56:27.974264 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899582/compress-overlay-q_b2xk5k/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11899582/extract-overlay-ramdisk-8efwiqcx/ramdisk
195 19:56:27.980836 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 19:56:27.980946 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 19:56:27.981034 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 19:56:27.981121 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 19:56:27.981200 Building ramdisk /var/lib/lava/dispatcher/tmp/11899582/extract-overlay-ramdisk-8efwiqcx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11899582/extract-overlay-ramdisk-8efwiqcx/ramdisk
200 19:56:28.561076 >> 228404 blocks
201 19:56:32.426963 rename /var/lib/lava/dispatcher/tmp/11899582/extract-overlay-ramdisk-8efwiqcx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/ramdisk/ramdisk.cpio.gz
202 19:56:32.427437 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 19:56:32.427578 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 19:56:32.427682 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 19:56:32.427789 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/kernel/Image'
206 19:56:44.370679 Returned 0 in 11 seconds
207 19:56:44.471732 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/kernel/image.itb
208 19:56:45.102243 output: FIT description: Kernel Image image with one or more FDT blobs
209 19:56:45.102624 output: Created: Sat Oct 28 20:56:44 2023
210 19:56:45.102699 output: Image 0 (kernel-1)
211 19:56:45.102766 output: Description:
212 19:56:45.102829 output: Created: Sat Oct 28 20:56:44 2023
213 19:56:45.102890 output: Type: Kernel Image
214 19:56:45.102953 output: Compression: lzma compressed
215 19:56:45.103013 output: Data Size: 11047522 Bytes = 10788.60 KiB = 10.54 MiB
216 19:56:45.103074 output: Architecture: AArch64
217 19:56:45.103147 output: OS: Linux
218 19:56:45.103247 output: Load Address: 0x00000000
219 19:56:45.103351 output: Entry Point: 0x00000000
220 19:56:45.103463 output: Hash algo: crc32
221 19:56:45.103520 output: Hash value: da40eda2
222 19:56:45.103578 output: Image 1 (fdt-1)
223 19:56:45.103635 output: Description: mt8192-asurada-spherion-r0
224 19:56:45.103689 output: Created: Sat Oct 28 20:56:44 2023
225 19:56:45.103743 output: Type: Flat Device Tree
226 19:56:45.103796 output: Compression: uncompressed
227 19:56:45.103849 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 19:56:45.103903 output: Architecture: AArch64
229 19:56:45.103956 output: Hash algo: crc32
230 19:56:45.104009 output: Hash value: cc4352de
231 19:56:45.104063 output: Image 2 (ramdisk-1)
232 19:56:45.104115 output: Description: unavailable
233 19:56:45.104168 output: Created: Sat Oct 28 20:56:44 2023
234 19:56:45.104220 output: Type: RAMDisk Image
235 19:56:45.104273 output: Compression: Unknown Compression
236 19:56:45.104326 output: Data Size: 39351787 Bytes = 38429.48 KiB = 37.53 MiB
237 19:56:45.104380 output: Architecture: AArch64
238 19:56:45.104433 output: OS: Linux
239 19:56:45.104486 output: Load Address: unavailable
240 19:56:45.104538 output: Entry Point: unavailable
241 19:56:45.104591 output: Hash algo: crc32
242 19:56:45.104643 output: Hash value: e46de46e
243 19:56:45.104696 output: Default Configuration: 'conf-1'
244 19:56:45.104749 output: Configuration 0 (conf-1)
245 19:56:45.104801 output: Description: mt8192-asurada-spherion-r0
246 19:56:45.104854 output: Kernel: kernel-1
247 19:56:45.104907 output: Init Ramdisk: ramdisk-1
248 19:56:45.104960 output: FDT: fdt-1
249 19:56:45.105013 output: Loadables: kernel-1
250 19:56:45.105066 output:
251 19:56:45.105265 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 19:56:45.105367 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 19:56:45.105470 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 19:56:45.105567 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 19:56:45.105646 No LXC device requested
256 19:56:45.105726 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 19:56:45.105812 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 19:56:45.105888 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 19:56:45.105958 Checking files for TFTP limit of 4294967296 bytes.
260 19:56:45.106466 end: 1 tftp-deploy (duration 00:00:19) [common]
261 19:56:45.106569 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 19:56:45.106660 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 19:56:45.106778 substitutions:
264 19:56:45.106844 - {DTB}: 11899582/tftp-deploy-xxarulxr/dtb/mt8192-asurada-spherion-r0.dtb
265 19:56:45.106908 - {INITRD}: 11899582/tftp-deploy-xxarulxr/ramdisk/ramdisk.cpio.gz
266 19:56:45.106968 - {KERNEL}: 11899582/tftp-deploy-xxarulxr/kernel/Image
267 19:56:45.107025 - {LAVA_MAC}: None
268 19:56:45.107082 - {PRESEED_CONFIG}: None
269 19:56:45.107137 - {PRESEED_LOCAL}: None
270 19:56:45.107191 - {RAMDISK}: 11899582/tftp-deploy-xxarulxr/ramdisk/ramdisk.cpio.gz
271 19:56:45.107245 - {ROOT_PART}: None
272 19:56:45.107299 - {ROOT}: None
273 19:56:45.107352 - {SERVER_IP}: 192.168.201.1
274 19:56:45.107451 - {TEE}: None
275 19:56:45.107507 Parsed boot commands:
276 19:56:45.107561 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 19:56:45.107744 Parsed boot commands: tftpboot 192.168.201.1 11899582/tftp-deploy-xxarulxr/kernel/image.itb 11899582/tftp-deploy-xxarulxr/kernel/cmdline
278 19:56:45.107833 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 19:56:45.107918 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 19:56:45.108011 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 19:56:45.108097 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 19:56:45.108172 Not connected, no need to disconnect.
283 19:56:45.108248 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 19:56:45.108327 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 19:56:45.108398 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 19:56:45.112304 Setting prompt string to ['lava-test: # ']
287 19:56:45.112692 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 19:56:45.112829 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 19:56:45.112935 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 19:56:45.113022 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 19:56:45.113286 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 19:56:50.265048 >> Command sent successfully.
293 19:56:50.271097 Returned 0 in 5 seconds
294 19:56:50.371826 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 19:56:50.373207 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 19:56:50.373715 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 19:56:50.374156 Setting prompt string to 'Starting depthcharge on Spherion...'
299 19:56:50.374494 Changing prompt to 'Starting depthcharge on Spherion...'
300 19:56:50.374833 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 19:56:50.376061 [Enter `^Ec?' for help]
302 19:56:50.539325
303 19:56:50.539916
304 19:56:50.540405 F0: 102B 0000
305 19:56:50.540745
306 19:56:50.541066 F3: 1001 0000 [0200]
307 19:56:50.542704
308 19:56:50.543326 F3: 1001 0000
309 19:56:50.543781
310 19:56:50.544213 F7: 102D 0000
311 19:56:50.544530
312 19:56:50.545563 F1: 0000 0000
313 19:56:50.545988
314 19:56:50.546323 V0: 0000 0000 [0001]
315 19:56:50.546637
316 19:56:50.548852 00: 0007 8000
317 19:56:50.549298
318 19:56:50.549729 01: 0000 0000
319 19:56:50.550076
320 19:56:50.552278 BP: 0C00 0209 [0000]
321 19:56:50.552704
322 19:56:50.553045 G0: 1182 0000
323 19:56:50.553359
324 19:56:50.555486 EC: 0000 0021 [4000]
325 19:56:50.555847
326 19:56:50.556159 S7: 0000 0000 [0000]
327 19:56:50.556459
328 19:56:50.559365 CC: 0000 0000 [0001]
329 19:56:50.559835
330 19:56:50.560176 T0: 0000 0040 [010F]
331 19:56:50.560495
332 19:56:50.562789 Jump to BL
333 19:56:50.563212
334 19:56:50.586187
335 19:56:50.586661
336 19:56:50.586999
337 19:56:50.593836 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 19:56:50.597475 ARM64: Exception handlers installed.
339 19:56:50.601379 ARM64: Testing exception
340 19:56:50.605281 ARM64: Done test exception
341 19:56:50.611620 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 19:56:50.621395 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 19:56:50.628213 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 19:56:50.638370 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 19:56:50.644652 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 19:56:50.651734 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 19:56:50.663088 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 19:56:50.670136 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 19:56:50.689668 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 19:56:50.692470 WDT: Last reset was cold boot
351 19:56:50.695772 SPI1(PAD0) initialized at 2873684 Hz
352 19:56:50.699160 SPI5(PAD0) initialized at 992727 Hz
353 19:56:50.702723 VBOOT: Loading verstage.
354 19:56:50.709652 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 19:56:50.712893 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 19:56:50.715486 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 19:56:50.719171 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 19:56:50.726376 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 19:56:50.733241 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 19:56:50.744373 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 19:56:50.744956
362 19:56:50.745328
363 19:56:50.753876 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 19:56:50.757332 ARM64: Exception handlers installed.
365 19:56:50.760475 ARM64: Testing exception
366 19:56:50.761041 ARM64: Done test exception
367 19:56:50.768517 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 19:56:50.771650 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 19:56:50.785072 Probing TPM: . done!
370 19:56:50.785642 TPM ready after 0 ms
371 19:56:50.791801 Connected to device vid:did:rid of 1ae0:0028:00
372 19:56:50.798690 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 19:56:50.840164 Initialized TPM device CR50 revision 0
374 19:56:50.850937 tlcl_send_startup: Startup return code is 0
375 19:56:50.851660 TPM: setup succeeded
376 19:56:50.862468 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 19:56:50.871810 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 19:56:50.882499 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 19:56:50.891757 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 19:56:50.895200 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 19:56:50.900372 in-header: 03 07 00 00 08 00 00 00
382 19:56:50.903890 in-data: aa e4 47 04 13 02 00 00
383 19:56:50.907202 Chrome EC: UHEPI supported
384 19:56:50.913825 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 19:56:50.918141 in-header: 03 9d 00 00 08 00 00 00
386 19:56:50.921840 in-data: 10 20 20 08 00 00 00 00
387 19:56:50.922431 Phase 1
388 19:56:50.929051 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 19:56:50.933012 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 19:56:50.940641 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 19:56:50.941067 Recovery requested (1009000e)
392 19:56:50.949284 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 19:56:50.954648 tlcl_extend: response is 0
394 19:56:50.962995 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 19:56:50.968698 tlcl_extend: response is 0
396 19:56:50.975771 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 19:56:50.995946 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 19:56:51.003352 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 19:56:51.003829
400 19:56:51.004168
401 19:56:51.011019 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 19:56:51.014727 ARM64: Exception handlers installed.
403 19:56:51.018457 ARM64: Testing exception
404 19:56:51.019050 ARM64: Done test exception
405 19:56:51.037872 pmic_efuse_setting: Set efuses in 11 msecs
406 19:56:51.046966 pmwrap_interface_init: Select PMIF_VLD_RDY
407 19:56:51.050662 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 19:56:51.054407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 19:56:51.057751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 19:56:51.065243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 19:56:51.068919 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 19:56:51.075665 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 19:56:51.079323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 19:56:51.082738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 19:56:51.089784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 19:56:51.092859 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 19:56:51.099420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 19:56:51.102800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 19:56:51.106437 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 19:56:51.112671 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 19:56:51.119558 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 19:56:51.126529 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 19:56:51.129664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 19:56:51.135825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 19:56:51.143327 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 19:56:51.146810 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 19:56:51.154280 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 19:56:51.157460 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 19:56:51.164680 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 19:56:51.167994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 19:56:51.175188 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 19:56:51.182217 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 19:56:51.186181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 19:56:51.189554 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 19:56:51.196418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 19:56:51.199918 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 19:56:51.206693 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 19:56:51.210971 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 19:56:51.214221 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 19:56:51.220275 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 19:56:51.224389 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 19:56:51.228300 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 19:56:51.235275 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 19:56:51.238595 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 19:56:51.244593 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 19:56:51.248494 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 19:56:51.251559 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 19:56:51.258114 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 19:56:51.261738 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 19:56:51.264865 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 19:56:51.271520 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 19:56:51.275188 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 19:56:51.277958 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 19:56:51.284767 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 19:56:51.288357 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 19:56:51.291779 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 19:56:51.295160 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 19:56:51.304651 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 19:56:51.311228 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 19:56:51.318185 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 19:56:51.324514 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 19:56:51.334866 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 19:56:51.337910 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 19:56:51.341392 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 19:56:51.347845 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 19:56:51.355064 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xc
467 19:56:51.357708 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 19:56:51.365705 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 19:56:51.368651 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 19:56:51.378100 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 19:56:51.381225 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 19:56:51.387799 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 19:56:51.391539 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 19:56:51.394768 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 19:56:51.397739 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 19:56:51.401669 ADC[4]: Raw value=895930 ID=7
477 19:56:51.404715 ADC[3]: Raw value=212700 ID=1
478 19:56:51.408074 RAM Code: 0x71
479 19:56:51.411078 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 19:56:51.415049 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 19:56:51.425890 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 19:56:51.431761 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 19:56:51.435547 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 19:56:51.439224 in-header: 03 07 00 00 08 00 00 00
485 19:56:51.442393 in-data: aa e4 47 04 13 02 00 00
486 19:56:51.442915 Chrome EC: UHEPI supported
487 19:56:51.449716 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 19:56:51.453323 in-header: 03 d5 00 00 08 00 00 00
489 19:56:51.456749 in-data: 98 20 60 08 00 00 00 00
490 19:56:51.460963 MRC: failed to locate region type 0.
491 19:56:51.467729 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 19:56:51.471557 DRAM-K: Running full calibration
493 19:56:51.478109 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 19:56:51.478739 header.status = 0x0
495 19:56:51.481194 header.version = 0x6 (expected: 0x6)
496 19:56:51.484985 header.size = 0xd00 (expected: 0xd00)
497 19:56:51.488901 header.flags = 0x0
498 19:56:51.491773 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 19:56:51.510037 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 19:56:51.517015 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 19:56:51.520460 dram_init: ddr_geometry: 2
502 19:56:51.523864 [EMI] MDL number = 2
503 19:56:51.524394 [EMI] Get MDL freq = 0
504 19:56:51.527234 dram_init: ddr_type: 0
505 19:56:51.527839 is_discrete_lpddr4: 1
506 19:56:51.530263 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 19:56:51.530684
508 19:56:51.531014
509 19:56:51.534000 [Bian_co] ETT version 0.0.0.1
510 19:56:51.540164 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 19:56:51.540677
512 19:56:51.543341 dramc_set_vcore_voltage set vcore to 650000
513 19:56:51.543837 Read voltage for 800, 4
514 19:56:51.547029 Vio18 = 0
515 19:56:51.547489 Vcore = 650000
516 19:56:51.547836 Vdram = 0
517 19:56:51.550261 Vddq = 0
518 19:56:51.550680 Vmddr = 0
519 19:56:51.554210 dram_init: config_dvfs: 1
520 19:56:51.556866 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 19:56:51.563575 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 19:56:51.566552 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 19:56:51.570083 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 19:56:51.573309 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 19:56:51.576656 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 19:56:51.579929 MEM_TYPE=3, freq_sel=18
527 19:56:51.583977 sv_algorithm_assistance_LP4_1600
528 19:56:51.587257 ============ PULL DRAM RESETB DOWN ============
529 19:56:51.590156 ========== PULL DRAM RESETB DOWN end =========
530 19:56:51.597222 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 19:56:51.600510 ===================================
532 19:56:51.601005 LPDDR4 DRAM CONFIGURATION
533 19:56:51.603366 ===================================
534 19:56:51.607496 EX_ROW_EN[0] = 0x0
535 19:56:51.610228 EX_ROW_EN[1] = 0x0
536 19:56:51.610662 LP4Y_EN = 0x0
537 19:56:51.613396 WORK_FSP = 0x0
538 19:56:51.613816 WL = 0x2
539 19:56:51.616742 RL = 0x2
540 19:56:51.617323 BL = 0x2
541 19:56:51.620520 RPST = 0x0
542 19:56:51.620942 RD_PRE = 0x0
543 19:56:51.623295 WR_PRE = 0x1
544 19:56:51.623740 WR_PST = 0x0
545 19:56:51.626977 DBI_WR = 0x0
546 19:56:51.627582 DBI_RD = 0x0
547 19:56:51.630268 OTF = 0x1
548 19:56:51.633519 ===================================
549 19:56:51.636701 ===================================
550 19:56:51.637148 ANA top config
551 19:56:51.640106 ===================================
552 19:56:51.643359 DLL_ASYNC_EN = 0
553 19:56:51.646852 ALL_SLAVE_EN = 1
554 19:56:51.650115 NEW_RANK_MODE = 1
555 19:56:51.650574 DLL_IDLE_MODE = 1
556 19:56:51.653414 LP45_APHY_COMB_EN = 1
557 19:56:51.656488 TX_ODT_DIS = 1
558 19:56:51.660312 NEW_8X_MODE = 1
559 19:56:51.663490 ===================================
560 19:56:51.666972 ===================================
561 19:56:51.670481 data_rate = 1600
562 19:56:51.670905 CKR = 1
563 19:56:51.673128 DQ_P2S_RATIO = 8
564 19:56:51.677006 ===================================
565 19:56:51.680456 CA_P2S_RATIO = 8
566 19:56:51.683646 DQ_CA_OPEN = 0
567 19:56:51.687487 DQ_SEMI_OPEN = 0
568 19:56:51.688015 CA_SEMI_OPEN = 0
569 19:56:51.690545 CA_FULL_RATE = 0
570 19:56:51.693773 DQ_CKDIV4_EN = 1
571 19:56:51.697153 CA_CKDIV4_EN = 1
572 19:56:51.700231 CA_PREDIV_EN = 0
573 19:56:51.704289 PH8_DLY = 0
574 19:56:51.704813 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 19:56:51.707776 DQ_AAMCK_DIV = 4
576 19:56:51.711557 CA_AAMCK_DIV = 4
577 19:56:51.715482 CA_ADMCK_DIV = 4
578 19:56:51.715917 DQ_TRACK_CA_EN = 0
579 19:56:51.719266 CA_PICK = 800
580 19:56:51.722678 CA_MCKIO = 800
581 19:56:51.726382 MCKIO_SEMI = 0
582 19:56:51.726811 PLL_FREQ = 3068
583 19:56:51.730295 DQ_UI_PI_RATIO = 32
584 19:56:51.734111 CA_UI_PI_RATIO = 0
585 19:56:51.737963 ===================================
586 19:56:51.741562 ===================================
587 19:56:51.742130 memory_type:LPDDR4
588 19:56:51.744905 GP_NUM : 10
589 19:56:51.745377 SRAM_EN : 1
590 19:56:51.748160 MD32_EN : 0
591 19:56:51.752234 ===================================
592 19:56:51.755813 [ANA_INIT] >>>>>>>>>>>>>>
593 19:56:51.756368 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 19:56:51.759731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 19:56:51.763565 ===================================
596 19:56:51.767342 data_rate = 1600,PCW = 0X7600
597 19:56:51.771075 ===================================
598 19:56:51.774737 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 19:56:51.778000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 19:56:51.785840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 19:56:51.789544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 19:56:51.793257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 19:56:51.797054 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 19:56:51.797580 [ANA_INIT] flow start
605 19:56:51.799829 [ANA_INIT] PLL >>>>>>>>
606 19:56:51.803560 [ANA_INIT] PLL <<<<<<<<
607 19:56:51.804001 [ANA_INIT] MIDPI >>>>>>>>
608 19:56:51.807365 [ANA_INIT] MIDPI <<<<<<<<
609 19:56:51.811113 [ANA_INIT] DLL >>>>>>>>
610 19:56:51.811661 [ANA_INIT] flow end
611 19:56:51.814310 ============ LP4 DIFF to SE enter ============
612 19:56:51.818485 ============ LP4 DIFF to SE exit ============
613 19:56:51.822264 [ANA_INIT] <<<<<<<<<<<<<
614 19:56:51.826037 [Flow] Enable top DCM control >>>>>
615 19:56:51.830151 [Flow] Enable top DCM control <<<<<
616 19:56:51.830744 Enable DLL master slave shuffle
617 19:56:51.837080 ==============================================================
618 19:56:51.837602 Gating Mode config
619 19:56:51.843849 ==============================================================
620 19:56:51.847223 Config description:
621 19:56:51.854027 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 19:56:51.860993 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 19:56:51.867252 SELPH_MODE 0: By rank 1: By Phase
624 19:56:51.874006 ==============================================================
625 19:56:51.874575 GAT_TRACK_EN = 1
626 19:56:51.877826 RX_GATING_MODE = 2
627 19:56:51.880860 RX_GATING_TRACK_MODE = 2
628 19:56:51.883996 SELPH_MODE = 1
629 19:56:51.887081 PICG_EARLY_EN = 1
630 19:56:51.890952 VALID_LAT_VALUE = 1
631 19:56:51.897395 ==============================================================
632 19:56:51.900990 Enter into Gating configuration >>>>
633 19:56:51.904028 Exit from Gating configuration <<<<
634 19:56:51.907312 Enter into DVFS_PRE_config >>>>>
635 19:56:51.917118 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 19:56:51.920372 Exit from DVFS_PRE_config <<<<<
637 19:56:51.924046 Enter into PICG configuration >>>>
638 19:56:51.927091 Exit from PICG configuration <<<<
639 19:56:51.930675 [RX_INPUT] configuration >>>>>
640 19:56:51.931270 [RX_INPUT] configuration <<<<<
641 19:56:51.937535 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 19:56:51.943936 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 19:56:51.947337 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 19:56:51.954116 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 19:56:51.961153 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 19:56:51.967329 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 19:56:51.970772 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 19:56:51.974173 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 19:56:51.980466 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 19:56:51.983867 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 19:56:51.987222 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 19:56:51.993841 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 19:56:51.996921 ===================================
654 19:56:51.997387 LPDDR4 DRAM CONFIGURATION
655 19:56:52.000200 ===================================
656 19:56:52.003858 EX_ROW_EN[0] = 0x0
657 19:56:52.004278 EX_ROW_EN[1] = 0x0
658 19:56:52.006957 LP4Y_EN = 0x0
659 19:56:52.007377 WORK_FSP = 0x0
660 19:56:52.010890 WL = 0x2
661 19:56:52.011460 RL = 0x2
662 19:56:52.013714 BL = 0x2
663 19:56:52.017025 RPST = 0x0
664 19:56:52.017447 RD_PRE = 0x0
665 19:56:52.020416 WR_PRE = 0x1
666 19:56:52.020840 WR_PST = 0x0
667 19:56:52.023688 DBI_WR = 0x0
668 19:56:52.024157 DBI_RD = 0x0
669 19:56:52.026514 OTF = 0x1
670 19:56:52.030287 ===================================
671 19:56:52.033399 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 19:56:52.036715 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 19:56:52.040420 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 19:56:52.043624 ===================================
675 19:56:52.047529 LPDDR4 DRAM CONFIGURATION
676 19:56:52.050357 ===================================
677 19:56:52.053656 EX_ROW_EN[0] = 0x10
678 19:56:52.054180 EX_ROW_EN[1] = 0x0
679 19:56:52.056649 LP4Y_EN = 0x0
680 19:56:52.057097 WORK_FSP = 0x0
681 19:56:52.060938 WL = 0x2
682 19:56:52.061466 RL = 0x2
683 19:56:52.063505 BL = 0x2
684 19:56:52.063942 RPST = 0x0
685 19:56:52.067597 RD_PRE = 0x0
686 19:56:52.068122 WR_PRE = 0x1
687 19:56:52.070756 WR_PST = 0x0
688 19:56:52.071284 DBI_WR = 0x0
689 19:56:52.073592 DBI_RD = 0x0
690 19:56:52.076954 OTF = 0x1
691 19:56:52.080628 ===================================
692 19:56:52.083224 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 19:56:52.088855 nWR fixed to 40
694 19:56:52.091967 [ModeRegInit_LP4] CH0 RK0
695 19:56:52.092403 [ModeRegInit_LP4] CH0 RK1
696 19:56:52.095613 [ModeRegInit_LP4] CH1 RK0
697 19:56:52.098840 [ModeRegInit_LP4] CH1 RK1
698 19:56:52.099321 match AC timing 13
699 19:56:52.105640 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 19:56:52.108683 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 19:56:52.111895 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 19:56:52.118542 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 19:56:52.122575 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 19:56:52.123101 [EMI DOE] emi_dcm 0
705 19:56:52.128890 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 19:56:52.129418 ==
707 19:56:52.132324 Dram Type= 6, Freq= 0, CH_0, rank 0
708 19:56:52.135535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 19:56:52.136057 ==
710 19:56:52.142143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 19:56:52.145336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 19:56:52.156687 [CA 0] Center 38 (7~69) winsize 63
713 19:56:52.159296 [CA 1] Center 37 (7~68) winsize 62
714 19:56:52.163279 [CA 2] Center 35 (5~66) winsize 62
715 19:56:52.166668 [CA 3] Center 35 (5~66) winsize 62
716 19:56:52.170097 [CA 4] Center 34 (4~65) winsize 62
717 19:56:52.173295 [CA 5] Center 34 (4~65) winsize 62
718 19:56:52.173821
719 19:56:52.176860 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 19:56:52.177392
721 19:56:52.179925 [CATrainingPosCal] consider 1 rank data
722 19:56:52.183465 u2DelayCellTimex100 = 270/100 ps
723 19:56:52.186347 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 19:56:52.189813 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 19:56:52.193543 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 19:56:52.196999 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 19:56:52.200181 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 19:56:52.203904 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 19:56:52.204415
730 19:56:52.210943 CA PerBit enable=1, Macro0, CA PI delay=34
731 19:56:52.211514
732 19:56:52.211870 [CBTSetCACLKResult] CA Dly = 34
733 19:56:52.214357 CS Dly: 6 (0~37)
734 19:56:52.214787 ==
735 19:56:52.217823 Dram Type= 6, Freq= 0, CH_0, rank 1
736 19:56:52.221380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 19:56:52.221808 ==
738 19:56:52.229773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 19:56:52.233067 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 19:56:52.242474 [CA 0] Center 38 (7~69) winsize 63
741 19:56:52.246793 [CA 1] Center 37 (7~68) winsize 62
742 19:56:52.249808 [CA 2] Center 35 (5~66) winsize 62
743 19:56:52.253643 [CA 3] Center 35 (5~66) winsize 62
744 19:56:52.257399 [CA 4] Center 34 (4~65) winsize 62
745 19:56:52.260947 [CA 5] Center 34 (4~65) winsize 62
746 19:56:52.261387
747 19:56:52.264589 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 19:56:52.265019
749 19:56:52.268614 [CATrainingPosCal] consider 2 rank data
750 19:56:52.269038 u2DelayCellTimex100 = 270/100 ps
751 19:56:52.272002 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 19:56:52.275894 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 19:56:52.279499 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 19:56:52.283239 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 19:56:52.287170 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 19:56:52.289828 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 19:56:52.290250
758 19:56:52.297602 CA PerBit enable=1, Macro0, CA PI delay=34
759 19:56:52.298112
760 19:56:52.298449 [CBTSetCACLKResult] CA Dly = 34
761 19:56:52.301288 CS Dly: 6 (0~38)
762 19:56:52.301711
763 19:56:52.304888 ----->DramcWriteLeveling(PI) begin...
764 19:56:52.305448 ==
765 19:56:52.308709 Dram Type= 6, Freq= 0, CH_0, rank 0
766 19:56:52.312557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 19:56:52.313081 ==
768 19:56:52.316058 Write leveling (Byte 0): 34 => 34
769 19:56:52.320003 Write leveling (Byte 1): 29 => 29
770 19:56:52.320424 DramcWriteLeveling(PI) end<-----
771 19:56:52.320759
772 19:56:52.321069 ==
773 19:56:52.323572 Dram Type= 6, Freq= 0, CH_0, rank 0
774 19:56:52.327578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 19:56:52.328094 ==
776 19:56:52.330783 [Gating] SW mode calibration
777 19:56:52.338479 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 19:56:52.345159 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 19:56:52.349401 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 19:56:52.353182 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 19:56:52.356521 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 19:56:52.360095 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 19:56:52.367027 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 19:56:52.371084 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 19:56:52.374453 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 19:56:52.378128 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 19:56:52.382346 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 19:56:52.389535 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 19:56:52.392947 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 19:56:52.397415 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 19:56:52.400249 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 19:56:52.404779 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 19:56:52.411834 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 19:56:52.415794 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:56:52.419206 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:56:52.422871 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 19:56:52.427114 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
798 19:56:52.430477 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
799 19:56:52.438004 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 19:56:52.441319 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 19:56:52.445019 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 19:56:52.448398 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 19:56:52.452272 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 19:56:52.459488 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 19:56:52.463663 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 19:56:52.467100 0 9 12 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
807 19:56:52.470667 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 19:56:52.474490 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 19:56:52.481600 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 19:56:52.485651 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 19:56:52.489369 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 19:56:52.492656 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
813 19:56:52.496888 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
814 19:56:52.500697 0 10 12 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (0 0)
815 19:56:52.507705 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 19:56:52.511727 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 19:56:52.515791 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 19:56:52.519031 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 19:56:52.522480 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 19:56:52.529197 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 19:56:52.532868 0 11 8 | B1->B0 | 2727 2b2b | 0 0 | (1 1) (0 0)
822 19:56:52.536108 0 11 12 | B1->B0 | 3535 3f3f | 0 0 | (0 0) (0 0)
823 19:56:52.542643 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
824 19:56:52.545937 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 19:56:52.549396 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 19:56:52.555902 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 19:56:52.558964 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 19:56:52.562510 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 19:56:52.569213 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 19:56:52.572996 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 19:56:52.575841 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 19:56:52.583073 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 19:56:52.586045 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 19:56:52.589630 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 19:56:52.592634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 19:56:52.599333 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 19:56:52.602263 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 19:56:52.605990 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 19:56:52.612744 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 19:56:52.616303 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 19:56:52.619586 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 19:56:52.626430 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 19:56:52.629795 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 19:56:52.632596 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 19:56:52.639639 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 19:56:52.642904 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 19:56:52.646048 Total UI for P1: 0, mck2ui 16
848 19:56:52.649172 best dqsien dly found for B0: ( 0, 14, 8)
849 19:56:52.652962 Total UI for P1: 0, mck2ui 16
850 19:56:52.656280 best dqsien dly found for B1: ( 0, 14, 10)
851 19:56:52.659562 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 19:56:52.662955 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
853 19:56:52.663381
854 19:56:52.666322 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 19:56:52.669138 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 19:56:52.672673 [Gating] SW calibration Done
857 19:56:52.673106 ==
858 19:56:52.675832 Dram Type= 6, Freq= 0, CH_0, rank 0
859 19:56:52.679247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 19:56:52.679728 ==
861 19:56:52.682581 RX Vref Scan: 0
862 19:56:52.683009
863 19:56:52.686034 RX Vref 0 -> 0, step: 1
864 19:56:52.686461
865 19:56:52.686803 RX Delay -130 -> 252, step: 16
866 19:56:52.692922 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
867 19:56:52.695983 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 19:56:52.699035 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 19:56:52.703122 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 19:56:52.706090 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 19:56:52.712993 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
872 19:56:52.715960 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 19:56:52.719292 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 19:56:52.722784 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 19:56:52.725737 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
876 19:56:52.732306 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 19:56:52.735864 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 19:56:52.739162 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 19:56:52.742807 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 19:56:52.746364 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 19:56:52.752671 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 19:56:52.753119 ==
883 19:56:52.755845 Dram Type= 6, Freq= 0, CH_0, rank 0
884 19:56:52.759117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 19:56:52.759606 ==
886 19:56:52.760060 DQS Delay:
887 19:56:52.763009 DQS0 = 0, DQS1 = 0
888 19:56:52.763497 DQM Delay:
889 19:56:52.765953 DQM0 = 80, DQM1 = 70
890 19:56:52.766367 DQ Delay:
891 19:56:52.769574 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
892 19:56:52.772595 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
893 19:56:52.776326 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
894 19:56:52.779747 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 19:56:52.780278
896 19:56:52.780618
897 19:56:52.780997 ==
898 19:56:52.782873 Dram Type= 6, Freq= 0, CH_0, rank 0
899 19:56:52.786137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 19:56:52.786571 ==
901 19:56:52.786909
902 19:56:52.787225
903 19:56:52.790343 TX Vref Scan disable
904 19:56:52.793226 == TX Byte 0 ==
905 19:56:52.796764 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
906 19:56:52.800344 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
907 19:56:52.803547 == TX Byte 1 ==
908 19:56:52.806875 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
909 19:56:52.809807 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
910 19:56:52.810237 ==
911 19:56:52.813592 Dram Type= 6, Freq= 0, CH_0, rank 0
912 19:56:52.816400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 19:56:52.819599 ==
914 19:56:52.831558 TX Vref=22, minBit 11, minWin=26, winSum=433
915 19:56:52.835309 TX Vref=24, minBit 11, minWin=26, winSum=440
916 19:56:52.838678 TX Vref=26, minBit 5, minWin=27, winSum=443
917 19:56:52.841722 TX Vref=28, minBit 11, minWin=27, winSum=449
918 19:56:52.845537 TX Vref=30, minBit 11, minWin=27, winSum=445
919 19:56:52.852193 TX Vref=32, minBit 9, minWin=27, winSum=442
920 19:56:52.855087 [TxChooseVref] Worse bit 11, Min win 27, Win sum 449, Final Vref 28
921 19:56:52.855557
922 19:56:52.858352 Final TX Range 1 Vref 28
923 19:56:52.858780
924 19:56:52.859148 ==
925 19:56:52.862832 Dram Type= 6, Freq= 0, CH_0, rank 0
926 19:56:52.865011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 19:56:52.868310 ==
928 19:56:52.868840
929 19:56:52.869181
930 19:56:52.869497 TX Vref Scan disable
931 19:56:52.873008 == TX Byte 0 ==
932 19:56:52.875455 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
933 19:56:52.882122 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
934 19:56:52.882666 == TX Byte 1 ==
935 19:56:52.885512 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
936 19:56:52.891788 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
937 19:56:52.892321
938 19:56:52.892860 [DATLAT]
939 19:56:52.893242 Freq=800, CH0 RK0
940 19:56:52.893564
941 19:56:52.895237 DATLAT Default: 0xa
942 19:56:52.895716 0, 0xFFFF, sum = 0
943 19:56:52.898773 1, 0xFFFF, sum = 0
944 19:56:52.899331 2, 0xFFFF, sum = 0
945 19:56:52.902024 3, 0xFFFF, sum = 0
946 19:56:52.902458 4, 0xFFFF, sum = 0
947 19:56:52.905416 5, 0xFFFF, sum = 0
948 19:56:52.909277 6, 0xFFFF, sum = 0
949 19:56:52.909816 7, 0xFFFF, sum = 0
950 19:56:52.912551 8, 0xFFFF, sum = 0
951 19:56:52.913095 9, 0x0, sum = 1
952 19:56:52.913448 10, 0x0, sum = 2
953 19:56:52.915958 11, 0x0, sum = 3
954 19:56:52.916502 12, 0x0, sum = 4
955 19:56:52.918706 best_step = 10
956 19:56:52.919130
957 19:56:52.919511 ==
958 19:56:52.922547 Dram Type= 6, Freq= 0, CH_0, rank 0
959 19:56:52.925845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 19:56:52.926390 ==
961 19:56:52.928812 RX Vref Scan: 1
962 19:56:52.929240
963 19:56:52.929581 Set Vref Range= 32 -> 127
964 19:56:52.929900
965 19:56:52.932112 RX Vref 32 -> 127, step: 1
966 19:56:52.932540
967 19:56:52.936065 RX Delay -111 -> 252, step: 8
968 19:56:52.936608
969 19:56:52.939112 Set Vref, RX VrefLevel [Byte0]: 32
970 19:56:52.942808 [Byte1]: 32
971 19:56:52.943345
972 19:56:52.945491 Set Vref, RX VrefLevel [Byte0]: 33
973 19:56:52.948758 [Byte1]: 33
974 19:56:52.952395
975 19:56:52.952852 Set Vref, RX VrefLevel [Byte0]: 34
976 19:56:52.956116 [Byte1]: 34
977 19:56:52.960195
978 19:56:52.960623 Set Vref, RX VrefLevel [Byte0]: 35
979 19:56:52.963965 [Byte1]: 35
980 19:56:52.968239
981 19:56:52.968792 Set Vref, RX VrefLevel [Byte0]: 36
982 19:56:52.971537 [Byte1]: 36
983 19:56:52.975577
984 19:56:52.976103 Set Vref, RX VrefLevel [Byte0]: 37
985 19:56:52.978923 [Byte1]: 37
986 19:56:52.983212
987 19:56:52.983805 Set Vref, RX VrefLevel [Byte0]: 38
988 19:56:52.986699 [Byte1]: 38
989 19:56:52.991007
990 19:56:52.991575 Set Vref, RX VrefLevel [Byte0]: 39
991 19:56:52.994355 [Byte1]: 39
992 19:56:52.998483
993 19:56:52.999014 Set Vref, RX VrefLevel [Byte0]: 40
994 19:56:53.002511 [Byte1]: 40
995 19:56:53.006331
996 19:56:53.006866 Set Vref, RX VrefLevel [Byte0]: 41
997 19:56:53.009145 [Byte1]: 41
998 19:56:53.013815
999 19:56:53.014339 Set Vref, RX VrefLevel [Byte0]: 42
1000 19:56:53.017252 [Byte1]: 42
1001 19:56:53.021203
1002 19:56:53.021645 Set Vref, RX VrefLevel [Byte0]: 43
1003 19:56:53.028106 [Byte1]: 43
1004 19:56:53.028638
1005 19:56:53.031168 Set Vref, RX VrefLevel [Byte0]: 44
1006 19:56:53.034509 [Byte1]: 44
1007 19:56:53.035032
1008 19:56:53.037751 Set Vref, RX VrefLevel [Byte0]: 45
1009 19:56:53.041806 [Byte1]: 45
1010 19:56:53.042334
1011 19:56:53.045282 Set Vref, RX VrefLevel [Byte0]: 46
1012 19:56:53.048353 [Byte1]: 46
1013 19:56:53.052631
1014 19:56:53.053061 Set Vref, RX VrefLevel [Byte0]: 47
1015 19:56:53.055862 [Byte1]: 47
1016 19:56:53.059705
1017 19:56:53.060133 Set Vref, RX VrefLevel [Byte0]: 48
1018 19:56:53.062852 [Byte1]: 48
1019 19:56:53.067913
1020 19:56:53.068339 Set Vref, RX VrefLevel [Byte0]: 49
1021 19:56:53.071156 [Byte1]: 49
1022 19:56:53.075233
1023 19:56:53.075704 Set Vref, RX VrefLevel [Byte0]: 50
1024 19:56:53.078556 [Byte1]: 50
1025 19:56:53.082511
1026 19:56:53.083018 Set Vref, RX VrefLevel [Byte0]: 51
1027 19:56:53.085953 [Byte1]: 51
1028 19:56:53.090264
1029 19:56:53.090779 Set Vref, RX VrefLevel [Byte0]: 52
1030 19:56:53.093832 [Byte1]: 52
1031 19:56:53.098972
1032 19:56:53.099516 Set Vref, RX VrefLevel [Byte0]: 53
1033 19:56:53.101099 [Byte1]: 53
1034 19:56:53.105632
1035 19:56:53.106144 Set Vref, RX VrefLevel [Byte0]: 54
1036 19:56:53.109447 [Byte1]: 54
1037 19:56:53.113386
1038 19:56:53.113901 Set Vref, RX VrefLevel [Byte0]: 55
1039 19:56:53.116235 [Byte1]: 55
1040 19:56:53.121011
1041 19:56:53.121427 Set Vref, RX VrefLevel [Byte0]: 56
1042 19:56:53.127082 [Byte1]: 56
1043 19:56:53.127727
1044 19:56:53.130800 Set Vref, RX VrefLevel [Byte0]: 57
1045 19:56:53.133761 [Byte1]: 57
1046 19:56:53.134273
1047 19:56:53.137431 Set Vref, RX VrefLevel [Byte0]: 58
1048 19:56:53.140334 [Byte1]: 58
1049 19:56:53.143941
1050 19:56:53.144450 Set Vref, RX VrefLevel [Byte0]: 59
1051 19:56:53.147137 [Byte1]: 59
1052 19:56:53.151420
1053 19:56:53.151938 Set Vref, RX VrefLevel [Byte0]: 60
1054 19:56:53.154830 [Byte1]: 60
1055 19:56:53.159142
1056 19:56:53.159738 Set Vref, RX VrefLevel [Byte0]: 61
1057 19:56:53.162658 [Byte1]: 61
1058 19:56:53.167009
1059 19:56:53.167561 Set Vref, RX VrefLevel [Byte0]: 62
1060 19:56:53.169844 [Byte1]: 62
1061 19:56:53.174287
1062 19:56:53.174797 Set Vref, RX VrefLevel [Byte0]: 63
1063 19:56:53.177564 [Byte1]: 63
1064 19:56:53.182166
1065 19:56:53.182679 Set Vref, RX VrefLevel [Byte0]: 64
1066 19:56:53.185780 [Byte1]: 64
1067 19:56:53.189653
1068 19:56:53.190072 Set Vref, RX VrefLevel [Byte0]: 65
1069 19:56:53.192966 [Byte1]: 65
1070 19:56:53.197129
1071 19:56:53.197550 Set Vref, RX VrefLevel [Byte0]: 66
1072 19:56:53.200617 [Byte1]: 66
1073 19:56:53.205082
1074 19:56:53.205616 Set Vref, RX VrefLevel [Byte0]: 67
1075 19:56:53.207916 [Byte1]: 67
1076 19:56:53.212705
1077 19:56:53.213213 Set Vref, RX VrefLevel [Byte0]: 68
1078 19:56:53.216153 [Byte1]: 68
1079 19:56:53.219967
1080 19:56:53.220389 Set Vref, RX VrefLevel [Byte0]: 69
1081 19:56:53.223249 [Byte1]: 69
1082 19:56:53.227757
1083 19:56:53.228268 Set Vref, RX VrefLevel [Byte0]: 70
1084 19:56:53.230945 [Byte1]: 70
1085 19:56:53.235814
1086 19:56:53.236325 Set Vref, RX VrefLevel [Byte0]: 71
1087 19:56:53.238831 [Byte1]: 71
1088 19:56:53.243705
1089 19:56:53.244217 Set Vref, RX VrefLevel [Byte0]: 72
1090 19:56:53.246763 [Byte1]: 72
1091 19:56:53.250826
1092 19:56:53.251453 Set Vref, RX VrefLevel [Byte0]: 73
1093 19:56:53.254186 [Byte1]: 73
1094 19:56:53.258895
1095 19:56:53.259543 Set Vref, RX VrefLevel [Byte0]: 74
1096 19:56:53.262209 [Byte1]: 74
1097 19:56:53.266146
1098 19:56:53.266568 Set Vref, RX VrefLevel [Byte0]: 75
1099 19:56:53.269286 [Byte1]: 75
1100 19:56:53.274110
1101 19:56:53.274632 Set Vref, RX VrefLevel [Byte0]: 76
1102 19:56:53.277170 [Byte1]: 76
1103 19:56:53.281693
1104 19:56:53.282294 Set Vref, RX VrefLevel [Byte0]: 77
1105 19:56:53.285043 [Byte1]: 77
1106 19:56:53.289136
1107 19:56:53.291991 Set Vref, RX VrefLevel [Byte0]: 78
1108 19:56:53.292417 [Byte1]: 78
1109 19:56:53.296747
1110 19:56:53.297266 Set Vref, RX VrefLevel [Byte0]: 79
1111 19:56:53.299733 [Byte1]: 79
1112 19:56:53.304358
1113 19:56:53.304777 Final RX Vref Byte 0 = 59 to rank0
1114 19:56:53.307757 Final RX Vref Byte 1 = 61 to rank0
1115 19:56:53.311268 Final RX Vref Byte 0 = 59 to rank1
1116 19:56:53.314619 Final RX Vref Byte 1 = 61 to rank1==
1117 19:56:53.317671 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 19:56:53.324270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 19:56:53.324695 ==
1120 19:56:53.325034 DQS Delay:
1121 19:56:53.325344 DQS0 = 0, DQS1 = 0
1122 19:56:53.327525 DQM Delay:
1123 19:56:53.327888 DQM0 = 82, DQM1 = 68
1124 19:56:53.330988 DQ Delay:
1125 19:56:53.334530 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1126 19:56:53.335057 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1127 19:56:53.337968 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1128 19:56:53.344367 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1129 19:56:53.344896
1130 19:56:53.345234
1131 19:56:53.350797 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1132 19:56:53.354291 CH0 RK0: MR19=606, MR18=2727
1133 19:56:53.360857 CH0_RK0: MR19=0x606, MR18=0x2727, DQSOSC=400, MR23=63, INC=92, DEC=61
1134 19:56:53.361372
1135 19:56:53.364055 ----->DramcWriteLeveling(PI) begin...
1136 19:56:53.364483 ==
1137 19:56:53.367650 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 19:56:53.370841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 19:56:53.371366 ==
1140 19:56:53.374352 Write leveling (Byte 0): 33 => 33
1141 19:56:53.377642 Write leveling (Byte 1): 32 => 32
1142 19:56:53.380845 DramcWriteLeveling(PI) end<-----
1143 19:56:53.381370
1144 19:56:53.381708 ==
1145 19:56:53.383974 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 19:56:53.387652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 19:56:53.388182 ==
1148 19:56:53.391104 [Gating] SW mode calibration
1149 19:56:53.397530 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 19:56:53.404348 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 19:56:53.407428 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 19:56:53.410802 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 19:56:53.417878 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1154 19:56:53.420498 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 19:56:53.423982 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 19:56:53.430775 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 19:56:53.434143 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 19:56:53.437834 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 19:56:53.444166 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 19:56:53.447502 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 19:56:53.451141 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 19:56:53.457240 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 19:56:53.461257 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 19:56:53.463872 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 19:56:53.508029 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 19:56:53.508967 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 19:56:53.509367 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 19:56:53.509687 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1169 19:56:53.509992 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1170 19:56:53.510376 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 19:56:53.510722 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 19:56:53.511185 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 19:56:53.511536 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 19:56:53.511850 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 19:56:53.552049 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 19:56:53.552677 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 19:56:53.553422 0 9 8 | B1->B0 | 2323 2b2b | 1 0 | (1 1) (0 0)
1178 19:56:53.553819 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1179 19:56:53.554165 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 19:56:53.554496 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 19:56:53.554884 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 19:56:53.555220 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 19:56:53.555572 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 19:56:53.555889 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1185 19:56:53.557337 0 10 8 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 0)
1186 19:56:53.560344 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1187 19:56:53.563840 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 19:56:53.571117 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 19:56:53.574513 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 19:56:53.577884 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 19:56:53.584082 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 19:56:53.587870 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 19:56:53.591355 0 11 8 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (1 1)
1194 19:56:53.597587 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 19:56:53.601068 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 19:56:53.604157 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 19:56:53.610688 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 19:56:53.614609 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 19:56:53.617459 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 19:56:53.621209 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1201 19:56:53.629352 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1202 19:56:53.632487 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 19:56:53.636307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 19:56:53.639771 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 19:56:53.646650 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 19:56:53.650526 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 19:56:53.653572 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 19:56:53.657141 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 19:56:53.663814 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 19:56:53.667301 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 19:56:53.670509 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 19:56:53.677438 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 19:56:53.680749 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 19:56:53.684151 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 19:56:53.687455 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 19:56:53.694553 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 19:56:53.697692 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1218 19:56:53.700772 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 19:56:53.703755 Total UI for P1: 0, mck2ui 16
1220 19:56:53.707987 best dqsien dly found for B0: ( 0, 14, 8)
1221 19:56:53.711229 Total UI for P1: 0, mck2ui 16
1222 19:56:53.714168 best dqsien dly found for B1: ( 0, 14, 10)
1223 19:56:53.717271 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1224 19:56:53.720946 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1225 19:56:53.721400
1226 19:56:53.727459 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1227 19:56:53.731092 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1228 19:56:53.731770 [Gating] SW calibration Done
1229 19:56:53.734154 ==
1230 19:56:53.737973 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 19:56:53.740935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 19:56:53.741401 ==
1233 19:56:53.741766 RX Vref Scan: 0
1234 19:56:53.742106
1235 19:56:53.743991 RX Vref 0 -> 0, step: 1
1236 19:56:53.744450
1237 19:56:53.746863 RX Delay -130 -> 252, step: 16
1238 19:56:53.750413 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1239 19:56:53.753767 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1240 19:56:53.760701 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1241 19:56:53.764294 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1242 19:56:53.767556 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1243 19:56:53.771057 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1244 19:56:53.774507 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1245 19:56:53.777437 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1246 19:56:53.783948 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1247 19:56:53.787789 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1248 19:56:53.791060 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1249 19:56:53.794369 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1250 19:56:53.797863 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1251 19:56:53.803958 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1252 19:56:53.807283 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1253 19:56:53.810457 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1254 19:56:53.810874 ==
1255 19:56:53.814074 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 19:56:53.817924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 19:56:53.818340 ==
1258 19:56:53.820496 DQS Delay:
1259 19:56:53.820912 DQS0 = 0, DQS1 = 0
1260 19:56:53.824426 DQM Delay:
1261 19:56:53.824949 DQM0 = 78, DQM1 = 69
1262 19:56:53.825333 DQ Delay:
1263 19:56:53.827754 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =69
1264 19:56:53.830662 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1265 19:56:53.834269 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1266 19:56:53.837629 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1267 19:56:53.838155
1268 19:56:53.838490
1269 19:56:53.841129 ==
1270 19:56:53.844363 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 19:56:53.847584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 19:56:53.848006 ==
1273 19:56:53.848338
1274 19:56:53.848644
1275 19:56:53.851324 TX Vref Scan disable
1276 19:56:53.851884 == TX Byte 0 ==
1277 19:56:53.854272 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1278 19:56:53.860686 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1279 19:56:53.861224 == TX Byte 1 ==
1280 19:56:53.864601 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1281 19:56:53.870866 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1282 19:56:53.871419 ==
1283 19:56:53.873976 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 19:56:53.877420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 19:56:53.877946 ==
1286 19:56:53.891101 TX Vref=22, minBit 12, minWin=26, winSum=435
1287 19:56:53.893510 TX Vref=24, minBit 1, minWin=27, winSum=442
1288 19:56:53.897268 TX Vref=26, minBit 2, minWin=27, winSum=442
1289 19:56:53.900362 TX Vref=28, minBit 1, minWin=27, winSum=442
1290 19:56:53.904001 TX Vref=30, minBit 1, minWin=27, winSum=440
1291 19:56:53.910784 TX Vref=32, minBit 1, minWin=27, winSum=440
1292 19:56:53.913939 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 24
1293 19:56:53.914401
1294 19:56:53.917009 Final TX Range 1 Vref 24
1295 19:56:53.917426
1296 19:56:53.917755 ==
1297 19:56:53.920549 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 19:56:53.923908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 19:56:53.927141 ==
1300 19:56:53.927585
1301 19:56:53.927918
1302 19:56:53.928219 TX Vref Scan disable
1303 19:56:53.930208 == TX Byte 0 ==
1304 19:56:53.933990 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1305 19:56:53.940271 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1306 19:56:53.940568 == TX Byte 1 ==
1307 19:56:53.943734 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1308 19:56:53.950288 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1309 19:56:53.950685
1310 19:56:53.950937 [DATLAT]
1311 19:56:53.951156 Freq=800, CH0 RK1
1312 19:56:53.951368
1313 19:56:53.953950 DATLAT Default: 0xa
1314 19:56:53.954337 0, 0xFFFF, sum = 0
1315 19:56:53.957162 1, 0xFFFF, sum = 0
1316 19:56:53.957558 2, 0xFFFF, sum = 0
1317 19:56:53.960508 3, 0xFFFF, sum = 0
1318 19:56:53.960952 4, 0xFFFF, sum = 0
1319 19:56:53.963472 5, 0xFFFF, sum = 0
1320 19:56:53.967099 6, 0xFFFF, sum = 0
1321 19:56:53.967529 7, 0xFFFF, sum = 0
1322 19:56:53.970159 8, 0xFFFF, sum = 0
1323 19:56:53.970523 9, 0x0, sum = 1
1324 19:56:53.970769 10, 0x0, sum = 2
1325 19:56:53.973901 11, 0x0, sum = 3
1326 19:56:53.974201 12, 0x0, sum = 4
1327 19:56:53.977030 best_step = 10
1328 19:56:53.977441
1329 19:56:53.977767 ==
1330 19:56:53.980518 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 19:56:53.983622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 19:56:53.984041 ==
1333 19:56:53.987267 RX Vref Scan: 0
1334 19:56:53.987711
1335 19:56:53.988038 RX Vref 0 -> 0, step: 1
1336 19:56:53.988346
1337 19:56:53.990681 RX Delay -111 -> 252, step: 8
1338 19:56:53.997979 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1339 19:56:54.000453 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1340 19:56:54.003925 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1341 19:56:54.007685 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1342 19:56:54.010759 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1343 19:56:54.017529 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1344 19:56:54.020468 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1345 19:56:54.023834 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1346 19:56:54.027494 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1347 19:56:54.030909 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1348 19:56:54.037054 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1349 19:56:54.040626 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1350 19:56:54.043847 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1351 19:56:54.047591 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1352 19:56:54.053507 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1353 19:56:54.057269 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1354 19:56:54.057822 ==
1355 19:56:54.060158 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 19:56:54.063782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 19:56:54.064248 ==
1358 19:56:54.064572 DQS Delay:
1359 19:56:54.067073 DQS0 = 0, DQS1 = 0
1360 19:56:54.067609 DQM Delay:
1361 19:56:54.070410 DQM0 = 79, DQM1 = 69
1362 19:56:54.070814 DQ Delay:
1363 19:56:54.073930 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1364 19:56:54.076939 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =92
1365 19:56:54.080315 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1366 19:56:54.084020 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =80
1367 19:56:54.084437
1368 19:56:54.084765
1369 19:56:54.093536 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
1370 19:56:54.094045 CH0 RK1: MR19=606, MR18=4D28
1371 19:56:54.101059 CH0_RK1: MR19=0x606, MR18=0x4D28, DQSOSC=390, MR23=63, INC=97, DEC=64
1372 19:56:54.103974 [RxdqsGatingPostProcess] freq 800
1373 19:56:54.111058 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 19:56:54.114161 Pre-setting of DQS Precalculation
1375 19:56:54.117459 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 19:56:54.118015 ==
1377 19:56:54.120121 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 19:56:54.123571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 19:56:54.127540 ==
1380 19:56:54.130816 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 19:56:54.137511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 19:56:54.146155 [CA 0] Center 36 (6~66) winsize 61
1383 19:56:54.149101 [CA 1] Center 36 (6~67) winsize 62
1384 19:56:54.152472 [CA 2] Center 34 (4~64) winsize 61
1385 19:56:54.155949 [CA 3] Center 33 (3~64) winsize 62
1386 19:56:54.159252 [CA 4] Center 34 (4~64) winsize 61
1387 19:56:54.162238 [CA 5] Center 33 (3~64) winsize 62
1388 19:56:54.162687
1389 19:56:54.166101 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1390 19:56:54.166659
1391 19:56:54.169018 [CATrainingPosCal] consider 1 rank data
1392 19:56:54.172806 u2DelayCellTimex100 = 270/100 ps
1393 19:56:54.175871 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1394 19:56:54.179212 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1395 19:56:54.182982 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1396 19:56:54.189346 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 19:56:54.192750 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1398 19:56:54.195646 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1399 19:56:54.196096
1400 19:56:54.199083 CA PerBit enable=1, Macro0, CA PI delay=33
1401 19:56:54.199675
1402 19:56:54.202275 [CBTSetCACLKResult] CA Dly = 33
1403 19:56:54.202757 CS Dly: 5 (0~36)
1404 19:56:54.203121 ==
1405 19:56:54.205466 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 19:56:54.213142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 19:56:54.213793 ==
1408 19:56:54.215877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 19:56:54.222339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 19:56:54.231840 [CA 0] Center 36 (6~67) winsize 62
1411 19:56:54.235438 [CA 1] Center 36 (6~67) winsize 62
1412 19:56:54.238323 [CA 2] Center 35 (5~65) winsize 61
1413 19:56:54.242099 [CA 3] Center 33 (3~64) winsize 62
1414 19:56:54.245329 [CA 4] Center 34 (4~65) winsize 62
1415 19:56:54.248326 [CA 5] Center 33 (3~64) winsize 62
1416 19:56:54.248889
1417 19:56:54.251723 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1418 19:56:54.252284
1419 19:56:54.255007 [CATrainingPosCal] consider 2 rank data
1420 19:56:54.258658 u2DelayCellTimex100 = 270/100 ps
1421 19:56:54.262014 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1422 19:56:54.265005 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1423 19:56:54.271707 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1424 19:56:54.274834 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 19:56:54.278319 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1426 19:56:54.282360 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1427 19:56:54.282890
1428 19:56:54.285793 CA PerBit enable=1, Macro0, CA PI delay=33
1429 19:56:54.286325
1430 19:56:54.289531 [CBTSetCACLKResult] CA Dly = 33
1431 19:56:54.290097 CS Dly: 6 (0~38)
1432 19:56:54.290470
1433 19:56:54.293327 ----->DramcWriteLeveling(PI) begin...
1434 19:56:54.293797 ==
1435 19:56:54.296688 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 19:56:54.300493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 19:56:54.300924 ==
1438 19:56:54.304037 Write leveling (Byte 0): 26 => 26
1439 19:56:54.307914 Write leveling (Byte 1): 28 => 28
1440 19:56:54.311532 DramcWriteLeveling(PI) end<-----
1441 19:56:54.311966
1442 19:56:54.312304 ==
1443 19:56:54.315124 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 19:56:54.319024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 19:56:54.319491 ==
1446 19:56:54.322192 [Gating] SW mode calibration
1447 19:56:54.328927 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 19:56:54.332049 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 19:56:54.339045 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 19:56:54.342568 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 19:56:54.345581 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1452 19:56:54.352305 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 19:56:54.355476 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 19:56:54.359456 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 19:56:54.361960 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 19:56:54.368985 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 19:56:54.372452 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 19:56:54.375622 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 19:56:54.382778 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 19:56:54.385765 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 19:56:54.389212 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 19:56:54.395698 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 19:56:54.399057 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 19:56:54.402658 0 7 28 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1465 19:56:54.409184 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 19:56:54.412291 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1467 19:56:54.415987 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1468 19:56:54.422172 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 19:56:54.425920 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 19:56:54.428875 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 19:56:54.435798 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 19:56:54.439156 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 19:56:54.442594 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 19:56:54.449158 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 19:56:54.451994 0 9 8 | B1->B0 | 2c2c 2525 | 1 0 | (0 0) (0 0)
1476 19:56:54.455555 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 19:56:54.462503 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 19:56:54.465768 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 19:56:54.468539 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 19:56:54.471999 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 19:56:54.478880 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 19:56:54.482680 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1483 19:56:54.485496 0 10 8 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
1484 19:56:54.492166 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 19:56:54.495984 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 19:56:54.499347 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 19:56:54.505350 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 19:56:54.508768 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 19:56:54.512272 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 19:56:54.518928 0 11 4 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
1491 19:56:54.522313 0 11 8 | B1->B0 | 4545 3636 | 0 0 | (0 0) (0 0)
1492 19:56:54.525314 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 19:56:54.532190 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 19:56:54.535893 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 19:56:54.539154 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 19:56:54.545402 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 19:56:54.549539 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 19:56:54.552118 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1499 19:56:54.558983 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 19:56:54.562787 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 19:56:54.565711 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 19:56:54.568654 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 19:56:54.575914 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 19:56:54.579219 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 19:56:54.582674 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 19:56:54.589118 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 19:56:54.592296 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 19:56:54.595894 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 19:56:54.602689 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 19:56:54.605661 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 19:56:54.609293 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 19:56:54.615441 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 19:56:54.619000 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 19:56:54.622872 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1515 19:56:54.629463 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 19:56:54.632602 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 19:56:54.635742 Total UI for P1: 0, mck2ui 16
1518 19:56:54.639361 best dqsien dly found for B0: ( 0, 14, 6)
1519 19:56:54.642513 Total UI for P1: 0, mck2ui 16
1520 19:56:54.645902 best dqsien dly found for B1: ( 0, 14, 6)
1521 19:56:54.648926 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1522 19:56:54.652118 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1523 19:56:54.652591
1524 19:56:54.655691 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 19:56:54.659046 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 19:56:54.662475 [Gating] SW calibration Done
1527 19:56:54.662927 ==
1528 19:56:54.665714 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 19:56:54.669176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 19:56:54.669730 ==
1531 19:56:54.672422 RX Vref Scan: 0
1532 19:56:54.672966
1533 19:56:54.673327 RX Vref 0 -> 0, step: 1
1534 19:56:54.673662
1535 19:56:54.676217 RX Delay -130 -> 252, step: 16
1536 19:56:54.682790 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1537 19:56:54.685750 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1538 19:56:54.689342 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1539 19:56:54.692837 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1540 19:56:54.696160 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1541 19:56:54.702655 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1542 19:56:54.705664 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1543 19:56:54.709085 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1544 19:56:54.712292 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1545 19:56:54.715659 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1546 19:56:54.719352 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1547 19:56:54.725323 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1548 19:56:54.728772 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1549 19:56:54.732776 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1550 19:56:54.735746 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1551 19:56:54.742643 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1552 19:56:54.743188 ==
1553 19:56:54.745764 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 19:56:54.749332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 19:56:54.749879 ==
1556 19:56:54.750251 DQS Delay:
1557 19:56:54.752237 DQS0 = 0, DQS1 = 0
1558 19:56:54.752717 DQM Delay:
1559 19:56:54.755953 DQM0 = 81, DQM1 = 72
1560 19:56:54.756405 DQ Delay:
1561 19:56:54.759072 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1562 19:56:54.762468 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1563 19:56:54.765860 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1564 19:56:54.769338 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1565 19:56:54.769793
1566 19:56:54.770151
1567 19:56:54.770484 ==
1568 19:56:54.772046 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 19:56:54.775741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 19:56:54.776292 ==
1571 19:56:54.776667
1572 19:56:54.777001
1573 19:56:54.779248 TX Vref Scan disable
1574 19:56:54.782556 == TX Byte 0 ==
1575 19:56:54.785823 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1576 19:56:54.789089 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1577 19:56:54.792007 == TX Byte 1 ==
1578 19:56:54.795452 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1579 19:56:54.798667 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1580 19:56:54.799077 ==
1581 19:56:54.802761 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 19:56:54.808990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 19:56:54.809502 ==
1584 19:56:54.820613 TX Vref=22, minBit 9, minWin=27, winSum=447
1585 19:56:54.823781 TX Vref=24, minBit 9, minWin=27, winSum=451
1586 19:56:54.827002 TX Vref=26, minBit 8, minWin=27, winSum=453
1587 19:56:54.830330 TX Vref=28, minBit 11, minWin=27, winSum=458
1588 19:56:54.833719 TX Vref=30, minBit 11, minWin=28, winSum=461
1589 19:56:54.840193 TX Vref=32, minBit 0, minWin=28, winSum=459
1590 19:56:54.843663 [TxChooseVref] Worse bit 11, Min win 28, Win sum 461, Final Vref 30
1591 19:56:54.844119
1592 19:56:54.847036 Final TX Range 1 Vref 30
1593 19:56:54.847500
1594 19:56:54.847838 ==
1595 19:56:54.850308 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 19:56:54.853789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 19:56:54.854373 ==
1598 19:56:54.856704
1599 19:56:54.857097
1600 19:56:54.857409 TX Vref Scan disable
1601 19:56:54.860840 == TX Byte 0 ==
1602 19:56:54.864553 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1603 19:56:54.868019 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1604 19:56:54.871148 == TX Byte 1 ==
1605 19:56:54.874892 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1606 19:56:54.878317 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1607 19:56:54.878783
1608 19:56:54.881060 [DATLAT]
1609 19:56:54.881468 Freq=800, CH1 RK0
1610 19:56:54.881793
1611 19:56:54.884744 DATLAT Default: 0xa
1612 19:56:54.885155 0, 0xFFFF, sum = 0
1613 19:56:54.887935 1, 0xFFFF, sum = 0
1614 19:56:54.888389 2, 0xFFFF, sum = 0
1615 19:56:54.891667 3, 0xFFFF, sum = 0
1616 19:56:54.892099 4, 0xFFFF, sum = 0
1617 19:56:54.894794 5, 0xFFFF, sum = 0
1618 19:56:54.895213 6, 0xFFFF, sum = 0
1619 19:56:54.898129 7, 0xFFFF, sum = 0
1620 19:56:54.898584 8, 0xFFFF, sum = 0
1621 19:56:54.901398 9, 0x0, sum = 1
1622 19:56:54.901817 10, 0x0, sum = 2
1623 19:56:54.904401 11, 0x0, sum = 3
1624 19:56:54.904819 12, 0x0, sum = 4
1625 19:56:54.907803 best_step = 10
1626 19:56:54.908215
1627 19:56:54.908545 ==
1628 19:56:54.911260 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 19:56:54.914799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 19:56:54.915216 ==
1631 19:56:54.915588 RX Vref Scan: 1
1632 19:56:54.918304
1633 19:56:54.918853 Set Vref Range= 32 -> 127
1634 19:56:54.919189
1635 19:56:54.921126 RX Vref 32 -> 127, step: 1
1636 19:56:54.921580
1637 19:56:54.924412 RX Delay -111 -> 252, step: 8
1638 19:56:54.924830
1639 19:56:54.928372 Set Vref, RX VrefLevel [Byte0]: 32
1640 19:56:54.930922 [Byte1]: 32
1641 19:56:54.931337
1642 19:56:54.934327 Set Vref, RX VrefLevel [Byte0]: 33
1643 19:56:54.937850 [Byte1]: 33
1644 19:56:54.941178
1645 19:56:54.941589 Set Vref, RX VrefLevel [Byte0]: 34
1646 19:56:54.944843 [Byte1]: 34
1647 19:56:54.948582
1648 19:56:54.948994 Set Vref, RX VrefLevel [Byte0]: 35
1649 19:56:54.952090 [Byte1]: 35
1650 19:56:54.956071
1651 19:56:54.956497 Set Vref, RX VrefLevel [Byte0]: 36
1652 19:56:54.959743 [Byte1]: 36
1653 19:56:54.964207
1654 19:56:54.964618 Set Vref, RX VrefLevel [Byte0]: 37
1655 19:56:54.968247 [Byte1]: 37
1656 19:56:54.971645
1657 19:56:54.972074 Set Vref, RX VrefLevel [Byte0]: 38
1658 19:56:54.975232 [Byte1]: 38
1659 19:56:54.978987
1660 19:56:54.979440 Set Vref, RX VrefLevel [Byte0]: 39
1661 19:56:54.982357 [Byte1]: 39
1662 19:56:54.986869
1663 19:56:54.987279 Set Vref, RX VrefLevel [Byte0]: 40
1664 19:56:54.990105 [Byte1]: 40
1665 19:56:54.995030
1666 19:56:54.995510 Set Vref, RX VrefLevel [Byte0]: 41
1667 19:56:54.997859 [Byte1]: 41
1668 19:56:55.002092
1669 19:56:55.002504 Set Vref, RX VrefLevel [Byte0]: 42
1670 19:56:55.006038 [Byte1]: 42
1671 19:56:55.010183
1672 19:56:55.010701 Set Vref, RX VrefLevel [Byte0]: 43
1673 19:56:55.013295 [Byte1]: 43
1674 19:56:55.017563
1675 19:56:55.018079 Set Vref, RX VrefLevel [Byte0]: 44
1676 19:56:55.020888 [Byte1]: 44
1677 19:56:55.025015
1678 19:56:55.025538 Set Vref, RX VrefLevel [Byte0]: 45
1679 19:56:55.028277 [Byte1]: 45
1680 19:56:55.032655
1681 19:56:55.033069 Set Vref, RX VrefLevel [Byte0]: 46
1682 19:56:55.036069 [Byte1]: 46
1683 19:56:55.040491
1684 19:56:55.040904 Set Vref, RX VrefLevel [Byte0]: 47
1685 19:56:55.043662 [Byte1]: 47
1686 19:56:55.048234
1687 19:56:55.048761 Set Vref, RX VrefLevel [Byte0]: 48
1688 19:56:55.051903 [Byte1]: 48
1689 19:56:55.056166
1690 19:56:55.056580 Set Vref, RX VrefLevel [Byte0]: 49
1691 19:56:55.059492 [Byte1]: 49
1692 19:56:55.063666
1693 19:56:55.064188 Set Vref, RX VrefLevel [Byte0]: 50
1694 19:56:55.066491 [Byte1]: 50
1695 19:56:55.071124
1696 19:56:55.074467 Set Vref, RX VrefLevel [Byte0]: 51
1697 19:56:55.074884 [Byte1]: 51
1698 19:56:55.078995
1699 19:56:55.079437 Set Vref, RX VrefLevel [Byte0]: 52
1700 19:56:55.082169 [Byte1]: 52
1701 19:56:55.086098
1702 19:56:55.086509 Set Vref, RX VrefLevel [Byte0]: 53
1703 19:56:55.090058 [Byte1]: 53
1704 19:56:55.094440
1705 19:56:55.094855 Set Vref, RX VrefLevel [Byte0]: 54
1706 19:56:55.097259 [Byte1]: 54
1707 19:56:55.101605
1708 19:56:55.102017 Set Vref, RX VrefLevel [Byte0]: 55
1709 19:56:55.104789 [Byte1]: 55
1710 19:56:55.109328
1711 19:56:55.109741 Set Vref, RX VrefLevel [Byte0]: 56
1712 19:56:55.112462 [Byte1]: 56
1713 19:56:55.117182
1714 19:56:55.117593 Set Vref, RX VrefLevel [Byte0]: 57
1715 19:56:55.120146 [Byte1]: 57
1716 19:56:55.124601
1717 19:56:55.125013 Set Vref, RX VrefLevel [Byte0]: 58
1718 19:56:55.127879 [Byte1]: 58
1719 19:56:55.132086
1720 19:56:55.132495 Set Vref, RX VrefLevel [Byte0]: 59
1721 19:56:55.135590 [Byte1]: 59
1722 19:56:55.139965
1723 19:56:55.140373 Set Vref, RX VrefLevel [Byte0]: 60
1724 19:56:55.143281 [Byte1]: 60
1725 19:56:55.147444
1726 19:56:55.147826 Set Vref, RX VrefLevel [Byte0]: 61
1727 19:56:55.150903 [Byte1]: 61
1728 19:56:55.155214
1729 19:56:55.155688 Set Vref, RX VrefLevel [Byte0]: 62
1730 19:56:55.158254 [Byte1]: 62
1731 19:56:55.162499
1732 19:56:55.162911 Set Vref, RX VrefLevel [Byte0]: 63
1733 19:56:55.165988 [Byte1]: 63
1734 19:56:55.170209
1735 19:56:55.170762 Set Vref, RX VrefLevel [Byte0]: 64
1736 19:56:55.173869 [Byte1]: 64
1737 19:56:55.178328
1738 19:56:55.178740 Set Vref, RX VrefLevel [Byte0]: 65
1739 19:56:55.181569 [Byte1]: 65
1740 19:56:55.186131
1741 19:56:55.186663 Set Vref, RX VrefLevel [Byte0]: 66
1742 19:56:55.189375 [Byte1]: 66
1743 19:56:55.193838
1744 19:56:55.194355 Set Vref, RX VrefLevel [Byte0]: 67
1745 19:56:55.197086 [Byte1]: 67
1746 19:56:55.201932
1747 19:56:55.202451 Set Vref, RX VrefLevel [Byte0]: 68
1748 19:56:55.204189 [Byte1]: 68
1749 19:56:55.208660
1750 19:56:55.209173 Set Vref, RX VrefLevel [Byte0]: 69
1751 19:56:55.211814 [Byte1]: 69
1752 19:56:55.216260
1753 19:56:55.216776 Set Vref, RX VrefLevel [Byte0]: 70
1754 19:56:55.219870 [Byte1]: 70
1755 19:56:55.223903
1756 19:56:55.224314 Set Vref, RX VrefLevel [Byte0]: 71
1757 19:56:55.227601 [Byte1]: 71
1758 19:56:55.231837
1759 19:56:55.232250 Set Vref, RX VrefLevel [Byte0]: 72
1760 19:56:55.234839 [Byte1]: 72
1761 19:56:55.239558
1762 19:56:55.240083 Set Vref, RX VrefLevel [Byte0]: 73
1763 19:56:55.242600 [Byte1]: 73
1764 19:56:55.247549
1765 19:56:55.248065 Set Vref, RX VrefLevel [Byte0]: 74
1766 19:56:55.250610 [Byte1]: 74
1767 19:56:55.255096
1768 19:56:55.255667 Set Vref, RX VrefLevel [Byte0]: 75
1769 19:56:55.257797 [Byte1]: 75
1770 19:56:55.262573
1771 19:56:55.263110 Set Vref, RX VrefLevel [Byte0]: 76
1772 19:56:55.265376 [Byte1]: 76
1773 19:56:55.269607
1774 19:56:55.270159 Final RX Vref Byte 0 = 55 to rank0
1775 19:56:55.272897 Final RX Vref Byte 1 = 53 to rank0
1776 19:56:55.276797 Final RX Vref Byte 0 = 55 to rank1
1777 19:56:55.280140 Final RX Vref Byte 1 = 53 to rank1==
1778 19:56:55.283338 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 19:56:55.289953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 19:56:55.290475 ==
1781 19:56:55.290816 DQS Delay:
1782 19:56:55.291126 DQS0 = 0, DQS1 = 0
1783 19:56:55.293483 DQM Delay:
1784 19:56:55.293997 DQM0 = 80, DQM1 = 71
1785 19:56:55.296769 DQ Delay:
1786 19:56:55.300303 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1787 19:56:55.300838 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1788 19:56:55.303582 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1789 19:56:55.306809 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1790 19:56:55.310340
1791 19:56:55.310855
1792 19:56:55.316413 [DQSOSCAuto] RK0, (LSB)MR18= 0x101a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1793 19:56:55.319752 CH1 RK0: MR19=606, MR18=101A
1794 19:56:55.326568 CH1_RK0: MR19=0x606, MR18=0x101A, DQSOSC=403, MR23=63, INC=90, DEC=60
1795 19:56:55.326983
1796 19:56:55.330268 ----->DramcWriteLeveling(PI) begin...
1797 19:56:55.330806 ==
1798 19:56:55.333780 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 19:56:55.336679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 19:56:55.337094 ==
1801 19:56:55.340045 Write leveling (Byte 0): 28 => 28
1802 19:56:55.343195 Write leveling (Byte 1): 30 => 30
1803 19:56:55.346652 DramcWriteLeveling(PI) end<-----
1804 19:56:55.347198
1805 19:56:55.347590 ==
1806 19:56:55.350530 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 19:56:55.353501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 19:56:55.354017 ==
1809 19:56:55.356633 [Gating] SW mode calibration
1810 19:56:55.363352 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 19:56:55.369969 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 19:56:55.373543 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1813 19:56:55.377028 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1814 19:56:55.383256 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1815 19:56:55.386705 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 19:56:55.390123 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 19:56:55.396612 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 19:56:55.400266 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 19:56:55.403550 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 19:56:55.410173 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 19:56:55.413952 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 19:56:55.416892 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 19:56:55.420112 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 19:56:55.426795 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 19:56:55.429964 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 19:56:55.433194 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 19:56:55.439705 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 19:56:55.443504 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1829 19:56:55.447084 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 19:56:55.453583 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1831 19:56:55.456415 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 19:56:55.459906 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 19:56:55.466624 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 19:56:55.470295 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 19:56:55.474111 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 19:56:55.480145 0 9 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1837 19:56:55.483531 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
1838 19:56:55.486813 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1839 19:56:55.493514 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 19:56:55.496712 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 19:56:55.500045 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 19:56:55.506498 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 19:56:55.509986 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 19:56:55.513010 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1845 19:56:55.516874 0 10 4 | B1->B0 | 3030 2929 | 1 1 | (1 1) (1 0)
1846 19:56:55.523226 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1847 19:56:55.526821 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 19:56:55.530124 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 19:56:55.536450 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 19:56:55.539960 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 19:56:55.542902 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 19:56:55.550176 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1853 19:56:55.553477 0 11 4 | B1->B0 | 3131 3737 | 0 0 | (0 0) (0 0)
1854 19:56:55.556281 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 19:56:55.563076 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 19:56:55.566785 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 19:56:55.569725 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 19:56:55.576256 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 19:56:55.579859 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 19:56:55.583290 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 19:56:55.590252 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1862 19:56:55.593141 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1863 19:56:55.596652 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 19:56:55.602999 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 19:56:55.606276 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 19:56:55.610183 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 19:56:55.616505 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 19:56:55.620033 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 19:56:55.623530 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 19:56:55.630185 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 19:56:55.632808 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 19:56:55.636323 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 19:56:55.639924 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 19:56:55.646553 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 19:56:55.649667 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 19:56:55.653234 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1877 19:56:55.659486 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 19:56:55.663049 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1879 19:56:55.666811 Total UI for P1: 0, mck2ui 16
1880 19:56:55.669966 best dqsien dly found for B0: ( 0, 14, 6)
1881 19:56:55.672903 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 19:56:55.676549 Total UI for P1: 0, mck2ui 16
1883 19:56:55.680334 best dqsien dly found for B1: ( 0, 14, 8)
1884 19:56:55.683501 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1885 19:56:55.686533 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1886 19:56:55.687084
1887 19:56:55.692857 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1888 19:56:55.696387 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1889 19:56:55.696959 [Gating] SW calibration Done
1890 19:56:55.700044 ==
1891 19:56:55.702893 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 19:56:55.706653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 19:56:55.707157 ==
1894 19:56:55.707573 RX Vref Scan: 0
1895 19:56:55.707921
1896 19:56:55.709851 RX Vref 0 -> 0, step: 1
1897 19:56:55.710305
1898 19:56:55.713359 RX Delay -130 -> 252, step: 16
1899 19:56:55.716050 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1900 19:56:55.719838 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1901 19:56:55.723051 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1902 19:56:55.729962 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1903 19:56:55.733075 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1904 19:56:55.736587 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1905 19:56:55.739858 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1906 19:56:55.743151 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1907 19:56:55.750008 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1908 19:56:55.752885 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1909 19:56:55.756398 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1910 19:56:55.759937 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1911 19:56:55.763194 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1912 19:56:55.769451 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1913 19:56:55.772728 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1914 19:56:55.776602 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1915 19:56:55.777060 ==
1916 19:56:55.780087 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 19:56:55.782642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 19:56:55.783104 ==
1919 19:56:55.786076 DQS Delay:
1920 19:56:55.786552 DQS0 = 0, DQS1 = 0
1921 19:56:55.789509 DQM Delay:
1922 19:56:55.789922 DQM0 = 80, DQM1 = 74
1923 19:56:55.790249 DQ Delay:
1924 19:56:55.792758 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1925 19:56:55.795912 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1926 19:56:55.799224 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1927 19:56:55.803075 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
1928 19:56:55.803520
1929 19:56:55.803848
1930 19:56:55.806270 ==
1931 19:56:55.809449 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 19:56:55.812603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 19:56:55.813023 ==
1934 19:56:55.813353
1935 19:56:55.813658
1936 19:56:55.816021 TX Vref Scan disable
1937 19:56:55.816433 == TX Byte 0 ==
1938 19:56:55.819889 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1939 19:56:55.826273 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1940 19:56:55.826796 == TX Byte 1 ==
1941 19:56:55.829462 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1942 19:56:55.836302 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1943 19:56:55.836719 ==
1944 19:56:55.839692 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 19:56:55.843693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 19:56:55.844109 ==
1947 19:56:55.856428 TX Vref=22, minBit 3, minWin=27, winSum=448
1948 19:56:55.859471 TX Vref=24, minBit 0, minWin=28, winSum=454
1949 19:56:55.862917 TX Vref=26, minBit 0, minWin=28, winSum=453
1950 19:56:55.865939 TX Vref=28, minBit 4, minWin=28, winSum=458
1951 19:56:55.869605 TX Vref=30, minBit 2, minWin=28, winSum=458
1952 19:56:55.875998 TX Vref=32, minBit 0, minWin=28, winSum=452
1953 19:56:55.879663 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 28
1954 19:56:55.880221
1955 19:56:55.882701 Final TX Range 1 Vref 28
1956 19:56:55.883157
1957 19:56:55.883558 ==
1958 19:56:55.885979 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 19:56:55.889293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 19:56:55.889812 ==
1961 19:56:55.892380
1962 19:56:55.892879
1963 19:56:55.893210 TX Vref Scan disable
1964 19:56:55.896204 == TX Byte 0 ==
1965 19:56:55.899428 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1966 19:56:55.906009 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1967 19:56:55.906530 == TX Byte 1 ==
1968 19:56:55.909221 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1969 19:56:55.916067 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1970 19:56:55.916523
1971 19:56:55.916885 [DATLAT]
1972 19:56:55.917222 Freq=800, CH1 RK1
1973 19:56:55.917549
1974 19:56:55.919119 DATLAT Default: 0xa
1975 19:56:55.919566 0, 0xFFFF, sum = 0
1976 19:56:55.922512 1, 0xFFFF, sum = 0
1977 19:56:55.922930 2, 0xFFFF, sum = 0
1978 19:56:55.925751 3, 0xFFFF, sum = 0
1979 19:56:55.929005 4, 0xFFFF, sum = 0
1980 19:56:55.929425 5, 0xFFFF, sum = 0
1981 19:56:55.932289 6, 0xFFFF, sum = 0
1982 19:56:55.932885 7, 0xFFFF, sum = 0
1983 19:56:55.935427 8, 0xFFFF, sum = 0
1984 19:56:55.935863 9, 0x0, sum = 1
1985 19:56:55.939494 10, 0x0, sum = 2
1986 19:56:55.939916 11, 0x0, sum = 3
1987 19:56:55.940561 12, 0x0, sum = 4
1988 19:56:55.942307 best_step = 10
1989 19:56:55.942717
1990 19:56:55.943040 ==
1991 19:56:55.945918 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 19:56:55.949183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 19:56:55.949602 ==
1994 19:56:55.952584 RX Vref Scan: 0
1995 19:56:55.953110
1996 19:56:55.953445 RX Vref 0 -> 0, step: 1
1997 19:56:55.956082
1998 19:56:55.956495 RX Delay -111 -> 252, step: 8
1999 19:56:55.962690 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2000 19:56:55.966290 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2001 19:56:55.969544 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2002 19:56:55.972670 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2003 19:56:55.975739 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2004 19:56:55.982754 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2005 19:56:55.986031 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2006 19:56:55.989281 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2007 19:56:55.992819 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2008 19:56:55.996592 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2009 19:56:56.002854 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2010 19:56:56.006043 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2011 19:56:56.009363 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2012 19:56:56.012909 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2013 19:56:56.016141 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2014 19:56:56.023209 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2015 19:56:56.023780 ==
2016 19:56:56.026033 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 19:56:56.029181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 19:56:56.029603 ==
2019 19:56:56.029937 DQS Delay:
2020 19:56:56.032760 DQS0 = 0, DQS1 = 0
2021 19:56:56.033279 DQM Delay:
2022 19:56:56.035844 DQM0 = 77, DQM1 = 72
2023 19:56:56.036260 DQ Delay:
2024 19:56:56.039486 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2025 19:56:56.042846 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2026 19:56:56.046615 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =64
2027 19:56:56.050025 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
2028 19:56:56.050543
2029 19:56:56.050875
2030 19:56:56.059344 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2031 19:56:56.059789 CH1 RK1: MR19=606, MR18=2139
2032 19:56:56.065824 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2033 19:56:56.070244 [RxdqsGatingPostProcess] freq 800
2034 19:56:56.076379 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 19:56:56.079448 Pre-setting of DQS Precalculation
2036 19:56:56.082689 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 19:56:56.089554 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 19:56:56.096028 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 19:56:56.096595
2040 19:56:56.096956
2041 19:56:56.099870 [Calibration Summary] 1600 Mbps
2042 19:56:56.102888 CH 0, Rank 0
2043 19:56:56.103344 SW Impedance : PASS
2044 19:56:56.105939 DUTY Scan : NO K
2045 19:56:56.109388 ZQ Calibration : PASS
2046 19:56:56.109844 Jitter Meter : NO K
2047 19:56:56.113043 CBT Training : PASS
2048 19:56:56.116616 Write leveling : PASS
2049 19:56:56.117074 RX DQS gating : PASS
2050 19:56:56.119176 RX DQ/DQS(RDDQC) : PASS
2051 19:56:56.122716 TX DQ/DQS : PASS
2052 19:56:56.123174 RX DATLAT : PASS
2053 19:56:56.126479 RX DQ/DQS(Engine): PASS
2054 19:56:56.126932 TX OE : NO K
2055 19:56:56.129192 All Pass.
2056 19:56:56.129604
2057 19:56:56.129933 CH 0, Rank 1
2058 19:56:56.132754 SW Impedance : PASS
2059 19:56:56.133302 DUTY Scan : NO K
2060 19:56:56.136203 ZQ Calibration : PASS
2061 19:56:56.139259 Jitter Meter : NO K
2062 19:56:56.139753 CBT Training : PASS
2063 19:56:56.142577 Write leveling : PASS
2064 19:56:56.146350 RX DQS gating : PASS
2065 19:56:56.146887 RX DQ/DQS(RDDQC) : PASS
2066 19:56:56.149578 TX DQ/DQS : PASS
2067 19:56:56.153174 RX DATLAT : PASS
2068 19:56:56.153693 RX DQ/DQS(Engine): PASS
2069 19:56:56.155916 TX OE : NO K
2070 19:56:56.156332 All Pass.
2071 19:56:56.156662
2072 19:56:56.160080 CH 1, Rank 0
2073 19:56:56.160604 SW Impedance : PASS
2074 19:56:56.162941 DUTY Scan : NO K
2075 19:56:56.165997 ZQ Calibration : PASS
2076 19:56:56.166413 Jitter Meter : NO K
2077 19:56:56.169428 CBT Training : PASS
2078 19:56:56.169845 Write leveling : PASS
2079 19:56:56.172742 RX DQS gating : PASS
2080 19:56:56.176490 RX DQ/DQS(RDDQC) : PASS
2081 19:56:56.177022 TX DQ/DQS : PASS
2082 19:56:56.179422 RX DATLAT : PASS
2083 19:56:56.183075 RX DQ/DQS(Engine): PASS
2084 19:56:56.183627 TX OE : NO K
2085 19:56:56.186083 All Pass.
2086 19:56:56.186492
2087 19:56:56.186816 CH 1, Rank 1
2088 19:56:56.189394 SW Impedance : PASS
2089 19:56:56.189807 DUTY Scan : NO K
2090 19:56:56.192794 ZQ Calibration : PASS
2091 19:56:56.196637 Jitter Meter : NO K
2092 19:56:56.197160 CBT Training : PASS
2093 19:56:56.200289 Write leveling : PASS
2094 19:56:56.200811 RX DQS gating : PASS
2095 19:56:56.203317 RX DQ/DQS(RDDQC) : PASS
2096 19:56:56.206553 TX DQ/DQS : PASS
2097 19:56:56.207082 RX DATLAT : PASS
2098 19:56:56.209917 RX DQ/DQS(Engine): PASS
2099 19:56:56.213251 TX OE : NO K
2100 19:56:56.213665 All Pass.
2101 19:56:56.213995
2102 19:56:56.216366 DramC Write-DBI off
2103 19:56:56.216777 PER_BANK_REFRESH: Hybrid Mode
2104 19:56:56.219811 TX_TRACKING: ON
2105 19:56:56.223216 [GetDramInforAfterCalByMRR] Vendor 6.
2106 19:56:56.226370 [GetDramInforAfterCalByMRR] Revision 606.
2107 19:56:56.229405 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 19:56:56.229822 MR0 0x3b3b
2109 19:56:56.232891 MR8 0x5151
2110 19:56:56.236025 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 19:56:56.236447
2112 19:56:56.236781 MR0 0x3b3b
2113 19:56:56.239335 MR8 0x5151
2114 19:56:56.243192 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 19:56:56.243752
2116 19:56:56.249349 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 19:56:56.252899 [FAST_K] Save calibration result to emmc
2118 19:56:56.259613 [FAST_K] Save calibration result to emmc
2119 19:56:56.260176 dram_init: config_dvfs: 1
2120 19:56:56.262943 dramc_set_vcore_voltage set vcore to 662500
2121 19:56:56.266195 Read voltage for 1200, 2
2122 19:56:56.266653 Vio18 = 0
2123 19:56:56.269073 Vcore = 662500
2124 19:56:56.269527 Vdram = 0
2125 19:56:56.269934 Vddq = 0
2126 19:56:56.272520 Vmddr = 0
2127 19:56:56.275859 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 19:56:56.282894 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 19:56:56.283474 MEM_TYPE=3, freq_sel=15
2130 19:56:56.286477 sv_algorithm_assistance_LP4_1600
2131 19:56:56.292312 ============ PULL DRAM RESETB DOWN ============
2132 19:56:56.295919 ========== PULL DRAM RESETB DOWN end =========
2133 19:56:56.299669 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 19:56:56.302407 ===================================
2135 19:56:56.305682 LPDDR4 DRAM CONFIGURATION
2136 19:56:56.308988 ===================================
2137 19:56:56.312344 EX_ROW_EN[0] = 0x0
2138 19:56:56.312846 EX_ROW_EN[1] = 0x0
2139 19:56:56.315885 LP4Y_EN = 0x0
2140 19:56:56.316307 WORK_FSP = 0x0
2141 19:56:56.319219 WL = 0x4
2142 19:56:56.319856 RL = 0x4
2143 19:56:56.322492 BL = 0x2
2144 19:56:56.322915 RPST = 0x0
2145 19:56:56.325961 RD_PRE = 0x0
2146 19:56:56.326484 WR_PRE = 0x1
2147 19:56:56.329017 WR_PST = 0x0
2148 19:56:56.329444 DBI_WR = 0x0
2149 19:56:56.332307 DBI_RD = 0x0
2150 19:56:56.332729 OTF = 0x1
2151 19:56:56.335596 ===================================
2152 19:56:56.339022 ===================================
2153 19:56:56.342525 ANA top config
2154 19:56:56.345600 ===================================
2155 19:56:56.346031 DLL_ASYNC_EN = 0
2156 19:56:56.348926 ALL_SLAVE_EN = 0
2157 19:56:56.353018 NEW_RANK_MODE = 1
2158 19:56:56.356186 DLL_IDLE_MODE = 1
2159 19:56:56.359360 LP45_APHY_COMB_EN = 1
2160 19:56:56.359805 TX_ODT_DIS = 1
2161 19:56:56.362530 NEW_8X_MODE = 1
2162 19:56:56.365863 ===================================
2163 19:56:56.369520 ===================================
2164 19:56:56.372546 data_rate = 2400
2165 19:56:56.375975 CKR = 1
2166 19:56:56.379736 DQ_P2S_RATIO = 8
2167 19:56:56.383004 ===================================
2168 19:56:56.383555 CA_P2S_RATIO = 8
2169 19:56:56.386267 DQ_CA_OPEN = 0
2170 19:56:56.389539 DQ_SEMI_OPEN = 0
2171 19:56:56.392298 CA_SEMI_OPEN = 0
2172 19:56:56.396129 CA_FULL_RATE = 0
2173 19:56:56.399484 DQ_CKDIV4_EN = 0
2174 19:56:56.400043 CA_CKDIV4_EN = 0
2175 19:56:56.402616 CA_PREDIV_EN = 0
2176 19:56:56.406050 PH8_DLY = 17
2177 19:56:56.409456 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 19:56:56.412720 DQ_AAMCK_DIV = 4
2179 19:56:56.416272 CA_AAMCK_DIV = 4
2180 19:56:56.416924 CA_ADMCK_DIV = 4
2181 19:56:56.419595 DQ_TRACK_CA_EN = 0
2182 19:56:56.422586 CA_PICK = 1200
2183 19:56:56.426595 CA_MCKIO = 1200
2184 19:56:56.429137 MCKIO_SEMI = 0
2185 19:56:56.432752 PLL_FREQ = 2366
2186 19:56:56.435912 DQ_UI_PI_RATIO = 32
2187 19:56:56.436372 CA_UI_PI_RATIO = 0
2188 19:56:56.439271 ===================================
2189 19:56:56.443130 ===================================
2190 19:56:56.446305 memory_type:LPDDR4
2191 19:56:56.449415 GP_NUM : 10
2192 19:56:56.449949 SRAM_EN : 1
2193 19:56:56.452648 MD32_EN : 0
2194 19:56:56.455979 ===================================
2195 19:56:56.459209 [ANA_INIT] >>>>>>>>>>>>>>
2196 19:56:56.462959 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 19:56:56.466194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 19:56:56.469196 ===================================
2199 19:56:56.469613 data_rate = 2400,PCW = 0X5b00
2200 19:56:56.472564 ===================================
2201 19:56:56.475672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 19:56:56.482686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 19:56:56.489496 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 19:56:56.492555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 19:56:56.496099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 19:56:56.499473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 19:56:56.502983 [ANA_INIT] flow start
2208 19:56:56.503590 [ANA_INIT] PLL >>>>>>>>
2209 19:56:56.506482 [ANA_INIT] PLL <<<<<<<<
2210 19:56:56.509520 [ANA_INIT] MIDPI >>>>>>>>
2211 19:56:56.512993 [ANA_INIT] MIDPI <<<<<<<<
2212 19:56:56.513551 [ANA_INIT] DLL >>>>>>>>
2213 19:56:56.516074 [ANA_INIT] DLL <<<<<<<<
2214 19:56:56.516527 [ANA_INIT] flow end
2215 19:56:56.522792 ============ LP4 DIFF to SE enter ============
2216 19:56:56.525772 ============ LP4 DIFF to SE exit ============
2217 19:56:56.529453 [ANA_INIT] <<<<<<<<<<<<<
2218 19:56:56.532399 [Flow] Enable top DCM control >>>>>
2219 19:56:56.536385 [Flow] Enable top DCM control <<<<<
2220 19:56:56.536945 Enable DLL master slave shuffle
2221 19:56:56.542901 ==============================================================
2222 19:56:56.545836 Gating Mode config
2223 19:56:56.549796 ==============================================================
2224 19:56:56.552539 Config description:
2225 19:56:56.562883 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 19:56:56.568863 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 19:56:56.572033 SELPH_MODE 0: By rank 1: By Phase
2228 19:56:56.579099 ==============================================================
2229 19:56:56.582670 GAT_TRACK_EN = 1
2230 19:56:56.586099 RX_GATING_MODE = 2
2231 19:56:56.589752 RX_GATING_TRACK_MODE = 2
2232 19:56:56.593010 SELPH_MODE = 1
2233 19:56:56.593568 PICG_EARLY_EN = 1
2234 19:56:56.596031 VALID_LAT_VALUE = 1
2235 19:56:56.602963 ==============================================================
2236 19:56:56.606239 Enter into Gating configuration >>>>
2237 19:56:56.609126 Exit from Gating configuration <<<<
2238 19:56:56.612550 Enter into DVFS_PRE_config >>>>>
2239 19:56:56.622580 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 19:56:56.625867 Exit from DVFS_PRE_config <<<<<
2241 19:56:56.629201 Enter into PICG configuration >>>>
2242 19:56:56.632787 Exit from PICG configuration <<<<
2243 19:56:56.635776 [RX_INPUT] configuration >>>>>
2244 19:56:56.638988 [RX_INPUT] configuration <<<<<
2245 19:56:56.642248 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 19:56:56.649244 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 19:56:56.655521 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 19:56:56.662035 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 19:56:56.668996 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 19:56:56.672851 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 19:56:56.679366 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 19:56:56.682067 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 19:56:56.685954 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 19:56:56.689138 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 19:56:56.695683 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 19:56:56.698853 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 19:56:56.702212 ===================================
2258 19:56:56.705841 LPDDR4 DRAM CONFIGURATION
2259 19:56:56.708933 ===================================
2260 19:56:56.709394 EX_ROW_EN[0] = 0x0
2261 19:56:56.712073 EX_ROW_EN[1] = 0x0
2262 19:56:56.712529 LP4Y_EN = 0x0
2263 19:56:56.715720 WORK_FSP = 0x0
2264 19:56:56.716269 WL = 0x4
2265 19:56:56.719329 RL = 0x4
2266 19:56:56.719922 BL = 0x2
2267 19:56:56.722438 RPST = 0x0
2268 19:56:56.722992 RD_PRE = 0x0
2269 19:56:56.725433 WR_PRE = 0x1
2270 19:56:56.725891 WR_PST = 0x0
2271 19:56:56.728844 DBI_WR = 0x0
2272 19:56:56.729299 DBI_RD = 0x0
2273 19:56:56.732124 OTF = 0x1
2274 19:56:56.735473 ===================================
2275 19:56:56.739025 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 19:56:56.742523 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 19:56:56.748770 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 19:56:56.752226 ===================================
2279 19:56:56.752643 LPDDR4 DRAM CONFIGURATION
2280 19:56:56.755510 ===================================
2281 19:56:56.758815 EX_ROW_EN[0] = 0x10
2282 19:56:56.761982 EX_ROW_EN[1] = 0x0
2283 19:56:56.762431 LP4Y_EN = 0x0
2284 19:56:56.765244 WORK_FSP = 0x0
2285 19:56:56.765655 WL = 0x4
2286 19:56:56.769402 RL = 0x4
2287 19:56:56.769934 BL = 0x2
2288 19:56:56.772142 RPST = 0x0
2289 19:56:56.772649 RD_PRE = 0x0
2290 19:56:56.775516 WR_PRE = 0x1
2291 19:56:56.775931 WR_PST = 0x0
2292 19:56:56.778961 DBI_WR = 0x0
2293 19:56:56.779370 DBI_RD = 0x0
2294 19:56:56.782200 OTF = 0x1
2295 19:56:56.785357 ===================================
2296 19:56:56.792208 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 19:56:56.792621 ==
2298 19:56:56.795204 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 19:56:56.798641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 19:56:56.799055 ==
2301 19:56:56.801921 [Duty_Offset_Calibration]
2302 19:56:56.802332 B0:2 B1:0 CA:3
2303 19:56:56.802657
2304 19:56:56.805719 [DutyScan_Calibration_Flow] k_type=0
2305 19:56:56.815928
2306 19:56:56.816457 ==CLK 0==
2307 19:56:56.818935 Final CLK duty delay cell = 0
2308 19:56:56.822651 [0] MAX Duty = 5062%(X100), DQS PI = 20
2309 19:56:56.825529 [0] MIN Duty = 4875%(X100), DQS PI = 58
2310 19:56:56.826039 [0] AVG Duty = 4968%(X100)
2311 19:56:56.828667
2312 19:56:56.832229 CH0 CLK Duty spec in!! Max-Min= 187%
2313 19:56:56.835128 [DutyScan_Calibration_Flow] ====Done====
2314 19:56:56.835594
2315 19:56:56.838957 [DutyScan_Calibration_Flow] k_type=1
2316 19:56:56.854026
2317 19:56:56.854571 ==DQS 0 ==
2318 19:56:56.857959 Final DQS duty delay cell = 0
2319 19:56:56.860328 [0] MAX Duty = 5093%(X100), DQS PI = 28
2320 19:56:56.863934 [0] MIN Duty = 4907%(X100), DQS PI = 44
2321 19:56:56.868193 [0] AVG Duty = 5000%(X100)
2322 19:56:56.868698
2323 19:56:56.869057 ==DQS 1 ==
2324 19:56:56.870458 Final DQS duty delay cell = -4
2325 19:56:56.874714 [-4] MAX Duty = 4969%(X100), DQS PI = 6
2326 19:56:56.877317 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2327 19:56:56.881224 [-4] AVG Duty = 4922%(X100)
2328 19:56:56.881733
2329 19:56:56.884283 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2330 19:56:56.884792
2331 19:56:56.886983 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2332 19:56:56.890299 [DutyScan_Calibration_Flow] ====Done====
2333 19:56:56.890709
2334 19:56:56.893473 [DutyScan_Calibration_Flow] k_type=3
2335 19:56:56.911381
2336 19:56:56.911974 ==DQM 0 ==
2337 19:56:56.914754 Final DQM duty delay cell = 0
2338 19:56:56.917859 [0] MAX Duty = 5124%(X100), DQS PI = 28
2339 19:56:56.921645 [0] MIN Duty = 4907%(X100), DQS PI = 0
2340 19:56:56.922203 [0] AVG Duty = 5015%(X100)
2341 19:56:56.924904
2342 19:56:56.925496 ==DQM 1 ==
2343 19:56:56.927959 Final DQM duty delay cell = 4
2344 19:56:56.931280 [4] MAX Duty = 5124%(X100), DQS PI = 0
2345 19:56:56.934991 [4] MIN Duty = 5000%(X100), DQS PI = 32
2346 19:56:56.935542 [4] AVG Duty = 5062%(X100)
2347 19:56:56.938153
2348 19:56:56.941514 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2349 19:56:56.942073
2350 19:56:56.945143 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2351 19:56:56.947858 [DutyScan_Calibration_Flow] ====Done====
2352 19:56:56.948314
2353 19:56:56.951455 [DutyScan_Calibration_Flow] k_type=2
2354 19:56:56.966381
2355 19:56:56.966943 ==DQ 0 ==
2356 19:56:56.969524 Final DQ duty delay cell = -4
2357 19:56:56.973241 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2358 19:56:56.976346 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2359 19:56:56.979289 [-4] AVG Duty = 4969%(X100)
2360 19:56:56.979766
2361 19:56:56.980125 ==DQ 1 ==
2362 19:56:56.982892 Final DQ duty delay cell = -4
2363 19:56:56.986401 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2364 19:56:56.989777 [-4] MIN Duty = 4907%(X100), DQS PI = 18
2365 19:56:56.992762 [-4] AVG Duty = 4953%(X100)
2366 19:56:56.993220
2367 19:56:56.995953 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2368 19:56:56.996412
2369 19:56:56.999051 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2370 19:56:57.002562 [DutyScan_Calibration_Flow] ====Done====
2371 19:56:57.002975 ==
2372 19:56:57.005646 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 19:56:57.008822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 19:56:57.009268 ==
2375 19:56:57.012269 [Duty_Offset_Calibration]
2376 19:56:57.012678 B0:1 B1:-2 CA:0
2377 19:56:57.013012
2378 19:56:57.015659 [DutyScan_Calibration_Flow] k_type=0
2379 19:56:57.026542
2380 19:56:57.027040 ==CLK 0==
2381 19:56:57.029736 Final CLK duty delay cell = 0
2382 19:56:57.033064 [0] MAX Duty = 5062%(X100), DQS PI = 30
2383 19:56:57.036970 [0] MIN Duty = 4876%(X100), DQS PI = 2
2384 19:56:57.037507 [0] AVG Duty = 4969%(X100)
2385 19:56:57.040037
2386 19:56:57.040463 CH1 CLK Duty spec in!! Max-Min= 186%
2387 19:56:57.046279 [DutyScan_Calibration_Flow] ====Done====
2388 19:56:57.046693
2389 19:56:57.050056 [DutyScan_Calibration_Flow] k_type=1
2390 19:56:57.065119
2391 19:56:57.065533 ==DQS 0 ==
2392 19:56:57.067962 Final DQS duty delay cell = -4
2393 19:56:57.071969 [-4] MAX Duty = 5000%(X100), DQS PI = 16
2394 19:56:57.074838 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2395 19:56:57.078170 [-4] AVG Duty = 4953%(X100)
2396 19:56:57.078580
2397 19:56:57.078909 ==DQS 1 ==
2398 19:56:57.081617 Final DQS duty delay cell = 0
2399 19:56:57.084916 [0] MAX Duty = 5093%(X100), DQS PI = 0
2400 19:56:57.088569 [0] MIN Duty = 4875%(X100), DQS PI = 26
2401 19:56:57.091666 [0] AVG Duty = 4984%(X100)
2402 19:56:57.092074
2403 19:56:57.095351 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2404 19:56:57.095800
2405 19:56:57.098542 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2406 19:56:57.101461 [DutyScan_Calibration_Flow] ====Done====
2407 19:56:57.101870
2408 19:56:57.104720 [DutyScan_Calibration_Flow] k_type=3
2409 19:56:57.121702
2410 19:56:57.122214 ==DQM 0 ==
2411 19:56:57.124739 Final DQM duty delay cell = 0
2412 19:56:57.127993 [0] MAX Duty = 5000%(X100), DQS PI = 22
2413 19:56:57.131800 [0] MIN Duty = 4876%(X100), DQS PI = 4
2414 19:56:57.132211 [0] AVG Duty = 4938%(X100)
2415 19:56:57.135033
2416 19:56:57.135476 ==DQM 1 ==
2417 19:56:57.138070 Final DQM duty delay cell = 0
2418 19:56:57.141441 [0] MAX Duty = 5031%(X100), DQS PI = 36
2419 19:56:57.145121 [0] MIN Duty = 4907%(X100), DQS PI = 4
2420 19:56:57.145772 [0] AVG Duty = 4969%(X100)
2421 19:56:57.146126
2422 19:56:57.151539 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2423 19:56:57.152186
2424 19:56:57.154747 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2425 19:56:57.158123 [DutyScan_Calibration_Flow] ====Done====
2426 19:56:57.158634
2427 19:56:57.161558 [DutyScan_Calibration_Flow] k_type=2
2428 19:56:57.177925
2429 19:56:57.178420 ==DQ 0 ==
2430 19:56:57.180779 Final DQ duty delay cell = 0
2431 19:56:57.184125 [0] MAX Duty = 5062%(X100), DQS PI = 12
2432 19:56:57.187661 [0] MIN Duty = 4938%(X100), DQS PI = 54
2433 19:56:57.188176 [0] AVG Duty = 5000%(X100)
2434 19:56:57.191661
2435 19:56:57.192170 ==DQ 1 ==
2436 19:56:57.194486 Final DQ duty delay cell = 0
2437 19:56:57.198227 [0] MAX Duty = 5125%(X100), DQS PI = 36
2438 19:56:57.201461 [0] MIN Duty = 4969%(X100), DQS PI = 26
2439 19:56:57.201972 [0] AVG Duty = 5047%(X100)
2440 19:56:57.202307
2441 19:56:57.207717 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2442 19:56:57.208227
2443 19:56:57.210964 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2444 19:56:57.214783 [DutyScan_Calibration_Flow] ====Done====
2445 19:56:57.217448 nWR fixed to 30
2446 19:56:57.217868 [ModeRegInit_LP4] CH0 RK0
2447 19:56:57.221612 [ModeRegInit_LP4] CH0 RK1
2448 19:56:57.224302 [ModeRegInit_LP4] CH1 RK0
2449 19:56:57.224716 [ModeRegInit_LP4] CH1 RK1
2450 19:56:57.227644 match AC timing 7
2451 19:56:57.230903 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 19:56:57.234706 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 19:56:57.241119 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 19:56:57.244831 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 19:56:57.251406 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 19:56:57.251947 ==
2457 19:56:57.254446 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 19:56:57.258108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 19:56:57.258636 ==
2460 19:56:57.264865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 19:56:57.268181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2462 19:56:57.278213 [CA 0] Center 40 (10~71) winsize 62
2463 19:56:57.281375 [CA 1] Center 39 (9~70) winsize 62
2464 19:56:57.284644 [CA 2] Center 36 (6~66) winsize 61
2465 19:56:57.288005 [CA 3] Center 35 (5~66) winsize 62
2466 19:56:57.291263 [CA 4] Center 34 (4~65) winsize 62
2467 19:56:57.294755 [CA 5] Center 33 (3~63) winsize 61
2468 19:56:57.295326
2469 19:56:57.298095 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2470 19:56:57.298658
2471 19:56:57.301275 [CATrainingPosCal] consider 1 rank data
2472 19:56:57.304590 u2DelayCellTimex100 = 270/100 ps
2473 19:56:57.307885 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2474 19:56:57.314538 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2475 19:56:57.317968 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2476 19:56:57.321260 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 19:56:57.325169 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2478 19:56:57.328037 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2479 19:56:57.328500
2480 19:56:57.331488 CA PerBit enable=1, Macro0, CA PI delay=33
2481 19:56:57.331948
2482 19:56:57.335043 [CBTSetCACLKResult] CA Dly = 33
2483 19:56:57.335629 CS Dly: 7 (0~38)
2484 19:56:57.338356 ==
2485 19:56:57.341148 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 19:56:57.344805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 19:56:57.345364 ==
2488 19:56:57.347710 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 19:56:57.354714 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2490 19:56:57.363877 [CA 0] Center 40 (10~70) winsize 61
2491 19:56:57.367610 [CA 1] Center 39 (9~70) winsize 62
2492 19:56:57.370882 [CA 2] Center 35 (5~66) winsize 62
2493 19:56:57.373886 [CA 3] Center 35 (5~66) winsize 62
2494 19:56:57.377625 [CA 4] Center 34 (4~65) winsize 62
2495 19:56:57.380479 [CA 5] Center 33 (3~64) winsize 62
2496 19:56:57.380937
2497 19:56:57.384258 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2498 19:56:57.384718
2499 19:56:57.387803 [CATrainingPosCal] consider 2 rank data
2500 19:56:57.391059 u2DelayCellTimex100 = 270/100 ps
2501 19:56:57.394018 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2502 19:56:57.401018 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2503 19:56:57.403865 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2504 19:56:57.407459 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 19:56:57.410770 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2506 19:56:57.413956 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2507 19:56:57.414514
2508 19:56:57.417423 CA PerBit enable=1, Macro0, CA PI delay=33
2509 19:56:57.417977
2510 19:56:57.420419 [CBTSetCACLKResult] CA Dly = 33
2511 19:56:57.420889 CS Dly: 8 (0~40)
2512 19:56:57.424412
2513 19:56:57.427340 ----->DramcWriteLeveling(PI) begin...
2514 19:56:57.427846 ==
2515 19:56:57.430708 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 19:56:57.433985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 19:56:57.434451 ==
2518 19:56:57.438680 Write leveling (Byte 0): 33 => 33
2519 19:56:57.440553 Write leveling (Byte 1): 30 => 30
2520 19:56:57.443818 DramcWriteLeveling(PI) end<-----
2521 19:56:57.444235
2522 19:56:57.444566 ==
2523 19:56:57.447449 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 19:56:57.450922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 19:56:57.451494 ==
2526 19:56:57.454648 [Gating] SW mode calibration
2527 19:56:57.461223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 19:56:57.464390 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 19:56:57.471004 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2530 19:56:57.474598 0 15 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2531 19:56:57.477892 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 19:56:57.484233 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 19:56:57.488023 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 19:56:57.491204 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 19:56:57.498142 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 19:56:57.501462 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 19:56:57.504731 1 0 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 1)
2538 19:56:57.510921 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 19:56:57.514198 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 19:56:57.517551 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 19:56:57.524340 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 19:56:57.527668 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 19:56:57.530960 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 19:56:57.537690 1 0 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2545 19:56:57.540407 1 1 0 | B1->B0 | 2c2c 3838 | 0 0 | (0 0) (0 0)
2546 19:56:57.544009 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2547 19:56:57.551102 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 19:56:57.554533 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 19:56:57.558013 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 19:56:57.564026 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 19:56:57.567127 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 19:56:57.570582 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 19:56:57.577490 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 19:56:57.580250 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 19:56:57.584001 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 19:56:57.587375 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 19:56:57.594384 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 19:56:57.597432 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 19:56:57.600940 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 19:56:57.607649 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 19:56:57.610930 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 19:56:57.613615 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 19:56:57.620353 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 19:56:57.624154 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 19:56:57.627057 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 19:56:57.633878 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 19:56:57.637607 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 19:56:57.640660 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 19:56:57.647294 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2570 19:56:57.650829 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 19:56:57.654135 Total UI for P1: 0, mck2ui 16
2572 19:56:57.657042 best dqsien dly found for B0: ( 1, 3, 30)
2573 19:56:57.660874 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 19:56:57.663750 Total UI for P1: 0, mck2ui 16
2575 19:56:57.667481 best dqsien dly found for B1: ( 1, 4, 2)
2576 19:56:57.670488 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2577 19:56:57.673856 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2578 19:56:57.674378
2579 19:56:57.677225 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2580 19:56:57.683581 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2581 19:56:57.684004 [Gating] SW calibration Done
2582 19:56:57.684340 ==
2583 19:56:57.687290 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 19:56:57.693882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 19:56:57.694477 ==
2586 19:56:57.694822 RX Vref Scan: 0
2587 19:56:57.695137
2588 19:56:57.697446 RX Vref 0 -> 0, step: 1
2589 19:56:57.697979
2590 19:56:57.700360 RX Delay -40 -> 252, step: 8
2591 19:56:57.703894 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2592 19:56:57.707229 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2593 19:56:57.710388 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2594 19:56:57.717295 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2595 19:56:57.720551 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2596 19:56:57.724083 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2597 19:56:57.726855 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2598 19:56:57.730227 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2599 19:56:57.733532 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2600 19:56:57.739956 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2601 19:56:57.743566 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2602 19:56:57.746958 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2603 19:56:57.750802 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2604 19:56:57.754057 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2605 19:56:57.760715 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2606 19:56:57.764089 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2607 19:56:57.764663 ==
2608 19:56:57.767135 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 19:56:57.770493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 19:56:57.771051 ==
2611 19:56:57.773507 DQS Delay:
2612 19:56:57.773961 DQS0 = 0, DQS1 = 0
2613 19:56:57.774322 DQM Delay:
2614 19:56:57.777003 DQM0 = 112, DQM1 = 101
2615 19:56:57.777415 DQ Delay:
2616 19:56:57.780611 DQ0 =111, DQ1 =115, DQ2 =111, DQ3 =107
2617 19:56:57.783719 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2618 19:56:57.787228 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2619 19:56:57.790318 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2620 19:56:57.793613
2621 19:56:57.794027
2622 19:56:57.794356 ==
2623 19:56:57.796772 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 19:56:57.800718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 19:56:57.801239 ==
2626 19:56:57.801574
2627 19:56:57.801877
2628 19:56:57.803406 TX Vref Scan disable
2629 19:56:57.803821 == TX Byte 0 ==
2630 19:56:57.810603 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2631 19:56:57.813306 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2632 19:56:57.813732 == TX Byte 1 ==
2633 19:56:57.820464 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2634 19:56:57.823794 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2635 19:56:57.824312 ==
2636 19:56:57.827332 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 19:56:57.830042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 19:56:57.830491 ==
2639 19:56:57.843566 TX Vref=22, minBit 1, minWin=25, winSum=417
2640 19:56:57.846309 TX Vref=24, minBit 1, minWin=25, winSum=419
2641 19:56:57.849420 TX Vref=26, minBit 3, minWin=26, winSum=428
2642 19:56:57.852630 TX Vref=28, minBit 12, minWin=26, winSum=434
2643 19:56:57.856055 TX Vref=30, minBit 12, minWin=26, winSum=435
2644 19:56:57.862861 TX Vref=32, minBit 2, minWin=26, winSum=429
2645 19:56:57.866834 [TxChooseVref] Worse bit 12, Min win 26, Win sum 435, Final Vref 30
2646 19:56:57.867432
2647 19:56:57.869881 Final TX Range 1 Vref 30
2648 19:56:57.870443
2649 19:56:57.870806 ==
2650 19:56:57.872639 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 19:56:57.876271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 19:56:57.879437 ==
2653 19:56:57.880002
2654 19:56:57.880365
2655 19:56:57.880702 TX Vref Scan disable
2656 19:56:57.883134 == TX Byte 0 ==
2657 19:56:57.886688 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2658 19:56:57.889990 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2659 19:56:57.893586 == TX Byte 1 ==
2660 19:56:57.896158 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2661 19:56:57.899589 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2662 19:56:57.903589
2663 19:56:57.904136 [DATLAT]
2664 19:56:57.904499 Freq=1200, CH0 RK0
2665 19:56:57.904838
2666 19:56:57.905998 DATLAT Default: 0xd
2667 19:56:57.906410 0, 0xFFFF, sum = 0
2668 19:56:57.909257 1, 0xFFFF, sum = 0
2669 19:56:57.909721 2, 0xFFFF, sum = 0
2670 19:56:57.912592 3, 0xFFFF, sum = 0
2671 19:56:57.913057 4, 0xFFFF, sum = 0
2672 19:56:57.916176 5, 0xFFFF, sum = 0
2673 19:56:57.919415 6, 0xFFFF, sum = 0
2674 19:56:57.919837 7, 0xFFFF, sum = 0
2675 19:56:57.922609 8, 0xFFFF, sum = 0
2676 19:56:57.923026 9, 0xFFFF, sum = 0
2677 19:56:57.925794 10, 0xFFFF, sum = 0
2678 19:56:57.926217 11, 0xFFFF, sum = 0
2679 19:56:57.929380 12, 0x0, sum = 1
2680 19:56:57.929802 13, 0x0, sum = 2
2681 19:56:57.932999 14, 0x0, sum = 3
2682 19:56:57.933419 15, 0x0, sum = 4
2683 19:56:57.933752 best_step = 13
2684 19:56:57.934055
2685 19:56:57.936022 ==
2686 19:56:57.939929 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 19:56:57.942705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 19:56:57.943126 ==
2689 19:56:57.943505 RX Vref Scan: 1
2690 19:56:57.943819
2691 19:56:57.945928 Set Vref Range= 32 -> 127
2692 19:56:57.946342
2693 19:56:57.949580 RX Vref 32 -> 127, step: 1
2694 19:56:57.950094
2695 19:56:57.953019 RX Delay -37 -> 252, step: 4
2696 19:56:57.953538
2697 19:56:57.956060 Set Vref, RX VrefLevel [Byte0]: 32
2698 19:56:57.959300 [Byte1]: 32
2699 19:56:57.959855
2700 19:56:57.962984 Set Vref, RX VrefLevel [Byte0]: 33
2701 19:56:57.966583 [Byte1]: 33
2702 19:56:57.969242
2703 19:56:57.969696 Set Vref, RX VrefLevel [Byte0]: 34
2704 19:56:57.972675 [Byte1]: 34
2705 19:56:57.977679
2706 19:56:57.978216 Set Vref, RX VrefLevel [Byte0]: 35
2707 19:56:57.981338 [Byte1]: 35
2708 19:56:57.985912
2709 19:56:57.986487 Set Vref, RX VrefLevel [Byte0]: 36
2710 19:56:57.989023 [Byte1]: 36
2711 19:56:57.993551
2712 19:56:57.994116 Set Vref, RX VrefLevel [Byte0]: 37
2713 19:56:57.996630 [Byte1]: 37
2714 19:56:58.001998
2715 19:56:58.002562 Set Vref, RX VrefLevel [Byte0]: 38
2716 19:56:58.004864 [Byte1]: 38
2717 19:56:58.010279
2718 19:56:58.010866 Set Vref, RX VrefLevel [Byte0]: 39
2719 19:56:58.012896 [Byte1]: 39
2720 19:56:58.017564
2721 19:56:58.018126 Set Vref, RX VrefLevel [Byte0]: 40
2722 19:56:58.020427 [Byte1]: 40
2723 19:56:58.025256
2724 19:56:58.025817 Set Vref, RX VrefLevel [Byte0]: 41
2725 19:56:58.028657 [Byte1]: 41
2726 19:56:58.033107
2727 19:56:58.033525 Set Vref, RX VrefLevel [Byte0]: 42
2728 19:56:58.037147 [Byte1]: 42
2729 19:56:58.041581
2730 19:56:58.042111 Set Vref, RX VrefLevel [Byte0]: 43
2731 19:56:58.044592 [Byte1]: 43
2732 19:56:58.049608
2733 19:56:58.050127 Set Vref, RX VrefLevel [Byte0]: 44
2734 19:56:58.052650 [Byte1]: 44
2735 19:56:58.057803
2736 19:56:58.058320 Set Vref, RX VrefLevel [Byte0]: 45
2737 19:56:58.061254 [Byte1]: 45
2738 19:56:58.065684
2739 19:56:58.066354 Set Vref, RX VrefLevel [Byte0]: 46
2740 19:56:58.068553 [Byte1]: 46
2741 19:56:58.073326
2742 19:56:58.073893 Set Vref, RX VrefLevel [Byte0]: 47
2743 19:56:58.076708 [Byte1]: 47
2744 19:56:58.081396
2745 19:56:58.081933 Set Vref, RX VrefLevel [Byte0]: 48
2746 19:56:58.084868 [Byte1]: 48
2747 19:56:58.089329
2748 19:56:58.089853 Set Vref, RX VrefLevel [Byte0]: 49
2749 19:56:58.093221 [Byte1]: 49
2750 19:56:58.097236
2751 19:56:58.097654 Set Vref, RX VrefLevel [Byte0]: 50
2752 19:56:58.100903 [Byte1]: 50
2753 19:56:58.106086
2754 19:56:58.106603 Set Vref, RX VrefLevel [Byte0]: 51
2755 19:56:58.108601 [Byte1]: 51
2756 19:56:58.113702
2757 19:56:58.114224 Set Vref, RX VrefLevel [Byte0]: 52
2758 19:56:58.116311 [Byte1]: 52
2759 19:56:58.121503
2760 19:56:58.122025 Set Vref, RX VrefLevel [Byte0]: 53
2761 19:56:58.125065 [Byte1]: 53
2762 19:56:58.129460
2763 19:56:58.130001 Set Vref, RX VrefLevel [Byte0]: 54
2764 19:56:58.132713 [Byte1]: 54
2765 19:56:58.137388
2766 19:56:58.137839 Set Vref, RX VrefLevel [Byte0]: 55
2767 19:56:58.140722 [Byte1]: 55
2768 19:56:58.145486
2769 19:56:58.146013 Set Vref, RX VrefLevel [Byte0]: 56
2770 19:56:58.148635 [Byte1]: 56
2771 19:56:58.153563
2772 19:56:58.154088 Set Vref, RX VrefLevel [Byte0]: 57
2773 19:56:58.156894 [Byte1]: 57
2774 19:56:58.161736
2775 19:56:58.162264 Set Vref, RX VrefLevel [Byte0]: 58
2776 19:56:58.164335 [Byte1]: 58
2777 19:56:58.169810
2778 19:56:58.170318 Set Vref, RX VrefLevel [Byte0]: 59
2779 19:56:58.172547 [Byte1]: 59
2780 19:56:58.177369
2781 19:56:58.177788 Set Vref, RX VrefLevel [Byte0]: 60
2782 19:56:58.180973 [Byte1]: 60
2783 19:56:58.185321
2784 19:56:58.185839 Set Vref, RX VrefLevel [Byte0]: 61
2785 19:56:58.188557 [Byte1]: 61
2786 19:56:58.192955
2787 19:56:58.193371 Set Vref, RX VrefLevel [Byte0]: 62
2788 19:56:58.196598 [Byte1]: 62
2789 19:56:58.201133
2790 19:56:58.201550 Set Vref, RX VrefLevel [Byte0]: 63
2791 19:56:58.204702 [Byte1]: 63
2792 19:56:58.209490
2793 19:56:58.209905 Set Vref, RX VrefLevel [Byte0]: 64
2794 19:56:58.212324 [Byte1]: 64
2795 19:56:58.217650
2796 19:56:58.218057 Set Vref, RX VrefLevel [Byte0]: 65
2797 19:56:58.220694 [Byte1]: 65
2798 19:56:58.225155
2799 19:56:58.225567 Set Vref, RX VrefLevel [Byte0]: 66
2800 19:56:58.228311 [Byte1]: 66
2801 19:56:58.232965
2802 19:56:58.233394 Set Vref, RX VrefLevel [Byte0]: 67
2803 19:56:58.236721 [Byte1]: 67
2804 19:56:58.240923
2805 19:56:58.241335 Set Vref, RX VrefLevel [Byte0]: 68
2806 19:56:58.244795 [Byte1]: 68
2807 19:56:58.249164
2808 19:56:58.249576 Set Vref, RX VrefLevel [Byte0]: 69
2809 19:56:58.252390 [Byte1]: 69
2810 19:56:58.257280
2811 19:56:58.257692 Set Vref, RX VrefLevel [Byte0]: 70
2812 19:56:58.260531 [Byte1]: 70
2813 19:56:58.265975
2814 19:56:58.266500 Set Vref, RX VrefLevel [Byte0]: 71
2815 19:56:58.268643 [Byte1]: 71
2816 19:56:58.274128
2817 19:56:58.274645 Set Vref, RX VrefLevel [Byte0]: 72
2818 19:56:58.277295 [Byte1]: 72
2819 19:56:58.281747
2820 19:56:58.282280 Set Vref, RX VrefLevel [Byte0]: 73
2821 19:56:58.284427 [Byte1]: 73
2822 19:56:58.289504
2823 19:56:58.290017 Final RX Vref Byte 0 = 62 to rank0
2824 19:56:58.292772 Final RX Vref Byte 1 = 57 to rank0
2825 19:56:58.296094 Final RX Vref Byte 0 = 62 to rank1
2826 19:56:58.299490 Final RX Vref Byte 1 = 57 to rank1==
2827 19:56:58.302562 Dram Type= 6, Freq= 0, CH_0, rank 0
2828 19:56:58.309393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 19:56:58.309909 ==
2830 19:56:58.310243 DQS Delay:
2831 19:56:58.310582 DQS0 = 0, DQS1 = 0
2832 19:56:58.312209 DQM Delay:
2833 19:56:58.312707 DQM0 = 112, DQM1 = 102
2834 19:56:58.315865 DQ Delay:
2835 19:56:58.319300 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2836 19:56:58.322887 DQ4 =114, DQ5 =104, DQ6 =118, DQ7 =120
2837 19:56:58.326384 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2838 19:56:58.329264 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =110
2839 19:56:58.329679
2840 19:56:58.330010
2841 19:56:58.336188 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2842 19:56:58.339458 CH0 RK0: MR19=303, MR18=FBFB
2843 19:56:58.346363 CH0_RK0: MR19=0x303, MR18=0xFBFB, DQSOSC=412, MR23=63, INC=38, DEC=25
2844 19:56:58.346878
2845 19:56:58.349795 ----->DramcWriteLeveling(PI) begin...
2846 19:56:58.350309 ==
2847 19:56:58.353066 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 19:56:58.356156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 19:56:58.356576 ==
2850 19:56:58.359956 Write leveling (Byte 0): 34 => 34
2851 19:56:58.363203 Write leveling (Byte 1): 30 => 30
2852 19:56:58.366254 DramcWriteLeveling(PI) end<-----
2853 19:56:58.366789
2854 19:56:58.367124 ==
2855 19:56:58.369553 Dram Type= 6, Freq= 0, CH_0, rank 1
2856 19:56:58.375741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2857 19:56:58.376244 ==
2858 19:56:58.376581 [Gating] SW mode calibration
2859 19:56:58.385748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2860 19:56:58.389106 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2861 19:56:58.392385 0 15 0 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
2862 19:56:58.398896 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 19:56:58.402824 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 19:56:58.406093 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 19:56:58.412354 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 19:56:58.416132 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 19:56:58.419530 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2868 19:56:58.426052 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2869 19:56:58.429531 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2870 19:56:58.432538 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 19:56:58.439558 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 19:56:58.442760 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 19:56:58.446617 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 19:56:58.452486 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 19:56:58.456009 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
2876 19:56:58.459507 1 0 28 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
2877 19:56:58.466264 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2878 19:56:58.469288 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 19:56:58.472759 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 19:56:58.476037 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 19:56:58.482707 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 19:56:58.486021 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 19:56:58.489261 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2884 19:56:58.496269 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2885 19:56:58.499150 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2886 19:56:58.502712 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 19:56:58.509181 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 19:56:58.512715 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 19:56:58.515611 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 19:56:58.522787 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 19:56:58.526275 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 19:56:58.529661 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 19:56:58.535564 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 19:56:58.539466 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 19:56:58.542731 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 19:56:58.549149 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 19:56:58.552432 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 19:56:58.555850 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 19:56:58.559132 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 19:56:58.566428 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2901 19:56:58.569247 Total UI for P1: 0, mck2ui 16
2902 19:56:58.572962 best dqsien dly found for B0: ( 1, 3, 26)
2903 19:56:58.576105 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2904 19:56:58.579859 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 19:56:58.582967 Total UI for P1: 0, mck2ui 16
2906 19:56:58.586205 best dqsien dly found for B1: ( 1, 3, 30)
2907 19:56:58.589725 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2908 19:56:58.592695 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2909 19:56:58.596099
2910 19:56:58.599374 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2911 19:56:58.602847 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2912 19:56:58.606044 [Gating] SW calibration Done
2913 19:56:58.606560 ==
2914 19:56:58.609297 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 19:56:58.612676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 19:56:58.613198 ==
2917 19:56:58.613601 RX Vref Scan: 0
2918 19:56:58.613917
2919 19:56:58.616380 RX Vref 0 -> 0, step: 1
2920 19:56:58.616898
2921 19:56:58.619781 RX Delay -40 -> 252, step: 8
2922 19:56:58.623033 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2923 19:56:58.626604 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2924 19:56:58.632718 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2925 19:56:58.635947 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2926 19:56:58.639483 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2927 19:56:58.643001 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2928 19:56:58.646037 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2929 19:56:58.649907 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2930 19:56:58.656279 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2931 19:56:58.659487 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2932 19:56:58.663084 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2933 19:56:58.666459 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2934 19:56:58.669356 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2935 19:56:58.676165 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2936 19:56:58.679802 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2937 19:56:58.682726 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2938 19:56:58.683251 ==
2939 19:56:58.686397 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 19:56:58.689526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 19:56:58.689949 ==
2942 19:56:58.693024 DQS Delay:
2943 19:56:58.693547 DQS0 = 0, DQS1 = 0
2944 19:56:58.696241 DQM Delay:
2945 19:56:58.696657 DQM0 = 112, DQM1 = 102
2946 19:56:58.696988 DQ Delay:
2947 19:56:58.699595 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2948 19:56:58.706547 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2949 19:56:58.709645 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2950 19:56:58.712546 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2951 19:56:58.712983
2952 19:56:58.713359
2953 19:56:58.713685 ==
2954 19:56:58.715818 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 19:56:58.719424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 19:56:58.719862 ==
2957 19:56:58.720197
2958 19:56:58.720507
2959 19:56:58.722593 TX Vref Scan disable
2960 19:56:58.726219 == TX Byte 0 ==
2961 19:56:58.730057 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2962 19:56:58.732937 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2963 19:56:58.736057 == TX Byte 1 ==
2964 19:56:58.739424 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2965 19:56:58.742907 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2966 19:56:58.743482 ==
2967 19:56:58.745937 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 19:56:58.749568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 19:56:58.749992 ==
2970 19:56:58.762688 TX Vref=22, minBit 1, minWin=25, winSum=427
2971 19:56:58.765864 TX Vref=24, minBit 1, minWin=26, winSum=428
2972 19:56:58.769437 TX Vref=26, minBit 7, minWin=26, winSum=433
2973 19:56:58.772754 TX Vref=28, minBit 0, minWin=27, winSum=441
2974 19:56:58.776236 TX Vref=30, minBit 1, minWin=27, winSum=440
2975 19:56:58.779666 TX Vref=32, minBit 0, minWin=27, winSum=441
2976 19:56:58.786126 [TxChooseVref] Worse bit 0, Min win 27, Win sum 441, Final Vref 28
2977 19:56:58.786642
2978 19:56:58.789535 Final TX Range 1 Vref 28
2979 19:56:58.790050
2980 19:56:58.790387 ==
2981 19:56:58.792748 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 19:56:58.796149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 19:56:58.796571 ==
2984 19:56:58.796904
2985 19:56:58.797213
2986 19:56:58.799227 TX Vref Scan disable
2987 19:56:58.802832 == TX Byte 0 ==
2988 19:56:58.806275 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2989 19:56:58.809583 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2990 19:56:58.812393 == TX Byte 1 ==
2991 19:56:58.815931 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2992 19:56:58.819655 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2993 19:56:58.820080
2994 19:56:58.823004 [DATLAT]
2995 19:56:58.823444 Freq=1200, CH0 RK1
2996 19:56:58.823789
2997 19:56:58.826457 DATLAT Default: 0xd
2998 19:56:58.826974 0, 0xFFFF, sum = 0
2999 19:56:58.829719 1, 0xFFFF, sum = 0
3000 19:56:58.830242 2, 0xFFFF, sum = 0
3001 19:56:58.832780 3, 0xFFFF, sum = 0
3002 19:56:58.833208 4, 0xFFFF, sum = 0
3003 19:56:58.835929 5, 0xFFFF, sum = 0
3004 19:56:58.836355 6, 0xFFFF, sum = 0
3005 19:56:58.839289 7, 0xFFFF, sum = 0
3006 19:56:58.839876 8, 0xFFFF, sum = 0
3007 19:56:58.842757 9, 0xFFFF, sum = 0
3008 19:56:58.846210 10, 0xFFFF, sum = 0
3009 19:56:58.846733 11, 0xFFFF, sum = 0
3010 19:56:58.849073 12, 0x0, sum = 1
3011 19:56:58.849500 13, 0x0, sum = 2
3012 19:56:58.849840 14, 0x0, sum = 3
3013 19:56:58.853228 15, 0x0, sum = 4
3014 19:56:58.853752 best_step = 13
3015 19:56:58.854090
3016 19:56:58.854401 ==
3017 19:56:58.856305 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 19:56:58.863094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 19:56:58.863672 ==
3020 19:56:58.864021 RX Vref Scan: 0
3021 19:56:58.864334
3022 19:56:58.866318 RX Vref 0 -> 0, step: 1
3023 19:56:58.866738
3024 19:56:58.869427 RX Delay -37 -> 252, step: 4
3025 19:56:58.873051 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3026 19:56:58.879723 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3027 19:56:58.882792 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3028 19:56:58.886219 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3029 19:56:58.889371 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3030 19:56:58.893036 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3031 19:56:58.895969 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3032 19:56:58.902696 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3033 19:56:58.906022 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3034 19:56:58.909351 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3035 19:56:58.912800 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3036 19:56:58.915888 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3037 19:56:58.922645 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3038 19:56:58.926063 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3039 19:56:58.929655 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3040 19:56:58.932344 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3041 19:56:58.932771 ==
3042 19:56:58.935523 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 19:56:58.942307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 19:56:58.942827 ==
3045 19:56:58.943164 DQS Delay:
3046 19:56:58.946392 DQS0 = 0, DQS1 = 0
3047 19:56:58.946903 DQM Delay:
3048 19:56:58.947244 DQM0 = 111, DQM1 = 102
3049 19:56:58.949139 DQ Delay:
3050 19:56:58.952631 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3051 19:56:58.955632 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3052 19:56:58.959525 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3053 19:56:58.962909 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3054 19:56:58.963488
3055 19:56:58.963838
3056 19:56:58.969371 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3057 19:56:58.972159 CH0 RK1: MR19=403, MR18=15FC
3058 19:56:58.979087 CH0_RK1: MR19=0x403, MR18=0x15FC, DQSOSC=401, MR23=63, INC=40, DEC=27
3059 19:56:58.982944 [RxdqsGatingPostProcess] freq 1200
3060 19:56:58.989252 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3061 19:56:58.992747 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 19:56:58.995635 best DQS1 dly(2T, 0.5T) = (0, 12)
3063 19:56:58.999059 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 19:56:58.999617 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3065 19:56:59.002770 best DQS0 dly(2T, 0.5T) = (0, 11)
3066 19:56:59.006159 best DQS1 dly(2T, 0.5T) = (0, 11)
3067 19:56:59.009149 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3068 19:56:59.012225 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3069 19:56:59.015517 Pre-setting of DQS Precalculation
3070 19:56:59.022465 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3071 19:56:59.022987 ==
3072 19:56:59.026015 Dram Type= 6, Freq= 0, CH_1, rank 0
3073 19:56:59.029069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 19:56:59.029528 ==
3075 19:56:59.035937 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3076 19:56:59.038893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3077 19:56:59.049092 [CA 0] Center 37 (7~67) winsize 61
3078 19:56:59.052041 [CA 1] Center 37 (7~68) winsize 62
3079 19:56:59.055680 [CA 2] Center 34 (4~64) winsize 61
3080 19:56:59.058940 [CA 3] Center 34 (4~64) winsize 61
3081 19:56:59.062752 [CA 4] Center 34 (4~64) winsize 61
3082 19:56:59.065410 [CA 5] Center 33 (3~63) winsize 61
3083 19:56:59.065896
3084 19:56:59.068957 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3085 19:56:59.069423
3086 19:56:59.072225 [CATrainingPosCal] consider 1 rank data
3087 19:56:59.075625 u2DelayCellTimex100 = 270/100 ps
3088 19:56:59.078939 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3089 19:56:59.082531 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3090 19:56:59.089124 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 19:56:59.092109 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 19:56:59.095117 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3093 19:56:59.098928 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3094 19:56:59.099518
3095 19:56:59.102341 CA PerBit enable=1, Macro0, CA PI delay=33
3096 19:56:59.102859
3097 19:56:59.105766 [CBTSetCACLKResult] CA Dly = 33
3098 19:56:59.106288 CS Dly: 6 (0~37)
3099 19:56:59.106627 ==
3100 19:56:59.109095 Dram Type= 6, Freq= 0, CH_1, rank 1
3101 19:56:59.115361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 19:56:59.115892 ==
3103 19:56:59.119156 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3104 19:56:59.125602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3105 19:56:59.134409 [CA 0] Center 37 (7~67) winsize 61
3106 19:56:59.137510 [CA 1] Center 37 (7~68) winsize 62
3107 19:56:59.141378 [CA 2] Center 34 (4~65) winsize 62
3108 19:56:59.144361 [CA 3] Center 33 (3~64) winsize 62
3109 19:56:59.148027 [CA 4] Center 34 (4~65) winsize 62
3110 19:56:59.151101 [CA 5] Center 33 (3~63) winsize 61
3111 19:56:59.151695
3112 19:56:59.154067 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3113 19:56:59.154485
3114 19:56:59.157978 [CATrainingPosCal] consider 2 rank data
3115 19:56:59.161305 u2DelayCellTimex100 = 270/100 ps
3116 19:56:59.164198 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3117 19:56:59.167491 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3118 19:56:59.174653 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3119 19:56:59.177364 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 19:56:59.181383 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3121 19:56:59.184267 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3122 19:56:59.184690
3123 19:56:59.187899 CA PerBit enable=1, Macro0, CA PI delay=33
3124 19:56:59.188423
3125 19:56:59.191210 [CBTSetCACLKResult] CA Dly = 33
3126 19:56:59.191915 CS Dly: 7 (0~39)
3127 19:56:59.192321
3128 19:56:59.194385 ----->DramcWriteLeveling(PI) begin...
3129 19:56:59.197584 ==
3130 19:56:59.200750 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 19:56:59.204359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 19:56:59.204890 ==
3133 19:56:59.207483 Write leveling (Byte 0): 25 => 25
3134 19:56:59.210926 Write leveling (Byte 1): 30 => 30
3135 19:56:59.214002 DramcWriteLeveling(PI) end<-----
3136 19:56:59.214459
3137 19:56:59.214805 ==
3138 19:56:59.217424 Dram Type= 6, Freq= 0, CH_1, rank 0
3139 19:56:59.220942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 19:56:59.221467 ==
3141 19:56:59.224017 [Gating] SW mode calibration
3142 19:56:59.230999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3143 19:56:59.237711 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3144 19:56:59.240812 0 15 0 | B1->B0 | 3232 2c2c | 0 1 | (0 0) (1 1)
3145 19:56:59.244158 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 19:56:59.247065 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 19:56:59.254048 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 19:56:59.257712 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 19:56:59.260918 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 19:56:59.267956 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 19:56:59.270848 0 15 28 | B1->B0 | 2929 2e2e | 0 0 | (1 0) (0 0)
3152 19:56:59.273845 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3153 19:56:59.281193 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 19:56:59.284082 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 19:56:59.287435 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 19:56:59.293746 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 19:56:59.297607 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 19:56:59.300421 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3159 19:56:59.306983 1 0 28 | B1->B0 | 3a3a 3838 | 0 1 | (0 0) (1 1)
3160 19:56:59.311121 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 19:56:59.314199 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 19:56:59.320752 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 19:56:59.324302 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 19:56:59.327213 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 19:56:59.333740 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 19:56:59.337408 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 19:56:59.341066 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3168 19:56:59.343899 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3169 19:56:59.351003 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 19:56:59.353998 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 19:56:59.357751 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 19:56:59.364058 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 19:56:59.367759 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 19:56:59.370642 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 19:56:59.377385 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 19:56:59.381399 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 19:56:59.384409 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 19:56:59.391205 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 19:56:59.393950 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 19:56:59.397632 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 19:56:59.403826 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 19:56:59.407450 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 19:56:59.411033 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3184 19:56:59.417653 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 19:56:59.418070 Total UI for P1: 0, mck2ui 16
3186 19:56:59.421348 best dqsien dly found for B0: ( 1, 3, 28)
3187 19:56:59.424384 Total UI for P1: 0, mck2ui 16
3188 19:56:59.427594 best dqsien dly found for B1: ( 1, 3, 28)
3189 19:56:59.431068 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3190 19:56:59.437428 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3191 19:56:59.437997
3192 19:56:59.440756 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3193 19:56:59.444129 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3194 19:56:59.447401 [Gating] SW calibration Done
3195 19:56:59.447821 ==
3196 19:56:59.450788 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 19:56:59.453890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 19:56:59.454308 ==
3199 19:56:59.454640 RX Vref Scan: 0
3200 19:56:59.457896
3201 19:56:59.458412 RX Vref 0 -> 0, step: 1
3202 19:56:59.458746
3203 19:56:59.461369 RX Delay -40 -> 252, step: 8
3204 19:56:59.463931 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3205 19:56:59.467364 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3206 19:56:59.474088 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3207 19:56:59.477267 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3208 19:56:59.481250 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3209 19:56:59.484554 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3210 19:56:59.487770 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3211 19:56:59.494458 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3212 19:56:59.497795 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3213 19:56:59.501113 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3214 19:56:59.504357 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3215 19:56:59.507575 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3216 19:56:59.510937 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3217 19:56:59.517467 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3218 19:56:59.520961 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3219 19:56:59.524168 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3220 19:56:59.524679 ==
3221 19:56:59.527656 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 19:56:59.530770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 19:56:59.533924 ==
3224 19:56:59.534337 DQS Delay:
3225 19:56:59.534666 DQS0 = 0, DQS1 = 0
3226 19:56:59.537332 DQM Delay:
3227 19:56:59.537748 DQM0 = 114, DQM1 = 106
3228 19:56:59.540739 DQ Delay:
3229 19:56:59.544337 DQ0 =123, DQ1 =111, DQ2 =99, DQ3 =115
3230 19:56:59.547548 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3231 19:56:59.550645 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =103
3232 19:56:59.554022 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3233 19:56:59.554587
3234 19:56:59.554942
3235 19:56:59.555252 ==
3236 19:56:59.557842 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 19:56:59.560962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 19:56:59.561488 ==
3239 19:56:59.561820
3240 19:56:59.562123
3241 19:56:59.564112 TX Vref Scan disable
3242 19:56:59.567048 == TX Byte 0 ==
3243 19:56:59.570603 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3244 19:56:59.574338 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3245 19:56:59.577558 == TX Byte 1 ==
3246 19:56:59.580659 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3247 19:56:59.584041 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3248 19:56:59.584460 ==
3249 19:56:59.587301 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 19:56:59.594030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 19:56:59.594550 ==
3252 19:56:59.604826 TX Vref=22, minBit 3, minWin=25, winSum=416
3253 19:56:59.607938 TX Vref=24, minBit 8, minWin=25, winSum=419
3254 19:56:59.611540 TX Vref=26, minBit 8, minWin=25, winSum=428
3255 19:56:59.614229 TX Vref=28, minBit 1, minWin=26, winSum=431
3256 19:56:59.618342 TX Vref=30, minBit 8, minWin=26, winSum=431
3257 19:56:59.621159 TX Vref=32, minBit 8, minWin=25, winSum=426
3258 19:56:59.628250 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
3259 19:56:59.628771
3260 19:56:59.631152 Final TX Range 1 Vref 28
3261 19:56:59.631619
3262 19:56:59.631955 ==
3263 19:56:59.634304 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 19:56:59.637935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 19:56:59.638352 ==
3266 19:56:59.638681
3267 19:56:59.641279
3268 19:56:59.641690 TX Vref Scan disable
3269 19:56:59.644572 == TX Byte 0 ==
3270 19:56:59.648022 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3271 19:56:59.651356 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3272 19:56:59.654254 == TX Byte 1 ==
3273 19:56:59.657804 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3274 19:56:59.661278 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3275 19:56:59.661801
3276 19:56:59.665211 [DATLAT]
3277 19:56:59.665725 Freq=1200, CH1 RK0
3278 19:56:59.666064
3279 19:56:59.667588 DATLAT Default: 0xd
3280 19:56:59.667999 0, 0xFFFF, sum = 0
3281 19:56:59.671139 1, 0xFFFF, sum = 0
3282 19:56:59.671621 2, 0xFFFF, sum = 0
3283 19:56:59.674787 3, 0xFFFF, sum = 0
3284 19:56:59.675323 4, 0xFFFF, sum = 0
3285 19:56:59.677915 5, 0xFFFF, sum = 0
3286 19:56:59.678332 6, 0xFFFF, sum = 0
3287 19:56:59.681544 7, 0xFFFF, sum = 0
3288 19:56:59.684537 8, 0xFFFF, sum = 0
3289 19:56:59.684956 9, 0xFFFF, sum = 0
3290 19:56:59.687904 10, 0xFFFF, sum = 0
3291 19:56:59.688440 11, 0xFFFF, sum = 0
3292 19:56:59.691013 12, 0x0, sum = 1
3293 19:56:59.691459 13, 0x0, sum = 2
3294 19:56:59.691798 14, 0x0, sum = 3
3295 19:56:59.694295 15, 0x0, sum = 4
3296 19:56:59.694709 best_step = 13
3297 19:56:59.695034
3298 19:56:59.698010 ==
3299 19:56:59.698418 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 19:56:59.704462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 19:56:59.704874 ==
3302 19:56:59.705202 RX Vref Scan: 1
3303 19:56:59.705504
3304 19:56:59.708079 Set Vref Range= 32 -> 127
3305 19:56:59.708491
3306 19:56:59.711204 RX Vref 32 -> 127, step: 1
3307 19:56:59.711645
3308 19:56:59.714447 RX Delay -21 -> 252, step: 4
3309 19:56:59.714897
3310 19:56:59.718108 Set Vref, RX VrefLevel [Byte0]: 32
3311 19:56:59.721397 [Byte1]: 32
3312 19:56:59.721916
3313 19:56:59.724111 Set Vref, RX VrefLevel [Byte0]: 33
3314 19:56:59.727635 [Byte1]: 33
3315 19:56:59.728143
3316 19:56:59.731272 Set Vref, RX VrefLevel [Byte0]: 34
3317 19:56:59.734153 [Byte1]: 34
3318 19:56:59.738540
3319 19:56:59.738947 Set Vref, RX VrefLevel [Byte0]: 35
3320 19:56:59.742097 [Byte1]: 35
3321 19:56:59.746719
3322 19:56:59.747127 Set Vref, RX VrefLevel [Byte0]: 36
3323 19:56:59.749593 [Byte1]: 36
3324 19:56:59.754443
3325 19:56:59.754990 Set Vref, RX VrefLevel [Byte0]: 37
3326 19:56:59.757665 [Byte1]: 37
3327 19:56:59.762812
3328 19:56:59.763317 Set Vref, RX VrefLevel [Byte0]: 38
3329 19:56:59.765417 [Byte1]: 38
3330 19:56:59.770309
3331 19:56:59.770719 Set Vref, RX VrefLevel [Byte0]: 39
3332 19:56:59.773348 [Byte1]: 39
3333 19:56:59.778183
3334 19:56:59.778601 Set Vref, RX VrefLevel [Byte0]: 40
3335 19:56:59.781353 [Byte1]: 40
3336 19:56:59.786069
3337 19:56:59.786578 Set Vref, RX VrefLevel [Byte0]: 41
3338 19:56:59.789723 [Byte1]: 41
3339 19:56:59.793824
3340 19:56:59.794233 Set Vref, RX VrefLevel [Byte0]: 42
3341 19:56:59.797256 [Byte1]: 42
3342 19:56:59.802422
3343 19:56:59.802933 Set Vref, RX VrefLevel [Byte0]: 43
3344 19:56:59.805238 [Byte1]: 43
3345 19:56:59.810295
3346 19:56:59.810808 Set Vref, RX VrefLevel [Byte0]: 44
3347 19:56:59.813240 [Byte1]: 44
3348 19:56:59.817926
3349 19:56:59.818336 Set Vref, RX VrefLevel [Byte0]: 45
3350 19:56:59.821743 [Byte1]: 45
3351 19:56:59.825509
3352 19:56:59.825979 Set Vref, RX VrefLevel [Byte0]: 46
3353 19:56:59.829578 [Byte1]: 46
3354 19:56:59.833660
3355 19:56:59.834283 Set Vref, RX VrefLevel [Byte0]: 47
3356 19:56:59.837057 [Byte1]: 47
3357 19:56:59.841677
3358 19:56:59.842191 Set Vref, RX VrefLevel [Byte0]: 48
3359 19:56:59.845198 [Byte1]: 48
3360 19:56:59.850019
3361 19:56:59.850534 Set Vref, RX VrefLevel [Byte0]: 49
3362 19:56:59.853294 [Byte1]: 49
3363 19:56:59.857689
3364 19:56:59.858196 Set Vref, RX VrefLevel [Byte0]: 50
3365 19:56:59.861162 [Byte1]: 50
3366 19:56:59.865592
3367 19:56:59.866102 Set Vref, RX VrefLevel [Byte0]: 51
3368 19:56:59.868451 [Byte1]: 51
3369 19:56:59.873608
3370 19:56:59.874115 Set Vref, RX VrefLevel [Byte0]: 52
3371 19:56:59.876750 [Byte1]: 52
3372 19:56:59.881412
3373 19:56:59.881960 Set Vref, RX VrefLevel [Byte0]: 53
3374 19:56:59.884994 [Byte1]: 53
3375 19:56:59.889273
3376 19:56:59.889823 Set Vref, RX VrefLevel [Byte0]: 54
3377 19:56:59.892441 [Byte1]: 54
3378 19:56:59.897182
3379 19:56:59.897751 Set Vref, RX VrefLevel [Byte0]: 55
3380 19:56:59.900100 [Byte1]: 55
3381 19:56:59.905093
3382 19:56:59.905600 Set Vref, RX VrefLevel [Byte0]: 56
3383 19:56:59.908045 [Byte1]: 56
3384 19:56:59.913219
3385 19:56:59.913726 Set Vref, RX VrefLevel [Byte0]: 57
3386 19:56:59.915887 [Byte1]: 57
3387 19:56:59.920708
3388 19:56:59.921211 Set Vref, RX VrefLevel [Byte0]: 58
3389 19:56:59.924094 [Byte1]: 58
3390 19:56:59.929109
3391 19:56:59.929533 Set Vref, RX VrefLevel [Byte0]: 59
3392 19:56:59.931707 [Byte1]: 59
3393 19:56:59.936937
3394 19:56:59.937437 Set Vref, RX VrefLevel [Byte0]: 60
3395 19:56:59.939866 [Byte1]: 60
3396 19:56:59.945070
3397 19:56:59.945585 Set Vref, RX VrefLevel [Byte0]: 61
3398 19:56:59.947998 [Byte1]: 61
3399 19:56:59.952696
3400 19:56:59.953201 Set Vref, RX VrefLevel [Byte0]: 62
3401 19:56:59.956054 [Byte1]: 62
3402 19:56:59.960979
3403 19:56:59.961483 Set Vref, RX VrefLevel [Byte0]: 63
3404 19:56:59.963772 [Byte1]: 63
3405 19:56:59.968727
3406 19:56:59.969316 Set Vref, RX VrefLevel [Byte0]: 64
3407 19:56:59.971832 [Byte1]: 64
3408 19:56:59.976579
3409 19:56:59.977128 Set Vref, RX VrefLevel [Byte0]: 65
3410 19:56:59.979770 [Byte1]: 65
3411 19:56:59.984082
3412 19:56:59.984490 Set Vref, RX VrefLevel [Byte0]: 66
3413 19:56:59.987418 [Byte1]: 66
3414 19:56:59.992625
3415 19:56:59.993127 Set Vref, RX VrefLevel [Byte0]: 67
3416 19:56:59.995540 [Byte1]: 67
3417 19:56:59.999993
3418 19:57:00.000514 Set Vref, RX VrefLevel [Byte0]: 68
3419 19:57:00.003351 [Byte1]: 68
3420 19:57:00.008087
3421 19:57:00.008591 Set Vref, RX VrefLevel [Byte0]: 69
3422 19:57:00.011352 [Byte1]: 69
3423 19:57:00.015750
3424 19:57:00.016237 Final RX Vref Byte 0 = 54 to rank0
3425 19:57:00.019425 Final RX Vref Byte 1 = 53 to rank0
3426 19:57:00.022882 Final RX Vref Byte 0 = 54 to rank1
3427 19:57:00.025907 Final RX Vref Byte 1 = 53 to rank1==
3428 19:57:00.029412 Dram Type= 6, Freq= 0, CH_1, rank 0
3429 19:57:00.032631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 19:57:00.036012 ==
3431 19:57:00.036429 DQS Delay:
3432 19:57:00.036762 DQS0 = 0, DQS1 = 0
3433 19:57:00.039342 DQM Delay:
3434 19:57:00.039787 DQM0 = 114, DQM1 = 107
3435 19:57:00.042774 DQ Delay:
3436 19:57:00.045993 DQ0 =120, DQ1 =108, DQ2 =104, DQ3 =112
3437 19:57:00.049383 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =112
3438 19:57:00.052927 DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =102
3439 19:57:00.055956 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =114
3440 19:57:00.056472
3441 19:57:00.056825
3442 19:57:00.062920 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3443 19:57:00.066418 CH1 RK0: MR19=303, MR18=F1F8
3444 19:57:00.072600 CH1_RK0: MR19=0x303, MR18=0xF1F8, DQSOSC=413, MR23=63, INC=38, DEC=25
3445 19:57:00.073117
3446 19:57:00.076377 ----->DramcWriteLeveling(PI) begin...
3447 19:57:00.076905 ==
3448 19:57:00.079596 Dram Type= 6, Freq= 0, CH_1, rank 1
3449 19:57:00.082855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 19:57:00.083369 ==
3451 19:57:00.085861 Write leveling (Byte 0): 26 => 26
3452 19:57:00.089510 Write leveling (Byte 1): 28 => 28
3453 19:57:00.092659 DramcWriteLeveling(PI) end<-----
3454 19:57:00.093173
3455 19:57:00.093508 ==
3456 19:57:00.095683 Dram Type= 6, Freq= 0, CH_1, rank 1
3457 19:57:00.102389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 19:57:00.102907 ==
3459 19:57:00.103242 [Gating] SW mode calibration
3460 19:57:00.112297 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3461 19:57:00.116279 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3462 19:57:00.119381 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 19:57:00.126217 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 19:57:00.129245 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 19:57:00.132805 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 19:57:00.139150 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 19:57:00.142531 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3468 19:57:00.146253 0 15 24 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
3469 19:57:00.153251 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3470 19:57:00.156223 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 19:57:00.159298 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 19:57:00.166162 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 19:57:00.169333 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 19:57:00.172419 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 19:57:00.179095 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3476 19:57:00.182963 1 0 24 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
3477 19:57:00.186050 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 19:57:00.192674 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 19:57:00.196003 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 19:57:00.198896 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 19:57:00.205810 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 19:57:00.209008 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 19:57:00.212690 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 19:57:00.219225 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3485 19:57:00.222176 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3486 19:57:00.225626 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 19:57:00.232327 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 19:57:00.235564 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 19:57:00.238804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 19:57:00.242671 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 19:57:00.248655 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 19:57:00.252400 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 19:57:00.255914 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 19:57:00.262093 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 19:57:00.265484 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 19:57:00.268416 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 19:57:00.274999 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 19:57:00.278894 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 19:57:00.282260 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3500 19:57:00.288734 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3501 19:57:00.292111 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3502 19:57:00.295540 Total UI for P1: 0, mck2ui 16
3503 19:57:00.298613 best dqsien dly found for B0: ( 1, 3, 22)
3504 19:57:00.302104 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 19:57:00.305201 Total UI for P1: 0, mck2ui 16
3506 19:57:00.308143 best dqsien dly found for B1: ( 1, 3, 26)
3507 19:57:00.311796 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3508 19:57:00.315553 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3509 19:57:00.316151
3510 19:57:00.322070 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3511 19:57:00.324729 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3512 19:57:00.328663 [Gating] SW calibration Done
3513 19:57:00.329219 ==
3514 19:57:00.331605 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 19:57:00.335033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 19:57:00.335664 ==
3517 19:57:00.336047 RX Vref Scan: 0
3518 19:57:00.336393
3519 19:57:00.338276 RX Vref 0 -> 0, step: 1
3520 19:57:00.338874
3521 19:57:00.341646 RX Delay -40 -> 252, step: 8
3522 19:57:00.344943 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3523 19:57:00.348722 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3524 19:57:00.354974 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3525 19:57:00.357994 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3526 19:57:00.361374 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3527 19:57:00.364923 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3528 19:57:00.368165 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3529 19:57:00.371316 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3530 19:57:00.378438 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3531 19:57:00.381569 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3532 19:57:00.384551 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3533 19:57:00.387728 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3534 19:57:00.394802 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3535 19:57:00.397653 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3536 19:57:00.401039 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3537 19:57:00.404230 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3538 19:57:00.404654 ==
3539 19:57:00.407559 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 19:57:00.414612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 19:57:00.415140 ==
3542 19:57:00.415536 DQS Delay:
3543 19:57:00.415913 DQS0 = 0, DQS1 = 0
3544 19:57:00.417686 DQM Delay:
3545 19:57:00.418105 DQM0 = 110, DQM1 = 109
3546 19:57:00.421491 DQ Delay:
3547 19:57:00.424006 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3548 19:57:00.427864 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3549 19:57:00.430735 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3550 19:57:00.434107 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3551 19:57:00.434529
3552 19:57:00.434865
3553 19:57:00.435196 ==
3554 19:57:00.437668 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 19:57:00.440563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 19:57:00.441177 ==
3557 19:57:00.443906
3558 19:57:00.444381
3559 19:57:00.445013 TX Vref Scan disable
3560 19:57:00.447042 == TX Byte 0 ==
3561 19:57:00.450578 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3562 19:57:00.454020 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3563 19:57:00.457432 == TX Byte 1 ==
3564 19:57:00.461130 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3565 19:57:00.464223 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3566 19:57:00.464646 ==
3567 19:57:00.467335 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 19:57:00.473911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 19:57:00.474420 ==
3570 19:57:00.484743 TX Vref=22, minBit 9, minWin=25, winSum=423
3571 19:57:00.487970 TX Vref=24, minBit 9, minWin=25, winSum=424
3572 19:57:00.491552 TX Vref=26, minBit 7, minWin=26, winSum=431
3573 19:57:00.495072 TX Vref=28, minBit 8, minWin=26, winSum=435
3574 19:57:00.498798 TX Vref=30, minBit 8, minWin=26, winSum=439
3575 19:57:00.501859 TX Vref=32, minBit 8, minWin=26, winSum=432
3576 19:57:00.508099 [TxChooseVref] Worse bit 8, Min win 26, Win sum 439, Final Vref 30
3577 19:57:00.508666
3578 19:57:00.511789 Final TX Range 1 Vref 30
3579 19:57:00.512352
3580 19:57:00.512722 ==
3581 19:57:00.515101 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 19:57:00.518213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 19:57:00.518680 ==
3584 19:57:00.519048
3585 19:57:00.521708
3586 19:57:00.522269 TX Vref Scan disable
3587 19:57:00.524730 == TX Byte 0 ==
3588 19:57:00.528347 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3589 19:57:00.531200 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3590 19:57:00.534898 == TX Byte 1 ==
3591 19:57:00.537974 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3592 19:57:00.540975 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3593 19:57:00.544817
3594 19:57:00.545378 [DATLAT]
3595 19:57:00.545750 Freq=1200, CH1 RK1
3596 19:57:00.546096
3597 19:57:00.548270 DATLAT Default: 0xd
3598 19:57:00.548736 0, 0xFFFF, sum = 0
3599 19:57:00.550783 1, 0xFFFF, sum = 0
3600 19:57:00.551206 2, 0xFFFF, sum = 0
3601 19:57:00.554537 3, 0xFFFF, sum = 0
3602 19:57:00.557776 4, 0xFFFF, sum = 0
3603 19:57:00.558314 5, 0xFFFF, sum = 0
3604 19:57:00.561197 6, 0xFFFF, sum = 0
3605 19:57:00.561732 7, 0xFFFF, sum = 0
3606 19:57:00.564498 8, 0xFFFF, sum = 0
3607 19:57:00.565031 9, 0xFFFF, sum = 0
3608 19:57:00.567571 10, 0xFFFF, sum = 0
3609 19:57:00.567999 11, 0xFFFF, sum = 0
3610 19:57:00.570752 12, 0x0, sum = 1
3611 19:57:00.571336 13, 0x0, sum = 2
3612 19:57:00.574255 14, 0x0, sum = 3
3613 19:57:00.574681 15, 0x0, sum = 4
3614 19:57:00.577734 best_step = 13
3615 19:57:00.578257
3616 19:57:00.578596 ==
3617 19:57:00.580437 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 19:57:00.584248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 19:57:00.584784 ==
3620 19:57:00.585234 RX Vref Scan: 0
3621 19:57:00.587457
3622 19:57:00.587889 RX Vref 0 -> 0, step: 1
3623 19:57:00.588328
3624 19:57:00.590878 RX Delay -21 -> 252, step: 4
3625 19:57:00.597368 iDelay=195, Bit 0, Center 112 (39 ~ 186) 148
3626 19:57:00.600713 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3627 19:57:00.603906 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3628 19:57:00.607717 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3629 19:57:00.610456 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3630 19:57:00.617195 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3631 19:57:00.620839 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3632 19:57:00.624136 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3633 19:57:00.626998 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3634 19:57:00.630529 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3635 19:57:00.636921 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3636 19:57:00.639956 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3637 19:57:00.643855 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3638 19:57:00.647150 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3639 19:57:00.649778 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3640 19:57:00.656732 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3641 19:57:00.657293 ==
3642 19:57:00.659843 Dram Type= 6, Freq= 0, CH_1, rank 1
3643 19:57:00.663541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3644 19:57:00.664190 ==
3645 19:57:00.664574 DQS Delay:
3646 19:57:00.666692 DQS0 = 0, DQS1 = 0
3647 19:57:00.667257 DQM Delay:
3648 19:57:00.669755 DQM0 = 110, DQM1 = 110
3649 19:57:00.670254 DQ Delay:
3650 19:57:00.673161 DQ0 =112, DQ1 =108, DQ2 =100, DQ3 =108
3651 19:57:00.676622 DQ4 =108, DQ5 =120, DQ6 =120, DQ7 =108
3652 19:57:00.680272 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =104
3653 19:57:00.683306 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3654 19:57:00.683909
3655 19:57:00.684281
3656 19:57:00.693592 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3657 19:57:00.696194 CH1 RK1: MR19=304, MR18=FA0A
3658 19:57:00.703076 CH1_RK1: MR19=0x304, MR18=0xFA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3659 19:57:00.706344 [RxdqsGatingPostProcess] freq 1200
3660 19:57:00.709825 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3661 19:57:00.712925 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 19:57:00.715980 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 19:57:00.719234 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 19:57:00.722998 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 19:57:00.725848 best DQS0 dly(2T, 0.5T) = (0, 11)
3666 19:57:00.729573 best DQS1 dly(2T, 0.5T) = (0, 11)
3667 19:57:00.733253 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3668 19:57:00.735971 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3669 19:57:00.739653 Pre-setting of DQS Precalculation
3670 19:57:00.742758 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3671 19:57:00.752653 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3672 19:57:00.759214 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3673 19:57:00.759872
3674 19:57:00.760244
3675 19:57:00.762440 [Calibration Summary] 2400 Mbps
3676 19:57:00.762994 CH 0, Rank 0
3677 19:57:00.766181 SW Impedance : PASS
3678 19:57:00.766741 DUTY Scan : NO K
3679 19:57:00.768735 ZQ Calibration : PASS
3680 19:57:00.772140 Jitter Meter : NO K
3681 19:57:00.772701 CBT Training : PASS
3682 19:57:00.775649 Write leveling : PASS
3683 19:57:00.778859 RX DQS gating : PASS
3684 19:57:00.779528 RX DQ/DQS(RDDQC) : PASS
3685 19:57:00.782213 TX DQ/DQS : PASS
3686 19:57:00.785417 RX DATLAT : PASS
3687 19:57:00.785974 RX DQ/DQS(Engine): PASS
3688 19:57:00.788289 TX OE : NO K
3689 19:57:00.788753 All Pass.
3690 19:57:00.789119
3691 19:57:00.792271 CH 0, Rank 1
3692 19:57:00.792827 SW Impedance : PASS
3693 19:57:00.795072 DUTY Scan : NO K
3694 19:57:00.798256 ZQ Calibration : PASS
3695 19:57:00.798840 Jitter Meter : NO K
3696 19:57:00.801582 CBT Training : PASS
3697 19:57:00.805409 Write leveling : PASS
3698 19:57:00.805962 RX DQS gating : PASS
3699 19:57:00.808164 RX DQ/DQS(RDDQC) : PASS
3700 19:57:00.811902 TX DQ/DQS : PASS
3701 19:57:00.812459 RX DATLAT : PASS
3702 19:57:00.815123 RX DQ/DQS(Engine): PASS
3703 19:57:00.815782 TX OE : NO K
3704 19:57:00.818186 All Pass.
3705 19:57:00.818661
3706 19:57:00.819026 CH 1, Rank 0
3707 19:57:00.821598 SW Impedance : PASS
3708 19:57:00.822151 DUTY Scan : NO K
3709 19:57:00.825383 ZQ Calibration : PASS
3710 19:57:00.828158 Jitter Meter : NO K
3711 19:57:00.828713 CBT Training : PASS
3712 19:57:00.831706 Write leveling : PASS
3713 19:57:00.834652 RX DQS gating : PASS
3714 19:57:00.835209 RX DQ/DQS(RDDQC) : PASS
3715 19:57:00.838305 TX DQ/DQS : PASS
3716 19:57:00.841233 RX DATLAT : PASS
3717 19:57:00.841698 RX DQ/DQS(Engine): PASS
3718 19:57:00.844885 TX OE : NO K
3719 19:57:00.845447 All Pass.
3720 19:57:00.845815
3721 19:57:00.848322 CH 1, Rank 1
3722 19:57:00.848885 SW Impedance : PASS
3723 19:57:00.851195 DUTY Scan : NO K
3724 19:57:00.854716 ZQ Calibration : PASS
3725 19:57:00.855283 Jitter Meter : NO K
3726 19:57:00.857955 CBT Training : PASS
3727 19:57:00.860842 Write leveling : PASS
3728 19:57:00.861306 RX DQS gating : PASS
3729 19:57:00.864237 RX DQ/DQS(RDDQC) : PASS
3730 19:57:00.868380 TX DQ/DQS : PASS
3731 19:57:00.868945 RX DATLAT : PASS
3732 19:57:00.871125 RX DQ/DQS(Engine): PASS
3733 19:57:00.874276 TX OE : NO K
3734 19:57:00.874741 All Pass.
3735 19:57:00.875110
3736 19:57:00.875491 DramC Write-DBI off
3737 19:57:00.877919 PER_BANK_REFRESH: Hybrid Mode
3738 19:57:00.880949 TX_TRACKING: ON
3739 19:57:00.887728 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3740 19:57:00.891067 [FAST_K] Save calibration result to emmc
3741 19:57:00.897368 dramc_set_vcore_voltage set vcore to 650000
3742 19:57:00.897917 Read voltage for 600, 5
3743 19:57:00.900691 Vio18 = 0
3744 19:57:00.901153 Vcore = 650000
3745 19:57:00.901532 Vdram = 0
3746 19:57:00.903870 Vddq = 0
3747 19:57:00.904331 Vmddr = 0
3748 19:57:00.907420 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3749 19:57:00.914102 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3750 19:57:00.916923 MEM_TYPE=3, freq_sel=19
3751 19:57:00.920098 sv_algorithm_assistance_LP4_1600
3752 19:57:00.923920 ============ PULL DRAM RESETB DOWN ============
3753 19:57:00.927067 ========== PULL DRAM RESETB DOWN end =========
3754 19:57:00.933792 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3755 19:57:00.937046 ===================================
3756 19:57:00.937345 LPDDR4 DRAM CONFIGURATION
3757 19:57:00.939902 ===================================
3758 19:57:00.943481 EX_ROW_EN[0] = 0x0
3759 19:57:00.943730 EX_ROW_EN[1] = 0x0
3760 19:57:00.946746 LP4Y_EN = 0x0
3761 19:57:00.946964 WORK_FSP = 0x0
3762 19:57:00.950463 WL = 0x2
3763 19:57:00.950643 RL = 0x2
3764 19:57:00.953249 BL = 0x2
3765 19:57:00.956400 RPST = 0x0
3766 19:57:00.956634 RD_PRE = 0x0
3767 19:57:00.959756 WR_PRE = 0x1
3768 19:57:00.959902 WR_PST = 0x0
3769 19:57:00.963101 DBI_WR = 0x0
3770 19:57:00.963233 DBI_RD = 0x0
3771 19:57:00.966462 OTF = 0x1
3772 19:57:00.969717 ===================================
3773 19:57:00.972920 ===================================
3774 19:57:00.973054 ANA top config
3775 19:57:00.975975 ===================================
3776 19:57:00.979413 DLL_ASYNC_EN = 0
3777 19:57:00.982831 ALL_SLAVE_EN = 1
3778 19:57:00.982965 NEW_RANK_MODE = 1
3779 19:57:00.986007 DLL_IDLE_MODE = 1
3780 19:57:00.989322 LP45_APHY_COMB_EN = 1
3781 19:57:00.992559 TX_ODT_DIS = 1
3782 19:57:00.995799 NEW_8X_MODE = 1
3783 19:57:00.999461 ===================================
3784 19:57:00.999592 ===================================
3785 19:57:01.002819 data_rate = 1200
3786 19:57:01.006173 CKR = 1
3787 19:57:01.009519 DQ_P2S_RATIO = 8
3788 19:57:01.012807 ===================================
3789 19:57:01.015900 CA_P2S_RATIO = 8
3790 19:57:01.019006 DQ_CA_OPEN = 0
3791 19:57:01.022512 DQ_SEMI_OPEN = 0
3792 19:57:01.022647 CA_SEMI_OPEN = 0
3793 19:57:01.025585 CA_FULL_RATE = 0
3794 19:57:01.028759 DQ_CKDIV4_EN = 1
3795 19:57:01.032077 CA_CKDIV4_EN = 1
3796 19:57:01.035611 CA_PREDIV_EN = 0
3797 19:57:01.039038 PH8_DLY = 0
3798 19:57:01.039169 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3799 19:57:01.042282 DQ_AAMCK_DIV = 4
3800 19:57:01.045475 CA_AAMCK_DIV = 4
3801 19:57:01.048685 CA_ADMCK_DIV = 4
3802 19:57:01.052240 DQ_TRACK_CA_EN = 0
3803 19:57:01.055396 CA_PICK = 600
3804 19:57:01.058591 CA_MCKIO = 600
3805 19:57:01.058726 MCKIO_SEMI = 0
3806 19:57:01.061792 PLL_FREQ = 2288
3807 19:57:01.065331 DQ_UI_PI_RATIO = 32
3808 19:57:01.068500 CA_UI_PI_RATIO = 0
3809 19:57:01.071794 ===================================
3810 19:57:01.075242 ===================================
3811 19:57:01.078762 memory_type:LPDDR4
3812 19:57:01.078895 GP_NUM : 10
3813 19:57:01.082017 SRAM_EN : 1
3814 19:57:01.085240 MD32_EN : 0
3815 19:57:01.088642 ===================================
3816 19:57:01.088813 [ANA_INIT] >>>>>>>>>>>>>>
3817 19:57:01.091979 <<<<<< [CONFIGURE PHASE]: ANA_TX
3818 19:57:01.095598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3819 19:57:01.098446 ===================================
3820 19:57:01.102008 data_rate = 1200,PCW = 0X5800
3821 19:57:01.105163 ===================================
3822 19:57:01.108804 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3823 19:57:01.115476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3824 19:57:01.118557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3825 19:57:01.126133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3826 19:57:01.128874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3827 19:57:01.131756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3828 19:57:01.132318 [ANA_INIT] flow start
3829 19:57:01.135577 [ANA_INIT] PLL >>>>>>>>
3830 19:57:01.138645 [ANA_INIT] PLL <<<<<<<<
3831 19:57:01.141579 [ANA_INIT] MIDPI >>>>>>>>
3832 19:57:01.142044 [ANA_INIT] MIDPI <<<<<<<<
3833 19:57:01.144851 [ANA_INIT] DLL >>>>>>>>
3834 19:57:01.148241 [ANA_INIT] flow end
3835 19:57:01.151671 ============ LP4 DIFF to SE enter ============
3836 19:57:01.155061 ============ LP4 DIFF to SE exit ============
3837 19:57:01.158185 [ANA_INIT] <<<<<<<<<<<<<
3838 19:57:01.161367 [Flow] Enable top DCM control >>>>>
3839 19:57:01.164942 [Flow] Enable top DCM control <<<<<
3840 19:57:01.168405 Enable DLL master slave shuffle
3841 19:57:01.172126 ==============================================================
3842 19:57:01.175566 Gating Mode config
3843 19:57:01.181385 ==============================================================
3844 19:57:01.181957 Config description:
3845 19:57:01.191062 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3846 19:57:01.197913 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3847 19:57:01.200993 SELPH_MODE 0: By rank 1: By Phase
3848 19:57:01.208125 ==============================================================
3849 19:57:01.211282 GAT_TRACK_EN = 1
3850 19:57:01.214340 RX_GATING_MODE = 2
3851 19:57:01.217874 RX_GATING_TRACK_MODE = 2
3852 19:57:01.221242 SELPH_MODE = 1
3853 19:57:01.224060 PICG_EARLY_EN = 1
3854 19:57:01.227679 VALID_LAT_VALUE = 1
3855 19:57:01.230959 ==============================================================
3856 19:57:01.234083 Enter into Gating configuration >>>>
3857 19:57:01.237453 Exit from Gating configuration <<<<
3858 19:57:01.241065 Enter into DVFS_PRE_config >>>>>
3859 19:57:01.254141 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3860 19:57:01.257383 Exit from DVFS_PRE_config <<<<<
3861 19:57:01.257848 Enter into PICG configuration >>>>
3862 19:57:01.261116 Exit from PICG configuration <<<<
3863 19:57:01.263958 [RX_INPUT] configuration >>>>>
3864 19:57:01.267516 [RX_INPUT] configuration <<<<<
3865 19:57:01.274036 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3866 19:57:01.277311 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3867 19:57:01.283759 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 19:57:01.291022 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 19:57:01.297482 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3870 19:57:01.304123 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3871 19:57:01.306948 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3872 19:57:01.310654 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3873 19:57:01.313934 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3874 19:57:01.320529 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3875 19:57:01.323950 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3876 19:57:01.327534 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3877 19:57:01.330530 ===================================
3878 19:57:01.333861 LPDDR4 DRAM CONFIGURATION
3879 19:57:01.337060 ===================================
3880 19:57:01.340757 EX_ROW_EN[0] = 0x0
3881 19:57:01.341402 EX_ROW_EN[1] = 0x0
3882 19:57:01.344460 LP4Y_EN = 0x0
3883 19:57:01.344911 WORK_FSP = 0x0
3884 19:57:01.347210 WL = 0x2
3885 19:57:01.347810 RL = 0x2
3886 19:57:01.350203 BL = 0x2
3887 19:57:01.350764 RPST = 0x0
3888 19:57:01.353511 RD_PRE = 0x0
3889 19:57:01.354068 WR_PRE = 0x1
3890 19:57:01.357165 WR_PST = 0x0
3891 19:57:01.357722 DBI_WR = 0x0
3892 19:57:01.360053 DBI_RD = 0x0
3893 19:57:01.360608 OTF = 0x1
3894 19:57:01.363981 ===================================
3895 19:57:01.370391 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3896 19:57:01.373223 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3897 19:57:01.376653 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 19:57:01.379759 ===================================
3899 19:57:01.383227 LPDDR4 DRAM CONFIGURATION
3900 19:57:01.386724 ===================================
3901 19:57:01.389781 EX_ROW_EN[0] = 0x10
3902 19:57:01.390237 EX_ROW_EN[1] = 0x0
3903 19:57:01.393146 LP4Y_EN = 0x0
3904 19:57:01.393698 WORK_FSP = 0x0
3905 19:57:01.396731 WL = 0x2
3906 19:57:01.397277 RL = 0x2
3907 19:57:01.400003 BL = 0x2
3908 19:57:01.400462 RPST = 0x0
3909 19:57:01.403175 RD_PRE = 0x0
3910 19:57:01.403682 WR_PRE = 0x1
3911 19:57:01.406463 WR_PST = 0x0
3912 19:57:01.407014 DBI_WR = 0x0
3913 19:57:01.410074 DBI_RD = 0x0
3914 19:57:01.410625 OTF = 0x1
3915 19:57:01.413283 ===================================
3916 19:57:01.419286 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3917 19:57:01.424259 nWR fixed to 30
3918 19:57:01.427506 [ModeRegInit_LP4] CH0 RK0
3919 19:57:01.428060 [ModeRegInit_LP4] CH0 RK1
3920 19:57:01.431022 [ModeRegInit_LP4] CH1 RK0
3921 19:57:01.434290 [ModeRegInit_LP4] CH1 RK1
3922 19:57:01.434940 match AC timing 17
3923 19:57:01.440834 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3924 19:57:01.444019 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3925 19:57:01.447568 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3926 19:57:01.454011 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3927 19:57:01.457528 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3928 19:57:01.458082 ==
3929 19:57:01.461271 Dram Type= 6, Freq= 0, CH_0, rank 0
3930 19:57:01.463982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 19:57:01.464446 ==
3932 19:57:01.471020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 19:57:01.477552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3934 19:57:01.480854 [CA 0] Center 37 (7~67) winsize 61
3935 19:57:01.483748 [CA 1] Center 36 (6~67) winsize 62
3936 19:57:01.487054 [CA 2] Center 35 (5~65) winsize 61
3937 19:57:01.491049 [CA 3] Center 35 (5~65) winsize 61
3938 19:57:01.494084 [CA 4] Center 34 (4~65) winsize 62
3939 19:57:01.497400 [CA 5] Center 34 (4~64) winsize 61
3940 19:57:01.497830
3941 19:57:01.500505 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3942 19:57:01.500933
3943 19:57:01.503940 [CATrainingPosCal] consider 1 rank data
3944 19:57:01.507344 u2DelayCellTimex100 = 270/100 ps
3945 19:57:01.510676 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3946 19:57:01.514036 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3947 19:57:01.517085 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3948 19:57:01.521343 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3949 19:57:01.523744 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3950 19:57:01.529993 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3951 19:57:01.530442
3952 19:57:01.533663 CA PerBit enable=1, Macro0, CA PI delay=34
3953 19:57:01.534208
3954 19:57:01.536776 [CBTSetCACLKResult] CA Dly = 34
3955 19:57:01.537243 CS Dly: 4 (0~35)
3956 19:57:01.537748 ==
3957 19:57:01.540003 Dram Type= 6, Freq= 0, CH_0, rank 1
3958 19:57:01.543545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 19:57:01.546672 ==
3960 19:57:01.549909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3961 19:57:01.556718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3962 19:57:01.559832 [CA 0] Center 37 (7~67) winsize 61
3963 19:57:01.563505 [CA 1] Center 36 (6~67) winsize 62
3964 19:57:01.566893 [CA 2] Center 35 (5~65) winsize 61
3965 19:57:01.570353 [CA 3] Center 35 (5~65) winsize 61
3966 19:57:01.573286 [CA 4] Center 34 (4~64) winsize 61
3967 19:57:01.576525 [CA 5] Center 33 (3~64) winsize 62
3968 19:57:01.576938
3969 19:57:01.580216 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3970 19:57:01.580629
3971 19:57:01.583508 [CATrainingPosCal] consider 2 rank data
3972 19:57:01.586626 u2DelayCellTimex100 = 270/100 ps
3973 19:57:01.589743 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3974 19:57:01.593650 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3975 19:57:01.596385 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3976 19:57:01.603216 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3977 19:57:01.606752 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3978 19:57:01.609830 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3979 19:57:01.610240
3980 19:57:01.613232 CA PerBit enable=1, Macro0, CA PI delay=34
3981 19:57:01.613753
3982 19:57:01.616405 [CBTSetCACLKResult] CA Dly = 34
3983 19:57:01.616815 CS Dly: 5 (0~37)
3984 19:57:01.617140
3985 19:57:01.619571 ----->DramcWriteLeveling(PI) begin...
3986 19:57:01.619988 ==
3987 19:57:01.623837 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 19:57:01.630360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 19:57:01.630876 ==
3990 19:57:01.633353 Write leveling (Byte 0): 35 => 35
3991 19:57:01.636457 Write leveling (Byte 1): 30 => 30
3992 19:57:01.636889 DramcWriteLeveling(PI) end<-----
3993 19:57:01.639596
3994 19:57:01.640022 ==
3995 19:57:01.643058 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 19:57:01.646784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 19:57:01.647313 ==
3998 19:57:01.649581 [Gating] SW mode calibration
3999 19:57:01.656539 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4000 19:57:01.659744 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4001 19:57:01.666559 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 19:57:01.670345 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 19:57:01.672869 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 19:57:01.680010 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4005 19:57:01.682812 0 9 16 | B1->B0 | 2d2d 2929 | 1 1 | (1 1) (1 0)
4006 19:57:01.687259 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 19:57:01.693028 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 19:57:01.696473 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 19:57:01.699549 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 19:57:01.706959 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 19:57:01.709584 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 19:57:01.712578 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4013 19:57:01.719582 0 10 16 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (1 1)
4014 19:57:01.723240 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 19:57:01.726276 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 19:57:01.732919 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 19:57:01.736279 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 19:57:01.739658 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 19:57:01.745961 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 19:57:01.749851 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 19:57:01.752401 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4022 19:57:01.759225 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 19:57:01.762841 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 19:57:01.765627 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 19:57:01.772136 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 19:57:01.775610 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 19:57:01.778861 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 19:57:01.785580 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 19:57:01.788976 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 19:57:01.792082 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 19:57:01.798755 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 19:57:01.802358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 19:57:01.805191 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 19:57:01.812002 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 19:57:01.815334 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 19:57:01.818765 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4037 19:57:01.825736 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4038 19:57:01.826297 Total UI for P1: 0, mck2ui 16
4039 19:57:01.828421 best dqsien dly found for B0: ( 0, 13, 12)
4040 19:57:01.835295 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 19:57:01.838319 Total UI for P1: 0, mck2ui 16
4042 19:57:01.841352 best dqsien dly found for B1: ( 0, 13, 16)
4043 19:57:01.844695 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4044 19:57:01.848263 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4045 19:57:01.848817
4046 19:57:01.851691 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4047 19:57:01.854888 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4048 19:57:01.858111 [Gating] SW calibration Done
4049 19:57:01.858663 ==
4050 19:57:01.861699 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 19:57:01.864883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 19:57:01.868139 ==
4053 19:57:01.868594 RX Vref Scan: 0
4054 19:57:01.868953
4055 19:57:01.871681 RX Vref 0 -> 0, step: 1
4056 19:57:01.872229
4057 19:57:01.874783 RX Delay -230 -> 252, step: 16
4058 19:57:01.878539 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4059 19:57:01.881235 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4060 19:57:01.884935 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4061 19:57:01.891217 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4062 19:57:01.894983 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4063 19:57:01.897777 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4064 19:57:01.901171 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4065 19:57:01.904081 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4066 19:57:01.910792 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4067 19:57:01.914668 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4068 19:57:01.917731 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4069 19:57:01.920783 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4070 19:57:01.927511 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4071 19:57:01.930440 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4072 19:57:01.934191 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4073 19:57:01.937271 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4074 19:57:01.940792 ==
4075 19:57:01.941247 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 19:57:01.947474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 19:57:01.948033 ==
4078 19:57:01.948399 DQS Delay:
4079 19:57:01.950701 DQS0 = 0, DQS1 = 0
4080 19:57:01.951250 DQM Delay:
4081 19:57:01.953850 DQM0 = 38, DQM1 = 29
4082 19:57:01.954403 DQ Delay:
4083 19:57:01.957297 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4084 19:57:01.960344 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4085 19:57:01.964351 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4086 19:57:01.967642 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4087 19:57:01.968197
4088 19:57:01.968557
4089 19:57:01.968889 ==
4090 19:57:01.970303 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 19:57:01.973678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 19:57:01.974240 ==
4093 19:57:01.974684
4094 19:57:01.975023
4095 19:57:01.976826 TX Vref Scan disable
4096 19:57:01.980268 == TX Byte 0 ==
4097 19:57:01.983350 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4098 19:57:01.987320 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4099 19:57:01.990216 == TX Byte 1 ==
4100 19:57:01.994029 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4101 19:57:01.997514 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4102 19:57:01.998070 ==
4103 19:57:01.999823 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 19:57:02.006451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 19:57:02.006996 ==
4106 19:57:02.007360
4107 19:57:02.007739
4108 19:57:02.008060 TX Vref Scan disable
4109 19:57:02.011226 == TX Byte 0 ==
4110 19:57:02.014672 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4111 19:57:02.021183 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4112 19:57:02.021725 == TX Byte 1 ==
4113 19:57:02.024221 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4114 19:57:02.031138 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4115 19:57:02.031727
4116 19:57:02.032089 [DATLAT]
4117 19:57:02.032425 Freq=600, CH0 RK0
4118 19:57:02.032752
4119 19:57:02.034474 DATLAT Default: 0x9
4120 19:57:02.034923 0, 0xFFFF, sum = 0
4121 19:57:02.037455 1, 0xFFFF, sum = 0
4122 19:57:02.041139 2, 0xFFFF, sum = 0
4123 19:57:02.041600 3, 0xFFFF, sum = 0
4124 19:57:02.044105 4, 0xFFFF, sum = 0
4125 19:57:02.044563 5, 0xFFFF, sum = 0
4126 19:57:02.047688 6, 0xFFFF, sum = 0
4127 19:57:02.048254 7, 0xFFFF, sum = 0
4128 19:57:02.050773 8, 0x0, sum = 1
4129 19:57:02.051333 9, 0x0, sum = 2
4130 19:57:02.051771 10, 0x0, sum = 3
4131 19:57:02.054169 11, 0x0, sum = 4
4132 19:57:02.054761 best_step = 9
4133 19:57:02.055128
4134 19:57:02.055504 ==
4135 19:57:02.057585 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 19:57:02.064194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 19:57:02.064739 ==
4138 19:57:02.065105 RX Vref Scan: 1
4139 19:57:02.065441
4140 19:57:02.067194 RX Vref 0 -> 0, step: 1
4141 19:57:02.067707
4142 19:57:02.071074 RX Delay -195 -> 252, step: 8
4143 19:57:02.071678
4144 19:57:02.074357 Set Vref, RX VrefLevel [Byte0]: 62
4145 19:57:02.077298 [Byte1]: 57
4146 19:57:02.077752
4147 19:57:02.080752 Final RX Vref Byte 0 = 62 to rank0
4148 19:57:02.084154 Final RX Vref Byte 1 = 57 to rank0
4149 19:57:02.087422 Final RX Vref Byte 0 = 62 to rank1
4150 19:57:02.090789 Final RX Vref Byte 1 = 57 to rank1==
4151 19:57:02.094212 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 19:57:02.097238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 19:57:02.097795 ==
4154 19:57:02.100545 DQS Delay:
4155 19:57:02.101096 DQS0 = 0, DQS1 = 0
4156 19:57:02.103867 DQM Delay:
4157 19:57:02.104419 DQM0 = 35, DQM1 = 28
4158 19:57:02.104783 DQ Delay:
4159 19:57:02.107128 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4160 19:57:02.110537 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4161 19:57:02.114152 DQ8 =20, DQ9 =20, DQ10 =28, DQ11 =20
4162 19:57:02.117237 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4163 19:57:02.117761
4164 19:57:02.118124
4165 19:57:02.127461 [DQSOSCAuto] RK0, (LSB)MR18= 0x4343, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4166 19:57:02.130237 CH0 RK0: MR19=808, MR18=4343
4167 19:57:02.137561 CH0_RK0: MR19=0x808, MR18=0x4343, DQSOSC=397, MR23=63, INC=166, DEC=110
4168 19:57:02.138130
4169 19:57:02.140498 ----->DramcWriteLeveling(PI) begin...
4170 19:57:02.140959 ==
4171 19:57:02.143589 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 19:57:02.147257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 19:57:02.147867 ==
4174 19:57:02.150770 Write leveling (Byte 0): 31 => 31
4175 19:57:02.153379 Write leveling (Byte 1): 31 => 31
4176 19:57:02.156878 DramcWriteLeveling(PI) end<-----
4177 19:57:02.157332
4178 19:57:02.157695 ==
4179 19:57:02.160404 Dram Type= 6, Freq= 0, CH_0, rank 1
4180 19:57:02.163361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 19:57:02.163969 ==
4182 19:57:02.167107 [Gating] SW mode calibration
4183 19:57:02.174105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4184 19:57:02.180089 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4185 19:57:02.183709 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 19:57:02.186848 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4187 19:57:02.193455 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 19:57:02.197015 0 9 12 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
4189 19:57:02.200174 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4190 19:57:02.206877 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 19:57:02.210144 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 19:57:02.213420 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 19:57:02.220112 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 19:57:02.223753 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 19:57:02.226592 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 19:57:02.233363 0 10 12 | B1->B0 | 2b2b 3030 | 0 0 | (0 0) (0 0)
4197 19:57:02.236856 0 10 16 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
4198 19:57:02.239781 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 19:57:02.246884 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 19:57:02.250257 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 19:57:02.253482 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 19:57:02.256671 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 19:57:02.263037 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 19:57:02.266716 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4205 19:57:02.269990 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4206 19:57:02.276335 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 19:57:02.279708 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 19:57:02.283235 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 19:57:02.289752 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 19:57:02.293196 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 19:57:02.296593 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 19:57:02.303582 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 19:57:02.306387 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 19:57:02.310339 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 19:57:02.316376 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 19:57:02.319943 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 19:57:02.323434 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 19:57:02.329914 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 19:57:02.333322 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 19:57:02.336293 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4221 19:57:02.339551 Total UI for P1: 0, mck2ui 16
4222 19:57:02.342971 best dqsien dly found for B0: ( 0, 13, 10)
4223 19:57:02.349934 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 19:57:02.350489 Total UI for P1: 0, mck2ui 16
4225 19:57:02.356280 best dqsien dly found for B1: ( 0, 13, 14)
4226 19:57:02.359519 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4227 19:57:02.362648 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4228 19:57:02.363214
4229 19:57:02.366557 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4230 19:57:02.369361 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4231 19:57:02.372948 [Gating] SW calibration Done
4232 19:57:02.373418 ==
4233 19:57:02.376364 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 19:57:02.379271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 19:57:02.379896 ==
4236 19:57:02.382546 RX Vref Scan: 0
4237 19:57:02.383001
4238 19:57:02.383364 RX Vref 0 -> 0, step: 1
4239 19:57:02.383760
4240 19:57:02.385958 RX Delay -230 -> 252, step: 16
4241 19:57:02.392478 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4242 19:57:02.395950 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4243 19:57:02.399424 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4244 19:57:02.402654 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4245 19:57:02.405562 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4246 19:57:02.412886 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4247 19:57:02.415776 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4248 19:57:02.419435 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4249 19:57:02.422190 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4250 19:57:02.428731 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4251 19:57:02.431985 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4252 19:57:02.435559 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4253 19:57:02.439097 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4254 19:57:02.445336 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4255 19:57:02.448860 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4256 19:57:02.452085 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4257 19:57:02.452661 ==
4258 19:57:02.455663 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 19:57:02.458850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 19:57:02.462009 ==
4261 19:57:02.462619 DQS Delay:
4262 19:57:02.463163 DQS0 = 0, DQS1 = 0
4263 19:57:02.465487 DQM Delay:
4264 19:57:02.466038 DQM0 = 39, DQM1 = 29
4265 19:57:02.469107 DQ Delay:
4266 19:57:02.469598 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4267 19:57:02.472112 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4268 19:57:02.475784 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4269 19:57:02.478737 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4270 19:57:02.479291
4271 19:57:02.482502
4272 19:57:02.483169 ==
4273 19:57:02.485444 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 19:57:02.488381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 19:57:02.488922 ==
4276 19:57:02.489291
4277 19:57:02.489623
4278 19:57:02.492338 TX Vref Scan disable
4279 19:57:02.492893 == TX Byte 0 ==
4280 19:57:02.498862 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4281 19:57:02.501714 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4282 19:57:02.502270 == TX Byte 1 ==
4283 19:57:02.508409 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4284 19:57:02.511661 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4285 19:57:02.512211 ==
4286 19:57:02.514966 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 19:57:02.518436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 19:57:02.518991 ==
4289 19:57:02.519580
4290 19:57:02.519937
4291 19:57:02.521243 TX Vref Scan disable
4292 19:57:02.524667 == TX Byte 0 ==
4293 19:57:02.527943 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4294 19:57:02.531579 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4295 19:57:02.534471 == TX Byte 1 ==
4296 19:57:02.538230 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4297 19:57:02.541067 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4298 19:57:02.544581
4299 19:57:02.544986 [DATLAT]
4300 19:57:02.545309 Freq=600, CH0 RK1
4301 19:57:02.545617
4302 19:57:02.547769 DATLAT Default: 0x9
4303 19:57:02.548058 0, 0xFFFF, sum = 0
4304 19:57:02.551746 1, 0xFFFF, sum = 0
4305 19:57:02.552135 2, 0xFFFF, sum = 0
4306 19:57:02.554912 3, 0xFFFF, sum = 0
4307 19:57:02.555300 4, 0xFFFF, sum = 0
4308 19:57:02.557946 5, 0xFFFF, sum = 0
4309 19:57:02.558338 6, 0xFFFF, sum = 0
4310 19:57:02.561103 7, 0xFFFF, sum = 0
4311 19:57:02.561402 8, 0x0, sum = 1
4312 19:57:02.564754 9, 0x0, sum = 2
4313 19:57:02.565171 10, 0x0, sum = 3
4314 19:57:02.567529 11, 0x0, sum = 4
4315 19:57:02.567884 best_step = 9
4316 19:57:02.568119
4317 19:57:02.568335 ==
4318 19:57:02.571011 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 19:57:02.577197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 19:57:02.577737 ==
4321 19:57:02.578118 RX Vref Scan: 0
4322 19:57:02.578446
4323 19:57:02.580762 RX Vref 0 -> 0, step: 1
4324 19:57:02.581057
4325 19:57:02.584166 RX Delay -195 -> 252, step: 8
4326 19:57:02.587383 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4327 19:57:02.594913 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4328 19:57:02.597513 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4329 19:57:02.601262 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4330 19:57:02.604433 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4331 19:57:02.610459 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4332 19:57:02.613692 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4333 19:57:02.616910 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4334 19:57:02.621008 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4335 19:57:02.623663 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4336 19:57:02.630570 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4337 19:57:02.633601 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4338 19:57:02.637480 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4339 19:57:02.643580 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4340 19:57:02.646773 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4341 19:57:02.650051 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4342 19:57:02.650660 ==
4343 19:57:02.653464 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 19:57:02.656746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 19:57:02.657195 ==
4346 19:57:02.660241 DQS Delay:
4347 19:57:02.660656 DQS0 = 0, DQS1 = 0
4348 19:57:02.663194 DQM Delay:
4349 19:57:02.663759 DQM0 = 33, DQM1 = 27
4350 19:57:02.664272 DQ Delay:
4351 19:57:02.666617 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4352 19:57:02.670020 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4353 19:57:02.673419 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4354 19:57:02.676676 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4355 19:57:02.677098
4356 19:57:02.677424
4357 19:57:02.686593 [DQSOSCAuto] RK1, (LSB)MR18= 0x7140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4358 19:57:02.689926 CH0 RK1: MR19=808, MR18=7140
4359 19:57:02.696653 CH0_RK1: MR19=0x808, MR18=0x7140, DQSOSC=388, MR23=63, INC=174, DEC=116
4360 19:57:02.697075 [RxdqsGatingPostProcess] freq 600
4361 19:57:02.703257 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4362 19:57:02.706861 Pre-setting of DQS Precalculation
4363 19:57:02.709904 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4364 19:57:02.713620 ==
4365 19:57:02.716306 Dram Type= 6, Freq= 0, CH_1, rank 0
4366 19:57:02.719984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 19:57:02.720510 ==
4368 19:57:02.723039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 19:57:02.730057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4370 19:57:02.734056 [CA 0] Center 35 (5~66) winsize 62
4371 19:57:02.737254 [CA 1] Center 35 (5~66) winsize 62
4372 19:57:02.740036 [CA 2] Center 34 (4~65) winsize 62
4373 19:57:02.743567 [CA 3] Center 34 (4~65) winsize 62
4374 19:57:02.747486 [CA 4] Center 34 (4~65) winsize 62
4375 19:57:02.750497 [CA 5] Center 34 (4~64) winsize 61
4376 19:57:02.751008
4377 19:57:02.753839 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4378 19:57:02.754354
4379 19:57:02.757482 [CATrainingPosCal] consider 1 rank data
4380 19:57:02.759907 u2DelayCellTimex100 = 270/100 ps
4381 19:57:02.763645 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4382 19:57:02.767210 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4383 19:57:02.773438 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4384 19:57:02.776872 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4385 19:57:02.780198 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4386 19:57:02.783472 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4387 19:57:02.784037
4388 19:57:02.786776 CA PerBit enable=1, Macro0, CA PI delay=34
4389 19:57:02.787332
4390 19:57:02.790469 [CBTSetCACLKResult] CA Dly = 34
4391 19:57:02.791027 CS Dly: 4 (0~35)
4392 19:57:02.793608 ==
4393 19:57:02.794074 Dram Type= 6, Freq= 0, CH_1, rank 1
4394 19:57:02.800067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 19:57:02.800632 ==
4396 19:57:02.803133 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4397 19:57:02.809826 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4398 19:57:02.813722 [CA 0] Center 36 (6~66) winsize 61
4399 19:57:02.817035 [CA 1] Center 36 (6~67) winsize 62
4400 19:57:02.820072 [CA 2] Center 34 (4~65) winsize 62
4401 19:57:02.823578 [CA 3] Center 34 (3~65) winsize 63
4402 19:57:02.826910 [CA 4] Center 34 (4~65) winsize 62
4403 19:57:02.830205 [CA 5] Center 33 (3~64) winsize 62
4404 19:57:02.830901
4405 19:57:02.833380 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4406 19:57:02.833944
4407 19:57:02.836866 [CATrainingPosCal] consider 2 rank data
4408 19:57:02.840221 u2DelayCellTimex100 = 270/100 ps
4409 19:57:02.843514 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4410 19:57:02.850251 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4411 19:57:02.853639 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4412 19:57:02.857085 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4413 19:57:02.860011 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4414 19:57:02.863520 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4415 19:57:02.864095
4416 19:57:02.866535 CA PerBit enable=1, Macro0, CA PI delay=34
4417 19:57:02.867089
4418 19:57:02.869732 [CBTSetCACLKResult] CA Dly = 34
4419 19:57:02.873068 CS Dly: 5 (0~37)
4420 19:57:02.873527
4421 19:57:02.876176 ----->DramcWriteLeveling(PI) begin...
4422 19:57:02.876600 ==
4423 19:57:02.879878 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 19:57:02.882757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 19:57:02.883179 ==
4426 19:57:02.886208 Write leveling (Byte 0): 30 => 30
4427 19:57:02.889636 Write leveling (Byte 1): 30 => 30
4428 19:57:02.893325 DramcWriteLeveling(PI) end<-----
4429 19:57:02.893842
4430 19:57:02.894180 ==
4431 19:57:02.896183 Dram Type= 6, Freq= 0, CH_1, rank 0
4432 19:57:02.899758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 19:57:02.900275 ==
4434 19:57:02.903146 [Gating] SW mode calibration
4435 19:57:02.909684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4436 19:57:02.916282 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4437 19:57:02.919796 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 19:57:02.923006 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 19:57:02.929577 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 19:57:02.933312 0 9 12 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 0)
4441 19:57:02.936355 0 9 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
4442 19:57:02.942917 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 19:57:02.945914 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 19:57:02.949664 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 19:57:02.956146 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 19:57:02.959553 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 19:57:02.962661 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 19:57:02.969424 0 10 12 | B1->B0 | 2d2d 3434 | 0 0 | (1 1) (0 0)
4449 19:57:02.972689 0 10 16 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
4450 19:57:02.976275 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 19:57:02.979642 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 19:57:02.986467 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 19:57:02.989361 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 19:57:02.993169 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 19:57:02.999428 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 19:57:03.002271 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 19:57:03.005827 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 19:57:03.012657 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 19:57:03.015989 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 19:57:03.019162 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 19:57:03.025814 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 19:57:03.029598 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 19:57:03.032014 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 19:57:03.038975 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 19:57:03.042596 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 19:57:03.045925 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 19:57:03.052043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 19:57:03.055557 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 19:57:03.058926 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 19:57:03.065948 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 19:57:03.069027 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 19:57:03.072137 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4473 19:57:03.078813 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4474 19:57:03.081980 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 19:57:03.085105 Total UI for P1: 0, mck2ui 16
4476 19:57:03.089109 best dqsien dly found for B0: ( 0, 13, 14)
4477 19:57:03.092412 Total UI for P1: 0, mck2ui 16
4478 19:57:03.095249 best dqsien dly found for B1: ( 0, 13, 14)
4479 19:57:03.098899 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4480 19:57:03.102100 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4481 19:57:03.102652
4482 19:57:03.105511 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4483 19:57:03.109141 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4484 19:57:03.112162 [Gating] SW calibration Done
4485 19:57:03.112628 ==
4486 19:57:03.115217 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 19:57:03.119033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 19:57:03.121874 ==
4489 19:57:03.122388 RX Vref Scan: 0
4490 19:57:03.122761
4491 19:57:03.124897 RX Vref 0 -> 0, step: 1
4492 19:57:03.125453
4493 19:57:03.128349 RX Delay -230 -> 252, step: 16
4494 19:57:03.131771 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4495 19:57:03.134953 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4496 19:57:03.138394 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4497 19:57:03.144840 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4498 19:57:03.148367 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4499 19:57:03.151850 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4500 19:57:03.155227 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4501 19:57:03.158579 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4502 19:57:03.165557 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4503 19:57:03.168231 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4504 19:57:03.171652 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4505 19:57:03.175174 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4506 19:57:03.182201 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4507 19:57:03.184961 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4508 19:57:03.188011 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4509 19:57:03.191624 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4510 19:57:03.192177 ==
4511 19:57:03.194764 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 19:57:03.201856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 19:57:03.202425 ==
4514 19:57:03.202793 DQS Delay:
4515 19:57:03.205022 DQS0 = 0, DQS1 = 0
4516 19:57:03.205570 DQM Delay:
4517 19:57:03.205942 DQM0 = 37, DQM1 = 27
4518 19:57:03.208143 DQ Delay:
4519 19:57:03.211465 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4520 19:57:03.215077 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4521 19:57:03.218383 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4522 19:57:03.221216 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4523 19:57:03.221682
4524 19:57:03.222090
4525 19:57:03.222485 ==
4526 19:57:03.224684 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 19:57:03.227977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 19:57:03.228554 ==
4529 19:57:03.228934
4530 19:57:03.229276
4531 19:57:03.231755 TX Vref Scan disable
4532 19:57:03.232219 == TX Byte 0 ==
4533 19:57:03.237990 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4534 19:57:03.241577 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4535 19:57:03.242134 == TX Byte 1 ==
4536 19:57:03.247907 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4537 19:57:03.251713 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4538 19:57:03.252190 ==
4539 19:57:03.254621 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 19:57:03.257881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 19:57:03.258301 ==
4542 19:57:03.261654
4543 19:57:03.262156
4544 19:57:03.262489 TX Vref Scan disable
4545 19:57:03.264929 == TX Byte 0 ==
4546 19:57:03.268005 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4547 19:57:03.274677 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4548 19:57:03.275200 == TX Byte 1 ==
4549 19:57:03.278309 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4550 19:57:03.284820 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4551 19:57:03.285334
4552 19:57:03.285670 [DATLAT]
4553 19:57:03.286174 Freq=600, CH1 RK0
4554 19:57:03.286623
4555 19:57:03.287894 DATLAT Default: 0x9
4556 19:57:03.288439 0, 0xFFFF, sum = 0
4557 19:57:03.291216 1, 0xFFFF, sum = 0
4558 19:57:03.291670 2, 0xFFFF, sum = 0
4559 19:57:03.294958 3, 0xFFFF, sum = 0
4560 19:57:03.298219 4, 0xFFFF, sum = 0
4561 19:57:03.298739 5, 0xFFFF, sum = 0
4562 19:57:03.301736 6, 0xFFFF, sum = 0
4563 19:57:03.302250 7, 0xFFFF, sum = 0
4564 19:57:03.304928 8, 0x0, sum = 1
4565 19:57:03.305448 9, 0x0, sum = 2
4566 19:57:03.305844 10, 0x0, sum = 3
4567 19:57:03.307775 11, 0x0, sum = 4
4568 19:57:03.308334 best_step = 9
4569 19:57:03.308688
4570 19:57:03.308999 ==
4571 19:57:03.311334 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 19:57:03.318139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 19:57:03.318654 ==
4574 19:57:03.318989 RX Vref Scan: 1
4575 19:57:03.319298
4576 19:57:03.321128 RX Vref 0 -> 0, step: 1
4577 19:57:03.321543
4578 19:57:03.324903 RX Delay -195 -> 252, step: 8
4579 19:57:03.325411
4580 19:57:03.328268 Set Vref, RX VrefLevel [Byte0]: 54
4581 19:57:03.331440 [Byte1]: 53
4582 19:57:03.331974
4583 19:57:03.334912 Final RX Vref Byte 0 = 54 to rank0
4584 19:57:03.337851 Final RX Vref Byte 1 = 53 to rank0
4585 19:57:03.341071 Final RX Vref Byte 0 = 54 to rank1
4586 19:57:03.344713 Final RX Vref Byte 1 = 53 to rank1==
4587 19:57:03.347512 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 19:57:03.350972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 19:57:03.351515 ==
4590 19:57:03.354565 DQS Delay:
4591 19:57:03.355072 DQS0 = 0, DQS1 = 0
4592 19:57:03.358218 DQM Delay:
4593 19:57:03.358725 DQM0 = 39, DQM1 = 27
4594 19:57:03.359060 DQ Delay:
4595 19:57:03.361131 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4596 19:57:03.364127 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4597 19:57:03.367997 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4598 19:57:03.371189 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4599 19:57:03.371727
4600 19:57:03.372061
4601 19:57:03.381283 [DQSOSCAuto] RK0, (LSB)MR18= 0x2633, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4602 19:57:03.384573 CH1 RK0: MR19=808, MR18=2633
4603 19:57:03.387717 CH1_RK0: MR19=0x808, MR18=0x2633, DQSOSC=400, MR23=63, INC=163, DEC=109
4604 19:57:03.391069
4605 19:57:03.394347 ----->DramcWriteLeveling(PI) begin...
4606 19:57:03.394772 ==
4607 19:57:03.397958 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 19:57:03.401145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 19:57:03.401662 ==
4610 19:57:03.403963 Write leveling (Byte 0): 29 => 29
4611 19:57:03.407448 Write leveling (Byte 1): 30 => 30
4612 19:57:03.410606 DramcWriteLeveling(PI) end<-----
4613 19:57:03.411174
4614 19:57:03.411560 ==
4615 19:57:03.413854 Dram Type= 6, Freq= 0, CH_1, rank 1
4616 19:57:03.418335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 19:57:03.418846 ==
4618 19:57:03.420909 [Gating] SW mode calibration
4619 19:57:03.427177 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4620 19:57:03.434248 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4621 19:57:03.437300 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 19:57:03.440562 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4623 19:57:03.447244 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4624 19:57:03.450961 0 9 12 | B1->B0 | 3030 2a2a | 1 1 | (0 0) (0 0)
4625 19:57:03.454239 0 9 16 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
4626 19:57:03.461110 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 19:57:03.463992 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 19:57:03.467530 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 19:57:03.474272 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 19:57:03.476919 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 19:57:03.480304 0 10 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
4632 19:57:03.487296 0 10 12 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
4633 19:57:03.490489 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 19:57:03.493693 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 19:57:03.497636 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 19:57:03.503747 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 19:57:03.506897 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 19:57:03.511118 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 19:57:03.517367 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 19:57:03.520081 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4641 19:57:03.523575 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 19:57:03.530166 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 19:57:03.534068 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 19:57:03.536913 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 19:57:03.544030 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 19:57:03.547061 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 19:57:03.550218 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 19:57:03.556631 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 19:57:03.560124 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 19:57:03.563293 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 19:57:03.569866 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 19:57:03.573670 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 19:57:03.576386 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 19:57:03.583238 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 19:57:03.586331 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4656 19:57:03.589439 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4657 19:57:03.593737 Total UI for P1: 0, mck2ui 16
4658 19:57:03.596378 best dqsien dly found for B0: ( 0, 13, 8)
4659 19:57:03.603060 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 19:57:03.603548 Total UI for P1: 0, mck2ui 16
4661 19:57:03.609993 best dqsien dly found for B1: ( 0, 13, 12)
4662 19:57:03.613339 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4663 19:57:03.616092 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4664 19:57:03.616552
4665 19:57:03.619342 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4666 19:57:03.622638 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4667 19:57:03.626782 [Gating] SW calibration Done
4668 19:57:03.627338 ==
4669 19:57:03.629514 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 19:57:03.632730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 19:57:03.633163 ==
4672 19:57:03.635901 RX Vref Scan: 0
4673 19:57:03.636316
4674 19:57:03.636644 RX Vref 0 -> 0, step: 1
4675 19:57:03.636950
4676 19:57:03.639587 RX Delay -230 -> 252, step: 16
4677 19:57:03.645812 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4678 19:57:03.649077 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4679 19:57:03.653038 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4680 19:57:03.656337 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4681 19:57:03.659470 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4682 19:57:03.666146 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4683 19:57:03.669363 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4684 19:57:03.672405 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4685 19:57:03.676094 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4686 19:57:03.682651 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4687 19:57:03.685476 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4688 19:57:03.689134 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4689 19:57:03.692064 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4690 19:57:03.699504 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4691 19:57:03.702723 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4692 19:57:03.705634 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4693 19:57:03.706120 ==
4694 19:57:03.709267 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 19:57:03.712495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 19:57:03.713195 ==
4697 19:57:03.715583 DQS Delay:
4698 19:57:03.715999 DQS0 = 0, DQS1 = 0
4699 19:57:03.718882 DQM Delay:
4700 19:57:03.719430 DQM0 = 36, DQM1 = 28
4701 19:57:03.719776 DQ Delay:
4702 19:57:03.722247 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4703 19:57:03.725982 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4704 19:57:03.729308 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4705 19:57:03.731836 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4706 19:57:03.732268
4707 19:57:03.732604
4708 19:57:03.735226 ==
4709 19:57:03.738605 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 19:57:03.742025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 19:57:03.742504 ==
4712 19:57:03.742845
4713 19:57:03.743150
4714 19:57:03.745617 TX Vref Scan disable
4715 19:57:03.746033 == TX Byte 0 ==
4716 19:57:03.751922 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4717 19:57:03.755458 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4718 19:57:03.755880 == TX Byte 1 ==
4719 19:57:03.761992 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4720 19:57:03.765411 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4721 19:57:03.766050 ==
4722 19:57:03.768936 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 19:57:03.772249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 19:57:03.772761 ==
4725 19:57:03.773094
4726 19:57:03.773400
4727 19:57:03.775076 TX Vref Scan disable
4728 19:57:03.778564 == TX Byte 0 ==
4729 19:57:03.781740 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4730 19:57:03.785016 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4731 19:57:03.788105 == TX Byte 1 ==
4732 19:57:03.791902 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4733 19:57:03.795826 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4734 19:57:03.796343
4735 19:57:03.798531 [DATLAT]
4736 19:57:03.798943 Freq=600, CH1 RK1
4737 19:57:03.799274
4738 19:57:03.801800 DATLAT Default: 0x9
4739 19:57:03.802214 0, 0xFFFF, sum = 0
4740 19:57:03.805231 1, 0xFFFF, sum = 0
4741 19:57:03.805754 2, 0xFFFF, sum = 0
4742 19:57:03.808551 3, 0xFFFF, sum = 0
4743 19:57:03.809070 4, 0xFFFF, sum = 0
4744 19:57:03.811925 5, 0xFFFF, sum = 0
4745 19:57:03.812349 6, 0xFFFF, sum = 0
4746 19:57:03.814915 7, 0xFFFF, sum = 0
4747 19:57:03.815335 8, 0x0, sum = 1
4748 19:57:03.818037 9, 0x0, sum = 2
4749 19:57:03.818493 10, 0x0, sum = 3
4750 19:57:03.821656 11, 0x0, sum = 4
4751 19:57:03.822083 best_step = 9
4752 19:57:03.822415
4753 19:57:03.822779 ==
4754 19:57:03.825244 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 19:57:03.831703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 19:57:03.832205 ==
4757 19:57:03.832543 RX Vref Scan: 0
4758 19:57:03.832855
4759 19:57:03.835099 RX Vref 0 -> 0, step: 1
4760 19:57:03.835558
4761 19:57:03.838117 RX Delay -195 -> 252, step: 8
4762 19:57:03.842084 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4763 19:57:03.847891 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4764 19:57:03.851365 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4765 19:57:03.855076 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4766 19:57:03.858449 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4767 19:57:03.861629 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4768 19:57:03.867920 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4769 19:57:03.871500 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4770 19:57:03.874488 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4771 19:57:03.878185 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4772 19:57:03.884703 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4773 19:57:03.887887 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4774 19:57:03.891627 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4775 19:57:03.894359 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4776 19:57:03.901772 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4777 19:57:03.904709 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4778 19:57:03.905264 ==
4779 19:57:03.908103 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 19:57:03.911289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 19:57:03.911735 ==
4782 19:57:03.914938 DQS Delay:
4783 19:57:03.915484 DQS0 = 0, DQS1 = 0
4784 19:57:03.915826 DQM Delay:
4785 19:57:03.918054 DQM0 = 36, DQM1 = 29
4786 19:57:03.918466 DQ Delay:
4787 19:57:03.921623 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4788 19:57:03.924398 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4789 19:57:03.927768 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4790 19:57:03.931123 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4791 19:57:03.931679
4792 19:57:03.932020
4793 19:57:03.940984 [DQSOSCAuto] RK1, (LSB)MR18= 0x3959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4794 19:57:03.941499 CH1 RK1: MR19=808, MR18=3959
4795 19:57:03.947898 CH1_RK1: MR19=0x808, MR18=0x3959, DQSOSC=393, MR23=63, INC=169, DEC=113
4796 19:57:03.950948 [RxdqsGatingPostProcess] freq 600
4797 19:57:03.957813 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4798 19:57:03.960636 Pre-setting of DQS Precalculation
4799 19:57:03.964038 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4800 19:57:03.970692 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4801 19:57:03.980810 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4802 19:57:03.981322
4803 19:57:03.981652
4804 19:57:03.984142 [Calibration Summary] 1200 Mbps
4805 19:57:03.984559 CH 0, Rank 0
4806 19:57:03.987153 SW Impedance : PASS
4807 19:57:03.987713 DUTY Scan : NO K
4808 19:57:03.990089 ZQ Calibration : PASS
4809 19:57:03.994146 Jitter Meter : NO K
4810 19:57:03.994664 CBT Training : PASS
4811 19:57:03.997604 Write leveling : PASS
4812 19:57:04.000425 RX DQS gating : PASS
4813 19:57:04.000934 RX DQ/DQS(RDDQC) : PASS
4814 19:57:04.004026 TX DQ/DQS : PASS
4815 19:57:04.004542 RX DATLAT : PASS
4816 19:57:04.007973 RX DQ/DQS(Engine): PASS
4817 19:57:04.010999 TX OE : NO K
4818 19:57:04.011559 All Pass.
4819 19:57:04.011897
4820 19:57:04.012204 CH 0, Rank 1
4821 19:57:04.014312 SW Impedance : PASS
4822 19:57:04.017522 DUTY Scan : NO K
4823 19:57:04.018038 ZQ Calibration : PASS
4824 19:57:04.020081 Jitter Meter : NO K
4825 19:57:04.023921 CBT Training : PASS
4826 19:57:04.024335 Write leveling : PASS
4827 19:57:04.026931 RX DQS gating : PASS
4828 19:57:04.030272 RX DQ/DQS(RDDQC) : PASS
4829 19:57:04.030778 TX DQ/DQS : PASS
4830 19:57:04.034307 RX DATLAT : PASS
4831 19:57:04.036932 RX DQ/DQS(Engine): PASS
4832 19:57:04.037446 TX OE : NO K
4833 19:57:04.040315 All Pass.
4834 19:57:04.040821
4835 19:57:04.041150 CH 1, Rank 0
4836 19:57:04.043718 SW Impedance : PASS
4837 19:57:04.044133 DUTY Scan : NO K
4838 19:57:04.046457 ZQ Calibration : PASS
4839 19:57:04.049767 Jitter Meter : NO K
4840 19:57:04.050183 CBT Training : PASS
4841 19:57:04.053299 Write leveling : PASS
4842 19:57:04.056582 RX DQS gating : PASS
4843 19:57:04.057000 RX DQ/DQS(RDDQC) : PASS
4844 19:57:04.060203 TX DQ/DQS : PASS
4845 19:57:04.063795 RX DATLAT : PASS
4846 19:57:04.064309 RX DQ/DQS(Engine): PASS
4847 19:57:04.067286 TX OE : NO K
4848 19:57:04.067849 All Pass.
4849 19:57:04.068187
4850 19:57:04.070095 CH 1, Rank 1
4851 19:57:04.070607 SW Impedance : PASS
4852 19:57:04.073843 DUTY Scan : NO K
4853 19:57:04.074353 ZQ Calibration : PASS
4854 19:57:04.076429 Jitter Meter : NO K
4855 19:57:04.080075 CBT Training : PASS
4856 19:57:04.080512 Write leveling : PASS
4857 19:57:04.082622 RX DQS gating : PASS
4858 19:57:04.086343 RX DQ/DQS(RDDQC) : PASS
4859 19:57:04.086876 TX DQ/DQS : PASS
4860 19:57:04.089292 RX DATLAT : PASS
4861 19:57:04.093008 RX DQ/DQS(Engine): PASS
4862 19:57:04.093424 TX OE : NO K
4863 19:57:04.096550 All Pass.
4864 19:57:04.097061
4865 19:57:04.097394 DramC Write-DBI off
4866 19:57:04.099699 PER_BANK_REFRESH: Hybrid Mode
4867 19:57:04.102934 TX_TRACKING: ON
4868 19:57:04.109375 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4869 19:57:04.113577 [FAST_K] Save calibration result to emmc
4870 19:57:04.116342 dramc_set_vcore_voltage set vcore to 662500
4871 19:57:04.119503 Read voltage for 933, 3
4872 19:57:04.119922 Vio18 = 0
4873 19:57:04.122817 Vcore = 662500
4874 19:57:04.123240 Vdram = 0
4875 19:57:04.123628 Vddq = 0
4876 19:57:04.126547 Vmddr = 0
4877 19:57:04.129841 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4878 19:57:04.136306 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4879 19:57:04.136819 MEM_TYPE=3, freq_sel=17
4880 19:57:04.139725 sv_algorithm_assistance_LP4_1600
4881 19:57:04.145792 ============ PULL DRAM RESETB DOWN ============
4882 19:57:04.149035 ========== PULL DRAM RESETB DOWN end =========
4883 19:57:04.152557 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4884 19:57:04.155850 ===================================
4885 19:57:04.159254 LPDDR4 DRAM CONFIGURATION
4886 19:57:04.163001 ===================================
4887 19:57:04.165778 EX_ROW_EN[0] = 0x0
4888 19:57:04.166292 EX_ROW_EN[1] = 0x0
4889 19:57:04.169154 LP4Y_EN = 0x0
4890 19:57:04.169664 WORK_FSP = 0x0
4891 19:57:04.172227 WL = 0x3
4892 19:57:04.172734 RL = 0x3
4893 19:57:04.176201 BL = 0x2
4894 19:57:04.176713 RPST = 0x0
4895 19:57:04.179170 RD_PRE = 0x0
4896 19:57:04.179708 WR_PRE = 0x1
4897 19:57:04.182682 WR_PST = 0x0
4898 19:57:04.183246 DBI_WR = 0x0
4899 19:57:04.185745 DBI_RD = 0x0
4900 19:57:04.186161 OTF = 0x1
4901 19:57:04.189393 ===================================
4902 19:57:04.192833 ===================================
4903 19:57:04.195437 ANA top config
4904 19:57:04.199466 ===================================
4905 19:57:04.202629 DLL_ASYNC_EN = 0
4906 19:57:04.203141 ALL_SLAVE_EN = 1
4907 19:57:04.206094 NEW_RANK_MODE = 1
4908 19:57:04.209073 DLL_IDLE_MODE = 1
4909 19:57:04.212053 LP45_APHY_COMB_EN = 1
4910 19:57:04.212463 TX_ODT_DIS = 1
4911 19:57:04.215666 NEW_8X_MODE = 1
4912 19:57:04.218809 ===================================
4913 19:57:04.222000 ===================================
4914 19:57:04.225501 data_rate = 1866
4915 19:57:04.229159 CKR = 1
4916 19:57:04.231984 DQ_P2S_RATIO = 8
4917 19:57:04.235612 ===================================
4918 19:57:04.239017 CA_P2S_RATIO = 8
4919 19:57:04.239609 DQ_CA_OPEN = 0
4920 19:57:04.242195 DQ_SEMI_OPEN = 0
4921 19:57:04.245647 CA_SEMI_OPEN = 0
4922 19:57:04.248748 CA_FULL_RATE = 0
4923 19:57:04.252107 DQ_CKDIV4_EN = 1
4924 19:57:04.252585 CA_CKDIV4_EN = 1
4925 19:57:04.255293 CA_PREDIV_EN = 0
4926 19:57:04.258785 PH8_DLY = 0
4927 19:57:04.262389 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4928 19:57:04.265711 DQ_AAMCK_DIV = 4
4929 19:57:04.268737 CA_AAMCK_DIV = 4
4930 19:57:04.271819 CA_ADMCK_DIV = 4
4931 19:57:04.272282 DQ_TRACK_CA_EN = 0
4932 19:57:04.275555 CA_PICK = 933
4933 19:57:04.279102 CA_MCKIO = 933
4934 19:57:04.282118 MCKIO_SEMI = 0
4935 19:57:04.285466 PLL_FREQ = 3732
4936 19:57:04.288694 DQ_UI_PI_RATIO = 32
4937 19:57:04.291931 CA_UI_PI_RATIO = 0
4938 19:57:04.295274 ===================================
4939 19:57:04.295877 ===================================
4940 19:57:04.298818 memory_type:LPDDR4
4941 19:57:04.301663 GP_NUM : 10
4942 19:57:04.302121 SRAM_EN : 1
4943 19:57:04.305457 MD32_EN : 0
4944 19:57:04.308544 ===================================
4945 19:57:04.311867 [ANA_INIT] >>>>>>>>>>>>>>
4946 19:57:04.315193 <<<<<< [CONFIGURE PHASE]: ANA_TX
4947 19:57:04.318776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4948 19:57:04.321699 ===================================
4949 19:57:04.324823 data_rate = 1866,PCW = 0X8f00
4950 19:57:04.325457 ===================================
4951 19:57:04.332001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4952 19:57:04.334845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4953 19:57:04.341640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4954 19:57:04.345025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4955 19:57:04.348590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4956 19:57:04.351606 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4957 19:57:04.355206 [ANA_INIT] flow start
4958 19:57:04.358519 [ANA_INIT] PLL >>>>>>>>
4959 19:57:04.359063 [ANA_INIT] PLL <<<<<<<<
4960 19:57:04.361960 [ANA_INIT] MIDPI >>>>>>>>
4961 19:57:04.365163 [ANA_INIT] MIDPI <<<<<<<<
4962 19:57:04.365715 [ANA_INIT] DLL >>>>>>>>
4963 19:57:04.368644 [ANA_INIT] flow end
4964 19:57:04.371770 ============ LP4 DIFF to SE enter ============
4965 19:57:04.374862 ============ LP4 DIFF to SE exit ============
4966 19:57:04.377991 [ANA_INIT] <<<<<<<<<<<<<
4967 19:57:04.381369 [Flow] Enable top DCM control >>>>>
4968 19:57:04.384509 [Flow] Enable top DCM control <<<<<
4969 19:57:04.388315 Enable DLL master slave shuffle
4970 19:57:04.394291 ==============================================================
4971 19:57:04.394753 Gating Mode config
4972 19:57:04.400818 ==============================================================
4973 19:57:04.404488 Config description:
4974 19:57:04.411034 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4975 19:57:04.417869 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4976 19:57:04.424397 SELPH_MODE 0: By rank 1: By Phase
4977 19:57:04.431107 ==============================================================
4978 19:57:04.434208 GAT_TRACK_EN = 1
4979 19:57:04.434672 RX_GATING_MODE = 2
4980 19:57:04.437429 RX_GATING_TRACK_MODE = 2
4981 19:57:04.441185 SELPH_MODE = 1
4982 19:57:04.443930 PICG_EARLY_EN = 1
4983 19:57:04.447586 VALID_LAT_VALUE = 1
4984 19:57:04.454028 ==============================================================
4985 19:57:04.457744 Enter into Gating configuration >>>>
4986 19:57:04.461772 Exit from Gating configuration <<<<
4987 19:57:04.464146 Enter into DVFS_PRE_config >>>>>
4988 19:57:04.474388 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4989 19:57:04.477071 Exit from DVFS_PRE_config <<<<<
4990 19:57:04.480865 Enter into PICG configuration >>>>
4991 19:57:04.483884 Exit from PICG configuration <<<<
4992 19:57:04.487332 [RX_INPUT] configuration >>>>>
4993 19:57:04.490229 [RX_INPUT] configuration <<<<<
4994 19:57:04.493914 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4995 19:57:04.500233 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4996 19:57:04.506996 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4997 19:57:04.510635 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4998 19:57:04.516799 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4999 19:57:04.523861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5000 19:57:04.527089 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5001 19:57:04.533530 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5002 19:57:04.537576 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5003 19:57:04.540470 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5004 19:57:04.543503 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5005 19:57:04.550225 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 19:57:04.553781 ===================================
5007 19:57:04.554342 LPDDR4 DRAM CONFIGURATION
5008 19:57:04.556992 ===================================
5009 19:57:04.560031 EX_ROW_EN[0] = 0x0
5010 19:57:04.563331 EX_ROW_EN[1] = 0x0
5011 19:57:04.563936 LP4Y_EN = 0x0
5012 19:57:04.566763 WORK_FSP = 0x0
5013 19:57:04.567310 WL = 0x3
5014 19:57:04.570044 RL = 0x3
5015 19:57:04.570598 BL = 0x2
5016 19:57:04.573206 RPST = 0x0
5017 19:57:04.573796 RD_PRE = 0x0
5018 19:57:04.576539 WR_PRE = 0x1
5019 19:57:04.576995 WR_PST = 0x0
5020 19:57:04.579902 DBI_WR = 0x0
5021 19:57:04.580358 DBI_RD = 0x0
5022 19:57:04.582997 OTF = 0x1
5023 19:57:04.586485 ===================================
5024 19:57:04.589822 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5025 19:57:04.593262 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5026 19:57:04.600058 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5027 19:57:04.603256 ===================================
5028 19:57:04.603879 LPDDR4 DRAM CONFIGURATION
5029 19:57:04.606591 ===================================
5030 19:57:04.609584 EX_ROW_EN[0] = 0x10
5031 19:57:04.612825 EX_ROW_EN[1] = 0x0
5032 19:57:04.613286 LP4Y_EN = 0x0
5033 19:57:04.616428 WORK_FSP = 0x0
5034 19:57:04.616882 WL = 0x3
5035 19:57:04.619544 RL = 0x3
5036 19:57:04.620011 BL = 0x2
5037 19:57:04.623211 RPST = 0x0
5038 19:57:04.623815 RD_PRE = 0x0
5039 19:57:04.626328 WR_PRE = 0x1
5040 19:57:04.626784 WR_PST = 0x0
5041 19:57:04.630221 DBI_WR = 0x0
5042 19:57:04.630776 DBI_RD = 0x0
5043 19:57:04.632772 OTF = 0x1
5044 19:57:04.636275 ===================================
5045 19:57:04.643537 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5046 19:57:04.646294 nWR fixed to 30
5047 19:57:04.646754 [ModeRegInit_LP4] CH0 RK0
5048 19:57:04.649706 [ModeRegInit_LP4] CH0 RK1
5049 19:57:04.652576 [ModeRegInit_LP4] CH1 RK0
5050 19:57:04.656213 [ModeRegInit_LP4] CH1 RK1
5051 19:57:04.656765 match AC timing 9
5052 19:57:04.659503 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5053 19:57:04.666365 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5054 19:57:04.669795 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5055 19:57:04.676070 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5056 19:57:04.679547 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5057 19:57:04.680110 ==
5058 19:57:04.682923 Dram Type= 6, Freq= 0, CH_0, rank 0
5059 19:57:04.685951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5060 19:57:04.686418 ==
5061 19:57:04.693334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5062 19:57:04.699233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5063 19:57:04.702477 [CA 0] Center 38 (8~69) winsize 62
5064 19:57:04.705949 [CA 1] Center 38 (7~69) winsize 63
5065 19:57:04.709593 [CA 2] Center 35 (5~65) winsize 61
5066 19:57:04.712859 [CA 3] Center 35 (5~65) winsize 61
5067 19:57:04.716057 [CA 4] Center 34 (4~64) winsize 61
5068 19:57:04.719077 [CA 5] Center 33 (3~64) winsize 62
5069 19:57:04.719669
5070 19:57:04.722835 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5071 19:57:04.723379
5072 19:57:04.725585 [CATrainingPosCal] consider 1 rank data
5073 19:57:04.729001 u2DelayCellTimex100 = 270/100 ps
5074 19:57:04.732560 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5075 19:57:04.735451 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5076 19:57:04.739065 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5077 19:57:04.742137 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5078 19:57:04.745343 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5079 19:57:04.748991 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5080 19:57:04.749545
5081 19:57:04.755777 CA PerBit enable=1, Macro0, CA PI delay=33
5082 19:57:04.756331
5083 19:57:04.758769 [CBTSetCACLKResult] CA Dly = 33
5084 19:57:04.759314 CS Dly: 7 (0~38)
5085 19:57:04.759742 ==
5086 19:57:04.762280 Dram Type= 6, Freq= 0, CH_0, rank 1
5087 19:57:04.765437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 19:57:04.765902 ==
5089 19:57:04.771737 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 19:57:04.778962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5091 19:57:04.781773 [CA 0] Center 38 (8~69) winsize 62
5092 19:57:04.784911 [CA 1] Center 38 (8~69) winsize 62
5093 19:57:04.788960 [CA 2] Center 35 (5~66) winsize 62
5094 19:57:04.791877 [CA 3] Center 35 (5~66) winsize 62
5095 19:57:04.795090 [CA 4] Center 34 (4~65) winsize 62
5096 19:57:04.798421 [CA 5] Center 33 (3~64) winsize 62
5097 19:57:04.798910
5098 19:57:04.801817 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5099 19:57:04.802270
5100 19:57:04.805326 [CATrainingPosCal] consider 2 rank data
5101 19:57:04.808466 u2DelayCellTimex100 = 270/100 ps
5102 19:57:04.811326 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5103 19:57:04.814816 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5104 19:57:04.818616 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5105 19:57:04.821385 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5106 19:57:04.827977 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5107 19:57:04.831872 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5108 19:57:04.832289
5109 19:57:04.834997 CA PerBit enable=1, Macro0, CA PI delay=33
5110 19:57:04.835446
5111 19:57:04.837964 [CBTSetCACLKResult] CA Dly = 33
5112 19:57:04.838377 CS Dly: 7 (0~39)
5113 19:57:04.838704
5114 19:57:04.841635 ----->DramcWriteLeveling(PI) begin...
5115 19:57:04.842051 ==
5116 19:57:04.845160 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 19:57:04.851328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 19:57:04.851874 ==
5119 19:57:04.854710 Write leveling (Byte 0): 28 => 28
5120 19:57:04.855361 Write leveling (Byte 1): 27 => 27
5121 19:57:04.858201 DramcWriteLeveling(PI) end<-----
5122 19:57:04.858614
5123 19:57:04.861298 ==
5124 19:57:04.864771 Dram Type= 6, Freq= 0, CH_0, rank 0
5125 19:57:04.867738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 19:57:04.868158 ==
5127 19:57:04.871560 [Gating] SW mode calibration
5128 19:57:04.877769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5129 19:57:04.881444 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5130 19:57:04.888180 0 14 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5131 19:57:04.891041 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5132 19:57:04.894441 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 19:57:04.901014 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 19:57:04.904319 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 19:57:04.907879 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 19:57:04.914256 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 19:57:04.917881 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 19:57:04.921067 0 15 0 | B1->B0 | 3333 2d2d | 0 1 | (0 0) (0 0)
5139 19:57:04.927393 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5140 19:57:04.930719 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 19:57:04.933676 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 19:57:04.940308 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 19:57:04.944110 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 19:57:04.947393 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 19:57:04.953806 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5146 19:57:04.956979 1 0 0 | B1->B0 | 2929 3a3a | 0 0 | (0 0) (0 0)
5147 19:57:04.960124 1 0 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5148 19:57:04.966790 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 19:57:04.969985 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 19:57:04.973480 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 19:57:04.979941 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 19:57:04.983500 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 19:57:04.986917 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5154 19:57:04.993296 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5155 19:57:04.996594 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5156 19:57:04.999957 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 19:57:05.003336 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 19:57:05.010046 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 19:57:05.013514 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 19:57:05.019637 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 19:57:05.022854 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 19:57:05.026593 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 19:57:05.033188 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 19:57:05.036180 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 19:57:05.039543 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 19:57:05.045896 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 19:57:05.049167 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 19:57:05.053085 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 19:57:05.059576 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 19:57:05.062885 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5171 19:57:05.066185 Total UI for P1: 0, mck2ui 16
5172 19:57:05.069582 best dqsien dly found for B0: ( 1, 2, 30)
5173 19:57:05.072421 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5174 19:57:05.075938 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 19:57:05.079173 Total UI for P1: 0, mck2ui 16
5176 19:57:05.082317 best dqsien dly found for B1: ( 1, 3, 2)
5177 19:57:05.085582 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5178 19:57:05.092206 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5179 19:57:05.092325
5180 19:57:05.095584 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5181 19:57:05.098989 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5182 19:57:05.102218 [Gating] SW calibration Done
5183 19:57:05.102299 ==
5184 19:57:05.105600 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 19:57:05.108726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 19:57:05.108808 ==
5187 19:57:05.108873 RX Vref Scan: 0
5188 19:57:05.112397
5189 19:57:05.112480 RX Vref 0 -> 0, step: 1
5190 19:57:05.112545
5191 19:57:05.115763 RX Delay -80 -> 252, step: 8
5192 19:57:05.118946 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5193 19:57:05.122520 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5194 19:57:05.129639 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5195 19:57:05.132289 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5196 19:57:05.135630 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5197 19:57:05.138687 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5198 19:57:05.142125 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5199 19:57:05.145681 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5200 19:57:05.151891 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5201 19:57:05.155771 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5202 19:57:05.158957 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5203 19:57:05.162192 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5204 19:57:05.165478 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5205 19:57:05.171783 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5206 19:57:05.175338 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5207 19:57:05.178892 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5208 19:57:05.179067 ==
5209 19:57:05.182002 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 19:57:05.185080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 19:57:05.188266 ==
5212 19:57:05.188484 DQS Delay:
5213 19:57:05.188625 DQS0 = 0, DQS1 = 0
5214 19:57:05.192374 DQM Delay:
5215 19:57:05.192627 DQM0 = 94, DQM1 = 82
5216 19:57:05.195058 DQ Delay:
5217 19:57:05.195264 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5218 19:57:05.199225 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5219 19:57:05.202071 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5220 19:57:05.208195 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5221 19:57:05.208537
5222 19:57:05.208811
5223 19:57:05.209096 ==
5224 19:57:05.212055 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 19:57:05.215325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 19:57:05.216039 ==
5227 19:57:05.216416
5228 19:57:05.216760
5229 19:57:05.218674 TX Vref Scan disable
5230 19:57:05.219224 == TX Byte 0 ==
5231 19:57:05.225546 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5232 19:57:05.228560 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5233 19:57:05.229117 == TX Byte 1 ==
5234 19:57:05.234788 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5235 19:57:05.238566 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5236 19:57:05.239119 ==
5237 19:57:05.241884 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 19:57:05.244992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 19:57:05.245554 ==
5240 19:57:05.245917
5241 19:57:05.246409
5242 19:57:05.247909 TX Vref Scan disable
5243 19:57:05.251541 == TX Byte 0 ==
5244 19:57:05.255220 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5245 19:57:05.258222 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5246 19:57:05.261449 == TX Byte 1 ==
5247 19:57:05.265536 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5248 19:57:05.268021 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5249 19:57:05.268477
5250 19:57:05.271576 [DATLAT]
5251 19:57:05.272031 Freq=933, CH0 RK0
5252 19:57:05.272395
5253 19:57:05.275040 DATLAT Default: 0xd
5254 19:57:05.275639 0, 0xFFFF, sum = 0
5255 19:57:05.277737 1, 0xFFFF, sum = 0
5256 19:57:05.278198 2, 0xFFFF, sum = 0
5257 19:57:05.281421 3, 0xFFFF, sum = 0
5258 19:57:05.281885 4, 0xFFFF, sum = 0
5259 19:57:05.284985 5, 0xFFFF, sum = 0
5260 19:57:05.285440 6, 0xFFFF, sum = 0
5261 19:57:05.288179 7, 0xFFFF, sum = 0
5262 19:57:05.291102 8, 0xFFFF, sum = 0
5263 19:57:05.291607 9, 0xFFFF, sum = 0
5264 19:57:05.294547 10, 0x0, sum = 1
5265 19:57:05.295009 11, 0x0, sum = 2
5266 19:57:05.295378 12, 0x0, sum = 3
5267 19:57:05.298116 13, 0x0, sum = 4
5268 19:57:05.298599 best_step = 11
5269 19:57:05.298968
5270 19:57:05.299368 ==
5271 19:57:05.301316 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 19:57:05.307661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 19:57:05.308073 ==
5274 19:57:05.308396 RX Vref Scan: 1
5275 19:57:05.308740
5276 19:57:05.311496 RX Vref 0 -> 0, step: 1
5277 19:57:05.311908
5278 19:57:05.314627 RX Delay -69 -> 252, step: 4
5279 19:57:05.315036
5280 19:57:05.318177 Set Vref, RX VrefLevel [Byte0]: 62
5281 19:57:05.321209 [Byte1]: 57
5282 19:57:05.321620
5283 19:57:05.324061 Final RX Vref Byte 0 = 62 to rank0
5284 19:57:05.327970 Final RX Vref Byte 1 = 57 to rank0
5285 19:57:05.331552 Final RX Vref Byte 0 = 62 to rank1
5286 19:57:05.334653 Final RX Vref Byte 1 = 57 to rank1==
5287 19:57:05.337774 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 19:57:05.340856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 19:57:05.341269 ==
5290 19:57:05.344742 DQS Delay:
5291 19:57:05.345255 DQS0 = 0, DQS1 = 0
5292 19:57:05.347526 DQM Delay:
5293 19:57:05.347933 DQM0 = 95, DQM1 = 84
5294 19:57:05.348257 DQ Delay:
5295 19:57:05.351240 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5296 19:57:05.354494 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5297 19:57:05.357771 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =78
5298 19:57:05.361128 DQ12 =88, DQ13 =90, DQ14 =94, DQ15 =90
5299 19:57:05.361535
5300 19:57:05.363930
5301 19:57:05.371088 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5302 19:57:05.374355 CH0 RK0: MR19=505, MR18=1212
5303 19:57:05.380869 CH0_RK0: MR19=0x505, MR18=0x1212, DQSOSC=416, MR23=63, INC=62, DEC=41
5304 19:57:05.381432
5305 19:57:05.383925 ----->DramcWriteLeveling(PI) begin...
5306 19:57:05.384339 ==
5307 19:57:05.387359 Dram Type= 6, Freq= 0, CH_0, rank 1
5308 19:57:05.390844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 19:57:05.391487 ==
5310 19:57:05.394387 Write leveling (Byte 0): 31 => 31
5311 19:57:05.397113 Write leveling (Byte 1): 30 => 30
5312 19:57:05.400428 DramcWriteLeveling(PI) end<-----
5313 19:57:05.400840
5314 19:57:05.401162 ==
5315 19:57:05.404224 Dram Type= 6, Freq= 0, CH_0, rank 1
5316 19:57:05.407163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 19:57:05.407678 ==
5318 19:57:05.410620 [Gating] SW mode calibration
5319 19:57:05.417229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5320 19:57:05.423943 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5321 19:57:05.427015 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5322 19:57:05.430539 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5323 19:57:05.436817 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 19:57:05.440365 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 19:57:05.444035 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 19:57:05.450871 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 19:57:05.454119 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 19:57:05.457514 0 14 28 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (1 1)
5329 19:57:05.464043 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5330 19:57:05.467126 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 19:57:05.470526 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 19:57:05.477520 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 19:57:05.480249 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 19:57:05.483663 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 19:57:05.490662 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 19:57:05.493874 0 15 28 | B1->B0 | 2626 3232 | 0 1 | (1 1) (0 0)
5337 19:57:05.496960 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5338 19:57:05.504015 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 19:57:05.507225 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 19:57:05.510567 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 19:57:05.516974 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 19:57:05.520189 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 19:57:05.523602 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 19:57:05.530116 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5345 19:57:05.533893 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5346 19:57:05.536646 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 19:57:05.540213 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 19:57:05.546673 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 19:57:05.549969 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 19:57:05.553070 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 19:57:05.560239 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 19:57:05.563378 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 19:57:05.567007 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 19:57:05.573487 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 19:57:05.576906 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 19:57:05.580093 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 19:57:05.586614 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 19:57:05.589516 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 19:57:05.593049 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 19:57:05.599910 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 19:57:05.603713 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 19:57:05.606328 Total UI for P1: 0, mck2ui 16
5363 19:57:05.609654 best dqsien dly found for B0: ( 1, 2, 30)
5364 19:57:05.613062 Total UI for P1: 0, mck2ui 16
5365 19:57:05.616369 best dqsien dly found for B1: ( 1, 2, 30)
5366 19:57:05.619846 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5367 19:57:05.622903 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5368 19:57:05.623362
5369 19:57:05.626405 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5370 19:57:05.629908 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5371 19:57:05.633336 [Gating] SW calibration Done
5372 19:57:05.633911 ==
5373 19:57:05.636158 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 19:57:05.642813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 19:57:05.643273 ==
5376 19:57:05.643802 RX Vref Scan: 0
5377 19:57:05.644154
5378 19:57:05.646274 RX Vref 0 -> 0, step: 1
5379 19:57:05.646728
5380 19:57:05.649494 RX Delay -80 -> 252, step: 8
5381 19:57:05.653074 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5382 19:57:05.656128 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5383 19:57:05.659785 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5384 19:57:05.662584 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5385 19:57:05.669054 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5386 19:57:05.672544 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5387 19:57:05.675608 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5388 19:57:05.678946 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5389 19:57:05.682378 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5390 19:57:05.685778 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5391 19:57:05.691966 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5392 19:57:05.695441 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5393 19:57:05.698601 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5394 19:57:05.702188 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5395 19:57:05.709149 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5396 19:57:05.711911 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5397 19:57:05.712152 ==
5398 19:57:05.715551 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 19:57:05.718837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 19:57:05.719165 ==
5401 19:57:05.719367 DQS Delay:
5402 19:57:05.722561 DQS0 = 0, DQS1 = 0
5403 19:57:05.722953 DQM Delay:
5404 19:57:05.725469 DQM0 = 92, DQM1 = 83
5405 19:57:05.725852 DQ Delay:
5406 19:57:05.729602 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =91
5407 19:57:05.732444 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5408 19:57:05.736131 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5409 19:57:05.738979 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5410 19:57:05.739489
5411 19:57:05.739860
5412 19:57:05.740270 ==
5413 19:57:05.742333 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 19:57:05.749042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 19:57:05.749604 ==
5416 19:57:05.749974
5417 19:57:05.750349
5418 19:57:05.750675 TX Vref Scan disable
5419 19:57:05.752199 == TX Byte 0 ==
5420 19:57:05.755493 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5421 19:57:05.762157 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5422 19:57:05.762708 == TX Byte 1 ==
5423 19:57:05.764899 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5424 19:57:05.772014 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5425 19:57:05.772664 ==
5426 19:57:05.775340 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 19:57:05.778319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 19:57:05.778781 ==
5429 19:57:05.779142
5430 19:57:05.779530
5431 19:57:05.781644 TX Vref Scan disable
5432 19:57:05.782099 == TX Byte 0 ==
5433 19:57:05.788407 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5434 19:57:05.791868 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5435 19:57:05.792495 == TX Byte 1 ==
5436 19:57:05.798201 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5437 19:57:05.801497 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5438 19:57:05.801954
5439 19:57:05.802365 [DATLAT]
5440 19:57:05.805229 Freq=933, CH0 RK1
5441 19:57:05.805791
5442 19:57:05.806155 DATLAT Default: 0xb
5443 19:57:05.808028 0, 0xFFFF, sum = 0
5444 19:57:05.808546 1, 0xFFFF, sum = 0
5445 19:57:05.811595 2, 0xFFFF, sum = 0
5446 19:57:05.812156 3, 0xFFFF, sum = 0
5447 19:57:05.814658 4, 0xFFFF, sum = 0
5448 19:57:05.818305 5, 0xFFFF, sum = 0
5449 19:57:05.818767 6, 0xFFFF, sum = 0
5450 19:57:05.821886 7, 0xFFFF, sum = 0
5451 19:57:05.822444 8, 0xFFFF, sum = 0
5452 19:57:05.824800 9, 0xFFFF, sum = 0
5453 19:57:05.825264 10, 0x0, sum = 1
5454 19:57:05.827753 11, 0x0, sum = 2
5455 19:57:05.828217 12, 0x0, sum = 3
5456 19:57:05.828586 13, 0x0, sum = 4
5457 19:57:05.831637 best_step = 11
5458 19:57:05.832185
5459 19:57:05.832550 ==
5460 19:57:05.834707 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 19:57:05.838152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 19:57:05.838746 ==
5463 19:57:05.841295 RX Vref Scan: 0
5464 19:57:05.841850
5465 19:57:05.845048 RX Vref 0 -> 0, step: 1
5466 19:57:05.845603
5467 19:57:05.845965 RX Delay -69 -> 252, step: 4
5468 19:57:05.852571 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5469 19:57:05.856067 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5470 19:57:05.859175 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5471 19:57:05.863075 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5472 19:57:05.865349 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5473 19:57:05.872272 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5474 19:57:05.875834 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5475 19:57:05.878532 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5476 19:57:05.882680 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5477 19:57:05.886005 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5478 19:57:05.889065 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5479 19:57:05.895370 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5480 19:57:05.898291 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5481 19:57:05.901598 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5482 19:57:05.905348 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5483 19:57:05.911976 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5484 19:57:05.912389 ==
5485 19:57:05.915083 Dram Type= 6, Freq= 0, CH_0, rank 1
5486 19:57:05.918061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 19:57:05.918474 ==
5488 19:57:05.918800 DQS Delay:
5489 19:57:05.922105 DQS0 = 0, DQS1 = 0
5490 19:57:05.922514 DQM Delay:
5491 19:57:05.925224 DQM0 = 92, DQM1 = 84
5492 19:57:05.925638 DQ Delay:
5493 19:57:05.928125 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5494 19:57:05.931380 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5495 19:57:05.935216 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5496 19:57:05.938303 DQ12 =90, DQ13 =88, DQ14 =96, DQ15 =92
5497 19:57:05.938719
5498 19:57:05.939042
5499 19:57:05.944971 [DQSOSCAuto] RK1, (LSB)MR18= 0x3314, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
5500 19:57:05.948012 CH0 RK1: MR19=505, MR18=3314
5501 19:57:05.954752 CH0_RK1: MR19=0x505, MR18=0x3314, DQSOSC=405, MR23=63, INC=66, DEC=44
5502 19:57:05.957968 [RxdqsGatingPostProcess] freq 933
5503 19:57:05.964719 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5504 19:57:05.967997 best DQS0 dly(2T, 0.5T) = (0, 10)
5505 19:57:05.971238 best DQS1 dly(2T, 0.5T) = (0, 11)
5506 19:57:05.974260 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5507 19:57:05.978202 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5508 19:57:05.978770 best DQS0 dly(2T, 0.5T) = (0, 10)
5509 19:57:05.981737 best DQS1 dly(2T, 0.5T) = (0, 10)
5510 19:57:05.985128 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5511 19:57:05.988031 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5512 19:57:05.991362 Pre-setting of DQS Precalculation
5513 19:57:05.997671 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5514 19:57:05.998219 ==
5515 19:57:06.000692 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 19:57:06.004471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 19:57:06.005031 ==
5518 19:57:06.011005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 19:57:06.017696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5520 19:57:06.021037 [CA 0] Center 37 (7~67) winsize 61
5521 19:57:06.024134 [CA 1] Center 37 (7~68) winsize 62
5522 19:57:06.027625 [CA 2] Center 34 (5~64) winsize 60
5523 19:57:06.030904 [CA 3] Center 34 (5~64) winsize 60
5524 19:57:06.034344 [CA 4] Center 35 (5~65) winsize 61
5525 19:57:06.037117 [CA 5] Center 33 (4~63) winsize 60
5526 19:57:06.037578
5527 19:57:06.040478 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5528 19:57:06.040939
5529 19:57:06.043776 [CATrainingPosCal] consider 1 rank data
5530 19:57:06.047311 u2DelayCellTimex100 = 270/100 ps
5531 19:57:06.050449 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5532 19:57:06.053567 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5533 19:57:06.057018 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5534 19:57:06.060259 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5535 19:57:06.063763 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5536 19:57:06.066925 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5537 19:57:06.067529
5538 19:57:06.073873 CA PerBit enable=1, Macro0, CA PI delay=33
5539 19:57:06.074423
5540 19:57:06.074789 [CBTSetCACLKResult] CA Dly = 33
5541 19:57:06.077231 CS Dly: 6 (0~37)
5542 19:57:06.077783 ==
5543 19:57:06.080516 Dram Type= 6, Freq= 0, CH_1, rank 1
5544 19:57:06.083522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 19:57:06.083988 ==
5546 19:57:06.089987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 19:57:06.096736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5548 19:57:06.099994 [CA 0] Center 37 (8~67) winsize 60
5549 19:57:06.103565 [CA 1] Center 37 (7~68) winsize 62
5550 19:57:06.107255 [CA 2] Center 35 (5~65) winsize 61
5551 19:57:06.110124 [CA 3] Center 34 (4~64) winsize 61
5552 19:57:06.113564 [CA 4] Center 35 (5~65) winsize 61
5553 19:57:06.116714 [CA 5] Center 34 (4~64) winsize 61
5554 19:57:06.117265
5555 19:57:06.120146 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5556 19:57:06.120702
5557 19:57:06.123516 [CATrainingPosCal] consider 2 rank data
5558 19:57:06.126380 u2DelayCellTimex100 = 270/100 ps
5559 19:57:06.130658 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5560 19:57:06.133192 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5561 19:57:06.136236 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5562 19:57:06.139856 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5563 19:57:06.146618 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5564 19:57:06.149679 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5565 19:57:06.150142
5566 19:57:06.152757 CA PerBit enable=1, Macro0, CA PI delay=33
5567 19:57:06.153219
5568 19:57:06.156289 [CBTSetCACLKResult] CA Dly = 33
5569 19:57:06.156824 CS Dly: 7 (0~39)
5570 19:57:06.157189
5571 19:57:06.159955 ----->DramcWriteLeveling(PI) begin...
5572 19:57:06.160424 ==
5573 19:57:06.162905 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 19:57:06.170029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 19:57:06.170601 ==
5576 19:57:06.172936 Write leveling (Byte 0): 25 => 25
5577 19:57:06.176544 Write leveling (Byte 1): 27 => 27
5578 19:57:06.177132 DramcWriteLeveling(PI) end<-----
5579 19:57:06.177506
5580 19:57:06.179543 ==
5581 19:57:06.182756 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 19:57:06.186420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 19:57:06.186884 ==
5584 19:57:06.189503 [Gating] SW mode calibration
5585 19:57:06.196402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5586 19:57:06.198894 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5587 19:57:06.205729 0 14 0 | B1->B0 | 3232 3131 | 1 1 | (0 0) (0 0)
5588 19:57:06.208834 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 19:57:06.211909 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 19:57:06.218953 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 19:57:06.222568 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 19:57:06.225881 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 19:57:06.231827 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5594 19:57:06.235033 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5595 19:57:06.238694 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5596 19:57:06.245285 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 19:57:06.248618 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 19:57:06.251853 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 19:57:06.259506 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 19:57:06.262211 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 19:57:06.265381 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 19:57:06.271729 0 15 28 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
5603 19:57:06.275294 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5604 19:57:06.278484 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 19:57:06.285022 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 19:57:06.288590 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 19:57:06.291897 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 19:57:06.298491 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 19:57:06.301705 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 19:57:06.304920 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5611 19:57:06.311278 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5612 19:57:06.315012 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 19:57:06.318373 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 19:57:06.324930 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 19:57:06.328217 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 19:57:06.331029 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 19:57:06.337877 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 19:57:06.341474 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 19:57:06.344637 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 19:57:06.351417 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 19:57:06.354455 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 19:57:06.358002 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 19:57:06.364582 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 19:57:06.367809 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 19:57:06.371352 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 19:57:06.378020 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5627 19:57:06.378529 Total UI for P1: 0, mck2ui 16
5628 19:57:06.381039 best dqsien dly found for B1: ( 1, 2, 26)
5629 19:57:06.387716 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 19:57:06.391158 Total UI for P1: 0, mck2ui 16
5631 19:57:06.394365 best dqsien dly found for B0: ( 1, 2, 28)
5632 19:57:06.397906 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5633 19:57:06.400808 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5634 19:57:06.401221
5635 19:57:06.404208 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5636 19:57:06.407126 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5637 19:57:06.410744 [Gating] SW calibration Done
5638 19:57:06.411156 ==
5639 19:57:06.414396 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 19:57:06.417735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 19:57:06.418251 ==
5642 19:57:06.421217 RX Vref Scan: 0
5643 19:57:06.421726
5644 19:57:06.423862 RX Vref 0 -> 0, step: 1
5645 19:57:06.424274
5646 19:57:06.424774 RX Delay -80 -> 252, step: 8
5647 19:57:06.431014 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5648 19:57:06.433897 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5649 19:57:06.437592 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5650 19:57:06.441253 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5651 19:57:06.444151 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5652 19:57:06.450996 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5653 19:57:06.453903 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5654 19:57:06.457271 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5655 19:57:06.460554 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5656 19:57:06.464065 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5657 19:57:06.467075 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5658 19:57:06.473777 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5659 19:57:06.477067 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5660 19:57:06.480558 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5661 19:57:06.483600 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5662 19:57:06.486914 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5663 19:57:06.490009 ==
5664 19:57:06.490301 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 19:57:06.497135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 19:57:06.497320 ==
5667 19:57:06.497505 DQS Delay:
5668 19:57:06.499972 DQS0 = 0, DQS1 = 0
5669 19:57:06.500151 DQM Delay:
5670 19:57:06.503353 DQM0 = 94, DQM1 = 86
5671 19:57:06.503520 DQ Delay:
5672 19:57:06.506651 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5673 19:57:06.509843 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5674 19:57:06.513213 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5675 19:57:06.516564 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5676 19:57:06.516711
5677 19:57:06.516838
5678 19:57:06.516946 ==
5679 19:57:06.519796 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 19:57:06.523261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 19:57:06.523381 ==
5682 19:57:06.523466
5683 19:57:06.523533
5684 19:57:06.526744 TX Vref Scan disable
5685 19:57:06.529646 == TX Byte 0 ==
5686 19:57:06.533298 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5687 19:57:06.536768 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5688 19:57:06.539600 == TX Byte 1 ==
5689 19:57:06.543141 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5690 19:57:06.546402 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5691 19:57:06.546483 ==
5692 19:57:06.550122 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 19:57:06.552960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 19:57:06.556277 ==
5695 19:57:06.556358
5696 19:57:06.556421
5697 19:57:06.556480 TX Vref Scan disable
5698 19:57:06.559878 == TX Byte 0 ==
5699 19:57:06.563193 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5700 19:57:06.566467 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5701 19:57:06.569957 == TX Byte 1 ==
5702 19:57:06.573326 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5703 19:57:06.579734 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5704 19:57:06.579815
5705 19:57:06.579879 [DATLAT]
5706 19:57:06.579938 Freq=933, CH1 RK0
5707 19:57:06.579997
5708 19:57:06.583673 DATLAT Default: 0xd
5709 19:57:06.583753 0, 0xFFFF, sum = 0
5710 19:57:06.586858 1, 0xFFFF, sum = 0
5711 19:57:06.586932 2, 0xFFFF, sum = 0
5712 19:57:06.590339 3, 0xFFFF, sum = 0
5713 19:57:06.592997 4, 0xFFFF, sum = 0
5714 19:57:06.593078 5, 0xFFFF, sum = 0
5715 19:57:06.596461 6, 0xFFFF, sum = 0
5716 19:57:06.596543 7, 0xFFFF, sum = 0
5717 19:57:06.599862 8, 0xFFFF, sum = 0
5718 19:57:06.599945 9, 0xFFFF, sum = 0
5719 19:57:06.603679 10, 0x0, sum = 1
5720 19:57:06.603760 11, 0x0, sum = 2
5721 19:57:06.606508 12, 0x0, sum = 3
5722 19:57:06.606589 13, 0x0, sum = 4
5723 19:57:06.606654 best_step = 11
5724 19:57:06.606713
5725 19:57:06.609924 ==
5726 19:57:06.612902 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 19:57:06.616889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 19:57:06.616970 ==
5729 19:57:06.617033 RX Vref Scan: 1
5730 19:57:06.617092
5731 19:57:06.619692 RX Vref 0 -> 0, step: 1
5732 19:57:06.619772
5733 19:57:06.623055 RX Delay -69 -> 252, step: 4
5734 19:57:06.623134
5735 19:57:06.626231 Set Vref, RX VrefLevel [Byte0]: 54
5736 19:57:06.629493 [Byte1]: 53
5737 19:57:06.629574
5738 19:57:06.632725 Final RX Vref Byte 0 = 54 to rank0
5739 19:57:06.636494 Final RX Vref Byte 1 = 53 to rank0
5740 19:57:06.639545 Final RX Vref Byte 0 = 54 to rank1
5741 19:57:06.642763 Final RX Vref Byte 1 = 53 to rank1==
5742 19:57:06.646996 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 19:57:06.649343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 19:57:06.652764 ==
5745 19:57:06.652844 DQS Delay:
5746 19:57:06.652908 DQS0 = 0, DQS1 = 0
5747 19:57:06.656041 DQM Delay:
5748 19:57:06.656122 DQM0 = 95, DQM1 = 89
5749 19:57:06.659311 DQ Delay:
5750 19:57:06.662785 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =94
5751 19:57:06.666099 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =92
5752 19:57:06.669611 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =80
5753 19:57:06.672427 DQ12 =100, DQ13 =96, DQ14 =94, DQ15 =96
5754 19:57:06.672507
5755 19:57:06.672571
5756 19:57:06.679421 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5757 19:57:06.682720 CH1 RK0: MR19=405, MR18=FE07
5758 19:57:06.689528 CH1_RK0: MR19=0x405, MR18=0xFE07, DQSOSC=419, MR23=63, INC=61, DEC=41
5759 19:57:06.689611
5760 19:57:06.692439 ----->DramcWriteLeveling(PI) begin...
5761 19:57:06.692521 ==
5762 19:57:06.695808 Dram Type= 6, Freq= 0, CH_1, rank 1
5763 19:57:06.699693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 19:57:06.699775 ==
5765 19:57:06.702524 Write leveling (Byte 0): 26 => 26
5766 19:57:06.705798 Write leveling (Byte 1): 27 => 27
5767 19:57:06.708995 DramcWriteLeveling(PI) end<-----
5768 19:57:06.709076
5769 19:57:06.709139 ==
5770 19:57:06.712607 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 19:57:06.715950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 19:57:06.716032 ==
5773 19:57:06.719356 [Gating] SW mode calibration
5774 19:57:06.726106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5775 19:57:06.732228 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5776 19:57:06.736007 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 19:57:06.742529 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 19:57:06.745418 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 19:57:06.749184 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 19:57:06.755701 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 19:57:06.758691 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5782 19:57:06.762265 0 14 24 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 1)
5783 19:57:06.768598 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5784 19:57:06.772064 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5785 19:57:06.775331 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 19:57:06.778621 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 19:57:06.785276 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 19:57:06.788405 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 19:57:06.792363 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 19:57:06.798898 0 15 24 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
5791 19:57:06.801601 0 15 28 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5792 19:57:06.805320 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 19:57:06.811681 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 19:57:06.815244 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 19:57:06.818840 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 19:57:06.825023 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 19:57:06.828638 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 19:57:06.831814 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5799 19:57:06.838103 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5800 19:57:06.841538 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 19:57:06.844922 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 19:57:06.851521 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 19:57:06.854685 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 19:57:06.858720 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 19:57:06.864678 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 19:57:06.868385 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 19:57:06.871630 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 19:57:06.878186 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 19:57:06.881601 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 19:57:06.884612 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 19:57:06.891525 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 19:57:06.895188 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 19:57:06.897991 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 19:57:06.904581 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5815 19:57:06.908287 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5816 19:57:06.911154 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 19:57:06.914646 Total UI for P1: 0, mck2ui 16
5818 19:57:06.918310 best dqsien dly found for B0: ( 1, 2, 26)
5819 19:57:06.921488 Total UI for P1: 0, mck2ui 16
5820 19:57:06.925033 best dqsien dly found for B1: ( 1, 2, 26)
5821 19:57:06.927666 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5822 19:57:06.931369 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5823 19:57:06.931491
5824 19:57:06.934554 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5825 19:57:06.941206 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5826 19:57:06.941289 [Gating] SW calibration Done
5827 19:57:06.944446 ==
5828 19:57:06.944527 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 19:57:06.950790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 19:57:06.950871 ==
5831 19:57:06.950935 RX Vref Scan: 0
5832 19:57:06.950994
5833 19:57:06.954416 RX Vref 0 -> 0, step: 1
5834 19:57:06.954497
5835 19:57:06.957602 RX Delay -80 -> 252, step: 8
5836 19:57:06.960793 iDelay=200, Bit 0, Center 99 (0 ~ 199) 200
5837 19:57:06.964182 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5838 19:57:06.967613 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5839 19:57:06.974102 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5840 19:57:06.977602 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5841 19:57:06.980725 iDelay=200, Bit 5, Center 99 (0 ~ 199) 200
5842 19:57:06.984556 iDelay=200, Bit 6, Center 99 (0 ~ 199) 200
5843 19:57:06.987714 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5844 19:57:06.990703 iDelay=200, Bit 8, Center 75 (-24 ~ 175) 200
5845 19:57:06.997673 iDelay=200, Bit 9, Center 79 (-24 ~ 183) 208
5846 19:57:07.000936 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5847 19:57:07.004240 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5848 19:57:07.007602 iDelay=200, Bit 12, Center 95 (-8 ~ 199) 208
5849 19:57:07.010947 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5850 19:57:07.017311 iDelay=200, Bit 14, Center 91 (-8 ~ 191) 200
5851 19:57:07.020661 iDelay=200, Bit 15, Center 91 (-8 ~ 191) 200
5852 19:57:07.020743 ==
5853 19:57:07.024356 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 19:57:07.027621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 19:57:07.027703 ==
5856 19:57:07.027790 DQS Delay:
5857 19:57:07.030738 DQS0 = 0, DQS1 = 0
5858 19:57:07.030819 DQM Delay:
5859 19:57:07.034109 DQM0 = 93, DQM1 = 88
5860 19:57:07.034190 DQ Delay:
5861 19:57:07.038017 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5862 19:57:07.040704 DQ4 =91, DQ5 =99, DQ6 =99, DQ7 =91
5863 19:57:07.043981 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =87
5864 19:57:07.047114 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =91
5865 19:57:07.047222
5866 19:57:07.047313
5867 19:57:07.047424 ==
5868 19:57:07.051008 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 19:57:07.053643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 19:57:07.057206 ==
5871 19:57:07.057288
5872 19:57:07.057352
5873 19:57:07.057411 TX Vref Scan disable
5874 19:57:07.060493 == TX Byte 0 ==
5875 19:57:07.063620 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5876 19:57:07.067050 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5877 19:57:07.070290 == TX Byte 1 ==
5878 19:57:07.073568 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5879 19:57:07.077064 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5880 19:57:07.080359 ==
5881 19:57:07.080440 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 19:57:07.086914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 19:57:07.086997 ==
5884 19:57:07.087061
5885 19:57:07.087120
5886 19:57:07.090069 TX Vref Scan disable
5887 19:57:07.090150 == TX Byte 0 ==
5888 19:57:07.096666 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5889 19:57:07.100512 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5890 19:57:07.100602 == TX Byte 1 ==
5891 19:57:07.107007 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5892 19:57:07.109845 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5893 19:57:07.109928
5894 19:57:07.109991 [DATLAT]
5895 19:57:07.113834 Freq=933, CH1 RK1
5896 19:57:07.113917
5897 19:57:07.113981 DATLAT Default: 0xb
5898 19:57:07.116938 0, 0xFFFF, sum = 0
5899 19:57:07.117021 1, 0xFFFF, sum = 0
5900 19:57:07.120359 2, 0xFFFF, sum = 0
5901 19:57:07.120449 3, 0xFFFF, sum = 0
5902 19:57:07.123027 4, 0xFFFF, sum = 0
5903 19:57:07.123109 5, 0xFFFF, sum = 0
5904 19:57:07.126433 6, 0xFFFF, sum = 0
5905 19:57:07.129909 7, 0xFFFF, sum = 0
5906 19:57:07.129993 8, 0xFFFF, sum = 0
5907 19:57:07.133152 9, 0xFFFF, sum = 0
5908 19:57:07.133235 10, 0x0, sum = 1
5909 19:57:07.133301 11, 0x0, sum = 2
5910 19:57:07.136502 12, 0x0, sum = 3
5911 19:57:07.136584 13, 0x0, sum = 4
5912 19:57:07.139872 best_step = 11
5913 19:57:07.139953
5914 19:57:07.140018 ==
5915 19:57:07.143088 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 19:57:07.146800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 19:57:07.146882 ==
5918 19:57:07.150060 RX Vref Scan: 0
5919 19:57:07.150140
5920 19:57:07.150204 RX Vref 0 -> 0, step: 1
5921 19:57:07.152767
5922 19:57:07.152848 RX Delay -69 -> 252, step: 4
5923 19:57:07.160702 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5924 19:57:07.163859 iDelay=203, Bit 1, Center 88 (-9 ~ 186) 196
5925 19:57:07.167962 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5926 19:57:07.170466 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5927 19:57:07.173844 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5928 19:57:07.181084 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5929 19:57:07.184223 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5930 19:57:07.187269 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5931 19:57:07.190656 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5932 19:57:07.194086 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5933 19:57:07.197081 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5934 19:57:07.203941 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5935 19:57:07.207119 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5936 19:57:07.210476 iDelay=203, Bit 13, Center 98 (3 ~ 194) 192
5937 19:57:07.213624 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5938 19:57:07.217418 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5939 19:57:07.217502 ==
5940 19:57:07.220398 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 19:57:07.226803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 19:57:07.226887 ==
5943 19:57:07.226972 DQS Delay:
5944 19:57:07.230035 DQS0 = 0, DQS1 = 0
5945 19:57:07.230138 DQM Delay:
5946 19:57:07.230223 DQM0 = 91, DQM1 = 90
5947 19:57:07.233403 DQ Delay:
5948 19:57:07.236741 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
5949 19:57:07.239984 DQ4 =90, DQ5 =100, DQ6 =104, DQ7 =88
5950 19:57:07.243581 DQ8 =76, DQ9 =80, DQ10 =90, DQ11 =84
5951 19:57:07.246816 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
5952 19:57:07.246899
5953 19:57:07.246983
5954 19:57:07.253594 [DQSOSCAuto] RK1, (LSB)MR18= 0x1225, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5955 19:57:07.256741 CH1 RK1: MR19=505, MR18=1225
5956 19:57:07.263178 CH1_RK1: MR19=0x505, MR18=0x1225, DQSOSC=410, MR23=63, INC=64, DEC=42
5957 19:57:07.266482 [RxdqsGatingPostProcess] freq 933
5958 19:57:07.273060 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5959 19:57:07.273145 best DQS0 dly(2T, 0.5T) = (0, 10)
5960 19:57:07.276493 best DQS1 dly(2T, 0.5T) = (0, 10)
5961 19:57:07.280091 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5962 19:57:07.283085 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5963 19:57:07.286510 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 19:57:07.289729 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 19:57:07.292790 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 19:57:07.296555 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 19:57:07.299489 Pre-setting of DQS Precalculation
5968 19:57:07.306141 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5969 19:57:07.312864 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5970 19:57:07.319522 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5971 19:57:07.319608
5972 19:57:07.319693
5973 19:57:07.322849 [Calibration Summary] 1866 Mbps
5974 19:57:07.322932 CH 0, Rank 0
5975 19:57:07.326178 SW Impedance : PASS
5976 19:57:07.329367 DUTY Scan : NO K
5977 19:57:07.329451 ZQ Calibration : PASS
5978 19:57:07.332650 Jitter Meter : NO K
5979 19:57:07.332734 CBT Training : PASS
5980 19:57:07.336231 Write leveling : PASS
5981 19:57:07.339371 RX DQS gating : PASS
5982 19:57:07.339492 RX DQ/DQS(RDDQC) : PASS
5983 19:57:07.342695 TX DQ/DQS : PASS
5984 19:57:07.346287 RX DATLAT : PASS
5985 19:57:07.346371 RX DQ/DQS(Engine): PASS
5986 19:57:07.349214 TX OE : NO K
5987 19:57:07.349297 All Pass.
5988 19:57:07.349382
5989 19:57:07.352528 CH 0, Rank 1
5990 19:57:07.352610 SW Impedance : PASS
5991 19:57:07.356304 DUTY Scan : NO K
5992 19:57:07.359741 ZQ Calibration : PASS
5993 19:57:07.359824 Jitter Meter : NO K
5994 19:57:07.362322 CBT Training : PASS
5995 19:57:07.365688 Write leveling : PASS
5996 19:57:07.365771 RX DQS gating : PASS
5997 19:57:07.369652 RX DQ/DQS(RDDQC) : PASS
5998 19:57:07.372457 TX DQ/DQS : PASS
5999 19:57:07.372538 RX DATLAT : PASS
6000 19:57:07.375974 RX DQ/DQS(Engine): PASS
6001 19:57:07.379429 TX OE : NO K
6002 19:57:07.379511 All Pass.
6003 19:57:07.379575
6004 19:57:07.379635 CH 1, Rank 0
6005 19:57:07.382684 SW Impedance : PASS
6006 19:57:07.385614 DUTY Scan : NO K
6007 19:57:07.385695 ZQ Calibration : PASS
6008 19:57:07.389322 Jitter Meter : NO K
6009 19:57:07.389404 CBT Training : PASS
6010 19:57:07.392328 Write leveling : PASS
6011 19:57:07.395551 RX DQS gating : PASS
6012 19:57:07.395632 RX DQ/DQS(RDDQC) : PASS
6013 19:57:07.398971 TX DQ/DQS : PASS
6014 19:57:07.402503 RX DATLAT : PASS
6015 19:57:07.402576 RX DQ/DQS(Engine): PASS
6016 19:57:07.405544 TX OE : NO K
6017 19:57:07.405626 All Pass.
6018 19:57:07.405690
6019 19:57:07.409005 CH 1, Rank 1
6020 19:57:07.409086 SW Impedance : PASS
6021 19:57:07.412519 DUTY Scan : NO K
6022 19:57:07.415438 ZQ Calibration : PASS
6023 19:57:07.415519 Jitter Meter : NO K
6024 19:57:07.418701 CBT Training : PASS
6025 19:57:07.422422 Write leveling : PASS
6026 19:57:07.422503 RX DQS gating : PASS
6027 19:57:07.425867 RX DQ/DQS(RDDQC) : PASS
6028 19:57:07.428786 TX DQ/DQS : PASS
6029 19:57:07.428868 RX DATLAT : PASS
6030 19:57:07.432096 RX DQ/DQS(Engine): PASS
6031 19:57:07.435232 TX OE : NO K
6032 19:57:07.435315 All Pass.
6033 19:57:07.435451
6034 19:57:07.435533 DramC Write-DBI off
6035 19:57:07.438531 PER_BANK_REFRESH: Hybrid Mode
6036 19:57:07.442198 TX_TRACKING: ON
6037 19:57:07.448753 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6038 19:57:07.452569 [FAST_K] Save calibration result to emmc
6039 19:57:07.458969 dramc_set_vcore_voltage set vcore to 650000
6040 19:57:07.459057 Read voltage for 400, 6
6041 19:57:07.461782 Vio18 = 0
6042 19:57:07.461864 Vcore = 650000
6043 19:57:07.461927 Vdram = 0
6044 19:57:07.461986 Vddq = 0
6045 19:57:07.466025 Vmddr = 0
6046 19:57:07.468647 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6047 19:57:07.475714 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6048 19:57:07.478368 MEM_TYPE=3, freq_sel=20
6049 19:57:07.478448 sv_algorithm_assistance_LP4_800
6050 19:57:07.485563 ============ PULL DRAM RESETB DOWN ============
6051 19:57:07.488497 ========== PULL DRAM RESETB DOWN end =========
6052 19:57:07.491819 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6053 19:57:07.495228 ===================================
6054 19:57:07.498500 LPDDR4 DRAM CONFIGURATION
6055 19:57:07.501660 ===================================
6056 19:57:07.504969 EX_ROW_EN[0] = 0x0
6057 19:57:07.505051 EX_ROW_EN[1] = 0x0
6058 19:57:07.508485 LP4Y_EN = 0x0
6059 19:57:07.508565 WORK_FSP = 0x0
6060 19:57:07.511633 WL = 0x2
6061 19:57:07.511713 RL = 0x2
6062 19:57:07.514709 BL = 0x2
6063 19:57:07.514789 RPST = 0x0
6064 19:57:07.518165 RD_PRE = 0x0
6065 19:57:07.518245 WR_PRE = 0x1
6066 19:57:07.521795 WR_PST = 0x0
6067 19:57:07.521876 DBI_WR = 0x0
6068 19:57:07.524969 DBI_RD = 0x0
6069 19:57:07.525050 OTF = 0x1
6070 19:57:07.528197 ===================================
6071 19:57:07.531945 ===================================
6072 19:57:07.534904 ANA top config
6073 19:57:07.538649 ===================================
6074 19:57:07.541467 DLL_ASYNC_EN = 0
6075 19:57:07.541548 ALL_SLAVE_EN = 1
6076 19:57:07.544805 NEW_RANK_MODE = 1
6077 19:57:07.548386 DLL_IDLE_MODE = 1
6078 19:57:07.551403 LP45_APHY_COMB_EN = 1
6079 19:57:07.554829 TX_ODT_DIS = 1
6080 19:57:07.554911 NEW_8X_MODE = 1
6081 19:57:07.558171 ===================================
6082 19:57:07.561662 ===================================
6083 19:57:07.564886 data_rate = 800
6084 19:57:07.568123 CKR = 1
6085 19:57:07.571567 DQ_P2S_RATIO = 4
6086 19:57:07.575538 ===================================
6087 19:57:07.578742 CA_P2S_RATIO = 4
6088 19:57:07.578824 DQ_CA_OPEN = 0
6089 19:57:07.582544 DQ_SEMI_OPEN = 1
6090 19:57:07.585449 CA_SEMI_OPEN = 1
6091 19:57:07.588548 CA_FULL_RATE = 0
6092 19:57:07.591861 DQ_CKDIV4_EN = 0
6093 19:57:07.594928 CA_CKDIV4_EN = 1
6094 19:57:07.595008 CA_PREDIV_EN = 0
6095 19:57:07.597821 PH8_DLY = 0
6096 19:57:07.601605 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6097 19:57:07.605050 DQ_AAMCK_DIV = 0
6098 19:57:07.607880 CA_AAMCK_DIV = 0
6099 19:57:07.611684 CA_ADMCK_DIV = 4
6100 19:57:07.611764 DQ_TRACK_CA_EN = 0
6101 19:57:07.614946 CA_PICK = 800
6102 19:57:07.618284 CA_MCKIO = 400
6103 19:57:07.621585 MCKIO_SEMI = 400
6104 19:57:07.624462 PLL_FREQ = 3016
6105 19:57:07.628052 DQ_UI_PI_RATIO = 32
6106 19:57:07.631155 CA_UI_PI_RATIO = 32
6107 19:57:07.634819 ===================================
6108 19:57:07.637711 ===================================
6109 19:57:07.637792 memory_type:LPDDR4
6110 19:57:07.641369 GP_NUM : 10
6111 19:57:07.644596 SRAM_EN : 1
6112 19:57:07.644678 MD32_EN : 0
6113 19:57:07.648346 ===================================
6114 19:57:07.651151 [ANA_INIT] >>>>>>>>>>>>>>
6115 19:57:07.654515 <<<<<< [CONFIGURE PHASE]: ANA_TX
6116 19:57:07.657942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6117 19:57:07.661361 ===================================
6118 19:57:07.664730 data_rate = 800,PCW = 0X7400
6119 19:57:07.668116 ===================================
6120 19:57:07.670931 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6121 19:57:07.674628 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6122 19:57:07.687620 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6123 19:57:07.691098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6124 19:57:07.694438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6125 19:57:07.697945 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6126 19:57:07.700827 [ANA_INIT] flow start
6127 19:57:07.704395 [ANA_INIT] PLL >>>>>>>>
6128 19:57:07.704480 [ANA_INIT] PLL <<<<<<<<
6129 19:57:07.708283 [ANA_INIT] MIDPI >>>>>>>>
6130 19:57:07.711374 [ANA_INIT] MIDPI <<<<<<<<
6131 19:57:07.711479 [ANA_INIT] DLL >>>>>>>>
6132 19:57:07.714414 [ANA_INIT] flow end
6133 19:57:07.717582 ============ LP4 DIFF to SE enter ============
6134 19:57:07.720893 ============ LP4 DIFF to SE exit ============
6135 19:57:07.724654 [ANA_INIT] <<<<<<<<<<<<<
6136 19:57:07.727643 [Flow] Enable top DCM control >>>>>
6137 19:57:07.731137 [Flow] Enable top DCM control <<<<<
6138 19:57:07.734393 Enable DLL master slave shuffle
6139 19:57:07.741106 ==============================================================
6140 19:57:07.741190 Gating Mode config
6141 19:57:07.747599 ==============================================================
6142 19:57:07.747682 Config description:
6143 19:57:07.757474 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6144 19:57:07.763997 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6145 19:57:07.770663 SELPH_MODE 0: By rank 1: By Phase
6146 19:57:07.773993 ==============================================================
6147 19:57:07.777817 GAT_TRACK_EN = 0
6148 19:57:07.780837 RX_GATING_MODE = 2
6149 19:57:07.784147 RX_GATING_TRACK_MODE = 2
6150 19:57:07.787622 SELPH_MODE = 1
6151 19:57:07.790864 PICG_EARLY_EN = 1
6152 19:57:07.794329 VALID_LAT_VALUE = 1
6153 19:57:07.800476 ==============================================================
6154 19:57:07.803823 Enter into Gating configuration >>>>
6155 19:57:07.807157 Exit from Gating configuration <<<<
6156 19:57:07.807239 Enter into DVFS_PRE_config >>>>>
6157 19:57:07.820524 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6158 19:57:07.823831 Exit from DVFS_PRE_config <<<<<
6159 19:57:07.826840 Enter into PICG configuration >>>>
6160 19:57:07.830201 Exit from PICG configuration <<<<
6161 19:57:07.833608 [RX_INPUT] configuration >>>>>
6162 19:57:07.833691 [RX_INPUT] configuration <<<<<
6163 19:57:07.840685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6164 19:57:07.846705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6165 19:57:07.850553 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6166 19:57:07.856661 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6167 19:57:07.863686 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6168 19:57:07.870232 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6169 19:57:07.873424 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6170 19:57:07.876710 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6171 19:57:07.883319 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6172 19:57:07.886574 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6173 19:57:07.890001 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6174 19:57:07.896295 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6175 19:57:07.900376 ===================================
6176 19:57:07.900458 LPDDR4 DRAM CONFIGURATION
6177 19:57:07.903241 ===================================
6178 19:57:07.906510 EX_ROW_EN[0] = 0x0
6179 19:57:07.906592 EX_ROW_EN[1] = 0x0
6180 19:57:07.909851 LP4Y_EN = 0x0
6181 19:57:07.909932 WORK_FSP = 0x0
6182 19:57:07.913025 WL = 0x2
6183 19:57:07.916367 RL = 0x2
6184 19:57:07.916449 BL = 0x2
6185 19:57:07.919851 RPST = 0x0
6186 19:57:07.919933 RD_PRE = 0x0
6187 19:57:07.923335 WR_PRE = 0x1
6188 19:57:07.923461 WR_PST = 0x0
6189 19:57:07.926228 DBI_WR = 0x0
6190 19:57:07.926317 DBI_RD = 0x0
6191 19:57:07.929558 OTF = 0x1
6192 19:57:07.932773 ===================================
6193 19:57:07.936619 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6194 19:57:07.939841 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6195 19:57:07.943062 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6196 19:57:07.946407 ===================================
6197 19:57:07.949293 LPDDR4 DRAM CONFIGURATION
6198 19:57:07.952757 ===================================
6199 19:57:07.955902 EX_ROW_EN[0] = 0x10
6200 19:57:07.955983 EX_ROW_EN[1] = 0x0
6201 19:57:07.959312 LP4Y_EN = 0x0
6202 19:57:07.959458 WORK_FSP = 0x0
6203 19:57:07.962510 WL = 0x2
6204 19:57:07.962590 RL = 0x2
6205 19:57:07.966135 BL = 0x2
6206 19:57:07.969703 RPST = 0x0
6207 19:57:07.969783 RD_PRE = 0x0
6208 19:57:07.972835 WR_PRE = 0x1
6209 19:57:07.972916 WR_PST = 0x0
6210 19:57:07.976045 DBI_WR = 0x0
6211 19:57:07.976126 DBI_RD = 0x0
6212 19:57:07.979132 OTF = 0x1
6213 19:57:07.983323 ===================================
6214 19:57:07.985950 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6215 19:57:07.991169 nWR fixed to 30
6216 19:57:07.994636 [ModeRegInit_LP4] CH0 RK0
6217 19:57:07.994718 [ModeRegInit_LP4] CH0 RK1
6218 19:57:07.998080 [ModeRegInit_LP4] CH1 RK0
6219 19:57:08.001270 [ModeRegInit_LP4] CH1 RK1
6220 19:57:08.001350 match AC timing 19
6221 19:57:08.007956 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6222 19:57:08.011175 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6223 19:57:08.014512 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6224 19:57:08.021580 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6225 19:57:08.024836 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6226 19:57:08.024918 ==
6227 19:57:08.028178 Dram Type= 6, Freq= 0, CH_0, rank 0
6228 19:57:08.031569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6229 19:57:08.031651 ==
6230 19:57:08.037839 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6231 19:57:08.044740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6232 19:57:08.047758 [CA 0] Center 36 (8~64) winsize 57
6233 19:57:08.051507 [CA 1] Center 36 (8~64) winsize 57
6234 19:57:08.054942 [CA 2] Center 36 (8~64) winsize 57
6235 19:57:08.055024 [CA 3] Center 36 (8~64) winsize 57
6236 19:57:08.058314 [CA 4] Center 36 (8~64) winsize 57
6237 19:57:08.061454 [CA 5] Center 36 (8~64) winsize 57
6238 19:57:08.061535
6239 19:57:08.067653 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6240 19:57:08.067737
6241 19:57:08.071330 [CATrainingPosCal] consider 1 rank data
6242 19:57:08.074274 u2DelayCellTimex100 = 270/100 ps
6243 19:57:08.078012 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 19:57:08.081443 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 19:57:08.084605 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 19:57:08.087821 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 19:57:08.091289 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 19:57:08.094957 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 19:57:08.095038
6250 19:57:08.097991 CA PerBit enable=1, Macro0, CA PI delay=36
6251 19:57:08.098072
6252 19:57:08.101448 [CBTSetCACLKResult] CA Dly = 36
6253 19:57:08.105032 CS Dly: 1 (0~32)
6254 19:57:08.105112 ==
6255 19:57:08.107840 Dram Type= 6, Freq= 0, CH_0, rank 1
6256 19:57:08.111064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 19:57:08.111145 ==
6258 19:57:08.117789 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 19:57:08.121627 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6260 19:57:08.124785 [CA 0] Center 36 (8~64) winsize 57
6261 19:57:08.127844 [CA 1] Center 36 (8~64) winsize 57
6262 19:57:08.131028 [CA 2] Center 36 (8~64) winsize 57
6263 19:57:08.134282 [CA 3] Center 36 (8~64) winsize 57
6264 19:57:08.137794 [CA 4] Center 36 (8~64) winsize 57
6265 19:57:08.141313 [CA 5] Center 36 (8~64) winsize 57
6266 19:57:08.141395
6267 19:57:08.144671 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6268 19:57:08.144752
6269 19:57:08.147872 [CATrainingPosCal] consider 2 rank data
6270 19:57:08.151120 u2DelayCellTimex100 = 270/100 ps
6271 19:57:08.154306 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 19:57:08.157849 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 19:57:08.161266 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 19:57:08.167579 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 19:57:08.170892 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 19:57:08.174074 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 19:57:08.174155
6278 19:57:08.177716 CA PerBit enable=1, Macro0, CA PI delay=36
6279 19:57:08.177800
6280 19:57:08.180779 [CBTSetCACLKResult] CA Dly = 36
6281 19:57:08.180861 CS Dly: 1 (0~32)
6282 19:57:08.180925
6283 19:57:08.184246 ----->DramcWriteLeveling(PI) begin...
6284 19:57:08.184328 ==
6285 19:57:08.187601 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 19:57:08.194504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 19:57:08.194592 ==
6288 19:57:08.197069 Write leveling (Byte 0): 40 => 8
6289 19:57:08.200804 Write leveling (Byte 1): 32 => 0
6290 19:57:08.200886 DramcWriteLeveling(PI) end<-----
6291 19:57:08.200951
6292 19:57:08.204057 ==
6293 19:57:08.207292 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 19:57:08.210515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 19:57:08.210597 ==
6296 19:57:08.213832 [Gating] SW mode calibration
6297 19:57:08.220413 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6298 19:57:08.223791 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6299 19:57:08.230138 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6300 19:57:08.234031 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6301 19:57:08.236993 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 19:57:08.244029 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 19:57:08.247226 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 19:57:08.250659 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 19:57:08.256898 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 19:57:08.260594 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 19:57:08.263588 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 19:57:08.267348 Total UI for P1: 0, mck2ui 16
6309 19:57:08.270683 best dqsien dly found for B0: ( 0, 14, 24)
6310 19:57:08.273499 Total UI for P1: 0, mck2ui 16
6311 19:57:08.277447 best dqsien dly found for B1: ( 0, 14, 24)
6312 19:57:08.280076 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6313 19:57:08.283638 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6314 19:57:08.283718
6315 19:57:08.290412 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6316 19:57:08.293901 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6317 19:57:08.297141 [Gating] SW calibration Done
6318 19:57:08.297223 ==
6319 19:57:08.300526 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 19:57:08.303316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 19:57:08.303425 ==
6322 19:57:08.303491 RX Vref Scan: 0
6323 19:57:08.303550
6324 19:57:08.306941 RX Vref 0 -> 0, step: 1
6325 19:57:08.307020
6326 19:57:08.309916 RX Delay -410 -> 252, step: 16
6327 19:57:08.313149 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6328 19:57:08.320025 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6329 19:57:08.323225 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6330 19:57:08.326799 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6331 19:57:08.330205 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6332 19:57:08.336328 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6333 19:57:08.339809 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6334 19:57:08.343356 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6335 19:57:08.347737 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6336 19:57:08.353363 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6337 19:57:08.356282 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6338 19:57:08.359699 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6339 19:57:08.362879 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6340 19:57:08.369649 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6341 19:57:08.373090 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6342 19:57:08.376396 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6343 19:57:08.376476 ==
6344 19:57:08.379656 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 19:57:08.386219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 19:57:08.386301 ==
6347 19:57:08.386365 DQS Delay:
6348 19:57:08.389967 DQS0 = 59, DQS1 = 59
6349 19:57:08.390047 DQM Delay:
6350 19:57:08.390110 DQM0 = 18, DQM1 = 11
6351 19:57:08.393201 DQ Delay:
6352 19:57:08.396008 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6353 19:57:08.399320 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6354 19:57:08.399429 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6355 19:57:08.402799 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6356 19:57:08.406241
6357 19:57:08.406321
6358 19:57:08.406384 ==
6359 19:57:08.409274 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 19:57:08.412958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 19:57:08.413043 ==
6362 19:57:08.413107
6363 19:57:08.413165
6364 19:57:08.416037 TX Vref Scan disable
6365 19:57:08.416116 == TX Byte 0 ==
6366 19:57:08.419629 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 19:57:08.426028 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 19:57:08.426109 == TX Byte 1 ==
6369 19:57:08.429271 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6370 19:57:08.435700 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6371 19:57:08.435787 ==
6372 19:57:08.439115 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 19:57:08.442733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 19:57:08.442815 ==
6375 19:57:08.442879
6376 19:57:08.442938
6377 19:57:08.445817 TX Vref Scan disable
6378 19:57:08.445897 == TX Byte 0 ==
6379 19:57:08.452598 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6380 19:57:08.455697 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6381 19:57:08.455779 == TX Byte 1 ==
6382 19:57:08.462270 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6383 19:57:08.465732 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6384 19:57:08.465814
6385 19:57:08.465878 [DATLAT]
6386 19:57:08.469228 Freq=400, CH0 RK0
6387 19:57:08.469308
6388 19:57:08.469371 DATLAT Default: 0xf
6389 19:57:08.472158 0, 0xFFFF, sum = 0
6390 19:57:08.472238 1, 0xFFFF, sum = 0
6391 19:57:08.475514 2, 0xFFFF, sum = 0
6392 19:57:08.475594 3, 0xFFFF, sum = 0
6393 19:57:08.478819 4, 0xFFFF, sum = 0
6394 19:57:08.478899 5, 0xFFFF, sum = 0
6395 19:57:08.482217 6, 0xFFFF, sum = 0
6396 19:57:08.482298 7, 0xFFFF, sum = 0
6397 19:57:08.485664 8, 0xFFFF, sum = 0
6398 19:57:08.485746 9, 0xFFFF, sum = 0
6399 19:57:08.488900 10, 0xFFFF, sum = 0
6400 19:57:08.492226 11, 0xFFFF, sum = 0
6401 19:57:08.492311 12, 0xFFFF, sum = 0
6402 19:57:08.495153 13, 0x0, sum = 1
6403 19:57:08.495234 14, 0x0, sum = 2
6404 19:57:08.498713 15, 0x0, sum = 3
6405 19:57:08.498794 16, 0x0, sum = 4
6406 19:57:08.498858 best_step = 14
6407 19:57:08.498916
6408 19:57:08.502099 ==
6409 19:57:08.505580 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 19:57:08.508869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 19:57:08.508951 ==
6412 19:57:08.509014 RX Vref Scan: 1
6413 19:57:08.509074
6414 19:57:08.512206 RX Vref 0 -> 0, step: 1
6415 19:57:08.512286
6416 19:57:08.515236 RX Delay -359 -> 252, step: 8
6417 19:57:08.515315
6418 19:57:08.518600 Set Vref, RX VrefLevel [Byte0]: 62
6419 19:57:08.521862 [Byte1]: 57
6420 19:57:08.525550
6421 19:57:08.525630 Final RX Vref Byte 0 = 62 to rank0
6422 19:57:08.528842 Final RX Vref Byte 1 = 57 to rank0
6423 19:57:08.532617 Final RX Vref Byte 0 = 62 to rank1
6424 19:57:08.535331 Final RX Vref Byte 1 = 57 to rank1==
6425 19:57:08.539129 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 19:57:08.545733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 19:57:08.545824 ==
6428 19:57:08.545910 DQS Delay:
6429 19:57:08.548727 DQS0 = 60, DQS1 = 68
6430 19:57:08.548810 DQM Delay:
6431 19:57:08.548895 DQM0 = 16, DQM1 = 13
6432 19:57:08.552004 DQ Delay:
6433 19:57:08.555642 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6434 19:57:08.558924 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6435 19:57:08.559008 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6436 19:57:08.562482 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6437 19:57:08.565759
6438 19:57:08.565842
6439 19:57:08.572353 [DQSOSCAuto] RK0, (LSB)MR18= 0x8787, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6440 19:57:08.575892 CH0 RK0: MR19=C0C, MR18=8787
6441 19:57:08.581994 CH0_RK0: MR19=0xC0C, MR18=0x8787, DQSOSC=392, MR23=63, INC=384, DEC=256
6442 19:57:08.582078 ==
6443 19:57:08.585891 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 19:57:08.588671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 19:57:08.588760 ==
6446 19:57:08.592262 [Gating] SW mode calibration
6447 19:57:08.598677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6448 19:57:08.605083 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6449 19:57:08.608972 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6450 19:57:08.611719 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6451 19:57:08.618440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 19:57:08.622065 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 19:57:08.625265 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 19:57:08.632205 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 19:57:08.635345 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 19:57:08.638905 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 19:57:08.644973 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 19:57:08.645058 Total UI for P1: 0, mck2ui 16
6459 19:57:08.648526 best dqsien dly found for B0: ( 0, 14, 24)
6460 19:57:08.651424 Total UI for P1: 0, mck2ui 16
6461 19:57:08.655212 best dqsien dly found for B1: ( 0, 14, 24)
6462 19:57:08.661924 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6463 19:57:08.664777 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6464 19:57:08.664861
6465 19:57:08.668305 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6466 19:57:08.671781 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6467 19:57:08.674971 [Gating] SW calibration Done
6468 19:57:08.675054 ==
6469 19:57:08.678526 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 19:57:08.681459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 19:57:08.681543 ==
6472 19:57:08.685402 RX Vref Scan: 0
6473 19:57:08.685484
6474 19:57:08.685569 RX Vref 0 -> 0, step: 1
6475 19:57:08.685649
6476 19:57:08.688270 RX Delay -410 -> 252, step: 16
6477 19:57:08.694661 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6478 19:57:08.697945 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6479 19:57:08.701271 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6480 19:57:08.704645 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6481 19:57:08.711340 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6482 19:57:08.715158 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6483 19:57:08.718474 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6484 19:57:08.721627 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6485 19:57:08.725004 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6486 19:57:08.731014 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6487 19:57:08.734522 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6488 19:57:08.737600 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6489 19:57:08.744111 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6490 19:57:08.747791 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6491 19:57:08.751027 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6492 19:57:08.754106 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6493 19:57:08.757774 ==
6494 19:57:08.760733 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 19:57:08.764252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 19:57:08.764336 ==
6497 19:57:08.764420 DQS Delay:
6498 19:57:08.767382 DQS0 = 59, DQS1 = 59
6499 19:57:08.767501 DQM Delay:
6500 19:57:08.770855 DQM0 = 17, DQM1 = 10
6501 19:57:08.770955 DQ Delay:
6502 19:57:08.773812 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6503 19:57:08.777258 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6504 19:57:08.780586 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6505 19:57:08.783851 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6506 19:57:08.783933
6507 19:57:08.783997
6508 19:57:08.784057 ==
6509 19:57:08.787008 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 19:57:08.790554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 19:57:08.790637 ==
6512 19:57:08.790702
6513 19:57:08.790761
6514 19:57:08.793701 TX Vref Scan disable
6515 19:57:08.793783 == TX Byte 0 ==
6516 19:57:08.800523 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6517 19:57:08.803874 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6518 19:57:08.803956 == TX Byte 1 ==
6519 19:57:08.810439 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6520 19:57:08.813605 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6521 19:57:08.813687 ==
6522 19:57:08.817357 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 19:57:08.820465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 19:57:08.820547 ==
6525 19:57:08.820612
6526 19:57:08.820671
6527 19:57:08.823855 TX Vref Scan disable
6528 19:57:08.826771 == TX Byte 0 ==
6529 19:57:08.830378 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6530 19:57:08.833440 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6531 19:57:08.833522 == TX Byte 1 ==
6532 19:57:08.840104 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6533 19:57:08.843601 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6534 19:57:08.843683
6535 19:57:08.843747 [DATLAT]
6536 19:57:08.846887 Freq=400, CH0 RK1
6537 19:57:08.846968
6538 19:57:08.847033 DATLAT Default: 0xe
6539 19:57:08.850081 0, 0xFFFF, sum = 0
6540 19:57:08.850164 1, 0xFFFF, sum = 0
6541 19:57:08.853344 2, 0xFFFF, sum = 0
6542 19:57:08.853427 3, 0xFFFF, sum = 0
6543 19:57:08.856862 4, 0xFFFF, sum = 0
6544 19:57:08.860143 5, 0xFFFF, sum = 0
6545 19:57:08.860227 6, 0xFFFF, sum = 0
6546 19:57:08.863335 7, 0xFFFF, sum = 0
6547 19:57:08.863458 8, 0xFFFF, sum = 0
6548 19:57:08.866467 9, 0xFFFF, sum = 0
6549 19:57:08.866549 10, 0xFFFF, sum = 0
6550 19:57:08.869681 11, 0xFFFF, sum = 0
6551 19:57:08.869763 12, 0xFFFF, sum = 0
6552 19:57:08.873457 13, 0x0, sum = 1
6553 19:57:08.873540 14, 0x0, sum = 2
6554 19:57:08.876461 15, 0x0, sum = 3
6555 19:57:08.876544 16, 0x0, sum = 4
6556 19:57:08.879949 best_step = 14
6557 19:57:08.880030
6558 19:57:08.880095 ==
6559 19:57:08.883226 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 19:57:08.886706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 19:57:08.886789 ==
6562 19:57:08.886855 RX Vref Scan: 0
6563 19:57:08.889841
6564 19:57:08.889921 RX Vref 0 -> 0, step: 1
6565 19:57:08.889986
6566 19:57:08.893124 RX Delay -359 -> 252, step: 8
6567 19:57:08.900591 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6568 19:57:08.903701 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6569 19:57:08.907244 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6570 19:57:08.913974 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6571 19:57:08.916899 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6572 19:57:08.920079 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6573 19:57:08.923583 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6574 19:57:08.930215 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6575 19:57:08.933337 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6576 19:57:08.936818 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6577 19:57:08.940190 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6578 19:57:08.946893 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6579 19:57:08.950515 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6580 19:57:08.953623 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6581 19:57:08.956929 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6582 19:57:08.963285 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6583 19:57:08.963390 ==
6584 19:57:08.966628 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 19:57:08.970076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 19:57:08.970159 ==
6587 19:57:08.970224 DQS Delay:
6588 19:57:08.973686 DQS0 = 60, DQS1 = 68
6589 19:57:08.973768 DQM Delay:
6590 19:57:08.976541 DQM0 = 11, DQM1 = 14
6591 19:57:08.976622 DQ Delay:
6592 19:57:08.979859 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6593 19:57:08.983059 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6594 19:57:08.986483 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6595 19:57:08.989775 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6596 19:57:08.989858
6597 19:57:08.989923
6598 19:57:08.996625 [DQSOSCAuto] RK1, (LSB)MR18= 0xcc81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6599 19:57:08.999964 CH0 RK1: MR19=C0C, MR18=CC81
6600 19:57:09.006606 CH0_RK1: MR19=0xC0C, MR18=0xCC81, DQSOSC=384, MR23=63, INC=400, DEC=267
6601 19:57:09.009795 [RxdqsGatingPostProcess] freq 400
6602 19:57:09.016535 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6603 19:57:09.019940 best DQS0 dly(2T, 0.5T) = (0, 10)
6604 19:57:09.020022 best DQS1 dly(2T, 0.5T) = (0, 10)
6605 19:57:09.022984 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6606 19:57:09.026616 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6607 19:57:09.029616 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 19:57:09.033325 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 19:57:09.036554 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 19:57:09.039795 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 19:57:09.043013 Pre-setting of DQS Precalculation
6612 19:57:09.049689 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6613 19:57:09.049772 ==
6614 19:57:09.052643 Dram Type= 6, Freq= 0, CH_1, rank 0
6615 19:57:09.056213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 19:57:09.056296 ==
6617 19:57:09.062483 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6618 19:57:09.066304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6619 19:57:09.069293 [CA 0] Center 36 (8~64) winsize 57
6620 19:57:09.072303 [CA 1] Center 36 (8~64) winsize 57
6621 19:57:09.076443 [CA 2] Center 36 (8~64) winsize 57
6622 19:57:09.079353 [CA 3] Center 36 (8~64) winsize 57
6623 19:57:09.082777 [CA 4] Center 36 (8~64) winsize 57
6624 19:57:09.085653 [CA 5] Center 36 (8~64) winsize 57
6625 19:57:09.085735
6626 19:57:09.089119 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6627 19:57:09.089210
6628 19:57:09.092431 [CATrainingPosCal] consider 1 rank data
6629 19:57:09.095791 u2DelayCellTimex100 = 270/100 ps
6630 19:57:09.099154 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 19:57:09.102370 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 19:57:09.109518 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 19:57:09.112786 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 19:57:09.115374 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 19:57:09.119144 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 19:57:09.119224
6637 19:57:09.122915 CA PerBit enable=1, Macro0, CA PI delay=36
6638 19:57:09.122995
6639 19:57:09.125471 [CBTSetCACLKResult] CA Dly = 36
6640 19:57:09.125551 CS Dly: 1 (0~32)
6641 19:57:09.128937 ==
6642 19:57:09.129017 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 19:57:09.135841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 19:57:09.135921 ==
6645 19:57:09.139096 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 19:57:09.145910 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6647 19:57:09.148932 [CA 0] Center 36 (8~64) winsize 57
6648 19:57:09.152264 [CA 1] Center 36 (8~64) winsize 57
6649 19:57:09.155460 [CA 2] Center 36 (8~64) winsize 57
6650 19:57:09.158677 [CA 3] Center 36 (8~64) winsize 57
6651 19:57:09.161932 [CA 4] Center 36 (8~64) winsize 57
6652 19:57:09.165480 [CA 5] Center 36 (8~64) winsize 57
6653 19:57:09.165562
6654 19:57:09.168819 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6655 19:57:09.168903
6656 19:57:09.171857 [CATrainingPosCal] consider 2 rank data
6657 19:57:09.175140 u2DelayCellTimex100 = 270/100 ps
6658 19:57:09.178774 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 19:57:09.182156 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 19:57:09.185361 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 19:57:09.188870 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 19:57:09.195468 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 19:57:09.198774 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 19:57:09.198857
6665 19:57:09.201677 CA PerBit enable=1, Macro0, CA PI delay=36
6666 19:57:09.201759
6667 19:57:09.205179 [CBTSetCACLKResult] CA Dly = 36
6668 19:57:09.205262 CS Dly: 1 (0~32)
6669 19:57:09.205356
6670 19:57:09.208358 ----->DramcWriteLeveling(PI) begin...
6671 19:57:09.208442 ==
6672 19:57:09.211564 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 19:57:09.218819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 19:57:09.218901 ==
6675 19:57:09.221967 Write leveling (Byte 0): 40 => 8
6676 19:57:09.222050 Write leveling (Byte 1): 40 => 8
6677 19:57:09.224837 DramcWriteLeveling(PI) end<-----
6678 19:57:09.224919
6679 19:57:09.225003 ==
6680 19:57:09.228198 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 19:57:09.235570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 19:57:09.235653 ==
6683 19:57:09.238034 [Gating] SW mode calibration
6684 19:57:09.244528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6685 19:57:09.248326 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6686 19:57:09.255021 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6687 19:57:09.258328 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6688 19:57:09.261343 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 19:57:09.268204 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 19:57:09.271132 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 19:57:09.274588 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 19:57:09.281692 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 19:57:09.284948 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 19:57:09.288017 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 19:57:09.291232 Total UI for P1: 0, mck2ui 16
6696 19:57:09.294619 best dqsien dly found for B0: ( 0, 14, 24)
6697 19:57:09.297774 Total UI for P1: 0, mck2ui 16
6698 19:57:09.301164 best dqsien dly found for B1: ( 0, 14, 24)
6699 19:57:09.304487 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6700 19:57:09.307818 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6701 19:57:09.307902
6702 19:57:09.314076 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6703 19:57:09.317459 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6704 19:57:09.317543 [Gating] SW calibration Done
6705 19:57:09.321204 ==
6706 19:57:09.324082 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 19:57:09.327554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 19:57:09.327649 ==
6709 19:57:09.327740 RX Vref Scan: 0
6710 19:57:09.327839
6711 19:57:09.330552 RX Vref 0 -> 0, step: 1
6712 19:57:09.330652
6713 19:57:09.334014 RX Delay -410 -> 252, step: 16
6714 19:57:09.337328 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6715 19:57:09.343911 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6716 19:57:09.347363 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6717 19:57:09.350823 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6718 19:57:09.355007 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6719 19:57:09.357404 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6720 19:57:09.364484 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6721 19:57:09.367908 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6722 19:57:09.371190 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6723 19:57:09.373998 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6724 19:57:09.381032 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6725 19:57:09.384377 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6726 19:57:09.387766 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6727 19:57:09.394171 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6728 19:57:09.397397 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6729 19:57:09.400661 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6730 19:57:09.400742 ==
6731 19:57:09.403968 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 19:57:09.407214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 19:57:09.407295 ==
6734 19:57:09.410601 DQS Delay:
6735 19:57:09.410681 DQS0 = 51, DQS1 = 67
6736 19:57:09.413967 DQM Delay:
6737 19:57:09.414047 DQM0 = 13, DQM1 = 19
6738 19:57:09.417351 DQ Delay:
6739 19:57:09.417432 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6740 19:57:09.420566 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6741 19:57:09.423829 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6742 19:57:09.427301 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6743 19:57:09.427381
6744 19:57:09.427488
6745 19:57:09.427547 ==
6746 19:57:09.430586 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 19:57:09.437218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 19:57:09.437301 ==
6749 19:57:09.437364
6750 19:57:09.437423
6751 19:57:09.437479 TX Vref Scan disable
6752 19:57:09.440597 == TX Byte 0 ==
6753 19:57:09.443873 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 19:57:09.446810 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 19:57:09.450119 == TX Byte 1 ==
6756 19:57:09.453433 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 19:57:09.457294 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 19:57:09.460006 ==
6759 19:57:09.463362 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 19:57:09.466841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 19:57:09.466923 ==
6762 19:57:09.466988
6763 19:57:09.467045
6764 19:57:09.470350 TX Vref Scan disable
6765 19:57:09.470431 == TX Byte 0 ==
6766 19:57:09.473358 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 19:57:09.480441 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 19:57:09.480552 == TX Byte 1 ==
6769 19:57:09.483686 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 19:57:09.490290 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 19:57:09.490397
6772 19:57:09.490489 [DATLAT]
6773 19:57:09.490586 Freq=400, CH1 RK0
6774 19:57:09.490674
6775 19:57:09.493468 DATLAT Default: 0xf
6776 19:57:09.493548 0, 0xFFFF, sum = 0
6777 19:57:09.496616 1, 0xFFFF, sum = 0
6778 19:57:09.499984 2, 0xFFFF, sum = 0
6779 19:57:09.500095 3, 0xFFFF, sum = 0
6780 19:57:09.503067 4, 0xFFFF, sum = 0
6781 19:57:09.503148 5, 0xFFFF, sum = 0
6782 19:57:09.507031 6, 0xFFFF, sum = 0
6783 19:57:09.507119 7, 0xFFFF, sum = 0
6784 19:57:09.509646 8, 0xFFFF, sum = 0
6785 19:57:09.509744 9, 0xFFFF, sum = 0
6786 19:57:09.513344 10, 0xFFFF, sum = 0
6787 19:57:09.513425 11, 0xFFFF, sum = 0
6788 19:57:09.516229 12, 0xFFFF, sum = 0
6789 19:57:09.516311 13, 0x0, sum = 1
6790 19:57:09.519864 14, 0x0, sum = 2
6791 19:57:09.519946 15, 0x0, sum = 3
6792 19:57:09.523445 16, 0x0, sum = 4
6793 19:57:09.523525 best_step = 14
6794 19:57:09.523588
6795 19:57:09.523647 ==
6796 19:57:09.526505 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 19:57:09.529986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 19:57:09.532783 ==
6799 19:57:09.532862 RX Vref Scan: 1
6800 19:57:09.532925
6801 19:57:09.536130 RX Vref 0 -> 0, step: 1
6802 19:57:09.536209
6803 19:57:09.539621 RX Delay -375 -> 252, step: 8
6804 19:57:09.539700
6805 19:57:09.542581 Set Vref, RX VrefLevel [Byte0]: 54
6806 19:57:09.545879 [Byte1]: 53
6807 19:57:09.545959
6808 19:57:09.549580 Final RX Vref Byte 0 = 54 to rank0
6809 19:57:09.552851 Final RX Vref Byte 1 = 53 to rank0
6810 19:57:09.555956 Final RX Vref Byte 0 = 54 to rank1
6811 19:57:09.559632 Final RX Vref Byte 1 = 53 to rank1==
6812 19:57:09.563012 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 19:57:09.565776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 19:57:09.569364 ==
6815 19:57:09.569445 DQS Delay:
6816 19:57:09.569509 DQS0 = 52, DQS1 = 68
6817 19:57:09.572726 DQM Delay:
6818 19:57:09.572808 DQM0 = 9, DQM1 = 13
6819 19:57:09.576002 DQ Delay:
6820 19:57:09.576083 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6821 19:57:09.579061 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6822 19:57:09.582709 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6823 19:57:09.586453 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6824 19:57:09.586534
6825 19:57:09.586599
6826 19:57:09.596102 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6827 19:57:09.599079 CH1 RK0: MR19=C0C, MR18=5E72
6828 19:57:09.602487 CH1_RK0: MR19=0xC0C, MR18=0x5E72, DQSOSC=395, MR23=63, INC=378, DEC=252
6829 19:57:09.605578 ==
6830 19:57:09.609074 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 19:57:09.612239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 19:57:09.612321 ==
6833 19:57:09.615784 [Gating] SW mode calibration
6834 19:57:09.622164 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6835 19:57:09.625474 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6836 19:57:09.631954 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6837 19:57:09.635371 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6838 19:57:09.638486 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 19:57:09.645226 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 19:57:09.649177 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 19:57:09.651891 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 19:57:09.658733 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 19:57:09.662178 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 19:57:09.664972 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 19:57:09.668159 Total UI for P1: 0, mck2ui 16
6846 19:57:09.671543 best dqsien dly found for B0: ( 0, 14, 24)
6847 19:57:09.675185 Total UI for P1: 0, mck2ui 16
6848 19:57:09.678279 best dqsien dly found for B1: ( 0, 14, 24)
6849 19:57:09.681648 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6850 19:57:09.687899 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6851 19:57:09.687981
6852 19:57:09.691461 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6853 19:57:09.694668 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6854 19:57:09.697994 [Gating] SW calibration Done
6855 19:57:09.698075 ==
6856 19:57:09.701466 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 19:57:09.704570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 19:57:09.704653 ==
6859 19:57:09.708019 RX Vref Scan: 0
6860 19:57:09.708100
6861 19:57:09.708165 RX Vref 0 -> 0, step: 1
6862 19:57:09.708226
6863 19:57:09.711584 RX Delay -410 -> 252, step: 16
6864 19:57:09.715034 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6865 19:57:09.721136 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6866 19:57:09.724451 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6867 19:57:09.727935 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6868 19:57:09.731330 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6869 19:57:09.737451 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6870 19:57:09.740966 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6871 19:57:09.744159 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6872 19:57:09.747644 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6873 19:57:09.754533 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6874 19:57:09.757917 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6875 19:57:09.760997 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6876 19:57:09.767972 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6877 19:57:09.770416 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6878 19:57:09.774184 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6879 19:57:09.777358 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6880 19:57:09.780438 ==
6881 19:57:09.780520 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 19:57:09.787389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 19:57:09.787505 ==
6884 19:57:09.787569 DQS Delay:
6885 19:57:09.790862 DQS0 = 59, DQS1 = 59
6886 19:57:09.790942 DQM Delay:
6887 19:57:09.793757 DQM0 = 19, DQM1 = 14
6888 19:57:09.793838 DQ Delay:
6889 19:57:09.797157 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6890 19:57:09.800519 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6891 19:57:09.803663 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6892 19:57:09.807395 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6893 19:57:09.807476
6894 19:57:09.807540
6895 19:57:09.807599 ==
6896 19:57:09.810186 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 19:57:09.813524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 19:57:09.813606 ==
6899 19:57:09.813670
6900 19:57:09.813728
6901 19:57:09.817007 TX Vref Scan disable
6902 19:57:09.817087 == TX Byte 0 ==
6903 19:57:09.823719 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6904 19:57:09.826964 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6905 19:57:09.827045 == TX Byte 1 ==
6906 19:57:09.833562 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6907 19:57:09.836924 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6908 19:57:09.837005 ==
6909 19:57:09.840062 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 19:57:09.843368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 19:57:09.843459 ==
6912 19:57:09.843524
6913 19:57:09.843582
6914 19:57:09.846679 TX Vref Scan disable
6915 19:57:09.846760 == TX Byte 0 ==
6916 19:57:09.853259 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6917 19:57:09.856466 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6918 19:57:09.856547 == TX Byte 1 ==
6919 19:57:09.863210 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6920 19:57:09.866519 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6921 19:57:09.866601
6922 19:57:09.866665 [DATLAT]
6923 19:57:09.869608 Freq=400, CH1 RK1
6924 19:57:09.869702
6925 19:57:09.869774 DATLAT Default: 0xe
6926 19:57:09.873460 0, 0xFFFF, sum = 0
6927 19:57:09.873542 1, 0xFFFF, sum = 0
6928 19:57:09.876412 2, 0xFFFF, sum = 0
6929 19:57:09.876494 3, 0xFFFF, sum = 0
6930 19:57:09.880386 4, 0xFFFF, sum = 0
6931 19:57:09.880468 5, 0xFFFF, sum = 0
6932 19:57:09.882890 6, 0xFFFF, sum = 0
6933 19:57:09.886329 7, 0xFFFF, sum = 0
6934 19:57:09.886410 8, 0xFFFF, sum = 0
6935 19:57:09.889595 9, 0xFFFF, sum = 0
6936 19:57:09.889677 10, 0xFFFF, sum = 0
6937 19:57:09.892831 11, 0xFFFF, sum = 0
6938 19:57:09.892913 12, 0xFFFF, sum = 0
6939 19:57:09.896679 13, 0x0, sum = 1
6940 19:57:09.896761 14, 0x0, sum = 2
6941 19:57:09.899545 15, 0x0, sum = 3
6942 19:57:09.899628 16, 0x0, sum = 4
6943 19:57:09.902675 best_step = 14
6944 19:57:09.902756
6945 19:57:09.902820 ==
6946 19:57:09.906061 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 19:57:09.909334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 19:57:09.909416 ==
6949 19:57:09.909480 RX Vref Scan: 0
6950 19:57:09.909539
6951 19:57:09.912827 RX Vref 0 -> 0, step: 1
6952 19:57:09.912907
6953 19:57:09.915977 RX Delay -359 -> 252, step: 8
6954 19:57:09.923617 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6955 19:57:09.927032 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6956 19:57:09.930129 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6957 19:57:09.933404 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6958 19:57:09.939834 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6959 19:57:09.943004 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6960 19:57:09.946875 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6961 19:57:09.953255 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6962 19:57:09.956698 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6963 19:57:09.960148 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6964 19:57:09.962847 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6965 19:57:09.969890 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6966 19:57:09.973019 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6967 19:57:09.976259 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6968 19:57:09.979467 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6969 19:57:09.986671 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6970 19:57:09.986752 ==
6971 19:57:09.989552 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 19:57:09.992920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 19:57:09.993001 ==
6974 19:57:09.993065 DQS Delay:
6975 19:57:09.996153 DQS0 = 60, DQS1 = 64
6976 19:57:09.996234 DQM Delay:
6977 19:57:09.999316 DQM0 = 13, DQM1 = 10
6978 19:57:09.999403 DQ Delay:
6979 19:57:10.003221 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6980 19:57:10.006595 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6981 19:57:10.010014 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6982 19:57:10.013008 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6983 19:57:10.013090
6984 19:57:10.013172
6985 19:57:10.019529 [DQSOSCAuto] RK1, (LSB)MR18= 0x79a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6986 19:57:10.022651 CH1 RK1: MR19=C0C, MR18=79A8
6987 19:57:10.028960 CH1_RK1: MR19=0xC0C, MR18=0x79A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6988 19:57:10.032339 [RxdqsGatingPostProcess] freq 400
6989 19:57:10.039493 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6990 19:57:10.042421 best DQS0 dly(2T, 0.5T) = (0, 10)
6991 19:57:10.045564 best DQS1 dly(2T, 0.5T) = (0, 10)
6992 19:57:10.045645 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6993 19:57:10.048963 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6994 19:57:10.052722 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 19:57:10.055773 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 19:57:10.059629 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 19:57:10.062552 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 19:57:10.066068 Pre-setting of DQS Precalculation
6999 19:57:10.072338 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7000 19:57:10.079123 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7001 19:57:10.085622 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7002 19:57:10.085708
7003 19:57:10.085793
7004 19:57:10.088806 [Calibration Summary] 800 Mbps
7005 19:57:10.088914 CH 0, Rank 0
7006 19:57:10.092140 SW Impedance : PASS
7007 19:57:10.095562 DUTY Scan : NO K
7008 19:57:10.095645 ZQ Calibration : PASS
7009 19:57:10.099227 Jitter Meter : NO K
7010 19:57:10.102427 CBT Training : PASS
7011 19:57:10.102509 Write leveling : PASS
7012 19:57:10.105748 RX DQS gating : PASS
7013 19:57:10.108554 RX DQ/DQS(RDDQC) : PASS
7014 19:57:10.108637 TX DQ/DQS : PASS
7015 19:57:10.112471 RX DATLAT : PASS
7016 19:57:10.112553 RX DQ/DQS(Engine): PASS
7017 19:57:10.115568 TX OE : NO K
7018 19:57:10.115651 All Pass.
7019 19:57:10.115735
7020 19:57:10.118871 CH 0, Rank 1
7021 19:57:10.118954 SW Impedance : PASS
7022 19:57:10.122094 DUTY Scan : NO K
7023 19:57:10.125863 ZQ Calibration : PASS
7024 19:57:10.125945 Jitter Meter : NO K
7025 19:57:10.128764 CBT Training : PASS
7026 19:57:10.132311 Write leveling : NO K
7027 19:57:10.132422 RX DQS gating : PASS
7028 19:57:10.135282 RX DQ/DQS(RDDQC) : PASS
7029 19:57:10.139032 TX DQ/DQS : PASS
7030 19:57:10.139114 RX DATLAT : PASS
7031 19:57:10.142142 RX DQ/DQS(Engine): PASS
7032 19:57:10.145478 TX OE : NO K
7033 19:57:10.145561 All Pass.
7034 19:57:10.145646
7035 19:57:10.145726 CH 1, Rank 0
7036 19:57:10.149193 SW Impedance : PASS
7037 19:57:10.152059 DUTY Scan : NO K
7038 19:57:10.152142 ZQ Calibration : PASS
7039 19:57:10.155607 Jitter Meter : NO K
7040 19:57:10.159042 CBT Training : PASS
7041 19:57:10.159125 Write leveling : PASS
7042 19:57:10.162160 RX DQS gating : PASS
7043 19:57:10.162242 RX DQ/DQS(RDDQC) : PASS
7044 19:57:10.165708 TX DQ/DQS : PASS
7045 19:57:10.168521 RX DATLAT : PASS
7046 19:57:10.168671 RX DQ/DQS(Engine): PASS
7047 19:57:10.172502 TX OE : NO K
7048 19:57:10.172584 All Pass.
7049 19:57:10.172648
7050 19:57:10.175045 CH 1, Rank 1
7051 19:57:10.175125 SW Impedance : PASS
7052 19:57:10.178628 DUTY Scan : NO K
7053 19:57:10.181925 ZQ Calibration : PASS
7054 19:57:10.182004 Jitter Meter : NO K
7055 19:57:10.185172 CBT Training : PASS
7056 19:57:10.188272 Write leveling : NO K
7057 19:57:10.188353 RX DQS gating : PASS
7058 19:57:10.191963 RX DQ/DQS(RDDQC) : PASS
7059 19:57:10.195266 TX DQ/DQS : PASS
7060 19:57:10.195372 RX DATLAT : PASS
7061 19:57:10.198489 RX DQ/DQS(Engine): PASS
7062 19:57:10.201812 TX OE : NO K
7063 19:57:10.201893 All Pass.
7064 19:57:10.201956
7065 19:57:10.202015 DramC Write-DBI off
7066 19:57:10.204984 PER_BANK_REFRESH: Hybrid Mode
7067 19:57:10.208487 TX_TRACKING: ON
7068 19:57:10.215272 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7069 19:57:10.221485 [FAST_K] Save calibration result to emmc
7070 19:57:10.225182 dramc_set_vcore_voltage set vcore to 725000
7071 19:57:10.225262 Read voltage for 1600, 0
7072 19:57:10.227935 Vio18 = 0
7073 19:57:10.228015 Vcore = 725000
7074 19:57:10.228077 Vdram = 0
7075 19:57:10.231276 Vddq = 0
7076 19:57:10.231381 Vmddr = 0
7077 19:57:10.234577 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7078 19:57:10.241245 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7079 19:57:10.245072 MEM_TYPE=3, freq_sel=13
7080 19:57:10.248022 sv_algorithm_assistance_LP4_3733
7081 19:57:10.251266 ============ PULL DRAM RESETB DOWN ============
7082 19:57:10.255133 ========== PULL DRAM RESETB DOWN end =========
7083 19:57:10.261790 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7084 19:57:10.261871 ===================================
7085 19:57:10.264384 LPDDR4 DRAM CONFIGURATION
7086 19:57:10.268271 ===================================
7087 19:57:10.271745 EX_ROW_EN[0] = 0x0
7088 19:57:10.271825 EX_ROW_EN[1] = 0x0
7089 19:57:10.274602 LP4Y_EN = 0x0
7090 19:57:10.274719 WORK_FSP = 0x1
7091 19:57:10.277828 WL = 0x5
7092 19:57:10.277907 RL = 0x5
7093 19:57:10.281231 BL = 0x2
7094 19:57:10.284600 RPST = 0x0
7095 19:57:10.284716 RD_PRE = 0x0
7096 19:57:10.287565 WR_PRE = 0x1
7097 19:57:10.287645 WR_PST = 0x1
7098 19:57:10.291477 DBI_WR = 0x0
7099 19:57:10.291556 DBI_RD = 0x0
7100 19:57:10.294483 OTF = 0x1
7101 19:57:10.297582 ===================================
7102 19:57:10.300840 ===================================
7103 19:57:10.300958 ANA top config
7104 19:57:10.304175 ===================================
7105 19:57:10.307591 DLL_ASYNC_EN = 0
7106 19:57:10.311122 ALL_SLAVE_EN = 0
7107 19:57:10.311204 NEW_RANK_MODE = 1
7108 19:57:10.314095 DLL_IDLE_MODE = 1
7109 19:57:10.317415 LP45_APHY_COMB_EN = 1
7110 19:57:10.320761 TX_ODT_DIS = 0
7111 19:57:10.320842 NEW_8X_MODE = 1
7112 19:57:10.324559 ===================================
7113 19:57:10.327714 ===================================
7114 19:57:10.330873 data_rate = 3200
7115 19:57:10.334009 CKR = 1
7116 19:57:10.337491 DQ_P2S_RATIO = 8
7117 19:57:10.340910 ===================================
7118 19:57:10.344507 CA_P2S_RATIO = 8
7119 19:57:10.347945 DQ_CA_OPEN = 0
7120 19:57:10.348026 DQ_SEMI_OPEN = 0
7121 19:57:10.350618 CA_SEMI_OPEN = 0
7122 19:57:10.353995 CA_FULL_RATE = 0
7123 19:57:10.357501 DQ_CKDIV4_EN = 0
7124 19:57:10.360886 CA_CKDIV4_EN = 0
7125 19:57:10.363726 CA_PREDIV_EN = 0
7126 19:57:10.367269 PH8_DLY = 12
7127 19:57:10.367350 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7128 19:57:10.370647 DQ_AAMCK_DIV = 4
7129 19:57:10.373762 CA_AAMCK_DIV = 4
7130 19:57:10.377211 CA_ADMCK_DIV = 4
7131 19:57:10.380551 DQ_TRACK_CA_EN = 0
7132 19:57:10.383730 CA_PICK = 1600
7133 19:57:10.387268 CA_MCKIO = 1600
7134 19:57:10.387364 MCKIO_SEMI = 0
7135 19:57:10.390410 PLL_FREQ = 3068
7136 19:57:10.394186 DQ_UI_PI_RATIO = 32
7137 19:57:10.397482 CA_UI_PI_RATIO = 0
7138 19:57:10.400416 ===================================
7139 19:57:10.404099 ===================================
7140 19:57:10.407327 memory_type:LPDDR4
7141 19:57:10.407448 GP_NUM : 10
7142 19:57:10.410324 SRAM_EN : 1
7143 19:57:10.410405 MD32_EN : 0
7144 19:57:10.413727 ===================================
7145 19:57:10.417105 [ANA_INIT] >>>>>>>>>>>>>>
7146 19:57:10.420445 <<<<<< [CONFIGURE PHASE]: ANA_TX
7147 19:57:10.423877 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7148 19:57:10.426963 ===================================
7149 19:57:10.430661 data_rate = 3200,PCW = 0X7600
7150 19:57:10.433622 ===================================
7151 19:57:10.436965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7152 19:57:10.443532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7153 19:57:10.447332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7154 19:57:10.453592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7155 19:57:10.456753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7156 19:57:10.460030 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7157 19:57:10.460112 [ANA_INIT] flow start
7158 19:57:10.463588 [ANA_INIT] PLL >>>>>>>>
7159 19:57:10.466958 [ANA_INIT] PLL <<<<<<<<
7160 19:57:10.467039 [ANA_INIT] MIDPI >>>>>>>>
7161 19:57:10.470427 [ANA_INIT] MIDPI <<<<<<<<
7162 19:57:10.473769 [ANA_INIT] DLL >>>>>>>>
7163 19:57:10.476563 [ANA_INIT] DLL <<<<<<<<
7164 19:57:10.476644 [ANA_INIT] flow end
7165 19:57:10.479978 ============ LP4 DIFF to SE enter ============
7166 19:57:10.486962 ============ LP4 DIFF to SE exit ============
7167 19:57:10.487044 [ANA_INIT] <<<<<<<<<<<<<
7168 19:57:10.490382 [Flow] Enable top DCM control >>>>>
7169 19:57:10.493436 [Flow] Enable top DCM control <<<<<
7170 19:57:10.497151 Enable DLL master slave shuffle
7171 19:57:10.503346 ==============================================================
7172 19:57:10.503468 Gating Mode config
7173 19:57:10.510306 ==============================================================
7174 19:57:10.513669 Config description:
7175 19:57:10.519974 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7176 19:57:10.526473 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7177 19:57:10.533324 SELPH_MODE 0: By rank 1: By Phase
7178 19:57:10.539820 ==============================================================
7179 19:57:10.543883 GAT_TRACK_EN = 1
7180 19:57:10.543964 RX_GATING_MODE = 2
7181 19:57:10.546740 RX_GATING_TRACK_MODE = 2
7182 19:57:10.550367 SELPH_MODE = 1
7183 19:57:10.553113 PICG_EARLY_EN = 1
7184 19:57:10.556423 VALID_LAT_VALUE = 1
7185 19:57:10.562828 ==============================================================
7186 19:57:10.566224 Enter into Gating configuration >>>>
7187 19:57:10.569873 Exit from Gating configuration <<<<
7188 19:57:10.573511 Enter into DVFS_PRE_config >>>>>
7189 19:57:10.583022 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7190 19:57:10.585853 Exit from DVFS_PRE_config <<<<<
7191 19:57:10.589266 Enter into PICG configuration >>>>
7192 19:57:10.592687 Exit from PICG configuration <<<<
7193 19:57:10.596165 [RX_INPUT] configuration >>>>>
7194 19:57:10.599502 [RX_INPUT] configuration <<<<<
7195 19:57:10.602537 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7196 19:57:10.609380 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7197 19:57:10.615985 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7198 19:57:10.622537 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7199 19:57:10.625765 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7200 19:57:10.632476 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7201 19:57:10.635374 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7202 19:57:10.642184 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7203 19:57:10.645537 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7204 19:57:10.649122 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7205 19:57:10.651964 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7206 19:57:10.659036 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7207 19:57:10.661926 ===================================
7208 19:57:10.662007 LPDDR4 DRAM CONFIGURATION
7209 19:57:10.665712 ===================================
7210 19:57:10.668700 EX_ROW_EN[0] = 0x0
7211 19:57:10.672202 EX_ROW_EN[1] = 0x0
7212 19:57:10.672283 LP4Y_EN = 0x0
7213 19:57:10.675175 WORK_FSP = 0x1
7214 19:57:10.675261 WL = 0x5
7215 19:57:10.678655 RL = 0x5
7216 19:57:10.678734 BL = 0x2
7217 19:57:10.681942 RPST = 0x0
7218 19:57:10.682022 RD_PRE = 0x0
7219 19:57:10.685276 WR_PRE = 0x1
7220 19:57:10.685355 WR_PST = 0x1
7221 19:57:10.688583 DBI_WR = 0x0
7222 19:57:10.688662 DBI_RD = 0x0
7223 19:57:10.692024 OTF = 0x1
7224 19:57:10.694952 ===================================
7225 19:57:10.698797 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7226 19:57:10.701971 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7227 19:57:10.708384 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7228 19:57:10.711767 ===================================
7229 19:57:10.711847 LPDDR4 DRAM CONFIGURATION
7230 19:57:10.714971 ===================================
7231 19:57:10.718467 EX_ROW_EN[0] = 0x10
7232 19:57:10.721477 EX_ROW_EN[1] = 0x0
7233 19:57:10.721556 LP4Y_EN = 0x0
7234 19:57:10.724813 WORK_FSP = 0x1
7235 19:57:10.724892 WL = 0x5
7236 19:57:10.728377 RL = 0x5
7237 19:57:10.728456 BL = 0x2
7238 19:57:10.731635 RPST = 0x0
7239 19:57:10.731715 RD_PRE = 0x0
7240 19:57:10.734876 WR_PRE = 0x1
7241 19:57:10.734956 WR_PST = 0x1
7242 19:57:10.738365 DBI_WR = 0x0
7243 19:57:10.738444 DBI_RD = 0x0
7244 19:57:10.741671 OTF = 0x1
7245 19:57:10.744909 ===================================
7246 19:57:10.751142 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7247 19:57:10.751223 ==
7248 19:57:10.755017 Dram Type= 6, Freq= 0, CH_0, rank 0
7249 19:57:10.758238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7250 19:57:10.758318 ==
7251 19:57:10.761217 [Duty_Offset_Calibration]
7252 19:57:10.761297 B0:2 B1:0 CA:3
7253 19:57:10.761360
7254 19:57:10.764620 [DutyScan_Calibration_Flow] k_type=0
7255 19:57:10.775316
7256 19:57:10.775426 ==CLK 0==
7257 19:57:10.779179 Final CLK duty delay cell = 0
7258 19:57:10.782242 [0] MAX Duty = 5031%(X100), DQS PI = 12
7259 19:57:10.785374 [0] MIN Duty = 4907%(X100), DQS PI = 6
7260 19:57:10.785455 [0] AVG Duty = 4969%(X100)
7261 19:57:10.789252
7262 19:57:10.789359 CH0 CLK Duty spec in!! Max-Min= 124%
7263 19:57:10.795296 [DutyScan_Calibration_Flow] ====Done====
7264 19:57:10.795379
7265 19:57:10.799255 [DutyScan_Calibration_Flow] k_type=1
7266 19:57:10.815568
7267 19:57:10.815653 ==DQS 0 ==
7268 19:57:10.819067 Final DQS duty delay cell = 0
7269 19:57:10.822257 [0] MAX Duty = 5125%(X100), DQS PI = 30
7270 19:57:10.825478 [0] MIN Duty = 4875%(X100), DQS PI = 52
7271 19:57:10.828889 [0] AVG Duty = 5000%(X100)
7272 19:57:10.828970
7273 19:57:10.829034 ==DQS 1 ==
7274 19:57:10.831950 Final DQS duty delay cell = 0
7275 19:57:10.835326 [0] MAX Duty = 5156%(X100), DQS PI = 32
7276 19:57:10.838393 [0] MIN Duty = 5031%(X100), DQS PI = 12
7277 19:57:10.841973 [0] AVG Duty = 5093%(X100)
7278 19:57:10.842054
7279 19:57:10.845339 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7280 19:57:10.845419
7281 19:57:10.848325 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7282 19:57:10.851990 [DutyScan_Calibration_Flow] ====Done====
7283 19:57:10.852069
7284 19:57:10.855305 [DutyScan_Calibration_Flow] k_type=3
7285 19:57:10.873280
7286 19:57:10.873365 ==DQM 0 ==
7287 19:57:10.876418 Final DQM duty delay cell = 0
7288 19:57:10.879244 [0] MAX Duty = 5187%(X100), DQS PI = 32
7289 19:57:10.882578 [0] MIN Duty = 4875%(X100), DQS PI = 0
7290 19:57:10.885787 [0] AVG Duty = 5031%(X100)
7291 19:57:10.885867
7292 19:57:10.885930 ==DQM 1 ==
7293 19:57:10.889107 Final DQM duty delay cell = 0
7294 19:57:10.892728 [0] MAX Duty = 4938%(X100), DQS PI = 0
7295 19:57:10.895851 [0] MIN Duty = 4813%(X100), DQS PI = 12
7296 19:57:10.899005 [0] AVG Duty = 4875%(X100)
7297 19:57:10.899085
7298 19:57:10.902624 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7299 19:57:10.902703
7300 19:57:10.905846 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7301 19:57:10.908865 [DutyScan_Calibration_Flow] ====Done====
7302 19:57:10.908970
7303 19:57:10.912465 [DutyScan_Calibration_Flow] k_type=2
7304 19:57:10.928829
7305 19:57:10.928917 ==DQ 0 ==
7306 19:57:10.932116 Final DQ duty delay cell = -4
7307 19:57:10.935984 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7308 19:57:10.939283 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7309 19:57:10.942496 [-4] AVG Duty = 4938%(X100)
7310 19:57:10.942576
7311 19:57:10.942639 ==DQ 1 ==
7312 19:57:10.945936 Final DQ duty delay cell = 0
7313 19:57:10.949031 [0] MAX Duty = 5156%(X100), DQS PI = 60
7314 19:57:10.952288 [0] MIN Duty = 5000%(X100), DQS PI = 18
7315 19:57:10.955692 [0] AVG Duty = 5078%(X100)
7316 19:57:10.955771
7317 19:57:10.958639 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7318 19:57:10.958719
7319 19:57:10.961995 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7320 19:57:10.965724 [DutyScan_Calibration_Flow] ====Done====
7321 19:57:10.965804 ==
7322 19:57:10.968859 Dram Type= 6, Freq= 0, CH_1, rank 0
7323 19:57:10.972343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7324 19:57:10.972424 ==
7325 19:57:10.975543 [Duty_Offset_Calibration]
7326 19:57:10.975623 B0:1 B1:-2 CA:0
7327 19:57:10.975686
7328 19:57:10.978931 [DutyScan_Calibration_Flow] k_type=0
7329 19:57:10.989726
7330 19:57:10.989806 ==CLK 0==
7331 19:57:10.992952 Final CLK duty delay cell = 0
7332 19:57:10.996361 [0] MAX Duty = 5062%(X100), DQS PI = 20
7333 19:57:10.999660 [0] MIN Duty = 4813%(X100), DQS PI = 60
7334 19:57:11.002980 [0] AVG Duty = 4937%(X100)
7335 19:57:11.003060
7336 19:57:11.006341 CH1 CLK Duty spec in!! Max-Min= 249%
7337 19:57:11.009492 [DutyScan_Calibration_Flow] ====Done====
7338 19:57:11.009573
7339 19:57:11.012559 [DutyScan_Calibration_Flow] k_type=1
7340 19:57:11.028689
7341 19:57:11.028776 ==DQS 0 ==
7342 19:57:11.031943 Final DQS duty delay cell = -4
7343 19:57:11.035282 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7344 19:57:11.038278 [-4] MIN Duty = 4813%(X100), DQS PI = 54
7345 19:57:11.041664 [-4] AVG Duty = 4906%(X100)
7346 19:57:11.041744
7347 19:57:11.041807 ==DQS 1 ==
7348 19:57:11.045072 Final DQS duty delay cell = 0
7349 19:57:11.048568 [0] MAX Duty = 5093%(X100), DQS PI = 60
7350 19:57:11.051463 [0] MIN Duty = 4844%(X100), DQS PI = 24
7351 19:57:11.054962 [0] AVG Duty = 4968%(X100)
7352 19:57:11.055041
7353 19:57:11.058422 CH1 DQS 0 Duty spec in!! Max-Min= 187%
7354 19:57:11.058501
7355 19:57:11.061649 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7356 19:57:11.064983 [DutyScan_Calibration_Flow] ====Done====
7357 19:57:11.065066
7358 19:57:11.068010 [DutyScan_Calibration_Flow] k_type=3
7359 19:57:11.085889
7360 19:57:11.085985 ==DQM 0 ==
7361 19:57:11.088871 Final DQM duty delay cell = 0
7362 19:57:11.092808 [0] MAX Duty = 5031%(X100), DQS PI = 26
7363 19:57:11.095879 [0] MIN Duty = 4813%(X100), DQS PI = 54
7364 19:57:11.095972 [0] AVG Duty = 4922%(X100)
7365 19:57:11.099064
7366 19:57:11.099145 ==DQM 1 ==
7367 19:57:11.102485 Final DQM duty delay cell = 0
7368 19:57:11.105696 [0] MAX Duty = 5062%(X100), DQS PI = 34
7369 19:57:11.109134 [0] MIN Duty = 4875%(X100), DQS PI = 24
7370 19:57:11.112860 [0] AVG Duty = 4968%(X100)
7371 19:57:11.112941
7372 19:57:11.115963 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7373 19:57:11.116044
7374 19:57:11.118880 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7375 19:57:11.122385 [DutyScan_Calibration_Flow] ====Done====
7376 19:57:11.122491
7377 19:57:11.125641 [DutyScan_Calibration_Flow] k_type=2
7378 19:57:11.142882
7379 19:57:11.142974 ==DQ 0 ==
7380 19:57:11.146160 Final DQ duty delay cell = 0
7381 19:57:11.149576 [0] MAX Duty = 5093%(X100), DQS PI = 20
7382 19:57:11.152756 [0] MIN Duty = 4907%(X100), DQS PI = 62
7383 19:57:11.152837 [0] AVG Duty = 5000%(X100)
7384 19:57:11.155824
7385 19:57:11.155905 ==DQ 1 ==
7386 19:57:11.159111 Final DQ duty delay cell = 0
7387 19:57:11.162622 [0] MAX Duty = 5125%(X100), DQS PI = 34
7388 19:57:11.165726 [0] MIN Duty = 4969%(X100), DQS PI = 24
7389 19:57:11.165807 [0] AVG Duty = 5047%(X100)
7390 19:57:11.169287
7391 19:57:11.172556 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7392 19:57:11.172637
7393 19:57:11.175669 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7394 19:57:11.178995 [DutyScan_Calibration_Flow] ====Done====
7395 19:57:11.182185 nWR fixed to 30
7396 19:57:11.182267 [ModeRegInit_LP4] CH0 RK0
7397 19:57:11.185961 [ModeRegInit_LP4] CH0 RK1
7398 19:57:11.188978 [ModeRegInit_LP4] CH1 RK0
7399 19:57:11.192384 [ModeRegInit_LP4] CH1 RK1
7400 19:57:11.192465 match AC timing 5
7401 19:57:11.198842 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7402 19:57:11.202289 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7403 19:57:11.205965 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7404 19:57:11.212339 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7405 19:57:11.215665 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7406 19:57:11.215746 [MiockJmeterHQA]
7407 19:57:11.215810
7408 19:57:11.219077 [DramcMiockJmeter] u1RxGatingPI = 0
7409 19:57:11.222061 0 : 4253, 4027
7410 19:57:11.222143 4 : 4368, 4140
7411 19:57:11.225314 8 : 4252, 4027
7412 19:57:11.225396 12 : 4252, 4027
7413 19:57:11.225462 16 : 4252, 4027
7414 19:57:11.228970 20 : 4253, 4026
7415 19:57:11.229052 24 : 4255, 4029
7416 19:57:11.232169 28 : 4252, 4027
7417 19:57:11.232250 32 : 4252, 4027
7418 19:57:11.235459 36 : 4366, 4139
7419 19:57:11.235541 40 : 4253, 4027
7420 19:57:11.238830 44 : 4255, 4029
7421 19:57:11.238912 48 : 4253, 4026
7422 19:57:11.238977 52 : 4363, 4137
7423 19:57:11.242110 56 : 4252, 4027
7424 19:57:11.242191 60 : 4363, 4137
7425 19:57:11.245304 64 : 4253, 4029
7426 19:57:11.245386 68 : 4250, 4026
7427 19:57:11.248559 72 : 4250, 4027
7428 19:57:11.248641 76 : 4252, 4030
7429 19:57:11.251848 80 : 4250, 4027
7430 19:57:11.251930 84 : 4250, 4027
7431 19:57:11.251995 88 : 4363, 4140
7432 19:57:11.254971 92 : 4250, 4027
7433 19:57:11.255053 96 : 4252, 4029
7434 19:57:11.258443 100 : 4250, 4026
7435 19:57:11.258525 104 : 4253, 3749
7436 19:57:11.261941 108 : 4250, 1
7437 19:57:11.262023 112 : 4360, 0
7438 19:57:11.262089 116 : 4363, 0
7439 19:57:11.265675 120 : 4252, 0
7440 19:57:11.265757 124 : 4253, 0
7441 19:57:11.269279 128 : 4250, 0
7442 19:57:11.269361 132 : 4252, 0
7443 19:57:11.269427 136 : 4250, 0
7444 19:57:11.271765 140 : 4250, 0
7445 19:57:11.271847 144 : 4253, 0
7446 19:57:11.275111 148 : 4361, 0
7447 19:57:11.275193 152 : 4250, 0
7448 19:57:11.275258 156 : 4250, 0
7449 19:57:11.278448 160 : 4360, 0
7450 19:57:11.278529 164 : 4360, 0
7451 19:57:11.281981 168 : 4363, 0
7452 19:57:11.282062 172 : 4250, 0
7453 19:57:11.282127 176 : 4250, 0
7454 19:57:11.284995 180 : 4250, 0
7455 19:57:11.285077 184 : 4252, 0
7456 19:57:11.285142 188 : 4250, 0
7457 19:57:11.288364 192 : 4250, 0
7458 19:57:11.288446 196 : 4249, 0
7459 19:57:11.291844 200 : 4250, 0
7460 19:57:11.291925 204 : 4250, 0
7461 19:57:11.291991 208 : 4252, 0
7462 19:57:11.295094 212 : 4250, 0
7463 19:57:11.295176 216 : 4361, 0
7464 19:57:11.298433 220 : 4250, 0
7465 19:57:11.298514 224 : 4249, 0
7466 19:57:11.298580 228 : 4250, 0
7467 19:57:11.301670 232 : 4250, 0
7468 19:57:11.301752 236 : 4249, 1152
7469 19:57:11.304648 240 : 4363, 4139
7470 19:57:11.304729 244 : 4249, 4027
7471 19:57:11.308213 248 : 4250, 4026
7472 19:57:11.308295 252 : 4250, 4027
7473 19:57:11.311546 256 : 4252, 4029
7474 19:57:11.311628 260 : 4250, 4027
7475 19:57:11.311693 264 : 4250, 4027
7476 19:57:11.314703 268 : 4250, 4027
7477 19:57:11.314784 272 : 4252, 4030
7478 19:57:11.318322 276 : 4250, 4027
7479 19:57:11.318405 280 : 4360, 4138
7480 19:57:11.321449 284 : 4361, 4137
7481 19:57:11.321531 288 : 4250, 4026
7482 19:57:11.325430 292 : 4363, 4140
7483 19:57:11.325512 296 : 4250, 4027
7484 19:57:11.328182 300 : 4250, 4026
7485 19:57:11.328264 304 : 4250, 4027
7486 19:57:11.331496 308 : 4252, 4029
7487 19:57:11.331577 312 : 4250, 4027
7488 19:57:11.334681 316 : 4250, 4027
7489 19:57:11.334763 320 : 4250, 4027
7490 19:57:11.334828 324 : 4252, 4029
7491 19:57:11.338078 328 : 4250, 4027
7492 19:57:11.338159 332 : 4360, 4138
7493 19:57:11.341345 336 : 4361, 4137
7494 19:57:11.341426 340 : 4250, 4026
7495 19:57:11.344826 344 : 4363, 4139
7496 19:57:11.344908 348 : 4250, 4027
7497 19:57:11.347991 352 : 4249, 4001
7498 19:57:11.348073 356 : 4250, 2479
7499 19:57:11.351333 360 : 4252, 0
7500 19:57:11.351438
7501 19:57:11.351502 MIOCK jitter meter ch=0
7502 19:57:11.351562
7503 19:57:11.354613 1T = (360-108) = 252 dly cells
7504 19:57:11.361126 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7505 19:57:11.361208 ==
7506 19:57:11.364408 Dram Type= 6, Freq= 0, CH_0, rank 0
7507 19:57:11.367932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7508 19:57:11.368014 ==
7509 19:57:11.374717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7510 19:57:11.378189 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7511 19:57:11.381251 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7512 19:57:11.387688 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7513 19:57:11.398064 [CA 0] Center 43 (13~74) winsize 62
7514 19:57:11.400980 [CA 1] Center 43 (13~74) winsize 62
7515 19:57:11.404576 [CA 2] Center 39 (10~68) winsize 59
7516 19:57:11.407368 [CA 3] Center 39 (10~68) winsize 59
7517 19:57:11.411046 [CA 4] Center 36 (7~66) winsize 60
7518 19:57:11.414229 [CA 5] Center 36 (7~66) winsize 60
7519 19:57:11.414309
7520 19:57:11.417631 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7521 19:57:11.417711
7522 19:57:11.421073 [CATrainingPosCal] consider 1 rank data
7523 19:57:11.424116 u2DelayCellTimex100 = 258/100 ps
7524 19:57:11.431062 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7525 19:57:11.434083 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7526 19:57:11.437618 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7527 19:57:11.440619 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7528 19:57:11.443835 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7529 19:57:11.447816 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7530 19:57:11.447897
7531 19:57:11.450682 CA PerBit enable=1, Macro0, CA PI delay=36
7532 19:57:11.450765
7533 19:57:11.454094 [CBTSetCACLKResult] CA Dly = 36
7534 19:57:11.457131 CS Dly: 11 (0~42)
7535 19:57:11.460983 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7536 19:57:11.464127 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7537 19:57:11.464210 ==
7538 19:57:11.467187 Dram Type= 6, Freq= 0, CH_0, rank 1
7539 19:57:11.474202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 19:57:11.474284 ==
7541 19:57:11.477691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7542 19:57:11.483941 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7543 19:57:11.487180 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7544 19:57:11.494045 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7545 19:57:11.501558 [CA 0] Center 44 (13~75) winsize 63
7546 19:57:11.505144 [CA 1] Center 43 (13~74) winsize 62
7547 19:57:11.508551 [CA 2] Center 39 (10~69) winsize 60
7548 19:57:11.511579 [CA 3] Center 39 (10~68) winsize 59
7549 19:57:11.515063 [CA 4] Center 37 (8~67) winsize 60
7550 19:57:11.518404 [CA 5] Center 36 (7~66) winsize 60
7551 19:57:11.518486
7552 19:57:11.521432 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7553 19:57:11.521514
7554 19:57:11.525477 [CATrainingPosCal] consider 2 rank data
7555 19:57:11.528130 u2DelayCellTimex100 = 258/100 ps
7556 19:57:11.534853 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7557 19:57:11.538431 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7558 19:57:11.541263 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7559 19:57:11.544812 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7560 19:57:11.548382 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7561 19:57:11.551655 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7562 19:57:11.551737
7563 19:57:11.554463 CA PerBit enable=1, Macro0, CA PI delay=36
7564 19:57:11.554571
7565 19:57:11.558145 [CBTSetCACLKResult] CA Dly = 36
7566 19:57:11.561229 CS Dly: 11 (0~43)
7567 19:57:11.564429 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7568 19:57:11.568007 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7569 19:57:11.568088
7570 19:57:11.571120 ----->DramcWriteLeveling(PI) begin...
7571 19:57:11.571203 ==
7572 19:57:11.574674 Dram Type= 6, Freq= 0, CH_0, rank 0
7573 19:57:11.581482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 19:57:11.581566 ==
7575 19:57:11.584273 Write leveling (Byte 0): 36 => 36
7576 19:57:11.587882 Write leveling (Byte 1): 26 => 26
7577 19:57:11.591188 DramcWriteLeveling(PI) end<-----
7578 19:57:11.591296
7579 19:57:11.591397 ==
7580 19:57:11.594468 Dram Type= 6, Freq= 0, CH_0, rank 0
7581 19:57:11.597518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7582 19:57:11.597600 ==
7583 19:57:11.601072 [Gating] SW mode calibration
7584 19:57:11.607656 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7585 19:57:11.610834 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7586 19:57:11.617635 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 19:57:11.621003 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 19:57:11.624127 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 19:57:11.630940 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 19:57:11.634064 1 4 16 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7591 19:57:11.637414 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7592 19:57:11.644169 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7593 19:57:11.647570 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 19:57:11.650721 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 19:57:11.657504 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 19:57:11.660607 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 19:57:11.664235 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7598 19:57:11.670838 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7599 19:57:11.674366 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
7600 19:57:11.677702 1 5 24 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
7601 19:57:11.684061 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 19:57:11.687192 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 19:57:11.690432 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 19:57:11.697022 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 19:57:11.700646 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7606 19:57:11.703897 1 6 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7607 19:57:11.710322 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7608 19:57:11.713575 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7609 19:57:11.716826 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 19:57:11.723583 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 19:57:11.727235 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 19:57:11.730243 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 19:57:11.736806 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 19:57:11.740332 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7615 19:57:11.743494 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7616 19:57:11.750242 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7617 19:57:11.753700 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 19:57:11.757004 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 19:57:11.763894 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 19:57:11.766589 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 19:57:11.769853 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 19:57:11.776696 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 19:57:11.779910 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 19:57:11.783426 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 19:57:11.789842 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 19:57:11.793145 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 19:57:11.796780 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 19:57:11.803103 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 19:57:11.806242 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7630 19:57:11.809560 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7631 19:57:11.813249 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7632 19:57:11.816501 Total UI for P1: 0, mck2ui 16
7633 19:57:11.819818 best dqsien dly found for B0: ( 1, 9, 14)
7634 19:57:11.826570 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7635 19:57:11.829836 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 19:57:11.833598 Total UI for P1: 0, mck2ui 16
7637 19:57:11.836258 best dqsien dly found for B1: ( 1, 9, 24)
7638 19:57:11.839798 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7639 19:57:11.842836 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7640 19:57:11.842917
7641 19:57:11.846141 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7642 19:57:11.852603 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7643 19:57:11.852685 [Gating] SW calibration Done
7644 19:57:11.852816 ==
7645 19:57:11.856112 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 19:57:11.862856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 19:57:11.862939 ==
7648 19:57:11.863005 RX Vref Scan: 0
7649 19:57:11.863065
7650 19:57:11.866155 RX Vref 0 -> 0, step: 1
7651 19:57:11.866236
7652 19:57:11.869301 RX Delay 0 -> 252, step: 8
7653 19:57:11.873038 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7654 19:57:11.875704 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7655 19:57:11.878936 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7656 19:57:11.885880 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7657 19:57:11.889176 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7658 19:57:11.892383 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7659 19:57:11.895822 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7660 19:57:11.898928 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7661 19:57:11.905750 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7662 19:57:11.909126 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7663 19:57:11.912683 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7664 19:57:11.915726 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7665 19:57:11.919046 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7666 19:57:11.925480 iDelay=192, Bit 13, Center 127 (64 ~ 191) 128
7667 19:57:11.928666 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7668 19:57:11.932320 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7669 19:57:11.932402 ==
7670 19:57:11.935805 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 19:57:11.938984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 19:57:11.939066 ==
7673 19:57:11.942244 DQS Delay:
7674 19:57:11.942325 DQS0 = 0, DQS1 = 0
7675 19:57:11.945458 DQM Delay:
7676 19:57:11.945540 DQM0 = 128, DQM1 = 122
7677 19:57:11.948783 DQ Delay:
7678 19:57:11.952177 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7679 19:57:11.955294 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7680 19:57:11.958543 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7681 19:57:11.961813 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =131
7682 19:57:11.961894
7683 19:57:11.961959
7684 19:57:11.962019 ==
7685 19:57:11.965159 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 19:57:11.968667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 19:57:11.968749 ==
7688 19:57:11.968813
7689 19:57:11.968872
7690 19:57:11.971737 TX Vref Scan disable
7691 19:57:11.975134 == TX Byte 0 ==
7692 19:57:11.978817 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7693 19:57:11.982237 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7694 19:57:11.985111 == TX Byte 1 ==
7695 19:57:11.988354 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7696 19:57:11.991850 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7697 19:57:11.991932 ==
7698 19:57:11.995420 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 19:57:12.001843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 19:57:12.001925 ==
7701 19:57:12.016095
7702 19:57:12.018786 TX Vref early break, caculate TX vref
7703 19:57:12.022196 TX Vref=16, minBit 8, minWin=21, winSum=362
7704 19:57:12.025372 TX Vref=18, minBit 8, minWin=21, winSum=366
7705 19:57:12.029099 TX Vref=20, minBit 8, minWin=22, winSum=380
7706 19:57:12.032060 TX Vref=22, minBit 9, minWin=23, winSum=390
7707 19:57:12.035893 TX Vref=24, minBit 4, minWin=24, winSum=399
7708 19:57:12.042166 TX Vref=26, minBit 9, minWin=24, winSum=405
7709 19:57:12.045169 TX Vref=28, minBit 8, minWin=24, winSum=406
7710 19:57:12.048467 TX Vref=30, minBit 9, minWin=23, winSum=405
7711 19:57:12.051879 TX Vref=32, minBit 11, minWin=22, winSum=393
7712 19:57:12.055670 TX Vref=34, minBit 8, minWin=22, winSum=385
7713 19:57:12.058762 TX Vref=36, minBit 8, minWin=21, winSum=374
7714 19:57:12.065476 [TxChooseVref] Worse bit 8, Min win 24, Win sum 406, Final Vref 28
7715 19:57:12.065559
7716 19:57:12.068395 Final TX Range 0 Vref 28
7717 19:57:12.068477
7718 19:57:12.068543 ==
7719 19:57:12.071878 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 19:57:12.075079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 19:57:12.075161 ==
7722 19:57:12.075227
7723 19:57:12.078640
7724 19:57:12.078721 TX Vref Scan disable
7725 19:57:12.085087 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7726 19:57:12.085168 == TX Byte 0 ==
7727 19:57:12.088651 u2DelayCellOfst[0]=15 cells (4 PI)
7728 19:57:12.091598 u2DelayCellOfst[1]=22 cells (6 PI)
7729 19:57:12.095436 u2DelayCellOfst[2]=11 cells (3 PI)
7730 19:57:12.098395 u2DelayCellOfst[3]=15 cells (4 PI)
7731 19:57:12.101809 u2DelayCellOfst[4]=11 cells (3 PI)
7732 19:57:12.104913 u2DelayCellOfst[5]=0 cells (0 PI)
7733 19:57:12.108352 u2DelayCellOfst[6]=22 cells (6 PI)
7734 19:57:12.111755 u2DelayCellOfst[7]=18 cells (5 PI)
7735 19:57:12.114804 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7736 19:57:12.118273 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7737 19:57:12.121406 == TX Byte 1 ==
7738 19:57:12.124909 u2DelayCellOfst[8]=0 cells (0 PI)
7739 19:57:12.128285 u2DelayCellOfst[9]=3 cells (1 PI)
7740 19:57:12.131667 u2DelayCellOfst[10]=11 cells (3 PI)
7741 19:57:12.134628 u2DelayCellOfst[11]=7 cells (2 PI)
7742 19:57:12.138496 u2DelayCellOfst[12]=18 cells (5 PI)
7743 19:57:12.138584 u2DelayCellOfst[13]=15 cells (4 PI)
7744 19:57:12.141661 u2DelayCellOfst[14]=18 cells (5 PI)
7745 19:57:12.144605 u2DelayCellOfst[15]=15 cells (4 PI)
7746 19:57:12.151210 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7747 19:57:12.154713 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7748 19:57:12.154794 DramC Write-DBI on
7749 19:57:12.157798 ==
7750 19:57:12.161612 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 19:57:12.164504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 19:57:12.164586 ==
7753 19:57:12.164652
7754 19:57:12.164711
7755 19:57:12.167730 TX Vref Scan disable
7756 19:57:12.167810 == TX Byte 0 ==
7757 19:57:12.174426 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7758 19:57:12.174508 == TX Byte 1 ==
7759 19:57:12.178176 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7760 19:57:12.181526 DramC Write-DBI off
7761 19:57:12.181607
7762 19:57:12.181672 [DATLAT]
7763 19:57:12.184631 Freq=1600, CH0 RK0
7764 19:57:12.184712
7765 19:57:12.184777 DATLAT Default: 0xf
7766 19:57:12.187998 0, 0xFFFF, sum = 0
7767 19:57:12.188081 1, 0xFFFF, sum = 0
7768 19:57:12.190912 2, 0xFFFF, sum = 0
7769 19:57:12.190994 3, 0xFFFF, sum = 0
7770 19:57:12.194372 4, 0xFFFF, sum = 0
7771 19:57:12.197725 5, 0xFFFF, sum = 0
7772 19:57:12.197808 6, 0xFFFF, sum = 0
7773 19:57:12.200812 7, 0xFFFF, sum = 0
7774 19:57:12.200895 8, 0xFFFF, sum = 0
7775 19:57:12.204254 9, 0xFFFF, sum = 0
7776 19:57:12.204337 10, 0xFFFF, sum = 0
7777 19:57:12.208082 11, 0xFFFF, sum = 0
7778 19:57:12.208165 12, 0xFFFF, sum = 0
7779 19:57:12.211040 13, 0xEFFF, sum = 0
7780 19:57:12.211122 14, 0x0, sum = 1
7781 19:57:12.214193 15, 0x0, sum = 2
7782 19:57:12.214275 16, 0x0, sum = 3
7783 19:57:12.217658 17, 0x0, sum = 4
7784 19:57:12.217740 best_step = 15
7785 19:57:12.217806
7786 19:57:12.217866 ==
7787 19:57:12.220875 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 19:57:12.223997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 19:57:12.227188 ==
7790 19:57:12.227268 RX Vref Scan: 1
7791 19:57:12.227333
7792 19:57:12.230604 Set Vref Range= 24 -> 127
7793 19:57:12.230685
7794 19:57:12.234493 RX Vref 24 -> 127, step: 1
7795 19:57:12.234575
7796 19:57:12.234640 RX Delay 11 -> 252, step: 4
7797 19:57:12.234701
7798 19:57:12.237692 Set Vref, RX VrefLevel [Byte0]: 24
7799 19:57:12.240438 [Byte1]: 24
7800 19:57:12.244546
7801 19:57:12.244627 Set Vref, RX VrefLevel [Byte0]: 25
7802 19:57:12.247587 [Byte1]: 25
7803 19:57:12.251914
7804 19:57:12.251994 Set Vref, RX VrefLevel [Byte0]: 26
7805 19:57:12.255441 [Byte1]: 26
7806 19:57:12.259717
7807 19:57:12.259798 Set Vref, RX VrefLevel [Byte0]: 27
7808 19:57:12.263004 [Byte1]: 27
7809 19:57:12.267553
7810 19:57:12.267634 Set Vref, RX VrefLevel [Byte0]: 28
7811 19:57:12.270641 [Byte1]: 28
7812 19:57:12.275240
7813 19:57:12.275321 Set Vref, RX VrefLevel [Byte0]: 29
7814 19:57:12.278301 [Byte1]: 29
7815 19:57:12.282617
7816 19:57:12.282698 Set Vref, RX VrefLevel [Byte0]: 30
7817 19:57:12.285801 [Byte1]: 30
7818 19:57:12.289984
7819 19:57:12.290065 Set Vref, RX VrefLevel [Byte0]: 31
7820 19:57:12.293372 [Byte1]: 31
7821 19:57:12.297663
7822 19:57:12.297744 Set Vref, RX VrefLevel [Byte0]: 32
7823 19:57:12.301342 [Byte1]: 32
7824 19:57:12.305662
7825 19:57:12.305744 Set Vref, RX VrefLevel [Byte0]: 33
7826 19:57:12.308483 [Byte1]: 33
7827 19:57:12.312991
7828 19:57:12.313072 Set Vref, RX VrefLevel [Byte0]: 34
7829 19:57:12.316685 [Byte1]: 34
7830 19:57:12.320792
7831 19:57:12.320873 Set Vref, RX VrefLevel [Byte0]: 35
7832 19:57:12.323924 [Byte1]: 35
7833 19:57:12.328832
7834 19:57:12.328913 Set Vref, RX VrefLevel [Byte0]: 36
7835 19:57:12.331496 [Byte1]: 36
7836 19:57:12.335807
7837 19:57:12.335889 Set Vref, RX VrefLevel [Byte0]: 37
7838 19:57:12.339056 [Byte1]: 37
7839 19:57:12.343226
7840 19:57:12.343329 Set Vref, RX VrefLevel [Byte0]: 38
7841 19:57:12.346963 [Byte1]: 38
7842 19:57:12.351447
7843 19:57:12.351528 Set Vref, RX VrefLevel [Byte0]: 39
7844 19:57:12.354481 [Byte1]: 39
7845 19:57:12.358582
7846 19:57:12.358666 Set Vref, RX VrefLevel [Byte0]: 40
7847 19:57:12.362241 [Byte1]: 40
7848 19:57:12.366533
7849 19:57:12.366615 Set Vref, RX VrefLevel [Byte0]: 41
7850 19:57:12.369838 [Byte1]: 41
7851 19:57:12.373822
7852 19:57:12.373903 Set Vref, RX VrefLevel [Byte0]: 42
7853 19:57:12.377461 [Byte1]: 42
7854 19:57:12.381994
7855 19:57:12.382076 Set Vref, RX VrefLevel [Byte0]: 43
7856 19:57:12.384833 [Byte1]: 43
7857 19:57:12.389088
7858 19:57:12.389169 Set Vref, RX VrefLevel [Byte0]: 44
7859 19:57:12.392252 [Byte1]: 44
7860 19:57:12.396779
7861 19:57:12.396860 Set Vref, RX VrefLevel [Byte0]: 45
7862 19:57:12.399843 [Byte1]: 45
7863 19:57:12.404856
7864 19:57:12.404936 Set Vref, RX VrefLevel [Byte0]: 46
7865 19:57:12.407429 [Byte1]: 46
7866 19:57:12.411842
7867 19:57:12.411923 Set Vref, RX VrefLevel [Byte0]: 47
7868 19:57:12.415115 [Byte1]: 47
7869 19:57:12.419503
7870 19:57:12.419585 Set Vref, RX VrefLevel [Byte0]: 48
7871 19:57:12.422794 [Byte1]: 48
7872 19:57:12.427191
7873 19:57:12.427272 Set Vref, RX VrefLevel [Byte0]: 49
7874 19:57:12.430494 [Byte1]: 49
7875 19:57:12.435027
7876 19:57:12.435107 Set Vref, RX VrefLevel [Byte0]: 50
7877 19:57:12.438340 [Byte1]: 50
7878 19:57:12.442295
7879 19:57:12.442375 Set Vref, RX VrefLevel [Byte0]: 51
7880 19:57:12.445812 [Byte1]: 51
7881 19:57:12.449992
7882 19:57:12.450073 Set Vref, RX VrefLevel [Byte0]: 52
7883 19:57:12.453158 [Byte1]: 52
7884 19:57:12.457465
7885 19:57:12.457545 Set Vref, RX VrefLevel [Byte0]: 53
7886 19:57:12.460853 [Byte1]: 53
7887 19:57:12.465325
7888 19:57:12.465441 Set Vref, RX VrefLevel [Byte0]: 54
7889 19:57:12.468415 [Byte1]: 54
7890 19:57:12.473064
7891 19:57:12.473145 Set Vref, RX VrefLevel [Byte0]: 55
7892 19:57:12.476140 [Byte1]: 55
7893 19:57:12.480310
7894 19:57:12.480391 Set Vref, RX VrefLevel [Byte0]: 56
7895 19:57:12.483458 [Byte1]: 56
7896 19:57:12.488077
7897 19:57:12.488158 Set Vref, RX VrefLevel [Byte0]: 57
7898 19:57:12.491256 [Byte1]: 57
7899 19:57:12.495512
7900 19:57:12.495592 Set Vref, RX VrefLevel [Byte0]: 58
7901 19:57:12.499014 [Byte1]: 58
7902 19:57:12.503539
7903 19:57:12.503639 Set Vref, RX VrefLevel [Byte0]: 59
7904 19:57:12.506459 [Byte1]: 59
7905 19:57:12.511330
7906 19:57:12.511452 Set Vref, RX VrefLevel [Byte0]: 60
7907 19:57:12.514167 [Byte1]: 60
7908 19:57:12.518294
7909 19:57:12.518388 Set Vref, RX VrefLevel [Byte0]: 61
7910 19:57:12.521787 [Byte1]: 61
7911 19:57:12.526401
7912 19:57:12.526481 Set Vref, RX VrefLevel [Byte0]: 62
7913 19:57:12.529345 [Byte1]: 62
7914 19:57:12.534012
7915 19:57:12.534091 Set Vref, RX VrefLevel [Byte0]: 63
7916 19:57:12.537360 [Byte1]: 63
7917 19:57:12.541663
7918 19:57:12.541744 Set Vref, RX VrefLevel [Byte0]: 64
7919 19:57:12.544652 [Byte1]: 64
7920 19:57:12.549030
7921 19:57:12.549111 Set Vref, RX VrefLevel [Byte0]: 65
7922 19:57:12.552287 [Byte1]: 65
7923 19:57:12.556742
7924 19:57:12.556822 Set Vref, RX VrefLevel [Byte0]: 66
7925 19:57:12.560055 [Byte1]: 66
7926 19:57:12.564576
7927 19:57:12.564657 Set Vref, RX VrefLevel [Byte0]: 67
7928 19:57:12.567382 [Byte1]: 67
7929 19:57:12.571911
7930 19:57:12.572025 Set Vref, RX VrefLevel [Byte0]: 68
7931 19:57:12.575254 [Byte1]: 68
7932 19:57:12.579371
7933 19:57:12.579508 Set Vref, RX VrefLevel [Byte0]: 69
7934 19:57:12.582551 [Byte1]: 69
7935 19:57:12.586970
7936 19:57:12.587094 Set Vref, RX VrefLevel [Byte0]: 70
7937 19:57:12.590474 [Byte1]: 70
7938 19:57:12.594793
7939 19:57:12.594900 Set Vref, RX VrefLevel [Byte0]: 71
7940 19:57:12.597764 [Byte1]: 71
7941 19:57:12.602108
7942 19:57:12.602189 Set Vref, RX VrefLevel [Byte0]: 72
7943 19:57:12.605852 [Byte1]: 72
7944 19:57:12.609694
7945 19:57:12.609774 Set Vref, RX VrefLevel [Byte0]: 73
7946 19:57:12.613284 [Byte1]: 73
7947 19:57:12.617308
7948 19:57:12.617389 Set Vref, RX VrefLevel [Byte0]: 74
7949 19:57:12.620961 [Byte1]: 74
7950 19:57:12.625351
7951 19:57:12.625431 Set Vref, RX VrefLevel [Byte0]: 75
7952 19:57:12.628556 [Byte1]: 75
7953 19:57:12.632596
7954 19:57:12.632676 Set Vref, RX VrefLevel [Byte0]: 76
7955 19:57:12.635937 [Byte1]: 76
7956 19:57:12.640344
7957 19:57:12.640425 Final RX Vref Byte 0 = 65 to rank0
7958 19:57:12.643714 Final RX Vref Byte 1 = 61 to rank0
7959 19:57:12.647204 Final RX Vref Byte 0 = 65 to rank1
7960 19:57:12.650287 Final RX Vref Byte 1 = 61 to rank1==
7961 19:57:12.654269 Dram Type= 6, Freq= 0, CH_0, rank 0
7962 19:57:12.660334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7963 19:57:12.660416 ==
7964 19:57:12.660480 DQS Delay:
7965 19:57:12.660539 DQS0 = 0, DQS1 = 0
7966 19:57:12.663632 DQM Delay:
7967 19:57:12.663712 DQM0 = 126, DQM1 = 119
7968 19:57:12.666932 DQ Delay:
7969 19:57:12.670351 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7970 19:57:12.673558 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7971 19:57:12.677309 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7972 19:57:12.680541 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =126
7973 19:57:12.680621
7974 19:57:12.680686
7975 19:57:12.680745
7976 19:57:12.683738 [DramC_TX_OE_Calibration] TA2
7977 19:57:12.687028 Original DQ_B0 (3 6) =30, OEN = 27
7978 19:57:12.690201 Original DQ_B1 (3 6) =30, OEN = 27
7979 19:57:12.693978 24, 0x0, End_B0=24 End_B1=24
7980 19:57:12.694060 25, 0x0, End_B0=25 End_B1=25
7981 19:57:12.696902 26, 0x0, End_B0=26 End_B1=26
7982 19:57:12.700369 27, 0x0, End_B0=27 End_B1=27
7983 19:57:12.703654 28, 0x0, End_B0=28 End_B1=28
7984 19:57:12.703735 29, 0x0, End_B0=29 End_B1=29
7985 19:57:12.706760 30, 0x0, End_B0=30 End_B1=30
7986 19:57:12.710360 31, 0x4141, End_B0=30 End_B1=30
7987 19:57:12.713218 Byte0 end_step=30 best_step=27
7988 19:57:12.716641 Byte1 end_step=30 best_step=27
7989 19:57:12.719971 Byte0 TX OE(2T, 0.5T) = (3, 3)
7990 19:57:12.723600 Byte1 TX OE(2T, 0.5T) = (3, 3)
7991 19:57:12.723681
7992 19:57:12.723745
7993 19:57:12.730296 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
7994 19:57:12.733166 CH0 RK0: MR19=303, MR18=1111
7995 19:57:12.739695 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=22, DEC=15
7996 19:57:12.739799
7997 19:57:12.742986 ----->DramcWriteLeveling(PI) begin...
7998 19:57:12.743068 ==
7999 19:57:12.746536 Dram Type= 6, Freq= 0, CH_0, rank 1
8000 19:57:12.749935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 19:57:12.750017 ==
8002 19:57:12.753088 Write leveling (Byte 0): 34 => 34
8003 19:57:12.756421 Write leveling (Byte 1): 28 => 28
8004 19:57:12.759495 DramcWriteLeveling(PI) end<-----
8005 19:57:12.759577
8006 19:57:12.759641 ==
8007 19:57:12.763258 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 19:57:12.766338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 19:57:12.766421 ==
8010 19:57:12.770037 [Gating] SW mode calibration
8011 19:57:12.776299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8012 19:57:12.782785 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8013 19:57:12.786187 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 19:57:12.789492 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 19:57:12.796550 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 19:57:12.799527 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8017 19:57:12.803136 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8018 19:57:12.809840 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8019 19:57:12.812980 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 19:57:12.816138 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 19:57:12.823108 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 19:57:12.826526 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 19:57:12.829512 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8024 19:57:12.836175 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
8025 19:57:12.839590 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8026 19:57:12.842718 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8027 19:57:12.849492 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 19:57:12.852705 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 19:57:12.855955 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 19:57:12.862724 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 19:57:12.866110 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8032 19:57:12.869128 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8033 19:57:12.876283 1 6 16 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8034 19:57:12.879222 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 19:57:12.882471 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 19:57:12.889000 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 19:57:12.892270 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 19:57:12.896014 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 19:57:12.902545 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 19:57:12.905965 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8041 19:57:12.909007 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8042 19:57:12.915667 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8043 19:57:12.918831 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8044 19:57:12.922510 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 19:57:12.928698 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 19:57:12.932093 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 19:57:12.935910 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 19:57:12.941912 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 19:57:12.945689 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 19:57:12.948703 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 19:57:12.955167 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 19:57:12.959024 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 19:57:12.962130 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 19:57:12.965262 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 19:57:12.972003 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8056 19:57:12.975277 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8057 19:57:12.978601 Total UI for P1: 0, mck2ui 16
8058 19:57:12.981905 best dqsien dly found for B0: ( 1, 9, 8)
8059 19:57:12.985278 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8060 19:57:12.991907 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8061 19:57:12.995244 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 19:57:12.998280 Total UI for P1: 0, mck2ui 16
8063 19:57:13.001645 best dqsien dly found for B1: ( 1, 9, 18)
8064 19:57:13.004810 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8065 19:57:13.008211 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8066 19:57:13.008293
8067 19:57:13.011668 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8068 19:57:13.018380 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8069 19:57:13.018462 [Gating] SW calibration Done
8070 19:57:13.018527 ==
8071 19:57:13.021949 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 19:57:13.028199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 19:57:13.028285 ==
8074 19:57:13.028350 RX Vref Scan: 0
8075 19:57:13.028411
8076 19:57:13.031586 RX Vref 0 -> 0, step: 1
8077 19:57:13.031668
8078 19:57:13.034807 RX Delay 0 -> 252, step: 8
8079 19:57:13.038159 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8080 19:57:13.041236 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8081 19:57:13.045125 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8082 19:57:13.051280 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8083 19:57:13.054858 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8084 19:57:13.058029 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8085 19:57:13.061170 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8086 19:57:13.064675 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8087 19:57:13.071097 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8088 19:57:13.074384 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8089 19:57:13.077875 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8090 19:57:13.081154 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8091 19:57:13.084623 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8092 19:57:13.091667 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8093 19:57:13.094168 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8094 19:57:13.097437 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8095 19:57:13.097519 ==
8096 19:57:13.100895 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 19:57:13.104140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 19:57:13.107014 ==
8099 19:57:13.107095 DQS Delay:
8100 19:57:13.107159 DQS0 = 0, DQS1 = 0
8101 19:57:13.110713 DQM Delay:
8102 19:57:13.110793 DQM0 = 127, DQM1 = 121
8103 19:57:13.114077 DQ Delay:
8104 19:57:13.117166 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8105 19:57:13.120696 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8106 19:57:13.123575 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8107 19:57:13.127270 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8108 19:57:13.127376
8109 19:57:13.127481
8110 19:57:13.127541 ==
8111 19:57:13.130425 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 19:57:13.133571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 19:57:13.133678 ==
8114 19:57:13.133750
8115 19:57:13.137242
8116 19:57:13.137330 TX Vref Scan disable
8117 19:57:13.140416 == TX Byte 0 ==
8118 19:57:13.143550 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8119 19:57:13.147117 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8120 19:57:13.150570 == TX Byte 1 ==
8121 19:57:13.153829 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8122 19:57:13.156875 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8123 19:57:13.156956 ==
8124 19:57:13.160298 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 19:57:13.166859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 19:57:13.166944 ==
8127 19:57:13.179314
8128 19:57:13.182972 TX Vref early break, caculate TX vref
8129 19:57:13.185777 TX Vref=16, minBit 9, minWin=21, winSum=364
8130 19:57:13.189076 TX Vref=18, minBit 0, minWin=22, winSum=371
8131 19:57:13.192390 TX Vref=20, minBit 8, minWin=22, winSum=377
8132 19:57:13.195703 TX Vref=22, minBit 9, minWin=23, winSum=393
8133 19:57:13.199042 TX Vref=24, minBit 1, minWin=24, winSum=397
8134 19:57:13.205640 TX Vref=26, minBit 8, minWin=24, winSum=407
8135 19:57:13.208879 TX Vref=28, minBit 8, minWin=24, winSum=409
8136 19:57:13.213010 TX Vref=30, minBit 8, minWin=24, winSum=407
8137 19:57:13.215572 TX Vref=32, minBit 8, minWin=22, winSum=395
8138 19:57:13.219306 TX Vref=34, minBit 8, minWin=22, winSum=387
8139 19:57:13.225765 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 28
8140 19:57:13.225848
8141 19:57:13.228967 Final TX Range 0 Vref 28
8142 19:57:13.229041
8143 19:57:13.229101 ==
8144 19:57:13.232710 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 19:57:13.235656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 19:57:13.235730 ==
8147 19:57:13.235792
8148 19:57:13.235850
8149 19:57:13.238973 TX Vref Scan disable
8150 19:57:13.245385 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8151 19:57:13.245468 == TX Byte 0 ==
8152 19:57:13.248871 u2DelayCellOfst[0]=11 cells (3 PI)
8153 19:57:13.252449 u2DelayCellOfst[1]=15 cells (4 PI)
8154 19:57:13.255413 u2DelayCellOfst[2]=11 cells (3 PI)
8155 19:57:13.258999 u2DelayCellOfst[3]=11 cells (3 PI)
8156 19:57:13.262198 u2DelayCellOfst[4]=7 cells (2 PI)
8157 19:57:13.265650 u2DelayCellOfst[5]=0 cells (0 PI)
8158 19:57:13.268709 u2DelayCellOfst[6]=18 cells (5 PI)
8159 19:57:13.272060 u2DelayCellOfst[7]=15 cells (4 PI)
8160 19:57:13.275365 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8161 19:57:13.278563 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8162 19:57:13.281932 == TX Byte 1 ==
8163 19:57:13.282013 u2DelayCellOfst[8]=0 cells (0 PI)
8164 19:57:13.285306 u2DelayCellOfst[9]=3 cells (1 PI)
8165 19:57:13.288727 u2DelayCellOfst[10]=7 cells (2 PI)
8166 19:57:13.292046 u2DelayCellOfst[11]=7 cells (2 PI)
8167 19:57:13.295228 u2DelayCellOfst[12]=15 cells (4 PI)
8168 19:57:13.298494 u2DelayCellOfst[13]=15 cells (4 PI)
8169 19:57:13.301920 u2DelayCellOfst[14]=15 cells (4 PI)
8170 19:57:13.305262 u2DelayCellOfst[15]=15 cells (4 PI)
8171 19:57:13.308802 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8172 19:57:13.315322 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8173 19:57:13.315461 DramC Write-DBI on
8174 19:57:13.315527 ==
8175 19:57:13.318868 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 19:57:13.321992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 19:57:13.324920 ==
8178 19:57:13.325001
8179 19:57:13.325065
8180 19:57:13.325124 TX Vref Scan disable
8181 19:57:13.329003 == TX Byte 0 ==
8182 19:57:13.331883 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8183 19:57:13.335659 == TX Byte 1 ==
8184 19:57:13.338253 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8185 19:57:13.341629 DramC Write-DBI off
8186 19:57:13.341710
8187 19:57:13.341774 [DATLAT]
8188 19:57:13.341834 Freq=1600, CH0 RK1
8189 19:57:13.341892
8190 19:57:13.344994 DATLAT Default: 0xf
8191 19:57:13.348660 0, 0xFFFF, sum = 0
8192 19:57:13.348742 1, 0xFFFF, sum = 0
8193 19:57:13.351818 2, 0xFFFF, sum = 0
8194 19:57:13.351901 3, 0xFFFF, sum = 0
8195 19:57:13.355005 4, 0xFFFF, sum = 0
8196 19:57:13.355087 5, 0xFFFF, sum = 0
8197 19:57:13.358445 6, 0xFFFF, sum = 0
8198 19:57:13.358527 7, 0xFFFF, sum = 0
8199 19:57:13.361809 8, 0xFFFF, sum = 0
8200 19:57:13.361891 9, 0xFFFF, sum = 0
8201 19:57:13.364786 10, 0xFFFF, sum = 0
8202 19:57:13.364868 11, 0xFFFF, sum = 0
8203 19:57:13.368098 12, 0xFFFF, sum = 0
8204 19:57:13.368180 13, 0xCFFF, sum = 0
8205 19:57:13.371997 14, 0x0, sum = 1
8206 19:57:13.372080 15, 0x0, sum = 2
8207 19:57:13.375077 16, 0x0, sum = 3
8208 19:57:13.375191 17, 0x0, sum = 4
8209 19:57:13.378340 best_step = 15
8210 19:57:13.378420
8211 19:57:13.378484 ==
8212 19:57:13.381688 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 19:57:13.384936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 19:57:13.385017 ==
8215 19:57:13.388154 RX Vref Scan: 0
8216 19:57:13.388235
8217 19:57:13.388300 RX Vref 0 -> 0, step: 1
8218 19:57:13.388361
8219 19:57:13.391634 RX Delay 3 -> 252, step: 4
8220 19:57:13.394888 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
8221 19:57:13.401523 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8222 19:57:13.405049 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8223 19:57:13.408778 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8224 19:57:13.411374 iDelay=195, Bit 4, Center 124 (71 ~ 178) 108
8225 19:57:13.414677 iDelay=195, Bit 5, Center 112 (59 ~ 166) 108
8226 19:57:13.421226 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8227 19:57:13.424633 iDelay=195, Bit 7, Center 136 (79 ~ 194) 116
8228 19:57:13.427984 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8229 19:57:13.431434 iDelay=195, Bit 9, Center 104 (47 ~ 162) 116
8230 19:57:13.434620 iDelay=195, Bit 10, Center 118 (63 ~ 174) 112
8231 19:57:13.441014 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8232 19:57:13.445207 iDelay=195, Bit 12, Center 124 (67 ~ 182) 116
8233 19:57:13.447788 iDelay=195, Bit 13, Center 122 (67 ~ 178) 112
8234 19:57:13.451022 iDelay=195, Bit 14, Center 128 (71 ~ 186) 116
8235 19:57:13.457936 iDelay=195, Bit 15, Center 124 (67 ~ 182) 116
8236 19:57:13.458018 ==
8237 19:57:13.461166 Dram Type= 6, Freq= 0, CH_0, rank 1
8238 19:57:13.464763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 19:57:13.464845 ==
8240 19:57:13.464910 DQS Delay:
8241 19:57:13.467909 DQS0 = 0, DQS1 = 0
8242 19:57:13.467990 DQM Delay:
8243 19:57:13.471087 DQM0 = 125, DQM1 = 117
8244 19:57:13.471168 DQ Delay:
8245 19:57:13.474869 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8246 19:57:13.477649 DQ4 =124, DQ5 =112, DQ6 =136, DQ7 =136
8247 19:57:13.480985 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8248 19:57:13.484657 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8249 19:57:13.484738
8250 19:57:13.484802
8251 19:57:13.484862
8252 19:57:13.488116 [DramC_TX_OE_Calibration] TA2
8253 19:57:13.491138 Original DQ_B0 (3 6) =30, OEN = 27
8254 19:57:13.494469 Original DQ_B1 (3 6) =30, OEN = 27
8255 19:57:13.497986 24, 0x0, End_B0=24 End_B1=24
8256 19:57:13.500989 25, 0x0, End_B0=25 End_B1=25
8257 19:57:13.504527 26, 0x0, End_B0=26 End_B1=26
8258 19:57:13.504630 27, 0x0, End_B0=27 End_B1=27
8259 19:57:13.508076 28, 0x0, End_B0=28 End_B1=28
8260 19:57:13.511224 29, 0x0, End_B0=29 End_B1=29
8261 19:57:13.514071 30, 0x0, End_B0=30 End_B1=30
8262 19:57:13.517242 31, 0x4141, End_B0=30 End_B1=30
8263 19:57:13.517324 Byte0 end_step=30 best_step=27
8264 19:57:13.520924 Byte1 end_step=30 best_step=27
8265 19:57:13.523969 Byte0 TX OE(2T, 0.5T) = (3, 3)
8266 19:57:13.527773 Byte1 TX OE(2T, 0.5T) = (3, 3)
8267 19:57:13.527853
8268 19:57:13.527919
8269 19:57:13.534603 [DQSOSCAuto] RK1, (LSB)MR18= 0x2512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8270 19:57:13.537461 CH0 RK1: MR19=303, MR18=2512
8271 19:57:13.543941 CH0_RK1: MR19=0x303, MR18=0x2512, DQSOSC=391, MR23=63, INC=24, DEC=16
8272 19:57:13.547224 [RxdqsGatingPostProcess] freq 1600
8273 19:57:13.553846 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8274 19:57:13.557070 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 19:57:13.557152 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 19:57:13.560476 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 19:57:13.564083 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 19:57:13.567298 best DQS0 dly(2T, 0.5T) = (1, 1)
8279 19:57:13.570539 best DQS1 dly(2T, 0.5T) = (1, 1)
8280 19:57:13.573530 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8281 19:57:13.577156 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8282 19:57:13.580387 Pre-setting of DQS Precalculation
8283 19:57:13.583667 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8284 19:57:13.586997 ==
8285 19:57:13.590437 Dram Type= 6, Freq= 0, CH_1, rank 0
8286 19:57:13.593925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 19:57:13.594015 ==
8288 19:57:13.597326 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8289 19:57:13.603953 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8290 19:57:13.607021 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8291 19:57:13.613492 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8292 19:57:13.621809 [CA 0] Center 41 (12~71) winsize 60
8293 19:57:13.625380 [CA 1] Center 42 (12~72) winsize 61
8294 19:57:13.628456 [CA 2] Center 37 (9~66) winsize 58
8295 19:57:13.631590 [CA 3] Center 36 (7~66) winsize 60
8296 19:57:13.635160 [CA 4] Center 37 (8~66) winsize 59
8297 19:57:13.638282 [CA 5] Center 36 (7~66) winsize 60
8298 19:57:13.638378
8299 19:57:13.641785 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8300 19:57:13.641865
8301 19:57:13.645067 [CATrainingPosCal] consider 1 rank data
8302 19:57:13.648327 u2DelayCellTimex100 = 258/100 ps
8303 19:57:13.651343 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8304 19:57:13.658447 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8305 19:57:13.661785 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8306 19:57:13.665347 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8307 19:57:13.668611 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8308 19:57:13.671610 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8309 19:57:13.671690
8310 19:57:13.675155 CA PerBit enable=1, Macro0, CA PI delay=36
8311 19:57:13.675263
8312 19:57:13.678818 [CBTSetCACLKResult] CA Dly = 36
8313 19:57:13.681664 CS Dly: 9 (0~40)
8314 19:57:13.684641 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8315 19:57:13.687895 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8316 19:57:13.688007 ==
8317 19:57:13.691627 Dram Type= 6, Freq= 0, CH_1, rank 1
8318 19:57:13.694798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 19:57:13.697820 ==
8320 19:57:13.701145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8321 19:57:13.704504 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8322 19:57:13.710994 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8323 19:57:13.714502 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8324 19:57:13.725044 [CA 0] Center 42 (13~72) winsize 60
8325 19:57:13.728246 [CA 1] Center 42 (13~72) winsize 60
8326 19:57:13.731323 [CA 2] Center 38 (9~67) winsize 59
8327 19:57:13.734633 [CA 3] Center 36 (7~66) winsize 60
8328 19:57:13.737765 [CA 4] Center 38 (8~68) winsize 61
8329 19:57:13.741348 [CA 5] Center 36 (6~67) winsize 62
8330 19:57:13.741428
8331 19:57:13.744669 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8332 19:57:13.744750
8333 19:57:13.748317 [CATrainingPosCal] consider 2 rank data
8334 19:57:13.751599 u2DelayCellTimex100 = 258/100 ps
8335 19:57:13.754496 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8336 19:57:13.761333 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8337 19:57:13.764707 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8338 19:57:13.768135 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8339 19:57:13.771317 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8340 19:57:13.774439 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8341 19:57:13.774520
8342 19:57:13.777954 CA PerBit enable=1, Macro0, CA PI delay=36
8343 19:57:13.778033
8344 19:57:13.780763 [CBTSetCACLKResult] CA Dly = 36
8345 19:57:13.784082 CS Dly: 11 (0~44)
8346 19:57:13.787670 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8347 19:57:13.790427 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8348 19:57:13.790507
8349 19:57:13.794529 ----->DramcWriteLeveling(PI) begin...
8350 19:57:13.794610 ==
8351 19:57:13.797496 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 19:57:13.803741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 19:57:13.803822 ==
8354 19:57:13.807168 Write leveling (Byte 0): 24 => 24
8355 19:57:13.810342 Write leveling (Byte 1): 28 => 28
8356 19:57:13.810423 DramcWriteLeveling(PI) end<-----
8357 19:57:13.813725
8358 19:57:13.813806 ==
8359 19:57:13.817180 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 19:57:13.820501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 19:57:13.820584 ==
8362 19:57:13.824259 [Gating] SW mode calibration
8363 19:57:13.830395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8364 19:57:13.833754 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8365 19:57:13.840203 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 19:57:13.843849 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 19:57:13.847194 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 19:57:13.853593 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 19:57:13.857179 1 4 16 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8370 19:57:13.860408 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 19:57:13.866812 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 19:57:13.870465 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 19:57:13.873230 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 19:57:13.880362 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 19:57:13.883748 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 19:57:13.886529 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8377 19:57:13.893259 1 5 16 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0)
8378 19:57:13.896942 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8379 19:57:13.900258 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 19:57:13.906333 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 19:57:13.909838 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 19:57:13.913137 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 19:57:13.919989 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 19:57:13.923368 1 6 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8385 19:57:13.926948 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 19:57:13.933041 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 19:57:13.936372 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 19:57:13.940018 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 19:57:13.946276 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 19:57:13.949468 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 19:57:13.952991 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 19:57:13.959902 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8393 19:57:13.963040 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8394 19:57:13.966022 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8395 19:57:13.973222 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 19:57:13.976499 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 19:57:13.979988 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 19:57:13.986062 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 19:57:13.989494 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 19:57:13.992705 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 19:57:13.996040 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 19:57:14.002801 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 19:57:14.006081 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 19:57:14.009452 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 19:57:14.015905 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 19:57:14.019307 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 19:57:14.023033 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 19:57:14.029323 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 19:57:14.033038 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8410 19:57:14.036254 Total UI for P1: 0, mck2ui 16
8411 19:57:14.039378 best dqsien dly found for B1: ( 1, 9, 14)
8412 19:57:14.043174 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 19:57:14.045842 Total UI for P1: 0, mck2ui 16
8414 19:57:14.049135 best dqsien dly found for B0: ( 1, 9, 16)
8415 19:57:14.052483 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8416 19:57:14.055880 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8417 19:57:14.055988
8418 19:57:14.062664 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8419 19:57:14.065946 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8420 19:57:14.069391 [Gating] SW calibration Done
8421 19:57:14.069475 ==
8422 19:57:14.072319 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 19:57:14.075890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 19:57:14.075999 ==
8425 19:57:14.076101 RX Vref Scan: 0
8426 19:57:14.076202
8427 19:57:14.079061 RX Vref 0 -> 0, step: 1
8428 19:57:14.079163
8429 19:57:14.082303 RX Delay 0 -> 252, step: 8
8430 19:57:14.085633 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8431 19:57:14.089083 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8432 19:57:14.095634 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8433 19:57:14.098949 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8434 19:57:14.102335 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8435 19:57:14.105636 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8436 19:57:14.109160 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8437 19:57:14.115593 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8438 19:57:14.118881 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8439 19:57:14.122228 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8440 19:57:14.125510 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8441 19:57:14.128988 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8442 19:57:14.135823 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8443 19:57:14.139082 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8444 19:57:14.142114 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8445 19:57:14.145268 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8446 19:57:14.145352 ==
8447 19:57:14.148953 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 19:57:14.155265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 19:57:14.155374 ==
8450 19:57:14.155464 DQS Delay:
8451 19:57:14.155544 DQS0 = 0, DQS1 = 0
8452 19:57:14.158979 DQM Delay:
8453 19:57:14.159086 DQM0 = 132, DQM1 = 126
8454 19:57:14.162236 DQ Delay:
8455 19:57:14.165422 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8456 19:57:14.168833 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8457 19:57:14.172320 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8458 19:57:14.175256 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8459 19:57:14.175363
8460 19:57:14.175488
8461 19:57:14.175568 ==
8462 19:57:14.178892 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 19:57:14.181708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 19:57:14.185399 ==
8465 19:57:14.185482
8466 19:57:14.185565
8467 19:57:14.185645 TX Vref Scan disable
8468 19:57:14.188390 == TX Byte 0 ==
8469 19:57:14.192166 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8470 19:57:14.195468 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8471 19:57:14.198724 == TX Byte 1 ==
8472 19:57:14.201699 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8473 19:57:14.205099 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8474 19:57:14.208542 ==
8475 19:57:14.208625 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 19:57:14.215171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 19:57:14.215254 ==
8478 19:57:14.227483
8479 19:57:14.230387 TX Vref early break, caculate TX vref
8480 19:57:14.233599 TX Vref=16, minBit 12, minWin=21, winSum=361
8481 19:57:14.236948 TX Vref=18, minBit 5, minWin=22, winSum=368
8482 19:57:14.240210 TX Vref=20, minBit 11, minWin=22, winSum=380
8483 19:57:14.243597 TX Vref=22, minBit 11, minWin=23, winSum=390
8484 19:57:14.247138 TX Vref=24, minBit 5, minWin=24, winSum=401
8485 19:57:14.254051 TX Vref=26, minBit 10, minWin=24, winSum=409
8486 19:57:14.257481 TX Vref=28, minBit 1, minWin=24, winSum=415
8487 19:57:14.260314 TX Vref=30, minBit 0, minWin=24, winSum=411
8488 19:57:14.264043 TX Vref=32, minBit 0, minWin=24, winSum=403
8489 19:57:14.267247 TX Vref=34, minBit 0, minWin=23, winSum=393
8490 19:57:14.273703 [TxChooseVref] Worse bit 1, Min win 24, Win sum 415, Final Vref 28
8491 19:57:14.273786
8492 19:57:14.277003 Final TX Range 0 Vref 28
8493 19:57:14.277087
8494 19:57:14.277171 ==
8495 19:57:14.280274 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 19:57:14.283838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 19:57:14.283922 ==
8498 19:57:14.284005
8499 19:57:14.284084
8500 19:57:14.287296 TX Vref Scan disable
8501 19:57:14.293528 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8502 19:57:14.293612 == TX Byte 0 ==
8503 19:57:14.296896 u2DelayCellOfst[0]=22 cells (6 PI)
8504 19:57:14.300120 u2DelayCellOfst[1]=18 cells (5 PI)
8505 19:57:14.303664 u2DelayCellOfst[2]=0 cells (0 PI)
8506 19:57:14.306998 u2DelayCellOfst[3]=7 cells (2 PI)
8507 19:57:14.310597 u2DelayCellOfst[4]=11 cells (3 PI)
8508 19:57:14.313777 u2DelayCellOfst[5]=26 cells (7 PI)
8509 19:57:14.316940 u2DelayCellOfst[6]=22 cells (6 PI)
8510 19:57:14.320274 u2DelayCellOfst[7]=7 cells (2 PI)
8511 19:57:14.323465 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8512 19:57:14.326872 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8513 19:57:14.329994 == TX Byte 1 ==
8514 19:57:14.330079 u2DelayCellOfst[8]=0 cells (0 PI)
8515 19:57:14.333756 u2DelayCellOfst[9]=7 cells (2 PI)
8516 19:57:14.336826 u2DelayCellOfst[10]=15 cells (4 PI)
8517 19:57:14.340104 u2DelayCellOfst[11]=11 cells (3 PI)
8518 19:57:14.343290 u2DelayCellOfst[12]=18 cells (5 PI)
8519 19:57:14.346663 u2DelayCellOfst[13]=22 cells (6 PI)
8520 19:57:14.350012 u2DelayCellOfst[14]=22 cells (6 PI)
8521 19:57:14.353285 u2DelayCellOfst[15]=22 cells (6 PI)
8522 19:57:14.356566 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8523 19:57:14.363588 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8524 19:57:14.363672 DramC Write-DBI on
8525 19:57:14.363756 ==
8526 19:57:14.366700 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 19:57:14.373117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 19:57:14.373201 ==
8529 19:57:14.373286
8530 19:57:14.373365
8531 19:57:14.373442 TX Vref Scan disable
8532 19:57:14.376634 == TX Byte 0 ==
8533 19:57:14.380615 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8534 19:57:14.383279 == TX Byte 1 ==
8535 19:57:14.387039 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8536 19:57:14.390262 DramC Write-DBI off
8537 19:57:14.390346
8538 19:57:14.390429 [DATLAT]
8539 19:57:14.390509 Freq=1600, CH1 RK0
8540 19:57:14.390587
8541 19:57:14.393689 DATLAT Default: 0xf
8542 19:57:14.396574 0, 0xFFFF, sum = 0
8543 19:57:14.396657 1, 0xFFFF, sum = 0
8544 19:57:14.400274 2, 0xFFFF, sum = 0
8545 19:57:14.400357 3, 0xFFFF, sum = 0
8546 19:57:14.403289 4, 0xFFFF, sum = 0
8547 19:57:14.403374 5, 0xFFFF, sum = 0
8548 19:57:14.406482 6, 0xFFFF, sum = 0
8549 19:57:14.406567 7, 0xFFFF, sum = 0
8550 19:57:14.409609 8, 0xFFFF, sum = 0
8551 19:57:14.409693 9, 0xFFFF, sum = 0
8552 19:57:14.413048 10, 0xFFFF, sum = 0
8553 19:57:14.413132 11, 0xFFFF, sum = 0
8554 19:57:14.416149 12, 0xFFFF, sum = 0
8555 19:57:14.416237 13, 0x8FFF, sum = 0
8556 19:57:14.419944 14, 0x0, sum = 1
8557 19:57:14.420027 15, 0x0, sum = 2
8558 19:57:14.422905 16, 0x0, sum = 3
8559 19:57:14.422987 17, 0x0, sum = 4
8560 19:57:14.426167 best_step = 15
8561 19:57:14.426248
8562 19:57:14.426314 ==
8563 19:57:14.429555 Dram Type= 6, Freq= 0, CH_1, rank 0
8564 19:57:14.432779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8565 19:57:14.432861 ==
8566 19:57:14.435969 RX Vref Scan: 1
8567 19:57:14.436050
8568 19:57:14.436115 Set Vref Range= 24 -> 127
8569 19:57:14.436175
8570 19:57:14.439520 RX Vref 24 -> 127, step: 1
8571 19:57:14.439601
8572 19:57:14.442873 RX Delay 11 -> 252, step: 4
8573 19:57:14.442954
8574 19:57:14.446025 Set Vref, RX VrefLevel [Byte0]: 24
8575 19:57:14.449466 [Byte1]: 24
8576 19:57:14.449547
8577 19:57:14.452788 Set Vref, RX VrefLevel [Byte0]: 25
8578 19:57:14.456486 [Byte1]: 25
8579 19:57:14.459530
8580 19:57:14.459611 Set Vref, RX VrefLevel [Byte0]: 26
8581 19:57:14.462878 [Byte1]: 26
8582 19:57:14.467248
8583 19:57:14.467358 Set Vref, RX VrefLevel [Byte0]: 27
8584 19:57:14.470308 [Byte1]: 27
8585 19:57:14.475237
8586 19:57:14.475345 Set Vref, RX VrefLevel [Byte0]: 28
8587 19:57:14.478178 [Byte1]: 28
8588 19:57:14.482551
8589 19:57:14.482633 Set Vref, RX VrefLevel [Byte0]: 29
8590 19:57:14.485666 [Byte1]: 29
8591 19:57:14.489962
8592 19:57:14.490043 Set Vref, RX VrefLevel [Byte0]: 30
8593 19:57:14.493388 [Byte1]: 30
8594 19:57:14.497717
8595 19:57:14.497798 Set Vref, RX VrefLevel [Byte0]: 31
8596 19:57:14.501373 [Byte1]: 31
8597 19:57:14.505264
8598 19:57:14.505349 Set Vref, RX VrefLevel [Byte0]: 32
8599 19:57:14.508542 [Byte1]: 32
8600 19:57:14.513197
8601 19:57:14.513278 Set Vref, RX VrefLevel [Byte0]: 33
8602 19:57:14.516357 [Byte1]: 33
8603 19:57:14.520556
8604 19:57:14.520637 Set Vref, RX VrefLevel [Byte0]: 34
8605 19:57:14.523941 [Byte1]: 34
8606 19:57:14.528426
8607 19:57:14.528507 Set Vref, RX VrefLevel [Byte0]: 35
8608 19:57:14.531502 [Byte1]: 35
8609 19:57:14.535871
8610 19:57:14.535952 Set Vref, RX VrefLevel [Byte0]: 36
8611 19:57:14.539075 [Byte1]: 36
8612 19:57:14.543311
8613 19:57:14.543433 Set Vref, RX VrefLevel [Byte0]: 37
8614 19:57:14.546526 [Byte1]: 37
8615 19:57:14.550841
8616 19:57:14.550923 Set Vref, RX VrefLevel [Byte0]: 38
8617 19:57:14.554320 [Byte1]: 38
8618 19:57:14.558607
8619 19:57:14.558688 Set Vref, RX VrefLevel [Byte0]: 39
8620 19:57:14.562100 [Byte1]: 39
8621 19:57:14.566312
8622 19:57:14.566393 Set Vref, RX VrefLevel [Byte0]: 40
8623 19:57:14.569600 [Byte1]: 40
8624 19:57:14.573981
8625 19:57:14.574062 Set Vref, RX VrefLevel [Byte0]: 41
8626 19:57:14.577104 [Byte1]: 41
8627 19:57:14.581571
8628 19:57:14.581651 Set Vref, RX VrefLevel [Byte0]: 42
8629 19:57:14.585283 [Byte1]: 42
8630 19:57:14.589266
8631 19:57:14.589345 Set Vref, RX VrefLevel [Byte0]: 43
8632 19:57:14.592409 [Byte1]: 43
8633 19:57:14.596980
8634 19:57:14.597060 Set Vref, RX VrefLevel [Byte0]: 44
8635 19:57:14.600152 [Byte1]: 44
8636 19:57:14.604193
8637 19:57:14.604272 Set Vref, RX VrefLevel [Byte0]: 45
8638 19:57:14.608060 [Byte1]: 45
8639 19:57:14.612128
8640 19:57:14.612207 Set Vref, RX VrefLevel [Byte0]: 46
8641 19:57:14.614927 [Byte1]: 46
8642 19:57:14.619635
8643 19:57:14.619715 Set Vref, RX VrefLevel [Byte0]: 47
8644 19:57:14.622873 [Byte1]: 47
8645 19:57:14.626886
8646 19:57:14.626965 Set Vref, RX VrefLevel [Byte0]: 48
8647 19:57:14.630399 [Byte1]: 48
8648 19:57:14.634840
8649 19:57:14.634919 Set Vref, RX VrefLevel [Byte0]: 49
8650 19:57:14.637999 [Byte1]: 49
8651 19:57:14.642451
8652 19:57:14.642530 Set Vref, RX VrefLevel [Byte0]: 50
8653 19:57:14.645576 [Byte1]: 50
8654 19:57:14.649751
8655 19:57:14.649831 Set Vref, RX VrefLevel [Byte0]: 51
8656 19:57:14.653124 [Byte1]: 51
8657 19:57:14.657533
8658 19:57:14.657613 Set Vref, RX VrefLevel [Byte0]: 52
8659 19:57:14.660926 [Byte1]: 52
8660 19:57:14.665251
8661 19:57:14.665332 Set Vref, RX VrefLevel [Byte0]: 53
8662 19:57:14.668797 [Byte1]: 53
8663 19:57:14.672954
8664 19:57:14.673033 Set Vref, RX VrefLevel [Byte0]: 54
8665 19:57:14.676454 [Byte1]: 54
8666 19:57:14.680578
8667 19:57:14.680658 Set Vref, RX VrefLevel [Byte0]: 55
8668 19:57:14.683813 [Byte1]: 55
8669 19:57:14.687802
8670 19:57:14.687883 Set Vref, RX VrefLevel [Byte0]: 56
8671 19:57:14.691502 [Byte1]: 56
8672 19:57:14.695746
8673 19:57:14.695826 Set Vref, RX VrefLevel [Byte0]: 57
8674 19:57:14.698673 [Byte1]: 57
8675 19:57:14.703197
8676 19:57:14.703278 Set Vref, RX VrefLevel [Byte0]: 58
8677 19:57:14.706463 [Byte1]: 58
8678 19:57:14.710778
8679 19:57:14.710859 Set Vref, RX VrefLevel [Byte0]: 59
8680 19:57:14.714174 [Byte1]: 59
8681 19:57:14.718305
8682 19:57:14.718390 Set Vref, RX VrefLevel [Byte0]: 60
8683 19:57:14.721877 [Byte1]: 60
8684 19:57:14.725944
8685 19:57:14.726025 Set Vref, RX VrefLevel [Byte0]: 61
8686 19:57:14.729175 [Byte1]: 61
8687 19:57:14.733899
8688 19:57:14.733980 Set Vref, RX VrefLevel [Byte0]: 62
8689 19:57:14.736723 [Byte1]: 62
8690 19:57:14.741103
8691 19:57:14.741212 Set Vref, RX VrefLevel [Byte0]: 63
8692 19:57:14.744282 [Byte1]: 63
8693 19:57:14.748605
8694 19:57:14.748684 Set Vref, RX VrefLevel [Byte0]: 64
8695 19:57:14.752488 [Byte1]: 64
8696 19:57:14.756595
8697 19:57:14.756676 Set Vref, RX VrefLevel [Byte0]: 65
8698 19:57:14.760030 [Byte1]: 65
8699 19:57:14.763929
8700 19:57:14.764010 Set Vref, RX VrefLevel [Byte0]: 66
8701 19:57:14.767729 [Byte1]: 66
8702 19:57:14.771655
8703 19:57:14.771766 Set Vref, RX VrefLevel [Byte0]: 67
8704 19:57:14.774850 [Byte1]: 67
8705 19:57:14.779377
8706 19:57:14.779502 Set Vref, RX VrefLevel [Byte0]: 68
8707 19:57:14.782622 [Byte1]: 68
8708 19:57:14.787066
8709 19:57:14.787178 Set Vref, RX VrefLevel [Byte0]: 69
8710 19:57:14.790074 [Byte1]: 69
8711 19:57:14.794681
8712 19:57:14.794761 Final RX Vref Byte 0 = 58 to rank0
8713 19:57:14.798056 Final RX Vref Byte 1 = 54 to rank0
8714 19:57:14.801368 Final RX Vref Byte 0 = 58 to rank1
8715 19:57:14.804494 Final RX Vref Byte 1 = 54 to rank1==
8716 19:57:14.807821 Dram Type= 6, Freq= 0, CH_1, rank 0
8717 19:57:14.814603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 19:57:14.814684 ==
8719 19:57:14.814748 DQS Delay:
8720 19:57:14.814807 DQS0 = 0, DQS1 = 0
8721 19:57:14.817966 DQM Delay:
8722 19:57:14.818046 DQM0 = 131, DQM1 = 123
8723 19:57:14.821253 DQ Delay:
8724 19:57:14.824522 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8725 19:57:14.828033 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8726 19:57:14.830911 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8727 19:57:14.834070 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8728 19:57:14.834150
8729 19:57:14.834213
8730 19:57:14.834272
8731 19:57:14.837638 [DramC_TX_OE_Calibration] TA2
8732 19:57:14.840859 Original DQ_B0 (3 6) =30, OEN = 27
8733 19:57:14.843982 Original DQ_B1 (3 6) =30, OEN = 27
8734 19:57:14.847601 24, 0x0, End_B0=24 End_B1=24
8735 19:57:14.847683 25, 0x0, End_B0=25 End_B1=25
8736 19:57:14.850985 26, 0x0, End_B0=26 End_B1=26
8737 19:57:14.854164 27, 0x0, End_B0=27 End_B1=27
8738 19:57:14.857282 28, 0x0, End_B0=28 End_B1=28
8739 19:57:14.861000 29, 0x0, End_B0=29 End_B1=29
8740 19:57:14.861081 30, 0x0, End_B0=30 End_B1=30
8741 19:57:14.864012 31, 0x5151, End_B0=30 End_B1=30
8742 19:57:14.867905 Byte0 end_step=30 best_step=27
8743 19:57:14.870611 Byte1 end_step=30 best_step=27
8744 19:57:14.874076 Byte0 TX OE(2T, 0.5T) = (3, 3)
8745 19:57:14.877573 Byte1 TX OE(2T, 0.5T) = (3, 3)
8746 19:57:14.877653
8747 19:57:14.877716
8748 19:57:14.883925 [DQSOSCAuto] RK0, (LSB)MR18= 0xb10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
8749 19:57:14.887241 CH1 RK0: MR19=303, MR18=B10
8750 19:57:14.893929 CH1_RK0: MR19=0x303, MR18=0xB10, DQSOSC=401, MR23=63, INC=22, DEC=15
8751 19:57:14.894012
8752 19:57:14.897402 ----->DramcWriteLeveling(PI) begin...
8753 19:57:14.897485 ==
8754 19:57:14.900734 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 19:57:14.903848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 19:57:14.903930 ==
8757 19:57:14.907248 Write leveling (Byte 0): 22 => 22
8758 19:57:14.910464 Write leveling (Byte 1): 28 => 28
8759 19:57:14.914066 DramcWriteLeveling(PI) end<-----
8760 19:57:14.914147
8761 19:57:14.914211 ==
8762 19:57:14.917297 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 19:57:14.920418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 19:57:14.920500 ==
8765 19:57:14.923928 [Gating] SW mode calibration
8766 19:57:14.930568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8767 19:57:14.937091 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8768 19:57:14.940659 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 19:57:14.943511 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 19:57:14.950303 1 4 8 | B1->B0 | 2323 3131 | 1 0 | (1 1) (0 0)
8771 19:57:14.953976 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8772 19:57:14.956810 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 19:57:14.963522 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 19:57:14.967085 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 19:57:14.970181 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 19:57:14.976905 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 19:57:14.980153 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8778 19:57:14.983602 1 5 8 | B1->B0 | 3434 2727 | 1 1 | (1 0) (1 0)
8779 19:57:14.990047 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8780 19:57:14.993731 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 19:57:14.997026 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 19:57:15.003652 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 19:57:15.006711 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 19:57:15.010264 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 19:57:15.016963 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
8786 19:57:15.020093 1 6 8 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8787 19:57:15.023456 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8788 19:57:15.030143 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 19:57:15.033526 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 19:57:15.037058 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 19:57:15.043645 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 19:57:15.047079 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 19:57:15.050170 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 19:57:15.053584 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8795 19:57:15.060477 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8796 19:57:15.063739 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 19:57:15.066637 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 19:57:15.073209 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 19:57:15.076826 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 19:57:15.080073 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 19:57:15.086499 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 19:57:15.090313 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 19:57:15.093594 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 19:57:15.099970 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 19:57:15.103125 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 19:57:15.106689 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 19:57:15.113099 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 19:57:15.116479 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 19:57:15.119668 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8810 19:57:15.126163 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8811 19:57:15.130456 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8812 19:57:15.132997 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 19:57:15.136640 Total UI for P1: 0, mck2ui 16
8814 19:57:15.139875 best dqsien dly found for B0: ( 1, 9, 8)
8815 19:57:15.142813 Total UI for P1: 0, mck2ui 16
8816 19:57:15.146256 best dqsien dly found for B1: ( 1, 9, 12)
8817 19:57:15.149511 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8818 19:57:15.152910 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8819 19:57:15.152989
8820 19:57:15.159911 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8821 19:57:15.163182 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8822 19:57:15.163262 [Gating] SW calibration Done
8823 19:57:15.166372 ==
8824 19:57:15.166452 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 19:57:15.172993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 19:57:15.173074 ==
8827 19:57:15.173138 RX Vref Scan: 0
8828 19:57:15.173197
8829 19:57:15.176940 RX Vref 0 -> 0, step: 1
8830 19:57:15.177019
8831 19:57:15.180184 RX Delay 0 -> 252, step: 8
8832 19:57:15.183635 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8833 19:57:15.186707 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8834 19:57:15.189540 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8835 19:57:15.196594 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8836 19:57:15.200012 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8837 19:57:15.202900 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8838 19:57:15.206242 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8839 19:57:15.209548 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8840 19:57:15.216482 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8841 19:57:15.219683 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8842 19:57:15.223216 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8843 19:57:15.225942 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8844 19:57:15.229154 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8845 19:57:15.236033 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8846 19:57:15.239060 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8847 19:57:15.242381 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8848 19:57:15.242460 ==
8849 19:57:15.245599 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 19:57:15.248998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 19:57:15.252697 ==
8852 19:57:15.252778 DQS Delay:
8853 19:57:15.252843 DQS0 = 0, DQS1 = 0
8854 19:57:15.255940 DQM Delay:
8855 19:57:15.256021 DQM0 = 133, DQM1 = 128
8856 19:57:15.258910 DQ Delay:
8857 19:57:15.262443 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8858 19:57:15.265647 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8859 19:57:15.268908 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8860 19:57:15.272556 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8861 19:57:15.272639
8862 19:57:15.272702
8863 19:57:15.272762 ==
8864 19:57:15.275583 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 19:57:15.279091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 19:57:15.279173 ==
8867 19:57:15.279237
8868 19:57:15.282414
8869 19:57:15.282494 TX Vref Scan disable
8870 19:57:15.285656 == TX Byte 0 ==
8871 19:57:15.289103 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8872 19:57:15.292107 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8873 19:57:15.295860 == TX Byte 1 ==
8874 19:57:15.299094 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8875 19:57:15.302095 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8876 19:57:15.302177 ==
8877 19:57:15.305807 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 19:57:15.312234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 19:57:15.312318 ==
8880 19:57:15.324227
8881 19:57:15.327639 TX Vref early break, caculate TX vref
8882 19:57:15.330787 TX Vref=16, minBit 0, minWin=22, winSum=377
8883 19:57:15.334328 TX Vref=18, minBit 0, minWin=23, winSum=383
8884 19:57:15.337332 TX Vref=20, minBit 0, minWin=22, winSum=390
8885 19:57:15.340513 TX Vref=22, minBit 5, minWin=23, winSum=402
8886 19:57:15.343984 TX Vref=24, minBit 0, minWin=24, winSum=410
8887 19:57:15.350431 TX Vref=26, minBit 1, minWin=25, winSum=420
8888 19:57:15.354067 TX Vref=28, minBit 5, minWin=24, winSum=419
8889 19:57:15.357626 TX Vref=30, minBit 5, minWin=23, winSum=412
8890 19:57:15.360747 TX Vref=32, minBit 5, minWin=23, winSum=407
8891 19:57:15.363873 TX Vref=34, minBit 1, minWin=22, winSum=393
8892 19:57:15.370815 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 26
8893 19:57:15.370899
8894 19:57:15.373887 Final TX Range 0 Vref 26
8895 19:57:15.373970
8896 19:57:15.374033 ==
8897 19:57:15.376956 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 19:57:15.380654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 19:57:15.380736 ==
8900 19:57:15.380800
8901 19:57:15.380860
8902 19:57:15.383755 TX Vref Scan disable
8903 19:57:15.390795 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8904 19:57:15.390877 == TX Byte 0 ==
8905 19:57:15.394054 u2DelayCellOfst[0]=18 cells (5 PI)
8906 19:57:15.397017 u2DelayCellOfst[1]=11 cells (3 PI)
8907 19:57:15.400417 u2DelayCellOfst[2]=0 cells (0 PI)
8908 19:57:15.403754 u2DelayCellOfst[3]=3 cells (1 PI)
8909 19:57:15.407327 u2DelayCellOfst[4]=3 cells (1 PI)
8910 19:57:15.410254 u2DelayCellOfst[5]=22 cells (6 PI)
8911 19:57:15.413552 u2DelayCellOfst[6]=18 cells (5 PI)
8912 19:57:15.416618 u2DelayCellOfst[7]=3 cells (1 PI)
8913 19:57:15.420247 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8914 19:57:15.423942 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8915 19:57:15.427183 == TX Byte 1 ==
8916 19:57:15.427264 u2DelayCellOfst[8]=0 cells (0 PI)
8917 19:57:15.430326 u2DelayCellOfst[9]=7 cells (2 PI)
8918 19:57:15.433240 u2DelayCellOfst[10]=15 cells (4 PI)
8919 19:57:15.436587 u2DelayCellOfst[11]=3 cells (1 PI)
8920 19:57:15.439968 u2DelayCellOfst[12]=18 cells (5 PI)
8921 19:57:15.443316 u2DelayCellOfst[13]=18 cells (5 PI)
8922 19:57:15.446838 u2DelayCellOfst[14]=22 cells (6 PI)
8923 19:57:15.450342 u2DelayCellOfst[15]=18 cells (5 PI)
8924 19:57:15.453253 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8925 19:57:15.459571 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8926 19:57:15.459659 DramC Write-DBI on
8927 19:57:15.459744 ==
8928 19:57:15.463064 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 19:57:15.469698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 19:57:15.469788 ==
8931 19:57:15.469874
8932 19:57:15.469955
8933 19:57:15.470032 TX Vref Scan disable
8934 19:57:15.473355 == TX Byte 0 ==
8935 19:57:15.476831 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8936 19:57:15.479937 == TX Byte 1 ==
8937 19:57:15.483308 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8938 19:57:15.487116 DramC Write-DBI off
8939 19:57:15.487196
8940 19:57:15.487259 [DATLAT]
8941 19:57:15.487331 Freq=1600, CH1 RK1
8942 19:57:15.487453
8943 19:57:15.489951 DATLAT Default: 0xf
8944 19:57:15.490031 0, 0xFFFF, sum = 0
8945 19:57:15.493251 1, 0xFFFF, sum = 0
8946 19:57:15.496721 2, 0xFFFF, sum = 0
8947 19:57:15.496802 3, 0xFFFF, sum = 0
8948 19:57:15.499881 4, 0xFFFF, sum = 0
8949 19:57:15.499963 5, 0xFFFF, sum = 0
8950 19:57:15.503340 6, 0xFFFF, sum = 0
8951 19:57:15.503449 7, 0xFFFF, sum = 0
8952 19:57:15.506217 8, 0xFFFF, sum = 0
8953 19:57:15.506301 9, 0xFFFF, sum = 0
8954 19:57:15.509806 10, 0xFFFF, sum = 0
8955 19:57:15.509891 11, 0xFFFF, sum = 0
8956 19:57:15.513452 12, 0xFFFF, sum = 0
8957 19:57:15.513537 13, 0x8FFF, sum = 0
8958 19:57:15.516656 14, 0x0, sum = 1
8959 19:57:15.516740 15, 0x0, sum = 2
8960 19:57:15.519638 16, 0x0, sum = 3
8961 19:57:15.519723 17, 0x0, sum = 4
8962 19:57:15.523368 best_step = 15
8963 19:57:15.523460
8964 19:57:15.523545 ==
8965 19:57:15.526222 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 19:57:15.530251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 19:57:15.530340 ==
8968 19:57:15.533288 RX Vref Scan: 0
8969 19:57:15.533372
8970 19:57:15.533457 RX Vref 0 -> 0, step: 1
8971 19:57:15.533538
8972 19:57:15.536426 RX Delay 11 -> 252, step: 4
8973 19:57:15.543311 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8974 19:57:15.546301 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8975 19:57:15.549790 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8976 19:57:15.552820 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8977 19:57:15.556329 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8978 19:57:15.562820 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8979 19:57:15.566242 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8980 19:57:15.569404 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8981 19:57:15.572603 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8982 19:57:15.576535 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8983 19:57:15.583070 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8984 19:57:15.585854 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8985 19:57:15.589461 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8986 19:57:15.592564 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8987 19:57:15.595880 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8988 19:57:15.602555 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8989 19:57:15.602640 ==
8990 19:57:15.605890 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 19:57:15.608997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 19:57:15.609083 ==
8993 19:57:15.609148 DQS Delay:
8994 19:57:15.612758 DQS0 = 0, DQS1 = 0
8995 19:57:15.612840 DQM Delay:
8996 19:57:15.615854 DQM0 = 130, DQM1 = 125
8997 19:57:15.615936 DQ Delay:
8998 19:57:15.619184 DQ0 =134, DQ1 =128, DQ2 =116, DQ3 =128
8999 19:57:15.622381 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =126
9000 19:57:15.625817 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9001 19:57:15.628972 DQ12 =132, DQ13 =136, DQ14 =130, DQ15 =134
9002 19:57:15.629057
9003 19:57:15.632105
9004 19:57:15.632185
9005 19:57:15.632249 [DramC_TX_OE_Calibration] TA2
9006 19:57:15.635402 Original DQ_B0 (3 6) =30, OEN = 27
9007 19:57:15.638804 Original DQ_B1 (3 6) =30, OEN = 27
9008 19:57:15.642254 24, 0x0, End_B0=24 End_B1=24
9009 19:57:15.645461 25, 0x0, End_B0=25 End_B1=25
9010 19:57:15.648919 26, 0x0, End_B0=26 End_B1=26
9011 19:57:15.649008 27, 0x0, End_B0=27 End_B1=27
9012 19:57:15.651917 28, 0x0, End_B0=28 End_B1=28
9013 19:57:15.655930 29, 0x0, End_B0=29 End_B1=29
9014 19:57:15.658944 30, 0x0, End_B0=30 End_B1=30
9015 19:57:15.661941 31, 0x4141, End_B0=30 End_B1=30
9016 19:57:15.662030 Byte0 end_step=30 best_step=27
9017 19:57:15.665590 Byte1 end_step=30 best_step=27
9018 19:57:15.669038 Byte0 TX OE(2T, 0.5T) = (3, 3)
9019 19:57:15.671698 Byte1 TX OE(2T, 0.5T) = (3, 3)
9020 19:57:15.671781
9021 19:57:15.671846
9022 19:57:15.682187 [DQSOSCAuto] RK1, (LSB)MR18= 0x121e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9023 19:57:15.682309 CH1 RK1: MR19=303, MR18=121E
9024 19:57:15.688561 CH1_RK1: MR19=0x303, MR18=0x121E, DQSOSC=394, MR23=63, INC=23, DEC=15
9025 19:57:15.691666 [RxdqsGatingPostProcess] freq 1600
9026 19:57:15.698485 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9027 19:57:15.701601 best DQS0 dly(2T, 0.5T) = (1, 1)
9028 19:57:15.704859 best DQS1 dly(2T, 0.5T) = (1, 1)
9029 19:57:15.708018 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9030 19:57:15.711725 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9031 19:57:15.711823 best DQS0 dly(2T, 0.5T) = (1, 1)
9032 19:57:15.714636 best DQS1 dly(2T, 0.5T) = (1, 1)
9033 19:57:15.718069 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9034 19:57:15.721429 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9035 19:57:15.724616 Pre-setting of DQS Precalculation
9036 19:57:15.731393 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9037 19:57:15.738035 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9038 19:57:15.744513 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9039 19:57:15.744627
9040 19:57:15.744693
9041 19:57:15.748174 [Calibration Summary] 3200 Mbps
9042 19:57:15.748259 CH 0, Rank 0
9043 19:57:15.751303 SW Impedance : PASS
9044 19:57:15.754742 DUTY Scan : NO K
9045 19:57:15.754828 ZQ Calibration : PASS
9046 19:57:15.757924 Jitter Meter : NO K
9047 19:57:15.761594 CBT Training : PASS
9048 19:57:15.761681 Write leveling : PASS
9049 19:57:15.764944 RX DQS gating : PASS
9050 19:57:15.767941 RX DQ/DQS(RDDQC) : PASS
9051 19:57:15.768027 TX DQ/DQS : PASS
9052 19:57:15.771145 RX DATLAT : PASS
9053 19:57:15.771228 RX DQ/DQS(Engine): PASS
9054 19:57:15.774393 TX OE : PASS
9055 19:57:15.774475 All Pass.
9056 19:57:15.774540
9057 19:57:15.778082 CH 0, Rank 1
9058 19:57:15.778166 SW Impedance : PASS
9059 19:57:15.781437 DUTY Scan : NO K
9060 19:57:15.784508 ZQ Calibration : PASS
9061 19:57:15.784591 Jitter Meter : NO K
9062 19:57:15.788129 CBT Training : PASS
9063 19:57:15.790960 Write leveling : PASS
9064 19:57:15.791043 RX DQS gating : PASS
9065 19:57:15.794270 RX DQ/DQS(RDDQC) : PASS
9066 19:57:15.797721 TX DQ/DQS : PASS
9067 19:57:15.797807 RX DATLAT : PASS
9068 19:57:15.800931 RX DQ/DQS(Engine): PASS
9069 19:57:15.804401 TX OE : PASS
9070 19:57:15.804515 All Pass.
9071 19:57:15.804608
9072 19:57:15.804695 CH 1, Rank 0
9073 19:57:15.807394 SW Impedance : PASS
9074 19:57:15.810654 DUTY Scan : NO K
9075 19:57:15.810741 ZQ Calibration : PASS
9076 19:57:15.814391 Jitter Meter : NO K
9077 19:57:15.817208 CBT Training : PASS
9078 19:57:15.817315 Write leveling : PASS
9079 19:57:15.821111 RX DQS gating : PASS
9080 19:57:15.824346 RX DQ/DQS(RDDQC) : PASS
9081 19:57:15.824430 TX DQ/DQS : PASS
9082 19:57:15.827612 RX DATLAT : PASS
9083 19:57:15.830586 RX DQ/DQS(Engine): PASS
9084 19:57:15.830668 TX OE : PASS
9085 19:57:15.830732 All Pass.
9086 19:57:15.834012
9087 19:57:15.834094 CH 1, Rank 1
9088 19:57:15.837165 SW Impedance : PASS
9089 19:57:15.837248 DUTY Scan : NO K
9090 19:57:15.840710 ZQ Calibration : PASS
9091 19:57:15.840796 Jitter Meter : NO K
9092 19:57:15.843741 CBT Training : PASS
9093 19:57:15.847518 Write leveling : PASS
9094 19:57:15.847615 RX DQS gating : PASS
9095 19:57:15.850662 RX DQ/DQS(RDDQC) : PASS
9096 19:57:15.853938 TX DQ/DQS : PASS
9097 19:57:15.854027 RX DATLAT : PASS
9098 19:57:15.857393 RX DQ/DQS(Engine): PASS
9099 19:57:15.860453 TX OE : PASS
9100 19:57:15.860544 All Pass.
9101 19:57:15.860610
9102 19:57:15.863751 DramC Write-DBI on
9103 19:57:15.863838 PER_BANK_REFRESH: Hybrid Mode
9104 19:57:15.867105 TX_TRACKING: ON
9105 19:57:15.877199 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9106 19:57:15.883904 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9107 19:57:15.890186 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9108 19:57:15.893448 [FAST_K] Save calibration result to emmc
9109 19:57:15.897205 sync common calibartion params.
9110 19:57:15.900626 sync cbt_mode0:1, 1:1
9111 19:57:15.900715 dram_init: ddr_geometry: 2
9112 19:57:15.904009 dram_init: ddr_geometry: 2
9113 19:57:15.906753 dram_init: ddr_geometry: 2
9114 19:57:15.910104 0:dram_rank_size:100000000
9115 19:57:15.910218 1:dram_rank_size:100000000
9116 19:57:15.916780 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9117 19:57:15.920198 DFS_SHUFFLE_HW_MODE: ON
9118 19:57:15.923829 dramc_set_vcore_voltage set vcore to 725000
9119 19:57:15.923919 Read voltage for 1600, 0
9120 19:57:15.927350 Vio18 = 0
9121 19:57:15.927450 Vcore = 725000
9122 19:57:15.927515 Vdram = 0
9123 19:57:15.929894 Vddq = 0
9124 19:57:15.929975 Vmddr = 0
9125 19:57:15.933452 switch to 3200 Mbps bootup
9126 19:57:15.933534 [DramcRunTimeConfig]
9127 19:57:15.936416 PHYPLL
9128 19:57:15.936498 DPM_CONTROL_AFTERK: ON
9129 19:57:15.939993 PER_BANK_REFRESH: ON
9130 19:57:15.943344 REFRESH_OVERHEAD_REDUCTION: ON
9131 19:57:15.943448 CMD_PICG_NEW_MODE: OFF
9132 19:57:15.946869 XRTWTW_NEW_MODE: ON
9133 19:57:15.946952 XRTRTR_NEW_MODE: ON
9134 19:57:15.950197 TX_TRACKING: ON
9135 19:57:15.950280 RDSEL_TRACKING: OFF
9136 19:57:15.953412 DQS Precalculation for DVFS: ON
9137 19:57:15.956632 RX_TRACKING: OFF
9138 19:57:15.956717 HW_GATING DBG: ON
9139 19:57:15.960173 ZQCS_ENABLE_LP4: ON
9140 19:57:15.960260 RX_PICG_NEW_MODE: ON
9141 19:57:15.963138 TX_PICG_NEW_MODE: ON
9142 19:57:15.963222 ENABLE_RX_DCM_DPHY: ON
9143 19:57:15.966676 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9144 19:57:15.969871 DUMMY_READ_FOR_TRACKING: OFF
9145 19:57:15.973025 !!! SPM_CONTROL_AFTERK: OFF
9146 19:57:15.976774 !!! SPM could not control APHY
9147 19:57:15.976861 IMPEDANCE_TRACKING: ON
9148 19:57:15.979771 TEMP_SENSOR: ON
9149 19:57:15.979855 HW_SAVE_FOR_SR: OFF
9150 19:57:15.983172 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9151 19:57:15.986147 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9152 19:57:15.989589 Read ODT Tracking: ON
9153 19:57:15.993113 Refresh Rate DeBounce: ON
9154 19:57:15.993195 DFS_NO_QUEUE_FLUSH: ON
9155 19:57:15.995999 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9156 19:57:15.999663 ENABLE_DFS_RUNTIME_MRW: OFF
9157 19:57:16.002972 DDR_RESERVE_NEW_MODE: ON
9158 19:57:16.003054 MR_CBT_SWITCH_FREQ: ON
9159 19:57:16.006363 =========================
9160 19:57:16.024868 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9161 19:57:16.028326 dram_init: ddr_geometry: 2
9162 19:57:16.046996 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9163 19:57:16.049701 dram_init: dram init end (result: 0)
9164 19:57:16.056483 DRAM-K: Full calibration passed in 24575 msecs
9165 19:57:16.059841 MRC: failed to locate region type 0.
9166 19:57:16.059923 DRAM rank0 size:0x100000000,
9167 19:57:16.063366 DRAM rank1 size=0x100000000
9168 19:57:16.073489 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9169 19:57:16.080051 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9170 19:57:16.086250 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9171 19:57:16.093305 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9172 19:57:16.096484 DRAM rank0 size:0x100000000,
9173 19:57:16.099653 DRAM rank1 size=0x100000000
9174 19:57:16.099735 CBMEM:
9175 19:57:16.102937 IMD: root @ 0xfffff000 254 entries.
9176 19:57:16.106243 IMD: root @ 0xffffec00 62 entries.
9177 19:57:16.109471 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9178 19:57:16.113080 WARNING: RO_VPD is uninitialized or empty.
9179 19:57:16.119318 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9180 19:57:16.126679 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9181 19:57:16.139120 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9182 19:57:16.151050 BS: romstage times (exec / console): total (unknown) / 24038 ms
9183 19:57:16.151157
9184 19:57:16.151223
9185 19:57:16.160487 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9186 19:57:16.164459 ARM64: Exception handlers installed.
9187 19:57:16.167270 ARM64: Testing exception
9188 19:57:16.170356 ARM64: Done test exception
9189 19:57:16.170438 Enumerating buses...
9190 19:57:16.174120 Show all devs... Before device enumeration.
9191 19:57:16.177231 Root Device: enabled 1
9192 19:57:16.180839 CPU_CLUSTER: 0: enabled 1
9193 19:57:16.180920 CPU: 00: enabled 1
9194 19:57:16.183749 Compare with tree...
9195 19:57:16.183831 Root Device: enabled 1
9196 19:57:16.187304 CPU_CLUSTER: 0: enabled 1
9197 19:57:16.190756 CPU: 00: enabled 1
9198 19:57:16.190837 Root Device scanning...
9199 19:57:16.193728 scan_static_bus for Root Device
9200 19:57:16.196917 CPU_CLUSTER: 0 enabled
9201 19:57:16.200560 scan_static_bus for Root Device done
9202 19:57:16.203575 scan_bus: bus Root Device finished in 8 msecs
9203 19:57:16.203656 done
9204 19:57:16.210617 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9205 19:57:16.213852 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9206 19:57:16.220318 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9207 19:57:16.223703 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9208 19:57:16.226663 Allocating resources...
9209 19:57:16.230023 Reading resources...
9210 19:57:16.233525 Root Device read_resources bus 0 link: 0
9211 19:57:16.233607 DRAM rank0 size:0x100000000,
9212 19:57:16.237408 DRAM rank1 size=0x100000000
9213 19:57:16.240270 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9214 19:57:16.243468 CPU: 00 missing read_resources
9215 19:57:16.250134 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9216 19:57:16.253433 Root Device read_resources bus 0 link: 0 done
9217 19:57:16.253516 Done reading resources.
9218 19:57:16.259919 Show resources in subtree (Root Device)...After reading.
9219 19:57:16.263122 Root Device child on link 0 CPU_CLUSTER: 0
9220 19:57:16.266401 CPU_CLUSTER: 0 child on link 0 CPU: 00
9221 19:57:16.276509 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9222 19:57:16.276597 CPU: 00
9223 19:57:16.279818 Root Device assign_resources, bus 0 link: 0
9224 19:57:16.282930 CPU_CLUSTER: 0 missing set_resources
9225 19:57:16.289861 Root Device assign_resources, bus 0 link: 0 done
9226 19:57:16.289944 Done setting resources.
9227 19:57:16.296296 Show resources in subtree (Root Device)...After assigning values.
9228 19:57:16.299739 Root Device child on link 0 CPU_CLUSTER: 0
9229 19:57:16.302830 CPU_CLUSTER: 0 child on link 0 CPU: 00
9230 19:57:16.312652 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9231 19:57:16.312737 CPU: 00
9232 19:57:16.316500 Done allocating resources.
9233 19:57:16.322682 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9234 19:57:16.322771 Enabling resources...
9235 19:57:16.322836 done.
9236 19:57:16.329093 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9237 19:57:16.329177 Initializing devices...
9238 19:57:16.332642 Root Device init
9239 19:57:16.335709 init hardware done!
9240 19:57:16.335790 0x00000018: ctrlr->caps
9241 19:57:16.339173 52.000 MHz: ctrlr->f_max
9242 19:57:16.342436 0.400 MHz: ctrlr->f_min
9243 19:57:16.342518 0x40ff8080: ctrlr->voltages
9244 19:57:16.345690 sclk: 390625
9245 19:57:16.345771 Bus Width = 1
9246 19:57:16.345835 sclk: 390625
9247 19:57:16.349125 Bus Width = 1
9248 19:57:16.349205 Early init status = 3
9249 19:57:16.355573 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9250 19:57:16.360041 in-header: 03 fc 00 00 01 00 00 00
9251 19:57:16.362368 in-data: 00
9252 19:57:16.365693 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9253 19:57:16.371267 in-header: 03 fd 00 00 00 00 00 00
9254 19:57:16.375037 in-data:
9255 19:57:16.378040 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9256 19:57:16.382466 in-header: 03 fc 00 00 01 00 00 00
9257 19:57:16.385913 in-data: 00
9258 19:57:16.388978 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9259 19:57:16.394930 in-header: 03 fd 00 00 00 00 00 00
9260 19:57:16.398157 in-data:
9261 19:57:16.401568 [SSUSB] Setting up USB HOST controller...
9262 19:57:16.404806 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9263 19:57:16.407867 [SSUSB] phy power-on done.
9264 19:57:16.411397 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9265 19:57:16.417590 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9266 19:57:16.421497 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9267 19:57:16.427693 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9268 19:57:16.434531 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9269 19:57:16.440811 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9270 19:57:16.447978 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9271 19:57:16.454592 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9272 19:57:16.457723 SPM: binary array size = 0x9dc
9273 19:57:16.460739 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9274 19:57:16.467367 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9275 19:57:16.473842 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9276 19:57:16.480972 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9277 19:57:16.483773 configure_display: Starting display init
9278 19:57:16.517881 anx7625_power_on_init: Init interface.
9279 19:57:16.520981 anx7625_disable_pd_protocol: Disabled PD feature.
9280 19:57:16.524133 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9281 19:57:16.552345 anx7625_start_dp_work: Secure OCM version=00
9282 19:57:16.555647 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9283 19:57:16.570570 sp_tx_get_edid_block: EDID Block = 1
9284 19:57:16.673154 Extracted contents:
9285 19:57:16.676148 header: 00 ff ff ff ff ff ff 00
9286 19:57:16.679605 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9287 19:57:16.682602 version: 01 04
9288 19:57:16.686187 basic params: 95 1f 11 78 0a
9289 19:57:16.689458 chroma info: 76 90 94 55 54 90 27 21 50 54
9290 19:57:16.692658 established: 00 00 00
9291 19:57:16.699355 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9292 19:57:16.702998 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9293 19:57:16.709969 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9294 19:57:16.715926 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9295 19:57:16.722602 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9296 19:57:16.725520 extensions: 00
9297 19:57:16.725612 checksum: fb
9298 19:57:16.725676
9299 19:57:16.729326 Manufacturer: IVO Model 57d Serial Number 0
9300 19:57:16.732241 Made week 0 of 2020
9301 19:57:16.732320 EDID version: 1.4
9302 19:57:16.735405 Digital display
9303 19:57:16.739034 6 bits per primary color channel
9304 19:57:16.739114 DisplayPort interface
9305 19:57:16.742601 Maximum image size: 31 cm x 17 cm
9306 19:57:16.745650 Gamma: 220%
9307 19:57:16.745729 Check DPMS levels
9308 19:57:16.748938 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9309 19:57:16.755317 First detailed timing is preferred timing
9310 19:57:16.755441 Established timings supported:
9311 19:57:16.758875 Standard timings supported:
9312 19:57:16.762191 Detailed timings
9313 19:57:16.765658 Hex of detail: 383680a07038204018303c0035ae10000019
9314 19:57:16.768928 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9315 19:57:16.775351 0780 0798 07c8 0820 hborder 0
9316 19:57:16.779054 0438 043b 0447 0458 vborder 0
9317 19:57:16.782220 -hsync -vsync
9318 19:57:16.782304 Did detailed timing
9319 19:57:16.788545 Hex of detail: 000000000000000000000000000000000000
9320 19:57:16.791817 Manufacturer-specified data, tag 0
9321 19:57:16.795671 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9322 19:57:16.799077 ASCII string: InfoVision
9323 19:57:16.801915 Hex of detail: 000000fe00523134304e574635205248200a
9324 19:57:16.805180 ASCII string: R140NWF5 RH
9325 19:57:16.805263 Checksum
9326 19:57:16.808394 Checksum: 0xfb (valid)
9327 19:57:16.811778 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9328 19:57:16.815209 DSI data_rate: 832800000 bps
9329 19:57:16.821924 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9330 19:57:16.825079 anx7625_parse_edid: pixelclock(138800).
9331 19:57:16.828757 hactive(1920), hsync(48), hfp(24), hbp(88)
9332 19:57:16.831868 vactive(1080), vsync(12), vfp(3), vbp(17)
9333 19:57:16.834926 anx7625_dsi_config: config dsi.
9334 19:57:16.841886 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9335 19:57:16.854818 anx7625_dsi_config: success to config DSI
9336 19:57:16.857926 anx7625_dp_start: MIPI phy setup OK.
9337 19:57:16.861736 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9338 19:57:16.864455 mtk_ddp_mode_set invalid vrefresh 60
9339 19:57:16.868229 main_disp_path_setup
9340 19:57:16.868327 ovl_layer_smi_id_en
9341 19:57:16.871532 ovl_layer_smi_id_en
9342 19:57:16.871617 ccorr_config
9343 19:57:16.871681 aal_config
9344 19:57:16.874606 gamma_config
9345 19:57:16.874689 postmask_config
9346 19:57:16.877793 dither_config
9347 19:57:16.881408 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9348 19:57:16.887659 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9349 19:57:16.890972 Root Device init finished in 555 msecs
9350 19:57:16.894282 CPU_CLUSTER: 0 init
9351 19:57:16.901324 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9352 19:57:16.907699 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9353 19:57:16.907798 APU_MBOX 0x190000b0 = 0x10001
9354 19:57:16.910939 APU_MBOX 0x190001b0 = 0x10001
9355 19:57:16.914268 APU_MBOX 0x190005b0 = 0x10001
9356 19:57:16.917507 APU_MBOX 0x190006b0 = 0x10001
9357 19:57:16.924032 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9358 19:57:16.933667 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9359 19:57:16.946358 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9360 19:57:16.952567 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9361 19:57:16.964753 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9362 19:57:16.973758 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9363 19:57:16.977153 CPU_CLUSTER: 0 init finished in 81 msecs
9364 19:57:16.980476 Devices initialized
9365 19:57:16.983358 Show all devs... After init.
9366 19:57:16.983499 Root Device: enabled 1
9367 19:57:16.986759 CPU_CLUSTER: 0: enabled 1
9368 19:57:16.990276 CPU: 00: enabled 1
9369 19:57:16.993341 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9370 19:57:16.996822 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9371 19:57:17.000206 ELOG: NV offset 0x57f000 size 0x1000
9372 19:57:17.006994 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9373 19:57:17.013629 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9374 19:57:17.017194 ELOG: Event(17) added with size 13 at 2023-10-28 19:57:17 UTC
9375 19:57:17.023620 out: cmd=0x121: 03 db 21 01 00 00 00 00
9376 19:57:17.026936 in-header: 03 57 00 00 2c 00 00 00
9377 19:57:17.036438 in-data: 07 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9378 19:57:17.043237 ELOG: Event(A1) added with size 10 at 2023-10-28 19:57:17 UTC
9379 19:57:17.049599 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9380 19:57:17.056651 ELOG: Event(A0) added with size 9 at 2023-10-28 19:57:17 UTC
9381 19:57:17.059368 elog_add_boot_reason: Logged dev mode boot
9382 19:57:17.066455 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9383 19:57:17.066572 Finalize devices...
9384 19:57:17.069819 Devices finalized
9385 19:57:17.073449 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9386 19:57:17.076927 Writing coreboot table at 0xffe64000
9387 19:57:17.079776 0. 000000000010a000-0000000000113fff: RAMSTAGE
9388 19:57:17.083008 1. 0000000040000000-00000000400fffff: RAM
9389 19:57:17.089679 2. 0000000040100000-000000004032afff: RAMSTAGE
9390 19:57:17.092902 3. 000000004032b000-00000000545fffff: RAM
9391 19:57:17.096362 4. 0000000054600000-000000005465ffff: BL31
9392 19:57:17.099229 5. 0000000054660000-00000000ffe63fff: RAM
9393 19:57:17.106710 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9394 19:57:17.109760 7. 0000000100000000-000000023fffffff: RAM
9395 19:57:17.113010 Passing 5 GPIOs to payload:
9396 19:57:17.116098 NAME | PORT | POLARITY | VALUE
9397 19:57:17.119468 EC in RW | 0x000000aa | low | undefined
9398 19:57:17.126680 EC interrupt | 0x00000005 | low | undefined
9399 19:57:17.130355 TPM interrupt | 0x000000ab | high | undefined
9400 19:57:17.136520 SD card detect | 0x00000011 | high | undefined
9401 19:57:17.139931 speaker enable | 0x00000093 | high | undefined
9402 19:57:17.143212 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9403 19:57:17.146419 in-header: 03 f9 00 00 02 00 00 00
9404 19:57:17.149698 in-data: 02 00
9405 19:57:17.153507 ADC[4]: Raw value=893341 ID=7
9406 19:57:17.154008 ADC[3]: Raw value=213070 ID=1
9407 19:57:17.156065 RAM Code: 0x71
9408 19:57:17.160316 ADC[6]: Raw value=74722 ID=0
9409 19:57:17.160803 ADC[5]: Raw value=212330 ID=1
9410 19:57:17.163281 SKU Code: 0x1
9411 19:57:17.166096 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 360f
9412 19:57:17.169303 coreboot table: 964 bytes.
9413 19:57:17.173294 IMD ROOT 0. 0xfffff000 0x00001000
9414 19:57:17.176665 IMD SMALL 1. 0xffffe000 0x00001000
9415 19:57:17.179755 RO MCACHE 2. 0xffffc000 0x00001104
9416 19:57:17.182600 CONSOLE 3. 0xfff7c000 0x00080000
9417 19:57:17.186664 FMAP 4. 0xfff7b000 0x00000452
9418 19:57:17.189190 TIME STAMP 5. 0xfff7a000 0x00000910
9419 19:57:17.192629 VBOOT WORK 6. 0xfff66000 0x00014000
9420 19:57:17.196005 RAMOOPS 7. 0xffe66000 0x00100000
9421 19:57:17.198915 COREBOOT 8. 0xffe64000 0x00002000
9422 19:57:17.202732 IMD small region:
9423 19:57:17.205903 IMD ROOT 0. 0xffffec00 0x00000400
9424 19:57:17.208915 VPD 1. 0xffffeb80 0x0000006c
9425 19:57:17.213006 MMC STATUS 2. 0xffffeb60 0x00000004
9426 19:57:17.215934 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9427 19:57:17.218957 Probing TPM: done!
9428 19:57:17.223000 Connected to device vid:did:rid of 1ae0:0028:00
9429 19:57:17.233738 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9430 19:57:17.237107 Initialized TPM device CR50 revision 0
9431 19:57:17.240073 Checking cr50 for pending updates
9432 19:57:17.244026 Reading cr50 TPM mode
9433 19:57:17.252890 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9434 19:57:17.259011 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9435 19:57:17.299290 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9436 19:57:17.302937 Checking segment from ROM address 0x40100000
9437 19:57:17.305889 Checking segment from ROM address 0x4010001c
9438 19:57:17.313090 Loading segment from ROM address 0x40100000
9439 19:57:17.313643 code (compression=0)
9440 19:57:17.322421 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9441 19:57:17.329678 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9442 19:57:17.330205 it's not compressed!
9443 19:57:17.336080 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9444 19:57:17.339087 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9445 19:57:17.359731 Loading segment from ROM address 0x4010001c
9446 19:57:17.360258 Entry Point 0x80000000
9447 19:57:17.363139 Loaded segments
9448 19:57:17.366433 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9449 19:57:17.372704 Jumping to boot code at 0x80000000(0xffe64000)
9450 19:57:17.379603 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9451 19:57:17.386264 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9452 19:57:17.394395 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9453 19:57:17.397718 Checking segment from ROM address 0x40100000
9454 19:57:17.400589 Checking segment from ROM address 0x4010001c
9455 19:57:17.407353 Loading segment from ROM address 0x40100000
9456 19:57:17.407895 code (compression=1)
9457 19:57:17.414027 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9458 19:57:17.424034 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9459 19:57:17.424536 using LZMA
9460 19:57:17.432461 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9461 19:57:17.439109 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9462 19:57:17.442182 Loading segment from ROM address 0x4010001c
9463 19:57:17.442601 Entry Point 0x54601000
9464 19:57:17.445711 Loaded segments
9465 19:57:17.448992 NOTICE: MT8192 bl31_setup
9466 19:57:17.456252 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9467 19:57:17.459891 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9468 19:57:17.462868 WARNING: region 0:
9469 19:57:17.466422 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 19:57:17.466947 WARNING: region 1:
9471 19:57:17.472866 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9472 19:57:17.475887 WARNING: region 2:
9473 19:57:17.479563 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9474 19:57:17.483036 WARNING: region 3:
9475 19:57:17.485884 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9476 19:57:17.489561 WARNING: region 4:
9477 19:57:17.495906 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9478 19:57:17.496473 WARNING: region 5:
9479 19:57:17.499710 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 19:57:17.503139 WARNING: region 6:
9481 19:57:17.506430 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 19:57:17.509170 WARNING: region 7:
9483 19:57:17.513079 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 19:57:17.519443 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9485 19:57:17.522751 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9486 19:57:17.526243 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9487 19:57:17.532679 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9488 19:57:17.536005 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9489 19:57:17.539745 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9490 19:57:17.545975 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9491 19:57:17.549765 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9492 19:57:17.552767 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9493 19:57:17.559810 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9494 19:57:17.562972 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9495 19:57:17.569482 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9496 19:57:17.573000 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9497 19:57:17.575840 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9498 19:57:17.582660 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9499 19:57:17.586247 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9500 19:57:17.592738 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9501 19:57:17.596309 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9502 19:57:17.599282 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9503 19:57:17.605955 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9504 19:57:17.609222 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9505 19:57:17.612928 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9506 19:57:17.619653 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9507 19:57:17.622304 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9508 19:57:17.629591 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9509 19:57:17.633001 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9510 19:57:17.636281 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9511 19:57:17.642446 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9512 19:57:17.646041 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9513 19:57:17.653129 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9514 19:57:17.656229 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9515 19:57:17.659463 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9516 19:57:17.665592 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9517 19:57:17.669185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9518 19:57:17.672458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9519 19:57:17.675642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9520 19:57:17.682192 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9521 19:57:17.685642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9522 19:57:17.688775 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9523 19:57:17.692353 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9524 19:57:17.698749 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9525 19:57:17.701994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9526 19:57:17.705314 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9527 19:57:17.709014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9528 19:57:17.716240 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9529 19:57:17.719185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9530 19:57:17.722284 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9531 19:57:17.726023 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9532 19:57:17.732485 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9533 19:57:17.735660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9534 19:57:17.742266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9535 19:57:17.745671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9536 19:57:17.749010 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9537 19:57:17.755727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9538 19:57:17.758866 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9539 19:57:17.765913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9540 19:57:17.768787 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9541 19:57:17.775803 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9542 19:57:17.778898 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9543 19:57:17.781956 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9544 19:57:17.789562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9545 19:57:17.792370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9546 19:57:17.798557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9547 19:57:17.801907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9548 19:57:17.809101 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9549 19:57:17.812532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9550 19:57:17.819079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9551 19:57:17.822362 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9552 19:57:17.825507 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9553 19:57:17.832525 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9554 19:57:17.836146 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9555 19:57:17.842356 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9556 19:57:17.845064 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9557 19:57:17.852223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9558 19:57:17.855272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9559 19:57:17.858893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9560 19:57:17.865242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9561 19:57:17.869001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9562 19:57:17.875595 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9563 19:57:17.879197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9564 19:57:17.885552 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9565 19:57:17.889201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9566 19:57:17.891996 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9567 19:57:17.898569 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9568 19:57:17.901910 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9569 19:57:17.908626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9570 19:57:17.912178 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9571 19:57:17.918856 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9572 19:57:17.922066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9573 19:57:17.925998 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9574 19:57:17.932950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9575 19:57:17.935657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9576 19:57:17.942500 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9577 19:57:17.945896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9578 19:57:17.952446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9579 19:57:17.955626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9580 19:57:17.959145 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9581 19:57:17.965640 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9582 19:57:17.969034 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9583 19:57:17.972611 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9584 19:57:17.975380 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9585 19:57:17.982088 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9586 19:57:17.985768 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9587 19:57:17.992003 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9588 19:57:17.995644 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9589 19:57:17.998690 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9590 19:57:18.005196 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9591 19:57:18.008560 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9592 19:57:18.015512 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9593 19:57:18.018971 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9594 19:57:18.022271 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9595 19:57:18.028569 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9596 19:57:18.032482 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9597 19:57:18.038560 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9598 19:57:18.041986 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9599 19:57:18.045284 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9600 19:57:18.048704 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9601 19:57:18.055273 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9602 19:57:18.058589 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9603 19:57:18.061805 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9604 19:57:18.068342 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9605 19:57:18.071687 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9606 19:57:18.075668 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9607 19:57:18.078803 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9608 19:57:18.085516 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9609 19:57:18.088771 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9610 19:57:18.095365 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9611 19:57:18.098755 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9612 19:57:18.102159 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9613 19:57:18.108884 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9614 19:57:18.111890 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9615 19:57:18.115528 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9616 19:57:18.122015 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9617 19:57:18.125465 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9618 19:57:18.132270 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9619 19:57:18.135516 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9620 19:57:18.138610 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9621 19:57:18.145085 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9622 19:57:18.148567 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9623 19:57:18.155973 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9624 19:57:18.158831 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9625 19:57:18.162881 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9626 19:57:18.168969 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9627 19:57:18.172090 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9628 19:57:18.175350 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9629 19:57:18.182308 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9630 19:57:18.185695 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9631 19:57:18.192207 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9632 19:57:18.195301 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9633 19:57:18.198571 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9634 19:57:18.205027 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9635 19:57:18.208686 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9636 19:57:18.215406 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9637 19:57:18.218564 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9638 19:57:18.222142 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9639 19:57:18.228535 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9640 19:57:18.231690 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9641 19:57:18.238591 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9642 19:57:18.241709 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9643 19:57:18.245309 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9644 19:57:18.252056 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9645 19:57:18.255176 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9646 19:57:18.258434 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9647 19:57:18.265109 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9648 19:57:18.268353 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9649 19:57:18.274829 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9650 19:57:18.278074 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9651 19:57:18.281561 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9652 19:57:18.288362 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9653 19:57:18.291391 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9654 19:57:18.298468 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9655 19:57:18.301825 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9656 19:57:18.305068 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9657 19:57:18.311592 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9658 19:57:18.314953 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9659 19:57:18.321477 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9660 19:57:18.324806 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9661 19:57:18.327835 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9662 19:57:18.334662 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9663 19:57:18.337712 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9664 19:57:18.341526 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9665 19:57:18.348052 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9666 19:57:18.351409 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9667 19:57:18.358239 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9668 19:57:18.361332 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9669 19:57:18.365057 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9670 19:57:18.371537 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9671 19:57:18.374908 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9672 19:57:18.381188 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9673 19:57:18.384708 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9674 19:57:18.391125 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9675 19:57:18.394628 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9676 19:57:18.397675 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9677 19:57:18.404420 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9678 19:57:18.407850 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9679 19:57:18.414357 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9680 19:57:18.417405 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9681 19:57:18.420847 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9682 19:57:18.427617 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9683 19:57:18.430914 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9684 19:57:18.437889 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9685 19:57:18.440800 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9686 19:57:18.447836 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9687 19:57:18.450593 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9688 19:57:18.454091 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9689 19:57:18.460557 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9690 19:57:18.463995 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9691 19:57:18.470698 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9692 19:57:18.474198 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9693 19:57:18.477076 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9694 19:57:18.484061 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9695 19:57:18.487171 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9696 19:57:18.494244 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9697 19:57:18.496961 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9698 19:57:18.503990 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9699 19:57:18.507236 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9700 19:57:18.510527 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9701 19:57:18.517407 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9702 19:57:18.520477 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9703 19:57:18.526863 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9704 19:57:18.530118 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9705 19:57:18.537009 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9706 19:57:18.540033 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9707 19:57:18.543590 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9708 19:57:18.549895 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9709 19:57:18.553412 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9710 19:57:18.559678 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9711 19:57:18.563695 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9712 19:57:18.566520 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9713 19:57:18.572963 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9714 19:57:18.576252 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9715 19:57:18.580513 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9716 19:57:18.583280 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9717 19:57:18.589389 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9718 19:57:18.592999 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9719 19:57:18.596542 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9720 19:57:18.603052 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9721 19:57:18.605898 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9722 19:57:18.609404 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9723 19:57:18.616357 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9724 19:57:18.619167 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9725 19:57:18.625930 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9726 19:57:18.629707 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9727 19:57:18.632783 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9728 19:57:18.639073 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9729 19:57:18.642335 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9730 19:57:18.648976 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9731 19:57:18.652183 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9732 19:57:18.655937 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9733 19:57:18.662248 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9734 19:57:18.665526 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9735 19:57:18.669073 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9736 19:57:18.675541 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9737 19:57:18.678784 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9738 19:57:18.682210 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9739 19:57:18.688827 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9740 19:57:18.692087 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9741 19:57:18.698381 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9742 19:57:18.702050 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9743 19:57:18.705434 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9744 19:57:18.711552 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9745 19:57:18.715205 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9746 19:57:18.721848 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9747 19:57:18.725180 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9748 19:57:18.728663 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9749 19:57:18.734841 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9750 19:57:18.738007 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9751 19:57:18.741369 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9752 19:57:18.748149 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9753 19:57:18.751530 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9754 19:57:18.754474 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9755 19:57:18.757722 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9756 19:57:18.764751 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9757 19:57:18.767745 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9758 19:57:18.771063 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9759 19:57:18.774496 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9760 19:57:18.780974 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9761 19:57:18.784485 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9762 19:57:18.787700 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9763 19:57:18.791335 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9764 19:57:18.797828 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9765 19:57:18.800826 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9766 19:57:18.804281 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9767 19:57:18.810910 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9768 19:57:18.814287 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9769 19:57:18.820898 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9770 19:57:18.824177 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9771 19:57:18.831108 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9772 19:57:18.833904 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9773 19:57:18.836915 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9774 19:57:18.843535 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9775 19:57:18.847110 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9776 19:57:18.853959 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9777 19:57:18.857093 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9778 19:57:18.860433 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9779 19:57:18.866942 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9780 19:57:18.870109 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9781 19:57:18.876787 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9782 19:57:18.880658 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9783 19:57:18.883910 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9784 19:57:18.890280 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9785 19:57:18.893541 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9786 19:57:18.900160 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9787 19:57:18.904256 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9788 19:57:18.907500 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9789 19:57:18.914250 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9790 19:57:18.917420 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9791 19:57:18.924125 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9792 19:57:18.927438 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9793 19:57:18.933706 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9794 19:57:18.936847 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9795 19:57:18.940243 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9796 19:57:18.946662 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9797 19:57:18.949859 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9798 19:57:18.957305 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9799 19:57:18.959650 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9800 19:57:18.963278 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9801 19:57:18.969810 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9802 19:57:18.973332 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9803 19:57:18.979646 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9804 19:57:18.983161 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9805 19:57:18.986669 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9806 19:57:18.992925 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9807 19:57:18.996637 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9808 19:57:19.002793 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9809 19:57:19.006373 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9810 19:57:19.012940 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9811 19:57:19.016231 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9812 19:57:19.019692 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9813 19:57:19.026667 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9814 19:57:19.029920 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9815 19:57:19.036391 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9816 19:57:19.039655 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9817 19:57:19.043554 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9818 19:57:19.050026 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9819 19:57:19.052846 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9820 19:57:19.059281 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9821 19:57:19.062634 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9822 19:57:19.066343 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9823 19:57:19.072628 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9824 19:57:19.075913 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9825 19:57:19.082862 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9826 19:57:19.086232 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9827 19:57:19.089275 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9828 19:57:19.096078 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9829 19:57:19.099352 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9830 19:57:19.105989 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9831 19:57:19.109387 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9832 19:57:19.112485 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9833 19:57:19.119345 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9834 19:57:19.122095 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9835 19:57:19.129502 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9836 19:57:19.132670 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9837 19:57:19.138798 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9838 19:57:19.142184 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9839 19:57:19.145768 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9840 19:57:19.152330 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9841 19:57:19.155792 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9842 19:57:19.161985 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9843 19:57:19.165292 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9844 19:57:19.171864 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9845 19:57:19.175092 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9846 19:57:19.181498 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9847 19:57:19.184783 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9848 19:57:19.188466 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9849 19:57:19.194824 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9850 19:57:19.198438 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9851 19:57:19.205342 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9852 19:57:19.208296 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9853 19:57:19.214691 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9854 19:57:19.217993 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9855 19:57:19.224913 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9856 19:57:19.227614 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9857 19:57:19.231045 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9858 19:57:19.237944 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9859 19:57:19.240984 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9860 19:57:19.247959 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9861 19:57:19.251138 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9862 19:57:19.257933 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9863 19:57:19.261390 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9864 19:57:19.264464 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9865 19:57:19.271378 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9866 19:57:19.274197 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9867 19:57:19.281429 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9868 19:57:19.284348 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9869 19:57:19.290963 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9870 19:57:19.294189 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9871 19:57:19.300773 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9872 19:57:19.304947 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9873 19:57:19.307882 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9874 19:57:19.314601 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9875 19:57:19.317877 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9876 19:57:19.324972 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9877 19:57:19.328436 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9878 19:57:19.334276 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9879 19:57:19.337615 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9880 19:57:19.340612 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9881 19:57:19.347187 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9882 19:57:19.350561 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9883 19:57:19.357249 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9884 19:57:19.360887 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9885 19:57:19.367254 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9886 19:57:19.370441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9887 19:57:19.373990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9888 19:57:19.380649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9889 19:57:19.383776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9890 19:57:19.390360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9891 19:57:19.393690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9892 19:57:19.400522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9893 19:57:19.404182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9894 19:57:19.410493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9895 19:57:19.413793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9896 19:57:19.420903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9897 19:57:19.423688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9898 19:57:19.430029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9899 19:57:19.434038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9900 19:57:19.440680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9901 19:57:19.443674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9902 19:57:19.450326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9903 19:57:19.453394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9904 19:57:19.459984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9905 19:57:19.463101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9906 19:57:19.469885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9907 19:57:19.472999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9908 19:57:19.479924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9909 19:57:19.483107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9910 19:57:19.489727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9911 19:57:19.492641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9912 19:57:19.499843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9913 19:57:19.503139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9914 19:57:19.509281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9915 19:57:19.512415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9916 19:57:19.519559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9917 19:57:19.522927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9918 19:57:19.526031 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9919 19:57:19.529462 INFO: [APUAPC] vio 0
9920 19:57:19.535757 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9921 19:57:19.539774 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9922 19:57:19.542443 INFO: [APUAPC] D0_APC_0: 0x400510
9923 19:57:19.545937 INFO: [APUAPC] D0_APC_1: 0x0
9924 19:57:19.549435 INFO: [APUAPC] D0_APC_2: 0x1540
9925 19:57:19.552646 INFO: [APUAPC] D0_APC_3: 0x0
9926 19:57:19.555896 INFO: [APUAPC] D1_APC_0: 0xffffffff
9927 19:57:19.559148 INFO: [APUAPC] D1_APC_1: 0xffffffff
9928 19:57:19.562820 INFO: [APUAPC] D1_APC_2: 0x3fffff
9929 19:57:19.566232 INFO: [APUAPC] D1_APC_3: 0x0
9930 19:57:19.569372 INFO: [APUAPC] D2_APC_0: 0xffffffff
9931 19:57:19.572597 INFO: [APUAPC] D2_APC_1: 0xffffffff
9932 19:57:19.575964 INFO: [APUAPC] D2_APC_2: 0x3fffff
9933 19:57:19.576045 INFO: [APUAPC] D2_APC_3: 0x0
9934 19:57:19.579293 INFO: [APUAPC] D3_APC_0: 0xffffffff
9935 19:57:19.585932 INFO: [APUAPC] D3_APC_1: 0xffffffff
9936 19:57:19.586416 INFO: [APUAPC] D3_APC_2: 0x3fffff
9937 19:57:19.589432 INFO: [APUAPC] D3_APC_3: 0x0
9938 19:57:19.592970 INFO: [APUAPC] D4_APC_0: 0xffffffff
9939 19:57:19.596449 INFO: [APUAPC] D4_APC_1: 0xffffffff
9940 19:57:19.599796 INFO: [APUAPC] D4_APC_2: 0x3fffff
9941 19:57:19.602875 INFO: [APUAPC] D4_APC_3: 0x0
9942 19:57:19.606200 INFO: [APUAPC] D5_APC_0: 0xffffffff
9943 19:57:19.609354 INFO: [APUAPC] D5_APC_1: 0xffffffff
9944 19:57:19.612716 INFO: [APUAPC] D5_APC_2: 0x3fffff
9945 19:57:19.616051 INFO: [APUAPC] D5_APC_3: 0x0
9946 19:57:19.619525 INFO: [APUAPC] D6_APC_0: 0xffffffff
9947 19:57:19.622859 INFO: [APUAPC] D6_APC_1: 0xffffffff
9948 19:57:19.625890 INFO: [APUAPC] D6_APC_2: 0x3fffff
9949 19:57:19.629290 INFO: [APUAPC] D6_APC_3: 0x0
9950 19:57:19.632845 INFO: [APUAPC] D7_APC_0: 0xffffffff
9951 19:57:19.635781 INFO: [APUAPC] D7_APC_1: 0xffffffff
9952 19:57:19.639203 INFO: [APUAPC] D7_APC_2: 0x3fffff
9953 19:57:19.642459 INFO: [APUAPC] D7_APC_3: 0x0
9954 19:57:19.645590 INFO: [APUAPC] D8_APC_0: 0xffffffff
9955 19:57:19.648942 INFO: [APUAPC] D8_APC_1: 0xffffffff
9956 19:57:19.652344 INFO: [APUAPC] D8_APC_2: 0x3fffff
9957 19:57:19.655372 INFO: [APUAPC] D8_APC_3: 0x0
9958 19:57:19.659037 INFO: [APUAPC] D9_APC_0: 0xffffffff
9959 19:57:19.662247 INFO: [APUAPC] D9_APC_1: 0xffffffff
9960 19:57:19.665109 INFO: [APUAPC] D9_APC_2: 0x3fffff
9961 19:57:19.668406 INFO: [APUAPC] D9_APC_3: 0x0
9962 19:57:19.671887 INFO: [APUAPC] D10_APC_0: 0xffffffff
9963 19:57:19.675159 INFO: [APUAPC] D10_APC_1: 0xffffffff
9964 19:57:19.678362 INFO: [APUAPC] D10_APC_2: 0x3fffff
9965 19:57:19.681979 INFO: [APUAPC] D10_APC_3: 0x0
9966 19:57:19.685185 INFO: [APUAPC] D11_APC_0: 0xffffffff
9967 19:57:19.688781 INFO: [APUAPC] D11_APC_1: 0xffffffff
9968 19:57:19.691626 INFO: [APUAPC] D11_APC_2: 0x3fffff
9969 19:57:19.695350 INFO: [APUAPC] D11_APC_3: 0x0
9970 19:57:19.698139 INFO: [APUAPC] D12_APC_0: 0xffffffff
9971 19:57:19.701708 INFO: [APUAPC] D12_APC_1: 0xffffffff
9972 19:57:19.705101 INFO: [APUAPC] D12_APC_2: 0x3fffff
9973 19:57:19.708217 INFO: [APUAPC] D12_APC_3: 0x0
9974 19:57:19.711302 INFO: [APUAPC] D13_APC_0: 0xffffffff
9975 19:57:19.714741 INFO: [APUAPC] D13_APC_1: 0xffffffff
9976 19:57:19.718123 INFO: [APUAPC] D13_APC_2: 0x3fffff
9977 19:57:19.721665 INFO: [APUAPC] D13_APC_3: 0x0
9978 19:57:19.724831 INFO: [APUAPC] D14_APC_0: 0xffffffff
9979 19:57:19.728386 INFO: [APUAPC] D14_APC_1: 0xffffffff
9980 19:57:19.731198 INFO: [APUAPC] D14_APC_2: 0x3fffff
9981 19:57:19.735119 INFO: [APUAPC] D14_APC_3: 0x0
9982 19:57:19.738310 INFO: [APUAPC] D15_APC_0: 0xffffffff
9983 19:57:19.741527 INFO: [APUAPC] D15_APC_1: 0xffffffff
9984 19:57:19.744557 INFO: [APUAPC] D15_APC_2: 0x3fffff
9985 19:57:19.747817 INFO: [APUAPC] D15_APC_3: 0x0
9986 19:57:19.751173 INFO: [APUAPC] APC_CON: 0x4
9987 19:57:19.754473 INFO: [NOCDAPC] D0_APC_0: 0x0
9988 19:57:19.757971 INFO: [NOCDAPC] D0_APC_1: 0x0
9989 19:57:19.761323 INFO: [NOCDAPC] D1_APC_0: 0x0
9990 19:57:19.764453 INFO: [NOCDAPC] D1_APC_1: 0xfff
9991 19:57:19.764558 INFO: [NOCDAPC] D2_APC_0: 0x0
9992 19:57:19.767688 INFO: [NOCDAPC] D2_APC_1: 0xfff
9993 19:57:19.770972 INFO: [NOCDAPC] D3_APC_0: 0x0
9994 19:57:19.774727 INFO: [NOCDAPC] D3_APC_1: 0xfff
9995 19:57:19.777962 INFO: [NOCDAPC] D4_APC_0: 0x0
9996 19:57:19.781186 INFO: [NOCDAPC] D4_APC_1: 0xfff
9997 19:57:19.784655 INFO: [NOCDAPC] D5_APC_0: 0x0
9998 19:57:19.787684 INFO: [NOCDAPC] D5_APC_1: 0xfff
9999 19:57:19.790957 INFO: [NOCDAPC] D6_APC_0: 0x0
10000 19:57:19.793988 INFO: [NOCDAPC] D6_APC_1: 0xfff
10001 19:57:19.797476 INFO: [NOCDAPC] D7_APC_0: 0x0
10002 19:57:19.801118 INFO: [NOCDAPC] D7_APC_1: 0xfff
10003 19:57:19.801244 INFO: [NOCDAPC] D8_APC_0: 0x0
10004 19:57:19.804063 INFO: [NOCDAPC] D8_APC_1: 0xfff
10005 19:57:19.807515 INFO: [NOCDAPC] D9_APC_0: 0x0
10006 19:57:19.810947 INFO: [NOCDAPC] D9_APC_1: 0xfff
10007 19:57:19.814108 INFO: [NOCDAPC] D10_APC_0: 0x0
10008 19:57:19.817768 INFO: [NOCDAPC] D10_APC_1: 0xfff
10009 19:57:19.820662 INFO: [NOCDAPC] D11_APC_0: 0x0
10010 19:57:19.824086 INFO: [NOCDAPC] D11_APC_1: 0xfff
10011 19:57:19.827541 INFO: [NOCDAPC] D12_APC_0: 0x0
10012 19:57:19.830496 INFO: [NOCDAPC] D12_APC_1: 0xfff
10013 19:57:19.834249 INFO: [NOCDAPC] D13_APC_0: 0x0
10014 19:57:19.837265 INFO: [NOCDAPC] D13_APC_1: 0xfff
10015 19:57:19.840675 INFO: [NOCDAPC] D14_APC_0: 0x0
10016 19:57:19.844564 INFO: [NOCDAPC] D14_APC_1: 0xfff
10017 19:57:19.844673 INFO: [NOCDAPC] D15_APC_0: 0x0
10018 19:57:19.847559 INFO: [NOCDAPC] D15_APC_1: 0xfff
10019 19:57:19.850495 INFO: [NOCDAPC] APC_CON: 0x4
10020 19:57:19.853692 INFO: [APUAPC] set_apusys_apc done
10021 19:57:19.856954 INFO: [DEVAPC] devapc_init done
10022 19:57:19.863624 INFO: GICv3 without legacy support detected.
10023 19:57:19.867455 INFO: ARM GICv3 driver initialized in EL3
10024 19:57:19.870858 INFO: Maximum SPI INTID supported: 639
10025 19:57:19.873804 INFO: BL31: Initializing runtime services
10026 19:57:19.880514 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10027 19:57:19.883624 INFO: SPM: enable CPC mode
10028 19:57:19.887223 INFO: mcdi ready for mcusys-off-idle and system suspend
10029 19:57:19.893137 INFO: BL31: Preparing for EL3 exit to normal world
10030 19:57:19.896716 INFO: Entry point address = 0x80000000
10031 19:57:19.896805 INFO: SPSR = 0x8
10032 19:57:19.903506
10033 19:57:19.903588
10034 19:57:19.903652
10035 19:57:19.906703 Starting depthcharge on Spherion...
10036 19:57:19.906783
10037 19:57:19.906846 Wipe memory regions:
10038 19:57:19.906905
10039 19:57:19.907616 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10040 19:57:19.907718 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10041 19:57:19.907801 Setting prompt string to ['asurada:']
10042 19:57:19.907880 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10043 19:57:19.909922 [0x00000040000000, 0x00000054600000)
10044 19:57:20.032271
10045 19:57:20.032406 [0x00000054660000, 0x00000080000000)
10046 19:57:20.292827
10047 19:57:20.292977 [0x000000821a7280, 0x000000ffe64000)
10048 19:57:21.038025
10049 19:57:21.038175 [0x00000100000000, 0x00000240000000)
10050 19:57:22.928595
10051 19:57:22.931212 Initializing XHCI USB controller at 0x11200000.
10052 19:57:23.969344
10053 19:57:23.972428 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10054 19:57:23.972526
10055 19:57:23.972591
10056 19:57:23.972649
10057 19:57:23.972922 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10059 19:57:24.073273 asurada: tftpboot 192.168.201.1 11899582/tftp-deploy-xxarulxr/kernel/image.itb 11899582/tftp-deploy-xxarulxr/kernel/cmdline
10060 19:57:24.073423 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 19:57:24.073578 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10062 19:57:24.078042 tftpboot 192.168.201.1 11899582/tftp-deploy-xxarulxr/kernel/image.itp-deploy-xxarulxr/kernel/cmdline
10063 19:57:24.078124
10064 19:57:24.078187 Waiting for link
10065 19:57:24.238408
10066 19:57:24.238533 R8152: Initializing
10067 19:57:24.238596
10068 19:57:24.242373 Version 6 (ocp_data = 5c30)
10069 19:57:24.242453
10070 19:57:24.245006 R8152: Done initializing
10071 19:57:24.245085
10072 19:57:24.245149 Adding net device
10073 19:57:26.149187
10074 19:57:26.149342 done.
10075 19:57:26.149409
10076 19:57:26.149526 MAC: 00:24:32:30:78:ff
10077 19:57:26.149604
10078 19:57:26.151605 Sending DHCP discover... done.
10079 19:57:26.151686
10080 19:57:26.154946 Waiting for reply... done.
10081 19:57:26.155028
10082 19:57:26.158169 Sending DHCP request... done.
10083 19:57:26.158248
10084 19:57:26.162806 Waiting for reply... done.
10085 19:57:26.162885
10086 19:57:26.162948 My ip is 192.168.201.21
10087 19:57:26.163006
10088 19:57:26.166144 The DHCP server ip is 192.168.201.1
10089 19:57:26.166224
10090 19:57:26.172749 TFTP server IP predefined by user: 192.168.201.1
10091 19:57:26.172828
10092 19:57:26.179680 Bootfile predefined by user: 11899582/tftp-deploy-xxarulxr/kernel/image.itb
10093 19:57:26.179761
10094 19:57:26.182639 Sending tftp read request... done.
10095 19:57:26.182725
10096 19:57:26.186820 Waiting for the transfer...
10097 19:57:26.186902
10098 19:57:26.766409 00000000 ################################################################
10099 19:57:26.766589
10100 19:57:27.332254 00080000 ################################################################
10101 19:57:27.332399
10102 19:57:27.910773 00100000 ################################################################
10103 19:57:27.910922
10104 19:57:28.498693 00180000 ################################################################
10105 19:57:28.498842
10106 19:57:29.094529 00200000 ################################################################
10107 19:57:29.094679
10108 19:57:29.664088 00280000 ################################################################
10109 19:57:29.664239
10110 19:57:30.205557 00300000 ################################################################
10111 19:57:30.205707
10112 19:57:30.749927 00380000 ################################################################
10113 19:57:30.750059
10114 19:57:31.289654 00400000 ################################################################
10115 19:57:31.289879
10116 19:57:31.860936 00480000 ################################################################
10117 19:57:31.861199
10118 19:57:32.438422 00500000 ################################################################
10119 19:57:32.438617
10120 19:57:33.031724 00580000 ################################################################
10121 19:57:33.031919
10122 19:57:33.616194 00600000 ################################################################
10123 19:57:33.616390
10124 19:57:34.211079 00680000 ################################################################
10125 19:57:34.211247
10126 19:57:34.795588 00700000 ################################################################
10127 19:57:34.795744
10128 19:57:35.392774 00780000 ################################################################
10129 19:57:35.392949
10130 19:57:35.978563 00800000 ################################################################
10131 19:57:35.978717
10132 19:57:36.577168 00880000 ################################################################
10133 19:57:36.577334
10134 19:57:37.159465 00900000 ################################################################
10135 19:57:37.159618
10136 19:57:37.742735 00980000 ################################################################
10137 19:57:37.742938
10138 19:57:38.336185 00a00000 ################################################################
10139 19:57:38.336379
10140 19:57:38.935606 00a80000 ################################################################
10141 19:57:38.935797
10142 19:57:39.507406 00b00000 ################################################################
10143 19:57:39.507638
10144 19:57:40.072715 00b80000 ################################################################
10145 19:57:40.072876
10146 19:57:40.639096 00c00000 ################################################################
10147 19:57:40.639306
10148 19:57:41.200762 00c80000 ################################################################
10149 19:57:41.200987
10150 19:57:41.766776 00d00000 ################################################################
10151 19:57:41.766918
10152 19:57:42.356735 00d80000 ################################################################
10153 19:57:42.356887
10154 19:57:42.954193 00e00000 ################################################################
10155 19:57:42.954337
10156 19:57:43.559107 00e80000 ################################################################
10157 19:57:43.559276
10158 19:57:44.158349 00f00000 ################################################################
10159 19:57:44.158502
10160 19:57:44.748741 00f80000 ################################################################
10161 19:57:44.748886
10162 19:57:45.356744 01000000 ################################################################
10163 19:57:45.356888
10164 19:57:45.958941 01080000 ################################################################
10165 19:57:45.959089
10166 19:57:46.566740 01100000 ################################################################
10167 19:57:46.566890
10168 19:57:47.167104 01180000 ################################################################
10169 19:57:47.167263
10170 19:57:47.755489 01200000 ################################################################
10171 19:57:47.755642
10172 19:57:48.304187 01280000 ################################################################
10173 19:57:48.304333
10174 19:57:48.890551 01300000 ################################################################
10175 19:57:48.890694
10176 19:57:49.483058 01380000 ################################################################
10177 19:57:49.483206
10178 19:57:50.065076 01400000 ################################################################
10179 19:57:50.065219
10180 19:57:50.646217 01480000 ################################################################
10181 19:57:50.646352
10182 19:57:51.229308 01500000 ################################################################
10183 19:57:51.229544
10184 19:57:51.801541 01580000 ################################################################
10185 19:57:51.801676
10186 19:57:52.396482 01600000 ################################################################
10187 19:57:52.396632
10188 19:57:52.991750 01680000 ################################################################
10189 19:57:52.991903
10190 19:57:53.597549 01700000 ################################################################
10191 19:57:53.597693
10192 19:57:54.185254 01780000 ################################################################
10193 19:57:54.185411
10194 19:57:54.778190 01800000 ################################################################
10195 19:57:54.778391
10196 19:57:55.364287 01880000 ################################################################
10197 19:57:55.364444
10198 19:57:55.960243 01900000 ################################################################
10199 19:57:55.960400
10200 19:57:56.563984 01980000 ################################################################
10201 19:57:56.564140
10202 19:57:57.159995 01a00000 ################################################################
10203 19:57:57.160150
10204 19:57:57.758384 01a80000 ################################################################
10205 19:57:57.758581
10206 19:57:58.324542 01b00000 ################################################################
10207 19:57:58.324697
10208 19:57:58.879969 01b80000 ################################################################
10209 19:57:58.880127
10210 19:57:59.429483 01c00000 ################################################################
10211 19:57:59.429642
10212 19:57:59.995370 01c80000 ################################################################
10213 19:57:59.995585
10214 19:58:00.558865 01d00000 ################################################################
10215 19:58:00.559015
10216 19:58:01.107887 01d80000 ################################################################
10217 19:58:01.108044
10218 19:58:01.669141 01e00000 ################################################################
10219 19:58:01.669292
10220 19:58:02.247268 01e80000 ################################################################
10221 19:58:02.247470
10222 19:58:02.821148 01f00000 ################################################################
10223 19:58:02.821363
10224 19:58:03.406259 01f80000 ################################################################
10225 19:58:03.406443
10226 19:58:03.968464 02000000 ################################################################
10227 19:58:03.968615
10228 19:58:04.530231 02080000 ################################################################
10229 19:58:04.530386
10230 19:58:05.079605 02100000 ################################################################
10231 19:58:05.079745
10232 19:58:05.630919 02180000 ################################################################
10233 19:58:05.631072
10234 19:58:06.170852 02200000 ################################################################
10235 19:58:06.171001
10236 19:58:06.750700 02280000 ################################################################
10237 19:58:06.750851
10238 19:58:07.332922 02300000 ################################################################
10239 19:58:07.333068
10240 19:58:07.912193 02380000 ################################################################
10241 19:58:07.912338
10242 19:58:08.495931 02400000 ################################################################
10243 19:58:08.496106
10244 19:58:09.085537 02480000 ################################################################
10245 19:58:09.085690
10246 19:58:09.646501 02500000 ################################################################
10247 19:58:09.646641
10248 19:58:10.212172 02580000 ################################################################
10249 19:58:10.212330
10250 19:58:10.759605 02600000 ################################################################
10251 19:58:10.759750
10252 19:58:11.340311 02680000 ################################################################
10253 19:58:11.340476
10254 19:58:11.913842 02700000 ################################################################
10255 19:58:11.913975
10256 19:58:12.495171 02780000 ################################################################
10257 19:58:12.495305
10258 19:58:13.146596 02800000 ################################################################
10259 19:58:13.146728
10260 19:58:13.857993 02880000 ################################################################
10261 19:58:13.858621
10262 19:58:14.559956 02900000 ################################################################
10263 19:58:14.560452
10264 19:58:15.180259 02980000 ################################################################
10265 19:58:15.180418
10266 19:58:15.752876 02a00000 ################################################################
10267 19:58:15.753060
10268 19:58:16.320693 02a80000 ################################################################
10269 19:58:16.320852
10270 19:58:16.869828 02b00000 ################################################################
10271 19:58:16.869985
10272 19:58:17.425309 02b80000 ################################################################
10273 19:58:17.425469
10274 19:58:17.979709 02c00000 ################################################################
10275 19:58:17.979874
10276 19:58:18.561020 02c80000 ################################################################
10277 19:58:18.561191
10278 19:58:19.147947 02d00000 ################################################################
10279 19:58:19.148138
10280 19:58:19.749000 02d80000 ################################################################
10281 19:58:19.749143
10282 19:58:20.343878 02e00000 ################################################################
10283 19:58:20.344013
10284 19:58:20.937284 02e80000 ################################################################
10285 19:58:20.937438
10286 19:58:21.514032 02f00000 ################################################################
10287 19:58:21.514181
10288 19:58:22.109701 02f80000 ################################################################
10289 19:58:22.109870
10290 19:58:22.238511 03000000 ############### done.
10291 19:58:22.238637
10292 19:58:22.242167 The bootfile was 50448622 bytes long.
10293 19:58:22.242250
10294 19:58:22.245095 Sending tftp read request... done.
10295 19:58:22.245178
10296 19:58:22.248850 Waiting for the transfer...
10297 19:58:22.248932
10298 19:58:22.252024 00000000 # done.
10299 19:58:22.252107
10300 19:58:22.258867 Command line loaded dynamically from TFTP file: 11899582/tftp-deploy-xxarulxr/kernel/cmdline
10301 19:58:22.258950
10302 19:58:22.272124 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10303 19:58:22.272210
10304 19:58:22.272274 Loading FIT.
10305 19:58:22.272333
10306 19:58:22.274958 Image ramdisk-1 has 39351787 bytes.
10307 19:58:22.275039
10308 19:58:22.278570 Image fdt-1 has 47278 bytes.
10309 19:58:22.278651
10310 19:58:22.281445 Image kernel-1 has 11047522 bytes.
10311 19:58:22.281525
10312 19:58:22.291312 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10313 19:58:22.291403
10314 19:58:22.308226 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10315 19:58:22.308314
10316 19:58:22.314928 Choosing best match conf-1 for compat google,spherion-rev2.
10317 19:58:22.315009
10318 19:58:22.322672 Connected to device vid:did:rid of 1ae0:0028:00
10319 19:58:22.331031
10320 19:58:22.334295 tpm_get_response: command 0x17b, return code 0x0
10321 19:58:22.334377
10322 19:58:22.337244 ec_init: CrosEC protocol v3 supported (256, 248)
10323 19:58:22.341694
10324 19:58:22.345144 tpm_cleanup: add release locality here.
10325 19:58:22.345226
10326 19:58:22.345291 Shutting down all USB controllers.
10327 19:58:22.347885
10328 19:58:22.347966 Removing current net device
10329 19:58:22.348030
10330 19:58:22.354646 Exiting depthcharge with code 4 at timestamp: 91765328
10331 19:58:22.354729
10332 19:58:22.357844 LZMA decompressing kernel-1 to 0x821a6718
10333 19:58:22.357926
10334 19:58:22.361506 LZMA decompressing kernel-1 to 0x40000000
10335 19:58:23.749462
10336 19:58:23.749603 jumping to kernel
10337 19:58:23.750128 end: 2.2.4 bootloader-commands (duration 00:01:04) [common]
10338 19:58:23.750230 start: 2.2.5 auto-login-action (timeout 00:03:21) [common]
10339 19:58:23.750306 Setting prompt string to ['Linux version [0-9]']
10340 19:58:23.750375 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10341 19:58:23.750442 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10342 19:58:23.831166
10343 19:58:23.834679 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10344 19:58:23.838189 start: 2.2.5.1 login-action (timeout 00:03:21) [common]
10345 19:58:23.838281 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10346 19:58:23.838353 Setting prompt string to []
10347 19:58:23.838432 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10348 19:58:23.838506 Using line separator: #'\n'#
10349 19:58:23.838565 No login prompt set.
10350 19:58:23.838627 Parsing kernel messages
10351 19:58:23.838682 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10352 19:58:23.838778 [login-action] Waiting for messages, (timeout 00:03:21)
10353 19:58:23.857831 [ 0.000000] Linux version 6.1.59-cip8-rt4 (KernelCI@build-j84202-arm64-gcc-10-defconfig-arm64-chromebook-st8dj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023
10354 19:58:23.860876 [ 0.000000] random: crng init done
10355 19:58:23.867543 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10356 19:58:23.871244 [ 0.000000] efi: UEFI not found.
10357 19:58:23.877550 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10358 19:58:23.884314 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10359 19:58:23.894086 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10360 19:58:23.903981 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10361 19:58:23.910591 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10362 19:58:23.917199 [ 0.000000] printk: bootconsole [mtk8250] enabled
10363 19:58:23.923547 [ 0.000000] NUMA: No NUMA configuration found
10364 19:58:23.930295 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10365 19:58:23.934397 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10366 19:58:23.936914 [ 0.000000] Zone ranges:
10367 19:58:23.943633 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10368 19:58:23.946768 [ 0.000000] DMA32 empty
10369 19:58:23.953718 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10370 19:58:23.957233 [ 0.000000] Movable zone start for each node
10371 19:58:23.959926 [ 0.000000] Early memory node ranges
10372 19:58:23.966947 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10373 19:58:23.973527 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10374 19:58:23.980055 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10375 19:58:23.986421 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10376 19:58:23.993403 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10377 19:58:23.999839 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10378 19:58:24.055660 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10379 19:58:24.062179 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10380 19:58:24.069105 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10381 19:58:24.072168 [ 0.000000] psci: probing for conduit method from DT.
10382 19:58:24.078846 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10383 19:58:24.082312 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10384 19:58:24.088662 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10385 19:58:24.092136 [ 0.000000] psci: SMC Calling Convention v1.2
10386 19:58:24.098793 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10387 19:58:24.102343 [ 0.000000] Detected VIPT I-cache on CPU0
10388 19:58:24.108675 [ 0.000000] CPU features: detected: GIC system register CPU interface
10389 19:58:24.115212 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10390 19:58:24.122252 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10391 19:58:24.128793 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10392 19:58:24.135175 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10393 19:58:24.145160 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10394 19:58:24.148562 [ 0.000000] alternatives: applying boot alternatives
10395 19:58:24.155033 [ 0.000000] Fallback order for Node 0: 0
10396 19:58:24.161887 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10397 19:58:24.164831 [ 0.000000] Policy zone: Normal
10398 19:58:24.178131 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10399 19:58:24.187750 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10400 19:58:24.200278 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10401 19:58:24.210059 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10402 19:58:24.217087 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10403 19:58:24.220138 <6>[ 0.000000] software IO TLB: area num 8.
10404 19:58:24.277183 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10405 19:58:24.426574 <6>[ 0.000000] Memory: 7930996K/8385536K available (17984K kernel code, 4116K rwdata, 17476K rodata, 8448K init, 615K bss, 421772K reserved, 32768K cma-reserved)
10406 19:58:24.433149 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10407 19:58:24.439724 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10408 19:58:24.443306 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10409 19:58:24.449654 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10410 19:58:24.456283 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10411 19:58:24.459293 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10412 19:58:24.469539 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10413 19:58:24.476745 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10414 19:58:24.479568 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10415 19:58:24.487230 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10416 19:58:24.490703 <6>[ 0.000000] GICv3: 608 SPIs implemented
10417 19:58:24.497710 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10418 19:58:24.500642 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10419 19:58:24.504288 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10420 19:58:24.513798 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10421 19:58:24.523752 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10422 19:58:24.537297 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10423 19:58:24.543705 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10424 19:58:24.553245 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10425 19:58:24.566329 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10426 19:58:24.572615 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10427 19:58:24.579240 <6>[ 0.009180] Console: colour dummy device 80x25
10428 19:58:24.589633 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10429 19:58:24.596270 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10430 19:58:24.599709 <6>[ 0.029247] LSM: Security Framework initializing
10431 19:58:24.605917 <6>[ 0.034214] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10432 19:58:24.615980 <6>[ 0.042029] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10433 19:58:24.625494 <6>[ 0.051436] cblist_init_generic: Setting adjustable number of callback queues.
10434 19:58:24.628968 <6>[ 0.058878] cblist_init_generic: Setting shift to 3 and lim to 1.
10435 19:58:24.638969 <6>[ 0.065254] cblist_init_generic: Setting adjustable number of callback queues.
10436 19:58:24.645423 <6>[ 0.072727] cblist_init_generic: Setting shift to 3 and lim to 1.
10437 19:58:24.648901 <6>[ 0.079165] rcu: Hierarchical SRCU implementation.
10438 19:58:24.655303 <6>[ 0.079167] rcu: Max phase no-delay instances is 1000.
10439 19:58:24.661698 <6>[ 0.079191] printk: bootconsole [mtk8250] printing thread started
10440 19:58:24.668777 <6>[ 0.097479] EFI services will not be available.
10441 19:58:24.672135 <6>[ 0.097677] smp: Bringing up secondary CPUs ...
10442 19:58:24.678221 <6>[ 0.097985] Detected VIPT I-cache on CPU1
10443 19:58:24.685137 <6>[ 0.098052] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10444 19:58:24.691952 <6>[ 0.098083] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10445 19:58:24.701192 <6>[ 0.125974] Detected VIPT I-cache on CPU2
10446 19:58:24.707878 <6>[ 0.126024] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10447 19:58:24.714489 <6>[ 0.126041] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10448 19:58:24.721580 <6>[ 0.126307] Detected VIPT I-cache on CPU3
10449 19:58:24.727837 <6>[ 0.126354] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10450 19:58:24.734190 <6>[ 0.126369] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10451 19:58:24.737749 <6>[ 0.126679] CPU features: detected: Spectre-v4
10452 19:58:24.744136 <6>[ 0.126685] CPU features: detected: Spectre-BHB
10453 19:58:24.747065 <6>[ 0.126689] Detected PIPT I-cache on CPU4
10454 19:58:24.753633 <6>[ 0.126747] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10455 19:58:24.760641 <6>[ 0.126764] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10456 19:58:24.767096 <6>[ 0.127059] Detected PIPT I-cache on CPU5
10457 19:58:24.773129 <6>[ 0.127120] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10458 19:58:24.780230 <6>[ 0.127137] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10459 19:58:24.783643 <6>[ 0.127413] Detected PIPT I-cache on CPU6
10460 19:58:24.793119 <6>[ 0.127476] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10461 19:58:24.799785 <6>[ 0.127492] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10462 19:58:24.803331 <6>[ 0.127781] Detected PIPT I-cache on CPU7
10463 19:58:24.809980 <6>[ 0.127846] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10464 19:58:24.816378 <6>[ 0.127862] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10465 19:58:24.822744 <6>[ 0.127909] smp: Brought up 1 node, 8 CPUs
10466 19:58:24.826524 <6>[ 0.127914] SMP: Total of 8 processors activated.
10467 19:58:24.833144 <6>[ 0.127917] CPU features: detected: 32-bit EL0 Support
10468 19:58:24.839833 <6>[ 0.127919] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10469 19:58:24.846093 <6>[ 0.127921] CPU features: detected: Common not Private translations
10470 19:58:24.852712 <6>[ 0.127923] CPU features: detected: CRC32 instructions
10471 19:58:24.859538 <6>[ 0.127926] CPU features: detected: RCpc load-acquire (LDAPR)
10472 19:58:24.862554 <6>[ 0.127927] CPU features: detected: LSE atomic instructions
10473 19:58:24.869764 <6>[ 0.127929] CPU features: detected: Privileged Access Never
10474 19:58:24.875955 <6>[ 0.127930] CPU features: detected: RAS Extension Support
10475 19:58:24.882730 <6>[ 0.127933] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10476 19:58:24.885532 <6>[ 0.128005] CPU: All CPU(s) started at EL2
10477 19:58:24.892514 <6>[ 0.128007] alternatives: applying system-wide alternatives
10478 19:58:24.896041 <6>[ 0.141063] devtmpfs: initialized
10479 19:58:24.921685 �a hash table entries: 512 (order 0, 4096 bytes)
10480 19:58:24.928133 <6>[ 0.355679] pri<ntk: console [ttyS0] printing thread started
10481 19:58:24.931808 6>[ 0.225640] pnp: PnP ACPI: disabled
10482 19:58:24.934761 <6>[ 0.355686] printk: console [ttyS0] enabled
10483 19:58:24.941259 <6>[ 0.355690] printk: bootconsole [mtk8250] disabled
10484 19:58:24.944730 <6>[ 0.365259] printk: bootconsole [mtk8250] printing thread stopped
10485 19:58:24.951374 <6>[ 0.366521] SuperH (H)SCI(F) driver initialized
10486 19:58:24.954592 <6>[ 0.366988] msm_serial: driver initialized
10487 19:58:24.964582 <6>[ 0.371647] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10488 19:58:24.971147 <6>[ 0.371676] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10489 19:58:24.981534 <6>[ 0.371705] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10490 19:58:24.990793 <6>[ 0.371734] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10491 19:58:25.001380 <6>[ 0.371756] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10492 19:58:25.007227 <6>[ 0.371784] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10493 19:58:25.019643 <6>[ 0.371812] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10494 19:58:25.036540 <6>[ 0.371940] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10495 19:58:25.037076 <6>[ 0.371970] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10496 19:58:25.040488 <6>[ 0.385007] loop: module loaded
10497 19:58:25.044978 <6>[ 0.387602] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10498 19:58:25.052441 <4>[ 0.412357] mtk-pmic-keys: Failed to locate of_node [id: -1]
10499 19:58:25.058352 <6>[ 0.413380] megasas: 07.719.03.00-rc1
10500 19:58:25.061267 <6>[ 0.426136] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10501 19:58:25.064656 <6>[ 0.428795] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10502 19:58:25.071342 <6>[ 0.441009] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10503 19:58:25.081441 <6>[ 0.494590] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10504 19:58:26.395565 <6>[ 1.824935] Freeing initrd memory: 38428K
10505 19:58:26.403081 <6>[ 1.831065] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10506 19:58:26.409814 <6>[ 1.835740] tun: Universal TUN/TAP device driver, 1.6
10507 19:58:26.413261 <6>[ 1.836478] thunder_xcv, ver 1.0
10508 19:58:26.416920 <6>[ 1.836495] thunder_bgx, ver 1.0
10509 19:58:26.419595 <6>[ 1.836508] nicpf, ver 1.0
10510 19:58:26.426321 <6>[ 1.837564] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10511 19:58:26.432909 <6>[ 1.837567] hns3: Copyright (c) 2017 Huawei Corporation.
10512 19:58:26.436679 <6>[ 1.837592] hclge is initializing
10513 19:58:26.443096 <6>[ 1.837604] e1000: Intel(R) PRO/1000 Network Driver
10514 19:58:26.447112 <6>[ 1.837606] e1000: Copyright (c) 1999-2006 Intel Corporation.
10515 19:58:26.453733 <6>[ 1.837625] e1000e: Intel(R) PRO/1000 Network Driver
10516 19:58:26.457453 <6>[ 1.837627] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10517 19:58:26.464163 <6>[ 1.837643] igb: Intel(R) Gigabit Ethernet Network Driver
10518 19:58:26.470833 <6>[ 1.837645] igb: Copyright (c) 2007-2014 Intel Corporation.
10519 19:58:26.478150 <6>[ 1.837658] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10520 19:58:26.484755 <6>[ 1.837660] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10521 19:58:26.487707 <6>[ 1.837955] sky2: driver version 1.30
10522 19:58:26.491282 <6>[ 1.839016] VFIO - User Level meta-driver version: 0.3
10523 19:58:26.498052 <6>[ 1.841849] usbcore: registered new interface driver usb-storage
10524 19:58:26.504396 <6>[ 1.842027] usbcore: registered new device driver onboard-usb-hub
10525 19:58:26.510917 <6>[ 1.844774] mt6397-rtc mt6359-rtc: registered as rtc0
10526 19:58:26.517621 <6>[ 1.844927] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-28T19:58:26 UTC (1698523106)
10527 19:58:26.524612 <6>[ 1.845547] i2c_dev: i2c /dev entries driver
10528 19:58:26.531057 <6>[ 1.852689] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10529 19:58:26.537284 <6>[ 1.867698] cpu cpu0: EM: created perf domain
10530 19:58:26.541102 <6>[ 1.868008] cpu cpu4: EM: created perf domain
10531 19:58:26.547264 <6>[ 1.871690] sdhci: Secure Digital Host Controller Interface driver
10532 19:58:26.550946 <6>[ 1.871691] sdhci: Copyright(c) Pierre Ossman
10533 19:58:26.557164 <6>[ 1.872056] Synopsys Designware Multimedia Card Interface Driver
10534 19:58:26.564051 <6>[ 1.872434] sdhci-pltfm: SDHCI platform and OF driver helper
10535 19:58:26.570686 <6>[ 1.876743] ledtrig-cpu: registered to indicate activity on CPUs
10536 19:58:26.573594 <6>[ 1.877081] mmc0: CQHCI version 5.10
10537 19:58:26.580764 <6>[ 1.877615] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10538 19:58:26.587030 <6>[ 1.877890] usbcore: registered new interface driver usbhid
10539 19:58:26.590224 <6>[ 1.877891] usbhid: USB HID core driver
10540 19:58:26.597146 <6>[ 1.878009] spi_master spi0: will run message pump with realtime priority
10541 19:58:26.610021 <6>[ 1.906124] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10542 19:58:26.623112 <6>[ 1.908743] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10543 19:58:26.629989 <6>[ 1.909784] cros-ec-spi spi0.0: Chrome EC device registered
10544 19:58:26.639753 <6>[ 1.926182] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10545 19:58:26.643227 <6>[ 1.928395] NET: Registered PF_PACKET protocol family
10546 19:58:26.649818 <6>[ 1.928483] 9pnet: Installing 9P2000 support
10547 19:58:26.653225 <5>[ 1.928523] Key type dns_resolver registered
10548 19:58:26.656632 <6>[ 1.928821] registered taskstats version 1
10549 19:58:26.663151 <5>[ 1.928837] Loading compiled-in X.509 certificates
10550 19:58:26.672539 <4>[ 1.950429] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10551 19:58:26.682752 <4>[ 1.950607] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10552 19:58:26.689212 <3>[ 1.950618] debugfs: File 'uA_load' in directory '/' already present!
10553 19:58:26.695867 <3>[ 1.950625] debugfs: File 'min_uV' in directory '/' already present!
10554 19:58:26.702498 <3>[ 1.950628] debugfs: File 'max_uV' in directory '/' already present!
10555 19:58:26.712733 <3>[ 1.950631] debugfs: File 'constraint_flags' in directory '/' already present!
10556 19:58:26.719278 <3>[ 1.952676] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10557 19:58:26.725713 <6>[ 1.960682] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10558 19:58:26.732587 <6>[ 1.961263] xhci-mtk 11200000.usb: xHCI Host Controller
10559 19:58:26.739086 <6>[ 1.961282] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10560 19:58:26.749004 <6>[ 1.961522] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10561 19:58:26.755454 <6>[ 1.961566] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10562 19:58:26.758974 <6>[ 1.961667] xhci-mtk 11200000.usb: xHCI Host Controller
10563 19:58:26.769071 <6>[ 1.961674] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10564 19:58:26.775249 <6>[ 1.961681] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10565 19:58:26.778577 <6>[ 1.962348] hub 1-0:1.0: USB hub found
10566 19:58:26.782057 <6>[ 1.962373] hub 1-0:1.0: 1 port detected
10567 19:58:26.791638 <6>[ 1.962596] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10568 19:58:26.794771 <6>[ 1.962858] hub 2-0:1.0: USB hub found
10569 19:58:26.798255 <6>[ 1.962877] hub 2-0:1.0: 1 port detected
10570 19:58:26.804787 <6>[ 1.965919] mtk-msdc 11f70000.mmc: Got CD GPIO
10571 19:58:26.808099 <6>[ 1.971472] mmc0: Command Queue Engine enabled
10572 19:58:26.814717 <6>[ 1.971485] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10573 19:58:26.821147 <6>[ 1.972128] mmcblk0: mmc0:0001 DA4128 116 GiB
10574 19:58:26.824839 <6>[ 1.975564] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10575 19:58:26.831160 <6>[ 1.976573] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10576 19:58:26.837898 <6>[ 1.977328] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10577 19:58:26.844750 <6>[ 1.978096] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10578 19:58:26.851380 <6>[ 1.980821] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10579 19:58:26.857485 <6>[ 1.980826] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10580 19:58:26.867577 <4>[ 1.980988] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10581 19:58:26.874022 <6>[ 1.981635] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10582 19:58:26.883994 <6>[ 1.981639] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10583 19:58:26.890955 <6>[ 1.981760] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10584 19:58:26.901105 <6>[ 1.981771] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10585 19:58:26.907233 <6>[ 1.981776] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10586 19:58:26.916811 <6>[ 1.981784] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10587 19:58:26.923778 <6>[ 1.983208] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10588 19:58:26.933580 <6>[ 1.983226] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10589 19:58:26.940404 <6>[ 1.983232] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10590 19:58:26.949978 <6>[ 1.983238] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10591 19:58:26.957083 <6>[ 1.983244] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10592 19:58:26.966725 <6>[ 1.983251] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10593 19:58:26.973306 <6>[ 1.983257] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10594 19:58:26.983110 <6>[ 1.983263] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10595 19:58:26.989530 <6>[ 1.983270] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10596 19:58:26.999572 <6>[ 1.983276] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10597 19:58:27.009925 <6>[ 1.983283] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10598 19:58:27.016309 <6>[ 1.983289] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10599 19:58:27.026540 <6>[ 1.983295] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10600 19:58:27.032867 <6>[ 1.983301] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10601 19:58:27.042890 <6>[ 1.983307] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10602 19:58:27.049221 <6>[ 1.983810] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10603 19:58:27.055698 <6>[ 1.984640] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10604 19:58:27.062174 <6>[ 1.985189] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10605 19:58:27.069042 <6>[ 1.985837] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10606 19:58:27.075418 <6>[ 1.986487] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10607 19:58:27.082247 <6>[ 1.986675] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10608 19:58:27.092083 <6>[ 1.986687] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10609 19:58:27.101971 <6>[ 1.986692] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10610 19:58:27.112317 <6>[ 1.986698] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10611 19:58:27.122110 <6>[ 1.986703] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10612 19:58:27.128629 <6>[ 1.986713] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10613 19:58:27.138329 <6>[ 1.986720] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10614 19:58:27.148360 <6>[ 1.986725] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10615 19:58:27.158100 <6>[ 1.986729] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10616 19:58:27.168243 <6>[ 1.986736] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10617 19:58:27.177927 <6>[ 1.986741] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10618 19:58:27.187752 <6>[ 1.987362] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10619 19:58:27.194830 <6>[ 2.381580] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10620 19:58:27.197671 <6>[ 2.533407] hub 1-1:1.0: USB hub found
10621 19:58:27.200952 <6>[ 2.533790] hub 1-1:1.0: 4 ports detected
10622 19:58:27.234571 <6>[ 2.657809] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10623 19:58:27.255564 <6>[ 2.683070] hub 2-1:1.0: USB hub found
10624 19:58:27.258571 <6>[ 2.683502] hub 2-1:1.0: 3 ports detected
10625 19:58:27.422803 <6>[ 2.845732] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10626 19:58:27.543225 <6>[ 2.973278] hub 1-1.4:1.0: USB hub found
10627 19:58:27.546533 <6>[ 2.973709] hub 1-1.4:1.0: 2 ports detected
10628 19:58:27.630678 <6>[ 3.053925] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10629 19:58:27.838329 <6>[ 3.261706] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10630 19:58:28.023065 <6>[ 3.445710] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10631 19:58:38.842996 <6>[ 14.274770] ALSA device list:
10632 19:58:38.849931 <6>[ 14.274793] No soundcards found.
10633 19:58:38.853461 <6>[ 14.279442] Freeing unused kernel memory: 8448K
10634 19:58:38.856216 <6>[ 14.279530] Run /init as init process
10635 19:58:38.878097 <6>[ 14.308948] NET: Registered PF_INET6 protocol family
10636 19:58:38.881554 <6>[ 14.309792] Segment Routing with IPv6
10637 19:58:38.887724 <6>[ 14.309809] In-situ OAM (IOAM) with IPv6
10638 19:58:38.892187
10639 19:58:38.915136 Welcome to [1mDebian GNU/Linux <30>[ 14.326262] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10640 19:58:38.921553 <30>[ 14.326749] systemd[1]: Detected architecture arm64.
10641 19:58:38.924881 11 (bullseye)[0m!
10642 19:58:38.924966
10643 19:58:38.946008 <30>[ 14.373704] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10644 19:58:39.109469 <30>[ 14.534529] systemd[1]: Queued start job for default target Graphical Interface.
10645 19:58:39.142902 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.570638] systemd[1]: Created slice system-getty.slice.
10646 19:58:39.146355 m-getty.slice[0m.
10647 19:58:39.169575 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.594293] systemd[1]: Created slice system-modprobe.slice.
10648 19:58:39.169663 m-modprobe.slice[0m.
10649 19:58:39.191532 [[0;32m OK [0m] Created slic<30>[ 14.619302] systemd[1]: Created slice system-serial\x2dgetty.slice.
10650 19:58:39.197785 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10651 19:58:39.215629 [[0;32m OK [0m] Created slic<30>[ 14.643413] systemd[1]: Created slice User and Session Slice.
10652 19:58:39.218855 e [0;1;39mUser and Session Slice[0m.
10653 19:58:39.242352 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 14.666580] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10654 19:58:39.245161 ssword …ts to Console Directory Watch[0m.
10655 19:58:39.269264 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 14.693922] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10656 19:58:39.272584 sword R…uests to Wall Directory Watch[0m.
10657 19:58:39.296801 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 14.717781] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10658 19:58:39.306455 l Encrypted Volu<30>[ 14.717998] systemd[1]: Reached target Local Encrypted Volumes.
10659 19:58:39.306546 mes[0m.
10660 19:58:39.326155 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 14.754254] systemd[1]: Reached target Paths.
10661 19:58:39.326244 s[0m.
10662 19:58:39.348956 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 14.773715] systemd[1]: Reached target Remote File Systems.
10663 19:58:39.349074 te File Systems[0m.
10664 19:58:39.370254 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 14.798106] systemd[1]: Reached target Slices.
10665 19:58:39.370338 es[0m.
10666 19:58:39.389620 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 14.817757] systemd[1]: Reached target Swap.
10667 19:58:39.389709 [0m.
10668 19:58:39.413369 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 14.838273] systemd[1]: Listening on initctl Compatibility Named Pipe.
10669 19:58:39.416598 l Compatibility Named Pipe[0m.
10670 19:58:39.426870 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 14.853544] systemd[1]: Listening on Journal Audit Socket.
10671 19:58:39.429952 l Audit Socket[0m.
10672 19:58:39.449858 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 14.874300] systemd[1]: Listening on Journal Socket (/dev/log).
10673 19:58:39.449942 l Socket (/dev/log)[0m.
10674 19:58:39.471214 [[0;32m OK [0m] Listening on<30>[ 14.899018] systemd[1]: Listening on Journal Socket.
10675 19:58:39.474538 [0;1;39mJournal Socket[0m.
10676 19:58:39.493542 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 14.918500] systemd[1]: Listening on Network Service Netlink Socket.
10677 19:58:39.496913 k Service Netlink Socket[0m.
10678 19:58:39.517437 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 14.942382] systemd[1]: Listening on udev Control Socket.
10679 19:58:39.517527 ontrol Socket[0m.
10680 19:58:39.539474 [[0;32m OK [0m] Listening on<30>[ 14.966861] systemd[1]: Listening on udev Kernel Socket.
10681 19:58:39.542111 [0;1;39mudev Kernel Socket[0m.
10682 19:58:39.601561 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.026279] systemd[1]: Mounting Huge Pages File System...
10683 19:58:39.601670 m[0m...
10684 19:58:39.623037 Mounting [0;1;39mPOSIX<30>[ 15.050606] systemd[1]: Mounting POSIX Message Queue File System...
10685 19:58:39.625692 Message Queue File System[0m...
10686 19:58:39.650733 Mounting [0;1;39mKerne<30>[ 15.078569] systemd[1]: Mounting Kernel Debug File System...
10687 19:58:39.653796 l Debug File System[0m...
10688 19:58:39.673523 <30>[ 15.098355] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10689 19:58:39.683279 <30>[ 15.103553] systemd[1]: Starting Create list of static device nodes for the current kernel...
10690 19:58:39.690089 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10691 19:58:39.737805 Starting [0;1;39mLoad Kernel Module co<30>[ 15.162441] systemd[1]: Starting Load Kernel Module configfs...
10692 19:58:39.737900 nfigfs[0m...
10693 19:58:39.759176 Starting [0;1;39mLoad <30>[ 15.186689] systemd[1]: Starting Load Kernel Module drm...
10694 19:58:39.761894 Kernel Module drm[0m...
10695 19:58:39.781053 <30>[ 15.206202] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10696 19:58:39.834908 Starting [0;1;39mJourn<30>[ 15.262722] systemd[1]: Starting Journal Service...
10697 19:58:39.835012 al Service[0m...
10698 19:58:39.859132 Starting [0;1;39mLoad <30>[ 15.287120] systemd[1]: Starting Load Kernel Modules...
10699 19:58:39.862437 Kernel Modules[0m...
10700 19:58:39.883687 Starting [0;1;39mRemou<30>[ 15.311584] systemd[1]: Starting Remount Root and Kernel File Systems...
10701 19:58:39.890291 nt Root and Kernel File Systems[0m...
10702 19:58:39.908802 Startin<30>[ 15.336415] systemd[1]: Starting Coldplug All udev Devices...
10703 19:58:39.911775 g [0;1;39mColdplug All udev Devices[0m...
10704 19:58:39.933884 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 15.362152] systemd[1]: Started Journal Service.
10705 19:58:39.937222 vice[0m.
10706 19:58:39.957516 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10707 19:58:39.975024 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10708 19:58:39.992153 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10709 19:58:40.015737 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10710 19:58:40.033355 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10711 19:58:40.054851 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10712 19:58:40.072336 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10713 19:58:40.092936 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10714 19:58:40.106275 See 'systemctl status systemd-remount-fs.service' for details.
10715 19:58:40.159709 Mounting [0;1;39mKernel Configuration File System[0m...
10716 19:58:40.179496 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10717 19:58:40.193450 <46>[ 15.620965] systemd-journald[192]: Received client request to flush runtime journal.
10718 19:58:40.204261 Starting [0;1;39mLoad/Save Random Seed[0m...
10719 19:58:40.223621 Starting [0;1;39mApply Kernel Variables[0m...
10720 19:58:40.242995 Starting [0;1;39mCreate System Users[0m...
10721 19:58:40.264215 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10722 19:58:40.279414 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10723 19:58:40.299292 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10724 19:58:40.312177 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10725 19:58:40.327790 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10726 19:58:40.344396 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10727 19:58:40.394589 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10728 19:58:40.418416 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10729 19:58:40.434326 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10730 19:58:40.450367 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10731 19:58:40.511373 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10732 19:58:40.534205 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10733 19:58:40.554841 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10734 19:58:40.579325 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10735 19:58:40.636316 Starting [0;1;39mNetwork Service[0m...
10736 19:58:40.658917 Starting [0;1;39mNetwork Time Synchronization[0m...
10737 19:58:40.678609 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10738 19:58:40.703643 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10739 19:58:40.729218 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10740 19:58:40.745033 <6>[ 16.171636] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10741 19:58:40.751828 <6>[ 16.171728] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10742 19:58:40.761668 <6>[ 16.171739] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10743 19:58:40.771825 <3>[ 16.172018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 19:58:40.778455 <3>[ 16.172064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 19:58:40.784912 <3>[ 16.172083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 19:58:40.795117 <6>[ 16.172414] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10747 19:58:40.801489 [[0;32m OK [<6>[ 16.194308] remoteproc remoteproc0: scp is available
10748 19:58:40.808402 0m] Created slic<6>[ 16.194488] remoteproc remoteproc0: powering up scp
10749 19:58:40.814627 <6>[ 16.194501] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10750 19:58:40.821741 <6>[ 16.194538] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10751 19:58:40.827932 <3>[ 16.202241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 19:58:40.837839 e [0;1;39msyste<3>[ 16.202267] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 19:58:40.847780 <3>[ 16.202270] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 19:58:40.854477 <3>[ 16.202275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 19:58:40.864179 <3>[ 16.202279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 19:58:40.870934 <3>[ 16.236872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 19:58:40.877627 <3>[ 16.275403] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 19:58:40.887617 <3>[ 16.275428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 19:58:40.893832 <3>[ 16.275432] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 19:58:40.900651 <4>[ 16.277156] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10761 19:58:40.911027 <3>[ 16.278519] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 19:58:40.918075 m-systemd\x2dbac<4>[ 16.278554] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10763 19:58:40.928044 klight.slice[0m<3>[ 16.278569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 19:58:40.928126 .
10765 19:58:40.938622 <3>[ 16.278578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 19:58:40.944955 <3>[ 16.278591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 19:58:40.951821 <3>[ 16.278600] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 19:58:40.962412 <3>[ 16.281162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 19:58:40.965280 <6>[ 16.282890] usbcore: registered new interface driver r8152
10770 19:58:40.972265 <6>[ 16.303966] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10771 19:58:40.978713 <6>[ 16.303982] pci_bus 0000:00: root bus resource [bus 00-ff]
10772 19:58:40.985963 <6>[ 16.303991] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10773 19:58:40.995738 <6>[ 16.303993] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10774 19:58:41.002339 <6>[ 16.304040] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10775 19:58:41.009208 <6>[ 16.304054] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10776 19:58:41.015634 <6>[ 16.304118] pci 0000:00:00.0: supports D1 D2
10777 19:58:41.022102 <6>[ 16.304120] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10778 19:58:41.028716 <6>[ 16.305852] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10779 19:58:41.035779 <6>[ 16.320022] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10780 19:58:41.045839 <6>[ 16.320056] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10781 19:58:41.052826 <6>[ 16.320066] remoteproc remoteproc0: remote processor scp is now up
10782 19:58:41.059623 <6>[ 16.325011] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10783 19:58:41.065726 <6>[ 16.327542] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10784 19:58:41.072689 <6>[ 16.327604] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10785 19:58:41.079381 <6>[ 16.327631] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10786 19:58:41.089195 <6>[ 16.327649] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10787 19:58:41.092519 <6>[ 16.327787] pci 0000:01:00.0: supports D1 D2
10788 19:58:41.102712 Startin<6>[ 16.327793] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10789 19:58:41.109332 <4>[ 16.330614] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10790 19:58:41.115907 <4>[ 16.330614] Fallback method does not support PEC.
10791 19:58:41.122426 <3>[ 16.347673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10792 19:58:41.132672 <3>[ 16.370985] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10793 19:58:41.136084 <6>[ 16.373002] mc: Linux media interface: v0.10
10794 19:58:41.146565 <6>[ 16.393873] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10795 19:58:41.152811 <6>[ 16.395172] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10796 19:58:41.162651 g [0;1;39mLoad/<6>[ 16.395319] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10797 19:58:41.172997 Save Screen …o<6>[ 16.395329] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10798 19:58:41.182640 f leds:white:kbd<6>[ 16.395348] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10799 19:58:41.189129 <6>[ 16.395364] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10800 19:58:41.200483 _backlight[0m..<6>[ 16.395380] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10801 19:58:41.203425 <6>[ 16.395397] pci 0000:00:00.0: PCI bridge to [bus 01]
10802 19:58:41.210369 <6>[ 16.395407] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10803 19:58:41.220443 <6>[ 16.397988] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10804 19:58:41.224256 .
10805 19:58:41.227356 <6>[ 16.398491] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10806 19:58:41.233946 <6>[ 16.398580] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10807 19:58:41.244312 <3>[ 16.399444] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10808 19:58:41.254723 <6>[ 16.401828] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10809 19:58:41.261437 <3>[ 16.424712] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10810 19:58:41.271820 Starting [0;1;39mNetwo<6>[ 16.429809] videodev: Linux video capture interface: v2.00
10811 19:58:41.281913 rk Name Resoluti<4>[ 16.442578] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10812 19:58:41.288833 <4>[ 16.442599] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10813 19:58:41.288937 on[0m...
10814 19:58:41.295654 <6>[ 16.445386] usbcore: registered new interface driver cdc_ether
10815 19:58:41.302764 <6>[ 16.484894] usbcore: registered new interface driver r8153_ecm
10816 19:58:41.312425 <3>[ 16.485761] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10817 19:58:41.315556 <6>[ 16.505706] r8152 2-1.3:1.0 eth0: v1.12.13
10818 19:58:41.322261 <6>[ 16.521137] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10819 19:58:41.331811 <3>[ 16.522167] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10820 19:58:41.335224 <6>[ 16.525489] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10821 19:58:41.338625 <6>[ 16.552240] Bluetooth: Core ver 2.22
10822 19:58:41.345092 <6>[ 16.552372] NET: Registered PF_BLUETOOTH protocol family
10823 19:58:41.351876 <6>[ 16.552377] Bluetooth: HCI device and connection manager initialized
10824 19:58:41.358782 <6>[ 16.552419] Bluetooth: HCI socket layer initialized
10825 19:58:41.362068 <6>[ 16.552428] Bluetooth: L2CAP socket layer initialized
10826 19:58:41.368122 <6>[ 16.552446] Bluetooth: SCO socket layer initialized
10827 19:58:41.375178 <6>[ 16.563544] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10828 19:58:41.387906 <6>[ 16.567665] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10829 19:58:41.394754 <6>[ 16.569665] usbcore: registered new interface driver uvcvideo
10830 19:58:41.401685 <3>[ 16.581321] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10831 19:58:41.407831 <6>[ 16.600393] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10832 19:58:41.414776 <6>[ 16.624785] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10833 19:58:41.421525 <6>[ 16.633858] usbcore: registered new interface driver btusb
10834 19:58:41.431539 <4>[ 16.634242] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10835 19:58:41.437702 <3>[ 16.634257] Bluetooth: hci0: Failed to load firmware file (-2)
10836 19:58:41.444532 <3>[ 16.634264] Bluetooth: hci0: Failed to set up firmware (-2)
10837 19:58:41.454520 <4>[ 16.634269] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10838 19:58:41.461254 <6>[ 16.635950] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10839 19:58:41.471240 <6>[ 16.639600] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10840 19:58:41.477889 <3>[ 16.640857] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10841 19:58:41.487859 <3>[ 16.641704] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10842 19:58:41.497465 <3>[ 16.663660] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 19:58:41.503754 <5>[ 16.788343] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10844 19:58:41.510466 <5>[ 16.800387] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10845 19:58:41.520333 <4>[ 16.800522] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10846 19:58:41.523652 <6>[ 16.800533] cfg80211: failed to load regulatory.db
10847 19:58:41.533455 <6>[ 16.906671] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10848 19:58:41.536692 <6>[ 16.906775] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10849 19:58:41.543370 <6>[ 16.925824] mt7921e 0000:01:00.0: ASIC revision: 79610010
10850 19:58:41.550069 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10851 19:58:41.570719 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10852 19:58:41.596286 <4>[ 17.020692] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10853 19:58:41.603042 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10854 19:58:41.623767 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10855 19:58:41.704788 <4>[ 17.127977] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10856 19:58:41.785822 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10857 19:58:41.812752 [[0;32m OK [0m] Reached target [0;1;39mNetw<4>[ 17.235559] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10858 19:58:41.812858 ork[0m.
10859 19:58:41.833360 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10860 19:58:41.846279 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10861 19:58:41.866140 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10862 19:58:41.878175 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10863 19:58:41.894194 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10864 19:58:41.920611 [[0;32m OK [0m] Started [0;1;39mDiscard unu<4>[ 17.343501] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10865 19:58:41.924367 sed blocks once a week[0m.
10866 19:58:41.937842 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10867 19:58:41.958333 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10868 19:58:41.970058 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10869 19:58:41.986220 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10870 19:58:42.006458 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10871 19:58:42.028141 <4>[ 17.452080] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10872 19:58:42.063270 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10873 19:58:42.097848 Starting [0;1;39mUser Login Management[0m...
10874 19:58:42.138103 Starting [0;1;39mPermi<4>[ 17.561364] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10875 19:58:42.138205 t User Sessions[0m...
10876 19:58:42.167973 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10877 19:58:42.185980 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10878 19:58:42.206572 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10879 19:58:42.222040 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10880 19:58:42.249096 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10881 19:58:42.264745 <4>[ 17.686209] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10882 19:58:42.272632 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10883 19:58:42.290741 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10884 19:58:42.308061 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10885 19:58:42.327168 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10886 19:58:42.375419 <4>[ 17.796031] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10887 19:58:42.387918 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10888 19:58:42.421378 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10889 19:58:42.437765
10890 19:58:42.437865
10891 19:58:42.441232 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10892 19:58:42.441332
10893 19:58:42.443868 debian-bullseye-arm64 login: root (automatic login)
10894 19:58:42.443955
10895 19:58:42.444032
10896 19:58:42.489285 <4>[ 17.905468] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10897 19:58:42.499524 Linux debian-bullseye-arm64 6.1.59-cip8-rt4 #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023 aarch64
10898 19:58:42.499611
10899 19:58:42.505826 The programs included with the Debian GNU/Linux system are free software;
10900 19:58:42.512545 the exact distribution terms for each program are described in the
10901 19:58:42.516087 individual files in /usr/share/doc/*/copyright.
10902 19:58:42.516167
10903 19:58:42.522580 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10904 19:58:42.525463 permitted by applicable law.
10905 19:58:42.525834 Matched prompt #10: / #
10907 19:58:42.526038 Setting prompt string to ['/ #']
10908 19:58:42.526131 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10910 19:58:42.526323 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10911 19:58:42.526409 start: 2.2.6 expect-shell-connection (timeout 00:03:03) [common]
10912 19:58:42.526477 Setting prompt string to ['/ #']
10913 19:58:42.526537 Forcing a shell prompt, looking for ['/ #']
10915 19:58:42.576749 / #
10916 19:58:42.576864 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10917 19:58:42.576966 Waiting using forced prompt support (timeout 00:02:30)
10918 19:58:42.591803 <4>[ 18.012488] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10919 19:58:42.591890
10920 19:58:42.595547 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10921 19:58:42.595652 start: 2.2.7 export-device-env (timeout 00:03:03) [common]
10922 19:58:42.595786 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10923 19:58:42.595873 end: 2.2 depthcharge-retry (duration 00:01:57) [common]
10924 19:58:42.595957 end: 2 depthcharge-action (duration 00:01:57) [common]
10925 19:58:42.596045 start: 3 lava-test-retry (timeout 00:07:44) [common]
10926 19:58:42.596128 start: 3.1 lava-test-shell (timeout 00:07:44) [common]
10927 19:58:42.596235 Using namespace: common
10929 19:58:42.696509 / # #
10930 19:58:42.696652 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10931 19:58:42.696789 #<3>[ 18.118071] mt7921e 0000:01:00.0: hardware init failed
10932 19:58:42.701463
10933 19:58:42.701730 Using /lava-11899582
10935 19:58:42.802038 / # export SHELL=/bin/sh
10936 19:58:42.802304 <6>[ 18.141320] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
10937 19:58:42.802392 <6>[ 18.141879] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10938 19:58:42.807438 export SHELL=/bin/sh
10940 19:58:42.908035 / # . /lava-11899582/environment
10941 19:58:42.914475 . /lava-11899582/environment
10943 19:58:43.016081 / # /lava-11899582/bin/lava-test-runner /lava-11899582/0
10944 19:58:43.016212 Test shell timeout: 10s (minimum of the action and connection timeout)
10945 19:58:43.022118 /lava-11899582/bin/lava-test-runner /lava-11899582/0
10946 19:58:43.044432 + export TESTRUN_ID=0_v4l2-compliance-uvc
10947 19:58:43.048050 + cd /lava-11899582/0/tests/0_v4l2-compliance-uvc
10948 19:58:43.048132 + cat uuid
10949 19:58:43.051049 + UUID=11899582_1.5.2.3.1
10950 19:58:43.051156 + set +x
10951 19:58:43.057777 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 11899582_1.5.2.3.1>
10952 19:58:43.058049 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 11899582_1.5.2.3.1
10953 19:58:43.058158 Starting test lava.0_v4l2-compliance-uvc (11899582_1.5.2.3.1)
10954 19:58:43.058276 Skipping test definition patterns.
10955 19:58:43.060830 + /usr/bin/v4l2-parser.sh -d uvcvideo
10956 19:58:43.067636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10957 19:58:43.067724 device: /dev/video0
10958 19:58:43.067961 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10960 19:58:49.556168 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
10961 19:58:49.571006 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
10962 19:58:49.578943
10963 19:58:49.594766 Compliance test for uvcvideo device /dev/video0:
10964 19:58:49.605226
10965 19:58:49.619346 Driver Info:
10966 19:58:49.631986 Driver name : uvcvideo
10967 19:58:49.648684 Card type : HD User Facing: HD User Facing
10968 19:58:49.661293 Bus info : usb-11200000.usb-1.4.1
10969 19:58:49.669351 Driver version : 6.1.59
10970 19:58:49.684177 Capabilities : 0x84a00001
10971 19:58:49.695800 Metadata Capture
10972 19:58:49.706790 Streaming
10973 19:58:49.718223 Extended Pix Format
10974 19:58:49.727535 Device Capabilities
10975 19:58:49.738767 Device Caps : 0x04200001
10976 19:58:49.751846 Streaming
10977 19:58:49.766697 Extended Pix Format
10978 19:58:49.777559 Media Driver Info:
10979 19:58:49.788227 Driver name : uvcvideo
10980 19:58:49.802503 Model : HD User Facing: HD User Facing
10981 19:58:49.809206 Serial : 200901010001
10982 19:58:49.826885 Bus info : usb-11200000.usb-1.4.1
10983 19:58:49.834391 Media version : 6.1.59
10984 19:58:49.848327 Hardware revision: 0x00009758 (38744)
10985 19:58:49.855990 Driver version : 6.1.59
10986 19:58:49.869943 Interface Info:
10987 19:58:49.886203 <LAVA_SIGNAL_TESTSET START Interface-Info>
10988 19:58:49.886721 ID : 0x03000002
10989 19:58:49.887328 Received signal: <TESTSET> START Interface-Info
10990 19:58:49.887718 Starting test_set Interface-Info
10991 19:58:49.896398 Type : V4L Video
10992 19:58:49.911585 Entity Info:
10993 19:58:49.918573 <LAVA_SIGNAL_TESTSET STOP>
10994 19:58:49.919354 Received signal: <TESTSET> STOP
10995 19:58:49.919751 Closing test_set Interface-Info
10996 19:58:49.927549 <LAVA_SIGNAL_TESTSET START Entity-Info>
10997 19:58:49.928334 Received signal: <TESTSET> START Entity-Info
10998 19:58:49.928688 Starting test_set Entity-Info
10999 19:58:49.930563 ID : 0x00000001 (1)
11000 19:58:49.942763 Name : HD User Facing: HD User Facing
11001 19:58:49.948182 Function : V4L2 I/O
11002 19:58:49.963708 Flags : default
11003 19:58:49.976011 Pad 0x01000007 : 0: Sink
11004 19:58:49.997978 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11005 19:58:50.002537
11006 19:58:50.015065 Required ioctls:
11007 19:58:50.024699 <LAVA_SIGNAL_TESTSET STOP>
11008 19:58:50.025486 Received signal: <TESTSET> STOP
11009 19:58:50.025838 Closing test_set Entity-Info
11010 19:58:50.034577 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11011 19:58:50.035361 Received signal: <TESTSET> START Required-ioctls
11012 19:58:50.035752 Starting test_set Required-ioctls
11013 19:58:50.037811 test MC information (see 'Media Driver Info' above): OK
11014 19:58:50.063606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11015 19:58:50.064405 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11017 19:58:50.067075 test VIDIOC_QUERYCAP: OK
11018 19:58:50.085226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11019 19:58:50.086005 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11021 19:58:50.088435 test invalid ioctls: OK
11022 19:58:50.110540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11023 19:58:50.111066
11024 19:58:50.111723 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11026 19:58:50.119585 Allow for multiple opens:
11027 19:58:50.127111 <LAVA_SIGNAL_TESTSET STOP>
11028 19:58:50.127965 Received signal: <TESTSET> STOP
11029 19:58:50.128322 Closing test_set Required-ioctls
11030 19:58:50.136945 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11031 19:58:50.137731 Received signal: <TESTSET> START Allow-for-multiple-opens
11032 19:58:50.138105 Starting test_set Allow-for-multiple-opens
11033 19:58:50.140044 test second /dev/video0 open: OK
11034 19:58:50.160787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11035 19:58:50.161569 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11037 19:58:50.163927 test VIDIOC_QUERYCAP: OK
11038 19:58:50.187099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11039 19:58:50.187876 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11041 19:58:50.190503 test VIDIOC_G/S_PRIORITY: OK
11042 19:58:50.212193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11043 19:58:50.212957 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11045 19:58:50.215543 test for unlimited opens: OK
11046 19:58:50.237815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11047 19:58:50.238274
11048 19:58:50.239044 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11050 19:58:50.250090 Debug ioctls:
11051 19:58:50.259022 <LAVA_SIGNAL_TESTSET STOP>
11052 19:58:50.259726 Received signal: <TESTSET> STOP
11053 19:58:50.260225 Closing test_set Allow-for-multiple-opens
11054 19:58:50.271132 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11055 19:58:50.271922 Received signal: <TESTSET> START Debug-ioctls
11056 19:58:50.272277 Starting test_set Debug-ioctls
11057 19:58:50.275144 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11058 19:58:50.298265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11059 19:58:50.299049 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11061 19:58:50.304993 test VIDIOC_LOG_STATUS: OK (Not Supported)
11062 19:58:50.322260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11063 19:58:50.322787
11064 19:58:50.323419 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11066 19:58:50.333355 Input ioctls:
11067 19:58:50.339804 <LAVA_SIGNAL_TESTSET STOP>
11068 19:58:50.340596 Received signal: <TESTSET> STOP
11069 19:58:50.340962 Closing test_set Debug-ioctls
11070 19:58:50.349507 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11071 19:58:50.350294 Received signal: <TESTSET> START Input-ioctls
11072 19:58:50.350650 Starting test_set Input-ioctls
11073 19:58:50.353202 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11074 19:58:50.378588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11075 19:58:50.379402 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11077 19:58:50.381464 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11078 19:58:50.399803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11079 19:58:50.400596 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11081 19:58:50.406401 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11082 19:58:50.431581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11083 19:58:50.432366 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11085 19:58:50.437921 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11086 19:58:50.458349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11087 19:58:50.459130 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11089 19:58:50.460906 test VIDIOC_G/S/ENUMINPUT: OK
11090 19:58:50.487422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11091 19:58:50.488206 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11093 19:58:50.490699 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11094 19:58:50.512271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11095 19:58:50.513054 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11097 19:58:50.515663 Inputs: 1 Audio Inputs: 0 Tuners: 0
11098 19:58:50.524174
11099 19:58:50.540192 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11100 19:58:50.567326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11101 19:58:50.568159 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11103 19:58:50.573676 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11104 19:58:50.598702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11105 19:58:50.599507 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11107 19:58:50.605062 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11108 19:58:50.627469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11109 19:58:50.628404 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11111 19:58:50.633973 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11112 19:58:50.653722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11113 19:58:50.654513 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11115 19:58:50.659825 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11116 19:58:50.678708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11117 19:58:50.679516 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11119 19:58:50.682099
11120 19:58:50.697931 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11121 19:58:50.724763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11122 19:58:50.725554 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11124 19:58:50.730941 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11125 19:58:50.755266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11126 19:58:50.756156 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11128 19:58:50.757565 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11129 19:58:50.778022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11130 19:58:50.778776 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11132 19:58:50.781622 test VIDIOC_G/S_EDID: OK (Not Supported)
11133 19:58:50.804065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11134 19:58:50.804580
11135 19:58:50.805176 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11137 19:58:50.816148 Control ioctls (Input 0):
11138 19:58:50.824452 <LAVA_SIGNAL_TESTSET STOP>
11139 19:58:50.825231 Received signal: <TESTSET> STOP
11140 19:58:50.825583 Closing test_set Input-ioctls
11141 19:58:50.834096 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11142 19:58:50.834919 Received signal: <TESTSET> START Control-ioctls-Input-0
11143 19:58:50.835281 Starting test_set Control-ioctls-Input-0
11144 19:58:50.837090 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11145 19:58:50.862812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11146 19:58:50.863577 test VIDIOC_QUERYCTRL: OK
11147 19:58:50.864207 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11149 19:58:50.883602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11150 19:58:50.884388 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11152 19:58:50.886527 test VIDIOC_G/S_CTRL: OK
11153 19:58:50.911595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11154 19:58:50.912384 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11156 19:58:50.915236 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11157 19:58:50.939802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11158 19:58:50.940587 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11160 19:58:50.946355 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11161 19:58:50.968576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11162 19:58:50.969356 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11164 19:58:50.972274 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11165 19:58:50.992028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11166 19:58:50.992819 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11168 19:58:50.995123 Standard Controls: 16 Private Controls: 0
11169 19:58:51.003960
11170 19:58:51.016797 Format ioctls (Input 0):
11171 19:58:51.026679 <LAVA_SIGNAL_TESTSET STOP>
11172 19:58:51.027510 Received signal: <TESTSET> STOP
11173 19:58:51.027947 Closing test_set Control-ioctls-Input-0
11174 19:58:51.036648 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11175 19:58:51.037420 Received signal: <TESTSET> START Format-ioctls-Input-0
11176 19:58:51.037797 Starting test_set Format-ioctls-Input-0
11177 19:58:51.040334 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11178 19:58:51.065241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11179 19:58:51.066024 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11181 19:58:51.068193 test VIDIOC_G/S_PARM: OK
11182 19:58:51.086914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11183 19:58:51.087730 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11185 19:58:51.089995 test VIDIOC_G_FBUF: OK (Not Supported)
11186 19:58:51.116721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11187 19:58:51.117484 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11189 19:58:51.120051 test VIDIOC_G_FMT: OK
11190 19:58:51.144701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11191 19:58:51.145491 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11193 19:58:51.148104 test VIDIOC_TRY_FMT: OK
11194 19:58:51.168951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11195 19:58:51.169737 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11197 19:58:51.175442 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11198 19:58:51.179785 test VIDIOC_S_FMT: OK
11199 19:58:51.209066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11200 19:58:51.209869 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11202 19:58:51.212299 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11203 19:58:51.234551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11204 19:58:51.235345 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11206 19:58:51.238043 test Cropping: OK (Not Supported)
11207 19:58:51.262403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11208 19:58:51.263191 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11210 19:58:51.265726 test Composing: OK (Not Supported)
11211 19:58:51.287321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11212 19:58:51.288368 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11214 19:58:51.290622 test Scaling: OK (Not Supported)
11215 19:58:51.311646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11216 19:58:51.312153
11217 19:58:51.312750 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11219 19:58:51.328806 Codec ioctls (Input 0):
11220 19:58:51.336313 <LAVA_SIGNAL_TESTSET STOP>
11221 19:58:51.337092 Received signal: <TESTSET> STOP
11222 19:58:51.337449 Closing test_set Format-ioctls-Input-0
11223 19:58:51.346738 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11224 19:58:51.347971 Received signal: <TESTSET> START Codec-ioctls-Input-0
11225 19:58:51.348377 Starting test_set Codec-ioctls-Input-0
11226 19:58:51.349735 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11227 19:58:51.375276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11228 19:58:51.376077 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11230 19:58:51.382494 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11231 19:58:51.401392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11232 19:58:51.402179 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11234 19:58:51.408089 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11235 19:58:51.426170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11236 19:58:51.426682
11237 19:58:51.427281 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11239 19:58:51.438138 Buffer ioctls (Input 0):
11240 19:58:51.445409 <LAVA_SIGNAL_TESTSET STOP>
11241 19:58:51.446209 Received signal: <TESTSET> STOP
11242 19:58:51.446578 Closing test_set Codec-ioctls-Input-0
11243 19:58:51.455173 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11244 19:58:51.456028 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11245 19:58:51.456390 Starting test_set Buffer-ioctls-Input-0
11246 19:58:51.458672 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11247 19:58:51.489607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11248 19:58:51.490140 test VIDIOC_EXPBUF: OK
11249 19:58:51.490748 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11251 19:58:51.510684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11252 19:58:51.511483 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11254 19:58:51.514401 test Requests: OK (Not Supported)
11255 19:58:51.541117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11256 19:58:51.541637
11257 19:58:51.542237 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11259 19:58:51.551759 Test input 0:
11260 19:58:51.566557
11261 19:58:51.576754 Streaming ioctls:
11262 19:58:51.583819 <LAVA_SIGNAL_TESTSET STOP>
11263 19:58:51.584601 Received signal: <TESTSET> STOP
11264 19:58:51.584955 Closing test_set Buffer-ioctls-Input-0
11265 19:58:51.594231 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11266 19:58:51.595019 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11267 19:58:51.595380 Starting test_set Streaming-ioctls_Test-input-0
11268 19:58:51.597234 test read/write: OK (Not Supported)
11269 19:58:51.619961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11270 19:58:51.620745 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11272 19:58:51.622548 test blocking wait: OK
11273 19:58:51.645002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11274 19:58:51.645768 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11276 19:58:51.655278 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11277 19:58:51.658295 test MMAP (no poll): FAIL
11278 19:58:51.682085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11279 19:58:51.682891 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11281 19:58:51.691978 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11282 19:58:51.692485 test MMAP (select): FAIL
11283 19:58:51.716931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11284 19:58:51.717691 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11286 19:58:51.727138 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11287 19:58:51.730137 test MMAP (epoll): FAIL
11288 19:58:51.755371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11289 19:58:51.755924
11290 19:58:51.756527 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11292 19:58:51.768253
11293 19:58:51.962706
11294 19:58:51.971911 test USERPTR (no poll): OK
11295 19:58:52.000878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11296 19:58:52.001399
11297 19:58:52.001996 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11299 19:58:52.014144
11300 19:58:52.212015
11301 19:58:52.220699 test USERPTR (select): OK
11302 19:58:52.245619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11303 19:58:52.246426 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11305 19:58:52.251735 test DMABUF: Cannot test, specify --expbuf-device
11306 19:58:52.256194
11307 19:58:52.272646 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11308 19:58:52.276308 <LAVA_TEST_RUNNER EXIT>
11309 19:58:52.277090 ok: lava_test_shell seems to have completed
11310 19:58:52.277469 Marking unfinished test run as failed
11312 19:58:52.282059 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11313 19:58:52.282697 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11314 19:58:52.283333 end: 3 lava-test-retry (duration 00:00:10) [common]
11315 19:58:52.283840 start: 4 finalize (timeout 00:07:34) [common]
11316 19:58:52.284295 start: 4.1 power-off (timeout 00:00:30) [common]
11317 19:58:52.285056 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11318 19:58:52.370287 >> Command sent successfully.
11319 19:58:52.375529 Returned 0 in 0 seconds
11320 19:58:52.476507 end: 4.1 power-off (duration 00:00:00) [common]
11322 19:58:52.477888 start: 4.2 read-feedback (timeout 00:07:34) [common]
11323 19:58:52.479078 Listened to connection for namespace 'common' for up to 1s
11324 19:58:53.479703 Finalising connection for namespace 'common'
11325 19:58:53.480328 Disconnecting from shell: Finalise
11326 19:58:53.480700 / #
11327 19:58:53.581636 end: 4.2 read-feedback (duration 00:00:01) [common]
11328 19:58:53.582269 end: 4 finalize (duration 00:00:01) [common]
11329 19:58:53.582850 Cleaning after the job
11330 19:58:53.583340 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/ramdisk
11331 19:58:53.609304 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/kernel
11332 19:58:53.628157 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/dtb
11333 19:58:53.628460 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899582/tftp-deploy-xxarulxr/modules
11334 19:58:53.638531 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11899582
11335 19:58:53.706681 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11899582
11336 19:58:53.706855 Job finished correctly