Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 34
- Kernel Warnings: 20
- Boot result: PASS
- Errors: 1
1 11:48:26.297851 lava-dispatcher, installed at version: 2023.10
2 11:48:26.298053 start: 0 validate
3 11:48:26.298183 Start time: 2023-11-24 11:48:26.298176+00:00 (UTC)
4 11:48:26.298301 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:48:26.298456 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:48:26.561693 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:48:26.562448 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:48:26.834163 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:48:26.834984 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:48:27.106060 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:48:27.106820 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:48:27.386357 validate duration: 1.09
14 11:48:27.387721 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:48:27.388259 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:48:27.388834 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:48:27.389470 Not decompressing ramdisk as can be used compressed.
18 11:48:27.389966 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 11:48:27.390331 saving as /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/ramdisk/rootfs.cpio.gz
20 11:48:27.390693 total size: 34390042 (32 MB)
21 11:48:27.395833 progress 0 % (0 MB)
22 11:48:27.427640 progress 5 % (1 MB)
23 11:48:27.441226 progress 10 % (3 MB)
24 11:48:27.451608 progress 15 % (4 MB)
25 11:48:27.460339 progress 20 % (6 MB)
26 11:48:27.469050 progress 25 % (8 MB)
27 11:48:27.477787 progress 30 % (9 MB)
28 11:48:27.486513 progress 35 % (11 MB)
29 11:48:27.495093 progress 40 % (13 MB)
30 11:48:27.504083 progress 45 % (14 MB)
31 11:48:27.512981 progress 50 % (16 MB)
32 11:48:27.521850 progress 55 % (18 MB)
33 11:48:27.530472 progress 60 % (19 MB)
34 11:48:27.539285 progress 65 % (21 MB)
35 11:48:27.548101 progress 70 % (22 MB)
36 11:48:27.556938 progress 75 % (24 MB)
37 11:48:27.565652 progress 80 % (26 MB)
38 11:48:27.574404 progress 85 % (27 MB)
39 11:48:27.583221 progress 90 % (29 MB)
40 11:48:27.591753 progress 95 % (31 MB)
41 11:48:27.600220 progress 100 % (32 MB)
42 11:48:27.600395 32 MB downloaded in 0.21 s (156.38 MB/s)
43 11:48:27.600600 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:48:27.600880 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:48:27.600966 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:48:27.601048 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:48:27.601187 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:48:27.601260 saving as /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/kernel/Image
50 11:48:27.601320 total size: 49107456 (46 MB)
51 11:48:27.601384 No compression specified
52 11:48:27.602537 progress 0 % (0 MB)
53 11:48:27.615485 progress 5 % (2 MB)
54 11:48:27.628426 progress 10 % (4 MB)
55 11:48:27.641231 progress 15 % (7 MB)
56 11:48:27.653791 progress 20 % (9 MB)
57 11:48:27.666440 progress 25 % (11 MB)
58 11:48:27.679067 progress 30 % (14 MB)
59 11:48:27.691374 progress 35 % (16 MB)
60 11:48:27.703850 progress 40 % (18 MB)
61 11:48:27.716487 progress 45 % (21 MB)
62 11:48:27.729147 progress 50 % (23 MB)
63 11:48:27.741694 progress 55 % (25 MB)
64 11:48:27.754225 progress 60 % (28 MB)
65 11:48:27.766775 progress 65 % (30 MB)
66 11:48:27.779527 progress 70 % (32 MB)
67 11:48:27.791885 progress 75 % (35 MB)
68 11:48:27.804477 progress 80 % (37 MB)
69 11:48:27.817064 progress 85 % (39 MB)
70 11:48:27.829606 progress 90 % (42 MB)
71 11:48:27.841818 progress 95 % (44 MB)
72 11:48:27.854111 progress 100 % (46 MB)
73 11:48:27.854308 46 MB downloaded in 0.25 s (185.12 MB/s)
74 11:48:27.854456 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:48:27.854679 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:48:27.854767 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:48:27.854854 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:48:27.854989 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:48:27.855057 saving as /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/dtb/mt8192-asurada-spherion-r0.dtb
81 11:48:27.855116 total size: 47278 (0 MB)
82 11:48:27.855176 No compression specified
83 11:48:27.856284 progress 69 % (0 MB)
84 11:48:27.856597 progress 100 % (0 MB)
85 11:48:27.856753 0 MB downloaded in 0.00 s (27.58 MB/s)
86 11:48:27.856873 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:48:27.857091 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:48:27.857173 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:48:27.857253 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:48:27.857367 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:48:27.857436 saving as /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/modules/modules.tar
93 11:48:27.857494 total size: 8624756 (8 MB)
94 11:48:27.857554 Using unxz to decompress xz
95 11:48:27.861681 progress 0 % (0 MB)
96 11:48:27.882309 progress 5 % (0 MB)
97 11:48:27.905733 progress 10 % (0 MB)
98 11:48:27.928817 progress 15 % (1 MB)
99 11:48:27.951636 progress 20 % (1 MB)
100 11:48:27.975308 progress 25 % (2 MB)
101 11:48:28.000111 progress 30 % (2 MB)
102 11:48:28.026463 progress 35 % (2 MB)
103 11:48:28.049388 progress 40 % (3 MB)
104 11:48:28.073128 progress 45 % (3 MB)
105 11:48:28.098125 progress 50 % (4 MB)
106 11:48:28.122237 progress 55 % (4 MB)
107 11:48:28.146647 progress 60 % (4 MB)
108 11:48:28.173572 progress 65 % (5 MB)
109 11:48:28.198226 progress 70 % (5 MB)
110 11:48:28.221398 progress 75 % (6 MB)
111 11:48:28.248299 progress 80 % (6 MB)
112 11:48:28.273537 progress 85 % (7 MB)
113 11:48:28.298102 progress 90 % (7 MB)
114 11:48:28.329297 progress 95 % (7 MB)
115 11:48:28.356699 progress 100 % (8 MB)
116 11:48:28.361558 8 MB downloaded in 0.50 s (16.32 MB/s)
117 11:48:28.361813 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:48:28.362106 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:48:28.362214 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:48:28.362327 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:48:28.362419 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:48:28.362528 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:48:28.362777 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp
125 11:48:28.362956 makedir: /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin
126 11:48:28.363103 makedir: /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/tests
127 11:48:28.363243 makedir: /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/results
128 11:48:28.363377 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-add-keys
129 11:48:28.363544 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-add-sources
130 11:48:28.363690 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-background-process-start
131 11:48:28.363839 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-background-process-stop
132 11:48:28.363988 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-common-functions
133 11:48:28.364160 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-echo-ipv4
134 11:48:28.364329 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-install-packages
135 11:48:28.364499 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-installed-packages
136 11:48:28.364648 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-os-build
137 11:48:28.364793 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-probe-channel
138 11:48:28.364937 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-probe-ip
139 11:48:28.365080 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-target-ip
140 11:48:28.365221 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-target-mac
141 11:48:28.365367 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-target-storage
142 11:48:28.365539 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-test-case
143 11:48:28.365709 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-test-event
144 11:48:28.365882 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-test-feedback
145 11:48:28.366052 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-test-raise
146 11:48:28.366222 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-test-reference
147 11:48:28.366393 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-test-runner
148 11:48:28.366562 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-test-set
149 11:48:28.366733 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-test-shell
150 11:48:28.366907 Updating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-install-packages (oe)
151 11:48:28.367104 Updating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/bin/lava-installed-packages (oe)
152 11:48:28.367267 Creating /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/environment
153 11:48:28.367405 LAVA metadata
154 11:48:28.367511 - LAVA_JOB_ID=12074062
155 11:48:28.367591 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:48:28.367721 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:48:28.367796 skipped lava-vland-overlay
158 11:48:28.367895 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:48:28.367996 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:48:28.368097 skipped lava-multinode-overlay
161 11:48:28.368220 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:48:28.368346 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:48:28.368461 Loading test definitions
164 11:48:28.368607 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:48:28.368727 Using /lava-12074062 at stage 0
166 11:48:28.369149 uuid=12074062_1.5.2.3.1 testdef=None
167 11:48:28.369271 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:48:28.369399 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:48:28.370129 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:48:28.370496 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:48:28.371390 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:48:28.371671 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:48:28.372524 runner path: /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/0/tests/0_cros-ec test_uuid 12074062_1.5.2.3.1
176 11:48:28.372689 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:48:28.373015 Creating lava-test-runner.conf files
179 11:48:28.373096 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074062/lava-overlay-tsi9pqcp/lava-12074062/0 for stage 0
180 11:48:28.373231 - 0_cros-ec
181 11:48:28.373372 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:48:28.373493 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:48:28.380714 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:48:28.380827 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:48:28.380927 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:48:28.381029 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:48:28.381138 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:48:29.351140 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:48:29.351542 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:48:29.351676 extracting modules file /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074062/extract-overlay-ramdisk-9oofcdmk/ramdisk
191 11:48:29.609681 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:48:29.609860 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:48:29.609980 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074062/compress-overlay-zjy1efhz/overlay-1.5.2.4.tar.gz to ramdisk
194 11:48:29.610061 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074062/compress-overlay-zjy1efhz/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074062/extract-overlay-ramdisk-9oofcdmk/ramdisk
195 11:48:29.616732 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:48:29.616862 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:48:29.616963 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:48:29.617067 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:48:29.617162 Building ramdisk /var/lib/lava/dispatcher/tmp/12074062/extract-overlay-ramdisk-9oofcdmk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074062/extract-overlay-ramdisk-9oofcdmk/ramdisk
200 11:48:30.378546 >> 271067 blocks
201 11:48:34.966501 rename /var/lib/lava/dispatcher/tmp/12074062/extract-overlay-ramdisk-9oofcdmk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/ramdisk/ramdisk.cpio.gz
202 11:48:34.966982 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:48:34.967177 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 11:48:34.967330 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 11:48:34.967489 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/kernel/Image'
206 11:48:46.732359 Returned 0 in 11 seconds
207 11:48:46.833352 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/kernel/image.itb
208 11:48:47.611381 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:48:47.611759 output: Created: Fri Nov 24 11:48:47 2023
210 11:48:47.611866 output: Image 0 (kernel-1)
211 11:48:47.611956 output: Description:
212 11:48:47.612040 output: Created: Fri Nov 24 11:48:47 2023
213 11:48:47.612124 output: Type: Kernel Image
214 11:48:47.612206 output: Compression: lzma compressed
215 11:48:47.612287 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
216 11:48:47.612383 output: Architecture: AArch64
217 11:48:47.612481 output: OS: Linux
218 11:48:47.612620 output: Load Address: 0x00000000
219 11:48:47.612716 output: Entry Point: 0x00000000
220 11:48:47.612810 output: Hash algo: crc32
221 11:48:47.612905 output: Hash value: 43cfb6ad
222 11:48:47.613000 output: Image 1 (fdt-1)
223 11:48:47.613093 output: Description: mt8192-asurada-spherion-r0
224 11:48:47.613185 output: Created: Fri Nov 24 11:48:47 2023
225 11:48:47.613276 output: Type: Flat Device Tree
226 11:48:47.613366 output: Compression: uncompressed
227 11:48:47.613456 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:48:47.613546 output: Architecture: AArch64
229 11:48:47.613637 output: Hash algo: crc32
230 11:48:47.613727 output: Hash value: cc4352de
231 11:48:47.613818 output: Image 2 (ramdisk-1)
232 11:48:47.613908 output: Description: unavailable
233 11:48:47.613998 output: Created: Fri Nov 24 11:48:47 2023
234 11:48:47.614088 output: Type: RAMDisk Image
235 11:48:47.614216 output: Compression: Unknown Compression
236 11:48:47.614306 output: Data Size: 47532051 Bytes = 46418.02 KiB = 45.33 MiB
237 11:48:47.614396 output: Architecture: AArch64
238 11:48:47.614486 output: OS: Linux
239 11:48:47.614576 output: Load Address: unavailable
240 11:48:47.614666 output: Entry Point: unavailable
241 11:48:47.614755 output: Hash algo: crc32
242 11:48:47.614845 output: Hash value: 7acfe0c3
243 11:48:47.614934 output: Default Configuration: 'conf-1'
244 11:48:47.615023 output: Configuration 0 (conf-1)
245 11:48:47.615112 output: Description: mt8192-asurada-spherion-r0
246 11:48:47.615201 output: Kernel: kernel-1
247 11:48:47.615290 output: Init Ramdisk: ramdisk-1
248 11:48:47.615379 output: FDT: fdt-1
249 11:48:47.615468 output: Loadables: kernel-1
250 11:48:47.615557 output:
251 11:48:47.615803 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 11:48:47.615936 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 11:48:47.616079 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 11:48:47.616214 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 11:48:47.616331 No LXC device requested
256 11:48:47.616453 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:48:47.616623 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 11:48:47.616737 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:48:47.616847 Checking files for TFTP limit of 4294967296 bytes.
260 11:48:47.617501 end: 1 tftp-deploy (duration 00:00:20) [common]
261 11:48:47.617640 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:48:47.617765 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:48:47.617937 substitutions:
264 11:48:47.618032 - {DTB}: 12074062/tftp-deploy-yu09ioqk/dtb/mt8192-asurada-spherion-r0.dtb
265 11:48:47.618133 - {INITRD}: 12074062/tftp-deploy-yu09ioqk/ramdisk/ramdisk.cpio.gz
266 11:48:47.618231 - {KERNEL}: 12074062/tftp-deploy-yu09ioqk/kernel/Image
267 11:48:47.618326 - {LAVA_MAC}: None
268 11:48:47.618420 - {PRESEED_CONFIG}: None
269 11:48:47.618514 - {PRESEED_LOCAL}: None
270 11:48:47.618607 - {RAMDISK}: 12074062/tftp-deploy-yu09ioqk/ramdisk/ramdisk.cpio.gz
271 11:48:47.618700 - {ROOT_PART}: None
272 11:48:47.618793 - {ROOT}: None
273 11:48:47.618885 - {SERVER_IP}: 192.168.201.1
274 11:48:47.618977 - {TEE}: None
275 11:48:47.619069 Parsed boot commands:
276 11:48:47.619160 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:48:47.619394 Parsed boot commands: tftpboot 192.168.201.1 12074062/tftp-deploy-yu09ioqk/kernel/image.itb 12074062/tftp-deploy-yu09ioqk/kernel/cmdline
278 11:48:47.619517 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:48:47.619644 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:48:47.619787 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:48:47.619913 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:48:47.620019 Not connected, no need to disconnect.
283 11:48:47.620134 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:48:47.620297 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:48:47.620396 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 11:48:47.624439 Setting prompt string to ['lava-test: # ']
287 11:48:47.624859 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:48:47.624985 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:48:47.625125 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:48:47.625250 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:48:47.625568 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 11:48:52.772204 >> Command sent successfully.
293 11:48:52.783698 Returned 0 in 5 seconds
294 11:48:52.885032 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:48:52.886687 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:48:52.887212 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:48:52.887698 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:48:52.888076 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:48:52.888441 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:48:52.889902 [Enter `^Ec?' for help]
302 11:48:53.056344 panfrost-driver-present RESULT=p
303 11:48:53.057170 F0: 102B 0000
304 11:48:53.057693
305 11:48:53.059267 F3: 1001 0000 [0200]
306 11:48:53.059764
307 11:48:53.060265 F3: 1001 0000
308 11:48:53.060811
309 11:48:53.061271 F7: 102D 0000
310 11:48:53.061715
311 11:48:53.062634 F1: 0000 0000
312 11:48:53.063131
313 11:48:53.063558 V0: 0000 0000 [0001]
314 11:48:53.063926
315 11:48:53.066427 00: 0007 8000
316 11:48:53.067059
317 11:48:53.067563 01: 0000 0000
318 11:48:53.068036
319 11:48:53.068484 BP: 0C00 0209 [0000]
320 11:48:53.069482
321 11:48:53.069963 G0: 1182 0000
322 11:48:53.070452
323 11:48:53.070911 EC: 0000 0021 [4000]
324 11:48:53.072792
325 11:48:53.073272 S7: 0000 0000 [0000]
326 11:48:53.073759
327 11:48:53.076037 CC: 0000 0000 [0001]
328 11:48:53.076754
329 11:48:53.077149 T0: 0000 0040 [010F]
330 11:48:53.077518
331 11:48:53.077860 Jump to BL
332 11:48:53.078195
333 11:48:53.102727
334 11:48:53.103303
335 11:48:53.103688
336 11:48:53.109491 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 11:48:53.112898 ARM64: Exception handlers installed.
338 11:48:53.116674 ARM64: Testing exception
339 11:48:53.119906 ARM64: Done test exception
340 11:48:53.126851 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 11:48:53.137017 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 11:48:53.143683 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 11:48:53.154137 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 11:48:53.160370 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 11:48:53.170576 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 11:48:53.180591 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 11:48:53.187415 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 11:48:53.205445 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 11:48:53.209146 WDT: Last reset was cold boot
350 11:48:53.212243 SPI1(PAD0) initialized at 2873684 Hz
351 11:48:53.215372 SPI5(PAD0) initialized at 992727 Hz
352 11:48:53.218680 VBOOT: Loading verstage.
353 11:48:53.225469 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 11:48:53.229049 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 11:48:53.232192 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 11:48:53.235501 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 11:48:53.243069 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 11:48:53.249688 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 11:48:53.260486 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 11:48:53.261114
361 11:48:53.261487
362 11:48:53.270801 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 11:48:53.274304 ARM64: Exception handlers installed.
364 11:48:53.277448 ARM64: Testing exception
365 11:48:53.278316 ARM64: Done test exception
366 11:48:53.284177 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 11:48:53.287423 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 11:48:53.301574 Probing TPM: . done!
369 11:48:53.302160 TPM ready after 0 ms
370 11:48:53.309081 Connected to device vid:did:rid of 1ae0:0028:00
371 11:48:53.316584 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
372 11:48:53.362611 Initialized TPM device CR50 revision 0
373 11:48:53.377657 tlcl_send_startup: Startup return code is 0
374 11:48:53.378366 TPM: setup succeeded
375 11:48:53.388832 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 11:48:53.397588 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 11:48:53.407197 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 11:48:53.416236 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 11:48:53.419576 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 11:48:53.422872 in-header: 03 07 00 00 08 00 00 00
381 11:48:53.426536 in-data: aa e4 47 04 13 02 00 00
382 11:48:53.429647 Chrome EC: UHEPI supported
383 11:48:53.436310 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 11:48:53.439797 in-header: 03 95 00 00 08 00 00 00
385 11:48:53.443381 in-data: 18 20 20 08 00 00 00 00
386 11:48:53.443949 Phase 1
387 11:48:53.446887 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 11:48:53.454610 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 11:48:53.458063 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 11:48:53.461825 Recovery requested (1009000e)
391 11:48:53.471107 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 11:48:53.476662 tlcl_extend: response is 0
393 11:48:53.486305 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 11:48:53.491156 tlcl_extend: response is 0
395 11:48:53.498431 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 11:48:53.518836 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 11:48:53.526252 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 11:48:53.526841
399 11:48:53.527215
400 11:48:53.536303 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 11:48:53.540272 ARM64: Exception handlers installed.
402 11:48:53.540931 ARM64: Testing exception
403 11:48:53.543240 ARM64: Done test exception
404 11:48:53.563975 pmic_efuse_setting: Set efuses in 11 msecs
405 11:48:53.567168 pmwrap_interface_init: Select PMIF_VLD_RDY
406 11:48:53.573852 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 11:48:53.577228 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 11:48:53.583805 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 11:48:53.587303 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 11:48:53.593963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 11:48:53.597153 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 11:48:53.600338 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 11:48:53.607259 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 11:48:53.610631 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 11:48:53.617031 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 11:48:53.620462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 11:48:53.623905 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 11:48:53.630796 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 11:48:53.636922 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 11:48:53.640759 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 11:48:53.648084 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 11:48:53.651740 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 11:48:53.659558 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 11:48:53.663103 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 11:48:53.670335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 11:48:53.674124 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 11:48:53.681295 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 11:48:53.688452 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 11:48:53.691970 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 11:48:53.695835 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 11:48:53.703009 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 11:48:53.710180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 11:48:53.713716 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 11:48:53.717341 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 11:48:53.721080 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 11:48:53.729060 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 11:48:53.732481 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 11:48:53.736195 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 11:48:53.743708 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 11:48:53.747019 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 11:48:53.754429 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 11:48:53.758365 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 11:48:53.761721 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 11:48:53.768631 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 11:48:53.772585 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 11:48:53.775972 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 11:48:53.779561 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 11:48:53.783399 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 11:48:53.790421 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 11:48:53.794421 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 11:48:53.798224 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 11:48:53.801658 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 11:48:53.805278 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 11:48:53.809285 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 11:48:53.816293 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 11:48:53.819749 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 11:48:53.827117 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 11:48:53.834170 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 11:48:53.841388 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 11:48:53.848914 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 11:48:53.856148 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 11:48:53.859974 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 11:48:53.866696 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 11:48:53.870570 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:48:53.877342 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x19
466 11:48:53.880781 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 11:48:53.888748 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 11:48:53.891906 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 11:48:53.901609 [RTC]rtc_get_frequency_meter,154: input=15, output=764
470 11:48:53.911033 [RTC]rtc_get_frequency_meter,154: input=23, output=949
471 11:48:53.920451 [RTC]rtc_get_frequency_meter,154: input=19, output=856
472 11:48:53.930054 [RTC]rtc_get_frequency_meter,154: input=17, output=810
473 11:48:53.939821 [RTC]rtc_get_frequency_meter,154: input=16, output=787
474 11:48:53.948731 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 11:48:53.958693 [RTC]rtc_get_frequency_meter,154: input=17, output=810
476 11:48:53.962105 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 11:48:53.969765 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 11:48:53.973746 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 11:48:53.977205 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 11:48:53.980573 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 11:48:53.984344 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 11:48:53.988187 ADC[4]: Raw value=670432 ID=5
483 11:48:53.991720 ADC[3]: Raw value=212917 ID=1
484 11:48:53.992204 RAM Code: 0x51
485 11:48:53.995420 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 11:48:54.002591 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 11:48:54.009838 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
488 11:48:54.013452 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
489 11:48:54.017043 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 11:48:54.020649 in-header: 03 07 00 00 08 00 00 00
491 11:48:54.024441 in-data: aa e4 47 04 13 02 00 00
492 11:48:54.027871 Chrome EC: UHEPI supported
493 11:48:54.034968 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 11:48:54.038949 in-header: 03 95 00 00 08 00 00 00
495 11:48:54.042416 in-data: 18 20 20 08 00 00 00 00
496 11:48:54.045826 MRC: failed to locate region type 0.
497 11:48:54.049257 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 11:48:54.052734 DRAM-K: Running full calibration
499 11:48:54.060303 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
500 11:48:54.060926 header.status = 0x0
501 11:48:54.063829 header.version = 0x6 (expected: 0x6)
502 11:48:54.067446 header.size = 0xd00 (expected: 0xd00)
503 11:48:54.071101 header.flags = 0x0
504 11:48:54.074324 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 11:48:54.094591 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 11:48:54.101637 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 11:48:54.102196 dram_init: ddr_geometry: 0
508 11:48:54.105341 [EMI] MDL number = 0
509 11:48:54.108919 [EMI] Get MDL freq = 0
510 11:48:54.109497 dram_init: ddr_type: 0
511 11:48:54.112483 is_discrete_lpddr4: 1
512 11:48:54.116291 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 11:48:54.116819
514 11:48:54.117199
515 11:48:54.117546 [Bian_co] ETT version 0.0.0.1
516 11:48:54.123636 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
517 11:48:54.124119
518 11:48:54.127367 dramc_set_vcore_voltage set vcore to 650000
519 11:48:54.127952 Read voltage for 800, 4
520 11:48:54.131178 Vio18 = 0
521 11:48:54.131657 Vcore = 650000
522 11:48:54.132037 Vdram = 0
523 11:48:54.132389 Vddq = 0
524 11:48:54.134722 Vmddr = 0
525 11:48:54.135299 dram_init: config_dvfs: 1
526 11:48:54.142111 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 11:48:54.145780 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 11:48:54.149407 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 11:48:54.152857 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 11:48:54.157086 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 11:48:54.160555 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 11:48:54.164156 MEM_TYPE=3, freq_sel=18
533 11:48:54.168034 sv_algorithm_assistance_LP4_1600
534 11:48:54.171411 ============ PULL DRAM RESETB DOWN ============
535 11:48:54.175213 ========== PULL DRAM RESETB DOWN end =========
536 11:48:54.179070 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 11:48:54.182587 ===================================
538 11:48:54.186389 LPDDR4 DRAM CONFIGURATION
539 11:48:54.189989 ===================================
540 11:48:54.190466 EX_ROW_EN[0] = 0x0
541 11:48:54.194014 EX_ROW_EN[1] = 0x0
542 11:48:54.194601 LP4Y_EN = 0x0
543 11:48:54.197592 WORK_FSP = 0x0
544 11:48:54.198202 WL = 0x2
545 11:48:54.201162 RL = 0x2
546 11:48:54.201642 BL = 0x2
547 11:48:54.202020 RPST = 0x0
548 11:48:54.205095 RD_PRE = 0x0
549 11:48:54.205573 WR_PRE = 0x1
550 11:48:54.208642 WR_PST = 0x0
551 11:48:54.209112 DBI_WR = 0x0
552 11:48:54.212010 DBI_RD = 0x0
553 11:48:54.212494 OTF = 0x1
554 11:48:54.215572 ===================================
555 11:48:54.219327 ===================================
556 11:48:54.219886 ANA top config
557 11:48:54.223166 ===================================
558 11:48:54.227088 DLL_ASYNC_EN = 0
559 11:48:54.230425 ALL_SLAVE_EN = 1
560 11:48:54.230897 NEW_RANK_MODE = 1
561 11:48:54.234299 DLL_IDLE_MODE = 1
562 11:48:54.238025 LP45_APHY_COMB_EN = 1
563 11:48:54.241609 TX_ODT_DIS = 1
564 11:48:54.242180 NEW_8X_MODE = 1
565 11:48:54.245027 ===================================
566 11:48:54.247923 ===================================
567 11:48:54.251560 data_rate = 1600
568 11:48:54.254663 CKR = 1
569 11:48:54.258001 DQ_P2S_RATIO = 8
570 11:48:54.261435 ===================================
571 11:48:54.265273 CA_P2S_RATIO = 8
572 11:48:54.265861 DQ_CA_OPEN = 0
573 11:48:54.268622 DQ_SEMI_OPEN = 0
574 11:48:54.272150 CA_SEMI_OPEN = 0
575 11:48:54.276071 CA_FULL_RATE = 0
576 11:48:54.276708 DQ_CKDIV4_EN = 1
577 11:48:54.279822 CA_CKDIV4_EN = 1
578 11:48:54.283142 CA_PREDIV_EN = 0
579 11:48:54.286852 PH8_DLY = 0
580 11:48:54.287450 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 11:48:54.290074 DQ_AAMCK_DIV = 4
582 11:48:54.293171 CA_AAMCK_DIV = 4
583 11:48:54.296574 CA_ADMCK_DIV = 4
584 11:48:54.299944 DQ_TRACK_CA_EN = 0
585 11:48:54.303210 CA_PICK = 800
586 11:48:54.307155 CA_MCKIO = 800
587 11:48:54.307625 MCKIO_SEMI = 0
588 11:48:54.310425 PLL_FREQ = 3068
589 11:48:54.314057 DQ_UI_PI_RATIO = 32
590 11:48:54.317128 CA_UI_PI_RATIO = 0
591 11:48:54.320570 ===================================
592 11:48:54.324066 ===================================
593 11:48:54.324588 memory_type:LPDDR4
594 11:48:54.327301 GP_NUM : 10
595 11:48:54.331253 SRAM_EN : 1
596 11:48:54.331823 MD32_EN : 0
597 11:48:54.334233 ===================================
598 11:48:54.338298 [ANA_INIT] >>>>>>>>>>>>>>
599 11:48:54.341574 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 11:48:54.345281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 11:48:54.348888 ===================================
602 11:48:54.349395 data_rate = 1600,PCW = 0X7600
603 11:48:54.352610 ===================================
604 11:48:54.356224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 11:48:54.362930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 11:48:54.366287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:48:54.373353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 11:48:54.376969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 11:48:54.379938 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:48:54.380547 [ANA_INIT] flow start
611 11:48:54.383327 [ANA_INIT] PLL >>>>>>>>
612 11:48:54.386432 [ANA_INIT] PLL <<<<<<<<
613 11:48:54.387022 [ANA_INIT] MIDPI >>>>>>>>
614 11:48:54.390234 [ANA_INIT] MIDPI <<<<<<<<
615 11:48:54.393104 [ANA_INIT] DLL >>>>>>>>
616 11:48:54.393586 [ANA_INIT] flow end
617 11:48:54.400240 ============ LP4 DIFF to SE enter ============
618 11:48:54.403281 ============ LP4 DIFF to SE exit ============
619 11:48:54.406571 [ANA_INIT] <<<<<<<<<<<<<
620 11:48:54.409708 [Flow] Enable top DCM control >>>>>
621 11:48:54.412890 [Flow] Enable top DCM control <<<<<
622 11:48:54.413371 Enable DLL master slave shuffle
623 11:48:54.419611 ==============================================================
624 11:48:54.422983 Gating Mode config
625 11:48:54.426175 ==============================================================
626 11:48:54.429698 Config description:
627 11:48:54.439887 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 11:48:54.446703 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 11:48:54.449672 SELPH_MODE 0: By rank 1: By Phase
630 11:48:54.456618 ==============================================================
631 11:48:54.459867 GAT_TRACK_EN = 1
632 11:48:54.463228 RX_GATING_MODE = 2
633 11:48:54.466439 RX_GATING_TRACK_MODE = 2
634 11:48:54.467037 SELPH_MODE = 1
635 11:48:54.469785 PICG_EARLY_EN = 1
636 11:48:54.473465 VALID_LAT_VALUE = 1
637 11:48:54.479712 ==============================================================
638 11:48:54.483422 Enter into Gating configuration >>>>
639 11:48:54.486763 Exit from Gating configuration <<<<
640 11:48:54.489752 Enter into DVFS_PRE_config >>>>>
641 11:48:54.500099 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 11:48:54.503273 Exit from DVFS_PRE_config <<<<<
643 11:48:54.506730 Enter into PICG configuration >>>>
644 11:48:54.509934 Exit from PICG configuration <<<<
645 11:48:54.513141 [RX_INPUT] configuration >>>>>
646 11:48:54.516488 [RX_INPUT] configuration <<<<<
647 11:48:54.519571 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 11:48:54.526743 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 11:48:54.533157 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 11:48:54.536677 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 11:48:54.543297 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 11:48:54.550009 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 11:48:54.553150 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 11:48:54.559878 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 11:48:54.563308 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 11:48:54.566792 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 11:48:54.569733 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 11:48:54.576663 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 11:48:54.579932 ===================================
660 11:48:54.580543 LPDDR4 DRAM CONFIGURATION
661 11:48:54.583237 ===================================
662 11:48:54.586404 EX_ROW_EN[0] = 0x0
663 11:48:54.589880 EX_ROW_EN[1] = 0x0
664 11:48:54.590466 LP4Y_EN = 0x0
665 11:48:54.593024 WORK_FSP = 0x0
666 11:48:54.593504 WL = 0x2
667 11:48:54.596643 RL = 0x2
668 11:48:54.597216 BL = 0x2
669 11:48:54.599931 RPST = 0x0
670 11:48:54.600558 RD_PRE = 0x0
671 11:48:54.603170 WR_PRE = 0x1
672 11:48:54.603749 WR_PST = 0x0
673 11:48:54.606497 DBI_WR = 0x0
674 11:48:54.607079 DBI_RD = 0x0
675 11:48:54.610052 OTF = 0x1
676 11:48:54.612948 ===================================
677 11:48:54.616294 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 11:48:54.619751 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 11:48:54.626335 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 11:48:54.629886 ===================================
681 11:48:54.630462 LPDDR4 DRAM CONFIGURATION
682 11:48:54.632998 ===================================
683 11:48:54.636440 EX_ROW_EN[0] = 0x10
684 11:48:54.637056 EX_ROW_EN[1] = 0x0
685 11:48:54.639897 LP4Y_EN = 0x0
686 11:48:54.640465 WORK_FSP = 0x0
687 11:48:54.643509 WL = 0x2
688 11:48:54.646318 RL = 0x2
689 11:48:54.646789 BL = 0x2
690 11:48:54.649582 RPST = 0x0
691 11:48:54.650053 RD_PRE = 0x0
692 11:48:54.652915 WR_PRE = 0x1
693 11:48:54.653385 WR_PST = 0x0
694 11:48:54.656462 DBI_WR = 0x0
695 11:48:54.657069 DBI_RD = 0x0
696 11:48:54.659825 OTF = 0x1
697 11:48:54.663023 ===================================
698 11:48:54.666354 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 11:48:54.672113 nWR fixed to 40
700 11:48:54.675282 [ModeRegInit_LP4] CH0 RK0
701 11:48:54.675854 [ModeRegInit_LP4] CH0 RK1
702 11:48:54.678736 [ModeRegInit_LP4] CH1 RK0
703 11:48:54.682412 [ModeRegInit_LP4] CH1 RK1
704 11:48:54.682993 match AC timing 12
705 11:48:54.688277 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
706 11:48:54.691744 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 11:48:54.695438 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 11:48:54.702046 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 11:48:54.705117 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 11:48:54.705592 [EMI DOE] emi_dcm 0
711 11:48:54.712215 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 11:48:54.712849 ==
713 11:48:54.715375 Dram Type= 6, Freq= 0, CH_0, rank 0
714 11:48:54.718467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
715 11:48:54.718941 ==
716 11:48:54.725124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 11:48:54.728898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 11:48:54.739165 [CA 0] Center 37 (7~68) winsize 62
719 11:48:54.742878 [CA 1] Center 37 (7~68) winsize 62
720 11:48:54.746188 [CA 2] Center 35 (4~66) winsize 63
721 11:48:54.749261 [CA 3] Center 35 (5~66) winsize 62
722 11:48:54.752298 [CA 4] Center 34 (4~65) winsize 62
723 11:48:54.755956 [CA 5] Center 34 (3~65) winsize 63
724 11:48:54.756566
725 11:48:54.759014 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 11:48:54.759590
727 11:48:54.762208 [CATrainingPosCal] consider 1 rank data
728 11:48:54.765718 u2DelayCellTimex100 = 270/100 ps
729 11:48:54.768972 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
730 11:48:54.775499 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
731 11:48:54.778735 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
732 11:48:54.782273 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
733 11:48:54.785437 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
734 11:48:54.788723 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
735 11:48:54.789193
736 11:48:54.792146 CA PerBit enable=1, Macro0, CA PI delay=34
737 11:48:54.792666
738 11:48:54.795360 [CBTSetCACLKResult] CA Dly = 34
739 11:48:54.795932 CS Dly: 5 (0~36)
740 11:48:54.799039 ==
741 11:48:54.802120 Dram Type= 6, Freq= 0, CH_0, rank 1
742 11:48:54.805341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
743 11:48:54.805816 ==
744 11:48:54.808633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 11:48:54.815482 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 11:48:54.825146 [CA 0] Center 37 (7~68) winsize 62
747 11:48:54.828674 [CA 1] Center 37 (6~68) winsize 63
748 11:48:54.831904 [CA 2] Center 35 (4~66) winsize 63
749 11:48:54.835123 [CA 3] Center 35 (4~66) winsize 63
750 11:48:54.838531 [CA 4] Center 34 (4~64) winsize 61
751 11:48:54.842076 [CA 5] Center 34 (3~65) winsize 63
752 11:48:54.842653
753 11:48:54.845048 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 11:48:54.845520
755 11:48:54.848438 [CATrainingPosCal] consider 2 rank data
756 11:48:54.852017 u2DelayCellTimex100 = 270/100 ps
757 11:48:54.854924 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
758 11:48:54.861479 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
759 11:48:54.865115 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
760 11:48:54.868389 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
761 11:48:54.871572 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
762 11:48:54.874907 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
763 11:48:54.875481
764 11:48:54.878063 CA PerBit enable=1, Macro0, CA PI delay=34
765 11:48:54.878536
766 11:48:54.881537 [CBTSetCACLKResult] CA Dly = 34
767 11:48:54.882012 CS Dly: 5 (0~37)
768 11:48:54.882383
769 11:48:54.884708 ----->DramcWriteLeveling(PI) begin...
770 11:48:54.887858 ==
771 11:48:54.891514 Dram Type= 6, Freq= 0, CH_0, rank 0
772 11:48:54.894705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
773 11:48:54.895182 ==
774 11:48:54.898358 Write leveling (Byte 0): 29 => 29
775 11:48:54.901541 Write leveling (Byte 1): 29 => 29
776 11:48:54.905082 DramcWriteLeveling(PI) end<-----
777 11:48:54.905555
778 11:48:54.905927 ==
779 11:48:54.909053 Dram Type= 6, Freq= 0, CH_0, rank 0
780 11:48:54.912940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 11:48:54.913498 ==
782 11:48:54.913883 [Gating] SW mode calibration
783 11:48:54.919993 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 11:48:54.926673 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 11:48:54.930351 0 6 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
786 11:48:54.934275 0 6 4 | B1->B0 | 2c2c 2626 | 1 0 | (1 0) (1 0)
787 11:48:54.941090 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 11:48:54.944314 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:48:54.947466 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:48:54.953835 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:48:54.957087 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:48:54.960675 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:48:54.967462 0 7 0 | B1->B0 | 2525 2d2d | 0 0 | (1 1) (0 0)
794 11:48:54.970553 0 7 4 | B1->B0 | 3a3a 4343 | 0 1 | (0 0) (0 0)
795 11:48:54.973999 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
796 11:48:54.980804 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 11:48:54.983844 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 11:48:54.987063 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 11:48:54.993688 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 11:48:54.997318 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 11:48:55.000301 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
802 11:48:55.007368 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 11:48:55.010371 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 11:48:55.014098 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 11:48:55.017422 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 11:48:55.023674 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 11:48:55.027263 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 11:48:55.030397 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 11:48:55.037150 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 11:48:55.040355 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 11:48:55.043766 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 11:48:55.050504 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 11:48:55.053668 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 11:48:55.057027 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 11:48:55.063883 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 11:48:55.067133 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 11:48:55.070355 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
818 11:48:55.073924 Total UI for P1: 0, mck2ui 16
819 11:48:55.077524 best dqsien dly found for B1: ( 0, 9, 30)
820 11:48:55.083424 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
821 11:48:55.083987 Total UI for P1: 0, mck2ui 16
822 11:48:55.090482 best dqsien dly found for B0: ( 0, 10, 0)
823 11:48:55.093539 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
824 11:48:55.096768 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
825 11:48:55.097241
826 11:48:55.100396 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
827 11:48:55.103657 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
828 11:48:55.107045 [Gating] SW calibration Done
829 11:48:55.107623 ==
830 11:48:55.110074 Dram Type= 6, Freq= 0, CH_0, rank 0
831 11:48:55.113661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
832 11:48:55.114235 ==
833 11:48:55.116898 RX Vref Scan: 0
834 11:48:55.117494
835 11:48:55.117925 RX Vref 0 -> 0, step: 1
836 11:48:55.118278
837 11:48:55.120623 RX Delay -130 -> 252, step: 16
838 11:48:55.123623 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
839 11:48:55.130091 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
840 11:48:55.133303 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
841 11:48:55.137222 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
842 11:48:55.140398 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
843 11:48:55.143701 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
844 11:48:55.150115 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
845 11:48:55.153591 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
846 11:48:55.156981 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
847 11:48:55.160341 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
848 11:48:55.163607 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
849 11:48:55.170238 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
850 11:48:55.173682 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
851 11:48:55.176824 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
852 11:48:55.180153 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
853 11:48:55.183565 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
854 11:48:55.186800 ==
855 11:48:55.190082 Dram Type= 6, Freq= 0, CH_0, rank 0
856 11:48:55.193325 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
857 11:48:55.193800 ==
858 11:48:55.194171 DQS Delay:
859 11:48:55.196775 DQS0 = 0, DQS1 = 0
860 11:48:55.197244 DQM Delay:
861 11:48:55.200199 DQM0 = 83, DQM1 = 75
862 11:48:55.200820 DQ Delay:
863 11:48:55.203653 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
864 11:48:55.206806 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
865 11:48:55.210237 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
866 11:48:55.213611 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
867 11:48:55.214086
868 11:48:55.214459
869 11:48:55.214800 ==
870 11:48:55.216648 Dram Type= 6, Freq= 0, CH_0, rank 0
871 11:48:55.220230 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
872 11:48:55.220908 ==
873 11:48:55.221293
874 11:48:55.221642
875 11:48:55.223510 TX Vref Scan disable
876 11:48:55.226568 == TX Byte 0 ==
877 11:48:55.230245 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
878 11:48:55.233363 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
879 11:48:55.236658 == TX Byte 1 ==
880 11:48:55.240171 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
881 11:48:55.243513 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
882 11:48:55.244084 ==
883 11:48:55.246851 Dram Type= 6, Freq= 0, CH_0, rank 0
884 11:48:55.249939 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
885 11:48:55.253208 ==
886 11:48:55.264069 TX Vref=22, minBit 0, minWin=27, winSum=441
887 11:48:55.267676 TX Vref=24, minBit 2, minWin=27, winSum=447
888 11:48:55.270817 TX Vref=26, minBit 2, minWin=27, winSum=451
889 11:48:55.274561 TX Vref=28, minBit 0, minWin=27, winSum=452
890 11:48:55.277648 TX Vref=30, minBit 0, minWin=28, winSum=454
891 11:48:55.281145 TX Vref=32, minBit 1, minWin=27, winSum=451
892 11:48:55.287345 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
893 11:48:55.287819
894 11:48:55.291003 Final TX Range 1 Vref 30
895 11:48:55.291471
896 11:48:55.291835 ==
897 11:48:55.294532 Dram Type= 6, Freq= 0, CH_0, rank 0
898 11:48:55.297941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 11:48:55.298514 ==
900 11:48:55.298888
901 11:48:55.299235
902 11:48:55.301090 TX Vref Scan disable
903 11:48:55.304482 == TX Byte 0 ==
904 11:48:55.307788 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
905 11:48:55.311009 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
906 11:48:55.314545 == TX Byte 1 ==
907 11:48:55.317669 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
908 11:48:55.321027 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
909 11:48:55.321499
910 11:48:55.324706 [DATLAT]
911 11:48:55.325279 Freq=800, CH0 RK0
912 11:48:55.325656
913 11:48:55.327783 DATLAT Default: 0xa
914 11:48:55.328250 0, 0xFFFF, sum = 0
915 11:48:55.331297 1, 0xFFFF, sum = 0
916 11:48:55.331890 2, 0xFFFF, sum = 0
917 11:48:55.334386 3, 0xFFFF, sum = 0
918 11:48:55.335019 4, 0xFFFF, sum = 0
919 11:48:55.337711 5, 0xFFFF, sum = 0
920 11:48:55.338288 6, 0xFFFF, sum = 0
921 11:48:55.340963 7, 0xFFFF, sum = 0
922 11:48:55.341442 8, 0x0, sum = 1
923 11:48:55.344932 9, 0x0, sum = 2
924 11:48:55.345519 10, 0x0, sum = 3
925 11:48:55.347545 11, 0x0, sum = 4
926 11:48:55.348024 best_step = 9
927 11:48:55.348396
928 11:48:55.348787 ==
929 11:48:55.350655 Dram Type= 6, Freq= 0, CH_0, rank 0
930 11:48:55.357794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
931 11:48:55.358290 ==
932 11:48:55.358669 RX Vref Scan: 1
933 11:48:55.359016
934 11:48:55.360878 Set Vref Range= 32 -> 127
935 11:48:55.361353
936 11:48:55.364147 RX Vref 32 -> 127, step: 1
937 11:48:55.364660
938 11:48:55.365045 RX Delay -95 -> 252, step: 8
939 11:48:55.365396
940 11:48:55.367545 Set Vref, RX VrefLevel [Byte0]: 32
941 11:48:55.370949 [Byte1]: 32
942 11:48:55.375058
943 11:48:55.375656 Set Vref, RX VrefLevel [Byte0]: 33
944 11:48:55.378473 [Byte1]: 33
945 11:48:55.382655
946 11:48:55.383229 Set Vref, RX VrefLevel [Byte0]: 34
947 11:48:55.386049 [Byte1]: 34
948 11:48:55.389967
949 11:48:55.390445 Set Vref, RX VrefLevel [Byte0]: 35
950 11:48:55.393362 [Byte1]: 35
951 11:48:55.397956
952 11:48:55.398538 Set Vref, RX VrefLevel [Byte0]: 36
953 11:48:55.401036 [Byte1]: 36
954 11:48:55.405502
955 11:48:55.406078 Set Vref, RX VrefLevel [Byte0]: 37
956 11:48:55.409046 [Byte1]: 37
957 11:48:55.412969
958 11:48:55.413554 Set Vref, RX VrefLevel [Byte0]: 38
959 11:48:55.416257 [Byte1]: 38
960 11:48:55.420332
961 11:48:55.420930 Set Vref, RX VrefLevel [Byte0]: 39
962 11:48:55.423790 [Byte1]: 39
963 11:48:55.428256
964 11:48:55.428808 Set Vref, RX VrefLevel [Byte0]: 40
965 11:48:55.431624 [Byte1]: 40
966 11:48:55.435808
967 11:48:55.436390 Set Vref, RX VrefLevel [Byte0]: 41
968 11:48:55.439201 [Byte1]: 41
969 11:48:55.443314
970 11:48:55.443894 Set Vref, RX VrefLevel [Byte0]: 42
971 11:48:55.447023 [Byte1]: 42
972 11:48:55.450939
973 11:48:55.451591 Set Vref, RX VrefLevel [Byte0]: 43
974 11:48:55.454079 [Byte1]: 43
975 11:48:55.458720
976 11:48:55.459326 Set Vref, RX VrefLevel [Byte0]: 44
977 11:48:55.461862 [Byte1]: 44
978 11:48:55.466421
979 11:48:55.467082 Set Vref, RX VrefLevel [Byte0]: 45
980 11:48:55.469254 [Byte1]: 45
981 11:48:55.473608
982 11:48:55.474183 Set Vref, RX VrefLevel [Byte0]: 46
983 11:48:55.476878 [Byte1]: 46
984 11:48:55.481369
985 11:48:55.481951 Set Vref, RX VrefLevel [Byte0]: 47
986 11:48:55.484850 [Byte1]: 47
987 11:48:55.488826
988 11:48:55.489305 Set Vref, RX VrefLevel [Byte0]: 48
989 11:48:55.492054 [Byte1]: 48
990 11:48:55.496621
991 11:48:55.497115 Set Vref, RX VrefLevel [Byte0]: 49
992 11:48:55.499581 [Byte1]: 49
993 11:48:55.504250
994 11:48:55.504881 Set Vref, RX VrefLevel [Byte0]: 50
995 11:48:55.507291 [Byte1]: 50
996 11:48:55.511865
997 11:48:55.512438 Set Vref, RX VrefLevel [Byte0]: 51
998 11:48:55.515097 [Byte1]: 51
999 11:48:55.519174
1000 11:48:55.519640 Set Vref, RX VrefLevel [Byte0]: 52
1001 11:48:55.522435 [Byte1]: 52
1002 11:48:55.526898
1003 11:48:55.527467 Set Vref, RX VrefLevel [Byte0]: 53
1004 11:48:55.530093 [Byte1]: 53
1005 11:48:55.534570
1006 11:48:55.535140 Set Vref, RX VrefLevel [Byte0]: 54
1007 11:48:55.537812 [Byte1]: 54
1008 11:48:55.542154
1009 11:48:55.542747 Set Vref, RX VrefLevel [Byte0]: 55
1010 11:48:55.545264 [Byte1]: 55
1011 11:48:55.549634
1012 11:48:55.550439 Set Vref, RX VrefLevel [Byte0]: 56
1013 11:48:55.553174 [Byte1]: 56
1014 11:48:55.557291
1015 11:48:55.557859 Set Vref, RX VrefLevel [Byte0]: 57
1016 11:48:55.560612 [Byte1]: 57
1017 11:48:55.564906
1018 11:48:55.565377 Set Vref, RX VrefLevel [Byte0]: 58
1019 11:48:55.568190 [Byte1]: 58
1020 11:48:55.572861
1021 11:48:55.573544 Set Vref, RX VrefLevel [Byte0]: 59
1022 11:48:55.576232 [Byte1]: 59
1023 11:48:55.580658
1024 11:48:55.581226 Set Vref, RX VrefLevel [Byte0]: 60
1025 11:48:55.583941 [Byte1]: 60
1026 11:48:55.587797
1027 11:48:55.588370 Set Vref, RX VrefLevel [Byte0]: 61
1028 11:48:55.590964 [Byte1]: 61
1029 11:48:55.595102
1030 11:48:55.595570 Set Vref, RX VrefLevel [Byte0]: 62
1031 11:48:55.598603 [Byte1]: 62
1032 11:48:55.603130
1033 11:48:55.603679 Set Vref, RX VrefLevel [Byte0]: 63
1034 11:48:55.606272 [Byte1]: 63
1035 11:48:55.610190
1036 11:48:55.610653 Set Vref, RX VrefLevel [Byte0]: 64
1037 11:48:55.613723 [Byte1]: 64
1038 11:48:55.617731
1039 11:48:55.618250 Set Vref, RX VrefLevel [Byte0]: 65
1040 11:48:55.621238 [Byte1]: 65
1041 11:48:55.625485
1042 11:48:55.625943 Set Vref, RX VrefLevel [Byte0]: 66
1043 11:48:55.628965 [Byte1]: 66
1044 11:48:55.633216
1045 11:48:55.633779 Set Vref, RX VrefLevel [Byte0]: 67
1046 11:48:55.636739 [Byte1]: 67
1047 11:48:55.640639
1048 11:48:55.641099 Set Vref, RX VrefLevel [Byte0]: 68
1049 11:48:55.644692 [Byte1]: 68
1050 11:48:55.648309
1051 11:48:55.651600 Set Vref, RX VrefLevel [Byte0]: 69
1052 11:48:55.654947 [Byte1]: 69
1053 11:48:55.655514
1054 11:48:55.658366 Set Vref, RX VrefLevel [Byte0]: 70
1055 11:48:55.661685 [Byte1]: 70
1056 11:48:55.662342
1057 11:48:55.664767 Set Vref, RX VrefLevel [Byte0]: 71
1058 11:48:55.668309 [Byte1]: 71
1059 11:48:55.668921
1060 11:48:55.671342 Final RX Vref Byte 0 = 50 to rank0
1061 11:48:55.675051 Final RX Vref Byte 1 = 56 to rank0
1062 11:48:55.678340 Final RX Vref Byte 0 = 50 to rank1
1063 11:48:55.681397 Final RX Vref Byte 1 = 56 to rank1==
1064 11:48:55.685073 Dram Type= 6, Freq= 0, CH_0, rank 0
1065 11:48:55.687992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1066 11:48:55.691149 ==
1067 11:48:55.691626 DQS Delay:
1068 11:48:55.692000 DQS0 = 0, DQS1 = 0
1069 11:48:55.694787 DQM Delay:
1070 11:48:55.695357 DQM0 = 83, DQM1 = 73
1071 11:48:55.698458 DQ Delay:
1072 11:48:55.699029 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1073 11:48:55.701323 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1074 11:48:55.704874 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1075 11:48:55.708224 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1076 11:48:55.708845
1077 11:48:55.711485
1078 11:48:55.718317 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1079 11:48:55.721161 CH0 RK0: MR19=606, MR18=3B3B
1080 11:48:55.727887 CH0_RK0: MR19=0x606, MR18=0x3B3B, DQSOSC=394, MR23=63, INC=95, DEC=63
1081 11:48:55.728486
1082 11:48:55.731534 ----->DramcWriteLeveling(PI) begin...
1083 11:48:55.732098 ==
1084 11:48:55.734305 Dram Type= 6, Freq= 0, CH_0, rank 1
1085 11:48:55.738065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1086 11:48:55.738628 ==
1087 11:48:55.741314 Write leveling (Byte 0): 28 => 28
1088 11:48:55.744807 Write leveling (Byte 1): 28 => 28
1089 11:48:55.748271 DramcWriteLeveling(PI) end<-----
1090 11:48:55.748872
1091 11:48:55.749244 ==
1092 11:48:55.751156 Dram Type= 6, Freq= 0, CH_0, rank 1
1093 11:48:55.754536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1094 11:48:55.755119 ==
1095 11:48:55.757985 [Gating] SW mode calibration
1096 11:48:55.764832 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1097 11:48:55.771380 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1098 11:48:55.775002 0 6 0 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 0)
1099 11:48:55.778057 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1100 11:48:55.785118 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1101 11:48:55.788203 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1102 11:48:55.791455 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1103 11:48:55.798442 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1104 11:48:55.801324 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1105 11:48:55.804717 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1106 11:48:55.808144 0 7 0 | B1->B0 | 2929 3232 | 0 0 | (0 0) (0 0)
1107 11:48:55.814592 0 7 4 | B1->B0 | 4141 4343 | 1 0 | (0 0) (0 0)
1108 11:48:55.817815 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1109 11:48:55.821204 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1110 11:48:55.828035 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1111 11:48:55.831398 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1112 11:48:55.834633 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1113 11:48:55.841439 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1114 11:48:55.844696 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1115 11:48:55.848188 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1116 11:48:55.854703 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1117 11:48:55.858111 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1118 11:48:55.861651 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1119 11:48:55.868406 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1120 11:48:55.871777 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1121 11:48:55.875141 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1122 11:48:55.881492 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1123 11:48:55.884683 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1124 11:48:55.888120 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 11:48:55.894803 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 11:48:55.898080 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 11:48:55.901258 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 11:48:55.908028 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 11:48:55.911266 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 11:48:55.914555 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1131 11:48:55.917741 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1132 11:48:55.921111 Total UI for P1: 0, mck2ui 16
1133 11:48:55.924319 best dqsien dly found for B0: ( 0, 10, 2)
1134 11:48:55.927820 Total UI for P1: 0, mck2ui 16
1135 11:48:55.931427 best dqsien dly found for B1: ( 0, 10, 0)
1136 11:48:55.934868 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1137 11:48:55.938073 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1138 11:48:55.941345
1139 11:48:55.944691 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1140 11:48:55.947865 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1141 11:48:55.950911 [Gating] SW calibration Done
1142 11:48:55.951447 ==
1143 11:48:55.954854 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 11:48:55.957855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1145 11:48:55.958421 ==
1146 11:48:55.958792 RX Vref Scan: 0
1147 11:48:55.961237
1148 11:48:55.961795 RX Vref 0 -> 0, step: 1
1149 11:48:55.962164
1150 11:48:55.964347 RX Delay -130 -> 252, step: 16
1151 11:48:55.967913 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1152 11:48:55.971221 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1153 11:48:55.977898 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1154 11:48:56.021842 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1155 11:48:56.022514 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1156 11:48:56.022901 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1157 11:48:56.023599 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1158 11:48:56.024023 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1159 11:48:56.024400 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1160 11:48:56.024776 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1161 11:48:56.025094 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1162 11:48:56.025405 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1163 11:48:56.025713 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1164 11:48:56.026019 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1165 11:48:56.026396 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1166 11:48:56.029956 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1167 11:48:56.030520 ==
1168 11:48:56.033179 Dram Type= 6, Freq= 0, CH_0, rank 1
1169 11:48:56.036721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1170 11:48:56.037427 ==
1171 11:48:56.037809 DQS Delay:
1172 11:48:56.040170 DQS0 = 0, DQS1 = 0
1173 11:48:56.040763 DQM Delay:
1174 11:48:56.043646 DQM0 = 80, DQM1 = 73
1175 11:48:56.044209 DQ Delay:
1176 11:48:56.046788 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1177 11:48:56.049989 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1178 11:48:56.053404 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1179 11:48:56.056475 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
1180 11:48:56.057075
1181 11:48:56.057445
1182 11:48:56.057783 ==
1183 11:48:56.060067 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 11:48:56.063167 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1185 11:48:56.063639 ==
1186 11:48:56.064010
1187 11:48:56.064347
1188 11:48:56.066491 TX Vref Scan disable
1189 11:48:56.069958 == TX Byte 0 ==
1190 11:48:56.073107 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1191 11:48:56.076648 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1192 11:48:56.079903 == TX Byte 1 ==
1193 11:48:56.083256 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1194 11:48:56.086629 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1195 11:48:56.087191 ==
1196 11:48:56.089976 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 11:48:56.096345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1198 11:48:56.096952 ==
1199 11:48:56.107907 TX Vref=22, minBit 2, minWin=27, winSum=437
1200 11:48:56.111486 TX Vref=24, minBit 0, minWin=27, winSum=448
1201 11:48:56.114842 TX Vref=26, minBit 6, minWin=27, winSum=452
1202 11:48:56.117951 TX Vref=28, minBit 2, minWin=28, winSum=457
1203 11:48:56.121225 TX Vref=30, minBit 2, minWin=28, winSum=459
1204 11:48:56.124912 TX Vref=32, minBit 2, minWin=28, winSum=458
1205 11:48:56.131432 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1206 11:48:56.132001
1207 11:48:56.134899 Final TX Range 1 Vref 30
1208 11:48:56.135462
1209 11:48:56.135832 ==
1210 11:48:56.137998 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 11:48:56.141494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1212 11:48:56.142056 ==
1213 11:48:56.142426
1214 11:48:56.144828
1215 11:48:56.145286 TX Vref Scan disable
1216 11:48:56.148197 == TX Byte 0 ==
1217 11:48:56.151804 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1218 11:48:56.156061 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1219 11:48:56.159588 == TX Byte 1 ==
1220 11:48:56.163550 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1221 11:48:56.166531 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1222 11:48:56.166999
1223 11:48:56.167440 [DATLAT]
1224 11:48:56.170103 Freq=800, CH0 RK1
1225 11:48:56.170663
1226 11:48:56.171075 DATLAT Default: 0x9
1227 11:48:56.173409 0, 0xFFFF, sum = 0
1228 11:48:56.173977 1, 0xFFFF, sum = 0
1229 11:48:56.176979 2, 0xFFFF, sum = 0
1230 11:48:56.177547 3, 0xFFFF, sum = 0
1231 11:48:56.180332 4, 0xFFFF, sum = 0
1232 11:48:56.180940 5, 0xFFFF, sum = 0
1233 11:48:56.183903 6, 0xFFFF, sum = 0
1234 11:48:56.184468 7, 0xFFFF, sum = 0
1235 11:48:56.186781 8, 0x0, sum = 1
1236 11:48:56.187351 9, 0x0, sum = 2
1237 11:48:56.190242 10, 0x0, sum = 3
1238 11:48:56.190812 11, 0x0, sum = 4
1239 11:48:56.193437 best_step = 9
1240 11:48:56.194135
1241 11:48:56.194524 ==
1242 11:48:56.196599 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 11:48:56.200276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1244 11:48:56.200898 ==
1245 11:48:56.201276 RX Vref Scan: 0
1246 11:48:56.201620
1247 11:48:56.203519 RX Vref 0 -> 0, step: 1
1248 11:48:56.203979
1249 11:48:56.207039 RX Delay -95 -> 252, step: 8
1250 11:48:56.209788 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1251 11:48:56.216972 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1252 11:48:56.219782 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1253 11:48:56.223031 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1254 11:48:56.226868 iDelay=209, Bit 4, Center 88 (-31 ~ 208) 240
1255 11:48:56.229774 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1256 11:48:56.236559 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1257 11:48:56.240047 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1258 11:48:56.243369 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1259 11:48:56.246390 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1260 11:48:56.250080 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1261 11:48:56.256925 iDelay=209, Bit 11, Center 64 (-47 ~ 176) 224
1262 11:48:56.260067 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1263 11:48:56.263296 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1264 11:48:56.266541 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1265 11:48:56.270086 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1266 11:48:56.273247 ==
1267 11:48:56.276715 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 11:48:56.279848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1269 11:48:56.280407 ==
1270 11:48:56.280837 DQS Delay:
1271 11:48:56.283144 DQS0 = 0, DQS1 = 0
1272 11:48:56.283715 DQM Delay:
1273 11:48:56.286349 DQM0 = 85, DQM1 = 73
1274 11:48:56.286909 DQ Delay:
1275 11:48:56.290039 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1276 11:48:56.293155 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1277 11:48:56.296307 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =64
1278 11:48:56.299887 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1279 11:48:56.300445
1280 11:48:56.300877
1281 11:48:56.306557 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1282 11:48:56.310075 CH0 RK1: MR19=606, MR18=4141
1283 11:48:56.316635 CH0_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1284 11:48:56.319516 [RxdqsGatingPostProcess] freq 800
1285 11:48:56.323262 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1286 11:48:56.326357 Pre-setting of DQS Precalculation
1287 11:48:56.333041 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1288 11:48:56.333606 ==
1289 11:48:56.336338 Dram Type= 6, Freq= 0, CH_1, rank 0
1290 11:48:56.339722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1291 11:48:56.340286 ==
1292 11:48:56.346167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1293 11:48:56.352618 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1294 11:48:56.360044 [CA 0] Center 36 (6~67) winsize 62
1295 11:48:56.363509 [CA 1] Center 36 (5~67) winsize 63
1296 11:48:56.366620 [CA 2] Center 34 (4~65) winsize 62
1297 11:48:56.369946 [CA 3] Center 34 (3~65) winsize 63
1298 11:48:56.373579 [CA 4] Center 33 (2~64) winsize 63
1299 11:48:56.377013 [CA 5] Center 33 (3~64) winsize 62
1300 11:48:56.377324
1301 11:48:56.380217 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1302 11:48:56.380568
1303 11:48:56.383537 [CATrainingPosCal] consider 1 rank data
1304 11:48:56.386749 u2DelayCellTimex100 = 270/100 ps
1305 11:48:56.390082 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1306 11:48:56.393494 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1307 11:48:56.400125 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1308 11:48:56.403462 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1309 11:48:56.407082 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1310 11:48:56.409991 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1311 11:48:56.410353
1312 11:48:56.413564 CA PerBit enable=1, Macro0, CA PI delay=33
1313 11:48:56.414025
1314 11:48:56.416655 [CBTSetCACLKResult] CA Dly = 33
1315 11:48:56.417116 CS Dly: 4 (0~35)
1316 11:48:56.417482 ==
1317 11:48:56.420382 Dram Type= 6, Freq= 0, CH_1, rank 1
1318 11:48:56.427161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1319 11:48:56.427753 ==
1320 11:48:56.430223 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1321 11:48:56.436879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1322 11:48:56.446121 [CA 0] Center 36 (6~67) winsize 62
1323 11:48:56.449453 [CA 1] Center 36 (5~67) winsize 63
1324 11:48:56.452945 [CA 2] Center 34 (4~65) winsize 62
1325 11:48:56.456345 [CA 3] Center 34 (4~65) winsize 62
1326 11:48:56.459804 [CA 4] Center 33 (3~64) winsize 62
1327 11:48:56.463010 [CA 5] Center 33 (3~64) winsize 62
1328 11:48:56.463570
1329 11:48:56.466259 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1330 11:48:56.466827
1331 11:48:56.469644 [CATrainingPosCal] consider 2 rank data
1332 11:48:56.472936 u2DelayCellTimex100 = 270/100 ps
1333 11:48:56.476553 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1334 11:48:56.479561 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1335 11:48:56.483214 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1336 11:48:56.489688 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1337 11:48:56.492900 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1338 11:48:56.496103 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1339 11:48:56.496614
1340 11:48:56.499779 CA PerBit enable=1, Macro0, CA PI delay=33
1341 11:48:56.500333
1342 11:48:56.503294 [CBTSetCACLKResult] CA Dly = 33
1343 11:48:56.503870 CS Dly: 4 (0~36)
1344 11:48:56.504235
1345 11:48:56.506368 ----->DramcWriteLeveling(PI) begin...
1346 11:48:56.506931 ==
1347 11:48:56.509742 Dram Type= 6, Freq= 0, CH_1, rank 0
1348 11:48:56.516607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1349 11:48:56.517159 ==
1350 11:48:56.519484 Write leveling (Byte 0): 26 => 26
1351 11:48:56.523038 Write leveling (Byte 1): 25 => 25
1352 11:48:56.523593 DramcWriteLeveling(PI) end<-----
1353 11:48:56.526504
1354 11:48:56.527056 ==
1355 11:48:56.529434 Dram Type= 6, Freq= 0, CH_1, rank 0
1356 11:48:56.532882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1357 11:48:56.533430 ==
1358 11:48:56.536016 [Gating] SW mode calibration
1359 11:48:56.543073 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1360 11:48:56.546286 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1361 11:48:56.552993 0 6 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
1362 11:48:56.556204 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1363 11:48:56.559725 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1364 11:48:56.566413 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1365 11:48:56.569313 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1366 11:48:56.572634 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1367 11:48:56.579917 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1368 11:48:56.583031 0 6 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1369 11:48:56.586460 0 7 0 | B1->B0 | 3333 4242 | 0 0 | (0 0) (0 0)
1370 11:48:56.593105 0 7 4 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
1371 11:48:56.596375 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1372 11:48:56.599378 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1373 11:48:56.603092 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1374 11:48:56.609779 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1375 11:48:56.612981 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1376 11:48:56.616542 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1377 11:48:56.622734 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1378 11:48:56.626187 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1379 11:48:56.629342 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1380 11:48:56.636140 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1381 11:48:56.639370 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1382 11:48:56.643008 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1383 11:48:56.649466 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1384 11:48:56.652809 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1385 11:48:56.656261 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1386 11:48:56.662629 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1387 11:48:56.666121 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 11:48:56.669229 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 11:48:56.676200 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 11:48:56.679492 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 11:48:56.682744 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 11:48:56.689474 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1393 11:48:56.692612 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1394 11:48:56.696038 Total UI for P1: 0, mck2ui 16
1395 11:48:56.699221 best dqsien dly found for B0: ( 0, 9, 28)
1396 11:48:56.702806 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1397 11:48:56.706066 Total UI for P1: 0, mck2ui 16
1398 11:48:56.709031 best dqsien dly found for B1: ( 0, 9, 30)
1399 11:48:56.712673 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1400 11:48:56.716045 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1401 11:48:56.716662
1402 11:48:56.722135 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1403 11:48:56.725505 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1404 11:48:56.728840 [Gating] SW calibration Done
1405 11:48:56.729301 ==
1406 11:48:56.732638 Dram Type= 6, Freq= 0, CH_1, rank 0
1407 11:48:56.735974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1408 11:48:56.736583 ==
1409 11:48:56.736961 RX Vref Scan: 0
1410 11:48:56.737301
1411 11:48:56.739087 RX Vref 0 -> 0, step: 1
1412 11:48:56.739708
1413 11:48:56.742398 RX Delay -130 -> 252, step: 16
1414 11:48:56.745476 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1415 11:48:56.749125 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1416 11:48:56.755690 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1417 11:48:56.758878 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1418 11:48:56.762516 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1419 11:48:56.765648 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1420 11:48:56.768785 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1421 11:48:56.775352 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1422 11:48:56.778949 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1423 11:48:56.782257 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1424 11:48:56.785420 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1425 11:48:56.788872 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1426 11:48:56.795579 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1427 11:48:56.798704 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1428 11:48:56.802272 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1429 11:48:56.805257 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1430 11:48:56.805717 ==
1431 11:48:56.808630 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 11:48:56.816013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1433 11:48:56.816627 ==
1434 11:48:56.817014 DQS Delay:
1435 11:48:56.817364 DQS0 = 0, DQS1 = 0
1436 11:48:56.819325 DQM Delay:
1437 11:48:56.819801 DQM0 = 81, DQM1 = 70
1438 11:48:56.820172 DQ Delay:
1439 11:48:56.823065 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1440 11:48:56.826793 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1441 11:48:56.830290 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1442 11:48:56.834176 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1443 11:48:56.834746
1444 11:48:56.835118
1445 11:48:56.835456 ==
1446 11:48:56.837682 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 11:48:56.841547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1448 11:48:56.842103 ==
1449 11:48:56.842474
1450 11:48:56.842815
1451 11:48:56.845495 TX Vref Scan disable
1452 11:48:56.845960 == TX Byte 0 ==
1453 11:48:56.852031 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1454 11:48:56.855425 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1455 11:48:56.856012 == TX Byte 1 ==
1456 11:48:56.862072 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1457 11:48:56.865359 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1458 11:48:56.866048 ==
1459 11:48:56.868430 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 11:48:56.871953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1461 11:48:56.872418 ==
1462 11:48:56.885709 TX Vref=22, minBit 9, minWin=27, winSum=448
1463 11:48:56.889071 TX Vref=24, minBit 0, minWin=28, winSum=449
1464 11:48:56.892726 TX Vref=26, minBit 0, minWin=28, winSum=454
1465 11:48:56.895511 TX Vref=28, minBit 0, minWin=28, winSum=454
1466 11:48:56.899045 TX Vref=30, minBit 2, minWin=28, winSum=456
1467 11:48:56.902521 TX Vref=32, minBit 0, minWin=28, winSum=453
1468 11:48:56.908943 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
1469 11:48:56.909415
1470 11:48:56.912324 Final TX Range 1 Vref 30
1471 11:48:56.912825
1472 11:48:56.913194 ==
1473 11:48:56.915348 Dram Type= 6, Freq= 0, CH_1, rank 0
1474 11:48:56.918908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1475 11:48:56.919374 ==
1476 11:48:56.919739
1477 11:48:56.920171
1478 11:48:56.922249 TX Vref Scan disable
1479 11:48:56.925615 == TX Byte 0 ==
1480 11:48:56.928802 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1481 11:48:56.932672 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1482 11:48:56.935686 == TX Byte 1 ==
1483 11:48:56.938960 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1484 11:48:56.942252 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1485 11:48:56.942810
1486 11:48:56.945836 [DATLAT]
1487 11:48:56.946398 Freq=800, CH1 RK0
1488 11:48:56.946774
1489 11:48:56.948638 DATLAT Default: 0xa
1490 11:48:56.949105 0, 0xFFFF, sum = 0
1491 11:48:56.952264 1, 0xFFFF, sum = 0
1492 11:48:56.952883 2, 0xFFFF, sum = 0
1493 11:48:56.955614 3, 0xFFFF, sum = 0
1494 11:48:56.956180 4, 0xFFFF, sum = 0
1495 11:48:56.959114 5, 0xFFFF, sum = 0
1496 11:48:56.959680 6, 0xFFFF, sum = 0
1497 11:48:56.962561 7, 0xFFFF, sum = 0
1498 11:48:56.963139 8, 0x0, sum = 1
1499 11:48:56.965564 9, 0x0, sum = 2
1500 11:48:56.966036 10, 0x0, sum = 3
1501 11:48:56.968760 11, 0x0, sum = 4
1502 11:48:56.969322 best_step = 9
1503 11:48:56.969695
1504 11:48:56.970039 ==
1505 11:48:56.972023 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 11:48:56.979073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1507 11:48:56.979637 ==
1508 11:48:56.980008 RX Vref Scan: 1
1509 11:48:56.980355
1510 11:48:56.982107 Set Vref Range= 32 -> 127
1511 11:48:56.982573
1512 11:48:56.985436 RX Vref 32 -> 127, step: 1
1513 11:48:56.985994
1514 11:48:56.986363 RX Delay -111 -> 252, step: 8
1515 11:48:56.986707
1516 11:48:56.988877 Set Vref, RX VrefLevel [Byte0]: 32
1517 11:48:56.992438 [Byte1]: 32
1518 11:48:56.996568
1519 11:48:56.997122 Set Vref, RX VrefLevel [Byte0]: 33
1520 11:48:56.999595 [Byte1]: 33
1521 11:48:57.004119
1522 11:48:57.004729 Set Vref, RX VrefLevel [Byte0]: 34
1523 11:48:57.007385 [Byte1]: 34
1524 11:48:57.011776
1525 11:48:57.012332 Set Vref, RX VrefLevel [Byte0]: 35
1526 11:48:57.015262 [Byte1]: 35
1527 11:48:57.019327
1528 11:48:57.019892 Set Vref, RX VrefLevel [Byte0]: 36
1529 11:48:57.022664 [Byte1]: 36
1530 11:48:57.026742
1531 11:48:57.027203 Set Vref, RX VrefLevel [Byte0]: 37
1532 11:48:57.030138 [Byte1]: 37
1533 11:48:57.034780
1534 11:48:57.035337 Set Vref, RX VrefLevel [Byte0]: 38
1535 11:48:57.037699 [Byte1]: 38
1536 11:48:57.042418
1537 11:48:57.042982 Set Vref, RX VrefLevel [Byte0]: 39
1538 11:48:57.045484 [Byte1]: 39
1539 11:48:57.050032
1540 11:48:57.050589 Set Vref, RX VrefLevel [Byte0]: 40
1541 11:48:57.053170 [Byte1]: 40
1542 11:48:57.057660
1543 11:48:57.058129 Set Vref, RX VrefLevel [Byte0]: 41
1544 11:48:57.060790 [Byte1]: 41
1545 11:48:57.065328
1546 11:48:57.065885 Set Vref, RX VrefLevel [Byte0]: 42
1547 11:48:57.068376 [Byte1]: 42
1548 11:48:57.072732
1549 11:48:57.073332 Set Vref, RX VrefLevel [Byte0]: 43
1550 11:48:57.076293 [Byte1]: 43
1551 11:48:57.080747
1552 11:48:57.081302 Set Vref, RX VrefLevel [Byte0]: 44
1553 11:48:57.083771 [Byte1]: 44
1554 11:48:57.088078
1555 11:48:57.088686 Set Vref, RX VrefLevel [Byte0]: 45
1556 11:48:57.091645 [Byte1]: 45
1557 11:48:57.095933
1558 11:48:57.096493 Set Vref, RX VrefLevel [Byte0]: 46
1559 11:48:57.099113 [Byte1]: 46
1560 11:48:57.103279
1561 11:48:57.103830 Set Vref, RX VrefLevel [Byte0]: 47
1562 11:48:57.106796 [Byte1]: 47
1563 11:48:57.111539
1564 11:48:57.112101 Set Vref, RX VrefLevel [Byte0]: 48
1565 11:48:57.114431 [Byte1]: 48
1566 11:48:57.118746
1567 11:48:57.119302 Set Vref, RX VrefLevel [Byte0]: 49
1568 11:48:57.121982 [Byte1]: 49
1569 11:48:57.126430
1570 11:48:57.127035 Set Vref, RX VrefLevel [Byte0]: 50
1571 11:48:57.129415 [Byte1]: 50
1572 11:48:57.134060
1573 11:48:57.134617 Set Vref, RX VrefLevel [Byte0]: 51
1574 11:48:57.137419 [Byte1]: 51
1575 11:48:57.142053
1576 11:48:57.142609 Set Vref, RX VrefLevel [Byte0]: 52
1577 11:48:57.144971 [Byte1]: 52
1578 11:48:57.149238
1579 11:48:57.152531 Set Vref, RX VrefLevel [Byte0]: 53
1580 11:48:57.153100 [Byte1]: 53
1581 11:48:57.157301
1582 11:48:57.157860 Set Vref, RX VrefLevel [Byte0]: 54
1583 11:48:57.160556 [Byte1]: 54
1584 11:48:57.164829
1585 11:48:57.165385 Set Vref, RX VrefLevel [Byte0]: 55
1586 11:48:57.168101 [Byte1]: 55
1587 11:48:57.172309
1588 11:48:57.172934 Set Vref, RX VrefLevel [Byte0]: 56
1589 11:48:57.175692 [Byte1]: 56
1590 11:48:57.179933
1591 11:48:57.180490 Set Vref, RX VrefLevel [Byte0]: 57
1592 11:48:57.183152 [Byte1]: 57
1593 11:48:57.187607
1594 11:48:57.188169 Set Vref, RX VrefLevel [Byte0]: 58
1595 11:48:57.191031 [Byte1]: 58
1596 11:48:57.195364
1597 11:48:57.195926 Set Vref, RX VrefLevel [Byte0]: 59
1598 11:48:57.198572 [Byte1]: 59
1599 11:48:57.202751
1600 11:48:57.203222 Set Vref, RX VrefLevel [Byte0]: 60
1601 11:48:57.206005 [Byte1]: 60
1602 11:48:57.210349
1603 11:48:57.210913 Set Vref, RX VrefLevel [Byte0]: 61
1604 11:48:57.214115 [Byte1]: 61
1605 11:48:57.218097
1606 11:48:57.218661 Set Vref, RX VrefLevel [Byte0]: 62
1607 11:48:57.221106 [Byte1]: 62
1608 11:48:57.225646
1609 11:48:57.226212 Set Vref, RX VrefLevel [Byte0]: 63
1610 11:48:57.229289 [Byte1]: 63
1611 11:48:57.233499
1612 11:48:57.234061 Set Vref, RX VrefLevel [Byte0]: 64
1613 11:48:57.236768 [Byte1]: 64
1614 11:48:57.241074
1615 11:48:57.241639 Set Vref, RX VrefLevel [Byte0]: 65
1616 11:48:57.244335 [Byte1]: 65
1617 11:48:57.249117
1618 11:48:57.249675 Set Vref, RX VrefLevel [Byte0]: 66
1619 11:48:57.252070 [Byte1]: 66
1620 11:48:57.256399
1621 11:48:57.257014 Set Vref, RX VrefLevel [Byte0]: 67
1622 11:48:57.259686 [Byte1]: 67
1623 11:48:57.263943
1624 11:48:57.264606 Set Vref, RX VrefLevel [Byte0]: 68
1625 11:48:57.267370 [Byte1]: 68
1626 11:48:57.271396
1627 11:48:57.271867 Set Vref, RX VrefLevel [Byte0]: 69
1628 11:48:57.274682 [Byte1]: 69
1629 11:48:57.279536
1630 11:48:57.280104 Set Vref, RX VrefLevel [Byte0]: 70
1631 11:48:57.282860 [Byte1]: 70
1632 11:48:57.286936
1633 11:48:57.287502 Set Vref, RX VrefLevel [Byte0]: 71
1634 11:48:57.290222 [Byte1]: 71
1635 11:48:57.294760
1636 11:48:57.295331 Set Vref, RX VrefLevel [Byte0]: 72
1637 11:48:57.297959 [Byte1]: 72
1638 11:48:57.302352
1639 11:48:57.302933 Set Vref, RX VrefLevel [Byte0]: 73
1640 11:48:57.305214 [Byte1]: 73
1641 11:48:57.309867
1642 11:48:57.310434 Final RX Vref Byte 0 = 59 to rank0
1643 11:48:57.313166 Final RX Vref Byte 1 = 55 to rank0
1644 11:48:57.316368 Final RX Vref Byte 0 = 59 to rank1
1645 11:48:57.319868 Final RX Vref Byte 1 = 55 to rank1==
1646 11:48:57.323404 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 11:48:57.329593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1648 11:48:57.330102 ==
1649 11:48:57.330467 DQS Delay:
1650 11:48:57.330805 DQS0 = 0, DQS1 = 0
1651 11:48:57.333022 DQM Delay:
1652 11:48:57.333485 DQM0 = 79, DQM1 = 72
1653 11:48:57.336485 DQ Delay:
1654 11:48:57.340090 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1655 11:48:57.340693 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1656 11:48:57.343225 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1657 11:48:57.346538 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1658 11:48:57.349766
1659 11:48:57.350325
1660 11:48:57.356562 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1661 11:48:57.359944 CH1 RK0: MR19=606, MR18=4C4C
1662 11:48:57.366205 CH1_RK0: MR19=0x606, MR18=0x4C4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1663 11:48:57.366754
1664 11:48:57.369751 ----->DramcWriteLeveling(PI) begin...
1665 11:48:57.370321 ==
1666 11:48:57.373284 Dram Type= 6, Freq= 0, CH_1, rank 1
1667 11:48:57.376806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1668 11:48:57.377367 ==
1669 11:48:57.379733 Write leveling (Byte 0): 26 => 26
1670 11:48:57.383162 Write leveling (Byte 1): 24 => 24
1671 11:48:57.386459 DramcWriteLeveling(PI) end<-----
1672 11:48:57.387013
1673 11:48:57.387377 ==
1674 11:48:57.389650 Dram Type= 6, Freq= 0, CH_1, rank 1
1675 11:48:57.393476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1676 11:48:57.394056 ==
1677 11:48:57.397282 [Gating] SW mode calibration
1678 11:48:57.403762 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1679 11:48:57.407266 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1680 11:48:57.413778 0 6 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1681 11:48:57.417085 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1682 11:48:57.420612 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1683 11:48:57.426886 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1684 11:48:57.430285 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1685 11:48:57.433691 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1686 11:48:57.440358 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1687 11:48:57.443932 0 6 28 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
1688 11:48:57.447203 0 7 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1689 11:48:57.453812 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1690 11:48:57.456883 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1691 11:48:57.460352 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1692 11:48:57.467119 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1693 11:48:57.470406 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1694 11:48:57.473649 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1695 11:48:57.480620 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1696 11:48:57.483938 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1697 11:48:57.487138 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1698 11:48:57.494067 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1699 11:48:57.497086 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1700 11:48:57.500365 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1701 11:48:57.506858 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1702 11:48:57.510273 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1703 11:48:57.513880 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1704 11:48:57.517018 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1705 11:48:57.523784 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1706 11:48:57.526928 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1707 11:48:57.530372 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1708 11:48:57.537255 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1709 11:48:57.540588 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1710 11:48:57.543941 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1711 11:48:57.550584 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1712 11:48:57.553438 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1713 11:48:57.556819 Total UI for P1: 0, mck2ui 16
1714 11:48:57.560468 best dqsien dly found for B0: ( 0, 9, 28)
1715 11:48:57.563763 Total UI for P1: 0, mck2ui 16
1716 11:48:57.567270 best dqsien dly found for B1: ( 0, 9, 30)
1717 11:48:57.570736 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1718 11:48:57.573882 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1719 11:48:57.574448
1720 11:48:57.576948 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1721 11:48:57.580493 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1722 11:48:57.583796 [Gating] SW calibration Done
1723 11:48:57.584358 ==
1724 11:48:57.587160 Dram Type= 6, Freq= 0, CH_1, rank 1
1725 11:48:57.590807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1726 11:48:57.594026 ==
1727 11:48:57.594595 RX Vref Scan: 0
1728 11:48:57.594965
1729 11:48:57.597045 RX Vref 0 -> 0, step: 1
1730 11:48:57.597512
1731 11:48:57.600372 RX Delay -130 -> 252, step: 16
1732 11:48:57.603628 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1733 11:48:57.606936 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1734 11:48:57.610692 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1735 11:48:57.613790 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1736 11:48:57.620570 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1737 11:48:57.623681 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1738 11:48:57.626920 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1739 11:48:57.630396 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1740 11:48:57.633601 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1741 11:48:57.637444 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1742 11:48:57.643842 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1743 11:48:57.647252 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1744 11:48:57.650401 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1745 11:48:57.653961 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1746 11:48:57.660422 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1747 11:48:57.663720 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1748 11:48:57.664280 ==
1749 11:48:57.667298 Dram Type= 6, Freq= 0, CH_1, rank 1
1750 11:48:57.670035 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1751 11:48:57.670507 ==
1752 11:48:57.673565 DQS Delay:
1753 11:48:57.674127 DQS0 = 0, DQS1 = 0
1754 11:48:57.674505 DQM Delay:
1755 11:48:57.677320 DQM0 = 81, DQM1 = 69
1756 11:48:57.677884 DQ Delay:
1757 11:48:57.680766 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1758 11:48:57.683781 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1759 11:48:57.687069 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1760 11:48:57.690315 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1761 11:48:57.690881
1762 11:48:57.691252
1763 11:48:57.691594 ==
1764 11:48:57.693880 Dram Type= 6, Freq= 0, CH_1, rank 1
1765 11:48:57.700437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1766 11:48:57.701059 ==
1767 11:48:57.701441
1768 11:48:57.701786
1769 11:48:57.702123 TX Vref Scan disable
1770 11:48:57.703586 == TX Byte 0 ==
1771 11:48:57.707017 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1772 11:48:57.711049 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1773 11:48:57.713203 == TX Byte 1 ==
1774 11:48:57.716817 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1775 11:48:57.723216 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1776 11:48:57.723685 ==
1777 11:48:57.726503 Dram Type= 6, Freq= 0, CH_1, rank 1
1778 11:48:57.729968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1779 11:48:57.730441 ==
1780 11:48:57.742704 TX Vref=22, minBit 8, minWin=27, winSum=452
1781 11:48:57.746053 TX Vref=24, minBit 8, minWin=28, winSum=459
1782 11:48:57.749443 TX Vref=26, minBit 0, minWin=28, winSum=458
1783 11:48:57.752678 TX Vref=28, minBit 0, minWin=28, winSum=459
1784 11:48:57.755634 TX Vref=30, minBit 0, minWin=28, winSum=461
1785 11:48:57.762492 TX Vref=32, minBit 0, minWin=28, winSum=458
1786 11:48:57.766187 [TxChooseVref] Worse bit 0, Min win 28, Win sum 461, Final Vref 30
1787 11:48:57.766774
1788 11:48:57.769195 Final TX Range 1 Vref 30
1789 11:48:57.769763
1790 11:48:57.770137 ==
1791 11:48:57.772406 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 11:48:57.775785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1793 11:48:57.776254 ==
1794 11:48:57.779386
1795 11:48:57.779852
1796 11:48:57.780219 TX Vref Scan disable
1797 11:48:57.782694 == TX Byte 0 ==
1798 11:48:57.786159 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1799 11:48:57.789172 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1800 11:48:57.792670 == TX Byte 1 ==
1801 11:48:57.795884 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1802 11:48:57.799532 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1803 11:48:57.802440
1804 11:48:57.802991 [DATLAT]
1805 11:48:57.803485 Freq=800, CH1 RK1
1806 11:48:57.803965
1807 11:48:57.805923 DATLAT Default: 0x9
1808 11:48:57.806508 0, 0xFFFF, sum = 0
1809 11:48:57.808996 1, 0xFFFF, sum = 0
1810 11:48:57.809488 2, 0xFFFF, sum = 0
1811 11:48:57.812593 3, 0xFFFF, sum = 0
1812 11:48:57.813182 4, 0xFFFF, sum = 0
1813 11:48:57.815668 5, 0xFFFF, sum = 0
1814 11:48:57.819154 6, 0xFFFF, sum = 0
1815 11:48:57.819749 7, 0xFFFF, sum = 0
1816 11:48:57.820255 8, 0x0, sum = 1
1817 11:48:57.822347 9, 0x0, sum = 2
1818 11:48:57.822836 10, 0x0, sum = 3
1819 11:48:57.826093 11, 0x0, sum = 4
1820 11:48:57.826586 best_step = 9
1821 11:48:57.827070
1822 11:48:57.827532 ==
1823 11:48:57.829288 Dram Type= 6, Freq= 0, CH_1, rank 1
1824 11:48:57.835966 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1825 11:48:57.836653 ==
1826 11:48:57.837151 RX Vref Scan: 0
1827 11:48:57.837616
1828 11:48:57.839097 RX Vref 0 -> 0, step: 1
1829 11:48:57.839608
1830 11:48:57.842786 RX Delay -111 -> 252, step: 8
1831 11:48:57.846120 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1832 11:48:57.849420 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1833 11:48:57.855968 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1834 11:48:57.859315 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1835 11:48:57.862499 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1836 11:48:57.865826 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1837 11:48:57.869181 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1838 11:48:57.873041 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1839 11:48:57.879294 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1840 11:48:57.882649 iDelay=217, Bit 9, Center 60 (-63 ~ 184) 248
1841 11:48:57.885701 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1842 11:48:57.889406 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1843 11:48:57.892586 iDelay=217, Bit 12, Center 84 (-39 ~ 208) 248
1844 11:48:57.899452 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1845 11:48:57.902534 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1846 11:48:57.905917 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1847 11:48:57.906508 ==
1848 11:48:57.908931 Dram Type= 6, Freq= 0, CH_1, rank 1
1849 11:48:57.912595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1850 11:48:57.915913 ==
1851 11:48:57.916495 DQS Delay:
1852 11:48:57.917054 DQS0 = 0, DQS1 = 0
1853 11:48:57.919312 DQM Delay:
1854 11:48:57.919898 DQM0 = 82, DQM1 = 72
1855 11:48:57.922366 DQ Delay:
1856 11:48:57.925472 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1857 11:48:57.925965 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1858 11:48:57.929199 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1859 11:48:57.932817 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
1860 11:48:57.936004
1861 11:48:57.936620
1862 11:48:57.942519 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1863 11:48:57.945956 CH1 RK1: MR19=606, MR18=4141
1864 11:48:57.952658 CH1_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1865 11:48:57.953246 [RxdqsGatingPostProcess] freq 800
1866 11:48:57.959348 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1867 11:48:57.962734 Pre-setting of DQS Precalculation
1868 11:48:57.965777 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1869 11:48:57.975747 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1870 11:48:57.982547 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1871 11:48:57.983116
1872 11:48:57.983484
1873 11:48:57.985768 [Calibration Summary] 1600 Mbps
1874 11:48:57.986340 CH 0, Rank 0
1875 11:48:57.989195 SW Impedance : PASS
1876 11:48:57.989764 DUTY Scan : NO K
1877 11:48:57.992614 ZQ Calibration : PASS
1878 11:48:57.995827 Jitter Meter : NO K
1879 11:48:57.996389 CBT Training : PASS
1880 11:48:57.999012 Write leveling : PASS
1881 11:48:58.002064 RX DQS gating : PASS
1882 11:48:58.002531 RX DQ/DQS(RDDQC) : PASS
1883 11:48:58.005493 TX DQ/DQS : PASS
1884 11:48:58.008699 RX DATLAT : PASS
1885 11:48:58.009165 RX DQ/DQS(Engine): PASS
1886 11:48:58.012074 TX OE : NO K
1887 11:48:58.012589 All Pass.
1888 11:48:58.012973
1889 11:48:58.015766 CH 0, Rank 1
1890 11:48:58.016335 SW Impedance : PASS
1891 11:48:58.019073 DUTY Scan : NO K
1892 11:48:58.022069 ZQ Calibration : PASS
1893 11:48:58.022617 Jitter Meter : NO K
1894 11:48:58.025379 CBT Training : PASS
1895 11:48:58.025842 Write leveling : PASS
1896 11:48:58.028999 RX DQS gating : PASS
1897 11:48:58.032017 RX DQ/DQS(RDDQC) : PASS
1898 11:48:58.032670 TX DQ/DQS : PASS
1899 11:48:58.035377 RX DATLAT : PASS
1900 11:48:58.038835 RX DQ/DQS(Engine): PASS
1901 11:48:58.039300 TX OE : NO K
1902 11:48:58.042245 All Pass.
1903 11:48:58.042705
1904 11:48:58.043070 CH 1, Rank 0
1905 11:48:58.045453 SW Impedance : PASS
1906 11:48:58.045916 DUTY Scan : NO K
1907 11:48:58.048824 ZQ Calibration : PASS
1908 11:48:58.052255 Jitter Meter : NO K
1909 11:48:58.052785 CBT Training : PASS
1910 11:48:58.055525 Write leveling : PASS
1911 11:48:58.058918 RX DQS gating : PASS
1912 11:48:58.059379 RX DQ/DQS(RDDQC) : PASS
1913 11:48:58.062218 TX DQ/DQS : PASS
1914 11:48:58.062680 RX DATLAT : PASS
1915 11:48:58.065741 RX DQ/DQS(Engine): PASS
1916 11:48:58.069073 TX OE : NO K
1917 11:48:58.069544 All Pass.
1918 11:48:58.069904
1919 11:48:58.070243 CH 1, Rank 1
1920 11:48:58.072295 SW Impedance : PASS
1921 11:48:58.075827 DUTY Scan : NO K
1922 11:48:58.076286 ZQ Calibration : PASS
1923 11:48:58.079247 Jitter Meter : NO K
1924 11:48:58.082244 CBT Training : PASS
1925 11:48:58.082705 Write leveling : PASS
1926 11:48:58.085943 RX DQS gating : PASS
1927 11:48:58.088934 RX DQ/DQS(RDDQC) : PASS
1928 11:48:58.089690 TX DQ/DQS : PASS
1929 11:48:58.092252 RX DATLAT : PASS
1930 11:48:58.095731 RX DQ/DQS(Engine): PASS
1931 11:48:58.096191 TX OE : NO K
1932 11:48:58.099059 All Pass.
1933 11:48:58.099519
1934 11:48:58.099880 DramC Write-DBI off
1935 11:48:58.102301 PER_BANK_REFRESH: Hybrid Mode
1936 11:48:58.102762 TX_TRACKING: ON
1937 11:48:58.105819 [GetDramInforAfterCalByMRR] Vendor 6.
1938 11:48:58.108956 [GetDramInforAfterCalByMRR] Revision 606.
1939 11:48:58.115931 [GetDramInforAfterCalByMRR] Revision 2 0.
1940 11:48:58.116496 MR0 0x3939
1941 11:48:58.116956 MR8 0x1111
1942 11:48:58.119316 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1943 11:48:58.119777
1944 11:48:58.122492 MR0 0x3939
1945 11:48:58.123013 MR8 0x1111
1946 11:48:58.125685 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1947 11:48:58.126293
1948 11:48:58.136109 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1949 11:48:58.139147 [FAST_K] Save calibration result to emmc
1950 11:48:58.142478 [FAST_K] Save calibration result to emmc
1951 11:48:58.145717 dram_init: config_dvfs: 1
1952 11:48:58.148977 dramc_set_vcore_voltage set vcore to 662500
1953 11:48:58.149439 Read voltage for 1200, 2
1954 11:48:58.152490 Vio18 = 0
1955 11:48:58.153095 Vcore = 662500
1956 11:48:58.153466 Vdram = 0
1957 11:48:58.155992 Vddq = 0
1958 11:48:58.156600 Vmddr = 0
1959 11:48:58.162441 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1960 11:48:58.165839 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1961 11:48:58.169316 MEM_TYPE=3, freq_sel=15
1962 11:48:58.172479 sv_algorithm_assistance_LP4_1600
1963 11:48:58.175613 ============ PULL DRAM RESETB DOWN ============
1964 11:48:58.179215 ========== PULL DRAM RESETB DOWN end =========
1965 11:48:58.185991 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1966 11:48:58.189328 ===================================
1967 11:48:58.189890 LPDDR4 DRAM CONFIGURATION
1968 11:48:58.192299 ===================================
1969 11:48:58.196184 EX_ROW_EN[0] = 0x0
1970 11:48:58.196793 EX_ROW_EN[1] = 0x0
1971 11:48:58.199385 LP4Y_EN = 0x0
1972 11:48:58.199934 WORK_FSP = 0x0
1973 11:48:58.202454 WL = 0x4
1974 11:48:58.202917 RL = 0x4
1975 11:48:58.205739 BL = 0x2
1976 11:48:58.208956 RPST = 0x0
1977 11:48:58.209424 RD_PRE = 0x0
1978 11:48:58.212475 WR_PRE = 0x1
1979 11:48:58.212967 WR_PST = 0x0
1980 11:48:58.216077 DBI_WR = 0x0
1981 11:48:58.216574 DBI_RD = 0x0
1982 11:48:58.219357 OTF = 0x1
1983 11:48:58.222564 ===================================
1984 11:48:58.226206 ===================================
1985 11:48:58.226665 ANA top config
1986 11:48:58.228988 ===================================
1987 11:48:58.232178 DLL_ASYNC_EN = 0
1988 11:48:58.235832 ALL_SLAVE_EN = 0
1989 11:48:58.236388 NEW_RANK_MODE = 1
1990 11:48:58.239155 DLL_IDLE_MODE = 1
1991 11:48:58.242794 LP45_APHY_COMB_EN = 1
1992 11:48:58.245875 TX_ODT_DIS = 1
1993 11:48:58.246439 NEW_8X_MODE = 1
1994 11:48:58.249425 ===================================
1995 11:48:58.252677 ===================================
1996 11:48:58.256159 data_rate = 2400
1997 11:48:58.259252 CKR = 1
1998 11:48:58.262716 DQ_P2S_RATIO = 8
1999 11:48:58.265968 ===================================
2000 11:48:58.269384 CA_P2S_RATIO = 8
2001 11:48:58.272444 DQ_CA_OPEN = 0
2002 11:48:58.273049 DQ_SEMI_OPEN = 0
2003 11:48:58.275870 CA_SEMI_OPEN = 0
2004 11:48:58.279056 CA_FULL_RATE = 0
2005 11:48:58.282485 DQ_CKDIV4_EN = 0
2006 11:48:58.285712 CA_CKDIV4_EN = 0
2007 11:48:58.289222 CA_PREDIV_EN = 0
2008 11:48:58.289782 PH8_DLY = 17
2009 11:48:58.292289 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2010 11:48:58.295868 DQ_AAMCK_DIV = 4
2011 11:48:58.299123 CA_AAMCK_DIV = 4
2012 11:48:58.302535 CA_ADMCK_DIV = 4
2013 11:48:58.305444 DQ_TRACK_CA_EN = 0
2014 11:48:58.309187 CA_PICK = 1200
2015 11:48:58.309748 CA_MCKIO = 1200
2016 11:48:58.311839 MCKIO_SEMI = 0
2017 11:48:58.315402 PLL_FREQ = 2366
2018 11:48:58.318758 DQ_UI_PI_RATIO = 32
2019 11:48:58.322063 CA_UI_PI_RATIO = 0
2020 11:48:58.325317 ===================================
2021 11:48:58.328664 ===================================
2022 11:48:58.332096 memory_type:LPDDR4
2023 11:48:58.332602 GP_NUM : 10
2024 11:48:58.335558 SRAM_EN : 1
2025 11:48:58.336134 MD32_EN : 0
2026 11:48:58.338763 ===================================
2027 11:48:58.342133 [ANA_INIT] >>>>>>>>>>>>>>
2028 11:48:58.345591 <<<<<< [CONFIGURE PHASE]: ANA_TX
2029 11:48:58.348883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2030 11:48:58.352245 ===================================
2031 11:48:58.355393 data_rate = 2400,PCW = 0X5b00
2032 11:48:58.358424 ===================================
2033 11:48:58.362142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2034 11:48:58.368859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2035 11:48:58.371794 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2036 11:48:58.378706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2037 11:48:58.382062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2038 11:48:58.385218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2039 11:48:58.385897 [ANA_INIT] flow start
2040 11:48:58.388730 [ANA_INIT] PLL >>>>>>>>
2041 11:48:58.392152 [ANA_INIT] PLL <<<<<<<<
2042 11:48:58.392744 [ANA_INIT] MIDPI >>>>>>>>
2043 11:48:58.395172 [ANA_INIT] MIDPI <<<<<<<<
2044 11:48:58.398728 [ANA_INIT] DLL >>>>>>>>
2045 11:48:58.399288 [ANA_INIT] DLL <<<<<<<<
2046 11:48:58.401796 [ANA_INIT] flow end
2047 11:48:58.405194 ============ LP4 DIFF to SE enter ============
2048 11:48:58.408258 ============ LP4 DIFF to SE exit ============
2049 11:48:58.412076 [ANA_INIT] <<<<<<<<<<<<<
2050 11:48:58.415241 [Flow] Enable top DCM control >>>>>
2051 11:48:58.418489 [Flow] Enable top DCM control <<<<<
2052 11:48:58.421830 Enable DLL master slave shuffle
2053 11:48:58.429121 ==============================================================
2054 11:48:58.429686 Gating Mode config
2055 11:48:58.435529 ==============================================================
2056 11:48:58.436091 Config description:
2057 11:48:58.445156 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2058 11:48:58.451925 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2059 11:48:58.458617 SELPH_MODE 0: By rank 1: By Phase
2060 11:48:58.461560 ==============================================================
2061 11:48:58.465121 GAT_TRACK_EN = 1
2062 11:48:58.468436 RX_GATING_MODE = 2
2063 11:48:58.471581 RX_GATING_TRACK_MODE = 2
2064 11:48:58.474900 SELPH_MODE = 1
2065 11:48:58.478700 PICG_EARLY_EN = 1
2066 11:48:58.482028 VALID_LAT_VALUE = 1
2067 11:48:58.488558 ==============================================================
2068 11:48:58.491984 Enter into Gating configuration >>>>
2069 11:48:58.492595 Exit from Gating configuration <<<<
2070 11:48:58.495303 Enter into DVFS_PRE_config >>>>>
2071 11:48:58.508637 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2072 11:48:58.511568 Exit from DVFS_PRE_config <<<<<
2073 11:48:58.515451 Enter into PICG configuration >>>>
2074 11:48:58.518478 Exit from PICG configuration <<<<
2075 11:48:58.519038 [RX_INPUT] configuration >>>>>
2076 11:48:58.521653 [RX_INPUT] configuration <<<<<
2077 11:48:58.528264 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2078 11:48:58.531983 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2079 11:48:58.538552 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2080 11:48:58.545513 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2081 11:48:58.552050 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2082 11:48:58.558531 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2083 11:48:58.562017 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2084 11:48:58.565216 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2085 11:48:58.568317 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2086 11:48:58.575374 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2087 11:48:58.579030 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2088 11:48:58.582004 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2089 11:48:58.585309 ===================================
2090 11:48:58.589016 LPDDR4 DRAM CONFIGURATION
2091 11:48:58.591851 ===================================
2092 11:48:58.595373 EX_ROW_EN[0] = 0x0
2093 11:48:58.595991 EX_ROW_EN[1] = 0x0
2094 11:48:58.598604 LP4Y_EN = 0x0
2095 11:48:58.599162 WORK_FSP = 0x0
2096 11:48:58.601637 WL = 0x4
2097 11:48:58.602095 RL = 0x4
2098 11:48:58.605281 BL = 0x2
2099 11:48:58.605842 RPST = 0x0
2100 11:48:58.608293 RD_PRE = 0x0
2101 11:48:58.608825 WR_PRE = 0x1
2102 11:48:58.611984 WR_PST = 0x0
2103 11:48:58.612584 DBI_WR = 0x0
2104 11:48:58.615113 DBI_RD = 0x0
2105 11:48:58.615673 OTF = 0x1
2106 11:48:58.618537 ===================================
2107 11:48:58.621827 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2108 11:48:58.628270 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2109 11:48:58.631753 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2110 11:48:58.635408 ===================================
2111 11:48:58.638697 LPDDR4 DRAM CONFIGURATION
2112 11:48:58.641751 ===================================
2113 11:48:58.642314 EX_ROW_EN[0] = 0x10
2114 11:48:58.645068 EX_ROW_EN[1] = 0x0
2115 11:48:58.648410 LP4Y_EN = 0x0
2116 11:48:58.649008 WORK_FSP = 0x0
2117 11:48:58.651707 WL = 0x4
2118 11:48:58.652264 RL = 0x4
2119 11:48:58.654977 BL = 0x2
2120 11:48:58.655536 RPST = 0x0
2121 11:48:58.658413 RD_PRE = 0x0
2122 11:48:58.658974 WR_PRE = 0x1
2123 11:48:58.661632 WR_PST = 0x0
2124 11:48:58.662093 DBI_WR = 0x0
2125 11:48:58.664980 DBI_RD = 0x0
2126 11:48:58.665536 OTF = 0x1
2127 11:48:58.668135 ===================================
2128 11:48:58.675060 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2129 11:48:58.675622 ==
2130 11:48:58.678516 Dram Type= 6, Freq= 0, CH_0, rank 0
2131 11:48:58.681785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2132 11:48:58.682376 ==
2133 11:48:58.685142 [Duty_Offset_Calibration]
2134 11:48:58.688445 B0:0 B1:2 CA:1
2135 11:48:58.688976
2136 11:48:58.691451 [DutyScan_Calibration_Flow] k_type=0
2137 11:48:58.699850
2138 11:48:58.700448 ==CLK 0==
2139 11:48:58.703126 Final CLK duty delay cell = 0
2140 11:48:58.706325 [0] MAX Duty = 5093%(X100), DQS PI = 12
2141 11:48:58.709620 [0] MIN Duty = 4938%(X100), DQS PI = 54
2142 11:48:58.710085 [0] AVG Duty = 5015%(X100)
2143 11:48:58.713431
2144 11:48:58.716339 CH0 CLK Duty spec in!! Max-Min= 155%
2145 11:48:58.719908 [DutyScan_Calibration_Flow] ====Done====
2146 11:48:58.720482
2147 11:48:58.723166 [DutyScan_Calibration_Flow] k_type=1
2148 11:48:58.739292
2149 11:48:58.739863 ==DQS 0 ==
2150 11:48:58.742547 Final DQS duty delay cell = 0
2151 11:48:58.745846 [0] MAX Duty = 5125%(X100), DQS PI = 32
2152 11:48:58.749474 [0] MIN Duty = 5031%(X100), DQS PI = 6
2153 11:48:58.750046 [0] AVG Duty = 5078%(X100)
2154 11:48:58.752697
2155 11:48:58.753263 ==DQS 1 ==
2156 11:48:58.756064 Final DQS duty delay cell = 0
2157 11:48:58.759295 [0] MAX Duty = 5062%(X100), DQS PI = 58
2158 11:48:58.762960 [0] MIN Duty = 4906%(X100), DQS PI = 16
2159 11:48:58.763532 [0] AVG Duty = 4984%(X100)
2160 11:48:58.765781
2161 11:48:58.769243 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2162 11:48:58.769813
2163 11:48:58.772850 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2164 11:48:58.775847 [DutyScan_Calibration_Flow] ====Done====
2165 11:48:58.776435
2166 11:48:58.779210 [DutyScan_Calibration_Flow] k_type=3
2167 11:48:58.796437
2168 11:48:58.797055 ==DQM 0 ==
2169 11:48:58.799727 Final DQM duty delay cell = 0
2170 11:48:58.803069 [0] MAX Duty = 5156%(X100), DQS PI = 20
2171 11:48:58.806592 [0] MIN Duty = 4969%(X100), DQS PI = 40
2172 11:48:58.809685 [0] AVG Duty = 5062%(X100)
2173 11:48:58.810190
2174 11:48:58.810679 ==DQM 1 ==
2175 11:48:58.812966 Final DQM duty delay cell = 4
2176 11:48:58.816605 [4] MAX Duty = 5187%(X100), DQS PI = 54
2177 11:48:58.819577 [4] MIN Duty = 5000%(X100), DQS PI = 16
2178 11:48:58.820025 [4] AVG Duty = 5093%(X100)
2179 11:48:58.823008
2180 11:48:58.826289 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2181 11:48:58.826775
2182 11:48:58.829726 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2183 11:48:58.832909 [DutyScan_Calibration_Flow] ====Done====
2184 11:48:58.833384
2185 11:48:58.836363 [DutyScan_Calibration_Flow] k_type=2
2186 11:48:58.851371
2187 11:48:58.851928 ==DQ 0 ==
2188 11:48:58.854823 Final DQ duty delay cell = -4
2189 11:48:58.857981 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2190 11:48:58.861819 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2191 11:48:58.864823 [-4] AVG Duty = 4937%(X100)
2192 11:48:58.865385
2193 11:48:58.865746 ==DQ 1 ==
2194 11:48:58.868204 Final DQ duty delay cell = -4
2195 11:48:58.871482 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2196 11:48:58.874572 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2197 11:48:58.877780 [-4] AVG Duty = 4969%(X100)
2198 11:48:58.878242
2199 11:48:58.881088 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2200 11:48:58.881548
2201 11:48:58.884436 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2202 11:48:58.887871 [DutyScan_Calibration_Flow] ====Done====
2203 11:48:58.888331 ==
2204 11:48:58.891487 Dram Type= 6, Freq= 0, CH_1, rank 0
2205 11:48:58.894913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2206 11:48:58.895477 ==
2207 11:48:58.898126 [Duty_Offset_Calibration]
2208 11:48:58.898765 B0:0 B1:5 CA:-5
2209 11:48:58.899140
2210 11:48:58.900971 [DutyScan_Calibration_Flow] k_type=0
2211 11:48:58.912121
2212 11:48:58.912709 ==CLK 0==
2213 11:48:58.915401 Final CLK duty delay cell = 0
2214 11:48:58.918729 [0] MAX Duty = 5094%(X100), DQS PI = 24
2215 11:48:58.921766 [0] MIN Duty = 4875%(X100), DQS PI = 46
2216 11:48:58.922228 [0] AVG Duty = 4984%(X100)
2217 11:48:58.925099
2218 11:48:58.928436 CH1 CLK Duty spec in!! Max-Min= 219%
2219 11:48:58.931906 [DutyScan_Calibration_Flow] ====Done====
2220 11:48:58.932367
2221 11:48:58.935097 [DutyScan_Calibration_Flow] k_type=1
2222 11:48:58.950689
2223 11:48:58.951244 ==DQS 0 ==
2224 11:48:58.953902 Final DQS duty delay cell = 0
2225 11:48:58.957338 [0] MAX Duty = 5125%(X100), DQS PI = 16
2226 11:48:58.960625 [0] MIN Duty = 4875%(X100), DQS PI = 40
2227 11:48:58.963947 [0] AVG Duty = 5000%(X100)
2228 11:48:58.964550
2229 11:48:58.964931 ==DQS 1 ==
2230 11:48:58.967280 Final DQS duty delay cell = -4
2231 11:48:58.970721 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2232 11:48:58.973979 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2233 11:48:58.977224 [-4] AVG Duty = 4953%(X100)
2234 11:48:58.977788
2235 11:48:58.981083 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2236 11:48:58.981644
2237 11:48:58.983836 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2238 11:48:58.987407 [DutyScan_Calibration_Flow] ====Done====
2239 11:48:58.987968
2240 11:48:58.990369 [DutyScan_Calibration_Flow] k_type=3
2241 11:48:59.005511
2242 11:48:59.006135 ==DQM 0 ==
2243 11:48:59.008695 Final DQM duty delay cell = -4
2244 11:48:59.012029 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2245 11:48:59.015549 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2246 11:48:59.018864 [-4] AVG Duty = 4969%(X100)
2247 11:48:59.019430
2248 11:48:59.019799 ==DQM 1 ==
2249 11:48:59.022095 Final DQM duty delay cell = -4
2250 11:48:59.025530 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2251 11:48:59.028887 [-4] MIN Duty = 4906%(X100), DQS PI = 58
2252 11:48:59.032221 [-4] AVG Duty = 5000%(X100)
2253 11:48:59.032837
2254 11:48:59.035689 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2255 11:48:59.036278
2256 11:48:59.038914 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2257 11:48:59.042003 [DutyScan_Calibration_Flow] ====Done====
2258 11:48:59.042534
2259 11:48:59.045355 [DutyScan_Calibration_Flow] k_type=2
2260 11:48:59.062788
2261 11:48:59.063341 ==DQ 0 ==
2262 11:48:59.066432 Final DQ duty delay cell = 0
2263 11:48:59.069574 [0] MAX Duty = 5093%(X100), DQS PI = 0
2264 11:48:59.072846 [0] MIN Duty = 4938%(X100), DQS PI = 44
2265 11:48:59.073410 [0] AVG Duty = 5015%(X100)
2266 11:48:59.073776
2267 11:48:59.076325 ==DQ 1 ==
2268 11:48:59.079530 Final DQ duty delay cell = 0
2269 11:48:59.082884 [0] MAX Duty = 5031%(X100), DQS PI = 8
2270 11:48:59.086237 [0] MIN Duty = 4907%(X100), DQS PI = 0
2271 11:48:59.086800 [0] AVG Duty = 4969%(X100)
2272 11:48:59.087168
2273 11:48:59.089703 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2274 11:48:59.090262
2275 11:48:59.092948 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2276 11:48:59.099595 [DutyScan_Calibration_Flow] ====Done====
2277 11:48:59.103063 nWR fixed to 30
2278 11:48:59.103642 [ModeRegInit_LP4] CH0 RK0
2279 11:48:59.105878 [ModeRegInit_LP4] CH0 RK1
2280 11:48:59.109252 [ModeRegInit_LP4] CH1 RK0
2281 11:48:59.109815 [ModeRegInit_LP4] CH1 RK1
2282 11:48:59.112711 match AC timing 6
2283 11:48:59.115922 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2284 11:48:59.119487 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2285 11:48:59.125813 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2286 11:48:59.129263 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2287 11:48:59.136139 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2288 11:48:59.136757 ==
2289 11:48:59.139395 Dram Type= 6, Freq= 0, CH_0, rank 0
2290 11:48:59.143196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2291 11:48:59.143777 ==
2292 11:48:59.149285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2293 11:48:59.152461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2294 11:48:59.162348 [CA 0] Center 39 (9~70) winsize 62
2295 11:48:59.165460 [CA 1] Center 39 (8~70) winsize 63
2296 11:48:59.168973 [CA 2] Center 36 (5~67) winsize 63
2297 11:48:59.172149 [CA 3] Center 35 (4~66) winsize 63
2298 11:48:59.175422 [CA 4] Center 34 (3~65) winsize 63
2299 11:48:59.178669 [CA 5] Center 33 (3~64) winsize 62
2300 11:48:59.179127
2301 11:48:59.182063 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2302 11:48:59.182618
2303 11:48:59.185752 [CATrainingPosCal] consider 1 rank data
2304 11:48:59.189265 u2DelayCellTimex100 = 270/100 ps
2305 11:48:59.192377 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2306 11:48:59.195526 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2307 11:48:59.202431 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2308 11:48:59.205448 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2309 11:48:59.208734 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2310 11:48:59.212292 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2311 11:48:59.212979
2312 11:48:59.215561 CA PerBit enable=1, Macro0, CA PI delay=33
2313 11:48:59.216012
2314 11:48:59.219162 [CBTSetCACLKResult] CA Dly = 33
2315 11:48:59.219619 CS Dly: 7 (0~38)
2316 11:48:59.222502 ==
2317 11:48:59.223055 Dram Type= 6, Freq= 0, CH_0, rank 1
2318 11:48:59.228919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2319 11:48:59.229381 ==
2320 11:48:59.232331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2321 11:48:59.239132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2322 11:48:59.247973 [CA 0] Center 39 (8~70) winsize 63
2323 11:48:59.251183 [CA 1] Center 38 (8~69) winsize 62
2324 11:48:59.254642 [CA 2] Center 36 (5~67) winsize 63
2325 11:48:59.257789 [CA 3] Center 35 (4~66) winsize 63
2326 11:48:59.261001 [CA 4] Center 33 (3~64) winsize 62
2327 11:48:59.264376 [CA 5] Center 34 (3~65) winsize 63
2328 11:48:59.264977
2329 11:48:59.268258 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2330 11:48:59.268865
2331 11:48:59.271239 [CATrainingPosCal] consider 2 rank data
2332 11:48:59.274620 u2DelayCellTimex100 = 270/100 ps
2333 11:48:59.277931 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2334 11:48:59.281457 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2335 11:48:59.288184 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2336 11:48:59.291136 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2337 11:48:59.294784 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2338 11:48:59.297847 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2339 11:48:59.298405
2340 11:48:59.301177 CA PerBit enable=1, Macro0, CA PI delay=33
2341 11:48:59.301734
2342 11:48:59.304638 [CBTSetCACLKResult] CA Dly = 33
2343 11:48:59.305194 CS Dly: 8 (0~40)
2344 11:48:59.305566
2345 11:48:59.307998 ----->DramcWriteLeveling(PI) begin...
2346 11:48:59.310997 ==
2347 11:48:59.311681 Dram Type= 6, Freq= 0, CH_0, rank 0
2348 11:48:59.318083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2349 11:48:59.318641 ==
2350 11:48:59.321097 Write leveling (Byte 0): 27 => 27
2351 11:48:59.324794 Write leveling (Byte 1): 27 => 27
2352 11:48:59.327917 DramcWriteLeveling(PI) end<-----
2353 11:48:59.328472
2354 11:48:59.328892 ==
2355 11:48:59.331233 Dram Type= 6, Freq= 0, CH_0, rank 0
2356 11:48:59.334735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2357 11:48:59.335205 ==
2358 11:48:59.337842 [Gating] SW mode calibration
2359 11:48:59.344613 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2360 11:48:59.347944 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2361 11:48:59.354578 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2362 11:48:59.358339 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2363 11:48:59.361154 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2364 11:48:59.368022 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2365 11:48:59.371273 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2366 11:48:59.374637 0 11 20 | B1->B0 | 2f2f 2b2b | 0 0 | (0 1) (0 0)
2367 11:48:59.381149 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2368 11:48:59.384666 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2369 11:48:59.387971 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2370 11:48:59.394668 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2371 11:48:59.397803 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2372 11:48:59.401351 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2373 11:48:59.407741 0 12 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2374 11:48:59.411248 0 12 20 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (0 0)
2375 11:48:59.414592 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2376 11:48:59.421327 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2377 11:48:59.424625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2378 11:48:59.428171 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2379 11:48:59.434336 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2380 11:48:59.437697 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2381 11:48:59.441099 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2382 11:48:59.444472 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2383 11:48:59.451114 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2384 11:48:59.454653 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2385 11:48:59.457932 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2386 11:48:59.464415 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2387 11:48:59.467871 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2388 11:48:59.471227 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2389 11:48:59.477903 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2390 11:48:59.481026 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2391 11:48:59.484466 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2392 11:48:59.491226 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2393 11:48:59.494560 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2394 11:48:59.497502 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2395 11:48:59.504230 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2396 11:48:59.507746 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2397 11:48:59.511053 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2398 11:48:59.517720 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2399 11:48:59.521115 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2400 11:48:59.524420 Total UI for P1: 0, mck2ui 16
2401 11:48:59.527674 best dqsien dly found for B0: ( 0, 15, 20)
2402 11:48:59.530903 Total UI for P1: 0, mck2ui 16
2403 11:48:59.534173 best dqsien dly found for B1: ( 0, 15, 18)
2404 11:48:59.537574 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2405 11:48:59.541215 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2406 11:48:59.541776
2407 11:48:59.544280 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2408 11:48:59.547858 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2409 11:48:59.551147 [Gating] SW calibration Done
2410 11:48:59.551710 ==
2411 11:48:59.554457 Dram Type= 6, Freq= 0, CH_0, rank 0
2412 11:48:59.557487 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2413 11:48:59.558051 ==
2414 11:48:59.561042 RX Vref Scan: 0
2415 11:48:59.561602
2416 11:48:59.564066 RX Vref 0 -> 0, step: 1
2417 11:48:59.564677
2418 11:48:59.565063 RX Delay -40 -> 252, step: 8
2419 11:48:59.571072 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2420 11:48:59.574531 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2421 11:48:59.578172 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2422 11:48:59.581112 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2423 11:48:59.584410 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2424 11:48:59.591162 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2425 11:48:59.594629 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2426 11:48:59.597839 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2427 11:48:59.601168 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2428 11:48:59.604531 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2429 11:48:59.611258 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2430 11:48:59.614352 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2431 11:48:59.617605 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2432 11:48:59.621066 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2433 11:48:59.624085 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2434 11:48:59.630763 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2435 11:48:59.631326 ==
2436 11:48:59.634121 Dram Type= 6, Freq= 0, CH_0, rank 0
2437 11:48:59.637461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2438 11:48:59.637930 ==
2439 11:48:59.638392 DQS Delay:
2440 11:48:59.640814 DQS0 = 0, DQS1 = 0
2441 11:48:59.641280 DQM Delay:
2442 11:48:59.644387 DQM0 = 115, DQM1 = 106
2443 11:48:59.644979 DQ Delay:
2444 11:48:59.647738 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2445 11:48:59.651190 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2446 11:48:59.654534 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2447 11:48:59.657793 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2448 11:48:59.658354
2449 11:48:59.658731
2450 11:48:59.661094 ==
2451 11:48:59.661667 Dram Type= 6, Freq= 0, CH_0, rank 0
2452 11:48:59.667742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2453 11:48:59.668305 ==
2454 11:48:59.668721
2455 11:48:59.669065
2456 11:48:59.670967 TX Vref Scan disable
2457 11:48:59.671527 == TX Byte 0 ==
2458 11:48:59.674420 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2459 11:48:59.680858 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2460 11:48:59.681417 == TX Byte 1 ==
2461 11:48:59.683948 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2462 11:48:59.690743 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2463 11:48:59.691294 ==
2464 11:48:59.693907 Dram Type= 6, Freq= 0, CH_0, rank 0
2465 11:48:59.697549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2466 11:48:59.698112 ==
2467 11:48:59.709106 TX Vref=22, minBit 10, minWin=25, winSum=421
2468 11:48:59.712768 TX Vref=24, minBit 15, minWin=25, winSum=426
2469 11:48:59.715931 TX Vref=26, minBit 1, minWin=26, winSum=429
2470 11:48:59.719429 TX Vref=28, minBit 2, minWin=27, winSum=437
2471 11:48:59.722849 TX Vref=30, minBit 5, minWin=26, winSum=434
2472 11:48:59.729439 TX Vref=32, minBit 10, minWin=26, winSum=437
2473 11:48:59.732711 [TxChooseVref] Worse bit 2, Min win 27, Win sum 437, Final Vref 28
2474 11:48:59.733184
2475 11:48:59.736035 Final TX Range 1 Vref 28
2476 11:48:59.736503
2477 11:48:59.736918 ==
2478 11:48:59.739318 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 11:48:59.742909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2480 11:48:59.743471 ==
2481 11:48:59.746043
2482 11:48:59.746506
2483 11:48:59.746870 TX Vref Scan disable
2484 11:48:59.749314 == TX Byte 0 ==
2485 11:48:59.753075 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2486 11:48:59.756191 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2487 11:48:59.759700 == TX Byte 1 ==
2488 11:48:59.762975 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2489 11:48:59.766127 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2490 11:48:59.766595
2491 11:48:59.769524 [DATLAT]
2492 11:48:59.770082 Freq=1200, CH0 RK0
2493 11:48:59.770456
2494 11:48:59.773101 DATLAT Default: 0xd
2495 11:48:59.773654 0, 0xFFFF, sum = 0
2496 11:48:59.776087 1, 0xFFFF, sum = 0
2497 11:48:59.776541 2, 0xFFFF, sum = 0
2498 11:48:59.779523 3, 0xFFFF, sum = 0
2499 11:48:59.779995 4, 0xFFFF, sum = 0
2500 11:48:59.782763 5, 0xFFFF, sum = 0
2501 11:48:59.783234 6, 0xFFFF, sum = 0
2502 11:48:59.786409 7, 0xFFFF, sum = 0
2503 11:48:59.786974 8, 0xFFFF, sum = 0
2504 11:48:59.789546 9, 0xFFFF, sum = 0
2505 11:48:59.790016 10, 0xFFFF, sum = 0
2506 11:48:59.793041 11, 0x0, sum = 1
2507 11:48:59.793611 12, 0x0, sum = 2
2508 11:48:59.796483 13, 0x0, sum = 3
2509 11:48:59.797095 14, 0x0, sum = 4
2510 11:48:59.799634 best_step = 12
2511 11:48:59.800187
2512 11:48:59.800604 ==
2513 11:48:59.802756 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 11:48:59.806282 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2515 11:48:59.806843 ==
2516 11:48:59.809894 RX Vref Scan: 1
2517 11:48:59.810450
2518 11:48:59.810822 Set Vref Range= 32 -> 127
2519 11:48:59.811170
2520 11:48:59.812749 RX Vref 32 -> 127, step: 1
2521 11:48:59.813216
2522 11:48:59.815930 RX Delay -21 -> 252, step: 4
2523 11:48:59.816627
2524 11:48:59.819234 Set Vref, RX VrefLevel [Byte0]: 32
2525 11:48:59.822856 [Byte1]: 32
2526 11:48:59.823321
2527 11:48:59.825934 Set Vref, RX VrefLevel [Byte0]: 33
2528 11:48:59.829277 [Byte1]: 33
2529 11:48:59.833737
2530 11:48:59.834201 Set Vref, RX VrefLevel [Byte0]: 34
2531 11:48:59.836982 [Byte1]: 34
2532 11:48:59.841820
2533 11:48:59.842376 Set Vref, RX VrefLevel [Byte0]: 35
2534 11:48:59.845007 [Byte1]: 35
2535 11:48:59.849799
2536 11:48:59.850353 Set Vref, RX VrefLevel [Byte0]: 36
2537 11:48:59.853127 [Byte1]: 36
2538 11:48:59.857806
2539 11:48:59.858365 Set Vref, RX VrefLevel [Byte0]: 37
2540 11:48:59.860976 [Byte1]: 37
2541 11:48:59.865350
2542 11:48:59.865916 Set Vref, RX VrefLevel [Byte0]: 38
2543 11:48:59.868846 [Byte1]: 38
2544 11:48:59.873475
2545 11:48:59.874029 Set Vref, RX VrefLevel [Byte0]: 39
2546 11:48:59.876663 [Byte1]: 39
2547 11:48:59.881287
2548 11:48:59.881858 Set Vref, RX VrefLevel [Byte0]: 40
2549 11:48:59.884792 [Byte1]: 40
2550 11:48:59.889401
2551 11:48:59.889957 Set Vref, RX VrefLevel [Byte0]: 41
2552 11:48:59.892803 [Byte1]: 41
2553 11:48:59.897311
2554 11:48:59.897868 Set Vref, RX VrefLevel [Byte0]: 42
2555 11:48:59.900549 [Byte1]: 42
2556 11:48:59.905120
2557 11:48:59.905680 Set Vref, RX VrefLevel [Byte0]: 43
2558 11:48:59.908217 [Byte1]: 43
2559 11:48:59.913205
2560 11:48:59.913765 Set Vref, RX VrefLevel [Byte0]: 44
2561 11:48:59.916295 [Byte1]: 44
2562 11:48:59.921141
2563 11:48:59.921696 Set Vref, RX VrefLevel [Byte0]: 45
2564 11:48:59.924013 [Byte1]: 45
2565 11:48:59.929243
2566 11:48:59.929806 Set Vref, RX VrefLevel [Byte0]: 46
2567 11:48:59.932029 [Byte1]: 46
2568 11:48:59.936621
2569 11:48:59.937087 Set Vref, RX VrefLevel [Byte0]: 47
2570 11:48:59.940420 [Byte1]: 47
2571 11:48:59.944471
2572 11:48:59.944970 Set Vref, RX VrefLevel [Byte0]: 48
2573 11:48:59.947732 [Byte1]: 48
2574 11:48:59.952401
2575 11:48:59.952903 Set Vref, RX VrefLevel [Byte0]: 49
2576 11:48:59.955929 [Byte1]: 49
2577 11:48:59.960348
2578 11:48:59.960846 Set Vref, RX VrefLevel [Byte0]: 50
2579 11:48:59.963666 [Byte1]: 50
2580 11:48:59.968475
2581 11:48:59.969069 Set Vref, RX VrefLevel [Byte0]: 51
2582 11:48:59.971747 [Byte1]: 51
2583 11:48:59.976656
2584 11:48:59.977227 Set Vref, RX VrefLevel [Byte0]: 52
2585 11:48:59.979788 [Byte1]: 52
2586 11:48:59.984379
2587 11:48:59.984982 Set Vref, RX VrefLevel [Byte0]: 53
2588 11:48:59.987576 [Byte1]: 53
2589 11:48:59.992570
2590 11:48:59.993124 Set Vref, RX VrefLevel [Byte0]: 54
2591 11:48:59.995567 [Byte1]: 54
2592 11:49:00.000148
2593 11:49:00.000751 Set Vref, RX VrefLevel [Byte0]: 55
2594 11:49:00.003639 [Byte1]: 55
2595 11:49:00.008256
2596 11:49:00.008871 Set Vref, RX VrefLevel [Byte0]: 56
2597 11:49:00.011495 [Byte1]: 56
2598 11:49:00.015752
2599 11:49:00.016417 Set Vref, RX VrefLevel [Byte0]: 57
2600 11:49:00.019406 [Byte1]: 57
2601 11:49:00.023788
2602 11:49:00.024344 Set Vref, RX VrefLevel [Byte0]: 58
2603 11:49:00.027068 [Byte1]: 58
2604 11:49:00.031719
2605 11:49:00.032182 Set Vref, RX VrefLevel [Byte0]: 59
2606 11:49:00.034944 [Byte1]: 59
2607 11:49:00.040038
2608 11:49:00.040644 Set Vref, RX VrefLevel [Byte0]: 60
2609 11:49:00.043150 [Byte1]: 60
2610 11:49:00.047934
2611 11:49:00.048536 Set Vref, RX VrefLevel [Byte0]: 61
2612 11:49:00.051218 [Byte1]: 61
2613 11:49:00.055671
2614 11:49:00.056230 Set Vref, RX VrefLevel [Byte0]: 62
2615 11:49:00.058998 [Byte1]: 62
2616 11:49:00.063497
2617 11:49:00.064056 Set Vref, RX VrefLevel [Byte0]: 63
2618 11:49:00.067123 [Byte1]: 63
2619 11:49:00.071439
2620 11:49:00.071997 Set Vref, RX VrefLevel [Byte0]: 64
2621 11:49:00.074663 [Byte1]: 64
2622 11:49:00.079742
2623 11:49:00.080298 Set Vref, RX VrefLevel [Byte0]: 65
2624 11:49:00.082818 [Byte1]: 65
2625 11:49:00.087379
2626 11:49:00.088098 Set Vref, RX VrefLevel [Byte0]: 66
2627 11:49:00.090814 [Byte1]: 66
2628 11:49:00.095298
2629 11:49:00.095862 Final RX Vref Byte 0 = 49 to rank0
2630 11:49:00.098619 Final RX Vref Byte 1 = 49 to rank0
2631 11:49:00.102003 Final RX Vref Byte 0 = 49 to rank1
2632 11:49:00.105458 Final RX Vref Byte 1 = 49 to rank1==
2633 11:49:00.108554 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 11:49:00.114950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2635 11:49:00.115506 ==
2636 11:49:00.115882 DQS Delay:
2637 11:49:00.116229 DQS0 = 0, DQS1 = 0
2638 11:49:00.118590 DQM Delay:
2639 11:49:00.119154 DQM0 = 114, DQM1 = 105
2640 11:49:00.121924 DQ Delay:
2641 11:49:00.125152 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =110
2642 11:49:00.128300 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2643 11:49:00.131739 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =98
2644 11:49:00.134955 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2645 11:49:00.135424
2646 11:49:00.135875
2647 11:49:00.141701 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2648 11:49:00.144980 CH0 RK0: MR19=404, MR18=606
2649 11:49:00.151680 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
2650 11:49:00.152150
2651 11:49:00.154970 ----->DramcWriteLeveling(PI) begin...
2652 11:49:00.155441 ==
2653 11:49:00.158606 Dram Type= 6, Freq= 0, CH_0, rank 1
2654 11:49:00.161842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2655 11:49:00.162173 ==
2656 11:49:00.164887 Write leveling (Byte 0): 28 => 28
2657 11:49:00.168226 Write leveling (Byte 1): 25 => 25
2658 11:49:00.171356 DramcWriteLeveling(PI) end<-----
2659 11:49:00.171550
2660 11:49:00.171706 ==
2661 11:49:00.174787 Dram Type= 6, Freq= 0, CH_0, rank 1
2662 11:49:00.178020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2663 11:49:00.181270 ==
2664 11:49:00.181407 [Gating] SW mode calibration
2665 11:49:00.191272 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2666 11:49:00.194859 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2667 11:49:00.198232 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2668 11:49:00.204907 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2669 11:49:00.208182 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2670 11:49:00.211792 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2671 11:49:00.218454 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2672 11:49:00.221470 0 11 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2673 11:49:00.224940 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2674 11:49:00.231646 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2675 11:49:00.234527 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2676 11:49:00.237998 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2677 11:49:00.244928 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2678 11:49:00.248298 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2679 11:49:00.251567 0 12 16 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2680 11:49:00.258606 0 12 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2681 11:49:00.261508 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2682 11:49:00.264969 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2683 11:49:00.271639 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2684 11:49:00.274640 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2685 11:49:00.278238 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2686 11:49:00.281729 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2687 11:49:00.288370 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2688 11:49:00.291675 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2689 11:49:00.295043 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2690 11:49:00.301793 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2691 11:49:00.304915 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2692 11:49:00.308396 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2693 11:49:00.314815 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2694 11:49:00.318106 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2695 11:49:00.321286 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2696 11:49:00.328022 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2697 11:49:00.331545 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2698 11:49:00.334590 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2699 11:49:00.341251 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2700 11:49:00.344622 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2701 11:49:00.348213 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2702 11:49:00.354741 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2703 11:49:00.357875 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2704 11:49:00.361098 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2705 11:49:00.368485 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2706 11:49:00.369100 Total UI for P1: 0, mck2ui 16
2707 11:49:00.374820 best dqsien dly found for B0: ( 0, 15, 18)
2708 11:49:00.378071 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2709 11:49:00.381270 Total UI for P1: 0, mck2ui 16
2710 11:49:00.384484 best dqsien dly found for B1: ( 0, 15, 22)
2711 11:49:00.388433 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2712 11:49:00.391874 best DQS1 dly(MCK, UI, PI) = (0, 15, 22)
2713 11:49:00.392440
2714 11:49:00.395122 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2715 11:49:00.398016 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 22)
2716 11:49:00.401291 [Gating] SW calibration Done
2717 11:49:00.401760 ==
2718 11:49:00.405028 Dram Type= 6, Freq= 0, CH_0, rank 1
2719 11:49:00.408435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2720 11:49:00.409058 ==
2721 11:49:00.411463 RX Vref Scan: 0
2722 11:49:00.411926
2723 11:49:00.414641 RX Vref 0 -> 0, step: 1
2724 11:49:00.415107
2725 11:49:00.415473 RX Delay -40 -> 252, step: 8
2726 11:49:00.421575 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2727 11:49:00.424809 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2728 11:49:00.428247 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2729 11:49:00.431695 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2730 11:49:00.435425 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2731 11:49:00.441801 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2732 11:49:00.445192 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2733 11:49:00.448299 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2734 11:49:00.451607 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2735 11:49:00.454839 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2736 11:49:00.458319 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2737 11:49:00.465096 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2738 11:49:00.468388 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2739 11:49:00.471696 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2740 11:49:00.475068 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2741 11:49:00.481800 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2742 11:49:00.482357 ==
2743 11:49:00.485075 Dram Type= 6, Freq= 0, CH_0, rank 1
2744 11:49:00.488604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2745 11:49:00.489171 ==
2746 11:49:00.489544 DQS Delay:
2747 11:49:00.491910 DQS0 = 0, DQS1 = 0
2748 11:49:00.492468 DQM Delay:
2749 11:49:00.495205 DQM0 = 114, DQM1 = 106
2750 11:49:00.495757 DQ Delay:
2751 11:49:00.498617 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2752 11:49:00.501932 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2753 11:49:00.505151 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2754 11:49:00.508610 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2755 11:49:00.509170
2756 11:49:00.509542
2757 11:49:00.509884 ==
2758 11:49:00.511726 Dram Type= 6, Freq= 0, CH_0, rank 1
2759 11:49:00.515174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2760 11:49:00.518392 ==
2761 11:49:00.518978
2762 11:49:00.519355
2763 11:49:00.519691 TX Vref Scan disable
2764 11:49:00.522191 == TX Byte 0 ==
2765 11:49:00.525402 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2766 11:49:00.528494 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2767 11:49:00.532029 == TX Byte 1 ==
2768 11:49:00.535008 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2769 11:49:00.538365 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2770 11:49:00.541655 ==
2771 11:49:00.542121 Dram Type= 6, Freq= 0, CH_0, rank 1
2772 11:49:00.548177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2773 11:49:00.548761 ==
2774 11:49:00.559904 TX Vref=22, minBit 13, minWin=24, winSum=421
2775 11:49:00.562956 TX Vref=24, minBit 1, minWin=26, winSum=427
2776 11:49:00.566363 TX Vref=26, minBit 8, minWin=26, winSum=430
2777 11:49:00.569660 TX Vref=28, minBit 9, minWin=26, winSum=432
2778 11:49:00.572890 TX Vref=30, minBit 9, minWin=26, winSum=435
2779 11:49:00.579575 TX Vref=32, minBit 8, minWin=26, winSum=432
2780 11:49:00.583079 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
2781 11:49:00.583644
2782 11:49:00.586262 Final TX Range 1 Vref 30
2783 11:49:00.586823
2784 11:49:00.587196 ==
2785 11:49:00.589706 Dram Type= 6, Freq= 0, CH_0, rank 1
2786 11:49:00.593156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2787 11:49:00.593725 ==
2788 11:49:00.596151
2789 11:49:00.596754
2790 11:49:00.597134 TX Vref Scan disable
2791 11:49:00.599475 == TX Byte 0 ==
2792 11:49:00.602598 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2793 11:49:00.606224 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2794 11:49:00.609362 == TX Byte 1 ==
2795 11:49:00.612917 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2796 11:49:00.616100 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2797 11:49:00.619199
2798 11:49:00.619701 [DATLAT]
2799 11:49:00.620184 Freq=1200, CH0 RK1
2800 11:49:00.620762
2801 11:49:00.622751 DATLAT Default: 0xc
2802 11:49:00.623234 0, 0xFFFF, sum = 0
2803 11:49:00.626102 1, 0xFFFF, sum = 0
2804 11:49:00.626591 2, 0xFFFF, sum = 0
2805 11:49:00.629161 3, 0xFFFF, sum = 0
2806 11:49:00.632493 4, 0xFFFF, sum = 0
2807 11:49:00.633018 5, 0xFFFF, sum = 0
2808 11:49:00.635830 6, 0xFFFF, sum = 0
2809 11:49:00.636377 7, 0xFFFF, sum = 0
2810 11:49:00.639215 8, 0xFFFF, sum = 0
2811 11:49:00.639700 9, 0xFFFF, sum = 0
2812 11:49:00.642945 10, 0xFFFF, sum = 0
2813 11:49:00.643523 11, 0x0, sum = 1
2814 11:49:00.646426 12, 0x0, sum = 2
2815 11:49:00.647138 13, 0x0, sum = 3
2816 11:49:00.649371 14, 0x0, sum = 4
2817 11:49:00.649864 best_step = 12
2818 11:49:00.650348
2819 11:49:00.650810 ==
2820 11:49:00.652623 Dram Type= 6, Freq= 0, CH_0, rank 1
2821 11:49:00.656014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2822 11:49:00.656628 ==
2823 11:49:00.659314 RX Vref Scan: 0
2824 11:49:00.659886
2825 11:49:00.662685 RX Vref 0 -> 0, step: 1
2826 11:49:00.663262
2827 11:49:00.663766 RX Delay -21 -> 252, step: 4
2828 11:49:00.670313 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2829 11:49:00.673193 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2830 11:49:00.676869 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2831 11:49:00.679920 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2832 11:49:00.683314 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2833 11:49:00.690356 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2834 11:49:00.693455 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2835 11:49:00.696670 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2836 11:49:00.700063 iDelay=195, Bit 8, Center 92 (31 ~ 154) 124
2837 11:49:00.703381 iDelay=195, Bit 9, Center 88 (27 ~ 150) 124
2838 11:49:00.709947 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2839 11:49:00.713498 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2840 11:49:00.716548 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2841 11:49:00.719947 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2842 11:49:00.723054 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
2843 11:49:00.730100 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2844 11:49:00.730676 ==
2845 11:49:00.733252 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 11:49:00.736322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2847 11:49:00.736868 ==
2848 11:49:00.737354 DQS Delay:
2849 11:49:00.739820 DQS0 = 0, DQS1 = 0
2850 11:49:00.740301 DQM Delay:
2851 11:49:00.743365 DQM0 = 115, DQM1 = 104
2852 11:49:00.743939 DQ Delay:
2853 11:49:00.746427 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2854 11:49:00.749891 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2855 11:49:00.753211 DQ8 =92, DQ9 =88, DQ10 =110, DQ11 =96
2856 11:49:00.756634 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =114
2857 11:49:00.757238
2858 11:49:00.757735
2859 11:49:00.766890 [DQSOSCAuto] RK1, (LSB)MR18= 0x1212, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2860 11:49:00.769813 CH0 RK1: MR19=404, MR18=1212
2861 11:49:00.773379 CH0_RK1: MR19=0x404, MR18=0x1212, DQSOSC=403, MR23=63, INC=40, DEC=26
2862 11:49:00.776495 [RxdqsGatingPostProcess] freq 1200
2863 11:49:00.782888 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2864 11:49:00.786458 Pre-setting of DQS Precalculation
2865 11:49:00.789690 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2866 11:49:00.793282 ==
2867 11:49:00.796464 Dram Type= 6, Freq= 0, CH_1, rank 0
2868 11:49:00.799525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2869 11:49:00.800107 ==
2870 11:49:00.803301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2871 11:49:00.809427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2872 11:49:00.818676 [CA 0] Center 37 (7~68) winsize 62
2873 11:49:00.822049 [CA 1] Center 37 (7~68) winsize 62
2874 11:49:00.825255 [CA 2] Center 34 (4~65) winsize 62
2875 11:49:00.828445 [CA 3] Center 33 (3~64) winsize 62
2876 11:49:00.831636 [CA 4] Center 32 (1~63) winsize 63
2877 11:49:00.834991 [CA 5] Center 32 (2~63) winsize 62
2878 11:49:00.835475
2879 11:49:00.838369 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2880 11:49:00.838853
2881 11:49:00.842037 [CATrainingPosCal] consider 1 rank data
2882 11:49:00.845615 u2DelayCellTimex100 = 270/100 ps
2883 11:49:00.848396 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2884 11:49:00.852072 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2885 11:49:00.858527 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2886 11:49:00.861636 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2887 11:49:00.865374 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2888 11:49:00.868332 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2889 11:49:00.868962
2890 11:49:00.871866 CA PerBit enable=1, Macro0, CA PI delay=32
2891 11:49:00.872350
2892 11:49:00.875103 [CBTSetCACLKResult] CA Dly = 32
2893 11:49:00.875680 CS Dly: 6 (0~37)
2894 11:49:00.878470 ==
2895 11:49:00.879046 Dram Type= 6, Freq= 0, CH_1, rank 1
2896 11:49:00.885400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2897 11:49:00.885981 ==
2898 11:49:00.888701 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2899 11:49:00.895225 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2900 11:49:00.903753 [CA 0] Center 37 (7~68) winsize 62
2901 11:49:00.907145 [CA 1] Center 37 (7~68) winsize 62
2902 11:49:00.910353 [CA 2] Center 34 (3~65) winsize 63
2903 11:49:00.914002 [CA 3] Center 33 (3~64) winsize 62
2904 11:49:00.917324 [CA 4] Center 32 (2~63) winsize 62
2905 11:49:00.920307 [CA 5] Center 32 (2~63) winsize 62
2906 11:49:00.921063
2907 11:49:00.923980 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2908 11:49:00.924592
2909 11:49:00.926790 [CATrainingPosCal] consider 2 rank data
2910 11:49:00.930387 u2DelayCellTimex100 = 270/100 ps
2911 11:49:00.933596 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2912 11:49:00.937210 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2913 11:49:00.943909 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2914 11:49:00.947205 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2915 11:49:00.950550 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2916 11:49:00.953796 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2917 11:49:00.954373
2918 11:49:00.957562 CA PerBit enable=1, Macro0, CA PI delay=32
2919 11:49:00.958143
2920 11:49:00.960898 [CBTSetCACLKResult] CA Dly = 32
2921 11:49:00.961501 CS Dly: 6 (0~38)
2922 11:49:00.962004
2923 11:49:00.964208 ----->DramcWriteLeveling(PI) begin...
2924 11:49:00.964836 ==
2925 11:49:00.967210 Dram Type= 6, Freq= 0, CH_1, rank 0
2926 11:49:00.974483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2927 11:49:00.975063 ==
2928 11:49:00.977086 Write leveling (Byte 0): 22 => 22
2929 11:49:00.980698 Write leveling (Byte 1): 22 => 22
2930 11:49:00.981277 DramcWriteLeveling(PI) end<-----
2931 11:49:00.983961
2932 11:49:00.984562 ==
2933 11:49:00.987269 Dram Type= 6, Freq= 0, CH_1, rank 0
2934 11:49:00.990754 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2935 11:49:00.991336 ==
2936 11:49:00.994174 [Gating] SW mode calibration
2937 11:49:01.000596 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2938 11:49:01.004042 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2939 11:49:01.010357 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2940 11:49:01.014097 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2941 11:49:01.017437 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2942 11:49:01.024099 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2943 11:49:01.027121 0 11 16 | B1->B0 | 3030 2424 | 0 0 | (0 0) (1 0)
2944 11:49:01.030951 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2945 11:49:01.037090 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2946 11:49:01.040967 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2947 11:49:01.044122 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2948 11:49:01.050607 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2949 11:49:01.054238 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2950 11:49:01.057225 0 12 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2951 11:49:01.063869 0 12 16 | B1->B0 | 3030 4040 | 0 0 | (1 1) (0 0)
2952 11:49:01.067479 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 11:49:01.070096 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 11:49:01.076860 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2955 11:49:01.080556 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2956 11:49:01.083763 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 11:49:01.090060 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2958 11:49:01.094003 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2959 11:49:01.096969 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2960 11:49:01.103887 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2961 11:49:01.106792 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:49:01.109891 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 11:49:01.116848 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 11:49:01.120185 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 11:49:01.123633 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 11:49:01.129981 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 11:49:01.133320 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 11:49:01.136435 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 11:49:01.139603 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 11:49:01.146355 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 11:49:01.149370 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 11:49:01.153110 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 11:49:01.159844 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 11:49:01.162804 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 11:49:01.166541 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2976 11:49:01.173056 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2977 11:49:01.176564 Total UI for P1: 0, mck2ui 16
2978 11:49:01.179784 best dqsien dly found for B0: ( 0, 15, 16)
2979 11:49:01.182775 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 11:49:01.186505 Total UI for P1: 0, mck2ui 16
2981 11:49:01.189732 best dqsien dly found for B1: ( 0, 15, 18)
2982 11:49:01.193113 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2983 11:49:01.196448 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2984 11:49:01.197066
2985 11:49:01.199789 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2986 11:49:01.203191 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2987 11:49:01.206423 [Gating] SW calibration Done
2988 11:49:01.206889 ==
2989 11:49:01.209578 Dram Type= 6, Freq= 0, CH_1, rank 0
2990 11:49:01.216341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2991 11:49:01.216939 ==
2992 11:49:01.217313 RX Vref Scan: 0
2993 11:49:01.217658
2994 11:49:01.219463 RX Vref 0 -> 0, step: 1
2995 11:49:01.219929
2996 11:49:01.222922 RX Delay -40 -> 252, step: 8
2997 11:49:01.226159 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
2998 11:49:01.229654 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
2999 11:49:01.232935 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3000 11:49:01.236417 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3001 11:49:01.242947 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3002 11:49:01.246416 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3003 11:49:01.249792 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3004 11:49:01.253166 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3005 11:49:01.256458 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3006 11:49:01.262896 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3007 11:49:01.266291 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3008 11:49:01.269565 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3009 11:49:01.272742 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3010 11:49:01.276659 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3011 11:49:01.282866 iDelay=208, Bit 14, Center 115 (48 ~ 183) 136
3012 11:49:01.286191 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3013 11:49:01.286680 ==
3014 11:49:01.289680 Dram Type= 6, Freq= 0, CH_1, rank 0
3015 11:49:01.293353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3016 11:49:01.293913 ==
3017 11:49:01.296339 DQS Delay:
3018 11:49:01.296836 DQS0 = 0, DQS1 = 0
3019 11:49:01.297213 DQM Delay:
3020 11:49:01.299775 DQM0 = 116, DQM1 = 108
3021 11:49:01.300374 DQ Delay:
3022 11:49:01.303060 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3023 11:49:01.306216 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3024 11:49:01.309821 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3025 11:49:01.312805 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3026 11:49:01.316268
3027 11:49:01.316881
3028 11:49:01.317257 ==
3029 11:49:01.319475 Dram Type= 6, Freq= 0, CH_1, rank 0
3030 11:49:01.323246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3031 11:49:01.324050 ==
3032 11:49:01.324677
3033 11:49:01.325049
3034 11:49:01.325783 TX Vref Scan disable
3035 11:49:01.326163 == TX Byte 0 ==
3036 11:49:01.333208 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3037 11:49:01.335920 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3038 11:49:01.336387 == TX Byte 1 ==
3039 11:49:01.342666 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3040 11:49:01.346185 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3041 11:49:01.346747 ==
3042 11:49:01.349493 Dram Type= 6, Freq= 0, CH_1, rank 0
3043 11:49:01.352826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3044 11:49:01.353387 ==
3045 11:49:01.364886 TX Vref=22, minBit 8, minWin=25, winSum=420
3046 11:49:01.368163 TX Vref=24, minBit 8, minWin=25, winSum=423
3047 11:49:01.371469 TX Vref=26, minBit 8, minWin=26, winSum=432
3048 11:49:01.374879 TX Vref=28, minBit 8, minWin=26, winSum=431
3049 11:49:01.378417 TX Vref=30, minBit 9, minWin=26, winSum=432
3050 11:49:01.385088 TX Vref=32, minBit 9, minWin=25, winSum=430
3051 11:49:01.388128 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 26
3052 11:49:01.388758
3053 11:49:01.391192 Final TX Range 1 Vref 26
3054 11:49:01.391755
3055 11:49:01.392124 ==
3056 11:49:01.395334 Dram Type= 6, Freq= 0, CH_1, rank 0
3057 11:49:01.398042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3058 11:49:01.398608 ==
3059 11:49:01.401546
3060 11:49:01.402104
3061 11:49:01.402471 TX Vref Scan disable
3062 11:49:01.404639 == TX Byte 0 ==
3063 11:49:01.407938 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3064 11:49:01.411398 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3065 11:49:01.414554 == TX Byte 1 ==
3066 11:49:01.418098 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3067 11:49:01.421080 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3068 11:49:01.424601
3069 11:49:01.425104 [DATLAT]
3070 11:49:01.425482 Freq=1200, CH1 RK0
3071 11:49:01.425829
3072 11:49:01.427647 DATLAT Default: 0xd
3073 11:49:01.428112 0, 0xFFFF, sum = 0
3074 11:49:01.431301 1, 0xFFFF, sum = 0
3075 11:49:01.431867 2, 0xFFFF, sum = 0
3076 11:49:01.434977 3, 0xFFFF, sum = 0
3077 11:49:01.435544 4, 0xFFFF, sum = 0
3078 11:49:01.437903 5, 0xFFFF, sum = 0
3079 11:49:01.441110 6, 0xFFFF, sum = 0
3080 11:49:01.441583 7, 0xFFFF, sum = 0
3081 11:49:01.444907 8, 0xFFFF, sum = 0
3082 11:49:01.445474 9, 0xFFFF, sum = 0
3083 11:49:01.447879 10, 0xFFFF, sum = 0
3084 11:49:01.448446 11, 0x0, sum = 1
3085 11:49:01.451109 12, 0x0, sum = 2
3086 11:49:01.451582 13, 0x0, sum = 3
3087 11:49:01.451965 14, 0x0, sum = 4
3088 11:49:01.454684 best_step = 12
3089 11:49:01.455243
3090 11:49:01.455617 ==
3091 11:49:01.457778 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 11:49:01.461514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3093 11:49:01.462072 ==
3094 11:49:01.464723 RX Vref Scan: 1
3095 11:49:01.465283
3096 11:49:01.467952 Set Vref Range= 32 -> 127
3097 11:49:01.468421
3098 11:49:01.468835 RX Vref 32 -> 127, step: 1
3099 11:49:01.469186
3100 11:49:01.471314 RX Delay -21 -> 252, step: 4
3101 11:49:01.471874
3102 11:49:01.474688 Set Vref, RX VrefLevel [Byte0]: 32
3103 11:49:01.477763 [Byte1]: 32
3104 11:49:01.481377
3105 11:49:01.481935 Set Vref, RX VrefLevel [Byte0]: 33
3106 11:49:01.484309 [Byte1]: 33
3107 11:49:01.489431
3108 11:49:01.489986 Set Vref, RX VrefLevel [Byte0]: 34
3109 11:49:01.492302 [Byte1]: 34
3110 11:49:01.497588
3111 11:49:01.498155 Set Vref, RX VrefLevel [Byte0]: 35
3112 11:49:01.500472 [Byte1]: 35
3113 11:49:01.505438
3114 11:49:01.506016 Set Vref, RX VrefLevel [Byte0]: 36
3115 11:49:01.508283 [Byte1]: 36
3116 11:49:01.513103
3117 11:49:01.513666 Set Vref, RX VrefLevel [Byte0]: 37
3118 11:49:01.515895 [Byte1]: 37
3119 11:49:01.520732
3120 11:49:01.521286 Set Vref, RX VrefLevel [Byte0]: 38
3121 11:49:01.524072 [Byte1]: 38
3122 11:49:01.528708
3123 11:49:01.529176 Set Vref, RX VrefLevel [Byte0]: 39
3124 11:49:01.532317 [Byte1]: 39
3125 11:49:01.536977
3126 11:49:01.537612 Set Vref, RX VrefLevel [Byte0]: 40
3127 11:49:01.539863 [Byte1]: 40
3128 11:49:01.544559
3129 11:49:01.545126 Set Vref, RX VrefLevel [Byte0]: 41
3130 11:49:01.547946 [Byte1]: 41
3131 11:49:01.552638
3132 11:49:01.553202 Set Vref, RX VrefLevel [Byte0]: 42
3133 11:49:01.555989 [Byte1]: 42
3134 11:49:01.560627
3135 11:49:01.561189 Set Vref, RX VrefLevel [Byte0]: 43
3136 11:49:01.563888 [Byte1]: 43
3137 11:49:01.568358
3138 11:49:01.568965 Set Vref, RX VrefLevel [Byte0]: 44
3139 11:49:01.571696 [Byte1]: 44
3140 11:49:01.576502
3141 11:49:01.577110 Set Vref, RX VrefLevel [Byte0]: 45
3142 11:49:01.579726 [Byte1]: 45
3143 11:49:01.584317
3144 11:49:01.584926 Set Vref, RX VrefLevel [Byte0]: 46
3145 11:49:01.587744 [Byte1]: 46
3146 11:49:01.592254
3147 11:49:01.592865 Set Vref, RX VrefLevel [Byte0]: 47
3148 11:49:01.595387 [Byte1]: 47
3149 11:49:01.600251
3150 11:49:01.600907 Set Vref, RX VrefLevel [Byte0]: 48
3151 11:49:01.603575 [Byte1]: 48
3152 11:49:01.608064
3153 11:49:01.608717 Set Vref, RX VrefLevel [Byte0]: 49
3154 11:49:01.611167 [Byte1]: 49
3155 11:49:01.615862
3156 11:49:01.616426 Set Vref, RX VrefLevel [Byte0]: 50
3157 11:49:01.618993 [Byte1]: 50
3158 11:49:01.623791
3159 11:49:01.624388 Set Vref, RX VrefLevel [Byte0]: 51
3160 11:49:01.626754 [Byte1]: 51
3161 11:49:01.631631
3162 11:49:01.632097 Set Vref, RX VrefLevel [Byte0]: 52
3163 11:49:01.634871 [Byte1]: 52
3164 11:49:01.639287
3165 11:49:01.639753 Set Vref, RX VrefLevel [Byte0]: 53
3166 11:49:01.642825 [Byte1]: 53
3167 11:49:01.647617
3168 11:49:01.648174 Set Vref, RX VrefLevel [Byte0]: 54
3169 11:49:01.650607 [Byte1]: 54
3170 11:49:01.655337
3171 11:49:01.655900 Set Vref, RX VrefLevel [Byte0]: 55
3172 11:49:01.658834 [Byte1]: 55
3173 11:49:01.663372
3174 11:49:01.663937 Set Vref, RX VrefLevel [Byte0]: 56
3175 11:49:01.666728 [Byte1]: 56
3176 11:49:01.671087
3177 11:49:01.671647 Set Vref, RX VrefLevel [Byte0]: 57
3178 11:49:01.674616 [Byte1]: 57
3179 11:49:01.679413
3180 11:49:01.679971 Set Vref, RX VrefLevel [Byte0]: 58
3181 11:49:01.682503 [Byte1]: 58
3182 11:49:01.686942
3183 11:49:01.687497 Set Vref, RX VrefLevel [Byte0]: 59
3184 11:49:01.690276 [Byte1]: 59
3185 11:49:01.694811
3186 11:49:01.695277 Set Vref, RX VrefLevel [Byte0]: 60
3187 11:49:01.698204 [Byte1]: 60
3188 11:49:01.702879
3189 11:49:01.703440 Set Vref, RX VrefLevel [Byte0]: 61
3190 11:49:01.706348 [Byte1]: 61
3191 11:49:01.710916
3192 11:49:01.711474 Set Vref, RX VrefLevel [Byte0]: 62
3193 11:49:01.714109 [Byte1]: 62
3194 11:49:01.718898
3195 11:49:01.719455 Set Vref, RX VrefLevel [Byte0]: 63
3196 11:49:01.722105 [Byte1]: 63
3197 11:49:01.726598
3198 11:49:01.727069 Set Vref, RX VrefLevel [Byte0]: 64
3199 11:49:01.729814 [Byte1]: 64
3200 11:49:01.734501
3201 11:49:01.734968 Set Vref, RX VrefLevel [Byte0]: 65
3202 11:49:01.737567 [Byte1]: 65
3203 11:49:01.742337
3204 11:49:01.742859 Final RX Vref Byte 0 = 54 to rank0
3205 11:49:01.745519 Final RX Vref Byte 1 = 50 to rank0
3206 11:49:01.748940 Final RX Vref Byte 0 = 54 to rank1
3207 11:49:01.752157 Final RX Vref Byte 1 = 50 to rank1==
3208 11:49:01.755892 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 11:49:01.762342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3210 11:49:01.762897 ==
3211 11:49:01.763272 DQS Delay:
3212 11:49:01.763617 DQS0 = 0, DQS1 = 0
3213 11:49:01.765818 DQM Delay:
3214 11:49:01.766385 DQM0 = 115, DQM1 = 105
3215 11:49:01.769124 DQ Delay:
3216 11:49:01.772471 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3217 11:49:01.775831 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3218 11:49:01.778983 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3219 11:49:01.782330 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =116
3220 11:49:01.782887
3221 11:49:01.783258
3222 11:49:01.789084 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3223 11:49:01.792668 CH1 RK0: MR19=404, MR18=1818
3224 11:49:01.799242 CH1_RK0: MR19=0x404, MR18=0x1818, DQSOSC=400, MR23=63, INC=40, DEC=27
3225 11:49:01.799804
3226 11:49:01.802402 ----->DramcWriteLeveling(PI) begin...
3227 11:49:01.802973 ==
3228 11:49:01.805671 Dram Type= 6, Freq= 0, CH_1, rank 1
3229 11:49:01.809144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3230 11:49:01.812204 ==
3231 11:49:01.812802 Write leveling (Byte 0): 20 => 20
3232 11:49:01.815642 Write leveling (Byte 1): 25 => 25
3233 11:49:01.819246 DramcWriteLeveling(PI) end<-----
3234 11:49:01.819819
3235 11:49:01.820193 ==
3236 11:49:01.822434 Dram Type= 6, Freq= 0, CH_1, rank 1
3237 11:49:01.829110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3238 11:49:01.829676 ==
3239 11:49:01.830165 [Gating] SW mode calibration
3240 11:49:01.838886 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3241 11:49:01.842175 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3242 11:49:01.845954 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3243 11:49:01.852333 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3244 11:49:01.855535 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3245 11:49:01.859335 0 11 12 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
3246 11:49:01.865517 0 11 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
3247 11:49:01.868841 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3248 11:49:01.872154 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3249 11:49:01.878643 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3250 11:49:01.882113 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3251 11:49:01.885661 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3252 11:49:01.892216 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3253 11:49:01.895808 0 12 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
3254 11:49:01.898999 0 12 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
3255 11:49:01.905751 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 11:49:01.909192 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3257 11:49:01.912465 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3258 11:49:01.919170 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3259 11:49:01.922552 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3260 11:49:01.925575 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3261 11:49:01.929043 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3262 11:49:01.935597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3263 11:49:01.938997 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3264 11:49:01.942583 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 11:49:01.948974 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 11:49:01.952274 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 11:49:01.955557 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 11:49:01.962425 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 11:49:01.965918 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 11:49:01.969114 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 11:49:01.975706 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 11:49:01.978793 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 11:49:01.982305 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 11:49:01.989106 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 11:49:01.992154 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 11:49:01.995850 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 11:49:02.002315 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3278 11:49:02.005539 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3279 11:49:02.008831 Total UI for P1: 0, mck2ui 16
3280 11:49:02.012446 best dqsien dly found for B0: ( 0, 15, 12)
3281 11:49:02.015570 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3282 11:49:02.019070 Total UI for P1: 0, mck2ui 16
3283 11:49:02.022253 best dqsien dly found for B1: ( 0, 15, 16)
3284 11:49:02.025664 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3285 11:49:02.028720 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3286 11:49:02.029190
3287 11:49:02.032290 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3288 11:49:02.039100 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3289 11:49:02.039673 [Gating] SW calibration Done
3290 11:49:02.042401 ==
3291 11:49:02.042967 Dram Type= 6, Freq= 0, CH_1, rank 1
3292 11:49:02.048879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3293 11:49:02.049342 ==
3294 11:49:02.049710 RX Vref Scan: 0
3295 11:49:02.050050
3296 11:49:02.052131 RX Vref 0 -> 0, step: 1
3297 11:49:02.052637
3298 11:49:02.055409 RX Delay -40 -> 252, step: 8
3299 11:49:02.058711 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3300 11:49:02.061996 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3301 11:49:02.065262 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3302 11:49:02.072179 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3303 11:49:02.075628 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3304 11:49:02.078743 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3305 11:49:02.082257 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3306 11:49:02.085366 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3307 11:49:02.092327 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3308 11:49:02.095430 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3309 11:49:02.098946 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3310 11:49:02.102147 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3311 11:49:02.105295 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3312 11:49:02.112248 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3313 11:49:02.115464 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3314 11:49:02.118857 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3315 11:49:02.119413 ==
3316 11:49:02.122273 Dram Type= 6, Freq= 0, CH_1, rank 1
3317 11:49:02.125443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3318 11:49:02.126000 ==
3319 11:49:02.128640 DQS Delay:
3320 11:49:02.129106 DQS0 = 0, DQS1 = 0
3321 11:49:02.132010 DQM Delay:
3322 11:49:02.132468 DQM0 = 116, DQM1 = 106
3323 11:49:02.132895 DQ Delay:
3324 11:49:02.135565 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3325 11:49:02.138880 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3326 11:49:02.142180 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
3327 11:49:02.148966 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =111
3328 11:49:02.149519
3329 11:49:02.149888
3330 11:49:02.150229 ==
3331 11:49:02.152160 Dram Type= 6, Freq= 0, CH_1, rank 1
3332 11:49:02.155622 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3333 11:49:02.156186 ==
3334 11:49:02.156617
3335 11:49:02.156973
3336 11:49:02.158990 TX Vref Scan disable
3337 11:49:02.159546 == TX Byte 0 ==
3338 11:49:02.165586 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3339 11:49:02.168983 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3340 11:49:02.169541 == TX Byte 1 ==
3341 11:49:02.175450 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3342 11:49:02.179000 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3343 11:49:02.179519 ==
3344 11:49:02.182302 Dram Type= 6, Freq= 0, CH_1, rank 1
3345 11:49:02.185238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3346 11:49:02.185703 ==
3347 11:49:02.198518 TX Vref=22, minBit 0, minWin=25, winSum=419
3348 11:49:02.201945 TX Vref=24, minBit 3, minWin=26, winSum=423
3349 11:49:02.205045 TX Vref=26, minBit 4, minWin=26, winSum=426
3350 11:49:02.208619 TX Vref=28, minBit 8, minWin=26, winSum=428
3351 11:49:02.211581 TX Vref=30, minBit 9, minWin=26, winSum=428
3352 11:49:02.214906 TX Vref=32, minBit 9, minWin=26, winSum=432
3353 11:49:02.221714 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 32
3354 11:49:02.222269
3355 11:49:02.225217 Final TX Range 1 Vref 32
3356 11:49:02.225774
3357 11:49:02.226147 ==
3358 11:49:02.228085 Dram Type= 6, Freq= 0, CH_1, rank 1
3359 11:49:02.231679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3360 11:49:02.232200 ==
3361 11:49:02.235000
3362 11:49:02.235570
3363 11:49:02.235938 TX Vref Scan disable
3364 11:49:02.238106 == TX Byte 0 ==
3365 11:49:02.241628 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3366 11:49:02.244985 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3367 11:49:02.248342 == TX Byte 1 ==
3368 11:49:02.251883 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3369 11:49:02.258170 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3370 11:49:02.258725
3371 11:49:02.259100 [DATLAT]
3372 11:49:02.259437 Freq=1200, CH1 RK1
3373 11:49:02.259766
3374 11:49:02.261783 DATLAT Default: 0xc
3375 11:49:02.262345 0, 0xFFFF, sum = 0
3376 11:49:02.265164 1, 0xFFFF, sum = 0
3377 11:49:02.265728 2, 0xFFFF, sum = 0
3378 11:49:02.268121 3, 0xFFFF, sum = 0
3379 11:49:02.271447 4, 0xFFFF, sum = 0
3380 11:49:02.271931 5, 0xFFFF, sum = 0
3381 11:49:02.274704 6, 0xFFFF, sum = 0
3382 11:49:02.275170 7, 0xFFFF, sum = 0
3383 11:49:02.278016 8, 0xFFFF, sum = 0
3384 11:49:02.278578 9, 0xFFFF, sum = 0
3385 11:49:02.281471 10, 0xFFFF, sum = 0
3386 11:49:02.282034 11, 0x0, sum = 1
3387 11:49:02.284799 12, 0x0, sum = 2
3388 11:49:02.285365 13, 0x0, sum = 3
3389 11:49:02.288003 14, 0x0, sum = 4
3390 11:49:02.288612 best_step = 12
3391 11:49:02.288986
3392 11:49:02.289326 ==
3393 11:49:02.291430 Dram Type= 6, Freq= 0, CH_1, rank 1
3394 11:49:02.294769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3395 11:49:02.295337 ==
3396 11:49:02.297914 RX Vref Scan: 0
3397 11:49:02.298378
3398 11:49:02.301191 RX Vref 0 -> 0, step: 1
3399 11:49:02.301653
3400 11:49:02.302018 RX Delay -29 -> 252, step: 4
3401 11:49:02.308614 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3402 11:49:02.312016 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3403 11:49:02.315625 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3404 11:49:02.318899 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3405 11:49:02.322211 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3406 11:49:02.328388 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3407 11:49:02.331850 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3408 11:49:02.335112 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3409 11:49:02.338598 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3410 11:49:02.341736 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3411 11:49:02.348968 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3412 11:49:02.352191 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3413 11:49:02.355317 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3414 11:49:02.358321 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3415 11:49:02.361896 iDelay=199, Bit 14, Center 114 (47 ~ 182) 136
3416 11:49:02.368665 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3417 11:49:02.369227 ==
3418 11:49:02.371853 Dram Type= 6, Freq= 0, CH_1, rank 1
3419 11:49:02.375043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3420 11:49:02.375599 ==
3421 11:49:02.375975 DQS Delay:
3422 11:49:02.378452 DQS0 = 0, DQS1 = 0
3423 11:49:02.379011 DQM Delay:
3424 11:49:02.382157 DQM0 = 115, DQM1 = 103
3425 11:49:02.382719 DQ Delay:
3426 11:49:02.385189 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =112
3427 11:49:02.388466 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3428 11:49:02.391790 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3429 11:49:02.395185 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =110
3430 11:49:02.395748
3431 11:49:02.396120
3432 11:49:02.405208 [DQSOSCAuto] RK1, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3433 11:49:02.408386 CH1 RK1: MR19=404, MR18=909
3434 11:49:02.411960 CH1_RK1: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
3435 11:49:02.414997 [RxdqsGatingPostProcess] freq 1200
3436 11:49:02.421813 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3437 11:49:02.425070 Pre-setting of DQS Precalculation
3438 11:49:02.428647 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3439 11:49:02.438306 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3440 11:49:02.445179 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3441 11:49:02.445671
3442 11:49:02.446045
3443 11:49:02.448452 [Calibration Summary] 2400 Mbps
3444 11:49:02.448968 CH 0, Rank 0
3445 11:49:02.452037 SW Impedance : PASS
3446 11:49:02.452663 DUTY Scan : NO K
3447 11:49:02.455215 ZQ Calibration : PASS
3448 11:49:02.458366 Jitter Meter : NO K
3449 11:49:02.458838 CBT Training : PASS
3450 11:49:02.461965 Write leveling : PASS
3451 11:49:02.465197 RX DQS gating : PASS
3452 11:49:02.465666 RX DQ/DQS(RDDQC) : PASS
3453 11:49:02.468790 TX DQ/DQS : PASS
3454 11:49:02.469357 RX DATLAT : PASS
3455 11:49:02.471890 RX DQ/DQS(Engine): PASS
3456 11:49:02.475453 TX OE : NO K
3457 11:49:02.476031 All Pass.
3458 11:49:02.476406
3459 11:49:02.476811 CH 0, Rank 1
3460 11:49:02.478779 SW Impedance : PASS
3461 11:49:02.481996 DUTY Scan : NO K
3462 11:49:02.482568 ZQ Calibration : PASS
3463 11:49:02.485232 Jitter Meter : NO K
3464 11:49:02.488816 CBT Training : PASS
3465 11:49:02.489389 Write leveling : PASS
3466 11:49:02.491907 RX DQS gating : PASS
3467 11:49:02.495302 RX DQ/DQS(RDDQC) : PASS
3468 11:49:02.495872 TX DQ/DQS : PASS
3469 11:49:02.498590 RX DATLAT : PASS
3470 11:49:02.502256 RX DQ/DQS(Engine): PASS
3471 11:49:02.503017 TX OE : NO K
3472 11:49:02.505104 All Pass.
3473 11:49:02.505572
3474 11:49:02.505945 CH 1, Rank 0
3475 11:49:02.508694 SW Impedance : PASS
3476 11:49:02.509267 DUTY Scan : NO K
3477 11:49:02.512076 ZQ Calibration : PASS
3478 11:49:02.515201 Jitter Meter : NO K
3479 11:49:02.515752 CBT Training : PASS
3480 11:49:02.518640 Write leveling : PASS
3481 11:49:02.519207 RX DQS gating : PASS
3482 11:49:02.521981 RX DQ/DQS(RDDQC) : PASS
3483 11:49:02.525210 TX DQ/DQS : PASS
3484 11:49:02.525783 RX DATLAT : PASS
3485 11:49:02.528221 RX DQ/DQS(Engine): PASS
3486 11:49:02.531747 TX OE : NO K
3487 11:49:02.532220 All Pass.
3488 11:49:02.532698
3489 11:49:02.533062 CH 1, Rank 1
3490 11:49:02.534962 SW Impedance : PASS
3491 11:49:02.538440 DUTY Scan : NO K
3492 11:49:02.538907 ZQ Calibration : PASS
3493 11:49:02.541745 Jitter Meter : NO K
3494 11:49:02.545079 CBT Training : PASS
3495 11:49:02.545543 Write leveling : PASS
3496 11:49:02.548457 RX DQS gating : PASS
3497 11:49:02.552092 RX DQ/DQS(RDDQC) : PASS
3498 11:49:02.552692 TX DQ/DQS : PASS
3499 11:49:02.555467 RX DATLAT : PASS
3500 11:49:02.556028 RX DQ/DQS(Engine): PASS
3501 11:49:02.558550 TX OE : NO K
3502 11:49:02.559106 All Pass.
3503 11:49:02.559477
3504 11:49:02.561920 DramC Write-DBI off
3505 11:49:02.565362 PER_BANK_REFRESH: Hybrid Mode
3506 11:49:02.565917 TX_TRACKING: ON
3507 11:49:02.575283 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3508 11:49:02.578543 [FAST_K] Save calibration result to emmc
3509 11:49:02.581887 dramc_set_vcore_voltage set vcore to 650000
3510 11:49:02.585253 Read voltage for 600, 5
3511 11:49:02.585813 Vio18 = 0
3512 11:49:02.588655 Vcore = 650000
3513 11:49:02.589213 Vdram = 0
3514 11:49:02.589589 Vddq = 0
3515 11:49:02.589931 Vmddr = 0
3516 11:49:02.595314 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3517 11:49:02.598681 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3518 11:49:02.602109 MEM_TYPE=3, freq_sel=19
3519 11:49:02.605361 sv_algorithm_assistance_LP4_1600
3520 11:49:02.608571 ============ PULL DRAM RESETB DOWN ============
3521 11:49:02.612179 ========== PULL DRAM RESETB DOWN end =========
3522 11:49:02.618564 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3523 11:49:02.621976 ===================================
3524 11:49:02.625467 LPDDR4 DRAM CONFIGURATION
3525 11:49:02.628395 ===================================
3526 11:49:02.628915 EX_ROW_EN[0] = 0x0
3527 11:49:02.631811 EX_ROW_EN[1] = 0x0
3528 11:49:02.632277 LP4Y_EN = 0x0
3529 11:49:02.635504 WORK_FSP = 0x0
3530 11:49:02.636169 WL = 0x2
3531 11:49:02.638642 RL = 0x2
3532 11:49:02.639112 BL = 0x2
3533 11:49:02.641775 RPST = 0x0
3534 11:49:02.642242 RD_PRE = 0x0
3535 11:49:02.645009 WR_PRE = 0x1
3536 11:49:02.645481 WR_PST = 0x0
3537 11:49:02.648476 DBI_WR = 0x0
3538 11:49:02.648991 DBI_RD = 0x0
3539 11:49:02.651774 OTF = 0x1
3540 11:49:02.655578 ===================================
3541 11:49:02.658659 ===================================
3542 11:49:02.659224 ANA top config
3543 11:49:02.662287 ===================================
3544 11:49:02.665217 DLL_ASYNC_EN = 0
3545 11:49:02.668860 ALL_SLAVE_EN = 1
3546 11:49:02.672261 NEW_RANK_MODE = 1
3547 11:49:02.672891 DLL_IDLE_MODE = 1
3548 11:49:02.675451 LP45_APHY_COMB_EN = 1
3549 11:49:02.678826 TX_ODT_DIS = 1
3550 11:49:02.682095 NEW_8X_MODE = 1
3551 11:49:02.685286 ===================================
3552 11:49:02.688955 ===================================
3553 11:49:02.691847 data_rate = 1200
3554 11:49:02.692314 CKR = 1
3555 11:49:02.695565 DQ_P2S_RATIO = 8
3556 11:49:02.698856 ===================================
3557 11:49:02.702001 CA_P2S_RATIO = 8
3558 11:49:02.705201 DQ_CA_OPEN = 0
3559 11:49:02.708494 DQ_SEMI_OPEN = 0
3560 11:49:02.712239 CA_SEMI_OPEN = 0
3561 11:49:02.712857 CA_FULL_RATE = 0
3562 11:49:02.717589 DQ_CKDIV4_EN = 1
3563 11:49:02.718666 CA_CKDIV4_EN = 1
3564 11:49:02.721888 CA_PREDIV_EN = 0
3565 11:49:02.725020 PH8_DLY = 0
3566 11:49:02.728738 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3567 11:49:02.729299 DQ_AAMCK_DIV = 4
3568 11:49:02.731575 CA_AAMCK_DIV = 4
3569 11:49:02.735250 CA_ADMCK_DIV = 4
3570 11:49:02.738467 DQ_TRACK_CA_EN = 0
3571 11:49:02.741548 CA_PICK = 600
3572 11:49:02.744876 CA_MCKIO = 600
3573 11:49:02.745342 MCKIO_SEMI = 0
3574 11:49:02.748606 PLL_FREQ = 2288
3575 11:49:02.751560 DQ_UI_PI_RATIO = 32
3576 11:49:02.754892 CA_UI_PI_RATIO = 0
3577 11:49:02.758104 ===================================
3578 11:49:02.761662 ===================================
3579 11:49:02.764624 memory_type:LPDDR4
3580 11:49:02.765094 GP_NUM : 10
3581 11:49:02.768080 SRAM_EN : 1
3582 11:49:02.771658 MD32_EN : 0
3583 11:49:02.774644 ===================================
3584 11:49:02.775217 [ANA_INIT] >>>>>>>>>>>>>>
3585 11:49:02.778038 <<<<<< [CONFIGURE PHASE]: ANA_TX
3586 11:49:02.781198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3587 11:49:02.784637 ===================================
3588 11:49:02.787997 data_rate = 1200,PCW = 0X5800
3589 11:49:02.791524 ===================================
3590 11:49:02.794851 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3591 11:49:02.801241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3592 11:49:02.804495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3593 11:49:02.811035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3594 11:49:02.814552 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3595 11:49:02.817398 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3596 11:49:02.820910 [ANA_INIT] flow start
3597 11:49:02.821483 [ANA_INIT] PLL >>>>>>>>
3598 11:49:02.824305 [ANA_INIT] PLL <<<<<<<<
3599 11:49:02.827776 [ANA_INIT] MIDPI >>>>>>>>
3600 11:49:02.828347 [ANA_INIT] MIDPI <<<<<<<<
3601 11:49:02.830904 [ANA_INIT] DLL >>>>>>>>
3602 11:49:02.834004 [ANA_INIT] flow end
3603 11:49:02.837945 ============ LP4 DIFF to SE enter ============
3604 11:49:02.840688 ============ LP4 DIFF to SE exit ============
3605 11:49:02.844144 [ANA_INIT] <<<<<<<<<<<<<
3606 11:49:02.847393 [Flow] Enable top DCM control >>>>>
3607 11:49:02.850855 [Flow] Enable top DCM control <<<<<
3608 11:49:02.854155 Enable DLL master slave shuffle
3609 11:49:02.857464 ==============================================================
3610 11:49:02.861011 Gating Mode config
3611 11:49:02.867250 ==============================================================
3612 11:49:02.867722 Config description:
3613 11:49:02.877188 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3614 11:49:02.884035 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3615 11:49:02.887669 SELPH_MODE 0: By rank 1: By Phase
3616 11:49:02.893882 ==============================================================
3617 11:49:02.896988 GAT_TRACK_EN = 1
3618 11:49:02.900422 RX_GATING_MODE = 2
3619 11:49:02.903919 RX_GATING_TRACK_MODE = 2
3620 11:49:02.907287 SELPH_MODE = 1
3621 11:49:02.910327 PICG_EARLY_EN = 1
3622 11:49:02.913686 VALID_LAT_VALUE = 1
3623 11:49:02.916729 ==============================================================
3624 11:49:02.920384 Enter into Gating configuration >>>>
3625 11:49:02.923836 Exit from Gating configuration <<<<
3626 11:49:02.926828 Enter into DVFS_PRE_config >>>>>
3627 11:49:02.940166 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3628 11:49:02.943482 Exit from DVFS_PRE_config <<<<<
3629 11:49:02.943955 Enter into PICG configuration >>>>
3630 11:49:02.946864 Exit from PICG configuration <<<<
3631 11:49:02.950127 [RX_INPUT] configuration >>>>>
3632 11:49:02.953426 [RX_INPUT] configuration <<<<<
3633 11:49:02.960011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3634 11:49:02.963594 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3635 11:49:02.969923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3636 11:49:02.976405 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3637 11:49:02.983125 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3638 11:49:02.989583 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3639 11:49:02.993442 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3640 11:49:02.996030 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3641 11:49:03.002633 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3642 11:49:03.006047 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3643 11:49:03.009449 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3644 11:49:03.012910 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3645 11:49:03.016309 ===================================
3646 11:49:03.019703 LPDDR4 DRAM CONFIGURATION
3647 11:49:03.022765 ===================================
3648 11:49:03.025960 EX_ROW_EN[0] = 0x0
3649 11:49:03.026434 EX_ROW_EN[1] = 0x0
3650 11:49:03.029016 LP4Y_EN = 0x0
3651 11:49:03.029484 WORK_FSP = 0x0
3652 11:49:03.032653 WL = 0x2
3653 11:49:03.033128 RL = 0x2
3654 11:49:03.035868 BL = 0x2
3655 11:49:03.036336 RPST = 0x0
3656 11:49:03.039254 RD_PRE = 0x0
3657 11:49:03.039724 WR_PRE = 0x1
3658 11:49:03.042540 WR_PST = 0x0
3659 11:49:03.043013 DBI_WR = 0x0
3660 11:49:03.046144 DBI_RD = 0x0
3661 11:49:03.049307 OTF = 0x1
3662 11:49:03.049781 ===================================
3663 11:49:03.055966 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3664 11:49:03.059317 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3665 11:49:03.062613 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3666 11:49:03.065727 ===================================
3667 11:49:03.069051 LPDDR4 DRAM CONFIGURATION
3668 11:49:03.072314 ===================================
3669 11:49:03.075658 EX_ROW_EN[0] = 0x10
3670 11:49:03.076227 EX_ROW_EN[1] = 0x0
3671 11:49:03.079240 LP4Y_EN = 0x0
3672 11:49:03.079808 WORK_FSP = 0x0
3673 11:49:03.081987 WL = 0x2
3674 11:49:03.082457 RL = 0x2
3675 11:49:03.085409 BL = 0x2
3676 11:49:03.085892 RPST = 0x0
3677 11:49:03.088901 RD_PRE = 0x0
3678 11:49:03.089470 WR_PRE = 0x1
3679 11:49:03.091921 WR_PST = 0x0
3680 11:49:03.092388 DBI_WR = 0x0
3681 11:49:03.095312 DBI_RD = 0x0
3682 11:49:03.098699 OTF = 0x1
3683 11:49:03.102078 ===================================
3684 11:49:03.105398 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3685 11:49:03.110401 nWR fixed to 30
3686 11:49:03.113854 [ModeRegInit_LP4] CH0 RK0
3687 11:49:03.114431 [ModeRegInit_LP4] CH0 RK1
3688 11:49:03.116900 [ModeRegInit_LP4] CH1 RK0
3689 11:49:03.120466 [ModeRegInit_LP4] CH1 RK1
3690 11:49:03.121079 match AC timing 16
3691 11:49:03.127032 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3692 11:49:03.130294 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3693 11:49:03.133554 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3694 11:49:03.140168 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3695 11:49:03.143446 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3696 11:49:03.143920 ==
3697 11:49:03.146564 Dram Type= 6, Freq= 0, CH_0, rank 0
3698 11:49:03.149791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3699 11:49:03.150234 ==
3700 11:49:03.156896 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3701 11:49:03.163533 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3702 11:49:03.166548 [CA 0] Center 35 (5~66) winsize 62
3703 11:49:03.170266 [CA 1] Center 35 (5~66) winsize 62
3704 11:49:03.173323 [CA 2] Center 34 (4~65) winsize 62
3705 11:49:03.176472 [CA 3] Center 34 (4~65) winsize 62
3706 11:49:03.180273 [CA 4] Center 33 (3~64) winsize 62
3707 11:49:03.183264 [CA 5] Center 33 (3~64) winsize 62
3708 11:49:03.183834
3709 11:49:03.186703 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3710 11:49:03.187279
3711 11:49:03.189912 [CATrainingPosCal] consider 1 rank data
3712 11:49:03.193471 u2DelayCellTimex100 = 270/100 ps
3713 11:49:03.196738 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3714 11:49:03.200259 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3715 11:49:03.203762 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3716 11:49:03.206719 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3717 11:49:03.209914 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3718 11:49:03.216345 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3719 11:49:03.216955
3720 11:49:03.219712 CA PerBit enable=1, Macro0, CA PI delay=33
3721 11:49:03.220282
3722 11:49:03.222894 [CBTSetCACLKResult] CA Dly = 33
3723 11:49:03.223365 CS Dly: 4 (0~35)
3724 11:49:03.223737 ==
3725 11:49:03.226472 Dram Type= 6, Freq= 0, CH_0, rank 1
3726 11:49:03.229400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3727 11:49:03.233125 ==
3728 11:49:03.236310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3729 11:49:03.242889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3730 11:49:03.246135 [CA 0] Center 36 (6~66) winsize 61
3731 11:49:03.249341 [CA 1] Center 35 (5~66) winsize 62
3732 11:49:03.253177 [CA 2] Center 34 (4~65) winsize 62
3733 11:49:03.256198 [CA 3] Center 34 (4~65) winsize 62
3734 11:49:03.259522 [CA 4] Center 33 (3~64) winsize 62
3735 11:49:03.262995 [CA 5] Center 33 (2~64) winsize 63
3736 11:49:03.263571
3737 11:49:03.266154 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3738 11:49:03.266724
3739 11:49:03.269490 [CATrainingPosCal] consider 2 rank data
3740 11:49:03.272556 u2DelayCellTimex100 = 270/100 ps
3741 11:49:03.276143 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3742 11:49:03.279183 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3743 11:49:03.282481 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3744 11:49:03.289250 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3745 11:49:03.292732 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3746 11:49:03.295913 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3747 11:49:03.296477
3748 11:49:03.299465 CA PerBit enable=1, Macro0, CA PI delay=33
3749 11:49:03.300026
3750 11:49:03.302846 [CBTSetCACLKResult] CA Dly = 33
3751 11:49:03.303405 CS Dly: 4 (0~35)
3752 11:49:03.303774
3753 11:49:03.305754 ----->DramcWriteLeveling(PI) begin...
3754 11:49:03.306229 ==
3755 11:49:03.309200 Dram Type= 6, Freq= 0, CH_0, rank 0
3756 11:49:03.316098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3757 11:49:03.316777 ==
3758 11:49:03.319134 Write leveling (Byte 0): 30 => 30
3759 11:49:03.322416 Write leveling (Byte 1): 31 => 31
3760 11:49:03.325769 DramcWriteLeveling(PI) end<-----
3761 11:49:03.326231
3762 11:49:03.326593 ==
3763 11:49:03.329052 Dram Type= 6, Freq= 0, CH_0, rank 0
3764 11:49:03.332194 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3765 11:49:03.332692 ==
3766 11:49:03.335650 [Gating] SW mode calibration
3767 11:49:03.342161 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3768 11:49:03.345291 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3769 11:49:03.352425 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3770 11:49:03.355595 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3771 11:49:03.358966 0 5 8 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
3772 11:49:03.365833 0 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3773 11:49:03.369127 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3774 11:49:03.372335 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3775 11:49:03.378869 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3776 11:49:03.382588 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3777 11:49:03.385292 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3778 11:49:03.392354 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3779 11:49:03.395698 0 6 8 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
3780 11:49:03.398946 0 6 12 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
3781 11:49:03.405709 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3782 11:49:03.408930 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3783 11:49:03.412375 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3784 11:49:03.418859 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3785 11:49:03.422131 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3786 11:49:03.425225 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3787 11:49:03.431924 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3788 11:49:03.435237 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3789 11:49:03.438436 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3790 11:49:03.445046 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3791 11:49:03.448550 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3792 11:49:03.451844 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3793 11:49:03.458284 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3794 11:49:03.461684 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3795 11:49:03.465024 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3796 11:49:03.471614 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3797 11:49:03.475203 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3798 11:49:03.478178 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3799 11:49:03.484959 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3800 11:49:03.488038 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3801 11:49:03.491751 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3802 11:49:03.497732 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3803 11:49:03.501372 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3804 11:49:03.504819 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3805 11:49:03.508119 Total UI for P1: 0, mck2ui 16
3806 11:49:03.511440 best dqsien dly found for B0: ( 0, 9, 8)
3807 11:49:03.514712 Total UI for P1: 0, mck2ui 16
3808 11:49:03.517785 best dqsien dly found for B1: ( 0, 9, 10)
3809 11:49:03.521141 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3810 11:49:03.524496 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3811 11:49:03.525098
3812 11:49:03.527772 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3813 11:49:03.534241 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3814 11:49:03.534845 [Gating] SW calibration Done
3815 11:49:03.537409 ==
3816 11:49:03.540822 Dram Type= 6, Freq= 0, CH_0, rank 0
3817 11:49:03.544073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3818 11:49:03.544587 ==
3819 11:49:03.545011 RX Vref Scan: 0
3820 11:49:03.545371
3821 11:49:03.547653 RX Vref 0 -> 0, step: 1
3822 11:49:03.548229
3823 11:49:03.550846 RX Delay -230 -> 252, step: 16
3824 11:49:03.554182 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3825 11:49:03.557303 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3826 11:49:03.563986 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3827 11:49:03.567439 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3828 11:49:03.570610 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3829 11:49:03.574107 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3830 11:49:03.580556 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3831 11:49:03.583859 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3832 11:49:03.587110 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3833 11:49:03.590394 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
3834 11:49:03.593730 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3835 11:49:03.600564 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3836 11:49:03.603987 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3837 11:49:03.607252 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3838 11:49:03.610506 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3839 11:49:03.617073 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3840 11:49:03.617697 ==
3841 11:49:03.619934 Dram Type= 6, Freq= 0, CH_0, rank 0
3842 11:49:03.624170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3843 11:49:03.624797 ==
3844 11:49:03.625293 DQS Delay:
3845 11:49:03.626643 DQS0 = 0, DQS1 = 0
3846 11:49:03.627121 DQM Delay:
3847 11:49:03.630286 DQM0 = 39, DQM1 = 32
3848 11:49:03.630862 DQ Delay:
3849 11:49:03.633202 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3850 11:49:03.636628 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3851 11:49:03.640208 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
3852 11:49:03.643433 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3853 11:49:03.644008
3854 11:49:03.644614
3855 11:49:03.645086 ==
3856 11:49:03.646308 Dram Type= 6, Freq= 0, CH_0, rank 0
3857 11:49:03.649982 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3858 11:49:03.653207 ==
3859 11:49:03.653787
3860 11:49:03.654281
3861 11:49:03.654737 TX Vref Scan disable
3862 11:49:03.656362 == TX Byte 0 ==
3863 11:49:03.659945 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3864 11:49:03.663222 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3865 11:49:03.666435 == TX Byte 1 ==
3866 11:49:03.669954 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3867 11:49:03.673210 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3868 11:49:03.676402 ==
3869 11:49:03.676949 Dram Type= 6, Freq= 0, CH_0, rank 0
3870 11:49:03.683058 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3871 11:49:03.683634 ==
3872 11:49:03.684123
3873 11:49:03.684622
3874 11:49:03.686320 TX Vref Scan disable
3875 11:49:03.686798 == TX Byte 0 ==
3876 11:49:03.693138 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3877 11:49:03.696380 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3878 11:49:03.697005 == TX Byte 1 ==
3879 11:49:03.702866 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3880 11:49:03.706332 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3881 11:49:03.706910
3882 11:49:03.707399 [DATLAT]
3883 11:49:03.709810 Freq=600, CH0 RK0
3884 11:49:03.710404
3885 11:49:03.710895 DATLAT Default: 0x9
3886 11:49:03.712954 0, 0xFFFF, sum = 0
3887 11:49:03.713539 1, 0xFFFF, sum = 0
3888 11:49:03.716237 2, 0xFFFF, sum = 0
3889 11:49:03.716771 3, 0xFFFF, sum = 0
3890 11:49:03.719851 4, 0xFFFF, sum = 0
3891 11:49:03.720432 5, 0xFFFF, sum = 0
3892 11:49:03.722589 6, 0xFFFF, sum = 0
3893 11:49:03.723073 7, 0x0, sum = 1
3894 11:49:03.726380 8, 0x0, sum = 2
3895 11:49:03.726970 9, 0x0, sum = 3
3896 11:49:03.729500 10, 0x0, sum = 4
3897 11:49:03.729987 best_step = 8
3898 11:49:03.730464
3899 11:49:03.730915 ==
3900 11:49:03.732557 Dram Type= 6, Freq= 0, CH_0, rank 0
3901 11:49:03.739177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3902 11:49:03.739646 ==
3903 11:49:03.740020 RX Vref Scan: 1
3904 11:49:03.740367
3905 11:49:03.742570 RX Vref 0 -> 0, step: 1
3906 11:49:03.743057
3907 11:49:03.746178 RX Delay -195 -> 252, step: 8
3908 11:49:03.746646
3909 11:49:03.749115 Set Vref, RX VrefLevel [Byte0]: 49
3910 11:49:03.752591 [Byte1]: 49
3911 11:49:03.753061
3912 11:49:03.755763 Final RX Vref Byte 0 = 49 to rank0
3913 11:49:03.759366 Final RX Vref Byte 1 = 49 to rank0
3914 11:49:03.762509 Final RX Vref Byte 0 = 49 to rank1
3915 11:49:03.766170 Final RX Vref Byte 1 = 49 to rank1==
3916 11:49:03.769112 Dram Type= 6, Freq= 0, CH_0, rank 0
3917 11:49:03.772446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3918 11:49:03.773055 ==
3919 11:49:03.775860 DQS Delay:
3920 11:49:03.776334 DQS0 = 0, DQS1 = 0
3921 11:49:03.776772 DQM Delay:
3922 11:49:03.778986 DQM0 = 40, DQM1 = 30
3923 11:49:03.779454 DQ Delay:
3924 11:49:03.782345 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3925 11:49:03.785663 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =52
3926 11:49:03.789227 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3927 11:49:03.792354 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3928 11:49:03.792859
3929 11:49:03.793233
3930 11:49:03.802261 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
3931 11:49:03.805456 CH0 RK0: MR19=808, MR18=4D4D
3932 11:49:03.811990 CH0_RK0: MR19=0x808, MR18=0x4D4D, DQSOSC=395, MR23=63, INC=168, DEC=112
3933 11:49:03.812609
3934 11:49:03.815572 ----->DramcWriteLeveling(PI) begin...
3935 11:49:03.816150 ==
3936 11:49:03.818493 Dram Type= 6, Freq= 0, CH_0, rank 1
3937 11:49:03.822148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3938 11:49:03.822718 ==
3939 11:49:03.825713 Write leveling (Byte 0): 30 => 30
3940 11:49:03.828407 Write leveling (Byte 1): 30 => 30
3941 11:49:03.832211 DramcWriteLeveling(PI) end<-----
3942 11:49:03.832843
3943 11:49:03.833229 ==
3944 11:49:03.834905 Dram Type= 6, Freq= 0, CH_0, rank 1
3945 11:49:03.838207 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3946 11:49:03.838746 ==
3947 11:49:03.841617 [Gating] SW mode calibration
3948 11:49:03.848459 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3949 11:49:03.855046 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3950 11:49:03.858331 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3951 11:49:03.861344 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3952 11:49:03.868350 0 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
3953 11:49:03.871732 0 5 12 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
3954 11:49:03.874974 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3955 11:49:03.881671 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3956 11:49:03.884894 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3957 11:49:03.887873 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3958 11:49:03.894642 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3959 11:49:03.898087 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3960 11:49:03.901248 0 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
3961 11:49:03.907866 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3962 11:49:03.911188 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3963 11:49:03.914242 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3964 11:49:03.921222 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3965 11:49:03.924467 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3966 11:49:03.927667 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3967 11:49:03.934332 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3968 11:49:03.937198 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3969 11:49:03.940645 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3970 11:49:03.947334 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3971 11:49:03.950724 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3972 11:49:03.954210 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3973 11:49:03.960882 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3974 11:49:03.963901 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3975 11:49:03.967302 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3976 11:49:03.974018 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3977 11:49:03.976897 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3978 11:49:03.980478 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 11:49:03.987146 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 11:49:03.990401 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 11:49:03.993755 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 11:49:04.000557 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 11:49:04.003840 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 11:49:04.006966 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3985 11:49:04.013428 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 11:49:04.014026 Total UI for P1: 0, mck2ui 16
3987 11:49:04.020365 best dqsien dly found for B0: ( 0, 9, 8)
3988 11:49:04.021142 Total UI for P1: 0, mck2ui 16
3989 11:49:04.023548 best dqsien dly found for B1: ( 0, 9, 8)
3990 11:49:04.029878 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3991 11:49:04.033431 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3992 11:49:04.033990
3993 11:49:04.036550 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3994 11:49:04.039875 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3995 11:49:04.043159 [Gating] SW calibration Done
3996 11:49:04.043647 ==
3997 11:49:04.046460 Dram Type= 6, Freq= 0, CH_0, rank 1
3998 11:49:04.050208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3999 11:49:04.050685 ==
4000 11:49:04.053203 RX Vref Scan: 0
4001 11:49:04.053669
4002 11:49:04.054040 RX Vref 0 -> 0, step: 1
4003 11:49:04.054387
4004 11:49:04.056678 RX Delay -230 -> 252, step: 16
4005 11:49:04.060064 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4006 11:49:04.066944 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4007 11:49:04.069902 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4008 11:49:04.073302 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4009 11:49:04.076648 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4010 11:49:04.083248 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4011 11:49:04.086757 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4012 11:49:04.089845 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4013 11:49:04.093101 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4014 11:49:04.096591 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4015 11:49:04.102752 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4016 11:49:04.106483 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4017 11:49:04.110282 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4018 11:49:04.112825 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4019 11:49:04.119545 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4020 11:49:04.122943 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4021 11:49:04.123504 ==
4022 11:49:04.126227 Dram Type= 6, Freq= 0, CH_0, rank 1
4023 11:49:04.129293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4024 11:49:04.129767 ==
4025 11:49:04.133123 DQS Delay:
4026 11:49:04.133686 DQS0 = 0, DQS1 = 0
4027 11:49:04.134062 DQM Delay:
4028 11:49:04.135917 DQM0 = 41, DQM1 = 33
4029 11:49:04.136387 DQ Delay:
4030 11:49:04.139284 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4031 11:49:04.142813 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4032 11:49:04.145880 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4033 11:49:04.149260 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4034 11:49:04.149731
4035 11:49:04.150104
4036 11:49:04.150449 ==
4037 11:49:04.152496 Dram Type= 6, Freq= 0, CH_0, rank 1
4038 11:49:04.159694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4039 11:49:04.160259 ==
4040 11:49:04.160703
4041 11:49:04.161060
4042 11:49:04.161389 TX Vref Scan disable
4043 11:49:04.162899 == TX Byte 0 ==
4044 11:49:04.166427 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4045 11:49:04.173209 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4046 11:49:04.173773 == TX Byte 1 ==
4047 11:49:04.176476 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4048 11:49:04.183434 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4049 11:49:04.183996 ==
4050 11:49:04.186535 Dram Type= 6, Freq= 0, CH_0, rank 1
4051 11:49:04.189827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4052 11:49:04.190388 ==
4053 11:49:04.190764
4054 11:49:04.191111
4055 11:49:04.192736 TX Vref Scan disable
4056 11:49:04.193207 == TX Byte 0 ==
4057 11:49:04.199727 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4058 11:49:04.203051 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4059 11:49:04.205899 == TX Byte 1 ==
4060 11:49:04.209426 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4061 11:49:04.212994 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4062 11:49:04.213557
4063 11:49:04.213932 [DATLAT]
4064 11:49:04.216165 Freq=600, CH0 RK1
4065 11:49:04.216789
4066 11:49:04.217178 DATLAT Default: 0x8
4067 11:49:04.219579 0, 0xFFFF, sum = 0
4068 11:49:04.222710 1, 0xFFFF, sum = 0
4069 11:49:04.223283 2, 0xFFFF, sum = 0
4070 11:49:04.226197 3, 0xFFFF, sum = 0
4071 11:49:04.226672 4, 0xFFFF, sum = 0
4072 11:49:04.229554 5, 0xFFFF, sum = 0
4073 11:49:04.230029 6, 0xFFFF, sum = 0
4074 11:49:04.232848 7, 0x0, sum = 1
4075 11:49:04.233417 8, 0x0, sum = 2
4076 11:49:04.233837 9, 0x0, sum = 3
4077 11:49:04.236013 10, 0x0, sum = 4
4078 11:49:04.236488 best_step = 8
4079 11:49:04.236905
4080 11:49:04.237253 ==
4081 11:49:04.239165 Dram Type= 6, Freq= 0, CH_0, rank 1
4082 11:49:04.245898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4083 11:49:04.246369 ==
4084 11:49:04.246744 RX Vref Scan: 0
4085 11:49:04.247093
4086 11:49:04.249283 RX Vref 0 -> 0, step: 1
4087 11:49:04.249754
4088 11:49:04.252476 RX Delay -195 -> 252, step: 8
4089 11:49:04.255643 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4090 11:49:04.262765 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4091 11:49:04.265850 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4092 11:49:04.269126 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4093 11:49:04.272479 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4094 11:49:04.279215 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4095 11:49:04.282582 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4096 11:49:04.285680 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4097 11:49:04.289024 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4098 11:49:04.292428 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4099 11:49:04.299010 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4100 11:49:04.302335 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4101 11:49:04.305524 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4102 11:49:04.309090 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4103 11:49:04.315559 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4104 11:49:04.318626 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4105 11:49:04.319111 ==
4106 11:49:04.322101 Dram Type= 6, Freq= 0, CH_0, rank 1
4107 11:49:04.325572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4108 11:49:04.326131 ==
4109 11:49:04.328744 DQS Delay:
4110 11:49:04.329305 DQS0 = 0, DQS1 = 0
4111 11:49:04.331984 DQM Delay:
4112 11:49:04.332556 DQM0 = 42, DQM1 = 32
4113 11:49:04.332945 DQ Delay:
4114 11:49:04.335124 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4115 11:49:04.338463 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =52
4116 11:49:04.342438 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4117 11:49:04.345130 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4118 11:49:04.345602
4119 11:49:04.345974
4120 11:49:04.355234 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e6e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4121 11:49:04.358252 CH0 RK1: MR19=808, MR18=6E6E
4122 11:49:04.365129 CH0_RK1: MR19=0x808, MR18=0x6E6E, DQSOSC=389, MR23=63, INC=173, DEC=115
4123 11:49:04.365700 [RxdqsGatingPostProcess] freq 600
4124 11:49:04.371615 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4125 11:49:04.375191 Pre-setting of DQS Precalculation
4126 11:49:04.378169 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4127 11:49:04.381632 ==
4128 11:49:04.382104 Dram Type= 6, Freq= 0, CH_1, rank 0
4129 11:49:04.388350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4130 11:49:04.389015 ==
4131 11:49:04.391939 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4132 11:49:04.398148 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4133 11:49:04.401890 [CA 0] Center 35 (5~66) winsize 62
4134 11:49:04.405261 [CA 1] Center 35 (5~65) winsize 61
4135 11:49:04.408589 [CA 2] Center 33 (3~64) winsize 62
4136 11:49:04.411760 [CA 3] Center 33 (3~64) winsize 62
4137 11:49:04.414748 [CA 4] Center 33 (2~64) winsize 63
4138 11:49:04.418182 [CA 5] Center 33 (2~64) winsize 63
4139 11:49:04.418767
4140 11:49:04.421740 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4141 11:49:04.422300
4142 11:49:04.424926 [CATrainingPosCal] consider 1 rank data
4143 11:49:04.428124 u2DelayCellTimex100 = 270/100 ps
4144 11:49:04.431683 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4145 11:49:04.438158 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4146 11:49:04.441713 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4147 11:49:04.444834 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4148 11:49:04.448149 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4149 11:49:04.451948 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4150 11:49:04.452555
4151 11:49:04.455216 CA PerBit enable=1, Macro0, CA PI delay=33
4152 11:49:04.455829
4153 11:49:04.457938 [CBTSetCACLKResult] CA Dly = 33
4154 11:49:04.458412 CS Dly: 4 (0~35)
4155 11:49:04.461357 ==
4156 11:49:04.464847 Dram Type= 6, Freq= 0, CH_1, rank 1
4157 11:49:04.468444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4158 11:49:04.469077 ==
4159 11:49:04.471567 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4160 11:49:04.477771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4161 11:49:04.481863 [CA 0] Center 35 (5~66) winsize 62
4162 11:49:04.485219 [CA 1] Center 34 (4~65) winsize 62
4163 11:49:04.488794 [CA 2] Center 33 (3~64) winsize 62
4164 11:49:04.491901 [CA 3] Center 33 (3~64) winsize 62
4165 11:49:04.495035 [CA 4] Center 32 (2~63) winsize 62
4166 11:49:04.498427 [CA 5] Center 32 (2~63) winsize 62
4167 11:49:04.498988
4168 11:49:04.501600 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4169 11:49:04.502072
4170 11:49:04.505164 [CATrainingPosCal] consider 2 rank data
4171 11:49:04.508333 u2DelayCellTimex100 = 270/100 ps
4172 11:49:04.511508 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4173 11:49:04.518242 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4174 11:49:04.521832 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4175 11:49:04.524647 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4176 11:49:04.528423 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4177 11:49:04.531638 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4178 11:49:04.532205
4179 11:49:04.534549 CA PerBit enable=1, Macro0, CA PI delay=32
4180 11:49:04.535021
4181 11:49:04.538226 [CBTSetCACLKResult] CA Dly = 32
4182 11:49:04.541161 CS Dly: 4 (0~35)
4183 11:49:04.541632
4184 11:49:04.544743 ----->DramcWriteLeveling(PI) begin...
4185 11:49:04.545220 ==
4186 11:49:04.548100 Dram Type= 6, Freq= 0, CH_1, rank 0
4187 11:49:04.551191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4188 11:49:04.551666 ==
4189 11:49:04.554730 Write leveling (Byte 0): 28 => 28
4190 11:49:04.557958 Write leveling (Byte 1): 27 => 27
4191 11:49:04.561271 DramcWriteLeveling(PI) end<-----
4192 11:49:04.561837
4193 11:49:04.562295 ==
4194 11:49:04.564893 Dram Type= 6, Freq= 0, CH_1, rank 0
4195 11:49:04.568014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4196 11:49:04.568490 ==
4197 11:49:04.571401 [Gating] SW mode calibration
4198 11:49:04.577942 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4199 11:49:04.584479 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4200 11:49:04.587835 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4201 11:49:04.591108 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4202 11:49:04.597934 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (1 0)
4203 11:49:04.601104 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 11:49:04.604748 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 11:49:04.611123 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 11:49:04.614271 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 11:49:04.618143 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 11:49:04.624304 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 11:49:04.627517 0 6 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4210 11:49:04.631048 0 6 8 | B1->B0 | 3636 4040 | 0 0 | (0 0) (0 0)
4211 11:49:04.637309 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 11:49:04.640780 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 11:49:04.643931 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 11:49:04.650312 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 11:49:04.653837 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 11:49:04.657326 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 11:49:04.663850 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4218 11:49:04.667288 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4219 11:49:04.670327 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 11:49:04.673958 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 11:49:04.680604 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 11:49:04.683836 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 11:49:04.687429 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 11:49:04.693874 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 11:49:04.696853 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 11:49:04.700330 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 11:49:04.707066 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 11:49:04.710428 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 11:49:04.716702 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 11:49:04.719739 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 11:49:04.723351 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 11:49:04.726859 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 11:49:04.733431 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4234 11:49:04.736496 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4235 11:49:04.739909 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 11:49:04.743207 Total UI for P1: 0, mck2ui 16
4237 11:49:04.746475 best dqsien dly found for B0: ( 0, 9, 6)
4238 11:49:04.749777 Total UI for P1: 0, mck2ui 16
4239 11:49:04.753236 best dqsien dly found for B1: ( 0, 9, 10)
4240 11:49:04.756454 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4241 11:49:04.759807 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4242 11:49:04.760371
4243 11:49:04.766370 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4244 11:49:04.769678 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4245 11:49:04.773211 [Gating] SW calibration Done
4246 11:49:04.773825 ==
4247 11:49:04.776383 Dram Type= 6, Freq= 0, CH_1, rank 0
4248 11:49:04.779915 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4249 11:49:04.780479 ==
4250 11:49:04.780920 RX Vref Scan: 0
4251 11:49:04.781274
4252 11:49:04.783566 RX Vref 0 -> 0, step: 1
4253 11:49:04.784127
4254 11:49:04.786302 RX Delay -230 -> 252, step: 16
4255 11:49:04.789698 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4256 11:49:04.793157 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4257 11:49:04.799787 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4258 11:49:04.803124 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4259 11:49:04.806335 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4260 11:49:04.809624 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4261 11:49:04.816459 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4262 11:49:04.819518 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4263 11:49:04.823263 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4264 11:49:04.826556 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4265 11:49:04.833219 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4266 11:49:04.836257 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4267 11:49:04.839406 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4268 11:49:04.842928 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4269 11:49:04.846095 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4270 11:49:04.852751 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4271 11:49:04.853222 ==
4272 11:49:04.855961 Dram Type= 6, Freq= 0, CH_1, rank 0
4273 11:49:04.859331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4274 11:49:04.859804 ==
4275 11:49:04.860174 DQS Delay:
4276 11:49:04.862749 DQS0 = 0, DQS1 = 0
4277 11:49:04.863286 DQM Delay:
4278 11:49:04.866106 DQM0 = 37, DQM1 = 33
4279 11:49:04.866681 DQ Delay:
4280 11:49:04.869435 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4281 11:49:04.872963 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4282 11:49:04.876026 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4283 11:49:04.879331 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =41
4284 11:49:04.879803
4285 11:49:04.880261
4286 11:49:04.880665 ==
4287 11:49:04.882728 Dram Type= 6, Freq= 0, CH_1, rank 0
4288 11:49:04.885852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4289 11:49:04.889497 ==
4290 11:49:04.890082
4291 11:49:04.890458
4292 11:49:04.890801 TX Vref Scan disable
4293 11:49:04.892450 == TX Byte 0 ==
4294 11:49:04.895819 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4295 11:49:04.899051 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4296 11:49:04.902649 == TX Byte 1 ==
4297 11:49:04.905793 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4298 11:49:04.909016 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4299 11:49:04.912460 ==
4300 11:49:04.915722 Dram Type= 6, Freq= 0, CH_1, rank 0
4301 11:49:04.919117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4302 11:49:04.919677 ==
4303 11:49:04.920052
4304 11:49:04.920413
4305 11:49:04.922255 TX Vref Scan disable
4306 11:49:04.925504 == TX Byte 0 ==
4307 11:49:04.928757 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4308 11:49:04.932323 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4309 11:49:04.935501 == TX Byte 1 ==
4310 11:49:04.938509 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4311 11:49:04.942127 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4312 11:49:04.942592
4313 11:49:04.942957 [DATLAT]
4314 11:49:04.945245 Freq=600, CH1 RK0
4315 11:49:04.945712
4316 11:49:04.946082 DATLAT Default: 0x9
4317 11:49:04.948574 0, 0xFFFF, sum = 0
4318 11:49:04.952042 1, 0xFFFF, sum = 0
4319 11:49:04.952555 2, 0xFFFF, sum = 0
4320 11:49:04.955461 3, 0xFFFF, sum = 0
4321 11:49:04.956021 4, 0xFFFF, sum = 0
4322 11:49:04.958580 5, 0xFFFF, sum = 0
4323 11:49:04.959050 6, 0xFFFF, sum = 0
4324 11:49:04.961777 7, 0x0, sum = 1
4325 11:49:04.962250 8, 0x0, sum = 2
4326 11:49:04.962625 9, 0x0, sum = 3
4327 11:49:04.965290 10, 0x0, sum = 4
4328 11:49:04.965763 best_step = 8
4329 11:49:04.966134
4330 11:49:04.966475 ==
4331 11:49:04.969026 Dram Type= 6, Freq= 0, CH_1, rank 0
4332 11:49:04.975234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4333 11:49:04.975788 ==
4334 11:49:04.976162 RX Vref Scan: 1
4335 11:49:04.976503
4336 11:49:04.978714 RX Vref 0 -> 0, step: 1
4337 11:49:04.979204
4338 11:49:04.981748 RX Delay -195 -> 252, step: 8
4339 11:49:04.982213
4340 11:49:04.985270 Set Vref, RX VrefLevel [Byte0]: 54
4341 11:49:04.988641 [Byte1]: 50
4342 11:49:04.989192
4343 11:49:04.991558 Final RX Vref Byte 0 = 54 to rank0
4344 11:49:04.995147 Final RX Vref Byte 1 = 50 to rank0
4345 11:49:04.998489 Final RX Vref Byte 0 = 54 to rank1
4346 11:49:05.001404 Final RX Vref Byte 1 = 50 to rank1==
4347 11:49:05.005102 Dram Type= 6, Freq= 0, CH_1, rank 0
4348 11:49:05.008397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4349 11:49:05.009015 ==
4350 11:49:05.011655 DQS Delay:
4351 11:49:05.012208 DQS0 = 0, DQS1 = 0
4352 11:49:05.015030 DQM Delay:
4353 11:49:05.015591 DQM0 = 37, DQM1 = 29
4354 11:49:05.015961 DQ Delay:
4355 11:49:05.018073 DQ0 =44, DQ1 =28, DQ2 =28, DQ3 =36
4356 11:49:05.021789 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4357 11:49:05.024905 DQ8 =12, DQ9 =16, DQ10 =36, DQ11 =20
4358 11:49:05.028628 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4359 11:49:05.029188
4360 11:49:05.031567
4361 11:49:05.038000 [DQSOSCAuto] RK0, (LSB)MR18= 0x7474, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4362 11:49:05.041395 CH1 RK0: MR19=808, MR18=7474
4363 11:49:05.047740 CH1_RK0: MR19=0x808, MR18=0x7474, DQSOSC=388, MR23=63, INC=174, DEC=116
4364 11:49:05.048275
4365 11:49:05.051432 ----->DramcWriteLeveling(PI) begin...
4366 11:49:05.051998 ==
4367 11:49:05.054430 Dram Type= 6, Freq= 0, CH_1, rank 1
4368 11:49:05.057694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4369 11:49:05.058164 ==
4370 11:49:05.061473 Write leveling (Byte 0): 30 => 30
4371 11:49:05.064597 Write leveling (Byte 1): 30 => 30
4372 11:49:05.067788 DramcWriteLeveling(PI) end<-----
4373 11:49:05.068346
4374 11:49:05.068784 ==
4375 11:49:05.071130 Dram Type= 6, Freq= 0, CH_1, rank 1
4376 11:49:05.074439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4377 11:49:05.075014 ==
4378 11:49:05.077771 [Gating] SW mode calibration
4379 11:49:05.084546 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4380 11:49:05.091058 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4381 11:49:05.094615 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4382 11:49:05.097884 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4383 11:49:05.104580 0 5 8 | B1->B0 | 3030 2727 | 0 1 | (0 0) (1 0)
4384 11:49:05.107728 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4385 11:49:05.111056 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4386 11:49:05.117750 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4387 11:49:05.120856 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4388 11:49:05.124306 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4389 11:49:05.130712 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4390 11:49:05.134113 0 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
4391 11:49:05.137482 0 6 8 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
4392 11:49:05.144017 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4393 11:49:05.147184 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4394 11:49:05.150732 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4395 11:49:05.157180 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4396 11:49:05.160222 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4397 11:49:05.163656 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4398 11:49:05.170121 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4399 11:49:05.173489 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4400 11:49:05.176940 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4401 11:49:05.183745 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4402 11:49:05.186921 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4403 11:49:05.190419 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4404 11:49:05.196914 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4405 11:49:05.200213 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4406 11:49:05.203545 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4407 11:49:05.210162 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4408 11:49:05.213730 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4409 11:49:05.216788 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4410 11:49:05.223442 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4411 11:49:05.226717 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 11:49:05.229784 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 11:49:05.236973 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 11:49:05.239753 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4415 11:49:05.243144 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4416 11:49:05.249549 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 11:49:05.250052 Total UI for P1: 0, mck2ui 16
4418 11:49:05.256334 best dqsien dly found for B0: ( 0, 9, 6)
4419 11:49:05.256846 Total UI for P1: 0, mck2ui 16
4420 11:49:05.259792 best dqsien dly found for B1: ( 0, 9, 8)
4421 11:49:05.266187 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4422 11:49:05.269682 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4423 11:49:05.270152
4424 11:49:05.272955 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4425 11:49:05.276194 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4426 11:49:05.279586 [Gating] SW calibration Done
4427 11:49:05.280059 ==
4428 11:49:05.282774 Dram Type= 6, Freq= 0, CH_1, rank 1
4429 11:49:05.286179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4430 11:49:05.286426 ==
4431 11:49:05.286620 RX Vref Scan: 0
4432 11:49:05.289412
4433 11:49:05.289655 RX Vref 0 -> 0, step: 1
4434 11:49:05.289851
4435 11:49:05.292664 RX Delay -230 -> 252, step: 16
4436 11:49:05.296153 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4437 11:49:05.302669 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4438 11:49:05.306185 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4439 11:49:05.309486 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4440 11:49:05.312791 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4441 11:49:05.316267 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4442 11:49:05.322754 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4443 11:49:05.326053 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4444 11:49:05.329708 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4445 11:49:05.332995 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4446 11:49:05.339499 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4447 11:49:05.343006 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4448 11:49:05.346175 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4449 11:49:05.349396 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4450 11:49:05.356049 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4451 11:49:05.359637 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4452 11:49:05.360192 ==
4453 11:49:05.362921 Dram Type= 6, Freq= 0, CH_1, rank 1
4454 11:49:05.366511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4455 11:49:05.367103 ==
4456 11:49:05.369721 DQS Delay:
4457 11:49:05.370283 DQS0 = 0, DQS1 = 0
4458 11:49:05.370652 DQM Delay:
4459 11:49:05.372757 DQM0 = 39, DQM1 = 34
4460 11:49:05.373360 DQ Delay:
4461 11:49:05.376121 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4462 11:49:05.379181 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4463 11:49:05.382746 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4464 11:49:05.385726 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4465 11:49:05.386191
4466 11:49:05.386558
4467 11:49:05.386899 ==
4468 11:49:05.389498 Dram Type= 6, Freq= 0, CH_1, rank 1
4469 11:49:05.396040 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4470 11:49:05.396649 ==
4471 11:49:05.397026
4472 11:49:05.397369
4473 11:49:05.397692 TX Vref Scan disable
4474 11:49:05.399615 == TX Byte 0 ==
4475 11:49:05.402856 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4476 11:49:05.409481 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4477 11:49:05.410176 == TX Byte 1 ==
4478 11:49:05.412695 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4479 11:49:05.418963 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4480 11:49:05.419513 ==
4481 11:49:05.422636 Dram Type= 6, Freq= 0, CH_1, rank 1
4482 11:49:05.425850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4483 11:49:05.426414 ==
4484 11:49:05.426788
4485 11:49:05.427127
4486 11:49:05.429150 TX Vref Scan disable
4487 11:49:05.429618 == TX Byte 0 ==
4488 11:49:05.436043 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4489 11:49:05.439146 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4490 11:49:05.439709 == TX Byte 1 ==
4491 11:49:05.445813 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4492 11:49:05.449289 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4493 11:49:05.449776
4494 11:49:05.450164 [DATLAT]
4495 11:49:05.452834 Freq=600, CH1 RK1
4496 11:49:05.453296
4497 11:49:05.453663 DATLAT Default: 0x8
4498 11:49:05.455594 0, 0xFFFF, sum = 0
4499 11:49:05.456066 1, 0xFFFF, sum = 0
4500 11:49:05.459399 2, 0xFFFF, sum = 0
4501 11:49:05.459966 3, 0xFFFF, sum = 0
4502 11:49:05.462610 4, 0xFFFF, sum = 0
4503 11:49:05.466105 5, 0xFFFF, sum = 0
4504 11:49:05.466670 6, 0xFFFF, sum = 0
4505 11:49:05.467045 7, 0x0, sum = 1
4506 11:49:05.469074 8, 0x0, sum = 2
4507 11:49:05.469549 9, 0x0, sum = 3
4508 11:49:05.472734 10, 0x0, sum = 4
4509 11:49:05.473334 best_step = 8
4510 11:49:05.473713
4511 11:49:05.474052 ==
4512 11:49:05.475648 Dram Type= 6, Freq= 0, CH_1, rank 1
4513 11:49:05.482595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4514 11:49:05.483160 ==
4515 11:49:05.483527 RX Vref Scan: 0
4516 11:49:05.483867
4517 11:49:05.485769 RX Vref 0 -> 0, step: 1
4518 11:49:05.486230
4519 11:49:05.489381 RX Delay -195 -> 252, step: 8
4520 11:49:05.492451 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4521 11:49:05.499475 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4522 11:49:05.502623 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4523 11:49:05.506078 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4524 11:49:05.508907 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4525 11:49:05.512608 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4526 11:49:05.519178 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4527 11:49:05.522199 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4528 11:49:05.525562 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4529 11:49:05.529104 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4530 11:49:05.535403 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4531 11:49:05.538882 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4532 11:49:05.542026 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4533 11:49:05.545274 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4534 11:49:05.552082 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4535 11:49:05.555323 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4536 11:49:05.555888 ==
4537 11:49:05.558641 Dram Type= 6, Freq= 0, CH_1, rank 1
4538 11:49:05.561994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4539 11:49:05.562564 ==
4540 11:49:05.565187 DQS Delay:
4541 11:49:05.565662 DQS0 = 0, DQS1 = 0
4542 11:49:05.566032 DQM Delay:
4543 11:49:05.568601 DQM0 = 36, DQM1 = 29
4544 11:49:05.569074 DQ Delay:
4545 11:49:05.571935 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4546 11:49:05.575259 DQ4 =40, DQ5 =44, DQ6 =44, DQ7 =32
4547 11:49:05.578988 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4548 11:49:05.582374 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4549 11:49:05.582937
4550 11:49:05.583310
4551 11:49:05.592311 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4552 11:49:05.592926 CH1 RK1: MR19=808, MR18=6161
4553 11:49:05.598625 CH1_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4554 11:49:05.602236 [RxdqsGatingPostProcess] freq 600
4555 11:49:05.608501 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4556 11:49:05.612185 Pre-setting of DQS Precalculation
4557 11:49:05.615027 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4558 11:49:05.621792 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4559 11:49:05.632120 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4560 11:49:05.632628
4561 11:49:05.633005
4562 11:49:05.635096 [Calibration Summary] 1200 Mbps
4563 11:49:05.635566 CH 0, Rank 0
4564 11:49:05.638113 SW Impedance : PASS
4565 11:49:05.638583 DUTY Scan : NO K
4566 11:49:05.641761 ZQ Calibration : PASS
4567 11:49:05.645472 Jitter Meter : NO K
4568 11:49:05.646033 CBT Training : PASS
4569 11:49:05.648388 Write leveling : PASS
4570 11:49:05.648907 RX DQS gating : PASS
4571 11:49:05.651837 RX DQ/DQS(RDDQC) : PASS
4572 11:49:05.655163 TX DQ/DQS : PASS
4573 11:49:05.655729 RX DATLAT : PASS
4574 11:49:05.658542 RX DQ/DQS(Engine): PASS
4575 11:49:05.661685 TX OE : NO K
4576 11:49:05.662248 All Pass.
4577 11:49:05.662631
4578 11:49:05.662979 CH 0, Rank 1
4579 11:49:05.664688 SW Impedance : PASS
4580 11:49:05.668107 DUTY Scan : NO K
4581 11:49:05.668618 ZQ Calibration : PASS
4582 11:49:05.671561 Jitter Meter : NO K
4583 11:49:05.674763 CBT Training : PASS
4584 11:49:05.675236 Write leveling : PASS
4585 11:49:05.678283 RX DQS gating : PASS
4586 11:49:05.681523 RX DQ/DQS(RDDQC) : PASS
4587 11:49:05.682023 TX DQ/DQS : PASS
4588 11:49:05.684971 RX DATLAT : PASS
4589 11:49:05.688406 RX DQ/DQS(Engine): PASS
4590 11:49:05.689008 TX OE : NO K
4591 11:49:05.691573 All Pass.
4592 11:49:05.692137
4593 11:49:05.692545 CH 1, Rank 0
4594 11:49:05.694531 SW Impedance : PASS
4595 11:49:05.694996 DUTY Scan : NO K
4596 11:49:05.698360 ZQ Calibration : PASS
4597 11:49:05.701119 Jitter Meter : NO K
4598 11:49:05.701591 CBT Training : PASS
4599 11:49:05.704901 Write leveling : PASS
4600 11:49:05.705469 RX DQS gating : PASS
4601 11:49:05.708133 RX DQ/DQS(RDDQC) : PASS
4602 11:49:05.711316 TX DQ/DQS : PASS
4603 11:49:05.711877 RX DATLAT : PASS
4604 11:49:05.714790 RX DQ/DQS(Engine): PASS
4605 11:49:05.718088 TX OE : NO K
4606 11:49:05.718652 All Pass.
4607 11:49:05.719033
4608 11:49:05.719376 CH 1, Rank 1
4609 11:49:05.721184 SW Impedance : PASS
4610 11:49:05.724625 DUTY Scan : NO K
4611 11:49:05.725201 ZQ Calibration : PASS
4612 11:49:05.727907 Jitter Meter : NO K
4613 11:49:05.731428 CBT Training : PASS
4614 11:49:05.731989 Write leveling : PASS
4615 11:49:05.734635 RX DQS gating : PASS
4616 11:49:05.737452 RX DQ/DQS(RDDQC) : PASS
4617 11:49:05.737986 TX DQ/DQS : PASS
4618 11:49:05.740914 RX DATLAT : PASS
4619 11:49:05.744464 RX DQ/DQS(Engine): PASS
4620 11:49:05.745083 TX OE : NO K
4621 11:49:05.747566 All Pass.
4622 11:49:05.748291
4623 11:49:05.748836 DramC Write-DBI off
4624 11:49:05.750801 PER_BANK_REFRESH: Hybrid Mode
4625 11:49:05.751271 TX_TRACKING: ON
4626 11:49:05.760995 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4627 11:49:05.764417 [FAST_K] Save calibration result to emmc
4628 11:49:05.767580 dramc_set_vcore_voltage set vcore to 662500
4629 11:49:05.770948 Read voltage for 933, 3
4630 11:49:05.771513 Vio18 = 0
4631 11:49:05.774528 Vcore = 662500
4632 11:49:05.775088 Vdram = 0
4633 11:49:05.775463 Vddq = 0
4634 11:49:05.775811 Vmddr = 0
4635 11:49:05.780913 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4636 11:49:05.787256 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4637 11:49:05.787808 MEM_TYPE=3, freq_sel=17
4638 11:49:05.791049 sv_algorithm_assistance_LP4_1600
4639 11:49:05.794114 ============ PULL DRAM RESETB DOWN ============
4640 11:49:05.801121 ========== PULL DRAM RESETB DOWN end =========
4641 11:49:05.804026 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4642 11:49:05.807137 ===================================
4643 11:49:05.810524 LPDDR4 DRAM CONFIGURATION
4644 11:49:05.813951 ===================================
4645 11:49:05.814519 EX_ROW_EN[0] = 0x0
4646 11:49:05.817198 EX_ROW_EN[1] = 0x0
4647 11:49:05.820626 LP4Y_EN = 0x0
4648 11:49:05.821185 WORK_FSP = 0x0
4649 11:49:05.823489 WL = 0x3
4650 11:49:05.823957 RL = 0x3
4651 11:49:05.827165 BL = 0x2
4652 11:49:05.827730 RPST = 0x0
4653 11:49:05.830471 RD_PRE = 0x0
4654 11:49:05.831039 WR_PRE = 0x1
4655 11:49:05.833492 WR_PST = 0x0
4656 11:49:05.833964 DBI_WR = 0x0
4657 11:49:05.837037 DBI_RD = 0x0
4658 11:49:05.837602 OTF = 0x1
4659 11:49:05.840381 ===================================
4660 11:49:05.843627 ===================================
4661 11:49:05.846948 ANA top config
4662 11:49:05.849922 ===================================
4663 11:49:05.850534 DLL_ASYNC_EN = 0
4664 11:49:05.853329 ALL_SLAVE_EN = 1
4665 11:49:05.856826 NEW_RANK_MODE = 1
4666 11:49:05.860030 DLL_IDLE_MODE = 1
4667 11:49:05.863428 LP45_APHY_COMB_EN = 1
4668 11:49:05.863900 TX_ODT_DIS = 1
4669 11:49:05.866746 NEW_8X_MODE = 1
4670 11:49:05.870414 ===================================
4671 11:49:05.873680 ===================================
4672 11:49:05.877131 data_rate = 1866
4673 11:49:05.880292 CKR = 1
4674 11:49:05.883470 DQ_P2S_RATIO = 8
4675 11:49:05.886864 ===================================
4676 11:49:05.887514 CA_P2S_RATIO = 8
4677 11:49:05.890348 DQ_CA_OPEN = 0
4678 11:49:05.893377 DQ_SEMI_OPEN = 0
4679 11:49:05.896547 CA_SEMI_OPEN = 0
4680 11:49:05.900183 CA_FULL_RATE = 0
4681 11:49:05.903505 DQ_CKDIV4_EN = 1
4682 11:49:05.904066 CA_CKDIV4_EN = 1
4683 11:49:05.906793 CA_PREDIV_EN = 0
4684 11:49:05.910154 PH8_DLY = 0
4685 11:49:05.913475 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4686 11:49:05.917065 DQ_AAMCK_DIV = 4
4687 11:49:05.919831 CA_AAMCK_DIV = 4
4688 11:49:05.920303 CA_ADMCK_DIV = 4
4689 11:49:05.923071 DQ_TRACK_CA_EN = 0
4690 11:49:05.926708 CA_PICK = 933
4691 11:49:05.930399 CA_MCKIO = 933
4692 11:49:05.933179 MCKIO_SEMI = 0
4693 11:49:05.936632 PLL_FREQ = 3732
4694 11:49:05.939894 DQ_UI_PI_RATIO = 32
4695 11:49:05.940367 CA_UI_PI_RATIO = 0
4696 11:49:05.943107 ===================================
4697 11:49:05.946355 ===================================
4698 11:49:05.949895 memory_type:LPDDR4
4699 11:49:05.953132 GP_NUM : 10
4700 11:49:05.953696 SRAM_EN : 1
4701 11:49:05.956228 MD32_EN : 0
4702 11:49:05.959667 ===================================
4703 11:49:05.963149 [ANA_INIT] >>>>>>>>>>>>>>
4704 11:49:05.966314 <<<<<< [CONFIGURE PHASE]: ANA_TX
4705 11:49:05.969967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4706 11:49:05.973367 ===================================
4707 11:49:05.973934 data_rate = 1866,PCW = 0X8f00
4708 11:49:05.976223 ===================================
4709 11:49:05.979968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4710 11:49:05.986443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4711 11:49:05.993196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4712 11:49:05.996283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4713 11:49:05.999559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4714 11:49:06.003047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4715 11:49:06.006230 [ANA_INIT] flow start
4716 11:49:06.009534 [ANA_INIT] PLL >>>>>>>>
4717 11:49:06.010095 [ANA_INIT] PLL <<<<<<<<
4718 11:49:06.012806 [ANA_INIT] MIDPI >>>>>>>>
4719 11:49:06.016442 [ANA_INIT] MIDPI <<<<<<<<
4720 11:49:06.017035 [ANA_INIT] DLL >>>>>>>>
4721 11:49:06.019652 [ANA_INIT] flow end
4722 11:49:06.022835 ============ LP4 DIFF to SE enter ============
4723 11:49:06.026296 ============ LP4 DIFF to SE exit ============
4724 11:49:06.029420 [ANA_INIT] <<<<<<<<<<<<<
4725 11:49:06.032731 [Flow] Enable top DCM control >>>>>
4726 11:49:06.036200 [Flow] Enable top DCM control <<<<<
4727 11:49:06.039377 Enable DLL master slave shuffle
4728 11:49:06.045926 ==============================================================
4729 11:49:06.046493 Gating Mode config
4730 11:49:06.052653 ==============================================================
4731 11:49:06.053179 Config description:
4732 11:49:06.062483 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4733 11:49:06.068902 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4734 11:49:06.075835 SELPH_MODE 0: By rank 1: By Phase
4735 11:49:06.078847 ==============================================================
4736 11:49:06.082325 GAT_TRACK_EN = 1
4737 11:49:06.085557 RX_GATING_MODE = 2
4738 11:49:06.089069 RX_GATING_TRACK_MODE = 2
4739 11:49:06.092242 SELPH_MODE = 1
4740 11:49:06.095725 PICG_EARLY_EN = 1
4741 11:49:06.098670 VALID_LAT_VALUE = 1
4742 11:49:06.105691 ==============================================================
4743 11:49:06.108965 Enter into Gating configuration >>>>
4744 11:49:06.112294 Exit from Gating configuration <<<<
4745 11:49:06.115573 Enter into DVFS_PRE_config >>>>>
4746 11:49:06.125812 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4747 11:49:06.128992 Exit from DVFS_PRE_config <<<<<
4748 11:49:06.132287 Enter into PICG configuration >>>>
4749 11:49:06.135405 Exit from PICG configuration <<<<
4750 11:49:06.138343 [RX_INPUT] configuration >>>>>
4751 11:49:06.138956 [RX_INPUT] configuration <<<<<
4752 11:49:06.145228 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4753 11:49:06.151721 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4754 11:49:06.154968 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4755 11:49:06.161687 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4756 11:49:06.168431 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4757 11:49:06.175122 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4758 11:49:06.178718 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4759 11:49:06.181413 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4760 11:49:06.188336 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4761 11:49:06.191616 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4762 11:49:06.195128 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4763 11:49:06.201359 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4764 11:49:06.205074 ===================================
4765 11:49:06.205636 LPDDR4 DRAM CONFIGURATION
4766 11:49:06.208199 ===================================
4767 11:49:06.211522 EX_ROW_EN[0] = 0x0
4768 11:49:06.214800 EX_ROW_EN[1] = 0x0
4769 11:49:06.215361 LP4Y_EN = 0x0
4770 11:49:06.218219 WORK_FSP = 0x0
4771 11:49:06.218794 WL = 0x3
4772 11:49:06.221676 RL = 0x3
4773 11:49:06.222232 BL = 0x2
4774 11:49:06.224638 RPST = 0x0
4775 11:49:06.225109 RD_PRE = 0x0
4776 11:49:06.228065 WR_PRE = 0x1
4777 11:49:06.228676 WR_PST = 0x0
4778 11:49:06.231326 DBI_WR = 0x0
4779 11:49:06.231889 DBI_RD = 0x0
4780 11:49:06.234620 OTF = 0x1
4781 11:49:06.237974 ===================================
4782 11:49:06.241581 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4783 11:49:06.244727 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4784 11:49:06.251066 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4785 11:49:06.254392 ===================================
4786 11:49:06.254867 LPDDR4 DRAM CONFIGURATION
4787 11:49:06.257943 ===================================
4788 11:49:06.261409 EX_ROW_EN[0] = 0x10
4789 11:49:06.261967 EX_ROW_EN[1] = 0x0
4790 11:49:06.264640 LP4Y_EN = 0x0
4791 11:49:06.265205 WORK_FSP = 0x0
4792 11:49:06.268136 WL = 0x3
4793 11:49:06.271044 RL = 0x3
4794 11:49:06.271514 BL = 0x2
4795 11:49:06.274544 RPST = 0x0
4796 11:49:06.275097 RD_PRE = 0x0
4797 11:49:06.277586 WR_PRE = 0x1
4798 11:49:06.278053 WR_PST = 0x0
4799 11:49:06.281441 DBI_WR = 0x0
4800 11:49:06.281911 DBI_RD = 0x0
4801 11:49:06.284594 OTF = 0x1
4802 11:49:06.287680 ===================================
4803 11:49:06.294147 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4804 11:49:06.297475 nWR fixed to 30
4805 11:49:06.298039 [ModeRegInit_LP4] CH0 RK0
4806 11:49:06.301202 [ModeRegInit_LP4] CH0 RK1
4807 11:49:06.304128 [ModeRegInit_LP4] CH1 RK0
4808 11:49:06.304630 [ModeRegInit_LP4] CH1 RK1
4809 11:49:06.307379 match AC timing 8
4810 11:49:06.310910 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4811 11:49:06.314201 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4812 11:49:06.321097 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4813 11:49:06.324035 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4814 11:49:06.330733 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4815 11:49:06.331304 ==
4816 11:49:06.333755 Dram Type= 6, Freq= 0, CH_0, rank 0
4817 11:49:06.337212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4818 11:49:06.337701 ==
4819 11:49:06.344015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4820 11:49:06.350260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4821 11:49:06.353492 [CA 0] Center 38 (8~69) winsize 62
4822 11:49:06.357059 [CA 1] Center 38 (8~69) winsize 62
4823 11:49:06.360368 [CA 2] Center 36 (6~67) winsize 62
4824 11:49:06.363697 [CA 3] Center 36 (6~66) winsize 61
4825 11:49:06.367107 [CA 4] Center 34 (4~65) winsize 62
4826 11:49:06.367665 [CA 5] Center 34 (4~64) winsize 61
4827 11:49:06.370338
4828 11:49:06.373620 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4829 11:49:06.374093
4830 11:49:06.377068 [CATrainingPosCal] consider 1 rank data
4831 11:49:06.380317 u2DelayCellTimex100 = 270/100 ps
4832 11:49:06.383643 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4833 11:49:06.387083 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4834 11:49:06.390224 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4835 11:49:06.393804 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4836 11:49:06.396867 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4837 11:49:06.400333 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4838 11:49:06.400955
4839 11:49:06.403540 CA PerBit enable=1, Macro0, CA PI delay=34
4840 11:49:06.407043
4841 11:49:06.407600 [CBTSetCACLKResult] CA Dly = 34
4842 11:49:06.410303 CS Dly: 7 (0~38)
4843 11:49:06.410859 ==
4844 11:49:06.413770 Dram Type= 6, Freq= 0, CH_0, rank 1
4845 11:49:06.416811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4846 11:49:06.417376 ==
4847 11:49:06.423396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4848 11:49:06.430103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4849 11:49:06.433425 [CA 0] Center 38 (8~69) winsize 62
4850 11:49:06.436893 [CA 1] Center 38 (8~69) winsize 62
4851 11:49:06.440012 [CA 2] Center 36 (5~67) winsize 63
4852 11:49:06.443187 [CA 3] Center 35 (5~66) winsize 62
4853 11:49:06.446444 [CA 4] Center 34 (4~65) winsize 62
4854 11:49:06.449703 [CA 5] Center 34 (4~65) winsize 62
4855 11:49:06.450269
4856 11:49:06.453372 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4857 11:49:06.453844
4858 11:49:06.456408 [CATrainingPosCal] consider 2 rank data
4859 11:49:06.459813 u2DelayCellTimex100 = 270/100 ps
4860 11:49:06.463233 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4861 11:49:06.466312 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4862 11:49:06.469860 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4863 11:49:06.473203 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4864 11:49:06.476393 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4865 11:49:06.479833 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4866 11:49:06.483149
4867 11:49:06.486277 CA PerBit enable=1, Macro0, CA PI delay=34
4868 11:49:06.486833
4869 11:49:06.489331 [CBTSetCACLKResult] CA Dly = 34
4870 11:49:06.489805 CS Dly: 7 (0~39)
4871 11:49:06.490182
4872 11:49:06.492847 ----->DramcWriteLeveling(PI) begin...
4873 11:49:06.493408 ==
4874 11:49:06.496013 Dram Type= 6, Freq= 0, CH_0, rank 0
4875 11:49:06.499720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4876 11:49:06.502750 ==
4877 11:49:06.503313 Write leveling (Byte 0): 24 => 24
4878 11:49:06.506333 Write leveling (Byte 1): 24 => 24
4879 11:49:06.509638 DramcWriteLeveling(PI) end<-----
4880 11:49:06.510194
4881 11:49:06.510571 ==
4882 11:49:06.512796 Dram Type= 6, Freq= 0, CH_0, rank 0
4883 11:49:06.519363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4884 11:49:06.519924 ==
4885 11:49:06.520300 [Gating] SW mode calibration
4886 11:49:06.529321 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4887 11:49:06.532737 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4888 11:49:06.539159 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4889 11:49:06.542657 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4890 11:49:06.545896 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4891 11:49:06.552411 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4892 11:49:06.555628 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4893 11:49:06.559281 0 10 20 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 1)
4894 11:49:06.565917 0 10 24 | B1->B0 | 2f2f 2727 | 0 0 | (1 1) (0 0)
4895 11:49:06.569063 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4896 11:49:06.572428 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4897 11:49:06.575516 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4898 11:49:06.582460 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4899 11:49:06.585603 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4900 11:49:06.588851 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4901 11:49:06.595744 0 11 20 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
4902 11:49:06.599044 0 11 24 | B1->B0 | 3a39 4646 | 1 0 | (0 0) (0 0)
4903 11:49:06.602181 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4904 11:49:06.608993 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4905 11:49:06.612352 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4906 11:49:06.615560 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4907 11:49:06.622007 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4908 11:49:06.625584 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4909 11:49:06.628786 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4910 11:49:06.635488 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4911 11:49:06.638735 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4912 11:49:06.642275 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4913 11:49:06.648818 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4914 11:49:06.651832 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4915 11:49:06.655209 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4916 11:49:06.661870 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4917 11:49:06.665157 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4918 11:49:06.668424 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4919 11:49:06.675017 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4920 11:49:06.678326 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4921 11:49:06.681951 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4922 11:49:06.688336 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4923 11:49:06.691729 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4924 11:49:06.695173 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4925 11:49:06.701520 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4926 11:49:06.704925 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4927 11:49:06.707923 Total UI for P1: 0, mck2ui 16
4928 11:49:06.711173 best dqsien dly found for B0: ( 0, 14, 20)
4929 11:49:06.714775 Total UI for P1: 0, mck2ui 16
4930 11:49:06.718290 best dqsien dly found for B1: ( 0, 14, 20)
4931 11:49:06.721450 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4932 11:49:06.725178 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4933 11:49:06.725738
4934 11:49:06.728137 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4935 11:49:06.731227 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4936 11:49:06.734676 [Gating] SW calibration Done
4937 11:49:06.735238 ==
4938 11:49:06.738054 Dram Type= 6, Freq= 0, CH_0, rank 0
4939 11:49:06.741168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4940 11:49:06.744678 ==
4941 11:49:06.745236 RX Vref Scan: 0
4942 11:49:06.745608
4943 11:49:06.747769 RX Vref 0 -> 0, step: 1
4944 11:49:06.748238
4945 11:49:06.750981 RX Delay -80 -> 252, step: 8
4946 11:49:06.754388 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
4947 11:49:06.757703 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4948 11:49:06.761105 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4949 11:49:06.764787 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4950 11:49:06.767954 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4951 11:49:06.774724 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
4952 11:49:06.778044 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4953 11:49:06.781170 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4954 11:49:06.784610 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4955 11:49:06.787901 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4956 11:49:06.791070 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4957 11:49:06.797711 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
4958 11:49:06.801096 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4959 11:49:06.804460 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4960 11:49:06.807777 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4961 11:49:06.811116 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4962 11:49:06.811684 ==
4963 11:49:06.814446 Dram Type= 6, Freq= 0, CH_0, rank 0
4964 11:49:06.821189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4965 11:49:06.821748 ==
4966 11:49:06.822130 DQS Delay:
4967 11:49:06.824544 DQS0 = 0, DQS1 = 0
4968 11:49:06.825112 DQM Delay:
4969 11:49:06.827469 DQM0 = 96, DQM1 = 86
4970 11:49:06.828024 DQ Delay:
4971 11:49:06.830879 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
4972 11:49:06.834149 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
4973 11:49:06.837363 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =75
4974 11:49:06.841026 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
4975 11:49:06.841589
4976 11:49:06.841962
4977 11:49:06.842305 ==
4978 11:49:06.843817 Dram Type= 6, Freq= 0, CH_0, rank 0
4979 11:49:06.847288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4980 11:49:06.847853 ==
4981 11:49:06.848222
4982 11:49:06.848634
4983 11:49:06.850308 TX Vref Scan disable
4984 11:49:06.853969 == TX Byte 0 ==
4985 11:49:06.857071 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
4986 11:49:06.860246 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
4987 11:49:06.863908 == TX Byte 1 ==
4988 11:49:06.866911 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
4989 11:49:06.870524 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
4990 11:49:06.871087 ==
4991 11:49:06.873688 Dram Type= 6, Freq= 0, CH_0, rank 0
4992 11:49:06.880761 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4993 11:49:06.881319 ==
4994 11:49:06.881695
4995 11:49:06.882033
4996 11:49:06.882356 TX Vref Scan disable
4997 11:49:06.883872 == TX Byte 0 ==
4998 11:49:06.887607 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
4999 11:49:06.891077 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5000 11:49:06.894399 == TX Byte 1 ==
5001 11:49:06.897555 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5002 11:49:06.904251 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5003 11:49:06.904874
5004 11:49:06.905249 [DATLAT]
5005 11:49:06.905589 Freq=933, CH0 RK0
5006 11:49:06.905919
5007 11:49:06.907319 DATLAT Default: 0xd
5008 11:49:06.907780 0, 0xFFFF, sum = 0
5009 11:49:06.910982 1, 0xFFFF, sum = 0
5010 11:49:06.911547 2, 0xFFFF, sum = 0
5011 11:49:06.914106 3, 0xFFFF, sum = 0
5012 11:49:06.917487 4, 0xFFFF, sum = 0
5013 11:49:06.918052 5, 0xFFFF, sum = 0
5014 11:49:06.920696 6, 0xFFFF, sum = 0
5015 11:49:06.921167 7, 0xFFFF, sum = 0
5016 11:49:06.923870 8, 0xFFFF, sum = 0
5017 11:49:06.924446 9, 0xFFFF, sum = 0
5018 11:49:06.927359 10, 0x0, sum = 1
5019 11:49:06.927925 11, 0x0, sum = 2
5020 11:49:06.930782 12, 0x0, sum = 3
5021 11:49:06.931348 13, 0x0, sum = 4
5022 11:49:06.931734 best_step = 11
5023 11:49:06.932078
5024 11:49:06.934000 ==
5025 11:49:06.934559 Dram Type= 6, Freq= 0, CH_0, rank 0
5026 11:49:06.940757 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5027 11:49:06.941386 ==
5028 11:49:06.941771 RX Vref Scan: 1
5029 11:49:06.942127
5030 11:49:06.943792 RX Vref 0 -> 0, step: 1
5031 11:49:06.944258
5032 11:49:06.947251 RX Delay -69 -> 252, step: 4
5033 11:49:06.947808
5034 11:49:06.950504 Set Vref, RX VrefLevel [Byte0]: 49
5035 11:49:06.953947 [Byte1]: 49
5036 11:49:06.954552
5037 11:49:06.957243 Final RX Vref Byte 0 = 49 to rank0
5038 11:49:06.960442 Final RX Vref Byte 1 = 49 to rank0
5039 11:49:06.963877 Final RX Vref Byte 0 = 49 to rank1
5040 11:49:06.967181 Final RX Vref Byte 1 = 49 to rank1==
5041 11:49:06.970449 Dram Type= 6, Freq= 0, CH_0, rank 0
5042 11:49:06.973734 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5043 11:49:06.976858 ==
5044 11:49:06.977332 DQS Delay:
5045 11:49:06.977705 DQS0 = 0, DQS1 = 0
5046 11:49:06.980294 DQM Delay:
5047 11:49:06.980903 DQM0 = 96, DQM1 = 86
5048 11:49:06.983766 DQ Delay:
5049 11:49:06.984330 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =94
5050 11:49:06.986985 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =102
5051 11:49:06.990331 DQ8 =76, DQ9 =70, DQ10 =88, DQ11 =78
5052 11:49:06.997213 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =98
5053 11:49:06.997791
5054 11:49:06.998168
5055 11:49:07.003504 [DQSOSCAuto] RK0, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5056 11:49:07.006884 CH0 RK0: MR19=505, MR18=2222
5057 11:49:07.013445 CH0_RK0: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5058 11:49:07.014019
5059 11:49:07.016552 ----->DramcWriteLeveling(PI) begin...
5060 11:49:07.017126 ==
5061 11:49:07.020055 Dram Type= 6, Freq= 0, CH_0, rank 1
5062 11:49:07.023376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5063 11:49:07.023937 ==
5064 11:49:07.026535 Write leveling (Byte 0): 30 => 30
5065 11:49:07.030029 Write leveling (Byte 1): 28 => 28
5066 11:49:07.033843 DramcWriteLeveling(PI) end<-----
5067 11:49:07.034407
5068 11:49:07.034780 ==
5069 11:49:07.036227 Dram Type= 6, Freq= 0, CH_0, rank 1
5070 11:49:07.039664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5071 11:49:07.040225 ==
5072 11:49:07.042845 [Gating] SW mode calibration
5073 11:49:07.049575 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5074 11:49:07.056187 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5075 11:49:07.059992 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5076 11:49:07.066406 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5077 11:49:07.069478 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5078 11:49:07.073116 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5079 11:49:07.076093 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5080 11:49:07.082875 0 10 20 | B1->B0 | 3232 2c2c | 0 0 | (0 1) (0 1)
5081 11:49:07.086202 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5082 11:49:07.089991 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5083 11:49:07.096143 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5084 11:49:07.099569 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5085 11:49:07.102839 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5086 11:49:07.109403 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5087 11:49:07.112757 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5088 11:49:07.116428 0 11 20 | B1->B0 | 2d2d 3535 | 1 0 | (0 0) (1 1)
5089 11:49:07.122762 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5090 11:49:07.126056 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5091 11:49:07.129415 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5092 11:49:07.135857 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5093 11:49:07.139101 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5094 11:49:07.142773 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5095 11:49:07.149233 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5096 11:49:07.152294 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5097 11:49:07.155571 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5098 11:49:07.162461 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5099 11:49:07.165940 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5100 11:49:07.168820 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5101 11:49:07.175564 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5102 11:49:07.179020 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5103 11:49:07.182134 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5104 11:49:07.188875 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5105 11:49:07.192069 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5106 11:49:07.195348 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5107 11:49:07.201884 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5108 11:49:07.205116 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 11:49:07.208406 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 11:49:07.215266 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 11:49:07.218084 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 11:49:07.221651 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5113 11:49:07.228402 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5114 11:49:07.231737 Total UI for P1: 0, mck2ui 16
5115 11:49:07.235131 best dqsien dly found for B0: ( 0, 14, 20)
5116 11:49:07.238334 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 11:49:07.241346 Total UI for P1: 0, mck2ui 16
5118 11:49:07.245176 best dqsien dly found for B1: ( 0, 14, 22)
5119 11:49:07.248332 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5120 11:49:07.251424 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5121 11:49:07.251910
5122 11:49:07.254493 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5123 11:49:07.258156 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5124 11:49:07.261328 [Gating] SW calibration Done
5125 11:49:07.261794 ==
5126 11:49:07.264650 Dram Type= 6, Freq= 0, CH_0, rank 1
5127 11:49:07.271435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5128 11:49:07.271999 ==
5129 11:49:07.272373 RX Vref Scan: 0
5130 11:49:07.272797
5131 11:49:07.274484 RX Vref 0 -> 0, step: 1
5132 11:49:07.275043
5133 11:49:07.277875 RX Delay -80 -> 252, step: 8
5134 11:49:07.280988 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5135 11:49:07.284909 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5136 11:49:07.287525 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5137 11:49:07.291186 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5138 11:49:07.297948 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5139 11:49:07.301155 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5140 11:49:07.304326 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5141 11:49:07.307718 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5142 11:49:07.310979 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5143 11:49:07.317720 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5144 11:49:07.321141 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5145 11:49:07.324676 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5146 11:49:07.327315 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5147 11:49:07.331122 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5148 11:49:07.337743 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5149 11:49:07.340745 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5150 11:49:07.341406 ==
5151 11:49:07.343868 Dram Type= 6, Freq= 0, CH_0, rank 1
5152 11:49:07.347688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5153 11:49:07.348257 ==
5154 11:49:07.348692 DQS Delay:
5155 11:49:07.350550 DQS0 = 0, DQS1 = 0
5156 11:49:07.351018 DQM Delay:
5157 11:49:07.353779 DQM0 = 95, DQM1 = 85
5158 11:49:07.354248 DQ Delay:
5159 11:49:07.357250 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5160 11:49:07.360450 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5161 11:49:07.364089 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5162 11:49:07.367081 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5163 11:49:07.367637
5164 11:49:07.368013
5165 11:49:07.368356 ==
5166 11:49:07.370929 Dram Type= 6, Freq= 0, CH_0, rank 1
5167 11:49:07.376912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5168 11:49:07.377461 ==
5169 11:49:07.377830
5170 11:49:07.378163
5171 11:49:07.378484 TX Vref Scan disable
5172 11:49:07.380327 == TX Byte 0 ==
5173 11:49:07.384063 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5174 11:49:07.387210 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5175 11:49:07.390171 == TX Byte 1 ==
5176 11:49:07.393936 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5177 11:49:07.400263 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5178 11:49:07.400875 ==
5179 11:49:07.403664 Dram Type= 6, Freq= 0, CH_0, rank 1
5180 11:49:07.406981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5181 11:49:07.407550 ==
5182 11:49:07.407920
5183 11:49:07.408261
5184 11:49:07.410196 TX Vref Scan disable
5185 11:49:07.410756 == TX Byte 0 ==
5186 11:49:07.416641 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5187 11:49:07.419987 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5188 11:49:07.423533 == TX Byte 1 ==
5189 11:49:07.426607 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5190 11:49:07.430374 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5191 11:49:07.430932
5192 11:49:07.431299 [DATLAT]
5193 11:49:07.433027 Freq=933, CH0 RK1
5194 11:49:07.433490
5195 11:49:07.433854 DATLAT Default: 0xb
5196 11:49:07.436677 0, 0xFFFF, sum = 0
5197 11:49:07.439788 1, 0xFFFF, sum = 0
5198 11:49:07.440360 2, 0xFFFF, sum = 0
5199 11:49:07.443161 3, 0xFFFF, sum = 0
5200 11:49:07.443634 4, 0xFFFF, sum = 0
5201 11:49:07.446226 5, 0xFFFF, sum = 0
5202 11:49:07.446694 6, 0xFFFF, sum = 0
5203 11:49:07.449597 7, 0xFFFF, sum = 0
5204 11:49:07.450086 8, 0xFFFF, sum = 0
5205 11:49:07.453065 9, 0xFFFF, sum = 0
5206 11:49:07.453534 10, 0x0, sum = 1
5207 11:49:07.456008 11, 0x0, sum = 2
5208 11:49:07.456503 12, 0x0, sum = 3
5209 11:49:07.459412 13, 0x0, sum = 4
5210 11:49:07.459923 best_step = 11
5211 11:49:07.460297
5212 11:49:07.460688 ==
5213 11:49:07.462892 Dram Type= 6, Freq= 0, CH_0, rank 1
5214 11:49:07.466176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5215 11:49:07.466644 ==
5216 11:49:07.469352 RX Vref Scan: 0
5217 11:49:07.469847
5218 11:49:07.472474 RX Vref 0 -> 0, step: 1
5219 11:49:07.472974
5220 11:49:07.473347 RX Delay -69 -> 252, step: 4
5221 11:49:07.480657 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5222 11:49:07.484050 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5223 11:49:07.487352 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5224 11:49:07.490959 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5225 11:49:07.494290 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5226 11:49:07.497236 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5227 11:49:07.504242 iDelay=203, Bit 6, Center 102 (11 ~ 194) 184
5228 11:49:07.507468 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5229 11:49:07.510707 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5230 11:49:07.513902 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5231 11:49:07.517453 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5232 11:49:07.524025 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5233 11:49:07.527536 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5234 11:49:07.530739 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5235 11:49:07.534032 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5236 11:49:07.537331 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5237 11:49:07.537897 ==
5238 11:49:07.540560 Dram Type= 6, Freq= 0, CH_0, rank 1
5239 11:49:07.546789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5240 11:49:07.547339 ==
5241 11:49:07.547706 DQS Delay:
5242 11:49:07.550463 DQS0 = 0, DQS1 = 0
5243 11:49:07.551025 DQM Delay:
5244 11:49:07.551397 DQM0 = 97, DQM1 = 86
5245 11:49:07.553358 DQ Delay:
5246 11:49:07.556965 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5247 11:49:07.560022 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =108
5248 11:49:07.563764 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5249 11:49:07.567171 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =94
5250 11:49:07.567787
5251 11:49:07.568161
5252 11:49:07.573789 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5253 11:49:07.576621 CH0 RK1: MR19=505, MR18=2E2E
5254 11:49:07.583492 CH0_RK1: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5255 11:49:07.586599 [RxdqsGatingPostProcess] freq 933
5256 11:49:07.593508 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5257 11:49:07.594062 Pre-setting of DQS Precalculation
5258 11:49:07.599900 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5259 11:49:07.600392 ==
5260 11:49:07.603308 Dram Type= 6, Freq= 0, CH_1, rank 0
5261 11:49:07.606812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5262 11:49:07.607528 ==
5263 11:49:07.613102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5264 11:49:07.619568 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5265 11:49:07.623003 [CA 0] Center 37 (7~68) winsize 62
5266 11:49:07.626362 [CA 1] Center 37 (6~68) winsize 63
5267 11:49:07.629716 [CA 2] Center 34 (4~65) winsize 62
5268 11:49:07.632893 [CA 3] Center 34 (4~65) winsize 62
5269 11:49:07.636412 [CA 4] Center 33 (2~64) winsize 63
5270 11:49:07.639854 [CA 5] Center 33 (2~64) winsize 63
5271 11:49:07.640421
5272 11:49:07.642732 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5273 11:49:07.643193
5274 11:49:07.646187 [CATrainingPosCal] consider 1 rank data
5275 11:49:07.649479 u2DelayCellTimex100 = 270/100 ps
5276 11:49:07.652667 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5277 11:49:07.655895 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5278 11:49:07.659389 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5279 11:49:07.662983 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5280 11:49:07.665857 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5281 11:49:07.672746 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5282 11:49:07.673302
5283 11:49:07.675884 CA PerBit enable=1, Macro0, CA PI delay=33
5284 11:49:07.676446
5285 11:49:07.679191 [CBTSetCACLKResult] CA Dly = 33
5286 11:49:07.679751 CS Dly: 5 (0~36)
5287 11:49:07.680143 ==
5288 11:49:07.682636 Dram Type= 6, Freq= 0, CH_1, rank 1
5289 11:49:07.685686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5290 11:49:07.689287 ==
5291 11:49:07.692362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5292 11:49:07.698942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5293 11:49:07.701976 [CA 0] Center 37 (6~68) winsize 63
5294 11:49:07.705483 [CA 1] Center 37 (6~68) winsize 63
5295 11:49:07.708759 [CA 2] Center 34 (4~65) winsize 62
5296 11:49:07.712296 [CA 3] Center 34 (4~65) winsize 62
5297 11:49:07.715378 [CA 4] Center 33 (2~64) winsize 63
5298 11:49:07.719914 [CA 5] Center 33 (2~64) winsize 63
5299 11:49:07.720378
5300 11:49:07.722015 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5301 11:49:07.722491
5302 11:49:07.725381 [CATrainingPosCal] consider 2 rank data
5303 11:49:07.728755 u2DelayCellTimex100 = 270/100 ps
5304 11:49:07.731899 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5305 11:49:07.735412 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5306 11:49:07.738756 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5307 11:49:07.745219 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5308 11:49:07.748702 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5309 11:49:07.751919 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5310 11:49:07.752583
5311 11:49:07.754958 CA PerBit enable=1, Macro0, CA PI delay=33
5312 11:49:07.755432
5313 11:49:07.758256 [CBTSetCACLKResult] CA Dly = 33
5314 11:49:07.758718 CS Dly: 5 (0~37)
5315 11:49:07.759081
5316 11:49:07.761825 ----->DramcWriteLeveling(PI) begin...
5317 11:49:07.764876 ==
5318 11:49:07.765489 Dram Type= 6, Freq= 0, CH_1, rank 0
5319 11:49:07.771528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5320 11:49:07.772098 ==
5321 11:49:07.775056 Write leveling (Byte 0): 24 => 24
5322 11:49:07.778687 Write leveling (Byte 1): 26 => 26
5323 11:49:07.779246 DramcWriteLeveling(PI) end<-----
5324 11:49:07.781780
5325 11:49:07.782333 ==
5326 11:49:07.785119 Dram Type= 6, Freq= 0, CH_1, rank 0
5327 11:49:07.788570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5328 11:49:07.789134 ==
5329 11:49:07.791469 [Gating] SW mode calibration
5330 11:49:07.798195 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5331 11:49:07.804643 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5332 11:49:07.808086 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 11:49:07.811264 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 11:49:07.814701 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 11:49:07.821301 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5336 11:49:07.824866 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
5337 11:49:07.827587 0 10 20 | B1->B0 | 3333 2323 | 1 0 | (0 1) (0 0)
5338 11:49:07.834612 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5339 11:49:07.837810 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 11:49:07.841108 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 11:49:07.847825 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 11:49:07.850719 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 11:49:07.854171 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 11:49:07.860837 0 11 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
5345 11:49:07.863993 0 11 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
5346 11:49:07.867537 0 11 24 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5347 11:49:07.874321 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 11:49:07.877432 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 11:49:07.880607 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 11:49:07.887015 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 11:49:07.890372 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 11:49:07.893607 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 11:49:07.900685 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5354 11:49:07.903897 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 11:49:07.907136 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 11:49:07.913759 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 11:49:07.917270 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 11:49:07.920309 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 11:49:07.927177 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 11:49:07.930451 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 11:49:07.933476 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 11:49:07.940107 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 11:49:07.943511 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 11:49:07.947140 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 11:49:07.953318 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 11:49:07.956954 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 11:49:07.959848 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 11:49:07.966977 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5369 11:49:07.969813 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5370 11:49:07.973359 Total UI for P1: 0, mck2ui 16
5371 11:49:07.976399 best dqsien dly found for B0: ( 0, 14, 16)
5372 11:49:07.979963 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 11:49:07.983061 Total UI for P1: 0, mck2ui 16
5374 11:49:07.986601 best dqsien dly found for B1: ( 0, 14, 20)
5375 11:49:07.989976 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5376 11:49:07.992973 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5377 11:49:07.993446
5378 11:49:07.999868 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5379 11:49:08.002936 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5380 11:49:08.006399 [Gating] SW calibration Done
5381 11:49:08.006961 ==
5382 11:49:08.009612 Dram Type= 6, Freq= 0, CH_1, rank 0
5383 11:49:08.013209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5384 11:49:08.013772 ==
5385 11:49:08.014147 RX Vref Scan: 0
5386 11:49:08.014499
5387 11:49:08.016050 RX Vref 0 -> 0, step: 1
5388 11:49:08.016646
5389 11:49:08.019290 RX Delay -80 -> 252, step: 8
5390 11:49:08.022981 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5391 11:49:08.026269 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5392 11:49:08.032813 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5393 11:49:08.036309 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5394 11:49:08.039645 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5395 11:49:08.042534 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5396 11:49:08.045984 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5397 11:49:08.049330 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5398 11:49:08.055658 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5399 11:49:08.058857 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5400 11:49:08.062562 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5401 11:49:08.065536 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5402 11:49:08.069090 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5403 11:49:08.075890 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5404 11:49:08.079039 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5405 11:49:08.081963 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5406 11:49:08.082438 ==
5407 11:49:08.085347 Dram Type= 6, Freq= 0, CH_1, rank 0
5408 11:49:08.088898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5409 11:49:08.089423 ==
5410 11:49:08.092193 DQS Delay:
5411 11:49:08.092804 DQS0 = 0, DQS1 = 0
5412 11:49:08.095671 DQM Delay:
5413 11:49:08.096260 DQM0 = 94, DQM1 = 87
5414 11:49:08.096815 DQ Delay:
5415 11:49:08.098798 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5416 11:49:08.101867 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5417 11:49:08.105518 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5418 11:49:08.108898 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =95
5419 11:49:08.109488
5420 11:49:08.111770
5421 11:49:08.112243 ==
5422 11:49:08.114995 Dram Type= 6, Freq= 0, CH_1, rank 0
5423 11:49:08.118634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5424 11:49:08.119218 ==
5425 11:49:08.119713
5426 11:49:08.120172
5427 11:49:08.121931 TX Vref Scan disable
5428 11:49:08.122406 == TX Byte 0 ==
5429 11:49:08.128463 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5430 11:49:08.131800 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5431 11:49:08.132281 == TX Byte 1 ==
5432 11:49:08.138419 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5433 11:49:08.141498 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5434 11:49:08.142079 ==
5435 11:49:08.144712 Dram Type= 6, Freq= 0, CH_1, rank 0
5436 11:49:08.148253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5437 11:49:08.148898 ==
5438 11:49:08.149391
5439 11:49:08.149846
5440 11:49:08.151300 TX Vref Scan disable
5441 11:49:08.154545 == TX Byte 0 ==
5442 11:49:08.158181 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5443 11:49:08.161287 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5444 11:49:08.164984 == TX Byte 1 ==
5445 11:49:08.168246 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5446 11:49:08.171521 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5447 11:49:08.172101
5448 11:49:08.174700 [DATLAT]
5449 11:49:08.175179 Freq=933, CH1 RK0
5450 11:49:08.175664
5451 11:49:08.177962 DATLAT Default: 0xd
5452 11:49:08.178441 0, 0xFFFF, sum = 0
5453 11:49:08.181431 1, 0xFFFF, sum = 0
5454 11:49:08.182010 2, 0xFFFF, sum = 0
5455 11:49:08.184590 3, 0xFFFF, sum = 0
5456 11:49:08.185171 4, 0xFFFF, sum = 0
5457 11:49:08.187942 5, 0xFFFF, sum = 0
5458 11:49:08.188427 6, 0xFFFF, sum = 0
5459 11:49:08.191088 7, 0xFFFF, sum = 0
5460 11:49:08.194708 8, 0xFFFF, sum = 0
5461 11:49:08.195297 9, 0xFFFF, sum = 0
5462 11:49:08.195792 10, 0x0, sum = 1
5463 11:49:08.197641 11, 0x0, sum = 2
5464 11:49:08.198128 12, 0x0, sum = 3
5465 11:49:08.200844 13, 0x0, sum = 4
5466 11:49:08.201330 best_step = 11
5467 11:49:08.201811
5468 11:49:08.202264 ==
5469 11:49:08.204191 Dram Type= 6, Freq= 0, CH_1, rank 0
5470 11:49:08.211022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5471 11:49:08.211593 ==
5472 11:49:08.212089 RX Vref Scan: 1
5473 11:49:08.212586
5474 11:49:08.214085 RX Vref 0 -> 0, step: 1
5475 11:49:08.214564
5476 11:49:08.217334 RX Delay -69 -> 252, step: 4
5477 11:49:08.217900
5478 11:49:08.220565 Set Vref, RX VrefLevel [Byte0]: 54
5479 11:49:08.224114 [Byte1]: 50
5480 11:49:08.224735
5481 11:49:08.227500 Final RX Vref Byte 0 = 54 to rank0
5482 11:49:08.230767 Final RX Vref Byte 1 = 50 to rank0
5483 11:49:08.234233 Final RX Vref Byte 0 = 54 to rank1
5484 11:49:08.237429 Final RX Vref Byte 1 = 50 to rank1==
5485 11:49:08.240796 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 11:49:08.243894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5487 11:49:08.244378 ==
5488 11:49:08.247070 DQS Delay:
5489 11:49:08.247548 DQS0 = 0, DQS1 = 0
5490 11:49:08.250737 DQM Delay:
5491 11:49:08.251313 DQM0 = 94, DQM1 = 88
5492 11:49:08.253934 DQ Delay:
5493 11:49:08.254413 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5494 11:49:08.257239 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5495 11:49:08.260579 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5496 11:49:08.263898 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5497 11:49:08.267106
5498 11:49:08.267680
5499 11:49:08.273934 [DQSOSCAuto] RK0, (LSB)MR18= 0x3030, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5500 11:49:08.277459 CH1 RK0: MR19=505, MR18=3030
5501 11:49:08.283544 CH1_RK0: MR19=0x505, MR18=0x3030, DQSOSC=406, MR23=63, INC=65, DEC=43
5502 11:49:08.284109
5503 11:49:08.286847 ----->DramcWriteLeveling(PI) begin...
5504 11:49:08.287336 ==
5505 11:49:08.290457 Dram Type= 6, Freq= 0, CH_1, rank 1
5506 11:49:08.293868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5507 11:49:08.294450 ==
5508 11:49:08.297165 Write leveling (Byte 0): 23 => 23
5509 11:49:08.300408 Write leveling (Byte 1): 22 => 22
5510 11:49:08.303540 DramcWriteLeveling(PI) end<-----
5511 11:49:08.304021
5512 11:49:08.304540 ==
5513 11:49:08.307148 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 11:49:08.310349 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5515 11:49:08.310949 ==
5516 11:49:08.313712 [Gating] SW mode calibration
5517 11:49:08.320322 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5518 11:49:08.326833 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5519 11:49:08.329958 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5520 11:49:08.333188 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5521 11:49:08.340078 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5522 11:49:08.343475 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5523 11:49:08.346924 0 10 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 1)
5524 11:49:08.353103 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5525 11:49:08.356306 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5526 11:49:08.359667 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5527 11:49:08.366399 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5528 11:49:08.369755 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5529 11:49:08.373389 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5530 11:49:08.379837 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5531 11:49:08.383270 0 11 16 | B1->B0 | 2424 4141 | 0 0 | (0 0) (0 0)
5532 11:49:08.386398 0 11 20 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
5533 11:49:08.392998 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5534 11:49:08.396280 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5535 11:49:08.399793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5536 11:49:08.406315 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5537 11:49:08.409300 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5538 11:49:08.412671 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5539 11:49:08.419539 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5540 11:49:08.422651 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5541 11:49:08.426016 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5542 11:49:08.432690 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5543 11:49:08.436256 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5544 11:49:08.439373 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5545 11:49:08.445731 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5546 11:49:08.449044 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5547 11:49:08.452191 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5548 11:49:08.459093 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5549 11:49:08.462101 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5550 11:49:08.465424 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5551 11:49:08.472159 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5552 11:49:08.475618 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5553 11:49:08.479168 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5554 11:49:08.485494 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5555 11:49:08.488483 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5556 11:49:08.492209 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 11:49:08.495300 Total UI for P1: 0, mck2ui 16
5558 11:49:08.498838 best dqsien dly found for B0: ( 0, 14, 16)
5559 11:49:08.501805 Total UI for P1: 0, mck2ui 16
5560 11:49:08.505103 best dqsien dly found for B1: ( 0, 14, 16)
5561 11:49:08.508631 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5562 11:49:08.511726 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5563 11:49:08.515370
5564 11:49:08.518352 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5565 11:49:08.521764 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5566 11:49:08.524863 [Gating] SW calibration Done
5567 11:49:08.525442 ==
5568 11:49:08.528347 Dram Type= 6, Freq= 0, CH_1, rank 1
5569 11:49:08.531771 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5570 11:49:08.532350 ==
5571 11:49:08.534665 RX Vref Scan: 0
5572 11:49:08.535241
5573 11:49:08.535728 RX Vref 0 -> 0, step: 1
5574 11:49:08.536191
5575 11:49:08.538196 RX Delay -80 -> 252, step: 8
5576 11:49:08.541361 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5577 11:49:08.548170 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5578 11:49:08.550990 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5579 11:49:08.554592 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5580 11:49:08.557800 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5581 11:49:08.561337 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5582 11:49:08.564433 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5583 11:49:08.570778 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5584 11:49:08.574832 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5585 11:49:08.577664 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5586 11:49:08.580943 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5587 11:49:08.584820 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5588 11:49:08.591235 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5589 11:49:08.594074 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5590 11:49:08.597669 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5591 11:49:08.600782 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5592 11:49:08.601363 ==
5593 11:49:08.604120 Dram Type= 6, Freq= 0, CH_1, rank 1
5594 11:49:08.607518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5595 11:49:08.608111 ==
5596 11:49:08.610882 DQS Delay:
5597 11:49:08.611469 DQS0 = 0, DQS1 = 0
5598 11:49:08.613940 DQM Delay:
5599 11:49:08.614531 DQM0 = 98, DQM1 = 89
5600 11:49:08.617488 DQ Delay:
5601 11:49:08.618064 DQ0 =107, DQ1 =91, DQ2 =87, DQ3 =95
5602 11:49:08.620611 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =91
5603 11:49:08.624166 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5604 11:49:08.627249 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5605 11:49:08.630364
5606 11:49:08.630845
5607 11:49:08.631326 ==
5608 11:49:08.633805 Dram Type= 6, Freq= 0, CH_1, rank 1
5609 11:49:08.637271 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5610 11:49:08.637855 ==
5611 11:49:08.638348
5612 11:49:08.638805
5613 11:49:08.640280 TX Vref Scan disable
5614 11:49:08.640799 == TX Byte 0 ==
5615 11:49:08.647224 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5616 11:49:08.650312 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5617 11:49:08.650895 == TX Byte 1 ==
5618 11:49:08.656740 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5619 11:49:08.660281 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5620 11:49:08.660913 ==
5621 11:49:08.663312 Dram Type= 6, Freq= 0, CH_1, rank 1
5622 11:49:08.666546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5623 11:49:08.667026 ==
5624 11:49:08.667509
5625 11:49:08.667960
5626 11:49:08.669837 TX Vref Scan disable
5627 11:49:08.673223 == TX Byte 0 ==
5628 11:49:08.676655 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5629 11:49:08.679872 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5630 11:49:08.683331 == TX Byte 1 ==
5631 11:49:08.686847 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5632 11:49:08.690202 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5633 11:49:08.690786
5634 11:49:08.693256 [DATLAT]
5635 11:49:08.693733 Freq=933, CH1 RK1
5636 11:49:08.694221
5637 11:49:08.696471 DATLAT Default: 0xb
5638 11:49:08.696980 0, 0xFFFF, sum = 0
5639 11:49:08.699903 1, 0xFFFF, sum = 0
5640 11:49:08.700345 2, 0xFFFF, sum = 0
5641 11:49:08.703258 3, 0xFFFF, sum = 0
5642 11:49:08.703844 4, 0xFFFF, sum = 0
5643 11:49:08.706513 5, 0xFFFF, sum = 0
5644 11:49:08.707000 6, 0xFFFF, sum = 0
5645 11:49:08.710110 7, 0xFFFF, sum = 0
5646 11:49:08.710707 8, 0xFFFF, sum = 0
5647 11:49:08.713496 9, 0xFFFF, sum = 0
5648 11:49:08.714076 10, 0x0, sum = 1
5649 11:49:08.716625 11, 0x0, sum = 2
5650 11:49:08.717198 12, 0x0, sum = 3
5651 11:49:08.719627 13, 0x0, sum = 4
5652 11:49:08.720101 best_step = 11
5653 11:49:08.720472
5654 11:49:08.720882 ==
5655 11:49:08.723157 Dram Type= 6, Freq= 0, CH_1, rank 1
5656 11:49:08.730012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5657 11:49:08.730603 ==
5658 11:49:08.730982 RX Vref Scan: 0
5659 11:49:08.731335
5660 11:49:08.732859 RX Vref 0 -> 0, step: 1
5661 11:49:08.733324
5662 11:49:08.736240 RX Delay -61 -> 252, step: 4
5663 11:49:08.739615 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5664 11:49:08.746272 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5665 11:49:08.749444 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5666 11:49:08.752887 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5667 11:49:08.755896 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5668 11:49:08.759516 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5669 11:49:08.762522 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5670 11:49:08.769431 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5671 11:49:08.772868 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5672 11:49:08.776024 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5673 11:49:08.779312 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5674 11:49:08.782579 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5675 11:49:08.789330 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5676 11:49:08.792806 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5677 11:49:08.796001 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5678 11:49:08.799296 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5679 11:49:08.799858 ==
5680 11:49:08.802608 Dram Type= 6, Freq= 0, CH_1, rank 1
5681 11:49:08.805658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5682 11:49:08.809118 ==
5683 11:49:08.809675 DQS Delay:
5684 11:49:08.810114 DQS0 = 0, DQS1 = 0
5685 11:49:08.812157 DQM Delay:
5686 11:49:08.812668 DQM0 = 95, DQM1 = 87
5687 11:49:08.815809 DQ Delay:
5688 11:49:08.818867 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =92
5689 11:49:08.819427 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =94
5690 11:49:08.822242 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5691 11:49:08.828617 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5692 11:49:08.829165
5693 11:49:08.829531
5694 11:49:08.836257 [DQSOSCAuto] RK1, (LSB)MR18= 0x2828, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5695 11:49:08.838832 CH1 RK1: MR19=505, MR18=2828
5696 11:49:08.845019 CH1_RK1: MR19=0x505, MR18=0x2828, DQSOSC=409, MR23=63, INC=64, DEC=43
5697 11:49:08.848726 [RxdqsGatingPostProcess] freq 933
5698 11:49:08.852087 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5699 11:49:08.855346 Pre-setting of DQS Precalculation
5700 11:49:08.862249 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5701 11:49:08.868306 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5702 11:49:08.875207 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5703 11:49:08.875792
5704 11:49:08.876285
5705 11:49:08.878138 [Calibration Summary] 1866 Mbps
5706 11:49:08.878613 CH 0, Rank 0
5707 11:49:08.881472 SW Impedance : PASS
5708 11:49:08.884892 DUTY Scan : NO K
5709 11:49:08.885396 ZQ Calibration : PASS
5710 11:49:08.888096 Jitter Meter : NO K
5711 11:49:08.891439 CBT Training : PASS
5712 11:49:08.891908 Write leveling : PASS
5713 11:49:08.894658 RX DQS gating : PASS
5714 11:49:08.898126 RX DQ/DQS(RDDQC) : PASS
5715 11:49:08.898695 TX DQ/DQS : PASS
5716 11:49:08.901137 RX DATLAT : PASS
5717 11:49:08.904761 RX DQ/DQS(Engine): PASS
5718 11:49:08.905327 TX OE : NO K
5719 11:49:08.908134 All Pass.
5720 11:49:08.908747
5721 11:49:08.909134 CH 0, Rank 1
5722 11:49:08.911308 SW Impedance : PASS
5723 11:49:08.911877 DUTY Scan : NO K
5724 11:49:08.914576 ZQ Calibration : PASS
5725 11:49:08.917868 Jitter Meter : NO K
5726 11:49:08.918431 CBT Training : PASS
5727 11:49:08.921229 Write leveling : PASS
5728 11:49:08.924684 RX DQS gating : PASS
5729 11:49:08.925254 RX DQ/DQS(RDDQC) : PASS
5730 11:49:08.927772 TX DQ/DQS : PASS
5731 11:49:08.931136 RX DATLAT : PASS
5732 11:49:08.931607 RX DQ/DQS(Engine): PASS
5733 11:49:08.934413 TX OE : NO K
5734 11:49:08.934886 All Pass.
5735 11:49:08.935260
5736 11:49:08.935606 CH 1, Rank 0
5737 11:49:08.937587 SW Impedance : PASS
5738 11:49:08.940738 DUTY Scan : NO K
5739 11:49:08.941217 ZQ Calibration : PASS
5740 11:49:08.944145 Jitter Meter : NO K
5741 11:49:08.947369 CBT Training : PASS
5742 11:49:08.947844 Write leveling : PASS
5743 11:49:08.951267 RX DQS gating : PASS
5744 11:49:08.954066 RX DQ/DQS(RDDQC) : PASS
5745 11:49:08.954544 TX DQ/DQS : PASS
5746 11:49:08.957371 RX DATLAT : PASS
5747 11:49:08.961048 RX DQ/DQS(Engine): PASS
5748 11:49:08.961622 TX OE : NO K
5749 11:49:08.964045 All Pass.
5750 11:49:08.964745
5751 11:49:08.965130 CH 1, Rank 1
5752 11:49:08.967356 SW Impedance : PASS
5753 11:49:08.967818 DUTY Scan : NO K
5754 11:49:08.970654 ZQ Calibration : PASS
5755 11:49:08.974437 Jitter Meter : NO K
5756 11:49:08.974999 CBT Training : PASS
5757 11:49:08.977238 Write leveling : PASS
5758 11:49:08.980411 RX DQS gating : PASS
5759 11:49:08.980925 RX DQ/DQS(RDDQC) : PASS
5760 11:49:08.984192 TX DQ/DQS : PASS
5761 11:49:08.987465 RX DATLAT : PASS
5762 11:49:08.988025 RX DQ/DQS(Engine): PASS
5763 11:49:08.990513 TX OE : NO K
5764 11:49:08.990981 All Pass.
5765 11:49:08.991354
5766 11:49:08.993914 DramC Write-DBI off
5767 11:49:08.997217 PER_BANK_REFRESH: Hybrid Mode
5768 11:49:08.997777 TX_TRACKING: ON
5769 11:49:09.007271 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5770 11:49:09.010745 [FAST_K] Save calibration result to emmc
5771 11:49:09.013952 dramc_set_vcore_voltage set vcore to 650000
5772 11:49:09.017302 Read voltage for 400, 6
5773 11:49:09.017865 Vio18 = 0
5774 11:49:09.018239 Vcore = 650000
5775 11:49:09.020765 Vdram = 0
5776 11:49:09.021326 Vddq = 0
5777 11:49:09.021700 Vmddr = 0
5778 11:49:09.027062 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5779 11:49:09.030076 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5780 11:49:09.033777 MEM_TYPE=3, freq_sel=20
5781 11:49:09.037101 sv_algorithm_assistance_LP4_800
5782 11:49:09.040051 ============ PULL DRAM RESETB DOWN ============
5783 11:49:09.043622 ========== PULL DRAM RESETB DOWN end =========
5784 11:49:09.049964 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5785 11:49:09.053235 ===================================
5786 11:49:09.053703 LPDDR4 DRAM CONFIGURATION
5787 11:49:09.056554 ===================================
5788 11:49:09.060109 EX_ROW_EN[0] = 0x0
5789 11:49:09.063440 EX_ROW_EN[1] = 0x0
5790 11:49:09.064016 LP4Y_EN = 0x0
5791 11:49:09.066428 WORK_FSP = 0x0
5792 11:49:09.066891 WL = 0x2
5793 11:49:09.070051 RL = 0x2
5794 11:49:09.070613 BL = 0x2
5795 11:49:09.073075 RPST = 0x0
5796 11:49:09.073536 RD_PRE = 0x0
5797 11:49:09.076587 WR_PRE = 0x1
5798 11:49:09.077050 WR_PST = 0x0
5799 11:49:09.079705 DBI_WR = 0x0
5800 11:49:09.080319 DBI_RD = 0x0
5801 11:49:09.082994 OTF = 0x1
5802 11:49:09.086483 ===================================
5803 11:49:09.089659 ===================================
5804 11:49:09.090124 ANA top config
5805 11:49:09.093186 ===================================
5806 11:49:09.096477 DLL_ASYNC_EN = 0
5807 11:49:09.099892 ALL_SLAVE_EN = 1
5808 11:49:09.103272 NEW_RANK_MODE = 1
5809 11:49:09.103839 DLL_IDLE_MODE = 1
5810 11:49:09.106353 LP45_APHY_COMB_EN = 1
5811 11:49:09.109539 TX_ODT_DIS = 1
5812 11:49:09.113327 NEW_8X_MODE = 1
5813 11:49:09.116260 ===================================
5814 11:49:09.119626 ===================================
5815 11:49:09.122954 data_rate = 800
5816 11:49:09.123518 CKR = 1
5817 11:49:09.126425 DQ_P2S_RATIO = 4
5818 11:49:09.129419 ===================================
5819 11:49:09.132856 CA_P2S_RATIO = 4
5820 11:49:09.136295 DQ_CA_OPEN = 0
5821 11:49:09.139487 DQ_SEMI_OPEN = 1
5822 11:49:09.142887 CA_SEMI_OPEN = 1
5823 11:49:09.143452 CA_FULL_RATE = 0
5824 11:49:09.146057 DQ_CKDIV4_EN = 0
5825 11:49:09.149490 CA_CKDIV4_EN = 1
5826 11:49:09.152397 CA_PREDIV_EN = 0
5827 11:49:09.155781 PH8_DLY = 0
5828 11:49:09.159163 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5829 11:49:09.162371 DQ_AAMCK_DIV = 0
5830 11:49:09.162932 CA_AAMCK_DIV = 0
5831 11:49:09.165585 CA_ADMCK_DIV = 4
5832 11:49:09.169044 DQ_TRACK_CA_EN = 0
5833 11:49:09.172420 CA_PICK = 800
5834 11:49:09.175668 CA_MCKIO = 400
5835 11:49:09.178660 MCKIO_SEMI = 400
5836 11:49:09.182325 PLL_FREQ = 3016
5837 11:49:09.182891 DQ_UI_PI_RATIO = 32
5838 11:49:09.185738 CA_UI_PI_RATIO = 32
5839 11:49:09.188688 ===================================
5840 11:49:09.192142 ===================================
5841 11:49:09.195414 memory_type:LPDDR4
5842 11:49:09.199159 GP_NUM : 10
5843 11:49:09.199733 SRAM_EN : 1
5844 11:49:09.201870 MD32_EN : 0
5845 11:49:09.205172 ===================================
5846 11:49:09.208674 [ANA_INIT] >>>>>>>>>>>>>>
5847 11:49:09.209243 <<<<<< [CONFIGURE PHASE]: ANA_TX
5848 11:49:09.215538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5849 11:49:09.218543 ===================================
5850 11:49:09.219109 data_rate = 800,PCW = 0X7400
5851 11:49:09.221879 ===================================
5852 11:49:09.225372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5853 11:49:09.231567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5854 11:49:09.241560 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5855 11:49:09.248420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5856 11:49:09.251768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5857 11:49:09.254822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5858 11:49:09.258153 [ANA_INIT] flow start
5859 11:49:09.258619 [ANA_INIT] PLL >>>>>>>>
5860 11:49:09.261431 [ANA_INIT] PLL <<<<<<<<
5861 11:49:09.264935 [ANA_INIT] MIDPI >>>>>>>>
5862 11:49:09.265546 [ANA_INIT] MIDPI <<<<<<<<
5863 11:49:09.267968 [ANA_INIT] DLL >>>>>>>>
5864 11:49:09.271387 [ANA_INIT] flow end
5865 11:49:09.274794 ============ LP4 DIFF to SE enter ============
5866 11:49:09.278241 ============ LP4 DIFF to SE exit ============
5867 11:49:09.281201 [ANA_INIT] <<<<<<<<<<<<<
5868 11:49:09.284614 [Flow] Enable top DCM control >>>>>
5869 11:49:09.287804 [Flow] Enable top DCM control <<<<<
5870 11:49:09.291387 Enable DLL master slave shuffle
5871 11:49:09.294925 ==============================================================
5872 11:49:09.297979 Gating Mode config
5873 11:49:09.304854 ==============================================================
5874 11:49:09.305424 Config description:
5875 11:49:09.314529 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5876 11:49:09.321251 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5877 11:49:09.324397 SELPH_MODE 0: By rank 1: By Phase
5878 11:49:09.331014 ==============================================================
5879 11:49:09.334238 GAT_TRACK_EN = 0
5880 11:49:09.337944 RX_GATING_MODE = 2
5881 11:49:09.340575 RX_GATING_TRACK_MODE = 2
5882 11:49:09.343908 SELPH_MODE = 1
5883 11:49:09.347538 PICG_EARLY_EN = 1
5884 11:49:09.350738 VALID_LAT_VALUE = 1
5885 11:49:09.353834 ==============================================================
5886 11:49:09.357417 Enter into Gating configuration >>>>
5887 11:49:09.360578 Exit from Gating configuration <<<<
5888 11:49:09.364019 Enter into DVFS_PRE_config >>>>>
5889 11:49:09.377174 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5890 11:49:09.380068 Exit from DVFS_PRE_config <<<<<
5891 11:49:09.383608 Enter into PICG configuration >>>>
5892 11:49:09.386915 Exit from PICG configuration <<<<
5893 11:49:09.387478 [RX_INPUT] configuration >>>>>
5894 11:49:09.390517 [RX_INPUT] configuration <<<<<
5895 11:49:09.397071 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5896 11:49:09.400476 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5897 11:49:09.406757 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5898 11:49:09.413723 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5899 11:49:09.420214 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5900 11:49:09.427017 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5901 11:49:09.430180 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5902 11:49:09.433150 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5903 11:49:09.440140 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5904 11:49:09.442874 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5905 11:49:09.446389 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5906 11:49:09.449723 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5907 11:49:09.452883 ===================================
5908 11:49:09.456493 LPDDR4 DRAM CONFIGURATION
5909 11:49:09.459332 ===================================
5910 11:49:09.463343 EX_ROW_EN[0] = 0x0
5911 11:49:09.463905 EX_ROW_EN[1] = 0x0
5912 11:49:09.466252 LP4Y_EN = 0x0
5913 11:49:09.466716 WORK_FSP = 0x0
5914 11:49:09.469651 WL = 0x2
5915 11:49:09.470111 RL = 0x2
5916 11:49:09.472546 BL = 0x2
5917 11:49:09.476272 RPST = 0x0
5918 11:49:09.476899 RD_PRE = 0x0
5919 11:49:09.479226 WR_PRE = 0x1
5920 11:49:09.479687 WR_PST = 0x0
5921 11:49:09.483147 DBI_WR = 0x0
5922 11:49:09.483706 DBI_RD = 0x0
5923 11:49:09.486590 OTF = 0x1
5924 11:49:09.489234 ===================================
5925 11:49:09.492800 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5926 11:49:09.496447 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5927 11:49:09.499530 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5928 11:49:09.502724 ===================================
5929 11:49:09.506017 LPDDR4 DRAM CONFIGURATION
5930 11:49:09.509411 ===================================
5931 11:49:09.512810 EX_ROW_EN[0] = 0x10
5932 11:49:09.513372 EX_ROW_EN[1] = 0x0
5933 11:49:09.516061 LP4Y_EN = 0x0
5934 11:49:09.516655 WORK_FSP = 0x0
5935 11:49:09.519336 WL = 0x2
5936 11:49:09.519897 RL = 0x2
5937 11:49:09.522700 BL = 0x2
5938 11:49:09.523259 RPST = 0x0
5939 11:49:09.525771 RD_PRE = 0x0
5940 11:49:09.526232 WR_PRE = 0x1
5941 11:49:09.529341 WR_PST = 0x0
5942 11:49:09.532488 DBI_WR = 0x0
5943 11:49:09.533088 DBI_RD = 0x0
5944 11:49:09.536174 OTF = 0x1
5945 11:49:09.539211 ===================================
5946 11:49:09.542572 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5947 11:49:09.547764 nWR fixed to 30
5948 11:49:09.550805 [ModeRegInit_LP4] CH0 RK0
5949 11:49:09.551367 [ModeRegInit_LP4] CH0 RK1
5950 11:49:09.553972 [ModeRegInit_LP4] CH1 RK0
5951 11:49:09.557425 [ModeRegInit_LP4] CH1 RK1
5952 11:49:09.558056 match AC timing 18
5953 11:49:09.564136 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5954 11:49:09.567094 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5955 11:49:09.570442 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5956 11:49:09.577212 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5957 11:49:09.580827 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5958 11:49:09.581390 ==
5959 11:49:09.584088 Dram Type= 6, Freq= 0, CH_0, rank 0
5960 11:49:09.587432 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5961 11:49:09.587996 ==
5962 11:49:09.593944 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5963 11:49:09.600376 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5964 11:49:09.603699 [CA 0] Center 36 (8~64) winsize 57
5965 11:49:09.606878 [CA 1] Center 36 (8~64) winsize 57
5966 11:49:09.610342 [CA 2] Center 36 (8~64) winsize 57
5967 11:49:09.613715 [CA 3] Center 36 (8~64) winsize 57
5968 11:49:09.617430 [CA 4] Center 36 (8~64) winsize 57
5969 11:49:09.617994 [CA 5] Center 36 (8~64) winsize 57
5970 11:49:09.618367
5971 11:49:09.623787 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5972 11:49:09.624353
5973 11:49:09.627183 [CATrainingPosCal] consider 1 rank data
5974 11:49:09.630600 u2DelayCellTimex100 = 270/100 ps
5975 11:49:09.633490 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5976 11:49:09.636763 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5977 11:49:09.640213 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5978 11:49:09.643642 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5979 11:49:09.646611 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5980 11:49:09.649950 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
5981 11:49:09.650413
5982 11:49:09.653437 CA PerBit enable=1, Macro0, CA PI delay=36
5983 11:49:09.654001
5984 11:49:09.656876 [CBTSetCACLKResult] CA Dly = 36
5985 11:49:09.659904 CS Dly: 1 (0~32)
5986 11:49:09.660370 ==
5987 11:49:09.663897 Dram Type= 6, Freq= 0, CH_0, rank 1
5988 11:49:09.666691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5989 11:49:09.667159 ==
5990 11:49:09.673214 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5991 11:49:09.680211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5992 11:49:09.683521 [CA 0] Center 36 (8~64) winsize 57
5993 11:49:09.684086 [CA 1] Center 36 (8~64) winsize 57
5994 11:49:09.686784 [CA 2] Center 36 (8~64) winsize 57
5995 11:49:09.689816 [CA 3] Center 36 (8~64) winsize 57
5996 11:49:09.693212 [CA 4] Center 36 (8~64) winsize 57
5997 11:49:09.696472 [CA 5] Center 36 (8~64) winsize 57
5998 11:49:09.696961
5999 11:49:09.699911 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6000 11:49:09.700474
6001 11:49:09.703462 [CATrainingPosCal] consider 2 rank data
6002 11:49:09.706478 u2DelayCellTimex100 = 270/100 ps
6003 11:49:09.710114 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6004 11:49:09.716642 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6005 11:49:09.719891 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6006 11:49:09.723232 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6007 11:49:09.726702 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6008 11:49:09.729899 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6009 11:49:09.730468
6010 11:49:09.733185 CA PerBit enable=1, Macro0, CA PI delay=36
6011 11:49:09.733655
6012 11:49:09.736379 [CBTSetCACLKResult] CA Dly = 36
6013 11:49:09.736897 CS Dly: 1 (0~32)
6014 11:49:09.737272
6015 11:49:09.740313 ----->DramcWriteLeveling(PI) begin...
6016 11:49:09.743200 ==
6017 11:49:09.746344 Dram Type= 6, Freq= 0, CH_0, rank 0
6018 11:49:09.749809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6019 11:49:09.750374 ==
6020 11:49:09.752876 Write leveling (Byte 0): 32 => 0
6021 11:49:09.756241 Write leveling (Byte 1): 32 => 0
6022 11:49:09.759462 DramcWriteLeveling(PI) end<-----
6023 11:49:09.759922
6024 11:49:09.760287 ==
6025 11:49:09.762806 Dram Type= 6, Freq= 0, CH_0, rank 0
6026 11:49:09.766746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6027 11:49:09.767323 ==
6028 11:49:09.769640 [Gating] SW mode calibration
6029 11:49:09.777053 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6030 11:49:09.782902 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6031 11:49:09.786226 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6032 11:49:09.789506 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6033 11:49:09.796097 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6034 11:49:09.799724 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6035 11:49:09.802929 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6036 11:49:09.806128 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6037 11:49:09.812630 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6038 11:49:09.816070 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6039 11:49:09.819330 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6040 11:49:09.822710 Total UI for P1: 0, mck2ui 16
6041 11:49:09.826640 best dqsien dly found for B0: ( 0, 10, 16)
6042 11:49:09.829219 Total UI for P1: 0, mck2ui 16
6043 11:49:09.832679 best dqsien dly found for B1: ( 0, 10, 16)
6044 11:49:09.836019 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6045 11:49:09.842532 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6046 11:49:09.843104
6047 11:49:09.845642 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6048 11:49:09.849109 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6049 11:49:09.852637 [Gating] SW calibration Done
6050 11:49:09.853188 ==
6051 11:49:09.855777 Dram Type= 6, Freq= 0, CH_0, rank 0
6052 11:49:09.859196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6053 11:49:09.859664 ==
6054 11:49:09.862485 RX Vref Scan: 0
6055 11:49:09.863060
6056 11:49:09.863434 RX Vref 0 -> 0, step: 1
6057 11:49:09.863784
6058 11:49:09.865364 RX Delay -410 -> 252, step: 16
6059 11:49:09.871920 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6060 11:49:09.875468 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6061 11:49:09.878682 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6062 11:49:09.881987 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6063 11:49:09.888679 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6064 11:49:09.891969 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6065 11:49:09.895449 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6066 11:49:09.898648 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6067 11:49:09.905165 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6068 11:49:09.908581 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6069 11:49:09.911968 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6070 11:49:09.915382 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6071 11:49:09.921679 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6072 11:49:09.925365 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6073 11:49:09.928294 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6074 11:49:09.932267 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6075 11:49:09.935358 ==
6076 11:49:09.938396 Dram Type= 6, Freq= 0, CH_0, rank 0
6077 11:49:09.941728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6078 11:49:09.942309 ==
6079 11:49:09.942801 DQS Delay:
6080 11:49:09.944838 DQS0 = 51, DQS1 = 59
6081 11:49:09.945319 DQM Delay:
6082 11:49:09.947946 DQM0 = 11, DQM1 = 11
6083 11:49:09.948421 DQ Delay:
6084 11:49:09.951270 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6085 11:49:09.954965 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6086 11:49:09.958196 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6087 11:49:09.961311 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6088 11:49:09.961788
6089 11:49:09.962271
6090 11:49:09.962727 ==
6091 11:49:09.964934 Dram Type= 6, Freq= 0, CH_0, rank 0
6092 11:49:09.968091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6093 11:49:09.968618 ==
6094 11:49:09.969120
6095 11:49:09.969592
6096 11:49:09.970979 TX Vref Scan disable
6097 11:49:09.971465 == TX Byte 0 ==
6098 11:49:09.977855 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6099 11:49:09.981006 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6100 11:49:09.981486 == TX Byte 1 ==
6101 11:49:09.987855 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6102 11:49:09.991342 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6103 11:49:09.991903 ==
6104 11:49:09.994702 Dram Type= 6, Freq= 0, CH_0, rank 0
6105 11:49:09.997664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6106 11:49:09.998230 ==
6107 11:49:09.998606
6108 11:49:10.000738
6109 11:49:10.001204 TX Vref Scan disable
6110 11:49:10.004489 == TX Byte 0 ==
6111 11:49:10.007624 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6112 11:49:10.011010 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6113 11:49:10.014319 == TX Byte 1 ==
6114 11:49:10.017205 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6115 11:49:10.021013 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6116 11:49:10.021579
6117 11:49:10.024154 [DATLAT]
6118 11:49:10.024759 Freq=400, CH0 RK0
6119 11:49:10.025141
6120 11:49:10.027623 DATLAT Default: 0xf
6121 11:49:10.028186 0, 0xFFFF, sum = 0
6122 11:49:10.030640 1, 0xFFFF, sum = 0
6123 11:49:10.031201 2, 0xFFFF, sum = 0
6124 11:49:10.033776 3, 0xFFFF, sum = 0
6125 11:49:10.034269 4, 0xFFFF, sum = 0
6126 11:49:10.037158 5, 0xFFFF, sum = 0
6127 11:49:10.037628 6, 0xFFFF, sum = 0
6128 11:49:10.040909 7, 0xFFFF, sum = 0
6129 11:49:10.041798 8, 0xFFFF, sum = 0
6130 11:49:10.043923 9, 0xFFFF, sum = 0
6131 11:49:10.044390 10, 0xFFFF, sum = 0
6132 11:49:10.047032 11, 0xFFFF, sum = 0
6133 11:49:10.047511 12, 0x0, sum = 1
6134 11:49:10.050417 13, 0x0, sum = 2
6135 11:49:10.050996 14, 0x0, sum = 3
6136 11:49:10.053646 15, 0x0, sum = 4
6137 11:49:10.054129 best_step = 13
6138 11:49:10.054504
6139 11:49:10.054854 ==
6140 11:49:10.056976 Dram Type= 6, Freq= 0, CH_0, rank 0
6141 11:49:10.063703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6142 11:49:10.064273 ==
6143 11:49:10.064723 RX Vref Scan: 1
6144 11:49:10.065086
6145 11:49:10.066659 RX Vref 0 -> 0, step: 1
6146 11:49:10.067128
6147 11:49:10.070138 RX Delay -359 -> 252, step: 8
6148 11:49:10.070826
6149 11:49:10.073413 Set Vref, RX VrefLevel [Byte0]: 49
6150 11:49:10.076681 [Byte1]: 49
6151 11:49:10.077152
6152 11:49:10.079996 Final RX Vref Byte 0 = 49 to rank0
6153 11:49:10.083423 Final RX Vref Byte 1 = 49 to rank0
6154 11:49:10.086963 Final RX Vref Byte 0 = 49 to rank1
6155 11:49:10.090201 Final RX Vref Byte 1 = 49 to rank1==
6156 11:49:10.093582 Dram Type= 6, Freq= 0, CH_0, rank 0
6157 11:49:10.100080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6158 11:49:10.100696 ==
6159 11:49:10.101081 DQS Delay:
6160 11:49:10.101424 DQS0 = 52, DQS1 = 68
6161 11:49:10.103255 DQM Delay:
6162 11:49:10.103717 DQM0 = 9, DQM1 = 16
6163 11:49:10.106530 DQ Delay:
6164 11:49:10.106996 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6165 11:49:10.110374 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6166 11:49:10.113428 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6167 11:49:10.116961 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6168 11:49:10.117525
6169 11:49:10.117899
6170 11:49:10.126742 [DQSOSCAuto] RK0, (LSB)MR18= 0xacac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6171 11:49:10.130008 CH0 RK0: MR19=C0C, MR18=ACAC
6172 11:49:10.136726 CH0_RK0: MR19=0xC0C, MR18=0xACAC, DQSOSC=388, MR23=63, INC=392, DEC=261
6173 11:49:10.137292 ==
6174 11:49:10.139848 Dram Type= 6, Freq= 0, CH_0, rank 1
6175 11:49:10.142907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6176 11:49:10.143378 ==
6177 11:49:10.146228 [Gating] SW mode calibration
6178 11:49:10.153124 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6179 11:49:10.156377 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6180 11:49:10.162886 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6181 11:49:10.166266 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6182 11:49:10.169770 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6183 11:49:10.176118 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6184 11:49:10.179359 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6185 11:49:10.182781 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6186 11:49:10.189209 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6187 11:49:10.192626 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6188 11:49:10.196173 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6189 11:49:10.199398 Total UI for P1: 0, mck2ui 16
6190 11:49:10.202388 best dqsien dly found for B0: ( 0, 10, 16)
6191 11:49:10.205833 Total UI for P1: 0, mck2ui 16
6192 11:49:10.208886 best dqsien dly found for B1: ( 0, 10, 24)
6193 11:49:10.212615 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6194 11:49:10.219248 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6195 11:49:10.219826
6196 11:49:10.222484 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6197 11:49:10.225543 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6198 11:49:10.228914 [Gating] SW calibration Done
6199 11:49:10.229494 ==
6200 11:49:10.232209 Dram Type= 6, Freq= 0, CH_0, rank 1
6201 11:49:10.235534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6202 11:49:10.236014 ==
6203 11:49:10.238525 RX Vref Scan: 0
6204 11:49:10.239001
6205 11:49:10.239481 RX Vref 0 -> 0, step: 1
6206 11:49:10.239938
6207 11:49:10.242135 RX Delay -410 -> 252, step: 16
6208 11:49:10.248478 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6209 11:49:10.252020 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6210 11:49:10.255419 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6211 11:49:10.258748 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6212 11:49:10.265223 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6213 11:49:10.268752 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6214 11:49:10.271591 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6215 11:49:10.275336 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6216 11:49:10.281763 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6217 11:49:10.284958 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6218 11:49:10.288475 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6219 11:49:10.291770 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6220 11:49:10.298335 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6221 11:49:10.301693 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6222 11:49:10.305111 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6223 11:49:10.308365 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6224 11:49:10.311854 ==
6225 11:49:10.314786 Dram Type= 6, Freq= 0, CH_0, rank 1
6226 11:49:10.318277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6227 11:49:10.318843 ==
6228 11:49:10.319220 DQS Delay:
6229 11:49:10.321458 DQS0 = 43, DQS1 = 59
6230 11:49:10.321928 DQM Delay:
6231 11:49:10.325050 DQM0 = 7, DQM1 = 14
6232 11:49:10.325612 DQ Delay:
6233 11:49:10.328417 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6234 11:49:10.331472 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6235 11:49:10.334709 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6236 11:49:10.337965 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6237 11:49:10.338534
6238 11:49:10.338909
6239 11:49:10.339253 ==
6240 11:49:10.341111 Dram Type= 6, Freq= 0, CH_0, rank 1
6241 11:49:10.344809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6242 11:49:10.346110 ==
6243 11:49:10.347792
6244 11:49:10.348953
6245 11:49:10.350613 TX Vref Scan disable
6246 11:49:10.351181 == TX Byte 0 ==
6247 11:49:10.354554 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6248 11:49:10.357655 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6249 11:49:10.358122 == TX Byte 1 ==
6250 11:49:10.364192 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6251 11:49:10.367606 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6252 11:49:10.368083 ==
6253 11:49:10.371231 Dram Type= 6, Freq= 0, CH_0, rank 1
6254 11:49:10.374191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6255 11:49:10.374678 ==
6256 11:49:10.375167
6257 11:49:10.375625
6258 11:49:10.377755 TX Vref Scan disable
6259 11:49:10.378233 == TX Byte 0 ==
6260 11:49:10.384312 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6261 11:49:10.387833 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6262 11:49:10.388413 == TX Byte 1 ==
6263 11:49:10.394000 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6264 11:49:10.397567 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6265 11:49:10.398155
6266 11:49:10.398656 [DATLAT]
6267 11:49:10.400642 Freq=400, CH0 RK1
6268 11:49:10.401118
6269 11:49:10.401601 DATLAT Default: 0xd
6270 11:49:10.404260 0, 0xFFFF, sum = 0
6271 11:49:10.404899 1, 0xFFFF, sum = 0
6272 11:49:10.407175 2, 0xFFFF, sum = 0
6273 11:49:10.407660 3, 0xFFFF, sum = 0
6274 11:49:10.410778 4, 0xFFFF, sum = 0
6275 11:49:10.411357 5, 0xFFFF, sum = 0
6276 11:49:10.413727 6, 0xFFFF, sum = 0
6277 11:49:10.414214 7, 0xFFFF, sum = 0
6278 11:49:10.417100 8, 0xFFFF, sum = 0
6279 11:49:10.420680 9, 0xFFFF, sum = 0
6280 11:49:10.421263 10, 0xFFFF, sum = 0
6281 11:49:10.424017 11, 0xFFFF, sum = 0
6282 11:49:10.424653 12, 0x0, sum = 1
6283 11:49:10.427118 13, 0x0, sum = 2
6284 11:49:10.427697 14, 0x0, sum = 3
6285 11:49:10.430599 15, 0x0, sum = 4
6286 11:49:10.431166 best_step = 13
6287 11:49:10.431539
6288 11:49:10.431878 ==
6289 11:49:10.433425 Dram Type= 6, Freq= 0, CH_0, rank 1
6290 11:49:10.436951 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6291 11:49:10.437414 ==
6292 11:49:10.440256 RX Vref Scan: 0
6293 11:49:10.440707
6294 11:49:10.443271 RX Vref 0 -> 0, step: 1
6295 11:49:10.443723
6296 11:49:10.444083 RX Delay -359 -> 252, step: 8
6297 11:49:10.452101 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6298 11:49:10.455722 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6299 11:49:10.458845 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6300 11:49:10.462292 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6301 11:49:10.468740 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6302 11:49:10.472023 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6303 11:49:10.475485 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6304 11:49:10.478857 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6305 11:49:10.485218 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6306 11:49:10.488655 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6307 11:49:10.492113 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6308 11:49:10.498844 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6309 11:49:10.502219 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6310 11:49:10.505269 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6311 11:49:10.508612 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6312 11:49:10.515607 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6313 11:49:10.516164 ==
6314 11:49:10.518646 Dram Type= 6, Freq= 0, CH_0, rank 1
6315 11:49:10.521880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6316 11:49:10.522442 ==
6317 11:49:10.522811 DQS Delay:
6318 11:49:10.525359 DQS0 = 52, DQS1 = 64
6319 11:49:10.525915 DQM Delay:
6320 11:49:10.528441 DQM0 = 10, DQM1 = 14
6321 11:49:10.528925 DQ Delay:
6322 11:49:10.531949 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6323 11:49:10.535056 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6324 11:49:10.538642 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6325 11:49:10.541842 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6326 11:49:10.542403
6327 11:49:10.542773
6328 11:49:10.548640 [DQSOSCAuto] RK1, (LSB)MR18= 0xb6b6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6329 11:49:10.551655 CH0 RK1: MR19=C0C, MR18=B6B6
6330 11:49:10.558318 CH0_RK1: MR19=0xC0C, MR18=0xB6B6, DQSOSC=387, MR23=63, INC=394, DEC=262
6331 11:49:10.561912 [RxdqsGatingPostProcess] freq 400
6332 11:49:10.568645 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6333 11:49:10.571518 Pre-setting of DQS Precalculation
6334 11:49:10.574689 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6335 11:49:10.575148 ==
6336 11:49:10.578038 Dram Type= 6, Freq= 0, CH_1, rank 0
6337 11:49:10.581790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6338 11:49:10.582348 ==
6339 11:49:10.588585 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6340 11:49:10.594829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6341 11:49:10.598439 [CA 0] Center 36 (8~64) winsize 57
6342 11:49:10.601298 [CA 1] Center 36 (8~64) winsize 57
6343 11:49:10.605141 [CA 2] Center 36 (8~64) winsize 57
6344 11:49:10.608258 [CA 3] Center 36 (8~64) winsize 57
6345 11:49:10.611206 [CA 4] Center 36 (8~64) winsize 57
6346 11:49:10.611668 [CA 5] Center 36 (8~64) winsize 57
6347 11:49:10.612102
6348 11:49:10.618115 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6349 11:49:10.618682
6350 11:49:10.621596 [CATrainingPosCal] consider 1 rank data
6351 11:49:10.624606 u2DelayCellTimex100 = 270/100 ps
6352 11:49:10.628137 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6353 11:49:10.631382 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6354 11:49:10.634768 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6355 11:49:10.638050 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6356 11:49:10.641244 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 11:49:10.644568 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 11:49:10.645034
6359 11:49:10.648082 CA PerBit enable=1, Macro0, CA PI delay=36
6360 11:49:10.648704
6361 11:49:10.650998 [CBTSetCACLKResult] CA Dly = 36
6362 11:49:10.654489 CS Dly: 1 (0~32)
6363 11:49:10.655053 ==
6364 11:49:10.657558 Dram Type= 6, Freq= 0, CH_1, rank 1
6365 11:49:10.661004 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6366 11:49:10.661513 ==
6367 11:49:10.667835 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6368 11:49:10.674039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6369 11:49:10.677624 [CA 0] Center 36 (8~64) winsize 57
6370 11:49:10.678101 [CA 1] Center 36 (8~64) winsize 57
6371 11:49:10.680840 [CA 2] Center 36 (8~64) winsize 57
6372 11:49:10.684035 [CA 3] Center 36 (8~64) winsize 57
6373 11:49:10.687561 [CA 4] Center 36 (8~64) winsize 57
6374 11:49:10.690919 [CA 5] Center 36 (8~64) winsize 57
6375 11:49:10.691472
6376 11:49:10.694137 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6377 11:49:10.694703
6378 11:49:10.700843 [CATrainingPosCal] consider 2 rank data
6379 11:49:10.701406 u2DelayCellTimex100 = 270/100 ps
6380 11:49:10.707426 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6381 11:49:10.710610 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6382 11:49:10.714086 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6383 11:49:10.717267 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6384 11:49:10.720881 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6385 11:49:10.724118 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6386 11:49:10.724709
6387 11:49:10.727111 CA PerBit enable=1, Macro0, CA PI delay=36
6388 11:49:10.727662
6389 11:49:10.730223 [CBTSetCACLKResult] CA Dly = 36
6390 11:49:10.733632 CS Dly: 1 (0~32)
6391 11:49:10.734189
6392 11:49:10.737039 ----->DramcWriteLeveling(PI) begin...
6393 11:49:10.737599 ==
6394 11:49:10.740067 Dram Type= 6, Freq= 0, CH_1, rank 0
6395 11:49:10.743600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6396 11:49:10.744162 ==
6397 11:49:10.746879 Write leveling (Byte 0): 32 => 0
6398 11:49:10.750284 Write leveling (Byte 1): 32 => 0
6399 11:49:10.753382 DramcWriteLeveling(PI) end<-----
6400 11:49:10.753845
6401 11:49:10.754208 ==
6402 11:49:10.756884 Dram Type= 6, Freq= 0, CH_1, rank 0
6403 11:49:10.760029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6404 11:49:10.760492 ==
6405 11:49:10.763483 [Gating] SW mode calibration
6406 11:49:10.770574 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6407 11:49:10.776697 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6408 11:49:10.780222 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6409 11:49:10.783089 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6410 11:49:10.790080 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 11:49:10.793108 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6412 11:49:10.796259 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 11:49:10.803246 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 11:49:10.806405 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 11:49:10.809680 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6416 11:49:10.816349 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 11:49:10.816970 Total UI for P1: 0, mck2ui 16
6418 11:49:10.822944 best dqsien dly found for B0: ( 0, 10, 16)
6419 11:49:10.823506 Total UI for P1: 0, mck2ui 16
6420 11:49:10.829519 best dqsien dly found for B1: ( 0, 10, 16)
6421 11:49:10.833040 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6422 11:49:10.835892 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6423 11:49:10.836358
6424 11:49:10.839468 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6425 11:49:10.842946 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6426 11:49:10.846050 [Gating] SW calibration Done
6427 11:49:10.846608 ==
6428 11:49:10.849158 Dram Type= 6, Freq= 0, CH_1, rank 0
6429 11:49:10.852571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6430 11:49:10.853042 ==
6431 11:49:10.856063 RX Vref Scan: 0
6432 11:49:10.856665
6433 11:49:10.859364 RX Vref 0 -> 0, step: 1
6434 11:49:10.859921
6435 11:49:10.860292 RX Delay -410 -> 252, step: 16
6436 11:49:10.865806 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6437 11:49:10.869255 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6438 11:49:10.872555 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6439 11:49:10.875566 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6440 11:49:10.882588 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6441 11:49:10.885822 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6442 11:49:10.889234 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6443 11:49:10.892616 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6444 11:49:10.899183 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6445 11:49:10.902505 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6446 11:49:10.905563 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6447 11:49:10.912142 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6448 11:49:10.915793 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6449 11:49:10.919072 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6450 11:49:10.922280 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6451 11:49:10.929165 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6452 11:49:10.929723 ==
6453 11:49:10.931999 Dram Type= 6, Freq= 0, CH_1, rank 0
6454 11:49:10.935573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6455 11:49:10.936131 ==
6456 11:49:10.936543 DQS Delay:
6457 11:49:10.938655 DQS0 = 43, DQS1 = 59
6458 11:49:10.939208 DQM Delay:
6459 11:49:10.942269 DQM0 = 6, DQM1 = 15
6460 11:49:10.942827 DQ Delay:
6461 11:49:10.945381 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6462 11:49:10.949019 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6463 11:49:10.951883 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6464 11:49:10.954935 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6465 11:49:10.955397
6466 11:49:10.955766
6467 11:49:10.956104 ==
6468 11:49:10.958567 Dram Type= 6, Freq= 0, CH_1, rank 0
6469 11:49:10.961787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6470 11:49:10.962269 ==
6471 11:49:10.962636
6472 11:49:10.962969
6473 11:49:10.965073 TX Vref Scan disable
6474 11:49:10.968321 == TX Byte 0 ==
6475 11:49:10.971905 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6476 11:49:10.974854 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6477 11:49:10.978209 == TX Byte 1 ==
6478 11:49:10.981938 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6479 11:49:10.984944 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6480 11:49:10.985411 ==
6481 11:49:10.987838 Dram Type= 6, Freq= 0, CH_1, rank 0
6482 11:49:10.991581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6483 11:49:10.994656 ==
6484 11:49:10.995218
6485 11:49:10.995584
6486 11:49:10.995918 TX Vref Scan disable
6487 11:49:10.998293 == TX Byte 0 ==
6488 11:49:11.001704 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6489 11:49:11.004783 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6490 11:49:11.008107 == TX Byte 1 ==
6491 11:49:11.011419 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6492 11:49:11.014645 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6493 11:49:11.015218
6494 11:49:11.018025 [DATLAT]
6495 11:49:11.018588 Freq=400, CH1 RK0
6496 11:49:11.018959
6497 11:49:11.021412 DATLAT Default: 0xf
6498 11:49:11.021971 0, 0xFFFF, sum = 0
6499 11:49:11.024459 1, 0xFFFF, sum = 0
6500 11:49:11.025072 2, 0xFFFF, sum = 0
6501 11:49:11.027461 3, 0xFFFF, sum = 0
6502 11:49:11.027930 4, 0xFFFF, sum = 0
6503 11:49:11.031054 5, 0xFFFF, sum = 0
6504 11:49:11.031623 6, 0xFFFF, sum = 0
6505 11:49:11.034453 7, 0xFFFF, sum = 0
6506 11:49:11.035018 8, 0xFFFF, sum = 0
6507 11:49:11.037546 9, 0xFFFF, sum = 0
6508 11:49:11.040923 10, 0xFFFF, sum = 0
6509 11:49:11.041497 11, 0xFFFF, sum = 0
6510 11:49:11.043953 12, 0x0, sum = 1
6511 11:49:11.044420 13, 0x0, sum = 2
6512 11:49:11.047630 14, 0x0, sum = 3
6513 11:49:11.048198 15, 0x0, sum = 4
6514 11:49:11.048636 best_step = 13
6515 11:49:11.049005
6516 11:49:11.050509 ==
6517 11:49:11.054074 Dram Type= 6, Freq= 0, CH_1, rank 0
6518 11:49:11.057705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6519 11:49:11.058273 ==
6520 11:49:11.058648 RX Vref Scan: 1
6521 11:49:11.058991
6522 11:49:11.060559 RX Vref 0 -> 0, step: 1
6523 11:49:11.061117
6524 11:49:11.064141 RX Delay -359 -> 252, step: 8
6525 11:49:11.064645
6526 11:49:11.067383 Set Vref, RX VrefLevel [Byte0]: 54
6527 11:49:11.070566 [Byte1]: 50
6528 11:49:11.074307
6529 11:49:11.074771 Final RX Vref Byte 0 = 54 to rank0
6530 11:49:11.077490 Final RX Vref Byte 1 = 50 to rank0
6531 11:49:11.080887 Final RX Vref Byte 0 = 54 to rank1
6532 11:49:11.084343 Final RX Vref Byte 1 = 50 to rank1==
6533 11:49:11.087634 Dram Type= 6, Freq= 0, CH_1, rank 0
6534 11:49:11.094394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6535 11:49:11.094959 ==
6536 11:49:11.095330 DQS Delay:
6537 11:49:11.097422 DQS0 = 48, DQS1 = 64
6538 11:49:11.097883 DQM Delay:
6539 11:49:11.098250 DQM0 = 8, DQM1 = 16
6540 11:49:11.100680 DQ Delay:
6541 11:49:11.103899 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
6542 11:49:11.104365 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6543 11:49:11.107341 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6544 11:49:11.110624 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6545 11:49:11.111086
6546 11:49:11.111453
6547 11:49:11.120494 [DQSOSCAuto] RK0, (LSB)MR18= 0xdfdf, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6548 11:49:11.123771 CH1 RK0: MR19=C0C, MR18=DFDF
6549 11:49:11.130622 CH1_RK0: MR19=0xC0C, MR18=0xDFDF, DQSOSC=382, MR23=63, INC=404, DEC=269
6550 11:49:11.131191 ==
6551 11:49:11.134248 Dram Type= 6, Freq= 0, CH_1, rank 1
6552 11:49:11.137413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6553 11:49:11.137978 ==
6554 11:49:11.140318 [Gating] SW mode calibration
6555 11:49:11.147213 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6556 11:49:11.153642 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6557 11:49:11.156884 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6558 11:49:11.160819 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6559 11:49:11.167014 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6560 11:49:11.170319 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6561 11:49:11.173478 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6562 11:49:11.180230 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6563 11:49:11.183659 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6564 11:49:11.186923 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6565 11:49:11.189990 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6566 11:49:11.193321 Total UI for P1: 0, mck2ui 16
6567 11:49:11.196562 best dqsien dly found for B0: ( 0, 10, 16)
6568 11:49:11.200051 Total UI for P1: 0, mck2ui 16
6569 11:49:11.203799 best dqsien dly found for B1: ( 0, 10, 16)
6570 11:49:11.206740 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6571 11:49:11.213336 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6572 11:49:11.213897
6573 11:49:11.216956 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6574 11:49:11.219810 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6575 11:49:11.223145 [Gating] SW calibration Done
6576 11:49:11.223727 ==
6577 11:49:11.226306 Dram Type= 6, Freq= 0, CH_1, rank 1
6578 11:49:11.229844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6579 11:49:11.230413 ==
6580 11:49:11.232949 RX Vref Scan: 0
6581 11:49:11.233507
6582 11:49:11.233875 RX Vref 0 -> 0, step: 1
6583 11:49:11.234216
6584 11:49:11.236361 RX Delay -410 -> 252, step: 16
6585 11:49:11.243056 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6586 11:49:11.246554 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6587 11:49:11.249729 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6588 11:49:11.252913 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6589 11:49:11.259519 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6590 11:49:11.262436 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6591 11:49:11.266085 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6592 11:49:11.269367 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6593 11:49:11.275860 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6594 11:49:11.279469 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6595 11:49:11.282588 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6596 11:49:11.285738 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6597 11:49:11.292734 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6598 11:49:11.295887 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6599 11:49:11.299190 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6600 11:49:11.305860 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6601 11:49:11.306436 ==
6602 11:49:11.308910 Dram Type= 6, Freq= 0, CH_1, rank 1
6603 11:49:11.312374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6604 11:49:11.313007 ==
6605 11:49:11.313501 DQS Delay:
6606 11:49:11.315940 DQS0 = 43, DQS1 = 59
6607 11:49:11.316557 DQM Delay:
6608 11:49:11.319043 DQM0 = 9, DQM1 = 17
6609 11:49:11.319533 DQ Delay:
6610 11:49:11.322275 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6611 11:49:11.325744 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6612 11:49:11.329231 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6613 11:49:11.332608 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6614 11:49:11.333181
6615 11:49:11.333673
6616 11:49:11.334128 ==
6617 11:49:11.335542 Dram Type= 6, Freq= 0, CH_1, rank 1
6618 11:49:11.339088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6619 11:49:11.339665 ==
6620 11:49:11.340153
6621 11:49:11.340656
6622 11:49:11.342093 TX Vref Scan disable
6623 11:49:11.342565 == TX Byte 0 ==
6624 11:49:11.348918 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6625 11:49:11.352078 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6626 11:49:11.352587 == TX Byte 1 ==
6627 11:49:11.358798 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6628 11:49:11.362026 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6629 11:49:11.362508 ==
6630 11:49:11.365722 Dram Type= 6, Freq= 0, CH_1, rank 1
6631 11:49:11.368929 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6632 11:49:11.369508 ==
6633 11:49:11.369997
6634 11:49:11.370453
6635 11:49:11.371941 TX Vref Scan disable
6636 11:49:11.372416 == TX Byte 0 ==
6637 11:49:11.378603 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6638 11:49:11.382136 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6639 11:49:11.382713 == TX Byte 1 ==
6640 11:49:11.389096 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6641 11:49:11.392120 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6642 11:49:11.392746
6643 11:49:11.393237 [DATLAT]
6644 11:49:11.395142 Freq=400, CH1 RK1
6645 11:49:11.395618
6646 11:49:11.396097 DATLAT Default: 0xd
6647 11:49:11.398872 0, 0xFFFF, sum = 0
6648 11:49:11.399458 1, 0xFFFF, sum = 0
6649 11:49:11.401975 2, 0xFFFF, sum = 0
6650 11:49:11.402562 3, 0xFFFF, sum = 0
6651 11:49:11.405437 4, 0xFFFF, sum = 0
6652 11:49:11.406022 5, 0xFFFF, sum = 0
6653 11:49:11.408343 6, 0xFFFF, sum = 0
6654 11:49:11.408876 7, 0xFFFF, sum = 0
6655 11:49:11.412131 8, 0xFFFF, sum = 0
6656 11:49:11.412758 9, 0xFFFF, sum = 0
6657 11:49:11.415295 10, 0xFFFF, sum = 0
6658 11:49:11.415885 11, 0xFFFF, sum = 0
6659 11:49:11.418463 12, 0x0, sum = 1
6660 11:49:11.418946 13, 0x0, sum = 2
6661 11:49:11.421952 14, 0x0, sum = 3
6662 11:49:11.422542 15, 0x0, sum = 4
6663 11:49:11.425141 best_step = 13
6664 11:49:11.425619
6665 11:49:11.426099 ==
6666 11:49:11.428836 Dram Type= 6, Freq= 0, CH_1, rank 1
6667 11:49:11.431709 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6668 11:49:11.432283 ==
6669 11:49:11.434999 RX Vref Scan: 0
6670 11:49:11.435572
6671 11:49:11.436056 RX Vref 0 -> 0, step: 1
6672 11:49:11.436546
6673 11:49:11.438395 RX Delay -359 -> 252, step: 8
6674 11:49:11.446911 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6675 11:49:11.450066 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6676 11:49:11.453327 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6677 11:49:11.456876 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6678 11:49:11.463297 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6679 11:49:11.466336 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6680 11:49:11.469926 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6681 11:49:11.473376 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6682 11:49:11.479617 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6683 11:49:11.483506 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6684 11:49:11.486389 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6685 11:49:11.490284 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6686 11:49:11.496712 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6687 11:49:11.499910 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6688 11:49:11.503482 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6689 11:49:11.509831 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6690 11:49:11.510478 ==
6691 11:49:11.513204 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 11:49:11.516464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6693 11:49:11.517089 ==
6694 11:49:11.517587 DQS Delay:
6695 11:49:11.519768 DQS0 = 48, DQS1 = 64
6696 11:49:11.520357 DQM Delay:
6697 11:49:11.522996 DQM0 = 9, DQM1 = 15
6698 11:49:11.523570 DQ Delay:
6699 11:49:11.526635 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6700 11:49:11.529787 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6701 11:49:11.532912 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6702 11:49:11.536232 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6703 11:49:11.536856
6704 11:49:11.537346
6705 11:49:11.542881 [DQSOSCAuto] RK1, (LSB)MR18= 0xabab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6706 11:49:11.546163 CH1 RK1: MR19=C0C, MR18=ABAB
6707 11:49:11.553032 CH1_RK1: MR19=0xC0C, MR18=0xABAB, DQSOSC=388, MR23=63, INC=392, DEC=261
6708 11:49:11.556038 [RxdqsGatingPostProcess] freq 400
6709 11:49:11.562541 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6710 11:49:11.563109 Pre-setting of DQS Precalculation
6711 11:49:11.569380 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6712 11:49:11.575967 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6713 11:49:11.582360 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6714 11:49:11.582930
6715 11:49:11.583415
6716 11:49:11.585716 [Calibration Summary] 800 Mbps
6717 11:49:11.589111 CH 0, Rank 0
6718 11:49:11.589585 SW Impedance : PASS
6719 11:49:11.592626 DUTY Scan : NO K
6720 11:49:11.595947 ZQ Calibration : PASS
6721 11:49:11.596550 Jitter Meter : NO K
6722 11:49:11.599117 CBT Training : PASS
6723 11:49:11.602455 Write leveling : PASS
6724 11:49:11.603023 RX DQS gating : PASS
6725 11:49:11.605453 RX DQ/DQS(RDDQC) : PASS
6726 11:49:11.605930 TX DQ/DQS : PASS
6727 11:49:11.608873 RX DATLAT : PASS
6728 11:49:11.612617 RX DQ/DQS(Engine): PASS
6729 11:49:11.613192 TX OE : NO K
6730 11:49:11.615643 All Pass.
6731 11:49:11.616208
6732 11:49:11.616776 CH 0, Rank 1
6733 11:49:11.619080 SW Impedance : PASS
6734 11:49:11.619653 DUTY Scan : NO K
6735 11:49:11.622197 ZQ Calibration : PASS
6736 11:49:11.625559 Jitter Meter : NO K
6737 11:49:11.626125 CBT Training : PASS
6738 11:49:11.629038 Write leveling : NO K
6739 11:49:11.632486 RX DQS gating : PASS
6740 11:49:11.633110 RX DQ/DQS(RDDQC) : PASS
6741 11:49:11.635435 TX DQ/DQS : PASS
6742 11:49:11.638781 RX DATLAT : PASS
6743 11:49:11.639348 RX DQ/DQS(Engine): PASS
6744 11:49:11.642081 TX OE : NO K
6745 11:49:11.642653 All Pass.
6746 11:49:11.643141
6747 11:49:11.645142 CH 1, Rank 0
6748 11:49:11.645613 SW Impedance : PASS
6749 11:49:11.648774 DUTY Scan : NO K
6750 11:49:11.652084 ZQ Calibration : PASS
6751 11:49:11.652704 Jitter Meter : NO K
6752 11:49:11.655322 CBT Training : PASS
6753 11:49:11.658744 Write leveling : PASS
6754 11:49:11.659219 RX DQS gating : PASS
6755 11:49:11.661799 RX DQ/DQS(RDDQC) : PASS
6756 11:49:11.664954 TX DQ/DQS : PASS
6757 11:49:11.665436 RX DATLAT : PASS
6758 11:49:11.668419 RX DQ/DQS(Engine): PASS
6759 11:49:11.669037 TX OE : NO K
6760 11:49:11.671869 All Pass.
6761 11:49:11.672440
6762 11:49:11.672980 CH 1, Rank 1
6763 11:49:11.674994 SW Impedance : PASS
6764 11:49:11.678242 DUTY Scan : NO K
6765 11:49:11.678717 ZQ Calibration : PASS
6766 11:49:11.681460 Jitter Meter : NO K
6767 11:49:11.681926 CBT Training : PASS
6768 11:49:11.684494 Write leveling : NO K
6769 11:49:11.688119 RX DQS gating : PASS
6770 11:49:11.688622 RX DQ/DQS(RDDQC) : PASS
6771 11:49:11.691546 TX DQ/DQS : PASS
6772 11:49:11.694829 RX DATLAT : PASS
6773 11:49:11.695387 RX DQ/DQS(Engine): PASS
6774 11:49:11.698260 TX OE : NO K
6775 11:49:11.698832 All Pass.
6776 11:49:11.699203
6777 11:49:11.701203 DramC Write-DBI off
6778 11:49:11.704783 PER_BANK_REFRESH: Hybrid Mode
6779 11:49:11.705343 TX_TRACKING: ON
6780 11:49:11.714689 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6781 11:49:11.717892 [FAST_K] Save calibration result to emmc
6782 11:49:11.721240 dramc_set_vcore_voltage set vcore to 725000
6783 11:49:11.724341 Read voltage for 1600, 0
6784 11:49:11.724847 Vio18 = 0
6785 11:49:11.725213 Vcore = 725000
6786 11:49:11.727601 Vdram = 0
6787 11:49:11.728064 Vddq = 0
6788 11:49:11.728427 Vmddr = 0
6789 11:49:11.734685 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6790 11:49:11.737835 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6791 11:49:11.740938 MEM_TYPE=3, freq_sel=13
6792 11:49:11.744369 sv_algorithm_assistance_LP4_3733
6793 11:49:11.747992 ============ PULL DRAM RESETB DOWN ============
6794 11:49:11.754209 ========== PULL DRAM RESETB DOWN end =========
6795 11:49:11.757521 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6796 11:49:11.760811 ===================================
6797 11:49:11.764224 LPDDR4 DRAM CONFIGURATION
6798 11:49:11.767573 ===================================
6799 11:49:11.768125 EX_ROW_EN[0] = 0x0
6800 11:49:11.770712 EX_ROW_EN[1] = 0x0
6801 11:49:11.771170 LP4Y_EN = 0x0
6802 11:49:11.774368 WORK_FSP = 0x1
6803 11:49:11.774829 WL = 0x5
6804 11:49:11.777409 RL = 0x5
6805 11:49:11.777870 BL = 0x2
6806 11:49:11.780623 RPST = 0x0
6807 11:49:11.783680 RD_PRE = 0x0
6808 11:49:11.784160 WR_PRE = 0x1
6809 11:49:11.787556 WR_PST = 0x1
6810 11:49:11.788132 DBI_WR = 0x0
6811 11:49:11.790605 DBI_RD = 0x0
6812 11:49:11.791079 OTF = 0x1
6813 11:49:11.794012 ===================================
6814 11:49:11.797093 ===================================
6815 11:49:11.801182 ANA top config
6816 11:49:11.803947 ===================================
6817 11:49:11.804562 DLL_ASYNC_EN = 0
6818 11:49:11.807505 ALL_SLAVE_EN = 0
6819 11:49:11.810413 NEW_RANK_MODE = 1
6820 11:49:11.813845 DLL_IDLE_MODE = 1
6821 11:49:11.814425 LP45_APHY_COMB_EN = 1
6822 11:49:11.817442 TX_ODT_DIS = 0
6823 11:49:11.820638 NEW_8X_MODE = 1
6824 11:49:11.823830 ===================================
6825 11:49:11.827354 ===================================
6826 11:49:11.830570 data_rate = 3200
6827 11:49:11.833906 CKR = 1
6828 11:49:11.837186 DQ_P2S_RATIO = 8
6829 11:49:11.840249 ===================================
6830 11:49:11.840878 CA_P2S_RATIO = 8
6831 11:49:11.843656 DQ_CA_OPEN = 0
6832 11:49:11.846830 DQ_SEMI_OPEN = 0
6833 11:49:11.849924 CA_SEMI_OPEN = 0
6834 11:49:11.853588 CA_FULL_RATE = 0
6835 11:49:11.856655 DQ_CKDIV4_EN = 0
6836 11:49:11.857131 CA_CKDIV4_EN = 0
6837 11:49:11.860056 CA_PREDIV_EN = 0
6838 11:49:11.863384 PH8_DLY = 12
6839 11:49:11.866783 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6840 11:49:11.869873 DQ_AAMCK_DIV = 4
6841 11:49:11.873737 CA_AAMCK_DIV = 4
6842 11:49:11.874324 CA_ADMCK_DIV = 4
6843 11:49:11.876452 DQ_TRACK_CA_EN = 0
6844 11:49:11.879716 CA_PICK = 1600
6845 11:49:11.882929 CA_MCKIO = 1600
6846 11:49:11.886221 MCKIO_SEMI = 0
6847 11:49:11.889851 PLL_FREQ = 3068
6848 11:49:11.892972 DQ_UI_PI_RATIO = 32
6849 11:49:11.896420 CA_UI_PI_RATIO = 0
6850 11:49:11.899756 ===================================
6851 11:49:11.903119 ===================================
6852 11:49:11.903713 memory_type:LPDDR4
6853 11:49:11.906088 GP_NUM : 10
6854 11:49:11.909239 SRAM_EN : 1
6855 11:49:11.909705 MD32_EN : 0
6856 11:49:11.912825 ===================================
6857 11:49:11.915865 [ANA_INIT] >>>>>>>>>>>>>>
6858 11:49:11.919407 <<<<<< [CONFIGURE PHASE]: ANA_TX
6859 11:49:11.922842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6860 11:49:11.926260 ===================================
6861 11:49:11.929270 data_rate = 3200,PCW = 0X7600
6862 11:49:11.932890 ===================================
6863 11:49:11.935987 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6864 11:49:11.939462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6865 11:49:11.945865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6866 11:49:11.949241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6867 11:49:11.952810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6868 11:49:11.955614 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6869 11:49:11.958863 [ANA_INIT] flow start
6870 11:49:11.962315 [ANA_INIT] PLL >>>>>>>>
6871 11:49:11.962883 [ANA_INIT] PLL <<<<<<<<
6872 11:49:11.965353 [ANA_INIT] MIDPI >>>>>>>>
6873 11:49:11.968857 [ANA_INIT] MIDPI <<<<<<<<
6874 11:49:11.972399 [ANA_INIT] DLL >>>>>>>>
6875 11:49:11.973009 [ANA_INIT] DLL <<<<<<<<
6876 11:49:11.975412 [ANA_INIT] flow end
6877 11:49:11.978767 ============ LP4 DIFF to SE enter ============
6878 11:49:11.982085 ============ LP4 DIFF to SE exit ============
6879 11:49:11.985203 [ANA_INIT] <<<<<<<<<<<<<
6880 11:49:11.988465 [Flow] Enable top DCM control >>>>>
6881 11:49:11.992038 [Flow] Enable top DCM control <<<<<
6882 11:49:11.995729 Enable DLL master slave shuffle
6883 11:49:12.001989 ==============================================================
6884 11:49:12.002565 Gating Mode config
6885 11:49:12.008604 ==============================================================
6886 11:49:12.009181 Config description:
6887 11:49:12.018759 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6888 11:49:12.025210 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6889 11:49:12.031920 SELPH_MODE 0: By rank 1: By Phase
6890 11:49:12.035044 ==============================================================
6891 11:49:12.038407 GAT_TRACK_EN = 1
6892 11:49:12.041729 RX_GATING_MODE = 2
6893 11:49:12.045168 RX_GATING_TRACK_MODE = 2
6894 11:49:12.048425 SELPH_MODE = 1
6895 11:49:12.051399 PICG_EARLY_EN = 1
6896 11:49:12.054654 VALID_LAT_VALUE = 1
6897 11:49:12.061458 ==============================================================
6898 11:49:12.064631 Enter into Gating configuration >>>>
6899 11:49:12.068457 Exit from Gating configuration <<<<
6900 11:49:12.069076 Enter into DVFS_PRE_config >>>>>
6901 11:49:12.081468 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6902 11:49:12.084824 Exit from DVFS_PRE_config <<<<<
6903 11:49:12.087978 Enter into PICG configuration >>>>
6904 11:49:12.091666 Exit from PICG configuration <<<<
6905 11:49:12.092272 [RX_INPUT] configuration >>>>>
6906 11:49:12.094906 [RX_INPUT] configuration <<<<<
6907 11:49:12.101311 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6908 11:49:12.104766 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6909 11:49:12.111469 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6910 11:49:12.118043 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6911 11:49:12.124735 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6912 11:49:12.131389 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6913 11:49:12.134721 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6914 11:49:12.138025 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6915 11:49:12.144770 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6916 11:49:12.148207 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6917 11:49:12.151491 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6918 11:49:12.154376 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6919 11:49:12.157789 ===================================
6920 11:49:12.161325 LPDDR4 DRAM CONFIGURATION
6921 11:49:12.164376 ===================================
6922 11:49:12.167969 EX_ROW_EN[0] = 0x0
6923 11:49:12.168586 EX_ROW_EN[1] = 0x0
6924 11:49:12.171102 LP4Y_EN = 0x0
6925 11:49:12.171678 WORK_FSP = 0x1
6926 11:49:12.174409 WL = 0x5
6927 11:49:12.174986 RL = 0x5
6928 11:49:12.177639 BL = 0x2
6929 11:49:12.178215 RPST = 0x0
6930 11:49:12.181134 RD_PRE = 0x0
6931 11:49:12.181733 WR_PRE = 0x1
6932 11:49:12.184128 WR_PST = 0x1
6933 11:49:12.187453 DBI_WR = 0x0
6934 11:49:12.187931 DBI_RD = 0x0
6935 11:49:12.190841 OTF = 0x1
6936 11:49:12.194581 ===================================
6937 11:49:12.197407 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6938 11:49:12.200815 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6939 11:49:12.204064 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6940 11:49:12.207630 ===================================
6941 11:49:12.210626 LPDDR4 DRAM CONFIGURATION
6942 11:49:12.214059 ===================================
6943 11:49:12.217468 EX_ROW_EN[0] = 0x10
6944 11:49:12.218047 EX_ROW_EN[1] = 0x0
6945 11:49:12.220923 LP4Y_EN = 0x0
6946 11:49:12.221503 WORK_FSP = 0x1
6947 11:49:12.223990 WL = 0x5
6948 11:49:12.224596 RL = 0x5
6949 11:49:12.227283 BL = 0x2
6950 11:49:12.227857 RPST = 0x0
6951 11:49:12.230786 RD_PRE = 0x0
6952 11:49:12.231363 WR_PRE = 0x1
6953 11:49:12.233985 WR_PST = 0x1
6954 11:49:12.234559 DBI_WR = 0x0
6955 11:49:12.237247 DBI_RD = 0x0
6956 11:49:12.240451 OTF = 0x1
6957 11:49:12.243851 ===================================
6958 11:49:12.247099 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6959 11:49:12.247677 ==
6960 11:49:12.250684 Dram Type= 6, Freq= 0, CH_0, rank 0
6961 11:49:12.257032 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6962 11:49:12.257596 ==
6963 11:49:12.258081 [Duty_Offset_Calibration]
6964 11:49:12.260194 B0:0 B1:2 CA:1
6965 11:49:12.260717
6966 11:49:12.263497 [DutyScan_Calibration_Flow] k_type=0
6967 11:49:12.273511
6968 11:49:12.274086 ==CLK 0==
6969 11:49:12.276679 Final CLK duty delay cell = 0
6970 11:49:12.280176 [0] MAX Duty = 5156%(X100), DQS PI = 22
6971 11:49:12.283331 [0] MIN Duty = 4907%(X100), DQS PI = 54
6972 11:49:12.286463 [0] AVG Duty = 5031%(X100)
6973 11:49:12.286940
6974 11:49:12.289898 CH0 CLK Duty spec in!! Max-Min= 249%
6975 11:49:12.293060 [DutyScan_Calibration_Flow] ====Done====
6976 11:49:12.293540
6977 11:49:12.296406 [DutyScan_Calibration_Flow] k_type=1
6978 11:49:12.313348
6979 11:49:12.313940 ==DQS 0 ==
6980 11:49:12.316856 Final DQS duty delay cell = 0
6981 11:49:12.320139 [0] MAX Duty = 5156%(X100), DQS PI = 34
6982 11:49:12.323584 [0] MIN Duty = 5031%(X100), DQS PI = 8
6983 11:49:12.326617 [0] AVG Duty = 5093%(X100)
6984 11:49:12.327096
6985 11:49:12.327575 ==DQS 1 ==
6986 11:49:12.330203 Final DQS duty delay cell = 0
6987 11:49:12.333088 [0] MAX Duty = 5031%(X100), DQS PI = 0
6988 11:49:12.336477 [0] MIN Duty = 4876%(X100), DQS PI = 18
6989 11:49:12.339890 [0] AVG Duty = 4953%(X100)
6990 11:49:12.340485
6991 11:49:12.343223 CH0 DQS 0 Duty spec in!! Max-Min= 125%
6992 11:49:12.343803
6993 11:49:12.346780 CH0 DQS 1 Duty spec in!! Max-Min= 155%
6994 11:49:12.349813 [DutyScan_Calibration_Flow] ====Done====
6995 11:49:12.350388
6996 11:49:12.352705 [DutyScan_Calibration_Flow] k_type=3
6997 11:49:12.370737
6998 11:49:12.371312 ==DQM 0 ==
6999 11:49:12.373799 Final DQM duty delay cell = 0
7000 11:49:12.376892 [0] MAX Duty = 5187%(X100), DQS PI = 22
7001 11:49:12.380730 [0] MIN Duty = 4907%(X100), DQS PI = 42
7002 11:49:12.383401 [0] AVG Duty = 5047%(X100)
7003 11:49:12.383881
7004 11:49:12.384363 ==DQM 1 ==
7005 11:49:12.386825 Final DQM duty delay cell = 0
7006 11:49:12.390555 [0] MAX Duty = 5031%(X100), DQS PI = 4
7007 11:49:12.393387 [0] MIN Duty = 4782%(X100), DQS PI = 14
7008 11:49:12.397016 [0] AVG Duty = 4906%(X100)
7009 11:49:12.397596
7010 11:49:12.400299 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7011 11:49:12.400934
7012 11:49:12.403740 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7013 11:49:12.406633 [DutyScan_Calibration_Flow] ====Done====
7014 11:49:12.407114
7015 11:49:12.409841 [DutyScan_Calibration_Flow] k_type=2
7016 11:49:12.426941
7017 11:49:12.427546 ==DQ 0 ==
7018 11:49:12.430133 Final DQ duty delay cell = 0
7019 11:49:12.433269 [0] MAX Duty = 5218%(X100), DQS PI = 18
7020 11:49:12.436685 [0] MIN Duty = 4938%(X100), DQS PI = 56
7021 11:49:12.437285 [0] AVG Duty = 5078%(X100)
7022 11:49:12.439983
7023 11:49:12.440590 ==DQ 1 ==
7024 11:49:12.443409 Final DQ duty delay cell = -4
7025 11:49:12.446712 [-4] MAX Duty = 5094%(X100), DQS PI = 6
7026 11:49:12.449996 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7027 11:49:12.453138 [-4] AVG Duty = 4969%(X100)
7028 11:49:12.453616
7029 11:49:12.456229 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7030 11:49:12.456742
7031 11:49:12.459932 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7032 11:49:12.463290 [DutyScan_Calibration_Flow] ====Done====
7033 11:49:12.463867 ==
7034 11:49:12.466811 Dram Type= 6, Freq= 0, CH_1, rank 0
7035 11:49:12.469771 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7036 11:49:12.470354 ==
7037 11:49:12.473391 [Duty_Offset_Calibration]
7038 11:49:12.473968 B0:0 B1:4 CA:-5
7039 11:49:12.474461
7040 11:49:12.476342 [DutyScan_Calibration_Flow] k_type=0
7041 11:49:12.487380
7042 11:49:12.487949 ==CLK 0==
7043 11:49:12.490776 Final CLK duty delay cell = 0
7044 11:49:12.494320 [0] MAX Duty = 5156%(X100), DQS PI = 20
7045 11:49:12.497244 [0] MIN Duty = 4906%(X100), DQS PI = 52
7046 11:49:12.500425 [0] AVG Duty = 5031%(X100)
7047 11:49:12.500937
7048 11:49:12.504018 CH1 CLK Duty spec in!! Max-Min= 250%
7049 11:49:12.507235 [DutyScan_Calibration_Flow] ====Done====
7050 11:49:12.507817
7051 11:49:12.510823 [DutyScan_Calibration_Flow] k_type=1
7052 11:49:12.526265
7053 11:49:12.526835 ==DQS 0 ==
7054 11:49:12.530173 Final DQS duty delay cell = 0
7055 11:49:12.533214 [0] MAX Duty = 5156%(X100), DQS PI = 18
7056 11:49:12.536324 [0] MIN Duty = 4844%(X100), DQS PI = 44
7057 11:49:12.539696 [0] AVG Duty = 5000%(X100)
7058 11:49:12.540274
7059 11:49:12.540813 ==DQS 1 ==
7060 11:49:12.543160 Final DQS duty delay cell = -4
7061 11:49:12.546519 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7062 11:49:12.549533 [-4] MIN Duty = 4844%(X100), DQS PI = 42
7063 11:49:12.552963 [-4] AVG Duty = 4922%(X100)
7064 11:49:12.553543
7065 11:49:12.556086 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7066 11:49:12.556705
7067 11:49:12.559562 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7068 11:49:12.563003 [DutyScan_Calibration_Flow] ====Done====
7069 11:49:12.563584
7070 11:49:12.565953 [DutyScan_Calibration_Flow] k_type=3
7071 11:49:12.582092
7072 11:49:12.582670 ==DQM 0 ==
7073 11:49:12.585233 Final DQM duty delay cell = -4
7074 11:49:12.588494 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7075 11:49:12.592032 [-4] MIN Duty = 4813%(X100), DQS PI = 44
7076 11:49:12.595266 [-4] AVG Duty = 4953%(X100)
7077 11:49:12.595848
7078 11:49:12.596336 ==DQM 1 ==
7079 11:49:12.598820 Final DQM duty delay cell = -4
7080 11:49:12.601796 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7081 11:49:12.605108 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7082 11:49:12.608563 [-4] AVG Duty = 5000%(X100)
7083 11:49:12.609042
7084 11:49:12.612047 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7085 11:49:12.612673
7086 11:49:12.615345 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7087 11:49:12.618831 [DutyScan_Calibration_Flow] ====Done====
7088 11:49:12.619407
7089 11:49:12.621864 [DutyScan_Calibration_Flow] k_type=2
7090 11:49:12.640005
7091 11:49:12.640625 ==DQ 0 ==
7092 11:49:12.643049 Final DQ duty delay cell = 0
7093 11:49:12.646184 [0] MAX Duty = 5093%(X100), DQS PI = 18
7094 11:49:12.649665 [0] MIN Duty = 4969%(X100), DQS PI = 46
7095 11:49:12.650242 [0] AVG Duty = 5031%(X100)
7096 11:49:12.653154
7097 11:49:12.653657 ==DQ 1 ==
7098 11:49:12.656349 Final DQ duty delay cell = 0
7099 11:49:12.659674 [0] MAX Duty = 5031%(X100), DQS PI = 4
7100 11:49:12.662974 [0] MIN Duty = 4907%(X100), DQS PI = 14
7101 11:49:12.663545 [0] AVG Duty = 4969%(X100)
7102 11:49:12.663921
7103 11:49:12.669558 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7104 11:49:12.670138
7105 11:49:12.672869 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7106 11:49:12.676465 [DutyScan_Calibration_Flow] ====Done====
7107 11:49:12.679617 nWR fixed to 30
7108 11:49:12.680189 [ModeRegInit_LP4] CH0 RK0
7109 11:49:12.682736 [ModeRegInit_LP4] CH0 RK1
7110 11:49:12.685869 [ModeRegInit_LP4] CH1 RK0
7111 11:49:12.689146 [ModeRegInit_LP4] CH1 RK1
7112 11:49:12.689611 match AC timing 4
7113 11:49:12.693010 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7114 11:49:12.699533 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7115 11:49:12.702704 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7116 11:49:12.709285 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7117 11:49:12.712461 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7118 11:49:12.713140 [MiockJmeterHQA]
7119 11:49:12.713544
7120 11:49:12.715829 [DramcMiockJmeter] u1RxGatingPI = 0
7121 11:49:12.719334 0 : 4255, 4027
7122 11:49:12.720058 4 : 4255, 4029
7123 11:49:12.723448 8 : 4363, 4138
7124 11:49:12.724075 12 : 4252, 4026
7125 11:49:12.724463 16 : 4253, 4027
7126 11:49:12.725875 20 : 4363, 4137
7127 11:49:12.726350 24 : 4363, 4138
7128 11:49:12.729070 28 : 4252, 4026
7129 11:49:12.729549 32 : 4252, 4027
7130 11:49:12.732323 36 : 4249, 4027
7131 11:49:12.732849 40 : 4363, 4137
7132 11:49:12.735673 44 : 4250, 4027
7133 11:49:12.736159 48 : 4360, 4137
7134 11:49:12.736575 52 : 4252, 4027
7135 11:49:12.739217 56 : 4249, 4027
7136 11:49:12.739801 60 : 4252, 4026
7137 11:49:12.742320 64 : 4252, 4030
7138 11:49:12.742794 68 : 4361, 4137
7139 11:49:12.745966 72 : 4252, 4027
7140 11:49:12.746545 76 : 4361, 4137
7141 11:49:12.746929 80 : 4252, 4026
7142 11:49:12.748936 84 : 4250, 4027
7143 11:49:12.749408 88 : 4250, 4027
7144 11:49:12.752351 92 : 4361, 4137
7145 11:49:12.752952 96 : 4250, 4027
7146 11:49:12.755828 100 : 4361, 2541
7147 11:49:12.756445 104 : 4361, 0
7148 11:49:12.756870 108 : 4361, 0
7149 11:49:12.758985 112 : 4247, 0
7150 11:49:12.759461 116 : 4360, 0
7151 11:49:12.762427 120 : 4360, 0
7152 11:49:12.763004 124 : 4249, 0
7153 11:49:12.763381 128 : 4250, 0
7154 11:49:12.765578 132 : 4250, 0
7155 11:49:12.766051 136 : 4249, 0
7156 11:49:12.768876 140 : 4250, 0
7157 11:49:12.769454 144 : 4250, 0
7158 11:49:12.769834 148 : 4249, 0
7159 11:49:12.772337 152 : 4252, 0
7160 11:49:12.772973 156 : 4250, 0
7161 11:49:12.775813 160 : 4250, 0
7162 11:49:12.776390 164 : 4252, 0
7163 11:49:12.776837 168 : 4250, 0
7164 11:49:12.778947 172 : 4360, 0
7165 11:49:12.779523 176 : 4360, 0
7166 11:49:12.779902 180 : 4250, 0
7167 11:49:12.782182 184 : 4361, 0
7168 11:49:12.782759 188 : 4249, 0
7169 11:49:12.785623 192 : 4250, 0
7170 11:49:12.786315 196 : 4250, 0
7171 11:49:12.786706 200 : 4249, 0
7172 11:49:12.788748 204 : 4252, 0
7173 11:49:12.789223 208 : 4361, 0
7174 11:49:12.792231 212 : 4249, 0
7175 11:49:12.792751 216 : 4250, 0
7176 11:49:12.793136 220 : 4250, 557
7177 11:49:12.795537 224 : 4362, 4115
7178 11:49:12.796010 228 : 4250, 4027
7179 11:49:12.798703 232 : 4250, 4026
7180 11:49:12.799181 236 : 4250, 4027
7181 11:49:12.802077 240 : 4252, 4030
7182 11:49:12.802550 244 : 4249, 4027
7183 11:49:12.805208 248 : 4252, 4026
7184 11:49:12.805683 252 : 4250, 4027
7185 11:49:12.808714 256 : 4252, 4030
7186 11:49:12.809289 260 : 4250, 4026
7187 11:49:12.812007 264 : 4361, 4137
7188 11:49:12.812659 268 : 4361, 4137
7189 11:49:12.815397 272 : 4250, 4027
7190 11:49:12.815973 276 : 4363, 4140
7191 11:49:12.816354 280 : 4361, 4137
7192 11:49:12.818629 284 : 4250, 4026
7193 11:49:12.819202 288 : 4250, 4027
7194 11:49:12.822229 292 : 4252, 4030
7195 11:49:12.822805 296 : 4249, 4027
7196 11:49:12.825127 300 : 4250, 4026
7197 11:49:12.825600 304 : 4250, 4027
7198 11:49:12.828713 308 : 4252, 4030
7199 11:49:12.829286 312 : 4249, 4027
7200 11:49:12.831932 316 : 4361, 4137
7201 11:49:12.832502 320 : 4361, 4137
7202 11:49:12.835442 324 : 4250, 4027
7203 11:49:12.836012 328 : 4363, 4140
7204 11:49:12.838738 332 : 4361, 4137
7205 11:49:12.839308 336 : 4250, 3942
7206 11:49:12.839686 340 : 4250, 2220
7207 11:49:12.841729 344 : 4252, 0
7208 11:49:12.842196
7209 11:49:12.845460 MIOCK jitter meter ch=0
7210 11:49:12.846019
7211 11:49:12.846388 1T = (344-104) = 240 dly cells
7212 11:49:12.851856 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7213 11:49:12.852407 ==
7214 11:49:12.854937 Dram Type= 6, Freq= 0, CH_0, rank 0
7215 11:49:12.858423 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7216 11:49:12.861980 ==
7217 11:49:12.865297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7218 11:49:12.868644 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7219 11:49:12.875456 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7220 11:49:12.881467 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7221 11:49:12.888436 [CA 0] Center 42 (12~73) winsize 62
7222 11:49:12.891714 [CA 1] Center 42 (12~73) winsize 62
7223 11:49:12.894936 [CA 2] Center 39 (9~69) winsize 61
7224 11:49:12.898321 [CA 3] Center 38 (9~68) winsize 60
7225 11:49:12.901303 [CA 4] Center 36 (6~67) winsize 62
7226 11:49:12.904986 [CA 5] Center 36 (6~66) winsize 61
7227 11:49:12.905554
7228 11:49:12.907813 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7229 11:49:12.908292
7230 11:49:12.911472 [CATrainingPosCal] consider 1 rank data
7231 11:49:12.915078 u2DelayCellTimex100 = 271/100 ps
7232 11:49:12.918059 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7233 11:49:12.924887 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7234 11:49:12.928063 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7235 11:49:12.931366 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7236 11:49:12.934759 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
7237 11:49:12.937955 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7238 11:49:12.938517
7239 11:49:12.941463 CA PerBit enable=1, Macro0, CA PI delay=36
7240 11:49:12.942029
7241 11:49:12.944708 [CBTSetCACLKResult] CA Dly = 36
7242 11:49:12.948000 CS Dly: 10 (0~41)
7243 11:49:12.951461 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7244 11:49:12.954250 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7245 11:49:12.954712 ==
7246 11:49:12.957662 Dram Type= 6, Freq= 0, CH_0, rank 1
7247 11:49:12.964327 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7248 11:49:12.964927 ==
7249 11:49:12.967387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7250 11:49:12.970860 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7251 11:49:12.977629 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7252 11:49:12.984050 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7253 11:49:12.991129 [CA 0] Center 42 (12~73) winsize 62
7254 11:49:12.994566 [CA 1] Center 42 (12~73) winsize 62
7255 11:49:12.997971 [CA 2] Center 38 (9~68) winsize 60
7256 11:49:13.000824 [CA 3] Center 37 (8~67) winsize 60
7257 11:49:13.004215 [CA 4] Center 36 (6~66) winsize 61
7258 11:49:13.007609 [CA 5] Center 36 (6~66) winsize 61
7259 11:49:13.008168
7260 11:49:13.010927 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7261 11:49:13.011493
7262 11:49:13.013830 [CATrainingPosCal] consider 2 rank data
7263 11:49:13.017438 u2DelayCellTimex100 = 271/100 ps
7264 11:49:13.020545 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7265 11:49:13.027553 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7266 11:49:13.030748 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7267 11:49:13.034083 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7268 11:49:13.037446 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7269 11:49:13.040600 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7270 11:49:13.041165
7271 11:49:13.043784 CA PerBit enable=1, Macro0, CA PI delay=36
7272 11:49:13.044244
7273 11:49:13.047206 [CBTSetCACLKResult] CA Dly = 36
7274 11:49:13.050769 CS Dly: 10 (0~42)
7275 11:49:13.053691 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7276 11:49:13.057282 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7277 11:49:13.057853
7278 11:49:13.060856 ----->DramcWriteLeveling(PI) begin...
7279 11:49:13.061427 ==
7280 11:49:13.064137 Dram Type= 6, Freq= 0, CH_0, rank 0
7281 11:49:13.070672 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7282 11:49:13.071244 ==
7283 11:49:13.074047 Write leveling (Byte 0): 31 => 31
7284 11:49:13.074637 Write leveling (Byte 1): 25 => 25
7285 11:49:13.077257 DramcWriteLeveling(PI) end<-----
7286 11:49:13.077818
7287 11:49:13.078259 ==
7288 11:49:13.080301 Dram Type= 6, Freq= 0, CH_0, rank 0
7289 11:49:13.087013 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7290 11:49:13.087617 ==
7291 11:49:13.090231 [Gating] SW mode calibration
7292 11:49:13.096815 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7293 11:49:13.100268 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7294 11:49:13.106774 0 12 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7295 11:49:13.110009 0 12 4 | B1->B0 | 2525 3434 | 1 0 | (1 1) (0 0)
7296 11:49:13.113814 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7297 11:49:13.120339 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7298 11:49:13.123905 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7299 11:49:13.127227 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7300 11:49:13.133921 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7301 11:49:13.136955 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7302 11:49:13.140418 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
7303 11:49:13.146854 0 13 4 | B1->B0 | 3030 2424 | 0 0 | (0 1) (1 0)
7304 11:49:13.149951 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7305 11:49:13.153406 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7306 11:49:13.160006 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7307 11:49:13.163257 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7308 11:49:13.166786 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7309 11:49:13.173241 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7310 11:49:13.176460 0 14 0 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
7311 11:49:13.179920 0 14 4 | B1->B0 | 3635 4646 | 1 0 | (1 1) (0 0)
7312 11:49:13.183350 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7313 11:49:13.189811 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7314 11:49:13.193105 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7315 11:49:13.196870 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7316 11:49:13.203085 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7317 11:49:13.206448 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7318 11:49:13.209575 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7319 11:49:13.216285 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7320 11:49:13.219593 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7321 11:49:13.223327 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7322 11:49:13.229901 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7323 11:49:13.232889 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7324 11:49:13.236382 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7325 11:49:13.242907 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7326 11:49:13.246216 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7327 11:49:13.249499 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7328 11:49:13.255979 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7329 11:49:13.259142 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7330 11:49:13.262751 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7331 11:49:13.269379 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7332 11:49:13.272446 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7333 11:49:13.275652 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7334 11:49:13.282763 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7335 11:49:13.285775 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7336 11:49:13.289108 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7337 11:49:13.292191 Total UI for P1: 0, mck2ui 16
7338 11:49:13.295861 best dqsien dly found for B0: ( 1, 1, 0)
7339 11:49:13.299401 Total UI for P1: 0, mck2ui 16
7340 11:49:13.302297 best dqsien dly found for B1: ( 1, 1, 4)
7341 11:49:13.305853 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7342 11:49:13.309211 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7343 11:49:13.309831
7344 11:49:13.312482 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7345 11:49:13.319087 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7346 11:49:13.319645 [Gating] SW calibration Done
7347 11:49:13.320017 ==
7348 11:49:13.322295 Dram Type= 6, Freq= 0, CH_0, rank 0
7349 11:49:13.328736 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7350 11:49:13.329208 ==
7351 11:49:13.329574 RX Vref Scan: 0
7352 11:49:13.329914
7353 11:49:13.332147 RX Vref 0 -> 0, step: 1
7354 11:49:13.332758
7355 11:49:13.335247 RX Delay 0 -> 252, step: 8
7356 11:49:13.338696 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7357 11:49:13.342070 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7358 11:49:13.345282 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7359 11:49:13.351985 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7360 11:49:13.355159 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7361 11:49:13.358432 iDelay=200, Bit 5, Center 119 (56 ~ 183) 128
7362 11:49:13.361851 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7363 11:49:13.365034 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7364 11:49:13.371829 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7365 11:49:13.375369 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7366 11:49:13.378523 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7367 11:49:13.382036 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7368 11:49:13.385264 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7369 11:49:13.391760 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7370 11:49:13.395197 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7371 11:49:13.398872 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7372 11:49:13.399437 ==
7373 11:49:13.401770 Dram Type= 6, Freq= 0, CH_0, rank 0
7374 11:49:13.405312 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7375 11:49:13.405772 ==
7376 11:49:13.408478 DQS Delay:
7377 11:49:13.409232 DQS0 = 0, DQS1 = 0
7378 11:49:13.412019 DQM Delay:
7379 11:49:13.412649 DQM0 = 130, DQM1 = 123
7380 11:49:13.413041 DQ Delay:
7381 11:49:13.418521 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7382 11:49:13.421825 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7383 11:49:13.425154 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
7384 11:49:13.428445 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7385 11:49:13.429040
7386 11:49:13.429407
7387 11:49:13.429747 ==
7388 11:49:13.431550 Dram Type= 6, Freq= 0, CH_0, rank 0
7389 11:49:13.434771 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7390 11:49:13.435342 ==
7391 11:49:13.435709
7392 11:49:13.436050
7393 11:49:13.438387 TX Vref Scan disable
7394 11:49:13.441801 == TX Byte 0 ==
7395 11:49:13.444961 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7396 11:49:13.448353 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7397 11:49:13.451505 == TX Byte 1 ==
7398 11:49:13.454616 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7399 11:49:13.458040 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7400 11:49:13.458505 ==
7401 11:49:13.461460 Dram Type= 6, Freq= 0, CH_0, rank 0
7402 11:49:13.467587 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7403 11:49:13.468136 ==
7404 11:49:13.481106
7405 11:49:13.484305 TX Vref early break, caculate TX vref
7406 11:49:13.487765 TX Vref=16, minBit 8, minWin=22, winSum=370
7407 11:49:13.491120 TX Vref=18, minBit 10, minWin=22, winSum=380
7408 11:49:13.494383 TX Vref=20, minBit 9, minWin=22, winSum=385
7409 11:49:13.497771 TX Vref=22, minBit 8, minWin=24, winSum=399
7410 11:49:13.501040 TX Vref=24, minBit 8, minWin=24, winSum=407
7411 11:49:13.507760 TX Vref=26, minBit 11, minWin=24, winSum=413
7412 11:49:13.511192 TX Vref=28, minBit 1, minWin=25, winSum=407
7413 11:49:13.514558 TX Vref=30, minBit 8, minWin=24, winSum=410
7414 11:49:13.517781 TX Vref=32, minBit 6, minWin=24, winSum=399
7415 11:49:13.520991 TX Vref=34, minBit 1, minWin=24, winSum=393
7416 11:49:13.527411 TX Vref=36, minBit 0, minWin=23, winSum=379
7417 11:49:13.530990 [TxChooseVref] Worse bit 1, Min win 25, Win sum 407, Final Vref 28
7418 11:49:13.531553
7419 11:49:13.533773 Final TX Range 0 Vref 28
7420 11:49:13.534237
7421 11:49:13.534600 ==
7422 11:49:13.537055 Dram Type= 6, Freq= 0, CH_0, rank 0
7423 11:49:13.540591 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7424 11:49:13.543798 ==
7425 11:49:13.544357
7426 11:49:13.544767
7427 11:49:13.545107 TX Vref Scan disable
7428 11:49:13.550853 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7429 11:49:13.551603 == TX Byte 0 ==
7430 11:49:13.553757 u2DelayCellOfst[0]=10 cells (3 PI)
7431 11:49:13.557197 u2DelayCellOfst[1]=14 cells (4 PI)
7432 11:49:13.560604 u2DelayCellOfst[2]=10 cells (3 PI)
7433 11:49:13.563929 u2DelayCellOfst[3]=7 cells (2 PI)
7434 11:49:13.567654 u2DelayCellOfst[4]=3 cells (1 PI)
7435 11:49:13.570471 u2DelayCellOfst[5]=0 cells (0 PI)
7436 11:49:13.573891 u2DelayCellOfst[6]=14 cells (4 PI)
7437 11:49:13.577428 u2DelayCellOfst[7]=14 cells (4 PI)
7438 11:49:13.580306 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7439 11:49:13.583794 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7440 11:49:13.587140 == TX Byte 1 ==
7441 11:49:13.590460 u2DelayCellOfst[8]=3 cells (1 PI)
7442 11:49:13.593965 u2DelayCellOfst[9]=0 cells (0 PI)
7443 11:49:13.596889 u2DelayCellOfst[10]=10 cells (3 PI)
7444 11:49:13.600353 u2DelayCellOfst[11]=3 cells (1 PI)
7445 11:49:13.600973 u2DelayCellOfst[12]=14 cells (4 PI)
7446 11:49:13.603896 u2DelayCellOfst[13]=14 cells (4 PI)
7447 11:49:13.606984 u2DelayCellOfst[14]=18 cells (5 PI)
7448 11:49:13.610051 u2DelayCellOfst[15]=14 cells (4 PI)
7449 11:49:13.616819 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7450 11:49:13.620388 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7451 11:49:13.621031 DramC Write-DBI on
7452 11:49:13.623596 ==
7453 11:49:13.626858 Dram Type= 6, Freq= 0, CH_0, rank 0
7454 11:49:13.629964 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7455 11:49:13.630527 ==
7456 11:49:13.630893
7457 11:49:13.631229
7458 11:49:13.633053 TX Vref Scan disable
7459 11:49:13.633514 == TX Byte 0 ==
7460 11:49:13.640301 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7461 11:49:13.640908 == TX Byte 1 ==
7462 11:49:13.643615 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7463 11:49:13.646463 DramC Write-DBI off
7464 11:49:13.646930
7465 11:49:13.647292 [DATLAT]
7466 11:49:13.650235 Freq=1600, CH0 RK0
7467 11:49:13.650796
7468 11:49:13.651163 DATLAT Default: 0xf
7469 11:49:13.653094 0, 0xFFFF, sum = 0
7470 11:49:13.653564 1, 0xFFFF, sum = 0
7471 11:49:13.656306 2, 0xFFFF, sum = 0
7472 11:49:13.656827 3, 0xFFFF, sum = 0
7473 11:49:13.659623 4, 0xFFFF, sum = 0
7474 11:49:13.662610 5, 0xFFFF, sum = 0
7475 11:49:13.663074 6, 0xFFFF, sum = 0
7476 11:49:13.666012 7, 0xFFFF, sum = 0
7477 11:49:13.666481 8, 0xFFFF, sum = 0
7478 11:49:13.669456 9, 0xFFFF, sum = 0
7479 11:49:13.669924 10, 0xFFFF, sum = 0
7480 11:49:13.672680 11, 0xFFFF, sum = 0
7481 11:49:13.673146 12, 0xFFF, sum = 0
7482 11:49:13.676206 13, 0x0, sum = 1
7483 11:49:13.676825 14, 0x0, sum = 2
7484 11:49:13.679454 15, 0x0, sum = 3
7485 11:49:13.680188 16, 0x0, sum = 4
7486 11:49:13.682709 best_step = 14
7487 11:49:13.683272
7488 11:49:13.683639 ==
7489 11:49:13.686036 Dram Type= 6, Freq= 0, CH_0, rank 0
7490 11:49:13.689276 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7491 11:49:13.689886 ==
7492 11:49:13.690258 RX Vref Scan: 1
7493 11:49:13.692682
7494 11:49:13.693142 Set Vref Range= 24 -> 127
7495 11:49:13.693508
7496 11:49:13.696044 RX Vref 24 -> 127, step: 1
7497 11:49:13.696547
7498 11:49:13.699213 RX Delay 11 -> 252, step: 4
7499 11:49:13.699770
7500 11:49:13.702560 Set Vref, RX VrefLevel [Byte0]: 24
7501 11:49:13.706170 [Byte1]: 24
7502 11:49:13.706633
7503 11:49:13.709219 Set Vref, RX VrefLevel [Byte0]: 25
7504 11:49:13.712539 [Byte1]: 25
7505 11:49:13.713115
7506 11:49:13.715686 Set Vref, RX VrefLevel [Byte0]: 26
7507 11:49:13.719237 [Byte1]: 26
7508 11:49:13.723202
7509 11:49:13.723755 Set Vref, RX VrefLevel [Byte0]: 27
7510 11:49:13.726284 [Byte1]: 27
7511 11:49:13.730990
7512 11:49:13.731542 Set Vref, RX VrefLevel [Byte0]: 28
7513 11:49:13.734102 [Byte1]: 28
7514 11:49:13.738421
7515 11:49:13.738975 Set Vref, RX VrefLevel [Byte0]: 29
7516 11:49:13.741732 [Byte1]: 29
7517 11:49:13.746126
7518 11:49:13.746690 Set Vref, RX VrefLevel [Byte0]: 30
7519 11:49:13.749321 [Byte1]: 30
7520 11:49:13.753482
7521 11:49:13.754037 Set Vref, RX VrefLevel [Byte0]: 31
7522 11:49:13.756979 [Byte1]: 31
7523 11:49:13.761288
7524 11:49:13.761749 Set Vref, RX VrefLevel [Byte0]: 32
7525 11:49:13.764552 [Byte1]: 32
7526 11:49:13.768848
7527 11:49:13.769419 Set Vref, RX VrefLevel [Byte0]: 33
7528 11:49:13.772153 [Byte1]: 33
7529 11:49:13.776434
7530 11:49:13.777044 Set Vref, RX VrefLevel [Byte0]: 34
7531 11:49:13.779804 [Byte1]: 34
7532 11:49:13.784162
7533 11:49:13.784797 Set Vref, RX VrefLevel [Byte0]: 35
7534 11:49:13.787274 [Byte1]: 35
7535 11:49:13.791379
7536 11:49:13.792071 Set Vref, RX VrefLevel [Byte0]: 36
7537 11:49:13.795059 [Byte1]: 36
7538 11:49:13.799169
7539 11:49:13.799724 Set Vref, RX VrefLevel [Byte0]: 37
7540 11:49:13.802732 [Byte1]: 37
7541 11:49:13.806889
7542 11:49:13.807440 Set Vref, RX VrefLevel [Byte0]: 38
7543 11:49:13.810235 [Byte1]: 38
7544 11:49:13.814503
7545 11:49:13.815058 Set Vref, RX VrefLevel [Byte0]: 39
7546 11:49:13.817814 [Byte1]: 39
7547 11:49:13.822014
7548 11:49:13.822568 Set Vref, RX VrefLevel [Byte0]: 40
7549 11:49:13.825161 [Byte1]: 40
7550 11:49:13.829706
7551 11:49:13.830257 Set Vref, RX VrefLevel [Byte0]: 41
7552 11:49:13.832988 [Byte1]: 41
7553 11:49:13.837269
7554 11:49:13.837826 Set Vref, RX VrefLevel [Byte0]: 42
7555 11:49:13.840424 [Byte1]: 42
7556 11:49:13.845040
7557 11:49:13.845594 Set Vref, RX VrefLevel [Byte0]: 43
7558 11:49:13.848582 [Byte1]: 43
7559 11:49:13.852430
7560 11:49:13.853036 Set Vref, RX VrefLevel [Byte0]: 44
7561 11:49:13.855701 [Byte1]: 44
7562 11:49:13.859831
7563 11:49:13.860296 Set Vref, RX VrefLevel [Byte0]: 45
7564 11:49:13.863188 [Byte1]: 45
7565 11:49:13.867910
7566 11:49:13.868477 Set Vref, RX VrefLevel [Byte0]: 46
7567 11:49:13.871042 [Byte1]: 46
7568 11:49:13.875446
7569 11:49:13.876000 Set Vref, RX VrefLevel [Byte0]: 47
7570 11:49:13.878791 [Byte1]: 47
7571 11:49:13.883011
7572 11:49:13.883566 Set Vref, RX VrefLevel [Byte0]: 48
7573 11:49:13.886384 [Byte1]: 48
7574 11:49:13.890361
7575 11:49:13.890825 Set Vref, RX VrefLevel [Byte0]: 49
7576 11:49:13.893551 [Byte1]: 49
7577 11:49:13.898381
7578 11:49:13.898933 Set Vref, RX VrefLevel [Byte0]: 50
7579 11:49:13.901312 [Byte1]: 50
7580 11:49:13.905576
7581 11:49:13.906137 Set Vref, RX VrefLevel [Byte0]: 51
7582 11:49:13.909043 [Byte1]: 51
7583 11:49:13.913571
7584 11:49:13.914123 Set Vref, RX VrefLevel [Byte0]: 52
7585 11:49:13.916441 [Byte1]: 52
7586 11:49:13.921197
7587 11:49:13.921662 Set Vref, RX VrefLevel [Byte0]: 53
7588 11:49:13.923982 [Byte1]: 53
7589 11:49:13.929089
7590 11:49:13.929653 Set Vref, RX VrefLevel [Byte0]: 54
7591 11:49:13.931900 [Byte1]: 54
7592 11:49:13.936210
7593 11:49:13.936826 Set Vref, RX VrefLevel [Byte0]: 55
7594 11:49:13.939638 [Byte1]: 55
7595 11:49:13.943830
7596 11:49:13.944387 Set Vref, RX VrefLevel [Byte0]: 56
7597 11:49:13.947120 [Byte1]: 56
7598 11:49:13.951301
7599 11:49:13.951856 Set Vref, RX VrefLevel [Byte0]: 57
7600 11:49:13.954598 [Byte1]: 57
7601 11:49:13.959134
7602 11:49:13.959684 Set Vref, RX VrefLevel [Byte0]: 58
7603 11:49:13.962392 [Byte1]: 58
7604 11:49:13.966951
7605 11:49:13.967503 Set Vref, RX VrefLevel [Byte0]: 59
7606 11:49:13.970027 [Byte1]: 59
7607 11:49:13.974303
7608 11:49:13.974849 Set Vref, RX VrefLevel [Byte0]: 60
7609 11:49:13.977481 [Byte1]: 60
7610 11:49:13.981878
7611 11:49:13.982427 Set Vref, RX VrefLevel [Byte0]: 61
7612 11:49:13.985203 [Byte1]: 61
7613 11:49:13.989465
7614 11:49:13.990032 Set Vref, RX VrefLevel [Byte0]: 62
7615 11:49:13.992542 [Byte1]: 62
7616 11:49:13.997391
7617 11:49:13.997950 Set Vref, RX VrefLevel [Byte0]: 63
7618 11:49:14.000268 [Byte1]: 63
7619 11:49:14.004879
7620 11:49:14.005434 Set Vref, RX VrefLevel [Byte0]: 64
7621 11:49:14.007978 [Byte1]: 64
7622 11:49:14.012456
7623 11:49:14.013081 Set Vref, RX VrefLevel [Byte0]: 65
7624 11:49:14.015666 [Byte1]: 65
7625 11:49:14.019901
7626 11:49:14.020455 Set Vref, RX VrefLevel [Byte0]: 66
7627 11:49:14.023182 [Byte1]: 66
7628 11:49:14.027704
7629 11:49:14.028280 Set Vref, RX VrefLevel [Byte0]: 67
7630 11:49:14.031011 [Byte1]: 67
7631 11:49:14.035028
7632 11:49:14.035575 Set Vref, RX VrefLevel [Byte0]: 68
7633 11:49:14.038611 [Byte1]: 68
7634 11:49:14.042886
7635 11:49:14.043437 Set Vref, RX VrefLevel [Byte0]: 69
7636 11:49:14.046243 [Byte1]: 69
7637 11:49:14.050557
7638 11:49:14.051116 Set Vref, RX VrefLevel [Byte0]: 70
7639 11:49:14.053855 [Byte1]: 70
7640 11:49:14.057912
7641 11:49:14.058377 Set Vref, RX VrefLevel [Byte0]: 71
7642 11:49:14.061485 [Byte1]: 71
7643 11:49:14.065572
7644 11:49:14.066083 Set Vref, RX VrefLevel [Byte0]: 72
7645 11:49:14.068883 [Byte1]: 72
7646 11:49:14.073459
7647 11:49:14.074036 Final RX Vref Byte 0 = 52 to rank0
7648 11:49:14.076660 Final RX Vref Byte 1 = 56 to rank0
7649 11:49:14.079926 Final RX Vref Byte 0 = 52 to rank1
7650 11:49:14.083479 Final RX Vref Byte 1 = 56 to rank1==
7651 11:49:14.086568 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 11:49:14.093074 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7653 11:49:14.093900 ==
7654 11:49:14.094403 DQS Delay:
7655 11:49:14.094861 DQS0 = 0, DQS1 = 0
7656 11:49:14.096622 DQM Delay:
7657 11:49:14.097108 DQM0 = 126, DQM1 = 120
7658 11:49:14.099507 DQ Delay:
7659 11:49:14.103285 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7660 11:49:14.106715 DQ4 =130, DQ5 =116, DQ6 =136, DQ7 =134
7661 11:49:14.109772 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7662 11:49:14.113239 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7663 11:49:14.113721
7664 11:49:14.114201
7665 11:49:14.114660
7666 11:49:14.116098 [DramC_TX_OE_Calibration] TA2
7667 11:49:14.119745 Original DQ_B0 (3 6) =30, OEN = 27
7668 11:49:14.123132 Original DQ_B1 (3 6) =30, OEN = 27
7669 11:49:14.126254 24, 0x0, End_B0=24 End_B1=24
7670 11:49:14.126807 25, 0x0, End_B0=25 End_B1=25
7671 11:49:14.129513 26, 0x0, End_B0=26 End_B1=26
7672 11:49:14.133065 27, 0x0, End_B0=27 End_B1=27
7673 11:49:14.136074 28, 0x0, End_B0=28 End_B1=28
7674 11:49:14.139469 29, 0x0, End_B0=29 End_B1=29
7675 11:49:14.140028 30, 0x0, End_B0=30 End_B1=30
7676 11:49:14.143039 31, 0x4141, End_B0=30 End_B1=30
7677 11:49:14.146029 Byte0 end_step=30 best_step=27
7678 11:49:14.149261 Byte1 end_step=30 best_step=27
7679 11:49:14.152892 Byte0 TX OE(2T, 0.5T) = (3, 3)
7680 11:49:14.156106 Byte1 TX OE(2T, 0.5T) = (3, 3)
7681 11:49:14.156722
7682 11:49:14.157215
7683 11:49:14.162734 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7684 11:49:14.166204 CH0 RK0: MR19=303, MR18=1B1B
7685 11:49:14.172647 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7686 11:49:14.173219
7687 11:49:14.176180 ----->DramcWriteLeveling(PI) begin...
7688 11:49:14.176829 ==
7689 11:49:14.179313 Dram Type= 6, Freq= 0, CH_0, rank 1
7690 11:49:14.182688 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7691 11:49:14.183264 ==
7692 11:49:14.185715 Write leveling (Byte 0): 29 => 29
7693 11:49:14.188954 Write leveling (Byte 1): 29 => 29
7694 11:49:14.192561 DramcWriteLeveling(PI) end<-----
7695 11:49:14.193138
7696 11:49:14.193717 ==
7697 11:49:14.195673 Dram Type= 6, Freq= 0, CH_0, rank 1
7698 11:49:14.199118 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7699 11:49:14.199682 ==
7700 11:49:14.202332 [Gating] SW mode calibration
7701 11:49:14.208960 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7702 11:49:14.215739 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7703 11:49:14.219034 0 12 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7704 11:49:14.225850 0 12 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7705 11:49:14.228851 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7706 11:49:14.232209 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7707 11:49:14.238792 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7708 11:49:14.242011 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7709 11:49:14.245499 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7710 11:49:14.251982 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7711 11:49:14.255659 0 13 0 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7712 11:49:14.258681 0 13 4 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
7713 11:49:14.265188 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7714 11:49:14.268869 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7715 11:49:14.272098 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7716 11:49:14.278788 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7717 11:49:14.281696 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7718 11:49:14.285214 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7719 11:49:14.288454 0 14 0 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7720 11:49:14.295099 0 14 4 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7721 11:49:14.298469 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7722 11:49:14.301813 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7723 11:49:14.308544 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7724 11:49:14.311781 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7725 11:49:14.315170 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7726 11:49:14.321715 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7727 11:49:14.325070 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7728 11:49:14.328344 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7729 11:49:14.335185 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7730 11:49:14.338050 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7731 11:49:14.341810 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7732 11:49:14.348166 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7733 11:49:14.351592 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7734 11:49:14.354943 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7735 11:49:14.361577 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7736 11:49:14.364646 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7737 11:49:14.368236 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7738 11:49:14.374817 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7739 11:49:14.378312 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7740 11:49:14.381592 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7741 11:49:14.388139 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7742 11:49:14.391329 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7743 11:49:14.394667 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7744 11:49:14.401472 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7745 11:49:14.402037 Total UI for P1: 0, mck2ui 16
7746 11:49:14.407979 best dqsien dly found for B0: ( 1, 0, 28)
7747 11:49:14.411107 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7748 11:49:14.414581 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7749 11:49:14.417719 Total UI for P1: 0, mck2ui 16
7750 11:49:14.421448 best dqsien dly found for B1: ( 1, 1, 4)
7751 11:49:14.424680 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7752 11:49:14.427984 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7753 11:49:14.428597
7754 11:49:14.431270 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7755 11:49:14.438074 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7756 11:49:14.438642 [Gating] SW calibration Done
7757 11:49:14.439045 ==
7758 11:49:14.441182 Dram Type= 6, Freq= 0, CH_0, rank 1
7759 11:49:14.447557 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7760 11:49:14.448112 ==
7761 11:49:14.448482 RX Vref Scan: 0
7762 11:49:14.448983
7763 11:49:14.451130 RX Vref 0 -> 0, step: 1
7764 11:49:14.451851
7765 11:49:14.454518 RX Delay 0 -> 252, step: 8
7766 11:49:14.457496 iDelay=208, Bit 0, Center 127 (64 ~ 191) 128
7767 11:49:14.461084 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
7768 11:49:14.464100 iDelay=208, Bit 2, Center 131 (72 ~ 191) 120
7769 11:49:14.470625 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
7770 11:49:14.473784 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
7771 11:49:14.477288 iDelay=208, Bit 5, Center 119 (64 ~ 175) 112
7772 11:49:14.480841 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
7773 11:49:14.483908 iDelay=208, Bit 7, Center 143 (80 ~ 207) 128
7774 11:49:14.490742 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
7775 11:49:14.493829 iDelay=208, Bit 9, Center 111 (56 ~ 167) 112
7776 11:49:14.497307 iDelay=208, Bit 10, Center 123 (64 ~ 183) 120
7777 11:49:14.500700 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
7778 11:49:14.504251 iDelay=208, Bit 12, Center 131 (72 ~ 191) 120
7779 11:49:14.510625 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
7780 11:49:14.513882 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
7781 11:49:14.517015 iDelay=208, Bit 15, Center 131 (72 ~ 191) 120
7782 11:49:14.517497 ==
7783 11:49:14.520983 Dram Type= 6, Freq= 0, CH_0, rank 1
7784 11:49:14.523894 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7785 11:49:14.524459 ==
7786 11:49:14.527425 DQS Delay:
7787 11:49:14.527982 DQS0 = 0, DQS1 = 0
7788 11:49:14.530544 DQM Delay:
7789 11:49:14.531105 DQM0 = 131, DQM1 = 124
7790 11:49:14.531472 DQ Delay:
7791 11:49:14.537335 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7792 11:49:14.540436 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7793 11:49:14.543907 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7794 11:49:14.546768 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7795 11:49:14.547237
7796 11:49:14.547634
7797 11:49:14.547977 ==
7798 11:49:14.550213 Dram Type= 6, Freq= 0, CH_0, rank 1
7799 11:49:14.553602 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7800 11:49:14.554186 ==
7801 11:49:14.554564
7802 11:49:14.554906
7803 11:49:14.557115 TX Vref Scan disable
7804 11:49:14.560101 == TX Byte 0 ==
7805 11:49:14.563736 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7806 11:49:14.567001 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7807 11:49:14.569997 == TX Byte 1 ==
7808 11:49:14.573506 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7809 11:49:14.576843 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7810 11:49:14.577406 ==
7811 11:49:14.580298 Dram Type= 6, Freq= 0, CH_0, rank 1
7812 11:49:14.586744 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7813 11:49:14.587304 ==
7814 11:49:14.598829
7815 11:49:14.602575 TX Vref early break, caculate TX vref
7816 11:49:14.605431 TX Vref=16, minBit 9, minWin=22, winSum=382
7817 11:49:14.608599 TX Vref=18, minBit 3, minWin=23, winSum=391
7818 11:49:14.611974 TX Vref=20, minBit 0, minWin=24, winSum=400
7819 11:49:14.615502 TX Vref=22, minBit 1, minWin=23, winSum=404
7820 11:49:14.618476 TX Vref=24, minBit 1, minWin=24, winSum=415
7821 11:49:14.625260 TX Vref=26, minBit 8, minWin=25, winSum=420
7822 11:49:14.628419 TX Vref=28, minBit 0, minWin=25, winSum=418
7823 11:49:14.631896 TX Vref=30, minBit 0, minWin=25, winSum=415
7824 11:49:14.635370 TX Vref=32, minBit 7, minWin=24, winSum=406
7825 11:49:14.638547 TX Vref=34, minBit 1, minWin=24, winSum=401
7826 11:49:14.645109 TX Vref=36, minBit 1, minWin=23, winSum=394
7827 11:49:14.648392 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 26
7828 11:49:14.648994
7829 11:49:14.651602 Final TX Range 0 Vref 26
7830 11:49:14.652153
7831 11:49:14.652567 ==
7832 11:49:14.654932 Dram Type= 6, Freq= 0, CH_0, rank 1
7833 11:49:14.658135 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7834 11:49:14.658607 ==
7835 11:49:14.661429
7836 11:49:14.661891
7837 11:49:14.662259 TX Vref Scan disable
7838 11:49:14.668090 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7839 11:49:14.668655 == TX Byte 0 ==
7840 11:49:14.671454 u2DelayCellOfst[0]=10 cells (3 PI)
7841 11:49:14.674691 u2DelayCellOfst[1]=18 cells (5 PI)
7842 11:49:14.678120 u2DelayCellOfst[2]=10 cells (3 PI)
7843 11:49:14.681579 u2DelayCellOfst[3]=14 cells (4 PI)
7844 11:49:14.684876 u2DelayCellOfst[4]=7 cells (2 PI)
7845 11:49:14.688358 u2DelayCellOfst[5]=0 cells (0 PI)
7846 11:49:14.691348 u2DelayCellOfst[6]=18 cells (5 PI)
7847 11:49:14.695032 u2DelayCellOfst[7]=18 cells (5 PI)
7848 11:49:14.698055 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7849 11:49:14.701414 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7850 11:49:14.704640 == TX Byte 1 ==
7851 11:49:14.708088 u2DelayCellOfst[8]=3 cells (1 PI)
7852 11:49:14.711700 u2DelayCellOfst[9]=0 cells (0 PI)
7853 11:49:14.714566 u2DelayCellOfst[10]=10 cells (3 PI)
7854 11:49:14.715033 u2DelayCellOfst[11]=7 cells (2 PI)
7855 11:49:14.717905 u2DelayCellOfst[12]=14 cells (4 PI)
7856 11:49:14.721423 u2DelayCellOfst[13]=14 cells (4 PI)
7857 11:49:14.724675 u2DelayCellOfst[14]=18 cells (5 PI)
7858 11:49:14.728212 u2DelayCellOfst[15]=14 cells (4 PI)
7859 11:49:14.734599 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7860 11:49:14.737975 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7861 11:49:14.738544 DramC Write-DBI on
7862 11:49:14.738930 ==
7863 11:49:14.741357 Dram Type= 6, Freq= 0, CH_0, rank 1
7864 11:49:14.747983 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7865 11:49:14.748592 ==
7866 11:49:14.748967
7867 11:49:14.749307
7868 11:49:14.749629 TX Vref Scan disable
7869 11:49:14.752400 == TX Byte 0 ==
7870 11:49:14.755456 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7871 11:49:14.758901 == TX Byte 1 ==
7872 11:49:14.762014 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7873 11:49:14.765317 DramC Write-DBI off
7874 11:49:14.765874
7875 11:49:14.766239 [DATLAT]
7876 11:49:14.766574 Freq=1600, CH0 RK1
7877 11:49:14.766904
7878 11:49:14.768475 DATLAT Default: 0xe
7879 11:49:14.768971 0, 0xFFFF, sum = 0
7880 11:49:14.771890 1, 0xFFFF, sum = 0
7881 11:49:14.775162 2, 0xFFFF, sum = 0
7882 11:49:14.775631 3, 0xFFFF, sum = 0
7883 11:49:14.778540 4, 0xFFFF, sum = 0
7884 11:49:14.779104 5, 0xFFFF, sum = 0
7885 11:49:14.781772 6, 0xFFFF, sum = 0
7886 11:49:14.782239 7, 0xFFFF, sum = 0
7887 11:49:14.785039 8, 0xFFFF, sum = 0
7888 11:49:14.785506 9, 0xFFFF, sum = 0
7889 11:49:14.788686 10, 0xFFFF, sum = 0
7890 11:49:14.789247 11, 0xFFFF, sum = 0
7891 11:49:14.791836 12, 0xCFFF, sum = 0
7892 11:49:14.792302 13, 0x0, sum = 1
7893 11:49:14.795376 14, 0x0, sum = 2
7894 11:49:14.795940 15, 0x0, sum = 3
7895 11:49:14.798449 16, 0x0, sum = 4
7896 11:49:14.798919 best_step = 14
7897 11:49:14.799287
7898 11:49:14.799620 ==
7899 11:49:14.801945 Dram Type= 6, Freq= 0, CH_0, rank 1
7900 11:49:14.805168 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7901 11:49:14.808647 ==
7902 11:49:14.809201 RX Vref Scan: 0
7903 11:49:14.809568
7904 11:49:14.812080 RX Vref 0 -> 0, step: 1
7905 11:49:14.812700
7906 11:49:14.813137 RX Delay 11 -> 252, step: 4
7907 11:49:14.819252 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7908 11:49:14.822346 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7909 11:49:14.825870 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7910 11:49:14.829193 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7911 11:49:14.832576 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
7912 11:49:14.839190 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7913 11:49:14.842369 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
7914 11:49:14.845724 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7915 11:49:14.848992 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7916 11:49:14.852126 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
7917 11:49:14.858892 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7918 11:49:14.861937 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7919 11:49:14.865795 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
7920 11:49:14.869008 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7921 11:49:14.875440 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
7922 11:49:14.879029 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7923 11:49:14.879584 ==
7924 11:49:14.881834 Dram Type= 6, Freq= 0, CH_0, rank 1
7925 11:49:14.886116 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7926 11:49:14.886678 ==
7927 11:49:14.888409 DQS Delay:
7928 11:49:14.888958 DQS0 = 0, DQS1 = 0
7929 11:49:14.889445 DQM Delay:
7930 11:49:14.892065 DQM0 = 128, DQM1 = 121
7931 11:49:14.892684 DQ Delay:
7932 11:49:14.895284 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
7933 11:49:14.898541 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7934 11:49:14.902072 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
7935 11:49:14.908598 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
7936 11:49:14.909172
7937 11:49:14.909665
7938 11:49:14.910117
7939 11:49:14.911690 [DramC_TX_OE_Calibration] TA2
7940 11:49:14.912172 Original DQ_B0 (3 6) =30, OEN = 27
7941 11:49:14.915622 Original DQ_B1 (3 6) =30, OEN = 27
7942 11:49:14.918666 24, 0x0, End_B0=24 End_B1=24
7943 11:49:14.922073 25, 0x0, End_B0=25 End_B1=25
7944 11:49:14.924993 26, 0x0, End_B0=26 End_B1=26
7945 11:49:14.928602 27, 0x0, End_B0=27 End_B1=27
7946 11:49:14.929213 28, 0x0, End_B0=28 End_B1=28
7947 11:49:14.931832 29, 0x0, End_B0=29 End_B1=29
7948 11:49:14.935226 30, 0x0, End_B0=30 End_B1=30
7949 11:49:14.938706 31, 0x4141, End_B0=30 End_B1=30
7950 11:49:14.941848 Byte0 end_step=30 best_step=27
7951 11:49:14.942420 Byte1 end_step=30 best_step=27
7952 11:49:14.945157 Byte0 TX OE(2T, 0.5T) = (3, 3)
7953 11:49:14.948344 Byte1 TX OE(2T, 0.5T) = (3, 3)
7954 11:49:14.948872
7955 11:49:14.949350
7956 11:49:14.958370 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7957 11:49:14.958957 CH0 RK1: MR19=303, MR18=2121
7958 11:49:14.964944 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
7959 11:49:14.967980 [RxdqsGatingPostProcess] freq 1600
7960 11:49:14.975223 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7961 11:49:14.978384 Pre-setting of DQS Precalculation
7962 11:49:14.981470 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7963 11:49:14.982028 ==
7964 11:49:14.984616 Dram Type= 6, Freq= 0, CH_1, rank 0
7965 11:49:14.991347 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7966 11:49:14.991910 ==
7967 11:49:14.994487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7968 11:49:15.001199 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7969 11:49:15.004380 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7970 11:49:15.010949 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7971 11:49:15.018461 [CA 0] Center 41 (11~71) winsize 61
7972 11:49:15.021434 [CA 1] Center 40 (10~71) winsize 62
7973 11:49:15.024785 [CA 2] Center 36 (7~66) winsize 60
7974 11:49:15.027932 [CA 3] Center 35 (6~65) winsize 60
7975 11:49:15.031353 [CA 4] Center 33 (3~63) winsize 61
7976 11:49:15.034713 [CA 5] Center 33 (4~63) winsize 60
7977 11:49:15.035290
7978 11:49:15.037861 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7979 11:49:15.038441
7980 11:49:15.044462 [CATrainingPosCal] consider 1 rank data
7981 11:49:15.045107 u2DelayCellTimex100 = 271/100 ps
7982 11:49:15.051092 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
7983 11:49:15.054463 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
7984 11:49:15.057568 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
7985 11:49:15.060784 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
7986 11:49:15.064381 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
7987 11:49:15.067565 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
7988 11:49:15.068035
7989 11:49:15.070804 CA PerBit enable=1, Macro0, CA PI delay=33
7990 11:49:15.071276
7991 11:49:15.074367 [CBTSetCACLKResult] CA Dly = 33
7992 11:49:15.077500 CS Dly: 9 (0~40)
7993 11:49:15.080945 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
7994 11:49:15.084556 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
7995 11:49:15.085123 ==
7996 11:49:15.087647 Dram Type= 6, Freq= 0, CH_1, rank 1
7997 11:49:15.091147 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7998 11:49:15.094237 ==
7999 11:49:15.097454 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8000 11:49:15.100603 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8001 11:49:15.107294 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8002 11:49:15.113977 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8003 11:49:15.120679 [CA 0] Center 41 (11~71) winsize 61
8004 11:49:15.123910 [CA 1] Center 40 (10~71) winsize 62
8005 11:49:15.127251 [CA 2] Center 36 (7~66) winsize 60
8006 11:49:15.130568 [CA 3] Center 36 (7~65) winsize 59
8007 11:49:15.133938 [CA 4] Center 34 (5~64) winsize 60
8008 11:49:15.137133 [CA 5] Center 34 (4~64) winsize 61
8009 11:49:15.137708
8010 11:49:15.140605 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8011 11:49:15.141177
8012 11:49:15.147151 [CATrainingPosCal] consider 2 rank data
8013 11:49:15.147734 u2DelayCellTimex100 = 271/100 ps
8014 11:49:15.153747 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8015 11:49:15.156970 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
8016 11:49:15.160216 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8017 11:49:15.163577 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8018 11:49:15.166885 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8019 11:49:15.170272 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8020 11:49:15.170841
8021 11:49:15.173693 CA PerBit enable=1, Macro0, CA PI delay=33
8022 11:49:15.174266
8023 11:49:15.176781 [CBTSetCACLKResult] CA Dly = 33
8024 11:49:15.180141 CS Dly: 9 (0~40)
8025 11:49:15.183267 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8026 11:49:15.186663 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8027 11:49:15.187240
8028 11:49:15.190036 ----->DramcWriteLeveling(PI) begin...
8029 11:49:15.190560 ==
8030 11:49:15.193147 Dram Type= 6, Freq= 0, CH_1, rank 0
8031 11:49:15.199673 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8032 11:49:15.200235 ==
8033 11:49:15.203389 Write leveling (Byte 0): 22 => 22
8034 11:49:15.206650 Write leveling (Byte 1): 22 => 22
8035 11:49:15.207148 DramcWriteLeveling(PI) end<-----
8036 11:49:15.207631
8037 11:49:15.209948 ==
8038 11:49:15.213070 Dram Type= 6, Freq= 0, CH_1, rank 0
8039 11:49:15.216183 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8040 11:49:15.216705 ==
8041 11:49:15.219415 [Gating] SW mode calibration
8042 11:49:15.227157 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8043 11:49:15.229828 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8044 11:49:15.236502 0 12 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8045 11:49:15.239762 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 11:49:15.243219 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 11:49:15.249653 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 11:49:15.252953 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 11:49:15.256276 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 11:49:15.262825 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 11:49:15.266019 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8052 11:49:15.269526 0 13 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
8053 11:49:15.276403 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8054 11:49:15.279372 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 11:49:15.282786 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 11:49:15.289360 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 11:49:15.292768 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 11:49:15.296168 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 11:49:15.302571 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8060 11:49:15.305688 0 14 0 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8061 11:49:15.309253 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 11:49:15.315782 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 11:49:15.318784 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 11:49:15.322397 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 11:49:15.329154 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 11:49:15.332211 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 11:49:15.335885 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8068 11:49:15.342345 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8069 11:49:15.345423 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8070 11:49:15.348879 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 11:49:15.355584 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 11:49:15.358482 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 11:49:15.361964 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 11:49:15.368973 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 11:49:15.371689 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 11:49:15.375633 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 11:49:15.381758 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 11:49:15.385494 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 11:49:15.388381 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 11:49:15.395100 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 11:49:15.398522 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 11:49:15.401594 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 11:49:15.408269 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8084 11:49:15.411255 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8085 11:49:15.414750 Total UI for P1: 0, mck2ui 16
8086 11:49:15.417836 best dqsien dly found for B0: ( 1, 0, 28)
8087 11:49:15.421650 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8088 11:49:15.424609 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 11:49:15.428140 Total UI for P1: 0, mck2ui 16
8090 11:49:15.431322 best dqsien dly found for B1: ( 1, 1, 0)
8091 11:49:15.437983 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8092 11:49:15.441377 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8093 11:49:15.441953
8094 11:49:15.444661 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8095 11:49:15.448076 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8096 11:49:15.451321 [Gating] SW calibration Done
8097 11:49:15.451891 ==
8098 11:49:15.454576 Dram Type= 6, Freq= 0, CH_1, rank 0
8099 11:49:15.457642 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8100 11:49:15.458131 ==
8101 11:49:15.458614 RX Vref Scan: 0
8102 11:49:15.461090
8103 11:49:15.461585 RX Vref 0 -> 0, step: 1
8104 11:49:15.462189
8105 11:49:15.464413 RX Delay 0 -> 252, step: 8
8106 11:49:15.467708 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8107 11:49:15.470854 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8108 11:49:15.477674 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8109 11:49:15.481163 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8110 11:49:15.484422 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8111 11:49:15.487707 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8112 11:49:15.490923 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8113 11:49:15.497848 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8114 11:49:15.500816 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8115 11:49:15.504352 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8116 11:49:15.507469 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8117 11:49:15.510895 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8118 11:49:15.517301 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8119 11:49:15.520651 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8120 11:49:15.524442 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8121 11:49:15.527521 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8122 11:49:15.528091 ==
8123 11:49:15.530851 Dram Type= 6, Freq= 0, CH_1, rank 0
8124 11:49:15.537292 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8125 11:49:15.537877 ==
8126 11:49:15.538372 DQS Delay:
8127 11:49:15.540588 DQS0 = 0, DQS1 = 0
8128 11:49:15.541071 DQM Delay:
8129 11:49:15.543725 DQM0 = 130, DQM1 = 125
8130 11:49:15.544202 DQ Delay:
8131 11:49:15.547520 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8132 11:49:15.550773 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8133 11:49:15.553656 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8134 11:49:15.556908 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8135 11:49:15.557387
8136 11:49:15.557971
8137 11:49:15.558432 ==
8138 11:49:15.560247 Dram Type= 6, Freq= 0, CH_1, rank 0
8139 11:49:15.566912 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8140 11:49:15.567417 ==
8141 11:49:15.567986
8142 11:49:15.568570
8143 11:49:15.569024 TX Vref Scan disable
8144 11:49:15.570416 == TX Byte 0 ==
8145 11:49:15.573596 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8146 11:49:15.580186 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8147 11:49:15.580710 == TX Byte 1 ==
8148 11:49:15.584207 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8149 11:49:15.590125 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8150 11:49:15.590700 ==
8151 11:49:15.593332 Dram Type= 6, Freq= 0, CH_1, rank 0
8152 11:49:15.596629 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8153 11:49:15.597114 ==
8154 11:49:15.609783
8155 11:49:15.613320 TX Vref early break, caculate TX vref
8156 11:49:15.616083 TX Vref=16, minBit 0, minWin=21, winSum=364
8157 11:49:15.619529 TX Vref=18, minBit 3, minWin=21, winSum=373
8158 11:49:15.623152 TX Vref=20, minBit 0, minWin=23, winSum=385
8159 11:49:15.626570 TX Vref=22, minBit 3, minWin=23, winSum=392
8160 11:49:15.629687 TX Vref=24, minBit 0, minWin=24, winSum=400
8161 11:49:15.636260 TX Vref=26, minBit 1, minWin=24, winSum=406
8162 11:49:15.639497 TX Vref=28, minBit 0, minWin=24, winSum=408
8163 11:49:15.642922 TX Vref=30, minBit 0, minWin=24, winSum=406
8164 11:49:15.645909 TX Vref=32, minBit 3, minWin=23, winSum=394
8165 11:49:15.649232 TX Vref=34, minBit 0, minWin=23, winSum=390
8166 11:49:15.652981 TX Vref=36, minBit 3, minWin=22, winSum=377
8167 11:49:15.659215 [TxChooseVref] Worse bit 0, Min win 24, Win sum 408, Final Vref 28
8168 11:49:15.659776
8169 11:49:15.662746 Final TX Range 0 Vref 28
8170 11:49:15.663230
8171 11:49:15.663712 ==
8172 11:49:15.665852 Dram Type= 6, Freq= 0, CH_1, rank 0
8173 11:49:15.669812 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8174 11:49:15.670415 ==
8175 11:49:15.670904
8176 11:49:15.671354
8177 11:49:15.672579 TX Vref Scan disable
8178 11:49:15.679221 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8179 11:49:15.679797 == TX Byte 0 ==
8180 11:49:15.682843 u2DelayCellOfst[0]=14 cells (4 PI)
8181 11:49:15.685869 u2DelayCellOfst[1]=10 cells (3 PI)
8182 11:49:15.689050 u2DelayCellOfst[2]=0 cells (0 PI)
8183 11:49:15.692646 u2DelayCellOfst[3]=7 cells (2 PI)
8184 11:49:15.696041 u2DelayCellOfst[4]=7 cells (2 PI)
8185 11:49:15.699272 u2DelayCellOfst[5]=14 cells (4 PI)
8186 11:49:15.702522 u2DelayCellOfst[6]=14 cells (4 PI)
8187 11:49:15.706212 u2DelayCellOfst[7]=3 cells (1 PI)
8188 11:49:15.709137 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8189 11:49:15.712531 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8190 11:49:15.715817 == TX Byte 1 ==
8191 11:49:15.719111 u2DelayCellOfst[8]=0 cells (0 PI)
8192 11:49:15.719684 u2DelayCellOfst[9]=3 cells (1 PI)
8193 11:49:15.722628 u2DelayCellOfst[10]=10 cells (3 PI)
8194 11:49:15.725688 u2DelayCellOfst[11]=3 cells (1 PI)
8195 11:49:15.729336 u2DelayCellOfst[12]=18 cells (5 PI)
8196 11:49:15.732191 u2DelayCellOfst[13]=21 cells (6 PI)
8197 11:49:15.735757 u2DelayCellOfst[14]=18 cells (5 PI)
8198 11:49:15.739172 u2DelayCellOfst[15]=18 cells (5 PI)
8199 11:49:15.745495 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8200 11:49:15.748880 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8201 11:49:15.749498 DramC Write-DBI on
8202 11:49:15.750006 ==
8203 11:49:15.752091 Dram Type= 6, Freq= 0, CH_1, rank 0
8204 11:49:15.759025 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8205 11:49:15.759615 ==
8206 11:49:15.760120
8207 11:49:15.760640
8208 11:49:15.761103 TX Vref Scan disable
8209 11:49:15.762529 == TX Byte 0 ==
8210 11:49:15.765980 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8211 11:49:15.769403 == TX Byte 1 ==
8212 11:49:15.772859 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8213 11:49:15.776150 DramC Write-DBI off
8214 11:49:15.776790
8215 11:49:15.777170 [DATLAT]
8216 11:49:15.777513 Freq=1600, CH1 RK0
8217 11:49:15.777844
8218 11:49:15.778987 DATLAT Default: 0xf
8219 11:49:15.782593 0, 0xFFFF, sum = 0
8220 11:49:15.783163 1, 0xFFFF, sum = 0
8221 11:49:15.785720 2, 0xFFFF, sum = 0
8222 11:49:15.786188 3, 0xFFFF, sum = 0
8223 11:49:15.789368 4, 0xFFFF, sum = 0
8224 11:49:15.789949 5, 0xFFFF, sum = 0
8225 11:49:15.792406 6, 0xFFFF, sum = 0
8226 11:49:15.793076 7, 0xFFFF, sum = 0
8227 11:49:15.795885 8, 0xFFFF, sum = 0
8228 11:49:15.796355 9, 0xFFFF, sum = 0
8229 11:49:15.799134 10, 0xFFFF, sum = 0
8230 11:49:15.799730 11, 0xFFFF, sum = 0
8231 11:49:15.802251 12, 0xF7F, sum = 0
8232 11:49:15.802924 13, 0x0, sum = 1
8233 11:49:15.805831 14, 0x0, sum = 2
8234 11:49:15.806407 15, 0x0, sum = 3
8235 11:49:15.809149 16, 0x0, sum = 4
8236 11:49:15.809637 best_step = 14
8237 11:49:15.810008
8238 11:49:15.810348 ==
8239 11:49:15.812738 Dram Type= 6, Freq= 0, CH_1, rank 0
8240 11:49:15.815744 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8241 11:49:15.818855 ==
8242 11:49:15.819327 RX Vref Scan: 1
8243 11:49:15.819692
8244 11:49:15.822112 Set Vref Range= 24 -> 127
8245 11:49:15.822572
8246 11:49:15.825717 RX Vref 24 -> 127, step: 1
8247 11:49:15.826284
8248 11:49:15.826653 RX Delay 3 -> 252, step: 4
8249 11:49:15.826996
8250 11:49:15.828872 Set Vref, RX VrefLevel [Byte0]: 24
8251 11:49:15.832250 [Byte1]: 24
8252 11:49:15.836182
8253 11:49:15.836806 Set Vref, RX VrefLevel [Byte0]: 25
8254 11:49:15.839219 [Byte1]: 25
8255 11:49:15.843641
8256 11:49:15.844199 Set Vref, RX VrefLevel [Byte0]: 26
8257 11:49:15.846937 [Byte1]: 26
8258 11:49:15.851412
8259 11:49:15.851992 Set Vref, RX VrefLevel [Byte0]: 27
8260 11:49:15.854640 [Byte1]: 27
8261 11:49:15.859005
8262 11:49:15.859558 Set Vref, RX VrefLevel [Byte0]: 28
8263 11:49:15.862004 [Byte1]: 28
8264 11:49:15.866291
8265 11:49:15.866864 Set Vref, RX VrefLevel [Byte0]: 29
8266 11:49:15.869896 [Byte1]: 29
8267 11:49:15.873990
8268 11:49:15.874619 Set Vref, RX VrefLevel [Byte0]: 30
8269 11:49:15.877461 [Byte1]: 30
8270 11:49:15.881953
8271 11:49:15.882531 Set Vref, RX VrefLevel [Byte0]: 31
8272 11:49:15.885166 [Byte1]: 31
8273 11:49:15.889590
8274 11:49:15.890157 Set Vref, RX VrefLevel [Byte0]: 32
8275 11:49:15.892760 [Byte1]: 32
8276 11:49:15.897180
8277 11:49:15.897748 Set Vref, RX VrefLevel [Byte0]: 33
8278 11:49:15.900380 [Byte1]: 33
8279 11:49:15.904684
8280 11:49:15.905152 Set Vref, RX VrefLevel [Byte0]: 34
8281 11:49:15.908090 [Byte1]: 34
8282 11:49:15.912632
8283 11:49:15.913191 Set Vref, RX VrefLevel [Byte0]: 35
8284 11:49:15.915928 [Byte1]: 35
8285 11:49:15.920059
8286 11:49:15.920706 Set Vref, RX VrefLevel [Byte0]: 36
8287 11:49:15.923442 [Byte1]: 36
8288 11:49:15.927728
8289 11:49:15.928293 Set Vref, RX VrefLevel [Byte0]: 37
8290 11:49:15.931263 [Byte1]: 37
8291 11:49:15.935726
8292 11:49:15.936308 Set Vref, RX VrefLevel [Byte0]: 38
8293 11:49:15.938757 [Byte1]: 38
8294 11:49:15.942912
8295 11:49:15.943369 Set Vref, RX VrefLevel [Byte0]: 39
8296 11:49:15.946115 [Byte1]: 39
8297 11:49:15.950569
8298 11:49:15.951026 Set Vref, RX VrefLevel [Byte0]: 40
8299 11:49:15.953851 [Byte1]: 40
8300 11:49:15.958304
8301 11:49:15.958765 Set Vref, RX VrefLevel [Byte0]: 41
8302 11:49:15.961532 [Byte1]: 41
8303 11:49:15.966137
8304 11:49:15.966559 Set Vref, RX VrefLevel [Byte0]: 42
8305 11:49:15.969398 [Byte1]: 42
8306 11:49:15.973803
8307 11:49:15.974301 Set Vref, RX VrefLevel [Byte0]: 43
8308 11:49:15.976883 [Byte1]: 43
8309 11:49:15.981080
8310 11:49:15.981497 Set Vref, RX VrefLevel [Byte0]: 44
8311 11:49:15.984458 [Byte1]: 44
8312 11:49:15.989205
8313 11:49:15.989760 Set Vref, RX VrefLevel [Byte0]: 45
8314 11:49:15.992298 [Byte1]: 45
8315 11:49:15.996537
8316 11:49:15.997006 Set Vref, RX VrefLevel [Byte0]: 46
8317 11:49:15.999742 [Byte1]: 46
8318 11:49:16.004150
8319 11:49:16.004864 Set Vref, RX VrefLevel [Byte0]: 47
8320 11:49:16.010911 [Byte1]: 47
8321 11:49:16.011477
8322 11:49:16.013848 Set Vref, RX VrefLevel [Byte0]: 48
8323 11:49:16.017450 [Byte1]: 48
8324 11:49:16.018019
8325 11:49:16.020719 Set Vref, RX VrefLevel [Byte0]: 49
8326 11:49:16.023880 [Byte1]: 49
8327 11:49:16.027437
8328 11:49:16.027998 Set Vref, RX VrefLevel [Byte0]: 50
8329 11:49:16.030640 [Byte1]: 50
8330 11:49:16.034973
8331 11:49:16.035553 Set Vref, RX VrefLevel [Byte0]: 51
8332 11:49:16.038638 [Byte1]: 51
8333 11:49:16.042676
8334 11:49:16.043240 Set Vref, RX VrefLevel [Byte0]: 52
8335 11:49:16.045883 [Byte1]: 52
8336 11:49:16.050032
8337 11:49:16.050502 Set Vref, RX VrefLevel [Byte0]: 53
8338 11:49:16.053250 [Byte1]: 53
8339 11:49:16.057996
8340 11:49:16.058562 Set Vref, RX VrefLevel [Byte0]: 54
8341 11:49:16.061047 [Byte1]: 54
8342 11:49:16.065640
8343 11:49:16.066204 Set Vref, RX VrefLevel [Byte0]: 55
8344 11:49:16.068977 [Byte1]: 55
8345 11:49:16.073387
8346 11:49:16.074017 Set Vref, RX VrefLevel [Byte0]: 56
8347 11:49:16.076704 [Byte1]: 56
8348 11:49:16.080955
8349 11:49:16.081517 Set Vref, RX VrefLevel [Byte0]: 57
8350 11:49:16.084270 [Byte1]: 57
8351 11:49:16.088809
8352 11:49:16.089376 Set Vref, RX VrefLevel [Byte0]: 58
8353 11:49:16.092013 [Byte1]: 58
8354 11:49:16.095982
8355 11:49:16.096445 Set Vref, RX VrefLevel [Byte0]: 59
8356 11:49:16.099915 [Byte1]: 59
8357 11:49:16.103648
8358 11:49:16.104235 Set Vref, RX VrefLevel [Byte0]: 60
8359 11:49:16.106811 [Byte1]: 60
8360 11:49:16.111430
8361 11:49:16.111993 Set Vref, RX VrefLevel [Byte0]: 61
8362 11:49:16.114703 [Byte1]: 61
8363 11:49:16.118948
8364 11:49:16.119414 Set Vref, RX VrefLevel [Byte0]: 62
8365 11:49:16.122550 [Byte1]: 62
8366 11:49:16.126838
8367 11:49:16.127406 Set Vref, RX VrefLevel [Byte0]: 63
8368 11:49:16.130238 [Byte1]: 63
8369 11:49:16.134605
8370 11:49:16.135173 Set Vref, RX VrefLevel [Byte0]: 64
8371 11:49:16.137474 [Byte1]: 64
8372 11:49:16.142173
8373 11:49:16.142760 Set Vref, RX VrefLevel [Byte0]: 65
8374 11:49:16.145271 [Byte1]: 65
8375 11:49:16.149639
8376 11:49:16.150273 Set Vref, RX VrefLevel [Byte0]: 66
8377 11:49:16.152737 [Byte1]: 66
8378 11:49:16.157458
8379 11:49:16.158025 Set Vref, RX VrefLevel [Byte0]: 67
8380 11:49:16.160651 [Byte1]: 67
8381 11:49:16.164987
8382 11:49:16.165454 Set Vref, RX VrefLevel [Byte0]: 68
8383 11:49:16.167977 [Byte1]: 68
8384 11:49:16.172737
8385 11:49:16.173303 Set Vref, RX VrefLevel [Byte0]: 69
8386 11:49:16.176231 [Byte1]: 69
8387 11:49:16.180445
8388 11:49:16.180953 Set Vref, RX VrefLevel [Byte0]: 70
8389 11:49:16.183578 [Byte1]: 70
8390 11:49:16.187942
8391 11:49:16.188432 Set Vref, RX VrefLevel [Byte0]: 71
8392 11:49:16.191044 [Byte1]: 71
8393 11:49:16.195331
8394 11:49:16.195798 Set Vref, RX VrefLevel [Byte0]: 72
8395 11:49:16.198839 [Byte1]: 72
8396 11:49:16.203417
8397 11:49:16.203984 Set Vref, RX VrefLevel [Byte0]: 73
8398 11:49:16.206300 [Byte1]: 73
8399 11:49:16.211049
8400 11:49:16.211618 Set Vref, RX VrefLevel [Byte0]: 74
8401 11:49:16.214214 [Byte1]: 74
8402 11:49:16.218597
8403 11:49:16.219165 Set Vref, RX VrefLevel [Byte0]: 75
8404 11:49:16.221615 [Byte1]: 75
8405 11:49:16.226421
8406 11:49:16.226989 Set Vref, RX VrefLevel [Byte0]: 76
8407 11:49:16.229264 [Byte1]: 76
8408 11:49:16.233861
8409 11:49:16.234424 Final RX Vref Byte 0 = 58 to rank0
8410 11:49:16.237189 Final RX Vref Byte 1 = 54 to rank0
8411 11:49:16.240704 Final RX Vref Byte 0 = 58 to rank1
8412 11:49:16.244105 Final RX Vref Byte 1 = 54 to rank1==
8413 11:49:16.247348 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 11:49:16.253853 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8415 11:49:16.254462 ==
8416 11:49:16.254865 DQS Delay:
8417 11:49:16.257254 DQS0 = 0, DQS1 = 0
8418 11:49:16.257819 DQM Delay:
8419 11:49:16.258191 DQM0 = 128, DQM1 = 123
8420 11:49:16.260173 DQ Delay:
8421 11:49:16.263422 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
8422 11:49:16.267034 DQ4 =126, DQ5 =140, DQ6 =134, DQ7 =126
8423 11:49:16.270161 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =112
8424 11:49:16.273546 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =132
8425 11:49:16.274120
8426 11:49:16.274601
8427 11:49:16.274957
8428 11:49:16.276660 [DramC_TX_OE_Calibration] TA2
8429 11:49:16.280148 Original DQ_B0 (3 6) =30, OEN = 27
8430 11:49:16.283598 Original DQ_B1 (3 6) =30, OEN = 27
8431 11:49:16.286655 24, 0x0, End_B0=24 End_B1=24
8432 11:49:16.287236 25, 0x0, End_B0=25 End_B1=25
8433 11:49:16.289926 26, 0x0, End_B0=26 End_B1=26
8434 11:49:16.293312 27, 0x0, End_B0=27 End_B1=27
8435 11:49:16.296621 28, 0x0, End_B0=28 End_B1=28
8436 11:49:16.299718 29, 0x0, End_B0=29 End_B1=29
8437 11:49:16.300194 30, 0x0, End_B0=30 End_B1=30
8438 11:49:16.303312 31, 0x4141, End_B0=30 End_B1=30
8439 11:49:16.306411 Byte0 end_step=30 best_step=27
8440 11:49:16.309721 Byte1 end_step=30 best_step=27
8441 11:49:16.313434 Byte0 TX OE(2T, 0.5T) = (3, 3)
8442 11:49:16.316385 Byte1 TX OE(2T, 0.5T) = (3, 3)
8443 11:49:16.316894
8444 11:49:16.317267
8445 11:49:16.322992 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8446 11:49:16.326319 CH1 RK0: MR19=303, MR18=2727
8447 11:49:16.333139 CH1_RK0: MR19=0x303, MR18=0x2727, DQSOSC=390, MR23=63, INC=24, DEC=16
8448 11:49:16.333690
8449 11:49:16.336652 ----->DramcWriteLeveling(PI) begin...
8450 11:49:16.337222 ==
8451 11:49:16.339952 Dram Type= 6, Freq= 0, CH_1, rank 1
8452 11:49:16.343375 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8453 11:49:16.343939 ==
8454 11:49:16.346401 Write leveling (Byte 0): 21 => 21
8455 11:49:16.349596 Write leveling (Byte 1): 20 => 20
8456 11:49:16.353107 DramcWriteLeveling(PI) end<-----
8457 11:49:16.353669
8458 11:49:16.354037 ==
8459 11:49:16.356322 Dram Type= 6, Freq= 0, CH_1, rank 1
8460 11:49:16.359913 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8461 11:49:16.360483 ==
8462 11:49:16.362729 [Gating] SW mode calibration
8463 11:49:16.369353 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8464 11:49:16.376412 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8465 11:49:16.379300 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8466 11:49:16.385798 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8467 11:49:16.389509 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8468 11:49:16.392667 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8469 11:49:16.399280 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8470 11:49:16.402954 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8471 11:49:16.405922 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8472 11:49:16.412351 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8473 11:49:16.415842 0 13 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8474 11:49:16.419131 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 11:49:16.425699 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8476 11:49:16.428899 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8477 11:49:16.432203 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8478 11:49:16.439454 0 13 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8479 11:49:16.442471 0 13 24 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8480 11:49:16.445660 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8481 11:49:16.452323 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8482 11:49:16.455596 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 11:49:16.459021 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 11:49:16.465341 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 11:49:16.468668 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 11:49:16.472123 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 11:49:16.479100 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8488 11:49:16.482463 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8489 11:49:16.485393 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8490 11:49:16.488699 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8491 11:49:16.495304 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 11:49:16.498796 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 11:49:16.501956 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 11:49:16.508611 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 11:49:16.512037 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 11:49:16.515180 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 11:49:16.521717 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 11:49:16.525216 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 11:49:16.528439 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 11:49:16.535035 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 11:49:16.538175 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 11:49:16.541680 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8503 11:49:16.548417 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8504 11:49:16.551425 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8505 11:49:16.555109 Total UI for P1: 0, mck2ui 16
8506 11:49:16.558153 best dqsien dly found for B0: ( 1, 0, 22)
8507 11:49:16.561401 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8508 11:49:16.564611 Total UI for P1: 0, mck2ui 16
8509 11:49:16.567822 best dqsien dly found for B1: ( 1, 0, 28)
8510 11:49:16.571539 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8511 11:49:16.574807 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8512 11:49:16.575355
8513 11:49:16.581328 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8514 11:49:16.584933 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8515 11:49:16.588035 [Gating] SW calibration Done
8516 11:49:16.588678 ==
8517 11:49:16.591602 Dram Type= 6, Freq= 0, CH_1, rank 1
8518 11:49:16.594495 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8519 11:49:16.594971 ==
8520 11:49:16.595340 RX Vref Scan: 0
8521 11:49:16.595700
8522 11:49:16.597924 RX Vref 0 -> 0, step: 1
8523 11:49:16.598482
8524 11:49:16.601111 RX Delay 0 -> 252, step: 8
8525 11:49:16.604640 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8526 11:49:16.608015 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8527 11:49:16.611265 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8528 11:49:16.618083 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8529 11:49:16.621222 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8530 11:49:16.624300 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8531 11:49:16.628208 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8532 11:49:16.631486 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8533 11:49:16.637776 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8534 11:49:16.641086 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8535 11:49:16.644419 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8536 11:49:16.647819 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8537 11:49:16.650934 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8538 11:49:16.657662 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8539 11:49:16.661467 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8540 11:49:16.664324 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8541 11:49:16.664844 ==
8542 11:49:16.667632 Dram Type= 6, Freq= 0, CH_1, rank 1
8543 11:49:16.671085 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8544 11:49:16.674038 ==
8545 11:49:16.674504 DQS Delay:
8546 11:49:16.674870 DQS0 = 0, DQS1 = 0
8547 11:49:16.677406 DQM Delay:
8548 11:49:16.677876 DQM0 = 130, DQM1 = 125
8549 11:49:16.680594 DQ Delay:
8550 11:49:16.684137 DQ0 =131, DQ1 =123, DQ2 =115, DQ3 =131
8551 11:49:16.687662 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8552 11:49:16.690798 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8553 11:49:16.694275 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8554 11:49:16.694845
8555 11:49:16.695219
8556 11:49:16.695560 ==
8557 11:49:16.697193 Dram Type= 6, Freq= 0, CH_1, rank 1
8558 11:49:16.700481 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8559 11:49:16.703665 ==
8560 11:49:16.704128
8561 11:49:16.704487
8562 11:49:16.704887 TX Vref Scan disable
8563 11:49:16.707307 == TX Byte 0 ==
8564 11:49:16.710375 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8565 11:49:16.713729 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8566 11:49:16.717151 == TX Byte 1 ==
8567 11:49:16.720557 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8568 11:49:16.723575 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8569 11:49:16.727134 ==
8570 11:49:16.727694 Dram Type= 6, Freq= 0, CH_1, rank 1
8571 11:49:16.733304 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8572 11:49:16.733861 ==
8573 11:49:16.746655
8574 11:49:16.749745 TX Vref early break, caculate TX vref
8575 11:49:16.752984 TX Vref=16, minBit 0, minWin=22, winSum=381
8576 11:49:16.756284 TX Vref=18, minBit 0, minWin=23, winSum=387
8577 11:49:16.759670 TX Vref=20, minBit 0, minWin=24, winSum=402
8578 11:49:16.763037 TX Vref=22, minBit 0, minWin=24, winSum=405
8579 11:49:16.766395 TX Vref=24, minBit 3, minWin=24, winSum=410
8580 11:49:16.773146 TX Vref=26, minBit 2, minWin=24, winSum=417
8581 11:49:16.776330 TX Vref=28, minBit 0, minWin=25, winSum=421
8582 11:49:16.779764 TX Vref=30, minBit 0, minWin=24, winSum=415
8583 11:49:16.783236 TX Vref=32, minBit 0, minWin=25, winSum=414
8584 11:49:16.786338 TX Vref=34, minBit 0, minWin=23, winSum=404
8585 11:49:16.789339 TX Vref=36, minBit 0, minWin=23, winSum=395
8586 11:49:16.796091 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8587 11:49:16.796600
8588 11:49:16.799250 Final TX Range 0 Vref 28
8589 11:49:16.799711
8590 11:49:16.800070 ==
8591 11:49:16.803074 Dram Type= 6, Freq= 0, CH_1, rank 1
8592 11:49:16.805990 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8593 11:49:16.806550 ==
8594 11:49:16.806917
8595 11:49:16.807251
8596 11:49:16.809230 TX Vref Scan disable
8597 11:49:16.815979 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8598 11:49:16.816620 == TX Byte 0 ==
8599 11:49:16.819385 u2DelayCellOfst[0]=18 cells (5 PI)
8600 11:49:16.822589 u2DelayCellOfst[1]=10 cells (3 PI)
8601 11:49:16.825859 u2DelayCellOfst[2]=0 cells (0 PI)
8602 11:49:16.829414 u2DelayCellOfst[3]=7 cells (2 PI)
8603 11:49:16.832670 u2DelayCellOfst[4]=7 cells (2 PI)
8604 11:49:16.836285 u2DelayCellOfst[5]=14 cells (4 PI)
8605 11:49:16.839202 u2DelayCellOfst[6]=18 cells (5 PI)
8606 11:49:16.842591 u2DelayCellOfst[7]=7 cells (2 PI)
8607 11:49:16.846048 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8608 11:49:16.849352 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8609 11:49:16.852640 == TX Byte 1 ==
8610 11:49:16.855771 u2DelayCellOfst[8]=0 cells (0 PI)
8611 11:49:16.859212 u2DelayCellOfst[9]=3 cells (1 PI)
8612 11:49:16.859797 u2DelayCellOfst[10]=7 cells (2 PI)
8613 11:49:16.862159 u2DelayCellOfst[11]=3 cells (1 PI)
8614 11:49:16.865198 u2DelayCellOfst[12]=14 cells (4 PI)
8615 11:49:16.868795 u2DelayCellOfst[13]=18 cells (5 PI)
8616 11:49:16.872297 u2DelayCellOfst[14]=18 cells (5 PI)
8617 11:49:16.875630 u2DelayCellOfst[15]=18 cells (5 PI)
8618 11:49:16.878834 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8619 11:49:16.885446 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8620 11:49:16.886007 DramC Write-DBI on
8621 11:49:16.886375 ==
8622 11:49:16.889144 Dram Type= 6, Freq= 0, CH_1, rank 1
8623 11:49:16.895525 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8624 11:49:16.896091 ==
8625 11:49:16.896594
8626 11:49:16.896950
8627 11:49:16.897279 TX Vref Scan disable
8628 11:49:16.899262 == TX Byte 0 ==
8629 11:49:16.902381 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8630 11:49:16.905902 == TX Byte 1 ==
8631 11:49:16.909410 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8632 11:49:16.912474 DramC Write-DBI off
8633 11:49:16.912971
8634 11:49:16.913337 [DATLAT]
8635 11:49:16.913676 Freq=1600, CH1 RK1
8636 11:49:16.914006
8637 11:49:16.915840 DATLAT Default: 0xe
8638 11:49:16.916296 0, 0xFFFF, sum = 0
8639 11:49:16.919017 1, 0xFFFF, sum = 0
8640 11:49:16.922538 2, 0xFFFF, sum = 0
8641 11:49:16.923006 3, 0xFFFF, sum = 0
8642 11:49:16.925524 4, 0xFFFF, sum = 0
8643 11:49:16.925990 5, 0xFFFF, sum = 0
8644 11:49:16.929044 6, 0xFFFF, sum = 0
8645 11:49:16.929511 7, 0xFFFF, sum = 0
8646 11:49:16.932138 8, 0xFFFF, sum = 0
8647 11:49:16.932647 9, 0xFFFF, sum = 0
8648 11:49:16.935675 10, 0xFFFF, sum = 0
8649 11:49:16.936245 11, 0xFFFF, sum = 0
8650 11:49:16.939176 12, 0xF7F, sum = 0
8651 11:49:16.939740 13, 0x0, sum = 1
8652 11:49:16.942113 14, 0x0, sum = 2
8653 11:49:16.942581 15, 0x0, sum = 3
8654 11:49:16.945666 16, 0x0, sum = 4
8655 11:49:16.946227 best_step = 14
8656 11:49:16.946599
8657 11:49:16.946937 ==
8658 11:49:16.948893 Dram Type= 6, Freq= 0, CH_1, rank 1
8659 11:49:16.952474 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8660 11:49:16.955350 ==
8661 11:49:16.955907 RX Vref Scan: 0
8662 11:49:16.956276
8663 11:49:16.958851 RX Vref 0 -> 0, step: 1
8664 11:49:16.959407
8665 11:49:16.959773 RX Delay 3 -> 252, step: 4
8666 11:49:16.966011 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8667 11:49:16.969519 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8668 11:49:16.973112 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8669 11:49:16.976139 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8670 11:49:16.979580 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8671 11:49:16.986412 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8672 11:49:16.989532 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8673 11:49:16.992925 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8674 11:49:16.996173 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8675 11:49:16.999552 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8676 11:49:17.006155 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8677 11:49:17.009186 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8678 11:49:17.012946 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8679 11:49:17.015855 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8680 11:49:17.022553 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8681 11:49:17.026186 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8682 11:49:17.026746 ==
8683 11:49:17.029185 Dram Type= 6, Freq= 0, CH_1, rank 1
8684 11:49:17.032577 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8685 11:49:17.033045 ==
8686 11:49:17.033414 DQS Delay:
8687 11:49:17.036067 DQS0 = 0, DQS1 = 0
8688 11:49:17.036677 DQM Delay:
8689 11:49:17.039393 DQM0 = 127, DQM1 = 122
8690 11:49:17.039951 DQ Delay:
8691 11:49:17.042635 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8692 11:49:17.045949 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8693 11:49:17.049346 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =112
8694 11:49:17.055864 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8695 11:49:17.056422
8696 11:49:17.056855
8697 11:49:17.057206
8698 11:49:17.059071 [DramC_TX_OE_Calibration] TA2
8699 11:49:17.059636 Original DQ_B0 (3 6) =30, OEN = 27
8700 11:49:17.062187 Original DQ_B1 (3 6) =30, OEN = 27
8701 11:49:17.065562 24, 0x0, End_B0=24 End_B1=24
8702 11:49:17.068951 25, 0x0, End_B0=25 End_B1=25
8703 11:49:17.072668 26, 0x0, End_B0=26 End_B1=26
8704 11:49:17.075540 27, 0x0, End_B0=27 End_B1=27
8705 11:49:17.076008 28, 0x0, End_B0=28 End_B1=28
8706 11:49:17.079027 29, 0x0, End_B0=29 End_B1=29
8707 11:49:17.082498 30, 0x0, End_B0=30 End_B1=30
8708 11:49:17.085809 31, 0x4545, End_B0=30 End_B1=30
8709 11:49:17.088727 Byte0 end_step=30 best_step=27
8710 11:49:17.089287 Byte1 end_step=30 best_step=27
8711 11:49:17.092590 Byte0 TX OE(2T, 0.5T) = (3, 3)
8712 11:49:17.095606 Byte1 TX OE(2T, 0.5T) = (3, 3)
8713 11:49:17.096167
8714 11:49:17.096589
8715 11:49:17.105442 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8716 11:49:17.106011 CH1 RK1: MR19=303, MR18=1D1D
8717 11:49:17.111784 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8718 11:49:17.115545 [RxdqsGatingPostProcess] freq 1600
8719 11:49:17.122212 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8720 11:49:17.125236 Pre-setting of DQS Precalculation
8721 11:49:17.128591 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8722 11:49:17.138547 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8723 11:49:17.145159 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8724 11:49:17.145723
8725 11:49:17.146089
8726 11:49:17.148314 [Calibration Summary] 3200 Mbps
8727 11:49:17.148929 CH 0, Rank 0
8728 11:49:17.151760 SW Impedance : PASS
8729 11:49:17.152351 DUTY Scan : NO K
8730 11:49:17.155163 ZQ Calibration : PASS
8731 11:49:17.158538 Jitter Meter : NO K
8732 11:49:17.159103 CBT Training : PASS
8733 11:49:17.161326 Write leveling : PASS
8734 11:49:17.164993 RX DQS gating : PASS
8735 11:49:17.165670 RX DQ/DQS(RDDQC) : PASS
8736 11:49:17.168374 TX DQ/DQS : PASS
8737 11:49:17.171465 RX DATLAT : PASS
8738 11:49:17.172020 RX DQ/DQS(Engine): PASS
8739 11:49:17.174712 TX OE : PASS
8740 11:49:17.175173 All Pass.
8741 11:49:17.175538
8742 11:49:17.178135 CH 0, Rank 1
8743 11:49:17.178691 SW Impedance : PASS
8744 11:49:17.181483 DUTY Scan : NO K
8745 11:49:17.184906 ZQ Calibration : PASS
8746 11:49:17.185458 Jitter Meter : NO K
8747 11:49:17.188102 CBT Training : PASS
8748 11:49:17.188706 Write leveling : PASS
8749 11:49:17.191268 RX DQS gating : PASS
8750 11:49:17.194835 RX DQ/DQS(RDDQC) : PASS
8751 11:49:17.195393 TX DQ/DQS : PASS
8752 11:49:17.198061 RX DATLAT : PASS
8753 11:49:17.201388 RX DQ/DQS(Engine): PASS
8754 11:49:17.201952 TX OE : PASS
8755 11:49:17.204649 All Pass.
8756 11:49:17.205203
8757 11:49:17.205573 CH 1, Rank 0
8758 11:49:17.208070 SW Impedance : PASS
8759 11:49:17.208679 DUTY Scan : NO K
8760 11:49:17.211157 ZQ Calibration : PASS
8761 11:49:17.214527 Jitter Meter : NO K
8762 11:49:17.215005 CBT Training : PASS
8763 11:49:17.217661 Write leveling : PASS
8764 11:49:17.221361 RX DQS gating : PASS
8765 11:49:17.221935 RX DQ/DQS(RDDQC) : PASS
8766 11:49:17.224241 TX DQ/DQS : PASS
8767 11:49:17.227749 RX DATLAT : PASS
8768 11:49:17.228322 RX DQ/DQS(Engine): PASS
8769 11:49:17.230982 TX OE : PASS
8770 11:49:17.231556 All Pass.
8771 11:49:17.232042
8772 11:49:17.234324 CH 1, Rank 1
8773 11:49:17.234799 SW Impedance : PASS
8774 11:49:17.237800 DUTY Scan : NO K
8775 11:49:17.240828 ZQ Calibration : PASS
8776 11:49:17.241303 Jitter Meter : NO K
8777 11:49:17.244208 CBT Training : PASS
8778 11:49:17.247622 Write leveling : PASS
8779 11:49:17.248200 RX DQS gating : PASS
8780 11:49:17.250953 RX DQ/DQS(RDDQC) : PASS
8781 11:49:17.251552 TX DQ/DQS : PASS
8782 11:49:17.254125 RX DATLAT : PASS
8783 11:49:17.257486 RX DQ/DQS(Engine): PASS
8784 11:49:17.258028 TX OE : PASS
8785 11:49:17.260406 All Pass.
8786 11:49:17.260920
8787 11:49:17.261402 DramC Write-DBI on
8788 11:49:17.263968 PER_BANK_REFRESH: Hybrid Mode
8789 11:49:17.267159 TX_TRACKING: ON
8790 11:49:17.273840 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8791 11:49:17.283894 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8792 11:49:17.290487 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8793 11:49:17.293555 [FAST_K] Save calibration result to emmc
8794 11:49:17.297223 sync common calibartion params.
8795 11:49:17.297796 sync cbt_mode0:0, 1:0
8796 11:49:17.300092 dram_init: ddr_geometry: 0
8797 11:49:17.303719 dram_init: ddr_geometry: 0
8798 11:49:17.307085 dram_init: ddr_geometry: 0
8799 11:49:17.307661 0:dram_rank_size:80000000
8800 11:49:17.310349 1:dram_rank_size:80000000
8801 11:49:17.316984 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8802 11:49:17.317569 DFS_SHUFFLE_HW_MODE: ON
8803 11:49:17.320309 dramc_set_vcore_voltage set vcore to 725000
8804 11:49:17.323850 Read voltage for 1600, 0
8805 11:49:17.324428 Vio18 = 0
8806 11:49:17.327028 Vcore = 725000
8807 11:49:17.327601 Vdram = 0
8808 11:49:17.328084 Vddq = 0
8809 11:49:17.330173 Vmddr = 0
8810 11:49:17.330743 switch to 3200 Mbps bootup
8811 11:49:17.333347 [DramcRunTimeConfig]
8812 11:49:17.333821 PHYPLL
8813 11:49:17.336732 DPM_CONTROL_AFTERK: ON
8814 11:49:17.337191 PER_BANK_REFRESH: ON
8815 11:49:17.340284 REFRESH_OVERHEAD_REDUCTION: ON
8816 11:49:17.343710 CMD_PICG_NEW_MODE: OFF
8817 11:49:17.344267 XRTWTW_NEW_MODE: ON
8818 11:49:17.347007 XRTRTR_NEW_MODE: ON
8819 11:49:17.347596 TX_TRACKING: ON
8820 11:49:17.350244 RDSEL_TRACKING: OFF
8821 11:49:17.353368 DQS Precalculation for DVFS: ON
8822 11:49:17.353846 RX_TRACKING: OFF
8823 11:49:17.356850 HW_GATING DBG: ON
8824 11:49:17.357322 ZQCS_ENABLE_LP4: ON
8825 11:49:17.360012 RX_PICG_NEW_MODE: ON
8826 11:49:17.360488 TX_PICG_NEW_MODE: ON
8827 11:49:17.363270 ENABLE_RX_DCM_DPHY: ON
8828 11:49:17.366395 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8829 11:49:17.369996 DUMMY_READ_FOR_TRACKING: OFF
8830 11:49:17.373152 !!! SPM_CONTROL_AFTERK: OFF
8831 11:49:17.373671 !!! SPM could not control APHY
8832 11:49:17.376622 IMPEDANCE_TRACKING: ON
8833 11:49:17.377100 TEMP_SENSOR: ON
8834 11:49:17.380131 HW_SAVE_FOR_SR: OFF
8835 11:49:17.383257 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8836 11:49:17.386749 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8837 11:49:17.389658 Read ODT Tracking: ON
8838 11:49:17.390131 Refresh Rate DeBounce: ON
8839 11:49:17.393044 DFS_NO_QUEUE_FLUSH: ON
8840 11:49:17.396492 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8841 11:49:17.400280 ENABLE_DFS_RUNTIME_MRW: OFF
8842 11:49:17.400913 DDR_RESERVE_NEW_MODE: ON
8843 11:49:17.403156 MR_CBT_SWITCH_FREQ: ON
8844 11:49:17.406350 =========================
8845 11:49:17.423858 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8846 11:49:17.426799 dram_init: ddr_geometry: 0
8847 11:49:17.445123 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8848 11:49:17.448464 dram_init: dram init end (result: 0)
8849 11:49:17.455103 DRAM-K: Full calibration passed in 23390 msecs
8850 11:49:17.458548 MRC: failed to locate region type 0.
8851 11:49:17.459120 DRAM rank0 size:0x80000000,
8852 11:49:17.461924 DRAM rank1 size=0x80000000
8853 11:49:17.472000 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8854 11:49:17.478144 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8855 11:49:17.484718 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8856 11:49:17.491227 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8857 11:49:17.494381 DRAM rank0 size:0x80000000,
8858 11:49:17.497867 DRAM rank1 size=0x80000000
8859 11:49:17.498431 CBMEM:
8860 11:49:17.501431 IMD: root @ 0xfffff000 254 entries.
8861 11:49:17.504762 IMD: root @ 0xffffec00 62 entries.
8862 11:49:17.508022 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8863 11:49:17.511168 WARNING: RO_VPD is uninitialized or empty.
8864 11:49:17.517542 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8865 11:49:17.524802 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8866 11:49:17.537429 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8867 11:49:17.549449 BS: romstage times (exec / console): total (unknown) / 22935 ms
8868 11:49:17.550025
8869 11:49:17.550517
8870 11:49:17.558786 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8871 11:49:17.562235 ARM64: Exception handlers installed.
8872 11:49:17.565447 ARM64: Testing exception
8873 11:49:17.569074 ARM64: Done test exception
8874 11:49:17.569636 Enumerating buses...
8875 11:49:17.571985 Show all devs... Before device enumeration.
8876 11:49:17.575893 Root Device: enabled 1
8877 11:49:17.578696 CPU_CLUSTER: 0: enabled 1
8878 11:49:17.579250 CPU: 00: enabled 1
8879 11:49:17.582148 Compare with tree...
8880 11:49:17.582627 Root Device: enabled 1
8881 11:49:17.585205 CPU_CLUSTER: 0: enabled 1
8882 11:49:17.588795 CPU: 00: enabled 1
8883 11:49:17.589371 Root Device scanning...
8884 11:49:17.592149 scan_static_bus for Root Device
8885 11:49:17.595491 CPU_CLUSTER: 0 enabled
8886 11:49:17.598498 scan_static_bus for Root Device done
8887 11:49:17.602109 scan_bus: bus Root Device finished in 8 msecs
8888 11:49:17.602678 done
8889 11:49:17.608371 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8890 11:49:17.611599 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8891 11:49:17.618334 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8892 11:49:17.621784 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8893 11:49:17.625013 Allocating resources...
8894 11:49:17.628327 Reading resources...
8895 11:49:17.631752 Root Device read_resources bus 0 link: 0
8896 11:49:17.632328 DRAM rank0 size:0x80000000,
8897 11:49:17.634834 DRAM rank1 size=0x80000000
8898 11:49:17.638211 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8899 11:49:17.641281 CPU: 00 missing read_resources
8900 11:49:17.648272 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8901 11:49:17.651449 Root Device read_resources bus 0 link: 0 done
8902 11:49:17.652025 Done reading resources.
8903 11:49:17.657945 Show resources in subtree (Root Device)...After reading.
8904 11:49:17.661642 Root Device child on link 0 CPU_CLUSTER: 0
8905 11:49:17.664844 CPU_CLUSTER: 0 child on link 0 CPU: 00
8906 11:49:17.674730 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8907 11:49:17.675298 CPU: 00
8908 11:49:17.677923 Root Device assign_resources, bus 0 link: 0
8909 11:49:17.681511 CPU_CLUSTER: 0 missing set_resources
8910 11:49:17.688089 Root Device assign_resources, bus 0 link: 0 done
8911 11:49:17.688693 Done setting resources.
8912 11:49:17.694412 Show resources in subtree (Root Device)...After assigning values.
8913 11:49:17.698088 Root Device child on link 0 CPU_CLUSTER: 0
8914 11:49:17.700961 CPU_CLUSTER: 0 child on link 0 CPU: 00
8915 11:49:17.710878 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8916 11:49:17.711433 CPU: 00
8917 11:49:17.713929 Done allocating resources.
8918 11:49:17.720820 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8919 11:49:17.721284 Enabling resources...
8920 11:49:17.721649 done.
8921 11:49:17.728057 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8922 11:49:17.728644 Initializing devices...
8923 11:49:17.730839 Root Device init
8924 11:49:17.731395 init hardware done!
8925 11:49:17.733946 0x00000018: ctrlr->caps
8926 11:49:17.737268 52.000 MHz: ctrlr->f_max
8927 11:49:17.737742 0.400 MHz: ctrlr->f_min
8928 11:49:17.740541 0x40ff8080: ctrlr->voltages
8929 11:49:17.744077 sclk: 390625
8930 11:49:17.744695 Bus Width = 1
8931 11:49:17.745072 sclk: 390625
8932 11:49:17.747297 Bus Width = 1
8933 11:49:17.747848 Early init status = 3
8934 11:49:17.753669 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8935 11:49:17.757399 in-header: 03 fc 00 00 01 00 00 00
8936 11:49:17.760539 in-data: 00
8937 11:49:17.764014 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8938 11:49:17.767900 in-header: 03 fd 00 00 00 00 00 00
8939 11:49:17.771083 in-data:
8940 11:49:17.774024 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8941 11:49:17.778393 in-header: 03 fc 00 00 01 00 00 00
8942 11:49:17.781810 in-data: 00
8943 11:49:17.785083 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8944 11:49:17.790741 in-header: 03 fd 00 00 00 00 00 00
8945 11:49:17.794078 in-data:
8946 11:49:17.797355 [SSUSB] Setting up USB HOST controller...
8947 11:49:17.800705 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8948 11:49:17.804065 [SSUSB] phy power-on done.
8949 11:49:17.807350 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8950 11:49:17.813687 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8951 11:49:17.817100 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8952 11:49:17.823720 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8953 11:49:17.830449 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8954 11:49:17.836744 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8955 11:49:17.843616 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8956 11:49:17.850332 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8957 11:49:17.853385 SPM: binary array size = 0x9dc
8958 11:49:17.856957 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8959 11:49:17.863406 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8960 11:49:17.869972 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8961 11:49:17.876478 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8962 11:49:17.879745 configure_display: Starting display init
8963 11:49:17.913807 anx7625_power_on_init: Init interface.
8964 11:49:17.916884 anx7625_disable_pd_protocol: Disabled PD feature.
8965 11:49:17.920345 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8966 11:49:17.948434 anx7625_start_dp_work: Secure OCM version=00
8967 11:49:17.951542 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8968 11:49:17.966386 sp_tx_get_edid_block: EDID Block = 1
8969 11:49:18.068941 Extracted contents:
8970 11:49:18.072251 header: 00 ff ff ff ff ff ff 00
8971 11:49:18.075568 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8972 11:49:18.078706 version: 01 04
8973 11:49:18.082238 basic params: 95 1f 11 78 0a
8974 11:49:18.085508 chroma info: 76 90 94 55 54 90 27 21 50 54
8975 11:49:18.088961 established: 00 00 00
8976 11:49:18.095658 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8977 11:49:18.098869 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8978 11:49:18.105313 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8979 11:49:18.112183 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8980 11:49:18.118357 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8981 11:49:18.121722 extensions: 00
8982 11:49:18.122296 checksum: fb
8983 11:49:18.122787
8984 11:49:18.125019 Manufacturer: IVO Model 57d Serial Number 0
8985 11:49:18.128577 Made week 0 of 2020
8986 11:49:18.129150 EDID version: 1.4
8987 11:49:18.131701 Digital display
8988 11:49:18.134886 6 bits per primary color channel
8989 11:49:18.135376 DisplayPort interface
8990 11:49:18.138414 Maximum image size: 31 cm x 17 cm
8991 11:49:18.141480 Gamma: 220%
8992 11:49:18.142028 Check DPMS levels
8993 11:49:18.144702 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
8994 11:49:18.151575 First detailed timing is preferred timing
8995 11:49:18.152149 Established timings supported:
8996 11:49:18.154965 Standard timings supported:
8997 11:49:18.158181 Detailed timings
8998 11:49:18.161200 Hex of detail: 383680a07038204018303c0035ae10000019
8999 11:49:18.168057 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9000 11:49:18.171683 0780 0798 07c8 0820 hborder 0
9001 11:49:18.174740 0438 043b 0447 0458 vborder 0
9002 11:49:18.177861 -hsync -vsync
9003 11:49:18.178335 Did detailed timing
9004 11:49:18.184477 Hex of detail: 000000000000000000000000000000000000
9005 11:49:18.188073 Manufacturer-specified data, tag 0
9006 11:49:18.190968 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9007 11:49:18.194313 ASCII string: InfoVision
9008 11:49:18.197791 Hex of detail: 000000fe00523134304e574635205248200a
9009 11:49:18.201226 ASCII string: R140NWF5 RH
9010 11:49:18.201786 Checksum
9011 11:49:18.204443 Checksum: 0xfb (valid)
9012 11:49:18.207654 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9013 11:49:18.211039 DSI data_rate: 832800000 bps
9014 11:49:18.217318 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9015 11:49:18.220768 anx7625_parse_edid: pixelclock(138800).
9016 11:49:18.224365 hactive(1920), hsync(48), hfp(24), hbp(88)
9017 11:49:18.227291 vactive(1080), vsync(12), vfp(3), vbp(17)
9018 11:49:18.231149 anx7625_dsi_config: config dsi.
9019 11:49:18.237498 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9020 11:49:18.251128 anx7625_dsi_config: success to config DSI
9021 11:49:18.254296 anx7625_dp_start: MIPI phy setup OK.
9022 11:49:18.257233 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9023 11:49:18.261183 mtk_ddp_mode_set invalid vrefresh 60
9024 11:49:18.264461 main_disp_path_setup
9025 11:49:18.265086 ovl_layer_smi_id_en
9026 11:49:18.267194 ovl_layer_smi_id_en
9027 11:49:18.267854 ccorr_config
9028 11:49:18.268333 aal_config
9029 11:49:18.270823 gamma_config
9030 11:49:18.271396 postmask_config
9031 11:49:18.274281 dither_config
9032 11:49:18.277716 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9033 11:49:18.284170 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9034 11:49:18.287184 Root Device init finished in 553 msecs
9035 11:49:18.290810 CPU_CLUSTER: 0 init
9036 11:49:18.297223 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9037 11:49:18.300636 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9038 11:49:18.304093 APU_MBOX 0x190000b0 = 0x10001
9039 11:49:18.307178 APU_MBOX 0x190001b0 = 0x10001
9040 11:49:18.310533 APU_MBOX 0x190005b0 = 0x10001
9041 11:49:18.314161 APU_MBOX 0x190006b0 = 0x10001
9042 11:49:18.317012 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9043 11:49:18.329946 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9044 11:49:18.342132 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9045 11:49:18.348807 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9046 11:49:18.360651 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9047 11:49:18.369707 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9048 11:49:18.373051 CPU_CLUSTER: 0 init finished in 81 msecs
9049 11:49:18.376676 Devices initialized
9050 11:49:18.379714 Show all devs... After init.
9051 11:49:18.380191 Root Device: enabled 1
9052 11:49:18.383210 CPU_CLUSTER: 0: enabled 1
9053 11:49:18.386460 CPU: 00: enabled 1
9054 11:49:18.389599 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9055 11:49:18.392813 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9056 11:49:18.396356 ELOG: NV offset 0x57f000 size 0x1000
9057 11:49:18.402762 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9058 11:49:18.409378 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9059 11:49:18.413055 ELOG: Event(17) added with size 13 at 2023-11-24 11:49:18 UTC
9060 11:49:18.419141 out: cmd=0x121: 03 db 21 01 00 00 00 00
9061 11:49:18.422502 in-header: 03 11 00 00 2c 00 00 00
9062 11:49:18.435863 in-data: 52 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9063 11:49:18.439145 ELOG: Event(A1) added with size 10 at 2023-11-24 11:49:18 UTC
9064 11:49:18.445783 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9065 11:49:18.452145 ELOG: Event(A0) added with size 9 at 2023-11-24 11:49:18 UTC
9066 11:49:18.455505 elog_add_boot_reason: Logged dev mode boot
9067 11:49:18.462324 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9068 11:49:18.462886 Finalize devices...
9069 11:49:18.465371 Devices finalized
9070 11:49:18.468654 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9071 11:49:18.472019 Writing coreboot table at 0xffe64000
9072 11:49:18.478850 0. 000000000010a000-0000000000113fff: RAMSTAGE
9073 11:49:18.482105 1. 0000000040000000-00000000400fffff: RAM
9074 11:49:18.485754 2. 0000000040100000-000000004032afff: RAMSTAGE
9075 11:49:18.489224 3. 000000004032b000-00000000545fffff: RAM
9076 11:49:18.492328 4. 0000000054600000-000000005465ffff: BL31
9077 11:49:18.495743 5. 0000000054660000-00000000ffe63fff: RAM
9078 11:49:18.502296 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9079 11:49:18.505885 7. 0000000100000000-000000013fffffff: RAM
9080 11:49:18.509110 Passing 5 GPIOs to payload:
9081 11:49:18.512380 NAME | PORT | POLARITY | VALUE
9082 11:49:18.518867 EC in RW | 0x000000aa | low | undefined
9083 11:49:18.522115 EC interrupt | 0x00000005 | low | undefined
9084 11:49:18.525185 TPM interrupt | 0x000000ab | high | undefined
9085 11:49:18.531930 SD card detect | 0x00000011 | high | undefined
9086 11:49:18.535279 speaker enable | 0x00000093 | high | undefined
9087 11:49:18.538587 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9088 11:49:18.541983 in-header: 03 f8 00 00 02 00 00 00
9089 11:49:18.545299 in-data: 03 00
9090 11:49:18.548457 ADC[4]: Raw value=668958 ID=5
9091 11:49:18.551866 ADC[3]: Raw value=212917 ID=1
9092 11:49:18.552419 RAM Code: 0x51
9093 11:49:18.555067 ADC[6]: Raw value=74778 ID=0
9094 11:49:18.558532 ADC[5]: Raw value=211444 ID=1
9095 11:49:18.559089 SKU Code: 0x1
9096 11:49:18.564925 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7ea
9097 11:49:18.565488 coreboot table: 964 bytes.
9098 11:49:18.567972 IMD ROOT 0. 0xfffff000 0x00001000
9099 11:49:18.571654 IMD SMALL 1. 0xffffe000 0x00001000
9100 11:49:18.574788 RO MCACHE 2. 0xffffc000 0x00001104
9101 11:49:18.577861 CONSOLE 3. 0xfff7c000 0x00080000
9102 11:49:18.581142 FMAP 4. 0xfff7b000 0x00000452
9103 11:49:18.584768 TIME STAMP 5. 0xfff7a000 0x00000910
9104 11:49:18.588091 VBOOT WORK 6. 0xfff66000 0x00014000
9105 11:49:18.591429 RAMOOPS 7. 0xffe66000 0x00100000
9106 11:49:18.594420 COREBOOT 8. 0xffe64000 0x00002000
9107 11:49:18.598012 IMD small region:
9108 11:49:18.601046 IMD ROOT 0. 0xffffec00 0x00000400
9109 11:49:18.604291 VPD 1. 0xffffeb80 0x0000006c
9110 11:49:18.607779 MMC STATUS 2. 0xffffeb60 0x00000004
9111 11:49:18.611172 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9112 11:49:18.614191 Probing TPM: done!
9113 11:49:18.620985 Connected to device vid:did:rid of 1ae0:0028:00
9114 11:49:18.627781 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9115 11:49:18.631454 Initialized TPM device CR50 revision 0
9116 11:49:18.634541 Checking cr50 for pending updates
9117 11:49:18.639605 Reading cr50 TPM mode
9118 11:49:18.648437 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9119 11:49:18.655052 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9120 11:49:18.695070 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9121 11:49:18.698105 Checking segment from ROM address 0x40100000
9122 11:49:18.701572 Checking segment from ROM address 0x4010001c
9123 11:49:18.708333 Loading segment from ROM address 0x40100000
9124 11:49:18.708965 code (compression=0)
9125 11:49:18.718554 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9126 11:49:18.725024 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9127 11:49:18.725507 it's not compressed!
9128 11:49:18.732052 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9129 11:49:18.734817 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9130 11:49:18.755564 Loading segment from ROM address 0x4010001c
9131 11:49:18.756138 Entry Point 0x80000000
9132 11:49:18.758906 Loaded segments
9133 11:49:18.762158 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9134 11:49:18.769084 Jumping to boot code at 0x80000000(0xffe64000)
9135 11:49:18.775728 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9136 11:49:18.782360 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9137 11:49:18.790379 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9138 11:49:18.793551 Checking segment from ROM address 0x40100000
9139 11:49:18.796501 Checking segment from ROM address 0x4010001c
9140 11:49:18.803283 Loading segment from ROM address 0x40100000
9141 11:49:18.803834 code (compression=1)
9142 11:49:18.810014 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9143 11:49:18.819762 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9144 11:49:18.820350 using LZMA
9145 11:49:18.828262 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9146 11:49:18.834998 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9147 11:49:18.838219 Loading segment from ROM address 0x4010001c
9148 11:49:18.838782 Entry Point 0x54601000
9149 11:49:18.841371 Loaded segments
9150 11:49:18.844793 NOTICE: MT8192 bl31_setup
9151 11:49:18.851957 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9152 11:49:18.855406 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9153 11:49:18.858391 WARNING: region 0:
9154 11:49:18.862019 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9155 11:49:18.862574 WARNING: region 1:
9156 11:49:18.868308 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9157 11:49:18.872190 WARNING: region 2:
9158 11:49:18.875357 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9159 11:49:18.878653 WARNING: region 3:
9160 11:49:18.881946 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9161 11:49:18.885611 WARNING: region 4:
9162 11:49:18.892301 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9163 11:49:18.892931 WARNING: region 5:
9164 11:49:18.895133 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9165 11:49:18.898657 WARNING: region 6:
9166 11:49:18.901825 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9167 11:49:18.905236 WARNING: region 7:
9168 11:49:18.908654 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9169 11:49:18.915114 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9170 11:49:18.918731 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9171 11:49:18.921893 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9172 11:49:18.928639 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9173 11:49:18.932204 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9174 11:49:18.935162 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9175 11:49:18.941947 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9176 11:49:18.945069 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9177 11:49:18.951860 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9178 11:49:18.955222 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9179 11:49:18.958724 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9180 11:49:18.965405 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9181 11:49:18.968852 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9182 11:49:18.971817 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9183 11:49:18.978500 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9184 11:49:18.981640 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9185 11:49:18.988652 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9186 11:49:18.991841 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9187 11:49:18.995126 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9188 11:49:19.001531 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9189 11:49:19.004973 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9190 11:49:19.008682 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9191 11:49:19.014864 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9192 11:49:19.018135 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9193 11:49:19.024965 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9194 11:49:19.028348 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9195 11:49:19.031809 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9196 11:49:19.038492 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9197 11:49:19.041840 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9198 11:49:19.048559 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9199 11:49:19.051872 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9200 11:49:19.055061 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9201 11:49:19.061643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9202 11:49:19.064966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9203 11:49:19.068683 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9204 11:49:19.071725 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9205 11:49:19.078262 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9206 11:49:19.081584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9207 11:49:19.084902 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9208 11:49:19.088231 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9209 11:49:19.094871 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9210 11:49:19.098165 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9211 11:49:19.101473 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9212 11:49:19.104969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9213 11:49:19.111362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9214 11:49:19.114909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9215 11:49:19.118224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9216 11:49:19.121667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9217 11:49:19.127944 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9218 11:49:19.131433 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9219 11:49:19.138164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9220 11:49:19.141240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9221 11:49:19.148201 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9222 11:49:19.151204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9223 11:49:19.154758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9224 11:49:19.161470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9225 11:49:19.165016 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9226 11:49:19.171523 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9227 11:49:19.174889 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9228 11:49:19.181529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9229 11:49:19.184966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9230 11:49:19.188236 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9231 11:49:19.194692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9232 11:49:19.197983 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9233 11:49:19.204917 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9234 11:49:19.208135 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9235 11:49:19.214880 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9236 11:49:19.218291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9237 11:49:19.221363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9238 11:49:19.228015 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9239 11:49:19.231380 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9240 11:49:19.238230 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9241 11:49:19.241121 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9242 11:49:19.248105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9243 11:49:19.251356 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9244 11:49:19.257782 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9245 11:49:19.261254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9246 11:49:19.264434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9247 11:49:19.271159 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9248 11:49:19.274543 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9249 11:49:19.281328 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9250 11:49:19.284678 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9251 11:49:19.291347 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9252 11:49:19.294597 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9253 11:49:19.298155 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9254 11:49:19.304883 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9255 11:49:19.308129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9256 11:49:19.314699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9257 11:49:19.318036 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9258 11:49:19.321649 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9259 11:49:19.327812 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9260 11:49:19.331569 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9261 11:49:19.338071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9262 11:49:19.341719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9263 11:49:19.348261 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9264 11:49:19.351150 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9265 11:49:19.354791 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9266 11:49:19.361527 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9267 11:49:19.365160 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9268 11:49:19.368225 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9269 11:49:19.371029 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9270 11:49:19.378064 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9271 11:49:19.381230 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9272 11:49:19.387787 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9273 11:49:19.391341 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9274 11:49:19.394738 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9275 11:49:19.401055 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9276 11:49:19.404878 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9277 11:49:19.411264 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9278 11:49:19.414906 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9279 11:49:19.418134 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9280 11:49:19.424974 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9281 11:49:19.428206 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9282 11:49:19.434621 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9283 11:49:19.437914 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9284 11:49:19.441110 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9285 11:49:19.447803 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9286 11:49:19.451189 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9287 11:49:19.454468 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9288 11:49:19.457772 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9289 11:49:19.464490 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9290 11:49:19.467833 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9291 11:49:19.470840 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9292 11:49:19.474327 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9293 11:49:19.480954 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9294 11:49:19.484477 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9295 11:49:19.491014 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9296 11:49:19.494234 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9297 11:49:19.497739 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9298 11:49:19.504749 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9299 11:49:19.507723 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9300 11:49:19.514564 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9301 11:49:19.517622 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9302 11:49:19.521100 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9303 11:49:19.527609 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9304 11:49:19.531106 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9305 11:49:19.537689 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9306 11:49:19.541296 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9307 11:49:19.544268 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9308 11:49:19.550819 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9309 11:49:19.554313 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9310 11:49:19.557592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9311 11:49:19.564432 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9312 11:49:19.567581 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9313 11:49:19.574331 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9314 11:49:19.577590 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9315 11:49:19.580927 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9316 11:49:19.587684 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9317 11:49:19.590974 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9318 11:49:19.597544 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9319 11:49:19.600924 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9320 11:49:19.604215 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9321 11:49:19.611201 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9322 11:49:19.614502 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9323 11:49:19.617544 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9324 11:49:19.624423 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9325 11:49:19.627712 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9326 11:49:19.634393 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9327 11:49:19.637574 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9328 11:49:19.641198 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9329 11:49:19.647706 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9330 11:49:19.650978 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9331 11:49:19.657478 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9332 11:49:19.660885 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9333 11:49:19.664310 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9334 11:49:19.670757 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9335 11:49:19.673917 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9336 11:49:19.680649 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9337 11:49:19.684139 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9338 11:49:19.687675 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9339 11:49:19.693950 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9340 11:49:19.697038 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9341 11:49:19.700594 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9342 11:49:19.707460 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9343 11:49:19.710715 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9344 11:49:19.717214 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9345 11:49:19.720763 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9346 11:49:19.723901 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9347 11:49:19.730560 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9348 11:49:19.734136 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9349 11:49:19.740600 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9350 11:49:19.743969 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9351 11:49:19.747495 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9352 11:49:19.753872 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9353 11:49:19.757162 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9354 11:49:19.763680 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9355 11:49:19.767121 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9356 11:49:19.769987 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9357 11:49:19.776985 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9358 11:49:19.780125 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9359 11:49:19.786742 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9360 11:49:19.790233 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9361 11:49:19.796557 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9362 11:49:19.800083 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9363 11:49:19.803150 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9364 11:49:19.809986 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9365 11:49:19.813146 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9366 11:49:19.819862 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9367 11:49:19.822969 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9368 11:49:19.829754 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9369 11:49:19.832637 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9370 11:49:19.836557 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9371 11:49:19.843132 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9372 11:49:19.846010 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9373 11:49:19.852653 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9374 11:49:19.856211 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9375 11:49:19.859594 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9376 11:49:19.866075 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9377 11:49:19.869107 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9378 11:49:19.876011 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9379 11:49:19.879478 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9380 11:49:19.885992 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9381 11:49:19.889128 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9382 11:49:19.892580 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9383 11:49:19.899352 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9384 11:49:19.902347 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9385 11:49:19.909155 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9386 11:49:19.912038 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9387 11:49:19.918724 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9388 11:49:19.922328 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9389 11:49:19.925489 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9390 11:49:19.931904 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9391 11:49:19.935397 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9392 11:49:19.941873 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9393 11:49:19.945106 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9394 11:49:19.951920 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9395 11:49:19.955247 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9396 11:49:19.958553 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9397 11:49:19.965326 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9398 11:49:19.968551 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9399 11:49:19.971669 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9400 11:49:19.975341 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9401 11:49:19.981723 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9402 11:49:19.985097 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9403 11:49:19.988459 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9404 11:49:19.995076 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9405 11:49:19.998272 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9406 11:49:20.001667 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9407 11:49:20.008434 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9408 11:49:20.011398 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9409 11:49:20.018178 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9410 11:49:20.021508 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9411 11:49:20.024744 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9412 11:49:20.031452 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9413 11:49:20.034957 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9414 11:49:20.037954 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9415 11:49:20.044811 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9416 11:49:20.047718 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9417 11:49:20.051170 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9418 11:49:20.057831 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9419 11:49:20.060911 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9420 11:49:20.067637 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9421 11:49:20.070720 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9422 11:49:20.074109 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9423 11:49:20.080728 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9424 11:49:20.084209 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9425 11:49:20.090787 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9426 11:49:20.094058 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9427 11:49:20.097248 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9428 11:49:20.104176 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9429 11:49:20.107405 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9430 11:49:20.110720 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9431 11:49:20.117254 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9432 11:49:20.121042 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9433 11:49:20.124233 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9434 11:49:20.130417 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9435 11:49:20.133820 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9436 11:49:20.140370 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9437 11:49:20.143771 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9438 11:49:20.146916 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9439 11:49:20.150620 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9440 11:49:20.157295 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9441 11:49:20.160050 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9442 11:49:20.163664 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9443 11:49:20.167083 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9444 11:49:20.169972 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9445 11:49:20.176616 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9446 11:49:20.180479 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9447 11:49:20.183244 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9448 11:49:20.186919 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9449 11:49:20.193488 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9450 11:49:20.196951 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9451 11:49:20.203263 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9452 11:49:20.206539 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9453 11:49:20.210176 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9454 11:49:20.216314 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9455 11:49:20.219936 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9456 11:49:20.226403 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9457 11:49:20.229512 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9458 11:49:20.232801 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9459 11:49:20.239862 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9460 11:49:20.243196 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9461 11:49:20.249733 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9462 11:49:20.252917 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9463 11:49:20.259590 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9464 11:49:20.262926 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9465 11:49:20.266367 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9466 11:49:20.272733 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9467 11:49:20.275835 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9468 11:49:20.282541 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9469 11:49:20.285814 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9470 11:49:20.289329 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9471 11:49:20.296197 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9472 11:49:20.299371 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9473 11:49:20.306190 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9474 11:49:20.309468 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9475 11:49:20.312676 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9476 11:49:20.319041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9477 11:49:20.322627 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9478 11:49:20.329449 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9479 11:49:20.332334 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9480 11:49:20.338890 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9481 11:49:20.342610 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9482 11:49:20.345669 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9483 11:49:20.352359 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9484 11:49:20.355780 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9485 11:49:20.362161 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9486 11:49:20.365860 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9487 11:49:20.368706 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9488 11:49:20.375359 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9489 11:49:20.378803 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9490 11:49:20.385314 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9491 11:49:20.388951 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9492 11:49:20.392154 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9493 11:49:20.398338 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9494 11:49:20.401813 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9495 11:49:20.408305 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9496 11:49:20.411603 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9497 11:49:20.418573 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9498 11:49:20.421443 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9499 11:49:20.424940 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9500 11:49:20.431608 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9501 11:49:20.434920 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9502 11:49:20.441439 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9503 11:49:20.444685 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9504 11:49:20.451308 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9505 11:49:20.454503 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9506 11:49:20.458081 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9507 11:49:20.464903 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9508 11:49:20.467939 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9509 11:49:20.474226 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9510 11:49:20.477704 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9511 11:49:20.480982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9512 11:49:20.487745 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9513 11:49:20.490852 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9514 11:49:20.497484 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9515 11:49:20.500881 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9516 11:49:20.503860 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9517 11:49:20.510935 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9518 11:49:20.514138 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9519 11:49:20.520729 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9520 11:49:20.523990 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9521 11:49:20.530511 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9522 11:49:20.533720 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9523 11:49:20.536976 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9524 11:49:20.544198 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9525 11:49:20.547209 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9526 11:49:20.553549 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9527 11:49:20.557234 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9528 11:49:20.563597 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9529 11:49:20.567171 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9530 11:49:20.570089 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9531 11:49:20.576922 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9532 11:49:20.580107 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9533 11:49:20.586877 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9534 11:49:20.590026 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9535 11:49:20.596686 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9536 11:49:20.599768 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9537 11:49:20.606649 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9538 11:49:20.609903 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9539 11:49:20.613005 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9540 11:49:20.620025 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9541 11:49:20.623060 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9542 11:49:20.629628 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9543 11:49:20.633071 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9544 11:49:20.639461 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9545 11:49:20.642749 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9546 11:49:20.646071 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9547 11:49:20.652500 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9548 11:49:20.656017 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9549 11:49:20.662644 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9550 11:49:20.665970 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9551 11:49:20.672520 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9552 11:49:20.675900 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9553 11:49:20.682554 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9554 11:49:20.685684 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9555 11:49:20.689329 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9556 11:49:20.696032 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9557 11:49:20.699259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9558 11:49:20.706055 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9559 11:49:20.709475 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9560 11:49:20.716129 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9561 11:49:20.719212 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9562 11:49:20.722376 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9563 11:49:20.729431 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9564 11:49:20.732460 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9565 11:49:20.738905 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9566 11:49:20.742566 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9567 11:49:20.749250 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9568 11:49:20.752391 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9569 11:49:20.759304 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9570 11:49:20.762159 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9571 11:49:20.765511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9572 11:49:20.772567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9573 11:49:20.775681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9574 11:49:20.782527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9575 11:49:20.785383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9576 11:49:20.792096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9577 11:49:20.795550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9578 11:49:20.802155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9579 11:49:20.805464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9580 11:49:20.812047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9581 11:49:20.815813 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9582 11:49:20.818738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9583 11:49:20.825294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9584 11:49:20.828477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9585 11:49:20.835280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9586 11:49:20.838593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9587 11:49:20.844957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9588 11:49:20.848785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9589 11:49:20.855277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9590 11:49:20.858675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9591 11:49:20.865298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9592 11:49:20.868322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9593 11:49:20.874957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9594 11:49:20.878435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9595 11:49:20.884742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9596 11:49:20.888225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9597 11:49:20.894770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9598 11:49:20.898193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9599 11:49:20.904796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9600 11:49:20.908109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9601 11:49:20.915087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9602 11:49:20.918253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9603 11:49:20.924765 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9604 11:49:20.925330 INFO: [APUAPC] vio 0
9605 11:49:20.931610 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9606 11:49:20.935177 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9607 11:49:20.938606 INFO: [APUAPC] D0_APC_0: 0x400510
9608 11:49:20.941873 INFO: [APUAPC] D0_APC_1: 0x0
9609 11:49:20.945115 INFO: [APUAPC] D0_APC_2: 0x1540
9610 11:49:20.948262 INFO: [APUAPC] D0_APC_3: 0x0
9611 11:49:20.951588 INFO: [APUAPC] D1_APC_0: 0xffffffff
9612 11:49:20.955222 INFO: [APUAPC] D1_APC_1: 0xffffffff
9613 11:49:20.958431 INFO: [APUAPC] D1_APC_2: 0x3fffff
9614 11:49:20.961629 INFO: [APUAPC] D1_APC_3: 0x0
9615 11:49:20.965182 INFO: [APUAPC] D2_APC_0: 0xffffffff
9616 11:49:20.968214 INFO: [APUAPC] D2_APC_1: 0xffffffff
9617 11:49:20.971593 INFO: [APUAPC] D2_APC_2: 0x3fffff
9618 11:49:20.974790 INFO: [APUAPC] D2_APC_3: 0x0
9619 11:49:20.978435 INFO: [APUAPC] D3_APC_0: 0xffffffff
9620 11:49:20.981476 INFO: [APUAPC] D3_APC_1: 0xffffffff
9621 11:49:20.985013 INFO: [APUAPC] D3_APC_2: 0x3fffff
9622 11:49:20.988119 INFO: [APUAPC] D3_APC_3: 0x0
9623 11:49:20.991332 INFO: [APUAPC] D4_APC_0: 0xffffffff
9624 11:49:20.994949 INFO: [APUAPC] D4_APC_1: 0xffffffff
9625 11:49:20.998578 INFO: [APUAPC] D4_APC_2: 0x3fffff
9626 11:49:20.999159 INFO: [APUAPC] D4_APC_3: 0x0
9627 11:49:21.001118 INFO: [APUAPC] D5_APC_0: 0xffffffff
9628 11:49:21.008078 INFO: [APUAPC] D5_APC_1: 0xffffffff
9629 11:49:21.011476 INFO: [APUAPC] D5_APC_2: 0x3fffff
9630 11:49:21.011961 INFO: [APUAPC] D5_APC_3: 0x0
9631 11:49:21.014535 INFO: [APUAPC] D6_APC_0: 0xffffffff
9632 11:49:21.017884 INFO: [APUAPC] D6_APC_1: 0xffffffff
9633 11:49:21.021287 INFO: [APUAPC] D6_APC_2: 0x3fffff
9634 11:49:21.024283 INFO: [APUAPC] D6_APC_3: 0x0
9635 11:49:21.027999 INFO: [APUAPC] D7_APC_0: 0xffffffff
9636 11:49:21.031142 INFO: [APUAPC] D7_APC_1: 0xffffffff
9637 11:49:21.034200 INFO: [APUAPC] D7_APC_2: 0x3fffff
9638 11:49:21.037709 INFO: [APUAPC] D7_APC_3: 0x0
9639 11:49:21.041083 INFO: [APUAPC] D8_APC_0: 0xffffffff
9640 11:49:21.044320 INFO: [APUAPC] D8_APC_1: 0xffffffff
9641 11:49:21.047772 INFO: [APUAPC] D8_APC_2: 0x3fffff
9642 11:49:21.051042 INFO: [APUAPC] D8_APC_3: 0x0
9643 11:49:21.054451 INFO: [APUAPC] D9_APC_0: 0xffffffff
9644 11:49:21.057546 INFO: [APUAPC] D9_APC_1: 0xffffffff
9645 11:49:21.061057 INFO: [APUAPC] D9_APC_2: 0x3fffff
9646 11:49:21.064183 INFO: [APUAPC] D9_APC_3: 0x0
9647 11:49:21.067743 INFO: [APUAPC] D10_APC_0: 0xffffffff
9648 11:49:21.070621 INFO: [APUAPC] D10_APC_1: 0xffffffff
9649 11:49:21.074049 INFO: [APUAPC] D10_APC_2: 0x3fffff
9650 11:49:21.077234 INFO: [APUAPC] D10_APC_3: 0x0
9651 11:49:21.081068 INFO: [APUAPC] D11_APC_0: 0xffffffff
9652 11:49:21.083909 INFO: [APUAPC] D11_APC_1: 0xffffffff
9653 11:49:21.087123 INFO: [APUAPC] D11_APC_2: 0x3fffff
9654 11:49:21.090400 INFO: [APUAPC] D11_APC_3: 0x0
9655 11:49:21.094309 INFO: [APUAPC] D12_APC_0: 0xffffffff
9656 11:49:21.097432 INFO: [APUAPC] D12_APC_1: 0xffffffff
9657 11:49:21.100705 INFO: [APUAPC] D12_APC_2: 0x3fffff
9658 11:49:21.104235 INFO: [APUAPC] D12_APC_3: 0x0
9659 11:49:21.107408 INFO: [APUAPC] D13_APC_0: 0xffffffff
9660 11:49:21.110438 INFO: [APUAPC] D13_APC_1: 0xffffffff
9661 11:49:21.114120 INFO: [APUAPC] D13_APC_2: 0x3fffff
9662 11:49:21.117231 INFO: [APUAPC] D13_APC_3: 0x0
9663 11:49:21.120389 INFO: [APUAPC] D14_APC_0: 0xffffffff
9664 11:49:21.123721 INFO: [APUAPC] D14_APC_1: 0xffffffff
9665 11:49:21.127440 INFO: [APUAPC] D14_APC_2: 0x3fffff
9666 11:49:21.130141 INFO: [APUAPC] D14_APC_3: 0x0
9667 11:49:21.133485 INFO: [APUAPC] D15_APC_0: 0xffffffff
9668 11:49:21.136880 INFO: [APUAPC] D15_APC_1: 0xffffffff
9669 11:49:21.140038 INFO: [APUAPC] D15_APC_2: 0x3fffff
9670 11:49:21.143864 INFO: [APUAPC] D15_APC_3: 0x0
9671 11:49:21.147089 INFO: [APUAPC] APC_CON: 0x4
9672 11:49:21.150003 INFO: [NOCDAPC] D0_APC_0: 0x0
9673 11:49:21.153233 INFO: [NOCDAPC] D0_APC_1: 0x0
9674 11:49:21.156948 INFO: [NOCDAPC] D1_APC_0: 0x0
9675 11:49:21.160123 INFO: [NOCDAPC] D1_APC_1: 0xfff
9676 11:49:21.163197 INFO: [NOCDAPC] D2_APC_0: 0x0
9677 11:49:21.166686 INFO: [NOCDAPC] D2_APC_1: 0xfff
9678 11:49:21.167260 INFO: [NOCDAPC] D3_APC_0: 0x0
9679 11:49:21.169951 INFO: [NOCDAPC] D3_APC_1: 0xfff
9680 11:49:21.173354 INFO: [NOCDAPC] D4_APC_0: 0x0
9681 11:49:21.176491 INFO: [NOCDAPC] D4_APC_1: 0xfff
9682 11:49:21.179858 INFO: [NOCDAPC] D5_APC_0: 0x0
9683 11:49:21.183324 INFO: [NOCDAPC] D5_APC_1: 0xfff
9684 11:49:21.186336 INFO: [NOCDAPC] D6_APC_0: 0x0
9685 11:49:21.190054 INFO: [NOCDAPC] D6_APC_1: 0xfff
9686 11:49:21.193183 INFO: [NOCDAPC] D7_APC_0: 0x0
9687 11:49:21.197047 INFO: [NOCDAPC] D7_APC_1: 0xfff
9688 11:49:21.200002 INFO: [NOCDAPC] D8_APC_0: 0x0
9689 11:49:21.200618 INFO: [NOCDAPC] D8_APC_1: 0xfff
9690 11:49:21.203491 INFO: [NOCDAPC] D9_APC_0: 0x0
9691 11:49:21.206384 INFO: [NOCDAPC] D9_APC_1: 0xfff
9692 11:49:21.209612 INFO: [NOCDAPC] D10_APC_0: 0x0
9693 11:49:21.213375 INFO: [NOCDAPC] D10_APC_1: 0xfff
9694 11:49:21.216800 INFO: [NOCDAPC] D11_APC_0: 0x0
9695 11:49:21.219712 INFO: [NOCDAPC] D11_APC_1: 0xfff
9696 11:49:21.223046 INFO: [NOCDAPC] D12_APC_0: 0x0
9697 11:49:21.226204 INFO: [NOCDAPC] D12_APC_1: 0xfff
9698 11:49:21.229851 INFO: [NOCDAPC] D13_APC_0: 0x0
9699 11:49:21.233197 INFO: [NOCDAPC] D13_APC_1: 0xfff
9700 11:49:21.236162 INFO: [NOCDAPC] D14_APC_0: 0x0
9701 11:49:21.239671 INFO: [NOCDAPC] D14_APC_1: 0xfff
9702 11:49:21.243178 INFO: [NOCDAPC] D15_APC_0: 0x0
9703 11:49:21.246115 INFO: [NOCDAPC] D15_APC_1: 0xfff
9704 11:49:21.246649 INFO: [NOCDAPC] APC_CON: 0x4
9705 11:49:21.249441 INFO: [APUAPC] set_apusys_apc done
9706 11:49:21.252932 INFO: [DEVAPC] devapc_init done
9707 11:49:21.259567 INFO: GICv3 without legacy support detected.
9708 11:49:21.262837 INFO: ARM GICv3 driver initialized in EL3
9709 11:49:21.266206 INFO: Maximum SPI INTID supported: 639
9710 11:49:21.269365 INFO: BL31: Initializing runtime services
9711 11:49:21.275858 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9712 11:49:21.279558 INFO: SPM: enable CPC mode
9713 11:49:21.282872 INFO: mcdi ready for mcusys-off-idle and system suspend
9714 11:49:21.289457 INFO: BL31: Preparing for EL3 exit to normal world
9715 11:49:21.292269 INFO: Entry point address = 0x80000000
9716 11:49:21.292785 INFO: SPSR = 0x8
9717 11:49:21.299740
9718 11:49:21.300305
9719 11:49:21.300714
9720 11:49:21.303115 Starting depthcharge on Spherion...
9721 11:49:21.303671
9722 11:49:21.304037 Wipe memory regions:
9723 11:49:21.304375
9724 11:49:21.307266 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9725 11:49:21.307838 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9726 11:49:21.308283 Setting prompt string to ['asurada:']
9727 11:49:21.308761 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9728 11:49:21.309489 [0x00000040000000, 0x00000054600000)
9729 11:49:21.429173
9730 11:49:21.429736 [0x00000054660000, 0x00000080000000)
9731 11:49:21.689178
9732 11:49:21.689739 [0x000000821a7280, 0x000000ffe64000)
9733 11:49:22.434187
9734 11:49:22.434746 [0x00000100000000, 0x00000140000000)
9735 11:49:22.815120
9736 11:49:22.819186 Initializing XHCI USB controller at 0x11200000.
9737 11:49:23.856103
9738 11:49:23.859245 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9739 11:49:23.859808
9740 11:49:23.860282
9741 11:49:23.860691
9742 11:49:23.861484 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9744 11:49:23.962904 asurada: tftpboot 192.168.201.1 12074062/tftp-deploy-yu09ioqk/kernel/image.itb 12074062/tftp-deploy-yu09ioqk/kernel/cmdline
9745 11:49:23.963560 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9746 11:49:23.964185 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9747 11:49:23.968333 tftpboot 192.168.201.1 12074062/tftp-deploy-yu09ioqk/kernel/image.itp-deploy-yu09ioqk/kernel/cmdline
9748 11:49:23.968875
9749 11:49:23.969247 Waiting for link
9750 11:49:24.129166
9751 11:49:24.129783 R8152: Initializing
9752 11:49:24.130173
9753 11:49:24.132190 Version 9 (ocp_data = 6010)
9754 11:49:24.132807
9755 11:49:24.135456 R8152: Done initializing
9756 11:49:24.136013
9757 11:49:24.136381 Adding net device
9758 11:49:26.143859
9759 11:49:26.144419 done.
9760 11:49:26.144856
9761 11:49:26.145203 MAC: 00:e0:4c:68:03:bd
9762 11:49:26.145531
9763 11:49:26.146864 Sending DHCP discover... done.
9764 11:49:26.147324
9765 11:49:35.865550 Waiting for reply... R8152: Bulk read error 0xffffffbf
9766 11:49:35.866126
9767 11:49:35.868694 Receive failed.
9768 11:49:35.869164
9769 11:49:35.869536 done.
9770 11:49:35.869880
9771 11:49:35.872253 Sending DHCP request... done.
9772 11:49:35.872868
9773 11:49:35.879394 Waiting for reply... done.
9774 11:49:35.880022
9775 11:49:35.880399 My ip is 192.168.201.16
9776 11:49:35.880805
9777 11:49:35.882653 The DHCP server ip is 192.168.201.1
9778 11:49:35.883228
9779 11:49:35.889185 TFTP server IP predefined by user: 192.168.201.1
9780 11:49:35.889746
9781 11:49:35.896035 Bootfile predefined by user: 12074062/tftp-deploy-yu09ioqk/kernel/image.itb
9782 11:49:35.896831
9783 11:49:35.898886 Sending tftp read request... done.
9784 11:49:35.899357
9785 11:49:35.905609 Waiting for the transfer...
9786 11:49:35.906170
9787 11:49:36.180908 00000000 ################################################################
9788 11:49:36.181057
9789 11:49:36.452464 00080000 ################################################################
9790 11:49:36.452643
9791 11:49:36.732482 00100000 ################################################################
9792 11:49:36.732652
9793 11:49:36.999647 00180000 ################################################################
9794 11:49:36.999781
9795 11:49:37.272205 00200000 ################################################################
9796 11:49:37.272341
9797 11:49:37.557610 00280000 ################################################################
9798 11:49:37.557746
9799 11:49:37.844981 00300000 ################################################################
9800 11:49:37.845130
9801 11:49:38.125691 00380000 ################################################################
9802 11:49:38.125823
9803 11:49:38.387073 00400000 ################################################################
9804 11:49:38.387195
9805 11:49:38.658618 00480000 ################################################################
9806 11:49:38.658755
9807 11:49:38.949468 00500000 ################################################################
9808 11:49:38.949602
9809 11:49:39.201879 00580000 ################################################################
9810 11:49:39.202004
9811 11:49:39.475104 00600000 ################################################################
9812 11:49:39.475233
9813 11:49:39.764785 00680000 ################################################################
9814 11:49:39.764917
9815 11:49:40.027592 00700000 ################################################################
9816 11:49:40.027721
9817 11:49:40.324581 00780000 ################################################################
9818 11:49:40.324760
9819 11:49:40.603672 00800000 ################################################################
9820 11:49:40.603828
9821 11:49:40.896517 00880000 ################################################################
9822 11:49:40.896655
9823 11:49:41.191437 00900000 ################################################################
9824 11:49:41.191574
9825 11:49:41.488182 00980000 ################################################################
9826 11:49:41.488328
9827 11:49:41.744274 00a00000 ################################################################
9828 11:49:41.744408
9829 11:49:42.038340 00a80000 ################################################################
9830 11:49:42.038476
9831 11:49:42.335280 00b00000 ################################################################
9832 11:49:42.335412
9833 11:49:42.630083 00b80000 ################################################################
9834 11:49:42.630216
9835 11:49:42.924537 00c00000 ################################################################
9836 11:49:42.924673
9837 11:49:43.219381 00c80000 ################################################################
9838 11:49:43.219529
9839 11:49:43.513560 00d00000 ################################################################
9840 11:49:43.513694
9841 11:49:43.811562 00d80000 ################################################################
9842 11:49:43.811696
9843 11:49:44.099975 00e00000 ################################################################
9844 11:49:44.100113
9845 11:49:44.389837 00e80000 ################################################################
9846 11:49:44.389970
9847 11:49:44.677566 00f00000 ################################################################
9848 11:49:44.677697
9849 11:49:44.969680 00f80000 ################################################################
9850 11:49:44.969811
9851 11:49:45.263725 01000000 ################################################################
9852 11:49:45.263864
9853 11:49:45.561604 01080000 ################################################################
9854 11:49:45.561740
9855 11:49:45.854020 01100000 ################################################################
9856 11:49:45.854150
9857 11:49:46.140798 01180000 ################################################################
9858 11:49:46.140937
9859 11:49:46.434727 01200000 ################################################################
9860 11:49:46.434867
9861 11:49:46.722875 01280000 ################################################################
9862 11:49:46.723029
9863 11:49:47.015877 01300000 ################################################################
9864 11:49:47.016038
9865 11:49:47.308831 01380000 ################################################################
9866 11:49:47.308991
9867 11:49:47.605718 01400000 ################################################################
9868 11:49:47.605850
9869 11:49:47.898428 01480000 ################################################################
9870 11:49:47.898561
9871 11:49:48.183295 01500000 ################################################################
9872 11:49:48.183457
9873 11:49:48.477056 01580000 ################################################################
9874 11:49:48.477194
9875 11:49:48.756353 01600000 ################################################################
9876 11:49:48.756482
9877 11:49:49.030379 01680000 ################################################################
9878 11:49:49.030510
9879 11:49:49.299956 01700000 ################################################################
9880 11:49:49.300083
9881 11:49:49.589700 01780000 ################################################################
9882 11:49:49.589836
9883 11:49:49.880534 01800000 ################################################################
9884 11:49:49.880740
9885 11:49:50.158673 01880000 ################################################################
9886 11:49:50.158806
9887 11:49:50.452770 01900000 ################################################################
9888 11:49:50.452904
9889 11:49:50.734047 01980000 ################################################################
9890 11:49:50.734193
9891 11:49:50.999303 01a00000 ################################################################
9892 11:49:50.999433
9893 11:49:51.277733 01a80000 ################################################################
9894 11:49:51.277913
9895 11:49:51.555042 01b00000 ################################################################
9896 11:49:51.555171
9897 11:49:51.851338 01b80000 ################################################################
9898 11:49:51.851485
9899 11:49:52.139473 01c00000 ################################################################
9900 11:49:52.139615
9901 11:49:52.407805 01c80000 ################################################################
9902 11:49:52.407939
9903 11:49:52.672630 01d00000 ################################################################
9904 11:49:52.672762
9905 11:49:52.932360 01d80000 ################################################################
9906 11:49:52.932528
9907 11:49:53.204175 01e00000 ################################################################
9908 11:49:53.204308
9909 11:49:53.489696 01e80000 ################################################################
9910 11:49:53.489828
9911 11:49:53.786984 01f00000 ################################################################
9912 11:49:53.787118
9913 11:49:54.080462 01f80000 ################################################################
9914 11:49:54.080635
9915 11:49:54.373144 02000000 ################################################################
9916 11:49:54.373275
9917 11:49:54.666029 02080000 ################################################################
9918 11:49:54.666161
9919 11:49:54.953345 02100000 ################################################################
9920 11:49:54.953480
9921 11:49:55.236420 02180000 ################################################################
9922 11:49:55.236606
9923 11:49:55.531327 02200000 ################################################################
9924 11:49:55.531459
9925 11:49:55.824937 02280000 ################################################################
9926 11:49:55.825071
9927 11:49:56.091150 02300000 ################################################################
9928 11:49:56.091286
9929 11:49:56.362918 02380000 ################################################################
9930 11:49:56.363049
9931 11:49:56.638881 02400000 ################################################################
9932 11:49:56.639014
9933 11:49:56.918059 02480000 ################################################################
9934 11:49:56.918189
9935 11:49:57.203917 02500000 ################################################################
9936 11:49:57.204097
9937 11:49:57.484152 02580000 ################################################################
9938 11:49:57.484292
9939 11:49:57.775534 02600000 ################################################################
9940 11:49:57.775672
9941 11:49:58.072346 02680000 ################################################################
9942 11:49:58.072480
9943 11:49:58.369363 02700000 ################################################################
9944 11:49:58.369500
9945 11:49:58.665626 02780000 ################################################################
9946 11:49:58.665762
9947 11:49:58.962902 02800000 ################################################################
9948 11:49:58.963035
9949 11:49:59.260423 02880000 ################################################################
9950 11:49:59.260576
9951 11:49:59.555902 02900000 ################################################################
9952 11:49:59.556039
9953 11:49:59.840678 02980000 ################################################################
9954 11:49:59.840811
9955 11:50:00.138092 02a00000 ################################################################
9956 11:50:00.138226
9957 11:50:00.435386 02a80000 ################################################################
9958 11:50:00.435529
9959 11:50:00.730640 02b00000 ################################################################
9960 11:50:00.730776
9961 11:50:01.023059 02b80000 ################################################################
9962 11:50:01.023216
9963 11:50:01.309984 02c00000 ################################################################
9964 11:50:01.310115
9965 11:50:01.585848 02c80000 ################################################################
9966 11:50:01.585986
9967 11:50:01.842549 02d00000 ################################################################
9968 11:50:01.842681
9969 11:50:02.117427 02d80000 ################################################################
9970 11:50:02.117561
9971 11:50:02.407459 02e00000 ################################################################
9972 11:50:02.407627
9973 11:50:02.697449 02e80000 ################################################################
9974 11:50:02.697583
9975 11:50:02.992029 02f00000 ################################################################
9976 11:50:02.992165
9977 11:50:03.281442 02f80000 ################################################################
9978 11:50:03.281585
9979 11:50:03.560001 03000000 ################################################################
9980 11:50:03.560138
9981 11:50:03.852744 03080000 ################################################################
9982 11:50:03.852882
9983 11:50:04.145288 03100000 ################################################################
9984 11:50:04.145421
9985 11:50:04.434513 03180000 ################################################################
9986 11:50:04.434642
9987 11:50:04.708996 03200000 ################################################################
9988 11:50:04.709128
9989 11:50:04.979770 03280000 ################################################################
9990 11:50:04.979903
9991 11:50:05.241742 03300000 ################################################################
9992 11:50:05.241872
9993 11:50:05.526700 03380000 ################################################################
9994 11:50:05.526828
9995 11:50:05.818624 03400000 ################################################################
9996 11:50:05.818780
9997 11:50:06.115266 03480000 ################################################################
9998 11:50:06.115440
9999 11:50:06.412612 03500000 ################################################################
10000 11:50:06.412743
10001 11:50:06.692057 03580000 ################################################################
10002 11:50:06.692215
10003 11:50:06.980387 03600000 ################################################################
10004 11:50:06.980580
10005 11:50:07.327429 03680000 ################################################################
10006 11:50:07.327733
10007 11:50:07.590742 03700000 ################################################################
10008 11:50:07.590880
10009 11:50:07.831123 03780000 ##################################################### done.
10010 11:50:07.831252
10011 11:50:07.834270 The bootfile was 58629610 bytes long.
10012 11:50:07.834360
10013 11:50:07.837666 Sending tftp read request... done.
10014 11:50:07.837846
10015 11:50:07.837950 Waiting for the transfer...
10016 11:50:07.838038
10017 11:50:07.841036 00000000 # done.
10018 11:50:07.841161
10019 11:50:07.847569 Command line loaded dynamically from TFTP file: 12074062/tftp-deploy-yu09ioqk/kernel/cmdline
10020 11:50:07.847759
10021 11:50:07.861098 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10022 11:50:07.861319
10023 11:50:07.864436 Loading FIT.
10024 11:50:07.864688
10025 11:50:07.867892 Image ramdisk-1 has 47532051 bytes.
10026 11:50:07.868149
10027 11:50:07.868304 Image fdt-1 has 47278 bytes.
10028 11:50:07.870860
10029 11:50:07.871124 Image kernel-1 has 11048246 bytes.
10030 11:50:07.871281
10031 11:50:07.880999 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10032 11:50:07.881353
10033 11:50:07.897489 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10034 11:50:07.897988
10035 11:50:07.904353 Choosing best match conf-1 for compat google,spherion-rev3.
10036 11:50:07.908384
10037 11:50:07.913176 Connected to device vid:did:rid of 1ae0:0028:00
10038 11:50:07.919896
10039 11:50:07.923221 tpm_get_response: command 0x17b, return code 0x0
10040 11:50:07.923787
10041 11:50:07.926288 ec_init: CrosEC protocol v3 supported (256, 248)
10042 11:50:07.930563
10043 11:50:07.933609 tpm_cleanup: add release locality here.
10044 11:50:07.934118
10045 11:50:07.934488 Shutting down all USB controllers.
10046 11:50:07.937013
10047 11:50:07.937473 Removing current net device
10048 11:50:07.937843
10049 11:50:07.943824 Exiting depthcharge with code 4 at timestamp: 74837655
10050 11:50:07.944326
10051 11:50:07.947095 LZMA decompressing kernel-1 to 0x821a6718
10052 11:50:07.947684
10053 11:50:07.950323 LZMA decompressing kernel-1 to 0x40000000
10054 11:50:09.338285
10055 11:50:09.338741 jumping to kernel
10056 11:50:09.340410 end: 2.2.4 bootloader-commands (duration 00:00:48) [common]
10057 11:50:09.340885 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10058 11:50:09.341203 Setting prompt string to ['Linux version [0-9]']
10059 11:50:09.341494 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 11:50:09.341833 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10061 11:50:09.389128
10062 11:50:09.392594 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10063 11:50:09.396337 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10064 11:50:09.396890 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10065 11:50:09.397407 Setting prompt string to []
10066 11:50:09.398095 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10067 11:50:09.398526 Using line separator: #'\n'#
10068 11:50:09.398868 No login prompt set.
10069 11:50:09.399212 Parsing kernel messages
10070 11:50:09.399523 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10071 11:50:09.400081 [login-action] Waiting for messages, (timeout 00:03:38)
10072 11:50:09.415473 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10073 11:50:09.418892 [ 0.000000] random: crng init done
10074 11:50:09.425378 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10075 11:50:09.428766 [ 0.000000] efi: UEFI not found.
10076 11:50:09.435378 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10077 11:50:09.441858 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10078 11:50:09.451986 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10079 11:50:09.461647 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10080 11:50:09.468295 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10081 11:50:09.474867 [ 0.000000] printk: bootconsole [mtk8250] enabled
10082 11:50:09.481565 [ 0.000000] NUMA: No NUMA configuration found
10083 11:50:09.487861 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10084 11:50:09.491473 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10085 11:50:09.494527 [ 0.000000] Zone ranges:
10086 11:50:09.501471 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10087 11:50:09.504436 [ 0.000000] DMA32 empty
10088 11:50:09.510922 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10089 11:50:09.514457 [ 0.000000] Movable zone start for each node
10090 11:50:09.517566 [ 0.000000] Early memory node ranges
10091 11:50:09.524315 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10092 11:50:09.530934 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10093 11:50:09.537345 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10094 11:50:09.544264 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10095 11:50:09.550935 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10096 11:50:09.557090 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10097 11:50:09.587643 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10098 11:50:09.594183 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10099 11:50:09.601222 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10100 11:50:09.604084 [ 0.000000] psci: probing for conduit method from DT.
10101 11:50:09.611000 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10102 11:50:09.614054 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10103 11:50:09.620671 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10104 11:50:09.624130 [ 0.000000] psci: SMC Calling Convention v1.2
10105 11:50:09.630938 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10106 11:50:09.633859 [ 0.000000] Detected VIPT I-cache on CPU0
10107 11:50:09.640663 [ 0.000000] CPU features: detected: GIC system register CPU interface
10108 11:50:09.647080 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10109 11:50:09.653754 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10110 11:50:09.660412 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10111 11:50:09.670224 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10112 11:50:09.677026 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10113 11:50:09.680417 [ 0.000000] alternatives: applying boot alternatives
10114 11:50:09.686707 [ 0.000000] Fallback order for Node 0: 0
10115 11:50:09.693120 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10116 11:50:09.696875 [ 0.000000] Policy zone: Normal
10117 11:50:09.709838 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10118 11:50:09.719747 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10119 11:50:09.729961 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10120 11:50:09.740172 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10121 11:50:09.746560 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10122 11:50:09.749503 <6>[ 0.000000] software IO TLB: area num 8.
10123 11:50:09.805456 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10124 11:50:09.885380 <6>[ 0.000000] Memory: 3808792K/4191232K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 349672K reserved, 32768K cma-reserved)
10125 11:50:09.892583 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10126 11:50:09.898828 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10127 11:50:09.902035 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10128 11:50:09.908743 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10129 11:50:09.915590 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10130 11:50:09.918836 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10131 11:50:09.928671 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10132 11:50:09.935432 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10133 11:50:09.941797 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10134 11:50:09.948330 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10135 11:50:09.951809 <6>[ 0.000000] GICv3: 608 SPIs implemented
10136 11:50:09.954856 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10137 11:50:09.961561 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10138 11:50:09.964979 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10139 11:50:09.971357 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10140 11:50:09.984922 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10141 11:50:09.997858 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10142 11:50:10.004431 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10143 11:50:10.011900 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10144 11:50:10.025217 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10145 11:50:10.032015 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10146 11:50:10.038901 <6>[ 0.009182] Console: colour dummy device 80x25
10147 11:50:10.048294 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10148 11:50:10.054857 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10149 11:50:10.058235 <6>[ 0.029220] LSM: Security Framework initializing
10150 11:50:10.065182 <6>[ 0.034163] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10151 11:50:10.074976 <6>[ 0.041770] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10152 11:50:10.081349 <6>[ 0.050994] cblist_init_generic: Setting adjustable number of callback queues.
10153 11:50:10.088272 <6>[ 0.058435] cblist_init_generic: Setting shift to 3 and lim to 1.
10154 11:50:10.097818 <6>[ 0.064773] cblist_init_generic: Setting adjustable number of callback queues.
10155 11:50:10.101300 <6>[ 0.072200] cblist_init_generic: Setting shift to 3 and lim to 1.
10156 11:50:10.108127 <6>[ 0.078639] rcu: Hierarchical SRCU implementation.
10157 11:50:10.114404 <6>[ 0.083653] rcu: Max phase no-delay instances is 1000.
10158 11:50:10.121462 <6>[ 0.090672] EFI services will not be available.
10159 11:50:10.124614 <6>[ 0.095621] smp: Bringing up secondary CPUs ...
10160 11:50:10.132696 <6>[ 0.100692] Detected VIPT I-cache on CPU1
10161 11:50:10.139007 <6>[ 0.100760] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10162 11:50:10.146021 <6>[ 0.100791] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10163 11:50:10.149217 <6>[ 0.101123] Detected VIPT I-cache on CPU2
10164 11:50:10.155600 <6>[ 0.101172] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10165 11:50:10.165656 <6>[ 0.101188] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10166 11:50:10.168617 <6>[ 0.101446] Detected VIPT I-cache on CPU3
10167 11:50:10.175627 <6>[ 0.101491] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10168 11:50:10.182316 <6>[ 0.101505] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10169 11:50:10.185455 <6>[ 0.101806] CPU features: detected: Spectre-v4
10170 11:50:10.192134 <6>[ 0.101813] CPU features: detected: Spectre-BHB
10171 11:50:10.195540 <6>[ 0.101817] Detected PIPT I-cache on CPU4
10172 11:50:10.201903 <6>[ 0.101874] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10173 11:50:10.208884 <6>[ 0.101891] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10174 11:50:10.215035 <6>[ 0.102178] Detected PIPT I-cache on CPU5
10175 11:50:10.221916 <6>[ 0.102240] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10176 11:50:10.228324 <6>[ 0.102255] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10177 11:50:10.231745 <6>[ 0.102529] Detected PIPT I-cache on CPU6
10178 11:50:10.238136 <6>[ 0.102591] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10179 11:50:10.244965 <6>[ 0.102607] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10180 11:50:10.251870 <6>[ 0.102903] Detected PIPT I-cache on CPU7
10181 11:50:10.258053 <6>[ 0.102968] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10182 11:50:10.264893 <6>[ 0.102984] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10183 11:50:10.268020 <6>[ 0.103031] smp: Brought up 1 node, 8 CPUs
10184 11:50:10.274626 <6>[ 0.244294] SMP: Total of 8 processors activated.
10185 11:50:10.278239 <6>[ 0.249214] CPU features: detected: 32-bit EL0 Support
10186 11:50:10.287900 <6>[ 0.254576] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10187 11:50:10.294666 <6>[ 0.263376] CPU features: detected: Common not Private translations
10188 11:50:10.300925 <6>[ 0.269852] CPU features: detected: CRC32 instructions
10189 11:50:10.304544 <6>[ 0.275236] CPU features: detected: RCpc load-acquire (LDAPR)
10190 11:50:10.311031 <6>[ 0.281232] CPU features: detected: LSE atomic instructions
10191 11:50:10.317609 <6>[ 0.287014] CPU features: detected: Privileged Access Never
10192 11:50:10.324058 <6>[ 0.292793] CPU features: detected: RAS Extension Support
10193 11:50:10.330823 <6>[ 0.298437] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10194 11:50:10.333837 <6>[ 0.305654] CPU: All CPU(s) started at EL2
10195 11:50:10.340663 <6>[ 0.309971] alternatives: applying system-wide alternatives
10196 11:50:10.348969 <6>[ 0.319812] devtmpfs: initialized
10197 11:50:10.364201 <6>[ 0.328129] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10198 11:50:10.370945 <6>[ 0.338091] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10199 11:50:10.377292 <6>[ 0.346268] pinctrl core: initialized pinctrl subsystem
10200 11:50:10.380581 <6>[ 0.352940] DMI not present or invalid.
10201 11:50:10.387256 <6>[ 0.357343] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10202 11:50:10.397136 <6>[ 0.364202] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10203 11:50:10.403714 <6>[ 0.371647] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10204 11:50:10.413564 <6>[ 0.379737] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10205 11:50:10.416834 <6>[ 0.387892] audit: initializing netlink subsys (disabled)
10206 11:50:10.427189 <5>[ 0.393588] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10207 11:50:10.433442 <6>[ 0.394283] thermal_sys: Registered thermal governor 'step_wise'
10208 11:50:10.440138 <6>[ 0.401554] thermal_sys: Registered thermal governor 'power_allocator'
10209 11:50:10.443443 <6>[ 0.407810] cpuidle: using governor menu
10210 11:50:10.449836 <6>[ 0.418769] NET: Registered PF_QIPCRTR protocol family
10211 11:50:10.456194 <6>[ 0.424250] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10212 11:50:10.462895 <6>[ 0.431353] ASID allocator initialised with 32768 entries
10213 11:50:10.466194 <6>[ 0.437899] Serial: AMBA PL011 UART driver
10214 11:50:10.475976 <4>[ 0.446717] Trying to register duplicate clock ID: 134
10215 11:50:10.532796 <6>[ 0.506614] KASLR enabled
10216 11:50:10.547043 <6>[ 0.514351] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10217 11:50:10.553660 <6>[ 0.521364] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10218 11:50:10.560252 <6>[ 0.527854] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10219 11:50:10.566914 <6>[ 0.534859] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10220 11:50:10.573352 <6>[ 0.541345] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10221 11:50:10.580286 <6>[ 0.548349] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10222 11:50:10.587052 <6>[ 0.554837] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10223 11:50:10.593471 <6>[ 0.561841] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10224 11:50:10.596651 <6>[ 0.569257] ACPI: Interpreter disabled.
10225 11:50:10.604946 <6>[ 0.575647] iommu: Default domain type: Translated
10226 11:50:10.611779 <6>[ 0.580761] iommu: DMA domain TLB invalidation policy: strict mode
10227 11:50:10.614866 <5>[ 0.587412] SCSI subsystem initialized
10228 11:50:10.621393 <6>[ 0.591575] usbcore: registered new interface driver usbfs
10229 11:50:10.627965 <6>[ 0.597307] usbcore: registered new interface driver hub
10230 11:50:10.631681 <6>[ 0.602860] usbcore: registered new device driver usb
10231 11:50:10.638455 <6>[ 0.608957] pps_core: LinuxPPS API ver. 1 registered
10232 11:50:10.648104 <6>[ 0.614150] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10233 11:50:10.651906 <6>[ 0.623498] PTP clock support registered
10234 11:50:10.654551 <6>[ 0.627738] EDAC MC: Ver: 3.0.0
10235 11:50:10.662262 <6>[ 0.632899] FPGA manager framework
10236 11:50:10.668669 <6>[ 0.636577] Advanced Linux Sound Architecture Driver Initialized.
10237 11:50:10.672324 <6>[ 0.643344] vgaarb: loaded
10238 11:50:10.678624 <6>[ 0.646512] clocksource: Switched to clocksource arch_sys_counter
10239 11:50:10.681871 <5>[ 0.652926] VFS: Disk quotas dquot_6.6.0
10240 11:50:10.689011 <6>[ 0.657110] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10241 11:50:10.691743 <6>[ 0.664299] pnp: PnP ACPI: disabled
10242 11:50:10.700088 <6>[ 0.670926] NET: Registered PF_INET protocol family
10243 11:50:10.706831 <6>[ 0.676305] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10244 11:50:10.718662 <6>[ 0.686217] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10245 11:50:10.728956 <6>[ 0.695004] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10246 11:50:10.735796 <6>[ 0.702967] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10247 11:50:10.741906 <6>[ 0.711368] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10248 11:50:10.752618 <6>[ 0.720007] TCP: Hash tables configured (established 32768 bind 32768)
10249 11:50:10.759006 <6>[ 0.726853] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10250 11:50:10.765902 <6>[ 0.733872] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10251 11:50:10.772667 <6>[ 0.741379] NET: Registered PF_UNIX/PF_LOCAL protocol family
10252 11:50:10.779059 <6>[ 0.747529] RPC: Registered named UNIX socket transport module.
10253 11:50:10.782412 <6>[ 0.753683] RPC: Registered udp transport module.
10254 11:50:10.788845 <6>[ 0.758615] RPC: Registered tcp transport module.
10255 11:50:10.795494 <6>[ 0.763547] RPC: Registered tcp NFSv4.1 backchannel transport module.
10256 11:50:10.798690 <6>[ 0.770214] PCI: CLS 0 bytes, default 64
10257 11:50:10.801828 <6>[ 0.774590] Unpacking initramfs...
10258 11:50:10.827654 <6>[ 0.794745] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10259 11:50:10.837337 <6>[ 0.803377] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10260 11:50:10.840802 <6>[ 0.812219] kvm [1]: IPA Size Limit: 40 bits
10261 11:50:10.847389 <6>[ 0.816745] kvm [1]: GICv3: no GICV resource entry
10262 11:50:10.850472 <6>[ 0.821766] kvm [1]: disabling GICv2 emulation
10263 11:50:10.857316 <6>[ 0.826453] kvm [1]: GIC system register CPU interface enabled
10264 11:50:10.860433 <6>[ 0.832627] kvm [1]: vgic interrupt IRQ18
10265 11:50:10.867215 <6>[ 0.836981] kvm [1]: VHE mode initialized successfully
10266 11:50:10.873830 <5>[ 0.843522] Initialise system trusted keyrings
10267 11:50:10.880439 <6>[ 0.848341] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10268 11:50:10.887459 <6>[ 0.858352] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10269 11:50:10.894347 <5>[ 0.864787] NFS: Registering the id_resolver key type
10270 11:50:10.897303 <5>[ 0.870088] Key type id_resolver registered
10271 11:50:10.904547 <5>[ 0.874502] Key type id_legacy registered
10272 11:50:10.910659 <6>[ 0.878781] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10273 11:50:10.917521 <6>[ 0.885705] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10274 11:50:10.923882 <6>[ 0.893409] 9p: Installing v9fs 9p2000 file system support
10275 11:50:10.961299 <5>[ 0.931876] Key type asymmetric registered
10276 11:50:10.964425 <5>[ 0.936208] Asymmetric key parser 'x509' registered
10277 11:50:10.974489 <6>[ 0.941344] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10278 11:50:10.977842 <6>[ 0.948979] io scheduler mq-deadline registered
10279 11:50:10.980968 <6>[ 0.953765] io scheduler kyber registered
10280 11:50:11.000101 <6>[ 0.970848] EINJ: ACPI disabled.
10281 11:50:11.032980 <4>[ 0.996860] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10282 11:50:11.042630 <4>[ 1.007507] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10283 11:50:11.057366 <6>[ 1.028252] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10284 11:50:11.065652 <6>[ 1.036243] printk: console [ttyS0] disabled
10285 11:50:11.093592 <6>[ 1.060890] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10286 11:50:11.100277 <6>[ 1.070367] printk: console [ttyS0] enabled
10287 11:50:11.103412 <6>[ 1.070367] printk: console [ttyS0] enabled
10288 11:50:11.110303 <6>[ 1.079260] printk: bootconsole [mtk8250] disabled
10289 11:50:11.113080 <6>[ 1.079260] printk: bootconsole [mtk8250] disabled
10290 11:50:11.119527 <6>[ 1.090471] SuperH (H)SCI(F) driver initialized
10291 11:50:11.123345 <6>[ 1.095733] msm_serial: driver initialized
10292 11:50:11.137279 <6>[ 1.104725] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10293 11:50:11.147232 <6>[ 1.113270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10294 11:50:11.153878 <6>[ 1.121812] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10295 11:50:11.164226 <6>[ 1.130441] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10296 11:50:11.174047 <6>[ 1.139153] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10297 11:50:11.180679 <6>[ 1.147874] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10298 11:50:11.190194 <6>[ 1.156414] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10299 11:50:11.197128 <6>[ 1.165217] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10300 11:50:11.206751 <6>[ 1.173761] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10301 11:50:11.218653 <6>[ 1.189268] loop: module loaded
10302 11:50:11.225199 <6>[ 1.195248] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10303 11:50:11.247835 <4>[ 1.218513] mtk-pmic-keys: Failed to locate of_node [id: -1]
10304 11:50:11.254982 <6>[ 1.225363] megasas: 07.719.03.00-rc1
10305 11:50:11.264552 <6>[ 1.235155] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10306 11:50:11.271438 <6>[ 1.241895] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10307 11:50:11.287830 <6>[ 1.258389] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10308 11:50:11.344344 <6>[ 1.308293] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10309 11:50:12.831267 <6>[ 2.802050] Freeing initrd memory: 46412K
10310 11:50:12.841004 <6>[ 2.812423] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10311 11:50:12.851978 <6>[ 2.823245] tun: Universal TUN/TAP device driver, 1.6
10312 11:50:12.855263 <6>[ 2.829300] thunder_xcv, ver 1.0
10313 11:50:12.858746 <6>[ 2.832801] thunder_bgx, ver 1.0
10314 11:50:12.862034 <6>[ 2.836296] nicpf, ver 1.0
10315 11:50:12.872306 <6>[ 2.840328] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10316 11:50:12.875886 <6>[ 2.847804] hns3: Copyright (c) 2017 Huawei Corporation.
10317 11:50:12.882488 <6>[ 2.853391] hclge is initializing
10318 11:50:12.885759 <6>[ 2.856966] e1000: Intel(R) PRO/1000 Network Driver
10319 11:50:12.892621 <6>[ 2.862096] e1000: Copyright (c) 1999-2006 Intel Corporation.
10320 11:50:12.895773 <6>[ 2.868107] e1000e: Intel(R) PRO/1000 Network Driver
10321 11:50:12.902326 <6>[ 2.873323] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10322 11:50:12.909451 <6>[ 2.879509] igb: Intel(R) Gigabit Ethernet Network Driver
10323 11:50:12.915611 <6>[ 2.885160] igb: Copyright (c) 2007-2014 Intel Corporation.
10324 11:50:12.922343 <6>[ 2.890994] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10325 11:50:12.928885 <6>[ 2.897512] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10326 11:50:12.932057 <6>[ 2.903976] sky2: driver version 1.30
10327 11:50:12.939072 <6>[ 2.908970] VFIO - User Level meta-driver version: 0.3
10328 11:50:12.946120 <6>[ 2.917218] usbcore: registered new interface driver usb-storage
10329 11:50:12.952615 <6>[ 2.923663] usbcore: registered new device driver onboard-usb-hub
10330 11:50:12.961966 <6>[ 2.932797] mt6397-rtc mt6359-rtc: registered as rtc0
10331 11:50:12.972115 <6>[ 2.938266] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:50:13 UTC (1700826613)
10332 11:50:12.975293 <6>[ 2.947830] i2c_dev: i2c /dev entries driver
10333 11:50:12.991881 <6>[ 2.959616] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10334 11:50:13.011960 <6>[ 2.982594] cpu cpu0: EM: created perf domain
10335 11:50:13.014875 <6>[ 2.987516] cpu cpu4: EM: created perf domain
10336 11:50:13.022055 <6>[ 2.993035] sdhci: Secure Digital Host Controller Interface driver
10337 11:50:13.028913 <6>[ 2.999467] sdhci: Copyright(c) Pierre Ossman
10338 11:50:13.035524 <6>[ 3.004385] Synopsys Designware Multimedia Card Interface Driver
10339 11:50:13.042111 <6>[ 3.010989] sdhci-pltfm: SDHCI platform and OF driver helper
10340 11:50:13.045373 <6>[ 3.011118] mmc0: CQHCI version 5.10
10341 11:50:13.051956 <6>[ 3.021062] ledtrig-cpu: registered to indicate activity on CPUs
10342 11:50:13.058481 <6>[ 3.028057] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10343 11:50:13.064916 <6>[ 3.035089] usbcore: registered new interface driver usbhid
10344 11:50:13.068319 <6>[ 3.040913] usbhid: USB HID core driver
10345 11:50:13.074975 <6>[ 3.045104] spi_master spi0: will run message pump with realtime priority
10346 11:50:13.118743 <6>[ 3.083131] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10347 11:50:13.138144 <6>[ 3.098782] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10348 11:50:13.141570 <6>[ 3.112968] mmc0: Command Queue Engine enabled
10349 11:50:13.148315 <6>[ 3.117747] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10350 11:50:13.155055 <6>[ 3.124460] cros-ec-spi spi0.0: Chrome EC device registered
10351 11:50:13.158244 <6>[ 3.125002] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10352 11:50:13.170131 <6>[ 3.141137] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10353 11:50:13.177759 <6>[ 3.148365] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10354 11:50:13.184543 <6>[ 3.154468] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10355 11:50:13.190619 <6>[ 3.160734] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10356 11:50:13.200588 <6>[ 3.165501] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10357 11:50:13.207540 <6>[ 3.177816] NET: Registered PF_PACKET protocol family
10358 11:50:13.210701 <6>[ 3.183177] 9pnet: Installing 9P2000 support
10359 11:50:13.217033 <5>[ 3.187734] Key type dns_resolver registered
10360 11:50:13.220274 <6>[ 3.192697] registered taskstats version 1
10361 11:50:13.227104 <5>[ 3.197077] Loading compiled-in X.509 certificates
10362 11:50:13.256675 <4>[ 3.220871] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10363 11:50:13.266434 <4>[ 3.231834] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10364 11:50:13.272986 <3>[ 3.242384] debugfs: File 'uA_load' in directory '/' already present!
10365 11:50:13.279901 <3>[ 3.249107] debugfs: File 'min_uV' in directory '/' already present!
10366 11:50:13.286308 <3>[ 3.255736] debugfs: File 'max_uV' in directory '/' already present!
10367 11:50:13.292819 <3>[ 3.262348] debugfs: File 'constraint_flags' in directory '/' already present!
10368 11:50:13.304665 <3>[ 3.272106] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10369 11:50:13.313032 <6>[ 3.283942] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10370 11:50:13.319848 <6>[ 3.290851] xhci-mtk 11200000.usb: xHCI Host Controller
10371 11:50:13.326555 <6>[ 3.296340] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10372 11:50:13.336421 <6>[ 3.304172] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10373 11:50:13.343266 <6>[ 3.313588] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10374 11:50:13.350048 <6>[ 3.319649] xhci-mtk 11200000.usb: xHCI Host Controller
10375 11:50:13.356488 <6>[ 3.325124] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10376 11:50:13.363286 <6>[ 3.332770] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10377 11:50:13.369973 <6>[ 3.340492] hub 1-0:1.0: USB hub found
10378 11:50:13.372966 <6>[ 3.344506] hub 1-0:1.0: 1 port detected
10379 11:50:13.379560 <6>[ 3.348780] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10380 11:50:13.386570 <6>[ 3.357517] hub 2-0:1.0: USB hub found
10381 11:50:13.390058 <6>[ 3.361531] hub 2-0:1.0: 1 port detected
10382 11:50:13.398053 <6>[ 3.369198] mtk-msdc 11f70000.mmc: Got CD GPIO
10383 11:50:13.408171 <6>[ 3.374909] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10384 11:50:13.414890 <6>[ 3.382941] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10385 11:50:13.424714 <4>[ 3.390837] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10386 11:50:13.431644 <6>[ 3.400362] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10387 11:50:13.441238 <6>[ 3.408440] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10388 11:50:13.448020 <6>[ 3.416452] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10389 11:50:13.454725 <6>[ 3.424369] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10390 11:50:13.464355 <6>[ 3.432191] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10391 11:50:13.474531 <6>[ 3.440009] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10392 11:50:13.484452 <6>[ 3.450310] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10393 11:50:13.490709 <6>[ 3.458673] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10394 11:50:13.500967 <6>[ 3.467018] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10395 11:50:13.507719 <6>[ 3.475357] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10396 11:50:13.517561 <6>[ 3.483695] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10397 11:50:13.524164 <6>[ 3.492040] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10398 11:50:13.533866 <6>[ 3.500378] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10399 11:50:13.540435 <6>[ 3.508717] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10400 11:50:13.550380 <6>[ 3.517056] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10401 11:50:13.556881 <6>[ 3.525395] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10402 11:50:13.566762 <6>[ 3.533733] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10403 11:50:13.573258 <6>[ 3.542070] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10404 11:50:13.583553 <6>[ 3.550408] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10405 11:50:13.590047 <6>[ 3.558746] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10406 11:50:13.600375 <6>[ 3.567084] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10407 11:50:13.606457 <6>[ 3.575854] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10408 11:50:13.613441 <6>[ 3.583070] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10409 11:50:13.619693 <6>[ 3.589922] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10410 11:50:13.626488 <6>[ 3.596766] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10411 11:50:13.632932 <6>[ 3.603745] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10412 11:50:13.642767 <6>[ 3.610601] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10413 11:50:13.652693 <6>[ 3.619727] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10414 11:50:13.662775 <6>[ 3.628845] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10415 11:50:13.672633 <6>[ 3.638138] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10416 11:50:13.682538 <6>[ 3.647611] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10417 11:50:13.689229 <6>[ 3.657093] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10418 11:50:13.699264 <6>[ 3.666213] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10419 11:50:13.709168 <6>[ 3.675679] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10420 11:50:13.718663 <6>[ 3.684796] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10421 11:50:13.728658 <6>[ 3.694089] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10422 11:50:13.738677 <6>[ 3.704249] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10423 11:50:13.748659 <6>[ 3.715717] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10424 11:50:13.779254 <6>[ 3.746795] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10425 11:50:13.807545 <6>[ 3.778412] hub 2-1:1.0: USB hub found
10426 11:50:13.810788 <6>[ 3.782871] hub 2-1:1.0: 3 ports detected
10427 11:50:13.818855 <6>[ 3.789830] hub 2-1:1.0: USB hub found
10428 11:50:13.821991 <6>[ 3.794139] hub 2-1:1.0: 3 ports detected
10429 11:50:13.930987 <6>[ 3.898791] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10430 11:50:14.085976 <6>[ 4.056921] hub 1-1:1.0: USB hub found
10431 11:50:14.089419 <6>[ 4.061420] hub 1-1:1.0: 4 ports detected
10432 11:50:14.099185 <6>[ 4.070064] hub 1-1:1.0: USB hub found
10433 11:50:14.102439 <6>[ 4.074431] hub 1-1:1.0: 4 ports detected
10434 11:50:14.163295 <6>[ 4.130895] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10435 11:50:14.423149 <6>[ 4.390817] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10436 11:50:14.555458 <6>[ 4.526588] hub 1-1.4:1.0: USB hub found
10437 11:50:14.558797 <6>[ 4.531260] hub 1-1.4:1.0: 2 ports detected
10438 11:50:14.568089 <6>[ 4.539370] hub 1-1.4:1.0: USB hub found
10439 11:50:14.571439 <6>[ 4.544041] hub 1-1.4:1.0: 2 ports detected
10440 11:50:14.866717 <6>[ 4.834820] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10441 11:50:15.058836 <6>[ 5.026788] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10442 11:50:26.039902 <6>[ 16.015794] ALSA device list:
10443 11:50:26.046739 <6>[ 16.019082] No soundcards found.
10444 11:50:26.054560 <6>[ 16.026855] Freeing unused kernel memory: 8384K
10445 11:50:26.057902 <6>[ 16.031894] Run /init as init process
10446 11:50:26.108339 <6>[ 16.080631] NET: Registered PF_INET6 protocol family
10447 11:50:26.114926 <6>[ 16.086686] Segment Routing with IPv6
10448 11:50:26.118281 <6>[ 16.090640] In-situ OAM (IOAM) with IPv6
10449 11:50:26.151856 <30>[ 16.104465] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10450 11:50:26.155161 <30>[ 16.128247] systemd[1]: Detected architecture arm64.
10451 11:50:26.155727
10452 11:50:26.161877 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10453 11:50:26.162442
10454 11:50:26.174587 <30>[ 16.146819] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10455 11:50:26.321160 <30>[ 16.290304] systemd[1]: Queued start job for default target Graphical Interface.
10456 11:50:26.370795 <30>[ 16.343280] systemd[1]: Created slice system-getty.slice.
10457 11:50:26.377605 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10458 11:50:26.395142 <30>[ 16.367239] systemd[1]: Created slice system-modprobe.slice.
10459 11:50:26.401253 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10460 11:50:26.419542 <30>[ 16.391987] systemd[1]: Created slice system-serial\x2dgetty.slice.
10461 11:50:26.429886 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10462 11:50:26.443080 <30>[ 16.415260] systemd[1]: Created slice User and Session Slice.
10463 11:50:26.449295 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10464 11:50:26.470054 <30>[ 16.439429] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10465 11:50:26.480077 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10466 11:50:26.498150 <30>[ 16.467476] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10467 11:50:26.504936 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10468 11:50:26.529311 <30>[ 16.495274] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10469 11:50:26.536152 <30>[ 16.507523] systemd[1]: Reached target Local Encrypted Volumes.
10470 11:50:26.542715 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10471 11:50:26.558844 <30>[ 16.531289] systemd[1]: Reached target Paths.
10472 11:50:26.562265 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10473 11:50:26.578063 <30>[ 16.550790] systemd[1]: Reached target Remote File Systems.
10474 11:50:26.584867 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10475 11:50:26.598333 <30>[ 16.570767] systemd[1]: Reached target Slices.
10476 11:50:26.601612 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10477 11:50:26.618417 <30>[ 16.590814] systemd[1]: Reached target Swap.
10478 11:50:26.621619 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10479 11:50:26.642245 <30>[ 16.611240] systemd[1]: Listening on initctl Compatibility Named Pipe.
10480 11:50:26.648630 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10481 11:50:26.664053 <30>[ 16.636174] systemd[1]: Listening on Journal Audit Socket.
10482 11:50:26.670484 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10483 11:50:26.687410 <30>[ 16.659921] systemd[1]: Listening on Journal Socket (/dev/log).
10484 11:50:26.694323 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10485 11:50:26.711676 <30>[ 16.684012] systemd[1]: Listening on Journal Socket.
10486 11:50:26.718030 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10487 11:50:26.734289 <30>[ 16.703500] systemd[1]: Listening on Network Service Netlink Socket.
10488 11:50:26.740846 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10489 11:50:26.755732 <30>[ 16.727977] systemd[1]: Listening on udev Control Socket.
10490 11:50:26.762250 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10491 11:50:26.779650 <30>[ 16.751901] systemd[1]: Listening on udev Kernel Socket.
10492 11:50:26.786044 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10493 11:50:26.826483 <30>[ 16.798948] systemd[1]: Mounting Huge Pages File System...
10494 11:50:26.833232 Mounting [0;1;39mHuge Pages File System[0m...
10495 11:50:26.849590 <30>[ 16.822068] systemd[1]: Mounting POSIX Message Queue File System...
10496 11:50:26.856656 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10497 11:50:26.874006 <30>[ 16.846263] systemd[1]: Mounting Kernel Debug File System...
10498 11:50:26.880404 Mounting [0;1;39mKernel Debug File System[0m...
10499 11:50:26.897802 <30>[ 16.866989] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10500 11:50:26.910678 <30>[ 16.879988] systemd[1]: Starting Create list of static device nodes for the current kernel...
10501 11:50:26.917286 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10502 11:50:26.938931 <30>[ 16.911255] systemd[1]: Starting Load Kernel Module configfs...
10503 11:50:26.945166 Starting [0;1;39mLoad Kernel Module configfs[0m...
10504 11:50:26.974851 <30>[ 16.947051] systemd[1]: Starting Load Kernel Module drm...
10505 11:50:26.981069 Starting [0;1;39mLoad Kernel Module drm[0m...
10506 11:50:26.997420 <30>[ 16.966904] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10507 11:50:27.011957 <30>[ 16.984515] systemd[1]: Starting Journal Service...
10508 11:50:27.015372 Starting [0;1;39mJournal Service[0m...
10509 11:50:27.032808 <30>[ 17.005250] systemd[1]: Starting Load Kernel Modules...
10510 11:50:27.039171 Starting [0;1;39mLoad Kernel Modules[0m...
10511 11:50:27.061720 <30>[ 17.031111] systemd[1]: Starting Remount Root and Kernel File Systems...
10512 11:50:27.068669 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10513 11:50:27.085067 <30>[ 17.057599] systemd[1]: Starting Coldplug All udev Devices...
10514 11:50:27.091830 Starting [0;1;39mColdplug All udev Devices[0m...
10515 11:50:27.111115 <30>[ 17.083813] systemd[1]: Started Journal Service.
10516 11:50:27.117761 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10517 11:50:27.133436 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10518 11:50:27.151831 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10519 11:50:27.167307 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10520 11:50:27.192716 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10521 11:50:27.213377 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10522 11:50:27.236914 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10523 11:50:27.260364 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10524 11:50:27.280191 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10525 11:50:27.294315 See 'systemctl status systemd-remount-fs.service' for details.
10526 11:50:27.345248 Mounting [0;1;39mKernel Configuration File System[0m...
10527 11:50:27.366041 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10528 11:50:27.378869 <46>[ 17.348233] systemd-journald[176]: Received client request to flush runtime journal.
10529 11:50:27.389730 Starting [0;1;39mLoad/Save Random Seed[0m...
10530 11:50:27.410791 Starting [0;1;39mApply Kernel Variables[0m...
10531 11:50:27.431936 Starting [0;1;39mCreate System Users[0m...
10532 11:50:27.450823 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10533 11:50:27.469159 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10534 11:50:27.495420 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10535 11:50:27.512111 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10536 11:50:27.527967 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10537 11:50:27.543682 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10538 11:50:27.587528 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10539 11:50:27.607000 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10540 11:50:27.618814 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10541 11:50:27.634571 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10542 11:50:27.687052 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10543 11:50:27.714799 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10544 11:50:27.734955 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10545 11:50:27.754664 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10546 11:50:27.807569 Starting [0;1;39mNetwork Service[0m...
10547 11:50:27.835804 Starting [0;1;39mNetwork Time Synchronization[0m...
10548 11:50:27.865251 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10549 11:50:27.895550 [[0;32m OK [0m] Started [0;<6>[ 17.863140] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10550 11:50:27.905489 1;39mNetwork Ser<6>[ 17.872971] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10551 11:50:27.906140 vice[0m.
10552 11:50:27.915575 <6>[ 17.882156] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10553 11:50:27.929542 <6>[ 17.902235] mc: Linux media interface: v0.10
10554 11:50:27.944147 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10555 11:50:27.960627 <4>[ 17.929868] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10556 11:50:27.973572 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronizatio<4>[ 17.943120] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10557 11:50:27.974147 n[0m.
10558 11:50:27.980402 <6>[ 17.948628] usbcore: registered new interface driver r8152
10559 11:50:27.987067 <3>[ 17.949647] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10560 11:50:27.996986 <3>[ 17.949663] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10561 11:50:28.003615 <3>[ 17.949678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10562 11:50:28.013387 <3>[ 17.954626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10563 11:50:28.019735 <3>[ 17.990674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10564 11:50:28.029479 <3>[ 17.990702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10565 11:50:28.039587 [[0;32m OK [<3>[ 17.990721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10566 11:50:28.049499 0m] Found device<6>[ 17.998634] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10567 11:50:28.059191 [0;1;39m/dev/t<6>[ 17.999253] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10568 11:50:28.059307 tyS0[0m.
10569 11:50:28.065903 <6>[ 17.999543] videodev: Linux video capture interface: v2.00
10570 11:50:28.073002 <3>[ 18.007496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10571 11:50:28.079836 <6>[ 18.014180] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10572 11:50:28.086286 <6>[ 18.014187] pci_bus 0000:00: root bus resource [bus 00-ff]
10573 11:50:28.092733 <6>[ 18.014194] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10574 11:50:28.103208 <6>[ 18.014199] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10575 11:50:28.109401 <6>[ 18.014230] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10576 11:50:28.116183 <6>[ 18.014251] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10577 11:50:28.122726 <6>[ 18.014329] pci 0000:00:00.0: supports D1 D2
10578 11:50:28.129324 <6>[ 18.014332] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10579 11:50:28.135975 <6>[ 18.016517] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10580 11:50:28.142966 <6>[ 18.016693] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10581 11:50:28.149768 <6>[ 18.016743] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10582 11:50:28.160099 <6>[ 18.016774] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10583 11:50:28.166905 <6>[ 18.018187] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10584 11:50:28.176823 <3>[ 18.026330] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10585 11:50:28.183247 <4>[ 18.035461] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10586 11:50:28.189892 <4>[ 18.035461] Fallback method does not support PEC.
10587 11:50:28.196686 <6>[ 18.037660] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10588 11:50:28.206483 <3>[ 18.043986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10589 11:50:28.213716 <3>[ 18.051846] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10590 11:50:28.219955 <6>[ 18.052241] pci 0000:01:00.0: supports D1 D2
10591 11:50:28.226573 <3>[ 18.058905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10592 11:50:28.236468 <3>[ 18.058909] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10593 11:50:28.243151 <3>[ 18.058963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10594 11:50:28.249849 <6>[ 18.064666] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10595 11:50:28.259507 <6>[ 18.066915] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10596 11:50:28.265882 <3>[ 18.071774] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10597 11:50:28.276203 <3>[ 18.071783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10598 11:50:28.282834 <3>[ 18.071793] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10599 11:50:28.289268 <6>[ 18.083534] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10600 11:50:28.299003 <3>[ 18.087945] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10601 11:50:28.305642 <6>[ 18.100059] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10602 11:50:28.312687 <3>[ 18.100824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10603 11:50:28.315809 <6>[ 18.116344] Bluetooth: Core ver 2.22
10604 11:50:28.325927 <6>[ 18.121415] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10605 11:50:28.332109 <6>[ 18.121530] usbcore: registered new interface driver cdc_ether
10606 11:50:28.336074 <6>[ 18.129180] NET: Registered PF_BLUETOOTH protocol family
10607 11:50:28.346739 <6>[ 18.136505] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10608 11:50:28.353953 <6>[ 18.136532] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10609 11:50:28.360698 <6>[ 18.136546] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10610 11:50:28.371067 <6>[ 18.136560] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10611 11:50:28.374220 <6>[ 18.136575] pci 0000:00:00.0: PCI bridge to [bus 01]
10612 11:50:28.384093 <6>[ 18.136582] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10613 11:50:28.390699 <3>[ 18.137573] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10614 11:50:28.400122 <3>[ 18.138225] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10615 11:50:28.406764 <6>[ 18.138417] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10616 11:50:28.413798 <6>[ 18.138800] usbcore: registered new interface driver r8153_ecm
10617 11:50:28.420584 <6>[ 18.139203] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10618 11:50:28.426934 <6>[ 18.139305] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10619 11:50:28.433164 <6>[ 18.146038] Bluetooth: HCI device and connection manager initialized
10620 11:50:28.440000 <6>[ 18.148580] pcieport 0000:00:00.0: PME: Signaling with IRQ 281
10621 11:50:28.446635 <6>[ 18.151207] remoteproc remoteproc0: scp is available
10622 11:50:28.449753 <6>[ 18.151280] remoteproc remoteproc0: powering up scp
10623 11:50:28.459882 <6>[ 18.151287] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10624 11:50:28.463305 <6>[ 18.151317] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10625 11:50:28.469718 <6>[ 18.154114] pcieport 0000:00:00.0: AER: enabled with IRQ 281
10626 11:50:28.476585 <6>[ 18.167556] Bluetooth: HCI socket layer initialized
10627 11:50:28.482926 <6>[ 18.183247] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10628 11:50:28.485933 <6>[ 18.191980] Bluetooth: L2CAP socket layer initialized
10629 11:50:28.499200 <6>[ 18.195440] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10630 11:50:28.505917 <6>[ 18.198523] usbcore: registered new interface driver uvcvideo
10631 11:50:28.509129 <6>[ 18.204428] Bluetooth: SCO socket layer initialized
10632 11:50:28.519526 <6>[ 18.276859] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10633 11:50:28.525791 <6>[ 18.276860] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10634 11:50:28.532021 <6>[ 18.282181] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10635 11:50:28.535797 <6>[ 18.287129] r8152 2-1.3:1.0 eth0: v1.12.13
10636 11:50:28.542144 <6>[ 18.291120] remoteproc remoteproc0: remote processor scp is now up
10637 11:50:28.551940 <6>[ 18.297591] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10638 11:50:28.558701 <5>[ 18.299396] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10639 11:50:28.565082 <6>[ 18.308630] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10640 11:50:28.571637 <5>[ 18.309682] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10641 11:50:28.581705 <6>[ 18.312717] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10642 11:50:28.588659 <3>[ 18.321505] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10643 11:50:28.598324 <3>[ 18.324013] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10644 11:50:28.601438 <6>[ 18.324127] usbcore: registered new interface driver btusb
10645 11:50:28.614769 <4>[ 18.324752] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10646 11:50:28.618299 <3>[ 18.324765] Bluetooth: hci0: Failed to load firmware file (-2)
10647 11:50:28.624889 <3>[ 18.324768] Bluetooth: hci0: Failed to set up firmware (-2)
10648 11:50:28.634912 <4>[ 18.324771] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10649 11:50:28.644452 <3>[ 18.337968] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10650 11:50:28.654665 [[0;32m OK [<4>[ 18.624324] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10651 11:50:28.661534 0m] Created slic<6>[ 18.633429] cfg80211: failed to load regulatory.db
10652 11:50:28.668199 e [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10653 11:50:28.675003 <3>[ 18.645137] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10654 11:50:28.682771 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10655 11:50:28.702407 [[0;32m OK [<6>[ 18.671415] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10656 11:50:28.708682 0m] Reached targ<6>[ 18.680136] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10657 11:50:28.718758 et [0;1;39mSyst<3>[ 18.680409] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10658 11:50:28.722300 em Time Synchronized[0m.
10659 11:50:28.735260 <6>[ 18.708076] mt7921e 0000:01:00.0: ASIC revision: 79610010
10660 11:50:28.755151 <3>[ 18.724352] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10661 11:50:28.766177 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10662 11:50:28.788019 <3>[ 18.756949] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10663 11:50:28.794177 Starting [0;1;39mNetwork Name Resolution[0m...
10664 11:50:28.810975 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10665 11:50:28.842869 <4>[ 18.808324] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10666 11:50:28.870635 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10667 11:50:28.950479 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10668 11:50:28.963420 <4>[ 18.929128] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10669 11:50:28.967284 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10670 11:50:28.989774 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10671 11:50:29.002115 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10672 11:50:29.025734 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10673 11:50:29.045504 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10674 11:50:29.061928 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10675 11:50:29.082979 <4>[ 19.049010] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10676 11:50:29.095321 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10677 11:50:29.110807 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10678 11:50:29.126254 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10679 11:50:29.146142 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10680 11:50:29.205168 [[0;32m OK [0m] Started [0;<4>[ 19.169481] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10681 11:50:29.208391 1;39mD-Bus System Message Bus[0m.
10682 11:50:29.249509 Starting [0;1;39mUser Login Management[0m...
10683 11:50:29.271171 Starting [0;1;39mPermit User Sessions[0m...
10684 11:50:29.291047 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10685 11:50:29.329625 [[0;32m OK [<4>[ 19.296367] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10686 11:50:29.336034 0m] Finished [0;1;39mPermit User Sessions[0m.
10687 11:50:29.354635 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10688 11:50:29.375041 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10689 11:50:29.438451 <4>[ 19.404987] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10690 11:50:29.452465 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10691 11:50:29.476178 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10692 11:50:29.494893 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10693 11:50:29.510754 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10694 11:50:29.526794 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10695 11:50:29.559040 <4>[ 19.525738] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10696 11:50:29.592627 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10697 11:50:29.630560 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10698 11:50:29.679810 <4>[ 19.646258] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10699 11:50:29.679982
10700 11:50:29.680068
10701 11:50:29.686577 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10702 11:50:29.686773
10703 11:50:29.689468 debian-bullseye-arm64 login: root (automatic login)
10704 11:50:29.689657
10705 11:50:29.689757
10706 11:50:29.724892 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
10707 11:50:29.725262
10708 11:50:29.731227 The programs included with the Debian GNU/Linux system are free software;
10709 11:50:29.738069 the exact distribution terms for each program are described in the
10710 11:50:29.741267 individual files in /usr/share/doc/*/copyright.
10711 11:50:29.741733
10712 11:50:29.748106 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10713 11:50:29.751437 permitted by applicable law.
10714 11:50:29.752998 Matched prompt #10: / #
10716 11:50:29.754097 Setting prompt string to ['/ #']
10717 11:50:29.754560 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10719 11:50:29.755614 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10720 11:50:29.756093 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
10721 11:50:29.756477 Setting prompt string to ['/ #']
10722 11:50:29.756870 Forcing a shell prompt, looking for ['/ #']
10724 11:50:29.807859 / #
10725 11:50:29.808540 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10726 11:50:29.809013 Waiting using forced prompt support (timeout 00:02:30)
10727 11:50:29.809536 <4>[ 19.765458] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10728 11:50:29.814312
10729 11:50:29.815491 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10730 11:50:29.816062 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
10731 11:50:29.816617 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10732 11:50:29.817112 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
10733 11:50:29.817565 end: 2 depthcharge-action (duration 00:01:42) [common]
10734 11:50:29.818042 start: 3 lava-test-retry (timeout 00:05:00) [common]
10735 11:50:29.818505 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10736 11:50:29.818912 Using namespace: common
10738 11:50:29.920053 / # #
10739 11:50:29.920759 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10740 11:50:29.921434 #<6>[ 19.857650] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c6803bd: link becomes ready
10741 11:50:29.921822 <6>[ 19.865689] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10742 11:50:29.922176 <4>[ 19.886215] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10743 11:50:29.926532
10744 11:50:29.969595 Using /lava-12074062
10746 11:50:30.071070 / # export SHELL=/bin/sh
10747 11:50:30.071864 <3>[ 20.002712] mt7921e 0000:01:00.0: hardware init failed
10748 11:50:30.077985 export SHELL=/bin/sh
10750 11:50:30.179781 / # . /lava-12074062/environment
10751 11:50:30.186089 . /lava-12074062/environment
10753 11:50:30.287912 / # /lava-12074062/bin/lava-test-runner /lava-12074062/0
10754 11:50:30.288590 Test shell timeout: 10s (minimum of the action and connection timeout)
10755 11:50:30.294272 /lava-12074062/bin/lava-test-runner /lava-12074062/0
10756 11:50:30.313969 + export TESTRUN_ID=0_cros-ec
10757 11:50:30.320453 +<8>[ 20.291861] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12074062_1.5.2.3.1>
10758 11:50:30.321366 Received signal: <STARTRUN> 0_cros-ec 12074062_1.5.2.3.1
10759 11:50:30.321803 Starting test lava.0_cros-ec (12074062_1.5.2.3.1)
10760 11:50:30.322253 Skipping test definition patterns.
10761 11:50:30.323654 cd /lava-12074062/0/tests/0_cros-ec
10762 11:50:30.327163 + cat uuid
10763 11:50:30.327729 + UUID=12074062_1.5.2.3.1
10764 11:50:30.328109 + set +x
10765 11:50:30.333364 + python3 -m cros.runners.lava_runner -v
10766 11:50:30.681365 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
10767 11:50:30.687803 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
10768 11:50:30.691267
10769 11:50:30.694526 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10771 11:50:30.697493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
10772 11:50:30.704261 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
10773 11:50:30.711069 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
10774 11:50:30.711625
10775 11:50:30.717631 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_ac<8
10776 11:50:30.718233 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_ac<8', 'result': 'unknown'}
10777 11:50:30.724624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_ac<8>[ 20.694005] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12074062_1.5.2.3.1>
10778 11:50:30.725477 Received signal: <ENDRUN> 0_cros-ec 12074062_1.5.2.3.1
10779 11:50:30.725935 Ending use of test pattern.
10780 11:50:30.726285 Ending test lava.0_cros-ec (12074062_1.5.2.3.1), duration 0.40
10782 11:50:30.727874 cel_iio_data_is_valid RESULT=skip>
10783 11:50:30.730827 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
10784 11:50:30.737409 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
10785 11:50:30.737880
10786 11:50:30.744209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
10787 11:50:30.745116 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
10789 11:50:30.750829 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10790 11:50:30.757027 Checks the standard ABI for the main Embedded Controller. ... ok
10791 11:50:30.757579
10792 11:50:30.760452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
10793 11:50:30.761223 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
10795 11:50:30.767171 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
10796 11:50:30.773871 Checks the main Embedded controller character device. ... ok
10797 11:50:30.774433
10798 11:50:30.776738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
10799 11:50:30.777487 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
10801 11:50:30.783557 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10802 11:50:30.790545 Checks basic comunication with the main Embedded controller. ... ok
10803 11:50:30.791196
10804 11:50:30.796812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
10805 11:50:30.797558 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
10807 11:50:30.800227 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10808 11:50:30.810085 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
10809 11:50:30.810643
10810 11:50:30.813077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
10811 11:50:30.813897 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
10813 11:50:30.820022 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10814 11:50:30.826487 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
10815 11:50:30.827042
10816 11:50:30.833407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
10817 11:50:30.834251 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
10819 11:50:30.839907 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
10820 11:50:30.846496 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
10821 11:50:30.847064
10822 11:50:30.853174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
10823 11:50:30.854018 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
10825 11:50:30.856328 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10826 11:50:30.866266 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
10827 11:50:30.866835
10828 11:50:30.869350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
10829 11:50:30.870183 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
10831 11:50:30.876325 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10832 11:50:30.886048 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
10833 11:50:30.886621
10834 11:50:30.889306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
10835 11:50:30.890154 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
10837 11:50:30.895799 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10838 11:50:30.902481 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
10839 11:50:30.903042
10840 11:50:30.909130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
10841 11:50:30.909990 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
10843 11:50:30.915917 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10844 11:50:30.922191 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
10845 11:50:30.922749
10846 11:50:30.928932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
10847 11:50:30.929784 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
10849 11:50:30.935445 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
10850 11:50:30.941759 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
10851 11:50:30.942230
10852 11:50:30.948602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
10853 11:50:30.949363 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
10855 11:50:30.958651 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
10856 11:50:30.961643 Check the cros battery ABI. ... skipped 'No BAT found'
10857 11:50:30.962107
10858 11:50:30.968381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
10859 11:50:30.969284 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
10861 11:50:30.975257 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
10862 11:50:30.981486 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
10863 11:50:30.982049
10864 11:50:30.988180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
10865 11:50:30.989192 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
10867 11:50:30.991329 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
10868 11:50:30.997848 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
10869 11:50:31.001074
10870 11:50:31.004385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
10871 11:50:31.005233 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
10873 11:50:31.011070 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
10874 11:50:31.017736 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
10875 11:50:31.018299
10876 11:50:31.024355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
10877 11:50:31.024926
10878 11:50:31.025576 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
10880 11:50:31.031031 ----------------------------------------------------------------------
10881 11:50:31.034377 Ran 18 tests in 0.006s
10882 11:50:31.034944
10883 11:50:31.035313 OK (skipped=15)
10884 11:50:31.037412 + set +x
10885 11:50:31.037889 <LAVA_TEST_RUNNER EXIT>
10886 11:50:31.038538 ok: lava_test_shell seems to have completed
10887 11:50:31.039473 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
10888 11:50:31.039973 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10889 11:50:31.040464 end: 3 lava-test-retry (duration 00:00:01) [common]
10890 11:50:31.040991 start: 4 finalize (timeout 00:07:56) [common]
10891 11:50:31.041481 start: 4.1 power-off (timeout 00:00:30) [common]
10892 11:50:31.042304 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10893 11:50:31.152371 >> Command sent successfully.
10894 11:50:31.155497 Returned 0 in 0 seconds
10895 11:50:31.256489 end: 4.1 power-off (duration 00:00:00) [common]
10897 11:50:31.258289 start: 4.2 read-feedback (timeout 00:07:56) [common]
10898 11:50:31.259627 Listened to connection for namespace 'common' for up to 1s
10899 11:50:32.260267 Finalising connection for namespace 'common'
10900 11:50:32.260993 Disconnecting from shell: Finalise
10901 11:50:32.261395 / #
10902 11:50:32.362418 end: 4.2 read-feedback (duration 00:00:01) [common]
10903 11:50:32.363116 end: 4 finalize (duration 00:00:01) [common]
10904 11:50:32.363740 Cleaning after the job
10905 11:50:32.364271 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/ramdisk
10906 11:50:32.395779 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/kernel
10907 11:50:32.413188 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/dtb
10908 11:50:32.413449 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074062/tftp-deploy-yu09ioqk/modules
10909 11:50:32.423371 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074062
10910 11:50:32.541549 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074062
10911 11:50:32.541726 Job finished correctly