Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 33
- Kernel Warnings: 20
- Boot result: PASS
- Errors: 0
1 11:47:22.351289 lava-dispatcher, installed at version: 2023.10
2 11:47:22.351495 start: 0 validate
3 11:47:22.351629 Start time: 2023-11-24 11:47:22.351621+00:00 (UTC)
4 11:47:22.351756 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:47:22.351893 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:47:22.623592 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:47:22.623848 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:47:22.883085 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:47:22.883809 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:47:23.154484 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:47:23.155153 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:47:23.430246 validate duration: 1.08
14 11:47:23.431529 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:47:23.432020 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:47:23.432516 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:47:23.433107 Not decompressing ramdisk as can be used compressed.
18 11:47:23.433553 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 11:47:23.433882 saving as /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/ramdisk/rootfs.cpio.gz
20 11:47:23.434203 total size: 43284872 (41 MB)
21 11:47:23.439224 progress 0 % (0 MB)
22 11:47:23.474448 progress 5 % (2 MB)
23 11:47:23.487452 progress 10 % (4 MB)
24 11:47:23.498789 progress 15 % (6 MB)
25 11:47:23.510122 progress 20 % (8 MB)
26 11:47:23.521453 progress 25 % (10 MB)
27 11:47:23.532651 progress 30 % (12 MB)
28 11:47:23.543964 progress 35 % (14 MB)
29 11:47:23.555243 progress 40 % (16 MB)
30 11:47:23.566664 progress 45 % (18 MB)
31 11:47:23.578042 progress 50 % (20 MB)
32 11:47:23.589254 progress 55 % (22 MB)
33 11:47:23.600552 progress 60 % (24 MB)
34 11:47:23.611881 progress 65 % (26 MB)
35 11:47:23.623257 progress 70 % (28 MB)
36 11:47:23.634630 progress 75 % (30 MB)
37 11:47:23.645994 progress 80 % (33 MB)
38 11:47:23.657326 progress 85 % (35 MB)
39 11:47:23.669114 progress 90 % (37 MB)
40 11:47:23.680775 progress 95 % (39 MB)
41 11:47:23.692101 progress 100 % (41 MB)
42 11:47:23.692449 41 MB downloaded in 0.26 s (159.83 MB/s)
43 11:47:23.692619 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:47:23.692869 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:47:23.692959 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:47:23.693043 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:47:23.693179 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:47:23.693251 saving as /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/kernel/Image
50 11:47:23.693311 total size: 49107456 (46 MB)
51 11:47:23.693371 No compression specified
52 11:47:23.694566 progress 0 % (0 MB)
53 11:47:23.707590 progress 5 % (2 MB)
54 11:47:23.720588 progress 10 % (4 MB)
55 11:47:23.733891 progress 15 % (7 MB)
56 11:47:23.747425 progress 20 % (9 MB)
57 11:47:23.760805 progress 25 % (11 MB)
58 11:47:23.773818 progress 30 % (14 MB)
59 11:47:23.786923 progress 35 % (16 MB)
60 11:47:23.800542 progress 40 % (18 MB)
61 11:47:23.814445 progress 45 % (21 MB)
62 11:47:23.828186 progress 50 % (23 MB)
63 11:47:23.842340 progress 55 % (25 MB)
64 11:47:23.855475 progress 60 % (28 MB)
65 11:47:23.868580 progress 65 % (30 MB)
66 11:47:23.881658 progress 70 % (32 MB)
67 11:47:23.894917 progress 75 % (35 MB)
68 11:47:23.908092 progress 80 % (37 MB)
69 11:47:23.921196 progress 85 % (39 MB)
70 11:47:23.934314 progress 90 % (42 MB)
71 11:47:23.947312 progress 95 % (44 MB)
72 11:47:23.959850 progress 100 % (46 MB)
73 11:47:23.960089 46 MB downloaded in 0.27 s (175.55 MB/s)
74 11:47:23.960284 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:47:23.960512 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:47:23.960601 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:47:23.960688 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:47:23.960826 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:47:23.960895 saving as /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/dtb/mt8192-asurada-spherion-r0.dtb
81 11:47:23.960956 total size: 47278 (0 MB)
82 11:47:23.961016 No compression specified
83 11:47:23.962344 progress 69 % (0 MB)
84 11:47:23.962618 progress 100 % (0 MB)
85 11:47:23.962772 0 MB downloaded in 0.00 s (24.84 MB/s)
86 11:47:23.962893 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:47:23.963112 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:47:23.963196 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:47:23.963278 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:47:23.963392 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:47:23.963463 saving as /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/modules/modules.tar
93 11:47:23.963523 total size: 8624756 (8 MB)
94 11:47:23.963583 Using unxz to decompress xz
95 11:47:23.967949 progress 0 % (0 MB)
96 11:47:23.989883 progress 5 % (0 MB)
97 11:47:24.015805 progress 10 % (0 MB)
98 11:47:24.042413 progress 15 % (1 MB)
99 11:47:24.068755 progress 20 % (1 MB)
100 11:47:24.095212 progress 25 % (2 MB)
101 11:47:24.123216 progress 30 % (2 MB)
102 11:47:24.150819 progress 35 % (2 MB)
103 11:47:24.174808 progress 40 % (3 MB)
104 11:47:24.199763 progress 45 % (3 MB)
105 11:47:24.225983 progress 50 % (4 MB)
106 11:47:24.251367 progress 55 % (4 MB)
107 11:47:24.276884 progress 60 % (4 MB)
108 11:47:24.305335 progress 65 % (5 MB)
109 11:47:24.331563 progress 70 % (5 MB)
110 11:47:24.357226 progress 75 % (6 MB)
111 11:47:24.386743 progress 80 % (6 MB)
112 11:47:24.414872 progress 85 % (7 MB)
113 11:47:24.442289 progress 90 % (7 MB)
114 11:47:24.476742 progress 95 % (7 MB)
115 11:47:24.506764 progress 100 % (8 MB)
116 11:47:24.511930 8 MB downloaded in 0.55 s (15.00 MB/s)
117 11:47:24.512184 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:47:24.512487 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:47:24.512579 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:47:24.512699 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:47:24.512804 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:47:24.512922 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:47:24.513189 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x
125 11:47:24.513327 makedir: /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin
126 11:47:24.513433 makedir: /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/tests
127 11:47:24.513531 makedir: /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/results
128 11:47:24.513649 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-add-keys
129 11:47:24.513802 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-add-sources
130 11:47:24.513932 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-background-process-start
131 11:47:24.514062 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-background-process-stop
132 11:47:24.514192 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-common-functions
133 11:47:24.514316 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-echo-ipv4
134 11:47:24.514439 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-install-packages
135 11:47:24.514561 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-installed-packages
136 11:47:24.514714 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-os-build
137 11:47:24.514837 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-probe-channel
138 11:47:24.514962 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-probe-ip
139 11:47:24.515086 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-target-ip
140 11:47:24.515207 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-target-mac
141 11:47:24.515331 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-target-storage
142 11:47:24.515458 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-test-case
143 11:47:24.515581 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-test-event
144 11:47:24.515702 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-test-feedback
145 11:47:24.515824 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-test-raise
146 11:47:24.515946 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-test-reference
147 11:47:24.516069 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-test-runner
148 11:47:24.516191 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-test-set
149 11:47:24.516354 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-test-shell
150 11:47:24.516480 Updating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-install-packages (oe)
151 11:47:24.516633 Updating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/bin/lava-installed-packages (oe)
152 11:47:24.516760 Creating /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/environment
153 11:47:24.516861 LAVA metadata
154 11:47:24.516932 - LAVA_JOB_ID=12074030
155 11:47:24.516995 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:47:24.517096 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:47:24.517164 skipped lava-vland-overlay
158 11:47:24.517237 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:47:24.517334 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:47:24.517447 skipped lava-multinode-overlay
161 11:47:24.517582 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:47:24.517703 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:47:24.517783 Loading test definitions
164 11:47:24.517872 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:47:24.517947 Using /lava-12074030 at stage 0
166 11:47:24.518260 uuid=12074030_1.5.2.3.1 testdef=None
167 11:47:24.518346 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:47:24.518431 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:47:24.518955 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:47:24.519169 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:47:24.519781 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:47:24.520005 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:47:24.520649 runner path: /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/0/tests/0_igt-gpu-panfrost test_uuid 12074030_1.5.2.3.1
176 11:47:24.520852 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:47:24.521057 Creating lava-test-runner.conf files
179 11:47:24.521118 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074030/lava-overlay-chsubs9x/lava-12074030/0 for stage 0
180 11:47:24.521205 - 0_igt-gpu-panfrost
181 11:47:24.521299 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:47:24.521380 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:47:24.528096 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:47:24.528227 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:47:24.528328 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:47:24.528413 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:47:24.528503 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:47:25.974372 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:47:25.974792 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 11:47:25.974913 extracting modules file /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074030/extract-overlay-ramdisk-_b7c4g2r/ramdisk
191 11:47:26.221869 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:47:26.222038 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 11:47:26.222136 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074030/compress-overlay-g13oib4r/overlay-1.5.2.4.tar.gz to ramdisk
194 11:47:26.222213 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074030/compress-overlay-g13oib4r/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074030/extract-overlay-ramdisk-_b7c4g2r/ramdisk
195 11:47:26.229441 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:47:26.229601 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 11:47:26.229726 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:47:26.229855 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 11:47:26.229975 Building ramdisk /var/lib/lava/dispatcher/tmp/12074030/extract-overlay-ramdisk-_b7c4g2r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074030/extract-overlay-ramdisk-_b7c4g2r/ramdisk
200 11:47:27.240931 >> 369976 blocks
201 11:47:33.272836 rename /var/lib/lava/dispatcher/tmp/12074030/extract-overlay-ramdisk-_b7c4g2r/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/ramdisk/ramdisk.cpio.gz
202 11:47:33.273338 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 11:47:33.273467 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 11:47:33.273571 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 11:47:33.273689 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/kernel/Image'
206 11:47:46.120859 Returned 0 in 12 seconds
207 11:47:46.221492 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/kernel/image.itb
208 11:47:47.015516 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:47:47.015888 output: Created: Fri Nov 24 11:47:46 2023
210 11:47:47.015959 output: Image 0 (kernel-1)
211 11:47:47.016026 output: Description:
212 11:47:47.016088 output: Created: Fri Nov 24 11:47:46 2023
213 11:47:47.016150 output: Type: Kernel Image
214 11:47:47.016215 output: Compression: lzma compressed
215 11:47:47.016274 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
216 11:47:47.016328 output: Architecture: AArch64
217 11:47:47.016380 output: OS: Linux
218 11:47:47.016436 output: Load Address: 0x00000000
219 11:47:47.016489 output: Entry Point: 0x00000000
220 11:47:47.016543 output: Hash algo: crc32
221 11:47:47.016594 output: Hash value: 43cfb6ad
222 11:47:47.016650 output: Image 1 (fdt-1)
223 11:47:47.016703 output: Description: mt8192-asurada-spherion-r0
224 11:47:47.016754 output: Created: Fri Nov 24 11:47:46 2023
225 11:47:47.016806 output: Type: Flat Device Tree
226 11:47:47.016858 output: Compression: uncompressed
227 11:47:47.016909 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:47:47.016960 output: Architecture: AArch64
229 11:47:47.017011 output: Hash algo: crc32
230 11:47:47.017062 output: Hash value: cc4352de
231 11:47:47.017113 output: Image 2 (ramdisk-1)
232 11:47:47.017164 output: Description: unavailable
233 11:47:47.017214 output: Created: Fri Nov 24 11:47:46 2023
234 11:47:47.017265 output: Type: RAMDisk Image
235 11:47:47.017316 output: Compression: Unknown Compression
236 11:47:47.017367 output: Data Size: 56411674 Bytes = 55089.53 KiB = 53.80 MiB
237 11:47:47.017418 output: Architecture: AArch64
238 11:47:47.017469 output: OS: Linux
239 11:47:47.017519 output: Load Address: unavailable
240 11:47:47.017570 output: Entry Point: unavailable
241 11:47:47.017621 output: Hash algo: crc32
242 11:47:47.017671 output: Hash value: cc129e7f
243 11:47:47.017721 output: Default Configuration: 'conf-1'
244 11:47:47.017772 output: Configuration 0 (conf-1)
245 11:47:47.017822 output: Description: mt8192-asurada-spherion-r0
246 11:47:47.017873 output: Kernel: kernel-1
247 11:47:47.017922 output: Init Ramdisk: ramdisk-1
248 11:47:47.017973 output: FDT: fdt-1
249 11:47:47.018023 output: Loadables: kernel-1
250 11:47:47.018073 output:
251 11:47:47.018276 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 11:47:47.018378 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 11:47:47.018479 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 11:47:47.018573 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 11:47:47.018648 No LXC device requested
256 11:47:47.018726 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:47:47.018809 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 11:47:47.018882 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:47:47.018951 Checking files for TFTP limit of 4294967296 bytes.
260 11:47:47.019448 end: 1 tftp-deploy (duration 00:00:24) [common]
261 11:47:47.019548 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:47:47.019637 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:47:47.019756 substitutions:
264 11:47:47.019821 - {DTB}: 12074030/tftp-deploy-k89iqby6/dtb/mt8192-asurada-spherion-r0.dtb
265 11:47:47.019884 - {INITRD}: 12074030/tftp-deploy-k89iqby6/ramdisk/ramdisk.cpio.gz
266 11:47:47.019941 - {KERNEL}: 12074030/tftp-deploy-k89iqby6/kernel/Image
267 11:47:47.019997 - {LAVA_MAC}: None
268 11:47:47.020053 - {PRESEED_CONFIG}: None
269 11:47:47.020107 - {PRESEED_LOCAL}: None
270 11:47:47.020160 - {RAMDISK}: 12074030/tftp-deploy-k89iqby6/ramdisk/ramdisk.cpio.gz
271 11:47:47.020224 - {ROOT_PART}: None
272 11:47:47.020280 - {ROOT}: None
273 11:47:47.020333 - {SERVER_IP}: 192.168.201.1
274 11:47:47.020385 - {TEE}: None
275 11:47:47.020437 Parsed boot commands:
276 11:47:47.020489 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:47:47.020662 Parsed boot commands: tftpboot 192.168.201.1 12074030/tftp-deploy-k89iqby6/kernel/image.itb 12074030/tftp-deploy-k89iqby6/kernel/cmdline
278 11:47:47.020749 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:47:47.020834 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:47:47.020926 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:47:47.021007 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:47:47.021077 Not connected, no need to disconnect.
283 11:47:47.021148 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:47:47.021227 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:47:47.021289 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 11:47:47.025217 Setting prompt string to ['lava-test: # ']
287 11:47:47.025591 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:47:47.025716 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:47:47.025831 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:47:47.025964 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:47:47.026203 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 11:47:52.154382 >> Command sent successfully.
293 11:47:52.157388 Returned 0 in 5 seconds
294 11:47:52.257736 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:47:52.258055 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:47:52.258150 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:47:52.258235 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:47:52.258300 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:47:52.258365 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:47:52.258635 [Enter `^Ec?' for help]
302 11:47:52.430231
303 11:47:52.430390
304 11:47:52.430465 F0: 102B 0000
305 11:47:52.430539
306 11:47:52.433918 F3: 1001 0000 [0200]
307 11:47:52.433999
308 11:47:52.434065 F3: 1001 0000
309 11:47:52.434125
310 11:47:52.434181 F7: 102D 0000
311 11:47:52.434239
312 11:47:52.437722 F1: 0000 0000
313 11:47:52.437805
314 11:47:52.437870 V0: 0000 0000 [0001]
315 11:47:52.437932
316 11:47:52.437997 00: 0007 8000
317 11:47:52.438061
318 11:47:52.441684 01: 0000 0000
319 11:47:52.441765
320 11:47:52.441829 BP: 0C00 0209 [0000]
321 11:47:52.441888
322 11:47:52.445059 G0: 1182 0000
323 11:47:52.445137
324 11:47:52.445200 EC: 0000 0021 [4000]
325 11:47:52.445260
326 11:47:52.448661 S7: 0000 0000 [0000]
327 11:47:52.448761
328 11:47:52.448832 CC: 0000 0000 [0001]
329 11:47:52.448895
330 11:47:52.451761 T0: 0000 0040 [010F]
331 11:47:52.451866
332 11:47:52.451957 Jump to BL
333 11:47:52.452056
334 11:47:52.477541
335 11:47:52.477696
336 11:47:52.477793
337 11:47:52.485560 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:47:52.488904 ARM64: Exception handlers installed.
339 11:47:52.492435 ARM64: Testing exception
340 11:47:52.496423 ARM64: Done test exception
341 11:47:52.503720 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:47:52.510383 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:47:52.520345 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:47:52.530708 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:47:52.537270 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:47:52.544055 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:47:52.554771 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:47:52.561041 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:47:52.580101 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:47:52.583813 WDT: Last reset was cold boot
351 11:47:52.586734 SPI1(PAD0) initialized at 2873684 Hz
352 11:47:52.590534 SPI5(PAD0) initialized at 992727 Hz
353 11:47:52.593395 VBOOT: Loading verstage.
354 11:47:52.600383 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:47:52.603487 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:47:52.606810 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:47:52.610145 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:47:52.617576 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:47:52.624051 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:47:52.635421 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
361 11:47:52.635515
362 11:47:52.635582
363 11:47:52.645290 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:47:52.648577 ARM64: Exception handlers installed.
365 11:47:52.652107 ARM64: Testing exception
366 11:47:52.652242 ARM64: Done test exception
367 11:47:52.658598 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:47:52.662161 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:47:52.676614 Probing TPM: . done!
370 11:47:52.676709 TPM ready after 0 ms
371 11:47:52.683219 Connected to device vid:did:rid of 1ae0:0028:00
372 11:47:52.690039 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 11:47:52.730422 Initialized TPM device CR50 revision 0
374 11:47:52.741879 tlcl_send_startup: Startup return code is 0
375 11:47:52.741987 TPM: setup succeeded
376 11:47:52.753327 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:47:52.761936 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:47:52.775011 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:47:52.782809 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:47:52.786176 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:47:52.790397 in-header: 03 07 00 00 08 00 00 00
382 11:47:52.793725 in-data: aa e4 47 04 13 02 00 00
383 11:47:52.797502 Chrome EC: UHEPI supported
384 11:47:52.804529 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:47:52.808427 in-header: 03 9d 00 00 08 00 00 00
386 11:47:52.811796 in-data: 10 20 20 08 00 00 00 00
387 11:47:52.811881 Phase 1
388 11:47:52.819098 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:47:52.822903 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:47:52.830105 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:47:52.834094 Recovery requested (1009000e)
392 11:47:52.839086 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:47:52.844571 tlcl_extend: response is 0
394 11:47:52.852562 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:47:52.858311 tlcl_extend: response is 0
396 11:47:52.864707 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:47:52.886065 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
398 11:47:52.892739 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:47:52.892867
400 11:47:52.892956
401 11:47:52.901275 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:47:52.905119 ARM64: Exception handlers installed.
403 11:47:52.908498 ARM64: Testing exception
404 11:47:52.908585 ARM64: Done test exception
405 11:47:52.928311 pmic_efuse_setting: Set efuses in 11 msecs
406 11:47:52.937011 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:47:52.940344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:47:52.944117 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:47:52.951374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:47:52.955317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:47:52.959023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:47:52.962641 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:47:52.970072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:47:52.973725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:47:52.976857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:47:52.983491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:47:52.986874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:47:52.993577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:47:52.997145 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:47:53.003478 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:47:53.010395 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:47:53.013315 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:47:53.020331 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:47:53.026763 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:47:53.030069 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:47:53.037350 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:47:53.041243 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:47:53.048369 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:47:53.054884 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:47:53.058377 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:47:53.065497 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:47:53.068866 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:47:53.075650 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:47:53.078973 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:47:53.085804 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:47:53.089601 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:47:53.093143 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:47:53.099993 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:47:53.103974 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:47:53.110710 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:47:53.114516 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:47:53.121338 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:47:53.124724 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:47:53.128548 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:47:53.135146 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:47:53.138495 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:47:53.141721 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:47:53.148391 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:47:53.151570 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:47:53.155153 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:47:53.161558 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:47:53.164999 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:47:53.168144 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:47:53.174862 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:47:53.178552 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:47:53.181894 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:47:53.185113 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:47:53.195077 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:47:53.201812 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:47:53.208068 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:47:53.215042 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:47:53.225143 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:47:53.228525 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:47:53.231520 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:47:53.238098 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:47:53.244992 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x14
467 11:47:53.248358 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:47:53.255338 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 11:47:53.258713 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:47:53.268048 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 11:47:53.271210 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 11:47:53.278292 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 11:47:53.281742 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
474 11:47:53.284617 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 11:47:53.288082 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
476 11:47:53.291324 ADC[4]: Raw value=898150 ID=7
477 11:47:53.294497 ADC[3]: Raw value=213440 ID=1
478 11:47:53.294580 RAM Code: 0x71
479 11:47:53.301321 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 11:47:53.304749 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 11:47:53.315186 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 11:47:53.321754 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 11:47:53.325069 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 11:47:53.328058 in-header: 03 07 00 00 08 00 00 00
485 11:47:53.331347 in-data: aa e4 47 04 13 02 00 00
486 11:47:53.334965 Chrome EC: UHEPI supported
487 11:47:53.342089 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 11:47:53.346137 in-header: 03 d5 00 00 08 00 00 00
489 11:47:53.346219 in-data: 98 20 60 08 00 00 00 00
490 11:47:53.349568 MRC: failed to locate region type 0.
491 11:47:53.356958 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 11:47:53.360398 DRAM-K: Running full calibration
493 11:47:53.367361 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 11:47:53.367443 header.status = 0x0
495 11:47:53.371119 header.version = 0x6 (expected: 0x6)
496 11:47:53.374519 header.size = 0xd00 (expected: 0xd00)
497 11:47:53.377703 header.flags = 0x0
498 11:47:53.381095 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 11:47:53.400398 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
500 11:47:53.407083 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 11:47:53.410471 dram_init: ddr_geometry: 2
502 11:47:53.413628 [EMI] MDL number = 2
503 11:47:53.413711 [EMI] Get MDL freq = 0
504 11:47:53.416723 dram_init: ddr_type: 0
505 11:47:53.416805 is_discrete_lpddr4: 1
506 11:47:53.420121 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 11:47:53.420234
508 11:47:53.420302
509 11:47:53.423638 [Bian_co] ETT version 0.0.0.1
510 11:47:53.429851 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 11:47:53.429934
512 11:47:53.433492 dramc_set_vcore_voltage set vcore to 650000
513 11:47:53.436792 Read voltage for 800, 4
514 11:47:53.436875 Vio18 = 0
515 11:47:53.436939 Vcore = 650000
516 11:47:53.437000 Vdram = 0
517 11:47:53.440078 Vddq = 0
518 11:47:53.440213 Vmddr = 0
519 11:47:53.443234 dram_init: config_dvfs: 1
520 11:47:53.446774 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 11:47:53.453458 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 11:47:53.456868 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 11:47:53.459730 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 11:47:53.463233 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 11:47:53.466776 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 11:47:53.470056 MEM_TYPE=3, freq_sel=18
527 11:47:53.473548 sv_algorithm_assistance_LP4_1600
528 11:47:53.476979 ============ PULL DRAM RESETB DOWN ============
529 11:47:53.479842 ========== PULL DRAM RESETB DOWN end =========
530 11:47:53.486527 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 11:47:53.489750 ===================================
532 11:47:53.493437 LPDDR4 DRAM CONFIGURATION
533 11:47:53.496655 ===================================
534 11:47:53.496764 EX_ROW_EN[0] = 0x0
535 11:47:53.500020 EX_ROW_EN[1] = 0x0
536 11:47:53.500119 LP4Y_EN = 0x0
537 11:47:53.503265 WORK_FSP = 0x0
538 11:47:53.503347 WL = 0x2
539 11:47:53.506604 RL = 0x2
540 11:47:53.506687 BL = 0x2
541 11:47:53.510027 RPST = 0x0
542 11:47:53.510110 RD_PRE = 0x0
543 11:47:53.513507 WR_PRE = 0x1
544 11:47:53.513589 WR_PST = 0x0
545 11:47:53.516451 DBI_WR = 0x0
546 11:47:53.516534 DBI_RD = 0x0
547 11:47:53.520002 OTF = 0x1
548 11:47:53.524029 ===================================
549 11:47:53.527403 ===================================
550 11:47:53.527485 ANA top config
551 11:47:53.530782 ===================================
552 11:47:53.534775 DLL_ASYNC_EN = 0
553 11:47:53.534858 ALL_SLAVE_EN = 1
554 11:47:53.538281 NEW_RANK_MODE = 1
555 11:47:53.541632 DLL_IDLE_MODE = 1
556 11:47:53.545513 LP45_APHY_COMB_EN = 1
557 11:47:53.545611 TX_ODT_DIS = 1
558 11:47:53.549238 NEW_8X_MODE = 1
559 11:47:53.552971 ===================================
560 11:47:53.556546 ===================================
561 11:47:53.559912 data_rate = 1600
562 11:47:53.560000 CKR = 1
563 11:47:53.563900 DQ_P2S_RATIO = 8
564 11:47:53.567471 ===================================
565 11:47:53.571185 CA_P2S_RATIO = 8
566 11:47:53.571318 DQ_CA_OPEN = 0
567 11:47:53.575101 DQ_SEMI_OPEN = 0
568 11:47:53.578635 CA_SEMI_OPEN = 0
569 11:47:53.582188 CA_FULL_RATE = 0
570 11:47:53.582301 DQ_CKDIV4_EN = 1
571 11:47:53.586214 CA_CKDIV4_EN = 1
572 11:47:53.589769 CA_PREDIV_EN = 0
573 11:47:53.593084 PH8_DLY = 0
574 11:47:53.593168 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 11:47:53.597374 DQ_AAMCK_DIV = 4
576 11:47:53.601332 CA_AAMCK_DIV = 4
577 11:47:53.604445 CA_ADMCK_DIV = 4
578 11:47:53.604528 DQ_TRACK_CA_EN = 0
579 11:47:53.608079 CA_PICK = 800
580 11:47:53.612362 CA_MCKIO = 800
581 11:47:53.615707 MCKIO_SEMI = 0
582 11:47:53.618655 PLL_FREQ = 3068
583 11:47:53.618738 DQ_UI_PI_RATIO = 32
584 11:47:53.622181 CA_UI_PI_RATIO = 0
585 11:47:53.625729 ===================================
586 11:47:53.629305 ===================================
587 11:47:53.632170 memory_type:LPDDR4
588 11:47:53.635946 GP_NUM : 10
589 11:47:53.636070 SRAM_EN : 1
590 11:47:53.639249 MD32_EN : 0
591 11:47:53.642098 ===================================
592 11:47:53.642201 [ANA_INIT] >>>>>>>>>>>>>>
593 11:47:53.645880 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 11:47:53.649355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 11:47:53.652404 ===================================
596 11:47:53.655639 data_rate = 1600,PCW = 0X7600
597 11:47:53.659082 ===================================
598 11:47:53.662501 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 11:47:53.669055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 11:47:53.675966 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 11:47:53.679172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 11:47:53.682343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 11:47:53.686443 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 11:47:53.686858 [ANA_INIT] flow start
605 11:47:53.689808 [ANA_INIT] PLL >>>>>>>>
606 11:47:53.693262 [ANA_INIT] PLL <<<<<<<<
607 11:47:53.693618 [ANA_INIT] MIDPI >>>>>>>>
608 11:47:53.696734 [ANA_INIT] MIDPI <<<<<<<<
609 11:47:53.700089 [ANA_INIT] DLL >>>>>>>>
610 11:47:53.700482 [ANA_INIT] flow end
611 11:47:53.704098 ============ LP4 DIFF to SE enter ============
612 11:47:53.707959 ============ LP4 DIFF to SE exit ============
613 11:47:53.711530 [ANA_INIT] <<<<<<<<<<<<<
614 11:47:53.715369 [Flow] Enable top DCM control >>>>>
615 11:47:53.718578 [Flow] Enable top DCM control <<<<<
616 11:47:53.722703 Enable DLL master slave shuffle
617 11:47:53.726619 ==============================================================
618 11:47:53.730043 Gating Mode config
619 11:47:53.733248 ==============================================================
620 11:47:53.736650 Config description:
621 11:47:53.746507 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 11:47:53.753497 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 11:47:53.756440 SELPH_MODE 0: By rank 1: By Phase
624 11:47:53.763089 ==============================================================
625 11:47:53.766590 GAT_TRACK_EN = 1
626 11:47:53.770084 RX_GATING_MODE = 2
627 11:47:53.772887 RX_GATING_TRACK_MODE = 2
628 11:47:53.773275 SELPH_MODE = 1
629 11:47:53.776563 PICG_EARLY_EN = 1
630 11:47:53.779777 VALID_LAT_VALUE = 1
631 11:47:53.786349 ==============================================================
632 11:47:53.790222 Enter into Gating configuration >>>>
633 11:47:53.793282 Exit from Gating configuration <<<<
634 11:47:53.796468 Enter into DVFS_PRE_config >>>>>
635 11:47:53.806449 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 11:47:53.809932 Exit from DVFS_PRE_config <<<<<
637 11:47:53.813244 Enter into PICG configuration >>>>
638 11:47:53.816758 Exit from PICG configuration <<<<
639 11:47:53.820057 [RX_INPUT] configuration >>>>>
640 11:47:53.823005 [RX_INPUT] configuration <<<<<
641 11:47:53.826970 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 11:47:53.833560 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 11:47:53.839606 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 11:47:53.846892 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 11:47:53.849773 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 11:47:53.856800 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 11:47:53.859780 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 11:47:53.866546 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 11:47:53.870095 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 11:47:53.873526 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 11:47:53.876364 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 11:47:53.884279 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 11:47:53.884801 ===================================
654 11:47:53.887794 LPDDR4 DRAM CONFIGURATION
655 11:47:53.891790 ===================================
656 11:47:53.892177 EX_ROW_EN[0] = 0x0
657 11:47:53.895172 EX_ROW_EN[1] = 0x0
658 11:47:53.895729 LP4Y_EN = 0x0
659 11:47:53.898923 WORK_FSP = 0x0
660 11:47:53.899473 WL = 0x2
661 11:47:53.902885 RL = 0x2
662 11:47:53.903348 BL = 0x2
663 11:47:53.906440 RPST = 0x0
664 11:47:53.906894 RD_PRE = 0x0
665 11:47:53.910079 WR_PRE = 0x1
666 11:47:53.910637 WR_PST = 0x0
667 11:47:53.914045 DBI_WR = 0x0
668 11:47:53.914505 DBI_RD = 0x0
669 11:47:53.917350 OTF = 0x1
670 11:47:53.921386 ===================================
671 11:47:53.924703 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 11:47:53.928979 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 11:47:53.932472 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 11:47:53.936193 ===================================
675 11:47:53.936637 LPDDR4 DRAM CONFIGURATION
676 11:47:53.939434 ===================================
677 11:47:53.943333 EX_ROW_EN[0] = 0x10
678 11:47:53.943836 EX_ROW_EN[1] = 0x0
679 11:47:53.946907 LP4Y_EN = 0x0
680 11:47:53.947380 WORK_FSP = 0x0
681 11:47:53.950327 WL = 0x2
682 11:47:53.950847 RL = 0x2
683 11:47:53.954513 BL = 0x2
684 11:47:53.954921 RPST = 0x0
685 11:47:53.958586 RD_PRE = 0x0
686 11:47:53.959010 WR_PRE = 0x1
687 11:47:53.961627 WR_PST = 0x0
688 11:47:53.962242 DBI_WR = 0x0
689 11:47:53.965653 DBI_RD = 0x0
690 11:47:53.966059 OTF = 0x1
691 11:47:53.969364 ===================================
692 11:47:53.976608 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 11:47:53.979992 nWR fixed to 40
694 11:47:53.980455 [ModeRegInit_LP4] CH0 RK0
695 11:47:53.983431 [ModeRegInit_LP4] CH0 RK1
696 11:47:53.987417 [ModeRegInit_LP4] CH1 RK0
697 11:47:53.987823 [ModeRegInit_LP4] CH1 RK1
698 11:47:53.991718 match AC timing 13
699 11:47:53.995208 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 11:47:53.999162 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 11:47:54.002594 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 11:47:54.006547 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 11:47:54.013341 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 11:47:54.013770 [EMI DOE] emi_dcm 0
705 11:47:54.017387 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 11:47:54.017793 ==
707 11:47:54.021011 Dram Type= 6, Freq= 0, CH_0, rank 0
708 11:47:54.025249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 11:47:54.025658 ==
710 11:47:54.032515 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 11:47:54.036016 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 11:47:54.046568 [CA 0] Center 38 (7~69) winsize 63
713 11:47:54.050467 [CA 1] Center 37 (7~68) winsize 62
714 11:47:54.053978 [CA 2] Center 35 (5~66) winsize 62
715 11:47:54.057513 [CA 3] Center 35 (5~66) winsize 62
716 11:47:54.061137 [CA 4] Center 34 (4~65) winsize 62
717 11:47:54.065182 [CA 5] Center 34 (4~65) winsize 62
718 11:47:54.065588
719 11:47:54.068775 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 11:47:54.069182
721 11:47:54.072131 [CATrainingPosCal] consider 1 rank data
722 11:47:54.072585 u2DelayCellTimex100 = 270/100 ps
723 11:47:54.076235 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 11:47:54.079667 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 11:47:54.083775 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 11:47:54.087016 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 11:47:54.091136 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 11:47:54.094469 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 11:47:54.094871
730 11:47:54.098293 CA PerBit enable=1, Macro0, CA PI delay=34
731 11:47:54.098700
732 11:47:54.101580 [CBTSetCACLKResult] CA Dly = 34
733 11:47:54.105128 CS Dly: 6 (0~37)
734 11:47:54.105535 ==
735 11:47:54.109005 Dram Type= 6, Freq= 0, CH_0, rank 1
736 11:47:54.112474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 11:47:54.112880 ==
738 11:47:54.116584 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 11:47:54.123410 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 11:47:54.133330 [CA 0] Center 38 (7~69) winsize 63
741 11:47:54.136933 [CA 1] Center 38 (7~69) winsize 63
742 11:47:54.140651 [CA 2] Center 35 (5~66) winsize 62
743 11:47:54.144124 [CA 3] Center 35 (5~66) winsize 62
744 11:47:54.148107 [CA 4] Center 34 (4~65) winsize 62
745 11:47:54.148565 [CA 5] Center 34 (4~65) winsize 62
746 11:47:54.151442
747 11:47:54.154734 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 11:47:54.155426
749 11:47:54.158849 [CATrainingPosCal] consider 2 rank data
750 11:47:54.159281 u2DelayCellTimex100 = 270/100 ps
751 11:47:54.162387 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 11:47:54.166027 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 11:47:54.170119 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 11:47:54.176578 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 11:47:54.179969 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 11:47:54.182970 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 11:47:54.183372
758 11:47:54.186354 CA PerBit enable=1, Macro0, CA PI delay=34
759 11:47:54.186757
760 11:47:54.189760 [CBTSetCACLKResult] CA Dly = 34
761 11:47:54.190223 CS Dly: 6 (0~38)
762 11:47:54.190645
763 11:47:54.193032 ----->DramcWriteLeveling(PI) begin...
764 11:47:54.193457 ==
765 11:47:54.196649 Dram Type= 6, Freq= 0, CH_0, rank 0
766 11:47:54.203238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 11:47:54.203645 ==
768 11:47:54.206388 Write leveling (Byte 0): 34 => 34
769 11:47:54.209479 Write leveling (Byte 1): 29 => 29
770 11:47:54.209884 DramcWriteLeveling(PI) end<-----
771 11:47:54.210298
772 11:47:54.212898 ==
773 11:47:54.216125 Dram Type= 6, Freq= 0, CH_0, rank 0
774 11:47:54.219802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 11:47:54.220237 ==
776 11:47:54.223175 [Gating] SW mode calibration
777 11:47:54.229862 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 11:47:54.233384 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 11:47:54.239930 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 11:47:54.242948 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 11:47:54.246530 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
782 11:47:54.252985 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 11:47:54.256869 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 11:47:54.259611 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 11:47:54.263504 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 11:47:54.270337 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 11:47:54.273907 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 11:47:54.277959 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:47:54.281486 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:47:54.288517 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:47:54.292001 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:47:54.295270 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:47:54.298657 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:47:54.305678 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:47:54.308853 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:47:54.312021 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:47:54.318816 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
798 11:47:54.322587 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
799 11:47:54.326051 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:47:54.328999 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:47:54.335908 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:47:54.339378 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:47:54.342324 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:47:54.348843 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:47:54.352182 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:47:54.355836 0 9 12 | B1->B0 | 2a2a 2d2d | 1 0 | (0 0) (0 0)
807 11:47:54.361997 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 11:47:54.365644 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 11:47:54.368815 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 11:47:54.375570 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 11:47:54.378605 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 11:47:54.382044 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 11:47:54.388876 0 10 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
814 11:47:54.392503 0 10 12 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
815 11:47:54.395414 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:47:54.402342 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:47:54.405722 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:47:54.408915 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 11:47:54.415824 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 11:47:54.419270 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 11:47:54.422600 0 11 8 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (0 0)
822 11:47:54.425803 0 11 12 | B1->B0 | 3131 4646 | 0 0 | (1 1) (0 0)
823 11:47:54.432317 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 11:47:54.435470 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 11:47:54.439017 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 11:47:54.445416 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 11:47:54.448981 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 11:47:54.452390 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 11:47:54.459076 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 11:47:54.462200 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 11:47:54.465426 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 11:47:54.472301 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 11:47:54.475834 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 11:47:54.479002 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 11:47:54.485439 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 11:47:54.489004 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 11:47:54.492180 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:47:54.499205 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:47:54.502246 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:47:54.505839 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:47:54.512779 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:47:54.515936 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:47:54.518858 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:47:54.522325 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:47:54.529187 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 11:47:54.532582 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 11:47:54.535912 Total UI for P1: 0, mck2ui 16
848 11:47:54.538959 best dqsien dly found for B0: ( 0, 14, 8)
849 11:47:54.542478 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 11:47:54.545814 Total UI for P1: 0, mck2ui 16
851 11:47:54.549375 best dqsien dly found for B1: ( 0, 14, 12)
852 11:47:54.552159 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
853 11:47:54.555742 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 11:47:54.559006
855 11:47:54.562297 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 11:47:54.565795 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 11:47:54.569234 [Gating] SW calibration Done
858 11:47:54.569654 ==
859 11:47:54.572095 Dram Type= 6, Freq= 0, CH_0, rank 0
860 11:47:54.575651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 11:47:54.576068 ==
862 11:47:54.576442 RX Vref Scan: 0
863 11:47:54.576753
864 11:47:54.578975 RX Vref 0 -> 0, step: 1
865 11:47:54.579392
866 11:47:54.582509 RX Delay -130 -> 252, step: 16
867 11:47:54.585253 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 11:47:54.588721 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 11:47:54.595714 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 11:47:54.599028 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 11:47:54.602429 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 11:47:54.605593 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 11:47:54.608703 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 11:47:54.615391 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 11:47:54.618972 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 11:47:54.622070 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
877 11:47:54.625625 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 11:47:54.629035 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 11:47:54.635424 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 11:47:54.638671 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 11:47:54.642125 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 11:47:54.645454 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 11:47:54.645839 ==
884 11:47:54.649005 Dram Type= 6, Freq= 0, CH_0, rank 0
885 11:47:54.655354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 11:47:54.655758 ==
887 11:47:54.656115 DQS Delay:
888 11:47:54.656444 DQS0 = 0, DQS1 = 0
889 11:47:54.658623 DQM Delay:
890 11:47:54.659002 DQM0 = 81, DQM1 = 70
891 11:47:54.662320 DQ Delay:
892 11:47:54.665558 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
893 11:47:54.665943 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 11:47:54.669009 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
895 11:47:54.671924 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 11:47:54.675646
897 11:47:54.676026
898 11:47:54.676376 ==
899 11:47:54.679019 Dram Type= 6, Freq= 0, CH_0, rank 0
900 11:47:54.683015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 11:47:54.683398 ==
902 11:47:54.683804
903 11:47:54.684275
904 11:47:54.684731 TX Vref Scan disable
905 11:47:54.686506 == TX Byte 0 ==
906 11:47:54.690255 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
907 11:47:54.693639 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
908 11:47:54.696452 == TX Byte 1 ==
909 11:47:54.700337 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
910 11:47:54.703295 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
911 11:47:54.706849 ==
912 11:47:54.710404 Dram Type= 6, Freq= 0, CH_0, rank 0
913 11:47:54.713782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 11:47:54.714164 ==
915 11:47:54.726254 TX Vref=22, minBit 1, minWin=27, winSum=435
916 11:47:54.730045 TX Vref=24, minBit 5, minWin=27, winSum=441
917 11:47:54.733387 TX Vref=26, minBit 8, minWin=27, winSum=446
918 11:47:54.736840 TX Vref=28, minBit 8, minWin=27, winSum=443
919 11:47:54.739693 TX Vref=30, minBit 4, minWin=27, winSum=443
920 11:47:54.743042 TX Vref=32, minBit 2, minWin=27, winSum=443
921 11:47:54.749956 [TxChooseVref] Worse bit 8, Min win 27, Win sum 446, Final Vref 26
922 11:47:54.750457
923 11:47:54.752959 Final TX Range 1 Vref 26
924 11:47:54.753515
925 11:47:54.753856 ==
926 11:47:54.756612 Dram Type= 6, Freq= 0, CH_0, rank 0
927 11:47:54.759621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 11:47:54.760044 ==
929 11:47:54.760450
930 11:47:54.760763
931 11:47:54.763583 TX Vref Scan disable
932 11:47:54.766516 == TX Byte 0 ==
933 11:47:54.769888 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
934 11:47:54.773275 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
935 11:47:54.776315 == TX Byte 1 ==
936 11:47:54.779688 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
937 11:47:54.783204 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
938 11:47:54.786529
939 11:47:54.786959 [DATLAT]
940 11:47:54.787400 Freq=800, CH0 RK0
941 11:47:54.787819
942 11:47:54.789746 DATLAT Default: 0xa
943 11:47:54.790312 0, 0xFFFF, sum = 0
944 11:47:54.793278 1, 0xFFFF, sum = 0
945 11:47:54.793731 2, 0xFFFF, sum = 0
946 11:47:54.796723 3, 0xFFFF, sum = 0
947 11:47:54.797164 4, 0xFFFF, sum = 0
948 11:47:54.799662 5, 0xFFFF, sum = 0
949 11:47:54.800101 6, 0xFFFF, sum = 0
950 11:47:54.803185 7, 0xFFFF, sum = 0
951 11:47:54.806558 8, 0xFFFF, sum = 0
952 11:47:54.806999 9, 0x0, sum = 1
953 11:47:54.807451 10, 0x0, sum = 2
954 11:47:54.809524 11, 0x0, sum = 3
955 11:47:54.809963 12, 0x0, sum = 4
956 11:47:54.813095 best_step = 10
957 11:47:54.813524
958 11:47:54.813963 ==
959 11:47:54.816403 Dram Type= 6, Freq= 0, CH_0, rank 0
960 11:47:54.819950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 11:47:54.820452 ==
962 11:47:54.822959 RX Vref Scan: 1
963 11:47:54.823393
964 11:47:54.823833 Set Vref Range= 32 -> 127
965 11:47:54.824404
966 11:47:54.826212 RX Vref 32 -> 127, step: 1
967 11:47:54.826646
968 11:47:54.830083 RX Delay -111 -> 252, step: 8
969 11:47:54.830516
970 11:47:54.833101 Set Vref, RX VrefLevel [Byte0]: 32
971 11:47:54.836323 [Byte1]: 32
972 11:47:54.836760
973 11:47:54.839899 Set Vref, RX VrefLevel [Byte0]: 33
974 11:47:54.842931 [Byte1]: 33
975 11:47:54.846676
976 11:47:54.847164 Set Vref, RX VrefLevel [Byte0]: 34
977 11:47:54.850163 [Byte1]: 34
978 11:47:54.854199
979 11:47:54.854633 Set Vref, RX VrefLevel [Byte0]: 35
980 11:47:54.857808 [Byte1]: 35
981 11:47:54.862403
982 11:47:54.862845 Set Vref, RX VrefLevel [Byte0]: 36
983 11:47:54.865472 [Byte1]: 36
984 11:47:54.869756
985 11:47:54.870304 Set Vref, RX VrefLevel [Byte0]: 37
986 11:47:54.872787 [Byte1]: 37
987 11:47:54.877522
988 11:47:54.877932 Set Vref, RX VrefLevel [Byte0]: 38
989 11:47:54.880946 [Byte1]: 38
990 11:47:54.884998
991 11:47:54.885456 Set Vref, RX VrefLevel [Byte0]: 39
992 11:47:54.888603 [Byte1]: 39
993 11:47:54.892749
994 11:47:54.893203 Set Vref, RX VrefLevel [Byte0]: 40
995 11:47:54.895962 [Byte1]: 40
996 11:47:54.900588
997 11:47:54.901000 Set Vref, RX VrefLevel [Byte0]: 41
998 11:47:54.903619 [Byte1]: 41
999 11:47:54.908234
1000 11:47:54.908657 Set Vref, RX VrefLevel [Byte0]: 42
1001 11:47:54.911117 [Byte1]: 42
1002 11:47:54.915778
1003 11:47:54.916453 Set Vref, RX VrefLevel [Byte0]: 43
1004 11:47:54.919106 [Byte1]: 43
1005 11:47:54.923512
1006 11:47:54.923923 Set Vref, RX VrefLevel [Byte0]: 44
1007 11:47:54.926871 [Byte1]: 44
1008 11:47:54.931026
1009 11:47:54.931437 Set Vref, RX VrefLevel [Byte0]: 45
1010 11:47:54.934408 [Byte1]: 45
1011 11:47:54.939299
1012 11:47:54.939780 Set Vref, RX VrefLevel [Byte0]: 46
1013 11:47:54.942622 [Byte1]: 46
1014 11:47:54.946664
1015 11:47:54.947092 Set Vref, RX VrefLevel [Byte0]: 47
1016 11:47:54.949827 [Byte1]: 47
1017 11:47:54.954153
1018 11:47:54.954585 Set Vref, RX VrefLevel [Byte0]: 48
1019 11:47:54.957933 [Byte1]: 48
1020 11:47:54.961457
1021 11:47:54.962031 Set Vref, RX VrefLevel [Byte0]: 49
1022 11:47:54.965091 [Byte1]: 49
1023 11:47:54.969563
1024 11:47:54.970161 Set Vref, RX VrefLevel [Byte0]: 50
1025 11:47:54.972363 [Byte1]: 50
1026 11:47:54.976644
1027 11:47:54.977094 Set Vref, RX VrefLevel [Byte0]: 51
1028 11:47:54.980175 [Byte1]: 51
1029 11:47:54.984848
1030 11:47:54.985252 Set Vref, RX VrefLevel [Byte0]: 52
1031 11:47:54.987779 [Byte1]: 52
1032 11:47:54.992499
1033 11:47:54.992902 Set Vref, RX VrefLevel [Byte0]: 53
1034 11:47:54.995293 [Byte1]: 53
1035 11:47:54.999964
1036 11:47:55.000410 Set Vref, RX VrefLevel [Byte0]: 54
1037 11:47:55.003315 [Byte1]: 54
1038 11:47:55.007248
1039 11:47:55.007692 Set Vref, RX VrefLevel [Byte0]: 55
1040 11:47:55.010842 [Byte1]: 55
1041 11:47:55.014963
1042 11:47:55.015369 Set Vref, RX VrefLevel [Byte0]: 56
1043 11:47:55.018631 [Byte1]: 56
1044 11:47:55.022584
1045 11:47:55.022988 Set Vref, RX VrefLevel [Byte0]: 57
1046 11:47:55.026247 [Byte1]: 57
1047 11:47:55.030468
1048 11:47:55.030981 Set Vref, RX VrefLevel [Byte0]: 58
1049 11:47:55.033684 [Byte1]: 58
1050 11:47:55.038212
1051 11:47:55.038681 Set Vref, RX VrefLevel [Byte0]: 59
1052 11:47:55.041187 [Byte1]: 59
1053 11:47:55.045918
1054 11:47:55.046341 Set Vref, RX VrefLevel [Byte0]: 60
1055 11:47:55.048932 [Byte1]: 60
1056 11:47:55.053107
1057 11:47:55.053524 Set Vref, RX VrefLevel [Byte0]: 61
1058 11:47:55.056435 [Byte1]: 61
1059 11:47:55.060935
1060 11:47:55.061374 Set Vref, RX VrefLevel [Byte0]: 62
1061 11:47:55.064432 [Byte1]: 62
1062 11:47:55.068468
1063 11:47:55.068882 Set Vref, RX VrefLevel [Byte0]: 63
1064 11:47:55.071708 [Byte1]: 63
1065 11:47:55.076280
1066 11:47:55.076806 Set Vref, RX VrefLevel [Byte0]: 64
1067 11:47:55.079825 [Byte1]: 64
1068 11:47:55.084161
1069 11:47:55.084709 Set Vref, RX VrefLevel [Byte0]: 65
1070 11:47:55.087227 [Byte1]: 65
1071 11:47:55.091515
1072 11:47:55.091926 Set Vref, RX VrefLevel [Byte0]: 66
1073 11:47:55.094808 [Byte1]: 66
1074 11:47:55.099121
1075 11:47:55.099645 Set Vref, RX VrefLevel [Byte0]: 67
1076 11:47:55.102649 [Byte1]: 67
1077 11:47:55.106897
1078 11:47:55.107477 Set Vref, RX VrefLevel [Byte0]: 68
1079 11:47:55.109839 [Byte1]: 68
1080 11:47:55.114881
1081 11:47:55.115291 Set Vref, RX VrefLevel [Byte0]: 69
1082 11:47:55.117820 [Byte1]: 69
1083 11:47:55.121882
1084 11:47:55.122290 Set Vref, RX VrefLevel [Byte0]: 70
1085 11:47:55.125246 [Byte1]: 70
1086 11:47:55.130058
1087 11:47:55.130470 Set Vref, RX VrefLevel [Byte0]: 71
1088 11:47:55.132927 [Byte1]: 71
1089 11:47:55.137432
1090 11:47:55.137839 Set Vref, RX VrefLevel [Byte0]: 72
1091 11:47:55.140514 [Byte1]: 72
1092 11:47:55.145001
1093 11:47:55.145413 Set Vref, RX VrefLevel [Byte0]: 73
1094 11:47:55.151889 [Byte1]: 73
1095 11:47:55.152438
1096 11:47:55.154711 Set Vref, RX VrefLevel [Byte0]: 74
1097 11:47:55.158247 [Byte1]: 74
1098 11:47:55.158690
1099 11:47:55.161769 Set Vref, RX VrefLevel [Byte0]: 75
1100 11:47:55.165125 [Byte1]: 75
1101 11:47:55.165708
1102 11:47:55.168017 Set Vref, RX VrefLevel [Byte0]: 76
1103 11:47:55.171532 [Byte1]: 76
1104 11:47:55.175547
1105 11:47:55.176101 Set Vref, RX VrefLevel [Byte0]: 77
1106 11:47:55.178995 [Byte1]: 77
1107 11:47:55.183540
1108 11:47:55.183953 Set Vref, RX VrefLevel [Byte0]: 78
1109 11:47:55.186307 [Byte1]: 78
1110 11:47:55.190724
1111 11:47:55.191133 Set Vref, RX VrefLevel [Byte0]: 79
1112 11:47:55.194087 [Byte1]: 79
1113 11:47:55.198531
1114 11:47:55.198944 Set Vref, RX VrefLevel [Byte0]: 80
1115 11:47:55.201868 [Byte1]: 80
1116 11:47:55.206283
1117 11:47:55.206693 Final RX Vref Byte 0 = 61 to rank0
1118 11:47:55.209453 Final RX Vref Byte 1 = 56 to rank0
1119 11:47:55.212744 Final RX Vref Byte 0 = 61 to rank1
1120 11:47:55.215984 Final RX Vref Byte 1 = 56 to rank1==
1121 11:47:55.219258 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 11:47:55.225997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 11:47:55.226412 ==
1124 11:47:55.226867 DQS Delay:
1125 11:47:55.227185 DQS0 = 0, DQS1 = 0
1126 11:47:55.229606 DQM Delay:
1127 11:47:55.230022 DQM0 = 82, DQM1 = 67
1128 11:47:55.233024 DQ Delay:
1129 11:47:55.236425 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1130 11:47:55.236845 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1131 11:47:55.239278 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1132 11:47:55.242824 DQ12 =72, DQ13 =68, DQ14 =76, DQ15 =76
1133 11:47:55.246190
1134 11:47:55.246606
1135 11:47:55.252659 [DQSOSCAuto] RK0, (LSB)MR18= 0x2524, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1136 11:47:55.256329 CH0 RK0: MR19=606, MR18=2524
1137 11:47:55.262662 CH0_RK0: MR19=0x606, MR18=0x2524, DQSOSC=400, MR23=63, INC=92, DEC=61
1138 11:47:55.263079
1139 11:47:55.266123 ----->DramcWriteLeveling(PI) begin...
1140 11:47:55.266546 ==
1141 11:47:55.269632 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 11:47:55.273159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 11:47:55.273592 ==
1144 11:47:55.276054 Write leveling (Byte 0): 30 => 30
1145 11:47:55.279454 Write leveling (Byte 1): 28 => 28
1146 11:47:55.282929 DramcWriteLeveling(PI) end<-----
1147 11:47:55.283355
1148 11:47:55.283679 ==
1149 11:47:55.286468 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 11:47:55.289365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 11:47:55.289804 ==
1152 11:47:55.292684 [Gating] SW mode calibration
1153 11:47:55.299542 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 11:47:55.306003 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 11:47:55.309403 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 11:47:55.312921 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 11:47:55.319360 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1158 11:47:55.322783 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:47:55.326506 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:47:55.332953 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:47:55.336197 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:47:55.339545 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:47:55.342987 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:47:55.349862 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:47:55.352869 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:47:55.397411 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:47:55.397843 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:47:55.398171 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:47:55.398477 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:47:55.399107 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:47:55.399431 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:47:55.399723 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1173 11:47:55.400005 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1174 11:47:55.400321 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1175 11:47:55.400681 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:47:55.441112 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:47:55.441663 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:47:55.442545 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:47:55.443034 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:47:55.443503 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:47:55.443991 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1182 11:47:55.444422 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1183 11:47:55.444742 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 11:47:55.445108 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 11:47:55.445459 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 11:47:55.466557 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 11:47:55.467303 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 11:47:55.467656 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
1189 11:47:55.467989 0 10 8 | B1->B0 | 3030 2b2b | 0 1 | (0 0) (1 0)
1190 11:47:55.468442 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1191 11:47:55.470525 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:47:55.473679 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:47:55.476874 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:47:55.480293 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:47:55.483827 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:47:55.490545 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1197 11:47:55.494038 0 11 8 | B1->B0 | 3232 3f3f | 1 1 | (0 0) (0 0)
1198 11:47:55.497579 0 11 12 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
1199 11:47:55.504054 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:47:55.507480 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:47:55.511032 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 11:47:55.514444 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 11:47:55.522097 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 11:47:55.525463 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1205 11:47:55.529017 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1206 11:47:55.532543 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1207 11:47:55.539954 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:47:55.543008 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:47:55.546414 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:47:55.549984 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:47:55.556133 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:47:55.559607 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:47:55.563286 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:47:55.569550 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:47:55.573471 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:47:55.576284 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:47:55.583143 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:47:55.586503 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:47:55.589659 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:47:55.596244 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:47:55.599371 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1222 11:47:55.602752 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 11:47:55.605966 Total UI for P1: 0, mck2ui 16
1224 11:47:55.609405 best dqsien dly found for B0: ( 0, 14, 8)
1225 11:47:55.612934 Total UI for P1: 0, mck2ui 16
1226 11:47:55.616351 best dqsien dly found for B1: ( 0, 14, 8)
1227 11:47:55.619489 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1228 11:47:55.622880 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 11:47:55.623087
1230 11:47:55.626400 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 11:47:55.632807 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 11:47:55.633140 [Gating] SW calibration Done
1233 11:47:55.633395 ==
1234 11:47:55.635947 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 11:47:55.642389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 11:47:55.642470 ==
1237 11:47:55.642534 RX Vref Scan: 0
1238 11:47:55.642593
1239 11:47:55.645983 RX Vref 0 -> 0, step: 1
1240 11:47:55.646067
1241 11:47:55.649451 RX Delay -130 -> 252, step: 16
1242 11:47:55.652935 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1243 11:47:55.655683 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1244 11:47:55.659202 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1245 11:47:55.666167 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1246 11:47:55.669088 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1247 11:47:55.672545 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1248 11:47:55.676161 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1249 11:47:55.679310 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1250 11:47:55.682697 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1251 11:47:55.689429 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1252 11:47:55.692388 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1253 11:47:55.695786 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1254 11:47:55.699381 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1255 11:47:55.705695 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1256 11:47:55.709308 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1257 11:47:55.712721 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1258 11:47:55.712807 ==
1259 11:47:55.716066 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 11:47:55.719199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 11:47:55.719300 ==
1262 11:47:55.722695 DQS Delay:
1263 11:47:55.722811 DQS0 = 0, DQS1 = 0
1264 11:47:55.722890 DQM Delay:
1265 11:47:55.726224 DQM0 = 79, DQM1 = 69
1266 11:47:55.726334 DQ Delay:
1267 11:47:55.729458 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =77
1268 11:47:55.732787 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
1269 11:47:55.735899 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1270 11:47:55.739426 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1271 11:47:55.739575
1272 11:47:55.739693
1273 11:47:55.739801 ==
1274 11:47:55.742418 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 11:47:55.749444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 11:47:55.749645 ==
1277 11:47:55.749801
1278 11:47:55.749946
1279 11:47:55.750086 TX Vref Scan disable
1280 11:47:55.752932 == TX Byte 0 ==
1281 11:47:55.756473 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1282 11:47:55.759944 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1283 11:47:55.763372 == TX Byte 1 ==
1284 11:47:55.766388 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1285 11:47:55.770019 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1286 11:47:55.773475 ==
1287 11:47:55.776568 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 11:47:55.779808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 11:47:55.780418 ==
1290 11:47:55.792356 TX Vref=22, minBit 1, minWin=26, winSum=435
1291 11:47:55.795894 TX Vref=24, minBit 1, minWin=27, winSum=441
1292 11:47:55.799499 TX Vref=26, minBit 1, minWin=27, winSum=445
1293 11:47:55.802504 TX Vref=28, minBit 1, minWin=27, winSum=444
1294 11:47:55.805952 TX Vref=30, minBit 1, minWin=27, winSum=445
1295 11:47:55.809390 TX Vref=32, minBit 2, minWin=27, winSum=445
1296 11:47:55.816096 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 26
1297 11:47:55.816567
1298 11:47:55.819013 Final TX Range 1 Vref 26
1299 11:47:55.819418
1300 11:47:55.819734 ==
1301 11:47:55.822448 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 11:47:55.825935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 11:47:55.826342 ==
1304 11:47:55.826660
1305 11:47:55.826958
1306 11:47:55.829355 TX Vref Scan disable
1307 11:47:55.832891 == TX Byte 0 ==
1308 11:47:55.835572 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1309 11:47:55.839006 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1310 11:47:55.842366 == TX Byte 1 ==
1311 11:47:55.845631 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1312 11:47:55.849431 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1313 11:47:55.852249
1314 11:47:55.852653 [DATLAT]
1315 11:47:55.852972 Freq=800, CH0 RK1
1316 11:47:55.853274
1317 11:47:55.855860 DATLAT Default: 0xa
1318 11:47:55.856307 0, 0xFFFF, sum = 0
1319 11:47:55.859378 1, 0xFFFF, sum = 0
1320 11:47:55.859974 2, 0xFFFF, sum = 0
1321 11:47:55.862480 3, 0xFFFF, sum = 0
1322 11:47:55.862913 4, 0xFFFF, sum = 0
1323 11:47:55.865473 5, 0xFFFF, sum = 0
1324 11:47:55.865886 6, 0xFFFF, sum = 0
1325 11:47:55.869113 7, 0xFFFF, sum = 0
1326 11:47:55.869526 8, 0xFFFF, sum = 0
1327 11:47:55.872544 9, 0x0, sum = 1
1328 11:47:55.872954 10, 0x0, sum = 2
1329 11:47:55.875534 11, 0x0, sum = 3
1330 11:47:55.876028 12, 0x0, sum = 4
1331 11:47:55.879000 best_step = 10
1332 11:47:55.879401
1333 11:47:55.879717 ==
1334 11:47:55.882601 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 11:47:55.885477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 11:47:55.885913 ==
1337 11:47:55.889139 RX Vref Scan: 0
1338 11:47:55.889547
1339 11:47:55.889868 RX Vref 0 -> 0, step: 1
1340 11:47:55.890226
1341 11:47:55.892260 RX Delay -111 -> 252, step: 8
1342 11:47:55.898882 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1343 11:47:55.902819 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1344 11:47:55.905480 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1345 11:47:55.909129 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1346 11:47:55.912542 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1347 11:47:55.918923 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1348 11:47:55.922458 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1349 11:47:55.925927 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1350 11:47:55.929164 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1351 11:47:55.932326 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1352 11:47:55.939172 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1353 11:47:55.942409 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1354 11:47:55.946013 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1355 11:47:55.948935 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1356 11:47:55.952364 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1357 11:47:55.958748 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1358 11:47:55.959227 ==
1359 11:47:55.962037 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 11:47:55.965310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 11:47:55.965883 ==
1362 11:47:55.966220 DQS Delay:
1363 11:47:55.969023 DQS0 = 0, DQS1 = 0
1364 11:47:55.969476 DQM Delay:
1365 11:47:55.972251 DQM0 = 79, DQM1 = 69
1366 11:47:55.972661 DQ Delay:
1367 11:47:55.975597 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1368 11:47:55.978853 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1369 11:47:55.982073 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1370 11:47:55.985642 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1371 11:47:55.986178
1372 11:47:55.986525
1373 11:47:55.992576 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1374 11:47:55.996007 CH0 RK1: MR19=606, MR18=4B25
1375 11:47:56.002604 CH0_RK1: MR19=0x606, MR18=0x4B25, DQSOSC=391, MR23=63, INC=96, DEC=64
1376 11:47:56.005947 [RxdqsGatingPostProcess] freq 800
1377 11:47:56.012759 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 11:47:56.016190 Pre-setting of DQS Precalculation
1379 11:47:56.019008 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 11:47:56.019414 ==
1381 11:47:56.022629 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 11:47:56.026090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 11:47:56.026500 ==
1384 11:47:56.032397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 11:47:56.039151 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 11:47:56.047498 [CA 0] Center 36 (6~66) winsize 61
1387 11:47:56.050953 [CA 1] Center 36 (6~67) winsize 62
1388 11:47:56.054003 [CA 2] Center 34 (4~64) winsize 61
1389 11:47:56.057429 [CA 3] Center 34 (4~64) winsize 61
1390 11:47:56.060431 [CA 4] Center 34 (4~64) winsize 61
1391 11:47:56.063809 [CA 5] Center 34 (4~64) winsize 61
1392 11:47:56.064281
1393 11:47:56.067315 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1394 11:47:56.067840
1395 11:47:56.070587 [CATrainingPosCal] consider 1 rank data
1396 11:47:56.074198 u2DelayCellTimex100 = 270/100 ps
1397 11:47:56.077396 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1398 11:47:56.080619 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 11:47:56.087422 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 11:47:56.090853 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 11:47:56.094239 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1402 11:47:56.096984 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 11:47:56.097539
1404 11:47:56.100753 CA PerBit enable=1, Macro0, CA PI delay=34
1405 11:47:56.101339
1406 11:47:56.103791 [CBTSetCACLKResult] CA Dly = 34
1407 11:47:56.104505 CS Dly: 5 (0~36)
1408 11:47:56.107262 ==
1409 11:47:56.107805 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 11:47:56.114160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 11:47:56.114846 ==
1412 11:47:56.117593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 11:47:56.123940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 11:47:56.133367 [CA 0] Center 37 (7~67) winsize 61
1415 11:47:56.136696 [CA 1] Center 37 (7~67) winsize 61
1416 11:47:56.140367 [CA 2] Center 35 (5~65) winsize 61
1417 11:47:56.143937 [CA 3] Center 33 (3~64) winsize 62
1418 11:47:56.146789 [CA 4] Center 34 (4~65) winsize 62
1419 11:47:56.149953 [CA 5] Center 33 (3~64) winsize 62
1420 11:47:56.150380
1421 11:47:56.153431 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1422 11:47:56.153843
1423 11:47:56.156618 [CATrainingPosCal] consider 2 rank data
1424 11:47:56.159929 u2DelayCellTimex100 = 270/100 ps
1425 11:47:56.163551 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1426 11:47:56.166917 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1427 11:47:56.170900 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1428 11:47:56.174361 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 11:47:56.178440 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 11:47:56.181891 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 11:47:56.182303
1432 11:47:56.185435 CA PerBit enable=1, Macro0, CA PI delay=34
1433 11:47:56.185843
1434 11:47:56.189267 [CBTSetCACLKResult] CA Dly = 34
1435 11:47:56.192683 CS Dly: 6 (0~38)
1436 11:47:56.193291
1437 11:47:56.196649 ----->DramcWriteLeveling(PI) begin...
1438 11:47:56.197068 ==
1439 11:47:56.200243 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 11:47:56.203740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 11:47:56.204151 ==
1442 11:47:56.207689 Write leveling (Byte 0): 26 => 26
1443 11:47:56.208127 Write leveling (Byte 1): 31 => 31
1444 11:47:56.211111 DramcWriteLeveling(PI) end<-----
1445 11:47:56.211534
1446 11:47:56.211964 ==
1447 11:47:56.214506 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 11:47:56.220947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 11:47:56.221364 ==
1450 11:47:56.224297 [Gating] SW mode calibration
1451 11:47:56.231160 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 11:47:56.234170 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 11:47:56.241084 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 11:47:56.244036 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1455 11:47:56.247700 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 11:47:56.250631 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:47:56.257666 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:47:56.260706 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:47:56.264316 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:47:56.270665 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:47:56.274045 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:47:56.277429 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:47:56.284247 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:47:56.287919 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:47:56.290993 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:47:56.297415 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:47:56.300796 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:47:56.304447 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:47:56.310835 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:47:56.314252 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1471 11:47:56.317790 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1472 11:47:56.324091 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:47:56.327517 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:47:56.330814 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:47:56.337548 0 8 24 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1476 11:47:56.341032 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:47:56.344023 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:47:56.347533 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:47:56.354472 0 9 8 | B1->B0 | 2929 2626 | 0 1 | (0 0) (1 1)
1480 11:47:56.357410 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:47:56.360819 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 11:47:56.367845 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 11:47:56.370894 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 11:47:56.374025 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 11:47:56.380905 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 11:47:56.384516 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 11:47:56.387305 0 10 8 | B1->B0 | 2d2d 2d2d | 1 0 | (1 1) (0 1)
1488 11:47:56.394291 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:47:56.397842 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:47:56.400741 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:47:56.407506 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:47:56.410625 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:47:56.413721 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:47:56.420660 0 11 4 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
1495 11:47:56.424176 0 11 8 | B1->B0 | 3939 3838 | 0 1 | (1 1) (0 0)
1496 11:47:56.427029 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:47:56.434120 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 11:47:56.437678 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 11:47:56.440391 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:47:56.447255 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 11:47:56.450701 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 11:47:56.454140 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 11:47:56.460543 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1504 11:47:56.464134 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:47:56.467578 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:47:56.470515 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:47:56.477233 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:47:56.480418 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:47:56.483910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:47:56.490880 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:47:56.494284 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:47:56.497170 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:47:56.504150 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:47:56.507021 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:47:56.510584 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:47:56.516810 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:47:56.520782 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 11:47:56.523879 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1519 11:47:56.530507 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 11:47:56.533920 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 11:47:56.537420 Total UI for P1: 0, mck2ui 16
1522 11:47:56.540305 best dqsien dly found for B0: ( 0, 14, 8)
1523 11:47:56.543767 Total UI for P1: 0, mck2ui 16
1524 11:47:56.547099 best dqsien dly found for B1: ( 0, 14, 6)
1525 11:47:56.550440 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1526 11:47:56.553793 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1527 11:47:56.554238
1528 11:47:56.557306 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1529 11:47:56.560606 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1530 11:47:56.563990 [Gating] SW calibration Done
1531 11:47:56.564443 ==
1532 11:47:56.567576 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 11:47:56.570626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 11:47:56.571047 ==
1535 11:47:56.574209 RX Vref Scan: 0
1536 11:47:56.574724
1537 11:47:56.577426 RX Vref 0 -> 0, step: 1
1538 11:47:56.577842
1539 11:47:56.578171 RX Delay -130 -> 252, step: 16
1540 11:47:56.583911 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1541 11:47:56.587293 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1542 11:47:56.590101 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1543 11:47:56.593912 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1544 11:47:56.596939 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1545 11:47:56.603789 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1546 11:47:56.606978 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1547 11:47:56.610528 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1548 11:47:56.614089 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1549 11:47:56.616977 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1550 11:47:56.623693 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1551 11:47:56.626704 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1552 11:47:56.630127 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1553 11:47:56.633449 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1554 11:47:56.637108 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1555 11:47:56.643576 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1556 11:47:56.643993 ==
1557 11:47:56.647123 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 11:47:56.650621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 11:47:56.651090 ==
1560 11:47:56.651431 DQS Delay:
1561 11:47:56.653909 DQS0 = 0, DQS1 = 0
1562 11:47:56.654324 DQM Delay:
1563 11:47:56.657174 DQM0 = 83, DQM1 = 74
1564 11:47:56.657589 DQ Delay:
1565 11:47:56.660172 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1566 11:47:56.663691 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1567 11:47:56.667009 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1568 11:47:56.670432 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1569 11:47:56.670872
1570 11:47:56.671203
1571 11:47:56.671511 ==
1572 11:47:56.673297 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 11:47:56.676793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 11:47:56.677210 ==
1575 11:47:56.680309
1576 11:47:56.680863
1577 11:47:56.681322 TX Vref Scan disable
1578 11:47:56.683786 == TX Byte 0 ==
1579 11:47:56.686929 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1580 11:47:56.690219 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1581 11:47:56.693772 == TX Byte 1 ==
1582 11:47:56.696657 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1583 11:47:56.700374 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1584 11:47:56.700919 ==
1585 11:47:56.703641 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 11:47:56.710007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 11:47:56.710424 ==
1588 11:47:56.722242 TX Vref=22, minBit 1, minWin=27, winSum=443
1589 11:47:56.725696 TX Vref=24, minBit 1, minWin=27, winSum=445
1590 11:47:56.729211 TX Vref=26, minBit 1, minWin=27, winSum=447
1591 11:47:56.732637 TX Vref=28, minBit 8, minWin=27, winSum=451
1592 11:47:56.735609 TX Vref=30, minBit 5, minWin=27, winSum=450
1593 11:47:56.739043 TX Vref=32, minBit 5, minWin=27, winSum=448
1594 11:47:56.746135 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 28
1595 11:47:56.746552
1596 11:47:56.749788 Final TX Range 1 Vref 28
1597 11:47:56.750200
1598 11:47:56.750523 ==
1599 11:47:56.753174 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 11:47:56.756570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 11:47:56.757110 ==
1602 11:47:56.757581
1603 11:47:56.758079
1604 11:47:56.759827 TX Vref Scan disable
1605 11:47:56.763471 == TX Byte 0 ==
1606 11:47:56.766287 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1607 11:47:56.769848 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1608 11:47:56.773133 == TX Byte 1 ==
1609 11:47:56.776503 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1610 11:47:56.780045 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1611 11:47:56.780581
1612 11:47:56.783647 [DATLAT]
1613 11:47:56.784060 Freq=800, CH1 RK0
1614 11:47:56.784443
1615 11:47:56.786762 DATLAT Default: 0xa
1616 11:47:56.787172 0, 0xFFFF, sum = 0
1617 11:47:56.789953 1, 0xFFFF, sum = 0
1618 11:47:56.790506 2, 0xFFFF, sum = 0
1619 11:47:56.793480 3, 0xFFFF, sum = 0
1620 11:47:56.793904 4, 0xFFFF, sum = 0
1621 11:47:56.796671 5, 0xFFFF, sum = 0
1622 11:47:56.797089 6, 0xFFFF, sum = 0
1623 11:47:56.800251 7, 0xFFFF, sum = 0
1624 11:47:56.800684 8, 0xFFFF, sum = 0
1625 11:47:56.803622 9, 0x0, sum = 1
1626 11:47:56.804038 10, 0x0, sum = 2
1627 11:47:56.806472 11, 0x0, sum = 3
1628 11:47:56.806932 12, 0x0, sum = 4
1629 11:47:56.809963 best_step = 10
1630 11:47:56.810466
1631 11:47:56.810795 ==
1632 11:47:56.813217 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 11:47:56.816705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 11:47:56.817117 ==
1635 11:47:56.817442 RX Vref Scan: 1
1636 11:47:56.820088
1637 11:47:56.820572 Set Vref Range= 32 -> 127
1638 11:47:56.820905
1639 11:47:56.823426 RX Vref 32 -> 127, step: 1
1640 11:47:56.823834
1641 11:47:56.826566 RX Delay -111 -> 252, step: 8
1642 11:47:56.826979
1643 11:47:56.830004 Set Vref, RX VrefLevel [Byte0]: 32
1644 11:47:56.833716 [Byte1]: 32
1645 11:47:56.834130
1646 11:47:56.836716 Set Vref, RX VrefLevel [Byte0]: 33
1647 11:47:56.839670 [Byte1]: 33
1648 11:47:56.840082
1649 11:47:56.843136 Set Vref, RX VrefLevel [Byte0]: 34
1650 11:47:56.846547 [Byte1]: 34
1651 11:47:56.850808
1652 11:47:56.851216 Set Vref, RX VrefLevel [Byte0]: 35
1653 11:47:56.853996 [Byte1]: 35
1654 11:47:56.858080
1655 11:47:56.858489 Set Vref, RX VrefLevel [Byte0]: 36
1656 11:47:56.861736 [Byte1]: 36
1657 11:47:56.865909
1658 11:47:56.866462 Set Vref, RX VrefLevel [Byte0]: 37
1659 11:47:56.869070 [Byte1]: 37
1660 11:47:56.873871
1661 11:47:56.874280 Set Vref, RX VrefLevel [Byte0]: 38
1662 11:47:56.876873 [Byte1]: 38
1663 11:47:56.881251
1664 11:47:56.881660 Set Vref, RX VrefLevel [Byte0]: 39
1665 11:47:56.884768 [Byte1]: 39
1666 11:47:56.889029
1667 11:47:56.889441 Set Vref, RX VrefLevel [Byte0]: 40
1668 11:47:56.892535 [Byte1]: 40
1669 11:47:56.896600
1670 11:47:56.897010 Set Vref, RX VrefLevel [Byte0]: 41
1671 11:47:56.900095 [Byte1]: 41
1672 11:47:56.904099
1673 11:47:56.904617 Set Vref, RX VrefLevel [Byte0]: 42
1674 11:47:56.907367 [Byte1]: 42
1675 11:47:56.911559
1676 11:47:56.911969 Set Vref, RX VrefLevel [Byte0]: 43
1677 11:47:56.915222 [Byte1]: 43
1678 11:47:56.919673
1679 11:47:56.920086 Set Vref, RX VrefLevel [Byte0]: 44
1680 11:47:56.923044 [Byte1]: 44
1681 11:47:56.927270
1682 11:47:56.927680 Set Vref, RX VrefLevel [Byte0]: 45
1683 11:47:56.930617 [Byte1]: 45
1684 11:47:56.934591
1685 11:47:56.935003 Set Vref, RX VrefLevel [Byte0]: 46
1686 11:47:56.937905 [Byte1]: 46
1687 11:47:56.942541
1688 11:47:56.942950 Set Vref, RX VrefLevel [Byte0]: 47
1689 11:47:56.945483 [Byte1]: 47
1690 11:47:56.950499
1691 11:47:56.950909 Set Vref, RX VrefLevel [Byte0]: 48
1692 11:47:56.953120 [Byte1]: 48
1693 11:47:56.957780
1694 11:47:56.958188 Set Vref, RX VrefLevel [Byte0]: 49
1695 11:47:56.960929 [Byte1]: 49
1696 11:47:56.965383
1697 11:47:56.965905 Set Vref, RX VrefLevel [Byte0]: 50
1698 11:47:56.968795 [Byte1]: 50
1699 11:47:56.973243
1700 11:47:56.973650 Set Vref, RX VrefLevel [Byte0]: 51
1701 11:47:56.976179 [Byte1]: 51
1702 11:47:56.980872
1703 11:47:56.981292 Set Vref, RX VrefLevel [Byte0]: 52
1704 11:47:56.983820 [Byte1]: 52
1705 11:47:56.988163
1706 11:47:56.988610 Set Vref, RX VrefLevel [Byte0]: 53
1707 11:47:56.991712 [Byte1]: 53
1708 11:47:56.995812
1709 11:47:56.996261 Set Vref, RX VrefLevel [Byte0]: 54
1710 11:47:56.999471 [Byte1]: 54
1711 11:47:57.003398
1712 11:47:57.003822 Set Vref, RX VrefLevel [Byte0]: 55
1713 11:47:57.006927 [Byte1]: 55
1714 11:47:57.011442
1715 11:47:57.011860 Set Vref, RX VrefLevel [Byte0]: 56
1716 11:47:57.014236 [Byte1]: 56
1717 11:47:57.018849
1718 11:47:57.019277 Set Vref, RX VrefLevel [Byte0]: 57
1719 11:47:57.022090 [Byte1]: 57
1720 11:47:57.026787
1721 11:47:57.027269 Set Vref, RX VrefLevel [Byte0]: 58
1722 11:47:57.030451 [Byte1]: 58
1723 11:47:57.034451
1724 11:47:57.035030 Set Vref, RX VrefLevel [Byte0]: 59
1725 11:47:57.037565 [Byte1]: 59
1726 11:47:57.041805
1727 11:47:57.042215 Set Vref, RX VrefLevel [Byte0]: 60
1728 11:47:57.045056 [Byte1]: 60
1729 11:47:57.049565
1730 11:47:57.050043 Set Vref, RX VrefLevel [Byte0]: 61
1731 11:47:57.052679 [Byte1]: 61
1732 11:47:57.057184
1733 11:47:57.057600 Set Vref, RX VrefLevel [Byte0]: 62
1734 11:47:57.060466 [Byte1]: 62
1735 11:47:57.064452
1736 11:47:57.064861 Set Vref, RX VrefLevel [Byte0]: 63
1737 11:47:57.068523 [Byte1]: 63
1738 11:47:57.072630
1739 11:47:57.073069 Set Vref, RX VrefLevel [Byte0]: 64
1740 11:47:57.075612 [Byte1]: 64
1741 11:47:57.079918
1742 11:47:57.080505 Set Vref, RX VrefLevel [Byte0]: 65
1743 11:47:57.083437 [Byte1]: 65
1744 11:47:57.087746
1745 11:47:57.088159 Set Vref, RX VrefLevel [Byte0]: 66
1746 11:47:57.090895 [Byte1]: 66
1747 11:47:57.095309
1748 11:47:57.095815 Set Vref, RX VrefLevel [Byte0]: 67
1749 11:47:57.098990 [Byte1]: 67
1750 11:47:57.103088
1751 11:47:57.103742 Set Vref, RX VrefLevel [Byte0]: 68
1752 11:47:57.106706 [Byte1]: 68
1753 11:47:57.110635
1754 11:47:57.111179 Set Vref, RX VrefLevel [Byte0]: 69
1755 11:47:57.114341 [Byte1]: 69
1756 11:47:57.118367
1757 11:47:57.118779 Set Vref, RX VrefLevel [Byte0]: 70
1758 11:47:57.121764 [Byte1]: 70
1759 11:47:57.125842
1760 11:47:57.126462 Set Vref, RX VrefLevel [Byte0]: 71
1761 11:47:57.129366 [Byte1]: 71
1762 11:47:57.133622
1763 11:47:57.134168 Set Vref, RX VrefLevel [Byte0]: 72
1764 11:47:57.136912 [Byte1]: 72
1765 11:47:57.141323
1766 11:47:57.141754 Set Vref, RX VrefLevel [Byte0]: 73
1767 11:47:57.144687 [Byte1]: 73
1768 11:47:57.149134
1769 11:47:57.149544 Set Vref, RX VrefLevel [Byte0]: 74
1770 11:47:57.152509 [Byte1]: 74
1771 11:47:57.156503
1772 11:47:57.156913 Final RX Vref Byte 0 = 58 to rank0
1773 11:47:57.159722 Final RX Vref Byte 1 = 53 to rank0
1774 11:47:57.163256 Final RX Vref Byte 0 = 58 to rank1
1775 11:47:57.166389 Final RX Vref Byte 1 = 53 to rank1==
1776 11:47:57.169834 Dram Type= 6, Freq= 0, CH_1, rank 0
1777 11:47:57.176815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1778 11:47:57.177231 ==
1779 11:47:57.177557 DQS Delay:
1780 11:47:57.177861 DQS0 = 0, DQS1 = 0
1781 11:47:57.180101 DQM Delay:
1782 11:47:57.180686 DQM0 = 81, DQM1 = 72
1783 11:47:57.183101 DQ Delay:
1784 11:47:57.186564 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1785 11:47:57.186980 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1786 11:47:57.189567 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1787 11:47:57.193267 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
1788 11:47:57.196734
1789 11:47:57.197144
1790 11:47:57.203424 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1791 11:47:57.206857 CH1 RK0: MR19=606, MR18=E18
1792 11:47:57.213211 CH1_RK0: MR19=0x606, MR18=0xE18, DQSOSC=403, MR23=63, INC=90, DEC=60
1793 11:47:57.213630
1794 11:47:57.216761 ----->DramcWriteLeveling(PI) begin...
1795 11:47:57.217179 ==
1796 11:47:57.220151 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 11:47:57.223073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 11:47:57.223485 ==
1799 11:47:57.226597 Write leveling (Byte 0): 26 => 26
1800 11:47:57.230117 Write leveling (Byte 1): 28 => 28
1801 11:47:57.233527 DramcWriteLeveling(PI) end<-----
1802 11:47:57.234116
1803 11:47:57.234587 ==
1804 11:47:57.236447 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 11:47:57.239787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 11:47:57.240383 ==
1807 11:47:57.243406 [Gating] SW mode calibration
1808 11:47:57.249787 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1809 11:47:57.256403 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1810 11:47:57.260143 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1811 11:47:57.263332 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1812 11:47:57.269717 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:47:57.273345 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:47:57.276425 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:47:57.283346 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:47:57.286224 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:47:57.289670 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:47:57.293451 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:47:57.299932 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:47:57.302963 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:47:57.306354 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:47:57.313207 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:47:57.316806 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:47:57.319722 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:47:57.326691 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:47:57.329671 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1827 11:47:57.333167 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1828 11:47:57.340256 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1829 11:47:57.343103 0 8 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1830 11:47:57.346528 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:47:57.353009 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:47:57.356457 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:47:57.359559 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:47:57.366641 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:47:57.370178 0 9 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1836 11:47:57.372995 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1837 11:47:57.379797 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 11:47:57.382877 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 11:47:57.386323 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 11:47:57.392801 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 11:47:57.396031 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 11:47:57.399524 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1843 11:47:57.402995 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (1 0) (1 1)
1844 11:47:57.409586 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1845 11:47:57.412869 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:47:57.416324 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:47:57.423346 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:47:57.426209 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:47:57.429632 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:47:57.435967 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1851 11:47:57.439567 0 11 4 | B1->B0 | 2525 3939 | 0 0 | (0 0) (0 0)
1852 11:47:57.442507 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1853 11:47:57.449581 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 11:47:57.452544 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 11:47:57.456101 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 11:47:57.462633 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 11:47:57.466114 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 11:47:57.469206 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 11:47:57.476401 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1860 11:47:57.479356 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1861 11:47:57.482842 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:47:57.486263 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:47:57.492884 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:47:57.495892 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:47:57.499340 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:47:57.506188 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:47:57.509244 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:47:57.512749 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:47:57.519367 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:47:57.522383 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:47:57.525841 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:47:57.532499 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:47:57.535873 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:47:57.539430 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:47:57.545872 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1876 11:47:57.549481 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1877 11:47:57.552488 Total UI for P1: 0, mck2ui 16
1878 11:47:57.555976 best dqsien dly found for B0: ( 0, 14, 4)
1879 11:47:57.559512 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 11:47:57.562937 Total UI for P1: 0, mck2ui 16
1881 11:47:57.565978 best dqsien dly found for B1: ( 0, 14, 8)
1882 11:47:57.569294 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1883 11:47:57.572796 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1884 11:47:57.572870
1885 11:47:57.576390 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1886 11:47:57.582835 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1887 11:47:57.582937 [Gating] SW calibration Done
1888 11:47:57.583027 ==
1889 11:47:57.585772 Dram Type= 6, Freq= 0, CH_1, rank 1
1890 11:47:57.592829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1891 11:47:57.592906 ==
1892 11:47:57.592969 RX Vref Scan: 0
1893 11:47:57.593028
1894 11:47:57.596184 RX Vref 0 -> 0, step: 1
1895 11:47:57.596297
1896 11:47:57.599103 RX Delay -130 -> 252, step: 16
1897 11:47:57.602565 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1898 11:47:57.606252 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1899 11:47:57.609240 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1900 11:47:57.615799 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1901 11:47:57.619270 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1902 11:47:57.622553 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1903 11:47:57.626058 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1904 11:47:57.629054 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1905 11:47:57.632554 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1906 11:47:57.639203 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1907 11:47:57.642399 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1908 11:47:57.646130 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1909 11:47:57.649106 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1910 11:47:57.656100 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1911 11:47:57.659065 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1912 11:47:57.662725 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1913 11:47:57.662807 ==
1914 11:47:57.665871 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 11:47:57.668983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 11:47:57.669072 ==
1917 11:47:57.672395 DQS Delay:
1918 11:47:57.672502 DQS0 = 0, DQS1 = 0
1919 11:47:57.675891 DQM Delay:
1920 11:47:57.676000 DQM0 = 78, DQM1 = 73
1921 11:47:57.676093 DQ Delay:
1922 11:47:57.679490 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1923 11:47:57.682516 DQ4 =77, DQ5 =85, DQ6 =93, DQ7 =77
1924 11:47:57.685997 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1925 11:47:57.689061 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1926 11:47:57.689142
1927 11:47:57.689205
1928 11:47:57.689265 ==
1929 11:47:57.692617 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 11:47:57.699277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 11:47:57.699407 ==
1932 11:47:57.699518
1933 11:47:57.699632
1934 11:47:57.699739 TX Vref Scan disable
1935 11:47:57.702770 == TX Byte 0 ==
1936 11:47:57.706306 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1937 11:47:57.709866 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1938 11:47:57.712764 == TX Byte 1 ==
1939 11:47:57.716172 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1940 11:47:57.719575 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1941 11:47:57.723232 ==
1942 11:47:57.726645 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 11:47:57.729500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 11:47:57.729600 ==
1945 11:47:57.742085 TX Vref=22, minBit 6, minWin=27, winSum=451
1946 11:47:57.745400 TX Vref=24, minBit 3, minWin=28, winSum=455
1947 11:47:57.748996 TX Vref=26, minBit 3, minWin=28, winSum=459
1948 11:47:57.752636 TX Vref=28, minBit 1, minWin=28, winSum=458
1949 11:47:57.755620 TX Vref=30, minBit 1, minWin=28, winSum=465
1950 11:47:57.759194 TX Vref=32, minBit 1, minWin=28, winSum=466
1951 11:47:57.765619 [TxChooseVref] Worse bit 1, Min win 28, Win sum 466, Final Vref 32
1952 11:47:57.765705
1953 11:47:57.769355 Final TX Range 1 Vref 32
1954 11:47:57.769466
1955 11:47:57.769567 ==
1956 11:47:57.772392 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 11:47:57.775975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 11:47:57.776061 ==
1959 11:47:57.776162
1960 11:47:57.776285
1961 11:47:57.778981 TX Vref Scan disable
1962 11:47:57.782412 == TX Byte 0 ==
1963 11:47:57.785416 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1964 11:47:57.789185 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1965 11:47:57.792147 == TX Byte 1 ==
1966 11:47:57.795736 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1967 11:47:57.798890 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1968 11:47:57.799001
1969 11:47:57.802326 [DATLAT]
1970 11:47:57.802435 Freq=800, CH1 RK1
1971 11:47:57.802530
1972 11:47:57.806001 DATLAT Default: 0xa
1973 11:47:57.806082 0, 0xFFFF, sum = 0
1974 11:47:57.809084 1, 0xFFFF, sum = 0
1975 11:47:57.809166 2, 0xFFFF, sum = 0
1976 11:47:57.812499 3, 0xFFFF, sum = 0
1977 11:47:57.812581 4, 0xFFFF, sum = 0
1978 11:47:57.815375 5, 0xFFFF, sum = 0
1979 11:47:57.815457 6, 0xFFFF, sum = 0
1980 11:47:57.818838 7, 0xFFFF, sum = 0
1981 11:47:57.818921 8, 0xFFFF, sum = 0
1982 11:47:57.822223 9, 0x0, sum = 1
1983 11:47:57.822307 10, 0x0, sum = 2
1984 11:47:57.825826 11, 0x0, sum = 3
1985 11:47:57.825909 12, 0x0, sum = 4
1986 11:47:57.829382 best_step = 10
1987 11:47:57.829464
1988 11:47:57.829527 ==
1989 11:47:57.832301 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 11:47:57.835631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 11:47:57.835712 ==
1992 11:47:57.838938 RX Vref Scan: 0
1993 11:47:57.839033
1994 11:47:57.839096 RX Vref 0 -> 0, step: 1
1995 11:47:57.839155
1996 11:47:57.842453 RX Delay -111 -> 252, step: 8
1997 11:47:57.848818 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1998 11:47:57.852293 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1999 11:47:57.855887 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2000 11:47:57.858736 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2001 11:47:57.862152 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2002 11:47:57.869072 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2003 11:47:57.872012 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2004 11:47:57.875625 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2005 11:47:57.879035 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2006 11:47:57.882575 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2007 11:47:57.889306 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2008 11:47:57.892406 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2009 11:47:57.895416 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2010 11:47:57.898986 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2011 11:47:57.902201 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2012 11:47:57.909225 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2013 11:47:57.909398 ==
2014 11:47:57.912467 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 11:47:57.915618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 11:47:57.915859 ==
2017 11:47:57.916046 DQS Delay:
2018 11:47:57.919115 DQS0 = 0, DQS1 = 0
2019 11:47:57.919354 DQM Delay:
2020 11:47:57.922647 DQM0 = 77, DQM1 = 75
2021 11:47:57.922944 DQ Delay:
2022 11:47:57.925964 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2023 11:47:57.929452 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2024 11:47:57.932319 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
2025 11:47:57.935907 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2026 11:47:57.936219
2027 11:47:57.936526
2028 11:47:57.942476 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2029 11:47:57.945978 CH1 RK1: MR19=606, MR18=1E36
2030 11:47:57.952238 CH1_RK1: MR19=0x606, MR18=0x1E36, DQSOSC=396, MR23=63, INC=94, DEC=62
2031 11:47:57.955855 [RxdqsGatingPostProcess] freq 800
2032 11:47:57.961947 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2033 11:47:57.965418 Pre-setting of DQS Precalculation
2034 11:47:57.968916 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2035 11:47:57.975839 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2036 11:47:57.982345 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2037 11:47:57.982464
2038 11:47:57.982560
2039 11:47:57.985676 [Calibration Summary] 1600 Mbps
2040 11:47:57.988672 CH 0, Rank 0
2041 11:47:57.988767 SW Impedance : PASS
2042 11:47:57.992041 DUTY Scan : NO K
2043 11:47:57.995560 ZQ Calibration : PASS
2044 11:47:57.995647 Jitter Meter : NO K
2045 11:47:57.998905 CBT Training : PASS
2046 11:47:58.002252 Write leveling : PASS
2047 11:47:58.002337 RX DQS gating : PASS
2048 11:47:58.005547 RX DQ/DQS(RDDQC) : PASS
2049 11:47:58.008907 TX DQ/DQS : PASS
2050 11:47:58.008992 RX DATLAT : PASS
2051 11:47:58.012256 RX DQ/DQS(Engine): PASS
2052 11:47:58.012341 TX OE : NO K
2053 11:47:58.015438 All Pass.
2054 11:47:58.015523
2055 11:47:58.015608 CH 0, Rank 1
2056 11:47:58.019002 SW Impedance : PASS
2057 11:47:58.019086 DUTY Scan : NO K
2058 11:47:58.022274 ZQ Calibration : PASS
2059 11:47:58.025635 Jitter Meter : NO K
2060 11:47:58.025719 CBT Training : PASS
2061 11:47:58.028875 Write leveling : PASS
2062 11:47:58.032171 RX DQS gating : PASS
2063 11:47:58.032292 RX DQ/DQS(RDDQC) : PASS
2064 11:47:58.035263 TX DQ/DQS : PASS
2065 11:47:58.038788 RX DATLAT : PASS
2066 11:47:58.038878 RX DQ/DQS(Engine): PASS
2067 11:47:58.042305 TX OE : NO K
2068 11:47:58.042402 All Pass.
2069 11:47:58.042500
2070 11:47:58.045236 CH 1, Rank 0
2071 11:47:58.045340 SW Impedance : PASS
2072 11:47:58.049061 DUTY Scan : NO K
2073 11:47:58.051909 ZQ Calibration : PASS
2074 11:47:58.052022 Jitter Meter : NO K
2075 11:47:58.055229 CBT Training : PASS
2076 11:47:58.055353 Write leveling : PASS
2077 11:47:58.058635 RX DQS gating : PASS
2078 11:47:58.061841 RX DQ/DQS(RDDQC) : PASS
2079 11:47:58.061980 TX DQ/DQS : PASS
2080 11:47:58.065503 RX DATLAT : PASS
2081 11:47:58.068615 RX DQ/DQS(Engine): PASS
2082 11:47:58.068779 TX OE : NO K
2083 11:47:58.072071 All Pass.
2084 11:47:58.072247
2085 11:47:58.072411 CH 1, Rank 1
2086 11:47:58.075528 SW Impedance : PASS
2087 11:47:58.075707 DUTY Scan : NO K
2088 11:47:58.079182 ZQ Calibration : PASS
2089 11:47:58.082096 Jitter Meter : NO K
2090 11:47:58.082383 CBT Training : PASS
2091 11:47:58.085550 Write leveling : PASS
2092 11:47:58.088891 RX DQS gating : PASS
2093 11:47:58.088976 RX DQ/DQS(RDDQC) : PASS
2094 11:47:58.092152 TX DQ/DQS : PASS
2095 11:47:58.092290 RX DATLAT : PASS
2096 11:47:58.095730 RX DQ/DQS(Engine): PASS
2097 11:47:58.098579 TX OE : NO K
2098 11:47:58.098667 All Pass.
2099 11:47:58.098752
2100 11:47:58.102149 DramC Write-DBI off
2101 11:47:58.102235 PER_BANK_REFRESH: Hybrid Mode
2102 11:47:58.105618 TX_TRACKING: ON
2103 11:47:58.108977 [GetDramInforAfterCalByMRR] Vendor 6.
2104 11:47:58.111881 [GetDramInforAfterCalByMRR] Revision 606.
2105 11:47:58.115480 [GetDramInforAfterCalByMRR] Revision 2 0.
2106 11:47:58.118830 MR0 0x3b3b
2107 11:47:58.118917 MR8 0x5151
2108 11:47:58.122174 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 11:47:58.122262
2110 11:47:58.122388 MR0 0x3b3b
2111 11:47:58.125188 MR8 0x5151
2112 11:47:58.128646 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 11:47:58.128756
2114 11:47:58.135368 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2115 11:47:58.138460 [FAST_K] Save calibration result to emmc
2116 11:47:58.145408 [FAST_K] Save calibration result to emmc
2117 11:47:58.145520 dram_init: config_dvfs: 1
2118 11:47:58.148441 dramc_set_vcore_voltage set vcore to 662500
2119 11:47:58.151844 Read voltage for 1200, 2
2120 11:47:58.151980 Vio18 = 0
2121 11:47:58.155114 Vcore = 662500
2122 11:47:58.155236 Vdram = 0
2123 11:47:58.155343 Vddq = 0
2124 11:47:58.158743 Vmddr = 0
2125 11:47:58.162237 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2126 11:47:58.168723 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2127 11:47:58.168805 MEM_TYPE=3, freq_sel=15
2128 11:47:58.172020 sv_algorithm_assistance_LP4_1600
2129 11:47:58.178946 ============ PULL DRAM RESETB DOWN ============
2130 11:47:58.181925 ========== PULL DRAM RESETB DOWN end =========
2131 11:47:58.185443 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 11:47:58.188984 ===================================
2133 11:47:58.191966 LPDDR4 DRAM CONFIGURATION
2134 11:47:58.195288 ===================================
2135 11:47:58.195386 EX_ROW_EN[0] = 0x0
2136 11:47:58.198738 EX_ROW_EN[1] = 0x0
2137 11:47:58.202309 LP4Y_EN = 0x0
2138 11:47:58.202390 WORK_FSP = 0x0
2139 11:47:58.205324 WL = 0x4
2140 11:47:58.205405 RL = 0x4
2141 11:47:58.208662 BL = 0x2
2142 11:47:58.208746 RPST = 0x0
2143 11:47:58.212009 RD_PRE = 0x0
2144 11:47:58.212104 WR_PRE = 0x1
2145 11:47:58.215201 WR_PST = 0x0
2146 11:47:58.215282 DBI_WR = 0x0
2147 11:47:58.218714 DBI_RD = 0x0
2148 11:47:58.218794 OTF = 0x1
2149 11:47:58.222080 ===================================
2150 11:47:58.225028 ===================================
2151 11:47:58.228492 ANA top config
2152 11:47:58.232075 ===================================
2153 11:47:58.232206 DLL_ASYNC_EN = 0
2154 11:47:58.235058 ALL_SLAVE_EN = 0
2155 11:47:58.238514 NEW_RANK_MODE = 1
2156 11:47:58.242181 DLL_IDLE_MODE = 1
2157 11:47:58.245103 LP45_APHY_COMB_EN = 1
2158 11:47:58.245185 TX_ODT_DIS = 1
2159 11:47:58.248891 NEW_8X_MODE = 1
2160 11:47:58.252144 ===================================
2161 11:47:58.255215 ===================================
2162 11:47:58.258427 data_rate = 2400
2163 11:47:58.262063 CKR = 1
2164 11:47:58.265212 DQ_P2S_RATIO = 8
2165 11:47:58.268799 ===================================
2166 11:47:58.268881 CA_P2S_RATIO = 8
2167 11:47:58.271770 DQ_CA_OPEN = 0
2168 11:47:58.275414 DQ_SEMI_OPEN = 0
2169 11:47:58.278394 CA_SEMI_OPEN = 0
2170 11:47:58.282165 CA_FULL_RATE = 0
2171 11:47:58.285268 DQ_CKDIV4_EN = 0
2172 11:47:58.285355 CA_CKDIV4_EN = 0
2173 11:47:58.288831 CA_PREDIV_EN = 0
2174 11:47:58.291709 PH8_DLY = 17
2175 11:47:58.295406 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2176 11:47:58.298840 DQ_AAMCK_DIV = 4
2177 11:47:58.301969 CA_AAMCK_DIV = 4
2178 11:47:58.302107 CA_ADMCK_DIV = 4
2179 11:47:58.305404 DQ_TRACK_CA_EN = 0
2180 11:47:58.308865 CA_PICK = 1200
2181 11:47:58.312156 CA_MCKIO = 1200
2182 11:47:58.315237 MCKIO_SEMI = 0
2183 11:47:58.318678 PLL_FREQ = 2366
2184 11:47:58.322025 DQ_UI_PI_RATIO = 32
2185 11:47:58.322146 CA_UI_PI_RATIO = 0
2186 11:47:58.325458 ===================================
2187 11:47:58.328852 ===================================
2188 11:47:58.332246 memory_type:LPDDR4
2189 11:47:58.335243 GP_NUM : 10
2190 11:47:58.335331 SRAM_EN : 1
2191 11:47:58.338834 MD32_EN : 0
2192 11:47:58.341792 ===================================
2193 11:47:58.345343 [ANA_INIT] >>>>>>>>>>>>>>
2194 11:47:58.348282 <<<<<< [CONFIGURE PHASE]: ANA_TX
2195 11:47:58.351850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2196 11:47:58.355459 ===================================
2197 11:47:58.355541 data_rate = 2400,PCW = 0X5b00
2198 11:47:58.358286 ===================================
2199 11:47:58.361598 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2200 11:47:58.368467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 11:47:58.375212 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 11:47:58.378357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2203 11:47:58.381704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2204 11:47:58.385253 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2205 11:47:58.388788 [ANA_INIT] flow start
2206 11:47:58.388875 [ANA_INIT] PLL >>>>>>>>
2207 11:47:58.391666 [ANA_INIT] PLL <<<<<<<<
2208 11:47:58.395005 [ANA_INIT] MIDPI >>>>>>>>
2209 11:47:58.398507 [ANA_INIT] MIDPI <<<<<<<<
2210 11:47:58.398590 [ANA_INIT] DLL >>>>>>>>
2211 11:47:58.401922 [ANA_INIT] DLL <<<<<<<<
2212 11:47:58.402012 [ANA_INIT] flow end
2213 11:47:58.408350 ============ LP4 DIFF to SE enter ============
2214 11:47:58.411779 ============ LP4 DIFF to SE exit ============
2215 11:47:58.415251 [ANA_INIT] <<<<<<<<<<<<<
2216 11:47:58.418712 [Flow] Enable top DCM control >>>>>
2217 11:47:58.422183 [Flow] Enable top DCM control <<<<<
2218 11:47:58.422267 Enable DLL master slave shuffle
2219 11:47:58.428875 ==============================================================
2220 11:47:58.431726 Gating Mode config
2221 11:47:58.435153 ==============================================================
2222 11:47:58.438663 Config description:
2223 11:47:58.448915 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2224 11:47:58.455529 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2225 11:47:58.458871 SELPH_MODE 0: By rank 1: By Phase
2226 11:47:58.465233 ==============================================================
2227 11:47:58.468753 GAT_TRACK_EN = 1
2228 11:47:58.472538 RX_GATING_MODE = 2
2229 11:47:58.475521 RX_GATING_TRACK_MODE = 2
2230 11:47:58.475607 SELPH_MODE = 1
2231 11:47:58.478455 PICG_EARLY_EN = 1
2232 11:47:58.482337 VALID_LAT_VALUE = 1
2233 11:47:58.488754 ==============================================================
2234 11:47:58.491773 Enter into Gating configuration >>>>
2235 11:47:58.495414 Exit from Gating configuration <<<<
2236 11:47:58.498397 Enter into DVFS_PRE_config >>>>>
2237 11:47:58.508839 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2238 11:47:58.512064 Exit from DVFS_PRE_config <<<<<
2239 11:47:58.515674 Enter into PICG configuration >>>>
2240 11:47:58.518499 Exit from PICG configuration <<<<
2241 11:47:58.521932 [RX_INPUT] configuration >>>>>
2242 11:47:58.525511 [RX_INPUT] configuration <<<<<
2243 11:47:58.528445 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2244 11:47:58.535559 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2245 11:47:58.541916 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 11:47:58.549032 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 11:47:58.551933 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 11:47:58.558947 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 11:47:58.561819 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2250 11:47:58.568716 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2251 11:47:58.572350 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2252 11:47:58.575419 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2253 11:47:58.578454 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2254 11:47:58.585360 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2255 11:47:58.588364 ===================================
2256 11:47:58.588449 LPDDR4 DRAM CONFIGURATION
2257 11:47:58.591994 ===================================
2258 11:47:58.595506 EX_ROW_EN[0] = 0x0
2259 11:47:58.598330 EX_ROW_EN[1] = 0x0
2260 11:47:58.598414 LP4Y_EN = 0x0
2261 11:47:58.602180 WORK_FSP = 0x0
2262 11:47:58.602261 WL = 0x4
2263 11:47:58.605271 RL = 0x4
2264 11:47:58.605351 BL = 0x2
2265 11:47:58.608429 RPST = 0x0
2266 11:47:58.608509 RD_PRE = 0x0
2267 11:47:58.611980 WR_PRE = 0x1
2268 11:47:58.612060 WR_PST = 0x0
2269 11:47:58.615141 DBI_WR = 0x0
2270 11:47:58.615221 DBI_RD = 0x0
2271 11:47:58.618638 OTF = 0x1
2272 11:47:58.621902 ===================================
2273 11:47:58.625157 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2274 11:47:58.628195 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2275 11:47:58.635016 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2276 11:47:58.638146 ===================================
2277 11:47:58.638256 LPDDR4 DRAM CONFIGURATION
2278 11:47:58.641974 ===================================
2279 11:47:58.644804 EX_ROW_EN[0] = 0x10
2280 11:47:58.648218 EX_ROW_EN[1] = 0x0
2281 11:47:58.648314 LP4Y_EN = 0x0
2282 11:47:58.651769 WORK_FSP = 0x0
2283 11:47:58.651879 WL = 0x4
2284 11:47:58.654763 RL = 0x4
2285 11:47:58.654841 BL = 0x2
2286 11:47:58.658242 RPST = 0x0
2287 11:47:58.658326 RD_PRE = 0x0
2288 11:47:58.661665 WR_PRE = 0x1
2289 11:47:58.661749 WR_PST = 0x0
2290 11:47:58.665214 DBI_WR = 0x0
2291 11:47:58.665298 DBI_RD = 0x0
2292 11:47:58.668644 OTF = 0x1
2293 11:47:58.671516 ===================================
2294 11:47:58.678445 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2295 11:47:58.678528 ==
2296 11:47:58.682035 Dram Type= 6, Freq= 0, CH_0, rank 0
2297 11:47:58.685460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2298 11:47:58.685548 ==
2299 11:47:58.688589 [Duty_Offset_Calibration]
2300 11:47:58.688697 B0:2 B1:0 CA:3
2301 11:47:58.688788
2302 11:47:58.692094 [DutyScan_Calibration_Flow] k_type=0
2303 11:47:58.701302
2304 11:47:58.701383 ==CLK 0==
2305 11:47:58.704828 Final CLK duty delay cell = 0
2306 11:47:58.708295 [0] MAX Duty = 5031%(X100), DQS PI = 12
2307 11:47:58.711184 [0] MIN Duty = 4906%(X100), DQS PI = 54
2308 11:47:58.711290 [0] AVG Duty = 4968%(X100)
2309 11:47:58.714762
2310 11:47:58.718290 CH0 CLK Duty spec in!! Max-Min= 125%
2311 11:47:58.721602 [DutyScan_Calibration_Flow] ====Done====
2312 11:47:58.721683
2313 11:47:58.724699 [DutyScan_Calibration_Flow] k_type=1
2314 11:47:58.740155
2315 11:47:58.740306 ==DQS 0 ==
2316 11:47:58.743158 Final DQS duty delay cell = 0
2317 11:47:58.746471 [0] MAX Duty = 5062%(X100), DQS PI = 12
2318 11:47:58.749873 [0] MIN Duty = 4907%(X100), DQS PI = 44
2319 11:47:58.753438 [0] AVG Duty = 4984%(X100)
2320 11:47:58.753519
2321 11:47:58.753582 ==DQS 1 ==
2322 11:47:58.756770 Final DQS duty delay cell = -4
2323 11:47:58.760064 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2324 11:47:58.763402 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2325 11:47:58.766403 [-4] AVG Duty = 4938%(X100)
2326 11:47:58.766484
2327 11:47:58.769822 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2328 11:47:58.769904
2329 11:47:58.773454 CH0 DQS 1 Duty spec in!! Max-Min= 62%
2330 11:47:58.776707 [DutyScan_Calibration_Flow] ====Done====
2331 11:47:58.776787
2332 11:47:58.779989 [DutyScan_Calibration_Flow] k_type=3
2333 11:47:58.837864
2334 11:47:58.838534 ==DQM 0 ==
2335 11:47:58.839110 Final DQM duty delay cell = 0
2336 11:47:58.839676 [0] MAX Duty = 5124%(X100), DQS PI = 28
2337 11:47:58.840249 [0] MIN Duty = 4907%(X100), DQS PI = 0
2338 11:47:58.840783 [0] AVG Duty = 5015%(X100)
2339 11:47:58.841320
2340 11:47:58.841627 ==DQM 1 ==
2341 11:47:58.841731 Final DQM duty delay cell = 4
2342 11:47:58.841835 [4] MAX Duty = 5124%(X100), DQS PI = 50
2343 11:47:58.841938 [4] MIN Duty = 5000%(X100), DQS PI = 14
2344 11:47:58.842038 [4] AVG Duty = 5062%(X100)
2345 11:47:58.842142
2346 11:47:58.842242 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2347 11:47:58.842330
2348 11:47:58.842415 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2349 11:47:58.842499 [DutyScan_Calibration_Flow] ====Done====
2350 11:47:58.842581
2351 11:47:58.842676 [DutyScan_Calibration_Flow] k_type=2
2352 11:47:58.852123
2353 11:47:58.852259 ==DQ 0 ==
2354 11:47:58.855787 Final DQ duty delay cell = -4
2355 11:47:58.859056 [-4] MAX Duty = 5000%(X100), DQS PI = 10
2356 11:47:58.862241 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2357 11:47:58.862325 [-4] AVG Duty = 4953%(X100)
2358 11:47:58.866017
2359 11:47:58.866175 ==DQ 1 ==
2360 11:47:58.869556 Final DQ duty delay cell = -4
2361 11:47:58.872560 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2362 11:47:58.875626 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2363 11:47:58.879096 [-4] AVG Duty = 4938%(X100)
2364 11:47:58.879178
2365 11:47:58.882456 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2366 11:47:58.882563
2367 11:47:58.885803 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2368 11:47:58.889249 [DutyScan_Calibration_Flow] ====Done====
2369 11:47:58.889330 ==
2370 11:47:58.892787 Dram Type= 6, Freq= 0, CH_1, rank 0
2371 11:47:58.895821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 11:47:58.895902 ==
2373 11:47:58.899337 [Duty_Offset_Calibration]
2374 11:47:58.899418 B0:1 B1:-2 CA:0
2375 11:47:58.899501
2376 11:47:58.902957 [DutyScan_Calibration_Flow] k_type=0
2377 11:47:58.912888
2378 11:47:58.912973 ==CLK 0==
2379 11:47:58.916402 Final CLK duty delay cell = 0
2380 11:47:58.920135 [0] MAX Duty = 5062%(X100), DQS PI = 30
2381 11:47:58.923606 [0] MIN Duty = 4876%(X100), DQS PI = 2
2382 11:47:58.924038 [0] AVG Duty = 4969%(X100)
2383 11:47:58.924562
2384 11:47:58.926680 CH1 CLK Duty spec in!! Max-Min= 186%
2385 11:47:58.933397 [DutyScan_Calibration_Flow] ====Done====
2386 11:47:58.933829
2387 11:47:58.936813 [DutyScan_Calibration_Flow] k_type=1
2388 11:47:58.951409
2389 11:47:58.951978 ==DQS 0 ==
2390 11:47:58.955058 Final DQS duty delay cell = -4
2391 11:47:58.958308 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2392 11:47:58.961783 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2393 11:47:58.964754 [-4] AVG Duty = 4938%(X100)
2394 11:47:58.965184
2395 11:47:58.965631 ==DQS 1 ==
2396 11:47:58.968054 Final DQS duty delay cell = 0
2397 11:47:58.971581 [0] MAX Duty = 5093%(X100), DQS PI = 0
2398 11:47:58.975049 [0] MIN Duty = 4844%(X100), DQS PI = 26
2399 11:47:58.977901 [0] AVG Duty = 4968%(X100)
2400 11:47:58.978331
2401 11:47:58.981434 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2402 11:47:58.981867
2403 11:47:58.984727 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2404 11:47:58.988005 [DutyScan_Calibration_Flow] ====Done====
2405 11:47:58.988482
2406 11:47:58.991437 [DutyScan_Calibration_Flow] k_type=3
2407 11:47:59.008021
2408 11:47:59.008539 ==DQM 0 ==
2409 11:47:59.011599 Final DQM duty delay cell = 0
2410 11:47:59.015000 [0] MAX Duty = 5000%(X100), DQS PI = 24
2411 11:47:59.018616 [0] MIN Duty = 4844%(X100), DQS PI = 52
2412 11:47:59.019052 [0] AVG Duty = 4922%(X100)
2413 11:47:59.021608
2414 11:47:59.022059 ==DQM 1 ==
2415 11:47:59.024855 Final DQM duty delay cell = 0
2416 11:47:59.028356 [0] MAX Duty = 5031%(X100), DQS PI = 36
2417 11:47:59.031354 [0] MIN Duty = 4907%(X100), DQS PI = 0
2418 11:47:59.031646 [0] AVG Duty = 4969%(X100)
2419 11:47:59.034757
2420 11:47:59.038188 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2421 11:47:59.038479
2422 11:47:59.041532 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2423 11:47:59.044990 [DutyScan_Calibration_Flow] ====Done====
2424 11:47:59.045399
2425 11:47:59.048582 [DutyScan_Calibration_Flow] k_type=2
2426 11:47:59.064721
2427 11:47:59.065142 ==DQ 0 ==
2428 11:47:59.068045 Final DQ duty delay cell = 0
2429 11:47:59.071674 [0] MAX Duty = 5093%(X100), DQS PI = 26
2430 11:47:59.074546 [0] MIN Duty = 4907%(X100), DQS PI = 56
2431 11:47:59.074959 [0] AVG Duty = 5000%(X100)
2432 11:47:59.077955
2433 11:47:59.078362 ==DQ 1 ==
2434 11:47:59.081446 Final DQ duty delay cell = 0
2435 11:47:59.084872 [0] MAX Duty = 5093%(X100), DQS PI = 18
2436 11:47:59.087804 [0] MIN Duty = 4969%(X100), DQS PI = 26
2437 11:47:59.088424 [0] AVG Duty = 5031%(X100)
2438 11:47:59.088856
2439 11:47:59.091369 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2440 11:47:59.094685
2441 11:47:59.098001 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2442 11:47:59.101657 [DutyScan_Calibration_Flow] ====Done====
2443 11:47:59.104669 nWR fixed to 30
2444 11:47:59.105105 [ModeRegInit_LP4] CH0 RK0
2445 11:47:59.108080 [ModeRegInit_LP4] CH0 RK1
2446 11:47:59.111535 [ModeRegInit_LP4] CH1 RK0
2447 11:47:59.111965 [ModeRegInit_LP4] CH1 RK1
2448 11:47:59.114963 match AC timing 7
2449 11:47:59.118320 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2450 11:47:59.121252 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2451 11:47:59.128000 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2452 11:47:59.131522 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2453 11:47:59.137939 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2454 11:47:59.138525 ==
2455 11:47:59.141259 Dram Type= 6, Freq= 0, CH_0, rank 0
2456 11:47:59.144421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2457 11:47:59.144899 ==
2458 11:47:59.151141 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2459 11:47:59.154473 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2460 11:47:59.164725 [CA 0] Center 40 (10~71) winsize 62
2461 11:47:59.168181 [CA 1] Center 39 (9~70) winsize 62
2462 11:47:59.171685 [CA 2] Center 36 (6~66) winsize 61
2463 11:47:59.174593 [CA 3] Center 35 (5~66) winsize 62
2464 11:47:59.178122 [CA 4] Center 34 (4~65) winsize 62
2465 11:47:59.181731 [CA 5] Center 33 (3~63) winsize 61
2466 11:47:59.182144
2467 11:47:59.184661 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2468 11:47:59.185117
2469 11:47:59.188051 [CATrainingPosCal] consider 1 rank data
2470 11:47:59.191629 u2DelayCellTimex100 = 270/100 ps
2471 11:47:59.194531 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2472 11:47:59.201134 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2473 11:47:59.204363 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2474 11:47:59.208134 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2475 11:47:59.210933 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2476 11:47:59.214432 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2477 11:47:59.214846
2478 11:47:59.217885 CA PerBit enable=1, Macro0, CA PI delay=33
2479 11:47:59.218480
2480 11:47:59.221363 [CBTSetCACLKResult] CA Dly = 33
2481 11:47:59.224616 CS Dly: 7 (0~38)
2482 11:47:59.225039 ==
2483 11:47:59.228077 Dram Type= 6, Freq= 0, CH_0, rank 1
2484 11:47:59.231545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 11:47:59.231965 ==
2486 11:47:59.234964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 11:47:59.241545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2488 11:47:59.250970 [CA 0] Center 40 (10~71) winsize 62
2489 11:47:59.253908 [CA 1] Center 39 (9~70) winsize 62
2490 11:47:59.257337 [CA 2] Center 35 (5~66) winsize 62
2491 11:47:59.260846 [CA 3] Center 35 (5~66) winsize 62
2492 11:47:59.264115 [CA 4] Center 34 (4~65) winsize 62
2493 11:47:59.267481 [CA 5] Center 33 (3~63) winsize 61
2494 11:47:59.267898
2495 11:47:59.271132 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2496 11:47:59.271584
2497 11:47:59.274607 [CATrainingPosCal] consider 2 rank data
2498 11:47:59.277482 u2DelayCellTimex100 = 270/100 ps
2499 11:47:59.280995 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2500 11:47:59.284453 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2501 11:47:59.291018 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2502 11:47:59.294473 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 11:47:59.297463 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2504 11:47:59.301046 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2505 11:47:59.301459
2506 11:47:59.304284 CA PerBit enable=1, Macro0, CA PI delay=33
2507 11:47:59.304697
2508 11:47:59.307759 [CBTSetCACLKResult] CA Dly = 33
2509 11:47:59.308257 CS Dly: 8 (0~40)
2510 11:47:59.308605
2511 11:47:59.310661 ----->DramcWriteLeveling(PI) begin...
2512 11:47:59.314199 ==
2513 11:47:59.317557 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 11:47:59.321134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 11:47:59.321551 ==
2516 11:47:59.324656 Write leveling (Byte 0): 33 => 33
2517 11:47:59.327423 Write leveling (Byte 1): 29 => 29
2518 11:47:59.330953 DramcWriteLeveling(PI) end<-----
2519 11:47:59.331369
2520 11:47:59.331698 ==
2521 11:47:59.334382 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 11:47:59.337906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 11:47:59.338323 ==
2524 11:47:59.340820 [Gating] SW mode calibration
2525 11:47:59.347942 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2526 11:47:59.350869 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2527 11:47:59.357897 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 11:47:59.361316 0 15 4 | B1->B0 | 2626 3232 | 1 1 | (0 0) (0 0)
2529 11:47:59.364151 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 11:47:59.370799 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 11:47:59.374479 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 11:47:59.377783 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 11:47:59.384436 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 11:47:59.387599 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2535 11:47:59.390988 1 0 0 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 1)
2536 11:47:59.397970 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 11:47:59.401296 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 11:47:59.404462 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 11:47:59.410968 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 11:47:59.414555 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 11:47:59.417538 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 11:47:59.424403 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 11:47:59.427160 1 1 0 | B1->B0 | 2c2c 3737 | 1 0 | (0 0) (0 0)
2544 11:47:59.430715 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 11:47:59.437542 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 11:47:59.440928 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 11:47:59.443984 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 11:47:59.451032 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 11:47:59.454104 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 11:47:59.457642 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2551 11:47:59.464100 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2552 11:47:59.467655 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2553 11:47:59.470708 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:47:59.474258 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:47:59.480913 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:47:59.484471 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:47:59.487336 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:47:59.494005 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:47:59.497377 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:47:59.500519 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:47:59.507312 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:47:59.510671 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:47:59.514404 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:47:59.520753 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:47:59.524306 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 11:47:59.527372 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 11:47:59.534190 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 11:47:59.537786 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2569 11:47:59.540666 Total UI for P1: 0, mck2ui 16
2570 11:47:59.543927 best dqsien dly found for B0: ( 1, 4, 0)
2571 11:47:59.547310 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 11:47:59.550897 Total UI for P1: 0, mck2ui 16
2573 11:47:59.554232 best dqsien dly found for B1: ( 1, 4, 4)
2574 11:47:59.557327 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2575 11:47:59.560774 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2576 11:47:59.561206
2577 11:47:59.564337 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2578 11:47:59.567182 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2579 11:47:59.570796 [Gating] SW calibration Done
2580 11:47:59.571208 ==
2581 11:47:59.574227 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 11:47:59.580722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 11:47:59.581135 ==
2584 11:47:59.581459 RX Vref Scan: 0
2585 11:47:59.581759
2586 11:47:59.584082 RX Vref 0 -> 0, step: 1
2587 11:47:59.584537
2588 11:47:59.587342 RX Delay -40 -> 252, step: 8
2589 11:47:59.590783 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2590 11:47:59.594152 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2591 11:47:59.597632 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2592 11:47:59.600906 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2593 11:47:59.607606 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2594 11:47:59.610679 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2595 11:47:59.613940 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2596 11:47:59.617459 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2597 11:47:59.620531 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2598 11:47:59.623904 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2599 11:47:59.630606 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2600 11:47:59.633963 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2601 11:47:59.637330 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2602 11:47:59.640853 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2603 11:47:59.647194 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2604 11:47:59.650600 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2605 11:47:59.651100 ==
2606 11:47:59.654614 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 11:47:59.657609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 11:47:59.658286 ==
2609 11:47:59.658877 DQS Delay:
2610 11:47:59.660804 DQS0 = 0, DQS1 = 0
2611 11:47:59.661278 DQM Delay:
2612 11:47:59.664309 DQM0 = 112, DQM1 = 102
2613 11:47:59.664745 DQ Delay:
2614 11:47:59.667657 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2615 11:47:59.670611 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2616 11:47:59.673990 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2617 11:47:59.677644 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2618 11:47:59.678140
2619 11:47:59.678582
2620 11:47:59.681112 ==
2621 11:47:59.681598 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 11:47:59.687428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 11:47:59.687959 ==
2624 11:47:59.688465
2625 11:47:59.688918
2626 11:47:59.690851 TX Vref Scan disable
2627 11:47:59.691313 == TX Byte 0 ==
2628 11:47:59.694427 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2629 11:47:59.700832 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2630 11:47:59.701357 == TX Byte 1 ==
2631 11:47:59.704094 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2632 11:47:59.710493 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2633 11:47:59.711082 ==
2634 11:47:59.713970 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 11:47:59.717240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 11:47:59.717751 ==
2637 11:47:59.729688 TX Vref=22, minBit 1, minWin=25, winSum=418
2638 11:47:59.733071 TX Vref=24, minBit 1, minWin=26, winSum=423
2639 11:47:59.736066 TX Vref=26, minBit 7, minWin=26, winSum=429
2640 11:47:59.739587 TX Vref=28, minBit 8, minWin=26, winSum=433
2641 11:47:59.742855 TX Vref=30, minBit 10, minWin=25, winSum=430
2642 11:47:59.749345 TX Vref=32, minBit 8, minWin=26, winSum=430
2643 11:47:59.752710 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 28
2644 11:47:59.753279
2645 11:47:59.756251 Final TX Range 1 Vref 28
2646 11:47:59.756737
2647 11:47:59.757160 ==
2648 11:47:59.759683 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 11:47:59.762711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 11:47:59.763099 ==
2651 11:47:59.763730
2652 11:47:59.766463
2653 11:47:59.766879 TX Vref Scan disable
2654 11:47:59.769491 == TX Byte 0 ==
2655 11:47:59.773180 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2656 11:47:59.776703 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2657 11:47:59.779668 == TX Byte 1 ==
2658 11:47:59.782665 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2659 11:47:59.786245 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2660 11:47:59.786755
2661 11:47:59.789776 [DATLAT]
2662 11:47:59.790284 Freq=1200, CH0 RK0
2663 11:47:59.790826
2664 11:47:59.793229 DATLAT Default: 0xd
2665 11:47:59.793833 0, 0xFFFF, sum = 0
2666 11:47:59.796679 1, 0xFFFF, sum = 0
2667 11:47:59.797315 2, 0xFFFF, sum = 0
2668 11:47:59.799510 3, 0xFFFF, sum = 0
2669 11:47:59.799993 4, 0xFFFF, sum = 0
2670 11:47:59.803166 5, 0xFFFF, sum = 0
2671 11:47:59.803677 6, 0xFFFF, sum = 0
2672 11:47:59.805971 7, 0xFFFF, sum = 0
2673 11:47:59.806428 8, 0xFFFF, sum = 0
2674 11:47:59.809305 9, 0xFFFF, sum = 0
2675 11:47:59.812849 10, 0xFFFF, sum = 0
2676 11:47:59.813818 11, 0xFFFF, sum = 0
2677 11:47:59.816377 12, 0x0, sum = 1
2678 11:47:59.816773 13, 0x0, sum = 2
2679 11:47:59.817235 14, 0x0, sum = 3
2680 11:47:59.819903 15, 0x0, sum = 4
2681 11:47:59.820469 best_step = 13
2682 11:47:59.821122
2683 11:47:59.822748 ==
2684 11:47:59.823370 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 11:47:59.829617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 11:47:59.830168 ==
2687 11:47:59.830596 RX Vref Scan: 1
2688 11:47:59.831071
2689 11:47:59.833014 Set Vref Range= 32 -> 127
2690 11:47:59.833567
2691 11:47:59.836084 RX Vref 32 -> 127, step: 1
2692 11:47:59.836612
2693 11:47:59.839554 RX Delay -37 -> 252, step: 4
2694 11:47:59.839988
2695 11:47:59.843023 Set Vref, RX VrefLevel [Byte0]: 32
2696 11:47:59.846011 [Byte1]: 32
2697 11:47:59.846571
2698 11:47:59.849473 Set Vref, RX VrefLevel [Byte0]: 33
2699 11:47:59.852864 [Byte1]: 33
2700 11:47:59.853460
2701 11:47:59.856073 Set Vref, RX VrefLevel [Byte0]: 34
2702 11:47:59.859604 [Byte1]: 34
2703 11:47:59.864146
2704 11:47:59.864740 Set Vref, RX VrefLevel [Byte0]: 35
2705 11:47:59.867487 [Byte1]: 35
2706 11:47:59.872142
2707 11:47:59.872709 Set Vref, RX VrefLevel [Byte0]: 36
2708 11:47:59.875533 [Byte1]: 36
2709 11:47:59.880078
2710 11:47:59.880751 Set Vref, RX VrefLevel [Byte0]: 37
2711 11:47:59.883394 [Byte1]: 37
2712 11:47:59.888126
2713 11:47:59.888711 Set Vref, RX VrefLevel [Byte0]: 38
2714 11:47:59.891395 [Byte1]: 38
2715 11:47:59.896392
2716 11:47:59.896879 Set Vref, RX VrefLevel [Byte0]: 39
2717 11:47:59.899159 [Byte1]: 39
2718 11:47:59.904159
2719 11:47:59.904651 Set Vref, RX VrefLevel [Byte0]: 40
2720 11:47:59.907195 [Byte1]: 40
2721 11:47:59.912320
2722 11:47:59.912858 Set Vref, RX VrefLevel [Byte0]: 41
2723 11:47:59.915452 [Byte1]: 41
2724 11:47:59.920017
2725 11:47:59.920520 Set Vref, RX VrefLevel [Byte0]: 42
2726 11:47:59.923042 [Byte1]: 42
2727 11:47:59.927680
2728 11:47:59.928271 Set Vref, RX VrefLevel [Byte0]: 43
2729 11:47:59.931076 [Byte1]: 43
2730 11:47:59.936287
2731 11:47:59.936812 Set Vref, RX VrefLevel [Byte0]: 44
2732 11:47:59.939378 [Byte1]: 44
2733 11:47:59.943891
2734 11:47:59.944491 Set Vref, RX VrefLevel [Byte0]: 45
2735 11:47:59.947481 [Byte1]: 45
2736 11:47:59.952131
2737 11:47:59.952645 Set Vref, RX VrefLevel [Byte0]: 46
2738 11:47:59.955022 [Byte1]: 46
2739 11:47:59.960016
2740 11:47:59.960541 Set Vref, RX VrefLevel [Byte0]: 47
2741 11:47:59.963530 [Byte1]: 47
2742 11:47:59.968100
2743 11:47:59.968539 Set Vref, RX VrefLevel [Byte0]: 48
2744 11:47:59.970897 [Byte1]: 48
2745 11:47:59.976280
2746 11:47:59.976868 Set Vref, RX VrefLevel [Byte0]: 49
2747 11:47:59.979082 [Byte1]: 49
2748 11:47:59.983706
2749 11:47:59.984194 Set Vref, RX VrefLevel [Byte0]: 50
2750 11:47:59.987134 [Byte1]: 50
2751 11:47:59.991948
2752 11:47:59.992669 Set Vref, RX VrefLevel [Byte0]: 51
2753 11:47:59.995221 [Byte1]: 51
2754 11:47:59.999954
2755 11:48:00.000674 Set Vref, RX VrefLevel [Byte0]: 52
2756 11:48:00.003455 [Byte1]: 52
2757 11:48:00.008188
2758 11:48:00.008648 Set Vref, RX VrefLevel [Byte0]: 53
2759 11:48:00.011040 [Byte1]: 53
2760 11:48:00.016120
2761 11:48:00.016699 Set Vref, RX VrefLevel [Byte0]: 54
2762 11:48:00.019498 [Byte1]: 54
2763 11:48:00.023854
2764 11:48:00.024416 Set Vref, RX VrefLevel [Byte0]: 55
2765 11:48:00.027169 [Byte1]: 55
2766 11:48:00.032044
2767 11:48:00.032628 Set Vref, RX VrefLevel [Byte0]: 56
2768 11:48:00.035108 [Byte1]: 56
2769 11:48:00.039923
2770 11:48:00.040445 Set Vref, RX VrefLevel [Byte0]: 57
2771 11:48:00.043250 [Byte1]: 57
2772 11:48:00.048070
2773 11:48:00.048692 Set Vref, RX VrefLevel [Byte0]: 58
2774 11:48:00.051281 [Byte1]: 58
2775 11:48:00.056096
2776 11:48:00.056655 Set Vref, RX VrefLevel [Byte0]: 59
2777 11:48:00.058962 [Byte1]: 59
2778 11:48:00.063879
2779 11:48:00.064335 Set Vref, RX VrefLevel [Byte0]: 60
2780 11:48:00.067392 [Byte1]: 60
2781 11:48:00.071997
2782 11:48:00.072425 Set Vref, RX VrefLevel [Byte0]: 61
2783 11:48:00.075477 [Byte1]: 61
2784 11:48:00.079991
2785 11:48:00.080421 Set Vref, RX VrefLevel [Byte0]: 62
2786 11:48:00.083495 [Byte1]: 62
2787 11:48:00.088252
2788 11:48:00.088702 Set Vref, RX VrefLevel [Byte0]: 63
2789 11:48:00.091163 [Byte1]: 63
2790 11:48:00.095677
2791 11:48:00.096348 Set Vref, RX VrefLevel [Byte0]: 64
2792 11:48:00.099144 [Byte1]: 64
2793 11:48:00.104160
2794 11:48:00.104664 Set Vref, RX VrefLevel [Byte0]: 65
2795 11:48:00.107163 [Byte1]: 65
2796 11:48:00.111843
2797 11:48:00.112289 Set Vref, RX VrefLevel [Byte0]: 66
2798 11:48:00.115201 [Byte1]: 66
2799 11:48:00.119996
2800 11:48:00.122940 Set Vref, RX VrefLevel [Byte0]: 67
2801 11:48:00.126425 [Byte1]: 67
2802 11:48:00.126879
2803 11:48:00.129840 Set Vref, RX VrefLevel [Byte0]: 68
2804 11:48:00.133093 [Byte1]: 68
2805 11:48:00.133172
2806 11:48:00.135974 Set Vref, RX VrefLevel [Byte0]: 69
2807 11:48:00.139794 [Byte1]: 69
2808 11:48:00.143388
2809 11:48:00.143468 Set Vref, RX VrefLevel [Byte0]: 70
2810 11:48:00.147047 [Byte1]: 70
2811 11:48:00.151710
2812 11:48:00.151789 Set Vref, RX VrefLevel [Byte0]: 71
2813 11:48:00.154814 [Byte1]: 71
2814 11:48:00.159568
2815 11:48:00.159647 Set Vref, RX VrefLevel [Byte0]: 72
2816 11:48:00.162910 [Byte1]: 72
2817 11:48:00.167356
2818 11:48:00.167435 Set Vref, RX VrefLevel [Byte0]: 73
2819 11:48:00.170746 [Byte1]: 73
2820 11:48:00.175952
2821 11:48:00.176499 Set Vref, RX VrefLevel [Byte0]: 74
2822 11:48:00.179166 [Byte1]: 74
2823 11:48:00.183782
2824 11:48:00.184232 Final RX Vref Byte 0 = 61 to rank0
2825 11:48:00.187163 Final RX Vref Byte 1 = 52 to rank0
2826 11:48:00.190593 Final RX Vref Byte 0 = 61 to rank1
2827 11:48:00.194170 Final RX Vref Byte 1 = 52 to rank1==
2828 11:48:00.197143 Dram Type= 6, Freq= 0, CH_0, rank 0
2829 11:48:00.204169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 11:48:00.204647 ==
2831 11:48:00.205191 DQS Delay:
2832 11:48:00.205611 DQS0 = 0, DQS1 = 0
2833 11:48:00.207426 DQM Delay:
2834 11:48:00.207854 DQM0 = 112, DQM1 = 101
2835 11:48:00.210386 DQ Delay:
2836 11:48:00.213808 DQ0 =112, DQ1 =112, DQ2 =114, DQ3 =108
2837 11:48:00.217387 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2838 11:48:00.220860 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2839 11:48:00.223634 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2840 11:48:00.224065
2841 11:48:00.224539
2842 11:48:00.230509 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
2843 11:48:00.233996 CH0 RK0: MR19=303, MR18=FCFB
2844 11:48:00.240467 CH0_RK0: MR19=0x303, MR18=0xFCFB, DQSOSC=411, MR23=63, INC=38, DEC=25
2845 11:48:00.240899
2846 11:48:00.243821 ----->DramcWriteLeveling(PI) begin...
2847 11:48:00.244291 ==
2848 11:48:00.247373 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 11:48:00.250294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 11:48:00.253569 ==
2851 11:48:00.254014 Write leveling (Byte 0): 31 => 31
2852 11:48:00.257436 Write leveling (Byte 1): 29 => 29
2853 11:48:00.260961 DramcWriteLeveling(PI) end<-----
2854 11:48:00.261392
2855 11:48:00.261830 ==
2856 11:48:00.263785 Dram Type= 6, Freq= 0, CH_0, rank 1
2857 11:48:00.270262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 11:48:00.270698 ==
2859 11:48:00.271136 [Gating] SW mode calibration
2860 11:48:00.280198 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2861 11:48:00.283902 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2862 11:48:00.287288 0 15 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
2863 11:48:00.293869 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 11:48:00.297264 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 11:48:00.300534 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 11:48:00.307061 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 11:48:00.310439 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 11:48:00.314136 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2869 11:48:00.320367 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
2870 11:48:00.323954 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2871 11:48:00.326964 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 11:48:00.333839 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 11:48:00.337286 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 11:48:00.340766 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 11:48:00.347218 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 11:48:00.350613 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2877 11:48:00.353642 1 0 28 | B1->B0 | 2727 4545 | 0 0 | (0 0) (0 0)
2878 11:48:00.360286 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2879 11:48:00.363531 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 11:48:00.367080 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 11:48:00.373587 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 11:48:00.377118 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 11:48:00.380650 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 11:48:00.387072 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 11:48:00.390022 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2886 11:48:00.393703 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2887 11:48:00.397002 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:48:00.403448 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 11:48:00.406570 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 11:48:00.410375 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 11:48:00.416703 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 11:48:00.419918 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 11:48:00.423512 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 11:48:00.430075 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 11:48:00.433618 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 11:48:00.436675 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 11:48:00.443654 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 11:48:00.447051 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 11:48:00.450077 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 11:48:00.457007 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 11:48:00.460358 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2902 11:48:00.463636 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2903 11:48:00.466949 Total UI for P1: 0, mck2ui 16
2904 11:48:00.470483 best dqsien dly found for B0: ( 1, 3, 28)
2905 11:48:00.476794 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 11:48:00.477209 Total UI for P1: 0, mck2ui 16
2907 11:48:00.480374 best dqsien dly found for B1: ( 1, 4, 0)
2908 11:48:00.486721 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2909 11:48:00.490337 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2910 11:48:00.490749
2911 11:48:00.493920 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2912 11:48:00.496777 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2913 11:48:00.500318 [Gating] SW calibration Done
2914 11:48:00.500739 ==
2915 11:48:00.503844 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 11:48:00.507024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 11:48:00.507442 ==
2918 11:48:00.507772 RX Vref Scan: 0
2919 11:48:00.510220
2920 11:48:00.510636 RX Vref 0 -> 0, step: 1
2921 11:48:00.510965
2922 11:48:00.513738 RX Delay -40 -> 252, step: 8
2923 11:48:00.516757 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2924 11:48:00.520192 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2925 11:48:00.527049 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2926 11:48:00.530351 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2927 11:48:00.533628 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2928 11:48:00.536730 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2929 11:48:00.540323 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2930 11:48:00.547009 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2931 11:48:00.550032 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2932 11:48:00.553560 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2933 11:48:00.556486 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2934 11:48:00.559872 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2935 11:48:00.563816 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2936 11:48:00.570460 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2937 11:48:00.573556 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2938 11:48:00.577074 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2939 11:48:00.577492 ==
2940 11:48:00.580008 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 11:48:00.583469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 11:48:00.587102 ==
2943 11:48:00.587518 DQS Delay:
2944 11:48:00.587852 DQS0 = 0, DQS1 = 0
2945 11:48:00.590051 DQM Delay:
2946 11:48:00.590465 DQM0 = 111, DQM1 = 101
2947 11:48:00.593733 DQ Delay:
2948 11:48:00.596529 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2949 11:48:00.599989 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2950 11:48:00.603536 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2951 11:48:00.606967 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
2952 11:48:00.607385
2953 11:48:00.607717
2954 11:48:00.608025 ==
2955 11:48:00.610492 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 11:48:00.613585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 11:48:00.614005 ==
2958 11:48:00.614359
2959 11:48:00.614668
2960 11:48:00.616739 TX Vref Scan disable
2961 11:48:00.620120 == TX Byte 0 ==
2962 11:48:00.623629 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2963 11:48:00.626825 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2964 11:48:00.630191 == TX Byte 1 ==
2965 11:48:00.633176 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2966 11:48:00.636751 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2967 11:48:00.637168 ==
2968 11:48:00.640250 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 11:48:00.643591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 11:48:00.646913 ==
2971 11:48:00.656838 TX Vref=22, minBit 0, minWin=26, winSum=426
2972 11:48:00.660555 TX Vref=24, minBit 4, minWin=26, winSum=432
2973 11:48:00.663662 TX Vref=26, minBit 5, minWin=26, winSum=432
2974 11:48:00.667057 TX Vref=28, minBit 8, minWin=26, winSum=439
2975 11:48:00.670014 TX Vref=30, minBit 13, minWin=26, winSum=441
2976 11:48:00.673562 TX Vref=32, minBit 8, minWin=26, winSum=439
2977 11:48:00.680068 [TxChooseVref] Worse bit 13, Min win 26, Win sum 441, Final Vref 30
2978 11:48:00.680553
2979 11:48:00.683419 Final TX Range 1 Vref 30
2980 11:48:00.683826
2981 11:48:00.684147 ==
2982 11:48:00.686771 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 11:48:00.690593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 11:48:00.691005 ==
2985 11:48:00.691329
2986 11:48:00.693462
2987 11:48:00.693867 TX Vref Scan disable
2988 11:48:00.696981 == TX Byte 0 ==
2989 11:48:00.700418 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2990 11:48:00.703345 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2991 11:48:00.706796 == TX Byte 1 ==
2992 11:48:00.710264 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2993 11:48:00.713740 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2994 11:48:00.716636
2995 11:48:00.717056 [DATLAT]
2996 11:48:00.717493 Freq=1200, CH0 RK1
2997 11:48:00.717905
2998 11:48:00.720551 DATLAT Default: 0xd
2999 11:48:00.720974 0, 0xFFFF, sum = 0
3000 11:48:00.723611 1, 0xFFFF, sum = 0
3001 11:48:00.724040 2, 0xFFFF, sum = 0
3002 11:48:00.726920 3, 0xFFFF, sum = 0
3003 11:48:00.727353 4, 0xFFFF, sum = 0
3004 11:48:00.730423 5, 0xFFFF, sum = 0
3005 11:48:00.733782 6, 0xFFFF, sum = 0
3006 11:48:00.734215 7, 0xFFFF, sum = 0
3007 11:48:00.736703 8, 0xFFFF, sum = 0
3008 11:48:00.737130 9, 0xFFFF, sum = 0
3009 11:48:00.740129 10, 0xFFFF, sum = 0
3010 11:48:00.740628 11, 0xFFFF, sum = 0
3011 11:48:00.743629 12, 0x0, sum = 1
3012 11:48:00.744061 13, 0x0, sum = 2
3013 11:48:00.747093 14, 0x0, sum = 3
3014 11:48:00.747521 15, 0x0, sum = 4
3015 11:48:00.747962 best_step = 13
3016 11:48:00.748454
3017 11:48:00.750138 ==
3018 11:48:00.753706 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 11:48:00.756988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 11:48:00.757414 ==
3021 11:48:00.757845 RX Vref Scan: 0
3022 11:48:00.758250
3023 11:48:00.760173 RX Vref 0 -> 0, step: 1
3024 11:48:00.760639
3025 11:48:00.763594 RX Delay -37 -> 252, step: 4
3026 11:48:00.766763 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3027 11:48:00.773467 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3028 11:48:00.776473 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3029 11:48:00.779826 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3030 11:48:00.783495 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3031 11:48:00.786474 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3032 11:48:00.793143 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3033 11:48:00.796403 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3034 11:48:00.799958 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3035 11:48:00.803226 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3036 11:48:00.806962 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3037 11:48:00.809940 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3038 11:48:00.816969 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3039 11:48:00.819877 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3040 11:48:00.823436 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3041 11:48:00.826444 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3042 11:48:00.826869 ==
3043 11:48:00.830222 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 11:48:00.836702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 11:48:00.837133 ==
3046 11:48:00.837562 DQS Delay:
3047 11:48:00.840032 DQS0 = 0, DQS1 = 0
3048 11:48:00.840498 DQM Delay:
3049 11:48:00.840930 DQM0 = 110, DQM1 = 101
3050 11:48:00.843576 DQ Delay:
3051 11:48:00.846523 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3052 11:48:00.850059 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3053 11:48:00.853426 DQ8 =90, DQ9 =82, DQ10 =104, DQ11 =92
3054 11:48:00.856838 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3055 11:48:00.857262
3056 11:48:00.857688
3057 11:48:00.863251 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3058 11:48:00.866737 CH0 RK1: MR19=403, MR18=12F9
3059 11:48:00.873445 CH0_RK1: MR19=0x403, MR18=0x12F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3060 11:48:00.877167 [RxdqsGatingPostProcess] freq 1200
3061 11:48:00.883216 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3062 11:48:00.886667 best DQS0 dly(2T, 0.5T) = (0, 12)
3063 11:48:00.889885 best DQS1 dly(2T, 0.5T) = (0, 12)
3064 11:48:00.890303 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3065 11:48:00.893627 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3066 11:48:00.896912 best DQS0 dly(2T, 0.5T) = (0, 11)
3067 11:48:00.899918 best DQS1 dly(2T, 0.5T) = (0, 12)
3068 11:48:00.903382 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3069 11:48:00.906693 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3070 11:48:00.909911 Pre-setting of DQS Precalculation
3071 11:48:00.916844 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3072 11:48:00.917279 ==
3073 11:48:00.920017 Dram Type= 6, Freq= 0, CH_1, rank 0
3074 11:48:00.923236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 11:48:00.923661 ==
3076 11:48:00.930006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3077 11:48:00.933440 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3078 11:48:00.942885 [CA 0] Center 37 (7~67) winsize 61
3079 11:48:00.946001 [CA 1] Center 37 (7~68) winsize 62
3080 11:48:00.949605 [CA 2] Center 34 (4~64) winsize 61
3081 11:48:00.953151 [CA 3] Center 33 (3~64) winsize 62
3082 11:48:00.955912 [CA 4] Center 34 (4~64) winsize 61
3083 11:48:00.959472 [CA 5] Center 33 (3~63) winsize 61
3084 11:48:00.959898
3085 11:48:00.963005 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3086 11:48:00.963429
3087 11:48:00.966391 [CATrainingPosCal] consider 1 rank data
3088 11:48:00.969226 u2DelayCellTimex100 = 270/100 ps
3089 11:48:00.972733 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3090 11:48:00.976169 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3091 11:48:00.982963 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 11:48:00.986140 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3093 11:48:00.989552 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 11:48:00.992934 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3095 11:48:00.993357
3096 11:48:00.996596 CA PerBit enable=1, Macro0, CA PI delay=33
3097 11:48:00.997016
3098 11:48:00.999225 [CBTSetCACLKResult] CA Dly = 33
3099 11:48:00.999643 CS Dly: 5 (0~36)
3100 11:48:00.999973 ==
3101 11:48:01.002715 Dram Type= 6, Freq= 0, CH_1, rank 1
3102 11:48:01.009570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 11:48:01.009992 ==
3104 11:48:01.013063 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3105 11:48:01.019387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3106 11:48:01.028658 [CA 0] Center 37 (7~67) winsize 61
3107 11:48:01.031999 [CA 1] Center 37 (7~68) winsize 62
3108 11:48:01.035273 [CA 2] Center 34 (4~65) winsize 62
3109 11:48:01.038226 [CA 3] Center 33 (3~64) winsize 62
3110 11:48:01.041715 [CA 4] Center 34 (4~65) winsize 62
3111 11:48:01.045044 [CA 5] Center 33 (2~64) winsize 63
3112 11:48:01.045462
3113 11:48:01.048265 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3114 11:48:01.048690
3115 11:48:01.051411 [CATrainingPosCal] consider 2 rank data
3116 11:48:01.054986 u2DelayCellTimex100 = 270/100 ps
3117 11:48:01.058266 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3118 11:48:01.061903 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3119 11:48:01.068275 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 11:48:01.071674 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3121 11:48:01.074710 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 11:48:01.078105 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3123 11:48:01.078523
3124 11:48:01.081615 CA PerBit enable=1, Macro0, CA PI delay=33
3125 11:48:01.082036
3126 11:48:01.084574 [CBTSetCACLKResult] CA Dly = 33
3127 11:48:01.084987 CS Dly: 6 (0~39)
3128 11:48:01.088168
3129 11:48:01.091381 ----->DramcWriteLeveling(PI) begin...
3130 11:48:01.091796 ==
3131 11:48:01.094893 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 11:48:01.098267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 11:48:01.098879 ==
3134 11:48:01.101255 Write leveling (Byte 0): 24 => 24
3135 11:48:01.104799 Write leveling (Byte 1): 29 => 29
3136 11:48:01.107964 DramcWriteLeveling(PI) end<-----
3137 11:48:01.108428
3138 11:48:01.108760 ==
3139 11:48:01.111324 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 11:48:01.114897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 11:48:01.115312 ==
3142 11:48:01.117978 [Gating] SW mode calibration
3143 11:48:01.124814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3144 11:48:01.131409 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3145 11:48:01.134939 0 15 0 | B1->B0 | 2f2f 2727 | 0 1 | (0 0) (1 1)
3146 11:48:01.138406 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 11:48:01.141294 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 11:48:01.148433 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 11:48:01.151349 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 11:48:01.154803 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 11:48:01.161731 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3152 11:48:01.164795 0 15 28 | B1->B0 | 2c2c 3131 | 0 0 | (0 0) (0 1)
3153 11:48:01.168154 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 11:48:01.175104 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 11:48:01.178598 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 11:48:01.181580 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 11:48:01.188752 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 11:48:01.191679 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 11:48:01.195222 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3160 11:48:01.201444 1 0 28 | B1->B0 | 3f3f 3d3c | 0 1 | (0 0) (0 0)
3161 11:48:01.204859 1 1 0 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
3162 11:48:01.208446 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 11:48:01.212038 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 11:48:01.218550 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 11:48:01.221905 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 11:48:01.224907 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 11:48:01.231802 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 11:48:01.235304 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 11:48:01.238491 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3170 11:48:01.245088 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 11:48:01.248579 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 11:48:01.251361 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 11:48:01.258605 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 11:48:01.261604 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 11:48:01.264833 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 11:48:01.271437 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 11:48:01.275132 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 11:48:01.278185 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 11:48:01.284896 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 11:48:01.287775 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 11:48:01.291376 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 11:48:01.297845 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 11:48:01.301409 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 11:48:01.304863 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3185 11:48:01.311176 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3186 11:48:01.311356 Total UI for P1: 0, mck2ui 16
3187 11:48:01.314427 best dqsien dly found for B1: ( 1, 3, 30)
3188 11:48:01.321377 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 11:48:01.324720 Total UI for P1: 0, mck2ui 16
3190 11:48:01.328194 best dqsien dly found for B0: ( 1, 3, 30)
3191 11:48:01.331604 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3192 11:48:01.334458 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3193 11:48:01.334587
3194 11:48:01.338031 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3195 11:48:01.341479 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3196 11:48:01.344853 [Gating] SW calibration Done
3197 11:48:01.344953 ==
3198 11:48:01.348076 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 11:48:01.351173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 11:48:01.351264 ==
3201 11:48:01.354474 RX Vref Scan: 0
3202 11:48:01.354555
3203 11:48:01.354620 RX Vref 0 -> 0, step: 1
3204 11:48:01.358029
3205 11:48:01.358110 RX Delay -40 -> 252, step: 8
3206 11:48:01.364357 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3207 11:48:01.367694 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3208 11:48:01.370953 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3209 11:48:01.374556 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3210 11:48:01.377753 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3211 11:48:01.384656 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3212 11:48:01.387798 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3213 11:48:01.391117 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3214 11:48:01.394567 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3215 11:48:01.397527 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3216 11:48:01.401115 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3217 11:48:01.407717 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3218 11:48:01.411185 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3219 11:48:01.414070 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3220 11:48:01.417727 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3221 11:48:01.424441 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3222 11:48:01.424521 ==
3223 11:48:01.427631 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 11:48:01.431500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 11:48:01.431581 ==
3226 11:48:01.431645 DQS Delay:
3227 11:48:01.434279 DQS0 = 0, DQS1 = 0
3228 11:48:01.434349 DQM Delay:
3229 11:48:01.437650 DQM0 = 114, DQM1 = 106
3230 11:48:01.437730 DQ Delay:
3231 11:48:01.441167 DQ0 =123, DQ1 =107, DQ2 =103, DQ3 =111
3232 11:48:01.444131 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3233 11:48:01.447744 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3234 11:48:01.451125 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3235 11:48:01.451211
3236 11:48:01.451288
3237 11:48:01.451365 ==
3238 11:48:01.454493 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 11:48:01.460818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 11:48:01.460918 ==
3241 11:48:01.460997
3242 11:48:01.461070
3243 11:48:01.461142 TX Vref Scan disable
3244 11:48:01.464969 == TX Byte 0 ==
3245 11:48:01.468168 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3246 11:48:01.474709 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3247 11:48:01.474875 == TX Byte 1 ==
3248 11:48:01.478106 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3249 11:48:01.481384 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3250 11:48:01.484623 ==
3251 11:48:01.488040 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 11:48:01.491172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 11:48:01.491374 ==
3254 11:48:01.503033 TX Vref=22, minBit 2, minWin=25, winSum=410
3255 11:48:01.505949 TX Vref=24, minBit 11, minWin=24, winSum=417
3256 11:48:01.509389 TX Vref=26, minBit 8, minWin=25, winSum=421
3257 11:48:01.513013 TX Vref=28, minBit 1, minWin=26, winSum=428
3258 11:48:01.516591 TX Vref=30, minBit 11, minWin=25, winSum=426
3259 11:48:01.522816 TX Vref=32, minBit 9, minWin=25, winSum=424
3260 11:48:01.526394 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3261 11:48:01.526810
3262 11:48:01.529704 Final TX Range 1 Vref 28
3263 11:48:01.530209
3264 11:48:01.530647 ==
3265 11:48:01.533027 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 11:48:01.536297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 11:48:01.539420 ==
3268 11:48:01.539827
3269 11:48:01.540145
3270 11:48:01.540499 TX Vref Scan disable
3271 11:48:01.543065 == TX Byte 0 ==
3272 11:48:01.546325 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3273 11:48:01.549874 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3274 11:48:01.553421 == TX Byte 1 ==
3275 11:48:01.556165 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3276 11:48:01.559469 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3277 11:48:01.562992
3278 11:48:01.563581 [DATLAT]
3279 11:48:01.563911 Freq=1200, CH1 RK0
3280 11:48:01.564366
3281 11:48:01.566217 DATLAT Default: 0xd
3282 11:48:01.566624 0, 0xFFFF, sum = 0
3283 11:48:01.569772 1, 0xFFFF, sum = 0
3284 11:48:01.570187 2, 0xFFFF, sum = 0
3285 11:48:01.573237 3, 0xFFFF, sum = 0
3286 11:48:01.573653 4, 0xFFFF, sum = 0
3287 11:48:01.576171 5, 0xFFFF, sum = 0
3288 11:48:01.579484 6, 0xFFFF, sum = 0
3289 11:48:01.579899 7, 0xFFFF, sum = 0
3290 11:48:01.582948 8, 0xFFFF, sum = 0
3291 11:48:01.583365 9, 0xFFFF, sum = 0
3292 11:48:01.586513 10, 0xFFFF, sum = 0
3293 11:48:01.586928 11, 0xFFFF, sum = 0
3294 11:48:01.589902 12, 0x0, sum = 1
3295 11:48:01.590312 13, 0x0, sum = 2
3296 11:48:01.593107 14, 0x0, sum = 3
3297 11:48:01.593514 15, 0x0, sum = 4
3298 11:48:01.593840 best_step = 13
3299 11:48:01.594137
3300 11:48:01.596804 ==
3301 11:48:01.600115 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 11:48:01.603367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 11:48:01.603688 ==
3304 11:48:01.603915 RX Vref Scan: 1
3305 11:48:01.604124
3306 11:48:01.606323 Set Vref Range= 32 -> 127
3307 11:48:01.606610
3308 11:48:01.609828 RX Vref 32 -> 127, step: 1
3309 11:48:01.610045
3310 11:48:01.613276 RX Delay -21 -> 252, step: 4
3311 11:48:01.613498
3312 11:48:01.616016 Set Vref, RX VrefLevel [Byte0]: 32
3313 11:48:01.619673 [Byte1]: 32
3314 11:48:01.619819
3315 11:48:01.622563 Set Vref, RX VrefLevel [Byte0]: 33
3316 11:48:01.625865 [Byte1]: 33
3317 11:48:01.625944
3318 11:48:01.629483 Set Vref, RX VrefLevel [Byte0]: 34
3319 11:48:01.632869 [Byte1]: 34
3320 11:48:01.636926
3321 11:48:01.637021 Set Vref, RX VrefLevel [Byte0]: 35
3322 11:48:01.640415 [Byte1]: 35
3323 11:48:01.645015
3324 11:48:01.645108 Set Vref, RX VrefLevel [Byte0]: 36
3325 11:48:01.648144 [Byte1]: 36
3326 11:48:01.652884
3327 11:48:01.652961 Set Vref, RX VrefLevel [Byte0]: 37
3328 11:48:01.656141 [Byte1]: 37
3329 11:48:01.660684
3330 11:48:01.660789 Set Vref, RX VrefLevel [Byte0]: 38
3331 11:48:01.664195 [Byte1]: 38
3332 11:48:01.668933
3333 11:48:01.669013 Set Vref, RX VrefLevel [Byte0]: 39
3334 11:48:01.672395 [Byte1]: 39
3335 11:48:01.676567
3336 11:48:01.676645 Set Vref, RX VrefLevel [Byte0]: 40
3337 11:48:01.679876 [Byte1]: 40
3338 11:48:01.684547
3339 11:48:01.684626 Set Vref, RX VrefLevel [Byte0]: 41
3340 11:48:01.688107 [Byte1]: 41
3341 11:48:01.692809
3342 11:48:01.692887 Set Vref, RX VrefLevel [Byte0]: 42
3343 11:48:01.695617 [Byte1]: 42
3344 11:48:01.700764
3345 11:48:01.700842 Set Vref, RX VrefLevel [Byte0]: 43
3346 11:48:01.703425 [Byte1]: 43
3347 11:48:01.708118
3348 11:48:01.708244 Set Vref, RX VrefLevel [Byte0]: 44
3349 11:48:01.711606 [Byte1]: 44
3350 11:48:01.716121
3351 11:48:01.716261 Set Vref, RX VrefLevel [Byte0]: 45
3352 11:48:01.719411 [Byte1]: 45
3353 11:48:01.724003
3354 11:48:01.724081 Set Vref, RX VrefLevel [Byte0]: 46
3355 11:48:01.727879 [Byte1]: 46
3356 11:48:01.732040
3357 11:48:01.732118 Set Vref, RX VrefLevel [Byte0]: 47
3358 11:48:01.735643 [Byte1]: 47
3359 11:48:01.740448
3360 11:48:01.740527 Set Vref, RX VrefLevel [Byte0]: 48
3361 11:48:01.743364 [Byte1]: 48
3362 11:48:01.748001
3363 11:48:01.748080 Set Vref, RX VrefLevel [Byte0]: 49
3364 11:48:01.751418 [Byte1]: 49
3365 11:48:01.755915
3366 11:48:01.755994 Set Vref, RX VrefLevel [Byte0]: 50
3367 11:48:01.759141 [Byte1]: 50
3368 11:48:01.763601
3369 11:48:01.763679 Set Vref, RX VrefLevel [Byte0]: 51
3370 11:48:01.766998 [Byte1]: 51
3371 11:48:01.771575
3372 11:48:01.771654 Set Vref, RX VrefLevel [Byte0]: 52
3373 11:48:01.775048 [Byte1]: 52
3374 11:48:01.779520
3375 11:48:01.779599 Set Vref, RX VrefLevel [Byte0]: 53
3376 11:48:01.782870 [Byte1]: 53
3377 11:48:01.787521
3378 11:48:01.787601 Set Vref, RX VrefLevel [Byte0]: 54
3379 11:48:01.791138 [Byte1]: 54
3380 11:48:01.795846
3381 11:48:01.795925 Set Vref, RX VrefLevel [Byte0]: 55
3382 11:48:01.798668 [Byte1]: 55
3383 11:48:01.803290
3384 11:48:01.803369 Set Vref, RX VrefLevel [Byte0]: 56
3385 11:48:01.806484 [Byte1]: 56
3386 11:48:01.811177
3387 11:48:01.811256 Set Vref, RX VrefLevel [Byte0]: 57
3388 11:48:01.814715 [Byte1]: 57
3389 11:48:01.819285
3390 11:48:01.819364 Set Vref, RX VrefLevel [Byte0]: 58
3391 11:48:01.822799 [Byte1]: 58
3392 11:48:01.826860
3393 11:48:01.826939 Set Vref, RX VrefLevel [Byte0]: 59
3394 11:48:01.830205 [Byte1]: 59
3395 11:48:01.834819
3396 11:48:01.834898 Set Vref, RX VrefLevel [Byte0]: 60
3397 11:48:01.838037 [Byte1]: 60
3398 11:48:01.842875
3399 11:48:01.842955 Set Vref, RX VrefLevel [Byte0]: 61
3400 11:48:01.846400 [Byte1]: 61
3401 11:48:01.850948
3402 11:48:01.851028 Set Vref, RX VrefLevel [Byte0]: 62
3403 11:48:01.854416 [Byte1]: 62
3404 11:48:01.858501
3405 11:48:01.858584 Set Vref, RX VrefLevel [Byte0]: 63
3406 11:48:01.861995 [Byte1]: 63
3407 11:48:01.866619
3408 11:48:01.866701 Set Vref, RX VrefLevel [Byte0]: 64
3409 11:48:01.869771 [Byte1]: 64
3410 11:48:01.874604
3411 11:48:01.874678 Set Vref, RX VrefLevel [Byte0]: 65
3412 11:48:01.877721 [Byte1]: 65
3413 11:48:01.882340
3414 11:48:01.882426 Set Vref, RX VrefLevel [Byte0]: 66
3415 11:48:01.885762 [Byte1]: 66
3416 11:48:01.890678
3417 11:48:01.890753 Set Vref, RX VrefLevel [Byte0]: 67
3418 11:48:01.893703 [Byte1]: 67
3419 11:48:01.898424
3420 11:48:01.898499 Final RX Vref Byte 0 = 54 to rank0
3421 11:48:01.901836 Final RX Vref Byte 1 = 51 to rank0
3422 11:48:01.905481 Final RX Vref Byte 0 = 54 to rank1
3423 11:48:01.908192 Final RX Vref Byte 1 = 51 to rank1==
3424 11:48:01.911878 Dram Type= 6, Freq= 0, CH_1, rank 0
3425 11:48:01.918383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 11:48:01.918460 ==
3427 11:48:01.918524 DQS Delay:
3428 11:48:01.918583 DQS0 = 0, DQS1 = 0
3429 11:48:01.921341 DQM Delay:
3430 11:48:01.921419 DQM0 = 114, DQM1 = 105
3431 11:48:01.924915 DQ Delay:
3432 11:48:01.928251 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3433 11:48:01.931636 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3434 11:48:01.935004 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =100
3435 11:48:01.938072 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =112
3436 11:48:01.938143
3437 11:48:01.938211
3438 11:48:01.947858 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3439 11:48:01.947936 CH1 RK0: MR19=303, MR18=F1F8
3440 11:48:01.954664 CH1_RK0: MR19=0x303, MR18=0xF1F8, DQSOSC=413, MR23=63, INC=38, DEC=25
3441 11:48:01.954740
3442 11:48:01.958256 ----->DramcWriteLeveling(PI) begin...
3443 11:48:01.958330 ==
3444 11:48:01.961384 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 11:48:01.964567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 11:48:01.968082 ==
3447 11:48:01.971448 Write leveling (Byte 0): 26 => 26
3448 11:48:01.971520 Write leveling (Byte 1): 28 => 28
3449 11:48:01.974744 DramcWriteLeveling(PI) end<-----
3450 11:48:01.974816
3451 11:48:01.974876 ==
3452 11:48:01.978178 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 11:48:01.984624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 11:48:01.984710 ==
3455 11:48:01.987843 [Gating] SW mode calibration
3456 11:48:01.994604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3457 11:48:01.997906 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3458 11:48:02.004859 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 11:48:02.007783 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 11:48:02.011245 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 11:48:02.018125 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 11:48:02.021295 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 11:48:02.024692 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3464 11:48:02.031170 0 15 24 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
3465 11:48:02.034643 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 11:48:02.038028 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 11:48:02.041402 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 11:48:02.047733 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 11:48:02.051186 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 11:48:02.054802 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 11:48:02.061051 1 0 20 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
3472 11:48:02.064382 1 0 24 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
3473 11:48:02.067613 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3474 11:48:02.074624 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 11:48:02.077850 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 11:48:02.081365 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 11:48:02.087821 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 11:48:02.091005 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 11:48:02.094320 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3480 11:48:02.101144 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3481 11:48:02.104407 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 11:48:02.107490 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 11:48:02.114094 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 11:48:02.117567 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 11:48:02.120633 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 11:48:02.127751 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 11:48:02.130740 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 11:48:02.134228 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 11:48:02.140525 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 11:48:02.143869 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 11:48:02.147256 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 11:48:02.154315 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 11:48:02.157089 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 11:48:02.160475 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 11:48:02.167450 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 11:48:02.170426 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3497 11:48:02.173832 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3498 11:48:02.177100 Total UI for P1: 0, mck2ui 16
3499 11:48:02.180232 best dqsien dly found for B0: ( 1, 3, 24)
3500 11:48:02.184063 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 11:48:02.186880 Total UI for P1: 0, mck2ui 16
3502 11:48:02.190196 best dqsien dly found for B1: ( 1, 3, 26)
3503 11:48:02.193631 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3504 11:48:02.200671 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3505 11:48:02.200753
3506 11:48:02.203799 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3507 11:48:02.207285 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3508 11:48:02.210238 [Gating] SW calibration Done
3509 11:48:02.210321 ==
3510 11:48:02.213527 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 11:48:02.216842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 11:48:02.216925 ==
3513 11:48:02.220018 RX Vref Scan: 0
3514 11:48:02.220100
3515 11:48:02.220183 RX Vref 0 -> 0, step: 1
3516 11:48:02.220302
3517 11:48:02.223763 RX Delay -40 -> 252, step: 8
3518 11:48:02.226838 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3519 11:48:02.230359 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3520 11:48:02.237060 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3521 11:48:02.240441 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3522 11:48:02.243299 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3523 11:48:02.246683 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3524 11:48:02.250207 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3525 11:48:02.257318 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3526 11:48:02.260094 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3527 11:48:02.263699 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3528 11:48:02.267085 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3529 11:48:02.269985 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3530 11:48:02.277200 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3531 11:48:02.280261 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3532 11:48:02.283800 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3533 11:48:02.286831 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3534 11:48:02.287304 ==
3535 11:48:02.290681 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 11:48:02.296844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 11:48:02.297450 ==
3538 11:48:02.298068 DQS Delay:
3539 11:48:02.300257 DQS0 = 0, DQS1 = 0
3540 11:48:02.300831 DQM Delay:
3541 11:48:02.301350 DQM0 = 110, DQM1 = 108
3542 11:48:02.303377 DQ Delay:
3543 11:48:02.307001 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3544 11:48:02.310386 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3545 11:48:02.313555 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3546 11:48:02.316964 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =115
3547 11:48:02.317401
3548 11:48:02.317832
3549 11:48:02.318236 ==
3550 11:48:02.319945 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 11:48:02.323891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 11:48:02.327065 ==
3553 11:48:02.327605
3554 11:48:02.328179
3555 11:48:02.328728 TX Vref Scan disable
3556 11:48:02.330171 == TX Byte 0 ==
3557 11:48:02.333644 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3558 11:48:02.337129 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3559 11:48:02.340110 == TX Byte 1 ==
3560 11:48:02.343630 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3561 11:48:02.346423 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3562 11:48:02.349678 ==
3563 11:48:02.350261 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 11:48:02.356310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 11:48:02.356871 ==
3566 11:48:02.367425 TX Vref=22, minBit 9, minWin=25, winSum=422
3567 11:48:02.370880 TX Vref=24, minBit 0, minWin=26, winSum=424
3568 11:48:02.374581 TX Vref=26, minBit 8, minWin=26, winSum=433
3569 11:48:02.377425 TX Vref=28, minBit 1, minWin=26, winSum=433
3570 11:48:02.380904 TX Vref=30, minBit 9, minWin=26, winSum=437
3571 11:48:02.387278 TX Vref=32, minBit 8, minWin=26, winSum=434
3572 11:48:02.390926 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3573 11:48:02.391348
3574 11:48:02.394074 Final TX Range 1 Vref 30
3575 11:48:02.394493
3576 11:48:02.394820 ==
3577 11:48:02.397712 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 11:48:02.400999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 11:48:02.401420 ==
3580 11:48:02.403695
3581 11:48:02.404107
3582 11:48:02.404516 TX Vref Scan disable
3583 11:48:02.407169 == TX Byte 0 ==
3584 11:48:02.410583 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3585 11:48:02.414143 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3586 11:48:02.417300 == TX Byte 1 ==
3587 11:48:02.420906 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3588 11:48:02.423649 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3589 11:48:02.427228
3590 11:48:02.427645 [DATLAT]
3591 11:48:02.427975 Freq=1200, CH1 RK1
3592 11:48:02.428350
3593 11:48:02.430444 DATLAT Default: 0xd
3594 11:48:02.430857 0, 0xFFFF, sum = 0
3595 11:48:02.434129 1, 0xFFFF, sum = 0
3596 11:48:02.434553 2, 0xFFFF, sum = 0
3597 11:48:02.437284 3, 0xFFFF, sum = 0
3598 11:48:02.440334 4, 0xFFFF, sum = 0
3599 11:48:02.440760 5, 0xFFFF, sum = 0
3600 11:48:02.443844 6, 0xFFFF, sum = 0
3601 11:48:02.444324 7, 0xFFFF, sum = 0
3602 11:48:02.447067 8, 0xFFFF, sum = 0
3603 11:48:02.447493 9, 0xFFFF, sum = 0
3604 11:48:02.450579 10, 0xFFFF, sum = 0
3605 11:48:02.451005 11, 0xFFFF, sum = 0
3606 11:48:02.454072 12, 0x0, sum = 1
3607 11:48:02.454498 13, 0x0, sum = 2
3608 11:48:02.457296 14, 0x0, sum = 3
3609 11:48:02.457559 15, 0x0, sum = 4
3610 11:48:02.457624 best_step = 13
3611 11:48:02.460354
3612 11:48:02.460435 ==
3613 11:48:02.463806 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 11:48:02.466793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 11:48:02.466874 ==
3616 11:48:02.466938 RX Vref Scan: 0
3617 11:48:02.466998
3618 11:48:02.470356 RX Vref 0 -> 0, step: 1
3619 11:48:02.470438
3620 11:48:02.473180 RX Delay -21 -> 252, step: 4
3621 11:48:02.476735 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3622 11:48:02.483529 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3623 11:48:02.486484 iDelay=195, Bit 2, Center 98 (27 ~ 170) 144
3624 11:48:02.489871 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3625 11:48:02.493396 iDelay=195, Bit 4, Center 108 (35 ~ 182) 148
3626 11:48:02.496999 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3627 11:48:02.502975 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3628 11:48:02.506594 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3629 11:48:02.510059 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3630 11:48:02.513116 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3631 11:48:02.516480 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3632 11:48:02.523378 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3633 11:48:02.526736 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3634 11:48:02.530057 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3635 11:48:02.533469 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3636 11:48:02.536616 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3637 11:48:02.539632 ==
3638 11:48:02.543562 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 11:48:02.546445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 11:48:02.546687 ==
3641 11:48:02.546878 DQS Delay:
3642 11:48:02.550096 DQS0 = 0, DQS1 = 0
3643 11:48:02.550396 DQM Delay:
3644 11:48:02.553130 DQM0 = 110, DQM1 = 109
3645 11:48:02.553453 DQ Delay:
3646 11:48:02.556704 DQ0 =114, DQ1 =108, DQ2 =98, DQ3 =108
3647 11:48:02.559974 DQ4 =108, DQ5 =120, DQ6 =120, DQ7 =108
3648 11:48:02.563027 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3649 11:48:02.566716 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3650 11:48:02.567179
3651 11:48:02.567539
3652 11:48:02.576543 [DQSOSCAuto] RK1, (LSB)MR18= 0xf807, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3653 11:48:02.580058 CH1 RK1: MR19=304, MR18=F807
3654 11:48:02.583539 CH1_RK1: MR19=0x304, MR18=0xF807, DQSOSC=407, MR23=63, INC=39, DEC=26
3655 11:48:02.586397 [RxdqsGatingPostProcess] freq 1200
3656 11:48:02.593436 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3657 11:48:02.596382 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 11:48:02.599803 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 11:48:02.603355 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 11:48:02.606651 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 11:48:02.609728 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 11:48:02.612993 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 11:48:02.616789 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 11:48:02.619631 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 11:48:02.620040 Pre-setting of DQS Precalculation
3666 11:48:02.626121 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3667 11:48:02.633006 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3668 11:48:02.639347 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3669 11:48:02.639758
3670 11:48:02.640094
3671 11:48:02.642849 [Calibration Summary] 2400 Mbps
3672 11:48:02.646210 CH 0, Rank 0
3673 11:48:02.646617 SW Impedance : PASS
3674 11:48:02.649591 DUTY Scan : NO K
3675 11:48:02.652858 ZQ Calibration : PASS
3676 11:48:02.653367 Jitter Meter : NO K
3677 11:48:02.656322 CBT Training : PASS
3678 11:48:02.659023 Write leveling : PASS
3679 11:48:02.659669 RX DQS gating : PASS
3680 11:48:02.662680 RX DQ/DQS(RDDQC) : PASS
3681 11:48:02.665863 TX DQ/DQS : PASS
3682 11:48:02.666281 RX DATLAT : PASS
3683 11:48:02.669087 RX DQ/DQS(Engine): PASS
3684 11:48:02.672434 TX OE : NO K
3685 11:48:02.672844 All Pass.
3686 11:48:02.673166
3687 11:48:02.673464 CH 0, Rank 1
3688 11:48:02.676055 SW Impedance : PASS
3689 11:48:02.679142 DUTY Scan : NO K
3690 11:48:02.679549 ZQ Calibration : PASS
3691 11:48:02.682551 Jitter Meter : NO K
3692 11:48:02.682981 CBT Training : PASS
3693 11:48:02.685773 Write leveling : PASS
3694 11:48:02.689170 RX DQS gating : PASS
3695 11:48:02.689784 RX DQ/DQS(RDDQC) : PASS
3696 11:48:02.692712 TX DQ/DQS : PASS
3697 11:48:02.695613 RX DATLAT : PASS
3698 11:48:02.696016 RX DQ/DQS(Engine): PASS
3699 11:48:02.698961 TX OE : NO K
3700 11:48:02.699406 All Pass.
3701 11:48:02.699728
3702 11:48:02.702466 CH 1, Rank 0
3703 11:48:02.702985 SW Impedance : PASS
3704 11:48:02.705962 DUTY Scan : NO K
3705 11:48:02.708845 ZQ Calibration : PASS
3706 11:48:02.709419 Jitter Meter : NO K
3707 11:48:02.712129 CBT Training : PASS
3708 11:48:02.715652 Write leveling : PASS
3709 11:48:02.716076 RX DQS gating : PASS
3710 11:48:02.719134 RX DQ/DQS(RDDQC) : PASS
3711 11:48:02.722350 TX DQ/DQS : PASS
3712 11:48:02.722740 RX DATLAT : PASS
3713 11:48:02.725524 RX DQ/DQS(Engine): PASS
3714 11:48:02.729172 TX OE : NO K
3715 11:48:02.729581 All Pass.
3716 11:48:02.729903
3717 11:48:02.730202 CH 1, Rank 1
3718 11:48:02.732098 SW Impedance : PASS
3719 11:48:02.735515 DUTY Scan : NO K
3720 11:48:02.735952 ZQ Calibration : PASS
3721 11:48:02.738924 Jitter Meter : NO K
3722 11:48:02.741766 CBT Training : PASS
3723 11:48:02.742216 Write leveling : PASS
3724 11:48:02.745302 RX DQS gating : PASS
3725 11:48:02.745719 RX DQ/DQS(RDDQC) : PASS
3726 11:48:02.748704 TX DQ/DQS : PASS
3727 11:48:02.752103 RX DATLAT : PASS
3728 11:48:02.752558 RX DQ/DQS(Engine): PASS
3729 11:48:02.755102 TX OE : NO K
3730 11:48:02.755526 All Pass.
3731 11:48:02.755951
3732 11:48:02.758780 DramC Write-DBI off
3733 11:48:02.761625 PER_BANK_REFRESH: Hybrid Mode
3734 11:48:02.762052 TX_TRACKING: ON
3735 11:48:02.771829 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3736 11:48:02.774882 [FAST_K] Save calibration result to emmc
3737 11:48:02.778596 dramc_set_vcore_voltage set vcore to 650000
3738 11:48:02.781641 Read voltage for 600, 5
3739 11:48:02.782067 Vio18 = 0
3740 11:48:02.785046 Vcore = 650000
3741 11:48:02.785481 Vdram = 0
3742 11:48:02.785911 Vddq = 0
3743 11:48:02.786328 Vmddr = 0
3744 11:48:02.791595 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3745 11:48:02.798165 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3746 11:48:02.798591 MEM_TYPE=3, freq_sel=19
3747 11:48:02.801653 sv_algorithm_assistance_LP4_1600
3748 11:48:02.805074 ============ PULL DRAM RESETB DOWN ============
3749 11:48:02.811363 ========== PULL DRAM RESETB DOWN end =========
3750 11:48:02.814824 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3751 11:48:02.817773 ===================================
3752 11:48:02.821302 LPDDR4 DRAM CONFIGURATION
3753 11:48:02.824848 ===================================
3754 11:48:02.825330 EX_ROW_EN[0] = 0x0
3755 11:48:02.828156 EX_ROW_EN[1] = 0x0
3756 11:48:02.828735 LP4Y_EN = 0x0
3757 11:48:02.831380 WORK_FSP = 0x0
3758 11:48:02.831821 WL = 0x2
3759 11:48:02.834664 RL = 0x2
3760 11:48:02.838342 BL = 0x2
3761 11:48:02.838806 RPST = 0x0
3762 11:48:02.841256 RD_PRE = 0x0
3763 11:48:02.841871 WR_PRE = 0x1
3764 11:48:02.844605 WR_PST = 0x0
3765 11:48:02.845046 DBI_WR = 0x0
3766 11:48:02.848026 DBI_RD = 0x0
3767 11:48:02.848565 OTF = 0x1
3768 11:48:02.851463 ===================================
3769 11:48:02.854265 ===================================
3770 11:48:02.857703 ANA top config
3771 11:48:02.861290 ===================================
3772 11:48:02.861853 DLL_ASYNC_EN = 0
3773 11:48:02.864645 ALL_SLAVE_EN = 1
3774 11:48:02.867517 NEW_RANK_MODE = 1
3775 11:48:02.870938 DLL_IDLE_MODE = 1
3776 11:48:02.871345 LP45_APHY_COMB_EN = 1
3777 11:48:02.874511 TX_ODT_DIS = 1
3778 11:48:02.877541 NEW_8X_MODE = 1
3779 11:48:02.881321 ===================================
3780 11:48:02.884497 ===================================
3781 11:48:02.887534 data_rate = 1200
3782 11:48:02.890769 CKR = 1
3783 11:48:02.894235 DQ_P2S_RATIO = 8
3784 11:48:02.897162 ===================================
3785 11:48:02.897585 CA_P2S_RATIO = 8
3786 11:48:02.900475 DQ_CA_OPEN = 0
3787 11:48:02.903804 DQ_SEMI_OPEN = 0
3788 11:48:02.907392 CA_SEMI_OPEN = 0
3789 11:48:02.910477 CA_FULL_RATE = 0
3790 11:48:02.913975 DQ_CKDIV4_EN = 1
3791 11:48:02.914446 CA_CKDIV4_EN = 1
3792 11:48:02.917410 CA_PREDIV_EN = 0
3793 11:48:02.920812 PH8_DLY = 0
3794 11:48:02.924171 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3795 11:48:02.927204 DQ_AAMCK_DIV = 4
3796 11:48:02.930828 CA_AAMCK_DIV = 4
3797 11:48:02.931309 CA_ADMCK_DIV = 4
3798 11:48:02.934256 DQ_TRACK_CA_EN = 0
3799 11:48:02.936928 CA_PICK = 600
3800 11:48:02.940569 CA_MCKIO = 600
3801 11:48:02.943434 MCKIO_SEMI = 0
3802 11:48:02.947002 PLL_FREQ = 2288
3803 11:48:02.950352 DQ_UI_PI_RATIO = 32
3804 11:48:02.950432 CA_UI_PI_RATIO = 0
3805 11:48:02.953780 ===================================
3806 11:48:02.956580 ===================================
3807 11:48:02.959830 memory_type:LPDDR4
3808 11:48:02.963219 GP_NUM : 10
3809 11:48:02.963300 SRAM_EN : 1
3810 11:48:02.966723 MD32_EN : 0
3811 11:48:02.970221 ===================================
3812 11:48:02.973526 [ANA_INIT] >>>>>>>>>>>>>>
3813 11:48:02.976361 <<<<<< [CONFIGURE PHASE]: ANA_TX
3814 11:48:02.979924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3815 11:48:02.983387 ===================================
3816 11:48:02.983468 data_rate = 1200,PCW = 0X5800
3817 11:48:02.986403 ===================================
3818 11:48:02.989903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3819 11:48:02.996275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 11:48:03.002878 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 11:48:03.006204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3822 11:48:03.009607 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3823 11:48:03.013121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3824 11:48:03.015929 [ANA_INIT] flow start
3825 11:48:03.019629 [ANA_INIT] PLL >>>>>>>>
3826 11:48:03.019711 [ANA_INIT] PLL <<<<<<<<
3827 11:48:03.022648 [ANA_INIT] MIDPI >>>>>>>>
3828 11:48:03.026206 [ANA_INIT] MIDPI <<<<<<<<
3829 11:48:03.026288 [ANA_INIT] DLL >>>>>>>>
3830 11:48:03.029152 [ANA_INIT] flow end
3831 11:48:03.032680 ============ LP4 DIFF to SE enter ============
3832 11:48:03.036192 ============ LP4 DIFF to SE exit ============
3833 11:48:03.039118 [ANA_INIT] <<<<<<<<<<<<<
3834 11:48:03.042619 [Flow] Enable top DCM control >>>>>
3835 11:48:03.045942 [Flow] Enable top DCM control <<<<<
3836 11:48:03.049092 Enable DLL master slave shuffle
3837 11:48:03.055917 ==============================================================
3838 11:48:03.055999 Gating Mode config
3839 11:48:03.062313 ==============================================================
3840 11:48:03.062395 Config description:
3841 11:48:03.072501 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3842 11:48:03.078783 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3843 11:48:03.086057 SELPH_MODE 0: By rank 1: By Phase
3844 11:48:03.088748 ==============================================================
3845 11:48:03.092140 GAT_TRACK_EN = 1
3846 11:48:03.095831 RX_GATING_MODE = 2
3847 11:48:03.099117 RX_GATING_TRACK_MODE = 2
3848 11:48:03.102380 SELPH_MODE = 1
3849 11:48:03.105810 PICG_EARLY_EN = 1
3850 11:48:03.109155 VALID_LAT_VALUE = 1
3851 11:48:03.115513 ==============================================================
3852 11:48:03.119052 Enter into Gating configuration >>>>
3853 11:48:03.122053 Exit from Gating configuration <<<<
3854 11:48:03.125578 Enter into DVFS_PRE_config >>>>>
3855 11:48:03.135638 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3856 11:48:03.138660 Exit from DVFS_PRE_config <<<<<
3857 11:48:03.141851 Enter into PICG configuration >>>>
3858 11:48:03.145456 Exit from PICG configuration <<<<
3859 11:48:03.148844 [RX_INPUT] configuration >>>>>
3860 11:48:03.148930 [RX_INPUT] configuration <<<<<
3861 11:48:03.155114 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3862 11:48:03.161985 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3863 11:48:03.165241 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3864 11:48:03.171887 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3865 11:48:03.178527 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 11:48:03.185425 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 11:48:03.188150 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3868 11:48:03.191945 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3869 11:48:03.198559 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3870 11:48:03.201525 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3871 11:48:03.204944 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3872 11:48:03.211902 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 11:48:03.215104 ===================================
3874 11:48:03.215236 LPDDR4 DRAM CONFIGURATION
3875 11:48:03.218590 ===================================
3876 11:48:03.221976 EX_ROW_EN[0] = 0x0
3877 11:48:03.222123 EX_ROW_EN[1] = 0x0
3878 11:48:03.225245 LP4Y_EN = 0x0
3879 11:48:03.225497 WORK_FSP = 0x0
3880 11:48:03.228872 WL = 0x2
3881 11:48:03.232346 RL = 0x2
3882 11:48:03.232622 BL = 0x2
3883 11:48:03.235337 RPST = 0x0
3884 11:48:03.235655 RD_PRE = 0x0
3885 11:48:03.238906 WR_PRE = 0x1
3886 11:48:03.239231 WR_PST = 0x0
3887 11:48:03.242433 DBI_WR = 0x0
3888 11:48:03.242819 DBI_RD = 0x0
3889 11:48:03.245915 OTF = 0x1
3890 11:48:03.249144 ===================================
3891 11:48:03.252546 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3892 11:48:03.255462 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3893 11:48:03.258702 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 11:48:03.262431 ===================================
3895 11:48:03.265704 LPDDR4 DRAM CONFIGURATION
3896 11:48:03.269087 ===================================
3897 11:48:03.272336 EX_ROW_EN[0] = 0x10
3898 11:48:03.272793 EX_ROW_EN[1] = 0x0
3899 11:48:03.275621 LP4Y_EN = 0x0
3900 11:48:03.276075 WORK_FSP = 0x0
3901 11:48:03.278797 WL = 0x2
3902 11:48:03.279248 RL = 0x2
3903 11:48:03.281949 BL = 0x2
3904 11:48:03.282406 RPST = 0x0
3905 11:48:03.285323 RD_PRE = 0x0
3906 11:48:03.288789 WR_PRE = 0x1
3907 11:48:03.289245 WR_PST = 0x0
3908 11:48:03.291700 DBI_WR = 0x0
3909 11:48:03.292153 DBI_RD = 0x0
3910 11:48:03.295477 OTF = 0x1
3911 11:48:03.298237 ===================================
3912 11:48:03.301890 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3913 11:48:03.306966 nWR fixed to 30
3914 11:48:03.310549 [ModeRegInit_LP4] CH0 RK0
3915 11:48:03.311038 [ModeRegInit_LP4] CH0 RK1
3916 11:48:03.313989 [ModeRegInit_LP4] CH1 RK0
3917 11:48:03.317285 [ModeRegInit_LP4] CH1 RK1
3918 11:48:03.317740 match AC timing 17
3919 11:48:03.323859 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3920 11:48:03.327380 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3921 11:48:03.330275 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3922 11:48:03.336696 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3923 11:48:03.340079 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3924 11:48:03.340621 ==
3925 11:48:03.343686 Dram Type= 6, Freq= 0, CH_0, rank 0
3926 11:48:03.346627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 11:48:03.347086 ==
3928 11:48:03.353502 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 11:48:03.360363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3930 11:48:03.363626 [CA 0] Center 37 (7~67) winsize 61
3931 11:48:03.366629 [CA 1] Center 37 (7~67) winsize 61
3932 11:48:03.370191 [CA 2] Center 35 (5~65) winsize 61
3933 11:48:03.373306 [CA 3] Center 35 (5~65) winsize 61
3934 11:48:03.376798 [CA 4] Center 34 (4~65) winsize 62
3935 11:48:03.380018 [CA 5] Center 34 (4~65) winsize 62
3936 11:48:03.380535
3937 11:48:03.382953 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3938 11:48:03.383393
3939 11:48:03.386357 [CATrainingPosCal] consider 1 rank data
3940 11:48:03.389566 u2DelayCellTimex100 = 270/100 ps
3941 11:48:03.392904 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3942 11:48:03.396559 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3943 11:48:03.400002 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3944 11:48:03.403082 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3945 11:48:03.406484 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3946 11:48:03.412859 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
3947 11:48:03.413319
3948 11:48:03.416369 CA PerBit enable=1, Macro0, CA PI delay=34
3949 11:48:03.416834
3950 11:48:03.419882 [CBTSetCACLKResult] CA Dly = 34
3951 11:48:03.420383 CS Dly: 4 (0~35)
3952 11:48:03.420755 ==
3953 11:48:03.423322 Dram Type= 6, Freq= 0, CH_0, rank 1
3954 11:48:03.426569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 11:48:03.429549 ==
3956 11:48:03.433065 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 11:48:03.439437 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3958 11:48:03.442875 [CA 0] Center 37 (7~67) winsize 61
3959 11:48:03.446464 [CA 1] Center 37 (7~67) winsize 61
3960 11:48:03.449919 [CA 2] Center 35 (5~65) winsize 61
3961 11:48:03.452757 [CA 3] Center 35 (5~65) winsize 61
3962 11:48:03.456170 [CA 4] Center 34 (4~65) winsize 62
3963 11:48:03.459612 [CA 5] Center 33 (3~64) winsize 62
3964 11:48:03.460028
3965 11:48:03.462564 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3966 11:48:03.463003
3967 11:48:03.466120 [CATrainingPosCal] consider 2 rank data
3968 11:48:03.469544 u2DelayCellTimex100 = 270/100 ps
3969 11:48:03.472992 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3970 11:48:03.476443 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3971 11:48:03.479579 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3972 11:48:03.486022 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3973 11:48:03.489268 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3974 11:48:03.492681 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3975 11:48:03.493256
3976 11:48:03.496167 CA PerBit enable=1, Macro0, CA PI delay=34
3977 11:48:03.496682
3978 11:48:03.499619 [CBTSetCACLKResult] CA Dly = 34
3979 11:48:03.500080 CS Dly: 4 (0~36)
3980 11:48:03.500524
3981 11:48:03.502404 ----->DramcWriteLeveling(PI) begin...
3982 11:48:03.502882 ==
3983 11:48:03.506209 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 11:48:03.512689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 11:48:03.513150 ==
3986 11:48:03.516015 Write leveling (Byte 0): 33 => 33
3987 11:48:03.519724 Write leveling (Byte 1): 32 => 32
3988 11:48:03.520469 DramcWriteLeveling(PI) end<-----
3989 11:48:03.520909
3990 11:48:03.523049 ==
3991 11:48:03.526169 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 11:48:03.529341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 11:48:03.529807 ==
3994 11:48:03.532804 [Gating] SW mode calibration
3995 11:48:03.539193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3996 11:48:03.542599 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3997 11:48:03.549383 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 11:48:03.552359 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 11:48:03.555686 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 11:48:03.562801 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 11:48:03.565602 0 9 16 | B1->B0 | 3232 2e2e | 0 1 | (0 0) (1 0)
4002 11:48:03.569191 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 11:48:03.575766 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 11:48:03.579164 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 11:48:03.582275 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 11:48:03.588699 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 11:48:03.592081 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 11:48:03.595322 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4009 11:48:03.602033 0 10 16 | B1->B0 | 3030 3a3a | 0 1 | (0 0) (0 0)
4010 11:48:03.605554 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 11:48:03.608612 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 11:48:03.615795 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 11:48:03.618581 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 11:48:03.621894 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 11:48:03.628645 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 11:48:03.632400 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4017 11:48:03.635198 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4018 11:48:03.642137 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 11:48:03.645514 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 11:48:03.648675 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 11:48:03.655612 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 11:48:03.658991 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 11:48:03.661888 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 11:48:03.668269 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 11:48:03.671890 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 11:48:03.675508 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 11:48:03.681913 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 11:48:03.685259 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 11:48:03.688170 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 11:48:03.691759 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 11:48:03.698143 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 11:48:03.701747 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 11:48:03.704874 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 11:48:03.708284 Total UI for P1: 0, mck2ui 16
4035 11:48:03.711566 best dqsien dly found for B0: ( 0, 13, 14)
4036 11:48:03.714899 Total UI for P1: 0, mck2ui 16
4037 11:48:03.718055 best dqsien dly found for B1: ( 0, 13, 14)
4038 11:48:03.721300 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4039 11:48:03.728377 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4040 11:48:03.728841
4041 11:48:03.731204 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4042 11:48:03.734555 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4043 11:48:03.737673 [Gating] SW calibration Done
4044 11:48:03.738307 ==
4045 11:48:03.741372 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 11:48:03.744048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 11:48:03.744129 ==
4048 11:48:03.747459 RX Vref Scan: 0
4049 11:48:03.747540
4050 11:48:03.747604 RX Vref 0 -> 0, step: 1
4051 11:48:03.747663
4052 11:48:03.750728 RX Delay -230 -> 252, step: 16
4053 11:48:03.754258 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4054 11:48:03.760630 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4055 11:48:03.763944 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4056 11:48:03.767456 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4057 11:48:03.771038 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4058 11:48:03.777693 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4059 11:48:03.781032 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4060 11:48:03.784073 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4061 11:48:03.787638 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4062 11:48:03.790711 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4063 11:48:03.797189 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4064 11:48:03.800638 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4065 11:48:03.804257 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4066 11:48:03.807686 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4067 11:48:03.813995 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4068 11:48:03.817469 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4069 11:48:03.817777 ==
4070 11:48:03.820532 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 11:48:03.824105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 11:48:03.824575 ==
4073 11:48:03.827552 DQS Delay:
4074 11:48:03.827935 DQS0 = 0, DQS1 = 0
4075 11:48:03.828404 DQM Delay:
4076 11:48:03.830557 DQM0 = 36, DQM1 = 26
4077 11:48:03.831015 DQ Delay:
4078 11:48:03.834143 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4079 11:48:03.837401 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4080 11:48:03.840837 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =17
4081 11:48:03.843733 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4082 11:48:03.844150
4083 11:48:03.844700
4084 11:48:03.845029 ==
4085 11:48:03.847166 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 11:48:03.853824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 11:48:03.854243 ==
4088 11:48:03.854573
4089 11:48:03.854877
4090 11:48:03.855196 TX Vref Scan disable
4091 11:48:03.857526 == TX Byte 0 ==
4092 11:48:03.860727 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4093 11:48:03.867413 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4094 11:48:03.867833 == TX Byte 1 ==
4095 11:48:03.870742 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4096 11:48:03.877521 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4097 11:48:03.877941 ==
4098 11:48:03.880943 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 11:48:03.883905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 11:48:03.884382 ==
4101 11:48:03.884722
4102 11:48:03.885030
4103 11:48:03.887427 TX Vref Scan disable
4104 11:48:03.890875 == TX Byte 0 ==
4105 11:48:03.894442 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4106 11:48:03.897304 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4107 11:48:03.900775 == TX Byte 1 ==
4108 11:48:03.903720 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4109 11:48:03.907265 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4110 11:48:03.907686
4111 11:48:03.908023 [DATLAT]
4112 11:48:03.910657 Freq=600, CH0 RK0
4113 11:48:03.911075
4114 11:48:03.913951 DATLAT Default: 0x9
4115 11:48:03.914371 0, 0xFFFF, sum = 0
4116 11:48:03.917466 1, 0xFFFF, sum = 0
4117 11:48:03.917950 2, 0xFFFF, sum = 0
4118 11:48:03.920672 3, 0xFFFF, sum = 0
4119 11:48:03.921095 4, 0xFFFF, sum = 0
4120 11:48:03.924113 5, 0xFFFF, sum = 0
4121 11:48:03.924583 6, 0xFFFF, sum = 0
4122 11:48:03.927123 7, 0xFFFF, sum = 0
4123 11:48:03.927547 8, 0x0, sum = 1
4124 11:48:03.930597 9, 0x0, sum = 2
4125 11:48:03.931020 10, 0x0, sum = 3
4126 11:48:03.933633 11, 0x0, sum = 4
4127 11:48:03.934053 best_step = 9
4128 11:48:03.934390
4129 11:48:03.934757 ==
4130 11:48:03.937104 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 11:48:03.940315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 11:48:03.940739 ==
4133 11:48:03.943474 RX Vref Scan: 1
4134 11:48:03.943894
4135 11:48:03.947162 RX Vref 0 -> 0, step: 1
4136 11:48:03.947581
4137 11:48:03.947914 RX Delay -195 -> 252, step: 8
4138 11:48:03.948265
4139 11:48:03.950254 Set Vref, RX VrefLevel [Byte0]: 61
4140 11:48:03.953782 [Byte1]: 52
4141 11:48:03.958211
4142 11:48:03.958626 Final RX Vref Byte 0 = 61 to rank0
4143 11:48:03.961526 Final RX Vref Byte 1 = 52 to rank0
4144 11:48:03.964878 Final RX Vref Byte 0 = 61 to rank1
4145 11:48:03.968087 Final RX Vref Byte 1 = 52 to rank1==
4146 11:48:03.971170 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 11:48:03.977827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 11:48:03.978248 ==
4149 11:48:03.978576 DQS Delay:
4150 11:48:03.978883 DQS0 = 0, DQS1 = 0
4151 11:48:03.981484 DQM Delay:
4152 11:48:03.981900 DQM0 = 35, DQM1 = 28
4153 11:48:03.985058 DQ Delay:
4154 11:48:03.988058 DQ0 =36, DQ1 =40, DQ2 =32, DQ3 =32
4155 11:48:03.988503 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =48
4156 11:48:03.991468 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4157 11:48:03.994930 DQ12 =32, DQ13 =36, DQ14 =40, DQ15 =36
4158 11:48:03.998423
4159 11:48:03.998839
4160 11:48:04.004845 [DQSOSCAuto] RK0, (LSB)MR18= 0x4140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4161 11:48:04.008393 CH0 RK0: MR19=808, MR18=4140
4162 11:48:04.014716 CH0_RK0: MR19=0x808, MR18=0x4140, DQSOSC=397, MR23=63, INC=166, DEC=110
4163 11:48:04.015138
4164 11:48:04.018084 ----->DramcWriteLeveling(PI) begin...
4165 11:48:04.018507 ==
4166 11:48:04.021652 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 11:48:04.024564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 11:48:04.024984 ==
4169 11:48:04.027967 Write leveling (Byte 0): 34 => 34
4170 11:48:04.031359 Write leveling (Byte 1): 33 => 33
4171 11:48:04.034986 DramcWriteLeveling(PI) end<-----
4172 11:48:04.035405
4173 11:48:04.035738 ==
4174 11:48:04.037940 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 11:48:04.041830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 11:48:04.042362 ==
4177 11:48:04.044589 [Gating] SW mode calibration
4178 11:48:04.051560 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4179 11:48:04.057583 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4180 11:48:04.061186 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 11:48:04.067646 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 11:48:04.071145 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 11:48:04.074135 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
4184 11:48:04.081063 0 9 16 | B1->B0 | 2e2e 2525 | 1 0 | (1 1) (0 0)
4185 11:48:04.084161 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 11:48:04.087294 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 11:48:04.093863 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 11:48:04.097617 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 11:48:04.100553 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 11:48:04.103950 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 11:48:04.110800 0 10 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
4192 11:48:04.114219 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4193 11:48:04.117188 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 11:48:04.124012 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 11:48:04.127306 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 11:48:04.130075 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 11:48:04.136711 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 11:48:04.140115 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 11:48:04.143734 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4200 11:48:04.150033 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 11:48:04.153606 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 11:48:04.156408 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 11:48:04.163490 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 11:48:04.166754 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 11:48:04.170306 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 11:48:04.176600 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 11:48:04.180084 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 11:48:04.183045 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 11:48:04.189845 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 11:48:04.193559 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 11:48:04.196211 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 11:48:04.203071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 11:48:04.206306 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 11:48:04.209913 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4215 11:48:04.216149 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 11:48:04.219644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4217 11:48:04.222886 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 11:48:04.226263 Total UI for P1: 0, mck2ui 16
4219 11:48:04.229812 best dqsien dly found for B0: ( 0, 13, 16)
4220 11:48:04.232566 Total UI for P1: 0, mck2ui 16
4221 11:48:04.236067 best dqsien dly found for B1: ( 0, 13, 16)
4222 11:48:04.239436 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4223 11:48:04.242946 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4224 11:48:04.243082
4225 11:48:04.249491 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4226 11:48:04.252558 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4227 11:48:04.256103 [Gating] SW calibration Done
4228 11:48:04.256339 ==
4229 11:48:04.259169 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 11:48:04.262650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 11:48:04.262823 ==
4232 11:48:04.262959 RX Vref Scan: 0
4233 11:48:04.263090
4234 11:48:04.266217 RX Vref 0 -> 0, step: 1
4235 11:48:04.266417
4236 11:48:04.269562 RX Delay -230 -> 252, step: 16
4237 11:48:04.272751 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4238 11:48:04.276030 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4239 11:48:04.282697 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4240 11:48:04.286275 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4241 11:48:04.289799 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4242 11:48:04.292811 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4243 11:48:04.299533 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4244 11:48:04.303115 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4245 11:48:04.306404 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4246 11:48:04.309630 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4247 11:48:04.316141 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4248 11:48:04.319480 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4249 11:48:04.322706 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4250 11:48:04.325805 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4251 11:48:04.332703 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4252 11:48:04.335998 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4253 11:48:04.336586 ==
4254 11:48:04.339231 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 11:48:04.342654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 11:48:04.343262 ==
4257 11:48:04.343721 DQS Delay:
4258 11:48:04.345644 DQS0 = 0, DQS1 = 0
4259 11:48:04.346203 DQM Delay:
4260 11:48:04.349269 DQM0 = 35, DQM1 = 28
4261 11:48:04.349776 DQ Delay:
4262 11:48:04.352733 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4263 11:48:04.355655 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4264 11:48:04.359062 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4265 11:48:04.362058 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4266 11:48:04.362614
4267 11:48:04.363080
4268 11:48:04.363569 ==
4269 11:48:04.365580 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 11:48:04.369187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 11:48:04.372071 ==
4272 11:48:04.372539
4273 11:48:04.372871
4274 11:48:04.373180 TX Vref Scan disable
4275 11:48:04.375556 == TX Byte 0 ==
4276 11:48:04.378988 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4277 11:48:04.386077 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4278 11:48:04.386592 == TX Byte 1 ==
4279 11:48:04.388979 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4280 11:48:04.395156 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4281 11:48:04.395578 ==
4282 11:48:04.398637 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 11:48:04.402210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 11:48:04.402630 ==
4285 11:48:04.402960
4286 11:48:04.403265
4287 11:48:04.405623 TX Vref Scan disable
4288 11:48:04.408576 == TX Byte 0 ==
4289 11:48:04.412116 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4290 11:48:04.415329 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4291 11:48:04.418340 == TX Byte 1 ==
4292 11:48:04.421741 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4293 11:48:04.425097 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4294 11:48:04.425511
4295 11:48:04.425838 [DATLAT]
4296 11:48:04.428467 Freq=600, CH0 RK1
4297 11:48:04.428880
4298 11:48:04.431806 DATLAT Default: 0x9
4299 11:48:04.432387 0, 0xFFFF, sum = 0
4300 11:48:04.434836 1, 0xFFFF, sum = 0
4301 11:48:04.435256 2, 0xFFFF, sum = 0
4302 11:48:04.438101 3, 0xFFFF, sum = 0
4303 11:48:04.438400 4, 0xFFFF, sum = 0
4304 11:48:04.441363 5, 0xFFFF, sum = 0
4305 11:48:04.441664 6, 0xFFFF, sum = 0
4306 11:48:04.445261 7, 0xFFFF, sum = 0
4307 11:48:04.445570 8, 0x0, sum = 1
4308 11:48:04.447981 9, 0x0, sum = 2
4309 11:48:04.448432 10, 0x0, sum = 3
4310 11:48:04.451237 11, 0x0, sum = 4
4311 11:48:04.451464 best_step = 9
4312 11:48:04.451640
4313 11:48:04.451805 ==
4314 11:48:04.454534 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 11:48:04.458079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 11:48:04.458262 ==
4317 11:48:04.461079 RX Vref Scan: 0
4318 11:48:04.461318
4319 11:48:04.464764 RX Vref 0 -> 0, step: 1
4320 11:48:04.464943
4321 11:48:04.465085 RX Delay -195 -> 252, step: 8
4322 11:48:04.472541 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4323 11:48:04.476053 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4324 11:48:04.479584 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4325 11:48:04.482482 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4326 11:48:04.488963 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4327 11:48:04.492468 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4328 11:48:04.495659 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4329 11:48:04.499243 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4330 11:48:04.502812 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4331 11:48:04.509048 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4332 11:48:04.512329 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4333 11:48:04.516028 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4334 11:48:04.519330 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4335 11:48:04.526198 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4336 11:48:04.529258 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4337 11:48:04.532611 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4338 11:48:04.533122 ==
4339 11:48:04.535996 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 11:48:04.538953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 11:48:04.542744 ==
4342 11:48:04.543161 DQS Delay:
4343 11:48:04.543490 DQS0 = 0, DQS1 = 0
4344 11:48:04.545857 DQM Delay:
4345 11:48:04.546273 DQM0 = 34, DQM1 = 28
4346 11:48:04.548860 DQ Delay:
4347 11:48:04.549276 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4348 11:48:04.552375 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4349 11:48:04.555632 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4350 11:48:04.559188 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4351 11:48:04.559604
4352 11:48:04.562187
4353 11:48:04.569319 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4354 11:48:04.572196 CH0 RK1: MR19=808, MR18=6B3A
4355 11:48:04.578857 CH0_RK1: MR19=0x808, MR18=0x6B3A, DQSOSC=389, MR23=63, INC=173, DEC=115
4356 11:48:04.582438 [RxdqsGatingPostProcess] freq 600
4357 11:48:04.585429 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4358 11:48:04.589028 Pre-setting of DQS Precalculation
4359 11:48:04.595328 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4360 11:48:04.595763 ==
4361 11:48:04.599098 Dram Type= 6, Freq= 0, CH_1, rank 0
4362 11:48:04.602674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 11:48:04.603201 ==
4364 11:48:04.608780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4365 11:48:04.611690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4366 11:48:04.616533 [CA 0] Center 36 (6~66) winsize 61
4367 11:48:04.619530 [CA 1] Center 35 (5~66) winsize 62
4368 11:48:04.622769 [CA 2] Center 34 (4~65) winsize 62
4369 11:48:04.626403 [CA 3] Center 34 (4~65) winsize 62
4370 11:48:04.629930 [CA 4] Center 34 (4~65) winsize 62
4371 11:48:04.633245 [CA 5] Center 33 (3~64) winsize 62
4372 11:48:04.633987
4373 11:48:04.636339 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4374 11:48:04.636805
4375 11:48:04.639733 [CATrainingPosCal] consider 1 rank data
4376 11:48:04.642787 u2DelayCellTimex100 = 270/100 ps
4377 11:48:04.646177 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4378 11:48:04.652324 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4379 11:48:04.656081 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4380 11:48:04.658925 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 11:48:04.662561 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 11:48:04.666020 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 11:48:04.666485
4384 11:48:04.669688 CA PerBit enable=1, Macro0, CA PI delay=33
4385 11:48:04.670249
4386 11:48:04.672595 [CBTSetCACLKResult] CA Dly = 33
4387 11:48:04.673079 CS Dly: 4 (0~35)
4388 11:48:04.675763 ==
4389 11:48:04.679217 Dram Type= 6, Freq= 0, CH_1, rank 1
4390 11:48:04.683072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 11:48:04.683646 ==
4392 11:48:04.685889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4393 11:48:04.692290 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4394 11:48:04.696656 [CA 0] Center 36 (6~66) winsize 61
4395 11:48:04.699627 [CA 1] Center 36 (6~67) winsize 62
4396 11:48:04.703124 [CA 2] Center 34 (4~65) winsize 62
4397 11:48:04.706443 [CA 3] Center 34 (3~65) winsize 63
4398 11:48:04.709961 [CA 4] Center 34 (4~65) winsize 62
4399 11:48:04.712796 [CA 5] Center 34 (3~65) winsize 63
4400 11:48:04.713259
4401 11:48:04.716416 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4402 11:48:04.716976
4403 11:48:04.719986 [CATrainingPosCal] consider 2 rank data
4404 11:48:04.723142 u2DelayCellTimex100 = 270/100 ps
4405 11:48:04.726859 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4406 11:48:04.729822 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4407 11:48:04.736511 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4408 11:48:04.739714 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 11:48:04.742849 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 11:48:04.746443 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 11:48:04.746909
4412 11:48:04.749342 CA PerBit enable=1, Macro0, CA PI delay=33
4413 11:48:04.749807
4414 11:48:04.752766 [CBTSetCACLKResult] CA Dly = 33
4415 11:48:04.753228 CS Dly: 4 (0~36)
4416 11:48:04.756102
4417 11:48:04.759262 ----->DramcWriteLeveling(PI) begin...
4418 11:48:04.759896 ==
4419 11:48:04.762392 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 11:48:04.766046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 11:48:04.766685 ==
4422 11:48:04.769237 Write leveling (Byte 0): 28 => 28
4423 11:48:04.772794 Write leveling (Byte 1): 31 => 31
4424 11:48:04.775747 DramcWriteLeveling(PI) end<-----
4425 11:48:04.776164
4426 11:48:04.776535 ==
4427 11:48:04.779511 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 11:48:04.782748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 11:48:04.783276 ==
4430 11:48:04.786050 [Gating] SW mode calibration
4431 11:48:04.792395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4432 11:48:04.799063 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4433 11:48:04.802453 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 11:48:04.805936 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 11:48:04.812459 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 11:48:04.815558 0 9 12 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0)
4437 11:48:04.819026 0 9 16 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0)
4438 11:48:04.826282 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 11:48:04.828790 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 11:48:04.832639 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 11:48:04.839634 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 11:48:04.842891 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 11:48:04.845798 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 11:48:04.852004 0 10 12 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
4445 11:48:04.855373 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4446 11:48:04.858875 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 11:48:04.862309 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 11:48:04.868734 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 11:48:04.871886 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 11:48:04.875741 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 11:48:04.882427 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 11:48:04.885317 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4453 11:48:04.888818 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4454 11:48:04.895557 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 11:48:04.898645 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 11:48:04.901794 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 11:48:04.908566 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 11:48:04.912051 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 11:48:04.915504 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 11:48:04.921717 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 11:48:04.925464 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 11:48:04.928253 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 11:48:04.935218 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 11:48:04.938469 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 11:48:04.941745 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 11:48:04.948660 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 11:48:04.951812 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 11:48:04.955066 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4469 11:48:04.957987 Total UI for P1: 0, mck2ui 16
4470 11:48:04.961824 best dqsien dly found for B0: ( 0, 13, 10)
4471 11:48:04.968505 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 11:48:04.969079 Total UI for P1: 0, mck2ui 16
4473 11:48:04.974859 best dqsien dly found for B1: ( 0, 13, 12)
4474 11:48:04.977797 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4475 11:48:04.981480 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4476 11:48:04.981900
4477 11:48:04.984456 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4478 11:48:04.988093 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4479 11:48:04.991332 [Gating] SW calibration Done
4480 11:48:04.991886 ==
4481 11:48:04.994388 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 11:48:04.998049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 11:48:04.998621 ==
4484 11:48:05.001196 RX Vref Scan: 0
4485 11:48:05.001607
4486 11:48:05.001964 RX Vref 0 -> 0, step: 1
4487 11:48:05.004613
4488 11:48:05.005039 RX Delay -230 -> 252, step: 16
4489 11:48:05.010636 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4490 11:48:05.014020 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4491 11:48:05.017744 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4492 11:48:05.021135 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4493 11:48:05.027583 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4494 11:48:05.030823 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4495 11:48:05.034425 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4496 11:48:05.037266 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4497 11:48:05.040918 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4498 11:48:05.047527 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4499 11:48:05.050913 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4500 11:48:05.054046 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4501 11:48:05.057214 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4502 11:48:05.064154 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4503 11:48:05.067569 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4504 11:48:05.070563 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4505 11:48:05.070984 ==
4506 11:48:05.074113 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 11:48:05.076951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 11:48:05.080581 ==
4509 11:48:05.081111 DQS Delay:
4510 11:48:05.081453 DQS0 = 0, DQS1 = 0
4511 11:48:05.083995 DQM Delay:
4512 11:48:05.084446 DQM0 = 38, DQM1 = 28
4513 11:48:05.086945 DQ Delay:
4514 11:48:05.087366 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4515 11:48:05.090598 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4516 11:48:05.094173 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4517 11:48:05.097108 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4518 11:48:05.100559
4519 11:48:05.100969
4520 11:48:05.101298 ==
4521 11:48:05.103783 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 11:48:05.106911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 11:48:05.107333 ==
4524 11:48:05.107666
4525 11:48:05.107972
4526 11:48:05.110413 TX Vref Scan disable
4527 11:48:05.110829 == TX Byte 0 ==
4528 11:48:05.117064 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4529 11:48:05.120323 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4530 11:48:05.120823 == TX Byte 1 ==
4531 11:48:05.127151 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4532 11:48:05.130429 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4533 11:48:05.130853 ==
4534 11:48:05.133510 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 11:48:05.137154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 11:48:05.137626 ==
4537 11:48:05.138142
4538 11:48:05.138477
4539 11:48:05.140077 TX Vref Scan disable
4540 11:48:05.143775 == TX Byte 0 ==
4541 11:48:05.146737 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4542 11:48:05.150658 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4543 11:48:05.153807 == TX Byte 1 ==
4544 11:48:05.157160 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4545 11:48:05.160368 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4546 11:48:05.163178
4547 11:48:05.163897 [DATLAT]
4548 11:48:05.164430 Freq=600, CH1 RK0
4549 11:48:05.164871
4550 11:48:05.166397 DATLAT Default: 0x9
4551 11:48:05.166947 0, 0xFFFF, sum = 0
4552 11:48:05.170091 1, 0xFFFF, sum = 0
4553 11:48:05.170514 2, 0xFFFF, sum = 0
4554 11:48:05.172901 3, 0xFFFF, sum = 0
4555 11:48:05.176908 4, 0xFFFF, sum = 0
4556 11:48:05.177330 5, 0xFFFF, sum = 0
4557 11:48:05.179941 6, 0xFFFF, sum = 0
4558 11:48:05.180514 7, 0xFFFF, sum = 0
4559 11:48:05.183384 8, 0x0, sum = 1
4560 11:48:05.183810 9, 0x0, sum = 2
4561 11:48:05.184142 10, 0x0, sum = 3
4562 11:48:05.186453 11, 0x0, sum = 4
4563 11:48:05.186841 best_step = 9
4564 11:48:05.187160
4565 11:48:05.187458 ==
4566 11:48:05.189997 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 11:48:05.196553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 11:48:05.196990 ==
4569 11:48:05.197326 RX Vref Scan: 1
4570 11:48:05.197637
4571 11:48:05.200002 RX Vref 0 -> 0, step: 1
4572 11:48:05.200457
4573 11:48:05.202808 RX Delay -195 -> 252, step: 8
4574 11:48:05.203226
4575 11:48:05.206585 Set Vref, RX VrefLevel [Byte0]: 54
4576 11:48:05.209868 [Byte1]: 51
4577 11:48:05.210288
4578 11:48:05.213247 Final RX Vref Byte 0 = 54 to rank0
4579 11:48:05.216012 Final RX Vref Byte 1 = 51 to rank0
4580 11:48:05.219618 Final RX Vref Byte 0 = 54 to rank1
4581 11:48:05.223180 Final RX Vref Byte 1 = 51 to rank1==
4582 11:48:05.225923 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 11:48:05.229822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 11:48:05.230241 ==
4585 11:48:05.233149 DQS Delay:
4586 11:48:05.233570 DQS0 = 0, DQS1 = 0
4587 11:48:05.235980 DQM Delay:
4588 11:48:05.236559 DQM0 = 38, DQM1 = 28
4589 11:48:05.236899 DQ Delay:
4590 11:48:05.239372 DQ0 =44, DQ1 =28, DQ2 =28, DQ3 =36
4591 11:48:05.242720 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4592 11:48:05.245888 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4593 11:48:05.249231 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4594 11:48:05.249649
4595 11:48:05.249974
4596 11:48:05.259651 [DQSOSCAuto] RK0, (LSB)MR18= 0x202d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4597 11:48:05.262939 CH1 RK0: MR19=808, MR18=202D
4598 11:48:05.269342 CH1_RK0: MR19=0x808, MR18=0x202D, DQSOSC=401, MR23=63, INC=163, DEC=108
4599 11:48:05.269870
4600 11:48:05.272366 ----->DramcWriteLeveling(PI) begin...
4601 11:48:05.272893 ==
4602 11:48:05.275647 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 11:48:05.278779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 11:48:05.279269 ==
4605 11:48:05.282454 Write leveling (Byte 0): 30 => 30
4606 11:48:05.285339 Write leveling (Byte 1): 30 => 30
4607 11:48:05.289274 DramcWriteLeveling(PI) end<-----
4608 11:48:05.289713
4609 11:48:05.290043 ==
4610 11:48:05.292284 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 11:48:05.295718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 11:48:05.296139 ==
4613 11:48:05.298737 [Gating] SW mode calibration
4614 11:48:05.305203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4615 11:48:05.312321 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4616 11:48:05.315222 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4617 11:48:05.318682 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 11:48:05.325086 0 9 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
4619 11:48:05.328583 0 9 12 | B1->B0 | 3333 2929 | 0 0 | (0 1) (1 1)
4620 11:48:05.332162 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4621 11:48:05.338342 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 11:48:05.341666 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 11:48:05.345353 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 11:48:05.352156 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 11:48:05.354951 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 11:48:05.358727 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
4627 11:48:05.364838 0 10 12 | B1->B0 | 3131 3b3b | 1 0 | (0 0) (1 1)
4628 11:48:05.368474 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 11:48:05.371869 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 11:48:05.378468 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 11:48:05.381752 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 11:48:05.384847 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 11:48:05.391372 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 11:48:05.395079 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 11:48:05.397978 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4636 11:48:05.404736 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4637 11:48:05.408159 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 11:48:05.411758 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 11:48:05.418182 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 11:48:05.420937 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 11:48:05.424581 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 11:48:05.431137 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 11:48:05.434676 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 11:48:05.437582 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 11:48:05.444127 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 11:48:05.447451 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 11:48:05.450489 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 11:48:05.457414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 11:48:05.460921 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 11:48:05.464250 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4651 11:48:05.470425 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4652 11:48:05.473981 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 11:48:05.476927 Total UI for P1: 0, mck2ui 16
4654 11:48:05.480427 best dqsien dly found for B0: ( 0, 13, 12)
4655 11:48:05.483963 Total UI for P1: 0, mck2ui 16
4656 11:48:05.487481 best dqsien dly found for B1: ( 0, 13, 14)
4657 11:48:05.490346 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4658 11:48:05.493845 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4659 11:48:05.493957
4660 11:48:05.496806 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4661 11:48:05.500135 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4662 11:48:05.503660 [Gating] SW calibration Done
4663 11:48:05.503778 ==
4664 11:48:05.507206 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 11:48:05.510058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 11:48:05.513810 ==
4667 11:48:05.513961 RX Vref Scan: 0
4668 11:48:05.514081
4669 11:48:05.517346 RX Vref 0 -> 0, step: 1
4670 11:48:05.517497
4671 11:48:05.520227 RX Delay -230 -> 252, step: 16
4672 11:48:05.523734 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4673 11:48:05.527303 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4674 11:48:05.530217 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4675 11:48:05.537019 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4676 11:48:05.540621 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4677 11:48:05.543600 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4678 11:48:05.547101 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4679 11:48:05.550124 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4680 11:48:05.557178 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4681 11:48:05.560174 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4682 11:48:05.563609 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4683 11:48:05.566801 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4684 11:48:05.573535 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4685 11:48:05.577038 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4686 11:48:05.580492 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4687 11:48:05.583762 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4688 11:48:05.584145 ==
4689 11:48:05.587121 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 11:48:05.593350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 11:48:05.593738 ==
4692 11:48:05.594044 DQS Delay:
4693 11:48:05.596927 DQS0 = 0, DQS1 = 0
4694 11:48:05.597313 DQM Delay:
4695 11:48:05.597698 DQM0 = 35, DQM1 = 28
4696 11:48:05.600252 DQ Delay:
4697 11:48:05.603370 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4698 11:48:05.606725 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4699 11:48:05.610009 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4700 11:48:05.613569 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4701 11:48:05.613999
4702 11:48:05.614421
4703 11:48:05.614943 ==
4704 11:48:05.617005 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 11:48:05.620469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 11:48:05.621042 ==
4707 11:48:05.621363
4708 11:48:05.621648
4709 11:48:05.623150 TX Vref Scan disable
4710 11:48:05.623584 == TX Byte 0 ==
4711 11:48:05.630164 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4712 11:48:05.633292 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4713 11:48:05.636773 == TX Byte 1 ==
4714 11:48:05.640190 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4715 11:48:05.643102 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4716 11:48:05.643651 ==
4717 11:48:05.646464 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 11:48:05.650015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 11:48:05.650446 ==
4720 11:48:05.652870
4721 11:48:05.653364
4722 11:48:05.653678 TX Vref Scan disable
4723 11:48:05.656529 == TX Byte 0 ==
4724 11:48:05.660126 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4725 11:48:05.666685 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4726 11:48:05.667198 == TX Byte 1 ==
4727 11:48:05.670104 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4728 11:48:05.676598 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4729 11:48:05.677094
4730 11:48:05.677407 [DATLAT]
4731 11:48:05.677695 Freq=600, CH1 RK1
4732 11:48:05.677973
4733 11:48:05.680140 DATLAT Default: 0x9
4734 11:48:05.680587 0, 0xFFFF, sum = 0
4735 11:48:05.683513 1, 0xFFFF, sum = 0
4736 11:48:05.683901 2, 0xFFFF, sum = 0
4737 11:48:05.686692 3, 0xFFFF, sum = 0
4738 11:48:05.689952 4, 0xFFFF, sum = 0
4739 11:48:05.690350 5, 0xFFFF, sum = 0
4740 11:48:05.693231 6, 0xFFFF, sum = 0
4741 11:48:05.693627 7, 0xFFFF, sum = 0
4742 11:48:05.696674 8, 0x0, sum = 1
4743 11:48:05.697070 9, 0x0, sum = 2
4744 11:48:05.697474 10, 0x0, sum = 3
4745 11:48:05.699609 11, 0x0, sum = 4
4746 11:48:05.700003 best_step = 9
4747 11:48:05.700354
4748 11:48:05.700650 ==
4749 11:48:05.703530 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 11:48:05.709667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 11:48:05.710211 ==
4752 11:48:05.710661 RX Vref Scan: 0
4753 11:48:05.711120
4754 11:48:05.712842 RX Vref 0 -> 0, step: 1
4755 11:48:05.713355
4756 11:48:05.716856 RX Delay -195 -> 252, step: 8
4757 11:48:05.719611 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4758 11:48:05.726111 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4759 11:48:05.729466 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4760 11:48:05.732674 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4761 11:48:05.736124 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4762 11:48:05.742761 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4763 11:48:05.746364 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4764 11:48:05.749365 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4765 11:48:05.752917 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4766 11:48:05.756481 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4767 11:48:05.762896 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4768 11:48:05.766141 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4769 11:48:05.769727 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4770 11:48:05.772694 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4771 11:48:05.779600 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4772 11:48:05.782704 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4773 11:48:05.783092 ==
4774 11:48:05.786294 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 11:48:05.789285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 11:48:05.789754 ==
4777 11:48:05.792930 DQS Delay:
4778 11:48:05.793461 DQS0 = 0, DQS1 = 0
4779 11:48:05.793810 DQM Delay:
4780 11:48:05.796394 DQM0 = 36, DQM1 = 29
4781 11:48:05.796918 DQ Delay:
4782 11:48:05.799661 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4783 11:48:05.802945 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4784 11:48:05.805913 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4785 11:48:05.809590 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4786 11:48:05.809976
4787 11:48:05.810279
4788 11:48:05.819131 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
4789 11:48:05.822844 CH1 RK1: MR19=808, MR18=3F5E
4790 11:48:05.825812 CH1_RK1: MR19=0x808, MR18=0x3F5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4791 11:48:05.829321 [RxdqsGatingPostProcess] freq 600
4792 11:48:05.836078 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4793 11:48:05.839145 Pre-setting of DQS Precalculation
4794 11:48:05.842521 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4795 11:48:05.849591 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4796 11:48:05.858964 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4797 11:48:05.859396
4798 11:48:05.859731
4799 11:48:05.862638 [Calibration Summary] 1200 Mbps
4800 11:48:05.863015 CH 0, Rank 0
4801 11:48:05.866162 SW Impedance : PASS
4802 11:48:05.866600 DUTY Scan : NO K
4803 11:48:05.869207 ZQ Calibration : PASS
4804 11:48:05.872712 Jitter Meter : NO K
4805 11:48:05.873236 CBT Training : PASS
4806 11:48:05.875639 Write leveling : PASS
4807 11:48:05.878978 RX DQS gating : PASS
4808 11:48:05.879489 RX DQ/DQS(RDDQC) : PASS
4809 11:48:05.882111 TX DQ/DQS : PASS
4810 11:48:05.885543 RX DATLAT : PASS
4811 11:48:05.886021 RX DQ/DQS(Engine): PASS
4812 11:48:05.888593 TX OE : NO K
4813 11:48:05.888984 All Pass.
4814 11:48:05.889461
4815 11:48:05.892091 CH 0, Rank 1
4816 11:48:05.892549 SW Impedance : PASS
4817 11:48:05.895732 DUTY Scan : NO K
4818 11:48:05.896171 ZQ Calibration : PASS
4819 11:48:05.898467 Jitter Meter : NO K
4820 11:48:05.902044 CBT Training : PASS
4821 11:48:05.902458 Write leveling : PASS
4822 11:48:05.905495 RX DQS gating : PASS
4823 11:48:05.908680 RX DQ/DQS(RDDQC) : PASS
4824 11:48:05.909239 TX DQ/DQS : PASS
4825 11:48:05.911883 RX DATLAT : PASS
4826 11:48:05.915367 RX DQ/DQS(Engine): PASS
4827 11:48:05.915891 TX OE : NO K
4828 11:48:05.918411 All Pass.
4829 11:48:05.918789
4830 11:48:05.919088 CH 1, Rank 0
4831 11:48:05.921506 SW Impedance : PASS
4832 11:48:05.921890 DUTY Scan : NO K
4833 11:48:05.925194 ZQ Calibration : PASS
4834 11:48:05.928555 Jitter Meter : NO K
4835 11:48:05.928941 CBT Training : PASS
4836 11:48:05.931599 Write leveling : PASS
4837 11:48:05.934925 RX DQS gating : PASS
4838 11:48:05.935344 RX DQ/DQS(RDDQC) : PASS
4839 11:48:05.938157 TX DQ/DQS : PASS
4840 11:48:05.941592 RX DATLAT : PASS
4841 11:48:05.942070 RX DQ/DQS(Engine): PASS
4842 11:48:05.945130 TX OE : NO K
4843 11:48:05.945523 All Pass.
4844 11:48:05.945825
4845 11:48:05.948662 CH 1, Rank 1
4846 11:48:05.949049 SW Impedance : PASS
4847 11:48:05.951596 DUTY Scan : NO K
4848 11:48:05.955037 ZQ Calibration : PASS
4849 11:48:05.955524 Jitter Meter : NO K
4850 11:48:05.958257 CBT Training : PASS
4851 11:48:05.961196 Write leveling : PASS
4852 11:48:05.961572 RX DQS gating : PASS
4853 11:48:05.964620 RX DQ/DQS(RDDQC) : PASS
4854 11:48:05.965004 TX DQ/DQS : PASS
4855 11:48:05.968080 RX DATLAT : PASS
4856 11:48:05.971563 RX DQ/DQS(Engine): PASS
4857 11:48:05.971946 TX OE : NO K
4858 11:48:05.974839 All Pass.
4859 11:48:05.975218
4860 11:48:05.975519 DramC Write-DBI off
4861 11:48:05.977934 PER_BANK_REFRESH: Hybrid Mode
4862 11:48:05.981411 TX_TRACKING: ON
4863 11:48:05.987928 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4864 11:48:05.991645 [FAST_K] Save calibration result to emmc
4865 11:48:05.994551 dramc_set_vcore_voltage set vcore to 662500
4866 11:48:05.997653 Read voltage for 933, 3
4867 11:48:05.998054 Vio18 = 0
4868 11:48:06.001082 Vcore = 662500
4869 11:48:06.001638 Vdram = 0
4870 11:48:06.002185 Vddq = 0
4871 11:48:06.004568 Vmddr = 0
4872 11:48:06.007927 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4873 11:48:06.014409 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4874 11:48:06.014974 MEM_TYPE=3, freq_sel=17
4875 11:48:06.017364 sv_algorithm_assistance_LP4_1600
4876 11:48:06.024145 ============ PULL DRAM RESETB DOWN ============
4877 11:48:06.027309 ========== PULL DRAM RESETB DOWN end =========
4878 11:48:06.031121 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4879 11:48:06.034335 ===================================
4880 11:48:06.037371 LPDDR4 DRAM CONFIGURATION
4881 11:48:06.040880 ===================================
4882 11:48:06.044060 EX_ROW_EN[0] = 0x0
4883 11:48:06.044595 EX_ROW_EN[1] = 0x0
4884 11:48:06.047556 LP4Y_EN = 0x0
4885 11:48:06.047932 WORK_FSP = 0x0
4886 11:48:06.050597 WL = 0x3
4887 11:48:06.050977 RL = 0x3
4888 11:48:06.054151 BL = 0x2
4889 11:48:06.054530 RPST = 0x0
4890 11:48:06.057639 RD_PRE = 0x0
4891 11:48:06.058076 WR_PRE = 0x1
4892 11:48:06.060510 WR_PST = 0x0
4893 11:48:06.060889 DBI_WR = 0x0
4894 11:48:06.063811 DBI_RD = 0x0
4895 11:48:06.064189 OTF = 0x1
4896 11:48:06.067045 ===================================
4897 11:48:06.070360 ===================================
4898 11:48:06.073921 ANA top config
4899 11:48:06.076855 ===================================
4900 11:48:06.080269 DLL_ASYNC_EN = 0
4901 11:48:06.080716 ALL_SLAVE_EN = 1
4902 11:48:06.083757 NEW_RANK_MODE = 1
4903 11:48:06.087364 DLL_IDLE_MODE = 1
4904 11:48:06.090158 LP45_APHY_COMB_EN = 1
4905 11:48:06.093374 TX_ODT_DIS = 1
4906 11:48:06.093764 NEW_8X_MODE = 1
4907 11:48:06.096956 ===================================
4908 11:48:06.100440 ===================================
4909 11:48:06.103823 data_rate = 1866
4910 11:48:06.106846 CKR = 1
4911 11:48:06.110242 DQ_P2S_RATIO = 8
4912 11:48:06.113806 ===================================
4913 11:48:06.116629 CA_P2S_RATIO = 8
4914 11:48:06.120252 DQ_CA_OPEN = 0
4915 11:48:06.120722 DQ_SEMI_OPEN = 0
4916 11:48:06.123051 CA_SEMI_OPEN = 0
4917 11:48:06.126651 CA_FULL_RATE = 0
4918 11:48:06.130029 DQ_CKDIV4_EN = 1
4919 11:48:06.133257 CA_CKDIV4_EN = 1
4920 11:48:06.136521 CA_PREDIV_EN = 0
4921 11:48:06.136906 PH8_DLY = 0
4922 11:48:06.139720 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4923 11:48:06.143402 DQ_AAMCK_DIV = 4
4924 11:48:06.146425 CA_AAMCK_DIV = 4
4925 11:48:06.149824 CA_ADMCK_DIV = 4
4926 11:48:06.153349 DQ_TRACK_CA_EN = 0
4927 11:48:06.153738 CA_PICK = 933
4928 11:48:06.156266 CA_MCKIO = 933
4929 11:48:06.159739 MCKIO_SEMI = 0
4930 11:48:06.162763 PLL_FREQ = 3732
4931 11:48:06.166369 DQ_UI_PI_RATIO = 32
4932 11:48:06.169554 CA_UI_PI_RATIO = 0
4933 11:48:06.172688 ===================================
4934 11:48:06.176146 ===================================
4935 11:48:06.179277 memory_type:LPDDR4
4936 11:48:06.179682 GP_NUM : 10
4937 11:48:06.182723 SRAM_EN : 1
4938 11:48:06.183109 MD32_EN : 0
4939 11:48:06.185987 ===================================
4940 11:48:06.189491 [ANA_INIT] >>>>>>>>>>>>>>
4941 11:48:06.192726 <<<<<< [CONFIGURE PHASE]: ANA_TX
4942 11:48:06.196080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4943 11:48:06.199544 ===================================
4944 11:48:06.202758 data_rate = 1866,PCW = 0X8f00
4945 11:48:06.206230 ===================================
4946 11:48:06.209099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4947 11:48:06.216173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4948 11:48:06.219090 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 11:48:06.225690 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4950 11:48:06.229047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4951 11:48:06.232548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4952 11:48:06.233082 [ANA_INIT] flow start
4953 11:48:06.235414 [ANA_INIT] PLL >>>>>>>>
4954 11:48:06.238755 [ANA_INIT] PLL <<<<<<<<
4955 11:48:06.239154 [ANA_INIT] MIDPI >>>>>>>>
4956 11:48:06.243560 [ANA_INIT] MIDPI <<<<<<<<
4957 11:48:06.245509 [ANA_INIT] DLL >>>>>>>>
4958 11:48:06.245909 [ANA_INIT] flow end
4959 11:48:06.252415 ============ LP4 DIFF to SE enter ============
4960 11:48:06.255674 ============ LP4 DIFF to SE exit ============
4961 11:48:06.258903 [ANA_INIT] <<<<<<<<<<<<<
4962 11:48:06.262198 [Flow] Enable top DCM control >>>>>
4963 11:48:06.265446 [Flow] Enable top DCM control <<<<<
4964 11:48:06.265844 Enable DLL master slave shuffle
4965 11:48:06.272314 ==============================================================
4966 11:48:06.275369 Gating Mode config
4967 11:48:06.278825 ==============================================================
4968 11:48:06.281783 Config description:
4969 11:48:06.291686 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4970 11:48:06.298217 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4971 11:48:06.301620 SELPH_MODE 0: By rank 1: By Phase
4972 11:48:06.308464 ==============================================================
4973 11:48:06.311908 GAT_TRACK_EN = 1
4974 11:48:06.315097 RX_GATING_MODE = 2
4975 11:48:06.318064 RX_GATING_TRACK_MODE = 2
4976 11:48:06.321705 SELPH_MODE = 1
4977 11:48:06.324570 PICG_EARLY_EN = 1
4978 11:48:06.325006 VALID_LAT_VALUE = 1
4979 11:48:06.331481 ==============================================================
4980 11:48:06.334449 Enter into Gating configuration >>>>
4981 11:48:06.338047 Exit from Gating configuration <<<<
4982 11:48:06.341368 Enter into DVFS_PRE_config >>>>>
4983 11:48:06.351145 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4984 11:48:06.354675 Exit from DVFS_PRE_config <<<<<
4985 11:48:06.357660 Enter into PICG configuration >>>>
4986 11:48:06.361102 Exit from PICG configuration <<<<
4987 11:48:06.363932 [RX_INPUT] configuration >>>>>
4988 11:48:06.367747 [RX_INPUT] configuration <<<<<
4989 11:48:06.374144 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4990 11:48:06.377330 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4991 11:48:06.384313 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4992 11:48:06.390845 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4993 11:48:06.397280 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 11:48:06.404191 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 11:48:06.407064 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4996 11:48:06.410561 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4997 11:48:06.414061 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4998 11:48:06.420524 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4999 11:48:06.424012 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5000 11:48:06.427379 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 11:48:06.430625 ===================================
5002 11:48:06.433811 LPDDR4 DRAM CONFIGURATION
5003 11:48:06.437336 ===================================
5004 11:48:06.440332 EX_ROW_EN[0] = 0x0
5005 11:48:06.440868 EX_ROW_EN[1] = 0x0
5006 11:48:06.443728 LP4Y_EN = 0x0
5007 11:48:06.444257 WORK_FSP = 0x0
5008 11:48:06.447329 WL = 0x3
5009 11:48:06.447745 RL = 0x3
5010 11:48:06.450121 BL = 0x2
5011 11:48:06.450536 RPST = 0x0
5012 11:48:06.453467 RD_PRE = 0x0
5013 11:48:06.453886 WR_PRE = 0x1
5014 11:48:06.456859 WR_PST = 0x0
5015 11:48:06.457275 DBI_WR = 0x0
5016 11:48:06.460449 DBI_RD = 0x0
5017 11:48:06.460867 OTF = 0x1
5018 11:48:06.463327 ===================================
5019 11:48:06.470483 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5020 11:48:06.473358 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5021 11:48:06.476366 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5022 11:48:06.479796 ===================================
5023 11:48:06.483425 LPDDR4 DRAM CONFIGURATION
5024 11:48:06.486314 ===================================
5025 11:48:06.489655 EX_ROW_EN[0] = 0x10
5026 11:48:06.490094 EX_ROW_EN[1] = 0x0
5027 11:48:06.493117 LP4Y_EN = 0x0
5028 11:48:06.493535 WORK_FSP = 0x0
5029 11:48:06.496580 WL = 0x3
5030 11:48:06.497044 RL = 0x3
5031 11:48:06.499536 BL = 0x2
5032 11:48:06.499957 RPST = 0x0
5033 11:48:06.503361 RD_PRE = 0x0
5034 11:48:06.503930 WR_PRE = 0x1
5035 11:48:06.506267 WR_PST = 0x0
5036 11:48:06.506689 DBI_WR = 0x0
5037 11:48:06.509729 DBI_RD = 0x0
5038 11:48:06.510140 OTF = 0x1
5039 11:48:06.513171 ===================================
5040 11:48:06.519610 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5041 11:48:06.524300 nWR fixed to 30
5042 11:48:06.527317 [ModeRegInit_LP4] CH0 RK0
5043 11:48:06.527742 [ModeRegInit_LP4] CH0 RK1
5044 11:48:06.530948 [ModeRegInit_LP4] CH1 RK0
5045 11:48:06.533956 [ModeRegInit_LP4] CH1 RK1
5046 11:48:06.534381 match AC timing 9
5047 11:48:06.541320 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5048 11:48:06.544010 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5049 11:48:06.547718 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5050 11:48:06.553967 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5051 11:48:06.557174 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5052 11:48:06.557704 ==
5053 11:48:06.561040 Dram Type= 6, Freq= 0, CH_0, rank 0
5054 11:48:06.564502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5055 11:48:06.564923 ==
5056 11:48:06.570769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5057 11:48:06.577138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5058 11:48:06.580826 [CA 0] Center 38 (8~69) winsize 62
5059 11:48:06.583817 [CA 1] Center 38 (7~69) winsize 63
5060 11:48:06.587311 [CA 2] Center 36 (6~66) winsize 61
5061 11:48:06.590762 [CA 3] Center 35 (5~66) winsize 62
5062 11:48:06.594043 [CA 4] Center 34 (4~65) winsize 62
5063 11:48:06.596949 [CA 5] Center 33 (3~64) winsize 62
5064 11:48:06.597044
5065 11:48:06.600014 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5066 11:48:06.600094
5067 11:48:06.603441 [CATrainingPosCal] consider 1 rank data
5068 11:48:06.606635 u2DelayCellTimex100 = 270/100 ps
5069 11:48:06.609833 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5070 11:48:06.613399 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5071 11:48:06.616971 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5072 11:48:06.619986 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5073 11:48:06.623569 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5074 11:48:06.630089 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5075 11:48:06.630170
5076 11:48:06.633584 CA PerBit enable=1, Macro0, CA PI delay=33
5077 11:48:06.633665
5078 11:48:06.636849 [CBTSetCACLKResult] CA Dly = 33
5079 11:48:06.636929 CS Dly: 6 (0~37)
5080 11:48:06.636992 ==
5081 11:48:06.639878 Dram Type= 6, Freq= 0, CH_0, rank 1
5082 11:48:06.643448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 11:48:06.646508 ==
5084 11:48:06.650048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 11:48:06.656396 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5086 11:48:06.659795 [CA 0] Center 38 (8~69) winsize 62
5087 11:48:06.663161 [CA 1] Center 38 (8~69) winsize 62
5088 11:48:06.666239 [CA 2] Center 35 (5~66) winsize 62
5089 11:48:06.669552 [CA 3] Center 35 (5~66) winsize 62
5090 11:48:06.672777 [CA 4] Center 34 (3~65) winsize 63
5091 11:48:06.676155 [CA 5] Center 33 (3~64) winsize 62
5092 11:48:06.676309
5093 11:48:06.679402 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5094 11:48:06.679487
5095 11:48:06.682962 [CATrainingPosCal] consider 2 rank data
5096 11:48:06.685962 u2DelayCellTimex100 = 270/100 ps
5097 11:48:06.689522 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5098 11:48:06.692527 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5099 11:48:06.696016 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5100 11:48:06.702490 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5101 11:48:06.706031 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5102 11:48:06.709348 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5103 11:48:06.709430
5104 11:48:06.712496 CA PerBit enable=1, Macro0, CA PI delay=33
5105 11:48:06.712578
5106 11:48:06.716032 [CBTSetCACLKResult] CA Dly = 33
5107 11:48:06.716112 CS Dly: 6 (0~38)
5108 11:48:06.716240
5109 11:48:06.719325 ----->DramcWriteLeveling(PI) begin...
5110 11:48:06.722375 ==
5111 11:48:06.725983 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 11:48:06.728819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 11:48:06.728907 ==
5114 11:48:06.732357 Write leveling (Byte 0): 32 => 32
5115 11:48:06.735774 Write leveling (Byte 1): 30 => 30
5116 11:48:06.739217 DramcWriteLeveling(PI) end<-----
5117 11:48:06.739316
5118 11:48:06.739379 ==
5119 11:48:06.742391 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 11:48:06.745788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 11:48:06.745875 ==
5122 11:48:06.749235 [Gating] SW mode calibration
5123 11:48:06.755402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5124 11:48:06.762298 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5125 11:48:06.765833 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
5126 11:48:06.768856 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5127 11:48:06.775284 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 11:48:06.778756 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 11:48:06.781997 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 11:48:06.788816 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 11:48:06.791819 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 11:48:06.795370 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5133 11:48:06.801854 0 15 0 | B1->B0 | 3333 2d2d | 1 1 | (1 1) (1 0)
5134 11:48:06.805251 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5135 11:48:06.808748 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 11:48:06.811639 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 11:48:06.818582 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 11:48:06.821946 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 11:48:06.825058 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 11:48:06.831461 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 11:48:06.834930 1 0 0 | B1->B0 | 2b2b 3b3b | 0 0 | (0 0) (0 0)
5142 11:48:06.838270 1 0 4 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
5143 11:48:06.845370 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 11:48:06.848260 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 11:48:06.851674 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 11:48:06.858238 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 11:48:06.861591 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 11:48:06.865185 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 11:48:06.871535 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5150 11:48:06.875026 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5151 11:48:06.878074 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 11:48:06.885251 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 11:48:06.888167 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 11:48:06.891705 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 11:48:06.898235 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 11:48:06.901319 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 11:48:06.904588 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 11:48:06.911271 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 11:48:06.914955 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 11:48:06.918644 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 11:48:06.925021 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 11:48:06.928383 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 11:48:06.931707 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 11:48:06.934808 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5165 11:48:06.941665 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5166 11:48:06.945053 Total UI for P1: 0, mck2ui 16
5167 11:48:06.948046 best dqsien dly found for B0: ( 1, 2, 28)
5168 11:48:06.951646 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 11:48:06.954573 Total UI for P1: 0, mck2ui 16
5170 11:48:06.958330 best dqsien dly found for B1: ( 1, 3, 2)
5171 11:48:06.961616 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5172 11:48:06.965125 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5173 11:48:06.965365
5174 11:48:06.968286 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5175 11:48:06.971818 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5176 11:48:06.974867 [Gating] SW calibration Done
5177 11:48:06.975105 ==
5178 11:48:06.978408 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 11:48:06.984831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 11:48:06.985294 ==
5181 11:48:06.985591 RX Vref Scan: 0
5182 11:48:06.985886
5183 11:48:06.987922 RX Vref 0 -> 0, step: 1
5184 11:48:06.988443
5185 11:48:06.991511 RX Delay -80 -> 252, step: 8
5186 11:48:06.994496 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5187 11:48:06.998053 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5188 11:48:07.001487 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5189 11:48:07.004195 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5190 11:48:07.007907 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5191 11:48:07.014593 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5192 11:48:07.017743 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5193 11:48:07.021303 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5194 11:48:07.024362 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5195 11:48:07.027528 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5196 11:48:07.034604 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5197 11:48:07.037684 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5198 11:48:07.041104 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5199 11:48:07.044151 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5200 11:48:07.047813 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5201 11:48:07.054122 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5202 11:48:07.054415 ==
5203 11:48:07.057487 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 11:48:07.061100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 11:48:07.061417 ==
5206 11:48:07.061649 DQS Delay:
5207 11:48:07.064594 DQS0 = 0, DQS1 = 0
5208 11:48:07.064880 DQM Delay:
5209 11:48:07.067288 DQM0 = 95, DQM1 = 82
5210 11:48:07.067590 DQ Delay:
5211 11:48:07.070595 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =95
5212 11:48:07.074411 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5213 11:48:07.077295 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5214 11:48:07.080889 DQ12 =83, DQ13 =91, DQ14 =95, DQ15 =91
5215 11:48:07.081170
5216 11:48:07.081488
5217 11:48:07.081723 ==
5218 11:48:07.083825 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 11:48:07.087273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 11:48:07.090871 ==
5221 11:48:07.091162
5222 11:48:07.091387
5223 11:48:07.091632 TX Vref Scan disable
5224 11:48:07.093778 == TX Byte 0 ==
5225 11:48:07.097367 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5226 11:48:07.100864 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5227 11:48:07.103841 == TX Byte 1 ==
5228 11:48:07.107410 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5229 11:48:07.110310 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5230 11:48:07.110592 ==
5231 11:48:07.113846 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 11:48:07.120121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 11:48:07.120457 ==
5234 11:48:07.120696
5235 11:48:07.120918
5236 11:48:07.123669 TX Vref Scan disable
5237 11:48:07.123946 == TX Byte 0 ==
5238 11:48:07.130411 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5239 11:48:07.133659 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5240 11:48:07.134008 == TX Byte 1 ==
5241 11:48:07.139874 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5242 11:48:07.143472 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5243 11:48:07.143751
5244 11:48:07.144031 [DATLAT]
5245 11:48:07.146601 Freq=933, CH0 RK0
5246 11:48:07.146982
5247 11:48:07.147314 DATLAT Default: 0xd
5248 11:48:07.149723 0, 0xFFFF, sum = 0
5249 11:48:07.150014 1, 0xFFFF, sum = 0
5250 11:48:07.153101 2, 0xFFFF, sum = 0
5251 11:48:07.153370 3, 0xFFFF, sum = 0
5252 11:48:07.156538 4, 0xFFFF, sum = 0
5253 11:48:07.156805 5, 0xFFFF, sum = 0
5254 11:48:07.159995 6, 0xFFFF, sum = 0
5255 11:48:07.163465 7, 0xFFFF, sum = 0
5256 11:48:07.163755 8, 0xFFFF, sum = 0
5257 11:48:07.166618 9, 0xFFFF, sum = 0
5258 11:48:07.166881 10, 0x0, sum = 1
5259 11:48:07.167110 11, 0x0, sum = 2
5260 11:48:07.169804 12, 0x0, sum = 3
5261 11:48:07.170100 13, 0x0, sum = 4
5262 11:48:07.173054 best_step = 11
5263 11:48:07.173345
5264 11:48:07.173574 ==
5265 11:48:07.176277 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 11:48:07.179379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 11:48:07.179602 ==
5268 11:48:07.182987 RX Vref Scan: 1
5269 11:48:07.183207
5270 11:48:07.186099 RX Vref 0 -> 0, step: 1
5271 11:48:07.186320
5272 11:48:07.186493 RX Delay -77 -> 252, step: 4
5273 11:48:07.186655
5274 11:48:07.189063 Set Vref, RX VrefLevel [Byte0]: 61
5275 11:48:07.192307 [Byte1]: 52
5276 11:48:07.197010
5277 11:48:07.197090 Final RX Vref Byte 0 = 61 to rank0
5278 11:48:07.200461 Final RX Vref Byte 1 = 52 to rank0
5279 11:48:07.204018 Final RX Vref Byte 0 = 61 to rank1
5280 11:48:07.206959 Final RX Vref Byte 1 = 52 to rank1==
5281 11:48:07.210441 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 11:48:07.216912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 11:48:07.216993 ==
5284 11:48:07.217056 DQS Delay:
5285 11:48:07.217115 DQS0 = 0, DQS1 = 0
5286 11:48:07.220496 DQM Delay:
5287 11:48:07.220575 DQM0 = 95, DQM1 = 83
5288 11:48:07.223970 DQ Delay:
5289 11:48:07.226812 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5290 11:48:07.230296 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5291 11:48:07.233703 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5292 11:48:07.237236 DQ12 =88, DQ13 =86, DQ14 =98, DQ15 =90
5293 11:48:07.237348
5294 11:48:07.237444
5295 11:48:07.243813 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5296 11:48:07.247076 CH0 RK0: MR19=505, MR18=1010
5297 11:48:07.254021 CH0_RK0: MR19=0x505, MR18=0x1010, DQSOSC=416, MR23=63, INC=62, DEC=41
5298 11:48:07.254104
5299 11:48:07.257242 ----->DramcWriteLeveling(PI) begin...
5300 11:48:07.257323 ==
5301 11:48:07.260690 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 11:48:07.263963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 11:48:07.264062 ==
5304 11:48:07.266966 Write leveling (Byte 0): 34 => 34
5305 11:48:07.270316 Write leveling (Byte 1): 29 => 29
5306 11:48:07.273834 DramcWriteLeveling(PI) end<-----
5307 11:48:07.273931
5308 11:48:07.274021 ==
5309 11:48:07.276721 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 11:48:07.280290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 11:48:07.280391 ==
5312 11:48:07.283550 [Gating] SW mode calibration
5313 11:48:07.290467 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5314 11:48:07.296900 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5315 11:48:07.300639 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
5316 11:48:07.306662 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 11:48:07.310227 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 11:48:07.313816 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 11:48:07.320349 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 11:48:07.323313 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 11:48:07.326779 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5322 11:48:07.330258 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
5323 11:48:07.336301 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5324 11:48:07.339694 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 11:48:07.343210 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 11:48:07.349704 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 11:48:07.353122 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 11:48:07.356540 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 11:48:07.362961 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 11:48:07.366367 0 15 28 | B1->B0 | 2a2a 3939 | 0 0 | (0 0) (0 0)
5331 11:48:07.369727 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5332 11:48:07.376452 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 11:48:07.379763 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 11:48:07.382991 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 11:48:07.389649 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 11:48:07.392865 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 11:48:07.396375 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 11:48:07.403057 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5339 11:48:07.406025 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5340 11:48:07.409441 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 11:48:07.416015 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 11:48:07.419179 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 11:48:07.422774 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 11:48:07.429054 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 11:48:07.432624 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 11:48:07.436096 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 11:48:07.442605 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 11:48:07.445636 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 11:48:07.449125 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 11:48:07.455662 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 11:48:07.459159 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 11:48:07.462403 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 11:48:07.469367 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 11:48:07.472386 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5355 11:48:07.475828 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5356 11:48:07.482142 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 11:48:07.482224 Total UI for P1: 0, mck2ui 16
5358 11:48:07.488967 best dqsien dly found for B0: ( 1, 2, 30)
5359 11:48:07.489047 Total UI for P1: 0, mck2ui 16
5360 11:48:07.495454 best dqsien dly found for B1: ( 1, 2, 30)
5361 11:48:07.499068 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5362 11:48:07.502144 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5363 11:48:07.502250
5364 11:48:07.505804 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5365 11:48:07.508639 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5366 11:48:07.511996 [Gating] SW calibration Done
5367 11:48:07.512101 ==
5368 11:48:07.515545 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 11:48:07.518922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 11:48:07.519003 ==
5371 11:48:07.522120 RX Vref Scan: 0
5372 11:48:07.522201
5373 11:48:07.522265 RX Vref 0 -> 0, step: 1
5374 11:48:07.522324
5375 11:48:07.525496 RX Delay -80 -> 252, step: 8
5376 11:48:07.528569 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5377 11:48:07.535453 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5378 11:48:07.538925 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5379 11:48:07.541804 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5380 11:48:07.545219 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5381 11:48:07.548483 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5382 11:48:07.552005 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5383 11:48:07.558527 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5384 11:48:07.562142 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5385 11:48:07.564997 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5386 11:48:07.568347 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5387 11:48:07.571977 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5388 11:48:07.578513 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5389 11:48:07.581776 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5390 11:48:07.585178 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5391 11:48:07.588731 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5392 11:48:07.588811 ==
5393 11:48:07.591763 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 11:48:07.598648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 11:48:07.598729 ==
5396 11:48:07.598792 DQS Delay:
5397 11:48:07.598850 DQS0 = 0, DQS1 = 0
5398 11:48:07.601890 DQM Delay:
5399 11:48:07.601969 DQM0 = 92, DQM1 = 82
5400 11:48:07.605392 DQ Delay:
5401 11:48:07.608437 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5402 11:48:07.611824 DQ4 =91, DQ5 =75, DQ6 =107, DQ7 =107
5403 11:48:07.615169 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5404 11:48:07.618520 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =87
5405 11:48:07.618594
5406 11:48:07.618721
5407 11:48:07.618811 ==
5408 11:48:07.621503 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 11:48:07.624848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 11:48:07.624926 ==
5411 11:48:07.624988
5412 11:48:07.625046
5413 11:48:07.628439 TX Vref Scan disable
5414 11:48:07.628541 == TX Byte 0 ==
5415 11:48:07.634981 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5416 11:48:07.638282 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5417 11:48:07.638356 == TX Byte 1 ==
5418 11:48:07.644619 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5419 11:48:07.648160 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5420 11:48:07.648294 ==
5421 11:48:07.651564 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 11:48:07.655054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 11:48:07.655135 ==
5424 11:48:07.655198
5425 11:48:07.657962
5426 11:48:07.658042 TX Vref Scan disable
5427 11:48:07.661556 == TX Byte 0 ==
5428 11:48:07.664445 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5429 11:48:07.671118 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5430 11:48:07.671199 == TX Byte 1 ==
5431 11:48:07.674600 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5432 11:48:07.680994 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5433 11:48:07.681075
5434 11:48:07.681138 [DATLAT]
5435 11:48:07.681195 Freq=933, CH0 RK1
5436 11:48:07.681252
5437 11:48:07.684439 DATLAT Default: 0xb
5438 11:48:07.684518 0, 0xFFFF, sum = 0
5439 11:48:07.687801 1, 0xFFFF, sum = 0
5440 11:48:07.691351 2, 0xFFFF, sum = 0
5441 11:48:07.691433 3, 0xFFFF, sum = 0
5442 11:48:07.694249 4, 0xFFFF, sum = 0
5443 11:48:07.694330 5, 0xFFFF, sum = 0
5444 11:48:07.697667 6, 0xFFFF, sum = 0
5445 11:48:07.697748 7, 0xFFFF, sum = 0
5446 11:48:07.701240 8, 0xFFFF, sum = 0
5447 11:48:07.701320 9, 0xFFFF, sum = 0
5448 11:48:07.704495 10, 0x0, sum = 1
5449 11:48:07.704576 11, 0x0, sum = 2
5450 11:48:07.708014 12, 0x0, sum = 3
5451 11:48:07.708122 13, 0x0, sum = 4
5452 11:48:07.708242 best_step = 11
5453 11:48:07.708318
5454 11:48:07.710963 ==
5455 11:48:07.714495 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 11:48:07.718159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 11:48:07.718239 ==
5458 11:48:07.718301 RX Vref Scan: 0
5459 11:48:07.718359
5460 11:48:07.721134 RX Vref 0 -> 0, step: 1
5461 11:48:07.721220
5462 11:48:07.724524 RX Delay -77 -> 252, step: 4
5463 11:48:07.731039 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5464 11:48:07.734445 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5465 11:48:07.737751 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5466 11:48:07.741013 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5467 11:48:07.744107 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5468 11:48:07.747420 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5469 11:48:07.754162 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5470 11:48:07.757207 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5471 11:48:07.760788 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5472 11:48:07.763712 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5473 11:48:07.767427 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5474 11:48:07.773800 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5475 11:48:07.777097 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5476 11:48:07.780135 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5477 11:48:07.783700 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5478 11:48:07.787141 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5479 11:48:07.787221 ==
5480 11:48:07.790035 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 11:48:07.796974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 11:48:07.797084 ==
5483 11:48:07.797150 DQS Delay:
5484 11:48:07.800487 DQS0 = 0, DQS1 = 0
5485 11:48:07.800566 DQM Delay:
5486 11:48:07.803446 DQM0 = 92, DQM1 = 83
5487 11:48:07.803526 DQ Delay:
5488 11:48:07.806918 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5489 11:48:07.810227 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =102
5490 11:48:07.813310 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5491 11:48:07.816811 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5492 11:48:07.816894
5493 11:48:07.816958
5494 11:48:07.823111 [DQSOSCAuto] RK1, (LSB)MR18= 0x3414, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
5495 11:48:07.826571 CH0 RK1: MR19=505, MR18=3414
5496 11:48:07.833418 CH0_RK1: MR19=0x505, MR18=0x3414, DQSOSC=405, MR23=63, INC=66, DEC=44
5497 11:48:07.836760 [RxdqsGatingPostProcess] freq 933
5498 11:48:07.843060 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5499 11:48:07.846532 best DQS0 dly(2T, 0.5T) = (0, 10)
5500 11:48:07.846612 best DQS1 dly(2T, 0.5T) = (0, 11)
5501 11:48:07.849460 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5502 11:48:07.853057 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5503 11:48:07.856331 best DQS0 dly(2T, 0.5T) = (0, 10)
5504 11:48:07.859735 best DQS1 dly(2T, 0.5T) = (0, 10)
5505 11:48:07.862661 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5506 11:48:07.866080 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5507 11:48:07.869300 Pre-setting of DQS Precalculation
5508 11:48:07.876160 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5509 11:48:07.876261 ==
5510 11:48:07.879677 Dram Type= 6, Freq= 0, CH_1, rank 0
5511 11:48:07.882751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 11:48:07.882851 ==
5513 11:48:07.889605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5514 11:48:07.892450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5515 11:48:07.896799 [CA 0] Center 37 (7~67) winsize 61
5516 11:48:07.900371 [CA 1] Center 37 (7~68) winsize 62
5517 11:48:07.903308 [CA 2] Center 34 (5~64) winsize 60
5518 11:48:07.906822 [CA 3] Center 34 (5~64) winsize 60
5519 11:48:07.910254 [CA 4] Center 34 (5~64) winsize 60
5520 11:48:07.913111 [CA 5] Center 34 (4~64) winsize 61
5521 11:48:07.913185
5522 11:48:07.916637 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5523 11:48:07.916713
5524 11:48:07.920173 [CATrainingPosCal] consider 1 rank data
5525 11:48:07.923090 u2DelayCellTimex100 = 270/100 ps
5526 11:48:07.926616 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5527 11:48:07.933111 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5528 11:48:07.936541 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5529 11:48:07.939839 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5530 11:48:07.943249 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5531 11:48:07.946692 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5532 11:48:07.946765
5533 11:48:07.949989 CA PerBit enable=1, Macro0, CA PI delay=34
5534 11:48:07.950060
5535 11:48:07.953091 [CBTSetCACLKResult] CA Dly = 34
5536 11:48:07.956636 CS Dly: 6 (0~37)
5537 11:48:07.956707 ==
5538 11:48:07.959565 Dram Type= 6, Freq= 0, CH_1, rank 1
5539 11:48:07.963001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 11:48:07.963102 ==
5541 11:48:07.969670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5542 11:48:07.973013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5543 11:48:07.977053 [CA 0] Center 37 (8~67) winsize 60
5544 11:48:07.979822 [CA 1] Center 37 (7~68) winsize 62
5545 11:48:07.983333 [CA 2] Center 36 (6~66) winsize 61
5546 11:48:07.986715 [CA 3] Center 34 (4~64) winsize 61
5547 11:48:07.990105 [CA 4] Center 35 (5~65) winsize 61
5548 11:48:07.993434 [CA 5] Center 34 (4~64) winsize 61
5549 11:48:07.993507
5550 11:48:07.996712 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5551 11:48:07.996816
5552 11:48:08.000097 [CATrainingPosCal] consider 2 rank data
5553 11:48:08.003106 u2DelayCellTimex100 = 270/100 ps
5554 11:48:08.006609 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5555 11:48:08.013233 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5556 11:48:08.016527 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5557 11:48:08.019988 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5558 11:48:08.023416 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5559 11:48:08.026342 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5560 11:48:08.026419
5561 11:48:08.029731 CA PerBit enable=1, Macro0, CA PI delay=34
5562 11:48:08.029810
5563 11:48:08.033243 [CBTSetCACLKResult] CA Dly = 34
5564 11:48:08.033346 CS Dly: 6 (0~38)
5565 11:48:08.033441
5566 11:48:08.039665 ----->DramcWriteLeveling(PI) begin...
5567 11:48:08.039744 ==
5568 11:48:08.043451 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 11:48:08.046168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 11:48:08.046244 ==
5571 11:48:08.049670 Write leveling (Byte 0): 27 => 27
5572 11:48:08.053293 Write leveling (Byte 1): 30 => 30
5573 11:48:08.056671 DramcWriteLeveling(PI) end<-----
5574 11:48:08.056773
5575 11:48:08.056867 ==
5576 11:48:08.059824 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 11:48:08.063197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 11:48:08.063299 ==
5579 11:48:08.066254 [Gating] SW mode calibration
5580 11:48:08.073207 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5581 11:48:08.079603 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5582 11:48:08.083076 0 14 0 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
5583 11:48:08.086051 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 11:48:08.093131 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 11:48:08.096518 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 11:48:08.099899 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 11:48:08.106600 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 11:48:08.109851 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5589 11:48:08.113357 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
5590 11:48:08.119832 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5591 11:48:08.123026 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 11:48:08.126387 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 11:48:08.132830 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 11:48:08.136264 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 11:48:08.139340 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 11:48:08.143080 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 11:48:08.149719 0 15 28 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
5598 11:48:08.153120 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 11:48:08.156027 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 11:48:08.162778 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 11:48:08.166212 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 11:48:08.169173 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 11:48:08.176068 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 11:48:08.179482 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 11:48:08.182608 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5606 11:48:08.189338 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 11:48:08.192615 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 11:48:08.196014 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 11:48:08.202383 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 11:48:08.206383 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 11:48:08.209326 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 11:48:08.215629 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 11:48:08.219168 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 11:48:08.222738 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 11:48:08.229023 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 11:48:08.232814 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 11:48:08.235576 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 11:48:08.242041 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 11:48:08.245172 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 11:48:08.248685 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5621 11:48:08.255241 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5622 11:48:08.258824 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 11:48:08.262258 Total UI for P1: 0, mck2ui 16
5624 11:48:08.265098 best dqsien dly found for B0: ( 1, 2, 26)
5625 11:48:08.268634 Total UI for P1: 0, mck2ui 16
5626 11:48:08.272235 best dqsien dly found for B1: ( 1, 2, 26)
5627 11:48:08.275119 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5628 11:48:08.278712 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5629 11:48:08.278792
5630 11:48:08.282159 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5631 11:48:08.285035 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5632 11:48:08.288428 [Gating] SW calibration Done
5633 11:48:08.288508 ==
5634 11:48:08.291857 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 11:48:08.294978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 11:48:08.298184 ==
5637 11:48:08.298264 RX Vref Scan: 0
5638 11:48:08.298328
5639 11:48:08.301815 RX Vref 0 -> 0, step: 1
5640 11:48:08.301895
5641 11:48:08.304693 RX Delay -80 -> 252, step: 8
5642 11:48:08.308188 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5643 11:48:08.311637 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5644 11:48:08.314529 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5645 11:48:08.318141 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5646 11:48:08.321645 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5647 11:48:08.327986 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5648 11:48:08.331489 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5649 11:48:08.334435 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5650 11:48:08.338040 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5651 11:48:08.341495 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5652 11:48:08.347715 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5653 11:48:08.351123 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5654 11:48:08.354478 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5655 11:48:08.357706 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5656 11:48:08.361112 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5657 11:48:08.367775 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5658 11:48:08.367857 ==
5659 11:48:08.371139 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 11:48:08.374179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 11:48:08.374261 ==
5662 11:48:08.374343 DQS Delay:
5663 11:48:08.377835 DQS0 = 0, DQS1 = 0
5664 11:48:08.377917 DQM Delay:
5665 11:48:08.381275 DQM0 = 94, DQM1 = 86
5666 11:48:08.381354 DQ Delay:
5667 11:48:08.384304 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5668 11:48:08.387691 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5669 11:48:08.391101 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5670 11:48:08.394166 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5671 11:48:08.394245
5672 11:48:08.394324
5673 11:48:08.394396 ==
5674 11:48:08.397543 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 11:48:08.401010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 11:48:08.401091 ==
5677 11:48:08.404366
5678 11:48:08.404444
5679 11:48:08.404507 TX Vref Scan disable
5680 11:48:08.407467 == TX Byte 0 ==
5681 11:48:08.411133 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5682 11:48:08.414048 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5683 11:48:08.417531 == TX Byte 1 ==
5684 11:48:08.421006 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5685 11:48:08.424074 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5686 11:48:08.424197 ==
5687 11:48:08.427463 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 11:48:08.434024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 11:48:08.434104 ==
5690 11:48:08.434168
5691 11:48:08.434226
5692 11:48:08.437452 TX Vref Scan disable
5693 11:48:08.437532 == TX Byte 0 ==
5694 11:48:08.443822 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5695 11:48:08.447250 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5696 11:48:08.447326 == TX Byte 1 ==
5697 11:48:08.453644 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5698 11:48:08.457022 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5699 11:48:08.457105
5700 11:48:08.457168 [DATLAT]
5701 11:48:08.460611 Freq=933, CH1 RK0
5702 11:48:08.460683
5703 11:48:08.460742 DATLAT Default: 0xd
5704 11:48:08.463956 0, 0xFFFF, sum = 0
5705 11:48:08.464416 1, 0xFFFF, sum = 0
5706 11:48:08.467479 2, 0xFFFF, sum = 0
5707 11:48:08.467899 3, 0xFFFF, sum = 0
5708 11:48:08.470817 4, 0xFFFF, sum = 0
5709 11:48:08.471241 5, 0xFFFF, sum = 0
5710 11:48:08.474110 6, 0xFFFF, sum = 0
5711 11:48:08.477180 7, 0xFFFF, sum = 0
5712 11:48:08.477605 8, 0xFFFF, sum = 0
5713 11:48:08.480640 9, 0xFFFF, sum = 0
5714 11:48:08.481066 10, 0x0, sum = 1
5715 11:48:08.481403 11, 0x0, sum = 2
5716 11:48:08.483656 12, 0x0, sum = 3
5717 11:48:08.484405 13, 0x0, sum = 4
5718 11:48:08.486850 best_step = 11
5719 11:48:08.487259
5720 11:48:08.487581 ==
5721 11:48:08.490330 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 11:48:08.493748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 11:48:08.494160 ==
5724 11:48:08.497013 RX Vref Scan: 1
5725 11:48:08.497425
5726 11:48:08.497746 RX Vref 0 -> 0, step: 1
5727 11:48:08.500473
5728 11:48:08.500891 RX Delay -69 -> 252, step: 4
5729 11:48:08.501219
5730 11:48:08.503883 Set Vref, RX VrefLevel [Byte0]: 54
5731 11:48:08.506792 [Byte1]: 51
5732 11:48:08.511363
5733 11:48:08.511815 Final RX Vref Byte 0 = 54 to rank0
5734 11:48:08.514485 Final RX Vref Byte 1 = 51 to rank0
5735 11:48:08.518279 Final RX Vref Byte 0 = 54 to rank1
5736 11:48:08.521371 Final RX Vref Byte 1 = 51 to rank1==
5737 11:48:08.524596 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 11:48:08.531046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 11:48:08.531459 ==
5740 11:48:08.531786 DQS Delay:
5741 11:48:08.532145 DQS0 = 0, DQS1 = 0
5742 11:48:08.534680 DQM Delay:
5743 11:48:08.535088 DQM0 = 96, DQM1 = 89
5744 11:48:08.538167 DQ Delay:
5745 11:48:08.541277 DQ0 =102, DQ1 =90, DQ2 =84, DQ3 =92
5746 11:48:08.544670 DQ4 =94, DQ5 =104, DQ6 =108, DQ7 =94
5747 11:48:08.548007 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =82
5748 11:48:08.550922 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =94
5749 11:48:08.551330
5750 11:48:08.551653
5751 11:48:08.557974 [DQSOSCAuto] RK0, (LSB)MR18= 0x20a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5752 11:48:08.561189 CH1 RK0: MR19=505, MR18=20A
5753 11:48:08.567670 CH1_RK0: MR19=0x505, MR18=0x20A, DQSOSC=418, MR23=63, INC=62, DEC=41
5754 11:48:08.568084
5755 11:48:08.571260 ----->DramcWriteLeveling(PI) begin...
5756 11:48:08.571770 ==
5757 11:48:08.574167 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 11:48:08.577658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 11:48:08.578070 ==
5760 11:48:08.581184 Write leveling (Byte 0): 26 => 26
5761 11:48:08.584088 Write leveling (Byte 1): 26 => 26
5762 11:48:08.587398 DramcWriteLeveling(PI) end<-----
5763 11:48:08.587806
5764 11:48:08.588252 ==
5765 11:48:08.590829 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 11:48:08.594037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 11:48:08.594448 ==
5768 11:48:08.597727 [Gating] SW mode calibration
5769 11:48:08.604329 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5770 11:48:08.610802 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5771 11:48:08.614425 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5772 11:48:08.620734 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 11:48:08.624038 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 11:48:08.627305 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 11:48:08.634123 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 11:48:08.637425 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 11:48:08.640250 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5778 11:48:08.646814 0 14 28 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
5779 11:48:08.650323 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 11:48:08.653905 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 11:48:08.656900 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 11:48:08.663941 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 11:48:08.667096 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 11:48:08.670643 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 11:48:08.676746 0 15 24 | B1->B0 | 2828 3737 | 0 0 | (0 0) (0 0)
5786 11:48:08.680315 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
5787 11:48:08.683995 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 11:48:08.690227 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 11:48:08.693572 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 11:48:08.697109 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 11:48:08.703674 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 11:48:08.707145 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 11:48:08.710020 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5794 11:48:08.716713 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5795 11:48:08.720376 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 11:48:08.723566 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 11:48:08.730193 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 11:48:08.733737 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 11:48:08.736581 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 11:48:08.743149 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 11:48:08.746885 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 11:48:08.749892 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 11:48:08.756834 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 11:48:08.760136 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 11:48:08.763088 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 11:48:08.769895 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 11:48:08.773305 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 11:48:08.776837 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 11:48:08.783278 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5810 11:48:08.786448 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 11:48:08.789938 Total UI for P1: 0, mck2ui 16
5812 11:48:08.792864 best dqsien dly found for B0: ( 1, 2, 24)
5813 11:48:08.796105 Total UI for P1: 0, mck2ui 16
5814 11:48:08.799647 best dqsien dly found for B1: ( 1, 2, 26)
5815 11:48:08.802652 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5816 11:48:08.806095 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5817 11:48:08.806555
5818 11:48:08.809465 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5819 11:48:08.813017 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5820 11:48:08.816447 [Gating] SW calibration Done
5821 11:48:08.816993 ==
5822 11:48:08.819803 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 11:48:08.822694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 11:48:08.826211 ==
5825 11:48:08.826781 RX Vref Scan: 0
5826 11:48:08.827301
5827 11:48:08.829595 RX Vref 0 -> 0, step: 1
5828 11:48:08.830240
5829 11:48:08.830859 RX Delay -80 -> 252, step: 8
5830 11:48:08.836719 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5831 11:48:08.839573 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5832 11:48:08.842646 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5833 11:48:08.846370 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5834 11:48:08.849729 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5835 11:48:08.852694 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5836 11:48:08.859638 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5837 11:48:08.862811 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5838 11:48:08.866265 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5839 11:48:08.869173 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5840 11:48:08.872514 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5841 11:48:08.879234 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5842 11:48:08.882701 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5843 11:48:08.885609 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5844 11:48:08.889094 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5845 11:48:08.892373 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5846 11:48:08.892456 ==
5847 11:48:08.895927 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 11:48:08.902117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 11:48:08.902230 ==
5850 11:48:08.902327 DQS Delay:
5851 11:48:08.905578 DQS0 = 0, DQS1 = 0
5852 11:48:08.905692 DQM Delay:
5853 11:48:08.905788 DQM0 = 94, DQM1 = 89
5854 11:48:08.909058 DQ Delay:
5855 11:48:08.911916 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5856 11:48:08.915422 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5857 11:48:08.918840 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =87
5858 11:48:08.922357 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5859 11:48:08.922470
5860 11:48:08.922565
5861 11:48:08.922655 ==
5862 11:48:08.925823 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 11:48:08.928682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 11:48:08.928777 ==
5865 11:48:08.928883
5866 11:48:08.928977
5867 11:48:08.932278 TX Vref Scan disable
5868 11:48:08.932355 == TX Byte 0 ==
5869 11:48:08.939024 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5870 11:48:08.942525 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5871 11:48:08.942629 == TX Byte 1 ==
5872 11:48:08.948928 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5873 11:48:08.952176 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5874 11:48:08.952280 ==
5875 11:48:08.955438 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 11:48:08.958843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 11:48:08.958950 ==
5878 11:48:08.959041
5879 11:48:08.962174
5880 11:48:08.962305 TX Vref Scan disable
5881 11:48:08.965009 == TX Byte 0 ==
5882 11:48:08.968358 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5883 11:48:08.975353 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5884 11:48:08.975459 == TX Byte 1 ==
5885 11:48:08.978268 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5886 11:48:08.985003 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5887 11:48:08.985109
5888 11:48:08.985200 [DATLAT]
5889 11:48:08.985295 Freq=933, CH1 RK1
5890 11:48:08.985381
5891 11:48:08.988530 DATLAT Default: 0xb
5892 11:48:08.988606 0, 0xFFFF, sum = 0
5893 11:48:08.992074 1, 0xFFFF, sum = 0
5894 11:48:08.992173 2, 0xFFFF, sum = 0
5895 11:48:08.995029 3, 0xFFFF, sum = 0
5896 11:48:08.998522 4, 0xFFFF, sum = 0
5897 11:48:08.998599 5, 0xFFFF, sum = 0
5898 11:48:09.001500 6, 0xFFFF, sum = 0
5899 11:48:09.001573 7, 0xFFFF, sum = 0
5900 11:48:09.005247 8, 0xFFFF, sum = 0
5901 11:48:09.005322 9, 0xFFFF, sum = 0
5902 11:48:09.008187 10, 0x0, sum = 1
5903 11:48:09.008326 11, 0x0, sum = 2
5904 11:48:09.011670 12, 0x0, sum = 3
5905 11:48:09.011775 13, 0x0, sum = 4
5906 11:48:09.011880 best_step = 11
5907 11:48:09.011972
5908 11:48:09.014909 ==
5909 11:48:09.015013 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 11:48:09.021529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 11:48:09.021631 ==
5912 11:48:09.021702 RX Vref Scan: 0
5913 11:48:09.021763
5914 11:48:09.025037 RX Vref 0 -> 0, step: 1
5915 11:48:09.025114
5916 11:48:09.028544 RX Delay -69 -> 252, step: 4
5917 11:48:09.031955 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5918 11:48:09.038355 iDelay=203, Bit 1, Center 88 (-9 ~ 186) 196
5919 11:48:09.041333 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5920 11:48:09.044691 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5921 11:48:09.048159 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5922 11:48:09.051646 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5923 11:48:09.058376 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5924 11:48:09.061300 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5925 11:48:09.064962 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5926 11:48:09.067942 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5927 11:48:09.071566 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5928 11:48:09.074850 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5929 11:48:09.081509 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5930 11:48:09.084747 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5931 11:48:09.088112 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5932 11:48:09.091217 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5933 11:48:09.091298 ==
5934 11:48:09.094732 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 11:48:09.101505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 11:48:09.101588 ==
5937 11:48:09.101652 DQS Delay:
5938 11:48:09.101712 DQS0 = 0, DQS1 = 0
5939 11:48:09.104932 DQM Delay:
5940 11:48:09.105013 DQM0 = 91, DQM1 = 90
5941 11:48:09.108076 DQ Delay:
5942 11:48:09.111022 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
5943 11:48:09.114569 DQ4 =88, DQ5 =102, DQ6 =102, DQ7 =88
5944 11:48:09.118091 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =82
5945 11:48:09.121058 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
5946 11:48:09.121190
5947 11:48:09.121285
5948 11:48:09.127665 [DQSOSCAuto] RK1, (LSB)MR18= 0x1023, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5949 11:48:09.131062 CH1 RK1: MR19=505, MR18=1023
5950 11:48:09.137602 CH1_RK1: MR19=0x505, MR18=0x1023, DQSOSC=410, MR23=63, INC=64, DEC=42
5951 11:48:09.141186 [RxdqsGatingPostProcess] freq 933
5952 11:48:09.144031 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5953 11:48:09.147595 best DQS0 dly(2T, 0.5T) = (0, 10)
5954 11:48:09.150921 best DQS1 dly(2T, 0.5T) = (0, 10)
5955 11:48:09.154234 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5956 11:48:09.157712 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5957 11:48:09.160842 best DQS0 dly(2T, 0.5T) = (0, 10)
5958 11:48:09.164208 best DQS1 dly(2T, 0.5T) = (0, 10)
5959 11:48:09.167759 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5960 11:48:09.170866 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5961 11:48:09.174392 Pre-setting of DQS Precalculation
5962 11:48:09.177322 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5963 11:48:09.187768 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5964 11:48:09.194313 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5965 11:48:09.194397
5966 11:48:09.194481
5967 11:48:09.197800 [Calibration Summary] 1866 Mbps
5968 11:48:09.197899 CH 0, Rank 0
5969 11:48:09.200659 SW Impedance : PASS
5970 11:48:09.200741 DUTY Scan : NO K
5971 11:48:09.204066 ZQ Calibration : PASS
5972 11:48:09.207398 Jitter Meter : NO K
5973 11:48:09.207482 CBT Training : PASS
5974 11:48:09.210637 Write leveling : PASS
5975 11:48:09.214141 RX DQS gating : PASS
5976 11:48:09.214226 RX DQ/DQS(RDDQC) : PASS
5977 11:48:09.217446 TX DQ/DQS : PASS
5978 11:48:09.220762 RX DATLAT : PASS
5979 11:48:09.220845 RX DQ/DQS(Engine): PASS
5980 11:48:09.223833 TX OE : NO K
5981 11:48:09.223915 All Pass.
5982 11:48:09.223999
5983 11:48:09.227120 CH 0, Rank 1
5984 11:48:09.227203 SW Impedance : PASS
5985 11:48:09.230674 DUTY Scan : NO K
5986 11:48:09.233577 ZQ Calibration : PASS
5987 11:48:09.233660 Jitter Meter : NO K
5988 11:48:09.237195 CBT Training : PASS
5989 11:48:09.237277 Write leveling : PASS
5990 11:48:09.240661 RX DQS gating : PASS
5991 11:48:09.243694 RX DQ/DQS(RDDQC) : PASS
5992 11:48:09.243776 TX DQ/DQS : PASS
5993 11:48:09.247131 RX DATLAT : PASS
5994 11:48:09.250592 RX DQ/DQS(Engine): PASS
5995 11:48:09.250674 TX OE : NO K
5996 11:48:09.253997 All Pass.
5997 11:48:09.254078
5998 11:48:09.254161 CH 1, Rank 0
5999 11:48:09.256940 SW Impedance : PASS
6000 11:48:09.257022 DUTY Scan : NO K
6001 11:48:09.260455 ZQ Calibration : PASS
6002 11:48:09.263755 Jitter Meter : NO K
6003 11:48:09.263837 CBT Training : PASS
6004 11:48:09.267043 Write leveling : PASS
6005 11:48:09.270382 RX DQS gating : PASS
6006 11:48:09.270464 RX DQ/DQS(RDDQC) : PASS
6007 11:48:09.273926 TX DQ/DQS : PASS
6008 11:48:09.277031 RX DATLAT : PASS
6009 11:48:09.277114 RX DQ/DQS(Engine): PASS
6010 11:48:09.280011 TX OE : NO K
6011 11:48:09.280093 All Pass.
6012 11:48:09.280192
6013 11:48:09.283558 CH 1, Rank 1
6014 11:48:09.283640 SW Impedance : PASS
6015 11:48:09.287081 DUTY Scan : NO K
6016 11:48:09.289972 ZQ Calibration : PASS
6017 11:48:09.290053 Jitter Meter : NO K
6018 11:48:09.293508 CBT Training : PASS
6019 11:48:09.293590 Write leveling : PASS
6020 11:48:09.296939 RX DQS gating : PASS
6021 11:48:09.300290 RX DQ/DQS(RDDQC) : PASS
6022 11:48:09.300373 TX DQ/DQS : PASS
6023 11:48:09.303360 RX DATLAT : PASS
6024 11:48:09.306833 RX DQ/DQS(Engine): PASS
6025 11:48:09.306915 TX OE : NO K
6026 11:48:09.309855 All Pass.
6027 11:48:09.309937
6028 11:48:09.310020 DramC Write-DBI off
6029 11:48:09.313421 PER_BANK_REFRESH: Hybrid Mode
6030 11:48:09.316352 TX_TRACKING: ON
6031 11:48:09.323060 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6032 11:48:09.326689 [FAST_K] Save calibration result to emmc
6033 11:48:09.329675 dramc_set_vcore_voltage set vcore to 650000
6034 11:48:09.333075 Read voltage for 400, 6
6035 11:48:09.333157 Vio18 = 0
6036 11:48:09.336351 Vcore = 650000
6037 11:48:09.336433 Vdram = 0
6038 11:48:09.336516 Vddq = 0
6039 11:48:09.340010 Vmddr = 0
6040 11:48:09.343193 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6041 11:48:09.349617 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6042 11:48:09.349701 MEM_TYPE=3, freq_sel=20
6043 11:48:09.353239 sv_algorithm_assistance_LP4_800
6044 11:48:09.359559 ============ PULL DRAM RESETB DOWN ============
6045 11:48:09.363147 ========== PULL DRAM RESETB DOWN end =========
6046 11:48:09.366720 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6047 11:48:09.369487 ===================================
6048 11:48:09.372764 LPDDR4 DRAM CONFIGURATION
6049 11:48:09.376163 ===================================
6050 11:48:09.379728 EX_ROW_EN[0] = 0x0
6051 11:48:09.379810 EX_ROW_EN[1] = 0x0
6052 11:48:09.382737 LP4Y_EN = 0x0
6053 11:48:09.382813 WORK_FSP = 0x0
6054 11:48:09.386271 WL = 0x2
6055 11:48:09.386345 RL = 0x2
6056 11:48:09.389664 BL = 0x2
6057 11:48:09.389745 RPST = 0x0
6058 11:48:09.392647 RD_PRE = 0x0
6059 11:48:09.392728 WR_PRE = 0x1
6060 11:48:09.396177 WR_PST = 0x0
6061 11:48:09.396295 DBI_WR = 0x0
6062 11:48:09.399646 DBI_RD = 0x0
6063 11:48:09.399717 OTF = 0x1
6064 11:48:09.402630 ===================================
6065 11:48:09.406177 ===================================
6066 11:48:09.409703 ANA top config
6067 11:48:09.412865 ===================================
6068 11:48:09.416087 DLL_ASYNC_EN = 0
6069 11:48:09.416171 ALL_SLAVE_EN = 1
6070 11:48:09.419577 NEW_RANK_MODE = 1
6071 11:48:09.422525 DLL_IDLE_MODE = 1
6072 11:48:09.425963 LP45_APHY_COMB_EN = 1
6073 11:48:09.426070 TX_ODT_DIS = 1
6074 11:48:09.429260 NEW_8X_MODE = 1
6075 11:48:09.432850 ===================================
6076 11:48:09.435824 ===================================
6077 11:48:09.439076 data_rate = 800
6078 11:48:09.442421 CKR = 1
6079 11:48:09.445891 DQ_P2S_RATIO = 4
6080 11:48:09.449497 ===================================
6081 11:48:09.452516 CA_P2S_RATIO = 4
6082 11:48:09.452595 DQ_CA_OPEN = 0
6083 11:48:09.455731 DQ_SEMI_OPEN = 1
6084 11:48:09.459231 CA_SEMI_OPEN = 1
6085 11:48:09.462384 CA_FULL_RATE = 0
6086 11:48:09.465630 DQ_CKDIV4_EN = 0
6087 11:48:09.469343 CA_CKDIV4_EN = 1
6088 11:48:09.469455 CA_PREDIV_EN = 0
6089 11:48:09.472864 PH8_DLY = 0
6090 11:48:09.475684 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6091 11:48:09.479108 DQ_AAMCK_DIV = 0
6092 11:48:09.482511 CA_AAMCK_DIV = 0
6093 11:48:09.486083 CA_ADMCK_DIV = 4
6094 11:48:09.486237 DQ_TRACK_CA_EN = 0
6095 11:48:09.489024 CA_PICK = 800
6096 11:48:09.492426 CA_MCKIO = 400
6097 11:48:09.495935 MCKIO_SEMI = 400
6098 11:48:09.498915 PLL_FREQ = 3016
6099 11:48:09.502343 DQ_UI_PI_RATIO = 32
6100 11:48:09.505865 CA_UI_PI_RATIO = 32
6101 11:48:09.509316 ===================================
6102 11:48:09.512261 ===================================
6103 11:48:09.512443 memory_type:LPDDR4
6104 11:48:09.515664 GP_NUM : 10
6105 11:48:09.518924 SRAM_EN : 1
6106 11:48:09.519094 MD32_EN : 0
6107 11:48:09.522295 ===================================
6108 11:48:09.525644 [ANA_INIT] >>>>>>>>>>>>>>
6109 11:48:09.529142 <<<<<< [CONFIGURE PHASE]: ANA_TX
6110 11:48:09.532017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6111 11:48:09.535408 ===================================
6112 11:48:09.538849 data_rate = 800,PCW = 0X7400
6113 11:48:09.542412 ===================================
6114 11:48:09.545320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6115 11:48:09.548735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 11:48:09.561804 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6117 11:48:09.565136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6118 11:48:09.568536 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6119 11:48:09.571938 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6120 11:48:09.575048 [ANA_INIT] flow start
6121 11:48:09.578257 [ANA_INIT] PLL >>>>>>>>
6122 11:48:09.578366 [ANA_INIT] PLL <<<<<<<<
6123 11:48:09.581478 [ANA_INIT] MIDPI >>>>>>>>
6124 11:48:09.584958 [ANA_INIT] MIDPI <<<<<<<<
6125 11:48:09.585073 [ANA_INIT] DLL >>>>>>>>
6126 11:48:09.588449 [ANA_INIT] flow end
6127 11:48:09.591458 ============ LP4 DIFF to SE enter ============
6128 11:48:09.594940 ============ LP4 DIFF to SE exit ============
6129 11:48:09.597940 [ANA_INIT] <<<<<<<<<<<<<
6130 11:48:09.601570 [Flow] Enable top DCM control >>>>>
6131 11:48:09.605116 [Flow] Enable top DCM control <<<<<
6132 11:48:09.608211 Enable DLL master slave shuffle
6133 11:48:09.614740 ==============================================================
6134 11:48:09.614893 Gating Mode config
6135 11:48:09.621690 ==============================================================
6136 11:48:09.621822 Config description:
6137 11:48:09.631241 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6138 11:48:09.638214 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6139 11:48:09.644663 SELPH_MODE 0: By rank 1: By Phase
6140 11:48:09.647638 ==============================================================
6141 11:48:09.651082 GAT_TRACK_EN = 0
6142 11:48:09.654532 RX_GATING_MODE = 2
6143 11:48:09.657919 RX_GATING_TRACK_MODE = 2
6144 11:48:09.661436 SELPH_MODE = 1
6145 11:48:09.664146 PICG_EARLY_EN = 1
6146 11:48:09.667958 VALID_LAT_VALUE = 1
6147 11:48:09.674406 ==============================================================
6148 11:48:09.677867 Enter into Gating configuration >>>>
6149 11:48:09.680840 Exit from Gating configuration <<<<
6150 11:48:09.684197 Enter into DVFS_PRE_config >>>>>
6151 11:48:09.694170 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6152 11:48:09.697218 Exit from DVFS_PRE_config <<<<<
6153 11:48:09.701044 Enter into PICG configuration >>>>
6154 11:48:09.703928 Exit from PICG configuration <<<<
6155 11:48:09.707463 [RX_INPUT] configuration >>>>>
6156 11:48:09.707579 [RX_INPUT] configuration <<<<<
6157 11:48:09.714011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6158 11:48:09.720570 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6159 11:48:09.726852 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6160 11:48:09.730325 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6161 11:48:09.737159 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6162 11:48:09.743633 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6163 11:48:09.747084 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6164 11:48:09.750671 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6165 11:48:09.757121 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6166 11:48:09.760431 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6167 11:48:09.763227 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6168 11:48:09.770150 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6169 11:48:09.773562 ===================================
6170 11:48:09.773651 LPDDR4 DRAM CONFIGURATION
6171 11:48:09.776915 ===================================
6172 11:48:09.780013 EX_ROW_EN[0] = 0x0
6173 11:48:09.783232 EX_ROW_EN[1] = 0x0
6174 11:48:09.783335 LP4Y_EN = 0x0
6175 11:48:09.786988 WORK_FSP = 0x0
6176 11:48:09.787099 WL = 0x2
6177 11:48:09.789988 RL = 0x2
6178 11:48:09.790099 BL = 0x2
6179 11:48:09.793561 RPST = 0x0
6180 11:48:09.793702 RD_PRE = 0x0
6181 11:48:09.796550 WR_PRE = 0x1
6182 11:48:09.796696 WR_PST = 0x0
6183 11:48:09.799970 DBI_WR = 0x0
6184 11:48:09.800121 DBI_RD = 0x0
6185 11:48:09.803141 OTF = 0x1
6186 11:48:09.806736 ===================================
6187 11:48:09.809985 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6188 11:48:09.813347 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6189 11:48:09.819775 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6190 11:48:09.823251 ===================================
6191 11:48:09.823422 LPDDR4 DRAM CONFIGURATION
6192 11:48:09.826167 ===================================
6193 11:48:09.829645 EX_ROW_EN[0] = 0x10
6194 11:48:09.833043 EX_ROW_EN[1] = 0x0
6195 11:48:09.833154 LP4Y_EN = 0x0
6196 11:48:09.836555 WORK_FSP = 0x0
6197 11:48:09.836658 WL = 0x2
6198 11:48:09.839462 RL = 0x2
6199 11:48:09.839563 BL = 0x2
6200 11:48:09.842753 RPST = 0x0
6201 11:48:09.842870 RD_PRE = 0x0
6202 11:48:09.845999 WR_PRE = 0x1
6203 11:48:09.846113 WR_PST = 0x0
6204 11:48:09.849489 DBI_WR = 0x0
6205 11:48:09.849587 DBI_RD = 0x0
6206 11:48:09.853001 OTF = 0x1
6207 11:48:09.855939 ===================================
6208 11:48:09.862414 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6209 11:48:09.866257 nWR fixed to 30
6210 11:48:09.866372 [ModeRegInit_LP4] CH0 RK0
6211 11:48:09.869039 [ModeRegInit_LP4] CH0 RK1
6212 11:48:09.872712 [ModeRegInit_LP4] CH1 RK0
6213 11:48:09.875657 [ModeRegInit_LP4] CH1 RK1
6214 11:48:09.875755 match AC timing 19
6215 11:48:09.882518 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6216 11:48:09.885966 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6217 11:48:09.888876 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6218 11:48:09.895903 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6219 11:48:09.898926 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6220 11:48:09.899096 ==
6221 11:48:09.902363 Dram Type= 6, Freq= 0, CH_0, rank 0
6222 11:48:09.905374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6223 11:48:09.905563 ==
6224 11:48:09.912135 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6225 11:48:09.919139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6226 11:48:09.922561 [CA 0] Center 36 (8~64) winsize 57
6227 11:48:09.925301 [CA 1] Center 36 (8~64) winsize 57
6228 11:48:09.928912 [CA 2] Center 36 (8~64) winsize 57
6229 11:48:09.928999 [CA 3] Center 36 (8~64) winsize 57
6230 11:48:09.931931 [CA 4] Center 36 (8~64) winsize 57
6231 11:48:09.935283 [CA 5] Center 36 (8~64) winsize 57
6232 11:48:09.935397
6233 11:48:09.938787 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6234 11:48:09.941711
6235 11:48:09.945263 [CATrainingPosCal] consider 1 rank data
6236 11:48:09.945362 u2DelayCellTimex100 = 270/100 ps
6237 11:48:09.951984 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 11:48:09.955048 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 11:48:09.958777 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 11:48:09.961702 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 11:48:09.965183 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 11:48:09.968710 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 11:48:09.968793
6244 11:48:09.971693 CA PerBit enable=1, Macro0, CA PI delay=36
6245 11:48:09.971791
6246 11:48:09.974943 [CBTSetCACLKResult] CA Dly = 36
6247 11:48:09.978484 CS Dly: 1 (0~32)
6248 11:48:09.978598 ==
6249 11:48:09.982047 Dram Type= 6, Freq= 0, CH_0, rank 1
6250 11:48:09.984772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 11:48:09.984853 ==
6252 11:48:09.991650 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6253 11:48:09.995119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6254 11:48:09.997901 [CA 0] Center 36 (8~64) winsize 57
6255 11:48:10.001561 [CA 1] Center 36 (8~64) winsize 57
6256 11:48:10.004984 [CA 2] Center 36 (8~64) winsize 57
6257 11:48:10.008091 [CA 3] Center 36 (8~64) winsize 57
6258 11:48:10.011497 [CA 4] Center 36 (8~64) winsize 57
6259 11:48:10.014830 [CA 5] Center 36 (8~64) winsize 57
6260 11:48:10.014940
6261 11:48:10.018146 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6262 11:48:10.018228
6263 11:48:10.021417 [CATrainingPosCal] consider 2 rank data
6264 11:48:10.024870 u2DelayCellTimex100 = 270/100 ps
6265 11:48:10.028119 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 11:48:10.031613 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 11:48:10.037954 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 11:48:10.040964 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 11:48:10.044658 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 11:48:10.048040 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 11:48:10.048127
6272 11:48:10.051559 CA PerBit enable=1, Macro0, CA PI delay=36
6273 11:48:10.051673
6274 11:48:10.054453 [CBTSetCACLKResult] CA Dly = 36
6275 11:48:10.054547 CS Dly: 1 (0~32)
6276 11:48:10.057785
6277 11:48:10.061001 ----->DramcWriteLeveling(PI) begin...
6278 11:48:10.061138 ==
6279 11:48:10.064185 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 11:48:10.067775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 11:48:10.067911 ==
6282 11:48:10.070812 Write leveling (Byte 0): 40 => 8
6283 11:48:10.074446 Write leveling (Byte 1): 40 => 8
6284 11:48:10.077903 DramcWriteLeveling(PI) end<-----
6285 11:48:10.078007
6286 11:48:10.078086 ==
6287 11:48:10.081271 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 11:48:10.083994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 11:48:10.084138 ==
6290 11:48:10.087680 [Gating] SW mode calibration
6291 11:48:10.094090 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6292 11:48:10.100690 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6293 11:48:10.104075 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 11:48:10.107416 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6295 11:48:10.114079 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 11:48:10.117070 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6297 11:48:10.120530 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 11:48:10.127065 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 11:48:10.130343 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 11:48:10.133784 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 11:48:10.140663 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 11:48:10.140771 Total UI for P1: 0, mck2ui 16
6303 11:48:10.146838 best dqsien dly found for B0: ( 0, 14, 24)
6304 11:48:10.146966 Total UI for P1: 0, mck2ui 16
6305 11:48:10.150557 best dqsien dly found for B1: ( 0, 14, 24)
6306 11:48:10.157000 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6307 11:48:10.160552 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6308 11:48:10.160677
6309 11:48:10.163417 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 11:48:10.166860 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6311 11:48:10.170144 [Gating] SW calibration Done
6312 11:48:10.170301 ==
6313 11:48:10.173556 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 11:48:10.176609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 11:48:10.176843 ==
6316 11:48:10.180044 RX Vref Scan: 0
6317 11:48:10.180290
6318 11:48:10.180533 RX Vref 0 -> 0, step: 1
6319 11:48:10.180718
6320 11:48:10.183536 RX Delay -410 -> 252, step: 16
6321 11:48:10.190240 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6322 11:48:10.193213 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6323 11:48:10.196611 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6324 11:48:10.200184 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6325 11:48:10.206572 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6326 11:48:10.209600 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6327 11:48:10.213117 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6328 11:48:10.216387 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6329 11:48:10.223379 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6330 11:48:10.226238 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6331 11:48:10.229845 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6332 11:48:10.233242 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6333 11:48:10.239541 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6334 11:48:10.242727 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6335 11:48:10.246293 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6336 11:48:10.252649 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6337 11:48:10.252983 ==
6338 11:48:10.256189 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 11:48:10.259118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 11:48:10.259422 ==
6341 11:48:10.259668 DQS Delay:
6342 11:48:10.262711 DQS0 = 59, DQS1 = 59
6343 11:48:10.263203 DQM Delay:
6344 11:48:10.266314 DQM0 = 18, DQM1 = 11
6345 11:48:10.266634 DQ Delay:
6346 11:48:10.269085 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6347 11:48:10.272545 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6348 11:48:10.275738 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6349 11:48:10.279151 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6350 11:48:10.279353
6351 11:48:10.279478
6352 11:48:10.279593 ==
6353 11:48:10.282390 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 11:48:10.285393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 11:48:10.285531 ==
6356 11:48:10.285636
6357 11:48:10.285733
6358 11:48:10.288877 TX Vref Scan disable
6359 11:48:10.292257 == TX Byte 0 ==
6360 11:48:10.295608 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 11:48:10.298989 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 11:48:10.302423 == TX Byte 1 ==
6363 11:48:10.305304 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 11:48:10.308931 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 11:48:10.309038 ==
6366 11:48:10.311922 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 11:48:10.315449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 11:48:10.315540 ==
6369 11:48:10.315606
6370 11:48:10.318964
6371 11:48:10.319082 TX Vref Scan disable
6372 11:48:10.322377 == TX Byte 0 ==
6373 11:48:10.325294 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6374 11:48:10.328571 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6375 11:48:10.331754 == TX Byte 1 ==
6376 11:48:10.335267 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6377 11:48:10.338891 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6378 11:48:10.339000
6379 11:48:10.339092 [DATLAT]
6380 11:48:10.341813 Freq=400, CH0 RK0
6381 11:48:10.341895
6382 11:48:10.345186 DATLAT Default: 0xf
6383 11:48:10.345268 0, 0xFFFF, sum = 0
6384 11:48:10.348525 1, 0xFFFF, sum = 0
6385 11:48:10.348619 2, 0xFFFF, sum = 0
6386 11:48:10.351715 3, 0xFFFF, sum = 0
6387 11:48:10.351824 4, 0xFFFF, sum = 0
6388 11:48:10.355124 5, 0xFFFF, sum = 0
6389 11:48:10.355226 6, 0xFFFF, sum = 0
6390 11:48:10.358484 7, 0xFFFF, sum = 0
6391 11:48:10.358565 8, 0xFFFF, sum = 0
6392 11:48:10.361539 9, 0xFFFF, sum = 0
6393 11:48:10.361651 10, 0xFFFF, sum = 0
6394 11:48:10.364893 11, 0xFFFF, sum = 0
6395 11:48:10.364994 12, 0xFFFF, sum = 0
6396 11:48:10.368396 13, 0x0, sum = 1
6397 11:48:10.368484 14, 0x0, sum = 2
6398 11:48:10.371873 15, 0x0, sum = 3
6399 11:48:10.371989 16, 0x0, sum = 4
6400 11:48:10.374744 best_step = 14
6401 11:48:10.374865
6402 11:48:10.374970 ==
6403 11:48:10.378296 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 11:48:10.381918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 11:48:10.382019 ==
6406 11:48:10.385145 RX Vref Scan: 1
6407 11:48:10.385324
6408 11:48:10.385487 RX Vref 0 -> 0, step: 1
6409 11:48:10.385627
6410 11:48:10.388156 RX Delay -359 -> 252, step: 8
6411 11:48:10.388326
6412 11:48:10.392049 Set Vref, RX VrefLevel [Byte0]: 61
6413 11:48:10.394799 [Byte1]: 52
6414 11:48:10.399361
6415 11:48:10.399503 Final RX Vref Byte 0 = 61 to rank0
6416 11:48:10.402922 Final RX Vref Byte 1 = 52 to rank0
6417 11:48:10.406484 Final RX Vref Byte 0 = 61 to rank1
6418 11:48:10.409670 Final RX Vref Byte 1 = 52 to rank1==
6419 11:48:10.412618 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 11:48:10.419250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 11:48:10.419358 ==
6422 11:48:10.419434 DQS Delay:
6423 11:48:10.419495 DQS0 = 60, DQS1 = 68
6424 11:48:10.422602 DQM Delay:
6425 11:48:10.422707 DQM0 = 14, DQM1 = 13
6426 11:48:10.426211 DQ Delay:
6427 11:48:10.429148 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6428 11:48:10.429228 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6429 11:48:10.432680 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6430 11:48:10.435968 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6431 11:48:10.436072
6432 11:48:10.439063
6433 11:48:10.445548 [DQSOSCAuto] RK0, (LSB)MR18= 0x8785, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6434 11:48:10.449030 CH0 RK0: MR19=C0C, MR18=8785
6435 11:48:10.455939 CH0_RK0: MR19=0xC0C, MR18=0x8785, DQSOSC=392, MR23=63, INC=384, DEC=256
6436 11:48:10.456053 ==
6437 11:48:10.459237 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 11:48:10.462231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 11:48:10.462311 ==
6440 11:48:10.465552 [Gating] SW mode calibration
6441 11:48:10.472105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6442 11:48:10.479127 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6443 11:48:10.482029 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 11:48:10.485464 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6445 11:48:10.492490 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 11:48:10.495803 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 11:48:10.498661 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 11:48:10.505439 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 11:48:10.508955 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 11:48:10.512174 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 11:48:10.518665 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 11:48:10.518748 Total UI for P1: 0, mck2ui 16
6453 11:48:10.522101 best dqsien dly found for B0: ( 0, 14, 24)
6454 11:48:10.525585 Total UI for P1: 0, mck2ui 16
6455 11:48:10.528599 best dqsien dly found for B1: ( 0, 14, 24)
6456 11:48:10.534981 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6457 11:48:10.538430 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6458 11:48:10.538535
6459 11:48:10.541983 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 11:48:10.545120 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6461 11:48:10.548360 [Gating] SW calibration Done
6462 11:48:10.548467 ==
6463 11:48:10.551696 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 11:48:10.555102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 11:48:10.555219 ==
6466 11:48:10.558741 RX Vref Scan: 0
6467 11:48:10.558818
6468 11:48:10.558900 RX Vref 0 -> 0, step: 1
6469 11:48:10.558988
6470 11:48:10.561699 RX Delay -410 -> 252, step: 16
6471 11:48:10.568676 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6472 11:48:10.571532 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6473 11:48:10.574914 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6474 11:48:10.578369 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6475 11:48:10.581981 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6476 11:48:10.588276 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6477 11:48:10.591665 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6478 11:48:10.595211 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6479 11:48:10.598736 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6480 11:48:10.604907 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6481 11:48:10.608140 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6482 11:48:10.611545 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6483 11:48:10.618315 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6484 11:48:10.621322 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6485 11:48:10.625071 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6486 11:48:10.628039 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6487 11:48:10.628112 ==
6488 11:48:10.631470 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 11:48:10.638905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 11:48:10.639076 ==
6491 11:48:10.639165 DQS Delay:
6492 11:48:10.641705 DQS0 = 59, DQS1 = 59
6493 11:48:10.641878 DQM Delay:
6494 11:48:10.644843 DQM0 = 17, DQM1 = 10
6495 11:48:10.644970 DQ Delay:
6496 11:48:10.647987 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6497 11:48:10.651309 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6498 11:48:10.654927 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6499 11:48:10.658646 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6500 11:48:10.659230
6501 11:48:10.659594
6502 11:48:10.659929 ==
6503 11:48:10.661432 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 11:48:10.665178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 11:48:10.665775 ==
6506 11:48:10.666149
6507 11:48:10.666489
6508 11:48:10.668027 TX Vref Scan disable
6509 11:48:10.668605 == TX Byte 0 ==
6510 11:48:10.675003 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6511 11:48:10.678129 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6512 11:48:10.678640 == TX Byte 1 ==
6513 11:48:10.684921 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6514 11:48:10.687732 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6515 11:48:10.688342 ==
6516 11:48:10.691330 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 11:48:10.694851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 11:48:10.695412 ==
6519 11:48:10.695812
6520 11:48:10.696185
6521 11:48:10.698168 TX Vref Scan disable
6522 11:48:10.698620 == TX Byte 0 ==
6523 11:48:10.704777 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6524 11:48:10.707991 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6525 11:48:10.708523 == TX Byte 1 ==
6526 11:48:10.714759 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6527 11:48:10.717934 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6528 11:48:10.718570
6529 11:48:10.719142 [DATLAT]
6530 11:48:10.721130 Freq=400, CH0 RK1
6531 11:48:10.721671
6532 11:48:10.722267 DATLAT Default: 0xe
6533 11:48:10.724493 0, 0xFFFF, sum = 0
6534 11:48:10.725246 1, 0xFFFF, sum = 0
6535 11:48:10.727498 2, 0xFFFF, sum = 0
6536 11:48:10.728065 3, 0xFFFF, sum = 0
6537 11:48:10.730914 4, 0xFFFF, sum = 0
6538 11:48:10.731384 5, 0xFFFF, sum = 0
6539 11:48:10.734631 6, 0xFFFF, sum = 0
6540 11:48:10.735103 7, 0xFFFF, sum = 0
6541 11:48:10.737824 8, 0xFFFF, sum = 0
6542 11:48:10.741263 9, 0xFFFF, sum = 0
6543 11:48:10.741930 10, 0xFFFF, sum = 0
6544 11:48:10.744171 11, 0xFFFF, sum = 0
6545 11:48:10.744692 12, 0xFFFF, sum = 0
6546 11:48:10.747696 13, 0x0, sum = 1
6547 11:48:10.748399 14, 0x0, sum = 2
6548 11:48:10.751056 15, 0x0, sum = 3
6549 11:48:10.751669 16, 0x0, sum = 4
6550 11:48:10.752304 best_step = 14
6551 11:48:10.752865
6552 11:48:10.754103 ==
6553 11:48:10.757907 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 11:48:10.761191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 11:48:10.761682 ==
6556 11:48:10.762263 RX Vref Scan: 0
6557 11:48:10.762818
6558 11:48:10.764100 RX Vref 0 -> 0, step: 1
6559 11:48:10.764653
6560 11:48:10.767405 RX Delay -359 -> 252, step: 8
6561 11:48:10.774763 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6562 11:48:10.777763 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6563 11:48:10.781022 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6564 11:48:10.784815 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6565 11:48:10.791376 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6566 11:48:10.794686 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6567 11:48:10.798246 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6568 11:48:10.801607 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6569 11:48:10.808156 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6570 11:48:10.811198 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6571 11:48:10.814556 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6572 11:48:10.818018 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6573 11:48:10.824552 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6574 11:48:10.827881 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6575 11:48:10.831055 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6576 11:48:10.837708 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6577 11:48:10.838173 ==
6578 11:48:10.841107 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 11:48:10.844131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 11:48:10.844665 ==
6581 11:48:10.845031 DQS Delay:
6582 11:48:10.847602 DQS0 = 60, DQS1 = 72
6583 11:48:10.848059 DQM Delay:
6584 11:48:10.851048 DQM0 = 11, DQM1 = 17
6585 11:48:10.851508 DQ Delay:
6586 11:48:10.854252 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6587 11:48:10.857523 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6588 11:48:10.861080 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6589 11:48:10.864596 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6590 11:48:10.865058
6591 11:48:10.865531
6592 11:48:10.871099 [DQSOSCAuto] RK1, (LSB)MR18= 0xca7e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6593 11:48:10.874502 CH0 RK1: MR19=C0C, MR18=CA7E
6594 11:48:10.880905 CH0_RK1: MR19=0xC0C, MR18=0xCA7E, DQSOSC=384, MR23=63, INC=400, DEC=267
6595 11:48:10.884528 [RxdqsGatingPostProcess] freq 400
6596 11:48:10.891003 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6597 11:48:10.891577 best DQS0 dly(2T, 0.5T) = (0, 10)
6598 11:48:10.894343 best DQS1 dly(2T, 0.5T) = (0, 10)
6599 11:48:10.897507 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6600 11:48:10.900662 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6601 11:48:10.903916 best DQS0 dly(2T, 0.5T) = (0, 10)
6602 11:48:10.907449 best DQS1 dly(2T, 0.5T) = (0, 10)
6603 11:48:10.910517 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6604 11:48:10.914141 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6605 11:48:10.917589 Pre-setting of DQS Precalculation
6606 11:48:10.924071 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6607 11:48:10.924729 ==
6608 11:48:10.927141 Dram Type= 6, Freq= 0, CH_1, rank 0
6609 11:48:10.930698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 11:48:10.931279 ==
6611 11:48:10.937126 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6612 11:48:10.940458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6613 11:48:10.944106 [CA 0] Center 36 (8~64) winsize 57
6614 11:48:10.947248 [CA 1] Center 36 (8~64) winsize 57
6615 11:48:10.950801 [CA 2] Center 36 (8~64) winsize 57
6616 11:48:10.953650 [CA 3] Center 36 (8~64) winsize 57
6617 11:48:10.957333 [CA 4] Center 36 (8~64) winsize 57
6618 11:48:10.960276 [CA 5] Center 36 (8~64) winsize 57
6619 11:48:10.960734
6620 11:48:10.963644 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6621 11:48:10.964099
6622 11:48:10.967326 [CATrainingPosCal] consider 1 rank data
6623 11:48:10.970229 u2DelayCellTimex100 = 270/100 ps
6624 11:48:10.973577 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 11:48:10.977272 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 11:48:10.980009 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 11:48:10.983894 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 11:48:10.990379 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 11:48:10.993437 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 11:48:10.993975
6631 11:48:10.997315 CA PerBit enable=1, Macro0, CA PI delay=36
6632 11:48:10.997775
6633 11:48:11.000593 [CBTSetCACLKResult] CA Dly = 36
6634 11:48:11.001050 CS Dly: 1 (0~32)
6635 11:48:11.001403 ==
6636 11:48:11.003570 Dram Type= 6, Freq= 0, CH_1, rank 1
6637 11:48:11.010583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 11:48:11.011139 ==
6639 11:48:11.013664 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6640 11:48:11.020590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6641 11:48:11.023682 [CA 0] Center 36 (8~64) winsize 57
6642 11:48:11.026910 [CA 1] Center 36 (8~64) winsize 57
6643 11:48:11.030449 [CA 2] Center 36 (8~64) winsize 57
6644 11:48:11.033491 [CA 3] Center 36 (8~64) winsize 57
6645 11:48:11.036945 [CA 4] Center 36 (8~64) winsize 57
6646 11:48:11.040489 [CA 5] Center 36 (8~64) winsize 57
6647 11:48:11.040949
6648 11:48:11.043397 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6649 11:48:11.043945
6650 11:48:11.046754 [CATrainingPosCal] consider 2 rank data
6651 11:48:11.050415 u2DelayCellTimex100 = 270/100 ps
6652 11:48:11.053633 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 11:48:11.056763 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 11:48:11.060238 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 11:48:11.063598 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 11:48:11.066810 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 11:48:11.069834 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 11:48:11.070290
6659 11:48:11.076472 CA PerBit enable=1, Macro0, CA PI delay=36
6660 11:48:11.077057
6661 11:48:11.079871 [CBTSetCACLKResult] CA Dly = 36
6662 11:48:11.080415 CS Dly: 1 (0~32)
6663 11:48:11.080791
6664 11:48:11.083303 ----->DramcWriteLeveling(PI) begin...
6665 11:48:11.083771 ==
6666 11:48:11.086339 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 11:48:11.089954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 11:48:11.090419 ==
6669 11:48:11.092990 Write leveling (Byte 0): 40 => 8
6670 11:48:11.096302 Write leveling (Byte 1): 40 => 8
6671 11:48:11.099437 DramcWriteLeveling(PI) end<-----
6672 11:48:11.099897
6673 11:48:11.100320 ==
6674 11:48:11.102902 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 11:48:11.109631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 11:48:11.110235 ==
6677 11:48:11.110757 [Gating] SW mode calibration
6678 11:48:11.119338 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6679 11:48:11.122833 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6680 11:48:11.125918 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6681 11:48:11.132640 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6682 11:48:11.136080 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 11:48:11.139563 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 11:48:11.145775 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 11:48:11.149399 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 11:48:11.152829 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 11:48:11.159563 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 11:48:11.162913 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 11:48:11.166333 Total UI for P1: 0, mck2ui 16
6690 11:48:11.169198 best dqsien dly found for B0: ( 0, 14, 24)
6691 11:48:11.172682 Total UI for P1: 0, mck2ui 16
6692 11:48:11.175888 best dqsien dly found for B1: ( 0, 14, 24)
6693 11:48:11.179301 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6694 11:48:11.182390 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6695 11:48:11.182856
6696 11:48:11.186036 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 11:48:11.192434 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6698 11:48:11.192907 [Gating] SW calibration Done
6699 11:48:11.193403 ==
6700 11:48:11.195950 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 11:48:11.202547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 11:48:11.203147 ==
6703 11:48:11.203621 RX Vref Scan: 0
6704 11:48:11.204184
6705 11:48:11.205536 RX Vref 0 -> 0, step: 1
6706 11:48:11.206089
6707 11:48:11.209159 RX Delay -410 -> 252, step: 16
6708 11:48:11.212335 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6709 11:48:11.215764 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6710 11:48:11.222383 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6711 11:48:11.225455 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6712 11:48:11.229073 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6713 11:48:11.232031 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6714 11:48:11.235490 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6715 11:48:11.242468 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6716 11:48:11.245583 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6717 11:48:11.248870 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6718 11:48:11.252540 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6719 11:48:11.258699 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6720 11:48:11.262031 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6721 11:48:11.265437 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6722 11:48:11.272291 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6723 11:48:11.275763 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6724 11:48:11.276359 ==
6725 11:48:11.278632 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 11:48:11.281830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 11:48:11.282153 ==
6728 11:48:11.285274 DQS Delay:
6729 11:48:11.285710 DQS0 = 51, DQS1 = 67
6730 11:48:11.286063 DQM Delay:
6731 11:48:11.288642 DQM0 = 12, DQM1 = 17
6732 11:48:11.288971 DQ Delay:
6733 11:48:11.292094 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6734 11:48:11.294932 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6735 11:48:11.298429 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6736 11:48:11.301823 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6737 11:48:11.302014
6738 11:48:11.302168
6739 11:48:11.302314 ==
6740 11:48:11.305319 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 11:48:11.308179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 11:48:11.311564 ==
6743 11:48:11.311653
6744 11:48:11.311719
6745 11:48:11.311779 TX Vref Scan disable
6746 11:48:11.315050 == TX Byte 0 ==
6747 11:48:11.317935 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 11:48:11.321323 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 11:48:11.324540 == TX Byte 1 ==
6750 11:48:11.328132 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 11:48:11.331497 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 11:48:11.331580 ==
6753 11:48:11.334706 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 11:48:11.340984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 11:48:11.341067 ==
6756 11:48:11.341133
6757 11:48:11.341198
6758 11:48:11.341256 TX Vref Scan disable
6759 11:48:11.344488 == TX Byte 0 ==
6760 11:48:11.347967 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 11:48:11.351390 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 11:48:11.354678 == TX Byte 1 ==
6763 11:48:11.358019 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 11:48:11.361207 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 11:48:11.361284
6766 11:48:11.364213 [DATLAT]
6767 11:48:11.364289 Freq=400, CH1 RK0
6768 11:48:11.364353
6769 11:48:11.367502 DATLAT Default: 0xf
6770 11:48:11.367579 0, 0xFFFF, sum = 0
6771 11:48:11.371092 1, 0xFFFF, sum = 0
6772 11:48:11.371205 2, 0xFFFF, sum = 0
6773 11:48:11.374292 3, 0xFFFF, sum = 0
6774 11:48:11.374396 4, 0xFFFF, sum = 0
6775 11:48:11.377640 5, 0xFFFF, sum = 0
6776 11:48:11.377722 6, 0xFFFF, sum = 0
6777 11:48:11.381092 7, 0xFFFF, sum = 0
6778 11:48:11.381195 8, 0xFFFF, sum = 0
6779 11:48:11.384519 9, 0xFFFF, sum = 0
6780 11:48:11.384594 10, 0xFFFF, sum = 0
6781 11:48:11.387893 11, 0xFFFF, sum = 0
6782 11:48:11.390860 12, 0xFFFF, sum = 0
6783 11:48:11.390972 13, 0x0, sum = 1
6784 11:48:11.391066 14, 0x0, sum = 2
6785 11:48:11.394286 15, 0x0, sum = 3
6786 11:48:11.394361 16, 0x0, sum = 4
6787 11:48:11.397810 best_step = 14
6788 11:48:11.397910
6789 11:48:11.398003 ==
6790 11:48:11.400713 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 11:48:11.404344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 11:48:11.404428 ==
6793 11:48:11.407770 RX Vref Scan: 1
6794 11:48:11.407846
6795 11:48:11.407909 RX Vref 0 -> 0, step: 1
6796 11:48:11.407969
6797 11:48:11.410802 RX Delay -375 -> 252, step: 8
6798 11:48:11.410901
6799 11:48:11.414259 Set Vref, RX VrefLevel [Byte0]: 54
6800 11:48:11.417709 [Byte1]: 51
6801 11:48:11.422486
6802 11:48:11.422590 Final RX Vref Byte 0 = 54 to rank0
6803 11:48:11.425935 Final RX Vref Byte 1 = 51 to rank0
6804 11:48:11.429435 Final RX Vref Byte 0 = 54 to rank1
6805 11:48:11.432427 Final RX Vref Byte 1 = 51 to rank1==
6806 11:48:11.435938 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 11:48:11.442759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 11:48:11.442864 ==
6809 11:48:11.442957 DQS Delay:
6810 11:48:11.445734 DQS0 = 56, DQS1 = 64
6811 11:48:11.445833 DQM Delay:
6812 11:48:11.445931 DQM0 = 13, DQM1 = 11
6813 11:48:11.449231 DQ Delay:
6814 11:48:11.452403 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6815 11:48:11.452484 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6816 11:48:11.456024 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6817 11:48:11.459244 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6818 11:48:11.459343
6819 11:48:11.462232
6820 11:48:11.468957 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6821 11:48:11.472607 CH1 RK0: MR19=C0C, MR18=5B6E
6822 11:48:11.479113 CH1_RK0: MR19=0xC0C, MR18=0x5B6E, DQSOSC=395, MR23=63, INC=378, DEC=252
6823 11:48:11.479193 ==
6824 11:48:11.482478 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 11:48:11.485993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 11:48:11.486089 ==
6827 11:48:11.488821 [Gating] SW mode calibration
6828 11:48:11.495635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6829 11:48:11.502088 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6830 11:48:11.505609 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6831 11:48:11.508937 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6832 11:48:11.512413 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 11:48:11.518898 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6834 11:48:11.522360 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 11:48:11.525268 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 11:48:11.532383 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 11:48:11.535367 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 11:48:11.538921 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 11:48:11.542325 Total UI for P1: 0, mck2ui 16
6840 11:48:11.545210 best dqsien dly found for B0: ( 0, 14, 24)
6841 11:48:11.548865 Total UI for P1: 0, mck2ui 16
6842 11:48:11.551675 best dqsien dly found for B1: ( 0, 14, 24)
6843 11:48:11.555187 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6844 11:48:11.561639 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6845 11:48:11.561744
6846 11:48:11.565330 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 11:48:11.568606 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6848 11:48:11.571759 [Gating] SW calibration Done
6849 11:48:11.571863 ==
6850 11:48:11.575263 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 11:48:11.578562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 11:48:11.578639 ==
6853 11:48:11.581792 RX Vref Scan: 0
6854 11:48:11.581895
6855 11:48:11.581985 RX Vref 0 -> 0, step: 1
6856 11:48:11.582071
6857 11:48:11.585263 RX Delay -410 -> 252, step: 16
6858 11:48:11.588340 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6859 11:48:11.594750 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6860 11:48:11.598252 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6861 11:48:11.601927 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6862 11:48:11.605011 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6863 11:48:11.611276 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6864 11:48:11.614574 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6865 11:48:11.618042 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6866 11:48:11.621410 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6867 11:48:11.628412 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6868 11:48:11.631370 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6869 11:48:11.634941 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6870 11:48:11.641427 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6871 11:48:11.644818 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6872 11:48:11.647802 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6873 11:48:11.651311 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6874 11:48:11.654272 ==
6875 11:48:11.654372 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 11:48:11.661372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 11:48:11.661453 ==
6878 11:48:11.661517 DQS Delay:
6879 11:48:11.664688 DQS0 = 59, DQS1 = 59
6880 11:48:11.664768 DQM Delay:
6881 11:48:11.667673 DQM0 = 19, DQM1 = 13
6882 11:48:11.667753 DQ Delay:
6883 11:48:11.671148 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6884 11:48:11.674505 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6885 11:48:11.677477 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6886 11:48:11.681085 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6887 11:48:11.681164
6888 11:48:11.681226
6889 11:48:11.681284 ==
6890 11:48:11.684410 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 11:48:11.687693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 11:48:11.687774 ==
6893 11:48:11.687836
6894 11:48:11.687895
6895 11:48:11.690932 TX Vref Scan disable
6896 11:48:11.691017 == TX Byte 0 ==
6897 11:48:11.697411 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6898 11:48:11.700815 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6899 11:48:11.700899 == TX Byte 1 ==
6900 11:48:11.707833 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6901 11:48:11.711185 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6902 11:48:11.711268 ==
6903 11:48:11.714300 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 11:48:11.717191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 11:48:11.717272 ==
6906 11:48:11.717338
6907 11:48:11.717426
6908 11:48:11.720612 TX Vref Scan disable
6909 11:48:11.720693 == TX Byte 0 ==
6910 11:48:11.727488 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6911 11:48:11.731235 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6912 11:48:11.731333 == TX Byte 1 ==
6913 11:48:11.737583 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6914 11:48:11.740525 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6915 11:48:11.740616
6916 11:48:11.740680 [DATLAT]
6917 11:48:11.744067 Freq=400, CH1 RK1
6918 11:48:11.744176
6919 11:48:11.744259 DATLAT Default: 0xe
6920 11:48:11.747139 0, 0xFFFF, sum = 0
6921 11:48:11.747286 1, 0xFFFF, sum = 0
6922 11:48:11.750585 2, 0xFFFF, sum = 0
6923 11:48:11.750666 3, 0xFFFF, sum = 0
6924 11:48:11.754310 4, 0xFFFF, sum = 0
6925 11:48:11.754392 5, 0xFFFF, sum = 0
6926 11:48:11.757265 6, 0xFFFF, sum = 0
6927 11:48:11.757347 7, 0xFFFF, sum = 0
6928 11:48:11.760583 8, 0xFFFF, sum = 0
6929 11:48:11.760664 9, 0xFFFF, sum = 0
6930 11:48:11.764211 10, 0xFFFF, sum = 0
6931 11:48:11.767042 11, 0xFFFF, sum = 0
6932 11:48:11.767123 12, 0xFFFF, sum = 0
6933 11:48:11.770525 13, 0x0, sum = 1
6934 11:48:11.770607 14, 0x0, sum = 2
6935 11:48:11.774009 15, 0x0, sum = 3
6936 11:48:11.774089 16, 0x0, sum = 4
6937 11:48:11.774153 best_step = 14
6938 11:48:11.774211
6939 11:48:11.776970 ==
6940 11:48:11.780548 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 11:48:11.783497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 11:48:11.783578 ==
6943 11:48:11.783642 RX Vref Scan: 0
6944 11:48:11.783701
6945 11:48:11.786981 RX Vref 0 -> 0, step: 1
6946 11:48:11.787061
6947 11:48:11.790069 RX Delay -359 -> 252, step: 8
6948 11:48:11.797246 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
6949 11:48:11.800417 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6950 11:48:11.803729 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6951 11:48:11.807101 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6952 11:48:11.814008 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6953 11:48:11.817423 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6954 11:48:11.820345 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6955 11:48:11.823941 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6956 11:48:11.830437 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6957 11:48:11.834147 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6958 11:48:11.837189 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6959 11:48:11.843563 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6960 11:48:11.847121 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6961 11:48:11.850175 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6962 11:48:11.853750 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6963 11:48:11.860190 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6964 11:48:11.860306 ==
6965 11:48:11.863342 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 11:48:11.866666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 11:48:11.866747 ==
6968 11:48:11.866810 DQS Delay:
6969 11:48:11.870049 DQS0 = 60, DQS1 = 64
6970 11:48:11.870129 DQM Delay:
6971 11:48:11.873517 DQM0 = 13, DQM1 = 10
6972 11:48:11.873597 DQ Delay:
6973 11:48:11.876986 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6974 11:48:11.879938 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6975 11:48:11.883368 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6976 11:48:11.886800 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6977 11:48:11.886879
6978 11:48:11.886941
6979 11:48:11.893344 [DQSOSCAuto] RK1, (LSB)MR18= 0x7aaa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6980 11:48:11.896784 CH1 RK1: MR19=C0C, MR18=7AAA
6981 11:48:11.903446 CH1_RK1: MR19=0xC0C, MR18=0x7AAA, DQSOSC=388, MR23=63, INC=392, DEC=261
6982 11:48:11.906738 [RxdqsGatingPostProcess] freq 400
6983 11:48:11.912974 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6984 11:48:11.916645 best DQS0 dly(2T, 0.5T) = (0, 10)
6985 11:48:11.916733 best DQS1 dly(2T, 0.5T) = (0, 10)
6986 11:48:11.919953 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6987 11:48:11.923308 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6988 11:48:11.926658 best DQS0 dly(2T, 0.5T) = (0, 10)
6989 11:48:11.930046 best DQS1 dly(2T, 0.5T) = (0, 10)
6990 11:48:11.933361 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6991 11:48:11.936813 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6992 11:48:11.939996 Pre-setting of DQS Precalculation
6993 11:48:11.946464 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6994 11:48:11.952918 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6995 11:48:11.959387 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6996 11:48:11.959470
6997 11:48:11.959532
6998 11:48:11.962962 [Calibration Summary] 800 Mbps
6999 11:48:11.963059 CH 0, Rank 0
7000 11:48:11.966426 SW Impedance : PASS
7001 11:48:11.969422 DUTY Scan : NO K
7002 11:48:11.969517 ZQ Calibration : PASS
7003 11:48:11.972755 Jitter Meter : NO K
7004 11:48:11.976260 CBT Training : PASS
7005 11:48:11.976351 Write leveling : PASS
7006 11:48:11.979840 RX DQS gating : PASS
7007 11:48:11.979920 RX DQ/DQS(RDDQC) : PASS
7008 11:48:11.982719 TX DQ/DQS : PASS
7009 11:48:11.986345 RX DATLAT : PASS
7010 11:48:11.986425 RX DQ/DQS(Engine): PASS
7011 11:48:11.989275 TX OE : NO K
7012 11:48:11.989355 All Pass.
7013 11:48:11.989418
7014 11:48:11.992769 CH 0, Rank 1
7015 11:48:11.992848 SW Impedance : PASS
7016 11:48:11.996321 DUTY Scan : NO K
7017 11:48:11.999105 ZQ Calibration : PASS
7018 11:48:11.999190 Jitter Meter : NO K
7019 11:48:12.002657 CBT Training : PASS
7020 11:48:12.006071 Write leveling : NO K
7021 11:48:12.006151 RX DQS gating : PASS
7022 11:48:12.009345 RX DQ/DQS(RDDQC) : PASS
7023 11:48:12.012791 TX DQ/DQS : PASS
7024 11:48:12.012875 RX DATLAT : PASS
7025 11:48:12.015769 RX DQ/DQS(Engine): PASS
7026 11:48:12.019134 TX OE : NO K
7027 11:48:12.019209 All Pass.
7028 11:48:12.019271
7029 11:48:12.019330 CH 1, Rank 0
7030 11:48:12.022318 SW Impedance : PASS
7031 11:48:12.025969 DUTY Scan : NO K
7032 11:48:12.026074 ZQ Calibration : PASS
7033 11:48:12.028840 Jitter Meter : NO K
7034 11:48:12.032364 CBT Training : PASS
7035 11:48:12.032441 Write leveling : PASS
7036 11:48:12.035741 RX DQS gating : PASS
7037 11:48:12.039057 RX DQ/DQS(RDDQC) : PASS
7038 11:48:12.039137 TX DQ/DQS : PASS
7039 11:48:12.042316 RX DATLAT : PASS
7040 11:48:12.042397 RX DQ/DQS(Engine): PASS
7041 11:48:12.045731 TX OE : NO K
7042 11:48:12.045812 All Pass.
7043 11:48:12.045883
7044 11:48:12.049294 CH 1, Rank 1
7045 11:48:12.049374 SW Impedance : PASS
7046 11:48:12.052097 DUTY Scan : NO K
7047 11:48:12.055856 ZQ Calibration : PASS
7048 11:48:12.055937 Jitter Meter : NO K
7049 11:48:12.059190 CBT Training : PASS
7050 11:48:12.062519 Write leveling : NO K
7051 11:48:12.062599 RX DQS gating : PASS
7052 11:48:12.065797 RX DQ/DQS(RDDQC) : PASS
7053 11:48:12.068809 TX DQ/DQS : PASS
7054 11:48:12.068892 RX DATLAT : PASS
7055 11:48:12.072342 RX DQ/DQS(Engine): PASS
7056 11:48:12.075720 TX OE : NO K
7057 11:48:12.075797 All Pass.
7058 11:48:12.075859
7059 11:48:12.075918 DramC Write-DBI off
7060 11:48:12.078716 PER_BANK_REFRESH: Hybrid Mode
7061 11:48:12.082259 TX_TRACKING: ON
7062 11:48:12.088616 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7063 11:48:12.095583 [FAST_K] Save calibration result to emmc
7064 11:48:12.099047 dramc_set_vcore_voltage set vcore to 725000
7065 11:48:12.099127 Read voltage for 1600, 0
7066 11:48:12.101960 Vio18 = 0
7067 11:48:12.102039 Vcore = 725000
7068 11:48:12.102116 Vdram = 0
7069 11:48:12.105449 Vddq = 0
7070 11:48:12.105529 Vmddr = 0
7071 11:48:12.108944 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7072 11:48:12.115229 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7073 11:48:12.118789 MEM_TYPE=3, freq_sel=13
7074 11:48:12.122287 sv_algorithm_assistance_LP4_3733
7075 11:48:12.125548 ============ PULL DRAM RESETB DOWN ============
7076 11:48:12.129071 ========== PULL DRAM RESETB DOWN end =========
7077 11:48:12.131849 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7078 11:48:12.135542 ===================================
7079 11:48:12.138608 LPDDR4 DRAM CONFIGURATION
7080 11:48:12.142233 ===================================
7081 11:48:12.145320 EX_ROW_EN[0] = 0x0
7082 11:48:12.145406 EX_ROW_EN[1] = 0x0
7083 11:48:12.148653 LP4Y_EN = 0x0
7084 11:48:12.148733 WORK_FSP = 0x1
7085 11:48:12.151874 WL = 0x5
7086 11:48:12.151953 RL = 0x5
7087 11:48:12.155347 BL = 0x2
7088 11:48:12.155427 RPST = 0x0
7089 11:48:12.158546 RD_PRE = 0x0
7090 11:48:12.161948 WR_PRE = 0x1
7091 11:48:12.162029 WR_PST = 0x1
7092 11:48:12.164907 DBI_WR = 0x0
7093 11:48:12.164999 DBI_RD = 0x0
7094 11:48:12.168789 OTF = 0x1
7095 11:48:12.172057 ===================================
7096 11:48:12.175334 ===================================
7097 11:48:12.175415 ANA top config
7098 11:48:12.178834 ===================================
7099 11:48:12.181760 DLL_ASYNC_EN = 0
7100 11:48:12.185199 ALL_SLAVE_EN = 0
7101 11:48:12.185280 NEW_RANK_MODE = 1
7102 11:48:12.188094 DLL_IDLE_MODE = 1
7103 11:48:12.191493 LP45_APHY_COMB_EN = 1
7104 11:48:12.195060 TX_ODT_DIS = 0
7105 11:48:12.195141 NEW_8X_MODE = 1
7106 11:48:12.198072 ===================================
7107 11:48:12.201573 ===================================
7108 11:48:12.205129 data_rate = 3200
7109 11:48:12.208124 CKR = 1
7110 11:48:12.211743 DQ_P2S_RATIO = 8
7111 11:48:12.214545 ===================================
7112 11:48:12.217865 CA_P2S_RATIO = 8
7113 11:48:12.221255 DQ_CA_OPEN = 0
7114 11:48:12.224834 DQ_SEMI_OPEN = 0
7115 11:48:12.224915 CA_SEMI_OPEN = 0
7116 11:48:12.227703 CA_FULL_RATE = 0
7117 11:48:12.231017 DQ_CKDIV4_EN = 0
7118 11:48:12.234521 CA_CKDIV4_EN = 0
7119 11:48:12.238016 CA_PREDIV_EN = 0
7120 11:48:12.241346 PH8_DLY = 12
7121 11:48:12.241427 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7122 11:48:12.244226 DQ_AAMCK_DIV = 4
7123 11:48:12.247999 CA_AAMCK_DIV = 4
7124 11:48:12.251068 CA_ADMCK_DIV = 4
7125 11:48:12.254298 DQ_TRACK_CA_EN = 0
7126 11:48:12.257756 CA_PICK = 1600
7127 11:48:12.261176 CA_MCKIO = 1600
7128 11:48:12.261277 MCKIO_SEMI = 0
7129 11:48:12.264415 PLL_FREQ = 3068
7130 11:48:12.267532 DQ_UI_PI_RATIO = 32
7131 11:48:12.271217 CA_UI_PI_RATIO = 0
7132 11:48:12.274054 ===================================
7133 11:48:12.277462 ===================================
7134 11:48:12.280889 memory_type:LPDDR4
7135 11:48:12.280969 GP_NUM : 10
7136 11:48:12.284151 SRAM_EN : 1
7137 11:48:12.287514 MD32_EN : 0
7138 11:48:12.290763 ===================================
7139 11:48:12.290844 [ANA_INIT] >>>>>>>>>>>>>>
7140 11:48:12.294256 <<<<<< [CONFIGURE PHASE]: ANA_TX
7141 11:48:12.297754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7142 11:48:12.300705 ===================================
7143 11:48:12.304152 data_rate = 3200,PCW = 0X7600
7144 11:48:12.307678 ===================================
7145 11:48:12.310587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7146 11:48:12.317599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 11:48:12.320457 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7148 11:48:12.327221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7149 11:48:12.330829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7150 11:48:12.334094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7151 11:48:12.334184 [ANA_INIT] flow start
7152 11:48:12.336954 [ANA_INIT] PLL >>>>>>>>
7153 11:48:12.340467 [ANA_INIT] PLL <<<<<<<<
7154 11:48:12.340541 [ANA_INIT] MIDPI >>>>>>>>
7155 11:48:12.343910 [ANA_INIT] MIDPI <<<<<<<<
7156 11:48:12.347358 [ANA_INIT] DLL >>>>>>>>
7157 11:48:12.350316 [ANA_INIT] DLL <<<<<<<<
7158 11:48:12.350416 [ANA_INIT] flow end
7159 11:48:12.353623 ============ LP4 DIFF to SE enter ============
7160 11:48:12.360480 ============ LP4 DIFF to SE exit ============
7161 11:48:12.360559 [ANA_INIT] <<<<<<<<<<<<<
7162 11:48:12.363648 [Flow] Enable top DCM control >>>>>
7163 11:48:12.366930 [Flow] Enable top DCM control <<<<<
7164 11:48:12.370584 Enable DLL master slave shuffle
7165 11:48:12.376626 ==============================================================
7166 11:48:12.376703 Gating Mode config
7167 11:48:12.383617 ==============================================================
7168 11:48:12.386617 Config description:
7169 11:48:12.397093 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7170 11:48:12.403480 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7171 11:48:12.406951 SELPH_MODE 0: By rank 1: By Phase
7172 11:48:12.413442 ==============================================================
7173 11:48:12.416944 GAT_TRACK_EN = 1
7174 11:48:12.417044 RX_GATING_MODE = 2
7175 11:48:12.420430 RX_GATING_TRACK_MODE = 2
7176 11:48:12.423382 SELPH_MODE = 1
7177 11:48:12.426539 PICG_EARLY_EN = 1
7178 11:48:12.430018 VALID_LAT_VALUE = 1
7179 11:48:12.436948 ==============================================================
7180 11:48:12.440328 Enter into Gating configuration >>>>
7181 11:48:12.443220 Exit from Gating configuration <<<<
7182 11:48:12.446648 Enter into DVFS_PRE_config >>>>>
7183 11:48:12.456799 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7184 11:48:12.459780 Exit from DVFS_PRE_config <<<<<
7185 11:48:12.463352 Enter into PICG configuration >>>>
7186 11:48:12.466854 Exit from PICG configuration <<<<
7187 11:48:12.469553 [RX_INPUT] configuration >>>>>
7188 11:48:12.473246 [RX_INPUT] configuration <<<<<
7189 11:48:12.476494 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7190 11:48:12.483238 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7191 11:48:12.489511 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7192 11:48:12.492973 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7193 11:48:12.499650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7194 11:48:12.506121 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7195 11:48:12.509367 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7196 11:48:12.515818 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7197 11:48:12.519266 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7198 11:48:12.522769 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7199 11:48:12.526217 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7200 11:48:12.532921 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7201 11:48:12.535971 ===================================
7202 11:48:12.539368 LPDDR4 DRAM CONFIGURATION
7203 11:48:12.539469 ===================================
7204 11:48:12.542726 EX_ROW_EN[0] = 0x0
7205 11:48:12.545650 EX_ROW_EN[1] = 0x0
7206 11:48:12.545753 LP4Y_EN = 0x0
7207 11:48:12.549218 WORK_FSP = 0x1
7208 11:48:12.549292 WL = 0x5
7209 11:48:12.552645 RL = 0x5
7210 11:48:12.552719 BL = 0x2
7211 11:48:12.555439 RPST = 0x0
7212 11:48:12.555537 RD_PRE = 0x0
7213 11:48:12.558859 WR_PRE = 0x1
7214 11:48:12.558958 WR_PST = 0x1
7215 11:48:12.562195 DBI_WR = 0x0
7216 11:48:12.562297 DBI_RD = 0x0
7217 11:48:12.565646 OTF = 0x1
7218 11:48:12.569113 ===================================
7219 11:48:12.571986 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7220 11:48:12.575516 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7221 11:48:12.582066 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7222 11:48:12.585786 ===================================
7223 11:48:12.585867 LPDDR4 DRAM CONFIGURATION
7224 11:48:12.588600 ===================================
7225 11:48:12.592003 EX_ROW_EN[0] = 0x10
7226 11:48:12.595249 EX_ROW_EN[1] = 0x0
7227 11:48:12.595329 LP4Y_EN = 0x0
7228 11:48:12.599080 WORK_FSP = 0x1
7229 11:48:12.599160 WL = 0x5
7230 11:48:12.601942 RL = 0x5
7231 11:48:12.602021 BL = 0x2
7232 11:48:12.605534 RPST = 0x0
7233 11:48:12.605614 RD_PRE = 0x0
7234 11:48:12.608317 WR_PRE = 0x1
7235 11:48:12.608397 WR_PST = 0x1
7236 11:48:12.611694 DBI_WR = 0x0
7237 11:48:12.611774 DBI_RD = 0x0
7238 11:48:12.615336 OTF = 0x1
7239 11:48:12.618579 ===================================
7240 11:48:12.625219 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7241 11:48:12.625301 ==
7242 11:48:12.628458 Dram Type= 6, Freq= 0, CH_0, rank 0
7243 11:48:12.631648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7244 11:48:12.631730 ==
7245 11:48:12.635026 [Duty_Offset_Calibration]
7246 11:48:12.635106 B0:2 B1:0 CA:3
7247 11:48:12.635169
7248 11:48:12.638532 [DutyScan_Calibration_Flow] k_type=0
7249 11:48:12.649420
7250 11:48:12.649500 ==CLK 0==
7251 11:48:12.652946 Final CLK duty delay cell = 0
7252 11:48:12.655803 [0] MAX Duty = 5031%(X100), DQS PI = 12
7253 11:48:12.659256 [0] MIN Duty = 4907%(X100), DQS PI = 6
7254 11:48:12.659336 [0] AVG Duty = 4969%(X100)
7255 11:48:12.662705
7256 11:48:12.662785 CH0 CLK Duty spec in!! Max-Min= 124%
7257 11:48:12.669516 [DutyScan_Calibration_Flow] ====Done====
7258 11:48:12.669602
7259 11:48:12.672526 [DutyScan_Calibration_Flow] k_type=1
7260 11:48:12.689233
7261 11:48:12.689425 ==DQS 0 ==
7262 11:48:12.692253 Final DQS duty delay cell = 0
7263 11:48:12.695518 [0] MAX Duty = 5125%(X100), DQS PI = 30
7264 11:48:12.698908 [0] MIN Duty = 4875%(X100), DQS PI = 50
7265 11:48:12.702390 [0] AVG Duty = 5000%(X100)
7266 11:48:12.702568
7267 11:48:12.702667 ==DQS 1 ==
7268 11:48:12.705525 Final DQS duty delay cell = 0
7269 11:48:12.708697 [0] MAX Duty = 5156%(X100), DQS PI = 30
7270 11:48:12.712135 [0] MIN Duty = 5062%(X100), DQS PI = 0
7271 11:48:12.715723 [0] AVG Duty = 5109%(X100)
7272 11:48:12.715840
7273 11:48:12.718538 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7274 11:48:12.718660
7275 11:48:12.721985 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7276 11:48:12.725428 [DutyScan_Calibration_Flow] ====Done====
7277 11:48:12.725555
7278 11:48:12.728400 [DutyScan_Calibration_Flow] k_type=3
7279 11:48:12.746985
7280 11:48:12.747066 ==DQM 0 ==
7281 11:48:12.750159 Final DQM duty delay cell = 0
7282 11:48:12.753632 [0] MAX Duty = 5156%(X100), DQS PI = 30
7283 11:48:12.756638 [0] MIN Duty = 4875%(X100), DQS PI = 0
7284 11:48:12.756720 [0] AVG Duty = 5015%(X100)
7285 11:48:12.760151
7286 11:48:12.760287 ==DQM 1 ==
7287 11:48:12.763722 Final DQM duty delay cell = 4
7288 11:48:12.767171 [4] MAX Duty = 5187%(X100), DQS PI = 62
7289 11:48:12.769982 [4] MIN Duty = 5000%(X100), DQS PI = 38
7290 11:48:12.773437 [4] AVG Duty = 5093%(X100)
7291 11:48:12.773534
7292 11:48:12.776387 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7293 11:48:12.776468
7294 11:48:12.779862 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7295 11:48:12.783690 [DutyScan_Calibration_Flow] ====Done====
7296 11:48:12.783776
7297 11:48:12.786587 [DutyScan_Calibration_Flow] k_type=2
7298 11:48:12.803150
7299 11:48:12.803269 ==DQ 0 ==
7300 11:48:12.806247 Final DQ duty delay cell = -4
7301 11:48:12.809524 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7302 11:48:12.812873 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7303 11:48:12.816273 [-4] AVG Duty = 4938%(X100)
7304 11:48:12.816421
7305 11:48:12.816538 ==DQ 1 ==
7306 11:48:12.819540 Final DQ duty delay cell = 0
7307 11:48:12.822997 [0] MAX Duty = 5156%(X100), DQS PI = 58
7308 11:48:12.826550 [0] MIN Duty = 5000%(X100), DQS PI = 16
7309 11:48:12.829553 [0] AVG Duty = 5078%(X100)
7310 11:48:12.829789
7311 11:48:12.833128 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7312 11:48:12.833420
7313 11:48:12.836313 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7314 11:48:12.840154 [DutyScan_Calibration_Flow] ====Done====
7315 11:48:12.840687 ==
7316 11:48:12.843238 Dram Type= 6, Freq= 0, CH_1, rank 0
7317 11:48:12.846884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7318 11:48:12.847456 ==
7319 11:48:12.849850 [Duty_Offset_Calibration]
7320 11:48:12.850412 B0:1 B1:-2 CA:1
7321 11:48:12.850772
7322 11:48:12.852814 [DutyScan_Calibration_Flow] k_type=0
7323 11:48:12.864009
7324 11:48:12.864772 ==CLK 0==
7325 11:48:12.867397 Final CLK duty delay cell = 0
7326 11:48:12.870581 [0] MAX Duty = 5094%(X100), DQS PI = 22
7327 11:48:12.873588 [0] MIN Duty = 4844%(X100), DQS PI = 4
7328 11:48:12.874044 [0] AVG Duty = 4969%(X100)
7329 11:48:12.876955
7330 11:48:12.880493 CH1 CLK Duty spec in!! Max-Min= 250%
7331 11:48:12.884056 [DutyScan_Calibration_Flow] ====Done====
7332 11:48:12.884634
7333 11:48:12.886837 [DutyScan_Calibration_Flow] k_type=1
7334 11:48:12.902721
7335 11:48:12.903274 ==DQS 0 ==
7336 11:48:12.905878 Final DQS duty delay cell = -4
7337 11:48:12.909182 [-4] MAX Duty = 4969%(X100), DQS PI = 26
7338 11:48:12.912728 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7339 11:48:12.916186 [-4] AVG Duty = 4906%(X100)
7340 11:48:12.916770
7341 11:48:12.917133 ==DQS 1 ==
7342 11:48:12.919157 Final DQS duty delay cell = 0
7343 11:48:12.922430 [0] MAX Duty = 5062%(X100), DQS PI = 0
7344 11:48:12.925758 [0] MIN Duty = 4844%(X100), DQS PI = 26
7345 11:48:12.928823 [0] AVG Duty = 4953%(X100)
7346 11:48:12.929434
7347 11:48:12.932308 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7348 11:48:12.932772
7349 11:48:12.935587 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7350 11:48:12.939044 [DutyScan_Calibration_Flow] ====Done====
7351 11:48:12.939498
7352 11:48:12.942033 [DutyScan_Calibration_Flow] k_type=3
7353 11:48:12.959514
7354 11:48:12.960030 ==DQM 0 ==
7355 11:48:12.962754 Final DQM duty delay cell = 0
7356 11:48:12.966425 [0] MAX Duty = 5000%(X100), DQS PI = 22
7357 11:48:12.969636 [0] MIN Duty = 4813%(X100), DQS PI = 54
7358 11:48:12.972926 [0] AVG Duty = 4906%(X100)
7359 11:48:12.973382
7360 11:48:12.973741 ==DQM 1 ==
7361 11:48:12.976482 Final DQM duty delay cell = 0
7362 11:48:12.979713 [0] MAX Duty = 5062%(X100), DQS PI = 34
7363 11:48:12.982879 [0] MIN Duty = 4875%(X100), DQS PI = 24
7364 11:48:12.986299 [0] AVG Duty = 4968%(X100)
7365 11:48:12.986839
7366 11:48:12.990044 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7367 11:48:12.990595
7368 11:48:12.992860 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7369 11:48:12.996256 [DutyScan_Calibration_Flow] ====Done====
7370 11:48:12.996798
7371 11:48:12.999670 [DutyScan_Calibration_Flow] k_type=2
7372 11:48:13.016001
7373 11:48:13.016083 ==DQ 0 ==
7374 11:48:13.019631 Final DQ duty delay cell = 0
7375 11:48:13.022310 [0] MAX Duty = 5093%(X100), DQS PI = 22
7376 11:48:13.025859 [0] MIN Duty = 4907%(X100), DQS PI = 60
7377 11:48:13.025959 [0] AVG Duty = 5000%(X100)
7378 11:48:13.029214
7379 11:48:13.029315 ==DQ 1 ==
7380 11:48:13.032773 Final DQ duty delay cell = 0
7381 11:48:13.035792 [0] MAX Duty = 5125%(X100), DQS PI = 34
7382 11:48:13.039451 [0] MIN Duty = 4969%(X100), DQS PI = 24
7383 11:48:13.039926 [0] AVG Duty = 5047%(X100)
7384 11:48:13.042649
7385 11:48:13.046515 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7386 11:48:13.046974
7387 11:48:13.049475 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7388 11:48:13.053116 [DutyScan_Calibration_Flow] ====Done====
7389 11:48:13.056583 nWR fixed to 30
7390 11:48:13.057069 [ModeRegInit_LP4] CH0 RK0
7391 11:48:13.059328 [ModeRegInit_LP4] CH0 RK1
7392 11:48:13.062738 [ModeRegInit_LP4] CH1 RK0
7393 11:48:13.066189 [ModeRegInit_LP4] CH1 RK1
7394 11:48:13.066647 match AC timing 5
7395 11:48:13.069473 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7396 11:48:13.075931 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7397 11:48:13.079406 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7398 11:48:13.085993 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7399 11:48:13.089682 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7400 11:48:13.090265 [MiockJmeterHQA]
7401 11:48:13.090756
7402 11:48:13.092936 [DramcMiockJmeter] u1RxGatingPI = 0
7403 11:48:13.096023 0 : 4255, 4027
7404 11:48:13.096571 4 : 4255, 4029
7405 11:48:13.099554 8 : 4368, 4140
7406 11:48:13.100186 12 : 4367, 4140
7407 11:48:13.100738 16 : 4255, 4029
7408 11:48:13.102432 20 : 4363, 4137
7409 11:48:13.102911 24 : 4255, 4029
7410 11:48:13.105886 28 : 4255, 4029
7411 11:48:13.106366 32 : 4257, 4032
7412 11:48:13.109438 36 : 4254, 4029
7413 11:48:13.109923 40 : 4366, 4140
7414 11:48:13.110418 44 : 4255, 4029
7415 11:48:13.112896 48 : 4255, 4029
7416 11:48:13.113377 52 : 4257, 4032
7417 11:48:13.115826 56 : 4255, 4029
7418 11:48:13.116360 60 : 4250, 4027
7419 11:48:13.119414 64 : 4257, 4032
7420 11:48:13.119987 68 : 4252, 4029
7421 11:48:13.122699 72 : 4253, 4029
7422 11:48:13.123364 76 : 4258, 4031
7423 11:48:13.123857 80 : 4252, 4030
7424 11:48:13.125858 84 : 4252, 4029
7425 11:48:13.126339 88 : 4363, 4140
7426 11:48:13.129121 92 : 4363, 4140
7427 11:48:13.129606 96 : 4253, 4029
7428 11:48:13.132591 100 : 4363, 4140
7429 11:48:13.133076 104 : 4255, 3601
7430 11:48:13.136006 108 : 4252, 1
7431 11:48:13.136692 112 : 4363, 0
7432 11:48:13.137192 116 : 4254, 0
7433 11:48:13.139209 120 : 4255, 0
7434 11:48:13.139693 124 : 4252, 0
7435 11:48:13.142142 128 : 4252, 0
7436 11:48:13.142625 132 : 4258, 0
7437 11:48:13.143115 136 : 4252, 0
7438 11:48:13.145596 140 : 4252, 0
7439 11:48:13.146086 144 : 4253, 0
7440 11:48:13.148940 148 : 4257, 0
7441 11:48:13.149478 152 : 4255, 0
7442 11:48:13.149972 156 : 4253, 0
7443 11:48:13.152306 160 : 4257, 0
7444 11:48:13.152793 164 : 4363, 0
7445 11:48:13.153282 168 : 4249, 0
7446 11:48:13.155667 172 : 4363, 0
7447 11:48:13.156268 176 : 4255, 0
7448 11:48:13.158615 180 : 4252, 0
7449 11:48:13.159095 184 : 4253, 0
7450 11:48:13.159585 188 : 4257, 0
7451 11:48:13.162367 192 : 4363, 0
7452 11:48:13.162942 196 : 4253, 0
7453 11:48:13.165537 200 : 4252, 0
7454 11:48:13.166018 204 : 4252, 0
7455 11:48:13.166508 208 : 4368, 0
7456 11:48:13.168993 212 : 4252, 0
7457 11:48:13.169473 216 : 4363, 0
7458 11:48:13.172525 220 : 4253, 0
7459 11:48:13.173097 224 : 4253, 0
7460 11:48:13.173598 228 : 4253, 0
7461 11:48:13.175796 232 : 4252, 0
7462 11:48:13.176325 236 : 4253, 1320
7463 11:48:13.178742 240 : 4363, 4139
7464 11:48:13.179209 244 : 4365, 4140
7465 11:48:13.182256 248 : 4252, 4029
7466 11:48:13.182846 252 : 4252, 4029
7467 11:48:13.183346 256 : 4255, 4029
7468 11:48:13.185817 260 : 4252, 4029
7469 11:48:13.186448 264 : 4363, 4140
7470 11:48:13.189003 268 : 4252, 4029
7471 11:48:13.189473 272 : 4255, 4029
7472 11:48:13.192156 276 : 4363, 4140
7473 11:48:13.192826 280 : 4363, 4140
7474 11:48:13.195367 284 : 4249, 4027
7475 11:48:13.195834 288 : 4253, 4029
7476 11:48:13.198874 292 : 4360, 4137
7477 11:48:13.199430 296 : 4252, 4029
7478 11:48:13.202085 300 : 4252, 4029
7479 11:48:13.202555 304 : 4361, 4137
7480 11:48:13.205873 308 : 4253, 4029
7481 11:48:13.206433 312 : 4252, 4029
7482 11:48:13.206809 316 : 4253, 4029
7483 11:48:13.208773 320 : 4257, 4032
7484 11:48:13.209241 324 : 4253, 4029
7485 11:48:13.212512 328 : 4252, 4029
7486 11:48:13.213075 332 : 4252, 4030
7487 11:48:13.215225 336 : 4257, 4032
7488 11:48:13.215784 340 : 4253, 4029
7489 11:48:13.218518 344 : 4253, 4029
7490 11:48:13.218987 348 : 4252, 4029
7491 11:48:13.222109 352 : 4257, 4031
7492 11:48:13.222653 356 : 4363, 3253
7493 11:48:13.225928 360 : 4253, 2
7494 11:48:13.226489
7495 11:48:13.226853 MIOCK jitter meter ch=0
7496 11:48:13.227207
7497 11:48:13.228512 1T = (360-108) = 252 dly cells
7498 11:48:13.235052 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7499 11:48:13.235591 ==
7500 11:48:13.238392 Dram Type= 6, Freq= 0, CH_0, rank 0
7501 11:48:13.241913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7502 11:48:13.242468 ==
7503 11:48:13.248613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7504 11:48:13.252118 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7505 11:48:13.254969 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7506 11:48:13.261472 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7507 11:48:13.271911 [CA 0] Center 44 (14~75) winsize 62
7508 11:48:13.274535 [CA 1] Center 43 (13~74) winsize 62
7509 11:48:13.278248 [CA 2] Center 39 (11~68) winsize 58
7510 11:48:13.281232 [CA 3] Center 39 (10~69) winsize 60
7511 11:48:13.284694 [CA 4] Center 37 (8~67) winsize 60
7512 11:48:13.288138 [CA 5] Center 37 (8~66) winsize 59
7513 11:48:13.288877
7514 11:48:13.291419 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7515 11:48:13.291984
7516 11:48:13.294609 [CATrainingPosCal] consider 1 rank data
7517 11:48:13.298019 u2DelayCellTimex100 = 258/100 ps
7518 11:48:13.304335 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7519 11:48:13.308243 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7520 11:48:13.311515 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7521 11:48:13.314470 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7522 11:48:13.318173 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7523 11:48:13.321516 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7524 11:48:13.321976
7525 11:48:13.324682 CA PerBit enable=1, Macro0, CA PI delay=37
7526 11:48:13.325144
7527 11:48:13.327751 [CBTSetCACLKResult] CA Dly = 37
7528 11:48:13.331564 CS Dly: 11 (0~42)
7529 11:48:13.334764 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7530 11:48:13.337566 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7531 11:48:13.338025 ==
7532 11:48:13.341222 Dram Type= 6, Freq= 0, CH_0, rank 1
7533 11:48:13.348011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7534 11:48:13.348616 ==
7535 11:48:13.351070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7536 11:48:13.354594 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7537 11:48:13.361608 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7538 11:48:13.367459 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7539 11:48:13.375185 [CA 0] Center 43 (13~74) winsize 62
7540 11:48:13.378772 [CA 1] Center 43 (13~74) winsize 62
7541 11:48:13.381961 [CA 2] Center 39 (10~68) winsize 59
7542 11:48:13.385095 [CA 3] Center 39 (10~68) winsize 59
7543 11:48:13.388419 [CA 4] Center 36 (6~66) winsize 61
7544 11:48:13.391985 [CA 5] Center 36 (6~66) winsize 61
7545 11:48:13.392730
7546 11:48:13.395046 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7547 11:48:13.395504
7548 11:48:13.398608 [CATrainingPosCal] consider 2 rank data
7549 11:48:13.401485 u2DelayCellTimex100 = 258/100 ps
7550 11:48:13.405077 CA0 delay=44 (14~74),Diff = 7 PI (26 cell)
7551 11:48:13.411641 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7552 11:48:13.415099 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7553 11:48:13.418105 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7554 11:48:13.421362 CA4 delay=37 (8~66),Diff = 0 PI (0 cell)
7555 11:48:13.425025 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7556 11:48:13.425484
7557 11:48:13.427951 CA PerBit enable=1, Macro0, CA PI delay=37
7558 11:48:13.428531
7559 11:48:13.431757 [CBTSetCACLKResult] CA Dly = 37
7560 11:48:13.434994 CS Dly: 11 (0~43)
7561 11:48:13.438353 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7562 11:48:13.441103 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7563 11:48:13.441564
7564 11:48:13.444465 ----->DramcWriteLeveling(PI) begin...
7565 11:48:13.444993 ==
7566 11:48:13.448246 Dram Type= 6, Freq= 0, CH_0, rank 0
7567 11:48:13.454569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7568 11:48:13.454992 ==
7569 11:48:13.458071 Write leveling (Byte 0): 35 => 35
7570 11:48:13.461457 Write leveling (Byte 1): 30 => 30
7571 11:48:13.462002 DramcWriteLeveling(PI) end<-----
7572 11:48:13.462347
7573 11:48:13.464555 ==
7574 11:48:13.467827 Dram Type= 6, Freq= 0, CH_0, rank 0
7575 11:48:13.471230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 11:48:13.471674 ==
7577 11:48:13.474477 [Gating] SW mode calibration
7578 11:48:13.481610 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7579 11:48:13.484570 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7580 11:48:13.490916 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 11:48:13.494554 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 11:48:13.498206 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 11:48:13.504334 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 11:48:13.507940 1 4 16 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7585 11:48:13.511056 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
7586 11:48:13.518022 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7587 11:48:13.521241 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 11:48:13.524500 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 11:48:13.530913 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 11:48:13.534279 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 11:48:13.537464 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 11:48:13.543988 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
7593 11:48:13.547485 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7594 11:48:13.550941 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7595 11:48:13.557726 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7596 11:48:13.560516 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 11:48:13.563947 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 11:48:13.570613 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 11:48:13.574025 1 6 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7600 11:48:13.577194 1 6 16 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7601 11:48:13.583677 1 6 20 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7602 11:48:13.587476 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
7603 11:48:13.590444 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 11:48:13.596928 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 11:48:13.600311 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 11:48:13.603742 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 11:48:13.610242 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 11:48:13.613818 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7609 11:48:13.617061 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7610 11:48:13.620369 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7611 11:48:13.626672 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7612 11:48:13.630112 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 11:48:13.633474 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 11:48:13.640266 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 11:48:13.643354 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 11:48:13.647123 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 11:48:13.653435 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 11:48:13.656846 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 11:48:13.659971 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 11:48:13.666899 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 11:48:13.669973 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 11:48:13.673327 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 11:48:13.679664 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 11:48:13.683609 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7625 11:48:13.686997 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7626 11:48:13.690135 Total UI for P1: 0, mck2ui 16
7627 11:48:13.693408 best dqsien dly found for B0: ( 1, 9, 16)
7628 11:48:13.699845 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7629 11:48:13.703150 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 11:48:13.706378 Total UI for P1: 0, mck2ui 16
7631 11:48:13.709807 best dqsien dly found for B1: ( 1, 9, 24)
7632 11:48:13.713484 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7633 11:48:13.716498 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7634 11:48:13.716987
7635 11:48:13.719883 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7636 11:48:13.723173 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7637 11:48:13.726698 [Gating] SW calibration Done
7638 11:48:13.727115 ==
7639 11:48:13.729610 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 11:48:13.736706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 11:48:13.737121 ==
7642 11:48:13.737448 RX Vref Scan: 0
7643 11:48:13.737758
7644 11:48:13.739625 RX Vref 0 -> 0, step: 1
7645 11:48:13.740085
7646 11:48:13.743149 RX Delay 0 -> 252, step: 8
7647 11:48:13.746338 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7648 11:48:13.749325 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7649 11:48:13.753052 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7650 11:48:13.756245 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7651 11:48:13.762644 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7652 11:48:13.766508 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7653 11:48:13.769386 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7654 11:48:13.772634 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7655 11:48:13.776103 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7656 11:48:13.782729 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7657 11:48:13.786197 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7658 11:48:13.789614 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7659 11:48:13.793152 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7660 11:48:13.795986 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7661 11:48:13.802948 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7662 11:48:13.805978 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7663 11:48:13.806412 ==
7664 11:48:13.809380 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 11:48:13.813112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 11:48:13.813535 ==
7667 11:48:13.816027 DQS Delay:
7668 11:48:13.816494 DQS0 = 0, DQS1 = 0
7669 11:48:13.816831 DQM Delay:
7670 11:48:13.819599 DQM0 = 128, DQM1 = 124
7671 11:48:13.820040 DQ Delay:
7672 11:48:13.822580 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7673 11:48:13.825916 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7674 11:48:13.829238 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7675 11:48:13.835734 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7676 11:48:13.836153
7677 11:48:13.836540
7678 11:48:13.836915 ==
7679 11:48:13.839310 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 11:48:13.842280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 11:48:13.842701 ==
7682 11:48:13.843076
7683 11:48:13.843611
7684 11:48:13.845842 TX Vref Scan disable
7685 11:48:13.846256 == TX Byte 0 ==
7686 11:48:13.852751 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7687 11:48:13.855698 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7688 11:48:13.856119 == TX Byte 1 ==
7689 11:48:13.862721 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7690 11:48:13.865887 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7691 11:48:13.866301 ==
7692 11:48:13.868779 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 11:48:13.872159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 11:48:13.872611 ==
7695 11:48:13.886913
7696 11:48:13.890401 TX Vref early break, caculate TX vref
7697 11:48:13.893733 TX Vref=16, minBit 4, minWin=21, winSum=361
7698 11:48:13.896762 TX Vref=18, minBit 4, minWin=23, winSum=378
7699 11:48:13.900265 TX Vref=20, minBit 0, minWin=24, winSum=386
7700 11:48:13.903193 TX Vref=22, minBit 4, minWin=24, winSum=397
7701 11:48:13.906604 TX Vref=24, minBit 4, minWin=24, winSum=400
7702 11:48:13.913596 TX Vref=26, minBit 4, minWin=25, winSum=414
7703 11:48:13.916872 TX Vref=28, minBit 4, minWin=24, winSum=414
7704 11:48:13.919953 TX Vref=30, minBit 8, minWin=24, winSum=408
7705 11:48:13.923059 TX Vref=32, minBit 0, minWin=24, winSum=398
7706 11:48:13.926356 TX Vref=34, minBit 0, minWin=23, winSum=387
7707 11:48:13.933203 [TxChooseVref] Worse bit 4, Min win 25, Win sum 414, Final Vref 26
7708 11:48:13.933825
7709 11:48:13.936868 Final TX Range 0 Vref 26
7710 11:48:13.937418
7711 11:48:13.937962 ==
7712 11:48:13.939659 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 11:48:13.943333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 11:48:13.943937 ==
7715 11:48:13.944516
7716 11:48:13.944920
7717 11:48:13.946696 TX Vref Scan disable
7718 11:48:13.953256 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7719 11:48:13.953856 == TX Byte 0 ==
7720 11:48:13.956749 u2DelayCellOfst[0]=11 cells (3 PI)
7721 11:48:13.959428 u2DelayCellOfst[1]=15 cells (4 PI)
7722 11:48:13.962923 u2DelayCellOfst[2]=7 cells (2 PI)
7723 11:48:13.966326 u2DelayCellOfst[3]=11 cells (3 PI)
7724 11:48:13.969736 u2DelayCellOfst[4]=3 cells (1 PI)
7725 11:48:13.972969 u2DelayCellOfst[5]=0 cells (0 PI)
7726 11:48:13.976330 u2DelayCellOfst[6]=15 cells (4 PI)
7727 11:48:13.979786 u2DelayCellOfst[7]=15 cells (4 PI)
7728 11:48:13.983123 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7729 11:48:13.985971 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7730 11:48:13.989782 == TX Byte 1 ==
7731 11:48:13.990193 u2DelayCellOfst[8]=0 cells (0 PI)
7732 11:48:13.992786 u2DelayCellOfst[9]=3 cells (1 PI)
7733 11:48:13.996126 u2DelayCellOfst[10]=7 cells (2 PI)
7734 11:48:13.999706 u2DelayCellOfst[11]=7 cells (2 PI)
7735 11:48:14.002668 u2DelayCellOfst[12]=15 cells (4 PI)
7736 11:48:14.006208 u2DelayCellOfst[13]=11 cells (3 PI)
7737 11:48:14.009679 u2DelayCellOfst[14]=18 cells (5 PI)
7738 11:48:14.012780 u2DelayCellOfst[15]=11 cells (3 PI)
7739 11:48:14.016139 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7740 11:48:14.022921 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7741 11:48:14.023558 DramC Write-DBI on
7742 11:48:14.024128 ==
7743 11:48:14.026167 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 11:48:14.029021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 11:48:14.032474 ==
7746 11:48:14.033116
7747 11:48:14.033694
7748 11:48:14.034327 TX Vref Scan disable
7749 11:48:14.036052 == TX Byte 0 ==
7750 11:48:14.039383 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7751 11:48:14.042790 == TX Byte 1 ==
7752 11:48:14.045803 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7753 11:48:14.049437 DramC Write-DBI off
7754 11:48:14.049721
7755 11:48:14.050011 [DATLAT]
7756 11:48:14.050316 Freq=1600, CH0 RK0
7757 11:48:14.050545
7758 11:48:14.052628 DATLAT Default: 0xf
7759 11:48:14.052938 0, 0xFFFF, sum = 0
7760 11:48:14.055936 1, 0xFFFF, sum = 0
7761 11:48:14.059509 2, 0xFFFF, sum = 0
7762 11:48:14.059735 3, 0xFFFF, sum = 0
7763 11:48:14.062384 4, 0xFFFF, sum = 0
7764 11:48:14.062714 5, 0xFFFF, sum = 0
7765 11:48:14.066008 6, 0xFFFF, sum = 0
7766 11:48:14.066402 7, 0xFFFF, sum = 0
7767 11:48:14.068867 8, 0xFFFF, sum = 0
7768 11:48:14.069162 9, 0xFFFF, sum = 0
7769 11:48:14.072418 10, 0xFFFF, sum = 0
7770 11:48:14.072759 11, 0xFFFF, sum = 0
7771 11:48:14.075888 12, 0xFFFF, sum = 0
7772 11:48:14.076158 13, 0xEFFF, sum = 0
7773 11:48:14.079245 14, 0x0, sum = 1
7774 11:48:14.079481 15, 0x0, sum = 2
7775 11:48:14.082478 16, 0x0, sum = 3
7776 11:48:14.082721 17, 0x0, sum = 4
7777 11:48:14.085948 best_step = 15
7778 11:48:14.086212
7779 11:48:14.086410 ==
7780 11:48:14.088849 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 11:48:14.092299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 11:48:14.092525 ==
7783 11:48:14.095661 RX Vref Scan: 1
7784 11:48:14.095903
7785 11:48:14.096079 Set Vref Range= 24 -> 127
7786 11:48:14.096271
7787 11:48:14.098853 RX Vref 24 -> 127, step: 1
7788 11:48:14.098944
7789 11:48:14.102023 RX Delay 11 -> 252, step: 4
7790 11:48:14.102104
7791 11:48:14.105398 Set Vref, RX VrefLevel [Byte0]: 24
7792 11:48:14.108473 [Byte1]: 24
7793 11:48:14.108546
7794 11:48:14.111853 Set Vref, RX VrefLevel [Byte0]: 25
7795 11:48:14.115324 [Byte1]: 25
7796 11:48:14.118325
7797 11:48:14.118410 Set Vref, RX VrefLevel [Byte0]: 26
7798 11:48:14.121912 [Byte1]: 26
7799 11:48:14.126314
7800 11:48:14.126401 Set Vref, RX VrefLevel [Byte0]: 27
7801 11:48:14.129390 [Byte1]: 27
7802 11:48:14.133760
7803 11:48:14.133842 Set Vref, RX VrefLevel [Byte0]: 28
7804 11:48:14.137073 [Byte1]: 28
7805 11:48:14.141563
7806 11:48:14.141644 Set Vref, RX VrefLevel [Byte0]: 29
7807 11:48:14.144701 [Byte1]: 29
7808 11:48:14.149306
7809 11:48:14.149380 Set Vref, RX VrefLevel [Byte0]: 30
7810 11:48:14.152296 [Byte1]: 30
7811 11:48:14.156417
7812 11:48:14.156490 Set Vref, RX VrefLevel [Byte0]: 31
7813 11:48:14.160045 [Byte1]: 31
7814 11:48:14.164473
7815 11:48:14.164542 Set Vref, RX VrefLevel [Byte0]: 32
7816 11:48:14.167464 [Byte1]: 32
7817 11:48:14.172047
7818 11:48:14.172119 Set Vref, RX VrefLevel [Byte0]: 33
7819 11:48:14.175448 [Byte1]: 33
7820 11:48:14.179619
7821 11:48:14.179693 Set Vref, RX VrefLevel [Byte0]: 34
7822 11:48:14.183111 [Byte1]: 34
7823 11:48:14.186974
7824 11:48:14.187046 Set Vref, RX VrefLevel [Byte0]: 35
7825 11:48:14.190236 [Byte1]: 35
7826 11:48:14.194978
7827 11:48:14.195052 Set Vref, RX VrefLevel [Byte0]: 36
7828 11:48:14.197869 [Byte1]: 36
7829 11:48:14.202303
7830 11:48:14.202376 Set Vref, RX VrefLevel [Byte0]: 37
7831 11:48:14.205436 [Byte1]: 37
7832 11:48:14.210089
7833 11:48:14.210164 Set Vref, RX VrefLevel [Byte0]: 38
7834 11:48:14.213400 [Byte1]: 38
7835 11:48:14.217376
7836 11:48:14.217443 Set Vref, RX VrefLevel [Byte0]: 39
7837 11:48:14.220812 [Byte1]: 39
7838 11:48:14.225393
7839 11:48:14.225460 Set Vref, RX VrefLevel [Byte0]: 40
7840 11:48:14.228226 [Byte1]: 40
7841 11:48:14.232716
7842 11:48:14.232793 Set Vref, RX VrefLevel [Byte0]: 41
7843 11:48:14.236127 [Byte1]: 41
7844 11:48:14.240349
7845 11:48:14.240419 Set Vref, RX VrefLevel [Byte0]: 42
7846 11:48:14.243618 [Byte1]: 42
7847 11:48:14.248010
7848 11:48:14.248080 Set Vref, RX VrefLevel [Byte0]: 43
7849 11:48:14.251359 [Byte1]: 43
7850 11:48:14.255828
7851 11:48:14.255900 Set Vref, RX VrefLevel [Byte0]: 44
7852 11:48:14.259249 [Byte1]: 44
7853 11:48:14.263367
7854 11:48:14.263437 Set Vref, RX VrefLevel [Byte0]: 45
7855 11:48:14.266205 [Byte1]: 45
7856 11:48:14.271023
7857 11:48:14.271105 Set Vref, RX VrefLevel [Byte0]: 46
7858 11:48:14.274340 [Byte1]: 46
7859 11:48:14.278434
7860 11:48:14.278514 Set Vref, RX VrefLevel [Byte0]: 47
7861 11:48:14.281964 [Byte1]: 47
7862 11:48:14.286029
7863 11:48:14.286106 Set Vref, RX VrefLevel [Byte0]: 48
7864 11:48:14.289430 [Byte1]: 48
7865 11:48:14.293436
7866 11:48:14.293510 Set Vref, RX VrefLevel [Byte0]: 49
7867 11:48:14.297257 [Byte1]: 49
7868 11:48:14.301175
7869 11:48:14.301244 Set Vref, RX VrefLevel [Byte0]: 50
7870 11:48:14.304675 [Byte1]: 50
7871 11:48:14.309180
7872 11:48:14.309253 Set Vref, RX VrefLevel [Byte0]: 51
7873 11:48:14.312378 [Byte1]: 51
7874 11:48:14.316373
7875 11:48:14.316443 Set Vref, RX VrefLevel [Byte0]: 52
7876 11:48:14.319562 [Byte1]: 52
7877 11:48:14.324002
7878 11:48:14.324076 Set Vref, RX VrefLevel [Byte0]: 53
7879 11:48:14.327405 [Byte1]: 53
7880 11:48:14.331525
7881 11:48:14.331605 Set Vref, RX VrefLevel [Byte0]: 54
7882 11:48:14.334999 [Byte1]: 54
7883 11:48:14.339163
7884 11:48:14.339235 Set Vref, RX VrefLevel [Byte0]: 55
7885 11:48:14.342462 [Byte1]: 55
7886 11:48:14.347035
7887 11:48:14.347114 Set Vref, RX VrefLevel [Byte0]: 56
7888 11:48:14.350272 [Byte1]: 56
7889 11:48:14.354592
7890 11:48:14.354667 Set Vref, RX VrefLevel [Byte0]: 57
7891 11:48:14.357911 [Byte1]: 57
7892 11:48:14.362127
7893 11:48:14.362199 Set Vref, RX VrefLevel [Byte0]: 58
7894 11:48:14.365189 [Byte1]: 58
7895 11:48:14.369847
7896 11:48:14.369923 Set Vref, RX VrefLevel [Byte0]: 59
7897 11:48:14.373298 [Byte1]: 59
7898 11:48:14.377460
7899 11:48:14.377529 Set Vref, RX VrefLevel [Byte0]: 60
7900 11:48:14.380852 [Byte1]: 60
7901 11:48:14.384942
7902 11:48:14.385010 Set Vref, RX VrefLevel [Byte0]: 61
7903 11:48:14.388451 [Byte1]: 61
7904 11:48:14.392617
7905 11:48:14.392702 Set Vref, RX VrefLevel [Byte0]: 62
7906 11:48:14.396131 [Byte1]: 62
7907 11:48:14.400149
7908 11:48:14.400238 Set Vref, RX VrefLevel [Byte0]: 63
7909 11:48:14.403534 [Byte1]: 63
7910 11:48:14.408060
7911 11:48:14.408133 Set Vref, RX VrefLevel [Byte0]: 64
7912 11:48:14.410834 [Byte1]: 64
7913 11:48:14.415655
7914 11:48:14.415721 Set Vref, RX VrefLevel [Byte0]: 65
7915 11:48:14.418706 [Byte1]: 65
7916 11:48:14.423229
7917 11:48:14.423297 Set Vref, RX VrefLevel [Byte0]: 66
7918 11:48:14.426613 [Byte1]: 66
7919 11:48:14.430878
7920 11:48:14.430954 Set Vref, RX VrefLevel [Byte0]: 67
7921 11:48:14.433697 [Byte1]: 67
7922 11:48:14.438578
7923 11:48:14.438646 Set Vref, RX VrefLevel [Byte0]: 68
7924 11:48:14.441481 [Byte1]: 68
7925 11:48:14.445777
7926 11:48:14.445857 Set Vref, RX VrefLevel [Byte0]: 69
7927 11:48:14.449106 [Byte1]: 69
7928 11:48:14.453581
7929 11:48:14.453651 Set Vref, RX VrefLevel [Byte0]: 70
7930 11:48:14.456884 [Byte1]: 70
7931 11:48:14.461056
7932 11:48:14.461134 Set Vref, RX VrefLevel [Byte0]: 71
7933 11:48:14.464377 [Byte1]: 71
7934 11:48:14.468694
7935 11:48:14.468765 Set Vref, RX VrefLevel [Byte0]: 72
7936 11:48:14.471991 [Byte1]: 72
7937 11:48:14.476529
7938 11:48:14.476601 Set Vref, RX VrefLevel [Byte0]: 73
7939 11:48:14.479895 [Byte1]: 73
7940 11:48:14.484105
7941 11:48:14.484176 Set Vref, RX VrefLevel [Byte0]: 74
7942 11:48:14.487348 [Byte1]: 74
7943 11:48:14.491631
7944 11:48:14.491703 Set Vref, RX VrefLevel [Byte0]: 75
7945 11:48:14.495180 [Byte1]: 75
7946 11:48:14.499244
7947 11:48:14.499320 Final RX Vref Byte 0 = 61 to rank0
7948 11:48:14.502703 Final RX Vref Byte 1 = 62 to rank0
7949 11:48:14.505638 Final RX Vref Byte 0 = 61 to rank1
7950 11:48:14.509105 Final RX Vref Byte 1 = 62 to rank1==
7951 11:48:14.512370 Dram Type= 6, Freq= 0, CH_0, rank 0
7952 11:48:14.519194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 11:48:14.519300 ==
7954 11:48:14.519366 DQS Delay:
7955 11:48:14.519424 DQS0 = 0, DQS1 = 0
7956 11:48:14.522519 DQM Delay:
7957 11:48:14.522593 DQM0 = 125, DQM1 = 120
7958 11:48:14.525807 DQ Delay:
7959 11:48:14.528932 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
7960 11:48:14.532078 DQ4 =124, DQ5 =112, DQ6 =132, DQ7 =138
7961 11:48:14.535519 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =116
7962 11:48:14.538941 DQ12 =126, DQ13 =124, DQ14 =132, DQ15 =128
7963 11:48:14.539048
7964 11:48:14.539138
7965 11:48:14.539264
7966 11:48:14.542389 [DramC_TX_OE_Calibration] TA2
7967 11:48:14.545806 Original DQ_B0 (3 6) =30, OEN = 27
7968 11:48:14.548704 Original DQ_B1 (3 6) =30, OEN = 27
7969 11:48:14.552150 24, 0x0, End_B0=24 End_B1=24
7970 11:48:14.552253 25, 0x0, End_B0=25 End_B1=25
7971 11:48:14.555697 26, 0x0, End_B0=26 End_B1=26
7972 11:48:14.558614 27, 0x0, End_B0=27 End_B1=27
7973 11:48:14.561935 28, 0x0, End_B0=28 End_B1=28
7974 11:48:14.565809 29, 0x0, End_B0=29 End_B1=29
7975 11:48:14.565891 30, 0x0, End_B0=30 End_B1=30
7976 11:48:14.568613 31, 0x4141, End_B0=30 End_B1=30
7977 11:48:14.571938 Byte0 end_step=30 best_step=27
7978 11:48:14.575305 Byte1 end_step=30 best_step=27
7979 11:48:14.578803 Byte0 TX OE(2T, 0.5T) = (3, 3)
7980 11:48:14.582035 Byte1 TX OE(2T, 0.5T) = (3, 3)
7981 11:48:14.582109
7982 11:48:14.582170
7983 11:48:14.588966 [DQSOSCAuto] RK0, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
7984 11:48:14.591850 CH0 RK0: MR19=303, MR18=1312
7985 11:48:14.598809 CH0_RK0: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
7986 11:48:14.598890
7987 11:48:14.601748 ----->DramcWriteLeveling(PI) begin...
7988 11:48:14.601826 ==
7989 11:48:14.605247 Dram Type= 6, Freq= 0, CH_0, rank 1
7990 11:48:14.608394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7991 11:48:14.608470 ==
7992 11:48:14.612040 Write leveling (Byte 0): 32 => 32
7993 11:48:14.615031 Write leveling (Byte 1): 28 => 28
7994 11:48:14.618496 DramcWriteLeveling(PI) end<-----
7995 11:48:14.618602
7996 11:48:14.618692 ==
7997 11:48:14.621762 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 11:48:14.625098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 11:48:14.625175 ==
8000 11:48:14.628591 [Gating] SW mode calibration
8001 11:48:14.634914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8002 11:48:14.641614 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8003 11:48:14.644971 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 11:48:14.651452 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 11:48:14.654878 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 11:48:14.658401 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8007 11:48:14.664777 1 4 16 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
8008 11:48:14.668159 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 11:48:14.671446 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 11:48:14.677994 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 11:48:14.681155 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 11:48:14.684757 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8013 11:48:14.691245 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8014 11:48:14.694721 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8015 11:48:14.697658 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8016 11:48:14.704709 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 11:48:14.708094 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 11:48:14.710979 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 11:48:14.717434 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 11:48:14.720800 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 11:48:14.724385 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8022 11:48:14.727620 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8023 11:48:14.733910 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8024 11:48:14.737676 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 11:48:14.740933 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 11:48:14.747320 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 11:48:14.750628 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 11:48:14.753962 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 11:48:14.760819 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 11:48:14.764347 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8031 11:48:14.767287 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 11:48:14.774071 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8033 11:48:14.776974 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 11:48:14.780309 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 11:48:14.787006 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 11:48:14.790149 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 11:48:14.793464 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 11:48:14.800365 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 11:48:14.804026 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 11:48:14.806792 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 11:48:14.813908 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 11:48:14.816756 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 11:48:14.820367 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 11:48:14.826953 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 11:48:14.829917 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 11:48:14.833120 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 11:48:14.840163 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8048 11:48:14.843191 Total UI for P1: 0, mck2ui 16
8049 11:48:14.846596 best dqsien dly found for B0: ( 1, 9, 10)
8050 11:48:14.849894 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8051 11:48:14.853416 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 11:48:14.856981 Total UI for P1: 0, mck2ui 16
8053 11:48:14.859946 best dqsien dly found for B1: ( 1, 9, 20)
8054 11:48:14.863059 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8055 11:48:14.866932 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8056 11:48:14.867011
8057 11:48:14.873067 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8058 11:48:14.876684 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8059 11:48:14.879944 [Gating] SW calibration Done
8060 11:48:14.880016 ==
8061 11:48:14.883370 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 11:48:14.886358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 11:48:14.886436 ==
8064 11:48:14.886499 RX Vref Scan: 0
8065 11:48:14.886562
8066 11:48:14.889787 RX Vref 0 -> 0, step: 1
8067 11:48:14.889874
8068 11:48:14.893144 RX Delay 0 -> 252, step: 8
8069 11:48:14.896547 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8070 11:48:14.900043 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8071 11:48:14.903046 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8072 11:48:14.910133 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8073 11:48:14.912985 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8074 11:48:14.916500 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8075 11:48:14.920105 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8076 11:48:14.923004 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8077 11:48:14.930050 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8078 11:48:14.932985 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8079 11:48:14.936553 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8080 11:48:14.939803 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8081 11:48:14.946047 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8082 11:48:14.949465 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8083 11:48:14.953004 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8084 11:48:14.956488 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8085 11:48:14.956563 ==
8086 11:48:14.959327 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 11:48:14.962977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 11:48:14.965955 ==
8089 11:48:14.966031 DQS Delay:
8090 11:48:14.966096 DQS0 = 0, DQS1 = 0
8091 11:48:14.969371 DQM Delay:
8092 11:48:14.969443 DQM0 = 128, DQM1 = 122
8093 11:48:14.972550 DQ Delay:
8094 11:48:14.975886 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8095 11:48:14.979108 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8096 11:48:14.982501 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8097 11:48:14.986008 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8098 11:48:14.986086
8099 11:48:14.986153
8100 11:48:14.986211 ==
8101 11:48:14.989525 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 11:48:14.992435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 11:48:14.992508 ==
8104 11:48:14.996034
8105 11:48:14.996140
8106 11:48:14.996238 TX Vref Scan disable
8107 11:48:14.999442 == TX Byte 0 ==
8108 11:48:15.002651 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8109 11:48:15.006116 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8110 11:48:15.009564 == TX Byte 1 ==
8111 11:48:15.012863 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8112 11:48:15.016084 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8113 11:48:15.016165 ==
8114 11:48:15.019461 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 11:48:15.025823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 11:48:15.025906 ==
8117 11:48:15.038079
8118 11:48:15.041502 TX Vref early break, caculate TX vref
8119 11:48:15.044486 TX Vref=16, minBit 1, minWin=21, winSum=364
8120 11:48:15.047966 TX Vref=18, minBit 8, minWin=22, winSum=374
8121 11:48:15.051380 TX Vref=20, minBit 8, minWin=22, winSum=380
8122 11:48:15.054871 TX Vref=22, minBit 1, minWin=23, winSum=391
8123 11:48:15.057664 TX Vref=24, minBit 1, minWin=23, winSum=397
8124 11:48:15.064826 TX Vref=26, minBit 9, minWin=24, winSum=410
8125 11:48:15.068016 TX Vref=28, minBit 0, minWin=25, winSum=409
8126 11:48:15.071271 TX Vref=30, minBit 8, minWin=24, winSum=409
8127 11:48:15.074399 TX Vref=32, minBit 7, minWin=24, winSum=401
8128 11:48:15.077508 TX Vref=34, minBit 8, minWin=22, winSum=386
8129 11:48:15.084392 [TxChooseVref] Worse bit 0, Min win 25, Win sum 409, Final Vref 28
8130 11:48:15.084471
8131 11:48:15.087550 Final TX Range 0 Vref 28
8132 11:48:15.087644
8133 11:48:15.087712 ==
8134 11:48:15.090813 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 11:48:15.094512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 11:48:15.094591 ==
8137 11:48:15.094654
8138 11:48:15.094717
8139 11:48:15.097937 TX Vref Scan disable
8140 11:48:15.104367 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8141 11:48:15.104443 == TX Byte 0 ==
8142 11:48:15.107848 u2DelayCellOfst[0]=11 cells (3 PI)
8143 11:48:15.111124 u2DelayCellOfst[1]=18 cells (5 PI)
8144 11:48:15.114419 u2DelayCellOfst[2]=11 cells (3 PI)
8145 11:48:15.117872 u2DelayCellOfst[3]=11 cells (3 PI)
8146 11:48:15.120716 u2DelayCellOfst[4]=7 cells (2 PI)
8147 11:48:15.124663 u2DelayCellOfst[5]=0 cells (0 PI)
8148 11:48:15.127443 u2DelayCellOfst[6]=18 cells (5 PI)
8149 11:48:15.130881 u2DelayCellOfst[7]=18 cells (5 PI)
8150 11:48:15.134351 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8151 11:48:15.137705 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8152 11:48:15.141264 == TX Byte 1 ==
8153 11:48:15.141339 u2DelayCellOfst[8]=0 cells (0 PI)
8154 11:48:15.144126 u2DelayCellOfst[9]=3 cells (1 PI)
8155 11:48:15.147513 u2DelayCellOfst[10]=11 cells (3 PI)
8156 11:48:15.151118 u2DelayCellOfst[11]=7 cells (2 PI)
8157 11:48:15.154087 u2DelayCellOfst[12]=15 cells (4 PI)
8158 11:48:15.157600 u2DelayCellOfst[13]=15 cells (4 PI)
8159 11:48:15.160952 u2DelayCellOfst[14]=15 cells (4 PI)
8160 11:48:15.164162 u2DelayCellOfst[15]=15 cells (4 PI)
8161 11:48:15.167768 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8162 11:48:15.173996 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8163 11:48:15.174126 DramC Write-DBI on
8164 11:48:15.174222 ==
8165 11:48:15.177070 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 11:48:15.180673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 11:48:15.183951 ==
8168 11:48:15.184062
8169 11:48:15.184168
8170 11:48:15.184287 TX Vref Scan disable
8171 11:48:15.187410 == TX Byte 0 ==
8172 11:48:15.190848 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8173 11:48:15.194345 == TX Byte 1 ==
8174 11:48:15.197543 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8175 11:48:15.200754 DramC Write-DBI off
8176 11:48:15.200859
8177 11:48:15.200952 [DATLAT]
8178 11:48:15.201068 Freq=1600, CH0 RK1
8179 11:48:15.201229
8180 11:48:15.203958 DATLAT Default: 0xf
8181 11:48:15.204051 0, 0xFFFF, sum = 0
8182 11:48:15.207418 1, 0xFFFF, sum = 0
8183 11:48:15.210807 2, 0xFFFF, sum = 0
8184 11:48:15.210884 3, 0xFFFF, sum = 0
8185 11:48:15.213811 4, 0xFFFF, sum = 0
8186 11:48:15.213920 5, 0xFFFF, sum = 0
8187 11:48:15.217544 6, 0xFFFF, sum = 0
8188 11:48:15.217650 7, 0xFFFF, sum = 0
8189 11:48:15.220393 8, 0xFFFF, sum = 0
8190 11:48:15.220471 9, 0xFFFF, sum = 0
8191 11:48:15.224092 10, 0xFFFF, sum = 0
8192 11:48:15.224196 11, 0xFFFF, sum = 0
8193 11:48:15.226925 12, 0xFFFF, sum = 0
8194 11:48:15.227028 13, 0xCFFF, sum = 0
8195 11:48:15.230668 14, 0x0, sum = 1
8196 11:48:15.230758 15, 0x0, sum = 2
8197 11:48:15.234077 16, 0x0, sum = 3
8198 11:48:15.234156 17, 0x0, sum = 4
8199 11:48:15.237010 best_step = 15
8200 11:48:15.237084
8201 11:48:15.237148 ==
8202 11:48:15.240454 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 11:48:15.243417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 11:48:15.243492 ==
8205 11:48:15.246868 RX Vref Scan: 0
8206 11:48:15.246946
8207 11:48:15.247011 RX Vref 0 -> 0, step: 1
8208 11:48:15.247069
8209 11:48:15.250251 RX Delay 3 -> 252, step: 4
8210 11:48:15.253845 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8211 11:48:15.260269 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8212 11:48:15.263791 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8213 11:48:15.267187 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8214 11:48:15.270500 iDelay=191, Bit 4, Center 122 (67 ~ 178) 112
8215 11:48:15.273726 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8216 11:48:15.280167 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8217 11:48:15.283669 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8218 11:48:15.286657 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8219 11:48:15.289982 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8220 11:48:15.293648 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8221 11:48:15.299728 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8222 11:48:15.303508 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8223 11:48:15.306563 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8224 11:48:15.309767 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8225 11:48:15.316873 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8226 11:48:15.316951 ==
8227 11:48:15.319739 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 11:48:15.323298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 11:48:15.323411 ==
8230 11:48:15.323505 DQS Delay:
8231 11:48:15.326635 DQS0 = 0, DQS1 = 0
8232 11:48:15.326739 DQM Delay:
8233 11:48:15.329918 DQM0 = 124, DQM1 = 118
8234 11:48:15.330029 DQ Delay:
8235 11:48:15.333090 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8236 11:48:15.336426 DQ4 =122, DQ5 =112, DQ6 =134, DQ7 =134
8237 11:48:15.339724 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8238 11:48:15.343326 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8239 11:48:15.343425
8240 11:48:15.346279
8241 11:48:15.346390
8242 11:48:15.346484 [DramC_TX_OE_Calibration] TA2
8243 11:48:15.349673 Original DQ_B0 (3 6) =30, OEN = 27
8244 11:48:15.352725 Original DQ_B1 (3 6) =30, OEN = 27
8245 11:48:15.356098 24, 0x0, End_B0=24 End_B1=24
8246 11:48:15.359705 25, 0x0, End_B0=25 End_B1=25
8247 11:48:15.362546 26, 0x0, End_B0=26 End_B1=26
8248 11:48:15.362621 27, 0x0, End_B0=27 End_B1=27
8249 11:48:15.366097 28, 0x0, End_B0=28 End_B1=28
8250 11:48:15.369705 29, 0x0, End_B0=29 End_B1=29
8251 11:48:15.372602 30, 0x0, End_B0=30 End_B1=30
8252 11:48:15.375935 31, 0x5151, End_B0=30 End_B1=30
8253 11:48:15.376046 Byte0 end_step=30 best_step=27
8254 11:48:15.379665 Byte1 end_step=30 best_step=27
8255 11:48:15.383155 Byte0 TX OE(2T, 0.5T) = (3, 3)
8256 11:48:15.386052 Byte1 TX OE(2T, 0.5T) = (3, 3)
8257 11:48:15.386163
8258 11:48:15.386252
8259 11:48:15.392597 [DQSOSCAuto] RK1, (LSB)MR18= 0x2613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
8260 11:48:15.396049 CH0 RK1: MR19=303, MR18=2613
8261 11:48:15.402936 CH0_RK1: MR19=0x303, MR18=0x2613, DQSOSC=390, MR23=63, INC=24, DEC=16
8262 11:48:15.406023 [RxdqsGatingPostProcess] freq 1600
8263 11:48:15.412483 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8264 11:48:15.416049 best DQS0 dly(2T, 0.5T) = (1, 1)
8265 11:48:15.416129 best DQS1 dly(2T, 0.5T) = (1, 1)
8266 11:48:15.419140 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8267 11:48:15.422498 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8268 11:48:15.426143 best DQS0 dly(2T, 0.5T) = (1, 1)
8269 11:48:15.429348 best DQS1 dly(2T, 0.5T) = (1, 1)
8270 11:48:15.432295 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8271 11:48:15.435773 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8272 11:48:15.439026 Pre-setting of DQS Precalculation
8273 11:48:15.445860 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8274 11:48:15.445940 ==
8275 11:48:15.448673 Dram Type= 6, Freq= 0, CH_1, rank 0
8276 11:48:15.452328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8277 11:48:15.452406 ==
8278 11:48:15.458597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8279 11:48:15.462185 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8280 11:48:15.465648 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8281 11:48:15.472153 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8282 11:48:15.480473 [CA 0] Center 41 (12~71) winsize 60
8283 11:48:15.483645 [CA 1] Center 42 (13~72) winsize 60
8284 11:48:15.486946 [CA 2] Center 38 (9~67) winsize 59
8285 11:48:15.490645 [CA 3] Center 37 (8~67) winsize 60
8286 11:48:15.493591 [CA 4] Center 37 (8~67) winsize 60
8287 11:48:15.497091 [CA 5] Center 36 (7~66) winsize 60
8288 11:48:15.497184
8289 11:48:15.500593 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8290 11:48:15.500701
8291 11:48:15.503900 [CATrainingPosCal] consider 1 rank data
8292 11:48:15.507456 u2DelayCellTimex100 = 258/100 ps
8293 11:48:15.510732 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8294 11:48:15.517210 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8295 11:48:15.520458 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8296 11:48:15.523855 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
8297 11:48:15.527065 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8298 11:48:15.530178 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8299 11:48:15.530276
8300 11:48:15.533476 CA PerBit enable=1, Macro0, CA PI delay=36
8301 11:48:15.533564
8302 11:48:15.536663 [CBTSetCACLKResult] CA Dly = 36
8303 11:48:15.540412 CS Dly: 10 (0~41)
8304 11:48:15.543493 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8305 11:48:15.546698 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8306 11:48:15.546823 ==
8307 11:48:15.550323 Dram Type= 6, Freq= 0, CH_1, rank 1
8308 11:48:15.553530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 11:48:15.556811 ==
8310 11:48:15.560345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8311 11:48:15.563248 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8312 11:48:15.570367 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8313 11:48:15.576781 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8314 11:48:15.583888 [CA 0] Center 42 (13~71) winsize 59
8315 11:48:15.587284 [CA 1] Center 42 (12~72) winsize 61
8316 11:48:15.590173 [CA 2] Center 37 (8~67) winsize 60
8317 11:48:15.593531 [CA 3] Center 37 (8~66) winsize 59
8318 11:48:15.597364 [CA 4] Center 38 (8~68) winsize 61
8319 11:48:15.600670 [CA 5] Center 37 (7~67) winsize 61
8320 11:48:15.600748
8321 11:48:15.603575 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8322 11:48:15.603676
8323 11:48:15.607169 [CATrainingPosCal] consider 2 rank data
8324 11:48:15.610615 u2DelayCellTimex100 = 258/100 ps
8325 11:48:15.613999 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8326 11:48:15.620554 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8327 11:48:15.623888 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8328 11:48:15.627276 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8329 11:48:15.630218 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8330 11:48:15.633458 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8331 11:48:15.633548
8332 11:48:15.636780 CA PerBit enable=1, Macro0, CA PI delay=36
8333 11:48:15.636863
8334 11:48:15.640069 [CBTSetCACLKResult] CA Dly = 36
8335 11:48:15.643213 CS Dly: 11 (0~43)
8336 11:48:15.646619 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8337 11:48:15.649822 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8338 11:48:15.649949
8339 11:48:15.653132 ----->DramcWriteLeveling(PI) begin...
8340 11:48:15.653221 ==
8341 11:48:15.656667 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 11:48:15.663120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 11:48:15.663204 ==
8344 11:48:15.666899 Write leveling (Byte 0): 24 => 24
8345 11:48:15.666995 Write leveling (Byte 1): 27 => 27
8346 11:48:15.669771 DramcWriteLeveling(PI) end<-----
8347 11:48:15.669853
8348 11:48:15.669918 ==
8349 11:48:15.673394 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 11:48:15.679910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 11:48:15.679991 ==
8352 11:48:15.682905 [Gating] SW mode calibration
8353 11:48:15.689889 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8354 11:48:15.692745 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8355 11:48:15.699355 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 11:48:15.702646 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 11:48:15.706008 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 11:48:15.712992 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 11:48:15.716414 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 11:48:15.719343 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 11:48:15.726164 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 11:48:15.729496 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 11:48:15.732559 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 11:48:15.738925 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 11:48:15.742427 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 11:48:15.745501 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 11:48:15.752506 1 5 16 | B1->B0 | 2424 2424 | 0 0 | (0 0) (1 0)
8368 11:48:15.755871 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 11:48:15.759359 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 11:48:15.765635 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 11:48:15.768696 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 11:48:15.771927 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 11:48:15.778847 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 11:48:15.782331 1 6 12 | B1->B0 | 2929 2424 | 0 0 | (1 1) (0 0)
8375 11:48:15.785280 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8376 11:48:15.791727 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 11:48:15.795227 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 11:48:15.798741 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 11:48:15.805105 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 11:48:15.808484 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 11:48:15.811896 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 11:48:15.818734 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8383 11:48:15.821609 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8384 11:48:15.825160 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 11:48:15.831457 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 11:48:15.834885 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 11:48:15.838054 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 11:48:15.844685 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 11:48:15.848115 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 11:48:15.851546 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 11:48:15.857989 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 11:48:15.861369 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 11:48:15.864520 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 11:48:15.871369 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 11:48:15.874502 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 11:48:15.877770 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 11:48:15.884209 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 11:48:15.888096 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8399 11:48:15.890933 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8400 11:48:15.897414 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8401 11:48:15.897510 Total UI for P1: 0, mck2ui 16
8402 11:48:15.900965 best dqsien dly found for B0: ( 1, 9, 16)
8403 11:48:15.907498 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 11:48:15.911018 Total UI for P1: 0, mck2ui 16
8405 11:48:15.914000 best dqsien dly found for B1: ( 1, 9, 16)
8406 11:48:15.917294 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8407 11:48:15.921059 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8408 11:48:15.921141
8409 11:48:15.924450 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8410 11:48:15.927397 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8411 11:48:15.930734 [Gating] SW calibration Done
8412 11:48:15.930842 ==
8413 11:48:15.934206 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 11:48:15.937123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 11:48:15.940517 ==
8416 11:48:15.940646 RX Vref Scan: 0
8417 11:48:15.940710
8418 11:48:15.943936 RX Vref 0 -> 0, step: 1
8419 11:48:15.944030
8420 11:48:15.944095 RX Delay 0 -> 252, step: 8
8421 11:48:15.950431 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8422 11:48:15.953852 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8423 11:48:15.957345 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8424 11:48:15.960827 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8425 11:48:15.964020 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8426 11:48:15.970299 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8427 11:48:15.973877 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8428 11:48:15.976925 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8429 11:48:15.980223 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8430 11:48:15.983420 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8431 11:48:15.990407 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8432 11:48:15.993454 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8433 11:48:15.996848 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8434 11:48:16.000057 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8435 11:48:16.006391 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8436 11:48:16.009951 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8437 11:48:16.010035 ==
8438 11:48:16.012833 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 11:48:16.016260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 11:48:16.016343 ==
8441 11:48:16.019669 DQS Delay:
8442 11:48:16.019751 DQS0 = 0, DQS1 = 0
8443 11:48:16.019817 DQM Delay:
8444 11:48:16.023162 DQM0 = 132, DQM1 = 126
8445 11:48:16.023272 DQ Delay:
8446 11:48:16.026058 DQ0 =135, DQ1 =127, DQ2 =123, DQ3 =131
8447 11:48:16.029734 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8448 11:48:16.035936 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8449 11:48:16.039387 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8450 11:48:16.039471
8451 11:48:16.039536
8452 11:48:16.039597 ==
8453 11:48:16.042870 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 11:48:16.046293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 11:48:16.046377 ==
8456 11:48:16.046443
8457 11:48:16.046504
8458 11:48:16.049295 TX Vref Scan disable
8459 11:48:16.052654 == TX Byte 0 ==
8460 11:48:16.056322 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8461 11:48:16.059269 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8462 11:48:16.062752 == TX Byte 1 ==
8463 11:48:16.065746 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8464 11:48:16.069386 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8465 11:48:16.069468 ==
8466 11:48:16.072921 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 11:48:16.076206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 11:48:16.079014 ==
8469 11:48:16.090268
8470 11:48:16.093635 TX Vref early break, caculate TX vref
8471 11:48:16.096867 TX Vref=16, minBit 10, minWin=21, winSum=363
8472 11:48:16.100188 TX Vref=18, minBit 5, minWin=22, winSum=372
8473 11:48:16.103461 TX Vref=20, minBit 8, minWin=23, winSum=385
8474 11:48:16.106414 TX Vref=22, minBit 10, minWin=23, winSum=390
8475 11:48:16.110160 TX Vref=24, minBit 0, minWin=24, winSum=405
8476 11:48:16.116543 TX Vref=26, minBit 5, minWin=24, winSum=411
8477 11:48:16.119974 TX Vref=28, minBit 1, minWin=24, winSum=417
8478 11:48:16.123423 TX Vref=30, minBit 1, minWin=24, winSum=414
8479 11:48:16.126284 TX Vref=32, minBit 0, minWin=23, winSum=402
8480 11:48:16.130030 TX Vref=34, minBit 0, minWin=23, winSum=392
8481 11:48:16.136605 [TxChooseVref] Worse bit 1, Min win 24, Win sum 417, Final Vref 28
8482 11:48:16.136729
8483 11:48:16.139860 Final TX Range 0 Vref 28
8484 11:48:16.139958
8485 11:48:16.140037 ==
8486 11:48:16.143118 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 11:48:16.146639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 11:48:16.146738 ==
8489 11:48:16.146834
8490 11:48:16.146910
8491 11:48:16.149653 TX Vref Scan disable
8492 11:48:16.156216 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8493 11:48:16.156356 == TX Byte 0 ==
8494 11:48:16.159613 u2DelayCellOfst[0]=22 cells (6 PI)
8495 11:48:16.162884 u2DelayCellOfst[1]=18 cells (5 PI)
8496 11:48:16.166122 u2DelayCellOfst[2]=0 cells (0 PI)
8497 11:48:16.169787 u2DelayCellOfst[3]=7 cells (2 PI)
8498 11:48:16.173289 u2DelayCellOfst[4]=11 cells (3 PI)
8499 11:48:16.176144 u2DelayCellOfst[5]=22 cells (6 PI)
8500 11:48:16.179668 u2DelayCellOfst[6]=22 cells (6 PI)
8501 11:48:16.183156 u2DelayCellOfst[7]=7 cells (2 PI)
8502 11:48:16.186013 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8503 11:48:16.189538 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8504 11:48:16.192764 == TX Byte 1 ==
8505 11:48:16.196078 u2DelayCellOfst[8]=0 cells (0 PI)
8506 11:48:16.196185 u2DelayCellOfst[9]=3 cells (1 PI)
8507 11:48:16.199549 u2DelayCellOfst[10]=11 cells (3 PI)
8508 11:48:16.202788 u2DelayCellOfst[11]=7 cells (2 PI)
8509 11:48:16.206097 u2DelayCellOfst[12]=15 cells (4 PI)
8510 11:48:16.209452 u2DelayCellOfst[13]=18 cells (5 PI)
8511 11:48:16.212558 u2DelayCellOfst[14]=18 cells (5 PI)
8512 11:48:16.216077 u2DelayCellOfst[15]=18 cells (5 PI)
8513 11:48:16.219007 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8514 11:48:16.226234 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8515 11:48:16.226342 DramC Write-DBI on
8516 11:48:16.226440 ==
8517 11:48:16.229051 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 11:48:16.236011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 11:48:16.236135 ==
8520 11:48:16.236251
8521 11:48:16.236314
8522 11:48:16.236377 TX Vref Scan disable
8523 11:48:16.239622 == TX Byte 0 ==
8524 11:48:16.242986 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8525 11:48:16.246237 == TX Byte 1 ==
8526 11:48:16.249397 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8527 11:48:16.252808 DramC Write-DBI off
8528 11:48:16.252915
8529 11:48:16.253007 [DATLAT]
8530 11:48:16.253102 Freq=1600, CH1 RK0
8531 11:48:16.253198
8532 11:48:16.256421 DATLAT Default: 0xf
8533 11:48:16.256539 0, 0xFFFF, sum = 0
8534 11:48:16.259889 1, 0xFFFF, sum = 0
8535 11:48:16.259994 2, 0xFFFF, sum = 0
8536 11:48:16.263302 3, 0xFFFF, sum = 0
8537 11:48:16.266615 4, 0xFFFF, sum = 0
8538 11:48:16.266718 5, 0xFFFF, sum = 0
8539 11:48:16.269756 6, 0xFFFF, sum = 0
8540 11:48:16.269860 7, 0xFFFF, sum = 0
8541 11:48:16.272745 8, 0xFFFF, sum = 0
8542 11:48:16.272846 9, 0xFFFF, sum = 0
8543 11:48:16.276341 10, 0xFFFF, sum = 0
8544 11:48:16.276441 11, 0xFFFF, sum = 0
8545 11:48:16.279326 12, 0xFFFF, sum = 0
8546 11:48:16.279439 13, 0x8FFF, sum = 0
8547 11:48:16.282795 14, 0x0, sum = 1
8548 11:48:16.282894 15, 0x0, sum = 2
8549 11:48:16.286333 16, 0x0, sum = 3
8550 11:48:16.286432 17, 0x0, sum = 4
8551 11:48:16.289698 best_step = 15
8552 11:48:16.289796
8553 11:48:16.289892 ==
8554 11:48:16.292559 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 11:48:16.295997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 11:48:16.296095 ==
8557 11:48:16.299505 RX Vref Scan: 1
8558 11:48:16.299604
8559 11:48:16.299699 Set Vref Range= 24 -> 127
8560 11:48:16.299775
8561 11:48:16.302483 RX Vref 24 -> 127, step: 1
8562 11:48:16.302582
8563 11:48:16.305906 RX Delay 11 -> 252, step: 4
8564 11:48:16.306003
8565 11:48:16.309072 Set Vref, RX VrefLevel [Byte0]: 24
8566 11:48:16.312528 [Byte1]: 24
8567 11:48:16.312641
8568 11:48:16.316068 Set Vref, RX VrefLevel [Byte0]: 25
8569 11:48:16.319364 [Byte1]: 25
8570 11:48:16.322435
8571 11:48:16.322540 Set Vref, RX VrefLevel [Byte0]: 26
8572 11:48:16.325479 [Byte1]: 26
8573 11:48:16.329867
8574 11:48:16.329965 Set Vref, RX VrefLevel [Byte0]: 27
8575 11:48:16.333254 [Byte1]: 27
8576 11:48:16.337777
8577 11:48:16.337877 Set Vref, RX VrefLevel [Byte0]: 28
8578 11:48:16.341274 [Byte1]: 28
8579 11:48:16.345267
8580 11:48:16.345365 Set Vref, RX VrefLevel [Byte0]: 29
8581 11:48:16.348719 [Byte1]: 29
8582 11:48:16.352753
8583 11:48:16.352851 Set Vref, RX VrefLevel [Byte0]: 30
8584 11:48:16.356058 [Byte1]: 30
8585 11:48:16.360688
8586 11:48:16.360787 Set Vref, RX VrefLevel [Byte0]: 31
8587 11:48:16.364216 [Byte1]: 31
8588 11:48:16.368342
8589 11:48:16.368440 Set Vref, RX VrefLevel [Byte0]: 32
8590 11:48:16.371193 [Byte1]: 32
8591 11:48:16.375832
8592 11:48:16.375945 Set Vref, RX VrefLevel [Byte0]: 33
8593 11:48:16.379023 [Byte1]: 33
8594 11:48:16.383316
8595 11:48:16.383413 Set Vref, RX VrefLevel [Byte0]: 34
8596 11:48:16.386810 [Byte1]: 34
8597 11:48:16.390909
8598 11:48:16.391062 Set Vref, RX VrefLevel [Byte0]: 35
8599 11:48:16.394315 [Byte1]: 35
8600 11:48:16.398905
8601 11:48:16.399002 Set Vref, RX VrefLevel [Byte0]: 36
8602 11:48:16.401753 [Byte1]: 36
8603 11:48:16.406398
8604 11:48:16.406495 Set Vref, RX VrefLevel [Byte0]: 37
8605 11:48:16.409309 [Byte1]: 37
8606 11:48:16.414019
8607 11:48:16.414099 Set Vref, RX VrefLevel [Byte0]: 38
8608 11:48:16.416997 [Byte1]: 38
8609 11:48:16.421420
8610 11:48:16.421518 Set Vref, RX VrefLevel [Byte0]: 39
8611 11:48:16.424746 [Byte1]: 39
8612 11:48:16.429275
8613 11:48:16.429392 Set Vref, RX VrefLevel [Byte0]: 40
8614 11:48:16.432082 [Byte1]: 40
8615 11:48:16.436552
8616 11:48:16.436636 Set Vref, RX VrefLevel [Byte0]: 41
8617 11:48:16.440136 [Byte1]: 41
8618 11:48:16.444102
8619 11:48:16.444234 Set Vref, RX VrefLevel [Byte0]: 42
8620 11:48:16.447446 [Byte1]: 42
8621 11:48:16.451580
8622 11:48:16.451691 Set Vref, RX VrefLevel [Byte0]: 43
8623 11:48:16.455168 [Byte1]: 43
8624 11:48:16.459628
8625 11:48:16.459738 Set Vref, RX VrefLevel [Byte0]: 44
8626 11:48:16.462907 [Byte1]: 44
8627 11:48:16.467361
8628 11:48:16.467467 Set Vref, RX VrefLevel [Byte0]: 45
8629 11:48:16.470365 [Byte1]: 45
8630 11:48:16.474952
8631 11:48:16.475060 Set Vref, RX VrefLevel [Byte0]: 46
8632 11:48:16.477915 [Byte1]: 46
8633 11:48:16.482493
8634 11:48:16.482597 Set Vref, RX VrefLevel [Byte0]: 47
8635 11:48:16.485777 [Byte1]: 47
8636 11:48:16.490137
8637 11:48:16.490240 Set Vref, RX VrefLevel [Byte0]: 48
8638 11:48:16.493059 [Byte1]: 48
8639 11:48:16.497603
8640 11:48:16.497686 Set Vref, RX VrefLevel [Byte0]: 49
8641 11:48:16.500866 [Byte1]: 49
8642 11:48:16.505068
8643 11:48:16.505169 Set Vref, RX VrefLevel [Byte0]: 50
8644 11:48:16.508573 [Byte1]: 50
8645 11:48:16.512715
8646 11:48:16.512795 Set Vref, RX VrefLevel [Byte0]: 51
8647 11:48:16.516199 [Byte1]: 51
8648 11:48:16.520411
8649 11:48:16.520524 Set Vref, RX VrefLevel [Byte0]: 52
8650 11:48:16.523785 [Byte1]: 52
8651 11:48:16.527835
8652 11:48:16.527938 Set Vref, RX VrefLevel [Byte0]: 53
8653 11:48:16.531239 [Byte1]: 53
8654 11:48:16.535685
8655 11:48:16.535800 Set Vref, RX VrefLevel [Byte0]: 54
8656 11:48:16.539036 [Byte1]: 54
8657 11:48:16.543120
8658 11:48:16.543222 Set Vref, RX VrefLevel [Byte0]: 55
8659 11:48:16.546514 [Byte1]: 55
8660 11:48:16.550937
8661 11:48:16.551038 Set Vref, RX VrefLevel [Byte0]: 56
8662 11:48:16.553997 [Byte1]: 56
8663 11:48:16.558493
8664 11:48:16.558596 Set Vref, RX VrefLevel [Byte0]: 57
8665 11:48:16.561456 [Byte1]: 57
8666 11:48:16.565973
8667 11:48:16.566082 Set Vref, RX VrefLevel [Byte0]: 58
8668 11:48:16.569177 [Byte1]: 58
8669 11:48:16.573656
8670 11:48:16.573732 Set Vref, RX VrefLevel [Byte0]: 59
8671 11:48:16.577328 [Byte1]: 59
8672 11:48:16.581493
8673 11:48:16.581597 Set Vref, RX VrefLevel [Byte0]: 60
8674 11:48:16.584354 [Byte1]: 60
8675 11:48:16.588987
8676 11:48:16.589064 Set Vref, RX VrefLevel [Byte0]: 61
8677 11:48:16.592479 [Byte1]: 61
8678 11:48:16.596636
8679 11:48:16.596742 Set Vref, RX VrefLevel [Byte0]: 62
8680 11:48:16.600112 [Byte1]: 62
8681 11:48:16.603998
8682 11:48:16.604094 Set Vref, RX VrefLevel [Byte0]: 63
8683 11:48:16.607591 [Byte1]: 63
8684 11:48:16.611719
8685 11:48:16.611800 Set Vref, RX VrefLevel [Byte0]: 64
8686 11:48:16.615417 [Byte1]: 64
8687 11:48:16.619443
8688 11:48:16.619524 Set Vref, RX VrefLevel [Byte0]: 65
8689 11:48:16.622813 [Byte1]: 65
8690 11:48:16.626799
8691 11:48:16.626879 Set Vref, RX VrefLevel [Byte0]: 66
8692 11:48:16.630353 [Byte1]: 66
8693 11:48:16.634889
8694 11:48:16.634992 Set Vref, RX VrefLevel [Byte0]: 67
8695 11:48:16.638198 [Byte1]: 67
8696 11:48:16.642470
8697 11:48:16.642565 Set Vref, RX VrefLevel [Byte0]: 68
8698 11:48:16.645373 [Byte1]: 68
8699 11:48:16.650085
8700 11:48:16.650183 Set Vref, RX VrefLevel [Byte0]: 69
8701 11:48:16.652955 [Byte1]: 69
8702 11:48:16.657665
8703 11:48:16.657762 Set Vref, RX VrefLevel [Byte0]: 70
8704 11:48:16.660519 [Byte1]: 70
8705 11:48:16.665018
8706 11:48:16.665117 Set Vref, RX VrefLevel [Byte0]: 71
8707 11:48:16.668237 [Byte1]: 71
8708 11:48:16.672562
8709 11:48:16.672660 Final RX Vref Byte 0 = 57 to rank0
8710 11:48:16.675852 Final RX Vref Byte 1 = 57 to rank0
8711 11:48:16.679001 Final RX Vref Byte 0 = 57 to rank1
8712 11:48:16.682873 Final RX Vref Byte 1 = 57 to rank1==
8713 11:48:16.685973 Dram Type= 6, Freq= 0, CH_1, rank 0
8714 11:48:16.692557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8715 11:48:16.692689 ==
8716 11:48:16.692786 DQS Delay:
8717 11:48:16.692864 DQS0 = 0, DQS1 = 0
8718 11:48:16.696050 DQM Delay:
8719 11:48:16.696174 DQM0 = 131, DQM1 = 123
8720 11:48:16.699415 DQ Delay:
8721 11:48:16.702459 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130
8722 11:48:16.706054 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
8723 11:48:16.709000 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8724 11:48:16.712379 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8725 11:48:16.712489
8726 11:48:16.712599
8727 11:48:16.712687
8728 11:48:16.715727 [DramC_TX_OE_Calibration] TA2
8729 11:48:16.719224 Original DQ_B0 (3 6) =30, OEN = 27
8730 11:48:16.722742 Original DQ_B1 (3 6) =30, OEN = 27
8731 11:48:16.725564 24, 0x0, End_B0=24 End_B1=24
8732 11:48:16.725648 25, 0x0, End_B0=25 End_B1=25
8733 11:48:16.729061 26, 0x0, End_B0=26 End_B1=26
8734 11:48:16.732105 27, 0x0, End_B0=27 End_B1=27
8735 11:48:16.735702 28, 0x0, End_B0=28 End_B1=28
8736 11:48:16.739251 29, 0x0, End_B0=29 End_B1=29
8737 11:48:16.739333 30, 0x0, End_B0=30 End_B1=30
8738 11:48:16.742618 31, 0x4545, End_B0=30 End_B1=30
8739 11:48:16.745454 Byte0 end_step=30 best_step=27
8740 11:48:16.748654 Byte1 end_step=30 best_step=27
8741 11:48:16.752216 Byte0 TX OE(2T, 0.5T) = (3, 3)
8742 11:48:16.755684 Byte1 TX OE(2T, 0.5T) = (3, 3)
8743 11:48:16.755767
8744 11:48:16.755832
8745 11:48:16.762116 [DQSOSCAuto] RK0, (LSB)MR18= 0x70c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8746 11:48:16.765579 CH1 RK0: MR19=303, MR18=70C
8747 11:48:16.772214 CH1_RK0: MR19=0x303, MR18=0x70C, DQSOSC=403, MR23=63, INC=22, DEC=15
8748 11:48:16.772299
8749 11:48:16.775629 ----->DramcWriteLeveling(PI) begin...
8750 11:48:16.775712 ==
8751 11:48:16.779100 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 11:48:16.782020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8753 11:48:16.782108 ==
8754 11:48:16.785364 Write leveling (Byte 0): 23 => 23
8755 11:48:16.788769 Write leveling (Byte 1): 29 => 29
8756 11:48:16.792106 DramcWriteLeveling(PI) end<-----
8757 11:48:16.792221
8758 11:48:16.792288 ==
8759 11:48:16.795619 Dram Type= 6, Freq= 0, CH_1, rank 1
8760 11:48:16.798943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8761 11:48:16.799026 ==
8762 11:48:16.802179 [Gating] SW mode calibration
8763 11:48:16.808376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8764 11:48:16.815086 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8765 11:48:16.818823 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 11:48:16.821672 1 4 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8767 11:48:16.828476 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8768 11:48:16.832018 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8769 11:48:16.834918 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 11:48:16.841948 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 11:48:16.844834 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 11:48:16.848197 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 11:48:16.855040 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 11:48:16.858118 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8775 11:48:16.861674 1 5 8 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (1 0)
8776 11:48:16.868229 1 5 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
8777 11:48:16.871772 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 11:48:16.875102 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 11:48:16.881324 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 11:48:16.884897 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 11:48:16.888331 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 11:48:16.894342 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8783 11:48:16.898333 1 6 8 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
8784 11:48:16.901354 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8785 11:48:16.908099 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 11:48:16.911487 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 11:48:16.914416 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 11:48:16.921401 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 11:48:16.924489 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 11:48:16.927949 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 11:48:16.934570 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8792 11:48:16.937595 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8793 11:48:16.941205 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8794 11:48:16.947656 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 11:48:16.951068 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 11:48:16.954531 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 11:48:16.961466 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 11:48:16.964455 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 11:48:16.967906 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 11:48:16.974398 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 11:48:16.977881 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 11:48:16.981249 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 11:48:16.983977 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 11:48:16.990888 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 11:48:16.994348 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 11:48:16.997599 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 11:48:17.004100 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8808 11:48:17.007530 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8809 11:48:17.010933 Total UI for P1: 0, mck2ui 16
8810 11:48:17.013744 best dqsien dly found for B0: ( 1, 9, 8)
8811 11:48:17.017289 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8812 11:48:17.024109 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 11:48:17.027094 Total UI for P1: 0, mck2ui 16
8814 11:48:17.030620 best dqsien dly found for B1: ( 1, 9, 12)
8815 11:48:17.034109 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8816 11:48:17.037528 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8817 11:48:17.037612
8818 11:48:17.040575 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8819 11:48:17.043684 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8820 11:48:17.046850 [Gating] SW calibration Done
8821 11:48:17.046947 ==
8822 11:48:17.050700 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 11:48:17.053750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 11:48:17.053834 ==
8825 11:48:17.057331 RX Vref Scan: 0
8826 11:48:17.057414
8827 11:48:17.060150 RX Vref 0 -> 0, step: 1
8828 11:48:17.060255
8829 11:48:17.060323 RX Delay 0 -> 252, step: 8
8830 11:48:17.067211 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8831 11:48:17.070093 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8832 11:48:17.073748 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8833 11:48:17.076957 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8834 11:48:17.080427 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8835 11:48:17.086618 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8836 11:48:17.089967 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8837 11:48:17.093581 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8838 11:48:17.096384 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8839 11:48:17.099950 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8840 11:48:17.106475 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8841 11:48:17.109953 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8842 11:48:17.113405 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8843 11:48:17.116323 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8844 11:48:17.119877 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8845 11:48:17.126512 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8846 11:48:17.126596 ==
8847 11:48:17.129868 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 11:48:17.132875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 11:48:17.132959 ==
8850 11:48:17.133025 DQS Delay:
8851 11:48:17.136365 DQS0 = 0, DQS1 = 0
8852 11:48:17.136448 DQM Delay:
8853 11:48:17.139903 DQM0 = 129, DQM1 = 127
8854 11:48:17.139986 DQ Delay:
8855 11:48:17.142796 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =131
8856 11:48:17.146234 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8857 11:48:17.149414 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8858 11:48:17.152755 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8859 11:48:17.155956
8860 11:48:17.156038
8861 11:48:17.156103 ==
8862 11:48:17.159742 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 11:48:17.162627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 11:48:17.162710 ==
8865 11:48:17.162777
8866 11:48:17.162838
8867 11:48:17.166270 TX Vref Scan disable
8868 11:48:17.166354 == TX Byte 0 ==
8869 11:48:17.172618 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8870 11:48:17.176155 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8871 11:48:17.176246 == TX Byte 1 ==
8872 11:48:17.182631 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8873 11:48:17.185973 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8874 11:48:17.186057 ==
8875 11:48:17.189004 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 11:48:17.192473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 11:48:17.192557 ==
8878 11:48:17.207962
8879 11:48:17.211332 TX Vref early break, caculate TX vref
8880 11:48:17.214558 TX Vref=16, minBit 8, minWin=21, winSum=371
8881 11:48:17.217754 TX Vref=18, minBit 0, minWin=22, winSum=386
8882 11:48:17.221429 TX Vref=20, minBit 0, minWin=23, winSum=393
8883 11:48:17.224385 TX Vref=22, minBit 0, minWin=24, winSum=398
8884 11:48:17.227942 TX Vref=24, minBit 0, minWin=23, winSum=407
8885 11:48:17.234393 TX Vref=26, minBit 0, minWin=25, winSum=415
8886 11:48:17.237397 TX Vref=28, minBit 0, minWin=24, winSum=414
8887 11:48:17.240950 TX Vref=30, minBit 1, minWin=24, winSum=408
8888 11:48:17.244377 TX Vref=32, minBit 1, minWin=23, winSum=402
8889 11:48:17.247851 TX Vref=34, minBit 1, minWin=23, winSum=396
8890 11:48:17.250880 TX Vref=36, minBit 1, minWin=22, winSum=386
8891 11:48:17.257545 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 26
8892 11:48:17.257661
8893 11:48:17.260858 Final TX Range 0 Vref 26
8894 11:48:17.260941
8895 11:48:17.261007 ==
8896 11:48:17.263874 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 11:48:17.267104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 11:48:17.267188 ==
8899 11:48:17.267254
8900 11:48:17.270547
8901 11:48:17.270630 TX Vref Scan disable
8902 11:48:17.277200 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8903 11:48:17.277284 == TX Byte 0 ==
8904 11:48:17.280641 u2DelayCellOfst[0]=18 cells (5 PI)
8905 11:48:17.283520 u2DelayCellOfst[1]=11 cells (3 PI)
8906 11:48:17.286898 u2DelayCellOfst[2]=0 cells (0 PI)
8907 11:48:17.290236 u2DelayCellOfst[3]=7 cells (2 PI)
8908 11:48:17.293860 u2DelayCellOfst[4]=7 cells (2 PI)
8909 11:48:17.297146 u2DelayCellOfst[5]=22 cells (6 PI)
8910 11:48:17.300454 u2DelayCellOfst[6]=18 cells (5 PI)
8911 11:48:17.303381 u2DelayCellOfst[7]=3 cells (1 PI)
8912 11:48:17.306861 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8913 11:48:17.310366 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8914 11:48:17.313313 == TX Byte 1 ==
8915 11:48:17.316886 u2DelayCellOfst[8]=0 cells (0 PI)
8916 11:48:17.320346 u2DelayCellOfst[9]=3 cells (1 PI)
8917 11:48:17.323605 u2DelayCellOfst[10]=11 cells (3 PI)
8918 11:48:17.326754 u2DelayCellOfst[11]=3 cells (1 PI)
8919 11:48:17.326838 u2DelayCellOfst[12]=11 cells (3 PI)
8920 11:48:17.329976 u2DelayCellOfst[13]=15 cells (4 PI)
8921 11:48:17.333423 u2DelayCellOfst[14]=15 cells (4 PI)
8922 11:48:17.336661 u2DelayCellOfst[15]=15 cells (4 PI)
8923 11:48:17.343098 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8924 11:48:17.346881 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8925 11:48:17.346966 DramC Write-DBI on
8926 11:48:17.349893 ==
8927 11:48:17.353217 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 11:48:17.356894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 11:48:17.356969 ==
8930 11:48:17.357032
8931 11:48:17.357097
8932 11:48:17.359927 TX Vref Scan disable
8933 11:48:17.359997 == TX Byte 0 ==
8934 11:48:17.366200 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8935 11:48:17.366274 == TX Byte 1 ==
8936 11:48:17.369553 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8937 11:48:17.373307 DramC Write-DBI off
8938 11:48:17.373390
8939 11:48:17.373455 [DATLAT]
8940 11:48:17.376615 Freq=1600, CH1 RK1
8941 11:48:17.376698
8942 11:48:17.376764 DATLAT Default: 0xf
8943 11:48:17.379483 0, 0xFFFF, sum = 0
8944 11:48:17.379568 1, 0xFFFF, sum = 0
8945 11:48:17.383118 2, 0xFFFF, sum = 0
8946 11:48:17.383230 3, 0xFFFF, sum = 0
8947 11:48:17.386060 4, 0xFFFF, sum = 0
8948 11:48:17.386171 5, 0xFFFF, sum = 0
8949 11:48:17.389468 6, 0xFFFF, sum = 0
8950 11:48:17.389556 7, 0xFFFF, sum = 0
8951 11:48:17.392870 8, 0xFFFF, sum = 0
8952 11:48:17.396295 9, 0xFFFF, sum = 0
8953 11:48:17.396371 10, 0xFFFF, sum = 0
8954 11:48:17.399409 11, 0xFFFF, sum = 0
8955 11:48:17.399482 12, 0xFFFF, sum = 0
8956 11:48:17.403212 13, 0x8FFF, sum = 0
8957 11:48:17.403288 14, 0x0, sum = 1
8958 11:48:17.406606 15, 0x0, sum = 2
8959 11:48:17.406691 16, 0x0, sum = 3
8960 11:48:17.409499 17, 0x0, sum = 4
8961 11:48:17.409583 best_step = 15
8962 11:48:17.409649
8963 11:48:17.409711 ==
8964 11:48:17.413126 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 11:48:17.416015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 11:48:17.416086 ==
8967 11:48:17.419489 RX Vref Scan: 0
8968 11:48:17.419560
8969 11:48:17.422555 RX Vref 0 -> 0, step: 1
8970 11:48:17.422627
8971 11:48:17.422695 RX Delay 3 -> 252, step: 4
8972 11:48:17.429887 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8973 11:48:17.433317 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8974 11:48:17.436900 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8975 11:48:17.439671 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8976 11:48:17.443037 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8977 11:48:17.449678 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8978 11:48:17.452991 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8979 11:48:17.456648 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
8980 11:48:17.459550 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8981 11:48:17.463134 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8982 11:48:17.470097 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8983 11:48:17.472908 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8984 11:48:17.476308 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8985 11:48:17.479684 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8986 11:48:17.483627 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8987 11:48:17.490028 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8988 11:48:17.490137 ==
8989 11:48:17.493376 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 11:48:17.496254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 11:48:17.496334 ==
8992 11:48:17.496397 DQS Delay:
8993 11:48:17.499936 DQS0 = 0, DQS1 = 0
8994 11:48:17.500022 DQM Delay:
8995 11:48:17.503263 DQM0 = 127, DQM1 = 124
8996 11:48:17.503337 DQ Delay:
8997 11:48:17.506517 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =124
8998 11:48:17.509690 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122
8999 11:48:17.512983 DQ8 =108, DQ9 =112, DQ10 =128, DQ11 =120
9000 11:48:17.519618 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9001 11:48:17.519692
9002 11:48:17.519759
9003 11:48:17.519825
9004 11:48:17.522617 [DramC_TX_OE_Calibration] TA2
9005 11:48:17.522687 Original DQ_B0 (3 6) =30, OEN = 27
9006 11:48:17.525992 Original DQ_B1 (3 6) =30, OEN = 27
9007 11:48:17.529406 24, 0x0, End_B0=24 End_B1=24
9008 11:48:17.532789 25, 0x0, End_B0=25 End_B1=25
9009 11:48:17.536345 26, 0x0, End_B0=26 End_B1=26
9010 11:48:17.536459 27, 0x0, End_B0=27 End_B1=27
9011 11:48:17.539138 28, 0x0, End_B0=28 End_B1=28
9012 11:48:17.542618 29, 0x0, End_B0=29 End_B1=29
9013 11:48:17.546043 30, 0x0, End_B0=30 End_B1=30
9014 11:48:17.549515 31, 0x4141, End_B0=30 End_B1=30
9015 11:48:17.552378 Byte0 end_step=30 best_step=27
9016 11:48:17.552479 Byte1 end_step=30 best_step=27
9017 11:48:17.555670 Byte0 TX OE(2T, 0.5T) = (3, 3)
9018 11:48:17.559054 Byte1 TX OE(2T, 0.5T) = (3, 3)
9019 11:48:17.559152
9020 11:48:17.559242
9021 11:48:17.569377 [DQSOSCAuto] RK1, (LSB)MR18= 0x111d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9022 11:48:17.569459 CH1 RK1: MR19=303, MR18=111D
9023 11:48:17.575652 CH1_RK1: MR19=0x303, MR18=0x111D, DQSOSC=395, MR23=63, INC=23, DEC=15
9024 11:48:17.579066 [RxdqsGatingPostProcess] freq 1600
9025 11:48:17.585893 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9026 11:48:17.589017 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 11:48:17.592729 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 11:48:17.595704 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 11:48:17.599063 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 11:48:17.599154 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 11:48:17.602474 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 11:48:17.605978 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 11:48:17.609250 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 11:48:17.612592 Pre-setting of DQS Precalculation
9035 11:48:17.619207 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9036 11:48:17.625633 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9037 11:48:17.632000 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9038 11:48:17.632084
9039 11:48:17.632149
9040 11:48:17.635432 [Calibration Summary] 3200 Mbps
9041 11:48:17.635515 CH 0, Rank 0
9042 11:48:17.638935 SW Impedance : PASS
9043 11:48:17.642324 DUTY Scan : NO K
9044 11:48:17.642435 ZQ Calibration : PASS
9045 11:48:17.645730 Jitter Meter : NO K
9046 11:48:17.648511 CBT Training : PASS
9047 11:48:17.648620 Write leveling : PASS
9048 11:48:17.652009 RX DQS gating : PASS
9049 11:48:17.655655 RX DQ/DQS(RDDQC) : PASS
9050 11:48:17.655761 TX DQ/DQS : PASS
9051 11:48:17.658491 RX DATLAT : PASS
9052 11:48:17.661978 RX DQ/DQS(Engine): PASS
9053 11:48:17.662086 TX OE : PASS
9054 11:48:17.662180 All Pass.
9055 11:48:17.662269
9056 11:48:17.665285 CH 0, Rank 1
9057 11:48:17.668298 SW Impedance : PASS
9058 11:48:17.668405 DUTY Scan : NO K
9059 11:48:17.672104 ZQ Calibration : PASS
9060 11:48:17.672226 Jitter Meter : NO K
9061 11:48:17.675058 CBT Training : PASS
9062 11:48:17.678737 Write leveling : PASS
9063 11:48:17.678845 RX DQS gating : PASS
9064 11:48:17.682071 RX DQ/DQS(RDDQC) : PASS
9065 11:48:17.684960 TX DQ/DQS : PASS
9066 11:48:17.685042 RX DATLAT : PASS
9067 11:48:17.688434 RX DQ/DQS(Engine): PASS
9068 11:48:17.691814 TX OE : PASS
9069 11:48:17.691920 All Pass.
9070 11:48:17.692012
9071 11:48:17.692108 CH 1, Rank 0
9072 11:48:17.695138 SW Impedance : PASS
9073 11:48:17.698385 DUTY Scan : NO K
9074 11:48:17.698488 ZQ Calibration : PASS
9075 11:48:17.701531 Jitter Meter : NO K
9076 11:48:17.705327 CBT Training : PASS
9077 11:48:17.705432 Write leveling : PASS
9078 11:48:17.708476 RX DQS gating : PASS
9079 11:48:17.711730 RX DQ/DQS(RDDQC) : PASS
9080 11:48:17.711834 TX DQ/DQS : PASS
9081 11:48:17.715080 RX DATLAT : PASS
9082 11:48:17.718473 RX DQ/DQS(Engine): PASS
9083 11:48:17.718582 TX OE : PASS
9084 11:48:17.718676 All Pass.
9085 11:48:17.718767
9086 11:48:17.721862 CH 1, Rank 1
9087 11:48:17.725153 SW Impedance : PASS
9088 11:48:17.725261 DUTY Scan : NO K
9089 11:48:17.727984 ZQ Calibration : PASS
9090 11:48:17.728089 Jitter Meter : NO K
9091 11:48:17.731475 CBT Training : PASS
9092 11:48:17.734940 Write leveling : PASS
9093 11:48:17.735050 RX DQS gating : PASS
9094 11:48:17.737883 RX DQ/DQS(RDDQC) : PASS
9095 11:48:17.741291 TX DQ/DQS : PASS
9096 11:48:17.741399 RX DATLAT : PASS
9097 11:48:17.744717 RX DQ/DQS(Engine): PASS
9098 11:48:17.748061 TX OE : PASS
9099 11:48:17.748169 All Pass.
9100 11:48:17.748284
9101 11:48:17.751558 DramC Write-DBI on
9102 11:48:17.751645 PER_BANK_REFRESH: Hybrid Mode
9103 11:48:17.754920 TX_TRACKING: ON
9104 11:48:17.764789 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9105 11:48:17.771188 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9106 11:48:17.777906 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 11:48:17.781049 [FAST_K] Save calibration result to emmc
9108 11:48:17.784342 sync common calibartion params.
9109 11:48:17.788103 sync cbt_mode0:1, 1:1
9110 11:48:17.788210 dram_init: ddr_geometry: 2
9111 11:48:17.791292 dram_init: ddr_geometry: 2
9112 11:48:17.794669 dram_init: ddr_geometry: 2
9113 11:48:17.798111 0:dram_rank_size:100000000
9114 11:48:17.798215 1:dram_rank_size:100000000
9115 11:48:17.804524 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9116 11:48:17.807856 DFS_SHUFFLE_HW_MODE: ON
9117 11:48:17.811083 dramc_set_vcore_voltage set vcore to 725000
9118 11:48:17.811154 Read voltage for 1600, 0
9119 11:48:17.814186 Vio18 = 0
9120 11:48:17.814254 Vcore = 725000
9121 11:48:17.814315 Vdram = 0
9122 11:48:17.817868 Vddq = 0
9123 11:48:17.817936 Vmddr = 0
9124 11:48:17.821183 switch to 3200 Mbps bootup
9125 11:48:17.821258 [DramcRunTimeConfig]
9126 11:48:17.821320 PHYPLL
9127 11:48:17.824568 DPM_CONTROL_AFTERK: ON
9128 11:48:17.827788 PER_BANK_REFRESH: ON
9129 11:48:17.827871 REFRESH_OVERHEAD_REDUCTION: ON
9130 11:48:17.831111 CMD_PICG_NEW_MODE: OFF
9131 11:48:17.834679 XRTWTW_NEW_MODE: ON
9132 11:48:17.834762 XRTRTR_NEW_MODE: ON
9133 11:48:17.837631 TX_TRACKING: ON
9134 11:48:17.837714 RDSEL_TRACKING: OFF
9135 11:48:17.841139 DQS Precalculation for DVFS: ON
9136 11:48:17.844032 RX_TRACKING: OFF
9137 11:48:17.844114 HW_GATING DBG: ON
9138 11:48:17.847438 ZQCS_ENABLE_LP4: ON
9139 11:48:17.847521 RX_PICG_NEW_MODE: ON
9140 11:48:17.850863 TX_PICG_NEW_MODE: ON
9141 11:48:17.850947 ENABLE_RX_DCM_DPHY: ON
9142 11:48:17.854131 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9143 11:48:17.857625 DUMMY_READ_FOR_TRACKING: OFF
9144 11:48:17.861057 !!! SPM_CONTROL_AFTERK: OFF
9145 11:48:17.864072 !!! SPM could not control APHY
9146 11:48:17.864182 IMPEDANCE_TRACKING: ON
9147 11:48:17.867417 TEMP_SENSOR: ON
9148 11:48:17.867500 HW_SAVE_FOR_SR: OFF
9149 11:48:17.870988 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9150 11:48:17.874473 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9151 11:48:17.877415 Read ODT Tracking: ON
9152 11:48:17.880870 Refresh Rate DeBounce: ON
9153 11:48:17.880953 DFS_NO_QUEUE_FLUSH: ON
9154 11:48:17.883880 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9155 11:48:17.887308 ENABLE_DFS_RUNTIME_MRW: OFF
9156 11:48:17.890743 DDR_RESERVE_NEW_MODE: ON
9157 11:48:17.890829 MR_CBT_SWITCH_FREQ: ON
9158 11:48:17.894099 =========================
9159 11:48:17.912909 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9160 11:48:17.915880 dram_init: ddr_geometry: 2
9161 11:48:17.934254 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9162 11:48:17.937149 dram_init: dram init end (result: 0)
9163 11:48:17.943719 DRAM-K: Full calibration passed in 24572 msecs
9164 11:48:17.947348 MRC: failed to locate region type 0.
9165 11:48:17.947432 DRAM rank0 size:0x100000000,
9166 11:48:17.950386 DRAM rank1 size=0x100000000
9167 11:48:17.960662 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9168 11:48:17.967539 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9169 11:48:17.973965 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9170 11:48:17.980365 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9171 11:48:17.983918 DRAM rank0 size:0x100000000,
9172 11:48:17.986742 DRAM rank1 size=0x100000000
9173 11:48:17.986839 CBMEM:
9174 11:48:17.990365 IMD: root @ 0xfffff000 254 entries.
9175 11:48:17.993239 IMD: root @ 0xffffec00 62 entries.
9176 11:48:17.996846 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9177 11:48:18.003377 WARNING: RO_VPD is uninitialized or empty.
9178 11:48:18.006686 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9179 11:48:18.014252 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9180 11:48:18.027096 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9181 11:48:18.038393 BS: romstage times (exec / console): total (unknown) / 24038 ms
9182 11:48:18.038512
9183 11:48:18.038621
9184 11:48:18.048220 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9185 11:48:18.051655 ARM64: Exception handlers installed.
9186 11:48:18.055205 ARM64: Testing exception
9187 11:48:18.057984 ARM64: Done test exception
9188 11:48:18.058081 Enumerating buses...
9189 11:48:18.061349 Show all devs... Before device enumeration.
9190 11:48:18.064966 Root Device: enabled 1
9191 11:48:18.068304 CPU_CLUSTER: 0: enabled 1
9192 11:48:18.068401 CPU: 00: enabled 1
9193 11:48:18.071206 Compare with tree...
9194 11:48:18.071289 Root Device: enabled 1
9195 11:48:18.074527 CPU_CLUSTER: 0: enabled 1
9196 11:48:18.077989 CPU: 00: enabled 1
9197 11:48:18.078083 Root Device scanning...
9198 11:48:18.081474 scan_static_bus for Root Device
9199 11:48:18.084431 CPU_CLUSTER: 0 enabled
9200 11:48:18.088047 scan_static_bus for Root Device done
9201 11:48:18.091067 scan_bus: bus Root Device finished in 8 msecs
9202 11:48:18.091151 done
9203 11:48:18.098087 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9204 11:48:18.101050 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9205 11:48:18.108138 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9206 11:48:18.111604 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9207 11:48:18.114497 Allocating resources...
9208 11:48:18.117911 Reading resources...
9209 11:48:18.121268 Root Device read_resources bus 0 link: 0
9210 11:48:18.121350 DRAM rank0 size:0x100000000,
9211 11:48:18.124578 DRAM rank1 size=0x100000000
9212 11:48:18.127954 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9213 11:48:18.131193 CPU: 00 missing read_resources
9214 11:48:18.134474 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9215 11:48:18.141054 Root Device read_resources bus 0 link: 0 done
9216 11:48:18.141182 Done reading resources.
9217 11:48:18.147854 Show resources in subtree (Root Device)...After reading.
9218 11:48:18.150793 Root Device child on link 0 CPU_CLUSTER: 0
9219 11:48:18.154711 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 11:48:18.164263 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 11:48:18.164347 CPU: 00
9222 11:48:18.167359 Root Device assign_resources, bus 0 link: 0
9223 11:48:18.170791 CPU_CLUSTER: 0 missing set_resources
9224 11:48:18.177381 Root Device assign_resources, bus 0 link: 0 done
9225 11:48:18.177465 Done setting resources.
9226 11:48:18.183835 Show resources in subtree (Root Device)...After assigning values.
9227 11:48:18.187311 Root Device child on link 0 CPU_CLUSTER: 0
9228 11:48:18.190884 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 11:48:18.200866 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 11:48:18.200952 CPU: 00
9231 11:48:18.203731 Done allocating resources.
9232 11:48:18.207248 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9233 11:48:18.210617 Enabling resources...
9234 11:48:18.210701 done.
9235 11:48:18.217019 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9236 11:48:18.217103 Initializing devices...
9237 11:48:18.220435 Root Device init
9238 11:48:18.220522 init hardware done!
9239 11:48:18.223600 0x00000018: ctrlr->caps
9240 11:48:18.227061 52.000 MHz: ctrlr->f_max
9241 11:48:18.227146 0.400 MHz: ctrlr->f_min
9242 11:48:18.230585 0x40ff8080: ctrlr->voltages
9243 11:48:18.233541 sclk: 390625
9244 11:48:18.233624 Bus Width = 1
9245 11:48:18.233690 sclk: 390625
9246 11:48:18.237152 Bus Width = 1
9247 11:48:18.237238 Early init status = 3
9248 11:48:18.244004 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9249 11:48:18.247290 in-header: 03 fc 00 00 01 00 00 00
9250 11:48:18.247373 in-data: 00
9251 11:48:18.253504 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9252 11:48:18.256977 in-header: 03 fd 00 00 00 00 00 00
9253 11:48:18.260429 in-data:
9254 11:48:18.263212 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9255 11:48:18.267390 in-header: 03 fc 00 00 01 00 00 00
9256 11:48:18.270092 in-data: 00
9257 11:48:18.273827 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9258 11:48:18.279054 in-header: 03 fd 00 00 00 00 00 00
9259 11:48:18.281996 in-data:
9260 11:48:18.285562 [SSUSB] Setting up USB HOST controller...
9261 11:48:18.288962 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9262 11:48:18.292463 [SSUSB] phy power-on done.
9263 11:48:18.295363 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9264 11:48:18.302318 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9265 11:48:18.305860 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9266 11:48:18.312174 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9267 11:48:18.318737 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9268 11:48:18.325704 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9269 11:48:18.331894 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9270 11:48:18.339061 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9271 11:48:18.341985 SPM: binary array size = 0x9dc
9272 11:48:18.345427 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9273 11:48:18.351930 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9274 11:48:18.358281 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9275 11:48:18.361601 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9276 11:48:18.368065 configure_display: Starting display init
9277 11:48:18.402393 anx7625_power_on_init: Init interface.
9278 11:48:18.405692 anx7625_disable_pd_protocol: Disabled PD feature.
9279 11:48:18.408566 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9280 11:48:18.436413 anx7625_start_dp_work: Secure OCM version=00
9281 11:48:18.439909 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9282 11:48:18.454550 sp_tx_get_edid_block: EDID Block = 1
9283 11:48:18.557121 Extracted contents:
9284 11:48:18.560622 header: 00 ff ff ff ff ff ff 00
9285 11:48:18.563435 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9286 11:48:18.566993 version: 01 04
9287 11:48:18.570471 basic params: 95 1f 11 78 0a
9288 11:48:18.573453 chroma info: 76 90 94 55 54 90 27 21 50 54
9289 11:48:18.576953 established: 00 00 00
9290 11:48:18.583698 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9291 11:48:18.587060 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9292 11:48:18.593530 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9293 11:48:18.599937 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9294 11:48:18.606915 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9295 11:48:18.610242 extensions: 00
9296 11:48:18.610352 checksum: fb
9297 11:48:18.610447
9298 11:48:18.613116 Manufacturer: IVO Model 57d Serial Number 0
9299 11:48:18.616537 Made week 0 of 2020
9300 11:48:18.619856 EDID version: 1.4
9301 11:48:18.619931 Digital display
9302 11:48:18.622909 6 bits per primary color channel
9303 11:48:18.622993 DisplayPort interface
9304 11:48:18.626308 Maximum image size: 31 cm x 17 cm
9305 11:48:18.629627 Gamma: 220%
9306 11:48:18.629710 Check DPMS levels
9307 11:48:18.633262 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9308 11:48:18.639710 First detailed timing is preferred timing
9309 11:48:18.639799 Established timings supported:
9310 11:48:18.643129 Standard timings supported:
9311 11:48:18.646209 Detailed timings
9312 11:48:18.649728 Hex of detail: 383680a07038204018303c0035ae10000019
9313 11:48:18.656170 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9314 11:48:18.659719 0780 0798 07c8 0820 hborder 0
9315 11:48:18.663133 0438 043b 0447 0458 vborder 0
9316 11:48:18.666093 -hsync -vsync
9317 11:48:18.666192 Did detailed timing
9318 11:48:18.673021 Hex of detail: 000000000000000000000000000000000000
9319 11:48:18.675954 Manufacturer-specified data, tag 0
9320 11:48:18.679420 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9321 11:48:18.682374 ASCII string: InfoVision
9322 11:48:18.685800 Hex of detail: 000000fe00523134304e574635205248200a
9323 11:48:18.689281 ASCII string: R140NWF5 RH
9324 11:48:18.689370 Checksum
9325 11:48:18.692570 Checksum: 0xfb (valid)
9326 11:48:18.696003 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9327 11:48:18.699109 DSI data_rate: 832800000 bps
9328 11:48:18.705946 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9329 11:48:18.708806 anx7625_parse_edid: pixelclock(138800).
9330 11:48:18.712360 hactive(1920), hsync(48), hfp(24), hbp(88)
9331 11:48:18.715767 vactive(1080), vsync(12), vfp(3), vbp(17)
9332 11:48:18.719188 anx7625_dsi_config: config dsi.
9333 11:48:18.725455 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9334 11:48:18.739325 anx7625_dsi_config: success to config DSI
9335 11:48:18.742389 anx7625_dp_start: MIPI phy setup OK.
9336 11:48:18.746225 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9337 11:48:18.749426 mtk_ddp_mode_set invalid vrefresh 60
9338 11:48:18.752354 main_disp_path_setup
9339 11:48:18.752436 ovl_layer_smi_id_en
9340 11:48:18.755634 ovl_layer_smi_id_en
9341 11:48:18.755716 ccorr_config
9342 11:48:18.755781 aal_config
9343 11:48:18.759417 gamma_config
9344 11:48:18.759500 postmask_config
9345 11:48:18.762317 dither_config
9346 11:48:18.765753 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9347 11:48:18.772463 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9348 11:48:18.775481 Root Device init finished in 552 msecs
9349 11:48:18.779141 CPU_CLUSTER: 0 init
9350 11:48:18.785454 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9351 11:48:18.788687 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9352 11:48:18.792157 APU_MBOX 0x190000b0 = 0x10001
9353 11:48:18.795472 APU_MBOX 0x190001b0 = 0x10001
9354 11:48:18.798890 APU_MBOX 0x190005b0 = 0x10001
9355 11:48:18.802429 APU_MBOX 0x190006b0 = 0x10001
9356 11:48:18.805214 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9357 11:48:18.818418 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9358 11:48:18.830591 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9359 11:48:18.837503 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9360 11:48:18.848849 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9361 11:48:18.858088 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9362 11:48:18.861103 CPU_CLUSTER: 0 init finished in 81 msecs
9363 11:48:18.864310 Devices initialized
9364 11:48:18.867940 Show all devs... After init.
9365 11:48:18.868058 Root Device: enabled 1
9366 11:48:18.871139 CPU_CLUSTER: 0: enabled 1
9367 11:48:18.874274 CPU: 00: enabled 1
9368 11:48:18.877877 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9369 11:48:18.881094 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9370 11:48:18.884166 ELOG: NV offset 0x57f000 size 0x1000
9371 11:48:18.890992 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9372 11:48:18.897957 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9373 11:48:18.901144 ELOG: Event(17) added with size 13 at 2023-11-24 11:48:18 UTC
9374 11:48:18.907631 out: cmd=0x121: 03 db 21 01 00 00 00 00
9375 11:48:18.911004 in-header: 03 5e 00 00 2c 00 00 00
9376 11:48:18.920871 in-data: 00 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 11:48:18.927305 ELOG: Event(A1) added with size 10 at 2023-11-24 11:48:18 UTC
9378 11:48:18.934363 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9379 11:48:18.940724 ELOG: Event(A0) added with size 9 at 2023-11-24 11:48:18 UTC
9380 11:48:18.944290 elog_add_boot_reason: Logged dev mode boot
9381 11:48:18.947668 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9382 11:48:18.950670 Finalize devices...
9383 11:48:18.954382 Devices finalized
9384 11:48:18.957599 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9385 11:48:18.960836 Writing coreboot table at 0xffe64000
9386 11:48:18.964004 0. 000000000010a000-0000000000113fff: RAMSTAGE
9387 11:48:18.967486 1. 0000000040000000-00000000400fffff: RAM
9388 11:48:18.974108 2. 0000000040100000-000000004032afff: RAMSTAGE
9389 11:48:18.977499 3. 000000004032b000-00000000545fffff: RAM
9390 11:48:18.980828 4. 0000000054600000-000000005465ffff: BL31
9391 11:48:18.983652 5. 0000000054660000-00000000ffe63fff: RAM
9392 11:48:18.990661 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9393 11:48:18.994222 7. 0000000100000000-000000023fffffff: RAM
9394 11:48:18.997342 Passing 5 GPIOs to payload:
9395 11:48:19.000483 NAME | PORT | POLARITY | VALUE
9396 11:48:19.004070 EC in RW | 0x000000aa | low | undefined
9397 11:48:19.010938 EC interrupt | 0x00000005 | low | undefined
9398 11:48:19.013717 TPM interrupt | 0x000000ab | high | undefined
9399 11:48:19.020610 SD card detect | 0x00000011 | high | undefined
9400 11:48:19.024131 speaker enable | 0x00000093 | high | undefined
9401 11:48:19.027008 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9402 11:48:19.030552 in-header: 03 f9 00 00 02 00 00 00
9403 11:48:19.034049 in-data: 02 00
9404 11:48:19.034130 ADC[4]: Raw value=892601 ID=7
9405 11:48:19.037127 ADC[3]: Raw value=213070 ID=1
9406 11:48:19.040621 RAM Code: 0x71
9407 11:48:19.040701 ADC[6]: Raw value=74722 ID=0
9408 11:48:19.043459 ADC[5]: Raw value=213070 ID=1
9409 11:48:19.046931 SKU Code: 0x1
9410 11:48:19.050354 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1593
9411 11:48:19.053824 coreboot table: 964 bytes.
9412 11:48:19.056761 IMD ROOT 0. 0xfffff000 0x00001000
9413 11:48:19.060338 IMD SMALL 1. 0xffffe000 0x00001000
9414 11:48:19.063729 RO MCACHE 2. 0xffffc000 0x00001104
9415 11:48:19.066595 CONSOLE 3. 0xfff7c000 0x00080000
9416 11:48:19.070168 FMAP 4. 0xfff7b000 0x00000452
9417 11:48:19.073642 TIME STAMP 5. 0xfff7a000 0x00000910
9418 11:48:19.076930 VBOOT WORK 6. 0xfff66000 0x00014000
9419 11:48:19.080058 RAMOOPS 7. 0xffe66000 0x00100000
9420 11:48:19.083531 COREBOOT 8. 0xffe64000 0x00002000
9421 11:48:19.083640 IMD small region:
9422 11:48:19.089933 IMD ROOT 0. 0xffffec00 0x00000400
9423 11:48:19.093125 VPD 1. 0xffffeb80 0x0000006c
9424 11:48:19.096442 MMC STATUS 2. 0xffffeb60 0x00000004
9425 11:48:19.099936 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9426 11:48:19.103545 Probing TPM: done!
9427 11:48:19.107221 Connected to device vid:did:rid of 1ae0:0028:00
9428 11:48:19.117190 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9429 11:48:19.120519 Initialized TPM device CR50 revision 0
9430 11:48:19.124026 Checking cr50 for pending updates
9431 11:48:19.127613 Reading cr50 TPM mode
9432 11:48:19.136763 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9433 11:48:19.143204 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9434 11:48:19.183254 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9435 11:48:19.186676 Checking segment from ROM address 0x40100000
9436 11:48:19.189605 Checking segment from ROM address 0x4010001c
9437 11:48:19.196418 Loading segment from ROM address 0x40100000
9438 11:48:19.196500 code (compression=0)
9439 11:48:19.206300 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9440 11:48:19.212865 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9441 11:48:19.212950 it's not compressed!
9442 11:48:19.219773 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9443 11:48:19.223261 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9444 11:48:19.243574 Loading segment from ROM address 0x4010001c
9445 11:48:19.243672 Entry Point 0x80000000
9446 11:48:19.247086 Loaded segments
9447 11:48:19.250490 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9448 11:48:19.256940 Jumping to boot code at 0x80000000(0xffe64000)
9449 11:48:19.263437 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9450 11:48:19.270532 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9451 11:48:19.278094 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9452 11:48:19.281651 Checking segment from ROM address 0x40100000
9453 11:48:19.284530 Checking segment from ROM address 0x4010001c
9454 11:48:19.291582 Loading segment from ROM address 0x40100000
9455 11:48:19.291667 code (compression=1)
9456 11:48:19.297986 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9457 11:48:19.307749 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9458 11:48:19.307838 using LZMA
9459 11:48:19.316231 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9460 11:48:19.322859 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9461 11:48:19.326209 Loading segment from ROM address 0x4010001c
9462 11:48:19.326288 Entry Point 0x54601000
9463 11:48:19.329708 Loaded segments
9464 11:48:19.332828 NOTICE: MT8192 bl31_setup
9465 11:48:19.339783 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9466 11:48:19.343433 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9467 11:48:19.347116 WARNING: region 0:
9468 11:48:19.350009 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 11:48:19.350090 WARNING: region 1:
9470 11:48:19.356458 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9471 11:48:19.359880 WARNING: region 2:
9472 11:48:19.363113 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9473 11:48:19.366654 WARNING: region 3:
9474 11:48:19.370208 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9475 11:48:19.373170 WARNING: region 4:
9476 11:48:19.380033 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 11:48:19.380145 WARNING: region 5:
9478 11:48:19.383475 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 11:48:19.386471 WARNING: region 6:
9480 11:48:19.389902 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 11:48:19.393458 WARNING: region 7:
9482 11:48:19.396385 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 11:48:19.403461 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9484 11:48:19.406318 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9485 11:48:19.409859 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9486 11:48:19.416832 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9487 11:48:19.420386 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9488 11:48:19.423121 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9489 11:48:19.429830 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9490 11:48:19.433172 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9491 11:48:19.436829 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9492 11:48:19.443100 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9493 11:48:19.447285 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9494 11:48:19.453173 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9495 11:48:19.456380 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9496 11:48:19.459968 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9497 11:48:19.466712 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9498 11:48:19.469951 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9499 11:48:19.473476 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9500 11:48:19.480161 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9501 11:48:19.483069 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9502 11:48:19.490323 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9503 11:48:19.493229 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9504 11:48:19.496809 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9505 11:48:19.503230 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9506 11:48:19.506838 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9507 11:48:19.512964 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9508 11:48:19.516333 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9509 11:48:19.519957 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9510 11:48:19.526337 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9511 11:48:19.529600 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9512 11:48:19.536485 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9513 11:48:19.539909 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9514 11:48:19.543382 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9515 11:48:19.549573 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9516 11:48:19.552895 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9517 11:48:19.556710 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9518 11:48:19.559511 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9519 11:48:19.566664 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9520 11:48:19.569681 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9521 11:48:19.573191 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9522 11:48:19.576590 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9523 11:48:19.583003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9524 11:48:19.586552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9525 11:48:19.589904 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9526 11:48:19.593351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9527 11:48:19.599899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9528 11:48:19.602792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9529 11:48:19.606343 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9530 11:48:19.609714 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9531 11:48:19.616093 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9532 11:48:19.619584 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9533 11:48:19.626557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9534 11:48:19.629506 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9535 11:48:19.636192 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9536 11:48:19.639798 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9537 11:48:19.642924 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9538 11:48:19.649521 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9539 11:48:19.652949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9540 11:48:19.659591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9541 11:48:19.663114 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9542 11:48:19.666291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9543 11:48:19.673109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9544 11:48:19.676510 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9545 11:48:19.682744 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9546 11:48:19.686231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9547 11:48:19.693045 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9548 11:48:19.696303 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9549 11:48:19.703084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9550 11:48:19.706063 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9551 11:48:19.709609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9552 11:48:19.716546 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9553 11:48:19.719545 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9554 11:48:19.725999 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9555 11:48:19.729350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9556 11:48:19.736122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9557 11:48:19.739705 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9558 11:48:19.742663 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9559 11:48:19.749477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9560 11:48:19.753040 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9561 11:48:19.759673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9562 11:48:19.762961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9563 11:48:19.769315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9564 11:48:19.772623 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9565 11:48:19.779620 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9566 11:48:19.782590 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9567 11:48:19.786002 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9568 11:48:19.792574 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9569 11:48:19.796287 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9570 11:48:19.802893 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9571 11:48:19.806228 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9572 11:48:19.809576 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9573 11:48:19.815969 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9574 11:48:19.819430 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9575 11:48:19.826461 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9576 11:48:19.829421 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9577 11:48:19.835892 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9578 11:48:19.839335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9579 11:48:19.842700 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9580 11:48:19.849215 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9581 11:48:19.852631 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9582 11:48:19.856044 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9583 11:48:19.859566 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9584 11:48:19.866001 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9585 11:48:19.869822 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9586 11:48:19.876243 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9587 11:48:19.879815 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9588 11:48:19.883166 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9589 11:48:19.890024 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9590 11:48:19.892970 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9591 11:48:19.899616 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9592 11:48:19.902873 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9593 11:48:19.906554 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9594 11:48:19.913111 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9595 11:48:19.916516 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9596 11:48:19.923316 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9597 11:48:19.926703 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9598 11:48:19.929665 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9599 11:48:19.933248 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9600 11:48:19.939797 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9601 11:48:19.943205 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9602 11:48:19.946463 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9603 11:48:19.952937 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9604 11:48:19.956282 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9605 11:48:19.959712 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9606 11:48:19.963368 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9607 11:48:19.969704 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9608 11:48:19.973136 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9609 11:48:19.979650 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9610 11:48:19.983207 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9611 11:48:19.986527 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9612 11:48:19.992803 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9613 11:48:19.996458 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9614 11:48:19.999812 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9615 11:48:20.006192 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9616 11:48:20.009534 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9617 11:48:20.016449 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9618 11:48:20.020055 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9619 11:48:20.022880 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9620 11:48:20.029523 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9621 11:48:20.032797 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9622 11:48:20.036327 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9623 11:48:20.043258 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9624 11:48:20.046170 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9625 11:48:20.052943 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9626 11:48:20.056377 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9627 11:48:20.059788 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9628 11:48:20.065978 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9629 11:48:20.069614 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9630 11:48:20.076034 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9631 11:48:20.079449 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9632 11:48:20.082912 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9633 11:48:20.089532 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9634 11:48:20.092987 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9635 11:48:20.099351 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9636 11:48:20.102482 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9637 11:48:20.106120 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9638 11:48:20.112881 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9639 11:48:20.116270 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9640 11:48:20.122519 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9641 11:48:20.125731 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9642 11:48:20.128977 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9643 11:48:20.135739 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9644 11:48:20.139008 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9645 11:48:20.145833 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9646 11:48:20.148855 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9647 11:48:20.152134 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9648 11:48:20.159110 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9649 11:48:20.162013 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9650 11:48:20.168923 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9651 11:48:20.172218 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9652 11:48:20.175780 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9653 11:48:20.182304 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9654 11:48:20.185720 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9655 11:48:20.188622 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9656 11:48:20.195445 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9657 11:48:20.198847 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9658 11:48:20.205427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9659 11:48:20.208892 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9660 11:48:20.212129 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9661 11:48:20.218605 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9662 11:48:20.221633 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9663 11:48:20.228472 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9664 11:48:20.231967 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9665 11:48:20.235206 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9666 11:48:20.241879 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9667 11:48:20.245159 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9668 11:48:20.251516 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9669 11:48:20.255130 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9670 11:48:20.258118 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9671 11:48:20.264955 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9672 11:48:20.268373 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9673 11:48:20.274674 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9674 11:48:20.278081 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9675 11:48:20.284636 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9676 11:48:20.288253 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9677 11:48:20.291119 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9678 11:48:20.297693 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9679 11:48:20.300923 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9680 11:48:20.307871 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9681 11:48:20.310884 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9682 11:48:20.317985 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9683 11:48:20.320896 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9684 11:48:20.324133 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9685 11:48:20.330935 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9686 11:48:20.334581 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9687 11:48:20.341147 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9688 11:48:20.344694 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9689 11:48:20.347491 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9690 11:48:20.354556 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9691 11:48:20.357379 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9692 11:48:20.364512 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9693 11:48:20.367591 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9694 11:48:20.374168 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9695 11:48:20.377535 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9696 11:48:20.380874 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9697 11:48:20.387302 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9698 11:48:20.390871 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9699 11:48:20.397409 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9700 11:48:20.400957 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9701 11:48:20.403811 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9702 11:48:20.410842 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9703 11:48:20.414146 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9704 11:48:20.420483 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9705 11:48:20.424011 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9706 11:48:20.430524 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9707 11:48:20.433892 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9708 11:48:20.437109 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9709 11:48:20.443859 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9710 11:48:20.447252 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9711 11:48:20.453695 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9712 11:48:20.457317 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9713 11:48:20.460625 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9714 11:48:20.463680 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9715 11:48:20.467214 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9716 11:48:20.473370 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9717 11:48:20.476980 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9718 11:48:20.483835 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9719 11:48:20.486765 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9720 11:48:20.490201 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9721 11:48:20.496613 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9722 11:48:20.500095 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9723 11:48:20.503218 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9724 11:48:20.510481 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9725 11:48:20.513676 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9726 11:48:20.517055 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9727 11:48:20.523544 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9728 11:48:20.526467 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9729 11:48:20.533488 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9730 11:48:20.536497 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9731 11:48:20.539980 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9732 11:48:20.546870 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9733 11:48:20.549744 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9734 11:48:20.553319 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9735 11:48:20.559848 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9736 11:48:20.562968 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9737 11:48:20.566457 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9738 11:48:20.573267 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9739 11:48:20.576688 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9740 11:48:20.582888 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9741 11:48:20.586328 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9742 11:48:20.589898 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9743 11:48:20.596419 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9744 11:48:20.599872 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9745 11:48:20.602884 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9746 11:48:20.609385 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9747 11:48:20.612933 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9748 11:48:20.619597 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9749 11:48:20.622981 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9750 11:48:20.626482 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9751 11:48:20.632877 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9752 11:48:20.636314 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9753 11:48:20.639227 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9754 11:48:20.642740 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9755 11:48:20.646235 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9756 11:48:20.652511 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9757 11:48:20.656067 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9758 11:48:20.659590 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9759 11:48:20.663013 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9760 11:48:20.669503 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9761 11:48:20.672805 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9762 11:48:20.676372 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9763 11:48:20.682713 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9764 11:48:20.686271 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9765 11:48:20.688990 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9766 11:48:20.695867 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9767 11:48:20.699406 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9768 11:48:20.702898 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9769 11:48:20.709029 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9770 11:48:20.712760 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9771 11:48:20.718905 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9772 11:48:20.722299 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9773 11:48:20.725500 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9774 11:48:20.732300 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9775 11:48:20.735584 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9776 11:48:20.742500 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9777 11:48:20.745400 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9778 11:48:20.752427 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9779 11:48:20.755278 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9780 11:48:20.758847 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9781 11:48:20.765291 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9782 11:48:20.768954 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9783 11:48:20.775258 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9784 11:48:20.778916 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9785 11:48:20.782033 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9786 11:48:20.788473 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9787 11:48:20.791800 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9788 11:48:20.798751 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9789 11:48:20.802391 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9790 11:48:20.805296 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9791 11:48:20.812306 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9792 11:48:20.815143 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9793 11:48:20.821951 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9794 11:48:20.825262 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9795 11:48:20.831769 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9796 11:48:20.835251 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9797 11:48:20.838515 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9798 11:48:20.845275 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9799 11:48:20.848232 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9800 11:48:20.855104 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9801 11:48:20.858106 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9802 11:48:20.864577 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9803 11:48:20.867937 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9804 11:48:20.871546 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9805 11:48:20.878006 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9806 11:48:20.881442 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9807 11:48:20.884693 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9808 11:48:20.891508 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9809 11:48:20.894906 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9810 11:48:20.901208 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9811 11:48:20.904821 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9812 11:48:20.907854 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9813 11:48:20.915007 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9814 11:48:20.918404 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9815 11:48:20.924845 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9816 11:48:20.927799 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9817 11:48:20.934543 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9818 11:48:20.938088 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9819 11:48:20.941160 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9820 11:48:20.948304 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9821 11:48:20.951186 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9822 11:48:20.957974 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9823 11:48:20.960937 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9824 11:48:20.964388 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9825 11:48:20.970807 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9826 11:48:20.974260 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9827 11:48:20.980826 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9828 11:48:20.984303 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9829 11:48:20.987752 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9830 11:48:20.994113 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9831 11:48:20.997609 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9832 11:48:21.004116 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9833 11:48:21.007677 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9834 11:48:21.014102 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9835 11:48:21.017306 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9836 11:48:21.020940 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9837 11:48:21.027583 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9838 11:48:21.030528 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9839 11:48:21.037210 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9840 11:48:21.040724 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9841 11:48:21.047135 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9842 11:48:21.050666 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9843 11:48:21.056806 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9844 11:48:21.060551 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9845 11:48:21.063726 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9846 11:48:21.070237 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9847 11:48:21.073495 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9848 11:48:21.080594 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9849 11:48:21.083569 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9850 11:48:21.090393 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9851 11:48:21.093762 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9852 11:48:21.096816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9853 11:48:21.103605 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9854 11:48:21.107154 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9855 11:48:21.113488 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9856 11:48:21.116980 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9857 11:48:21.123731 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9858 11:48:21.126475 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9859 11:48:21.129890 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9860 11:48:21.136641 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9861 11:48:21.139824 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9862 11:48:21.146573 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9863 11:48:21.150019 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9864 11:48:21.156407 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9865 11:48:21.159858 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9866 11:48:21.163309 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9867 11:48:21.170047 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9868 11:48:21.173500 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9869 11:48:21.179659 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9870 11:48:21.183328 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9871 11:48:21.189973 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9872 11:48:21.193450 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9873 11:48:21.196870 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9874 11:48:21.203264 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9875 11:48:21.206654 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9876 11:48:21.213100 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9877 11:48:21.216493 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9878 11:48:21.223316 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9879 11:48:21.226206 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9880 11:48:21.233296 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9881 11:48:21.236685 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9882 11:48:21.239581 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9883 11:48:21.246466 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9884 11:48:21.249778 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9885 11:48:21.256250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9886 11:48:21.259680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9887 11:48:21.263111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9888 11:48:21.269626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9889 11:48:21.273019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9890 11:48:21.279817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9891 11:48:21.282656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9892 11:48:21.289775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9893 11:48:21.292559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9894 11:48:21.299388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9895 11:48:21.302862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9896 11:48:21.309417 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9897 11:48:21.312696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9898 11:48:21.319018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9899 11:48:21.322520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9900 11:48:21.329190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9901 11:48:21.332738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9902 11:48:21.339134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9903 11:48:21.342068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9904 11:48:21.348881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9905 11:48:21.352292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9906 11:48:21.358885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9907 11:48:21.362085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9908 11:48:21.368610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9909 11:48:21.372151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9910 11:48:21.379176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9911 11:48:21.381932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9912 11:48:21.388957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9913 11:48:21.391829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9914 11:48:21.398698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9915 11:48:21.402110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9916 11:48:21.408627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9917 11:48:21.411734 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9918 11:48:21.415487 INFO: [APUAPC] vio 0
9919 11:48:21.419043 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9920 11:48:21.425422 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9921 11:48:21.428172 INFO: [APUAPC] D0_APC_0: 0x400510
9922 11:48:21.428284 INFO: [APUAPC] D0_APC_1: 0x0
9923 11:48:21.431663 INFO: [APUAPC] D0_APC_2: 0x1540
9924 11:48:21.435235 INFO: [APUAPC] D0_APC_3: 0x0
9925 11:48:21.438575 INFO: [APUAPC] D1_APC_0: 0xffffffff
9926 11:48:21.441503 INFO: [APUAPC] D1_APC_1: 0xffffffff
9927 11:48:21.445082 INFO: [APUAPC] D1_APC_2: 0x3fffff
9928 11:48:21.447954 INFO: [APUAPC] D1_APC_3: 0x0
9929 11:48:21.451467 INFO: [APUAPC] D2_APC_0: 0xffffffff
9930 11:48:21.455079 INFO: [APUAPC] D2_APC_1: 0xffffffff
9931 11:48:21.458364 INFO: [APUAPC] D2_APC_2: 0x3fffff
9932 11:48:21.461718 INFO: [APUAPC] D2_APC_3: 0x0
9933 11:48:21.464695 INFO: [APUAPC] D3_APC_0: 0xffffffff
9934 11:48:21.468213 INFO: [APUAPC] D3_APC_1: 0xffffffff
9935 11:48:21.471659 INFO: [APUAPC] D3_APC_2: 0x3fffff
9936 11:48:21.475143 INFO: [APUAPC] D3_APC_3: 0x0
9937 11:48:21.478354 INFO: [APUAPC] D4_APC_0: 0xffffffff
9938 11:48:21.481377 INFO: [APUAPC] D4_APC_1: 0xffffffff
9939 11:48:21.484765 INFO: [APUAPC] D4_APC_2: 0x3fffff
9940 11:48:21.487956 INFO: [APUAPC] D4_APC_3: 0x0
9941 11:48:21.491632 INFO: [APUAPC] D5_APC_0: 0xffffffff
9942 11:48:21.494548 INFO: [APUAPC] D5_APC_1: 0xffffffff
9943 11:48:21.498092 INFO: [APUAPC] D5_APC_2: 0x3fffff
9944 11:48:21.501673 INFO: [APUAPC] D5_APC_3: 0x0
9945 11:48:21.504529 INFO: [APUAPC] D6_APC_0: 0xffffffff
9946 11:48:21.508110 INFO: [APUAPC] D6_APC_1: 0xffffffff
9947 11:48:21.511480 INFO: [APUAPC] D6_APC_2: 0x3fffff
9948 11:48:21.514437 INFO: [APUAPC] D6_APC_3: 0x0
9949 11:48:21.518315 INFO: [APUAPC] D7_APC_0: 0xffffffff
9950 11:48:21.521334 INFO: [APUAPC] D7_APC_1: 0xffffffff
9951 11:48:21.524599 INFO: [APUAPC] D7_APC_2: 0x3fffff
9952 11:48:21.527787 INFO: [APUAPC] D7_APC_3: 0x0
9953 11:48:21.531252 INFO: [APUAPC] D8_APC_0: 0xffffffff
9954 11:48:21.534691 INFO: [APUAPC] D8_APC_1: 0xffffffff
9955 11:48:21.538094 INFO: [APUAPC] D8_APC_2: 0x3fffff
9956 11:48:21.540977 INFO: [APUAPC] D8_APC_3: 0x0
9957 11:48:21.544560 INFO: [APUAPC] D9_APC_0: 0xffffffff
9958 11:48:21.547474 INFO: [APUAPC] D9_APC_1: 0xffffffff
9959 11:48:21.550921 INFO: [APUAPC] D9_APC_2: 0x3fffff
9960 11:48:21.554466 INFO: [APUAPC] D9_APC_3: 0x0
9961 11:48:21.557962 INFO: [APUAPC] D10_APC_0: 0xffffffff
9962 11:48:21.560731 INFO: [APUAPC] D10_APC_1: 0xffffffff
9963 11:48:21.564076 INFO: [APUAPC] D10_APC_2: 0x3fffff
9964 11:48:21.567481 INFO: [APUAPC] D10_APC_3: 0x0
9965 11:48:21.570962 INFO: [APUAPC] D11_APC_0: 0xffffffff
9966 11:48:21.574473 INFO: [APUAPC] D11_APC_1: 0xffffffff
9967 11:48:21.577376 INFO: [APUAPC] D11_APC_2: 0x3fffff
9968 11:48:21.580896 INFO: [APUAPC] D11_APC_3: 0x0
9969 11:48:21.584403 INFO: [APUAPC] D12_APC_0: 0xffffffff
9970 11:48:21.587410 INFO: [APUAPC] D12_APC_1: 0xffffffff
9971 11:48:21.590714 INFO: [APUAPC] D12_APC_2: 0x3fffff
9972 11:48:21.594355 INFO: [APUAPC] D12_APC_3: 0x0
9973 11:48:21.597158 INFO: [APUAPC] D13_APC_0: 0xffffffff
9974 11:48:21.600414 INFO: [APUAPC] D13_APC_1: 0xffffffff
9975 11:48:21.604117 INFO: [APUAPC] D13_APC_2: 0x3fffff
9976 11:48:21.607024 INFO: [APUAPC] D13_APC_3: 0x0
9977 11:48:21.610541 INFO: [APUAPC] D14_APC_0: 0xffffffff
9978 11:48:21.613989 INFO: [APUAPC] D14_APC_1: 0xffffffff
9979 11:48:21.616991 INFO: [APUAPC] D14_APC_2: 0x3fffff
9980 11:48:21.620358 INFO: [APUAPC] D14_APC_3: 0x0
9981 11:48:21.623995 INFO: [APUAPC] D15_APC_0: 0xffffffff
9982 11:48:21.627440 INFO: [APUAPC] D15_APC_1: 0xffffffff
9983 11:48:21.630302 INFO: [APUAPC] D15_APC_2: 0x3fffff
9984 11:48:21.633826 INFO: [APUAPC] D15_APC_3: 0x0
9985 11:48:21.636886 INFO: [APUAPC] APC_CON: 0x4
9986 11:48:21.636999 INFO: [NOCDAPC] D0_APC_0: 0x0
9987 11:48:21.640444 INFO: [NOCDAPC] D0_APC_1: 0x0
9988 11:48:21.643596 INFO: [NOCDAPC] D1_APC_0: 0x0
9989 11:48:21.646842 INFO: [NOCDAPC] D1_APC_1: 0xfff
9990 11:48:21.650596 INFO: [NOCDAPC] D2_APC_0: 0x0
9991 11:48:21.653790 INFO: [NOCDAPC] D2_APC_1: 0xfff
9992 11:48:21.657081 INFO: [NOCDAPC] D3_APC_0: 0x0
9993 11:48:21.660454 INFO: [NOCDAPC] D3_APC_1: 0xfff
9994 11:48:21.663860 INFO: [NOCDAPC] D4_APC_0: 0x0
9995 11:48:21.666675 INFO: [NOCDAPC] D4_APC_1: 0xfff
9996 11:48:21.670027 INFO: [NOCDAPC] D5_APC_0: 0x0
9997 11:48:21.670130 INFO: [NOCDAPC] D5_APC_1: 0xfff
9998 11:48:21.673556 INFO: [NOCDAPC] D6_APC_0: 0x0
9999 11:48:21.676989 INFO: [NOCDAPC] D6_APC_1: 0xfff
10000 11:48:21.680501 INFO: [NOCDAPC] D7_APC_0: 0x0
10001 11:48:21.683413 INFO: [NOCDAPC] D7_APC_1: 0xfff
10002 11:48:21.686850 INFO: [NOCDAPC] D8_APC_0: 0x0
10003 11:48:21.690273 INFO: [NOCDAPC] D8_APC_1: 0xfff
10004 11:48:21.693850 INFO: [NOCDAPC] D9_APC_0: 0x0
10005 11:48:21.696687 INFO: [NOCDAPC] D9_APC_1: 0xfff
10006 11:48:21.700101 INFO: [NOCDAPC] D10_APC_0: 0x0
10007 11:48:21.703432 INFO: [NOCDAPC] D10_APC_1: 0xfff
10008 11:48:21.706674 INFO: [NOCDAPC] D11_APC_0: 0x0
10009 11:48:21.706777 INFO: [NOCDAPC] D11_APC_1: 0xfff
10010 11:48:21.709825 INFO: [NOCDAPC] D12_APC_0: 0x0
10011 11:48:21.713418 INFO: [NOCDAPC] D12_APC_1: 0xfff
10012 11:48:21.716799 INFO: [NOCDAPC] D13_APC_0: 0x0
10013 11:48:21.720174 INFO: [NOCDAPC] D13_APC_1: 0xfff
10014 11:48:21.723162 INFO: [NOCDAPC] D14_APC_0: 0x0
10015 11:48:21.726600 INFO: [NOCDAPC] D14_APC_1: 0xfff
10016 11:48:21.730071 INFO: [NOCDAPC] D15_APC_0: 0x0
10017 11:48:21.733548 INFO: [NOCDAPC] D15_APC_1: 0xfff
10018 11:48:21.736473 INFO: [NOCDAPC] APC_CON: 0x4
10019 11:48:21.740010 INFO: [APUAPC] set_apusys_apc done
10020 11:48:21.743324 INFO: [DEVAPC] devapc_init done
10021 11:48:21.746927 INFO: GICv3 without legacy support detected.
10022 11:48:21.749874 INFO: ARM GICv3 driver initialized in EL3
10023 11:48:21.753142 INFO: Maximum SPI INTID supported: 639
10024 11:48:21.756634 INFO: BL31: Initializing runtime services
10025 11:48:21.763136 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10026 11:48:21.766607 INFO: SPM: enable CPC mode
10027 11:48:21.773248 INFO: mcdi ready for mcusys-off-idle and system suspend
10028 11:48:21.776442 INFO: BL31: Preparing for EL3 exit to normal world
10029 11:48:21.779649 INFO: Entry point address = 0x80000000
10030 11:48:21.783139 INFO: SPSR = 0x8
10031 11:48:21.787857
10032 11:48:21.787972
10033 11:48:21.788070
10034 11:48:21.791116 Starting depthcharge on Spherion...
10035 11:48:21.791218
10036 11:48:21.791317 Wipe memory regions:
10037 11:48:21.791407
10038 11:48:21.792290 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10039 11:48:21.792396 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10040 11:48:21.792486 Setting prompt string to ['asurada:']
10041 11:48:21.792592 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10042 11:48:21.794706 [0x00000040000000, 0x00000054600000)
10043 11:48:21.917057
10044 11:48:21.917233 [0x00000054660000, 0x00000080000000)
10045 11:48:22.177448
10046 11:48:22.177616 [0x000000821a7280, 0x000000ffe64000)
10047 11:48:22.922402
10048 11:48:22.922599 [0x00000100000000, 0x00000240000000)
10049 11:48:24.813156
10050 11:48:24.816449 Initializing XHCI USB controller at 0x11200000.
10051 11:48:25.855653
10052 11:48:25.858615 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10053 11:48:25.859334
10054 11:48:25.859676
10055 11:48:25.859978
10056 11:48:25.860800 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10058 11:48:25.961809 asurada: tftpboot 192.168.201.1 12074030/tftp-deploy-k89iqby6/kernel/image.itb 12074030/tftp-deploy-k89iqby6/kernel/cmdline
10059 11:48:25.961968 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 11:48:25.962051 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10061 11:48:25.966668 tftpboot 192.168.201.1 12074030/tftp-deploy-k89iqby6/kernel/image.itbtp-deploy-k89iqby6/kernel/cmdline
10062 11:48:25.966752
10063 11:48:25.966816 Waiting for link
10064 11:48:26.127554
10065 11:48:26.128076 R8152: Initializing
10066 11:48:26.128448
10067 11:48:26.130926 Version 6 (ocp_data = 5c30)
10068 11:48:26.131414
10069 11:48:26.133789 R8152: Done initializing
10070 11:48:26.134201
10071 11:48:26.134524 Adding net device
10072 11:48:28.034743
10073 11:48:28.035219 done.
10074 11:48:28.035598
10075 11:48:28.035939 MAC: 00:24:32:30:78:ff
10076 11:48:28.036282
10077 11:48:28.038281 Sending DHCP discover... done.
10078 11:48:28.038695
10079 11:48:28.041605 Waiting for reply... done.
10080 11:48:28.042017
10081 11:48:28.044812 Sending DHCP request... done.
10082 11:48:28.045235
10083 11:48:28.050588 Waiting for reply... done.
10084 11:48:28.050995
10085 11:48:28.051330 My ip is 192.168.201.21
10086 11:48:28.051743
10087 11:48:28.053654 The DHCP server ip is 192.168.201.1
10088 11:48:28.054067
10089 11:48:28.060323 TFTP server IP predefined by user: 192.168.201.1
10090 11:48:28.060739
10091 11:48:28.066781 Bootfile predefined by user: 12074030/tftp-deploy-k89iqby6/kernel/image.itb
10092 11:48:28.067196
10093 11:48:28.070290 Sending tftp read request... done.
10094 11:48:28.070701
10095 11:48:28.076642 Waiting for the transfer...
10096 11:48:28.077082
10097 11:48:28.765716 00000000 ################################################################
10098 11:48:28.766249
10099 11:48:29.465931 00080000 ################################################################
10100 11:48:29.466479
10101 11:48:30.191352 00100000 ################################################################
10102 11:48:30.191856
10103 11:48:30.935211 00180000 ################################################################
10104 11:48:30.935735
10105 11:48:31.663314 00200000 ################################################################
10106 11:48:31.663816
10107 11:48:32.395686 00280000 ################################################################
10108 11:48:32.396182
10109 11:48:33.092391 00300000 ################################################################
10110 11:48:33.092902
10111 11:48:33.820397 00380000 ################################################################
10112 11:48:33.820881
10113 11:48:34.533314 00400000 ################################################################
10114 11:48:34.533997
10115 11:48:35.175369 00480000 ################################################################
10116 11:48:35.175506
10117 11:48:35.748760 00500000 ################################################################
10118 11:48:35.748887
10119 11:48:36.326486 00580000 ################################################################
10120 11:48:36.326624
10121 11:48:36.938464 00600000 ################################################################
10122 11:48:36.938595
10123 11:48:37.586398 00680000 ################################################################
10124 11:48:37.586899
10125 11:48:38.190686 00700000 ################################################################
10126 11:48:38.190823
10127 11:48:38.859021 00780000 ################################################################
10128 11:48:38.859158
10129 11:48:39.490757 00800000 ################################################################
10130 11:48:39.490893
10131 11:48:40.030234 00880000 ################################################################
10132 11:48:40.030365
10133 11:48:40.626604 00900000 ################################################################
10134 11:48:40.626738
10135 11:48:41.215478 00980000 ################################################################
10136 11:48:41.215609
10137 11:48:41.786079 00a00000 ################################################################
10138 11:48:41.786216
10139 11:48:42.415057 00a80000 ################################################################
10140 11:48:42.415216
10141 11:48:43.067733 00b00000 ################################################################
10142 11:48:43.068354
10143 11:48:43.754490 00b80000 ################################################################
10144 11:48:43.755062
10145 11:48:44.369417 00c00000 ################################################################
10146 11:48:44.369551
10147 11:48:45.033740 00c80000 ################################################################
10148 11:48:45.034230
10149 11:48:45.748578 00d00000 ################################################################
10150 11:48:45.748734
10151 11:48:46.427279 00d80000 ################################################################
10152 11:48:46.427464
10153 11:48:46.973172 00e00000 ################################################################
10154 11:48:46.973341
10155 11:48:47.519819 00e80000 ################################################################
10156 11:48:47.519954
10157 11:48:48.072312 00f00000 ################################################################
10158 11:48:48.072445
10159 11:48:48.630570 00f80000 ################################################################
10160 11:48:48.630764
10161 11:48:49.235600 01000000 ################################################################
10162 11:48:49.235737
10163 11:48:49.820349 01080000 ################################################################
10164 11:48:49.820486
10165 11:48:50.405189 01100000 ################################################################
10166 11:48:50.405656
10167 11:48:50.979717 01180000 ################################################################
10168 11:48:50.979854
10169 11:48:51.563218 01200000 ################################################################
10170 11:48:51.563714
10171 11:48:52.158067 01280000 ################################################################
10172 11:48:52.158204
10173 11:48:52.772734 01300000 ################################################################
10174 11:48:52.772869
10175 11:48:53.386510 01380000 ################################################################
10176 11:48:53.386652
10177 11:48:54.002502 01400000 ################################################################
10178 11:48:54.002645
10179 11:48:54.664830 01480000 ################################################################
10180 11:48:54.664960
10181 11:48:55.250355 01500000 ################################################################
10182 11:48:55.250492
10183 11:48:55.845059 01580000 ################################################################
10184 11:48:55.845190
10185 11:48:56.482373 01600000 ################################################################
10186 11:48:56.482520
10187 11:48:57.073149 01680000 ################################################################
10188 11:48:57.073286
10189 11:48:57.700425 01700000 ################################################################
10190 11:48:57.700634
10191 11:48:58.330800 01780000 ################################################################
10192 11:48:58.330931
10193 11:48:58.968596 01800000 ################################################################
10194 11:48:58.968731
10195 11:48:59.653313 01880000 ################################################################
10196 11:48:59.653473
10197 11:49:00.318371 01900000 ################################################################
10198 11:49:00.318536
10199 11:49:00.968883 01980000 ################################################################
10200 11:49:00.969014
10201 11:49:01.619780 01a00000 ################################################################
10202 11:49:01.619911
10203 11:49:02.262561 01a80000 ################################################################
10204 11:49:02.262708
10205 11:49:02.961756 01b00000 ################################################################
10206 11:49:02.961903
10207 11:49:03.595418 01b80000 ################################################################
10208 11:49:03.595933
10209 11:49:04.242216 01c00000 ################################################################
10210 11:49:04.242347
10211 11:49:04.926136 01c80000 ################################################################
10212 11:49:04.926269
10213 11:49:05.634649 01d00000 ################################################################
10214 11:49:05.634783
10215 11:49:06.330217 01d80000 ################################################################
10216 11:49:06.330348
10217 11:49:07.034942 01e00000 ################################################################
10218 11:49:07.035098
10219 11:49:07.737002 01e80000 ################################################################
10220 11:49:07.737132
10221 11:49:08.404730 01f00000 ################################################################
10222 11:49:08.404889
10223 11:49:08.974547 01f80000 ################################################################
10224 11:49:08.974683
10225 11:49:09.519152 02000000 ################################################################
10226 11:49:09.519316
10227 11:49:10.053267 02080000 ################################################################
10228 11:49:10.053427
10229 11:49:10.583725 02100000 ################################################################
10230 11:49:10.583895
10231 11:49:11.116687 02180000 ################################################################
10232 11:49:11.116826
10233 11:49:11.661408 02200000 ################################################################
10234 11:49:11.661544
10235 11:49:12.210375 02280000 ################################################################
10236 11:49:12.210518
10237 11:49:12.755674 02300000 ################################################################
10238 11:49:12.755808
10239 11:49:13.315781 02380000 ################################################################
10240 11:49:13.315917
10241 11:49:13.871120 02400000 ################################################################
10242 11:49:13.871262
10243 11:49:14.476767 02480000 ################################################################
10244 11:49:14.477317
10245 11:49:15.166161 02500000 ################################################################
10246 11:49:15.166694
10247 11:49:15.805909 02580000 ################################################################
10248 11:49:15.806627
10249 11:49:16.413781 02600000 ################################################################
10250 11:49:16.413940
10251 11:49:17.051570 02680000 ################################################################
10252 11:49:17.051800
10253 11:49:17.704447 02700000 ################################################################
10254 11:49:17.704959
10255 11:49:18.288150 02780000 ################################################################
10256 11:49:18.288321
10257 11:49:18.856463 02800000 ################################################################
10258 11:49:18.856594
10259 11:49:19.443625 02880000 ################################################################
10260 11:49:19.444343
10261 11:49:20.059393 02900000 ################################################################
10262 11:49:20.059528
10263 11:49:20.655745 02980000 ################################################################
10264 11:49:20.655913
10265 11:49:21.306205 02a00000 ################################################################
10266 11:49:21.306338
10267 11:49:21.902630 02a80000 ################################################################
10268 11:49:21.902900
10269 11:49:22.495972 02b00000 ################################################################
10270 11:49:22.496186
10271 11:49:23.100715 02b80000 ################################################################
10272 11:49:23.101208
10273 11:49:23.721175 02c00000 ################################################################
10274 11:49:23.721310
10275 11:49:24.368033 02c80000 ################################################################
10276 11:49:24.368180
10277 11:49:24.979632 02d00000 ################################################################
10278 11:49:24.979771
10279 11:49:25.588708 02d80000 ################################################################
10280 11:49:25.588861
10281 11:49:26.168503 02e00000 ################################################################
10282 11:49:26.168641
10283 11:49:26.786287 02e80000 ################################################################
10284 11:49:26.786781
10285 11:49:27.449641 02f00000 ################################################################
10286 11:49:27.450129
10287 11:49:28.077380 02f80000 ################################################################
10288 11:49:28.077897
10289 11:49:28.674170 03000000 ################################################################
10290 11:49:28.674306
10291 11:49:29.299382 03080000 ################################################################
10292 11:49:29.299559
10293 11:49:29.967057 03100000 ################################################################
10294 11:49:29.967567
10295 11:49:30.631820 03180000 ################################################################
10296 11:49:30.631950
10297 11:49:31.208089 03200000 ################################################################
10298 11:49:31.208294
10299 11:49:31.879146 03280000 ################################################################
10300 11:49:31.879672
10301 11:49:32.504341 03300000 ################################################################
10302 11:49:32.504476
10303 11:49:33.150093 03380000 ################################################################
10304 11:49:33.150238
10305 11:49:33.792561 03400000 ################################################################
10306 11:49:33.792710
10307 11:49:34.396411 03480000 ################################################################
10308 11:49:34.396544
10309 11:49:34.977846 03500000 ################################################################
10310 11:49:34.977980
10311 11:49:35.638650 03580000 ################################################################
10312 11:49:35.639256
10313 11:49:36.357342 03600000 ################################################################
10314 11:49:36.358064
10315 11:49:36.961409 03680000 ################################################################
10316 11:49:36.961554
10317 11:49:37.595253 03700000 ################################################################
10318 11:49:37.595465
10319 11:49:38.293226 03780000 ################################################################
10320 11:49:38.293732
10321 11:49:38.999262 03800000 ################################################################
10322 11:49:38.999791
10323 11:49:39.708542 03880000 ################################################################
10324 11:49:39.709072
10325 11:49:40.406544 03900000 ################################################################
10326 11:49:40.407091
10327 11:49:41.118912 03980000 ################################################################
10328 11:49:41.119409
10329 11:49:41.827736 03a00000 ################################################################
10330 11:49:41.828307
10331 11:49:42.474442 03a80000 ################################################################
10332 11:49:42.474578
10333 11:49:43.161369 03b00000 ################################################################
10334 11:49:43.161975
10335 11:49:43.812498 03b80000 ################################################################
10336 11:49:43.813066
10337 11:49:44.479800 03c00000 ################################################################
10338 11:49:44.480352
10339 11:49:45.135924 03c80000 ################################################################
10340 11:49:45.136652
10341 11:49:45.756590 03d00000 ################################################################
10342 11:49:45.756730
10343 11:49:46.359783 03d80000 ################################################################
10344 11:49:46.360022
10345 11:49:46.939971 03e00000 ################################################################
10346 11:49:46.940150
10347 11:49:47.533619 03e80000 ################################################################
10348 11:49:47.534110
10349 11:49:48.179637 03f00000 ################################################################
10350 11:49:48.180146
10351 11:49:48.858755 03f80000 ################################################################
10352 11:49:48.859421
10353 11:49:49.363031 04000000 ################################################# done.
10354 11:49:49.363162
10355 11:49:49.366620 The bootfile was 67509234 bytes long.
10356 11:49:49.366772
10357 11:49:49.369928 Sending tftp read request... done.
10358 11:49:49.370015
10359 11:49:49.370084 Waiting for the transfer...
10360 11:49:49.370148
10361 11:49:49.373282 00000000 # done.
10362 11:49:49.373377
10363 11:49:49.379395 Command line loaded dynamically from TFTP file: 12074030/tftp-deploy-k89iqby6/kernel/cmdline
10364 11:49:49.379496
10365 11:49:49.393013 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10366 11:49:49.393484
10367 11:49:49.396424 Loading FIT.
10368 11:49:49.396880
10369 11:49:49.399672 Image ramdisk-1 has 56411674 bytes.
10370 11:49:49.400125
10371 11:49:49.402974 Image fdt-1 has 47278 bytes.
10372 11:49:49.403485
10373 11:49:49.403852 Image kernel-1 has 11048246 bytes.
10374 11:49:49.406215
10375 11:49:49.413096 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10376 11:49:49.413645
10377 11:49:49.429298 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10378 11:49:49.432908
10379 11:49:49.436388 Choosing best match conf-1 for compat google,spherion-rev2.
10380 11:49:49.440647
10381 11:49:49.444856 Connected to device vid:did:rid of 1ae0:0028:00
10382 11:49:49.453172
10383 11:49:49.456857 tpm_get_response: command 0x17b, return code 0x0
10384 11:49:49.457496
10385 11:49:49.459648 ec_init: CrosEC protocol v3 supported (256, 248)
10386 11:49:49.464796
10387 11:49:49.468595 tpm_cleanup: add release locality here.
10388 11:49:49.469243
10389 11:49:49.469785 Shutting down all USB controllers.
10390 11:49:49.472669
10391 11:49:49.473196 Removing current net device
10392 11:49:49.473550
10393 11:49:49.478012 Exiting depthcharge with code 4 at timestamp: 116996422
10394 11:49:49.478467
10395 11:49:49.481256 LZMA decompressing kernel-1 to 0x821a6718
10396 11:49:49.481766
10397 11:49:49.484758 LZMA decompressing kernel-1 to 0x40000000
10398 11:49:50.873790
10399 11:49:50.873920 jumping to kernel
10400 11:49:50.874435 end: 2.2.4 bootloader-commands (duration 00:01:29) [common]
10401 11:49:50.874560 start: 2.2.5 auto-login-action (timeout 00:02:56) [common]
10402 11:49:50.874636 Setting prompt string to ['Linux version [0-9]']
10403 11:49:50.874703 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10404 11:49:50.874770 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10405 11:49:50.955449
10406 11:49:50.958420 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10407 11:49:50.962186 start: 2.2.5.1 login-action (timeout 00:02:56) [common]
10408 11:49:50.962277 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10409 11:49:50.962347 Setting prompt string to []
10410 11:49:50.962426 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10411 11:49:50.962498 Using line separator: #'\n'#
10412 11:49:50.962557 No login prompt set.
10413 11:49:50.962617 Parsing kernel messages
10414 11:49:50.962671 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10415 11:49:50.962771 [login-action] Waiting for messages, (timeout 00:02:56)
10416 11:49:50.981362 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10417 11:49:50.984602 [ 0.000000] random: crng init done
10418 11:49:50.991259 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10419 11:49:50.994994 [ 0.000000] efi: UEFI not found.
10420 11:49:51.001371 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10421 11:49:51.008209 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10422 11:49:51.017811 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10423 11:49:51.028148 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10424 11:49:51.034409 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10425 11:49:51.041019 [ 0.000000] printk: bootconsole [mtk8250] enabled
10426 11:49:51.047829 [ 0.000000] NUMA: No NUMA configuration found
10427 11:49:51.054683 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10428 11:49:51.057455 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10429 11:49:51.060841 [ 0.000000] Zone ranges:
10430 11:49:51.067650 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10431 11:49:51.070841 [ 0.000000] DMA32 empty
10432 11:49:51.077967 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10433 11:49:51.080977 [ 0.000000] Movable zone start for each node
10434 11:49:51.084541 [ 0.000000] Early memory node ranges
10435 11:49:51.090664 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10436 11:49:51.097876 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10437 11:49:51.104208 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10438 11:49:51.110615 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10439 11:49:51.114215 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10440 11:49:51.124069 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10441 11:49:51.179373 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10442 11:49:51.186035 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10443 11:49:51.192813 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10444 11:49:51.195927 [ 0.000000] psci: probing for conduit method from DT.
10445 11:49:51.202740 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10446 11:49:51.206344 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10447 11:49:51.212791 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10448 11:49:51.215684 [ 0.000000] psci: SMC Calling Convention v1.2
10449 11:49:51.222421 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10450 11:49:51.226122 [ 0.000000] Detected VIPT I-cache on CPU0
10451 11:49:51.232524 [ 0.000000] CPU features: detected: GIC system register CPU interface
10452 11:49:51.238993 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10453 11:49:51.246114 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10454 11:49:51.252530 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10455 11:49:51.261910 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10456 11:49:51.268592 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10457 11:49:51.272042 [ 0.000000] alternatives: applying boot alternatives
10458 11:49:51.278831 [ 0.000000] Fallback order for Node 0: 0
10459 11:49:51.285456 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10460 11:49:51.288430 [ 0.000000] Policy zone: Normal
10461 11:49:51.301737 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10462 11:49:51.311540 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10463 11:49:51.323587 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10464 11:49:51.333489 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10465 11:49:51.339831 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10466 11:49:51.343032 <6>[ 0.000000] software IO TLB: area num 8.
10467 11:49:51.399719 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10468 11:49:51.548882 <6>[ 0.000000] Memory: 7914532K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 438236K reserved, 32768K cma-reserved)
10469 11:49:51.555294 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10470 11:49:51.562103 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10471 11:49:51.565749 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10472 11:49:51.571951 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10473 11:49:51.579007 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10474 11:49:51.581830 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10475 11:49:51.591798 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10476 11:49:51.598622 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10477 11:49:51.605006 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10478 11:49:51.611635 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10479 11:49:51.614873 <6>[ 0.000000] GICv3: 608 SPIs implemented
10480 11:49:51.618086 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10481 11:49:51.625053 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10482 11:49:51.628040 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10483 11:49:51.634959 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10484 11:49:51.648408 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10485 11:49:51.660931 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10486 11:49:51.667808 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10487 11:49:51.675477 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10488 11:49:51.688974 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10489 11:49:51.695169 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10490 11:49:51.701796 <6>[ 0.009183] Console: colour dummy device 80x25
10491 11:49:51.712031 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10492 11:49:51.718597 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10493 11:49:51.721631 <6>[ 0.029215] LSM: Security Framework initializing
10494 11:49:51.728756 <6>[ 0.034153] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10495 11:49:51.738303 <6>[ 0.041965] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10496 11:49:51.748193 <6>[ 0.051376] cblist_init_generic: Setting adjustable number of callback queues.
10497 11:49:51.751494 <6>[ 0.058865] cblist_init_generic: Setting shift to 3 and lim to 1.
10498 11:49:51.761509 <6>[ 0.065203] cblist_init_generic: Setting adjustable number of callback queues.
10499 11:49:51.768170 <6>[ 0.072630] cblist_init_generic: Setting shift to 3 and lim to 1.
10500 11:49:51.771335 <6>[ 0.079070] rcu: Hierarchical SRCU implementation.
10501 11:49:51.777854 <6>[ 0.084085] rcu: Max phase no-delay instances is 1000.
10502 11:49:51.784219 <6>[ 0.091109] EFI services will not be available.
10503 11:49:51.787664 <6>[ 0.096069] smp: Bringing up secondary CPUs ...
10504 11:49:51.796437 <6>[ 0.101115] Detected VIPT I-cache on CPU1
10505 11:49:51.802835 <6>[ 0.101185] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10506 11:49:51.809462 <6>[ 0.101217] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10507 11:49:51.813048 <6>[ 0.101559] Detected VIPT I-cache on CPU2
10508 11:49:51.819590 <6>[ 0.101613] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10509 11:49:51.826067 <6>[ 0.101632] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10510 11:49:51.832782 <6>[ 0.101896] Detected VIPT I-cache on CPU3
10511 11:49:51.839454 <6>[ 0.101940] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10512 11:49:51.845885 <6>[ 0.101954] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10513 11:49:51.849632 <6>[ 0.102255] CPU features: detected: Spectre-v4
10514 11:49:51.855908 <6>[ 0.102262] CPU features: detected: Spectre-BHB
10515 11:49:51.859782 <6>[ 0.102267] Detected PIPT I-cache on CPU4
10516 11:49:51.865753 <6>[ 0.102326] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10517 11:49:51.872797 <6>[ 0.102342] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10518 11:49:51.879208 <6>[ 0.102633] Detected PIPT I-cache on CPU5
10519 11:49:51.885669 <6>[ 0.102696] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10520 11:49:51.892136 <6>[ 0.102712] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10521 11:49:51.896189 <6>[ 0.102994] Detected PIPT I-cache on CPU6
10522 11:49:51.902285 <6>[ 0.103060] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10523 11:49:51.909048 <6>[ 0.103076] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10524 11:49:51.915592 <6>[ 0.103374] Detected PIPT I-cache on CPU7
10525 11:49:51.922250 <6>[ 0.103438] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10526 11:49:51.928773 <6>[ 0.103455] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10527 11:49:51.932456 <6>[ 0.103502] smp: Brought up 1 node, 8 CPUs
10528 11:49:51.938586 <6>[ 0.244840] SMP: Total of 8 processors activated.
10529 11:49:51.942302 <6>[ 0.249761] CPU features: detected: 32-bit EL0 Support
10530 11:49:51.951777 <6>[ 0.255124] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10531 11:49:51.958548 <6>[ 0.263978] CPU features: detected: Common not Private translations
10532 11:49:51.965462 <6>[ 0.270453] CPU features: detected: CRC32 instructions
10533 11:49:51.968319 <6>[ 0.275804] CPU features: detected: RCpc load-acquire (LDAPR)
10534 11:49:51.974886 <6>[ 0.281801] CPU features: detected: LSE atomic instructions
10535 11:49:51.981841 <6>[ 0.287582] CPU features: detected: Privileged Access Never
10536 11:49:51.988020 <6>[ 0.293362] CPU features: detected: RAS Extension Support
10537 11:49:51.994677 <6>[ 0.298970] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10538 11:49:51.997939 <6>[ 0.306233] CPU: All CPU(s) started at EL2
10539 11:49:52.004835 <6>[ 0.310576] alternatives: applying system-wide alternatives
10540 11:49:52.013869 <6>[ 0.321287] devtmpfs: initialized
10541 11:49:52.026306 <6>[ 0.330273] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10542 11:49:52.036686 <6>[ 0.340237] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10543 11:49:52.039968 <6>[ 0.347849] pinctrl core: initialized pinctrl subsystem
10544 11:49:52.047089 <6>[ 0.354525] DMI not present or invalid.
10545 11:49:52.054256 <6>[ 0.358938] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10546 11:49:52.061002 <6>[ 0.365814] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10547 11:49:52.070657 <6>[ 0.373398] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10548 11:49:52.077019 <6>[ 0.381623] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10549 11:49:52.084031 <6>[ 0.389869] audit: initializing netlink subsys (disabled)
10550 11:49:52.090419 <5>[ 0.395562] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10551 11:49:52.097182 <6>[ 0.396265] thermal_sys: Registered thermal governor 'step_wise'
10552 11:49:52.103277 <6>[ 0.403529] thermal_sys: Registered thermal governor 'power_allocator'
10553 11:49:52.110194 <6>[ 0.409784] cpuidle: using governor menu
10554 11:49:52.113385 <6>[ 0.420742] NET: Registered PF_QIPCRTR protocol family
10555 11:49:52.120030 <6>[ 0.426226] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10556 11:49:52.126556 <6>[ 0.433330] ASID allocator initialised with 32768 entries
10557 11:49:52.133317 <6>[ 0.439898] Serial: AMBA PL011 UART driver
10558 11:49:52.141288 <4>[ 0.448678] Trying to register duplicate clock ID: 134
10559 11:49:52.195886 <6>[ 0.506339] KASLR enabled
10560 11:49:52.210270 <6>[ 0.514077] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10561 11:49:52.216694 <6>[ 0.521090] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10562 11:49:52.223458 <6>[ 0.527579] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10563 11:49:52.230467 <6>[ 0.534584] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10564 11:49:52.236586 <6>[ 0.541073] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10565 11:49:52.243651 <6>[ 0.548076] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10566 11:49:52.249658 <6>[ 0.554565] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10567 11:49:52.256374 <6>[ 0.561569] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10568 11:49:52.259750 <6>[ 0.569065] ACPI: Interpreter disabled.
10569 11:49:52.268168 <6>[ 0.575463] iommu: Default domain type: Translated
10570 11:49:52.274867 <6>[ 0.580575] iommu: DMA domain TLB invalidation policy: strict mode
10571 11:49:52.278162 <5>[ 0.587234] SCSI subsystem initialized
10572 11:49:52.285330 <6>[ 0.591398] usbcore: registered new interface driver usbfs
10573 11:49:52.291691 <6>[ 0.597129] usbcore: registered new interface driver hub
10574 11:49:52.294425 <6>[ 0.602681] usbcore: registered new device driver usb
10575 11:49:52.302017 <6>[ 0.608778] pps_core: LinuxPPS API ver. 1 registered
10576 11:49:52.311749 <6>[ 0.613973] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10577 11:49:52.314828 <6>[ 0.623319] PTP clock support registered
10578 11:49:52.317926 <6>[ 0.627563] EDAC MC: Ver: 3.0.0
10579 11:49:52.325708 <6>[ 0.632699] FPGA manager framework
10580 11:49:52.329157 <6>[ 0.636379] Advanced Linux Sound Architecture Driver Initialized.
10581 11:49:52.332493 <6>[ 0.643144] vgaarb: loaded
10582 11:49:52.339242 <6>[ 0.646310] clocksource: Switched to clocksource arch_sys_counter
10583 11:49:52.345925 <5>[ 0.652745] VFS: Disk quotas dquot_6.6.0
10584 11:49:52.352741 <6>[ 0.656929] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10585 11:49:52.355855 <6>[ 0.664119] pnp: PnP ACPI: disabled
10586 11:49:52.363551 <6>[ 0.670775] NET: Registered PF_INET protocol family
10587 11:49:52.373306 <6>[ 0.676366] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10588 11:49:52.385094 <6>[ 0.688676] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10589 11:49:52.394986 <6>[ 0.697491] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10590 11:49:52.401366 <6>[ 0.705462] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10591 11:49:52.411017 <6>[ 0.714163] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10592 11:49:52.417779 <6>[ 0.723914] TCP: Hash tables configured (established 65536 bind 65536)
10593 11:49:52.424649 <6>[ 0.730772] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10594 11:49:52.434414 <6>[ 0.737971] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10595 11:49:52.440915 <6>[ 0.745669] NET: Registered PF_UNIX/PF_LOCAL protocol family
10596 11:49:52.443987 <6>[ 0.751841] RPC: Registered named UNIX socket transport module.
10597 11:49:52.450580 <6>[ 0.757995] RPC: Registered udp transport module.
10598 11:49:52.454263 <6>[ 0.762928] RPC: Registered tcp transport module.
10599 11:49:52.463819 <6>[ 0.767859] RPC: Registered tcp NFSv4.1 backchannel transport module.
10600 11:49:52.467227 <6>[ 0.774530] PCI: CLS 0 bytes, default 64
10601 11:49:52.470319 <6>[ 0.778919] Unpacking initramfs...
10602 11:49:52.494556 <6>[ 0.798460] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10603 11:49:52.504330 <6>[ 0.807112] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10604 11:49:52.507739 <6>[ 0.815972] kvm [1]: IPA Size Limit: 40 bits
10605 11:49:52.514505 <6>[ 0.820502] kvm [1]: GICv3: no GICV resource entry
10606 11:49:52.517864 <6>[ 0.825524] kvm [1]: disabling GICv2 emulation
10607 11:49:52.524436 <6>[ 0.830210] kvm [1]: GIC system register CPU interface enabled
10608 11:49:52.527518 <6>[ 0.836376] kvm [1]: vgic interrupt IRQ18
10609 11:49:52.534321 <6>[ 0.840736] kvm [1]: VHE mode initialized successfully
10610 11:49:52.540841 <5>[ 0.847252] Initialise system trusted keyrings
10611 11:49:52.547372 <6>[ 0.852101] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10612 11:49:52.554803 <6>[ 0.862134] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10613 11:49:52.561475 <5>[ 0.868577] NFS: Registering the id_resolver key type
10614 11:49:52.564519 <5>[ 0.873883] Key type id_resolver registered
10615 11:49:52.571399 <5>[ 0.878305] Key type id_legacy registered
10616 11:49:52.578074 <6>[ 0.882585] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10617 11:49:52.584941 <6>[ 0.889508] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10618 11:49:52.591095 <6>[ 0.897237] 9p: Installing v9fs 9p2000 file system support
10619 11:49:52.628569 <5>[ 0.935732] Key type asymmetric registered
10620 11:49:52.632148 <5>[ 0.940068] Asymmetric key parser 'x509' registered
10621 11:49:52.642018 <6>[ 0.945275] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10622 11:49:52.645301 <6>[ 0.952895] io scheduler mq-deadline registered
10623 11:49:52.648576 <6>[ 0.957666] io scheduler kyber registered
10624 11:49:52.667779 <6>[ 0.974940] EINJ: ACPI disabled.
10625 11:49:52.699393 <4>[ 1.000286] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10626 11:49:52.709374 <4>[ 1.010901] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10627 11:49:52.727408 <6>[ 1.031752] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10628 11:49:52.730902 <6>[ 1.039777] printk: console [ttyS0] disabled
10629 11:49:52.760411 <6>[ 1.064426] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10630 11:49:52.767016 <6>[ 1.073907] printk: console [ttyS0] enabled
10631 11:49:52.770285 <6>[ 1.073907] printk: console [ttyS0] enabled
10632 11:49:52.777032 <6>[ 1.082800] printk: bootconsole [mtk8250] disabled
10633 11:49:52.780399 <6>[ 1.082800] printk: bootconsole [mtk8250] disabled
10634 11:49:52.787058 <6>[ 1.094029] SuperH (H)SCI(F) driver initialized
10635 11:49:52.790124 <6>[ 1.099309] msm_serial: driver initialized
10636 11:49:52.804140 <6>[ 1.108288] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10637 11:49:52.814149 <6>[ 1.116838] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10638 11:49:52.820827 <6>[ 1.125380] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10639 11:49:52.831066 <6>[ 1.134008] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10640 11:49:52.840841 <6>[ 1.142716] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10641 11:49:52.847231 <6>[ 1.151430] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10642 11:49:52.857454 <6>[ 1.159978] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10643 11:49:52.864075 <6>[ 1.168770] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10644 11:49:52.873969 <6>[ 1.177313] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10645 11:49:52.885671 <6>[ 1.193003] loop: module loaded
10646 11:49:52.892180 <6>[ 1.199120] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10647 11:49:52.915370 <4>[ 1.222686] mtk-pmic-keys: Failed to locate of_node [id: -1]
10648 11:49:52.922276 <6>[ 1.229724] megasas: 07.719.03.00-rc1
10649 11:49:52.932432 <6>[ 1.239435] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10650 11:49:52.938624 <6>[ 1.245705] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10651 11:49:52.955206 <6>[ 1.262413] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10652 11:49:53.011773 <6>[ 1.312203] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10653 11:49:54.866020 <6>[ 3.173546] Freeing initrd memory: 55084K
10654 11:49:54.876498 <6>[ 3.183944] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10655 11:49:54.887407 <6>[ 3.194816] tun: Universal TUN/TAP device driver, 1.6
10656 11:49:54.890508 <6>[ 3.200872] thunder_xcv, ver 1.0
10657 11:49:54.893770 <6>[ 3.204379] thunder_bgx, ver 1.0
10658 11:49:54.897226 <6>[ 3.207872] nicpf, ver 1.0
10659 11:49:54.907882 <6>[ 3.211884] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10660 11:49:54.911114 <6>[ 3.219360] hns3: Copyright (c) 2017 Huawei Corporation.
10661 11:49:54.917537 <6>[ 3.224945] hclge is initializing
10662 11:49:54.920867 <6>[ 3.228520] e1000: Intel(R) PRO/1000 Network Driver
10663 11:49:54.927938 <6>[ 3.233649] e1000: Copyright (c) 1999-2006 Intel Corporation.
10664 11:49:54.930639 <6>[ 3.239661] e1000e: Intel(R) PRO/1000 Network Driver
10665 11:49:54.937487 <6>[ 3.244877] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10666 11:49:54.944109 <6>[ 3.251064] igb: Intel(R) Gigabit Ethernet Network Driver
10667 11:49:54.950803 <6>[ 3.256714] igb: Copyright (c) 2007-2014 Intel Corporation.
10668 11:49:54.957435 <6>[ 3.262549] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10669 11:49:54.963758 <6>[ 3.269067] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10670 11:49:54.967401 <6>[ 3.275530] sky2: driver version 1.30
10671 11:49:54.974173 <6>[ 3.280517] VFIO - User Level meta-driver version: 0.3
10672 11:49:54.981146 <6>[ 3.288783] usbcore: registered new interface driver usb-storage
10673 11:49:54.987897 <6>[ 3.295227] usbcore: registered new device driver onboard-usb-hub
10674 11:49:54.996730 <6>[ 3.304406] mt6397-rtc mt6359-rtc: registered as rtc0
10675 11:49:55.007207 <6>[ 3.309875] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:49:55 UTC (1700826595)
10676 11:49:55.009984 <6>[ 3.319438] i2c_dev: i2c /dev entries driver
10677 11:49:55.026917 <6>[ 3.331203] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10678 11:49:55.046887 <6>[ 3.354206] cpu cpu0: EM: created perf domain
10679 11:49:55.051298 <6>[ 3.359124] cpu cpu4: EM: created perf domain
10680 11:49:55.056753 <6>[ 3.364381] sdhci: Secure Digital Host Controller Interface driver
10681 11:49:55.063405 <6>[ 3.370813] sdhci: Copyright(c) Pierre Ossman
10682 11:49:55.069947 <6>[ 3.375768] Synopsys Designware Multimedia Card Interface Driver
10683 11:49:55.076742 <6>[ 3.382405] sdhci-pltfm: SDHCI platform and OF driver helper
10684 11:49:55.079797 <6>[ 3.382524] mmc0: CQHCI version 5.10
10685 11:49:55.086852 <6>[ 3.392537] ledtrig-cpu: registered to indicate activity on CPUs
10686 11:49:55.093388 <6>[ 3.399526] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10687 11:49:55.100418 <6>[ 3.406600] usbcore: registered new interface driver usbhid
10688 11:49:55.103213 <6>[ 3.412424] usbhid: USB HID core driver
10689 11:49:55.109606 <6>[ 3.416630] spi_master spi0: will run message pump with realtime priority
10690 11:49:55.153221 <6>[ 3.453824] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10691 11:49:55.172150 <6>[ 3.469656] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10692 11:49:55.179296 <6>[ 3.485460] cros-ec-spi spi0.0: Chrome EC device registered
10693 11:49:55.183009 <6>[ 3.491567] mmc0: Command Queue Engine enabled
10694 11:49:55.189192 <6>[ 3.496337] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10695 11:49:55.196530 <6>[ 3.504051] mmcblk0: mmc0:0001 DA4128 116 GiB
10696 11:49:55.207063 <6>[ 3.514554] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10697 11:49:55.215271 <6>[ 3.522374] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10698 11:49:55.224768 <6>[ 3.526273] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10699 11:49:55.228005 <6>[ 3.528320] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10700 11:49:55.234864 <6>[ 3.538252] NET: Registered PF_PACKET protocol family
10701 11:49:55.241316 <6>[ 3.542932] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10702 11:49:55.244669 <6>[ 3.547512] 9pnet: Installing 9P2000 support
10703 11:49:55.251061 <5>[ 3.558521] Key type dns_resolver registered
10704 11:49:55.254581 <6>[ 3.563457] registered taskstats version 1
10705 11:49:55.261258 <5>[ 3.567841] Loading compiled-in X.509 certificates
10706 11:49:55.289329 <4>[ 3.590336] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10707 11:49:55.299341 <4>[ 3.601121] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10708 11:49:55.306356 <3>[ 3.611673] debugfs: File 'uA_load' in directory '/' already present!
10709 11:49:55.312873 <3>[ 3.618465] debugfs: File 'min_uV' in directory '/' already present!
10710 11:49:55.319286 <3>[ 3.625098] debugfs: File 'max_uV' in directory '/' already present!
10711 11:49:55.326043 <3>[ 3.631723] debugfs: File 'constraint_flags' in directory '/' already present!
10712 11:49:55.337302 <3>[ 3.641443] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10713 11:49:55.347610 <6>[ 3.655304] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10714 11:49:55.354617 <6>[ 3.662247] xhci-mtk 11200000.usb: xHCI Host Controller
10715 11:49:55.364680 <6>[ 3.667765] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10716 11:49:55.371057 <6>[ 3.675596] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10717 11:49:55.377849 <6>[ 3.685008] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10718 11:49:55.384314 <6>[ 3.691082] xhci-mtk 11200000.usb: xHCI Host Controller
10719 11:49:55.390733 <6>[ 3.696558] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10720 11:49:55.397773 <6>[ 3.704204] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10721 11:49:55.404733 <6>[ 3.711861] hub 1-0:1.0: USB hub found
10722 11:49:55.407721 <6>[ 3.715867] hub 1-0:1.0: 1 port detected
10723 11:49:55.417384 <6>[ 3.720135] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10724 11:49:55.420861 <6>[ 3.728676] hub 2-0:1.0: USB hub found
10725 11:49:55.424539 <6>[ 3.732679] hub 2-0:1.0: 1 port detected
10726 11:49:55.432975 <6>[ 3.740392] mtk-msdc 11f70000.mmc: Got CD GPIO
10727 11:49:55.443237 <6>[ 3.747204] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10728 11:49:55.449498 <6>[ 3.755225] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10729 11:49:55.459810 <4>[ 3.763137] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10730 11:49:55.469629 <6>[ 3.772660] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10731 11:49:55.475882 <6>[ 3.780737] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10732 11:49:55.482426 <6>[ 3.788745] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10733 11:49:55.492739 <6>[ 3.796666] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10734 11:49:55.499672 <6>[ 3.804482] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10735 11:49:55.509255 <6>[ 3.812299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10736 11:49:55.518855 <6>[ 3.822670] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10737 11:49:55.526029 <6>[ 3.831033] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10738 11:49:55.535531 <6>[ 3.839372] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10739 11:49:55.542604 <6>[ 3.847712] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10740 11:49:55.552141 <6>[ 3.856053] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10741 11:49:55.559137 <6>[ 3.864393] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10742 11:49:55.568968 <6>[ 3.872731] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10743 11:49:55.575249 <6>[ 3.881071] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10744 11:49:55.585207 <6>[ 3.889442] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10745 11:49:55.592032 <6>[ 3.897782] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10746 11:49:55.601648 <6>[ 3.906121] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10747 11:49:55.611779 <6>[ 3.914471] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10748 11:49:55.618291 <6>[ 3.922811] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10749 11:49:55.628421 <6>[ 3.931149] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10750 11:49:55.634892 <6>[ 3.939490] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10751 11:49:55.641670 <6>[ 3.948242] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10752 11:49:55.647820 <6>[ 3.955475] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10753 11:49:55.654636 <6>[ 3.962334] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10754 11:49:55.665110 <6>[ 3.969167] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10755 11:49:55.671766 <6>[ 3.976184] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10756 11:49:55.677858 <6>[ 3.983049] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10757 11:49:55.688166 <6>[ 3.992181] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10758 11:49:55.697959 <6>[ 4.001300] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10759 11:49:55.707940 <6>[ 4.010594] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10760 11:49:55.717810 <6>[ 4.020069] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10761 11:49:55.727499 <6>[ 4.029537] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10762 11:49:55.734538 <6>[ 4.038658] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10763 11:49:55.744412 <6>[ 4.048127] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10764 11:49:55.754212 <6>[ 4.057246] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10765 11:49:55.763883 <6>[ 4.066542] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10766 11:49:55.774218 <6>[ 4.076703] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10767 11:49:55.784074 <6>[ 4.088245] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10768 11:49:55.814552 <6>[ 4.118783] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10769 11:49:55.841916 <6>[ 4.149345] hub 2-1:1.0: USB hub found
10770 11:49:55.844917 <6>[ 4.153750] hub 2-1:1.0: 3 ports detected
10771 11:49:55.853171 <6>[ 4.160475] hub 2-1:1.0: USB hub found
10772 11:49:55.856322 <6>[ 4.164942] hub 2-1:1.0: 3 ports detected
10773 11:49:55.966161 <6>[ 4.270607] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10774 11:49:56.120786 <6>[ 4.428272] hub 1-1:1.0: USB hub found
10775 11:49:56.123755 <6>[ 4.432780] hub 1-1:1.0: 4 ports detected
10776 11:49:56.133719 <6>[ 4.441323] hub 1-1:1.0: USB hub found
10777 11:49:56.137066 <6>[ 4.445856] hub 1-1:1.0: 4 ports detected
10778 11:49:56.206072 <6>[ 4.510669] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10779 11:49:56.458491 <6>[ 4.762603] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10780 11:49:56.590368 <6>[ 4.898136] hub 1-1.4:1.0: USB hub found
10781 11:49:56.594016 <6>[ 4.902790] hub 1-1.4:1.0: 2 ports detected
10782 11:49:56.603274 <6>[ 4.910789] hub 1-1.4:1.0: USB hub found
10783 11:49:56.606646 <6>[ 4.915332] hub 1-1.4:1.0: 2 ports detected
10784 11:49:56.902429 <6>[ 5.206599] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10785 11:49:57.094353 <6>[ 5.398619] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10786 11:50:08.058542 <6>[ 16.367593] ALSA device list:
10787 11:50:08.061884 <6>[ 16.370885] No soundcards found.
10788 11:50:08.069926 <6>[ 16.378830] Freeing unused kernel memory: 8384K
10789 11:50:08.073489 <6>[ 16.383833] Run /init as init process
10790 11:50:08.121576 <6>[ 16.430833] NET: Registered PF_INET6 protocol family
10791 11:50:08.128351 <6>[ 16.437254] Segment Routing with IPv6
10792 11:50:08.131583 <6>[ 16.441212] In-situ OAM (IOAM) with IPv6
10793 11:50:08.165595 <30>[ 16.454367] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10794 11:50:08.168419 <30>[ 16.478165] systemd[1]: Detected architecture arm64.
10795 11:50:08.168519
10796 11:50:08.174889 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10797 11:50:08.174972
10798 11:50:08.189456 <30>[ 16.498576] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10799 11:50:08.335169 <30>[ 16.641087] systemd[1]: Queued start job for default target Graphical Interface.
10800 11:50:08.402458 <30>[ 16.711627] systemd[1]: Created slice system-getty.slice.
10801 11:50:08.408967 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10802 11:50:08.426180 <30>[ 16.735349] systemd[1]: Created slice system-modprobe.slice.
10803 11:50:08.432689 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10804 11:50:08.454744 <30>[ 16.763819] systemd[1]: Created slice system-serial\x2dgetty.slice.
10805 11:50:08.464584 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10806 11:50:08.478730 <30>[ 16.787580] systemd[1]: Created slice User and Session Slice.
10807 11:50:08.485238 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10808 11:50:08.505980 <30>[ 16.811447] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10809 11:50:08.515436 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10810 11:50:08.533732 <30>[ 16.839348] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10811 11:50:08.540386 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10812 11:50:08.564630 <30>[ 16.867083] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10813 11:50:08.571158 <30>[ 16.879345] systemd[1]: Reached target Local Encrypted Volumes.
10814 11:50:08.577620 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10815 11:50:08.594182 <30>[ 16.903123] systemd[1]: Reached target Paths.
10816 11:50:08.597488 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10817 11:50:08.613515 <30>[ 16.922584] systemd[1]: Reached target Remote File Systems.
10818 11:50:08.619879 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10819 11:50:08.633638 <30>[ 16.942570] systemd[1]: Reached target Slices.
10820 11:50:08.636875 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10821 11:50:08.653379 <30>[ 16.962596] systemd[1]: Reached target Swap.
10822 11:50:08.656713 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10823 11:50:08.677120 <30>[ 16.983088] systemd[1]: Listening on initctl Compatibility Named Pipe.
10824 11:50:08.683984 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10825 11:50:08.698882 <30>[ 17.008104] systemd[1]: Listening on Journal Audit Socket.
10826 11:50:08.706029 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10827 11:50:08.722865 <30>[ 17.031775] systemd[1]: Listening on Journal Socket (/dev/log).
10828 11:50:08.729389 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10829 11:50:08.746986 <30>[ 17.055786] systemd[1]: Listening on Journal Socket.
10830 11:50:08.753171 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10831 11:50:08.765857 <30>[ 17.075154] systemd[1]: Listening on udev Control Socket.
10832 11:50:08.772858 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10833 11:50:08.790680 <30>[ 17.099639] systemd[1]: Listening on udev Kernel Socket.
10834 11:50:08.797130 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10835 11:50:08.849900 <30>[ 17.158843] systemd[1]: Mounting Huge Pages File System...
10836 11:50:08.856405 Mounting [0;1;39mHuge Pages File System[0m...
10837 11:50:08.873785 <30>[ 17.182565] systemd[1]: Mounting POSIX Message Queue File System...
10838 11:50:08.880002 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10839 11:50:08.901487 <30>[ 17.210659] systemd[1]: Mounting Kernel Debug File System...
10840 11:50:08.907956 Mounting [0;1;39mKernel Debug File System[0m...
10841 11:50:08.924974 <30>[ 17.231017] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10842 11:50:08.972974 <30>[ 17.278934] systemd[1]: Starting Create list of static device nodes for the current kernel...
10843 11:50:08.979641 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10844 11:50:09.002035 <30>[ 17.310883] systemd[1]: Starting Load Kernel Module configfs...
10845 11:50:09.008337 Starting [0;1;39mLoad Kernel Module configfs[0m...
10846 11:50:09.025330 <30>[ 17.334441] systemd[1]: Starting Load Kernel Module drm...
10847 11:50:09.031980 Starting [0;1;39mLoad Kernel Module drm[0m...
10848 11:50:09.049145 <30>[ 17.354702] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10849 11:50:09.063085 <30>[ 17.372337] systemd[1]: Starting Journal Service...
10850 11:50:09.066615 Starting [0;1;39mJournal Service[0m...
10851 11:50:09.084304 <30>[ 17.393414] systemd[1]: Starting Load Kernel Modules...
10852 11:50:09.091143 Starting [0;1;39mLoad Kernel Modules[0m...
10853 11:50:09.113765 <30>[ 17.419615] systemd[1]: Starting Remount Root and Kernel File Systems...
10854 11:50:09.120218 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10855 11:50:09.136490 <30>[ 17.445573] systemd[1]: Starting Coldplug All udev Devices...
10856 11:50:09.142864 Starting [0;1;39mColdplug All udev Devices[0m...
10857 11:50:09.160404 <30>[ 17.469523] systemd[1]: Started Journal Service.
10858 11:50:09.166809 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10859 11:50:09.183966 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10860 11:50:09.202302 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10861 11:50:09.218444 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10862 11:50:09.240327 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10863 11:50:09.255996 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10864 11:50:09.276529 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10865 11:50:09.294291 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10866 11:50:09.315601 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10867 11:50:09.329357 See 'systemctl status systemd-remount-fs.service' for details.
10868 11:50:09.390938 Mounting [0;1;39mKernel Configuration File System[0m...
10869 11:50:09.408512 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10870 11:50:09.421140 <46>[ 17.727267] systemd-journald[183]: Received client request to flush runtime journal.
10871 11:50:09.430071 Starting [0;1;39mLoad/Save Random Seed[0m...
10872 11:50:09.452232 Starting [0;1;39mApply Kernel Variables[0m...
10873 11:50:09.470346 Starting [0;1;39mCreate System Users[0m...
10874 11:50:09.488574 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10875 11:50:09.506959 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10876 11:50:09.526655 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10877 11:50:09.543584 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10878 11:50:09.563183 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10879 11:50:09.579312 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10880 11:50:09.630177 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10881 11:50:09.653078 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10882 11:50:09.665629 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10883 11:50:09.681606 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10884 11:50:09.717812 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10885 11:50:09.746059 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10886 11:50:09.767593 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10887 11:50:09.788171 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10888 11:50:09.839883 Starting [0;1;39mNetwork Time Synchronization[0m...
10889 11:50:09.865324 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10890 11:50:09.900867 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10891 11:50:09.923453 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10892 11:50:09.934520 <6>[ 18.240503] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10893 11:50:09.940987 <6>[ 18.245626] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10894 11:50:09.950893 <6>[ 18.254436] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10895 11:50:09.954216 <6>[ 18.260438] remoteproc remoteproc0: scp is available
10896 11:50:09.964530 <6>[ 18.265634] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10897 11:50:09.970853 <6>[ 18.269884] remoteproc remoteproc0: powering up scp
10898 11:50:09.977251 <6>[ 18.283681] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10899 11:50:09.984042 <6>[ 18.292237] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10900 11:50:09.990595 [[0;32m OK [<6>[ 18.293246] mc: Linux media interface: v0.10
10901 11:50:09.997055 0m] Started [0;<6>[ 18.300510] usbcore: registered new interface driver r8152
10902 11:50:10.000179 1;39mNetwork Time Synchronization[0m.
10903 11:50:10.027168 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_ba<4>[ 18.331963] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10904 11:50:10.027280 cklight[0m.
10905 11:50:10.037307 <3>[ 18.333003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10906 11:50:10.043852 <4>[ 18.343539] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10907 11:50:10.050414 <3>[ 18.350050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 11:50:10.057298 <6>[ 18.358185] videodev: Linux video capture interface: v2.00
10909 11:50:10.066729 <3>[ 18.365480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10910 11:50:10.073249 [[0;32m OK [<3>[ 18.380229] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 11:50:10.083031 0m] Found device<6>[ 18.383551] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10912 11:50:10.093027 [0;1;39m/dev/t<3>[ 18.390235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10913 11:50:10.093114 tyS0[0m.
10914 11:50:10.103182 <6>[ 18.394833] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10915 11:50:10.109946 <6>[ 18.407991] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10916 11:50:10.116362 <3>[ 18.415970] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10917 11:50:10.126350 <6>[ 18.419162] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10918 11:50:10.135911 <4>[ 18.420550] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10919 11:50:10.139349 <4>[ 18.420550] Fallback method does not support PEC.
10920 11:50:10.149502 <6>[ 18.423298] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10921 11:50:10.156198 <6>[ 18.423297] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10922 11:50:10.165892 <6>[ 18.423472] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10923 11:50:10.169291 <6>[ 18.423543] pci_bus 0000:00: root bus resource [bus 00-ff]
10924 11:50:10.176229 <6>[ 18.423553] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10925 11:50:10.187256 <6>[ 18.423556] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10926 11:50:10.193768 <6>[ 18.423595] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10927 11:50:10.200545 <6>[ 18.423615] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10928 11:50:10.207311 <6>[ 18.423681] pci 0000:00:00.0: supports D1 D2
10929 11:50:10.213520 <6>[ 18.423683] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10930 11:50:10.221107 <4>[ 18.429901] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10931 11:50:10.230610 <4>[ 18.429914] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10932 11:50:10.237102 <3>[ 18.430827] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10933 11:50:10.247282 <3>[ 18.430834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10934 11:50:10.253699 <3>[ 18.433754] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10935 11:50:10.263906 <6>[ 18.437711] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10936 11:50:10.267777 <6>[ 18.437986] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10937 11:50:10.277768 <6>[ 18.438027] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10938 11:50:10.284373 <6>[ 18.438055] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10939 11:50:10.291542 <6>[ 18.438074] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10940 11:50:10.294957 <6>[ 18.438249] pci 0000:01:00.0: supports D1 D2
10941 11:50:10.301333 <6>[ 18.438254] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10942 11:50:10.308034 <6>[ 18.441757] remoteproc remoteproc0: remote processor scp is now up
10943 11:50:10.314692 <6>[ 18.454484] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10944 11:50:10.324840 <6>[ 18.454534] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10945 11:50:10.331346 <6>[ 18.454537] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10946 11:50:10.341855 <6>[ 18.454546] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10947 11:50:10.348529 <6>[ 18.454559] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10948 11:50:10.355103 <6>[ 18.454572] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10949 11:50:10.361872 <6>[ 18.454585] pci 0000:00:00.0: PCI bridge to [bus 01]
10950 11:50:10.368387 <6>[ 18.454590] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10951 11:50:10.378335 <3>[ 18.454782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10952 11:50:10.385572 <6>[ 18.458872] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10953 11:50:10.392542 <6>[ 18.462054] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10954 11:50:10.399182 <6>[ 18.480823] r8152 2-1.3:1.0 eth0: v1.12.13
10955 11:50:10.405759 <3>[ 18.485016] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10956 11:50:10.415950 <3>[ 18.485020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10957 11:50:10.422648 <3>[ 18.494548] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 11:50:10.429534 <6>[ 18.494805] usbcore: registered new interface driver cdc_ether
10959 11:50:10.439444 <3>[ 18.514283] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 11:50:10.442735 <6>[ 18.521099] Bluetooth: Core ver 2.22
10961 11:50:10.449420 <6>[ 18.521711] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10962 11:50:10.462188 <6>[ 18.523767] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10963 11:50:10.469106 <6>[ 18.523958] usbcore: registered new interface driver uvcvideo
10964 11:50:10.475423 <3>[ 18.529203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10965 11:50:10.482357 <6>[ 18.537078] NET: Registered PF_BLUETOOTH protocol family
10966 11:50:10.488907 <3>[ 18.537518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 11:50:10.498628 <3>[ 18.544859] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10968 11:50:10.505018 <6>[ 18.546046] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10969 11:50:10.508728 <6>[ 18.546247] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10970 11:50:10.515116 <6>[ 18.551922] usbcore: registered new interface driver r8153_ecm
10971 11:50:10.522016 <6>[ 18.552661] Bluetooth: HCI device and connection manager initialized
10972 11:50:10.528470 <6>[ 18.552682] Bluetooth: HCI socket layer initialized
10973 11:50:10.534694 <3>[ 18.560770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10974 11:50:10.542433 <6>[ 18.568840] Bluetooth: L2CAP socket layer initialized
10975 11:50:10.545222 <6>[ 18.569645] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10976 11:50:10.555299 <6>[ 18.569825] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10977 11:50:10.565241 <6>[ 18.572619] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10978 11:50:10.571952 <3>[ 18.577140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10979 11:50:10.579078 <3>[ 18.583166] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 11:50:10.585565 <6>[ 18.583370] Bluetooth: SCO socket layer initialized
10981 11:50:10.592339 <3>[ 18.583920] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10982 11:50:10.602641 <3>[ 18.590828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10983 11:50:10.609242 <6>[ 18.599671] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10984 11:50:10.616399 <3>[ 18.605826] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10985 11:50:10.623620 <3>[ 18.607023] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 11:50:10.629755 <6>[ 18.631242] usbcore: registered new interface driver btusb
10987 11:50:10.640714 <4>[ 18.632131] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10988 11:50:10.647246 <3>[ 18.632139] Bluetooth: hci0: Failed to load firmware file (-2)
10989 11:50:10.654018 <3>[ 18.632141] Bluetooth: hci0: Failed to set up firmware (-2)
10990 11:50:10.663446 <4>[ 18.632144] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10991 11:50:10.670577 <5>[ 18.648279] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10992 11:50:10.682686 <3>[ 18.661548] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10993 11:50:10.686677 <5>[ 18.674134] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10994 11:50:10.696996 <3>[ 18.700806] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 11:50:10.703214 <4>[ 18.708016] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10996 11:50:10.713198 <3>[ 18.732219] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 11:50:10.719613 <6>[ 18.737250] cfg80211: failed to load regulatory.db
10998 11:50:10.726310 <6>[ 18.830745] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10999 11:50:10.733220 <3>[ 18.856996] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 11:50:10.739641 <6>[ 18.861437] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11001 11:50:10.749415 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11002 11:50:10.766178 <6>[ 19.075579] mt7921e 0000:01:00.0: ASIC revision: 79610010
11003 11:50:10.810885 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11004 11:50:10.825543 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11005 11:50:10.845000 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11006 11:50:10.857868 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11007 11:50:10.871735 <4>[ 19.174395] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11008 11:50:10.878408 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11009 11:50:10.901355 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11010 11:50:10.913408 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11011 11:50:10.933522 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11012 11:50:10.949344 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11013 11:50:10.965297 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11014 11:50:10.990558 <4>[ 19.293229] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11015 11:50:11.000323 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11016 11:50:11.046469 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11017 11:50:11.084916 Starting [0;1;39mUser Login Management[0m...
11018 11:50:11.111126 <4>[ 19.413582] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11019 11:50:11.117710 Starting [0;1;39mPermit User Sessions[0m...
11020 11:50:11.137828 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11021 11:50:11.236558 [[0;32m OK [0m] Started [0;<4>[ 19.537394] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11022 11:50:11.236663 1;39mGetty on tty1[0m.
11023 11:50:11.259952 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11024 11:50:11.266951 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11025 11:50:11.285865 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11026 11:50:11.306170 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11027 11:50:11.325942 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11028 11:50:11.354485 [[0;32m OK [<4>[ 19.657423] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11029 11:50:11.360829 0m] Reached target [0;1;39mMulti-User System[0m.
11030 11:50:11.375539 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11031 11:50:11.434644 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11032 11:50:11.474761 <4>[ 19.777533] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11033 11:50:11.481010 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11034 11:50:11.504051
11035 11:50:11.504137
11036 11:50:11.507328 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11037 11:50:11.507410
11038 11:50:11.510739 debian-bullseye-arm64 login: root (automatic login)
11039 11:50:11.510821
11040 11:50:11.510885
11041 11:50:11.529097 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
11042 11:50:11.529181
11043 11:50:11.535791 The programs included with the Debian GNU/Linux system are free software;
11044 11:50:11.542128 the exact distribution terms for each program are described in the
11045 11:50:11.545528 individual files in /usr/share/doc/*/copyright.
11046 11:50:11.545610
11047 11:50:11.552066 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11048 11:50:11.555532 permitted by applicable law.
11049 11:50:11.555911 Matched prompt #10: / #
11051 11:50:11.556113 Setting prompt string to ['/ #']
11052 11:50:11.556213 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11054 11:50:11.556437 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11055 11:50:11.556523 start: 2.2.6 expect-shell-connection (timeout 00:02:35) [common]
11056 11:50:11.556591 Setting prompt string to ['/ #']
11057 11:50:11.556650 Forcing a shell prompt, looking for ['/ #']
11059 11:50:11.606863 / #
11060 11:50:11.606969 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11061 11:50:11.607043 Waiting using forced prompt support (timeout 00:02:30)
11062 11:50:11.607138 <4>[ 19.897479] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11063 11:50:11.611857
11064 11:50:11.612166 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11065 11:50:11.612270 start: 2.2.7 export-device-env (timeout 00:02:35) [common]
11066 11:50:11.612362 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11067 11:50:11.612448 end: 2.2 depthcharge-retry (duration 00:02:25) [common]
11068 11:50:11.612531 end: 2 depthcharge-action (duration 00:02:25) [common]
11069 11:50:11.612618 start: 3 lava-test-retry (timeout 00:07:12) [common]
11070 11:50:11.612699 start: 3.1 lava-test-shell (timeout 00:07:12) [common]
11071 11:50:11.612770 Using namespace: common
11073 11:50:11.713102 / # #
11074 11:50:11.713229 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11075 11:50:11.714216 #<4>[ 20.016784] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11076 11:50:11.756365
11077 11:50:11.756643 Using /lava-12074030
11079 11:50:11.856956 / # export SHELL=/bin/sh
11080 11:50:11.857123 export SHELL=/bin/sh<4>[ 20.137261] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11081 11:50:11.862105
11083 11:50:11.962624 / # . /lava-12074030/environment
11084 11:50:11.962788 . /lava-12074030/environment<4>[ 20.256634] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11085 11:50:11.968328
11087 11:50:12.068866 / # /lava-12074030/bin/lava-test-runner /lava-12074030/0
11088 11:50:12.068987 Test shell timeout: 10s (minimum of the action and connection timeout)
11089 11:50:12.069317 /lava-12074030/bin/lava-test-runner /lava-12074030/0<3>[ 20.374927] mt7921e 0000:01:00.0: hardware init failed
11090 11:50:12.073756
11091 11:50:12.116360 + export TESTRUN<8>[ 20.408120] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12074030_1.5.2.3.1>
11092 11:50:12.116474 _ID=0_igt-gpu-panfrost
11093 11:50:12.116568 + cd /lava-12074030/0/tests/0_igt-gpu-panfrost
11094 11:50:12.116664 + cat uuid
11095 11:50:12.116726 + UUID=12074030_1.5.2.3.1
11096 11:50:12.116784 + set +x
11097 11:50:12.117017 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12074030_1.5.2.3.1
11098 11:50:12.117086 Starting test lava.0_igt-gpu-panfrost (12074030_1.5.2.3.1)
11099 11:50:12.117168 Skipping test definition patterns.
11100 11:50:12.120532 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11101 11:50:12.132960 <8>[ 20.442414] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11102 11:50:12.133214 Received signal: <TESTSET> START panfrost_gem_new
11103 11:50:12.133286 Starting test_set panfrost_gem_new
11104 11:50:12.165342 <14>[ 20.474786] [IGT] panfrost_gem_new: executing
11105 11:50:12.175227 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.482711] [IGT] panfrost_gem_new: exiting, ret=77
11106 11:50:12.175311 .1.62-cip9 aarch64)
11107 11:50:12.188455 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c<8>[ 20.496340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11108 11:50:12.188712 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11110 11:50:12.191664 :621:
11111 11:50:12.191744 Test requirement: !(fd<0)
11112 11:50:12.198291 No known gpu found for chipset flags 0x32 (panfrost)
11113 11:50:12.202047 Last errno: 2, No such file or directory
11114 11:50:12.205131 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11115 11:50:12.211737 <14>[ 20.520268] [IGT] panfrost_gem_new: executing
11116 11:50:12.218350 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.527117] [IGT] panfrost_gem_new: exiting, ret=77
11117 11:50:12.221620 rch64) (Linux: 6.1.62-cip9 aarch64)
11118 11:50:12.231487 Test requirement not met in<8>[ 20.538033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11119 11:50:12.231744 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11121 11:50:12.234932 function drm_open_driver, file ../lib/drmtest.c:621:
11122 11:50:12.237925 Test requirement: !(fd<0)
11123 11:50:12.241574 No known gpu found for chipset flags 0x32 (panfrost)
11124 11:50:12.248081 Last errno: 2, No such f<14>[ 20.557910] [IGT] panfrost_gem_new: executing
11125 11:50:12.251487 ile or directory
11126 11:50:12.257955 [1mSubtest ge<14>[ 20.566032] [IGT] panfrost_gem_new: exiting, ret=77
11127 11:50:12.261631 m-new-0: SKIP (0.000s)[0m
11128 11:50:12.270834 IGT-Version: 1.27.1-g621c2d3 (aarch6<8>[ 20.577427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11129 11:50:12.271090 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11131 11:50:12.274455 4) (Linux: 6.1.62-cip9 aarch64)
11132 11:50:12.277619 <8>[ 20.586171] <LAVA_SIGNAL_TESTSET STOP>
11133 11:50:12.277701
11134 11:50:12.277936 Received signal: <TESTSET> STOP
11135 11:50:12.278004 Closing test_set panfrost_gem_new
11136 11:50:12.284069 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11137 11:50:12.287316 Test requirement: !(fd<0)
11138 11:50:12.290907 No known gpu found for chipset flags 0x32 (panfrost)
11139 11:50:12.293919 Last errno: 2, No such file or directory
11140 11:50:12.300636 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11141 11:50:12.307105 <8>[ 20.616686] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11142 11:50:12.307360 Received signal: <TESTSET> START panfrost_get_param
11143 11:50:12.307429 Starting test_set panfrost_get_param
11144 11:50:12.334199 <14>[ 20.643488] [IGT] panfrost_get_param: executing
11145 11:50:12.344131 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.651541] [IGT] panfrost_get_param: exiting, ret=77
11146 11:50:12.347213 .1.62-cip9 aarch64)
11147 11:50:12.353937 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11148 11:50:12.360336 Test requ<8>[ 20.667821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11149 11:50:12.360419 irement: !(fd<0)
11150 11:50:12.360663 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11152 11:50:12.367223 No known gpu found for chipset flags 0x32 (panfrost)
11153 11:50:12.370515 Last errno: 2, No such file or directory
11154 11:50:12.373621 [1mSubtest base-params: SKIP (0.000s)[0m
11155 11:50:12.380082 <14>[ 20.688029] [IGT] panfrost_get_param: executing
11156 11:50:12.386792 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.695669] [IGT] panfrost_get_param: exiting, ret=77
11157 11:50:12.389943 rch64) (Linux: 6.1.62-cip9 aarch64)
11158 11:50:12.399943 Test requirement not met in function drm_op<8>[ 20.708358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11159 11:50:12.400198 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11161 11:50:12.406604 en_driver, file ../lib/drmtest.c:621:
11162 11:50:12.406685 Test requirement: !(fd<0)
11163 11:50:12.413215 No known gpu found for chipset flags 0x32 (panfrost)
11164 11:50:12.416346 Last errno: 2, No such file or directory
11165 11:50:12.419718 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11166 11:50:12.427812 <14>[ 20.737483] [IGT] panfrost_get_param: executing
11167 11:50:12.438002 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.745504] [IGT] panfrost_get_param: exiting, ret=77
11168 11:50:12.441387 rch64) (Linux: 6.1.62-cip9 aarch64)
11169 11:50:12.454492 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c<8>[ 20.759867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11170 11:50:12.454577 :621:
11171 11:50:12.454815 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11173 11:50:12.461015 Test requirement: !(fd<0)<8>[ 20.769610] <LAVA_SIGNAL_TESTSET STOP>
11174 11:50:12.461097
11175 11:50:12.461331 Received signal: <TESTSET> STOP
11176 11:50:12.461395 Closing test_set panfrost_get_param
11177 11:50:12.464491 No known gpu found for chipset flags 0x32 (panfrost)
11178 11:50:12.467648 Last errno: 2, No such file or directory
11179 11:50:12.474507 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11180 11:50:12.491279 <8>[ 20.800802] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11181 11:50:12.491534 Received signal: <TESTSET> START panfrost_prime
11182 11:50:12.491602 Starting test_set panfrost_prime
11183 11:50:12.518085 <14>[ 20.827737] [IGT] panfrost_prime: executing
11184 11:50:12.525266 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.835336] [IGT] panfrost_prime: exiting, ret=77
11185 11:50:12.527961 rch64) (Linux: 6.1.62-cip9 aarch64)
11186 11:50:12.541383 Test requirement not met in function drm_op<8>[ 20.846831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11187 11:50:12.541639 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11189 11:50:12.548123 en_driver, file ../lib/drmtest.c<8>[ 20.856333] <LAVA_SIGNAL_TESTSET STOP>
11190 11:50:12.548270 :621:
11191 11:50:12.548508 Received signal: <TESTSET> STOP
11192 11:50:12.548574 Closing test_set panfrost_prime
11193 11:50:12.551557 Test requirement: !(fd<0)
11194 11:50:12.554638 No known gpu found for chipset flags 0x32 (panfrost)
11195 11:50:12.558146 Last errno: 2, No such file or directory
11196 11:50:12.561246 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11197 11:50:12.577602 <8>[ 20.886861] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11198 11:50:12.577856 Received signal: <TESTSET> START panfrost_submit
11199 11:50:12.577926 Starting test_set panfrost_submit
11200 11:50:12.603953 <14>[ 20.913509] [IGT] panfrost_submit: executing
11201 11:50:12.610739 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.921273] [IGT] panfrost_submit: exiting, ret=77
11202 11:50:12.613997 rch64) (Linux: 6.1.62-cip9 aarch64)
11203 11:50:12.626982 Test requirement not met in function drm_open_driver, file <8>[ 20.934022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11204 11:50:12.627238 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11206 11:50:12.630314 ../lib/drmtest.c:621:
11207 11:50:12.630395 Test requirement: !(fd<0)
11208 11:50:12.637398 No known gpu found for chipset flags 0x32 (panfrost)
11209 11:50:12.640712 Last errno: 2, No such file or directory
11210 11:50:12.647003 [1mSubtest pa<14>[ 20.954727] [IGT] panfrost_submit: executing
11211 11:50:12.647085 n-submit: SKIP (0.000s)[0m
11212 11:50:12.654117 IGT<14>[ 20.962162] [IGT] panfrost_submit: exiting, ret=77
11213 11:50:12.667330 -Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)<8>[ 20.973610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11214 11:50:12.667415
11215 11:50:12.667651 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11217 11:50:12.673668 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11218 11:50:12.676894 Test requirement: !(fd<0)
11219 11:50:12.680635 No known gpu found for chipset flags 0x32 (panfrost)
11220 11:50:12.683662 Last errno: 2, No such file or directory
11221 11:50:12.693238 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)<14>[ 21.003137] [IGT] panfrost_submit: executing
11222 11:50:12.693320 [0m
11223 11:50:12.703495 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 21.011491] [IGT] panfrost_submit: exiting, ret=77
11224 11:50:12.706595 rch64) (Linux: 6.1.62-cip9 aarch64)
11225 11:50:12.719741 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c<8>[ 21.026227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11226 11:50:12.719825 :621:
11227 11:50:12.720063 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11229 11:50:12.722912 Test requirement: !(fd<0)
11230 11:50:12.729680 No known gpu found for chipset flags 0x32 (panfrost)
11231 11:50:12.732851 Last errno: 2, No such file or directory
11232 11:50:12.736235 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11233 11:50:12.742906 <14>[ 21.050591] [IGT] panfrost_submit: executing
11234 11:50:12.749615 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 21.058280] [IGT] panfrost_submit: exiting, ret=77
11235 11:50:12.753043 rch64) (Linux: 6.1.62-cip9 aarch64)
11236 11:50:12.766391 Test requirement not met in function drm_op<8>[ 21.071024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11237 11:50:12.766648 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11239 11:50:12.769410 en_driver, file ../lib/drmtest.c:621:
11240 11:50:12.772688 Test requirement: !(fd<0)
11241 11:50:12.775878 No known gpu found for chipset flags 0x32 (panfrost)
11242 11:50:12.779208 Last errno: 2, No such file or directory
11243 11:50:12.785785 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11244 11:50:12.792463 <14>[ 21.101706] [IGT] panfrost_submit: executing
11245 11:50:12.802355 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.109383] [IGT] panfrost_submit: exiting, ret=77
11246 11:50:12.802438 .1.62-cip9 aarch64)
11247 11:50:12.809125 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11248 11:50:12.818896 Test requ<8>[ 21.125188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11249 11:50:12.819153 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11251 11:50:12.821891 irement: !(fd<0)
11252 11:50:12.825514 No known gpu found for chipset flags 0x32 (panfrost)
11253 11:50:12.828868 Last errno: 2, No such file or directory
11254 11:50:12.838333 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[<14>[ 21.148991] [IGT] panfrost_submit: executing
11255 11:50:12.838415 0m
11256 11:50:12.848315 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 21.156419] [IGT] panfrost_submit: exiting, ret=77
11257 11:50:12.851975 rch64) (Linux: 6.1.62-cip9 aarch64)
11258 11:50:12.861764 Test requirement not met in function drm_op<8>[ 21.169003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11259 11:50:12.862020 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11261 11:50:12.868454 en_driver, file ../lib/drmtest.c:621:
11262 11:50:12.868535 Test requirement: !(fd<0)
11263 11:50:12.874958 No known gpu found for chipset flags 0x32 (panfrost)
11264 11:50:12.878533 Last errno: 2, No such file or directory
11265 11:50:12.881879 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11266 11:50:12.889889 <14>[ 21.199398] [IGT] panfrost_submit: executing
11267 11:50:12.899937 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.207312] [IGT] panfrost_submit: exiting, ret=77
11268 11:50:12.900020 .1.62-cip9 aarch64)
11269 11:50:12.910056 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11270 11:50:12.916110 Test requ<8>[ 21.223241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11271 11:50:12.916224 irement: !(fd<0)
11272 11:50:12.916465 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11274 11:50:12.922628 No known gpu found for chipset flags 0x32 (panfrost)
11275 11:50:12.926044 Last errno: 2, No such file or directory
11276 11:50:12.929442 [1mSubtest pan-reset: SKIP (0.000s)[0m
11277 11:50:12.936237 <14>[ 21.245713] [IGT] panfrost_submit: executing
11278 11:50:12.942737 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 21.252573] [IGT] panfrost_submit: exiting, ret=77
11279 11:50:12.946182 rch64) (Linux: 6.1.62-cip9 aarch64)
11280 11:50:12.959596 Test requirement not met in function drm_op<8>[ 21.264740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11281 11:50:12.959854 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11283 11:50:12.962606 en_driver, file ../lib/drmtest.c:621:
11284 11:50:12.966052 Test requirement: !(fd<0)
11285 11:50:12.969239 No known gpu found for chipset flags 0x32 (panfrost)
11286 11:50:12.972641 Last errno: 2, No such file or directory
11287 11:50:12.979406 [1mSubtest pa<14>[ 21.288262] [IGT] panfrost_submit: executing
11288 11:50:12.985954 n-submit-and-close: SKIP (0.000s<14>[ 21.295232] [IGT] panfrost_submit: exiting, ret=77
11289 11:50:12.986036 )[0m
11290 11:50:12.992265 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11291 11:50:13.002306 Test requirement not<8>[ 21.308449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11292 11:50:13.002559 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11294 11:50:13.009091 met in function drm_open_driver<8>[ 21.319133] <LAVA_SIGNAL_TESTSET STOP>
11295 11:50:13.009342 Received signal: <TESTSET> STOP
11296 11:50:13.009408 Closing test_set panfrost_submit
11297 11:50:13.018824 , file ../lib/dr<8>[ 21.324921] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12074030_1.5.2.3.1>
11298 11:50:13.018905 mtest.c:621:
11299 11:50:13.019135 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12074030_1.5.2.3.1
11300 11:50:13.019213 Ending use of test pattern.
11301 11:50:13.019270 Ending test lava.0_igt-gpu-panfrost (12074030_1.5.2.3.1), duration 0.90
11303 11:50:13.022110 Test requirement: !(fd<0)
11304 11:50:13.025997 No known gpu found for chipset flags 0x32 (panfrost)
11305 11:50:13.028715 Last errno: 2, No such file or directory
11306 11:50:13.035696 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11307 11:50:13.035776 + set +x
11308 11:50:13.038520 <LAVA_TEST_RUNNER EXIT>
11309 11:50:13.038771 ok: lava_test_shell seems to have completed
11310 11:50:13.039075 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11311 11:50:13.039176 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11312 11:50:13.039262 end: 3 lava-test-retry (duration 00:00:01) [common]
11313 11:50:13.039348 start: 4 finalize (timeout 00:07:10) [common]
11314 11:50:13.039435 start: 4.1 power-off (timeout 00:00:30) [common]
11315 11:50:13.039585 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11316 11:50:13.115957 >> Command sent successfully.
11317 11:50:13.118444 Returned 0 in 0 seconds
11318 11:50:13.218857 end: 4.1 power-off (duration 00:00:00) [common]
11320 11:50:13.219167 start: 4.2 read-feedback (timeout 00:07:10) [common]
11321 11:50:13.219433 Listened to connection for namespace 'common' for up to 1s
11322 11:50:14.220335 Finalising connection for namespace 'common'
11323 11:50:14.220491 Disconnecting from shell: Finalise
11324 11:50:14.220566 / #
11325 11:50:14.320894 end: 4.2 read-feedback (duration 00:00:01) [common]
11326 11:50:14.321049 end: 4 finalize (duration 00:00:01) [common]
11327 11:50:14.321166 Cleaning after the job
11328 11:50:14.321263 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/ramdisk
11329 11:50:14.329085 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/kernel
11330 11:50:14.337322 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/dtb
11331 11:50:14.337492 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074030/tftp-deploy-k89iqby6/modules
11332 11:50:14.344728 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074030
11333 11:50:14.459836 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074030
11334 11:50:14.460001 Job finished correctly