Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 37
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 11:48:30.223572 lava-dispatcher, installed at version: 2023.10
2 11:48:30.223772 start: 0 validate
3 11:48:30.223896 Start time: 2023-11-24 11:48:30.223889+00:00 (UTC)
4 11:48:30.224012 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:48:30.224142 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:48:30.483841 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:48:30.484518 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:48:30.753760 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:48:30.754549 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:48:31.023361 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:48:31.024048 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:48:31.292740 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:48:31.293452 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:48:31.569229 validate duration: 1.35
16 11:48:31.569485 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:48:31.569585 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:48:31.569677 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:48:31.569801 Not decompressing ramdisk as can be used compressed.
20 11:48:31.569885 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/initrd.cpio.gz
21 11:48:31.569950 saving as /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/ramdisk/initrd.cpio.gz
22 11:48:31.570015 total size: 5625687 (5 MB)
23 11:48:31.571124 progress 0 % (0 MB)
24 11:48:31.572672 progress 5 % (0 MB)
25 11:48:31.574197 progress 10 % (0 MB)
26 11:48:31.575601 progress 15 % (0 MB)
27 11:48:31.577167 progress 20 % (1 MB)
28 11:48:31.578590 progress 25 % (1 MB)
29 11:48:31.580111 progress 30 % (1 MB)
30 11:48:31.581689 progress 35 % (1 MB)
31 11:48:31.583126 progress 40 % (2 MB)
32 11:48:31.584713 progress 45 % (2 MB)
33 11:48:31.586056 progress 50 % (2 MB)
34 11:48:31.587616 progress 55 % (2 MB)
35 11:48:31.589137 progress 60 % (3 MB)
36 11:48:31.590544 progress 65 % (3 MB)
37 11:48:31.592040 progress 70 % (3 MB)
38 11:48:31.593406 progress 75 % (4 MB)
39 11:48:31.594958 progress 80 % (4 MB)
40 11:48:31.596292 progress 85 % (4 MB)
41 11:48:31.597782 progress 90 % (4 MB)
42 11:48:31.599354 progress 95 % (5 MB)
43 11:48:31.600783 progress 100 % (5 MB)
44 11:48:31.600976 5 MB downloaded in 0.03 s (173.29 MB/s)
45 11:48:31.601128 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:48:31.601366 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:48:31.601456 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:48:31.601539 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:48:31.601666 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:48:31.601740 saving as /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/kernel/Image
52 11:48:31.601801 total size: 49107456 (46 MB)
53 11:48:31.601863 No compression specified
54 11:48:31.603006 progress 0 % (0 MB)
55 11:48:31.615084 progress 5 % (2 MB)
56 11:48:31.627105 progress 10 % (4 MB)
57 11:48:31.639321 progress 15 % (7 MB)
58 11:48:31.651346 progress 20 % (9 MB)
59 11:48:31.663456 progress 25 % (11 MB)
60 11:48:31.675732 progress 30 % (14 MB)
61 11:48:31.688115 progress 35 % (16 MB)
62 11:48:31.700516 progress 40 % (18 MB)
63 11:48:31.712642 progress 45 % (21 MB)
64 11:48:31.724701 progress 50 % (23 MB)
65 11:48:31.736735 progress 55 % (25 MB)
66 11:48:31.748728 progress 60 % (28 MB)
67 11:48:31.760697 progress 65 % (30 MB)
68 11:48:31.772792 progress 70 % (32 MB)
69 11:48:31.784993 progress 75 % (35 MB)
70 11:48:31.797314 progress 80 % (37 MB)
71 11:48:31.809662 progress 85 % (39 MB)
72 11:48:31.821624 progress 90 % (42 MB)
73 11:48:31.833505 progress 95 % (44 MB)
74 11:48:31.845307 progress 100 % (46 MB)
75 11:48:31.845503 46 MB downloaded in 0.24 s (192.17 MB/s)
76 11:48:31.845652 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:48:31.845885 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:48:31.845972 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:48:31.846059 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:48:31.846192 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:48:31.846262 saving as /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/dtb/mt8192-asurada-spherion-r0.dtb
83 11:48:31.846325 total size: 47278 (0 MB)
84 11:48:31.846392 No compression specified
85 11:48:31.847503 progress 69 % (0 MB)
86 11:48:31.847769 progress 100 % (0 MB)
87 11:48:31.847923 0 MB downloaded in 0.00 s (28.25 MB/s)
88 11:48:31.848045 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:48:31.848265 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:48:31.848352 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:48:31.848434 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:48:31.848544 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 11:48:31.848611 saving as /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/nfsrootfs/full.rootfs.tar
95 11:48:31.848675 total size: 195204440 (186 MB)
96 11:48:31.848737 Using unxz to decompress xz
97 11:48:31.852060 progress 0 % (0 MB)
98 11:48:32.392204 progress 5 % (9 MB)
99 11:48:32.876535 progress 10 % (18 MB)
100 11:48:33.442871 progress 15 % (27 MB)
101 11:48:33.716938 progress 20 % (37 MB)
102 11:48:34.159002 progress 25 % (46 MB)
103 11:48:34.721957 progress 30 % (55 MB)
104 11:48:35.261695 progress 35 % (65 MB)
105 11:48:35.826819 progress 40 % (74 MB)
106 11:48:36.397339 progress 45 % (83 MB)
107 11:48:37.008045 progress 50 % (93 MB)
108 11:48:37.619387 progress 55 % (102 MB)
109 11:48:38.260493 progress 60 % (111 MB)
110 11:48:38.632409 progress 65 % (121 MB)
111 11:48:38.713691 progress 70 % (130 MB)
112 11:48:38.852864 progress 75 % (139 MB)
113 11:48:38.932262 progress 80 % (148 MB)
114 11:48:38.976907 progress 85 % (158 MB)
115 11:48:39.066689 progress 90 % (167 MB)
116 11:48:39.428132 progress 95 % (176 MB)
117 11:48:40.002125 progress 100 % (186 MB)
118 11:48:40.007207 186 MB downloaded in 8.16 s (22.82 MB/s)
119 11:48:40.007459 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:48:40.007724 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:48:40.007817 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:48:40.007905 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:48:40.008056 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:48:40.008131 saving as /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/modules/modules.tar
126 11:48:40.008196 total size: 8624756 (8 MB)
127 11:48:40.008262 Using unxz to decompress xz
128 11:48:40.012290 progress 0 % (0 MB)
129 11:48:40.033974 progress 5 % (0 MB)
130 11:48:40.057734 progress 10 % (0 MB)
131 11:48:40.081283 progress 15 % (1 MB)
132 11:48:40.105083 progress 20 % (1 MB)
133 11:48:40.129849 progress 25 % (2 MB)
134 11:48:40.155418 progress 30 % (2 MB)
135 11:48:40.181459 progress 35 % (2 MB)
136 11:48:40.204999 progress 40 % (3 MB)
137 11:48:40.229554 progress 45 % (3 MB)
138 11:48:40.254939 progress 50 % (4 MB)
139 11:48:40.279221 progress 55 % (4 MB)
140 11:48:40.305582 progress 60 % (4 MB)
141 11:48:40.334394 progress 65 % (5 MB)
142 11:48:40.360401 progress 70 % (5 MB)
143 11:48:40.385316 progress 75 % (6 MB)
144 11:48:40.414723 progress 80 % (6 MB)
145 11:48:40.441786 progress 85 % (7 MB)
146 11:48:40.468063 progress 90 % (7 MB)
147 11:48:40.501671 progress 95 % (7 MB)
148 11:48:40.531899 progress 100 % (8 MB)
149 11:48:40.537218 8 MB downloaded in 0.53 s (15.55 MB/s)
150 11:48:40.537474 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:48:40.537734 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:48:40.537827 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:48:40.537923 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:48:43.780079 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12074061/extract-nfsrootfs-mw13pg1y
156 11:48:43.780278 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:48:43.780386 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 11:48:43.780558 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8
159 11:48:43.780682 makedir: /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin
160 11:48:43.780782 makedir: /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/tests
161 11:48:43.780879 makedir: /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/results
162 11:48:43.780982 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-add-keys
163 11:48:43.781121 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-add-sources
164 11:48:43.781246 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-background-process-start
165 11:48:43.781371 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-background-process-stop
166 11:48:43.781495 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-common-functions
167 11:48:43.781616 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-echo-ipv4
168 11:48:43.781737 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-install-packages
169 11:48:43.781858 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-installed-packages
170 11:48:43.781977 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-os-build
171 11:48:43.782103 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-probe-channel
172 11:48:43.782224 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-probe-ip
173 11:48:43.782346 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-target-ip
174 11:48:43.782521 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-target-mac
175 11:48:43.782644 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-target-storage
176 11:48:43.782768 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-test-case
177 11:48:43.782893 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-test-event
178 11:48:43.783014 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-test-feedback
179 11:48:43.783135 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-test-raise
180 11:48:43.783255 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-test-reference
181 11:48:43.783376 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-test-runner
182 11:48:43.783499 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-test-set
183 11:48:43.783620 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-test-shell
184 11:48:43.783743 Updating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-add-keys (debian)
185 11:48:43.783890 Updating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-add-sources (debian)
186 11:48:43.784029 Updating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-install-packages (debian)
187 11:48:43.784164 Updating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-installed-packages (debian)
188 11:48:43.784298 Updating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/bin/lava-os-build (debian)
189 11:48:43.784416 Creating /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/environment
190 11:48:43.784514 LAVA metadata
191 11:48:43.784585 - LAVA_JOB_ID=12074061
192 11:48:43.784648 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:48:43.784750 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 11:48:43.784818 skipped lava-vland-overlay
195 11:48:43.784894 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:48:43.784974 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 11:48:43.785036 skipped lava-multinode-overlay
198 11:48:43.785111 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:48:43.785203 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 11:48:43.785277 Loading test definitions
201 11:48:43.785367 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 11:48:43.785439 Using /lava-12074061 at stage 0
203 11:48:43.785708 uuid=12074061_1.6.2.3.1 testdef=None
204 11:48:43.785801 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:48:43.785888 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 11:48:43.786329 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:48:43.786603 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 11:48:43.787181 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:48:43.787416 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 11:48:43.787948 runner path: /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/0/tests/0_timesync-off test_uuid 12074061_1.6.2.3.1
213 11:48:43.788101 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:48:43.788330 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 11:48:43.788404 Using /lava-12074061 at stage 0
217 11:48:43.788501 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:48:43.788580 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/0/tests/1_kselftest-alsa'
219 11:48:55.328076 Running '/usr/bin/git checkout kernelci.org
220 11:48:55.470265 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 11:48:55.471009 uuid=12074061_1.6.2.3.5 testdef=None
222 11:48:55.471166 end: 1.6.2.3.5 git-repo-action (duration 00:00:12) [common]
224 11:48:55.471421 start: 1.6.2.3.6 test-overlay (timeout 00:09:36) [common]
225 11:48:55.472179 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:48:55.472417 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:36) [common]
228 11:48:55.473400 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:48:55.473640 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:36) [common]
231 11:48:55.474679 runner path: /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/0/tests/1_kselftest-alsa test_uuid 12074061_1.6.2.3.5
232 11:48:55.474776 BOARD='mt8192-asurada-spherion-r0'
233 11:48:55.474844 BRANCH='cip-gitlab'
234 11:48:55.474906 SKIPFILE='/dev/null'
235 11:48:55.474965 SKIP_INSTALL='True'
236 11:48:55.475022 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:48:55.475082 TST_CASENAME=''
238 11:48:55.475139 TST_CMDFILES='alsa'
239 11:48:55.475278 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:48:55.475487 Creating lava-test-runner.conf files
242 11:48:55.475554 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074061/lava-overlay-o0hi1lt8/lava-12074061/0 for stage 0
243 11:48:55.475646 - 0_timesync-off
244 11:48:55.475717 - 1_kselftest-alsa
245 11:48:55.475814 end: 1.6.2.3 test-definition (duration 00:00:12) [common]
246 11:48:55.475904 start: 1.6.2.4 compress-overlay (timeout 00:09:36) [common]
247 11:49:03.052468 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:49:03.052677 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:29) [common]
249 11:49:03.052775 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:49:03.052876 end: 1.6.2 lava-overlay (duration 00:00:19) [common]
251 11:49:03.052971 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:29) [common]
252 11:49:03.213938 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:49:03.214303 start: 1.6.4 extract-modules (timeout 00:09:28) [common]
254 11:49:03.214430 extracting modules file /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074061/extract-nfsrootfs-mw13pg1y
255 11:49:03.416058 extracting modules file /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074061/extract-overlay-ramdisk-dtexovdi/ramdisk
256 11:49:03.616586 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:49:03.616756 start: 1.6.5 apply-overlay-tftp (timeout 00:09:28) [common]
258 11:49:03.616854 [common] Applying overlay to NFS
259 11:49:03.616925 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074061/compress-overlay-58tq1vmr/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074061/extract-nfsrootfs-mw13pg1y
260 11:49:04.512838 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:49:04.513009 start: 1.6.6 configure-preseed-file (timeout 00:09:27) [common]
262 11:49:04.513112 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:49:04.513205 start: 1.6.7 compress-ramdisk (timeout 00:09:27) [common]
264 11:49:04.513292 Building ramdisk /var/lib/lava/dispatcher/tmp/12074061/extract-overlay-ramdisk-dtexovdi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074061/extract-overlay-ramdisk-dtexovdi/ramdisk
265 11:49:04.828079 >> 130520 blocks
266 11:49:06.844888 rename /var/lib/lava/dispatcher/tmp/12074061/extract-overlay-ramdisk-dtexovdi/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/ramdisk/ramdisk.cpio.gz
267 11:49:06.845307 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:49:06.845505 start: 1.6.8 prepare-kernel (timeout 00:09:25) [common]
269 11:49:06.845626 start: 1.6.8.1 prepare-fit (timeout 00:09:25) [common]
270 11:49:06.845758 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/kernel/Image'
271 11:49:19.011443 Returned 0 in 12 seconds
272 11:49:19.112357 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/kernel/image.itb
273 11:49:19.468567 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:49:19.468911 output: Created: Fri Nov 24 11:49:19 2023
275 11:49:19.468990 output: Image 0 (kernel-1)
276 11:49:19.469058 output: Description:
277 11:49:19.469122 output: Created: Fri Nov 24 11:49:19 2023
278 11:49:19.469182 output: Type: Kernel Image
279 11:49:19.469275 output: Compression: lzma compressed
280 11:49:19.469336 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
281 11:49:19.469392 output: Architecture: AArch64
282 11:49:19.469450 output: OS: Linux
283 11:49:19.469507 output: Load Address: 0x00000000
284 11:49:19.469561 output: Entry Point: 0x00000000
285 11:49:19.469615 output: Hash algo: crc32
286 11:49:19.469698 output: Hash value: 43cfb6ad
287 11:49:19.469753 output: Image 1 (fdt-1)
288 11:49:19.469806 output: Description: mt8192-asurada-spherion-r0
289 11:49:19.469859 output: Created: Fri Nov 24 11:49:19 2023
290 11:49:19.469912 output: Type: Flat Device Tree
291 11:49:19.469965 output: Compression: uncompressed
292 11:49:19.470018 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:49:19.470071 output: Architecture: AArch64
294 11:49:19.470145 output: Hash algo: crc32
295 11:49:19.470227 output: Hash value: cc4352de
296 11:49:19.470281 output: Image 2 (ramdisk-1)
297 11:49:19.470373 output: Description: unavailable
298 11:49:19.470473 output: Created: Fri Nov 24 11:49:19 2023
299 11:49:19.470546 output: Type: RAMDisk Image
300 11:49:19.470600 output: Compression: Unknown Compression
301 11:49:19.470654 output: Data Size: 18760003 Bytes = 18320.32 KiB = 17.89 MiB
302 11:49:19.470709 output: Architecture: AArch64
303 11:49:19.470762 output: OS: Linux
304 11:49:19.470815 output: Load Address: unavailable
305 11:49:19.470868 output: Entry Point: unavailable
306 11:49:19.470921 output: Hash algo: crc32
307 11:49:19.470973 output: Hash value: ad795e8d
308 11:49:19.471027 output: Default Configuration: 'conf-1'
309 11:49:19.471079 output: Configuration 0 (conf-1)
310 11:49:19.471132 output: Description: mt8192-asurada-spherion-r0
311 11:49:19.471185 output: Kernel: kernel-1
312 11:49:19.471238 output: Init Ramdisk: ramdisk-1
313 11:49:19.471291 output: FDT: fdt-1
314 11:49:19.471344 output: Loadables: kernel-1
315 11:49:19.471396 output:
316 11:49:19.471588 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 11:49:19.471684 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 11:49:19.471786 end: 1.6 prepare-tftp-overlay (duration 00:00:39) [common]
319 11:49:19.471882 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:12) [common]
320 11:49:19.471965 No LXC device requested
321 11:49:19.472042 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:49:19.472127 start: 1.8 deploy-device-env (timeout 00:09:12) [common]
323 11:49:19.472204 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:49:19.472270 Checking files for TFTP limit of 4294967296 bytes.
325 11:49:19.472744 end: 1 tftp-deploy (duration 00:00:48) [common]
326 11:49:19.472852 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:49:19.472948 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:49:19.473077 substitutions:
329 11:49:19.473147 - {DTB}: 12074061/tftp-deploy-vlhdt09n/dtb/mt8192-asurada-spherion-r0.dtb
330 11:49:19.473214 - {INITRD}: 12074061/tftp-deploy-vlhdt09n/ramdisk/ramdisk.cpio.gz
331 11:49:19.473314 - {KERNEL}: 12074061/tftp-deploy-vlhdt09n/kernel/Image
332 11:49:19.473371 - {LAVA_MAC}: None
333 11:49:19.473427 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12074061/extract-nfsrootfs-mw13pg1y
334 11:49:19.473483 - {NFS_SERVER_IP}: 192.168.201.1
335 11:49:19.473537 - {PRESEED_CONFIG}: None
336 11:49:19.473591 - {PRESEED_LOCAL}: None
337 11:49:19.473646 - {RAMDISK}: 12074061/tftp-deploy-vlhdt09n/ramdisk/ramdisk.cpio.gz
338 11:49:19.473700 - {ROOT_PART}: None
339 11:49:19.473755 - {ROOT}: None
340 11:49:19.473809 - {SERVER_IP}: 192.168.201.1
341 11:49:19.473862 - {TEE}: None
342 11:49:19.473916 Parsed boot commands:
343 11:49:19.473969 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:49:19.474141 Parsed boot commands: tftpboot 192.168.201.1 12074061/tftp-deploy-vlhdt09n/kernel/image.itb 12074061/tftp-deploy-vlhdt09n/kernel/cmdline
345 11:49:19.474228 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:49:19.474311 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:49:19.474428 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:49:19.474531 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:49:19.474606 Not connected, no need to disconnect.
350 11:49:19.474681 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:49:19.474761 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:49:19.474833 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 11:49:19.478065 Setting prompt string to ['lava-test: # ']
354 11:49:19.478396 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:49:19.478541 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:49:19.478636 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:49:19.478721 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:49:19.478905 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 11:49:24.621673 >> Command sent successfully.
360 11:49:24.632213 Returned 0 in 5 seconds
361 11:49:24.733446 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:49:24.735064 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:49:24.735634 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:49:24.736142 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:49:24.736531 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:49:24.736997 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:49:24.738283 [Enter `^Ec?' for help]
369 11:49:24.898935
370 11:49:24.899480
371 11:49:24.899916 F0: 102B 0000
372 11:49:24.900315
373 11:49:24.900677 F3: 1001 0000 [0200]
374 11:49:24.901894
375 11:49:24.902375 F3: 1001 0000
376 11:49:24.902827
377 11:49:24.903190 F7: 102D 0000
378 11:49:24.903536
379 11:49:24.905422 F1: 0000 0000
380 11:49:24.905904
381 11:49:24.906288 V0: 0000 0000 [0001]
382 11:49:24.906698
383 11:49:24.908537 00: 0007 8000
384 11:49:24.908994
385 11:49:24.909367 01: 0000 0000
386 11:49:24.909728
387 11:49:24.911991 BP: 0C00 0209 [0000]
388 11:49:24.912471
389 11:49:24.912851 G0: 1182 0000
390 11:49:24.913209
391 11:49:24.916493 EC: 0000 0021 [4000]
392 11:49:24.916976
393 11:49:24.917357 S7: 0000 0000 [0000]
394 11:49:24.917879
395 11:49:24.919411 CC: 0000 0000 [0001]
396 11:49:24.919890
397 11:49:24.920268 T0: 0000 0040 [010F]
398 11:49:24.920770
399 11:49:24.921137 Jump to BL
400 11:49:24.921511
401 11:49:24.946307
402 11:49:24.946859
403 11:49:24.947338
404 11:49:24.953672 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:49:24.957265 ARM64: Exception handlers installed.
406 11:49:24.960963 ARM64: Testing exception
407 11:49:24.963835 ARM64: Done test exception
408 11:49:24.970865 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:49:24.981040 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:49:24.987628 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:49:24.998422 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:49:25.004243 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:49:25.010972 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:49:25.022238 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:49:25.029477 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:49:25.049003 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:49:25.052576 WDT: Last reset was cold boot
418 11:49:25.055462 SPI1(PAD0) initialized at 2873684 Hz
419 11:49:25.058945 SPI5(PAD0) initialized at 992727 Hz
420 11:49:25.062204 VBOOT: Loading verstage.
421 11:49:25.068790 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:49:25.072118 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:49:25.075564 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:49:25.078536 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:49:25.086656 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:49:25.092849 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:49:25.103741 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 11:49:25.104229
429 11:49:25.104608
430 11:49:25.113750 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:49:25.117615 ARM64: Exception handlers installed.
432 11:49:25.120550 ARM64: Testing exception
433 11:49:25.121033 ARM64: Done test exception
434 11:49:25.127358 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:49:25.130363 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:49:25.144672 Probing TPM: . done!
437 11:49:25.145159 TPM ready after 0 ms
438 11:49:25.151701 Connected to device vid:did:rid of 1ae0:0028:00
439 11:49:25.158671 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 11:49:25.213181 Initialized TPM device CR50 revision 0
441 11:49:25.225382 tlcl_send_startup: Startup return code is 0
442 11:49:25.225893 TPM: setup succeeded
443 11:49:25.236480 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:49:25.245655 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:49:25.255444 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:49:25.264623 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:49:25.268307 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:49:25.279022 in-header: 03 07 00 00 08 00 00 00
449 11:49:25.282725 in-data: aa e4 47 04 13 02 00 00
450 11:49:25.286309 Chrome EC: UHEPI supported
451 11:49:25.293408 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:49:25.297062 in-header: 03 ad 00 00 08 00 00 00
453 11:49:25.301077 in-data: 00 20 20 08 00 00 00 00
454 11:49:25.301517 Phase 1
455 11:49:25.304745 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:49:25.311838 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:49:25.316045 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:49:25.319658 Recovery requested (1009000e)
459 11:49:25.328371 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:49:25.333782 tlcl_extend: response is 0
461 11:49:25.342795 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:49:25.348584 tlcl_extend: response is 0
463 11:49:25.355175 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:49:25.375735 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 11:49:25.382575 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:49:25.383195
467 11:49:25.383717
468 11:49:25.392742 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:49:25.396198 ARM64: Exception handlers installed.
470 11:49:25.396670 ARM64: Testing exception
471 11:49:25.399480 ARM64: Done test exception
472 11:49:25.418264 pmic_efuse_setting: Set efuses in 11 msecs
473 11:49:25.426237 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:49:25.429834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:49:25.433336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:49:25.440045 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:49:25.443342 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:49:25.450499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:49:25.453724 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:49:25.458145 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:49:25.465426 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:49:25.469225 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:49:25.472770 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:49:25.476839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:49:25.483957 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:49:25.487202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:49:25.493926 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:49:25.497232 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:49:25.504431 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:49:25.511930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:49:25.515669 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:49:25.522991 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:49:25.526614 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:49:25.533541 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:49:25.537620 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:49:25.543702 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:49:25.550805 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:49:25.553867 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:49:25.560568 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:49:25.564107 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:49:25.570754 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:49:25.574334 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:49:25.580791 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:49:25.584104 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:49:25.590641 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:49:25.594481 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:49:25.600702 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:49:25.604200 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:49:25.611456 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:49:25.614562 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:49:25.620808 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:49:25.624283 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:49:25.627518 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:49:25.632216 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:49:25.639124 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:49:25.641857 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:49:25.645577 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:49:25.652450 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:49:25.655347 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:49:25.659094 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:49:25.661925 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:49:25.669210 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:49:25.672001 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:49:25.675732 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:49:25.682940 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:49:25.690924 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:49:25.697931 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:49:25.705379 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:49:25.712860 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:49:25.716452 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:49:25.724106 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:49:25.727351 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:49:25.734361 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 11:49:25.737675 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:49:25.745226 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:49:25.748787 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:49:25.758332 [RTC]rtc_get_frequency_meter,154: input=15, output=772
538 11:49:25.767697 [RTC]rtc_get_frequency_meter,154: input=23, output=957
539 11:49:25.776545 [RTC]rtc_get_frequency_meter,154: input=19, output=866
540 11:49:25.786341 [RTC]rtc_get_frequency_meter,154: input=17, output=818
541 11:49:25.796829 [RTC]rtc_get_frequency_meter,154: input=16, output=795
542 11:49:25.800451 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 11:49:25.804425 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 11:49:25.808038 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 11:49:25.815769 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 11:49:25.818978 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 11:49:25.819543 ADC[4]: Raw value=902139 ID=7
548 11:49:25.822270 ADC[3]: Raw value=213179 ID=1
549 11:49:25.825563 RAM Code: 0x71
550 11:49:25.829151 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 11:49:25.835349 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 11:49:25.842263 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 11:49:25.849072 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 11:49:25.852178 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 11:49:25.855290 in-header: 03 07 00 00 08 00 00 00
556 11:49:25.859030 in-data: aa e4 47 04 13 02 00 00
557 11:49:25.862259 Chrome EC: UHEPI supported
558 11:49:25.868682 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 11:49:25.872002 in-header: 03 ed 00 00 08 00 00 00
560 11:49:25.875355 in-data: 80 20 60 08 00 00 00 00
561 11:49:25.878886 MRC: failed to locate region type 0.
562 11:49:25.885562 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 11:49:25.888964 DRAM-K: Running full calibration
564 11:49:25.895360 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 11:49:25.895804 header.status = 0x0
566 11:49:25.898550 header.version = 0x6 (expected: 0x6)
567 11:49:25.902582 header.size = 0xd00 (expected: 0xd00)
568 11:49:25.905320 header.flags = 0x0
569 11:49:25.908661 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 11:49:25.928123 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
571 11:49:25.934807 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 11:49:25.938320 dram_init: ddr_geometry: 2
573 11:49:25.938838 [EMI] MDL number = 2
574 11:49:25.942247 [EMI] Get MDL freq = 0
575 11:49:25.945207 dram_init: ddr_type: 0
576 11:49:25.945688 is_discrete_lpddr4: 1
577 11:49:25.948314 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 11:49:25.948794
579 11:49:25.949173
580 11:49:25.951947 [Bian_co] ETT version 0.0.0.1
581 11:49:25.958862 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 11:49:25.959452
583 11:49:25.962012 dramc_set_vcore_voltage set vcore to 650000
584 11:49:25.962641 Read voltage for 800, 4
585 11:49:25.965279 Vio18 = 0
586 11:49:25.965854 Vcore = 650000
587 11:49:25.966244 Vdram = 0
588 11:49:25.969018 Vddq = 0
589 11:49:25.969500 Vmddr = 0
590 11:49:25.971683 dram_init: config_dvfs: 1
591 11:49:25.975056 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 11:49:25.981569 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 11:49:25.985097 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 11:49:25.988333 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 11:49:25.991928 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 11:49:25.994985 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 11:49:25.999100 MEM_TYPE=3, freq_sel=18
598 11:49:26.002915 sv_algorithm_assistance_LP4_1600
599 11:49:26.006578 ============ PULL DRAM RESETB DOWN ============
600 11:49:26.010424 ========== PULL DRAM RESETB DOWN end =========
601 11:49:26.014015 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 11:49:26.017582 ===================================
603 11:49:26.021188 LPDDR4 DRAM CONFIGURATION
604 11:49:26.024893 ===================================
605 11:49:26.025377 EX_ROW_EN[0] = 0x0
606 11:49:26.028683 EX_ROW_EN[1] = 0x0
607 11:49:26.029209 LP4Y_EN = 0x0
608 11:49:26.032284 WORK_FSP = 0x0
609 11:49:26.032825 WL = 0x2
610 11:49:26.036271 RL = 0x2
611 11:49:26.037013 BL = 0x2
612 11:49:26.037482 RPST = 0x0
613 11:49:26.039892 RD_PRE = 0x0
614 11:49:26.040551 WR_PRE = 0x1
615 11:49:26.043436 WR_PST = 0x0
616 11:49:26.044007 DBI_WR = 0x0
617 11:49:26.046990 DBI_RD = 0x0
618 11:49:26.047465 OTF = 0x1
619 11:49:26.050505 ===================================
620 11:49:26.054788 ===================================
621 11:49:26.055414 ANA top config
622 11:49:26.057729 ===================================
623 11:49:26.062264 DLL_ASYNC_EN = 0
624 11:49:26.065431 ALL_SLAVE_EN = 1
625 11:49:26.065905 NEW_RANK_MODE = 1
626 11:49:26.068912 DLL_IDLE_MODE = 1
627 11:49:26.072722 LP45_APHY_COMB_EN = 1
628 11:49:26.073195 TX_ODT_DIS = 1
629 11:49:26.076862 NEW_8X_MODE = 1
630 11:49:26.080462 ===================================
631 11:49:26.084455 ===================================
632 11:49:26.088274 data_rate = 1600
633 11:49:26.088594 CKR = 1
634 11:49:26.091945 DQ_P2S_RATIO = 8
635 11:49:26.095259 ===================================
636 11:49:26.098901 CA_P2S_RATIO = 8
637 11:49:26.103331 DQ_CA_OPEN = 0
638 11:49:26.103664 DQ_SEMI_OPEN = 0
639 11:49:26.106234 CA_SEMI_OPEN = 0
640 11:49:26.109608 CA_FULL_RATE = 0
641 11:49:26.113418 DQ_CKDIV4_EN = 1
642 11:49:26.113665 CA_CKDIV4_EN = 1
643 11:49:26.117004 CA_PREDIV_EN = 0
644 11:49:26.120891 PH8_DLY = 0
645 11:49:26.124655 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 11:49:26.124984 DQ_AAMCK_DIV = 4
647 11:49:26.128293 CA_AAMCK_DIV = 4
648 11:49:26.132219 CA_ADMCK_DIV = 4
649 11:49:26.135990 DQ_TRACK_CA_EN = 0
650 11:49:26.136667 CA_PICK = 800
651 11:49:26.139778 CA_MCKIO = 800
652 11:49:26.143639 MCKIO_SEMI = 0
653 11:49:26.147183 PLL_FREQ = 3068
654 11:49:26.147705 DQ_UI_PI_RATIO = 32
655 11:49:26.151364 CA_UI_PI_RATIO = 0
656 11:49:26.154697 ===================================
657 11:49:26.158186 ===================================
658 11:49:26.161909 memory_type:LPDDR4
659 11:49:26.162542 GP_NUM : 10
660 11:49:26.165579 SRAM_EN : 1
661 11:49:26.166130 MD32_EN : 0
662 11:49:26.169472 ===================================
663 11:49:26.172813 [ANA_INIT] >>>>>>>>>>>>>>
664 11:49:26.176083 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 11:49:26.180100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 11:49:26.180681 ===================================
667 11:49:26.183849 data_rate = 1600,PCW = 0X7600
668 11:49:26.187302 ===================================
669 11:49:26.191316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 11:49:26.198489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 11:49:26.202486 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 11:49:26.205697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 11:49:26.209722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 11:49:26.213056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 11:49:26.216845 [ANA_INIT] flow start
676 11:49:26.217321 [ANA_INIT] PLL >>>>>>>>
677 11:49:26.220648 [ANA_INIT] PLL <<<<<<<<
678 11:49:26.225011 [ANA_INIT] MIDPI >>>>>>>>
679 11:49:26.225559 [ANA_INIT] MIDPI <<<<<<<<
680 11:49:26.228277 [ANA_INIT] DLL >>>>>>>>
681 11:49:26.228750 [ANA_INIT] flow end
682 11:49:26.231601 ============ LP4 DIFF to SE enter ============
683 11:49:26.239314 ============ LP4 DIFF to SE exit ============
684 11:49:26.239867 [ANA_INIT] <<<<<<<<<<<<<
685 11:49:26.243055 [Flow] Enable top DCM control >>>>>
686 11:49:26.246526 [Flow] Enable top DCM control <<<<<
687 11:49:26.250095 Enable DLL master slave shuffle
688 11:49:26.253929 ==============================================================
689 11:49:26.257762 Gating Mode config
690 11:49:26.261443 ==============================================================
691 11:49:26.265217 Config description:
692 11:49:26.271951 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 11:49:26.279570 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 11:49:26.286269 SELPH_MODE 0: By rank 1: By Phase
695 11:49:26.290544 ==============================================================
696 11:49:26.293750 GAT_TRACK_EN = 1
697 11:49:26.297440 RX_GATING_MODE = 2
698 11:49:26.301441 RX_GATING_TRACK_MODE = 2
699 11:49:26.301937 SELPH_MODE = 1
700 11:49:26.304807 PICG_EARLY_EN = 1
701 11:49:26.309032 VALID_LAT_VALUE = 1
702 11:49:26.312559 ==============================================================
703 11:49:26.316229 Enter into Gating configuration >>>>
704 11:49:26.319774 Exit from Gating configuration <<<<
705 11:49:26.323635 Enter into DVFS_PRE_config >>>>>
706 11:49:26.334719 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 11:49:26.338117 Exit from DVFS_PRE_config <<<<<
708 11:49:26.341039 Enter into PICG configuration >>>>
709 11:49:26.344772 Exit from PICG configuration <<<<
710 11:49:26.347623 [RX_INPUT] configuration >>>>>
711 11:49:26.350947 [RX_INPUT] configuration <<<<<
712 11:49:26.354577 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 11:49:26.361125 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 11:49:26.367965 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 11:49:26.371223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 11:49:26.377900 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 11:49:26.384805 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 11:49:26.387981 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 11:49:26.394761 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 11:49:26.397830 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 11:49:26.401539 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 11:49:26.405234 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 11:49:26.411534 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 11:49:26.412069 ===================================
725 11:49:26.415001 LPDDR4 DRAM CONFIGURATION
726 11:49:26.418700 ===================================
727 11:49:26.421735 EX_ROW_EN[0] = 0x0
728 11:49:26.422257 EX_ROW_EN[1] = 0x0
729 11:49:26.425324 LP4Y_EN = 0x0
730 11:49:26.425758 WORK_FSP = 0x0
731 11:49:26.428615 WL = 0x2
732 11:49:26.429051 RL = 0x2
733 11:49:26.431721 BL = 0x2
734 11:49:26.432160 RPST = 0x0
735 11:49:26.435177 RD_PRE = 0x0
736 11:49:26.435616 WR_PRE = 0x1
737 11:49:26.438358 WR_PST = 0x0
738 11:49:26.441846 DBI_WR = 0x0
739 11:49:26.442423 DBI_RD = 0x0
740 11:49:26.445431 OTF = 0x1
741 11:49:26.448670 ===================================
742 11:49:26.451927 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 11:49:26.455422 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 11:49:26.458454 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 11:49:26.461518 ===================================
746 11:49:26.464990 LPDDR4 DRAM CONFIGURATION
747 11:49:26.468519 ===================================
748 11:49:26.471751 EX_ROW_EN[0] = 0x10
749 11:49:26.472190 EX_ROW_EN[1] = 0x0
750 11:49:26.475118 LP4Y_EN = 0x0
751 11:49:26.475563 WORK_FSP = 0x0
752 11:49:26.478499 WL = 0x2
753 11:49:26.478939 RL = 0x2
754 11:49:26.481671 BL = 0x2
755 11:49:26.482119 RPST = 0x0
756 11:49:26.484983 RD_PRE = 0x0
757 11:49:26.485425 WR_PRE = 0x1
758 11:49:26.488700 WR_PST = 0x0
759 11:49:26.489138 DBI_WR = 0x0
760 11:49:26.491960 DBI_RD = 0x0
761 11:49:26.492401 OTF = 0x1
762 11:49:26.495080 ===================================
763 11:49:26.501608 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 11:49:26.506249 nWR fixed to 40
765 11:49:26.509585 [ModeRegInit_LP4] CH0 RK0
766 11:49:26.510101 [ModeRegInit_LP4] CH0 RK1
767 11:49:26.512976 [ModeRegInit_LP4] CH1 RK0
768 11:49:26.516374 [ModeRegInit_LP4] CH1 RK1
769 11:49:26.516955 match AC timing 13
770 11:49:26.523451 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 11:49:26.526754 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 11:49:26.530004 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 11:49:26.536685 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 11:49:26.540589 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 11:49:26.541045 [EMI DOE] emi_dcm 0
776 11:49:26.546634 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 11:49:26.547206 ==
778 11:49:26.550371 Dram Type= 6, Freq= 0, CH_0, rank 0
779 11:49:26.553038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 11:49:26.553621 ==
781 11:49:26.560191 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 11:49:26.563040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 11:49:26.574252 [CA 0] Center 38 (7~69) winsize 63
784 11:49:26.577170 [CA 1] Center 38 (7~69) winsize 63
785 11:49:26.580625 [CA 2] Center 35 (5~66) winsize 62
786 11:49:26.584036 [CA 3] Center 35 (5~66) winsize 62
787 11:49:26.587225 [CA 4] Center 35 (4~66) winsize 63
788 11:49:26.590468 [CA 5] Center 33 (3~64) winsize 62
789 11:49:26.590896
790 11:49:26.593821 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 11:49:26.594439
792 11:49:26.597662 [CATrainingPosCal] consider 1 rank data
793 11:49:26.600491 u2DelayCellTimex100 = 270/100 ps
794 11:49:26.603988 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 11:49:26.607648 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 11:49:26.614191 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 11:49:26.617194 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 11:49:26.620755 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
799 11:49:26.623852 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 11:49:26.624313
801 11:49:26.628018 CA PerBit enable=1, Macro0, CA PI delay=33
802 11:49:26.628557
803 11:49:26.630495 [CBTSetCACLKResult] CA Dly = 33
804 11:49:26.631013 CS Dly: 6 (0~37)
805 11:49:26.633802 ==
806 11:49:26.634433 Dram Type= 6, Freq= 0, CH_0, rank 1
807 11:49:26.640693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 11:49:26.641195 ==
809 11:49:26.644010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 11:49:26.650778 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 11:49:26.660431 [CA 0] Center 38 (7~69) winsize 63
812 11:49:26.663704 [CA 1] Center 38 (7~69) winsize 63
813 11:49:26.667616 [CA 2] Center 36 (5~67) winsize 63
814 11:49:26.670684 [CA 3] Center 35 (5~66) winsize 62
815 11:49:26.673726 [CA 4] Center 35 (4~66) winsize 63
816 11:49:26.676969 [CA 5] Center 34 (4~65) winsize 62
817 11:49:26.677404
818 11:49:26.680498 [CmdBusTrainingLP45] Vref(ca) range 1: 32
819 11:49:26.680951
820 11:49:26.683671 [CATrainingPosCal] consider 2 rank data
821 11:49:26.687110 u2DelayCellTimex100 = 270/100 ps
822 11:49:26.690579 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 11:49:26.694519 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 11:49:26.700596 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
825 11:49:26.704094 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 11:49:26.707336 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
827 11:49:26.710787 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 11:49:26.711337
829 11:49:26.714168 CA PerBit enable=1, Macro0, CA PI delay=34
830 11:49:26.714683
831 11:49:26.717336 [CBTSetCACLKResult] CA Dly = 34
832 11:49:26.717916 CS Dly: 6 (0~38)
833 11:49:26.718305
834 11:49:26.720823 ----->DramcWriteLeveling(PI) begin...
835 11:49:26.723956 ==
836 11:49:26.724544 Dram Type= 6, Freq= 0, CH_0, rank 0
837 11:49:26.730477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 11:49:26.731199 ==
839 11:49:26.733970 Write leveling (Byte 0): 34 => 34
840 11:49:26.737337 Write leveling (Byte 1): 29 => 29
841 11:49:26.737821 DramcWriteLeveling(PI) end<-----
842 11:49:26.740699
843 11:49:26.741183 ==
844 11:49:26.743972 Dram Type= 6, Freq= 0, CH_0, rank 0
845 11:49:26.747515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 11:49:26.747956 ==
847 11:49:26.751040 [Gating] SW mode calibration
848 11:49:26.758538 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 11:49:26.762883 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 11:49:26.765704 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 11:49:26.769896 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
852 11:49:26.776216 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
853 11:49:26.779755 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:49:26.783339 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:49:26.787078 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:49:26.793503 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:49:26.797021 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:49:26.800113 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:49:26.807251 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:49:26.810909 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:49:26.813582 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:49:26.820200 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:49:26.823613 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:49:26.826921 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:49:26.833568 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:49:26.836802 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:49:26.840314 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
868 11:49:26.846961 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
869 11:49:26.850523 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:49:26.853833 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:49:26.857175 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 11:49:26.863587 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:49:26.867287 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:49:26.870155 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:49:26.876914 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
876 11:49:26.880268 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
877 11:49:26.883561 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
878 11:49:26.890480 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 11:49:26.893974 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 11:49:26.897215 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 11:49:26.903766 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:49:26.907536 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
883 11:49:26.910176 0 10 4 | B1->B0 | 3434 2c2c | 1 1 | (1 0) (1 0)
884 11:49:26.917095 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
885 11:49:26.920879 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
886 11:49:26.923890 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 11:49:26.930572 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 11:49:26.933674 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 11:49:26.937142 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:49:26.940529 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:49:26.946956 0 11 4 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
892 11:49:26.950700 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
893 11:49:26.953945 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
894 11:49:26.960766 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 11:49:26.963841 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 11:49:26.967297 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 11:49:26.973787 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:49:26.977141 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:49:26.980579 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
900 11:49:26.987809 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 11:49:26.990473 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:49:26.993967 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:49:27.000832 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:49:27.003882 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:49:27.007644 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:49:27.014161 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:49:27.017634 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:49:27.020922 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:49:27.027330 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:49:27.030838 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:49:27.034175 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:49:27.037110 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:49:27.044138 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:49:27.047648 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:49:27.050717 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 11:49:27.057663 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
917 11:49:27.060741 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
918 11:49:27.064178 Total UI for P1: 0, mck2ui 16
919 11:49:27.067130 best dqsien dly found for B0: ( 0, 14, 6)
920 11:49:27.070676 Total UI for P1: 0, mck2ui 16
921 11:49:27.074366 best dqsien dly found for B1: ( 0, 14, 10)
922 11:49:27.077262 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
923 11:49:27.080846 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
924 11:49:27.081328
925 11:49:27.083920 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
926 11:49:27.087584 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
927 11:49:27.090917 [Gating] SW calibration Done
928 11:49:27.091464 ==
929 11:49:27.094134 Dram Type= 6, Freq= 0, CH_0, rank 0
930 11:49:27.097675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 11:49:27.098228 ==
932 11:49:27.100592 RX Vref Scan: 0
933 11:49:27.101102
934 11:49:27.104236 RX Vref 0 -> 0, step: 1
935 11:49:27.104683
936 11:49:27.107551 RX Delay -130 -> 252, step: 16
937 11:49:27.110554 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
938 11:49:27.114199 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 11:49:27.117412 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
940 11:49:27.120795 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
941 11:49:27.123913 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
942 11:49:27.131013 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
943 11:49:27.133958 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 11:49:27.137521 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 11:49:27.140840 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 11:49:27.147810 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
947 11:49:27.150837 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 11:49:27.154064 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 11:49:27.157355 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
950 11:49:27.160715 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 11:49:27.167724 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 11:49:27.171327 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
953 11:49:27.171905 ==
954 11:49:27.174106 Dram Type= 6, Freq= 0, CH_0, rank 0
955 11:49:27.177320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 11:49:27.177800 ==
957 11:49:27.178182 DQS Delay:
958 11:49:27.181189 DQS0 = 0, DQS1 = 0
959 11:49:27.181707 DQM Delay:
960 11:49:27.184213 DQM0 = 90, DQM1 = 79
961 11:49:27.184690 DQ Delay:
962 11:49:27.187662 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
963 11:49:27.190742 DQ4 =85, DQ5 =85, DQ6 =101, DQ7 =101
964 11:49:27.194001 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
965 11:49:27.197432 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =77
966 11:49:27.197998
967 11:49:27.198455
968 11:49:27.198826 ==
969 11:49:27.200839 Dram Type= 6, Freq= 0, CH_0, rank 0
970 11:49:27.204285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 11:49:27.207558 ==
972 11:49:27.208075
973 11:49:27.208451
974 11:49:27.208831 TX Vref Scan disable
975 11:49:27.210671 == TX Byte 0 ==
976 11:49:27.214298 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
977 11:49:27.217725 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
978 11:49:27.221266 == TX Byte 1 ==
979 11:49:27.224323 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
980 11:49:27.227693 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
981 11:49:27.230914 ==
982 11:49:27.231389 Dram Type= 6, Freq= 0, CH_0, rank 0
983 11:49:27.237618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 11:49:27.238191 ==
985 11:49:27.250433 TX Vref=22, minBit 8, minWin=26, winSum=437
986 11:49:27.253542 TX Vref=24, minBit 6, minWin=27, winSum=444
987 11:49:27.257369 TX Vref=26, minBit 8, minWin=27, winSum=447
988 11:49:27.260875 TX Vref=28, minBit 9, minWin=27, winSum=451
989 11:49:27.263883 TX Vref=30, minBit 12, minWin=27, winSum=450
990 11:49:27.270438 TX Vref=32, minBit 11, minWin=27, winSum=452
991 11:49:27.273679 [TxChooseVref] Worse bit 11, Min win 27, Win sum 452, Final Vref 32
992 11:49:27.274152
993 11:49:27.277041 Final TX Range 1 Vref 32
994 11:49:27.277515
995 11:49:27.277892 ==
996 11:49:27.280201 Dram Type= 6, Freq= 0, CH_0, rank 0
997 11:49:27.284047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 11:49:27.284523 ==
999 11:49:27.284895
1000 11:49:27.287004
1001 11:49:27.287475 TX Vref Scan disable
1002 11:49:27.290762 == TX Byte 0 ==
1003 11:49:27.293930 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1004 11:49:27.297306 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1005 11:49:27.300437 == TX Byte 1 ==
1006 11:49:27.303860 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1007 11:49:27.307109 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1008 11:49:27.310615
1009 11:49:27.311168 [DATLAT]
1010 11:49:27.311542 Freq=800, CH0 RK0
1011 11:49:27.311901
1012 11:49:27.313912 DATLAT Default: 0xa
1013 11:49:27.314762 0, 0xFFFF, sum = 0
1014 11:49:27.317435 1, 0xFFFF, sum = 0
1015 11:49:27.317935 2, 0xFFFF, sum = 0
1016 11:49:27.321343 3, 0xFFFF, sum = 0
1017 11:49:27.321861 4, 0xFFFF, sum = 0
1018 11:49:27.323784 5, 0xFFFF, sum = 0
1019 11:49:27.324338 6, 0xFFFF, sum = 0
1020 11:49:27.327404 7, 0xFFFF, sum = 0
1021 11:49:27.330635 8, 0xFFFF, sum = 0
1022 11:49:27.331159 9, 0x0, sum = 1
1023 11:49:27.331590 10, 0x0, sum = 2
1024 11:49:27.333795 11, 0x0, sum = 3
1025 11:49:27.334527 12, 0x0, sum = 4
1026 11:49:27.337284 best_step = 10
1027 11:49:27.337889
1028 11:49:27.338374 ==
1029 11:49:27.340436 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 11:49:27.343662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 11:49:27.343905 ==
1032 11:49:27.347057 RX Vref Scan: 1
1033 11:49:27.347309
1034 11:49:27.347516 Set Vref Range= 32 -> 127
1035 11:49:27.347658
1036 11:49:27.350235 RX Vref 32 -> 127, step: 1
1037 11:49:27.350511
1038 11:49:27.353486 RX Delay -79 -> 252, step: 8
1039 11:49:27.353725
1040 11:49:27.356769 Set Vref, RX VrefLevel [Byte0]: 32
1041 11:49:27.360259 [Byte1]: 32
1042 11:49:27.360394
1043 11:49:27.363864 Set Vref, RX VrefLevel [Byte0]: 33
1044 11:49:27.366941 [Byte1]: 33
1045 11:49:27.370155
1046 11:49:27.370314 Set Vref, RX VrefLevel [Byte0]: 34
1047 11:49:27.373542 [Byte1]: 34
1048 11:49:27.378121
1049 11:49:27.378227 Set Vref, RX VrefLevel [Byte0]: 35
1050 11:49:27.381396 [Byte1]: 35
1051 11:49:27.385394
1052 11:49:27.385499 Set Vref, RX VrefLevel [Byte0]: 36
1053 11:49:27.388846 [Byte1]: 36
1054 11:49:27.393043
1055 11:49:27.393171 Set Vref, RX VrefLevel [Byte0]: 37
1056 11:49:27.396296 [Byte1]: 37
1057 11:49:27.401139
1058 11:49:27.401257 Set Vref, RX VrefLevel [Byte0]: 38
1059 11:49:27.404401 [Byte1]: 38
1060 11:49:27.408385
1061 11:49:27.408764 Set Vref, RX VrefLevel [Byte0]: 39
1062 11:49:27.411727 [Byte1]: 39
1063 11:49:27.416247
1064 11:49:27.416711 Set Vref, RX VrefLevel [Byte0]: 40
1065 11:49:27.419188 [Byte1]: 40
1066 11:49:27.424062
1067 11:49:27.424482 Set Vref, RX VrefLevel [Byte0]: 41
1068 11:49:27.427152 [Byte1]: 41
1069 11:49:27.431664
1070 11:49:27.432215 Set Vref, RX VrefLevel [Byte0]: 42
1071 11:49:27.434806 [Byte1]: 42
1072 11:49:27.438901
1073 11:49:27.439381 Set Vref, RX VrefLevel [Byte0]: 43
1074 11:49:27.442211 [Byte1]: 43
1075 11:49:27.446989
1076 11:49:27.447492 Set Vref, RX VrefLevel [Byte0]: 44
1077 11:49:27.450468 [Byte1]: 44
1078 11:49:27.454063
1079 11:49:27.454595 Set Vref, RX VrefLevel [Byte0]: 45
1080 11:49:27.457415 [Byte1]: 45
1081 11:49:27.461480
1082 11:49:27.461905 Set Vref, RX VrefLevel [Byte0]: 46
1083 11:49:27.464609 [Byte1]: 46
1084 11:49:27.468998
1085 11:49:27.469428 Set Vref, RX VrefLevel [Byte0]: 47
1086 11:49:27.472826 [Byte1]: 47
1087 11:49:27.476324
1088 11:49:27.476754 Set Vref, RX VrefLevel [Byte0]: 48
1089 11:49:27.479621 [Byte1]: 48
1090 11:49:27.483891
1091 11:49:27.484421 Set Vref, RX VrefLevel [Byte0]: 49
1092 11:49:27.487181 [Byte1]: 49
1093 11:49:27.491370
1094 11:49:27.491834 Set Vref, RX VrefLevel [Byte0]: 50
1095 11:49:27.494831 [Byte1]: 50
1096 11:49:27.498916
1097 11:49:27.499369 Set Vref, RX VrefLevel [Byte0]: 51
1098 11:49:27.503215 [Byte1]: 51
1099 11:49:27.506561
1100 11:49:27.507051 Set Vref, RX VrefLevel [Byte0]: 52
1101 11:49:27.509920 [Byte1]: 52
1102 11:49:27.514215
1103 11:49:27.514735 Set Vref, RX VrefLevel [Byte0]: 53
1104 11:49:27.517197 [Byte1]: 53
1105 11:49:27.521552
1106 11:49:27.521970 Set Vref, RX VrefLevel [Byte0]: 54
1107 11:49:27.525002 [Byte1]: 54
1108 11:49:27.529447
1109 11:49:27.529893 Set Vref, RX VrefLevel [Byte0]: 55
1110 11:49:27.532846 [Byte1]: 55
1111 11:49:27.536645
1112 11:49:27.537069 Set Vref, RX VrefLevel [Byte0]: 56
1113 11:49:27.539842 [Byte1]: 56
1114 11:49:27.544597
1115 11:49:27.545068 Set Vref, RX VrefLevel [Byte0]: 57
1116 11:49:27.547702 [Byte1]: 57
1117 11:49:27.551751
1118 11:49:27.552196 Set Vref, RX VrefLevel [Byte0]: 58
1119 11:49:27.555013 [Byte1]: 58
1120 11:49:27.559592
1121 11:49:27.560013 Set Vref, RX VrefLevel [Byte0]: 59
1122 11:49:27.562696 [Byte1]: 59
1123 11:49:27.567183
1124 11:49:27.567605 Set Vref, RX VrefLevel [Byte0]: 60
1125 11:49:27.570186 [Byte1]: 60
1126 11:49:27.574432
1127 11:49:27.574870 Set Vref, RX VrefLevel [Byte0]: 61
1128 11:49:27.577550 [Byte1]: 61
1129 11:49:27.581961
1130 11:49:27.582380 Set Vref, RX VrefLevel [Byte0]: 62
1131 11:49:27.585256 [Byte1]: 62
1132 11:49:27.589482
1133 11:49:27.590079 Set Vref, RX VrefLevel [Byte0]: 63
1134 11:49:27.593123 [Byte1]: 63
1135 11:49:27.597154
1136 11:49:27.600499 Set Vref, RX VrefLevel [Byte0]: 64
1137 11:49:27.601062 [Byte1]: 64
1138 11:49:27.604674
1139 11:49:27.605241 Set Vref, RX VrefLevel [Byte0]: 65
1140 11:49:27.608172 [Byte1]: 65
1141 11:49:27.612270
1142 11:49:27.612690 Set Vref, RX VrefLevel [Byte0]: 66
1143 11:49:27.615724 [Byte1]: 66
1144 11:49:27.619932
1145 11:49:27.620372 Set Vref, RX VrefLevel [Byte0]: 67
1146 11:49:27.623144 [Byte1]: 67
1147 11:49:27.627007
1148 11:49:27.627607 Set Vref, RX VrefLevel [Byte0]: 68
1149 11:49:27.630493 [Byte1]: 68
1150 11:49:27.634715
1151 11:49:27.635285 Set Vref, RX VrefLevel [Byte0]: 69
1152 11:49:27.637936 [Byte1]: 69
1153 11:49:27.642535
1154 11:49:27.643123 Set Vref, RX VrefLevel [Byte0]: 70
1155 11:49:27.645442 [Byte1]: 70
1156 11:49:27.649687
1157 11:49:27.650268 Set Vref, RX VrefLevel [Byte0]: 71
1158 11:49:27.652923 [Byte1]: 71
1159 11:49:27.657433
1160 11:49:27.657851 Set Vref, RX VrefLevel [Byte0]: 72
1161 11:49:27.660741 [Byte1]: 72
1162 11:49:27.664828
1163 11:49:27.665421 Set Vref, RX VrefLevel [Byte0]: 73
1164 11:49:27.668199 [Byte1]: 73
1165 11:49:27.672286
1166 11:49:27.672811 Set Vref, RX VrefLevel [Byte0]: 74
1167 11:49:27.675898 [Byte1]: 74
1168 11:49:27.679990
1169 11:49:27.680595 Set Vref, RX VrefLevel [Byte0]: 75
1170 11:49:27.683049 [Byte1]: 75
1171 11:49:27.687283
1172 11:49:27.687392 Set Vref, RX VrefLevel [Byte0]: 76
1173 11:49:27.690394 [Byte1]: 76
1174 11:49:27.695113
1175 11:49:27.695702 Set Vref, RX VrefLevel [Byte0]: 77
1176 11:49:27.698352 [Byte1]: 77
1177 11:49:27.702508
1178 11:49:27.703096 Set Vref, RX VrefLevel [Byte0]: 78
1179 11:49:27.706295 [Byte1]: 78
1180 11:49:27.710278
1181 11:49:27.710755 Final RX Vref Byte 0 = 61 to rank0
1182 11:49:27.713878 Final RX Vref Byte 1 = 57 to rank0
1183 11:49:27.716747 Final RX Vref Byte 0 = 61 to rank1
1184 11:49:27.720494 Final RX Vref Byte 1 = 57 to rank1==
1185 11:49:27.723503 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 11:49:27.730230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 11:49:27.730740 ==
1188 11:49:27.731080 DQS Delay:
1189 11:49:27.731391 DQS0 = 0, DQS1 = 0
1190 11:49:27.733658 DQM Delay:
1191 11:49:27.734078 DQM0 = 93, DQM1 = 83
1192 11:49:27.736820 DQ Delay:
1193 11:49:27.740568 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1194 11:49:27.744051 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1195 11:49:27.744494 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1196 11:49:27.750459 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1197 11:49:27.750899
1198 11:49:27.751236
1199 11:49:27.756813 [DQSOSCAuto] RK0, (LSB)MR18= 0x3833, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1200 11:49:27.760548 CH0 RK0: MR19=606, MR18=3833
1201 11:49:27.766807 CH0_RK0: MR19=0x606, MR18=0x3833, DQSOSC=395, MR23=63, INC=94, DEC=63
1202 11:49:27.767249
1203 11:49:27.770364 ----->DramcWriteLeveling(PI) begin...
1204 11:49:27.770822 ==
1205 11:49:27.773957 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 11:49:27.776854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 11:49:27.777354 ==
1208 11:49:27.780246 Write leveling (Byte 0): 31 => 31
1209 11:49:27.783783 Write leveling (Byte 1): 30 => 30
1210 11:49:27.786302 DramcWriteLeveling(PI) end<-----
1211 11:49:27.786417
1212 11:49:27.786485 ==
1213 11:49:27.789900 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 11:49:27.793405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 11:49:27.793567 ==
1216 11:49:27.796821 [Gating] SW mode calibration
1217 11:49:27.803834 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 11:49:27.810427 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 11:49:27.813634 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 11:49:27.816846 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1221 11:49:27.823434 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:49:27.867070 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:49:27.867614 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:49:27.867699 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:49:27.868158 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:49:27.868425 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:49:27.868694 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:49:27.868778 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:49:27.868870 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:49:27.868969 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:49:27.869058 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:49:27.898136 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:49:27.898964 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:49:27.899391 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:49:27.899759 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1236 11:49:27.900101 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1237 11:49:27.900431 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:49:27.902494 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:49:27.902963 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:49:27.905392 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:49:27.908830 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:49:27.915618 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:49:27.918878 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:49:27.922362 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:49:27.928800 0 9 8 | B1->B0 | 2e2e 3333 | 0 1 | (0 0) (1 1)
1246 11:49:27.932158 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 11:49:27.935588 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:49:27.942247 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:49:27.945533 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 11:49:27.949033 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 11:49:27.955537 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 11:49:27.959170 0 10 4 | B1->B0 | 3232 3030 | 1 1 | (1 1) (0 1)
1253 11:49:27.962588 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1254 11:49:27.968838 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:49:27.972856 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:49:27.975515 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:49:27.982559 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:49:27.985608 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:49:27.988976 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:49:27.995674 0 11 4 | B1->B0 | 2929 3636 | 0 0 | (0 0) (0 0)
1261 11:49:27.998828 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1262 11:49:28.002276 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:49:28.005945 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:49:28.013462 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:49:28.016953 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:49:28.020628 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:49:28.024051 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:49:28.030469 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 11:49:28.034133 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:49:28.037912 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:49:28.041107 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:49:28.047780 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:49:28.051284 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:49:28.054897 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:49:28.061706 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:49:28.064986 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:49:28.068292 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:49:28.075148 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:49:28.077954 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:49:28.081346 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:49:28.084614 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:49:28.091887 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:49:28.094927 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:49:28.098530 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1285 11:49:28.101944 Total UI for P1: 0, mck2ui 16
1286 11:49:28.105023 best dqsien dly found for B1: ( 0, 14, 2)
1287 11:49:28.111948 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1288 11:49:28.112547 Total UI for P1: 0, mck2ui 16
1289 11:49:28.118528 best dqsien dly found for B0: ( 0, 14, 4)
1290 11:49:28.121843 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1291 11:49:28.124926 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1292 11:49:28.125390
1293 11:49:28.128620 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1294 11:49:28.131846 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1295 11:49:28.134935 [Gating] SW calibration Done
1296 11:49:28.135412 ==
1297 11:49:28.138144 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 11:49:28.141568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 11:49:28.142037 ==
1300 11:49:28.145333 RX Vref Scan: 0
1301 11:49:28.145799
1302 11:49:28.146172 RX Vref 0 -> 0, step: 1
1303 11:49:28.146581
1304 11:49:28.148456 RX Delay -130 -> 252, step: 16
1305 11:49:28.151763 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1306 11:49:28.158684 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1307 11:49:28.162236 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1308 11:49:28.165152 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1309 11:49:28.168586 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1310 11:49:28.172089 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1311 11:49:28.175003 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1312 11:49:28.181733 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1313 11:49:28.185376 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1314 11:49:28.188537 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1315 11:49:28.191733 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1316 11:49:28.195318 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1317 11:49:28.201626 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1318 11:49:28.205166 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1319 11:49:28.208703 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1320 11:49:28.212020 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1321 11:49:28.212490 ==
1322 11:49:28.215138 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 11:49:28.222205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 11:49:28.222769 ==
1325 11:49:28.223150 DQS Delay:
1326 11:49:28.225137 DQS0 = 0, DQS1 = 0
1327 11:49:28.225634 DQM Delay:
1328 11:49:28.226005 DQM0 = 90, DQM1 = 80
1329 11:49:28.228598 DQ Delay:
1330 11:49:28.231912 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1331 11:49:28.235303 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
1332 11:49:28.238584 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1333 11:49:28.241813 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1334 11:49:28.242466
1335 11:49:28.242869
1336 11:49:28.243232 ==
1337 11:49:28.245189 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 11:49:28.248959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 11:49:28.249585 ==
1340 11:49:28.250140
1341 11:49:28.250686
1342 11:49:28.252120 TX Vref Scan disable
1343 11:49:28.252604 == TX Byte 0 ==
1344 11:49:28.258309 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1345 11:49:28.262210 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1346 11:49:28.262791 == TX Byte 1 ==
1347 11:49:28.268675 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1348 11:49:28.272026 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1349 11:49:28.272509 ==
1350 11:49:28.275000 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 11:49:28.278540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 11:49:28.279114 ==
1353 11:49:28.292366 TX Vref=22, minBit 8, minWin=27, winSum=446
1354 11:49:28.296086 TX Vref=24, minBit 1, minWin=27, winSum=446
1355 11:49:28.299202 TX Vref=26, minBit 3, minWin=27, winSum=449
1356 11:49:28.302701 TX Vref=28, minBit 8, minWin=27, winSum=454
1357 11:49:28.305991 TX Vref=30, minBit 6, minWin=28, winSum=459
1358 11:49:28.312211 TX Vref=32, minBit 14, minWin=27, winSum=456
1359 11:49:28.316189 [TxChooseVref] Worse bit 6, Min win 28, Win sum 459, Final Vref 30
1360 11:49:28.316601
1361 11:49:28.318817 Final TX Range 1 Vref 30
1362 11:49:28.319229
1363 11:49:28.319552 ==
1364 11:49:28.322676 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 11:49:28.325998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 11:49:28.326467 ==
1367 11:49:28.326801
1368 11:49:28.329121
1369 11:49:28.329528 TX Vref Scan disable
1370 11:49:28.332581 == TX Byte 0 ==
1371 11:49:28.335642 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1372 11:49:28.339279 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1373 11:49:28.342251 == TX Byte 1 ==
1374 11:49:28.345571 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1375 11:49:28.348955 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1376 11:49:28.352404
1377 11:49:28.352483 [DATLAT]
1378 11:49:28.352546 Freq=800, CH0 RK1
1379 11:49:28.352606
1380 11:49:28.355557 DATLAT Default: 0xa
1381 11:49:28.355636 0, 0xFFFF, sum = 0
1382 11:49:28.359449 1, 0xFFFF, sum = 0
1383 11:49:28.359530 2, 0xFFFF, sum = 0
1384 11:49:28.362320 3, 0xFFFF, sum = 0
1385 11:49:28.362436 4, 0xFFFF, sum = 0
1386 11:49:28.365757 5, 0xFFFF, sum = 0
1387 11:49:28.365839 6, 0xFFFF, sum = 0
1388 11:49:28.369203 7, 0xFFFF, sum = 0
1389 11:49:28.369285 8, 0xFFFF, sum = 0
1390 11:49:28.372507 9, 0x0, sum = 1
1391 11:49:28.372590 10, 0x0, sum = 2
1392 11:49:28.375551 11, 0x0, sum = 3
1393 11:49:28.375632 12, 0x0, sum = 4
1394 11:49:28.378802 best_step = 10
1395 11:49:28.378885
1396 11:49:28.378949 ==
1397 11:49:28.382164 Dram Type= 6, Freq= 0, CH_0, rank 1
1398 11:49:28.385560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 11:49:28.385641 ==
1400 11:49:28.389181 RX Vref Scan: 0
1401 11:49:28.389260
1402 11:49:28.389323 RX Vref 0 -> 0, step: 1
1403 11:49:28.389383
1404 11:49:28.392208 RX Delay -95 -> 252, step: 8
1405 11:49:28.398927 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1406 11:49:28.402347 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1407 11:49:28.405533 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1408 11:49:28.409127 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1409 11:49:28.412312 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1410 11:49:28.418914 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1411 11:49:28.422251 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1412 11:49:28.425854 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1413 11:49:28.429406 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1414 11:49:28.432583 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1415 11:49:28.435939 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1416 11:49:28.442532 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1417 11:49:28.445997 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1418 11:49:28.449337 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1419 11:49:28.452648 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1420 11:49:28.459313 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1421 11:49:28.459394 ==
1422 11:49:28.462414 Dram Type= 6, Freq= 0, CH_0, rank 1
1423 11:49:28.465972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 11:49:28.466052 ==
1425 11:49:28.466115 DQS Delay:
1426 11:49:28.469171 DQS0 = 0, DQS1 = 0
1427 11:49:28.469251 DQM Delay:
1428 11:49:28.472426 DQM0 = 90, DQM1 = 82
1429 11:49:28.472506 DQ Delay:
1430 11:49:28.475845 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1431 11:49:28.479195 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1432 11:49:28.482761 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =80
1433 11:49:28.485949 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1434 11:49:28.486031
1435 11:49:28.486096
1436 11:49:28.492698 [DQSOSCAuto] RK1, (LSB)MR18= 0x431e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1437 11:49:28.495898 CH0 RK1: MR19=606, MR18=431E
1438 11:49:28.502562 CH0_RK1: MR19=0x606, MR18=0x431E, DQSOSC=393, MR23=63, INC=95, DEC=63
1439 11:49:28.506224 [RxdqsGatingPostProcess] freq 800
1440 11:49:28.512849 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1441 11:49:28.512931 Pre-setting of DQS Precalculation
1442 11:49:28.519377 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1443 11:49:28.519460 ==
1444 11:49:28.522922 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 11:49:28.525934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 11:49:28.526017 ==
1447 11:49:28.532671 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1448 11:49:28.539668 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1449 11:49:28.547208 [CA 0] Center 36 (6~67) winsize 62
1450 11:49:28.550407 [CA 1] Center 36 (6~67) winsize 62
1451 11:49:28.553768 [CA 2] Center 34 (4~65) winsize 62
1452 11:49:28.557171 [CA 3] Center 34 (4~65) winsize 62
1453 11:49:28.560442 [CA 4] Center 34 (4~65) winsize 62
1454 11:49:28.563855 [CA 5] Center 34 (3~65) winsize 63
1455 11:49:28.563937
1456 11:49:28.567104 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1457 11:49:28.567186
1458 11:49:28.570564 [CATrainingPosCal] consider 1 rank data
1459 11:49:28.574107 u2DelayCellTimex100 = 270/100 ps
1460 11:49:28.577213 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1461 11:49:28.580873 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 11:49:28.587325 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 11:49:28.591145 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 11:49:28.594402 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 11:49:28.597375 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1466 11:49:28.597458
1467 11:49:28.600905 CA PerBit enable=1, Macro0, CA PI delay=34
1468 11:49:28.600987
1469 11:49:28.604164 [CBTSetCACLKResult] CA Dly = 34
1470 11:49:28.604246 CS Dly: 5 (0~36)
1471 11:49:28.604311 ==
1472 11:49:28.607930 Dram Type= 6, Freq= 0, CH_1, rank 1
1473 11:49:28.613998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 11:49:28.614081 ==
1475 11:49:28.617482 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1476 11:49:28.623862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1477 11:49:28.633962 [CA 0] Center 37 (6~68) winsize 63
1478 11:49:28.636957 [CA 1] Center 37 (6~68) winsize 63
1479 11:49:28.640225 [CA 2] Center 35 (4~66) winsize 63
1480 11:49:28.643317 [CA 3] Center 34 (4~65) winsize 62
1481 11:49:28.646863 [CA 4] Center 34 (4~65) winsize 62
1482 11:49:28.650125 [CA 5] Center 34 (4~64) winsize 61
1483 11:49:28.650206
1484 11:49:28.653702 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1485 11:49:28.653783
1486 11:49:28.656972 [CATrainingPosCal] consider 2 rank data
1487 11:49:28.660118 u2DelayCellTimex100 = 270/100 ps
1488 11:49:28.663611 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1489 11:49:28.666889 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1490 11:49:28.670636 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1491 11:49:28.674319 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1492 11:49:28.678308 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1493 11:49:28.681598 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1494 11:49:28.681680
1495 11:49:28.686093 CA PerBit enable=1, Macro0, CA PI delay=34
1496 11:49:28.686176
1497 11:49:28.689305 [CBTSetCACLKResult] CA Dly = 34
1498 11:49:28.693083 CS Dly: 6 (0~38)
1499 11:49:28.693165
1500 11:49:28.696599 ----->DramcWriteLeveling(PI) begin...
1501 11:49:28.696683 ==
1502 11:49:28.700230 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 11:49:28.703894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 11:49:28.703977 ==
1505 11:49:28.708230 Write leveling (Byte 0): 28 => 28
1506 11:49:28.708314 Write leveling (Byte 1): 28 => 28
1507 11:49:28.711012 DramcWriteLeveling(PI) end<-----
1508 11:49:28.711094
1509 11:49:28.711159 ==
1510 11:49:28.714405 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 11:49:28.721103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1512 11:49:28.721186 ==
1513 11:49:28.724411 [Gating] SW mode calibration
1514 11:49:28.730943 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1515 11:49:28.734695 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1516 11:49:28.737767 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1517 11:49:28.744873 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1518 11:49:28.747762 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1519 11:49:28.751332 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:49:28.758314 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:49:28.761345 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:49:28.764764 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:49:28.771328 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:49:28.774527 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:49:28.777881 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:49:28.784816 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:49:28.788025 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:49:28.791394 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:49:28.797845 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:49:28.801252 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:49:28.804783 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:49:28.808112 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1533 11:49:28.814818 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1534 11:49:28.818030 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1535 11:49:28.821233 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:49:28.828001 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:49:28.831498 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:49:28.835198 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:49:28.841752 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:49:28.845026 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:49:28.848141 0 9 4 | B1->B0 | 2322 2828 | 1 0 | (0 0) (0 0)
1542 11:49:28.854899 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1543 11:49:28.857906 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 11:49:28.861710 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 11:49:28.868427 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:49:28.871735 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:49:28.874715 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 11:49:28.878029 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1549 11:49:28.885056 0 10 4 | B1->B0 | 2c2c 2828 | 1 0 | (1 0) (1 0)
1550 11:49:28.888482 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:49:28.891688 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:49:28.898543 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:49:28.902176 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:49:28.905449 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:49:28.912120 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:49:28.914937 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1557 11:49:28.918711 0 11 4 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
1558 11:49:28.925132 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1559 11:49:28.928728 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:49:28.932013 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 11:49:28.938549 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:49:28.941956 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:49:28.945104 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:49:28.951790 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 11:49:28.955167 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1566 11:49:28.958573 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1567 11:49:28.961891 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:49:28.968582 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:49:28.971735 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:49:28.975014 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:49:28.981670 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:49:28.984926 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:49:28.988519 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:49:28.995015 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:49:28.998341 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:49:29.001775 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:49:29.008513 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:49:29.011852 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:49:29.015078 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:49:29.022262 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1581 11:49:29.025337 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1582 11:49:29.028634 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 11:49:29.031924 Total UI for P1: 0, mck2ui 16
1584 11:49:29.035587 best dqsien dly found for B0: ( 0, 14, 2)
1585 11:49:29.038534 Total UI for P1: 0, mck2ui 16
1586 11:49:29.042155 best dqsien dly found for B1: ( 0, 14, 6)
1587 11:49:29.045077 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1588 11:49:29.048977 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1589 11:49:29.049076
1590 11:49:29.052122 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1591 11:49:29.055863 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1592 11:49:29.058848 [Gating] SW calibration Done
1593 11:49:29.058924 ==
1594 11:49:29.062261 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 11:49:29.065621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 11:49:29.068738 ==
1597 11:49:29.068809 RX Vref Scan: 0
1598 11:49:29.068869
1599 11:49:29.072137 RX Vref 0 -> 0, step: 1
1600 11:49:29.072209
1601 11:49:29.075487 RX Delay -130 -> 252, step: 16
1602 11:49:29.078646 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1603 11:49:29.082373 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1604 11:49:29.085662 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1605 11:49:29.088990 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1606 11:49:29.095604 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1607 11:49:29.098940 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1608 11:49:29.102615 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1609 11:49:29.105580 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1610 11:49:29.108819 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1611 11:49:29.115678 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1612 11:49:29.118831 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1613 11:49:29.122175 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1614 11:49:29.125474 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1615 11:49:29.128724 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1616 11:49:29.135613 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1617 11:49:29.139311 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1618 11:49:29.139397 ==
1619 11:49:29.143189 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 11:49:29.145767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 11:49:29.145867 ==
1622 11:49:29.145957 DQS Delay:
1623 11:49:29.149141 DQS0 = 0, DQS1 = 0
1624 11:49:29.149239 DQM Delay:
1625 11:49:29.152535 DQM0 = 88, DQM1 = 80
1626 11:49:29.152605 DQ Delay:
1627 11:49:29.155628 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1628 11:49:29.159155 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1629 11:49:29.162991 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1630 11:49:29.165628 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1631 11:49:29.165703
1632 11:49:29.165772
1633 11:49:29.165830 ==
1634 11:49:29.169177 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 11:49:29.172275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 11:49:29.175802 ==
1637 11:49:29.175892
1638 11:49:29.175981
1639 11:49:29.176072 TX Vref Scan disable
1640 11:49:29.179327 == TX Byte 0 ==
1641 11:49:29.182871 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1642 11:49:29.185774 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1643 11:49:29.189303 == TX Byte 1 ==
1644 11:49:29.192447 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1645 11:49:29.196141 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1646 11:49:29.199447 ==
1647 11:49:29.199521 Dram Type= 6, Freq= 0, CH_1, rank 0
1648 11:49:29.205929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1649 11:49:29.206030 ==
1650 11:49:29.217664 TX Vref=22, minBit 10, minWin=27, winSum=450
1651 11:49:29.221073 TX Vref=24, minBit 15, minWin=27, winSum=453
1652 11:49:29.224514 TX Vref=26, minBit 0, minWin=28, winSum=457
1653 11:49:29.227697 TX Vref=28, minBit 15, minWin=27, winSum=456
1654 11:49:29.231424 TX Vref=30, minBit 8, minWin=28, winSum=459
1655 11:49:29.237793 TX Vref=32, minBit 8, minWin=28, winSum=459
1656 11:49:29.241134 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1657 11:49:29.241280
1658 11:49:29.244422 Final TX Range 1 Vref 30
1659 11:49:29.244521
1660 11:49:29.244614 ==
1661 11:49:29.247909 Dram Type= 6, Freq= 0, CH_1, rank 0
1662 11:49:29.251155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1663 11:49:29.251235 ==
1664 11:49:29.251300
1665 11:49:29.255217
1666 11:49:29.255287 TX Vref Scan disable
1667 11:49:29.259339 == TX Byte 0 ==
1668 11:49:29.262136 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1669 11:49:29.265882 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1670 11:49:29.268756 == TX Byte 1 ==
1671 11:49:29.272143 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1672 11:49:29.275609 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1673 11:49:29.275699
1674 11:49:29.278744 [DATLAT]
1675 11:49:29.278845 Freq=800, CH1 RK0
1676 11:49:29.278935
1677 11:49:29.282000 DATLAT Default: 0xa
1678 11:49:29.282101 0, 0xFFFF, sum = 0
1679 11:49:29.285480 1, 0xFFFF, sum = 0
1680 11:49:29.285582 2, 0xFFFF, sum = 0
1681 11:49:29.288970 3, 0xFFFF, sum = 0
1682 11:49:29.289071 4, 0xFFFF, sum = 0
1683 11:49:29.291891 5, 0xFFFF, sum = 0
1684 11:49:29.291970 6, 0xFFFF, sum = 0
1685 11:49:29.295202 7, 0xFFFF, sum = 0
1686 11:49:29.295275 8, 0xFFFF, sum = 0
1687 11:49:29.298895 9, 0x0, sum = 1
1688 11:49:29.298968 10, 0x0, sum = 2
1689 11:49:29.302071 11, 0x0, sum = 3
1690 11:49:29.302142 12, 0x0, sum = 4
1691 11:49:29.305445 best_step = 10
1692 11:49:29.305530
1693 11:49:29.305590 ==
1694 11:49:29.308861 Dram Type= 6, Freq= 0, CH_1, rank 0
1695 11:49:29.312258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1696 11:49:29.312358 ==
1697 11:49:29.312452 RX Vref Scan: 1
1698 11:49:29.312540
1699 11:49:29.315597 Set Vref Range= 32 -> 127
1700 11:49:29.315667
1701 11:49:29.318760 RX Vref 32 -> 127, step: 1
1702 11:49:29.318830
1703 11:49:29.322172 RX Delay -95 -> 252, step: 8
1704 11:49:29.322266
1705 11:49:29.325559 Set Vref, RX VrefLevel [Byte0]: 32
1706 11:49:29.328928 [Byte1]: 32
1707 11:49:29.329031
1708 11:49:29.332637 Set Vref, RX VrefLevel [Byte0]: 33
1709 11:49:29.335613 [Byte1]: 33
1710 11:49:29.335719
1711 11:49:29.338756 Set Vref, RX VrefLevel [Byte0]: 34
1712 11:49:29.342227 [Byte1]: 34
1713 11:49:29.345965
1714 11:49:29.346064 Set Vref, RX VrefLevel [Byte0]: 35
1715 11:49:29.349374 [Byte1]: 35
1716 11:49:29.353326
1717 11:49:29.353425 Set Vref, RX VrefLevel [Byte0]: 36
1718 11:49:29.356880 [Byte1]: 36
1719 11:49:29.361146
1720 11:49:29.361244 Set Vref, RX VrefLevel [Byte0]: 37
1721 11:49:29.364433 [Byte1]: 37
1722 11:49:29.368437
1723 11:49:29.368535 Set Vref, RX VrefLevel [Byte0]: 38
1724 11:49:29.371760 [Byte1]: 38
1725 11:49:29.376430
1726 11:49:29.376510 Set Vref, RX VrefLevel [Byte0]: 39
1727 11:49:29.379709 [Byte1]: 39
1728 11:49:29.383460
1729 11:49:29.387049 Set Vref, RX VrefLevel [Byte0]: 40
1730 11:49:29.390147 [Byte1]: 40
1731 11:49:29.390251
1732 11:49:29.393724 Set Vref, RX VrefLevel [Byte0]: 41
1733 11:49:29.396924 [Byte1]: 41
1734 11:49:29.397022
1735 11:49:29.400297 Set Vref, RX VrefLevel [Byte0]: 42
1736 11:49:29.403956 [Byte1]: 42
1737 11:49:29.404056
1738 11:49:29.407189 Set Vref, RX VrefLevel [Byte0]: 43
1739 11:49:29.410373 [Byte1]: 43
1740 11:49:29.414442
1741 11:49:29.414518 Set Vref, RX VrefLevel [Byte0]: 44
1742 11:49:29.417420 [Byte1]: 44
1743 11:49:29.421955
1744 11:49:29.422056 Set Vref, RX VrefLevel [Byte0]: 45
1745 11:49:29.425110 [Byte1]: 45
1746 11:49:29.429503
1747 11:49:29.429606 Set Vref, RX VrefLevel [Byte0]: 46
1748 11:49:29.432774 [Byte1]: 46
1749 11:49:29.437460
1750 11:49:29.437531 Set Vref, RX VrefLevel [Byte0]: 47
1751 11:49:29.440092 [Byte1]: 47
1752 11:49:29.444772
1753 11:49:29.444845 Set Vref, RX VrefLevel [Byte0]: 48
1754 11:49:29.447863 [Byte1]: 48
1755 11:49:29.452130
1756 11:49:29.452206 Set Vref, RX VrefLevel [Byte0]: 49
1757 11:49:29.455483 [Byte1]: 49
1758 11:49:29.460140
1759 11:49:29.460212 Set Vref, RX VrefLevel [Byte0]: 50
1760 11:49:29.463125 [Byte1]: 50
1761 11:49:29.467465
1762 11:49:29.467546 Set Vref, RX VrefLevel [Byte0]: 51
1763 11:49:29.470567 [Byte1]: 51
1764 11:49:29.474831
1765 11:49:29.474929 Set Vref, RX VrefLevel [Byte0]: 52
1766 11:49:29.478234 [Byte1]: 52
1767 11:49:29.483028
1768 11:49:29.483131 Set Vref, RX VrefLevel [Byte0]: 53
1769 11:49:29.486049 [Byte1]: 53
1770 11:49:29.490130
1771 11:49:29.490228 Set Vref, RX VrefLevel [Byte0]: 54
1772 11:49:29.493462 [Byte1]: 54
1773 11:49:29.497536
1774 11:49:29.497631 Set Vref, RX VrefLevel [Byte0]: 55
1775 11:49:29.500954 [Byte1]: 55
1776 11:49:29.505518
1777 11:49:29.505618 Set Vref, RX VrefLevel [Byte0]: 56
1778 11:49:29.508986 [Byte1]: 56
1779 11:49:29.513142
1780 11:49:29.513246 Set Vref, RX VrefLevel [Byte0]: 57
1781 11:49:29.516258 [Byte1]: 57
1782 11:49:29.520544
1783 11:49:29.520642 Set Vref, RX VrefLevel [Byte0]: 58
1784 11:49:29.524054 [Byte1]: 58
1785 11:49:29.527981
1786 11:49:29.528082 Set Vref, RX VrefLevel [Byte0]: 59
1787 11:49:29.531523 [Byte1]: 59
1788 11:49:29.535634
1789 11:49:29.535706 Set Vref, RX VrefLevel [Byte0]: 60
1790 11:49:29.538778 [Byte1]: 60
1791 11:49:29.543367
1792 11:49:29.543501 Set Vref, RX VrefLevel [Byte0]: 61
1793 11:49:29.546370 [Byte1]: 61
1794 11:49:29.550668
1795 11:49:29.550765 Set Vref, RX VrefLevel [Byte0]: 62
1796 11:49:29.554154 [Byte1]: 62
1797 11:49:29.558459
1798 11:49:29.558538 Set Vref, RX VrefLevel [Byte0]: 63
1799 11:49:29.561907 [Byte1]: 63
1800 11:49:29.566553
1801 11:49:29.566640 Set Vref, RX VrefLevel [Byte0]: 64
1802 11:49:29.569391 [Byte1]: 64
1803 11:49:29.573614
1804 11:49:29.573713 Set Vref, RX VrefLevel [Byte0]: 65
1805 11:49:29.576975 [Byte1]: 65
1806 11:49:29.581198
1807 11:49:29.581300 Set Vref, RX VrefLevel [Byte0]: 66
1808 11:49:29.584405 [Byte1]: 66
1809 11:49:29.589011
1810 11:49:29.589137 Set Vref, RX VrefLevel [Byte0]: 67
1811 11:49:29.591934 [Byte1]: 67
1812 11:49:29.596487
1813 11:49:29.596599 Set Vref, RX VrefLevel [Byte0]: 68
1814 11:49:29.600156 [Byte1]: 68
1815 11:49:29.603888
1816 11:49:29.603995 Set Vref, RX VrefLevel [Byte0]: 69
1817 11:49:29.607293 [Byte1]: 69
1818 11:49:29.611464
1819 11:49:29.611571 Set Vref, RX VrefLevel [Byte0]: 70
1820 11:49:29.615270 [Byte1]: 70
1821 11:49:29.619601
1822 11:49:29.619699 Set Vref, RX VrefLevel [Byte0]: 71
1823 11:49:29.622515 [Byte1]: 71
1824 11:49:29.626997
1825 11:49:29.627097 Set Vref, RX VrefLevel [Byte0]: 72
1826 11:49:29.630181 [Byte1]: 72
1827 11:49:29.634786
1828 11:49:29.634885 Set Vref, RX VrefLevel [Byte0]: 73
1829 11:49:29.637764 [Byte1]: 73
1830 11:49:29.641948
1831 11:49:29.642044 Set Vref, RX VrefLevel [Byte0]: 74
1832 11:49:29.645246 [Byte1]: 74
1833 11:49:29.649546
1834 11:49:29.649680 Set Vref, RX VrefLevel [Byte0]: 75
1835 11:49:29.653278 [Byte1]: 75
1836 11:49:29.657155
1837 11:49:29.657254 Set Vref, RX VrefLevel [Byte0]: 76
1838 11:49:29.660336 [Byte1]: 76
1839 11:49:29.665263
1840 11:49:29.665373 Set Vref, RX VrefLevel [Byte0]: 77
1841 11:49:29.668223 [Byte1]: 77
1842 11:49:29.672527
1843 11:49:29.672631 Set Vref, RX VrefLevel [Byte0]: 78
1844 11:49:29.675858 [Byte1]: 78
1845 11:49:29.679805
1846 11:49:29.679903 Set Vref, RX VrefLevel [Byte0]: 79
1847 11:49:29.683312 [Byte1]: 79
1848 11:49:29.687488
1849 11:49:29.687593 Final RX Vref Byte 0 = 54 to rank0
1850 11:49:29.691090 Final RX Vref Byte 1 = 65 to rank0
1851 11:49:29.694503 Final RX Vref Byte 0 = 54 to rank1
1852 11:49:29.697840 Final RX Vref Byte 1 = 65 to rank1==
1853 11:49:29.700896 Dram Type= 6, Freq= 0, CH_1, rank 0
1854 11:49:29.704322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 11:49:29.707863 ==
1856 11:49:29.707971 DQS Delay:
1857 11:49:29.708069 DQS0 = 0, DQS1 = 0
1858 11:49:29.711127 DQM Delay:
1859 11:49:29.711231 DQM0 = 92, DQM1 = 81
1860 11:49:29.714212 DQ Delay:
1861 11:49:29.717801 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1862 11:49:29.720679 DQ4 =88, DQ5 =104, DQ6 =100, DQ7 =88
1863 11:49:29.724365 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1864 11:49:29.727372 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1865 11:49:29.727471
1866 11:49:29.727561
1867 11:49:29.734340 [DQSOSCAuto] RK0, (LSB)MR18= 0x3451, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1868 11:49:29.737590 CH1 RK0: MR19=606, MR18=3451
1869 11:49:29.744310 CH1_RK0: MR19=0x606, MR18=0x3451, DQSOSC=389, MR23=63, INC=97, DEC=65
1870 11:49:29.744410
1871 11:49:29.747913 ----->DramcWriteLeveling(PI) begin...
1872 11:49:29.748010 ==
1873 11:49:29.750824 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 11:49:29.754034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 11:49:29.754140 ==
1876 11:49:29.757467 Write leveling (Byte 0): 28 => 28
1877 11:49:29.760776 Write leveling (Byte 1): 29 => 29
1878 11:49:29.764188 DramcWriteLeveling(PI) end<-----
1879 11:49:29.764297
1880 11:49:29.764387 ==
1881 11:49:29.767652 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 11:49:29.770825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 11:49:29.770923 ==
1884 11:49:29.774217 [Gating] SW mode calibration
1885 11:49:29.780855 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1886 11:49:29.787620 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1887 11:49:29.791281 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1888 11:49:29.794269 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1889 11:49:29.801117 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:49:29.804081 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:49:29.807468 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:49:29.814085 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:49:29.817416 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:49:29.820955 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:49:29.827543 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:49:29.831031 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:49:29.834367 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:49:29.840785 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:49:29.844408 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:49:29.847717 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:49:29.854521 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:49:29.857635 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:49:29.861106 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:49:29.864249 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1905 11:49:29.871062 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:49:29.874635 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:49:29.877725 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:49:29.884101 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:49:29.887695 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:49:29.890785 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:49:29.897538 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:49:29.900739 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 11:49:29.904435 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 11:49:29.910744 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 11:49:29.914129 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 11:49:29.917367 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 11:49:29.924238 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 11:49:29.927388 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 11:49:29.930761 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1920 11:49:29.937436 0 10 4 | B1->B0 | 2d2d 2b2b | 0 0 | (0 1) (0 1)
1921 11:49:29.940620 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 11:49:29.944307 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 11:49:29.950989 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 11:49:29.954104 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 11:49:29.957808 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 11:49:29.961298 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 11:49:29.967642 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 11:49:29.971057 0 11 4 | B1->B0 | 3131 2c2c | 0 1 | (0 0) (0 0)
1929 11:49:29.974293 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1930 11:49:29.980828 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 11:49:29.984236 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 11:49:29.987561 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 11:49:29.994294 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 11:49:29.997586 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 11:49:30.001050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 11:49:30.007941 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1937 11:49:30.011107 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1938 11:49:30.014551 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:49:30.021254 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:49:30.024313 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:49:30.027894 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:49:30.031262 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:49:30.037984 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:49:30.041363 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:49:30.044561 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 11:49:30.051146 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 11:49:30.054572 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 11:49:30.057843 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 11:49:30.064754 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 11:49:30.067759 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 11:49:30.071156 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 11:49:30.077799 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1953 11:49:30.081257 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1954 11:49:30.084615 Total UI for P1: 0, mck2ui 16
1955 11:49:30.088131 best dqsien dly found for B1: ( 0, 14, 4)
1956 11:49:30.091762 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1957 11:49:30.094862 Total UI for P1: 0, mck2ui 16
1958 11:49:30.098009 best dqsien dly found for B0: ( 0, 14, 6)
1959 11:49:30.101114 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1960 11:49:30.104890 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1961 11:49:30.104992
1962 11:49:30.108040 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1963 11:49:30.114485 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1964 11:49:30.114572 [Gating] SW calibration Done
1965 11:49:30.114639 ==
1966 11:49:30.117958 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 11:49:30.124724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 11:49:30.124849 ==
1969 11:49:30.124959 RX Vref Scan: 0
1970 11:49:30.125056
1971 11:49:30.127924 RX Vref 0 -> 0, step: 1
1972 11:49:30.128024
1973 11:49:30.131165 RX Delay -130 -> 252, step: 16
1974 11:49:30.134758 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1975 11:49:30.138036 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1976 11:49:30.141603 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1977 11:49:30.148060 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1978 11:49:30.151269 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1979 11:49:30.154491 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1980 11:49:30.157906 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1981 11:49:30.161320 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1982 11:49:30.164891 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1983 11:49:30.171295 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1984 11:49:30.174789 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1985 11:49:30.178221 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1986 11:49:30.181148 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1987 11:49:30.187972 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1988 11:49:30.191235 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1989 11:49:30.194837 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1990 11:49:30.194916 ==
1991 11:49:30.197985 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 11:49:30.201242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 11:49:30.201340 ==
1994 11:49:30.204490 DQS Delay:
1995 11:49:30.204565 DQS0 = 0, DQS1 = 0
1996 11:49:30.204634 DQM Delay:
1997 11:49:30.208131 DQM0 = 86, DQM1 = 81
1998 11:49:30.208227 DQ Delay:
1999 11:49:30.211238 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
2000 11:49:30.214492 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =77
2001 11:49:30.218210 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
2002 11:49:30.221809 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2003 11:49:30.221907
2004 11:49:30.222000
2005 11:49:30.222088 ==
2006 11:49:30.224903 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 11:49:30.231824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 11:49:30.231927 ==
2009 11:49:30.232017
2010 11:49:30.232104
2011 11:49:30.232189 TX Vref Scan disable
2012 11:49:30.234872 == TX Byte 0 ==
2013 11:49:30.238490 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2014 11:49:30.244904 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2015 11:49:30.245013 == TX Byte 1 ==
2016 11:49:30.248326 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2017 11:49:30.254799 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2018 11:49:30.254902 ==
2019 11:49:30.258338 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 11:49:30.261604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 11:49:30.261708 ==
2022 11:49:30.273770 TX Vref=22, minBit 13, minWin=27, winSum=450
2023 11:49:30.277045 TX Vref=24, minBit 13, minWin=27, winSum=454
2024 11:49:30.280468 TX Vref=26, minBit 13, minWin=27, winSum=457
2025 11:49:30.283798 TX Vref=28, minBit 9, minWin=27, winSum=458
2026 11:49:30.287436 TX Vref=30, minBit 9, minWin=27, winSum=458
2027 11:49:30.293797 TX Vref=32, minBit 8, minWin=28, winSum=458
2028 11:49:30.297029 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
2029 11:49:30.297114
2030 11:49:30.300744 Final TX Range 1 Vref 32
2031 11:49:30.300828
2032 11:49:30.300894 ==
2033 11:49:30.303674 Dram Type= 6, Freq= 0, CH_1, rank 1
2034 11:49:30.307343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2035 11:49:30.307481 ==
2036 11:49:30.310724
2037 11:49:30.310808
2038 11:49:30.310875 TX Vref Scan disable
2039 11:49:30.313778 == TX Byte 0 ==
2040 11:49:30.317665 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2041 11:49:30.320483 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2042 11:49:30.324130 == TX Byte 1 ==
2043 11:49:30.327241 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2044 11:49:30.330946 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2045 11:49:30.334035
2046 11:49:30.334118 [DATLAT]
2047 11:49:30.334185 Freq=800, CH1 RK1
2048 11:49:30.334247
2049 11:49:30.337412 DATLAT Default: 0xa
2050 11:49:30.337495 0, 0xFFFF, sum = 0
2051 11:49:30.340642 1, 0xFFFF, sum = 0
2052 11:49:30.340727 2, 0xFFFF, sum = 0
2053 11:49:30.343831 3, 0xFFFF, sum = 0
2054 11:49:30.343917 4, 0xFFFF, sum = 0
2055 11:49:30.347246 5, 0xFFFF, sum = 0
2056 11:49:30.350656 6, 0xFFFF, sum = 0
2057 11:49:30.350741 7, 0xFFFF, sum = 0
2058 11:49:30.353787 8, 0xFFFF, sum = 0
2059 11:49:30.353889 9, 0x0, sum = 1
2060 11:49:30.353987 10, 0x0, sum = 2
2061 11:49:30.357204 11, 0x0, sum = 3
2062 11:49:30.357288 12, 0x0, sum = 4
2063 11:49:30.360498 best_step = 10
2064 11:49:30.360585
2065 11:49:30.360651 ==
2066 11:49:30.364308 Dram Type= 6, Freq= 0, CH_1, rank 1
2067 11:49:30.367270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2068 11:49:30.367356 ==
2069 11:49:30.370611 RX Vref Scan: 0
2070 11:49:30.370695
2071 11:49:30.370761 RX Vref 0 -> 0, step: 1
2072 11:49:30.370825
2073 11:49:30.373756 RX Delay -79 -> 252, step: 8
2074 11:49:30.380648 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2075 11:49:30.383693 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2076 11:49:30.387192 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2077 11:49:30.390628 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2078 11:49:30.394164 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2079 11:49:30.400614 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2080 11:49:30.403980 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
2081 11:49:30.407126 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2082 11:49:30.411001 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2083 11:49:30.413898 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2084 11:49:30.420432 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2085 11:49:30.424000 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2086 11:49:30.427509 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2087 11:49:30.430519 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2088 11:49:30.433874 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2089 11:49:30.440469 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2090 11:49:30.440556 ==
2091 11:49:30.443810 Dram Type= 6, Freq= 0, CH_1, rank 1
2092 11:49:30.447170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2093 11:49:30.447254 ==
2094 11:49:30.447352 DQS Delay:
2095 11:49:30.450604 DQS0 = 0, DQS1 = 0
2096 11:49:30.450706 DQM Delay:
2097 11:49:30.453795 DQM0 = 92, DQM1 = 82
2098 11:49:30.453878 DQ Delay:
2099 11:49:30.457016 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2100 11:49:30.460538 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
2101 11:49:30.463839 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2102 11:49:30.467374 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2103 11:49:30.467457
2104 11:49:30.467523
2105 11:49:30.474016 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2106 11:49:30.477059 CH1 RK1: MR19=606, MR18=3C11
2107 11:49:30.483995 CH1_RK1: MR19=0x606, MR18=0x3C11, DQSOSC=394, MR23=63, INC=95, DEC=63
2108 11:49:30.487377 [RxdqsGatingPostProcess] freq 800
2109 11:49:30.493911 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2110 11:49:30.497317 Pre-setting of DQS Precalculation
2111 11:49:30.500641 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2112 11:49:30.507120 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2113 11:49:30.513886 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2114 11:49:30.513997
2115 11:49:30.514091
2116 11:49:30.517352 [Calibration Summary] 1600 Mbps
2117 11:49:30.520711 CH 0, Rank 0
2118 11:49:30.520794 SW Impedance : PASS
2119 11:49:30.524266 DUTY Scan : NO K
2120 11:49:30.527449 ZQ Calibration : PASS
2121 11:49:30.527533 Jitter Meter : NO K
2122 11:49:30.530569 CBT Training : PASS
2123 11:49:30.533952 Write leveling : PASS
2124 11:49:30.534036 RX DQS gating : PASS
2125 11:49:30.537419 RX DQ/DQS(RDDQC) : PASS
2126 11:49:30.537503 TX DQ/DQS : PASS
2127 11:49:30.540777 RX DATLAT : PASS
2128 11:49:30.543909 RX DQ/DQS(Engine): PASS
2129 11:49:30.543992 TX OE : NO K
2130 11:49:30.547276 All Pass.
2131 11:49:30.547359
2132 11:49:30.547426 CH 0, Rank 1
2133 11:49:30.550639 SW Impedance : PASS
2134 11:49:30.550722 DUTY Scan : NO K
2135 11:49:30.554221 ZQ Calibration : PASS
2136 11:49:30.557504 Jitter Meter : NO K
2137 11:49:30.557587 CBT Training : PASS
2138 11:49:30.560579 Write leveling : PASS
2139 11:49:30.564246 RX DQS gating : PASS
2140 11:49:30.564330 RX DQ/DQS(RDDQC) : PASS
2141 11:49:30.567362 TX DQ/DQS : PASS
2142 11:49:30.570603 RX DATLAT : PASS
2143 11:49:30.570689 RX DQ/DQS(Engine): PASS
2144 11:49:30.574125 TX OE : NO K
2145 11:49:30.574209 All Pass.
2146 11:49:30.574275
2147 11:49:30.577343 CH 1, Rank 0
2148 11:49:30.577426 SW Impedance : PASS
2149 11:49:30.580515 DUTY Scan : NO K
2150 11:49:30.580599 ZQ Calibration : PASS
2151 11:49:30.583895 Jitter Meter : NO K
2152 11:49:30.587374 CBT Training : PASS
2153 11:49:30.587486 Write leveling : PASS
2154 11:49:30.590868 RX DQS gating : PASS
2155 11:49:30.594221 RX DQ/DQS(RDDQC) : PASS
2156 11:49:30.594309 TX DQ/DQS : PASS
2157 11:49:30.597665 RX DATLAT : PASS
2158 11:49:30.600782 RX DQ/DQS(Engine): PASS
2159 11:49:30.600866 TX OE : NO K
2160 11:49:30.604077 All Pass.
2161 11:49:30.604165
2162 11:49:30.604231 CH 1, Rank 1
2163 11:49:30.607771 SW Impedance : PASS
2164 11:49:30.607883 DUTY Scan : NO K
2165 11:49:30.610874 ZQ Calibration : PASS
2166 11:49:30.614235 Jitter Meter : NO K
2167 11:49:30.614318 CBT Training : PASS
2168 11:49:30.617580 Write leveling : PASS
2169 11:49:30.617663 RX DQS gating : PASS
2170 11:49:30.620787 RX DQ/DQS(RDDQC) : PASS
2171 11:49:30.624093 TX DQ/DQS : PASS
2172 11:49:30.624177 RX DATLAT : PASS
2173 11:49:30.627373 RX DQ/DQS(Engine): PASS
2174 11:49:30.630819 TX OE : NO K
2175 11:49:30.630903 All Pass.
2176 11:49:30.630970
2177 11:49:30.634223 DramC Write-DBI off
2178 11:49:30.634306 PER_BANK_REFRESH: Hybrid Mode
2179 11:49:30.637473 TX_TRACKING: ON
2180 11:49:30.641012 [GetDramInforAfterCalByMRR] Vendor 6.
2181 11:49:30.644132 [GetDramInforAfterCalByMRR] Revision 606.
2182 11:49:30.647527 [GetDramInforAfterCalByMRR] Revision 2 0.
2183 11:49:30.647611 MR0 0x3b3b
2184 11:49:30.650806 MR8 0x5151
2185 11:49:30.654269 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 11:49:30.654353
2187 11:49:30.654456 MR0 0x3b3b
2188 11:49:30.654519 MR8 0x5151
2189 11:49:30.660836 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2190 11:49:30.660921
2191 11:49:30.667625 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2192 11:49:30.670955 [FAST_K] Save calibration result to emmc
2193 11:49:30.674368 [FAST_K] Save calibration result to emmc
2194 11:49:30.677620 dram_init: config_dvfs: 1
2195 11:49:30.681389 dramc_set_vcore_voltage set vcore to 662500
2196 11:49:30.684504 Read voltage for 1200, 2
2197 11:49:30.684587 Vio18 = 0
2198 11:49:30.687659 Vcore = 662500
2199 11:49:30.687745 Vdram = 0
2200 11:49:30.687813 Vddq = 0
2201 11:49:30.687874 Vmddr = 0
2202 11:49:30.694375 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2203 11:49:30.700923 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2204 11:49:30.701007 MEM_TYPE=3, freq_sel=15
2205 11:49:30.704893 sv_algorithm_assistance_LP4_1600
2206 11:49:30.707860 ============ PULL DRAM RESETB DOWN ============
2207 11:49:30.714227 ========== PULL DRAM RESETB DOWN end =========
2208 11:49:30.717990 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2209 11:49:30.720879 ===================================
2210 11:49:30.724587 LPDDR4 DRAM CONFIGURATION
2211 11:49:30.727759 ===================================
2212 11:49:30.727844 EX_ROW_EN[0] = 0x0
2213 11:49:30.731188 EX_ROW_EN[1] = 0x0
2214 11:49:30.731285 LP4Y_EN = 0x0
2215 11:49:30.734560 WORK_FSP = 0x0
2216 11:49:30.734648 WL = 0x4
2217 11:49:30.737899 RL = 0x4
2218 11:49:30.738018 BL = 0x2
2219 11:49:30.741167 RPST = 0x0
2220 11:49:30.741239 RD_PRE = 0x0
2221 11:49:30.744794 WR_PRE = 0x1
2222 11:49:30.744869 WR_PST = 0x0
2223 11:49:30.748054 DBI_WR = 0x0
2224 11:49:30.751468 DBI_RD = 0x0
2225 11:49:30.751544 OTF = 0x1
2226 11:49:30.754408 ===================================
2227 11:49:30.758234 ===================================
2228 11:49:30.758306 ANA top config
2229 11:49:30.761361 ===================================
2230 11:49:30.764652 DLL_ASYNC_EN = 0
2231 11:49:30.768384 ALL_SLAVE_EN = 0
2232 11:49:30.770859 NEW_RANK_MODE = 1
2233 11:49:30.774197 DLL_IDLE_MODE = 1
2234 11:49:30.774273 LP45_APHY_COMB_EN = 1
2235 11:49:30.777555 TX_ODT_DIS = 1
2236 11:49:30.781026 NEW_8X_MODE = 1
2237 11:49:30.784206 ===================================
2238 11:49:30.787586 ===================================
2239 11:49:30.791115 data_rate = 2400
2240 11:49:30.794396 CKR = 1
2241 11:49:30.794486 DQ_P2S_RATIO = 8
2242 11:49:30.798156 ===================================
2243 11:49:30.801541 CA_P2S_RATIO = 8
2244 11:49:30.804563 DQ_CA_OPEN = 0
2245 11:49:30.807830 DQ_SEMI_OPEN = 0
2246 11:49:30.811141 CA_SEMI_OPEN = 0
2247 11:49:30.814200 CA_FULL_RATE = 0
2248 11:49:30.814283 DQ_CKDIV4_EN = 0
2249 11:49:30.817675 CA_CKDIV4_EN = 0
2250 11:49:30.821151 CA_PREDIV_EN = 0
2251 11:49:30.824584 PH8_DLY = 17
2252 11:49:30.827951 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2253 11:49:30.831209 DQ_AAMCK_DIV = 4
2254 11:49:30.831286 CA_AAMCK_DIV = 4
2255 11:49:30.834408 CA_ADMCK_DIV = 4
2256 11:49:30.837672 DQ_TRACK_CA_EN = 0
2257 11:49:30.840679 CA_PICK = 1200
2258 11:49:30.843930 CA_MCKIO = 1200
2259 11:49:30.847552 MCKIO_SEMI = 0
2260 11:49:30.850970 PLL_FREQ = 2366
2261 11:49:30.851048 DQ_UI_PI_RATIO = 32
2262 11:49:30.853849 CA_UI_PI_RATIO = 0
2263 11:49:30.857539 ===================================
2264 11:49:30.860743 ===================================
2265 11:49:30.864205 memory_type:LPDDR4
2266 11:49:30.867463 GP_NUM : 10
2267 11:49:30.867542 SRAM_EN : 1
2268 11:49:30.870671 MD32_EN : 0
2269 11:49:30.874066 ===================================
2270 11:49:30.877605 [ANA_INIT] >>>>>>>>>>>>>>
2271 11:49:30.877688 <<<<<< [CONFIGURE PHASE]: ANA_TX
2272 11:49:30.880816 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2273 11:49:30.883903 ===================================
2274 11:49:30.887331 data_rate = 2400,PCW = 0X5b00
2275 11:49:30.890816 ===================================
2276 11:49:30.893908 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2277 11:49:30.900582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2278 11:49:30.907640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2279 11:49:30.910673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2280 11:49:30.914062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2281 11:49:30.917637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2282 11:49:30.921044 [ANA_INIT] flow start
2283 11:49:30.921131 [ANA_INIT] PLL >>>>>>>>
2284 11:49:30.924111 [ANA_INIT] PLL <<<<<<<<
2285 11:49:30.927564 [ANA_INIT] MIDPI >>>>>>>>
2286 11:49:30.927650 [ANA_INIT] MIDPI <<<<<<<<
2287 11:49:30.931297 [ANA_INIT] DLL >>>>>>>>
2288 11:49:30.934249 [ANA_INIT] DLL <<<<<<<<
2289 11:49:30.934360 [ANA_INIT] flow end
2290 11:49:30.938096 ============ LP4 DIFF to SE enter ============
2291 11:49:30.944188 ============ LP4 DIFF to SE exit ============
2292 11:49:30.944275 [ANA_INIT] <<<<<<<<<<<<<
2293 11:49:30.947759 [Flow] Enable top DCM control >>>>>
2294 11:49:30.950821 [Flow] Enable top DCM control <<<<<
2295 11:49:30.954199 Enable DLL master slave shuffle
2296 11:49:30.961156 ==============================================================
2297 11:49:30.961244 Gating Mode config
2298 11:49:30.967636 ==============================================================
2299 11:49:30.970768 Config description:
2300 11:49:30.981059 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2301 11:49:30.987633 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2302 11:49:30.991100 SELPH_MODE 0: By rank 1: By Phase
2303 11:49:30.997845 ==============================================================
2304 11:49:31.001111 GAT_TRACK_EN = 1
2305 11:49:31.001197 RX_GATING_MODE = 2
2306 11:49:31.004224 RX_GATING_TRACK_MODE = 2
2307 11:49:31.007912 SELPH_MODE = 1
2308 11:49:31.010992 PICG_EARLY_EN = 1
2309 11:49:31.014299 VALID_LAT_VALUE = 1
2310 11:49:31.021223 ==============================================================
2311 11:49:31.024533 Enter into Gating configuration >>>>
2312 11:49:31.027778 Exit from Gating configuration <<<<
2313 11:49:31.031419 Enter into DVFS_PRE_config >>>>>
2314 11:49:31.041473 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2315 11:49:31.044448 Exit from DVFS_PRE_config <<<<<
2316 11:49:31.047747 Enter into PICG configuration >>>>
2317 11:49:31.051459 Exit from PICG configuration <<<<
2318 11:49:31.054762 [RX_INPUT] configuration >>>>>
2319 11:49:31.054848 [RX_INPUT] configuration <<<<<
2320 11:49:31.061051 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2321 11:49:31.067721 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2322 11:49:31.071051 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2323 11:49:31.077786 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2324 11:49:31.084533 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2325 11:49:31.091126 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2326 11:49:31.094419 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2327 11:49:31.097805 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2328 11:49:31.104606 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2329 11:49:31.108282 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2330 11:49:31.111357 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2331 11:49:31.114509 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2332 11:49:31.118010 ===================================
2333 11:49:31.121220 LPDDR4 DRAM CONFIGURATION
2334 11:49:31.124799 ===================================
2335 11:49:31.128245 EX_ROW_EN[0] = 0x0
2336 11:49:31.128331 EX_ROW_EN[1] = 0x0
2337 11:49:31.131305 LP4Y_EN = 0x0
2338 11:49:31.131392 WORK_FSP = 0x0
2339 11:49:31.134652 WL = 0x4
2340 11:49:31.134738 RL = 0x4
2341 11:49:31.137869 BL = 0x2
2342 11:49:31.137955 RPST = 0x0
2343 11:49:31.141183 RD_PRE = 0x0
2344 11:49:31.141268 WR_PRE = 0x1
2345 11:49:31.144840 WR_PST = 0x0
2346 11:49:31.144927 DBI_WR = 0x0
2347 11:49:31.147938 DBI_RD = 0x0
2348 11:49:31.151358 OTF = 0x1
2349 11:49:31.154534 ===================================
2350 11:49:31.158127 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2351 11:49:31.161045 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2352 11:49:31.165324 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2353 11:49:31.167870 ===================================
2354 11:49:31.171131 LPDDR4 DRAM CONFIGURATION
2355 11:49:31.174336 ===================================
2356 11:49:31.177946 EX_ROW_EN[0] = 0x10
2357 11:49:31.178032 EX_ROW_EN[1] = 0x0
2358 11:49:31.181338 LP4Y_EN = 0x0
2359 11:49:31.181449 WORK_FSP = 0x0
2360 11:49:31.184572 WL = 0x4
2361 11:49:31.184680 RL = 0x4
2362 11:49:31.188157 BL = 0x2
2363 11:49:31.188241 RPST = 0x0
2364 11:49:31.191600 RD_PRE = 0x0
2365 11:49:31.191682 WR_PRE = 0x1
2366 11:49:31.194610 WR_PST = 0x0
2367 11:49:31.194691 DBI_WR = 0x0
2368 11:49:31.197889 DBI_RD = 0x0
2369 11:49:31.197970 OTF = 0x1
2370 11:49:31.201388 ===================================
2371 11:49:31.208174 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2372 11:49:31.208258 ==
2373 11:49:31.211216 Dram Type= 6, Freq= 0, CH_0, rank 0
2374 11:49:31.214676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 11:49:31.217896 ==
2376 11:49:31.217989 [Duty_Offset_Calibration]
2377 11:49:31.221261 B0:2 B1:0 CA:1
2378 11:49:31.221343
2379 11:49:31.224837 [DutyScan_Calibration_Flow] k_type=0
2380 11:49:31.232246
2381 11:49:31.232327 ==CLK 0==
2382 11:49:31.235755 Final CLK duty delay cell = -4
2383 11:49:31.238941 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2384 11:49:31.242423 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2385 11:49:31.245807 [-4] AVG Duty = 4953%(X100)
2386 11:49:31.245889
2387 11:49:31.249467 CH0 CLK Duty spec in!! Max-Min= 156%
2388 11:49:31.252398 [DutyScan_Calibration_Flow] ====Done====
2389 11:49:31.252480
2390 11:49:31.255790 [DutyScan_Calibration_Flow] k_type=1
2391 11:49:31.271133
2392 11:49:31.271215 ==DQS 0 ==
2393 11:49:31.274290 Final DQS duty delay cell = 0
2394 11:49:31.278014 [0] MAX Duty = 5187%(X100), DQS PI = 30
2395 11:49:31.280962 [0] MIN Duty = 4938%(X100), DQS PI = 0
2396 11:49:31.281044 [0] AVG Duty = 5062%(X100)
2397 11:49:31.284783
2398 11:49:31.284863 ==DQS 1 ==
2399 11:49:31.287856 Final DQS duty delay cell = -4
2400 11:49:31.291372 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2401 11:49:31.294524 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2402 11:49:31.297884 [-4] AVG Duty = 5031%(X100)
2403 11:49:31.297967
2404 11:49:31.301342 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2405 11:49:31.301423
2406 11:49:31.304752 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2407 11:49:31.307739 [DutyScan_Calibration_Flow] ====Done====
2408 11:49:31.307820
2409 11:49:31.311036 [DutyScan_Calibration_Flow] k_type=3
2410 11:49:31.327867
2411 11:49:31.327951 ==DQM 0 ==
2412 11:49:31.331507 Final DQM duty delay cell = 0
2413 11:49:31.334517 [0] MAX Duty = 5062%(X100), DQS PI = 24
2414 11:49:31.337870 [0] MIN Duty = 4813%(X100), DQS PI = 0
2415 11:49:31.337952 [0] AVG Duty = 4937%(X100)
2416 11:49:31.341503
2417 11:49:31.341588 ==DQM 1 ==
2418 11:49:31.344699 Final DQM duty delay cell = 0
2419 11:49:31.348345 [0] MAX Duty = 5187%(X100), DQS PI = 46
2420 11:49:31.351313 [0] MIN Duty = 5000%(X100), DQS PI = 12
2421 11:49:31.351395 [0] AVG Duty = 5093%(X100)
2422 11:49:31.354825
2423 11:49:31.358094 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2424 11:49:31.358175
2425 11:49:31.361497 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2426 11:49:31.364718 [DutyScan_Calibration_Flow] ====Done====
2427 11:49:31.364799
2428 11:49:31.367970 [DutyScan_Calibration_Flow] k_type=2
2429 11:49:31.384314
2430 11:49:31.384397 ==DQ 0 ==
2431 11:49:31.388218 Final DQ duty delay cell = -4
2432 11:49:31.391193 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2433 11:49:31.394454 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2434 11:49:31.398017 [-4] AVG Duty = 4953%(X100)
2435 11:49:31.398104
2436 11:49:31.398190 ==DQ 1 ==
2437 11:49:31.401012 Final DQ duty delay cell = 4
2438 11:49:31.404642 [4] MAX Duty = 5093%(X100), DQS PI = 4
2439 11:49:31.407793 [4] MIN Duty = 5031%(X100), DQS PI = 0
2440 11:49:31.407879 [4] AVG Duty = 5062%(X100)
2441 11:49:31.411266
2442 11:49:31.414512 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2443 11:49:31.414598
2444 11:49:31.418011 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2445 11:49:31.421350 [DutyScan_Calibration_Flow] ====Done====
2446 11:49:31.421436 ==
2447 11:49:31.424710 Dram Type= 6, Freq= 0, CH_1, rank 0
2448 11:49:31.428208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 11:49:31.428295 ==
2450 11:49:31.431371 [Duty_Offset_Calibration]
2451 11:49:31.431457 B0:0 B1:-1 CA:2
2452 11:49:31.431543
2453 11:49:31.434654 [DutyScan_Calibration_Flow] k_type=0
2454 11:49:31.444678
2455 11:49:31.444764 ==CLK 0==
2456 11:49:31.448088 Final CLK duty delay cell = 0
2457 11:49:31.451556 [0] MAX Duty = 5156%(X100), DQS PI = 16
2458 11:49:31.454622 [0] MIN Duty = 4938%(X100), DQS PI = 44
2459 11:49:31.454708 [0] AVG Duty = 5047%(X100)
2460 11:49:31.458083
2461 11:49:31.461353 CH1 CLK Duty spec in!! Max-Min= 218%
2462 11:49:31.464526 [DutyScan_Calibration_Flow] ====Done====
2463 11:49:31.464613
2464 11:49:31.467767 [DutyScan_Calibration_Flow] k_type=1
2465 11:49:31.484323
2466 11:49:31.484410 ==DQS 0 ==
2467 11:49:31.487464 Final DQS duty delay cell = 0
2468 11:49:31.490775 [0] MAX Duty = 5093%(X100), DQS PI = 24
2469 11:49:31.494318 [0] MIN Duty = 4969%(X100), DQS PI = 0
2470 11:49:31.494448 [0] AVG Duty = 5031%(X100)
2471 11:49:31.497528
2472 11:49:31.497614 ==DQS 1 ==
2473 11:49:31.500843 Final DQS duty delay cell = 0
2474 11:49:31.504099 [0] MAX Duty = 5156%(X100), DQS PI = 0
2475 11:49:31.507353 [0] MIN Duty = 4875%(X100), DQS PI = 34
2476 11:49:31.507440 [0] AVG Duty = 5015%(X100)
2477 11:49:31.510910
2478 11:49:31.514128 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2479 11:49:31.514239
2480 11:49:31.517669 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2481 11:49:31.520800 [DutyScan_Calibration_Flow] ====Done====
2482 11:49:31.520912
2483 11:49:31.523997 [DutyScan_Calibration_Flow] k_type=3
2484 11:49:31.541434
2485 11:49:31.541522 ==DQM 0 ==
2486 11:49:31.544761 Final DQM duty delay cell = 4
2487 11:49:31.548131 [4] MAX Duty = 5093%(X100), DQS PI = 6
2488 11:49:31.551450 [4] MIN Duty = 4938%(X100), DQS PI = 48
2489 11:49:31.551536 [4] AVG Duty = 5015%(X100)
2490 11:49:31.554992
2491 11:49:31.555079 ==DQM 1 ==
2492 11:49:31.558139 Final DQM duty delay cell = 0
2493 11:49:31.561945 [0] MAX Duty = 5249%(X100), DQS PI = 0
2494 11:49:31.564686 [0] MIN Duty = 4875%(X100), DQS PI = 36
2495 11:49:31.564796 [0] AVG Duty = 5062%(X100)
2496 11:49:31.564899
2497 11:49:31.571641 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2498 11:49:31.571726
2499 11:49:31.574873 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2500 11:49:31.578353 [DutyScan_Calibration_Flow] ====Done====
2501 11:49:31.578485
2502 11:49:31.581375 [DutyScan_Calibration_Flow] k_type=2
2503 11:49:31.597831
2504 11:49:31.597920 ==DQ 0 ==
2505 11:49:31.601176 Final DQ duty delay cell = 0
2506 11:49:31.604650 [0] MAX Duty = 5062%(X100), DQS PI = 18
2507 11:49:31.608026 [0] MIN Duty = 4938%(X100), DQS PI = 46
2508 11:49:31.608112 [0] AVG Duty = 5000%(X100)
2509 11:49:31.608199
2510 11:49:31.611325 ==DQ 1 ==
2511 11:49:31.614510 Final DQ duty delay cell = 0
2512 11:49:31.618070 [0] MAX Duty = 5031%(X100), DQS PI = 0
2513 11:49:31.621475 [0] MIN Duty = 4813%(X100), DQS PI = 34
2514 11:49:31.621565 [0] AVG Duty = 4922%(X100)
2515 11:49:31.621650
2516 11:49:31.624870 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2517 11:49:31.624956
2518 11:49:31.628011 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2519 11:49:31.634953 [DutyScan_Calibration_Flow] ====Done====
2520 11:49:31.637907 nWR fixed to 30
2521 11:49:31.637994 [ModeRegInit_LP4] CH0 RK0
2522 11:49:31.641418 [ModeRegInit_LP4] CH0 RK1
2523 11:49:31.644804 [ModeRegInit_LP4] CH1 RK0
2524 11:49:31.644890 [ModeRegInit_LP4] CH1 RK1
2525 11:49:31.648122 match AC timing 7
2526 11:49:31.651426 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2527 11:49:31.654876 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2528 11:49:31.661330 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2529 11:49:31.664790 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2530 11:49:31.671505 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2531 11:49:31.671591 ==
2532 11:49:31.674717 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 11:49:31.678125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 11:49:31.678209 ==
2535 11:49:31.685074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2536 11:49:31.687960 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2537 11:49:31.697853 [CA 0] Center 38 (8~69) winsize 62
2538 11:49:31.701189 [CA 1] Center 38 (8~69) winsize 62
2539 11:49:31.704614 [CA 2] Center 35 (5~66) winsize 62
2540 11:49:31.708091 [CA 3] Center 35 (4~66) winsize 63
2541 11:49:31.711144 [CA 4] Center 34 (4~65) winsize 62
2542 11:49:31.714526 [CA 5] Center 33 (3~63) winsize 61
2543 11:49:31.714610
2544 11:49:31.717643 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2545 11:49:31.717752
2546 11:49:31.720899 [CATrainingPosCal] consider 1 rank data
2547 11:49:31.724910 u2DelayCellTimex100 = 270/100 ps
2548 11:49:31.728058 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2549 11:49:31.731584 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2550 11:49:31.737654 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2551 11:49:31.741388 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2552 11:49:31.744399 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2553 11:49:31.747663 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2554 11:49:31.747747
2555 11:49:31.751038 CA PerBit enable=1, Macro0, CA PI delay=33
2556 11:49:31.751122
2557 11:49:31.754297 [CBTSetCACLKResult] CA Dly = 33
2558 11:49:31.754455 CS Dly: 6 (0~37)
2559 11:49:31.754537 ==
2560 11:49:31.758010 Dram Type= 6, Freq= 0, CH_0, rank 1
2561 11:49:31.764690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2562 11:49:31.764774 ==
2563 11:49:31.767739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2564 11:49:31.774350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2565 11:49:31.783416 [CA 0] Center 39 (8~70) winsize 63
2566 11:49:31.786735 [CA 1] Center 38 (8~69) winsize 62
2567 11:49:31.790291 [CA 2] Center 35 (5~66) winsize 62
2568 11:49:31.793722 [CA 3] Center 35 (5~66) winsize 62
2569 11:49:31.797079 [CA 4] Center 34 (4~65) winsize 62
2570 11:49:31.800102 [CA 5] Center 34 (4~64) winsize 61
2571 11:49:31.800201
2572 11:49:31.803558 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2573 11:49:31.803658
2574 11:49:31.807091 [CATrainingPosCal] consider 2 rank data
2575 11:49:31.810508 u2DelayCellTimex100 = 270/100 ps
2576 11:49:31.813537 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2577 11:49:31.816906 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2578 11:49:31.820483 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2579 11:49:31.826804 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2580 11:49:31.830273 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2581 11:49:31.833401 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2582 11:49:31.833500
2583 11:49:31.837268 CA PerBit enable=1, Macro0, CA PI delay=33
2584 11:49:31.837366
2585 11:49:31.840108 [CBTSetCACLKResult] CA Dly = 33
2586 11:49:31.840181 CS Dly: 7 (0~39)
2587 11:49:31.840242
2588 11:49:31.843840 ----->DramcWriteLeveling(PI) begin...
2589 11:49:31.843937 ==
2590 11:49:31.847145 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 11:49:31.853371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 11:49:31.853445 ==
2593 11:49:31.857315 Write leveling (Byte 0): 34 => 34
2594 11:49:31.860746 Write leveling (Byte 1): 30 => 30
2595 11:49:31.860841 DramcWriteLeveling(PI) end<-----
2596 11:49:31.860929
2597 11:49:31.864000 ==
2598 11:49:31.864070 Dram Type= 6, Freq= 0, CH_0, rank 0
2599 11:49:31.870719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2600 11:49:31.870816 ==
2601 11:49:31.873796 [Gating] SW mode calibration
2602 11:49:31.880941 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2603 11:49:31.884017 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2604 11:49:31.890570 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2605 11:49:31.894586 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2606 11:49:31.897587 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 11:49:31.904408 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 11:49:31.907466 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 11:49:31.910644 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 11:49:31.914134 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2611 11:49:31.920784 0 15 28 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
2612 11:49:31.924183 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
2613 11:49:31.927443 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 11:49:31.934203 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 11:49:31.937602 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 11:49:31.941070 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 11:49:31.948181 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 11:49:31.950721 1 0 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
2619 11:49:31.954282 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2620 11:49:31.960907 1 1 0 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2621 11:49:31.964772 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 11:49:31.967570 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 11:49:31.974241 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 11:49:31.977727 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 11:49:31.980921 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 11:49:31.987481 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 11:49:31.990788 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2628 11:49:31.993862 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2629 11:49:32.000690 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:49:32.004245 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:49:32.007586 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:49:32.010653 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:49:32.017355 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:49:32.020751 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:49:32.023990 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 11:49:32.030742 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 11:49:32.034366 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 11:49:32.037182 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 11:49:32.043952 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 11:49:32.047723 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 11:49:32.051269 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 11:49:32.057472 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2643 11:49:32.060840 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2644 11:49:32.064117 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2645 11:49:32.067418 Total UI for P1: 0, mck2ui 16
2646 11:49:32.070914 best dqsien dly found for B0: ( 1, 3, 26)
2647 11:49:32.077752 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2648 11:49:32.077823 Total UI for P1: 0, mck2ui 16
2649 11:49:32.080709 best dqsien dly found for B1: ( 1, 3, 30)
2650 11:49:32.087527 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2651 11:49:32.090969 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2652 11:49:32.091045
2653 11:49:32.093941 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2654 11:49:32.097643 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2655 11:49:32.100851 [Gating] SW calibration Done
2656 11:49:32.100945 ==
2657 11:49:32.104552 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 11:49:32.107516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 11:49:32.107610 ==
2660 11:49:32.110850 RX Vref Scan: 0
2661 11:49:32.110954
2662 11:49:32.111049 RX Vref 0 -> 0, step: 1
2663 11:49:32.111138
2664 11:49:32.114098 RX Delay -40 -> 252, step: 8
2665 11:49:32.117530 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2666 11:49:32.124249 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2667 11:49:32.127568 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2668 11:49:32.130699 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2669 11:49:32.134374 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2670 11:49:32.137441 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2671 11:49:32.141071 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2672 11:49:32.147727 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2673 11:49:32.151133 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2674 11:49:32.154375 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2675 11:49:32.157730 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2676 11:49:32.161298 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2677 11:49:32.167800 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2678 11:49:32.171089 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2679 11:49:32.174291 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2680 11:49:32.177633 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2681 11:49:32.177740 ==
2682 11:49:32.180928 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 11:49:32.184675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 11:49:32.187592 ==
2685 11:49:32.187692 DQS Delay:
2686 11:49:32.187787 DQS0 = 0, DQS1 = 0
2687 11:49:32.190813 DQM Delay:
2688 11:49:32.190895 DQM0 = 122, DQM1 = 110
2689 11:49:32.193973 DQ Delay:
2690 11:49:32.197327 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2691 11:49:32.200834 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2692 11:49:32.204302 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2693 11:49:32.207710 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2694 11:49:32.207782
2695 11:49:32.207844
2696 11:49:32.207911 ==
2697 11:49:32.210889 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 11:49:32.214392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 11:49:32.214472 ==
2700 11:49:32.217227
2701 11:49:32.217325
2702 11:49:32.217415 TX Vref Scan disable
2703 11:49:32.221178 == TX Byte 0 ==
2704 11:49:32.224276 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2705 11:49:32.227540 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2706 11:49:32.230892 == TX Byte 1 ==
2707 11:49:32.234157 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2708 11:49:32.237589 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2709 11:49:32.237693 ==
2710 11:49:32.240960 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 11:49:32.247660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2712 11:49:32.247738 ==
2713 11:49:32.257931 TX Vref=22, minBit 7, minWin=22, winSum=400
2714 11:49:32.262172 TX Vref=24, minBit 0, minWin=24, winSum=410
2715 11:49:32.265086 TX Vref=26, minBit 1, minWin=24, winSum=417
2716 11:49:32.268054 TX Vref=28, minBit 7, minWin=24, winSum=419
2717 11:49:32.271395 TX Vref=30, minBit 7, minWin=24, winSum=420
2718 11:49:32.274759 TX Vref=32, minBit 1, minWin=25, winSum=419
2719 11:49:32.281194 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 32
2720 11:49:32.281303
2721 11:49:32.284602 Final TX Range 1 Vref 32
2722 11:49:32.284676
2723 11:49:32.284737 ==
2724 11:49:32.288275 Dram Type= 6, Freq= 0, CH_0, rank 0
2725 11:49:32.291330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2726 11:49:32.291403 ==
2727 11:49:32.291464
2728 11:49:32.294830
2729 11:49:32.294899 TX Vref Scan disable
2730 11:49:32.297771 == TX Byte 0 ==
2731 11:49:32.301376 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2732 11:49:32.304735 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2733 11:49:32.308026 == TX Byte 1 ==
2734 11:49:32.311401 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2735 11:49:32.314729 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2736 11:49:32.314809
2737 11:49:32.317842 [DATLAT]
2738 11:49:32.317940 Freq=1200, CH0 RK0
2739 11:49:32.318030
2740 11:49:32.321257 DATLAT Default: 0xd
2741 11:49:32.321326 0, 0xFFFF, sum = 0
2742 11:49:32.324723 1, 0xFFFF, sum = 0
2743 11:49:32.324800 2, 0xFFFF, sum = 0
2744 11:49:32.327812 3, 0xFFFF, sum = 0
2745 11:49:32.327882 4, 0xFFFF, sum = 0
2746 11:49:32.331413 5, 0xFFFF, sum = 0
2747 11:49:32.331484 6, 0xFFFF, sum = 0
2748 11:49:32.334795 7, 0xFFFF, sum = 0
2749 11:49:32.338146 8, 0xFFFF, sum = 0
2750 11:49:32.338216 9, 0xFFFF, sum = 0
2751 11:49:32.341105 10, 0xFFFF, sum = 0
2752 11:49:32.341174 11, 0xFFFF, sum = 0
2753 11:49:32.344572 12, 0x0, sum = 1
2754 11:49:32.344646 13, 0x0, sum = 2
2755 11:49:32.348153 14, 0x0, sum = 3
2756 11:49:32.348223 15, 0x0, sum = 4
2757 11:49:32.348282 best_step = 13
2758 11:49:32.348339
2759 11:49:32.351208 ==
2760 11:49:32.351282 Dram Type= 6, Freq= 0, CH_0, rank 0
2761 11:49:32.358136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2762 11:49:32.358208 ==
2763 11:49:32.358268 RX Vref Scan: 1
2764 11:49:32.358324
2765 11:49:32.361539 Set Vref Range= 32 -> 127
2766 11:49:32.361605
2767 11:49:32.364695 RX Vref 32 -> 127, step: 1
2768 11:49:32.364777
2769 11:49:32.368448 RX Delay -13 -> 252, step: 4
2770 11:49:32.368524
2771 11:49:32.371794 Set Vref, RX VrefLevel [Byte0]: 32
2772 11:49:32.375074 [Byte1]: 32
2773 11:49:32.375143
2774 11:49:32.378011 Set Vref, RX VrefLevel [Byte0]: 33
2775 11:49:32.381362 [Byte1]: 33
2776 11:49:32.381432
2777 11:49:32.384833 Set Vref, RX VrefLevel [Byte0]: 34
2778 11:49:32.388035 [Byte1]: 34
2779 11:49:32.391971
2780 11:49:32.392056 Set Vref, RX VrefLevel [Byte0]: 35
2781 11:49:32.395445 [Byte1]: 35
2782 11:49:32.400041
2783 11:49:32.400122 Set Vref, RX VrefLevel [Byte0]: 36
2784 11:49:32.403589 [Byte1]: 36
2785 11:49:32.407837
2786 11:49:32.407918 Set Vref, RX VrefLevel [Byte0]: 37
2787 11:49:32.411087 [Byte1]: 37
2788 11:49:32.415909
2789 11:49:32.415991 Set Vref, RX VrefLevel [Byte0]: 38
2790 11:49:32.419155 [Byte1]: 38
2791 11:49:32.423470
2792 11:49:32.423552 Set Vref, RX VrefLevel [Byte0]: 39
2793 11:49:32.426996 [Byte1]: 39
2794 11:49:32.431554
2795 11:49:32.431651 Set Vref, RX VrefLevel [Byte0]: 40
2796 11:49:32.434806 [Byte1]: 40
2797 11:49:32.439554
2798 11:49:32.439657 Set Vref, RX VrefLevel [Byte0]: 41
2799 11:49:32.442976 [Byte1]: 41
2800 11:49:32.447379
2801 11:49:32.447489 Set Vref, RX VrefLevel [Byte0]: 42
2802 11:49:32.450795 [Byte1]: 42
2803 11:49:32.455071
2804 11:49:32.455190 Set Vref, RX VrefLevel [Byte0]: 43
2805 11:49:32.458498 [Byte1]: 43
2806 11:49:32.463277
2807 11:49:32.463360 Set Vref, RX VrefLevel [Byte0]: 44
2808 11:49:32.466270 [Byte1]: 44
2809 11:49:32.472038
2810 11:49:32.472122 Set Vref, RX VrefLevel [Byte0]: 45
2811 11:49:32.474018 [Byte1]: 45
2812 11:49:32.478931
2813 11:49:32.479073 Set Vref, RX VrefLevel [Byte0]: 46
2814 11:49:32.482613 [Byte1]: 46
2815 11:49:32.486580
2816 11:49:32.486684 Set Vref, RX VrefLevel [Byte0]: 47
2817 11:49:32.490127 [Byte1]: 47
2818 11:49:32.494985
2819 11:49:32.495066 Set Vref, RX VrefLevel [Byte0]: 48
2820 11:49:32.497915 [Byte1]: 48
2821 11:49:32.502345
2822 11:49:32.502463 Set Vref, RX VrefLevel [Byte0]: 49
2823 11:49:32.505782 [Byte1]: 49
2824 11:49:32.510536
2825 11:49:32.510618 Set Vref, RX VrefLevel [Byte0]: 50
2826 11:49:32.513728 [Byte1]: 50
2827 11:49:32.518679
2828 11:49:32.518847 Set Vref, RX VrefLevel [Byte0]: 51
2829 11:49:32.521627 [Byte1]: 51
2830 11:49:32.525996
2831 11:49:32.526106 Set Vref, RX VrefLevel [Byte0]: 52
2832 11:49:32.529548 [Byte1]: 52
2833 11:49:32.534104
2834 11:49:32.534270 Set Vref, RX VrefLevel [Byte0]: 53
2835 11:49:32.537559 [Byte1]: 53
2836 11:49:32.541983
2837 11:49:32.542097 Set Vref, RX VrefLevel [Byte0]: 54
2838 11:49:32.545218 [Byte1]: 54
2839 11:49:32.550082
2840 11:49:32.550183 Set Vref, RX VrefLevel [Byte0]: 55
2841 11:49:32.553512 [Byte1]: 55
2842 11:49:32.557768
2843 11:49:32.557873 Set Vref, RX VrefLevel [Byte0]: 56
2844 11:49:32.560902 [Byte1]: 56
2845 11:49:32.565546
2846 11:49:32.565631 Set Vref, RX VrefLevel [Byte0]: 57
2847 11:49:32.569261 [Byte1]: 57
2848 11:49:32.573393
2849 11:49:32.573506 Set Vref, RX VrefLevel [Byte0]: 58
2850 11:49:32.576869 [Byte1]: 58
2851 11:49:32.581642
2852 11:49:32.581754 Set Vref, RX VrefLevel [Byte0]: 59
2853 11:49:32.584685 [Byte1]: 59
2854 11:49:32.589175
2855 11:49:32.589267 Set Vref, RX VrefLevel [Byte0]: 60
2856 11:49:32.592673 [Byte1]: 60
2857 11:49:32.597204
2858 11:49:32.597288 Set Vref, RX VrefLevel [Byte0]: 61
2859 11:49:32.600784 [Byte1]: 61
2860 11:49:32.605169
2861 11:49:32.605254 Set Vref, RX VrefLevel [Byte0]: 62
2862 11:49:32.608491 [Byte1]: 62
2863 11:49:32.613134
2864 11:49:32.613218 Set Vref, RX VrefLevel [Byte0]: 63
2865 11:49:32.616135 [Byte1]: 63
2866 11:49:32.621064
2867 11:49:32.621175 Set Vref, RX VrefLevel [Byte0]: 64
2868 11:49:32.624275 [Byte1]: 64
2869 11:49:32.629297
2870 11:49:32.629403 Set Vref, RX VrefLevel [Byte0]: 65
2871 11:49:32.632004 [Byte1]: 65
2872 11:49:32.636718
2873 11:49:32.636824 Set Vref, RX VrefLevel [Byte0]: 66
2874 11:49:32.640065 [Byte1]: 66
2875 11:49:32.644688
2876 11:49:32.644788 Set Vref, RX VrefLevel [Byte0]: 67
2877 11:49:32.647936 [Byte1]: 67
2878 11:49:32.652938
2879 11:49:32.653037 Set Vref, RX VrefLevel [Byte0]: 68
2880 11:49:32.655884 [Byte1]: 68
2881 11:49:32.660414
2882 11:49:32.660498 Set Vref, RX VrefLevel [Byte0]: 69
2883 11:49:32.663447 [Byte1]: 69
2884 11:49:32.668182
2885 11:49:32.668275 Final RX Vref Byte 0 = 60 to rank0
2886 11:49:32.671445 Final RX Vref Byte 1 = 50 to rank0
2887 11:49:32.675045 Final RX Vref Byte 0 = 60 to rank1
2888 11:49:32.678365 Final RX Vref Byte 1 = 50 to rank1==
2889 11:49:32.681724 Dram Type= 6, Freq= 0, CH_0, rank 0
2890 11:49:32.685245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 11:49:32.688346 ==
2892 11:49:32.688430 DQS Delay:
2893 11:49:32.688497 DQS0 = 0, DQS1 = 0
2894 11:49:32.691737 DQM Delay:
2895 11:49:32.691831 DQM0 = 122, DQM1 = 109
2896 11:49:32.695015 DQ Delay:
2897 11:49:32.698328 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2898 11:49:32.701761 DQ4 =126, DQ5 =116, DQ6 =128, DQ7 =128
2899 11:49:32.704932 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =108
2900 11:49:32.708280 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2901 11:49:32.708393
2902 11:49:32.708487
2903 11:49:32.715085 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2904 11:49:32.718250 CH0 RK0: MR19=404, MR18=B08
2905 11:49:32.725222 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2906 11:49:32.725338
2907 11:49:32.728550 ----->DramcWriteLeveling(PI) begin...
2908 11:49:32.728654 ==
2909 11:49:32.731882 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 11:49:32.734960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 11:49:32.735049 ==
2912 11:49:32.738338 Write leveling (Byte 0): 34 => 34
2913 11:49:32.741627 Write leveling (Byte 1): 29 => 29
2914 11:49:32.745119 DramcWriteLeveling(PI) end<-----
2915 11:49:32.745230
2916 11:49:32.745324 ==
2917 11:49:32.748308 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 11:49:32.751938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 11:49:32.755097 ==
2920 11:49:32.755200 [Gating] SW mode calibration
2921 11:49:32.765296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2922 11:49:32.768271 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2923 11:49:32.772081 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
2924 11:49:32.778839 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 11:49:32.781798 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 11:49:32.785571 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 11:49:32.791908 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 11:49:32.795511 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 11:49:32.798618 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2930 11:49:32.802095 0 15 28 | B1->B0 | 2e2e 2c2c | 1 0 | (1 0) (0 0)
2931 11:49:32.808663 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 11:49:32.812070 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 11:49:32.815459 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 11:49:32.822354 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 11:49:32.825321 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 11:49:32.828750 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 11:49:32.835406 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2938 11:49:32.838663 1 0 28 | B1->B0 | 3c3c 3f3f | 0 0 | (0 0) (0 0)
2939 11:49:32.842280 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 11:49:32.848642 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 11:49:32.852185 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 11:49:32.855080 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 11:49:32.861982 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 11:49:32.865159 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 11:49:32.868269 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 11:49:32.875184 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2947 11:49:32.878608 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2948 11:49:32.881928 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 11:49:32.888437 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 11:49:32.891913 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 11:49:32.895717 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 11:49:32.898511 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 11:49:32.905797 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:49:32.909226 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:49:32.911979 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:49:32.918973 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:49:32.922191 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:49:32.925405 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 11:49:32.932351 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 11:49:32.935282 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 11:49:32.938768 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:49:32.945705 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2963 11:49:32.948923 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2964 11:49:32.952108 Total UI for P1: 0, mck2ui 16
2965 11:49:32.956177 best dqsien dly found for B1: ( 1, 3, 28)
2966 11:49:32.959473 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 11:49:32.962179 Total UI for P1: 0, mck2ui 16
2968 11:49:32.965603 best dqsien dly found for B0: ( 1, 3, 30)
2969 11:49:32.968936 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2970 11:49:32.972263 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2971 11:49:32.972369
2972 11:49:32.975832 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2973 11:49:32.982401 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2974 11:49:32.982527 [Gating] SW calibration Done
2975 11:49:32.982621 ==
2976 11:49:32.985447 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 11:49:32.992406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 11:49:32.992517 ==
2979 11:49:32.992609 RX Vref Scan: 0
2980 11:49:32.992781
2981 11:49:32.995862 RX Vref 0 -> 0, step: 1
2982 11:49:32.995938
2983 11:49:32.999050 RX Delay -40 -> 252, step: 8
2984 11:49:33.002705 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2985 11:49:33.005546 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2986 11:49:33.008961 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2987 11:49:33.012475 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2988 11:49:33.019074 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2989 11:49:33.022646 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2990 11:49:33.025713 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2991 11:49:33.029223 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2992 11:49:33.032483 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2993 11:49:33.035792 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2994 11:49:33.042690 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2995 11:49:33.046055 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2996 11:49:33.049569 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2997 11:49:33.052946 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2998 11:49:33.059265 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2999 11:49:33.062775 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3000 11:49:33.062852 ==
3001 11:49:33.066138 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 11:49:33.069533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 11:49:33.069634 ==
3004 11:49:33.069724 DQS Delay:
3005 11:49:33.072847 DQS0 = 0, DQS1 = 0
3006 11:49:33.072945 DQM Delay:
3007 11:49:33.075974 DQM0 = 120, DQM1 = 109
3008 11:49:33.076070 DQ Delay:
3009 11:49:33.079161 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3010 11:49:33.082585 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3011 11:49:33.085868 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3012 11:49:33.089551 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
3013 11:49:33.089653
3014 11:49:33.092658
3015 11:49:33.092756 ==
3016 11:49:33.096301 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 11:49:33.099521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 11:49:33.099625 ==
3019 11:49:33.099715
3020 11:49:33.099811
3021 11:49:33.102657 TX Vref Scan disable
3022 11:49:33.102739 == TX Byte 0 ==
3023 11:49:33.109473 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3024 11:49:33.112669 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3025 11:49:33.112777 == TX Byte 1 ==
3026 11:49:33.119515 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3027 11:49:33.122772 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3028 11:49:33.122847 ==
3029 11:49:33.125730 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 11:49:33.129598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 11:49:33.129671 ==
3032 11:49:33.141818 TX Vref=22, minBit 1, minWin=24, winSum=408
3033 11:49:33.145177 TX Vref=24, minBit 0, minWin=24, winSum=413
3034 11:49:33.148996 TX Vref=26, minBit 1, minWin=24, winSum=417
3035 11:49:33.152043 TX Vref=28, minBit 1, minWin=25, winSum=422
3036 11:49:33.155405 TX Vref=30, minBit 1, minWin=25, winSum=425
3037 11:49:33.158761 TX Vref=32, minBit 1, minWin=25, winSum=420
3038 11:49:33.165577 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 30
3039 11:49:33.165682
3040 11:49:33.168624 Final TX Range 1 Vref 30
3041 11:49:33.168721
3042 11:49:33.168809 ==
3043 11:49:33.172346 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 11:49:33.175569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 11:49:33.175640 ==
3046 11:49:33.175704
3047 11:49:33.175762
3048 11:49:33.178676 TX Vref Scan disable
3049 11:49:33.182223 == TX Byte 0 ==
3050 11:49:33.185525 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3051 11:49:33.189286 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3052 11:49:33.192349 == TX Byte 1 ==
3053 11:49:33.195477 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3054 11:49:33.198717 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3055 11:49:33.198791
3056 11:49:33.202217 [DATLAT]
3057 11:49:33.202324 Freq=1200, CH0 RK1
3058 11:49:33.202449
3059 11:49:33.205775 DATLAT Default: 0xd
3060 11:49:33.205910 0, 0xFFFF, sum = 0
3061 11:49:33.209087 1, 0xFFFF, sum = 0
3062 11:49:33.209191 2, 0xFFFF, sum = 0
3063 11:49:33.212067 3, 0xFFFF, sum = 0
3064 11:49:33.212177 4, 0xFFFF, sum = 0
3065 11:49:33.215470 5, 0xFFFF, sum = 0
3066 11:49:33.215583 6, 0xFFFF, sum = 0
3067 11:49:33.219681 7, 0xFFFF, sum = 0
3068 11:49:33.219794 8, 0xFFFF, sum = 0
3069 11:49:33.222216 9, 0xFFFF, sum = 0
3070 11:49:33.222344 10, 0xFFFF, sum = 0
3071 11:49:33.225616 11, 0xFFFF, sum = 0
3072 11:49:33.225719 12, 0x0, sum = 1
3073 11:49:33.229000 13, 0x0, sum = 2
3074 11:49:33.229108 14, 0x0, sum = 3
3075 11:49:33.232263 15, 0x0, sum = 4
3076 11:49:33.232366 best_step = 13
3077 11:49:33.232457
3078 11:49:33.232548 ==
3079 11:49:33.235518 Dram Type= 6, Freq= 0, CH_0, rank 1
3080 11:49:33.242342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 11:49:33.242483 ==
3082 11:49:33.242549 RX Vref Scan: 0
3083 11:49:33.242607
3084 11:49:33.245904 RX Vref 0 -> 0, step: 1
3085 11:49:33.246001
3086 11:49:33.249257 RX Delay -21 -> 252, step: 4
3087 11:49:33.252429 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3088 11:49:33.255522 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3089 11:49:33.258976 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3090 11:49:33.265823 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3091 11:49:33.269283 iDelay=195, Bit 4, Center 120 (51 ~ 190) 140
3092 11:49:33.272374 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3093 11:49:33.276006 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3094 11:49:33.279191 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3095 11:49:33.285850 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3096 11:49:33.289375 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3097 11:49:33.292962 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3098 11:49:33.295833 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3099 11:49:33.299253 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3100 11:49:33.305753 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3101 11:49:33.309313 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3102 11:49:33.312580 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3103 11:49:33.312683 ==
3104 11:49:33.316052 Dram Type= 6, Freq= 0, CH_0, rank 1
3105 11:49:33.319138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 11:49:33.319219 ==
3107 11:49:33.322528 DQS Delay:
3108 11:49:33.322603 DQS0 = 0, DQS1 = 0
3109 11:49:33.326108 DQM Delay:
3110 11:49:33.326203 DQM0 = 119, DQM1 = 107
3111 11:49:33.326291 DQ Delay:
3112 11:49:33.332835 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =112
3113 11:49:33.335858 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3114 11:49:33.339011 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3115 11:49:33.342621 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3116 11:49:33.342718
3117 11:49:33.342806
3118 11:49:33.349287 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3119 11:49:33.352824 CH0 RK1: MR19=403, MR18=10F7
3120 11:49:33.359490 CH0_RK1: MR19=0x403, MR18=0x10F7, DQSOSC=403, MR23=63, INC=40, DEC=26
3121 11:49:33.363033 [RxdqsGatingPostProcess] freq 1200
3122 11:49:33.366101 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3123 11:49:33.369300 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 11:49:33.372998 best DQS1 dly(2T, 0.5T) = (0, 11)
3125 11:49:33.376310 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 11:49:33.379460 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3127 11:49:33.382863 best DQS0 dly(2T, 0.5T) = (0, 11)
3128 11:49:33.386050 best DQS1 dly(2T, 0.5T) = (0, 11)
3129 11:49:33.389139 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3130 11:49:33.392732 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3131 11:49:33.396365 Pre-setting of DQS Precalculation
3132 11:49:33.399687 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3133 11:49:33.399789 ==
3134 11:49:33.402728 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 11:49:33.409172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 11:49:33.409274 ==
3137 11:49:33.412562 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3138 11:49:33.419418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3139 11:49:33.428029 [CA 0] Center 37 (7~68) winsize 62
3140 11:49:33.431518 [CA 1] Center 37 (7~68) winsize 62
3141 11:49:33.434685 [CA 2] Center 35 (5~65) winsize 61
3142 11:49:33.438270 [CA 3] Center 34 (4~65) winsize 62
3143 11:49:33.441494 [CA 4] Center 34 (4~64) winsize 61
3144 11:49:33.444957 [CA 5] Center 33 (3~64) winsize 62
3145 11:49:33.445045
3146 11:49:33.448511 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3147 11:49:33.448618
3148 11:49:33.451867 [CATrainingPosCal] consider 1 rank data
3149 11:49:33.454713 u2DelayCellTimex100 = 270/100 ps
3150 11:49:33.458287 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3151 11:49:33.461689 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3152 11:49:33.468308 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3153 11:49:33.471869 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3154 11:49:33.475057 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 11:49:33.478018 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3156 11:49:33.478121
3157 11:49:33.481737 CA PerBit enable=1, Macro0, CA PI delay=33
3158 11:49:33.481837
3159 11:49:33.484989 [CBTSetCACLKResult] CA Dly = 33
3160 11:49:33.485100 CS Dly: 5 (0~36)
3161 11:49:33.485191 ==
3162 11:49:33.488059 Dram Type= 6, Freq= 0, CH_1, rank 1
3163 11:49:33.494967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 11:49:33.495053 ==
3165 11:49:33.498636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3166 11:49:33.505010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3167 11:49:33.513707 [CA 0] Center 38 (8~68) winsize 61
3168 11:49:33.517502 [CA 1] Center 38 (8~69) winsize 62
3169 11:49:33.520514 [CA 2] Center 35 (5~66) winsize 62
3170 11:49:33.524240 [CA 3] Center 34 (4~65) winsize 62
3171 11:49:33.527379 [CA 4] Center 35 (5~65) winsize 61
3172 11:49:33.530366 [CA 5] Center 34 (4~64) winsize 61
3173 11:49:33.530464
3174 11:49:33.533628 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3175 11:49:33.533723
3176 11:49:33.537013 [CATrainingPosCal] consider 2 rank data
3177 11:49:33.540299 u2DelayCellTimex100 = 270/100 ps
3178 11:49:33.543820 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3179 11:49:33.547132 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3180 11:49:33.553704 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3181 11:49:33.557312 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3182 11:49:33.560270 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3183 11:49:33.563728 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3184 11:49:33.563839
3185 11:49:33.566996 CA PerBit enable=1, Macro0, CA PI delay=34
3186 11:49:33.567071
3187 11:49:33.570623 [CBTSetCACLKResult] CA Dly = 34
3188 11:49:33.570706 CS Dly: 6 (0~39)
3189 11:49:33.570771
3190 11:49:33.574005 ----->DramcWriteLeveling(PI) begin...
3191 11:49:33.577231 ==
3192 11:49:33.577313 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 11:49:33.583955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 11:49:33.584039 ==
3195 11:49:33.587389 Write leveling (Byte 0): 25 => 25
3196 11:49:33.590502 Write leveling (Byte 1): 27 => 27
3197 11:49:33.593781 DramcWriteLeveling(PI) end<-----
3198 11:49:33.593864
3199 11:49:33.593929 ==
3200 11:49:33.597561 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 11:49:33.600483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 11:49:33.600565 ==
3203 11:49:33.603884 [Gating] SW mode calibration
3204 11:49:33.610717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3205 11:49:33.613931 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3206 11:49:33.620947 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 11:49:33.624338 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 11:49:33.627577 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 11:49:33.634026 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 11:49:33.637610 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 11:49:33.640982 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3212 11:49:33.648035 0 15 24 | B1->B0 | 3131 2828 | 1 0 | (1 0) (0 0)
3213 11:49:33.651219 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3214 11:49:33.654917 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 11:49:33.657746 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 11:49:33.664351 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 11:49:33.668018 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 11:49:33.671141 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 11:49:33.677669 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3220 11:49:33.680835 1 0 24 | B1->B0 | 3939 4343 | 0 0 | (1 1) (0 0)
3221 11:49:33.684072 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 11:49:33.691222 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 11:49:33.694268 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 11:49:33.698013 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 11:49:33.704530 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 11:49:33.707856 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 11:49:33.710851 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 11:49:33.717678 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3229 11:49:33.721002 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3230 11:49:33.724349 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 11:49:33.730926 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 11:49:33.734725 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 11:49:33.737577 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 11:49:33.744182 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 11:49:33.747517 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:49:33.751435 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:49:33.754163 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:49:33.760847 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:49:33.764353 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:49:33.767770 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:49:33.774365 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 11:49:33.777802 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 11:49:33.781080 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3244 11:49:33.787674 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3245 11:49:33.790882 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3246 11:49:33.794252 Total UI for P1: 0, mck2ui 16
3247 11:49:33.797699 best dqsien dly found for B0: ( 1, 3, 22)
3248 11:49:33.801181 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 11:49:33.804424 Total UI for P1: 0, mck2ui 16
3250 11:49:33.807636 best dqsien dly found for B1: ( 1, 3, 26)
3251 11:49:33.811079 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3252 11:49:33.814183 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3253 11:49:33.814291
3254 11:49:33.821099 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3255 11:49:33.824349 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3256 11:49:33.824433 [Gating] SW calibration Done
3257 11:49:33.827552 ==
3258 11:49:33.827628 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 11:49:33.834366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 11:49:33.834492 ==
3261 11:49:33.834559 RX Vref Scan: 0
3262 11:49:33.834621
3263 11:49:33.837735 RX Vref 0 -> 0, step: 1
3264 11:49:33.837817
3265 11:49:33.840779 RX Delay -40 -> 252, step: 8
3266 11:49:33.844290 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3267 11:49:33.847683 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3268 11:49:33.851063 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3269 11:49:33.857534 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3270 11:49:33.861094 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3271 11:49:33.864327 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3272 11:49:33.867674 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3273 11:49:33.871119 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3274 11:49:33.874552 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3275 11:49:33.881194 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3276 11:49:33.884309 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3277 11:49:33.887562 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3278 11:49:33.891104 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3279 11:49:33.894444 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3280 11:49:33.901543 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3281 11:49:33.904768 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3282 11:49:33.904844 ==
3283 11:49:33.908045 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 11:49:33.911431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 11:49:33.911514 ==
3286 11:49:33.914734 DQS Delay:
3287 11:49:33.914815 DQS0 = 0, DQS1 = 0
3288 11:49:33.914880 DQM Delay:
3289 11:49:33.917962 DQM0 = 120, DQM1 = 113
3290 11:49:33.918044 DQ Delay:
3291 11:49:33.921375 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3292 11:49:33.924529 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3293 11:49:33.928222 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3294 11:49:33.934575 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3295 11:49:33.934654
3296 11:49:33.934717
3297 11:49:33.934776 ==
3298 11:49:33.938096 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 11:49:33.941509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 11:49:33.941609 ==
3301 11:49:33.941704
3302 11:49:33.941792
3303 11:49:33.944867 TX Vref Scan disable
3304 11:49:33.944972 == TX Byte 0 ==
3305 11:49:33.951885 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3306 11:49:33.955020 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3307 11:49:33.955122 == TX Byte 1 ==
3308 11:49:33.961503 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3309 11:49:33.964718 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3310 11:49:33.964820 ==
3311 11:49:33.967937 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 11:49:33.971403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 11:49:33.971515 ==
3314 11:49:33.983496 TX Vref=22, minBit 7, minWin=24, winSum=405
3315 11:49:33.987255 TX Vref=24, minBit 11, minWin=24, winSum=411
3316 11:49:33.990416 TX Vref=26, minBit 3, minWin=25, winSum=416
3317 11:49:33.993443 TX Vref=28, minBit 9, minWin=25, winSum=419
3318 11:49:33.997069 TX Vref=30, minBit 10, minWin=25, winSum=420
3319 11:49:34.003692 TX Vref=32, minBit 10, minWin=25, winSum=421
3320 11:49:34.007068 [TxChooseVref] Worse bit 10, Min win 25, Win sum 421, Final Vref 32
3321 11:49:34.007143
3322 11:49:34.010752 Final TX Range 1 Vref 32
3323 11:49:34.010826
3324 11:49:34.010888 ==
3325 11:49:34.013893 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 11:49:34.017162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 11:49:34.017269 ==
3328 11:49:34.020366
3329 11:49:34.020464
3330 11:49:34.020554 TX Vref Scan disable
3331 11:49:34.023913 == TX Byte 0 ==
3332 11:49:34.027238 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3333 11:49:34.030289 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3334 11:49:34.033910 == TX Byte 1 ==
3335 11:49:34.037075 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3336 11:49:34.040548 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3337 11:49:34.044075
3338 11:49:34.044181 [DATLAT]
3339 11:49:34.044283 Freq=1200, CH1 RK0
3340 11:49:34.044378
3341 11:49:34.047067 DATLAT Default: 0xd
3342 11:49:34.047170 0, 0xFFFF, sum = 0
3343 11:49:34.050466 1, 0xFFFF, sum = 0
3344 11:49:34.050547 2, 0xFFFF, sum = 0
3345 11:49:34.053881 3, 0xFFFF, sum = 0
3346 11:49:34.053994 4, 0xFFFF, sum = 0
3347 11:49:34.057074 5, 0xFFFF, sum = 0
3348 11:49:34.057177 6, 0xFFFF, sum = 0
3349 11:49:34.060726 7, 0xFFFF, sum = 0
3350 11:49:34.063900 8, 0xFFFF, sum = 0
3351 11:49:34.063999 9, 0xFFFF, sum = 0
3352 11:49:34.067410 10, 0xFFFF, sum = 0
3353 11:49:34.067510 11, 0xFFFF, sum = 0
3354 11:49:34.070581 12, 0x0, sum = 1
3355 11:49:34.070680 13, 0x0, sum = 2
3356 11:49:34.070775 14, 0x0, sum = 3
3357 11:49:34.074028 15, 0x0, sum = 4
3358 11:49:34.074125 best_step = 13
3359 11:49:34.074227
3360 11:49:34.077172 ==
3361 11:49:34.077270 Dram Type= 6, Freq= 0, CH_1, rank 0
3362 11:49:34.083872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3363 11:49:34.083974 ==
3364 11:49:34.084050 RX Vref Scan: 1
3365 11:49:34.084113
3366 11:49:34.087127 Set Vref Range= 32 -> 127
3367 11:49:34.087230
3368 11:49:34.090561 RX Vref 32 -> 127, step: 1
3369 11:49:34.090648
3370 11:49:34.093836 RX Delay -13 -> 252, step: 4
3371 11:49:34.093942
3372 11:49:34.097350 Set Vref, RX VrefLevel [Byte0]: 32
3373 11:49:34.100999 [Byte1]: 32
3374 11:49:34.101103
3375 11:49:34.104041 Set Vref, RX VrefLevel [Byte0]: 33
3376 11:49:34.107446 [Byte1]: 33
3377 11:49:34.107546
3378 11:49:34.110553 Set Vref, RX VrefLevel [Byte0]: 34
3379 11:49:34.113963 [Byte1]: 34
3380 11:49:34.118032
3381 11:49:34.118136 Set Vref, RX VrefLevel [Byte0]: 35
3382 11:49:34.121389 [Byte1]: 35
3383 11:49:34.126083
3384 11:49:34.126180 Set Vref, RX VrefLevel [Byte0]: 36
3385 11:49:34.129349 [Byte1]: 36
3386 11:49:34.133801
3387 11:49:34.133903 Set Vref, RX VrefLevel [Byte0]: 37
3388 11:49:34.136862 [Byte1]: 37
3389 11:49:34.141636
3390 11:49:34.141743 Set Vref, RX VrefLevel [Byte0]: 38
3391 11:49:34.145057 [Byte1]: 38
3392 11:49:34.149854
3393 11:49:34.149953 Set Vref, RX VrefLevel [Byte0]: 39
3394 11:49:34.153098 [Byte1]: 39
3395 11:49:34.157542
3396 11:49:34.157619 Set Vref, RX VrefLevel [Byte0]: 40
3397 11:49:34.160765 [Byte1]: 40
3398 11:49:34.165368
3399 11:49:34.165439 Set Vref, RX VrefLevel [Byte0]: 41
3400 11:49:34.168864 [Byte1]: 41
3401 11:49:34.173218
3402 11:49:34.173287 Set Vref, RX VrefLevel [Byte0]: 42
3403 11:49:34.176464 [Byte1]: 42
3404 11:49:34.181196
3405 11:49:34.181267 Set Vref, RX VrefLevel [Byte0]: 43
3406 11:49:34.184293 [Byte1]: 43
3407 11:49:34.189088
3408 11:49:34.189186 Set Vref, RX VrefLevel [Byte0]: 44
3409 11:49:34.192629 [Byte1]: 44
3410 11:49:34.197023
3411 11:49:34.197121 Set Vref, RX VrefLevel [Byte0]: 45
3412 11:49:34.200095 [Byte1]: 45
3413 11:49:34.204846
3414 11:49:34.204943 Set Vref, RX VrefLevel [Byte0]: 46
3415 11:49:34.207969 [Byte1]: 46
3416 11:49:34.212458
3417 11:49:34.212554 Set Vref, RX VrefLevel [Byte0]: 47
3418 11:49:34.215818 [Byte1]: 47
3419 11:49:34.220820
3420 11:49:34.220921 Set Vref, RX VrefLevel [Byte0]: 48
3421 11:49:34.223673 [Byte1]: 48
3422 11:49:34.228608
3423 11:49:34.228705 Set Vref, RX VrefLevel [Byte0]: 49
3424 11:49:34.231671 [Byte1]: 49
3425 11:49:34.236116
3426 11:49:34.236212 Set Vref, RX VrefLevel [Byte0]: 50
3427 11:49:34.239634 [Byte1]: 50
3428 11:49:34.244220
3429 11:49:34.244319 Set Vref, RX VrefLevel [Byte0]: 51
3430 11:49:34.247483 [Byte1]: 51
3431 11:49:34.252048
3432 11:49:34.252156 Set Vref, RX VrefLevel [Byte0]: 52
3433 11:49:34.255396 [Byte1]: 52
3434 11:49:34.260066
3435 11:49:34.260166 Set Vref, RX VrefLevel [Byte0]: 53
3436 11:49:34.263372 [Byte1]: 53
3437 11:49:34.267807
3438 11:49:34.267909 Set Vref, RX VrefLevel [Byte0]: 54
3439 11:49:34.271131 [Byte1]: 54
3440 11:49:34.276025
3441 11:49:34.276129 Set Vref, RX VrefLevel [Byte0]: 55
3442 11:49:34.279077 [Byte1]: 55
3443 11:49:34.283482
3444 11:49:34.283599 Set Vref, RX VrefLevel [Byte0]: 56
3445 11:49:34.286860 [Byte1]: 56
3446 11:49:34.291799
3447 11:49:34.291903 Set Vref, RX VrefLevel [Byte0]: 57
3448 11:49:34.295331 [Byte1]: 57
3449 11:49:34.299312
3450 11:49:34.299414 Set Vref, RX VrefLevel [Byte0]: 58
3451 11:49:34.302599 [Byte1]: 58
3452 11:49:34.307341
3453 11:49:34.307439 Set Vref, RX VrefLevel [Byte0]: 59
3454 11:49:34.310634 [Byte1]: 59
3455 11:49:34.315263
3456 11:49:34.315365 Set Vref, RX VrefLevel [Byte0]: 60
3457 11:49:34.318616 [Byte1]: 60
3458 11:49:34.322901
3459 11:49:34.323003 Set Vref, RX VrefLevel [Byte0]: 61
3460 11:49:34.326251 [Byte1]: 61
3461 11:49:34.330971
3462 11:49:34.331078 Set Vref, RX VrefLevel [Byte0]: 62
3463 11:49:34.334135 [Byte1]: 62
3464 11:49:34.338959
3465 11:49:34.339041 Set Vref, RX VrefLevel [Byte0]: 63
3466 11:49:34.342273 [Byte1]: 63
3467 11:49:34.346660
3468 11:49:34.349907 Set Vref, RX VrefLevel [Byte0]: 64
3469 11:49:34.353284 [Byte1]: 64
3470 11:49:34.353384
3471 11:49:34.356608 Set Vref, RX VrefLevel [Byte0]: 65
3472 11:49:34.360145 [Byte1]: 65
3473 11:49:34.360245
3474 11:49:34.363249 Set Vref, RX VrefLevel [Byte0]: 66
3475 11:49:34.366531 [Byte1]: 66
3476 11:49:34.370238
3477 11:49:34.370339 Final RX Vref Byte 0 = 52 to rank0
3478 11:49:34.373763 Final RX Vref Byte 1 = 52 to rank0
3479 11:49:34.377178 Final RX Vref Byte 0 = 52 to rank1
3480 11:49:34.380369 Final RX Vref Byte 1 = 52 to rank1==
3481 11:49:34.383518 Dram Type= 6, Freq= 0, CH_1, rank 0
3482 11:49:34.390345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3483 11:49:34.390483 ==
3484 11:49:34.390578 DQS Delay:
3485 11:49:34.390665 DQS0 = 0, DQS1 = 0
3486 11:49:34.393749 DQM Delay:
3487 11:49:34.393849 DQM0 = 119, DQM1 = 112
3488 11:49:34.397083 DQ Delay:
3489 11:49:34.400548 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3490 11:49:34.403344 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3491 11:49:34.406785 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3492 11:49:34.410517 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3493 11:49:34.410591
3494 11:49:34.410677
3495 11:49:34.420368 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3496 11:49:34.420475 CH1 RK0: MR19=404, MR18=417
3497 11:49:34.427223 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3498 11:49:34.427324
3499 11:49:34.430224 ----->DramcWriteLeveling(PI) begin...
3500 11:49:34.430322 ==
3501 11:49:34.433508 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 11:49:34.436886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 11:49:34.439954 ==
3504 11:49:34.440056 Write leveling (Byte 0): 24 => 24
3505 11:49:34.443596 Write leveling (Byte 1): 28 => 28
3506 11:49:34.446749 DramcWriteLeveling(PI) end<-----
3507 11:49:34.446849
3508 11:49:34.446941 ==
3509 11:49:34.450140 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 11:49:34.456553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 11:49:34.456661 ==
3512 11:49:34.460075 [Gating] SW mode calibration
3513 11:49:34.466667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3514 11:49:34.470096 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3515 11:49:34.477048 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 11:49:34.480240 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 11:49:34.483217 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 11:49:34.486848 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 11:49:34.493802 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 11:49:34.496996 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3521 11:49:34.500198 0 15 24 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 0)
3522 11:49:34.507074 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3523 11:49:34.510243 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 11:49:34.513835 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 11:49:34.520586 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 11:49:34.524278 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 11:49:34.526933 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 11:49:34.533469 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 11:49:34.536813 1 0 24 | B1->B0 | 3c3c 2e2e | 0 0 | (0 0) (0 0)
3530 11:49:34.540526 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3531 11:49:34.547121 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 11:49:34.550489 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 11:49:34.553567 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 11:49:34.560123 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 11:49:34.563493 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 11:49:34.567323 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 11:49:34.570230 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3538 11:49:34.576939 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 11:49:34.579902 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:49:34.583211 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 11:49:34.590236 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 11:49:34.593290 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:49:34.596524 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:49:34.603258 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:49:34.606643 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:49:34.609871 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:49:34.616450 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:49:34.620125 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:49:34.623043 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:49:34.629706 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:49:34.633057 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:49:34.636582 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 11:49:34.643098 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3554 11:49:34.646348 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 11:49:34.649710 Total UI for P1: 0, mck2ui 16
3556 11:49:34.653517 best dqsien dly found for B0: ( 1, 3, 24)
3557 11:49:34.656593 Total UI for P1: 0, mck2ui 16
3558 11:49:34.659644 best dqsien dly found for B1: ( 1, 3, 24)
3559 11:49:34.663361 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3560 11:49:34.666302 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3561 11:49:34.666439
3562 11:49:34.669848 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3563 11:49:34.672730 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3564 11:49:34.676084 [Gating] SW calibration Done
3565 11:49:34.676181 ==
3566 11:49:34.679848 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 11:49:34.682803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 11:49:34.686283 ==
3569 11:49:34.686405 RX Vref Scan: 0
3570 11:49:34.686517
3571 11:49:34.689366 RX Vref 0 -> 0, step: 1
3572 11:49:34.689466
3573 11:49:34.692689 RX Delay -40 -> 252, step: 8
3574 11:49:34.696228 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3575 11:49:34.699346 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3576 11:49:34.702793 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3577 11:49:34.706039 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3578 11:49:34.713061 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3579 11:49:34.716097 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3580 11:49:34.719404 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3581 11:49:34.722627 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3582 11:49:34.726537 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3583 11:49:34.729526 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3584 11:49:34.735803 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3585 11:49:34.739282 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3586 11:49:34.742420 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3587 11:49:34.746356 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3588 11:49:34.752392 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3589 11:49:34.755694 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3590 11:49:34.755778 ==
3591 11:49:34.759092 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 11:49:34.762611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 11:49:34.762695 ==
3594 11:49:34.765629 DQS Delay:
3595 11:49:34.765712 DQS0 = 0, DQS1 = 0
3596 11:49:34.765778 DQM Delay:
3597 11:49:34.769466 DQM0 = 120, DQM1 = 113
3598 11:49:34.769549 DQ Delay:
3599 11:49:34.772435 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3600 11:49:34.775936 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3601 11:49:34.778987 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3602 11:49:34.785758 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3603 11:49:34.785856
3604 11:49:34.785921
3605 11:49:34.785982 ==
3606 11:49:34.789079 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 11:49:34.792352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 11:49:34.792451 ==
3609 11:49:34.792518
3610 11:49:34.792578
3611 11:49:34.795946 TX Vref Scan disable
3612 11:49:34.796044 == TX Byte 0 ==
3613 11:49:34.802615 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3614 11:49:34.805706 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3615 11:49:34.805804 == TX Byte 1 ==
3616 11:49:34.812449 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3617 11:49:34.816028 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3618 11:49:34.816140 ==
3619 11:49:34.819187 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 11:49:34.822449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 11:49:34.822536 ==
3622 11:49:34.834926 TX Vref=22, minBit 1, minWin=25, winSum=416
3623 11:49:34.838007 TX Vref=24, minBit 9, minWin=25, winSum=421
3624 11:49:34.842072 TX Vref=26, minBit 3, minWin=26, winSum=427
3625 11:49:34.845040 TX Vref=28, minBit 3, minWin=26, winSum=430
3626 11:49:34.848100 TX Vref=30, minBit 1, minWin=26, winSum=428
3627 11:49:34.851590 TX Vref=32, minBit 1, minWin=26, winSum=427
3628 11:49:34.858237 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 28
3629 11:49:34.858319
3630 11:49:34.862100 Final TX Range 1 Vref 28
3631 11:49:34.862175
3632 11:49:34.862276 ==
3633 11:49:34.864944 Dram Type= 6, Freq= 0, CH_1, rank 1
3634 11:49:34.868294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3635 11:49:34.868377 ==
3636 11:49:34.868456
3637 11:49:34.871473
3638 11:49:34.871547 TX Vref Scan disable
3639 11:49:34.874851 == TX Byte 0 ==
3640 11:49:34.878077 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3641 11:49:34.881702 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3642 11:49:34.884757 == TX Byte 1 ==
3643 11:49:34.888181 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3644 11:49:34.891294 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3645 11:49:34.895020
3646 11:49:34.895097 [DATLAT]
3647 11:49:34.895178 Freq=1200, CH1 RK1
3648 11:49:34.895258
3649 11:49:34.898243 DATLAT Default: 0xd
3650 11:49:34.898316 0, 0xFFFF, sum = 0
3651 11:49:34.901551 1, 0xFFFF, sum = 0
3652 11:49:34.901641 2, 0xFFFF, sum = 0
3653 11:49:34.904651 3, 0xFFFF, sum = 0
3654 11:49:34.904725 4, 0xFFFF, sum = 0
3655 11:49:34.907972 5, 0xFFFF, sum = 0
3656 11:49:34.911130 6, 0xFFFF, sum = 0
3657 11:49:34.911218 7, 0xFFFF, sum = 0
3658 11:49:34.914633 8, 0xFFFF, sum = 0
3659 11:49:34.914714 9, 0xFFFF, sum = 0
3660 11:49:34.918076 10, 0xFFFF, sum = 0
3661 11:49:34.918149 11, 0xFFFF, sum = 0
3662 11:49:34.921238 12, 0x0, sum = 1
3663 11:49:34.921314 13, 0x0, sum = 2
3664 11:49:34.924974 14, 0x0, sum = 3
3665 11:49:34.925050 15, 0x0, sum = 4
3666 11:49:34.925112 best_step = 13
3667 11:49:34.927804
3668 11:49:34.927884 ==
3669 11:49:34.931525 Dram Type= 6, Freq= 0, CH_1, rank 1
3670 11:49:34.934561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3671 11:49:34.934637 ==
3672 11:49:34.934697 RX Vref Scan: 0
3673 11:49:34.934754
3674 11:49:34.938060 RX Vref 0 -> 0, step: 1
3675 11:49:34.938127
3676 11:49:34.941166 RX Delay -13 -> 252, step: 4
3677 11:49:34.944815 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3678 11:49:34.951233 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3679 11:49:34.954869 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3680 11:49:34.958052 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3681 11:49:34.961340 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3682 11:49:34.964471 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3683 11:49:34.971284 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3684 11:49:34.974314 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3685 11:49:34.977917 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3686 11:49:34.981629 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3687 11:49:34.984604 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3688 11:49:34.990948 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3689 11:49:34.994639 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3690 11:49:34.997931 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3691 11:49:35.001680 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3692 11:49:35.004369 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3693 11:49:35.007569 ==
3694 11:49:35.007648 Dram Type= 6, Freq= 0, CH_1, rank 1
3695 11:49:35.014530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3696 11:49:35.014615 ==
3697 11:49:35.014677 DQS Delay:
3698 11:49:35.017889 DQS0 = 0, DQS1 = 0
3699 11:49:35.017960 DQM Delay:
3700 11:49:35.021202 DQM0 = 119, DQM1 = 113
3701 11:49:35.021286 DQ Delay:
3702 11:49:35.024351 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3703 11:49:35.027876 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3704 11:49:35.030800 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =108
3705 11:49:35.034179 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3706 11:49:35.034275
3707 11:49:35.034347
3708 11:49:35.044189 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 406 ps
3709 11:49:35.044265 CH1 RK1: MR19=403, MR18=8EC
3710 11:49:35.050839 CH1_RK1: MR19=0x403, MR18=0x8EC, DQSOSC=406, MR23=63, INC=39, DEC=26
3711 11:49:35.053969 [RxdqsGatingPostProcess] freq 1200
3712 11:49:35.060601 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3713 11:49:35.063878 best DQS0 dly(2T, 0.5T) = (0, 11)
3714 11:49:35.067507 best DQS1 dly(2T, 0.5T) = (0, 11)
3715 11:49:35.070786 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3716 11:49:35.074332 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3717 11:49:35.077433 best DQS0 dly(2T, 0.5T) = (0, 11)
3718 11:49:35.077569 best DQS1 dly(2T, 0.5T) = (0, 11)
3719 11:49:35.080845 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3720 11:49:35.084108 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3721 11:49:35.087951 Pre-setting of DQS Precalculation
3722 11:49:35.094269 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3723 11:49:35.100316 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3724 11:49:35.107471 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3725 11:49:35.107555
3726 11:49:35.107621
3727 11:49:35.110591 [Calibration Summary] 2400 Mbps
3728 11:49:35.113717 CH 0, Rank 0
3729 11:49:35.113806 SW Impedance : PASS
3730 11:49:35.117321 DUTY Scan : NO K
3731 11:49:35.120861 ZQ Calibration : PASS
3732 11:49:35.120946 Jitter Meter : NO K
3733 11:49:35.123674 CBT Training : PASS
3734 11:49:35.123758 Write leveling : PASS
3735 11:49:35.127332 RX DQS gating : PASS
3736 11:49:35.130510 RX DQ/DQS(RDDQC) : PASS
3737 11:49:35.130594 TX DQ/DQS : PASS
3738 11:49:35.133522 RX DATLAT : PASS
3739 11:49:35.136953 RX DQ/DQS(Engine): PASS
3740 11:49:35.137037 TX OE : NO K
3741 11:49:35.140047 All Pass.
3742 11:49:35.140131
3743 11:49:35.140197 CH 0, Rank 1
3744 11:49:35.143341 SW Impedance : PASS
3745 11:49:35.143424 DUTY Scan : NO K
3746 11:49:35.146570 ZQ Calibration : PASS
3747 11:49:35.150119 Jitter Meter : NO K
3748 11:49:35.150203 CBT Training : PASS
3749 11:49:35.153231 Write leveling : PASS
3750 11:49:35.156477 RX DQS gating : PASS
3751 11:49:35.156575 RX DQ/DQS(RDDQC) : PASS
3752 11:49:35.160034 TX DQ/DQS : PASS
3753 11:49:35.163168 RX DATLAT : PASS
3754 11:49:35.163252 RX DQ/DQS(Engine): PASS
3755 11:49:35.166738 TX OE : NO K
3756 11:49:35.166825 All Pass.
3757 11:49:35.166891
3758 11:49:35.170090 CH 1, Rank 0
3759 11:49:35.170173 SW Impedance : PASS
3760 11:49:35.173407 DUTY Scan : NO K
3761 11:49:35.176901 ZQ Calibration : PASS
3762 11:49:35.176985 Jitter Meter : NO K
3763 11:49:35.180187 CBT Training : PASS
3764 11:49:35.180270 Write leveling : PASS
3765 11:49:35.183643 RX DQS gating : PASS
3766 11:49:35.186810 RX DQ/DQS(RDDQC) : PASS
3767 11:49:35.186894 TX DQ/DQS : PASS
3768 11:49:35.190167 RX DATLAT : PASS
3769 11:49:35.193368 RX DQ/DQS(Engine): PASS
3770 11:49:35.193452 TX OE : NO K
3771 11:49:35.197230 All Pass.
3772 11:49:35.197313
3773 11:49:35.197380 CH 1, Rank 1
3774 11:49:35.200256 SW Impedance : PASS
3775 11:49:35.200340 DUTY Scan : NO K
3776 11:49:35.203154 ZQ Calibration : PASS
3777 11:49:35.206964 Jitter Meter : NO K
3778 11:49:35.207048 CBT Training : PASS
3779 11:49:35.209909 Write leveling : PASS
3780 11:49:35.213391 RX DQS gating : PASS
3781 11:49:35.213474 RX DQ/DQS(RDDQC) : PASS
3782 11:49:35.217019 TX DQ/DQS : PASS
3783 11:49:35.220302 RX DATLAT : PASS
3784 11:49:35.220386 RX DQ/DQS(Engine): PASS
3785 11:49:35.223392 TX OE : NO K
3786 11:49:35.223476 All Pass.
3787 11:49:35.223542
3788 11:49:35.226609 DramC Write-DBI off
3789 11:49:35.230126 PER_BANK_REFRESH: Hybrid Mode
3790 11:49:35.230210 TX_TRACKING: ON
3791 11:49:35.240014 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3792 11:49:35.243509 [FAST_K] Save calibration result to emmc
3793 11:49:35.246582 dramc_set_vcore_voltage set vcore to 650000
3794 11:49:35.249850 Read voltage for 600, 5
3795 11:49:35.249934 Vio18 = 0
3796 11:49:35.250000 Vcore = 650000
3797 11:49:35.253265 Vdram = 0
3798 11:49:35.253401 Vddq = 0
3799 11:49:35.253469 Vmddr = 0
3800 11:49:35.259862 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3801 11:49:35.263355 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3802 11:49:35.266305 MEM_TYPE=3, freq_sel=19
3803 11:49:35.269928 sv_algorithm_assistance_LP4_1600
3804 11:49:35.273224 ============ PULL DRAM RESETB DOWN ============
3805 11:49:35.276562 ========== PULL DRAM RESETB DOWN end =========
3806 11:49:35.282905 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3807 11:49:35.286111 ===================================
3808 11:49:35.286220 LPDDR4 DRAM CONFIGURATION
3809 11:49:35.289304 ===================================
3810 11:49:35.292835 EX_ROW_EN[0] = 0x0
3811 11:49:35.296391 EX_ROW_EN[1] = 0x0
3812 11:49:35.296474 LP4Y_EN = 0x0
3813 11:49:35.299290 WORK_FSP = 0x0
3814 11:49:35.299373 WL = 0x2
3815 11:49:35.302724 RL = 0x2
3816 11:49:35.302808 BL = 0x2
3817 11:49:35.306024 RPST = 0x0
3818 11:49:35.306107 RD_PRE = 0x0
3819 11:49:35.309946 WR_PRE = 0x1
3820 11:49:35.310029 WR_PST = 0x0
3821 11:49:35.313235 DBI_WR = 0x0
3822 11:49:35.313318 DBI_RD = 0x0
3823 11:49:35.316589 OTF = 0x1
3824 11:49:35.319615 ===================================
3825 11:49:35.323369 ===================================
3826 11:49:35.323453 ANA top config
3827 11:49:35.326371 ===================================
3828 11:49:35.329730 DLL_ASYNC_EN = 0
3829 11:49:35.332743 ALL_SLAVE_EN = 1
3830 11:49:35.336037 NEW_RANK_MODE = 1
3831 11:49:35.336122 DLL_IDLE_MODE = 1
3832 11:49:35.340199 LP45_APHY_COMB_EN = 1
3833 11:49:35.342886 TX_ODT_DIS = 1
3834 11:49:35.346137 NEW_8X_MODE = 1
3835 11:49:35.349316 ===================================
3836 11:49:35.352850 ===================================
3837 11:49:35.352934 data_rate = 1200
3838 11:49:35.356016 CKR = 1
3839 11:49:35.359493 DQ_P2S_RATIO = 8
3840 11:49:35.362608 ===================================
3841 11:49:35.366089 CA_P2S_RATIO = 8
3842 11:49:35.369462 DQ_CA_OPEN = 0
3843 11:49:35.372854 DQ_SEMI_OPEN = 0
3844 11:49:35.372977 CA_SEMI_OPEN = 0
3845 11:49:35.376073 CA_FULL_RATE = 0
3846 11:49:35.379285 DQ_CKDIV4_EN = 1
3847 11:49:35.382849 CA_CKDIV4_EN = 1
3848 11:49:35.386110 CA_PREDIV_EN = 0
3849 11:49:35.389534 PH8_DLY = 0
3850 11:49:35.389618 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3851 11:49:35.392621 DQ_AAMCK_DIV = 4
3852 11:49:35.396177 CA_AAMCK_DIV = 4
3853 11:49:35.399451 CA_ADMCK_DIV = 4
3854 11:49:35.402515 DQ_TRACK_CA_EN = 0
3855 11:49:35.406265 CA_PICK = 600
3856 11:49:35.409468 CA_MCKIO = 600
3857 11:49:35.409552 MCKIO_SEMI = 0
3858 11:49:35.412695 PLL_FREQ = 2288
3859 11:49:35.416121 DQ_UI_PI_RATIO = 32
3860 11:49:35.419367 CA_UI_PI_RATIO = 0
3861 11:49:35.422816 ===================================
3862 11:49:35.426021 ===================================
3863 11:49:35.429452 memory_type:LPDDR4
3864 11:49:35.429536 GP_NUM : 10
3865 11:49:35.432591 SRAM_EN : 1
3866 11:49:35.432674 MD32_EN : 0
3867 11:49:35.436088 ===================================
3868 11:49:35.439292 [ANA_INIT] >>>>>>>>>>>>>>
3869 11:49:35.442525 <<<<<< [CONFIGURE PHASE]: ANA_TX
3870 11:49:35.445676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3871 11:49:35.449500 ===================================
3872 11:49:35.452570 data_rate = 1200,PCW = 0X5800
3873 11:49:35.455682 ===================================
3874 11:49:35.459335 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3875 11:49:35.466141 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3876 11:49:35.469313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3877 11:49:35.475603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3878 11:49:35.479053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3879 11:49:35.482459 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3880 11:49:35.482535 [ANA_INIT] flow start
3881 11:49:35.485793 [ANA_INIT] PLL >>>>>>>>
3882 11:49:35.489647 [ANA_INIT] PLL <<<<<<<<
3883 11:49:35.489734 [ANA_INIT] MIDPI >>>>>>>>
3884 11:49:35.492458 [ANA_INIT] MIDPI <<<<<<<<
3885 11:49:35.495683 [ANA_INIT] DLL >>>>>>>>
3886 11:49:35.495761 [ANA_INIT] flow end
3887 11:49:35.502303 ============ LP4 DIFF to SE enter ============
3888 11:49:35.505777 ============ LP4 DIFF to SE exit ============
3889 11:49:35.505875 [ANA_INIT] <<<<<<<<<<<<<
3890 11:49:35.509342 [Flow] Enable top DCM control >>>>>
3891 11:49:35.512720 [Flow] Enable top DCM control <<<<<
3892 11:49:35.516160 Enable DLL master slave shuffle
3893 11:49:35.522315 ==============================================================
3894 11:49:35.525608 Gating Mode config
3895 11:49:35.529163 ==============================================================
3896 11:49:35.532777 Config description:
3897 11:49:35.542964 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3898 11:49:35.549395 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3899 11:49:35.552780 SELPH_MODE 0: By rank 1: By Phase
3900 11:49:35.559197 ==============================================================
3901 11:49:35.562552 GAT_TRACK_EN = 1
3902 11:49:35.566047 RX_GATING_MODE = 2
3903 11:49:35.566136 RX_GATING_TRACK_MODE = 2
3904 11:49:35.569091 SELPH_MODE = 1
3905 11:49:35.572532 PICG_EARLY_EN = 1
3906 11:49:35.575626 VALID_LAT_VALUE = 1
3907 11:49:35.582616 ==============================================================
3908 11:49:35.586325 Enter into Gating configuration >>>>
3909 11:49:35.589105 Exit from Gating configuration <<<<
3910 11:49:35.592151 Enter into DVFS_PRE_config >>>>>
3911 11:49:35.602196 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3912 11:49:35.605573 Exit from DVFS_PRE_config <<<<<
3913 11:49:35.608928 Enter into PICG configuration >>>>
3914 11:49:35.612150 Exit from PICG configuration <<<<
3915 11:49:35.615853 [RX_INPUT] configuration >>>>>
3916 11:49:35.618828 [RX_INPUT] configuration <<<<<
3917 11:49:35.622309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3918 11:49:35.629286 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3919 11:49:35.635464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3920 11:49:35.642100 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3921 11:49:35.645680 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3922 11:49:35.652012 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3923 11:49:35.655611 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3924 11:49:35.662211 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3925 11:49:35.665484 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3926 11:49:35.668803 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3927 11:49:35.671960 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3928 11:49:35.678531 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3929 11:49:35.682117 ===================================
3930 11:49:35.682205 LPDDR4 DRAM CONFIGURATION
3931 11:49:35.685350 ===================================
3932 11:49:35.688939 EX_ROW_EN[0] = 0x0
3933 11:49:35.692038 EX_ROW_EN[1] = 0x0
3934 11:49:35.692143 LP4Y_EN = 0x0
3935 11:49:35.695084 WORK_FSP = 0x0
3936 11:49:35.695186 WL = 0x2
3937 11:49:35.698302 RL = 0x2
3938 11:49:35.698443 BL = 0x2
3939 11:49:35.701914 RPST = 0x0
3940 11:49:35.702015 RD_PRE = 0x0
3941 11:49:35.705089 WR_PRE = 0x1
3942 11:49:35.705188 WR_PST = 0x0
3943 11:49:35.708150 DBI_WR = 0x0
3944 11:49:35.708251 DBI_RD = 0x0
3945 11:49:35.711888 OTF = 0x1
3946 11:49:35.715305 ===================================
3947 11:49:35.718485 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3948 11:49:35.722025 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3949 11:49:35.728535 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3950 11:49:35.731724 ===================================
3951 11:49:35.731823 LPDDR4 DRAM CONFIGURATION
3952 11:49:35.735045 ===================================
3953 11:49:35.738288 EX_ROW_EN[0] = 0x10
3954 11:49:35.741937 EX_ROW_EN[1] = 0x0
3955 11:49:35.742038 LP4Y_EN = 0x0
3956 11:49:35.745420 WORK_FSP = 0x0
3957 11:49:35.745505 WL = 0x2
3958 11:49:35.748465 RL = 0x2
3959 11:49:35.748564 BL = 0x2
3960 11:49:35.751718 RPST = 0x0
3961 11:49:35.751819 RD_PRE = 0x0
3962 11:49:35.754843 WR_PRE = 0x1
3963 11:49:35.754914 WR_PST = 0x0
3964 11:49:35.758283 DBI_WR = 0x0
3965 11:49:35.758393 DBI_RD = 0x0
3966 11:49:35.761721 OTF = 0x1
3967 11:49:35.765375 ===================================
3968 11:49:35.771469 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3969 11:49:35.775096 nWR fixed to 30
3970 11:49:35.775197 [ModeRegInit_LP4] CH0 RK0
3971 11:49:35.778280 [ModeRegInit_LP4] CH0 RK1
3972 11:49:35.781617 [ModeRegInit_LP4] CH1 RK0
3973 11:49:35.785205 [ModeRegInit_LP4] CH1 RK1
3974 11:49:35.785305 match AC timing 17
3975 11:49:35.791488 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3976 11:49:35.794513 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3977 11:49:35.797877 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3978 11:49:35.804476 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3979 11:49:35.807701 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3980 11:49:35.807779 ==
3981 11:49:35.811057 Dram Type= 6, Freq= 0, CH_0, rank 0
3982 11:49:35.814262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 11:49:35.814363 ==
3984 11:49:35.821475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3985 11:49:35.827718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3986 11:49:35.831181 [CA 0] Center 36 (6~67) winsize 62
3987 11:49:35.834218 [CA 1] Center 36 (6~67) winsize 62
3988 11:49:35.837720 [CA 2] Center 34 (4~65) winsize 62
3989 11:49:35.841023 [CA 3] Center 34 (4~65) winsize 62
3990 11:49:35.844471 [CA 4] Center 34 (4~65) winsize 62
3991 11:49:35.847686 [CA 5] Center 33 (3~64) winsize 62
3992 11:49:35.847785
3993 11:49:35.851451 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3994 11:49:35.851526
3995 11:49:35.854155 [CATrainingPosCal] consider 1 rank data
3996 11:49:35.857594 u2DelayCellTimex100 = 270/100 ps
3997 11:49:35.860732 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3998 11:49:35.864320 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3999 11:49:35.867850 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4000 11:49:35.870893 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4001 11:49:35.874122 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4002 11:49:35.877210 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4003 11:49:35.880626
4004 11:49:35.884285 CA PerBit enable=1, Macro0, CA PI delay=33
4005 11:49:35.884389
4006 11:49:35.887210 [CBTSetCACLKResult] CA Dly = 33
4007 11:49:35.887310 CS Dly: 5 (0~36)
4008 11:49:35.887406 ==
4009 11:49:35.890720 Dram Type= 6, Freq= 0, CH_0, rank 1
4010 11:49:35.894293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 11:49:35.894411 ==
4012 11:49:35.900593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4013 11:49:35.907028 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4014 11:49:35.910737 [CA 0] Center 36 (6~67) winsize 62
4015 11:49:35.913813 [CA 1] Center 36 (6~67) winsize 62
4016 11:49:35.917406 [CA 2] Center 34 (4~65) winsize 62
4017 11:49:35.920846 [CA 3] Center 34 (4~65) winsize 62
4018 11:49:35.924026 [CA 4] Center 34 (3~65) winsize 63
4019 11:49:35.927344 [CA 5] Center 33 (3~64) winsize 62
4020 11:49:35.927425
4021 11:49:35.930502 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4022 11:49:35.930575
4023 11:49:35.933721 [CATrainingPosCal] consider 2 rank data
4024 11:49:35.937256 u2DelayCellTimex100 = 270/100 ps
4025 11:49:35.940770 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4026 11:49:35.944105 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4027 11:49:35.947491 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4028 11:49:35.950456 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4029 11:49:35.954058 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4030 11:49:35.960930 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4031 11:49:35.961042
4032 11:49:35.963981 CA PerBit enable=1, Macro0, CA PI delay=33
4033 11:49:35.964099
4034 11:49:35.967070 [CBTSetCACLKResult] CA Dly = 33
4035 11:49:35.967171 CS Dly: 5 (0~37)
4036 11:49:35.967261
4037 11:49:35.970390 ----->DramcWriteLeveling(PI) begin...
4038 11:49:35.970505 ==
4039 11:49:35.974027 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 11:49:35.977056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 11:49:35.980785 ==
4042 11:49:35.980886 Write leveling (Byte 0): 34 => 34
4043 11:49:35.984074 Write leveling (Byte 1): 29 => 29
4044 11:49:35.987195 DramcWriteLeveling(PI) end<-----
4045 11:49:35.987303
4046 11:49:35.987397 ==
4047 11:49:35.990632 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 11:49:35.997156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 11:49:35.997260 ==
4050 11:49:36.000788 [Gating] SW mode calibration
4051 11:49:36.007065 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4052 11:49:36.010262 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4053 11:49:36.017311 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 11:49:36.020489 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4055 11:49:36.023465 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 11:49:36.030501 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4057 11:49:36.033737 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4058 11:49:36.037215 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 11:49:36.040393 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 11:49:36.046824 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 11:49:36.050608 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 11:49:36.053931 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 11:49:36.060108 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
4064 11:49:36.063699 0 10 12 | B1->B0 | 2828 3939 | 0 1 | (0 0) (0 0)
4065 11:49:36.066723 0 10 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
4066 11:49:36.073522 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 11:49:36.076889 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 11:49:36.079894 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 11:49:36.086523 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 11:49:36.090271 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 11:49:36.093192 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 11:49:36.099839 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4073 11:49:36.103189 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4074 11:49:36.106611 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:49:36.113010 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:49:36.116772 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:49:36.119968 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:49:36.126316 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:49:36.130087 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:49:36.133619 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:49:36.139906 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:49:36.143337 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:49:36.146467 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:49:36.153098 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:49:36.156385 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:49:36.159936 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:49:36.166778 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:49:36.170003 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4089 11:49:36.173463 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4090 11:49:36.176784 Total UI for P1: 0, mck2ui 16
4091 11:49:36.179738 best dqsien dly found for B0: ( 0, 13, 12)
4092 11:49:36.183373 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 11:49:36.186557 Total UI for P1: 0, mck2ui 16
4094 11:49:36.190089 best dqsien dly found for B1: ( 0, 13, 16)
4095 11:49:36.193642 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4096 11:49:36.196705 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4097 11:49:36.199987
4098 11:49:36.203113 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4099 11:49:36.206668 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4100 11:49:36.209977 [Gating] SW calibration Done
4101 11:49:36.210076 ==
4102 11:49:36.213314 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 11:49:36.216389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 11:49:36.216492 ==
4105 11:49:36.216586 RX Vref Scan: 0
4106 11:49:36.216675
4107 11:49:36.220093 RX Vref 0 -> 0, step: 1
4108 11:49:36.220198
4109 11:49:36.222978 RX Delay -230 -> 252, step: 16
4110 11:49:36.226511 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4111 11:49:36.232840 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4112 11:49:36.236257 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4113 11:49:36.239391 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4114 11:49:36.242823 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4115 11:49:36.246285 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4116 11:49:36.252572 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4117 11:49:36.256204 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4118 11:49:36.259626 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4119 11:49:36.262777 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4120 11:49:36.269772 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4121 11:49:36.272787 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4122 11:49:36.276221 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4123 11:49:36.279267 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4124 11:49:36.285668 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4125 11:49:36.289392 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4126 11:49:36.289498 ==
4127 11:49:36.292341 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 11:49:36.295972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 11:49:36.296075 ==
4130 11:49:36.299335 DQS Delay:
4131 11:49:36.299438 DQS0 = 0, DQS1 = 0
4132 11:49:36.299532 DQM Delay:
4133 11:49:36.302396 DQM0 = 52, DQM1 = 42
4134 11:49:36.302520 DQ Delay:
4135 11:49:36.305897 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4136 11:49:36.309341 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4137 11:49:36.312599 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4138 11:49:36.315461 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4139 11:49:36.315557
4140 11:49:36.315647
4141 11:49:36.315738 ==
4142 11:49:36.318855 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 11:49:36.325257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 11:49:36.325360 ==
4145 11:49:36.325451
4146 11:49:36.325517
4147 11:49:36.325574 TX Vref Scan disable
4148 11:49:36.329485 == TX Byte 0 ==
4149 11:49:36.332524 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4150 11:49:36.336228 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4151 11:49:36.339646 == TX Byte 1 ==
4152 11:49:36.342600 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4153 11:49:36.346290 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4154 11:49:36.349818 ==
4155 11:49:36.352952 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 11:49:36.356169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 11:49:36.356270 ==
4158 11:49:36.356364
4159 11:49:36.356451
4160 11:49:36.359306 TX Vref Scan disable
4161 11:49:36.362794 == TX Byte 0 ==
4162 11:49:36.365855 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4163 11:49:36.369505 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4164 11:49:36.369606 == TX Byte 1 ==
4165 11:49:36.376299 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4166 11:49:36.379590 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4167 11:49:36.379691
4168 11:49:36.379781 [DATLAT]
4169 11:49:36.382772 Freq=600, CH0 RK0
4170 11:49:36.382850
4171 11:49:36.382911 DATLAT Default: 0x9
4172 11:49:36.385889 0, 0xFFFF, sum = 0
4173 11:49:36.385989 1, 0xFFFF, sum = 0
4174 11:49:36.389590 2, 0xFFFF, sum = 0
4175 11:49:36.392745 3, 0xFFFF, sum = 0
4176 11:49:36.392820 4, 0xFFFF, sum = 0
4177 11:49:36.395923 5, 0xFFFF, sum = 0
4178 11:49:36.396024 6, 0xFFFF, sum = 0
4179 11:49:36.399276 7, 0xFFFF, sum = 0
4180 11:49:36.399376 8, 0x0, sum = 1
4181 11:49:36.399471 9, 0x0, sum = 2
4182 11:49:36.402570 10, 0x0, sum = 3
4183 11:49:36.402667 11, 0x0, sum = 4
4184 11:49:36.405915 best_step = 9
4185 11:49:36.406014
4186 11:49:36.406104 ==
4187 11:49:36.409406 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 11:49:36.412704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 11:49:36.412804 ==
4190 11:49:36.415883 RX Vref Scan: 1
4191 11:49:36.415952
4192 11:49:36.416011 RX Vref 0 -> 0, step: 1
4193 11:49:36.416068
4194 11:49:36.419142 RX Delay -179 -> 252, step: 8
4195 11:49:36.419233
4196 11:49:36.422705 Set Vref, RX VrefLevel [Byte0]: 60
4197 11:49:36.425859 [Byte1]: 50
4198 11:49:36.430193
4199 11:49:36.430295 Final RX Vref Byte 0 = 60 to rank0
4200 11:49:36.433251 Final RX Vref Byte 1 = 50 to rank0
4201 11:49:36.436502 Final RX Vref Byte 0 = 60 to rank1
4202 11:49:36.440056 Final RX Vref Byte 1 = 50 to rank1==
4203 11:49:36.443197 Dram Type= 6, Freq= 0, CH_0, rank 0
4204 11:49:36.449664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 11:49:36.449774 ==
4206 11:49:36.449866 DQS Delay:
4207 11:49:36.449965 DQS0 = 0, DQS1 = 0
4208 11:49:36.453530 DQM Delay:
4209 11:49:36.453605 DQM0 = 50, DQM1 = 37
4210 11:49:36.456789 DQ Delay:
4211 11:49:36.460045 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4212 11:49:36.460124 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4213 11:49:36.463156 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4214 11:49:36.469817 DQ12 =48, DQ13 =36, DQ14 =48, DQ15 =44
4215 11:49:36.469920
4216 11:49:36.470011
4217 11:49:36.476545 [DQSOSCAuto] RK0, (LSB)MR18= 0x5852, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4218 11:49:36.479824 CH0 RK0: MR19=808, MR18=5852
4219 11:49:36.486723 CH0_RK0: MR19=0x808, MR18=0x5852, DQSOSC=393, MR23=63, INC=169, DEC=113
4220 11:49:36.486833
4221 11:49:36.489909 ----->DramcWriteLeveling(PI) begin...
4222 11:49:36.490010 ==
4223 11:49:36.493558 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 11:49:36.496519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 11:49:36.496630 ==
4226 11:49:36.500025 Write leveling (Byte 0): 33 => 33
4227 11:49:36.503104 Write leveling (Byte 1): 33 => 33
4228 11:49:36.506925 DramcWriteLeveling(PI) end<-----
4229 11:49:36.507027
4230 11:49:36.507118 ==
4231 11:49:36.509699 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 11:49:36.512841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 11:49:36.512941 ==
4234 11:49:36.516452 [Gating] SW mode calibration
4235 11:49:36.522852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4236 11:49:36.529572 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4237 11:49:36.533041 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4238 11:49:36.536379 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4239 11:49:36.542982 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 11:49:36.546291 0 9 12 | B1->B0 | 3333 3333 | 1 1 | (0 0) (1 0)
4241 11:49:36.549423 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4242 11:49:36.556784 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 11:49:36.559686 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 11:49:36.562726 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 11:49:36.569567 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 11:49:36.572673 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 11:49:36.576357 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 11:49:36.582574 0 10 12 | B1->B0 | 3030 3636 | 0 0 | (0 0) (0 0)
4249 11:49:36.586226 0 10 16 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
4250 11:49:36.589272 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 11:49:36.596539 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:49:36.599392 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 11:49:36.602756 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 11:49:36.609570 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 11:49:36.612567 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 11:49:36.615990 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4257 11:49:36.622626 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4258 11:49:36.626249 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:49:36.629673 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:49:36.636186 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:49:36.639182 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:49:36.642595 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:49:36.649110 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:49:36.652218 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:49:36.655700 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:49:36.662619 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:49:36.666210 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:49:36.668996 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:49:36.675870 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:49:36.678828 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:49:36.682398 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 11:49:36.688907 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4273 11:49:36.692676 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 11:49:36.695633 Total UI for P1: 0, mck2ui 16
4275 11:49:36.699282 best dqsien dly found for B0: ( 0, 13, 12)
4276 11:49:36.702190 Total UI for P1: 0, mck2ui 16
4277 11:49:36.705417 best dqsien dly found for B1: ( 0, 13, 12)
4278 11:49:36.708733 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4279 11:49:36.712346 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4280 11:49:36.712443
4281 11:49:36.715213 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4282 11:49:36.718776 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4283 11:49:36.721908 [Gating] SW calibration Done
4284 11:49:36.721981 ==
4285 11:49:36.725409 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 11:49:36.728491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 11:49:36.728564 ==
4288 11:49:36.732116 RX Vref Scan: 0
4289 11:49:36.732220
4290 11:49:36.735628 RX Vref 0 -> 0, step: 1
4291 11:49:36.735704
4292 11:49:36.735768 RX Delay -230 -> 252, step: 16
4293 11:49:36.742208 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4294 11:49:36.745682 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4295 11:49:36.748697 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4296 11:49:36.752316 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4297 11:49:36.758780 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4298 11:49:36.761968 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4299 11:49:36.765351 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4300 11:49:36.768979 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4301 11:49:36.772208 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4302 11:49:36.779060 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4303 11:49:36.782320 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4304 11:49:36.785391 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4305 11:49:36.788580 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4306 11:49:36.795428 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4307 11:49:36.799045 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4308 11:49:36.801942 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4309 11:49:36.802020 ==
4310 11:49:36.805689 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 11:49:36.808554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 11:49:36.808627 ==
4313 11:49:36.811852 DQS Delay:
4314 11:49:36.811922 DQS0 = 0, DQS1 = 0
4315 11:49:36.815233 DQM Delay:
4316 11:49:36.815307 DQM0 = 52, DQM1 = 45
4317 11:49:36.815377 DQ Delay:
4318 11:49:36.818621 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4319 11:49:36.822037 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4320 11:49:36.825557 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4321 11:49:36.828740 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4322 11:49:36.828818
4323 11:49:36.828898
4324 11:49:36.832202 ==
4325 11:49:36.835123 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 11:49:36.838549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 11:49:36.838633 ==
4328 11:49:36.838698
4329 11:49:36.838758
4330 11:49:36.842386 TX Vref Scan disable
4331 11:49:36.842500 == TX Byte 0 ==
4332 11:49:36.848723 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4333 11:49:36.851741 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4334 11:49:36.851828 == TX Byte 1 ==
4335 11:49:36.858246 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4336 11:49:36.861613 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4337 11:49:36.861695 ==
4338 11:49:36.865119 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 11:49:36.868217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 11:49:36.868300 ==
4341 11:49:36.868369
4342 11:49:36.868456
4343 11:49:36.871525 TX Vref Scan disable
4344 11:49:36.875089 == TX Byte 0 ==
4345 11:49:36.878116 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4346 11:49:36.881718 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4347 11:49:36.884873 == TX Byte 1 ==
4348 11:49:36.888159 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4349 11:49:36.891418 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4350 11:49:36.891502
4351 11:49:36.894899 [DATLAT]
4352 11:49:36.894982 Freq=600, CH0 RK1
4353 11:49:36.895050
4354 11:49:36.898030 DATLAT Default: 0x9
4355 11:49:36.898113 0, 0xFFFF, sum = 0
4356 11:49:36.901546 1, 0xFFFF, sum = 0
4357 11:49:36.901630 2, 0xFFFF, sum = 0
4358 11:49:36.905004 3, 0xFFFF, sum = 0
4359 11:49:36.905089 4, 0xFFFF, sum = 0
4360 11:49:36.908687 5, 0xFFFF, sum = 0
4361 11:49:36.908769 6, 0xFFFF, sum = 0
4362 11:49:36.911701 7, 0xFFFF, sum = 0
4363 11:49:36.911784 8, 0x0, sum = 1
4364 11:49:36.914949 9, 0x0, sum = 2
4365 11:49:36.915032 10, 0x0, sum = 3
4366 11:49:36.918348 11, 0x0, sum = 4
4367 11:49:36.918452 best_step = 9
4368 11:49:36.918517
4369 11:49:36.918576 ==
4370 11:49:36.921968 Dram Type= 6, Freq= 0, CH_0, rank 1
4371 11:49:36.925034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 11:49:36.928256 ==
4373 11:49:36.928337 RX Vref Scan: 0
4374 11:49:36.928401
4375 11:49:36.931807 RX Vref 0 -> 0, step: 1
4376 11:49:36.931888
4377 11:49:36.934759 RX Delay -163 -> 252, step: 8
4378 11:49:36.938087 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4379 11:49:36.941809 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4380 11:49:36.948264 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4381 11:49:36.951636 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4382 11:49:36.955227 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4383 11:49:36.958045 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4384 11:49:36.961226 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4385 11:49:36.968013 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4386 11:49:36.971459 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4387 11:49:36.974903 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4388 11:49:36.977954 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4389 11:49:36.984590 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4390 11:49:36.987933 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4391 11:49:36.991418 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4392 11:49:36.994437 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4393 11:49:36.997982 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4394 11:49:36.998064 ==
4395 11:49:37.001096 Dram Type= 6, Freq= 0, CH_0, rank 1
4396 11:49:37.007638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 11:49:37.007721 ==
4398 11:49:37.007785 DQS Delay:
4399 11:49:37.011401 DQS0 = 0, DQS1 = 0
4400 11:49:37.011482 DQM Delay:
4401 11:49:37.011548 DQM0 = 49, DQM1 = 41
4402 11:49:37.014756 DQ Delay:
4403 11:49:37.018060 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4404 11:49:37.021239 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4405 11:49:37.024685 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4406 11:49:37.028003 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =52
4407 11:49:37.028084
4408 11:49:37.028149
4409 11:49:37.034711 [DQSOSCAuto] RK1, (LSB)MR18= 0x6431, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4410 11:49:37.038274 CH0 RK1: MR19=808, MR18=6431
4411 11:49:37.045088 CH0_RK1: MR19=0x808, MR18=0x6431, DQSOSC=391, MR23=63, INC=171, DEC=114
4412 11:49:37.047673 [RxdqsGatingPostProcess] freq 600
4413 11:49:37.051044 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4414 11:49:37.054339 Pre-setting of DQS Precalculation
4415 11:49:37.061107 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4416 11:49:37.061189 ==
4417 11:49:37.064506 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 11:49:37.067673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 11:49:37.067756 ==
4420 11:49:37.074338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4421 11:49:37.080853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4422 11:49:37.084372 [CA 0] Center 35 (5~66) winsize 62
4423 11:49:37.088000 [CA 1] Center 35 (5~66) winsize 62
4424 11:49:37.090980 [CA 2] Center 34 (4~65) winsize 62
4425 11:49:37.094453 [CA 3] Center 33 (3~64) winsize 62
4426 11:49:37.097426 [CA 4] Center 34 (3~65) winsize 63
4427 11:49:37.100687 [CA 5] Center 33 (3~64) winsize 62
4428 11:49:37.100771
4429 11:49:37.104245 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4430 11:49:37.104329
4431 11:49:37.107515 [CATrainingPosCal] consider 1 rank data
4432 11:49:37.111152 u2DelayCellTimex100 = 270/100 ps
4433 11:49:37.114294 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4434 11:49:37.117917 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4435 11:49:37.121018 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 11:49:37.124311 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4437 11:49:37.127861 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4438 11:49:37.131109 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4439 11:49:37.131214
4440 11:49:37.134190 CA PerBit enable=1, Macro0, CA PI delay=33
4441 11:49:37.134298
4442 11:49:37.137733 [CBTSetCACLKResult] CA Dly = 33
4443 11:49:37.141385 CS Dly: 5 (0~36)
4444 11:49:37.141468 ==
4445 11:49:37.144718 Dram Type= 6, Freq= 0, CH_1, rank 1
4446 11:49:37.148043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 11:49:37.148128 ==
4448 11:49:37.154302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4449 11:49:37.161266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4450 11:49:37.164431 [CA 0] Center 35 (5~66) winsize 62
4451 11:49:37.167655 [CA 1] Center 35 (5~66) winsize 62
4452 11:49:37.171023 [CA 2] Center 34 (4~65) winsize 62
4453 11:49:37.174226 [CA 3] Center 34 (4~65) winsize 62
4454 11:49:37.177407 [CA 4] Center 34 (4~65) winsize 62
4455 11:49:37.180828 [CA 5] Center 34 (3~65) winsize 63
4456 11:49:37.180930
4457 11:49:37.183965 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4458 11:49:37.184066
4459 11:49:37.187604 [CATrainingPosCal] consider 2 rank data
4460 11:49:37.191092 u2DelayCellTimex100 = 270/100 ps
4461 11:49:37.194297 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4462 11:49:37.197648 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4463 11:49:37.200999 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4464 11:49:37.204001 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4465 11:49:37.207651 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4466 11:49:37.210676 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4467 11:49:37.210747
4468 11:49:37.213949 CA PerBit enable=1, Macro0, CA PI delay=33
4469 11:49:37.217633
4470 11:49:37.217706 [CBTSetCACLKResult] CA Dly = 33
4471 11:49:37.221050 CS Dly: 5 (0~36)
4472 11:49:37.221148
4473 11:49:37.224390 ----->DramcWriteLeveling(PI) begin...
4474 11:49:37.224502 ==
4475 11:49:37.227676 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 11:49:37.230622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 11:49:37.230737 ==
4478 11:49:37.233904 Write leveling (Byte 0): 29 => 29
4479 11:49:37.237497 Write leveling (Byte 1): 29 => 29
4480 11:49:37.240675 DramcWriteLeveling(PI) end<-----
4481 11:49:37.240775
4482 11:49:37.240863 ==
4483 11:49:37.244246 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 11:49:37.247218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 11:49:37.247291 ==
4486 11:49:37.250889 [Gating] SW mode calibration
4487 11:49:37.257311 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4488 11:49:37.264359 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4489 11:49:37.267518 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4490 11:49:37.273955 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4491 11:49:37.277297 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4492 11:49:37.280730 0 9 12 | B1->B0 | 2c2c 2b2b | 0 0 | (0 0) (0 0)
4493 11:49:37.287671 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 11:49:37.290649 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 11:49:37.294163 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 11:49:37.297737 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 11:49:37.304120 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 11:49:37.307955 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 11:49:37.310749 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4500 11:49:37.317431 0 10 12 | B1->B0 | 3a3a 3d3d | 1 0 | (0 0) (1 1)
4501 11:49:37.320649 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 11:49:37.324198 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 11:49:37.330603 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:49:37.333968 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 11:49:37.337555 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 11:49:37.344164 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 11:49:37.347416 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4508 11:49:37.351106 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4509 11:49:37.357420 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:49:37.360936 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:49:37.363926 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:49:37.370784 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:49:37.374074 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:49:37.377150 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:49:37.383938 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:49:37.387279 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:49:37.390685 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:49:37.394188 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:49:37.400619 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:49:37.403973 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:49:37.407418 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:49:37.414034 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:49:37.417150 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 11:49:37.420582 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 11:49:37.423790 Total UI for P1: 0, mck2ui 16
4526 11:49:37.427491 best dqsien dly found for B0: ( 0, 13, 10)
4527 11:49:37.430658 Total UI for P1: 0, mck2ui 16
4528 11:49:37.434029 best dqsien dly found for B1: ( 0, 13, 10)
4529 11:49:37.437395 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4530 11:49:37.441074 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4531 11:49:37.443864
4532 11:49:37.447338 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4533 11:49:37.450485 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4534 11:49:37.453990 [Gating] SW calibration Done
4535 11:49:37.454065 ==
4536 11:49:37.457391 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 11:49:37.460569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 11:49:37.460643 ==
4539 11:49:37.460705 RX Vref Scan: 0
4540 11:49:37.460763
4541 11:49:37.463829 RX Vref 0 -> 0, step: 1
4542 11:49:37.463901
4543 11:49:37.467113 RX Delay -230 -> 252, step: 16
4544 11:49:37.470482 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4545 11:49:37.477140 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4546 11:49:37.480532 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4547 11:49:37.483501 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4548 11:49:37.487049 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4549 11:49:37.490261 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4550 11:49:37.496624 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4551 11:49:37.500210 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4552 11:49:37.503607 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4553 11:49:37.506801 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4554 11:49:37.513495 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4555 11:49:37.516764 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4556 11:49:37.519966 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4557 11:49:37.523435 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4558 11:49:37.530314 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4559 11:49:37.533763 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4560 11:49:37.533850 ==
4561 11:49:37.537126 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 11:49:37.539948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 11:49:37.540031 ==
4564 11:49:37.543895 DQS Delay:
4565 11:49:37.543977 DQS0 = 0, DQS1 = 0
4566 11:49:37.544043 DQM Delay:
4567 11:49:37.546840 DQM0 = 51, DQM1 = 44
4568 11:49:37.546923 DQ Delay:
4569 11:49:37.550075 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4570 11:49:37.553504 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4571 11:49:37.556854 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4572 11:49:37.560140 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4573 11:49:37.560222
4574 11:49:37.560287
4575 11:49:37.560347 ==
4576 11:49:37.563434 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 11:49:37.566860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 11:49:37.569909 ==
4579 11:49:37.569991
4580 11:49:37.570056
4581 11:49:37.570117 TX Vref Scan disable
4582 11:49:37.573642 == TX Byte 0 ==
4583 11:49:37.577276 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4584 11:49:37.580062 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4585 11:49:37.583476 == TX Byte 1 ==
4586 11:49:37.586344 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4587 11:49:37.593182 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4588 11:49:37.593265 ==
4589 11:49:37.596607 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 11:49:37.599910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 11:49:37.599994 ==
4592 11:49:37.600059
4593 11:49:37.600117
4594 11:49:37.603205 TX Vref Scan disable
4595 11:49:37.603287 == TX Byte 0 ==
4596 11:49:37.609959 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4597 11:49:37.613072 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4598 11:49:37.613159 == TX Byte 1 ==
4599 11:49:37.619763 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4600 11:49:37.623146 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4601 11:49:37.623231
4602 11:49:37.623296 [DATLAT]
4603 11:49:37.626625 Freq=600, CH1 RK0
4604 11:49:37.626709
4605 11:49:37.626774 DATLAT Default: 0x9
4606 11:49:37.629695 0, 0xFFFF, sum = 0
4607 11:49:37.629780 1, 0xFFFF, sum = 0
4608 11:49:37.633411 2, 0xFFFF, sum = 0
4609 11:49:37.633527 3, 0xFFFF, sum = 0
4610 11:49:37.636488 4, 0xFFFF, sum = 0
4611 11:49:37.639778 5, 0xFFFF, sum = 0
4612 11:49:37.639862 6, 0xFFFF, sum = 0
4613 11:49:37.643031 7, 0xFFFF, sum = 0
4614 11:49:37.643115 8, 0x0, sum = 1
4615 11:49:37.643182 9, 0x0, sum = 2
4616 11:49:37.646295 10, 0x0, sum = 3
4617 11:49:37.646403 11, 0x0, sum = 4
4618 11:49:37.649623 best_step = 9
4619 11:49:37.649706
4620 11:49:37.649771 ==
4621 11:49:37.653036 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 11:49:37.656810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 11:49:37.656893 ==
4624 11:49:37.659667 RX Vref Scan: 1
4625 11:49:37.659751
4626 11:49:37.659816 RX Vref 0 -> 0, step: 1
4627 11:49:37.659876
4628 11:49:37.663091 RX Delay -179 -> 252, step: 8
4629 11:49:37.663175
4630 11:49:37.666124 Set Vref, RX VrefLevel [Byte0]: 52
4631 11:49:37.669389 [Byte1]: 52
4632 11:49:37.673535
4633 11:49:37.673617 Final RX Vref Byte 0 = 52 to rank0
4634 11:49:37.677117 Final RX Vref Byte 1 = 52 to rank0
4635 11:49:37.680313 Final RX Vref Byte 0 = 52 to rank1
4636 11:49:37.683586 Final RX Vref Byte 1 = 52 to rank1==
4637 11:49:37.687247 Dram Type= 6, Freq= 0, CH_1, rank 0
4638 11:49:37.693776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 11:49:37.693861 ==
4640 11:49:37.693927 DQS Delay:
4641 11:49:37.693987 DQS0 = 0, DQS1 = 0
4642 11:49:37.696685 DQM Delay:
4643 11:49:37.696768 DQM0 = 49, DQM1 = 41
4644 11:49:37.700466 DQ Delay:
4645 11:49:37.703255 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4646 11:49:37.706924 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4647 11:49:37.707008 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4648 11:49:37.713271 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4649 11:49:37.713355
4650 11:49:37.713420
4651 11:49:37.720256 [DQSOSCAuto] RK0, (LSB)MR18= 0x466e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4652 11:49:37.723499 CH1 RK0: MR19=808, MR18=466E
4653 11:49:37.730014 CH1_RK0: MR19=0x808, MR18=0x466E, DQSOSC=389, MR23=63, INC=173, DEC=115
4654 11:49:37.730099
4655 11:49:37.733356 ----->DramcWriteLeveling(PI) begin...
4656 11:49:37.733442 ==
4657 11:49:37.736972 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 11:49:37.740193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 11:49:37.740275 ==
4660 11:49:37.743595 Write leveling (Byte 0): 26 => 26
4661 11:49:37.746791 Write leveling (Byte 1): 28 => 28
4662 11:49:37.749997 DramcWriteLeveling(PI) end<-----
4663 11:49:37.750079
4664 11:49:37.750144 ==
4665 11:49:37.753246 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 11:49:37.756882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 11:49:37.756965 ==
4668 11:49:37.760071 [Gating] SW mode calibration
4669 11:49:37.766445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4670 11:49:37.773469 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4671 11:49:37.776574 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4672 11:49:37.780320 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4673 11:49:37.786659 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4674 11:49:37.790006 0 9 12 | B1->B0 | 2727 3131 | 0 0 | (1 1) (0 1)
4675 11:49:37.793451 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4676 11:49:37.799648 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 11:49:37.803030 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 11:49:37.806754 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 11:49:37.812956 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 11:49:37.816555 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 11:49:37.820121 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4682 11:49:37.826545 0 10 12 | B1->B0 | 3e3e 3232 | 1 0 | (0 0) (0 0)
4683 11:49:37.829843 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4684 11:49:37.833077 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 11:49:37.839754 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 11:49:37.842987 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 11:49:37.846379 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 11:49:37.853220 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 11:49:37.856713 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 11:49:37.859924 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4691 11:49:37.866320 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:49:37.870048 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 11:49:37.872829 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 11:49:37.879670 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:49:37.883118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 11:49:37.886275 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:49:37.892914 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:49:37.896535 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:49:37.899791 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:49:37.902927 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:49:37.909795 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:49:37.913270 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:49:37.916202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:49:37.922646 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:49:37.926071 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:49:37.929354 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 11:49:37.932833 Total UI for P1: 0, mck2ui 16
4708 11:49:37.935928 best dqsien dly found for B0: ( 0, 13, 10)
4709 11:49:37.939462 Total UI for P1: 0, mck2ui 16
4710 11:49:37.942650 best dqsien dly found for B1: ( 0, 13, 10)
4711 11:49:37.946155 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4712 11:49:37.952787 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4713 11:49:37.952889
4714 11:49:37.956055 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4715 11:49:37.959252 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4716 11:49:37.962509 [Gating] SW calibration Done
4717 11:49:37.962607 ==
4718 11:49:37.965783 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 11:49:37.970154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 11:49:37.970262 ==
4721 11:49:37.970356 RX Vref Scan: 0
4722 11:49:37.970468
4723 11:49:37.973010 RX Vref 0 -> 0, step: 1
4724 11:49:37.973106
4725 11:49:37.976703 RX Delay -230 -> 252, step: 16
4726 11:49:37.979272 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4727 11:49:37.982623 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4728 11:49:37.989374 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4729 11:49:37.992803 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4730 11:49:37.996473 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4731 11:49:37.999508 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4732 11:49:38.005906 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4733 11:49:38.009219 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4734 11:49:38.012948 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4735 11:49:38.015956 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4736 11:49:38.019396 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4737 11:49:38.026282 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4738 11:49:38.029159 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4739 11:49:38.032905 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4740 11:49:38.035956 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4741 11:49:38.042904 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4742 11:49:38.043008 ==
4743 11:49:38.045964 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 11:49:38.049376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 11:49:38.049464 ==
4746 11:49:38.049549 DQS Delay:
4747 11:49:38.052605 DQS0 = 0, DQS1 = 0
4748 11:49:38.052691 DQM Delay:
4749 11:49:38.055828 DQM0 = 52, DQM1 = 47
4750 11:49:38.055913 DQ Delay:
4751 11:49:38.059069 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4752 11:49:38.062817 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4753 11:49:38.066314 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4754 11:49:38.069366 DQ12 =65, DQ13 =49, DQ14 =49, DQ15 =65
4755 11:49:38.069452
4756 11:49:38.069521
4757 11:49:38.069585 ==
4758 11:49:38.072709 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 11:49:38.075894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 11:49:38.075979 ==
4761 11:49:38.076045
4762 11:49:38.076105
4763 11:49:38.079174 TX Vref Scan disable
4764 11:49:38.082310 == TX Byte 0 ==
4765 11:49:38.085645 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4766 11:49:38.088950 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4767 11:49:38.092377 == TX Byte 1 ==
4768 11:49:38.095562 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4769 11:49:38.099253 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4770 11:49:38.099337 ==
4771 11:49:38.102388 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 11:49:38.108894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 11:49:38.108978 ==
4774 11:49:38.109043
4775 11:49:38.109104
4776 11:49:38.109163 TX Vref Scan disable
4777 11:49:38.113119 == TX Byte 0 ==
4778 11:49:38.116517 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4779 11:49:38.123444 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4780 11:49:38.123529 == TX Byte 1 ==
4781 11:49:38.126427 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4782 11:49:38.133383 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4783 11:49:38.133468
4784 11:49:38.133534 [DATLAT]
4785 11:49:38.133596 Freq=600, CH1 RK1
4786 11:49:38.133655
4787 11:49:38.136581 DATLAT Default: 0x9
4788 11:49:38.136665 0, 0xFFFF, sum = 0
4789 11:49:38.140071 1, 0xFFFF, sum = 0
4790 11:49:38.140157 2, 0xFFFF, sum = 0
4791 11:49:38.142917 3, 0xFFFF, sum = 0
4792 11:49:38.146505 4, 0xFFFF, sum = 0
4793 11:49:38.146590 5, 0xFFFF, sum = 0
4794 11:49:38.149541 6, 0xFFFF, sum = 0
4795 11:49:38.149626 7, 0xFFFF, sum = 0
4796 11:49:38.153235 8, 0x0, sum = 1
4797 11:49:38.153325 9, 0x0, sum = 2
4798 11:49:38.153394 10, 0x0, sum = 3
4799 11:49:38.156408 11, 0x0, sum = 4
4800 11:49:38.156492 best_step = 9
4801 11:49:38.156557
4802 11:49:38.156619 ==
4803 11:49:38.159360 Dram Type= 6, Freq= 0, CH_1, rank 1
4804 11:49:38.166556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4805 11:49:38.166640 ==
4806 11:49:38.166705 RX Vref Scan: 0
4807 11:49:38.166770
4808 11:49:38.169656 RX Vref 0 -> 0, step: 1
4809 11:49:38.169740
4810 11:49:38.173039 RX Delay -179 -> 252, step: 8
4811 11:49:38.176388 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4812 11:49:38.183005 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4813 11:49:38.186411 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4814 11:49:38.189370 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4815 11:49:38.192900 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4816 11:49:38.196341 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4817 11:49:38.263550 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4818 11:49:38.263704 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4819 11:49:38.263808 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4820 11:49:38.263891 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4821 11:49:38.263983 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4822 11:49:38.264061 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4823 11:49:38.264138 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4824 11:49:38.264235 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4825 11:49:38.264330 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4826 11:49:38.264424 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4827 11:49:38.264518 ==
4828 11:49:38.264613 Dram Type= 6, Freq= 0, CH_1, rank 1
4829 11:49:38.264708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4830 11:49:38.264801 ==
4831 11:49:38.264894 DQS Delay:
4832 11:49:38.264987 DQS0 = 0, DQS1 = 0
4833 11:49:38.265079 DQM Delay:
4834 11:49:38.265172 DQM0 = 49, DQM1 = 44
4835 11:49:38.265264 DQ Delay:
4836 11:49:38.265357 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4837 11:49:38.265449 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4838 11:49:38.265541 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4839 11:49:38.266144 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4840 11:49:38.266220
4841 11:49:38.266316
4842 11:49:38.272924 [DQSOSCAuto] RK1, (LSB)MR18= 0x591e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4843 11:49:38.276482 CH1 RK1: MR19=808, MR18=591E
4844 11:49:38.282887 CH1_RK1: MR19=0x808, MR18=0x591E, DQSOSC=393, MR23=63, INC=169, DEC=113
4845 11:49:38.285949 [RxdqsGatingPostProcess] freq 600
4846 11:49:38.292891 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4847 11:49:38.292994 Pre-setting of DQS Precalculation
4848 11:49:38.299543 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4849 11:49:38.306007 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4850 11:49:38.313058 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4851 11:49:38.313156
4852 11:49:38.313221
4853 11:49:38.316000 [Calibration Summary] 1200 Mbps
4854 11:49:38.319476 CH 0, Rank 0
4855 11:49:38.319572 SW Impedance : PASS
4856 11:49:38.322959 DUTY Scan : NO K
4857 11:49:38.323047 ZQ Calibration : PASS
4858 11:49:38.326067 Jitter Meter : NO K
4859 11:49:38.329501 CBT Training : PASS
4860 11:49:38.329585 Write leveling : PASS
4861 11:49:38.332947 RX DQS gating : PASS
4862 11:49:38.336069 RX DQ/DQS(RDDQC) : PASS
4863 11:49:38.336152 TX DQ/DQS : PASS
4864 11:49:38.339300 RX DATLAT : PASS
4865 11:49:38.342690 RX DQ/DQS(Engine): PASS
4866 11:49:38.342772 TX OE : NO K
4867 11:49:38.345950 All Pass.
4868 11:49:38.346034
4869 11:49:38.346100 CH 0, Rank 1
4870 11:49:38.349562 SW Impedance : PASS
4871 11:49:38.349650 DUTY Scan : NO K
4872 11:49:38.352988 ZQ Calibration : PASS
4873 11:49:38.355855 Jitter Meter : NO K
4874 11:49:38.355955 CBT Training : PASS
4875 11:49:38.359666 Write leveling : PASS
4876 11:49:38.362692 RX DQS gating : PASS
4877 11:49:38.362801 RX DQ/DQS(RDDQC) : PASS
4878 11:49:38.366114 TX DQ/DQS : PASS
4879 11:49:38.369354 RX DATLAT : PASS
4880 11:49:38.369475 RX DQ/DQS(Engine): PASS
4881 11:49:38.372289 TX OE : NO K
4882 11:49:38.372417 All Pass.
4883 11:49:38.372539
4884 11:49:38.375778 CH 1, Rank 0
4885 11:49:38.375875 SW Impedance : PASS
4886 11:49:38.379176 DUTY Scan : NO K
4887 11:49:38.379274 ZQ Calibration : PASS
4888 11:49:38.382268 Jitter Meter : NO K
4889 11:49:38.385862 CBT Training : PASS
4890 11:49:38.385958 Write leveling : PASS
4891 11:49:38.389232 RX DQS gating : PASS
4892 11:49:38.392305 RX DQ/DQS(RDDQC) : PASS
4893 11:49:38.392402 TX DQ/DQS : PASS
4894 11:49:38.396133 RX DATLAT : PASS
4895 11:49:38.398913 RX DQ/DQS(Engine): PASS
4896 11:49:38.398997 TX OE : NO K
4897 11:49:38.402527 All Pass.
4898 11:49:38.402609
4899 11:49:38.402673 CH 1, Rank 1
4900 11:49:38.405648 SW Impedance : PASS
4901 11:49:38.405745 DUTY Scan : NO K
4902 11:49:38.408679 ZQ Calibration : PASS
4903 11:49:38.412070 Jitter Meter : NO K
4904 11:49:38.412152 CBT Training : PASS
4905 11:49:38.415442 Write leveling : PASS
4906 11:49:38.418810 RX DQS gating : PASS
4907 11:49:38.418908 RX DQ/DQS(RDDQC) : PASS
4908 11:49:38.422222 TX DQ/DQS : PASS
4909 11:49:38.422313 RX DATLAT : PASS
4910 11:49:38.425489 RX DQ/DQS(Engine): PASS
4911 11:49:38.429029 TX OE : NO K
4912 11:49:38.429134 All Pass.
4913 11:49:38.429231
4914 11:49:38.432260 DramC Write-DBI off
4915 11:49:38.435594 PER_BANK_REFRESH: Hybrid Mode
4916 11:49:38.435682 TX_TRACKING: ON
4917 11:49:38.445391 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4918 11:49:38.448830 [FAST_K] Save calibration result to emmc
4919 11:49:38.452280 dramc_set_vcore_voltage set vcore to 662500
4920 11:49:38.452393 Read voltage for 933, 3
4921 11:49:38.455425 Vio18 = 0
4922 11:49:38.455507 Vcore = 662500
4923 11:49:38.455589 Vdram = 0
4924 11:49:38.458763 Vddq = 0
4925 11:49:38.458844 Vmddr = 0
4926 11:49:38.465216 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4927 11:49:38.468566 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4928 11:49:38.472141 MEM_TYPE=3, freq_sel=17
4929 11:49:38.475174 sv_algorithm_assistance_LP4_1600
4930 11:49:38.478638 ============ PULL DRAM RESETB DOWN ============
4931 11:49:38.481712 ========== PULL DRAM RESETB DOWN end =========
4932 11:49:38.488475 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4933 11:49:38.492024 ===================================
4934 11:49:38.492108 LPDDR4 DRAM CONFIGURATION
4935 11:49:38.494903 ===================================
4936 11:49:38.498399 EX_ROW_EN[0] = 0x0
4937 11:49:38.501896 EX_ROW_EN[1] = 0x0
4938 11:49:38.501980 LP4Y_EN = 0x0
4939 11:49:38.505101 WORK_FSP = 0x0
4940 11:49:38.505185 WL = 0x3
4941 11:49:38.508320 RL = 0x3
4942 11:49:38.508404 BL = 0x2
4943 11:49:38.511752 RPST = 0x0
4944 11:49:38.511835 RD_PRE = 0x0
4945 11:49:38.515099 WR_PRE = 0x1
4946 11:49:38.515183 WR_PST = 0x0
4947 11:49:38.518085 DBI_WR = 0x0
4948 11:49:38.518174 DBI_RD = 0x0
4949 11:49:38.521710 OTF = 0x1
4950 11:49:38.524780 ===================================
4951 11:49:38.528344 ===================================
4952 11:49:38.528428 ANA top config
4953 11:49:38.531336 ===================================
4954 11:49:38.534820 DLL_ASYNC_EN = 0
4955 11:49:38.538297 ALL_SLAVE_EN = 1
4956 11:49:38.541820 NEW_RANK_MODE = 1
4957 11:49:38.541905 DLL_IDLE_MODE = 1
4958 11:49:38.544750 LP45_APHY_COMB_EN = 1
4959 11:49:38.548128 TX_ODT_DIS = 1
4960 11:49:38.551429 NEW_8X_MODE = 1
4961 11:49:38.554730 ===================================
4962 11:49:38.558278 ===================================
4963 11:49:38.558362 data_rate = 1866
4964 11:49:38.561519 CKR = 1
4965 11:49:38.565007 DQ_P2S_RATIO = 8
4966 11:49:38.568252 ===================================
4967 11:49:38.571563 CA_P2S_RATIO = 8
4968 11:49:38.574706 DQ_CA_OPEN = 0
4969 11:49:38.578257 DQ_SEMI_OPEN = 0
4970 11:49:38.578365 CA_SEMI_OPEN = 0
4971 11:49:38.581314 CA_FULL_RATE = 0
4972 11:49:38.584889 DQ_CKDIV4_EN = 1
4973 11:49:38.588101 CA_CKDIV4_EN = 1
4974 11:49:38.591274 CA_PREDIV_EN = 0
4975 11:49:38.594649 PH8_DLY = 0
4976 11:49:38.594732 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4977 11:49:38.598093 DQ_AAMCK_DIV = 4
4978 11:49:38.601436 CA_AAMCK_DIV = 4
4979 11:49:38.605132 CA_ADMCK_DIV = 4
4980 11:49:38.608007 DQ_TRACK_CA_EN = 0
4981 11:49:38.611527 CA_PICK = 933
4982 11:49:38.614673 CA_MCKIO = 933
4983 11:49:38.614755 MCKIO_SEMI = 0
4984 11:49:38.617957 PLL_FREQ = 3732
4985 11:49:38.621346 DQ_UI_PI_RATIO = 32
4986 11:49:38.624439 CA_UI_PI_RATIO = 0
4987 11:49:38.628142 ===================================
4988 11:49:38.630989 ===================================
4989 11:49:38.634700 memory_type:LPDDR4
4990 11:49:38.634782 GP_NUM : 10
4991 11:49:38.638090 SRAM_EN : 1
4992 11:49:38.640978 MD32_EN : 0
4993 11:49:38.641060 ===================================
4994 11:49:38.644358 [ANA_INIT] >>>>>>>>>>>>>>
4995 11:49:38.648081 <<<<<< [CONFIGURE PHASE]: ANA_TX
4996 11:49:38.651423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4997 11:49:38.654754 ===================================
4998 11:49:38.657756 data_rate = 1866,PCW = 0X8f00
4999 11:49:38.661363 ===================================
5000 11:49:38.664442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5001 11:49:38.671237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 11:49:38.674502 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5003 11:49:38.680985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5004 11:49:38.684764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5005 11:49:38.687739 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5006 11:49:38.687821 [ANA_INIT] flow start
5007 11:49:38.690947 [ANA_INIT] PLL >>>>>>>>
5008 11:49:38.694326 [ANA_INIT] PLL <<<<<<<<
5009 11:49:38.694462 [ANA_INIT] MIDPI >>>>>>>>
5010 11:49:38.697494 [ANA_INIT] MIDPI <<<<<<<<
5011 11:49:38.701291 [ANA_INIT] DLL >>>>>>>>
5012 11:49:38.701373 [ANA_INIT] flow end
5013 11:49:38.707581 ============ LP4 DIFF to SE enter ============
5014 11:49:38.711487 ============ LP4 DIFF to SE exit ============
5015 11:49:38.714656 [ANA_INIT] <<<<<<<<<<<<<
5016 11:49:38.717692 [Flow] Enable top DCM control >>>>>
5017 11:49:38.721395 [Flow] Enable top DCM control <<<<<
5018 11:49:38.721478 Enable DLL master slave shuffle
5019 11:49:38.727719 ==============================================================
5020 11:49:38.731050 Gating Mode config
5021 11:49:38.734101 ==============================================================
5022 11:49:38.737850 Config description:
5023 11:49:38.747678 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5024 11:49:38.754415 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5025 11:49:38.757773 SELPH_MODE 0: By rank 1: By Phase
5026 11:49:38.764589 ==============================================================
5027 11:49:38.767986 GAT_TRACK_EN = 1
5028 11:49:38.770859 RX_GATING_MODE = 2
5029 11:49:38.774298 RX_GATING_TRACK_MODE = 2
5030 11:49:38.774410 SELPH_MODE = 1
5031 11:49:38.777565 PICG_EARLY_EN = 1
5032 11:49:38.780888 VALID_LAT_VALUE = 1
5033 11:49:38.787341 ==============================================================
5034 11:49:38.790665 Enter into Gating configuration >>>>
5035 11:49:38.794004 Exit from Gating configuration <<<<
5036 11:49:38.797521 Enter into DVFS_PRE_config >>>>>
5037 11:49:38.807810 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5038 11:49:38.810838 Exit from DVFS_PRE_config <<<<<
5039 11:49:38.814318 Enter into PICG configuration >>>>
5040 11:49:38.817617 Exit from PICG configuration <<<<
5041 11:49:38.820722 [RX_INPUT] configuration >>>>>
5042 11:49:38.824231 [RX_INPUT] configuration <<<<<
5043 11:49:38.827396 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5044 11:49:38.834371 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5045 11:49:38.840978 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5046 11:49:38.844502 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5047 11:49:38.851211 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5048 11:49:38.857511 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5049 11:49:38.860581 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5050 11:49:38.867644 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5051 11:49:38.871041 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5052 11:49:38.874006 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5053 11:49:38.877531 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5054 11:49:38.883803 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 11:49:38.887479 ===================================
5056 11:49:38.887557 LPDDR4 DRAM CONFIGURATION
5057 11:49:38.890832 ===================================
5058 11:49:38.893824 EX_ROW_EN[0] = 0x0
5059 11:49:38.897196 EX_ROW_EN[1] = 0x0
5060 11:49:38.897269 LP4Y_EN = 0x0
5061 11:49:38.900381 WORK_FSP = 0x0
5062 11:49:38.900459 WL = 0x3
5063 11:49:38.903701 RL = 0x3
5064 11:49:38.903785 BL = 0x2
5065 11:49:38.906786 RPST = 0x0
5066 11:49:38.906859 RD_PRE = 0x0
5067 11:49:38.910464 WR_PRE = 0x1
5068 11:49:38.910535 WR_PST = 0x0
5069 11:49:38.913738 DBI_WR = 0x0
5070 11:49:38.913807 DBI_RD = 0x0
5071 11:49:38.917251 OTF = 0x1
5072 11:49:38.920549 ===================================
5073 11:49:38.923969 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5074 11:49:38.927271 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5075 11:49:38.933843 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5076 11:49:38.936951 ===================================
5077 11:49:38.937039 LPDDR4 DRAM CONFIGURATION
5078 11:49:38.940074 ===================================
5079 11:49:38.943680 EX_ROW_EN[0] = 0x10
5080 11:49:38.947027 EX_ROW_EN[1] = 0x0
5081 11:49:38.947105 LP4Y_EN = 0x0
5082 11:49:38.950176 WORK_FSP = 0x0
5083 11:49:38.950251 WL = 0x3
5084 11:49:38.953569 RL = 0x3
5085 11:49:38.953645 BL = 0x2
5086 11:49:38.957103 RPST = 0x0
5087 11:49:38.957181 RD_PRE = 0x0
5088 11:49:38.960211 WR_PRE = 0x1
5089 11:49:38.960286 WR_PST = 0x0
5090 11:49:38.963419 DBI_WR = 0x0
5091 11:49:38.963511 DBI_RD = 0x0
5092 11:49:38.966928 OTF = 0x1
5093 11:49:38.970123 ===================================
5094 11:49:38.976771 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5095 11:49:38.980329 nWR fixed to 30
5096 11:49:38.983462 [ModeRegInit_LP4] CH0 RK0
5097 11:49:38.983547 [ModeRegInit_LP4] CH0 RK1
5098 11:49:38.986811 [ModeRegInit_LP4] CH1 RK0
5099 11:49:38.989729 [ModeRegInit_LP4] CH1 RK1
5100 11:49:38.989820 match AC timing 9
5101 11:49:38.996883 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5102 11:49:38.999642 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5103 11:49:39.003099 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5104 11:49:39.010039 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5105 11:49:39.013453 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5106 11:49:39.013575 ==
5107 11:49:39.016605 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 11:49:39.019917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 11:49:39.020033 ==
5110 11:49:39.026531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5111 11:49:39.033253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5112 11:49:39.036424 [CA 0] Center 38 (7~69) winsize 63
5113 11:49:39.039872 [CA 1] Center 38 (8~69) winsize 62
5114 11:49:39.043170 [CA 2] Center 35 (5~66) winsize 62
5115 11:49:39.046339 [CA 3] Center 34 (4~65) winsize 62
5116 11:49:39.049909 [CA 4] Center 34 (4~64) winsize 61
5117 11:49:39.052842 [CA 5] Center 33 (3~64) winsize 62
5118 11:49:39.052954
5119 11:49:39.056466 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5120 11:49:39.056562
5121 11:49:39.059645 [CATrainingPosCal] consider 1 rank data
5122 11:49:39.062908 u2DelayCellTimex100 = 270/100 ps
5123 11:49:39.066319 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5124 11:49:39.069615 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5125 11:49:39.072820 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5126 11:49:39.076165 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5127 11:49:39.079633 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5128 11:49:39.082881 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5129 11:49:39.082972
5130 11:49:39.089782 CA PerBit enable=1, Macro0, CA PI delay=33
5131 11:49:39.089887
5132 11:49:39.089990 [CBTSetCACLKResult] CA Dly = 33
5133 11:49:39.093154 CS Dly: 7 (0~38)
5134 11:49:39.093230 ==
5135 11:49:39.096240 Dram Type= 6, Freq= 0, CH_0, rank 1
5136 11:49:39.099665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 11:49:39.099774 ==
5138 11:49:39.106083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5139 11:49:39.112512 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5140 11:49:39.115866 [CA 0] Center 38 (8~69) winsize 62
5141 11:49:39.119413 [CA 1] Center 38 (8~69) winsize 62
5142 11:49:39.122794 [CA 2] Center 36 (6~66) winsize 61
5143 11:49:39.125912 [CA 3] Center 35 (5~66) winsize 62
5144 11:49:39.129229 [CA 4] Center 34 (4~65) winsize 62
5145 11:49:39.132458 [CA 5] Center 34 (4~65) winsize 62
5146 11:49:39.132560
5147 11:49:39.135876 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5148 11:49:39.135978
5149 11:49:39.139048 [CATrainingPosCal] consider 2 rank data
5150 11:49:39.142380 u2DelayCellTimex100 = 270/100 ps
5151 11:49:39.146146 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5152 11:49:39.149145 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5153 11:49:39.152493 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5154 11:49:39.155790 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5155 11:49:39.159302 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5156 11:49:39.165782 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5157 11:49:39.165885
5158 11:49:39.169196 CA PerBit enable=1, Macro0, CA PI delay=34
5159 11:49:39.169307
5160 11:49:39.172660 [CBTSetCACLKResult] CA Dly = 34
5161 11:49:39.172766 CS Dly: 8 (0~40)
5162 11:49:39.172863
5163 11:49:39.175741 ----->DramcWriteLeveling(PI) begin...
5164 11:49:39.175842 ==
5165 11:49:39.179288 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 11:49:39.182332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 11:49:39.185723 ==
5168 11:49:39.185828 Write leveling (Byte 0): 31 => 31
5169 11:49:39.188816 Write leveling (Byte 1): 29 => 29
5170 11:49:39.192363 DramcWriteLeveling(PI) end<-----
5171 11:49:39.192454
5172 11:49:39.192521 ==
5173 11:49:39.195654 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 11:49:39.202684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 11:49:39.202770 ==
5176 11:49:39.205587 [Gating] SW mode calibration
5177 11:49:39.212089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5178 11:49:39.215565 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5179 11:49:39.221958 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5180 11:49:39.225826 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 11:49:39.228793 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 11:49:39.235558 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 11:49:39.238657 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 11:49:39.242105 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 11:49:39.245850 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5186 11:49:39.252356 0 14 28 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
5187 11:49:39.255655 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5188 11:49:39.258783 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 11:49:39.265545 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 11:49:39.268729 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 11:49:39.271981 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 11:49:39.278997 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 11:49:39.281977 0 15 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
5194 11:49:39.285185 0 15 28 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
5195 11:49:39.292037 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5196 11:49:39.295650 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 11:49:39.298695 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 11:49:39.305557 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 11:49:39.308738 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 11:49:39.312073 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 11:49:39.318265 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 11:49:39.321629 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5203 11:49:39.325100 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 11:49:39.331798 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:49:39.335528 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:49:39.338511 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:49:39.345225 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:49:39.348673 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:49:39.351839 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:49:39.358245 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:49:39.361415 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:49:39.365160 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:49:39.371479 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:49:39.374924 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:49:39.378633 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:49:39.381855 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:49:39.388474 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5218 11:49:39.391858 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5219 11:49:39.394847 Total UI for P1: 0, mck2ui 16
5220 11:49:39.398123 best dqsien dly found for B0: ( 1, 2, 24)
5221 11:49:39.401899 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5222 11:49:39.408106 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 11:49:39.411536 Total UI for P1: 0, mck2ui 16
5224 11:49:39.414883 best dqsien dly found for B1: ( 1, 2, 30)
5225 11:49:39.417969 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5226 11:49:39.421603 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5227 11:49:39.421684
5228 11:49:39.424948 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5229 11:49:39.428348 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5230 11:49:39.431332 [Gating] SW calibration Done
5231 11:49:39.431416 ==
5232 11:49:39.434781 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 11:49:39.438179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 11:49:39.438292 ==
5235 11:49:39.441685 RX Vref Scan: 0
5236 11:49:39.441789
5237 11:49:39.441882 RX Vref 0 -> 0, step: 1
5238 11:49:39.441972
5239 11:49:39.444638 RX Delay -80 -> 252, step: 8
5240 11:49:39.451568 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5241 11:49:39.455317 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5242 11:49:39.458260 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5243 11:49:39.461564 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5244 11:49:39.465214 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5245 11:49:39.468324 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5246 11:49:39.471606 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5247 11:49:39.477998 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5248 11:49:39.481720 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5249 11:49:39.484776 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5250 11:49:39.488241 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5251 11:49:39.491653 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5252 11:49:39.498243 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5253 11:49:39.501583 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5254 11:49:39.505149 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5255 11:49:39.508398 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5256 11:49:39.508473 ==
5257 11:49:39.511527 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 11:49:39.514768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 11:49:39.514873 ==
5260 11:49:39.518507 DQS Delay:
5261 11:49:39.518606 DQS0 = 0, DQS1 = 0
5262 11:49:39.521728 DQM Delay:
5263 11:49:39.521827 DQM0 = 106, DQM1 = 89
5264 11:49:39.521930 DQ Delay:
5265 11:49:39.524715 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5266 11:49:39.528670 DQ4 =107, DQ5 =95, DQ6 =119, DQ7 =115
5267 11:49:39.531543 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5268 11:49:39.534660 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5269 11:49:39.537959
5270 11:49:39.538064
5271 11:49:39.538167 ==
5272 11:49:39.541104 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 11:49:39.544517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 11:49:39.544624 ==
5275 11:49:39.544731
5276 11:49:39.544831
5277 11:49:39.548411 TX Vref Scan disable
5278 11:49:39.548492 == TX Byte 0 ==
5279 11:49:39.555008 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5280 11:49:39.558107 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5281 11:49:39.558216 == TX Byte 1 ==
5282 11:49:39.564787 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5283 11:49:39.568398 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5284 11:49:39.568480 ==
5285 11:49:39.571579 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 11:49:39.575075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 11:49:39.575159 ==
5288 11:49:39.575264
5289 11:49:39.575365
5290 11:49:39.578112 TX Vref Scan disable
5291 11:49:39.581589 == TX Byte 0 ==
5292 11:49:39.584755 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5293 11:49:39.588376 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5294 11:49:39.591527 == TX Byte 1 ==
5295 11:49:39.595002 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5296 11:49:39.598018 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5297 11:49:39.598092
5298 11:49:39.601448 [DATLAT]
5299 11:49:39.601558 Freq=933, CH0 RK0
5300 11:49:39.601654
5301 11:49:39.604905 DATLAT Default: 0xd
5302 11:49:39.604989 0, 0xFFFF, sum = 0
5303 11:49:39.607889 1, 0xFFFF, sum = 0
5304 11:49:39.607979 2, 0xFFFF, sum = 0
5305 11:49:39.611371 3, 0xFFFF, sum = 0
5306 11:49:39.611466 4, 0xFFFF, sum = 0
5307 11:49:39.614447 5, 0xFFFF, sum = 0
5308 11:49:39.614529 6, 0xFFFF, sum = 0
5309 11:49:39.618030 7, 0xFFFF, sum = 0
5310 11:49:39.618118 8, 0xFFFF, sum = 0
5311 11:49:39.620980 9, 0xFFFF, sum = 0
5312 11:49:39.621067 10, 0x0, sum = 1
5313 11:49:39.624569 11, 0x0, sum = 2
5314 11:49:39.624656 12, 0x0, sum = 3
5315 11:49:39.628073 13, 0x0, sum = 4
5316 11:49:39.628160 best_step = 11
5317 11:49:39.628228
5318 11:49:39.628291 ==
5319 11:49:39.631137 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 11:49:39.638185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 11:49:39.638300 ==
5322 11:49:39.638404 RX Vref Scan: 1
5323 11:49:39.638471
5324 11:49:39.641113 RX Vref 0 -> 0, step: 1
5325 11:49:39.641198
5326 11:49:39.644985 RX Delay -53 -> 252, step: 4
5327 11:49:39.645097
5328 11:49:39.647732 Set Vref, RX VrefLevel [Byte0]: 60
5329 11:49:39.650961 [Byte1]: 50
5330 11:49:39.651047
5331 11:49:39.654146 Final RX Vref Byte 0 = 60 to rank0
5332 11:49:39.657455 Final RX Vref Byte 1 = 50 to rank0
5333 11:49:39.661010 Final RX Vref Byte 0 = 60 to rank1
5334 11:49:39.664594 Final RX Vref Byte 1 = 50 to rank1==
5335 11:49:39.667396 Dram Type= 6, Freq= 0, CH_0, rank 0
5336 11:49:39.670911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 11:49:39.670992 ==
5338 11:49:39.674114 DQS Delay:
5339 11:49:39.674187 DQS0 = 0, DQS1 = 0
5340 11:49:39.674253 DQM Delay:
5341 11:49:39.677700 DQM0 = 106, DQM1 = 93
5342 11:49:39.677776 DQ Delay:
5343 11:49:39.681273 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =104
5344 11:49:39.684096 DQ4 =110, DQ5 =98, DQ6 =116, DQ7 =112
5345 11:49:39.687364 DQ8 =88, DQ9 =76, DQ10 =92, DQ11 =90
5346 11:49:39.690728 DQ12 =98, DQ13 =96, DQ14 =104, DQ15 =100
5347 11:49:39.693969
5348 11:49:39.694058
5349 11:49:39.700774 [DQSOSCAuto] RK0, (LSB)MR18= 0x221e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5350 11:49:39.704182 CH0 RK0: MR19=505, MR18=221E
5351 11:49:39.710803 CH0_RK0: MR19=0x505, MR18=0x221E, DQSOSC=411, MR23=63, INC=64, DEC=42
5352 11:49:39.710955
5353 11:49:39.713981 ----->DramcWriteLeveling(PI) begin...
5354 11:49:39.714086 ==
5355 11:49:39.717868 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 11:49:39.721262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 11:49:39.721362 ==
5358 11:49:39.724082 Write leveling (Byte 0): 32 => 32
5359 11:49:39.727851 Write leveling (Byte 1): 30 => 30
5360 11:49:39.730613 DramcWriteLeveling(PI) end<-----
5361 11:49:39.730692
5362 11:49:39.730759 ==
5363 11:49:39.734035 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 11:49:39.737245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 11:49:39.737318 ==
5366 11:49:39.740986 [Gating] SW mode calibration
5367 11:49:39.747512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5368 11:49:39.754039 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5369 11:49:39.757225 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 11:49:39.760822 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 11:49:39.767101 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 11:49:39.770666 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 11:49:39.774192 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 11:49:39.780784 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 11:49:39.783791 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5376 11:49:39.787472 0 14 28 | B1->B0 | 2e2e 2424 | 1 0 | (0 0) (1 0)
5377 11:49:39.793802 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 11:49:39.797273 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 11:49:39.801200 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 11:49:39.808114 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 11:49:39.811154 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 11:49:39.814580 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 11:49:39.821400 0 15 24 | B1->B0 | 2626 2727 | 1 0 | (0 0) (0 0)
5384 11:49:39.824155 0 15 28 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
5385 11:49:39.827567 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 11:49:39.834140 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 11:49:39.838097 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 11:49:39.841045 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 11:49:39.844276 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 11:49:39.851040 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 11:49:39.854104 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5392 11:49:39.857512 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5393 11:49:39.864457 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5394 11:49:39.867555 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:49:39.871213 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:49:39.877267 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:49:39.880706 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:49:39.884435 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:49:39.890720 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:49:39.894163 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:49:39.897546 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:49:39.904221 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:49:39.907427 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:49:39.910979 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 11:49:39.917485 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:49:39.920913 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:49:39.924086 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 11:49:39.930914 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5409 11:49:39.934211 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 11:49:39.937444 Total UI for P1: 0, mck2ui 16
5411 11:49:39.941051 best dqsien dly found for B0: ( 1, 2, 28)
5412 11:49:39.944126 Total UI for P1: 0, mck2ui 16
5413 11:49:39.947337 best dqsien dly found for B1: ( 1, 2, 28)
5414 11:49:39.950967 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5415 11:49:39.954237 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5416 11:49:39.954852
5417 11:49:39.957577 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5418 11:49:39.961195 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5419 11:49:39.964568 [Gating] SW calibration Done
5420 11:49:39.965137 ==
5421 11:49:39.967174 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 11:49:39.970890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 11:49:39.971461 ==
5424 11:49:39.974281 RX Vref Scan: 0
5425 11:49:39.974870
5426 11:49:39.977400 RX Vref 0 -> 0, step: 1
5427 11:49:39.977967
5428 11:49:39.978339 RX Delay -80 -> 252, step: 8
5429 11:49:39.984038 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5430 11:49:39.987070 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5431 11:49:39.990490 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5432 11:49:39.993968 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5433 11:49:39.997296 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5434 11:49:40.000909 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5435 11:49:40.007333 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5436 11:49:40.010519 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5437 11:49:40.014029 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5438 11:49:40.017263 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5439 11:49:40.020200 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5440 11:49:40.026814 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5441 11:49:40.030268 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5442 11:49:40.034099 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5443 11:49:40.037058 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5444 11:49:40.040574 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5445 11:49:40.041142 ==
5446 11:49:40.043774 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 11:49:40.050465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 11:49:40.051034 ==
5449 11:49:40.051413 DQS Delay:
5450 11:49:40.051762 DQS0 = 0, DQS1 = 0
5451 11:49:40.053181 DQM Delay:
5452 11:49:40.053647 DQM0 = 104, DQM1 = 90
5453 11:49:40.056863 DQ Delay:
5454 11:49:40.060072 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5455 11:49:40.063413 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5456 11:49:40.066825 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5457 11:49:40.070170 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5458 11:49:40.070777
5459 11:49:40.071161
5460 11:49:40.071511 ==
5461 11:49:40.073669 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 11:49:40.076619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 11:49:40.077097 ==
5464 11:49:40.077472
5465 11:49:40.077818
5466 11:49:40.079975 TX Vref Scan disable
5467 11:49:40.083671 == TX Byte 0 ==
5468 11:49:40.086518 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5469 11:49:40.089636 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5470 11:49:40.092974 == TX Byte 1 ==
5471 11:49:40.096327 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5472 11:49:40.099585 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5473 11:49:40.100076 ==
5474 11:49:40.103115 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 11:49:40.106532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 11:49:40.109577 ==
5477 11:49:40.110048
5478 11:49:40.110442
5479 11:49:40.110789 TX Vref Scan disable
5480 11:49:40.113204 == TX Byte 0 ==
5481 11:49:40.116721 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5482 11:49:40.123725 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5483 11:49:40.124295 == TX Byte 1 ==
5484 11:49:40.126544 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5485 11:49:40.133345 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5486 11:49:40.133911
5487 11:49:40.134283 [DATLAT]
5488 11:49:40.134698 Freq=933, CH0 RK1
5489 11:49:40.135040
5490 11:49:40.136479 DATLAT Default: 0xb
5491 11:49:40.136966 0, 0xFFFF, sum = 0
5492 11:49:40.139741 1, 0xFFFF, sum = 0
5493 11:49:40.140314 2, 0xFFFF, sum = 0
5494 11:49:40.143267 3, 0xFFFF, sum = 0
5495 11:49:40.146543 4, 0xFFFF, sum = 0
5496 11:49:40.147119 5, 0xFFFF, sum = 0
5497 11:49:40.149923 6, 0xFFFF, sum = 0
5498 11:49:40.150528 7, 0xFFFF, sum = 0
5499 11:49:40.153056 8, 0xFFFF, sum = 0
5500 11:49:40.153626 9, 0xFFFF, sum = 0
5501 11:49:40.156104 10, 0x0, sum = 1
5502 11:49:40.156582 11, 0x0, sum = 2
5503 11:49:40.159674 12, 0x0, sum = 3
5504 11:49:40.160243 13, 0x0, sum = 4
5505 11:49:40.160620 best_step = 11
5506 11:49:40.162992
5507 11:49:40.163554 ==
5508 11:49:40.166487 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 11:49:40.169539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 11:49:40.170108 ==
5511 11:49:40.170520 RX Vref Scan: 0
5512 11:49:40.170873
5513 11:49:40.172578 RX Vref 0 -> 0, step: 1
5514 11:49:40.173047
5515 11:49:40.175915 RX Delay -53 -> 252, step: 4
5516 11:49:40.183315 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5517 11:49:40.186497 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5518 11:49:40.189544 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5519 11:49:40.192591 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5520 11:49:40.196040 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5521 11:49:40.199569 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5522 11:49:40.205919 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5523 11:49:40.209157 iDelay=203, Bit 7, Center 112 (27 ~ 198) 172
5524 11:49:40.212666 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5525 11:49:40.215905 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5526 11:49:40.219064 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5527 11:49:40.226242 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5528 11:49:40.229070 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5529 11:49:40.232530 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5530 11:49:40.235822 iDelay=203, Bit 14, Center 104 (19 ~ 190) 172
5531 11:49:40.239211 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5532 11:49:40.239773 ==
5533 11:49:40.243013 Dram Type= 6, Freq= 0, CH_0, rank 1
5534 11:49:40.249506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 11:49:40.250077 ==
5536 11:49:40.250487 DQS Delay:
5537 11:49:40.252658 DQS0 = 0, DQS1 = 0
5538 11:49:40.253219 DQM Delay:
5539 11:49:40.255703 DQM0 = 104, DQM1 = 92
5540 11:49:40.256268 DQ Delay:
5541 11:49:40.258579 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5542 11:49:40.262490 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =112
5543 11:49:40.265739 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5544 11:49:40.269107 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =98
5545 11:49:40.269671
5546 11:49:40.270038
5547 11:49:40.275708 [DQSOSCAuto] RK1, (LSB)MR18= 0x2606, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
5548 11:49:40.278760 CH0 RK1: MR19=505, MR18=2606
5549 11:49:40.285727 CH0_RK1: MR19=0x505, MR18=0x2606, DQSOSC=409, MR23=63, INC=64, DEC=43
5550 11:49:40.288951 [RxdqsGatingPostProcess] freq 933
5551 11:49:40.295343 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5552 11:49:40.298951 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 11:49:40.299521 best DQS1 dly(2T, 0.5T) = (0, 10)
5554 11:49:40.302011 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 11:49:40.305565 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5556 11:49:40.308628 best DQS0 dly(2T, 0.5T) = (0, 10)
5557 11:49:40.312412 best DQS1 dly(2T, 0.5T) = (0, 10)
5558 11:49:40.315462 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5559 11:49:40.319135 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5560 11:49:40.322441 Pre-setting of DQS Precalculation
5561 11:49:40.328633 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5562 11:49:40.329102 ==
5563 11:49:40.332017 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 11:49:40.335168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 11:49:40.335667 ==
5566 11:49:40.342269 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 11:49:40.345338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5568 11:49:40.349314 [CA 0] Center 37 (7~68) winsize 62
5569 11:49:40.352821 [CA 1] Center 37 (7~68) winsize 62
5570 11:49:40.356267 [CA 2] Center 35 (5~66) winsize 62
5571 11:49:40.359547 [CA 3] Center 34 (4~65) winsize 62
5572 11:49:40.362866 [CA 4] Center 34 (4~65) winsize 62
5573 11:49:40.366240 [CA 5] Center 34 (4~65) winsize 62
5574 11:49:40.366824
5575 11:49:40.369726 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5576 11:49:40.370290
5577 11:49:40.373049 [CATrainingPosCal] consider 1 rank data
5578 11:49:40.376305 u2DelayCellTimex100 = 270/100 ps
5579 11:49:40.379854 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5580 11:49:40.386223 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5581 11:49:40.389559 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5582 11:49:40.392647 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5583 11:49:40.395906 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5584 11:49:40.399592 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5585 11:49:40.400204
5586 11:49:40.402792 CA PerBit enable=1, Macro0, CA PI delay=34
5587 11:49:40.403361
5588 11:49:40.406086 [CBTSetCACLKResult] CA Dly = 34
5589 11:49:40.406700 CS Dly: 6 (0~37)
5590 11:49:40.409805 ==
5591 11:49:40.410442 Dram Type= 6, Freq= 0, CH_1, rank 1
5592 11:49:40.415866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 11:49:40.416435 ==
5594 11:49:40.419159 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 11:49:40.425827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5596 11:49:40.429709 [CA 0] Center 37 (7~68) winsize 62
5597 11:49:40.432938 [CA 1] Center 38 (7~69) winsize 63
5598 11:49:40.436465 [CA 2] Center 36 (6~66) winsize 61
5599 11:49:40.439733 [CA 3] Center 35 (5~65) winsize 61
5600 11:49:40.443086 [CA 4] Center 35 (5~65) winsize 61
5601 11:49:40.446587 [CA 5] Center 34 (5~64) winsize 60
5602 11:49:40.447148
5603 11:49:40.449643 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5604 11:49:40.450208
5605 11:49:40.452931 [CATrainingPosCal] consider 2 rank data
5606 11:49:40.456277 u2DelayCellTimex100 = 270/100 ps
5607 11:49:40.459560 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5608 11:49:40.462842 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5609 11:49:40.469554 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5610 11:49:40.473025 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5611 11:49:40.476216 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5612 11:49:40.479128 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5613 11:49:40.479594
5614 11:49:40.482505 CA PerBit enable=1, Macro0, CA PI delay=34
5615 11:49:40.482970
5616 11:49:40.486163 [CBTSetCACLKResult] CA Dly = 34
5617 11:49:40.486789 CS Dly: 7 (0~39)
5618 11:49:40.489273
5619 11:49:40.492517 ----->DramcWriteLeveling(PI) begin...
5620 11:49:40.492994 ==
5621 11:49:40.496300 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 11:49:40.499483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 11:49:40.500060 ==
5624 11:49:40.503003 Write leveling (Byte 0): 27 => 27
5625 11:49:40.505918 Write leveling (Byte 1): 28 => 28
5626 11:49:40.508911 DramcWriteLeveling(PI) end<-----
5627 11:49:40.509378
5628 11:49:40.509746 ==
5629 11:49:40.512442 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 11:49:40.515820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 11:49:40.516288 ==
5632 11:49:40.519274 [Gating] SW mode calibration
5633 11:49:40.525736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5634 11:49:40.532632 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5635 11:49:40.535559 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 11:49:40.539220 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 11:49:40.545870 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 11:49:40.548832 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 11:49:40.552458 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 11:49:40.558981 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5641 11:49:40.562678 0 14 24 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 1)
5642 11:49:40.565535 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5643 11:49:40.572544 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 11:49:40.575530 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 11:49:40.578932 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 11:49:40.582139 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 11:49:40.588837 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 11:49:40.592102 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 11:49:40.595357 0 15 24 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
5650 11:49:40.602562 0 15 28 | B1->B0 | 3d3d 3f3f | 0 0 | (0 0) (0 0)
5651 11:49:40.605777 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 11:49:40.608650 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 11:49:40.615708 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 11:49:40.618846 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 11:49:40.622114 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 11:49:40.628525 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5657 11:49:40.632056 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5658 11:49:40.635210 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:49:40.641988 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:49:40.645759 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:49:40.649026 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 11:49:40.655280 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 11:49:40.659085 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:49:40.662166 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:49:40.669131 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:49:40.672148 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:49:40.675165 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:49:40.682017 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:49:40.685705 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:49:40.688669 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 11:49:40.694931 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:49:40.698785 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:49:40.701642 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5674 11:49:40.705238 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 11:49:40.708715 Total UI for P1: 0, mck2ui 16
5676 11:49:40.711795 best dqsien dly found for B0: ( 1, 2, 24)
5677 11:49:40.715082 Total UI for P1: 0, mck2ui 16
5678 11:49:40.718749 best dqsien dly found for B1: ( 1, 2, 26)
5679 11:49:40.721974 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5680 11:49:40.728419 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5681 11:49:40.728977
5682 11:49:40.731876 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5683 11:49:40.735456 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5684 11:49:40.738076 [Gating] SW calibration Done
5685 11:49:40.738576 ==
5686 11:49:40.741464 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 11:49:40.745275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 11:49:40.745845 ==
5689 11:49:40.746214 RX Vref Scan: 0
5690 11:49:40.748586
5691 11:49:40.749047 RX Vref 0 -> 0, step: 1
5692 11:49:40.749413
5693 11:49:40.751851 RX Delay -80 -> 252, step: 8
5694 11:49:40.754848 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5695 11:49:40.758270 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5696 11:49:40.765147 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5697 11:49:40.768628 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5698 11:49:40.771733 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5699 11:49:40.775026 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5700 11:49:40.778420 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5701 11:49:40.781521 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5702 11:49:40.788136 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5703 11:49:40.791687 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5704 11:49:40.795154 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5705 11:49:40.798492 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5706 11:49:40.801288 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5707 11:49:40.805059 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5708 11:49:40.811452 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5709 11:49:40.815299 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5710 11:49:40.815866 ==
5711 11:49:40.818023 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 11:49:40.821217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 11:49:40.821680 ==
5714 11:49:40.824757 DQS Delay:
5715 11:49:40.825298 DQS0 = 0, DQS1 = 0
5716 11:49:40.825671 DQM Delay:
5717 11:49:40.827846 DQM0 = 102, DQM1 = 96
5718 11:49:40.828533 DQ Delay:
5719 11:49:40.833020 DQ0 =111, DQ1 =95, DQ2 =91, DQ3 =99
5720 11:49:40.834556 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5721 11:49:40.838421 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5722 11:49:40.841448 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5723 11:49:40.841916
5724 11:49:40.842282
5725 11:49:40.844451 ==
5726 11:49:40.848031 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 11:49:40.851069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 11:49:40.851537 ==
5729 11:49:40.851907
5730 11:49:40.852243
5731 11:49:40.854461 TX Vref Scan disable
5732 11:49:40.854925 == TX Byte 0 ==
5733 11:49:40.857654 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5734 11:49:40.864301 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5735 11:49:40.864766 == TX Byte 1 ==
5736 11:49:40.868263 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5737 11:49:40.874204 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5738 11:49:40.874702 ==
5739 11:49:40.877932 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 11:49:40.881044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 11:49:40.881513 ==
5742 11:49:40.881877
5743 11:49:40.882300
5744 11:49:40.884383 TX Vref Scan disable
5745 11:49:40.887721 == TX Byte 0 ==
5746 11:49:40.891427 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5747 11:49:40.894108 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5748 11:49:40.897513 == TX Byte 1 ==
5749 11:49:40.900982 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5750 11:49:40.904057 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5751 11:49:40.904530
5752 11:49:40.907435 [DATLAT]
5753 11:49:40.907912 Freq=933, CH1 RK0
5754 11:49:40.908290
5755 11:49:40.911020 DATLAT Default: 0xd
5756 11:49:40.911488 0, 0xFFFF, sum = 0
5757 11:49:40.914113 1, 0xFFFF, sum = 0
5758 11:49:40.914614 2, 0xFFFF, sum = 0
5759 11:49:40.917491 3, 0xFFFF, sum = 0
5760 11:49:40.917966 4, 0xFFFF, sum = 0
5761 11:49:40.920967 5, 0xFFFF, sum = 0
5762 11:49:40.921583 6, 0xFFFF, sum = 0
5763 11:49:40.924277 7, 0xFFFF, sum = 0
5764 11:49:40.924917 8, 0xFFFF, sum = 0
5765 11:49:40.927407 9, 0xFFFF, sum = 0
5766 11:49:40.927887 10, 0x0, sum = 1
5767 11:49:40.931268 11, 0x0, sum = 2
5768 11:49:40.931749 12, 0x0, sum = 3
5769 11:49:40.934180 13, 0x0, sum = 4
5770 11:49:40.934707 best_step = 11
5771 11:49:40.935082
5772 11:49:40.935425 ==
5773 11:49:40.937797 Dram Type= 6, Freq= 0, CH_1, rank 0
5774 11:49:40.941032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 11:49:40.943826 ==
5776 11:49:40.944299 RX Vref Scan: 1
5777 11:49:40.944675
5778 11:49:40.947508 RX Vref 0 -> 0, step: 1
5779 11:49:40.947986
5780 11:49:40.950602 RX Delay -53 -> 252, step: 4
5781 11:49:40.950933
5782 11:49:40.953883 Set Vref, RX VrefLevel [Byte0]: 52
5783 11:49:40.956801 [Byte1]: 52
5784 11:49:40.957049
5785 11:49:40.960143 Final RX Vref Byte 0 = 52 to rank0
5786 11:49:40.963618 Final RX Vref Byte 1 = 52 to rank0
5787 11:49:40.967214 Final RX Vref Byte 0 = 52 to rank1
5788 11:49:40.970204 Final RX Vref Byte 1 = 52 to rank1==
5789 11:49:40.973527 Dram Type= 6, Freq= 0, CH_1, rank 0
5790 11:49:40.976672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 11:49:40.976796 ==
5792 11:49:40.976892 DQS Delay:
5793 11:49:40.980571 DQS0 = 0, DQS1 = 0
5794 11:49:40.980678 DQM Delay:
5795 11:49:40.983321 DQM0 = 104, DQM1 = 97
5796 11:49:40.983429 DQ Delay:
5797 11:49:40.986686 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5798 11:49:40.990286 DQ4 =104, DQ5 =112, DQ6 =116, DQ7 =100
5799 11:49:40.993493 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =92
5800 11:49:40.997038 DQ12 =106, DQ13 =100, DQ14 =102, DQ15 =104
5801 11:49:40.997123
5802 11:49:40.997189
5803 11:49:41.006939 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5804 11:49:41.010021 CH1 RK0: MR19=505, MR18=1C35
5805 11:49:41.013438 CH1_RK0: MR19=0x505, MR18=0x1C35, DQSOSC=405, MR23=63, INC=66, DEC=44
5806 11:49:41.016915
5807 11:49:41.020226 ----->DramcWriteLeveling(PI) begin...
5808 11:49:41.020314 ==
5809 11:49:41.023695 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 11:49:41.026880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 11:49:41.026966 ==
5812 11:49:41.030170 Write leveling (Byte 0): 28 => 28
5813 11:49:41.033374 Write leveling (Byte 1): 28 => 28
5814 11:49:41.036547 DramcWriteLeveling(PI) end<-----
5815 11:49:41.036633
5816 11:49:41.036701 ==
5817 11:49:41.040117 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 11:49:41.043247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 11:49:41.043334 ==
5820 11:49:41.046630 [Gating] SW mode calibration
5821 11:49:41.053465 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5822 11:49:41.060052 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5823 11:49:41.063210 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 11:49:41.066720 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 11:49:41.073055 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 11:49:41.076315 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 11:49:41.080188 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 11:49:41.086518 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5829 11:49:41.089460 0 14 24 | B1->B0 | 3131 3434 | 0 0 | (0 1) (0 1)
5830 11:49:41.093332 0 14 28 | B1->B0 | 2525 2f2f | 0 1 | (1 0) (1 0)
5831 11:49:41.099437 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 11:49:41.102839 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 11:49:41.106286 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 11:49:41.112925 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 11:49:41.116279 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 11:49:41.119850 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 11:49:41.123270 0 15 24 | B1->B0 | 2d2d 2525 | 1 0 | (0 0) (0 0)
5838 11:49:41.129480 0 15 28 | B1->B0 | 4545 4040 | 0 0 | (0 0) (0 0)
5839 11:49:41.132865 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 11:49:41.136084 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 11:49:41.142941 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 11:49:41.146094 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 11:49:41.152444 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 11:49:41.155718 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 11:49:41.159533 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5846 11:49:41.162806 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5847 11:49:41.169083 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:49:41.172635 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:49:41.176014 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:49:41.182658 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:49:41.185635 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 11:49:41.189040 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:49:41.195702 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:49:41.198940 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:49:41.202488 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:49:41.209061 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:49:41.212323 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:49:41.215762 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:49:41.222405 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:49:41.225598 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:49:41.228826 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5862 11:49:41.235454 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5863 11:49:41.235570 Total UI for P1: 0, mck2ui 16
5864 11:49:41.242487 best dqsien dly found for B1: ( 1, 2, 26)
5865 11:49:41.245299 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 11:49:41.248938 Total UI for P1: 0, mck2ui 16
5867 11:49:41.252379 best dqsien dly found for B0: ( 1, 2, 26)
5868 11:49:41.255514 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5869 11:49:41.258860 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5870 11:49:41.258943
5871 11:49:41.262012 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5872 11:49:41.265670 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5873 11:49:41.268830 [Gating] SW calibration Done
5874 11:49:41.268912 ==
5875 11:49:41.271868 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 11:49:41.275279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 11:49:41.278561 ==
5878 11:49:41.278644 RX Vref Scan: 0
5879 11:49:41.278709
5880 11:49:41.281772 RX Vref 0 -> 0, step: 1
5881 11:49:41.281854
5882 11:49:41.285058 RX Delay -80 -> 252, step: 8
5883 11:49:41.288372 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5884 11:49:41.291859 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5885 11:49:41.294981 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5886 11:49:41.298500 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5887 11:49:41.301838 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5888 11:49:41.308799 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5889 11:49:41.311924 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5890 11:49:41.315332 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5891 11:49:41.318565 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5892 11:49:41.321945 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5893 11:49:41.325121 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5894 11:49:41.332060 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5895 11:49:41.335310 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5896 11:49:41.338533 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5897 11:49:41.341811 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5898 11:49:41.345264 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5899 11:49:41.345360 ==
5900 11:49:41.348868 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 11:49:41.355321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 11:49:41.355407 ==
5903 11:49:41.355472 DQS Delay:
5904 11:49:41.358661 DQS0 = 0, DQS1 = 0
5905 11:49:41.358747 DQM Delay:
5906 11:49:41.362057 DQM0 = 102, DQM1 = 96
5907 11:49:41.362150 DQ Delay:
5908 11:49:41.365192 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5909 11:49:41.368446 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5910 11:49:41.371631 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5911 11:49:41.374880 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5912 11:49:41.374962
5913 11:49:41.375026
5914 11:49:41.375085 ==
5915 11:49:41.378261 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 11:49:41.381775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 11:49:41.381863 ==
5918 11:49:41.384966
5919 11:49:41.385049
5920 11:49:41.385115 TX Vref Scan disable
5921 11:49:41.388122 == TX Byte 0 ==
5922 11:49:41.391576 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5923 11:49:41.394828 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5924 11:49:41.398252 == TX Byte 1 ==
5925 11:49:41.401584 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5926 11:49:41.405042 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5927 11:49:41.405130 ==
5928 11:49:41.408012 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 11:49:41.414973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 11:49:41.415067 ==
5931 11:49:41.415134
5932 11:49:41.415193
5933 11:49:41.415255 TX Vref Scan disable
5934 11:49:41.418952 == TX Byte 0 ==
5935 11:49:41.422531 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5936 11:49:41.429035 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5937 11:49:41.429122 == TX Byte 1 ==
5938 11:49:41.432190 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5939 11:49:41.438635 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5940 11:49:41.438722
5941 11:49:41.438788 [DATLAT]
5942 11:49:41.438847 Freq=933, CH1 RK1
5943 11:49:41.438906
5944 11:49:41.442138 DATLAT Default: 0xb
5945 11:49:41.442221 0, 0xFFFF, sum = 0
5946 11:49:41.445513 1, 0xFFFF, sum = 0
5947 11:49:41.445598 2, 0xFFFF, sum = 0
5948 11:49:41.448808 3, 0xFFFF, sum = 0
5949 11:49:41.452224 4, 0xFFFF, sum = 0
5950 11:49:41.452308 5, 0xFFFF, sum = 0
5951 11:49:41.455349 6, 0xFFFF, sum = 0
5952 11:49:41.455434 7, 0xFFFF, sum = 0
5953 11:49:41.458836 8, 0xFFFF, sum = 0
5954 11:49:41.458922 9, 0xFFFF, sum = 0
5955 11:49:41.462037 10, 0x0, sum = 1
5956 11:49:41.462122 11, 0x0, sum = 2
5957 11:49:41.465338 12, 0x0, sum = 3
5958 11:49:41.465422 13, 0x0, sum = 4
5959 11:49:41.465489 best_step = 11
5960 11:49:41.465549
5961 11:49:41.468655 ==
5962 11:49:41.472088 Dram Type= 6, Freq= 0, CH_1, rank 1
5963 11:49:41.475794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5964 11:49:41.475879 ==
5965 11:49:41.475944 RX Vref Scan: 0
5966 11:49:41.476004
5967 11:49:41.478830 RX Vref 0 -> 0, step: 1
5968 11:49:41.478914
5969 11:49:41.482309 RX Delay -53 -> 252, step: 4
5970 11:49:41.485519 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5971 11:49:41.491970 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5972 11:49:41.495399 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5973 11:49:41.498733 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5974 11:49:41.502341 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5975 11:49:41.505631 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5976 11:49:41.512179 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5977 11:49:41.515306 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5978 11:49:41.518779 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5979 11:49:41.522040 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5980 11:49:41.525522 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5981 11:49:41.528643 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5982 11:49:41.535361 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5983 11:49:41.538737 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5984 11:49:41.541906 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5985 11:49:41.545640 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5986 11:49:41.545725 ==
5987 11:49:41.548811 Dram Type= 6, Freq= 0, CH_1, rank 1
5988 11:49:41.555198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5989 11:49:41.555285 ==
5990 11:49:41.555351 DQS Delay:
5991 11:49:41.558950 DQS0 = 0, DQS1 = 0
5992 11:49:41.559115 DQM Delay:
5993 11:49:41.559190 DQM0 = 104, DQM1 = 97
5994 11:49:41.562089 DQ Delay:
5995 11:49:41.565788 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5996 11:49:41.568967 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5997 11:49:41.572680 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =94
5998 11:49:41.575718 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =106
5999 11:49:41.575882
6000 11:49:41.575959
6001 11:49:41.582097 [DQSOSCAuto] RK1, (LSB)MR18= 0x2603, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
6002 11:49:41.585546 CH1 RK1: MR19=505, MR18=2603
6003 11:49:41.592085 CH1_RK1: MR19=0x505, MR18=0x2603, DQSOSC=409, MR23=63, INC=64, DEC=43
6004 11:49:41.595195 [RxdqsGatingPostProcess] freq 933
6005 11:49:41.601998 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6006 11:49:41.605516 best DQS0 dly(2T, 0.5T) = (0, 10)
6007 11:49:41.605699 best DQS1 dly(2T, 0.5T) = (0, 10)
6008 11:49:41.608556 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6009 11:49:41.611965 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6010 11:49:41.615575 best DQS0 dly(2T, 0.5T) = (0, 10)
6011 11:49:41.618769 best DQS1 dly(2T, 0.5T) = (0, 10)
6012 11:49:41.622048 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6013 11:49:41.625365 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6014 11:49:41.628535 Pre-setting of DQS Precalculation
6015 11:49:41.635200 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6016 11:49:41.641735 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6017 11:49:41.648346 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6018 11:49:41.648516
6019 11:49:41.648617
6020 11:49:41.651736 [Calibration Summary] 1866 Mbps
6021 11:49:41.651853 CH 0, Rank 0
6022 11:49:41.655450 SW Impedance : PASS
6023 11:49:41.658570 DUTY Scan : NO K
6024 11:49:41.658749 ZQ Calibration : PASS
6025 11:49:41.662630 Jitter Meter : NO K
6026 11:49:41.662795 CBT Training : PASS
6027 11:49:41.665308 Write leveling : PASS
6028 11:49:41.668819 RX DQS gating : PASS
6029 11:49:41.668987 RX DQ/DQS(RDDQC) : PASS
6030 11:49:41.671935 TX DQ/DQS : PASS
6031 11:49:41.675741 RX DATLAT : PASS
6032 11:49:41.675910 RX DQ/DQS(Engine): PASS
6033 11:49:41.678431 TX OE : NO K
6034 11:49:41.678571 All Pass.
6035 11:49:41.678648
6036 11:49:41.681984 CH 0, Rank 1
6037 11:49:41.682151 SW Impedance : PASS
6038 11:49:41.685268 DUTY Scan : NO K
6039 11:49:41.688822 ZQ Calibration : PASS
6040 11:49:41.688998 Jitter Meter : NO K
6041 11:49:41.692251 CBT Training : PASS
6042 11:49:41.695053 Write leveling : PASS
6043 11:49:41.695241 RX DQS gating : PASS
6044 11:49:41.698784 RX DQ/DQS(RDDQC) : PASS
6045 11:49:41.701769 TX DQ/DQS : PASS
6046 11:49:41.701889 RX DATLAT : PASS
6047 11:49:41.704819 RX DQ/DQS(Engine): PASS
6048 11:49:41.704989 TX OE : NO K
6049 11:49:41.708297 All Pass.
6050 11:49:41.708487
6051 11:49:41.708606 CH 1, Rank 0
6052 11:49:41.711896 SW Impedance : PASS
6053 11:49:41.712076 DUTY Scan : NO K
6054 11:49:41.714961 ZQ Calibration : PASS
6055 11:49:41.718534 Jitter Meter : NO K
6056 11:49:41.718840 CBT Training : PASS
6057 11:49:41.722156 Write leveling : PASS
6058 11:49:41.724946 RX DQS gating : PASS
6059 11:49:41.725256 RX DQ/DQS(RDDQC) : PASS
6060 11:49:41.728341 TX DQ/DQS : PASS
6061 11:49:41.731430 RX DATLAT : PASS
6062 11:49:41.731842 RX DQ/DQS(Engine): PASS
6063 11:49:41.735097 TX OE : NO K
6064 11:49:41.735461 All Pass.
6065 11:49:41.735747
6066 11:49:41.738768 CH 1, Rank 1
6067 11:49:41.739127 SW Impedance : PASS
6068 11:49:41.741746 DUTY Scan : NO K
6069 11:49:41.745650 ZQ Calibration : PASS
6070 11:49:41.746424 Jitter Meter : NO K
6071 11:49:41.749261 CBT Training : PASS
6072 11:49:41.752271 Write leveling : PASS
6073 11:49:41.752836 RX DQS gating : PASS
6074 11:49:41.754914 RX DQ/DQS(RDDQC) : PASS
6075 11:49:41.758490 TX DQ/DQS : PASS
6076 11:49:41.758962 RX DATLAT : PASS
6077 11:49:41.761560 RX DQ/DQS(Engine): PASS
6078 11:49:41.762023 TX OE : NO K
6079 11:49:41.764997 All Pass.
6080 11:49:41.765557
6081 11:49:41.765928 DramC Write-DBI off
6082 11:49:41.768502 PER_BANK_REFRESH: Hybrid Mode
6083 11:49:41.771938 TX_TRACKING: ON
6084 11:49:41.778421 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6085 11:49:41.781596 [FAST_K] Save calibration result to emmc
6086 11:49:41.788606 dramc_set_vcore_voltage set vcore to 650000
6087 11:49:41.789177 Read voltage for 400, 6
6088 11:49:41.789556 Vio18 = 0
6089 11:49:41.791883 Vcore = 650000
6090 11:49:41.792352 Vdram = 0
6091 11:49:41.792719 Vddq = 0
6092 11:49:41.794683 Vmddr = 0
6093 11:49:41.798893 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6094 11:49:41.804767 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6095 11:49:41.805231 MEM_TYPE=3, freq_sel=20
6096 11:49:41.808218 sv_algorithm_assistance_LP4_800
6097 11:49:41.814776 ============ PULL DRAM RESETB DOWN ============
6098 11:49:41.818051 ========== PULL DRAM RESETB DOWN end =========
6099 11:49:41.821419 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6100 11:49:41.825061 ===================================
6101 11:49:41.828064 LPDDR4 DRAM CONFIGURATION
6102 11:49:41.831704 ===================================
6103 11:49:41.834773 EX_ROW_EN[0] = 0x0
6104 11:49:41.835246 EX_ROW_EN[1] = 0x0
6105 11:49:41.838016 LP4Y_EN = 0x0
6106 11:49:41.838519 WORK_FSP = 0x0
6107 11:49:41.841570 WL = 0x2
6108 11:49:41.842038 RL = 0x2
6109 11:49:41.845117 BL = 0x2
6110 11:49:41.845588 RPST = 0x0
6111 11:49:41.848314 RD_PRE = 0x0
6112 11:49:41.848896 WR_PRE = 0x1
6113 11:49:41.851260 WR_PST = 0x0
6114 11:49:41.851732 DBI_WR = 0x0
6115 11:49:41.854731 DBI_RD = 0x0
6116 11:49:41.855202 OTF = 0x1
6117 11:49:41.858184 ===================================
6118 11:49:41.861804 ===================================
6119 11:49:41.864915 ANA top config
6120 11:49:41.868713 ===================================
6121 11:49:41.871496 DLL_ASYNC_EN = 0
6122 11:49:41.872075 ALL_SLAVE_EN = 1
6123 11:49:41.874769 NEW_RANK_MODE = 1
6124 11:49:41.878338 DLL_IDLE_MODE = 1
6125 11:49:41.881124 LP45_APHY_COMB_EN = 1
6126 11:49:41.881597 TX_ODT_DIS = 1
6127 11:49:41.884772 NEW_8X_MODE = 1
6128 11:49:41.888041 ===================================
6129 11:49:41.891042 ===================================
6130 11:49:41.894462 data_rate = 800
6131 11:49:41.897731 CKR = 1
6132 11:49:41.901219 DQ_P2S_RATIO = 4
6133 11:49:41.904423 ===================================
6134 11:49:41.907564 CA_P2S_RATIO = 4
6135 11:49:41.908048 DQ_CA_OPEN = 0
6136 11:49:41.910903 DQ_SEMI_OPEN = 1
6137 11:49:41.914675 CA_SEMI_OPEN = 1
6138 11:49:41.918212 CA_FULL_RATE = 0
6139 11:49:41.921141 DQ_CKDIV4_EN = 0
6140 11:49:41.924353 CA_CKDIV4_EN = 1
6141 11:49:41.924841 CA_PREDIV_EN = 0
6142 11:49:41.928650 PH8_DLY = 0
6143 11:49:41.930900 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6144 11:49:41.934563 DQ_AAMCK_DIV = 0
6145 11:49:41.937487 CA_AAMCK_DIV = 0
6146 11:49:41.940951 CA_ADMCK_DIV = 4
6147 11:49:41.941427 DQ_TRACK_CA_EN = 0
6148 11:49:41.944236 CA_PICK = 800
6149 11:49:41.947620 CA_MCKIO = 400
6150 11:49:41.950886 MCKIO_SEMI = 400
6151 11:49:41.954470 PLL_FREQ = 3016
6152 11:49:41.957744 DQ_UI_PI_RATIO = 32
6153 11:49:41.960877 CA_UI_PI_RATIO = 32
6154 11:49:41.964511 ===================================
6155 11:49:41.967776 ===================================
6156 11:49:41.968428 memory_type:LPDDR4
6157 11:49:41.970772 GP_NUM : 10
6158 11:49:41.974297 SRAM_EN : 1
6159 11:49:41.974994 MD32_EN : 0
6160 11:49:41.978111 ===================================
6161 11:49:41.981072 [ANA_INIT] >>>>>>>>>>>>>>
6162 11:49:41.984465 <<<<<< [CONFIGURE PHASE]: ANA_TX
6163 11:49:41.987531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6164 11:49:41.991087 ===================================
6165 11:49:41.993976 data_rate = 800,PCW = 0X7400
6166 11:49:41.997684 ===================================
6167 11:49:42.001104 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6168 11:49:42.004080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6169 11:49:42.017506 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6170 11:49:42.020584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6171 11:49:42.024136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6172 11:49:42.027176 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6173 11:49:42.030501 [ANA_INIT] flow start
6174 11:49:42.030994 [ANA_INIT] PLL >>>>>>>>
6175 11:49:42.033686 [ANA_INIT] PLL <<<<<<<<
6176 11:49:42.037019 [ANA_INIT] MIDPI >>>>>>>>
6177 11:49:42.040560 [ANA_INIT] MIDPI <<<<<<<<
6178 11:49:42.041031 [ANA_INIT] DLL >>>>>>>>
6179 11:49:42.044104 [ANA_INIT] flow end
6180 11:49:42.047171 ============ LP4 DIFF to SE enter ============
6181 11:49:42.050550 ============ LP4 DIFF to SE exit ============
6182 11:49:42.054165 [ANA_INIT] <<<<<<<<<<<<<
6183 11:49:42.057447 [Flow] Enable top DCM control >>>>>
6184 11:49:42.060944 [Flow] Enable top DCM control <<<<<
6185 11:49:42.064095 Enable DLL master slave shuffle
6186 11:49:42.070502 ==============================================================
6187 11:49:42.071096 Gating Mode config
6188 11:49:42.077407 ==============================================================
6189 11:49:42.077992 Config description:
6190 11:49:42.087107 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6191 11:49:42.093653 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6192 11:49:42.100795 SELPH_MODE 0: By rank 1: By Phase
6193 11:49:42.103506 ==============================================================
6194 11:49:42.107313 GAT_TRACK_EN = 0
6195 11:49:42.110138 RX_GATING_MODE = 2
6196 11:49:42.113769 RX_GATING_TRACK_MODE = 2
6197 11:49:42.117245 SELPH_MODE = 1
6198 11:49:42.120823 PICG_EARLY_EN = 1
6199 11:49:42.123582 VALID_LAT_VALUE = 1
6200 11:49:42.127152 ==============================================================
6201 11:49:42.130553 Enter into Gating configuration >>>>
6202 11:49:42.133584 Exit from Gating configuration <<<<
6203 11:49:42.137047 Enter into DVFS_PRE_config >>>>>
6204 11:49:42.150341 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6205 11:49:42.153438 Exit from DVFS_PRE_config <<<<<
6206 11:49:42.156711 Enter into PICG configuration >>>>
6207 11:49:42.159948 Exit from PICG configuration <<<<
6208 11:49:42.160510 [RX_INPUT] configuration >>>>>
6209 11:49:42.163330 [RX_INPUT] configuration <<<<<
6210 11:49:42.170131 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6211 11:49:42.173435 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6212 11:49:42.179724 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6213 11:49:42.186625 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6214 11:49:42.193543 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6215 11:49:42.200341 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6216 11:49:42.203377 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6217 11:49:42.206907 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6218 11:49:42.213453 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6219 11:49:42.216493 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6220 11:49:42.220042 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6221 11:49:42.223627 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6222 11:49:42.226602 ===================================
6223 11:49:42.230099 LPDDR4 DRAM CONFIGURATION
6224 11:49:42.232999 ===================================
6225 11:49:42.236730 EX_ROW_EN[0] = 0x0
6226 11:49:42.237218 EX_ROW_EN[1] = 0x0
6227 11:49:42.240049 LP4Y_EN = 0x0
6228 11:49:42.240618 WORK_FSP = 0x0
6229 11:49:42.243365 WL = 0x2
6230 11:49:42.244025 RL = 0x2
6231 11:49:42.246210 BL = 0x2
6232 11:49:42.246724 RPST = 0x0
6233 11:49:42.249728 RD_PRE = 0x0
6234 11:49:42.250464 WR_PRE = 0x1
6235 11:49:42.252765 WR_PST = 0x0
6236 11:49:42.253356 DBI_WR = 0x0
6237 11:49:42.256409 DBI_RD = 0x0
6238 11:49:42.259435 OTF = 0x1
6239 11:49:42.259934 ===================================
6240 11:49:42.266219 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6241 11:49:42.269531 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6242 11:49:42.272730 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6243 11:49:42.276065 ===================================
6244 11:49:42.279400 LPDDR4 DRAM CONFIGURATION
6245 11:49:42.283140 ===================================
6246 11:49:42.285984 EX_ROW_EN[0] = 0x10
6247 11:49:42.286489 EX_ROW_EN[1] = 0x0
6248 11:49:42.289915 LP4Y_EN = 0x0
6249 11:49:42.290500 WORK_FSP = 0x0
6250 11:49:42.293124 WL = 0x2
6251 11:49:42.293608 RL = 0x2
6252 11:49:42.296464 BL = 0x2
6253 11:49:42.296962 RPST = 0x0
6254 11:49:42.299266 RD_PRE = 0x0
6255 11:49:42.299728 WR_PRE = 0x1
6256 11:49:42.302823 WR_PST = 0x0
6257 11:49:42.303288 DBI_WR = 0x0
6258 11:49:42.306251 DBI_RD = 0x0
6259 11:49:42.306756 OTF = 0x1
6260 11:49:42.309670 ===================================
6261 11:49:42.315812 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6262 11:49:42.320801 nWR fixed to 30
6263 11:49:42.324082 [ModeRegInit_LP4] CH0 RK0
6264 11:49:42.324544 [ModeRegInit_LP4] CH0 RK1
6265 11:49:42.327421 [ModeRegInit_LP4] CH1 RK0
6266 11:49:42.331024 [ModeRegInit_LP4] CH1 RK1
6267 11:49:42.331487 match AC timing 19
6268 11:49:42.337350 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6269 11:49:42.340659 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6270 11:49:42.344261 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6271 11:49:42.350790 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6272 11:49:42.353821 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6273 11:49:42.354284 ==
6274 11:49:42.357152 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 11:49:42.360582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 11:49:42.361129 ==
6277 11:49:42.367647 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6278 11:49:42.373784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6279 11:49:42.377314 [CA 0] Center 36 (8~64) winsize 57
6280 11:49:42.380753 [CA 1] Center 36 (8~64) winsize 57
6281 11:49:42.384014 [CA 2] Center 36 (8~64) winsize 57
6282 11:49:42.384480 [CA 3] Center 36 (8~64) winsize 57
6283 11:49:42.387393 [CA 4] Center 36 (8~64) winsize 57
6284 11:49:42.390496 [CA 5] Center 36 (8~64) winsize 57
6285 11:49:42.390956
6286 11:49:42.393953 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6287 11:49:42.397162
6288 11:49:42.401092 [CATrainingPosCal] consider 1 rank data
6289 11:49:42.401667 u2DelayCellTimex100 = 270/100 ps
6290 11:49:42.407049 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 11:49:42.410839 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 11:49:42.413742 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 11:49:42.417154 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 11:49:42.420767 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 11:49:42.424381 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 11:49:42.425002
6297 11:49:42.427366 CA PerBit enable=1, Macro0, CA PI delay=36
6298 11:49:42.427827
6299 11:49:42.430661 [CBTSetCACLKResult] CA Dly = 36
6300 11:49:42.433939 CS Dly: 1 (0~32)
6301 11:49:42.434662 ==
6302 11:49:42.437371 Dram Type= 6, Freq= 0, CH_0, rank 1
6303 11:49:42.440721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 11:49:42.441292 ==
6305 11:49:42.447221 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6306 11:49:42.450312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6307 11:49:42.453614 [CA 0] Center 36 (8~64) winsize 57
6308 11:49:42.457026 [CA 1] Center 36 (8~64) winsize 57
6309 11:49:42.460361 [CA 2] Center 36 (8~64) winsize 57
6310 11:49:42.463899 [CA 3] Center 36 (8~64) winsize 57
6311 11:49:42.466856 [CA 4] Center 36 (8~64) winsize 57
6312 11:49:42.470463 [CA 5] Center 36 (8~64) winsize 57
6313 11:49:42.471038
6314 11:49:42.473770 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6315 11:49:42.474233
6316 11:49:42.476952 [CATrainingPosCal] consider 2 rank data
6317 11:49:42.480201 u2DelayCellTimex100 = 270/100 ps
6318 11:49:42.483594 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 11:49:42.486976 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 11:49:42.490450 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 11:49:42.496854 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 11:49:42.500140 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 11:49:42.503289 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 11:49:42.503850
6325 11:49:42.506949 CA PerBit enable=1, Macro0, CA PI delay=36
6326 11:49:42.507520
6327 11:49:42.510476 [CBTSetCACLKResult] CA Dly = 36
6328 11:49:42.510941 CS Dly: 1 (0~32)
6329 11:49:42.511307
6330 11:49:42.513570 ----->DramcWriteLeveling(PI) begin...
6331 11:49:42.516701 ==
6332 11:49:42.517164 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 11:49:42.523273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 11:49:42.523738 ==
6335 11:49:42.526913 Write leveling (Byte 0): 40 => 8
6336 11:49:42.530550 Write leveling (Byte 1): 32 => 0
6337 11:49:42.531128 DramcWriteLeveling(PI) end<-----
6338 11:49:42.533609
6339 11:49:42.534066 ==
6340 11:49:42.536626 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 11:49:42.540344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 11:49:42.540920 ==
6343 11:49:42.543287 [Gating] SW mode calibration
6344 11:49:42.550029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6345 11:49:42.553399 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6346 11:49:42.560211 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6347 11:49:42.563077 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6348 11:49:42.566491 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6349 11:49:42.573140 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6350 11:49:42.576797 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 11:49:42.579860 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 11:49:42.586232 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 11:49:42.589902 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 11:49:42.593283 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6355 11:49:42.596095 Total UI for P1: 0, mck2ui 16
6356 11:49:42.599642 best dqsien dly found for B0: ( 0, 14, 24)
6357 11:49:42.602983 Total UI for P1: 0, mck2ui 16
6358 11:49:42.606261 best dqsien dly found for B1: ( 0, 14, 24)
6359 11:49:42.609432 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6360 11:49:42.612669 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6361 11:49:42.613119
6362 11:49:42.619570 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6363 11:49:42.622721 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6364 11:49:42.625997 [Gating] SW calibration Done
6365 11:49:42.626479 ==
6366 11:49:42.629292 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 11:49:42.632920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 11:49:42.633374 ==
6369 11:49:42.633730 RX Vref Scan: 0
6370 11:49:42.634064
6371 11:49:42.635964 RX Vref 0 -> 0, step: 1
6372 11:49:42.636430
6373 11:49:42.639791 RX Delay -410 -> 252, step: 16
6374 11:49:42.642799 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6375 11:49:42.649234 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6376 11:49:42.653025 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6377 11:49:42.656174 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6378 11:49:42.659601 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6379 11:49:42.666041 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6380 11:49:42.669114 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6381 11:49:42.673222 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6382 11:49:42.676460 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6383 11:49:42.679486 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6384 11:49:42.686353 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6385 11:49:42.689465 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6386 11:49:42.692705 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6387 11:49:42.699417 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6388 11:49:42.702519 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6389 11:49:42.705937 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6390 11:49:42.706577 ==
6391 11:49:42.709348 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 11:49:42.712682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 11:49:42.713255 ==
6394 11:49:42.716042 DQS Delay:
6395 11:49:42.716636 DQS0 = 27, DQS1 = 43
6396 11:49:42.719453 DQM Delay:
6397 11:49:42.719923 DQM0 = 11, DQM1 = 13
6398 11:49:42.722998 DQ Delay:
6399 11:49:42.723566 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6400 11:49:42.726624 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6401 11:49:42.730008 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6402 11:49:42.732774 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6403 11:49:42.733340
6404 11:49:42.733875
6405 11:49:42.734231 ==
6406 11:49:42.736461 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 11:49:42.742672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 11:49:42.743191 ==
6409 11:49:42.743580
6410 11:49:42.744119
6411 11:49:42.744611 TX Vref Scan disable
6412 11:49:42.746136 == TX Byte 0 ==
6413 11:49:42.749539 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 11:49:42.753335 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 11:49:42.756115 == TX Byte 1 ==
6416 11:49:42.759088 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6417 11:49:42.762638 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6418 11:49:42.766282 ==
6419 11:49:42.769310 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 11:49:42.773121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 11:49:42.773696 ==
6422 11:49:42.774075
6423 11:49:42.774456
6424 11:49:42.775791 TX Vref Scan disable
6425 11:49:42.776267 == TX Byte 0 ==
6426 11:49:42.779562 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6427 11:49:42.785707 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6428 11:49:42.786275 == TX Byte 1 ==
6429 11:49:42.789130 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6430 11:49:42.796028 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6431 11:49:42.796775
6432 11:49:42.797282 [DATLAT]
6433 11:49:42.797637 Freq=400, CH0 RK0
6434 11:49:42.797972
6435 11:49:42.798715 DATLAT Default: 0xf
6436 11:49:42.802009 0, 0xFFFF, sum = 0
6437 11:49:42.802524 1, 0xFFFF, sum = 0
6438 11:49:42.805597 2, 0xFFFF, sum = 0
6439 11:49:42.806147 3, 0xFFFF, sum = 0
6440 11:49:42.809072 4, 0xFFFF, sum = 0
6441 11:49:42.809540 5, 0xFFFF, sum = 0
6442 11:49:42.811942 6, 0xFFFF, sum = 0
6443 11:49:42.812412 7, 0xFFFF, sum = 0
6444 11:49:42.815581 8, 0xFFFF, sum = 0
6445 11:49:42.816051 9, 0xFFFF, sum = 0
6446 11:49:42.818900 10, 0xFFFF, sum = 0
6447 11:49:42.819371 11, 0xFFFF, sum = 0
6448 11:49:42.822437 12, 0xFFFF, sum = 0
6449 11:49:42.823021 13, 0x0, sum = 1
6450 11:49:42.825452 14, 0x0, sum = 2
6451 11:49:42.825925 15, 0x0, sum = 3
6452 11:49:42.828766 16, 0x0, sum = 4
6453 11:49:42.829240 best_step = 14
6454 11:49:42.829603
6455 11:49:42.829940 ==
6456 11:49:42.832461 Dram Type= 6, Freq= 0, CH_0, rank 0
6457 11:49:42.838855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 11:49:42.839327 ==
6459 11:49:42.839693 RX Vref Scan: 1
6460 11:49:42.840035
6461 11:49:42.842046 RX Vref 0 -> 0, step: 1
6462 11:49:42.842537
6463 11:49:42.845299 RX Delay -327 -> 252, step: 8
6464 11:49:42.845764
6465 11:49:42.848875 Set Vref, RX VrefLevel [Byte0]: 60
6466 11:49:42.852818 [Byte1]: 50
6467 11:49:42.853387
6468 11:49:42.855249 Final RX Vref Byte 0 = 60 to rank0
6469 11:49:42.858856 Final RX Vref Byte 1 = 50 to rank0
6470 11:49:42.862057 Final RX Vref Byte 0 = 60 to rank1
6471 11:49:42.865782 Final RX Vref Byte 1 = 50 to rank1==
6472 11:49:42.868662 Dram Type= 6, Freq= 0, CH_0, rank 0
6473 11:49:42.872198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 11:49:42.872777 ==
6475 11:49:42.875091 DQS Delay:
6476 11:49:42.875551 DQS0 = 28, DQS1 = 48
6477 11:49:42.878631 DQM Delay:
6478 11:49:42.879202 DQM0 = 12, DQM1 = 15
6479 11:49:42.879575 DQ Delay:
6480 11:49:42.882373 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6481 11:49:42.885450 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6482 11:49:42.888409 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6483 11:49:42.892094 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6484 11:49:42.892655
6485 11:49:42.893022
6486 11:49:42.901885 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaa2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6487 11:49:42.904824 CH0 RK0: MR19=C0C, MR18=AAA2
6488 11:49:42.908224 CH0_RK0: MR19=0xC0C, MR18=0xAAA2, DQSOSC=388, MR23=63, INC=392, DEC=261
6489 11:49:42.911558 ==
6490 11:49:42.914645 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 11:49:42.918208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 11:49:42.918791 ==
6493 11:49:42.921519 [Gating] SW mode calibration
6494 11:49:42.928317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6495 11:49:42.931945 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6496 11:49:42.938027 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6497 11:49:42.941437 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6498 11:49:42.945294 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6499 11:49:42.951368 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 11:49:42.954939 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 11:49:42.958658 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 11:49:42.964728 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 11:49:42.968013 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 11:49:42.971180 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6505 11:49:42.974775 Total UI for P1: 0, mck2ui 16
6506 11:49:42.977984 best dqsien dly found for B0: ( 0, 14, 24)
6507 11:49:42.981464 Total UI for P1: 0, mck2ui 16
6508 11:49:42.984459 best dqsien dly found for B1: ( 0, 14, 24)
6509 11:49:42.988279 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6510 11:49:42.991192 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6511 11:49:42.991688
6512 11:49:42.997920 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6513 11:49:43.000987 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6514 11:49:43.004536 [Gating] SW calibration Done
6515 11:49:43.005000 ==
6516 11:49:43.007886 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 11:49:43.011444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 11:49:43.011917 ==
6519 11:49:43.012285 RX Vref Scan: 0
6520 11:49:43.012625
6521 11:49:43.014712 RX Vref 0 -> 0, step: 1
6522 11:49:43.015278
6523 11:49:43.017620 RX Delay -410 -> 252, step: 16
6524 11:49:43.020962 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6525 11:49:43.027526 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6526 11:49:43.031404 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6527 11:49:43.034125 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6528 11:49:43.037593 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6529 11:49:43.044650 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6530 11:49:43.047933 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6531 11:49:43.051021 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6532 11:49:43.054484 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6533 11:49:43.058365 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6534 11:49:43.064747 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6535 11:49:43.067444 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6536 11:49:43.070911 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6537 11:49:43.077726 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6538 11:49:43.081642 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6539 11:49:43.084243 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6540 11:49:43.084782 ==
6541 11:49:43.087559 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 11:49:43.090835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 11:49:43.094434 ==
6544 11:49:43.095049 DQS Delay:
6545 11:49:43.095465 DQS0 = 27, DQS1 = 43
6546 11:49:43.097422 DQM Delay:
6547 11:49:43.098001 DQM0 = 9, DQM1 = 15
6548 11:49:43.100876 DQ Delay:
6549 11:49:43.101358 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6550 11:49:43.104158 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6551 11:49:43.107902 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6552 11:49:43.110594 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6553 11:49:43.111147
6554 11:49:43.111521
6555 11:49:43.111864 ==
6556 11:49:43.114072 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 11:49:43.120798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 11:49:43.121286 ==
6559 11:49:43.121659
6560 11:49:43.122000
6561 11:49:43.122326 TX Vref Scan disable
6562 11:49:43.123816 == TX Byte 0 ==
6563 11:49:43.127372 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6564 11:49:43.130662 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6565 11:49:43.133852 == TX Byte 1 ==
6566 11:49:43.137305 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6567 11:49:43.140265 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6568 11:49:43.143580 ==
6569 11:49:43.144132 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 11:49:43.150526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 11:49:43.151003 ==
6572 11:49:43.151603
6573 11:49:43.151979
6574 11:49:43.152320 TX Vref Scan disable
6575 11:49:43.153698 == TX Byte 0 ==
6576 11:49:43.157262 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6577 11:49:43.160788 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6578 11:49:43.163611 == TX Byte 1 ==
6579 11:49:43.167104 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6580 11:49:43.170625 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6581 11:49:43.171091
6582 11:49:43.173774 [DATLAT]
6583 11:49:43.174439 Freq=400, CH0 RK1
6584 11:49:43.174832
6585 11:49:43.177327 DATLAT Default: 0xe
6586 11:49:43.177901 0, 0xFFFF, sum = 0
6587 11:49:43.180394 1, 0xFFFF, sum = 0
6588 11:49:43.180975 2, 0xFFFF, sum = 0
6589 11:49:43.184009 3, 0xFFFF, sum = 0
6590 11:49:43.184498 4, 0xFFFF, sum = 0
6591 11:49:43.187065 5, 0xFFFF, sum = 0
6592 11:49:43.187650 6, 0xFFFF, sum = 0
6593 11:49:43.190177 7, 0xFFFF, sum = 0
6594 11:49:43.193530 8, 0xFFFF, sum = 0
6595 11:49:43.194040 9, 0xFFFF, sum = 0
6596 11:49:43.196789 10, 0xFFFF, sum = 0
6597 11:49:43.197280 11, 0xFFFF, sum = 0
6598 11:49:43.199886 12, 0xFFFF, sum = 0
6599 11:49:43.200451 13, 0x0, sum = 1
6600 11:49:43.203764 14, 0x0, sum = 2
6601 11:49:43.204346 15, 0x0, sum = 3
6602 11:49:43.207231 16, 0x0, sum = 4
6603 11:49:43.207885 best_step = 14
6604 11:49:43.208468
6605 11:49:43.208985 ==
6606 11:49:43.210256 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 11:49:43.213479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 11:49:43.214130 ==
6609 11:49:43.216743 RX Vref Scan: 0
6610 11:49:43.217400
6611 11:49:43.220149 RX Vref 0 -> 0, step: 1
6612 11:49:43.220775
6613 11:49:43.221174 RX Delay -327 -> 252, step: 8
6614 11:49:43.229123 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6615 11:49:43.231913 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6616 11:49:43.235380 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6617 11:49:43.238427 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6618 11:49:43.245372 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6619 11:49:43.248849 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6620 11:49:43.252001 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6621 11:49:43.255525 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6622 11:49:43.262080 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6623 11:49:43.265429 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6624 11:49:43.268453 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6625 11:49:43.275481 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6626 11:49:43.278470 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6627 11:49:43.282143 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6628 11:49:43.285421 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6629 11:49:43.291794 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6630 11:49:43.292266 ==
6631 11:49:43.295164 Dram Type= 6, Freq= 0, CH_0, rank 1
6632 11:49:43.298417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 11:49:43.299260 ==
6634 11:49:43.299895 DQS Delay:
6635 11:49:43.301884 DQS0 = 28, DQS1 = 44
6636 11:49:43.302348 DQM Delay:
6637 11:49:43.304872 DQM0 = 9, DQM1 = 15
6638 11:49:43.305338 DQ Delay:
6639 11:49:43.308280 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6640 11:49:43.311933 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6641 11:49:43.314984 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6642 11:49:43.318510 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6643 11:49:43.319068
6644 11:49:43.319444
6645 11:49:43.325492 [DQSOSCAuto] RK1, (LSB)MR18= 0xb569, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6646 11:49:43.328825 CH0 RK1: MR19=C0C, MR18=B569
6647 11:49:43.335234 CH0_RK1: MR19=0xC0C, MR18=0xB569, DQSOSC=387, MR23=63, INC=394, DEC=262
6648 11:49:43.338855 [RxdqsGatingPostProcess] freq 400
6649 11:49:43.344939 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6650 11:49:43.345508 best DQS0 dly(2T, 0.5T) = (0, 10)
6651 11:49:43.348514 best DQS1 dly(2T, 0.5T) = (0, 10)
6652 11:49:43.351669 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6653 11:49:43.354577 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6654 11:49:43.358338 best DQS0 dly(2T, 0.5T) = (0, 10)
6655 11:49:43.361468 best DQS1 dly(2T, 0.5T) = (0, 10)
6656 11:49:43.364910 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6657 11:49:43.368357 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6658 11:49:43.371722 Pre-setting of DQS Precalculation
6659 11:49:43.378102 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6660 11:49:43.378615 ==
6661 11:49:43.381443 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 11:49:43.384474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 11:49:43.384937 ==
6664 11:49:43.391360 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6665 11:49:43.395031 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6666 11:49:43.397886 [CA 0] Center 36 (8~64) winsize 57
6667 11:49:43.401232 [CA 1] Center 36 (8~64) winsize 57
6668 11:49:43.404739 [CA 2] Center 36 (8~64) winsize 57
6669 11:49:43.407727 [CA 3] Center 36 (8~64) winsize 57
6670 11:49:43.410995 [CA 4] Center 36 (8~64) winsize 57
6671 11:49:43.414681 [CA 5] Center 36 (8~64) winsize 57
6672 11:49:43.415247
6673 11:49:43.417619 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6674 11:49:43.418104
6675 11:49:43.420941 [CATrainingPosCal] consider 1 rank data
6676 11:49:43.424777 u2DelayCellTimex100 = 270/100 ps
6677 11:49:43.427534 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 11:49:43.431006 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 11:49:43.437661 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 11:49:43.440888 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 11:49:43.444421 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 11:49:43.447453 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 11:49:43.447916
6684 11:49:43.450613 CA PerBit enable=1, Macro0, CA PI delay=36
6685 11:49:43.451077
6686 11:49:43.453888 [CBTSetCACLKResult] CA Dly = 36
6687 11:49:43.454353 CS Dly: 1 (0~32)
6688 11:49:43.457683 ==
6689 11:49:43.458257 Dram Type= 6, Freq= 0, CH_1, rank 1
6690 11:49:43.464011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 11:49:43.464480 ==
6692 11:49:43.467229 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6693 11:49:43.474002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6694 11:49:43.477409 [CA 0] Center 36 (8~64) winsize 57
6695 11:49:43.480586 [CA 1] Center 36 (8~64) winsize 57
6696 11:49:43.483906 [CA 2] Center 36 (8~64) winsize 57
6697 11:49:43.487407 [CA 3] Center 36 (8~64) winsize 57
6698 11:49:43.490529 [CA 4] Center 36 (8~64) winsize 57
6699 11:49:43.493902 [CA 5] Center 36 (8~64) winsize 57
6700 11:49:43.494374
6701 11:49:43.497137 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6702 11:49:43.497629
6703 11:49:43.500773 [CATrainingPosCal] consider 2 rank data
6704 11:49:43.503706 u2DelayCellTimex100 = 270/100 ps
6705 11:49:43.507322 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 11:49:43.510926 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 11:49:43.513626 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 11:49:43.517073 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 11:49:43.520890 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 11:49:43.527289 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 11:49:43.527845
6712 11:49:43.530843 CA PerBit enable=1, Macro0, CA PI delay=36
6713 11:49:43.531421
6714 11:49:43.534082 [CBTSetCACLKResult] CA Dly = 36
6715 11:49:43.534689 CS Dly: 1 (0~32)
6716 11:49:43.535175
6717 11:49:43.537294 ----->DramcWriteLeveling(PI) begin...
6718 11:49:43.537778 ==
6719 11:49:43.540675 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 11:49:43.544004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 11:49:43.546914 ==
6722 11:49:43.547391 Write leveling (Byte 0): 40 => 8
6723 11:49:43.550496 Write leveling (Byte 1): 32 => 0
6724 11:49:43.554008 DramcWriteLeveling(PI) end<-----
6725 11:49:43.554632
6726 11:49:43.555117 ==
6727 11:49:43.557367 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 11:49:43.563578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 11:49:43.564061 ==
6730 11:49:43.564539 [Gating] SW mode calibration
6731 11:49:43.573811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6732 11:49:43.577016 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6733 11:49:43.583509 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6734 11:49:43.586628 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6735 11:49:43.590366 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6736 11:49:43.593651 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6737 11:49:43.599963 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 11:49:43.603455 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 11:49:43.606648 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 11:49:43.613577 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 11:49:43.616893 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6742 11:49:43.620560 Total UI for P1: 0, mck2ui 16
6743 11:49:43.623665 best dqsien dly found for B0: ( 0, 14, 24)
6744 11:49:43.626482 Total UI for P1: 0, mck2ui 16
6745 11:49:43.630159 best dqsien dly found for B1: ( 0, 14, 24)
6746 11:49:43.633969 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6747 11:49:43.636986 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6748 11:49:43.637629
6749 11:49:43.639860 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6750 11:49:43.646497 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6751 11:49:43.646976 [Gating] SW calibration Done
6752 11:49:43.647452 ==
6753 11:49:43.650207 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 11:49:43.656872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 11:49:43.657461 ==
6756 11:49:43.657952 RX Vref Scan: 0
6757 11:49:43.658427
6758 11:49:43.659789 RX Vref 0 -> 0, step: 1
6759 11:49:43.660266
6760 11:49:43.663721 RX Delay -410 -> 252, step: 16
6761 11:49:43.666460 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6762 11:49:43.669772 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6763 11:49:43.676505 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6764 11:49:43.679954 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6765 11:49:43.683069 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6766 11:49:43.686507 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6767 11:49:43.693436 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6768 11:49:43.696196 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6769 11:49:43.699513 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6770 11:49:43.702878 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6771 11:49:43.709913 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6772 11:49:43.713076 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6773 11:49:43.716209 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6774 11:49:43.719667 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6775 11:49:43.726426 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6776 11:49:43.730056 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6777 11:49:43.730709 ==
6778 11:49:43.733033 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 11:49:43.736092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 11:49:43.736557 ==
6781 11:49:43.739475 DQS Delay:
6782 11:49:43.739953 DQS0 = 27, DQS1 = 43
6783 11:49:43.743036 DQM Delay:
6784 11:49:43.743527 DQM0 = 9, DQM1 = 18
6785 11:49:43.743903 DQ Delay:
6786 11:49:43.746140 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6787 11:49:43.749792 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6788 11:49:43.753113 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6789 11:49:43.756382 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =32
6790 11:49:43.756966
6791 11:49:43.757360
6792 11:49:43.757706 ==
6793 11:49:43.759799 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 11:49:43.763046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 11:49:43.763541 ==
6796 11:49:43.766355
6797 11:49:43.767006
6798 11:49:43.767411 TX Vref Scan disable
6799 11:49:43.769608 == TX Byte 0 ==
6800 11:49:43.773301 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 11:49:43.776140 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 11:49:43.779744 == TX Byte 1 ==
6803 11:49:43.782958 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6804 11:49:43.786451 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6805 11:49:43.786914 ==
6806 11:49:43.790088 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 11:49:43.796383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 11:49:43.796964 ==
6809 11:49:43.797390
6810 11:49:43.797921
6811 11:49:43.798272 TX Vref Scan disable
6812 11:49:43.799426 == TX Byte 0 ==
6813 11:49:43.803033 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6814 11:49:43.806522 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6815 11:49:43.809757 == TX Byte 1 ==
6816 11:49:43.812887 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6817 11:49:43.816260 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6818 11:49:43.816829
6819 11:49:43.819231 [DATLAT]
6820 11:49:43.819753 Freq=400, CH1 RK0
6821 11:49:43.820132
6822 11:49:43.823403 DATLAT Default: 0xf
6823 11:49:43.824133 0, 0xFFFF, sum = 0
6824 11:49:43.826856 1, 0xFFFF, sum = 0
6825 11:49:43.827434 2, 0xFFFF, sum = 0
6826 11:49:43.829151 3, 0xFFFF, sum = 0
6827 11:49:43.829625 4, 0xFFFF, sum = 0
6828 11:49:43.832822 5, 0xFFFF, sum = 0
6829 11:49:43.833401 6, 0xFFFF, sum = 0
6830 11:49:43.836473 7, 0xFFFF, sum = 0
6831 11:49:43.837095 8, 0xFFFF, sum = 0
6832 11:49:43.840058 9, 0xFFFF, sum = 0
6833 11:49:43.840634 10, 0xFFFF, sum = 0
6834 11:49:43.842587 11, 0xFFFF, sum = 0
6835 11:49:43.845993 12, 0xFFFF, sum = 0
6836 11:49:43.846515 13, 0x0, sum = 1
6837 11:49:43.846902 14, 0x0, sum = 2
6838 11:49:43.849366 15, 0x0, sum = 3
6839 11:49:43.849948 16, 0x0, sum = 4
6840 11:49:43.852990 best_step = 14
6841 11:49:43.853561
6842 11:49:43.853933 ==
6843 11:49:43.856096 Dram Type= 6, Freq= 0, CH_1, rank 0
6844 11:49:43.859301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 11:49:43.859876 ==
6846 11:49:43.863274 RX Vref Scan: 1
6847 11:49:43.863843
6848 11:49:43.864210 RX Vref 0 -> 0, step: 1
6849 11:49:43.864554
6850 11:49:43.866331 RX Delay -327 -> 252, step: 8
6851 11:49:43.866952
6852 11:49:43.869480 Set Vref, RX VrefLevel [Byte0]: 52
6853 11:49:43.872731 [Byte1]: 52
6854 11:49:43.877626
6855 11:49:43.878196 Final RX Vref Byte 0 = 52 to rank0
6856 11:49:43.881247 Final RX Vref Byte 1 = 52 to rank0
6857 11:49:43.884319 Final RX Vref Byte 0 = 52 to rank1
6858 11:49:43.887787 Final RX Vref Byte 1 = 52 to rank1==
6859 11:49:43.890931 Dram Type= 6, Freq= 0, CH_1, rank 0
6860 11:49:43.897080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 11:49:43.897549 ==
6862 11:49:43.897932 DQS Delay:
6863 11:49:43.900673 DQS0 = 28, DQS1 = 40
6864 11:49:43.901138 DQM Delay:
6865 11:49:43.901507 DQM0 = 7, DQM1 = 12
6866 11:49:43.904165 DQ Delay:
6867 11:49:43.907403 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6868 11:49:43.907909 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6869 11:49:43.910739 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6870 11:49:43.913859 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6871 11:49:43.914694
6872 11:49:43.915117
6873 11:49:43.924097 [DQSOSCAuto] RK0, (LSB)MR18= 0x9cd7, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6874 11:49:43.927079 CH1 RK0: MR19=C0C, MR18=9CD7
6875 11:49:43.934210 CH1_RK0: MR19=0xC0C, MR18=0x9CD7, DQSOSC=383, MR23=63, INC=402, DEC=268
6876 11:49:43.934841 ==
6877 11:49:43.937493 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 11:49:43.941391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 11:49:43.941973 ==
6880 11:49:43.943618 [Gating] SW mode calibration
6881 11:49:43.951092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6882 11:49:43.954168 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6883 11:49:43.960526 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6884 11:49:43.964216 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6885 11:49:43.967751 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6886 11:49:43.974365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6887 11:49:43.977572 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 11:49:43.980754 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 11:49:43.987233 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 11:49:43.990728 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 11:49:43.993660 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6892 11:49:43.997136 Total UI for P1: 0, mck2ui 16
6893 11:49:44.000063 best dqsien dly found for B0: ( 0, 14, 24)
6894 11:49:44.003762 Total UI for P1: 0, mck2ui 16
6895 11:49:44.007278 best dqsien dly found for B1: ( 0, 14, 24)
6896 11:49:44.010473 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6897 11:49:44.013683 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6898 11:49:44.014255
6899 11:49:44.020221 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6900 11:49:44.023265 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6901 11:49:44.026986 [Gating] SW calibration Done
6902 11:49:44.027453 ==
6903 11:49:44.030197 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 11:49:44.033256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 11:49:44.033727 ==
6906 11:49:44.034096 RX Vref Scan: 0
6907 11:49:44.034486
6908 11:49:44.037033 RX Vref 0 -> 0, step: 1
6909 11:49:44.037500
6910 11:49:44.040112 RX Delay -410 -> 252, step: 16
6911 11:49:44.043242 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6912 11:49:44.050450 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6913 11:49:44.053944 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6914 11:49:44.056585 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6915 11:49:44.060300 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6916 11:49:44.066939 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6917 11:49:44.069868 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6918 11:49:44.073364 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6919 11:49:44.076765 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6920 11:49:44.083211 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6921 11:49:44.086505 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6922 11:49:44.090052 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6923 11:49:44.093361 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6924 11:49:44.099963 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6925 11:49:44.103357 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6926 11:49:44.106487 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6927 11:49:44.106954 ==
6928 11:49:44.110095 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 11:49:44.113336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 11:49:44.116444 ==
6931 11:49:44.116909 DQS Delay:
6932 11:49:44.117321 DQS0 = 35, DQS1 = 35
6933 11:49:44.119605 DQM Delay:
6934 11:49:44.120067 DQM0 = 16, DQM1 = 13
6935 11:49:44.122990 DQ Delay:
6936 11:49:44.126233 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6937 11:49:44.126742 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6938 11:49:44.129966 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6939 11:49:44.132994 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6940 11:49:44.133514
6941 11:49:44.136409
6942 11:49:44.136873 ==
6943 11:49:44.139759 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 11:49:44.143050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 11:49:44.143780 ==
6946 11:49:44.144245
6947 11:49:44.144638
6948 11:49:44.146242 TX Vref Scan disable
6949 11:49:44.146778 == TX Byte 0 ==
6950 11:49:44.150063 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6951 11:49:44.156238 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6952 11:49:44.156704 == TX Byte 1 ==
6953 11:49:44.159446 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6954 11:49:44.166268 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6955 11:49:44.166879 ==
6956 11:49:44.169724 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 11:49:44.173014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 11:49:44.173554 ==
6959 11:49:44.173924
6960 11:49:44.174314
6961 11:49:44.176523 TX Vref Scan disable
6962 11:49:44.177085 == TX Byte 0 ==
6963 11:49:44.179413 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6964 11:49:44.186765 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6965 11:49:44.187293 == TX Byte 1 ==
6966 11:49:44.189947 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6967 11:49:44.196491 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6968 11:49:44.197027
6969 11:49:44.197398 [DATLAT]
6970 11:49:44.197800 Freq=400, CH1 RK1
6971 11:49:44.198186
6972 11:49:44.199615 DATLAT Default: 0xe
6973 11:49:44.200101 0, 0xFFFF, sum = 0
6974 11:49:44.202978 1, 0xFFFF, sum = 0
6975 11:49:44.206150 2, 0xFFFF, sum = 0
6976 11:49:44.206687 3, 0xFFFF, sum = 0
6977 11:49:44.209449 4, 0xFFFF, sum = 0
6978 11:49:44.209876 5, 0xFFFF, sum = 0
6979 11:49:44.212689 6, 0xFFFF, sum = 0
6980 11:49:44.213116 7, 0xFFFF, sum = 0
6981 11:49:44.216138 8, 0xFFFF, sum = 0
6982 11:49:44.216563 9, 0xFFFF, sum = 0
6983 11:49:44.219677 10, 0xFFFF, sum = 0
6984 11:49:44.220256 11, 0xFFFF, sum = 0
6985 11:49:44.222818 12, 0xFFFF, sum = 0
6986 11:49:44.223335 13, 0x0, sum = 1
6987 11:49:44.225930 14, 0x0, sum = 2
6988 11:49:44.226421 15, 0x0, sum = 3
6989 11:49:44.229469 16, 0x0, sum = 4
6990 11:49:44.229918 best_step = 14
6991 11:49:44.230269
6992 11:49:44.230630 ==
6993 11:49:44.232607 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 11:49:44.236205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 11:49:44.236723 ==
6996 11:49:44.239422 RX Vref Scan: 0
6997 11:49:44.239845
6998 11:49:44.242652 RX Vref 0 -> 0, step: 1
6999 11:49:44.243079
7000 11:49:44.243410 RX Delay -311 -> 252, step: 8
7001 11:49:44.251805 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
7002 11:49:44.254935 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7003 11:49:44.258306 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7004 11:49:44.261831 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
7005 11:49:44.268467 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7006 11:49:44.271375 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7007 11:49:44.274891 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7008 11:49:44.278487 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
7009 11:49:44.284609 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7010 11:49:44.288603 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7011 11:49:44.291631 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7012 11:49:44.297917 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
7013 11:49:44.301449 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7014 11:49:44.304883 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7015 11:49:44.307962 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7016 11:49:44.314517 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
7017 11:49:44.315137 ==
7018 11:49:44.317896 Dram Type= 6, Freq= 0, CH_1, rank 1
7019 11:49:44.321307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7020 11:49:44.321777 ==
7021 11:49:44.322147 DQS Delay:
7022 11:49:44.324854 DQS0 = 32, DQS1 = 36
7023 11:49:44.325343 DQM Delay:
7024 11:49:44.327959 DQM0 = 11, DQM1 = 10
7025 11:49:44.328424 DQ Delay:
7026 11:49:44.331510 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
7027 11:49:44.335058 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
7028 11:49:44.337712 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7029 11:49:44.341047 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7030 11:49:44.341489
7031 11:49:44.341824
7032 11:49:44.347767 [DQSOSCAuto] RK1, (LSB)MR18= 0xaa51, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7033 11:49:44.351005 CH1 RK1: MR19=C0C, MR18=AA51
7034 11:49:44.357829 CH1_RK1: MR19=0xC0C, MR18=0xAA51, DQSOSC=388, MR23=63, INC=392, DEC=261
7035 11:49:44.361091 [RxdqsGatingPostProcess] freq 400
7036 11:49:44.368414 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7037 11:49:44.368927 best DQS0 dly(2T, 0.5T) = (0, 10)
7038 11:49:44.370992 best DQS1 dly(2T, 0.5T) = (0, 10)
7039 11:49:44.374557 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7040 11:49:44.378027 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7041 11:49:44.381332 best DQS0 dly(2T, 0.5T) = (0, 10)
7042 11:49:44.384460 best DQS1 dly(2T, 0.5T) = (0, 10)
7043 11:49:44.387871 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7044 11:49:44.390922 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7045 11:49:44.394372 Pre-setting of DQS Precalculation
7046 11:49:44.401113 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7047 11:49:44.407714 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7048 11:49:44.414485 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7049 11:49:44.414969
7050 11:49:44.415447
7051 11:49:44.417701 [Calibration Summary] 800 Mbps
7052 11:49:44.418186 CH 0, Rank 0
7053 11:49:44.420858 SW Impedance : PASS
7054 11:49:44.424141 DUTY Scan : NO K
7055 11:49:44.424680 ZQ Calibration : PASS
7056 11:49:44.427814 Jitter Meter : NO K
7057 11:49:44.428249 CBT Training : PASS
7058 11:49:44.431025 Write leveling : PASS
7059 11:49:44.434533 RX DQS gating : PASS
7060 11:49:44.435065 RX DQ/DQS(RDDQC) : PASS
7061 11:49:44.437782 TX DQ/DQS : PASS
7062 11:49:44.440781 RX DATLAT : PASS
7063 11:49:44.441219 RX DQ/DQS(Engine): PASS
7064 11:49:44.444041 TX OE : NO K
7065 11:49:44.444473 All Pass.
7066 11:49:44.444916
7067 11:49:44.447610 CH 0, Rank 1
7068 11:49:44.448032 SW Impedance : PASS
7069 11:49:44.450848 DUTY Scan : NO K
7070 11:49:44.454241 ZQ Calibration : PASS
7071 11:49:44.454691 Jitter Meter : NO K
7072 11:49:44.457375 CBT Training : PASS
7073 11:49:44.460703 Write leveling : NO K
7074 11:49:44.461219 RX DQS gating : PASS
7075 11:49:44.463953 RX DQ/DQS(RDDQC) : PASS
7076 11:49:44.467308 TX DQ/DQS : PASS
7077 11:49:44.467733 RX DATLAT : PASS
7078 11:49:44.470727 RX DQ/DQS(Engine): PASS
7079 11:49:44.474175 TX OE : NO K
7080 11:49:44.474767 All Pass.
7081 11:49:44.475111
7082 11:49:44.475430 CH 1, Rank 0
7083 11:49:44.477776 SW Impedance : PASS
7084 11:49:44.478298 DUTY Scan : NO K
7085 11:49:44.481133 ZQ Calibration : PASS
7086 11:49:44.484463 Jitter Meter : NO K
7087 11:49:44.484981 CBT Training : PASS
7088 11:49:44.487282 Write leveling : PASS
7089 11:49:44.491318 RX DQS gating : PASS
7090 11:49:44.491840 RX DQ/DQS(RDDQC) : PASS
7091 11:49:44.494221 TX DQ/DQS : PASS
7092 11:49:44.497631 RX DATLAT : PASS
7093 11:49:44.498153 RX DQ/DQS(Engine): PASS
7094 11:49:44.500878 TX OE : NO K
7095 11:49:44.501323 All Pass.
7096 11:49:44.501657
7097 11:49:44.504344 CH 1, Rank 1
7098 11:49:44.504863 SW Impedance : PASS
7099 11:49:44.507296 DUTY Scan : NO K
7100 11:49:44.510483 ZQ Calibration : PASS
7101 11:49:44.510903 Jitter Meter : NO K
7102 11:49:44.513747 CBT Training : PASS
7103 11:49:44.517104 Write leveling : NO K
7104 11:49:44.517525 RX DQS gating : PASS
7105 11:49:44.520746 RX DQ/DQS(RDDQC) : PASS
7106 11:49:44.523712 TX DQ/DQS : PASS
7107 11:49:44.524140 RX DATLAT : PASS
7108 11:49:44.527064 RX DQ/DQS(Engine): PASS
7109 11:49:44.527485 TX OE : NO K
7110 11:49:44.530378 All Pass.
7111 11:49:44.530829
7112 11:49:44.531161 DramC Write-DBI off
7113 11:49:44.533925 PER_BANK_REFRESH: Hybrid Mode
7114 11:49:44.537921 TX_TRACKING: ON
7115 11:49:44.543546 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7116 11:49:44.546881 [FAST_K] Save calibration result to emmc
7117 11:49:44.553589 dramc_set_vcore_voltage set vcore to 725000
7118 11:49:44.554017 Read voltage for 1600, 0
7119 11:49:44.556991 Vio18 = 0
7120 11:49:44.557412 Vcore = 725000
7121 11:49:44.557750 Vdram = 0
7122 11:49:44.558062 Vddq = 0
7123 11:49:44.560325 Vmddr = 0
7124 11:49:44.563658 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7125 11:49:44.570474 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7126 11:49:44.573508 MEM_TYPE=3, freq_sel=13
7127 11:49:44.574004 sv_algorithm_assistance_LP4_3733
7128 11:49:44.580393 ============ PULL DRAM RESETB DOWN ============
7129 11:49:44.583527 ========== PULL DRAM RESETB DOWN end =========
7130 11:49:44.586757 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7131 11:49:44.590143 ===================================
7132 11:49:44.593566 LPDDR4 DRAM CONFIGURATION
7133 11:49:44.597170 ===================================
7134 11:49:44.600299 EX_ROW_EN[0] = 0x0
7135 11:49:44.600721 EX_ROW_EN[1] = 0x0
7136 11:49:44.603994 LP4Y_EN = 0x0
7137 11:49:44.604418 WORK_FSP = 0x1
7138 11:49:44.606585 WL = 0x5
7139 11:49:44.607080 RL = 0x5
7140 11:49:44.609798 BL = 0x2
7141 11:49:44.610240 RPST = 0x0
7142 11:49:44.613423 RD_PRE = 0x0
7143 11:49:44.613843 WR_PRE = 0x1
7144 11:49:44.616776 WR_PST = 0x1
7145 11:49:44.617197 DBI_WR = 0x0
7146 11:49:44.620097 DBI_RD = 0x0
7147 11:49:44.620612 OTF = 0x1
7148 11:49:44.623263 ===================================
7149 11:49:44.627075 ===================================
7150 11:49:44.629926 ANA top config
7151 11:49:44.633592 ===================================
7152 11:49:44.636467 DLL_ASYNC_EN = 0
7153 11:49:44.636978 ALL_SLAVE_EN = 0
7154 11:49:44.639972 NEW_RANK_MODE = 1
7155 11:49:44.643173 DLL_IDLE_MODE = 1
7156 11:49:44.646587 LP45_APHY_COMB_EN = 1
7157 11:49:44.649731 TX_ODT_DIS = 0
7158 11:49:44.650156 NEW_8X_MODE = 1
7159 11:49:44.653291 ===================================
7160 11:49:44.656737 ===================================
7161 11:49:44.659792 data_rate = 3200
7162 11:49:44.663332 CKR = 1
7163 11:49:44.666315 DQ_P2S_RATIO = 8
7164 11:49:44.669778 ===================================
7165 11:49:44.673194 CA_P2S_RATIO = 8
7166 11:49:44.676307 DQ_CA_OPEN = 0
7167 11:49:44.676738 DQ_SEMI_OPEN = 0
7168 11:49:44.679690 CA_SEMI_OPEN = 0
7169 11:49:44.682778 CA_FULL_RATE = 0
7170 11:49:44.686621 DQ_CKDIV4_EN = 0
7171 11:49:44.689579 CA_CKDIV4_EN = 0
7172 11:49:44.690048 CA_PREDIV_EN = 0
7173 11:49:44.692949 PH8_DLY = 12
7174 11:49:44.696487 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7175 11:49:44.699793 DQ_AAMCK_DIV = 4
7176 11:49:44.702867 CA_AAMCK_DIV = 4
7177 11:49:44.706371 CA_ADMCK_DIV = 4
7178 11:49:44.709388 DQ_TRACK_CA_EN = 0
7179 11:49:44.709823 CA_PICK = 1600
7180 11:49:44.713088 CA_MCKIO = 1600
7181 11:49:44.716029 MCKIO_SEMI = 0
7182 11:49:44.719414 PLL_FREQ = 3068
7183 11:49:44.722978 DQ_UI_PI_RATIO = 32
7184 11:49:44.726300 CA_UI_PI_RATIO = 0
7185 11:49:44.729715 ===================================
7186 11:49:44.733024 ===================================
7187 11:49:44.733545 memory_type:LPDDR4
7188 11:49:44.736644 GP_NUM : 10
7189 11:49:44.739698 SRAM_EN : 1
7190 11:49:44.740128 MD32_EN : 0
7191 11:49:44.742775 ===================================
7192 11:49:44.746123 [ANA_INIT] >>>>>>>>>>>>>>
7193 11:49:44.749435 <<<<<< [CONFIGURE PHASE]: ANA_TX
7194 11:49:44.752809 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7195 11:49:44.756260 ===================================
7196 11:49:44.759148 data_rate = 3200,PCW = 0X7600
7197 11:49:44.762816 ===================================
7198 11:49:44.766044 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7199 11:49:44.769493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7200 11:49:44.776016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7201 11:49:44.779166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7202 11:49:44.782604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7203 11:49:44.789047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7204 11:49:44.789523 [ANA_INIT] flow start
7205 11:49:44.792681 [ANA_INIT] PLL >>>>>>>>
7206 11:49:44.793257 [ANA_INIT] PLL <<<<<<<<
7207 11:49:44.796027 [ANA_INIT] MIDPI >>>>>>>>
7208 11:49:44.799118 [ANA_INIT] MIDPI <<<<<<<<
7209 11:49:44.802649 [ANA_INIT] DLL >>>>>>>>
7210 11:49:44.803124 [ANA_INIT] DLL <<<<<<<<
7211 11:49:44.805952 [ANA_INIT] flow end
7212 11:49:44.809254 ============ LP4 DIFF to SE enter ============
7213 11:49:44.813008 ============ LP4 DIFF to SE exit ============
7214 11:49:44.816014 [ANA_INIT] <<<<<<<<<<<<<
7215 11:49:44.819272 [Flow] Enable top DCM control >>>>>
7216 11:49:44.822514 [Flow] Enable top DCM control <<<<<
7217 11:49:44.825885 Enable DLL master slave shuffle
7218 11:49:44.832508 ==============================================================
7219 11:49:44.833078 Gating Mode config
7220 11:49:44.839193 ==============================================================
7221 11:49:44.839723 Config description:
7222 11:49:44.849010 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7223 11:49:44.855690 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7224 11:49:44.862443 SELPH_MODE 0: By rank 1: By Phase
7225 11:49:44.865863 ==============================================================
7226 11:49:44.868891 GAT_TRACK_EN = 1
7227 11:49:44.872643 RX_GATING_MODE = 2
7228 11:49:44.875544 RX_GATING_TRACK_MODE = 2
7229 11:49:44.878975 SELPH_MODE = 1
7230 11:49:44.882335 PICG_EARLY_EN = 1
7231 11:49:44.886083 VALID_LAT_VALUE = 1
7232 11:49:44.892162 ==============================================================
7233 11:49:44.895659 Enter into Gating configuration >>>>
7234 11:49:44.898607 Exit from Gating configuration <<<<
7235 11:49:44.899177 Enter into DVFS_PRE_config >>>>>
7236 11:49:44.912175 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7237 11:49:44.915433 Exit from DVFS_PRE_config <<<<<
7238 11:49:44.918870 Enter into PICG configuration >>>>
7239 11:49:44.922105 Exit from PICG configuration <<<<
7240 11:49:44.922617 [RX_INPUT] configuration >>>>>
7241 11:49:44.925396 [RX_INPUT] configuration <<<<<
7242 11:49:44.931831 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7243 11:49:44.935368 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7244 11:49:44.942323 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7245 11:49:44.948488 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7246 11:49:44.955278 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7247 11:49:44.961797 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7248 11:49:44.965260 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7249 11:49:44.968364 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7250 11:49:44.974815 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7251 11:49:44.978380 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7252 11:49:44.981726 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7253 11:49:44.985275 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7254 11:49:44.988072 ===================================
7255 11:49:44.991692 LPDDR4 DRAM CONFIGURATION
7256 11:49:44.995030 ===================================
7257 11:49:44.998282 EX_ROW_EN[0] = 0x0
7258 11:49:44.998788 EX_ROW_EN[1] = 0x0
7259 11:49:45.001377 LP4Y_EN = 0x0
7260 11:49:45.001868 WORK_FSP = 0x1
7261 11:49:45.004963 WL = 0x5
7262 11:49:45.005595 RL = 0x5
7263 11:49:45.008103 BL = 0x2
7264 11:49:45.008565 RPST = 0x0
7265 11:49:45.012166 RD_PRE = 0x0
7266 11:49:45.012644 WR_PRE = 0x1
7267 11:49:45.014770 WR_PST = 0x1
7268 11:49:45.018148 DBI_WR = 0x0
7269 11:49:45.018654 DBI_RD = 0x0
7270 11:49:45.021396 OTF = 0x1
7271 11:49:45.024934 ===================================
7272 11:49:45.028092 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7273 11:49:45.032038 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7274 11:49:45.035051 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7275 11:49:45.038176 ===================================
7276 11:49:45.041650 LPDDR4 DRAM CONFIGURATION
7277 11:49:45.045346 ===================================
7278 11:49:45.047932 EX_ROW_EN[0] = 0x10
7279 11:49:45.048402 EX_ROW_EN[1] = 0x0
7280 11:49:45.051497 LP4Y_EN = 0x0
7281 11:49:45.052061 WORK_FSP = 0x1
7282 11:49:45.054895 WL = 0x5
7283 11:49:45.055462 RL = 0x5
7284 11:49:45.058561 BL = 0x2
7285 11:49:45.059119 RPST = 0x0
7286 11:49:45.061696 RD_PRE = 0x0
7287 11:49:45.062261 WR_PRE = 0x1
7288 11:49:45.064923 WR_PST = 0x1
7289 11:49:45.065491 DBI_WR = 0x0
7290 11:49:45.068200 DBI_RD = 0x0
7291 11:49:45.068768 OTF = 0x1
7292 11:49:45.071511 ===================================
7293 11:49:45.077964 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7294 11:49:45.078571 ==
7295 11:49:45.081902 Dram Type= 6, Freq= 0, CH_0, rank 0
7296 11:49:45.087721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7297 11:49:45.088253 ==
7298 11:49:45.088626 [Duty_Offset_Calibration]
7299 11:49:45.091147 B0:2 B1:0 CA:1
7300 11:49:45.091612
7301 11:49:45.094213 [DutyScan_Calibration_Flow] k_type=0
7302 11:49:45.103053
7303 11:49:45.103631 ==CLK 0==
7304 11:49:45.106835 Final CLK duty delay cell = -4
7305 11:49:45.109815 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7306 11:49:45.113471 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7307 11:49:45.116501 [-4] AVG Duty = 4937%(X100)
7308 11:49:45.117060
7309 11:49:45.120160 CH0 CLK Duty spec in!! Max-Min= 187%
7310 11:49:45.123114 [DutyScan_Calibration_Flow] ====Done====
7311 11:49:45.123653
7312 11:49:45.126484 [DutyScan_Calibration_Flow] k_type=1
7313 11:49:45.142725
7314 11:49:45.143258 ==DQS 0 ==
7315 11:49:45.146063 Final DQS duty delay cell = 0
7316 11:49:45.149278 [0] MAX Duty = 5249%(X100), DQS PI = 32
7317 11:49:45.152669 [0] MIN Duty = 4938%(X100), DQS PI = 62
7318 11:49:45.156219 [0] AVG Duty = 5093%(X100)
7319 11:49:45.156793
7320 11:49:45.157260 ==DQS 1 ==
7321 11:49:45.159061 Final DQS duty delay cell = -4
7322 11:49:45.162610 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7323 11:49:45.166417 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7324 11:49:45.169613 [-4] AVG Duty = 5000%(X100)
7325 11:49:45.170175
7326 11:49:45.173082 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7327 11:49:45.173645
7328 11:49:45.175860 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7329 11:49:45.179149 [DutyScan_Calibration_Flow] ====Done====
7330 11:49:45.179709
7331 11:49:45.182498 [DutyScan_Calibration_Flow] k_type=3
7332 11:49:45.200014
7333 11:49:45.200581 ==DQM 0 ==
7334 11:49:45.203629 Final DQM duty delay cell = 0
7335 11:49:45.206668 [0] MAX Duty = 5124%(X100), DQS PI = 26
7336 11:49:45.209881 [0] MIN Duty = 4813%(X100), DQS PI = 50
7337 11:49:45.213537 [0] AVG Duty = 4968%(X100)
7338 11:49:45.214100
7339 11:49:45.214511 ==DQM 1 ==
7340 11:49:45.216574 Final DQM duty delay cell = 0
7341 11:49:45.220245 [0] MAX Duty = 5249%(X100), DQS PI = 28
7342 11:49:45.223314 [0] MIN Duty = 5000%(X100), DQS PI = 20
7343 11:49:45.226654 [0] AVG Duty = 5124%(X100)
7344 11:49:45.227113
7345 11:49:45.229764 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7346 11:49:45.230227
7347 11:49:45.233308 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7348 11:49:45.236714 [DutyScan_Calibration_Flow] ====Done====
7349 11:49:45.237285
7350 11:49:45.239972 [DutyScan_Calibration_Flow] k_type=2
7351 11:49:45.257899
7352 11:49:45.258520 ==DQ 0 ==
7353 11:49:45.260948 Final DQ duty delay cell = 0
7354 11:49:45.264154 [0] MAX Duty = 5156%(X100), DQS PI = 34
7355 11:49:45.267076 [0] MIN Duty = 5000%(X100), DQS PI = 16
7356 11:49:45.267546 [0] AVG Duty = 5078%(X100)
7357 11:49:45.270780
7358 11:49:45.271342 ==DQ 1 ==
7359 11:49:45.274049 Final DQ duty delay cell = 0
7360 11:49:45.277036 [0] MAX Duty = 4969%(X100), DQS PI = 52
7361 11:49:45.280675 [0] MIN Duty = 4875%(X100), DQS PI = 10
7362 11:49:45.281127 [0] AVG Duty = 4922%(X100)
7363 11:49:45.281480
7364 11:49:45.287544 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7365 11:49:45.287995
7366 11:49:45.290699 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7367 11:49:45.294061 [DutyScan_Calibration_Flow] ====Done====
7368 11:49:45.294535 ==
7369 11:49:45.297217 Dram Type= 6, Freq= 0, CH_1, rank 0
7370 11:49:45.300479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7371 11:49:45.300935 ==
7372 11:49:45.303926 [Duty_Offset_Calibration]
7373 11:49:45.304365 B0:0 B1:-1 CA:2
7374 11:49:45.304722
7375 11:49:45.307828 [DutyScan_Calibration_Flow] k_type=0
7376 11:49:45.317867
7377 11:49:45.318454 ==CLK 0==
7378 11:49:45.320681 Final CLK duty delay cell = 0
7379 11:49:45.323907 [0] MAX Duty = 5156%(X100), DQS PI = 10
7380 11:49:45.327129 [0] MIN Duty = 4906%(X100), DQS PI = 46
7381 11:49:45.330875 [0] AVG Duty = 5031%(X100)
7382 11:49:45.331328
7383 11:49:45.333716 CH1 CLK Duty spec in!! Max-Min= 250%
7384 11:49:45.337534 [DutyScan_Calibration_Flow] ====Done====
7385 11:49:45.338052
7386 11:49:45.340647 [DutyScan_Calibration_Flow] k_type=1
7387 11:49:45.357103
7388 11:49:45.357652 ==DQS 0 ==
7389 11:49:45.360485 Final DQS duty delay cell = 0
7390 11:49:45.363792 [0] MAX Duty = 5093%(X100), DQS PI = 24
7391 11:49:45.367264 [0] MIN Duty = 4969%(X100), DQS PI = 0
7392 11:49:45.370733 [0] AVG Duty = 5031%(X100)
7393 11:49:45.371139
7394 11:49:45.371458 ==DQS 1 ==
7395 11:49:45.374006 Final DQS duty delay cell = 0
7396 11:49:45.378012 [0] MAX Duty = 5187%(X100), DQS PI = 0
7397 11:49:45.381134 [0] MIN Duty = 4844%(X100), DQS PI = 34
7398 11:49:45.381646 [0] AVG Duty = 5015%(X100)
7399 11:49:45.384146
7400 11:49:45.387083 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7401 11:49:45.387492
7402 11:49:45.390659 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7403 11:49:45.394428 [DutyScan_Calibration_Flow] ====Done====
7404 11:49:45.394946
7405 11:49:45.397379 [DutyScan_Calibration_Flow] k_type=3
7406 11:49:45.415425
7407 11:49:45.415976 ==DQM 0 ==
7408 11:49:45.418528 Final DQM duty delay cell = 4
7409 11:49:45.422081 [4] MAX Duty = 5156%(X100), DQS PI = 24
7410 11:49:45.425341 [4] MIN Duty = 4969%(X100), DQS PI = 46
7411 11:49:45.428346 [4] AVG Duty = 5062%(X100)
7412 11:49:45.428803
7413 11:49:45.429158 ==DQM 1 ==
7414 11:49:45.431554 Final DQM duty delay cell = 0
7415 11:49:45.434759 [0] MAX Duty = 5249%(X100), DQS PI = 58
7416 11:49:45.438548 [0] MIN Duty = 4876%(X100), DQS PI = 34
7417 11:49:45.441672 [0] AVG Duty = 5062%(X100)
7418 11:49:45.442225
7419 11:49:45.445079 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7420 11:49:45.445637
7421 11:49:45.448196 CH1 DQM 1 Duty spec in!! Max-Min= 373%
7422 11:49:45.451357 [DutyScan_Calibration_Flow] ====Done====
7423 11:49:45.451811
7424 11:49:45.454838 [DutyScan_Calibration_Flow] k_type=2
7425 11:49:45.472277
7426 11:49:45.472829 ==DQ 0 ==
7427 11:49:45.475817 Final DQ duty delay cell = 0
7428 11:49:45.478354 [0] MAX Duty = 5093%(X100), DQS PI = 22
7429 11:49:45.481999 [0] MIN Duty = 4969%(X100), DQS PI = 48
7430 11:49:45.482601 [0] AVG Duty = 5031%(X100)
7431 11:49:45.485405
7432 11:49:45.485955 ==DQ 1 ==
7433 11:49:45.488813 Final DQ duty delay cell = 0
7434 11:49:45.492003 [0] MAX Duty = 5062%(X100), DQS PI = 2
7435 11:49:45.495287 [0] MIN Duty = 4844%(X100), DQS PI = 32
7436 11:49:45.495845 [0] AVG Duty = 4953%(X100)
7437 11:49:45.496207
7438 11:49:45.498834 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7439 11:49:45.502042
7440 11:49:45.505232 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7441 11:49:45.508328 [DutyScan_Calibration_Flow] ====Done====
7442 11:49:45.511662 nWR fixed to 30
7443 11:49:45.512271 [ModeRegInit_LP4] CH0 RK0
7444 11:49:45.515714 [ModeRegInit_LP4] CH0 RK1
7445 11:49:45.518421 [ModeRegInit_LP4] CH1 RK0
7446 11:49:45.521959 [ModeRegInit_LP4] CH1 RK1
7447 11:49:45.522579 match AC timing 5
7448 11:49:45.525314 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7449 11:49:45.532010 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7450 11:49:45.534711 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7451 11:49:45.541964 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7452 11:49:45.544707 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7453 11:49:45.545173 [MiockJmeterHQA]
7454 11:49:45.545539
7455 11:49:45.548082 [DramcMiockJmeter] u1RxGatingPI = 0
7456 11:49:45.551561 0 : 4255, 4027
7457 11:49:45.552231 4 : 4363, 4138
7458 11:49:45.554577 8 : 4253, 4027
7459 11:49:45.555049 12 : 4363, 4137
7460 11:49:45.555423 16 : 4253, 4026
7461 11:49:45.558015 20 : 4252, 4027
7462 11:49:45.558522 24 : 4252, 4027
7463 11:49:45.561607 28 : 4363, 4137
7464 11:49:45.562074 32 : 4363, 4138
7465 11:49:45.564717 36 : 4253, 4027
7466 11:49:45.565292 40 : 4252, 4027
7467 11:49:45.565673 44 : 4252, 4027
7468 11:49:45.568049 48 : 4253, 4026
7469 11:49:45.568517 52 : 4255, 4030
7470 11:49:45.571740 56 : 4363, 4137
7471 11:49:45.572315 60 : 4253, 4027
7472 11:49:45.574857 64 : 4252, 4026
7473 11:49:45.575326 68 : 4253, 4026
7474 11:49:45.578543 72 : 4252, 4030
7475 11:49:45.579114 76 : 4249, 4027
7476 11:49:45.579490 80 : 4363, 4137
7477 11:49:45.581450 84 : 4361, 4138
7478 11:49:45.582037 88 : 4250, 3756
7479 11:49:45.585025 92 : 4252, 1
7480 11:49:45.585495 96 : 4250, 0
7481 11:49:45.585870 100 : 4252, 0
7482 11:49:45.588387 104 : 4249, 0
7483 11:49:45.588974 108 : 4250, 0
7484 11:49:45.591792 112 : 4252, 0
7485 11:49:45.592365 116 : 4250, 0
7486 11:49:45.592742 120 : 4252, 0
7487 11:49:45.595002 124 : 4252, 0
7488 11:49:45.595571 128 : 4250, 0
7489 11:49:45.598032 132 : 4252, 0
7490 11:49:45.598640 136 : 4250, 0
7491 11:49:45.599024 140 : 4361, 0
7492 11:49:45.601163 144 : 4249, 0
7493 11:49:45.601633 148 : 4253, 0
7494 11:49:45.604355 152 : 4252, 0
7495 11:49:45.604911 156 : 4250, 0
7496 11:49:45.605289 160 : 4252, 0
7497 11:49:45.608211 164 : 4252, 0
7498 11:49:45.608782 168 : 4250, 0
7499 11:49:45.609158 172 : 4252, 0
7500 11:49:45.611009 176 : 4252, 0
7501 11:49:45.611480 180 : 4250, 0
7502 11:49:45.614883 184 : 4252, 0
7503 11:49:45.615450 188 : 4360, 0
7504 11:49:45.615826 192 : 4361, 0
7505 11:49:45.617640 196 : 4363, 0
7506 11:49:45.618106 200 : 4250, 0
7507 11:49:45.621342 204 : 4250, 2000
7508 11:49:45.621916 208 : 4250, 4027
7509 11:49:45.624427 212 : 4250, 4027
7510 11:49:45.624897 216 : 4250, 4027
7511 11:49:45.628209 220 : 4250, 4026
7512 11:49:45.628778 224 : 4361, 4137
7513 11:49:45.629153 228 : 4250, 4026
7514 11:49:45.631088 232 : 4250, 4027
7515 11:49:45.631545 236 : 4360, 4137
7516 11:49:45.634495 240 : 4250, 4026
7517 11:49:45.635069 244 : 4250, 4027
7518 11:49:45.638034 248 : 4363, 4140
7519 11:49:45.638636 252 : 4249, 4027
7520 11:49:45.641309 256 : 4250, 4027
7521 11:49:45.641888 260 : 4250, 4027
7522 11:49:45.644455 264 : 4252, 4029
7523 11:49:45.644926 268 : 4250, 4027
7524 11:49:45.647522 272 : 4250, 4026
7525 11:49:45.648088 276 : 4361, 4137
7526 11:49:45.650846 280 : 4250, 4027
7527 11:49:45.651317 284 : 4250, 4027
7528 11:49:45.651692 288 : 4360, 4138
7529 11:49:45.654258 292 : 4250, 4026
7530 11:49:45.654778 296 : 4250, 4027
7531 11:49:45.657442 300 : 4363, 4140
7532 11:49:45.657910 304 : 4250, 4027
7533 11:49:45.660921 308 : 4250, 4026
7534 11:49:45.661388 312 : 4250, 4002
7535 11:49:45.664179 316 : 4252, 2523
7536 11:49:45.664602 320 : 4250, 85
7537 11:49:45.664942
7538 11:49:45.667823 MIOCK jitter meter ch=0
7539 11:49:45.668241
7540 11:49:45.670775 1T = (320-92) = 228 dly cells
7541 11:49:45.674280 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7542 11:49:45.677519 ==
7543 11:49:45.677943 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 11:49:45.684596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 11:49:45.685125 ==
7546 11:49:45.687867 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7547 11:49:45.693932 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7548 11:49:45.698174 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7549 11:49:45.703748 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7550 11:49:45.712589 [CA 0] Center 42 (12~72) winsize 61
7551 11:49:45.715707 [CA 1] Center 42 (12~72) winsize 61
7552 11:49:45.718782 [CA 2] Center 37 (7~67) winsize 61
7553 11:49:45.722442 [CA 3] Center 37 (7~67) winsize 61
7554 11:49:45.725217 [CA 4] Center 35 (5~66) winsize 62
7555 11:49:45.728809 [CA 5] Center 35 (5~65) winsize 61
7556 11:49:45.729376
7557 11:49:45.732283 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7558 11:49:45.732807
7559 11:49:45.735560 [CATrainingPosCal] consider 1 rank data
7560 11:49:45.738993 u2DelayCellTimex100 = 285/100 ps
7561 11:49:45.742467 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7562 11:49:45.748697 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7563 11:49:45.751852 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7564 11:49:45.755313 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7565 11:49:45.758521 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7566 11:49:45.761827 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7567 11:49:45.762352
7568 11:49:45.764880 CA PerBit enable=1, Macro0, CA PI delay=35
7569 11:49:45.765301
7570 11:49:45.768509 [CBTSetCACLKResult] CA Dly = 35
7571 11:49:45.771488 CS Dly: 10 (0~41)
7572 11:49:45.775048 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7573 11:49:45.778718 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7574 11:49:45.779245 ==
7575 11:49:45.781427 Dram Type= 6, Freq= 0, CH_0, rank 1
7576 11:49:45.785360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 11:49:45.788018 ==
7578 11:49:45.791294 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7579 11:49:45.794884 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7580 11:49:45.801647 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7581 11:49:45.804720 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7582 11:49:45.815539 [CA 0] Center 43 (13~74) winsize 62
7583 11:49:45.818997 [CA 1] Center 43 (13~73) winsize 61
7584 11:49:45.822127 [CA 2] Center 38 (9~68) winsize 60
7585 11:49:45.825516 [CA 3] Center 38 (9~68) winsize 60
7586 11:49:45.828538 [CA 4] Center 37 (7~67) winsize 61
7587 11:49:45.831901 [CA 5] Center 36 (6~66) winsize 61
7588 11:49:45.832464
7589 11:49:45.835216 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7590 11:49:45.835786
7591 11:49:45.838869 [CATrainingPosCal] consider 2 rank data
7592 11:49:45.841788 u2DelayCellTimex100 = 285/100 ps
7593 11:49:45.848551 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7594 11:49:45.851842 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7595 11:49:45.854981 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7596 11:49:45.858629 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7597 11:49:45.861704 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7598 11:49:45.865089 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7599 11:49:45.865654
7600 11:49:45.868552 CA PerBit enable=1, Macro0, CA PI delay=35
7601 11:49:45.869117
7602 11:49:45.871813 [CBTSetCACLKResult] CA Dly = 35
7603 11:49:45.875644 CS Dly: 11 (0~43)
7604 11:49:45.878439 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7605 11:49:45.881848 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7606 11:49:45.882440
7607 11:49:45.884981 ----->DramcWriteLeveling(PI) begin...
7608 11:49:45.885550 ==
7609 11:49:45.888848 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 11:49:45.894993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 11:49:45.895563 ==
7612 11:49:45.898445 Write leveling (Byte 0): 37 => 37
7613 11:49:45.901970 Write leveling (Byte 1): 30 => 30
7614 11:49:45.902469 DramcWriteLeveling(PI) end<-----
7615 11:49:45.902849
7616 11:49:45.904787 ==
7617 11:49:45.908328 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 11:49:45.911745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 11:49:45.912325 ==
7620 11:49:45.914946 [Gating] SW mode calibration
7621 11:49:45.921679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7622 11:49:45.924799 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7623 11:49:45.931159 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 11:49:45.934744 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 11:49:45.938169 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7626 11:49:45.944369 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7627 11:49:45.948092 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7628 11:49:45.951240 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7629 11:49:45.958191 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7630 11:49:45.961311 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7631 11:49:45.964906 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7632 11:49:45.971225 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7633 11:49:45.974500 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7634 11:49:45.977622 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7635 11:49:45.984480 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7636 11:49:45.987780 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7637 11:49:45.991172 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 11:49:45.997800 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 11:49:46.001002 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 11:49:46.004093 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7641 11:49:46.011031 1 6 8 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7642 11:49:46.014106 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7643 11:49:46.017530 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7644 11:49:46.024888 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7645 11:49:46.027837 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 11:49:46.031285 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 11:49:46.034709 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 11:49:46.041121 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 11:49:46.044250 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7650 11:49:46.047556 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7651 11:49:46.054042 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7652 11:49:46.057550 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7653 11:49:46.060854 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 11:49:46.067303 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 11:49:46.070606 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 11:49:46.074282 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 11:49:46.080733 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 11:49:46.084465 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 11:49:46.087086 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 11:49:46.094002 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:49:46.096996 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:49:46.100552 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 11:49:46.107274 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 11:49:46.110455 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 11:49:46.113834 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7666 11:49:46.120488 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7667 11:49:46.120913 Total UI for P1: 0, mck2ui 16
7668 11:49:46.127287 best dqsien dly found for B0: ( 1, 9, 8)
7669 11:49:46.130741 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7670 11:49:46.134190 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7671 11:49:46.140712 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 11:49:46.141292 Total UI for P1: 0, mck2ui 16
7673 11:49:46.144130 best dqsien dly found for B1: ( 1, 9, 18)
7674 11:49:46.147282 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7675 11:49:46.153716 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7676 11:49:46.154258
7677 11:49:46.157316 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7678 11:49:46.160427 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7679 11:49:46.163769 [Gating] SW calibration Done
7680 11:49:46.164192 ==
7681 11:49:46.166905 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 11:49:46.169987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 11:49:46.170448 ==
7684 11:49:46.173803 RX Vref Scan: 0
7685 11:49:46.174328
7686 11:49:46.174718 RX Vref 0 -> 0, step: 1
7687 11:49:46.175035
7688 11:49:46.177128 RX Delay 0 -> 252, step: 8
7689 11:49:46.180316 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7690 11:49:46.184370 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7691 11:49:46.190238 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7692 11:49:46.193566 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7693 11:49:46.197193 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7694 11:49:46.200405 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7695 11:49:46.203360 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7696 11:49:46.210117 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7697 11:49:46.213352 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7698 11:49:46.217463 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7699 11:49:46.220210 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7700 11:49:46.224162 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7701 11:49:46.230059 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7702 11:49:46.233608 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7703 11:49:46.237093 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7704 11:49:46.240446 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7705 11:49:46.240966 ==
7706 11:49:46.243420 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 11:49:46.246763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 11:49:46.250027 ==
7709 11:49:46.250598 DQS Delay:
7710 11:49:46.250949 DQS0 = 0, DQS1 = 0
7711 11:49:46.253558 DQM Delay:
7712 11:49:46.254122 DQM0 = 138, DQM1 = 126
7713 11:49:46.256873 DQ Delay:
7714 11:49:46.260427 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7715 11:49:46.263610 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7716 11:49:46.266494 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7717 11:49:46.270609 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7718 11:49:46.271171
7719 11:49:46.271546
7720 11:49:46.271892 ==
7721 11:49:46.273450 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 11:49:46.277308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 11:49:46.277875 ==
7724 11:49:46.280527
7725 11:49:46.281092
7726 11:49:46.281469 TX Vref Scan disable
7727 11:49:46.283290 == TX Byte 0 ==
7728 11:49:46.286510 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7729 11:49:46.290458 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7730 11:49:46.293642 == TX Byte 1 ==
7731 11:49:46.296872 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7732 11:49:46.300029 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7733 11:49:46.300504 ==
7734 11:49:46.303446 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 11:49:46.310010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 11:49:46.310620 ==
7737 11:49:46.323461
7738 11:49:46.326595 TX Vref early break, caculate TX vref
7739 11:49:46.330210 TX Vref=16, minBit 11, minWin=22, winSum=373
7740 11:49:46.333528 TX Vref=18, minBit 8, minWin=23, winSum=387
7741 11:49:46.336962 TX Vref=20, minBit 11, minWin=23, winSum=395
7742 11:49:46.340012 TX Vref=22, minBit 7, minWin=24, winSum=407
7743 11:49:46.343536 TX Vref=24, minBit 7, minWin=24, winSum=416
7744 11:49:46.349891 TX Vref=26, minBit 2, minWin=25, winSum=421
7745 11:49:46.353384 TX Vref=28, minBit 4, minWin=25, winSum=426
7746 11:49:46.356469 TX Vref=30, minBit 0, minWin=25, winSum=426
7747 11:49:46.360455 TX Vref=32, minBit 0, minWin=25, winSum=415
7748 11:49:46.363061 TX Vref=34, minBit 2, minWin=24, winSum=405
7749 11:49:46.366887 TX Vref=36, minBit 0, minWin=24, winSum=394
7750 11:49:46.373626 [TxChooseVref] Worse bit 4, Min win 25, Win sum 426, Final Vref 28
7751 11:49:46.374198
7752 11:49:46.376995 Final TX Range 0 Vref 28
7753 11:49:46.377563
7754 11:49:46.377936 ==
7755 11:49:46.379905 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 11:49:46.383170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 11:49:46.383649 ==
7758 11:49:46.384024
7759 11:49:46.384369
7760 11:49:46.386724 TX Vref Scan disable
7761 11:49:46.393320 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7762 11:49:46.393868 == TX Byte 0 ==
7763 11:49:46.396641 u2DelayCellOfst[0]=13 cells (4 PI)
7764 11:49:46.400178 u2DelayCellOfst[1]=17 cells (5 PI)
7765 11:49:46.403213 u2DelayCellOfst[2]=10 cells (3 PI)
7766 11:49:46.406312 u2DelayCellOfst[3]=10 cells (3 PI)
7767 11:49:46.410182 u2DelayCellOfst[4]=6 cells (2 PI)
7768 11:49:46.413111 u2DelayCellOfst[5]=0 cells (0 PI)
7769 11:49:46.416582 u2DelayCellOfst[6]=17 cells (5 PI)
7770 11:49:46.419744 u2DelayCellOfst[7]=13 cells (4 PI)
7771 11:49:46.422850 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7772 11:49:46.426486 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7773 11:49:46.430011 == TX Byte 1 ==
7774 11:49:46.433183 u2DelayCellOfst[8]=0 cells (0 PI)
7775 11:49:46.436599 u2DelayCellOfst[9]=0 cells (0 PI)
7776 11:49:46.437126 u2DelayCellOfst[10]=3 cells (1 PI)
7777 11:49:46.439698 u2DelayCellOfst[11]=0 cells (0 PI)
7778 11:49:46.443302 u2DelayCellOfst[12]=6 cells (2 PI)
7779 11:49:46.446688 u2DelayCellOfst[13]=10 cells (3 PI)
7780 11:49:46.449845 u2DelayCellOfst[14]=10 cells (3 PI)
7781 11:49:46.453354 u2DelayCellOfst[15]=6 cells (2 PI)
7782 11:49:46.455906 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7783 11:49:46.462843 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7784 11:49:46.463272 DramC Write-DBI on
7785 11:49:46.463612 ==
7786 11:49:46.466253 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 11:49:46.473058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 11:49:46.473604 ==
7789 11:49:46.473947
7790 11:49:46.474260
7791 11:49:46.474637 TX Vref Scan disable
7792 11:49:46.476853 == TX Byte 0 ==
7793 11:49:46.479922 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7794 11:49:46.483634 == TX Byte 1 ==
7795 11:49:46.486705 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7796 11:49:46.490154 DramC Write-DBI off
7797 11:49:46.490754
7798 11:49:46.491101 [DATLAT]
7799 11:49:46.491418 Freq=1600, CH0 RK0
7800 11:49:46.491722
7801 11:49:46.493179 DATLAT Default: 0xf
7802 11:49:46.493612 0, 0xFFFF, sum = 0
7803 11:49:46.496981 1, 0xFFFF, sum = 0
7804 11:49:46.499836 2, 0xFFFF, sum = 0
7805 11:49:46.500273 3, 0xFFFF, sum = 0
7806 11:49:46.503607 4, 0xFFFF, sum = 0
7807 11:49:46.504139 5, 0xFFFF, sum = 0
7808 11:49:46.507147 6, 0xFFFF, sum = 0
7809 11:49:46.507674 7, 0xFFFF, sum = 0
7810 11:49:46.509920 8, 0xFFFF, sum = 0
7811 11:49:46.510591 9, 0xFFFF, sum = 0
7812 11:49:46.513087 10, 0xFFFF, sum = 0
7813 11:49:46.513519 11, 0xFFFF, sum = 0
7814 11:49:46.517007 12, 0xFFFF, sum = 0
7815 11:49:46.517533 13, 0xFFFF, sum = 0
7816 11:49:46.519838 14, 0x0, sum = 1
7817 11:49:46.520274 15, 0x0, sum = 2
7818 11:49:46.523254 16, 0x0, sum = 3
7819 11:49:46.523785 17, 0x0, sum = 4
7820 11:49:46.526365 best_step = 15
7821 11:49:46.526827
7822 11:49:46.527167 ==
7823 11:49:46.529816 Dram Type= 6, Freq= 0, CH_0, rank 0
7824 11:49:46.533260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7825 11:49:46.533783 ==
7826 11:49:46.534125 RX Vref Scan: 1
7827 11:49:46.536411
7828 11:49:46.536835 Set Vref Range= 24 -> 127
7829 11:49:46.537176
7830 11:49:46.540186 RX Vref 24 -> 127, step: 1
7831 11:49:46.540708
7832 11:49:46.543053 RX Delay 19 -> 252, step: 4
7833 11:49:46.543478
7834 11:49:46.546716 Set Vref, RX VrefLevel [Byte0]: 24
7835 11:49:46.550091 [Byte1]: 24
7836 11:49:46.550656
7837 11:49:46.553531 Set Vref, RX VrefLevel [Byte0]: 25
7838 11:49:46.556368 [Byte1]: 25
7839 11:49:46.557022
7840 11:49:46.559795 Set Vref, RX VrefLevel [Byte0]: 26
7841 11:49:46.563070 [Byte1]: 26
7842 11:49:46.566973
7843 11:49:46.567537 Set Vref, RX VrefLevel [Byte0]: 27
7844 11:49:46.570554 [Byte1]: 27
7845 11:49:46.574970
7846 11:49:46.575531 Set Vref, RX VrefLevel [Byte0]: 28
7847 11:49:46.578241 [Byte1]: 28
7848 11:49:46.582159
7849 11:49:46.582792 Set Vref, RX VrefLevel [Byte0]: 29
7850 11:49:46.585547 [Byte1]: 29
7851 11:49:46.589954
7852 11:49:46.590573 Set Vref, RX VrefLevel [Byte0]: 30
7853 11:49:46.593308 [Byte1]: 30
7854 11:49:46.597564
7855 11:49:46.598126 Set Vref, RX VrefLevel [Byte0]: 31
7856 11:49:46.600612 [Byte1]: 31
7857 11:49:46.605029
7858 11:49:46.605498 Set Vref, RX VrefLevel [Byte0]: 32
7859 11:49:46.608367 [Byte1]: 32
7860 11:49:46.612724
7861 11:49:46.613283 Set Vref, RX VrefLevel [Byte0]: 33
7862 11:49:46.615503 [Byte1]: 33
7863 11:49:46.620142
7864 11:49:46.620703 Set Vref, RX VrefLevel [Byte0]: 34
7865 11:49:46.623228 [Byte1]: 34
7866 11:49:46.627914
7867 11:49:46.628478 Set Vref, RX VrefLevel [Byte0]: 35
7868 11:49:46.630895 [Byte1]: 35
7869 11:49:46.635017
7870 11:49:46.635618 Set Vref, RX VrefLevel [Byte0]: 36
7871 11:49:46.638318 [Byte1]: 36
7872 11:49:46.642647
7873 11:49:46.643209 Set Vref, RX VrefLevel [Byte0]: 37
7874 11:49:46.645700 [Byte1]: 37
7875 11:49:46.650574
7876 11:49:46.651150 Set Vref, RX VrefLevel [Byte0]: 38
7877 11:49:46.653631 [Byte1]: 38
7878 11:49:46.658003
7879 11:49:46.658602 Set Vref, RX VrefLevel [Byte0]: 39
7880 11:49:46.660905 [Byte1]: 39
7881 11:49:46.665530
7882 11:49:46.666096 Set Vref, RX VrefLevel [Byte0]: 40
7883 11:49:46.668870 [Byte1]: 40
7884 11:49:46.673266
7885 11:49:46.673828 Set Vref, RX VrefLevel [Byte0]: 41
7886 11:49:46.676491 [Byte1]: 41
7887 11:49:46.680543
7888 11:49:46.681105 Set Vref, RX VrefLevel [Byte0]: 42
7889 11:49:46.683951 [Byte1]: 42
7890 11:49:46.688181
7891 11:49:46.688741 Set Vref, RX VrefLevel [Byte0]: 43
7892 11:49:46.691599 [Byte1]: 43
7893 11:49:46.695631
7894 11:49:46.696190 Set Vref, RX VrefLevel [Byte0]: 44
7895 11:49:46.699200 [Byte1]: 44
7896 11:49:46.703094
7897 11:49:46.703561 Set Vref, RX VrefLevel [Byte0]: 45
7898 11:49:46.707043 [Byte1]: 45
7899 11:49:46.711003
7900 11:49:46.711568 Set Vref, RX VrefLevel [Byte0]: 46
7901 11:49:46.714463 [Byte1]: 46
7902 11:49:46.718551
7903 11:49:46.719115 Set Vref, RX VrefLevel [Byte0]: 47
7904 11:49:46.722087 [Byte1]: 47
7905 11:49:46.726075
7906 11:49:46.726691 Set Vref, RX VrefLevel [Byte0]: 48
7907 11:49:46.729461 [Byte1]: 48
7908 11:49:46.733701
7909 11:49:46.734276 Set Vref, RX VrefLevel [Byte0]: 49
7910 11:49:46.736825 [Byte1]: 49
7911 11:49:46.741050
7912 11:49:46.741619 Set Vref, RX VrefLevel [Byte0]: 50
7913 11:49:46.744457 [Byte1]: 50
7914 11:49:46.749109
7915 11:49:46.749679 Set Vref, RX VrefLevel [Byte0]: 51
7916 11:49:46.751783 [Byte1]: 51
7917 11:49:46.756341
7918 11:49:46.756917 Set Vref, RX VrefLevel [Byte0]: 52
7919 11:49:46.759429 [Byte1]: 52
7920 11:49:46.763736
7921 11:49:46.764207 Set Vref, RX VrefLevel [Byte0]: 53
7922 11:49:46.767379 [Byte1]: 53
7923 11:49:46.771365
7924 11:49:46.771831 Set Vref, RX VrefLevel [Byte0]: 54
7925 11:49:46.774453 [Byte1]: 54
7926 11:49:46.779131
7927 11:49:46.779599 Set Vref, RX VrefLevel [Byte0]: 55
7928 11:49:46.782332 [Byte1]: 55
7929 11:49:46.786760
7930 11:49:46.787333 Set Vref, RX VrefLevel [Byte0]: 56
7931 11:49:46.789847 [Byte1]: 56
7932 11:49:46.794179
7933 11:49:46.794784 Set Vref, RX VrefLevel [Byte0]: 57
7934 11:49:46.797808 [Byte1]: 57
7935 11:49:46.801596
7936 11:49:46.802085 Set Vref, RX VrefLevel [Byte0]: 58
7937 11:49:46.805252 [Byte1]: 58
7938 11:49:46.809333
7939 11:49:46.809909 Set Vref, RX VrefLevel [Byte0]: 59
7940 11:49:46.813085 [Byte1]: 59
7941 11:49:46.816971
7942 11:49:46.817547 Set Vref, RX VrefLevel [Byte0]: 60
7943 11:49:46.819927 [Byte1]: 60
7944 11:49:46.824958
7945 11:49:46.825527 Set Vref, RX VrefLevel [Byte0]: 61
7946 11:49:46.827507 [Byte1]: 61
7947 11:49:46.832377
7948 11:49:46.832953 Set Vref, RX VrefLevel [Byte0]: 62
7949 11:49:46.835203 [Byte1]: 62
7950 11:49:46.839425
7951 11:49:46.839992 Set Vref, RX VrefLevel [Byte0]: 63
7952 11:49:46.843427 [Byte1]: 63
7953 11:49:46.847609
7954 11:49:46.848180 Set Vref, RX VrefLevel [Byte0]: 64
7955 11:49:46.850370 [Byte1]: 64
7956 11:49:46.854591
7957 11:49:46.855160 Set Vref, RX VrefLevel [Byte0]: 65
7958 11:49:46.858207 [Byte1]: 65
7959 11:49:46.862059
7960 11:49:46.862563 Set Vref, RX VrefLevel [Byte0]: 66
7961 11:49:46.865612 [Byte1]: 66
7962 11:49:46.869770
7963 11:49:46.870344 Set Vref, RX VrefLevel [Byte0]: 67
7964 11:49:46.873210 [Byte1]: 67
7965 11:49:46.877346
7966 11:49:46.877816 Set Vref, RX VrefLevel [Byte0]: 68
7967 11:49:46.881187 [Byte1]: 68
7968 11:49:46.885328
7969 11:49:46.885898 Set Vref, RX VrefLevel [Byte0]: 69
7970 11:49:46.888321 [Byte1]: 69
7971 11:49:46.892703
7972 11:49:46.893175 Set Vref, RX VrefLevel [Byte0]: 70
7973 11:49:46.895699 [Byte1]: 70
7974 11:49:46.899873
7975 11:49:46.900380 Set Vref, RX VrefLevel [Byte0]: 71
7976 11:49:46.903383 [Byte1]: 71
7977 11:49:46.907377
7978 11:49:46.907843 Set Vref, RX VrefLevel [Byte0]: 72
7979 11:49:46.910908 [Byte1]: 72
7980 11:49:46.915008
7981 11:49:46.915434 Set Vref, RX VrefLevel [Byte0]: 73
7982 11:49:46.918879 [Byte1]: 73
7983 11:49:46.922630
7984 11:49:46.923055 Set Vref, RX VrefLevel [Byte0]: 74
7985 11:49:46.926286 [Byte1]: 74
7986 11:49:46.930835
7987 11:49:46.931367 Set Vref, RX VrefLevel [Byte0]: 75
7988 11:49:46.933518 [Byte1]: 75
7989 11:49:46.938200
7990 11:49:46.938859 Set Vref, RX VrefLevel [Byte0]: 76
7991 11:49:46.941387 [Byte1]: 76
7992 11:49:46.945380
7993 11:49:46.945844 Set Vref, RX VrefLevel [Byte0]: 77
7994 11:49:46.948779 [Byte1]: 77
7995 11:49:46.952989
7996 11:49:46.953455 Set Vref, RX VrefLevel [Byte0]: 78
7997 11:49:46.956531 [Byte1]: 78
7998 11:49:46.960675
7999 11:49:46.961235 Set Vref, RX VrefLevel [Byte0]: 79
8000 11:49:46.964135 [Byte1]: 79
8001 11:49:46.968393
8002 11:49:46.968851 Set Vref, RX VrefLevel [Byte0]: 80
8003 11:49:46.971488 [Byte1]: 80
8004 11:49:46.975606
8005 11:49:46.976066 Final RX Vref Byte 0 = 63 to rank0
8006 11:49:46.979116 Final RX Vref Byte 1 = 63 to rank0
8007 11:49:46.982200 Final RX Vref Byte 0 = 63 to rank1
8008 11:49:46.985806 Final RX Vref Byte 1 = 63 to rank1==
8009 11:49:46.989140 Dram Type= 6, Freq= 0, CH_0, rank 0
8010 11:49:46.995988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 11:49:46.996515 ==
8012 11:49:46.996862 DQS Delay:
8013 11:49:46.999243 DQS0 = 0, DQS1 = 0
8014 11:49:46.999672 DQM Delay:
8015 11:49:47.000012 DQM0 = 136, DQM1 = 124
8016 11:49:47.002466 DQ Delay:
8017 11:49:47.005992 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
8018 11:49:47.008861 DQ4 =138, DQ5 =126, DQ6 =144, DQ7 =142
8019 11:49:47.012111 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
8020 11:49:47.015330 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
8021 11:49:47.015779
8022 11:49:47.016220
8023 11:49:47.016637
8024 11:49:47.019058 [DramC_TX_OE_Calibration] TA2
8025 11:49:47.022620 Original DQ_B0 (3 6) =30, OEN = 27
8026 11:49:47.026062 Original DQ_B1 (3 6) =30, OEN = 27
8027 11:49:47.028964 24, 0x0, End_B0=24 End_B1=24
8028 11:49:47.029556 25, 0x0, End_B0=25 End_B1=25
8029 11:49:47.032318 26, 0x0, End_B0=26 End_B1=26
8030 11:49:47.035852 27, 0x0, End_B0=27 End_B1=27
8031 11:49:47.038896 28, 0x0, End_B0=28 End_B1=28
8032 11:49:47.042447 29, 0x0, End_B0=29 End_B1=29
8033 11:49:47.043022 30, 0x0, End_B0=30 End_B1=30
8034 11:49:47.045263 31, 0x4141, End_B0=30 End_B1=30
8035 11:49:47.049029 Byte0 end_step=30 best_step=27
8036 11:49:47.051961 Byte1 end_step=30 best_step=27
8037 11:49:47.055530 Byte0 TX OE(2T, 0.5T) = (3, 3)
8038 11:49:47.058697 Byte1 TX OE(2T, 0.5T) = (3, 3)
8039 11:49:47.059388
8040 11:49:47.059906
8041 11:49:47.065412 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
8042 11:49:47.068796 CH0 RK0: MR19=303, MR18=1B19
8043 11:49:47.075070 CH0_RK0: MR19=0x303, MR18=0x1B19, DQSOSC=396, MR23=63, INC=23, DEC=15
8044 11:49:47.075536
8045 11:49:47.078337 ----->DramcWriteLeveling(PI) begin...
8046 11:49:47.078950 ==
8047 11:49:47.081965 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 11:49:47.085322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 11:49:47.085901 ==
8050 11:49:47.088545 Write leveling (Byte 0): 38 => 38
8051 11:49:47.091622 Write leveling (Byte 1): 30 => 30
8052 11:49:47.095685 DramcWriteLeveling(PI) end<-----
8053 11:49:47.096264
8054 11:49:47.096639 ==
8055 11:49:47.098202 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 11:49:47.101991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 11:49:47.102615 ==
8058 11:49:47.105188 [Gating] SW mode calibration
8059 11:49:47.111948 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8060 11:49:47.118647 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8061 11:49:47.122504 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 11:49:47.128575 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 11:49:47.132143 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 11:49:47.135177 1 4 12 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (1 1)
8065 11:49:47.138761 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 11:49:47.145057 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 11:49:47.148271 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 11:49:47.151429 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 11:49:47.158542 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 11:49:47.161543 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 11:49:47.164890 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 11:49:47.171290 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
8073 11:49:47.174861 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 11:49:47.178090 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 11:49:47.184841 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 11:49:47.188044 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 11:49:47.191712 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 11:49:47.198172 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 11:49:47.201454 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8080 11:49:47.204627 1 6 12 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
8081 11:49:47.211312 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8082 11:49:47.214583 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 11:49:47.218181 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 11:49:47.224599 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 11:49:47.228181 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 11:49:47.231397 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 11:49:47.237953 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 11:49:47.241412 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8089 11:49:47.244793 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8090 11:49:47.251082 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:49:47.254814 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:49:47.258107 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:49:47.265015 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:49:47.267764 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:49:47.271324 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:49:47.277839 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:49:47.281225 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 11:49:47.284586 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 11:49:47.287910 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 11:49:47.294509 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 11:49:47.298102 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 11:49:47.301057 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 11:49:47.307545 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 11:49:47.311387 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8105 11:49:47.314544 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8106 11:49:47.317862 Total UI for P1: 0, mck2ui 16
8107 11:49:47.321257 best dqsien dly found for B0: ( 1, 9, 12)
8108 11:49:47.327670 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 11:49:47.328204 Total UI for P1: 0, mck2ui 16
8110 11:49:47.334367 best dqsien dly found for B1: ( 1, 9, 14)
8111 11:49:47.338039 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8112 11:49:47.341437 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8113 11:49:47.341991
8114 11:49:47.344809 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8115 11:49:47.348223 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8116 11:49:47.351386 [Gating] SW calibration Done
8117 11:49:47.351944 ==
8118 11:49:47.354868 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 11:49:47.357967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 11:49:47.358545 ==
8121 11:49:47.360873 RX Vref Scan: 0
8122 11:49:47.361371
8123 11:49:47.361745 RX Vref 0 -> 0, step: 1
8124 11:49:47.362090
8125 11:49:47.363998 RX Delay 0 -> 252, step: 8
8126 11:49:47.368006 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8127 11:49:47.374353 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8128 11:49:47.377757 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8129 11:49:47.380839 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8130 11:49:47.384363 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8131 11:49:47.387195 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8132 11:49:47.394058 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8133 11:49:47.397473 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8134 11:49:47.400767 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8135 11:49:47.403861 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8136 11:49:47.407384 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8137 11:49:47.413756 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8138 11:49:47.417086 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8139 11:49:47.420504 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8140 11:49:47.423695 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8141 11:49:47.430250 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8142 11:49:47.430720 ==
8143 11:49:47.433930 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 11:49:47.436821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 11:49:47.437252 ==
8146 11:49:47.437610 DQS Delay:
8147 11:49:47.440785 DQS0 = 0, DQS1 = 0
8148 11:49:47.441316 DQM Delay:
8149 11:49:47.443501 DQM0 = 136, DQM1 = 126
8150 11:49:47.443929 DQ Delay:
8151 11:49:47.446817 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8152 11:49:47.450654 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8153 11:49:47.454046 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8154 11:49:47.457247 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8155 11:49:47.457792
8156 11:49:47.458131
8157 11:49:47.460101 ==
8158 11:49:47.460533 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 11:49:47.467298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 11:49:47.467839 ==
8161 11:49:47.468181
8162 11:49:47.468496
8163 11:49:47.470366 TX Vref Scan disable
8164 11:49:47.470878 == TX Byte 0 ==
8165 11:49:47.473886 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8166 11:49:47.480346 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8167 11:49:47.480898 == TX Byte 1 ==
8168 11:49:47.483649 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8169 11:49:47.490471 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8170 11:49:47.491032 ==
8171 11:49:47.493157 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 11:49:47.496898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 11:49:47.497473 ==
8174 11:49:47.511581
8175 11:49:47.515016 TX Vref early break, caculate TX vref
8176 11:49:47.518481 TX Vref=16, minBit 0, minWin=23, winSum=389
8177 11:49:47.521617 TX Vref=18, minBit 1, minWin=24, winSum=400
8178 11:49:47.525216 TX Vref=20, minBit 0, minWin=25, winSum=407
8179 11:49:47.528450 TX Vref=22, minBit 0, minWin=25, winSum=414
8180 11:49:47.531447 TX Vref=24, minBit 2, minWin=25, winSum=420
8181 11:49:47.538559 TX Vref=26, minBit 8, minWin=25, winSum=428
8182 11:49:47.541350 TX Vref=28, minBit 0, minWin=26, winSum=430
8183 11:49:47.544662 TX Vref=30, minBit 2, minWin=26, winSum=427
8184 11:49:47.548226 TX Vref=32, minBit 0, minWin=25, winSum=420
8185 11:49:47.551229 TX Vref=34, minBit 0, minWin=25, winSum=412
8186 11:49:47.554659 TX Vref=36, minBit 2, minWin=24, winSum=398
8187 11:49:47.561378 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8188 11:49:47.561512
8189 11:49:47.564659 Final TX Range 0 Vref 28
8190 11:49:47.564774
8191 11:49:47.564863 ==
8192 11:49:47.567999 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 11:49:47.571382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 11:49:47.571484 ==
8195 11:49:47.571564
8196 11:49:47.571638
8197 11:49:47.574564 TX Vref Scan disable
8198 11:49:47.581599 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8199 11:49:47.581683 == TX Byte 0 ==
8200 11:49:47.585360 u2DelayCellOfst[0]=13 cells (4 PI)
8201 11:49:47.588306 u2DelayCellOfst[1]=20 cells (6 PI)
8202 11:49:47.591676 u2DelayCellOfst[2]=13 cells (4 PI)
8203 11:49:47.595020 u2DelayCellOfst[3]=13 cells (4 PI)
8204 11:49:47.598142 u2DelayCellOfst[4]=10 cells (3 PI)
8205 11:49:47.601871 u2DelayCellOfst[5]=0 cells (0 PI)
8206 11:49:47.605144 u2DelayCellOfst[6]=20 cells (6 PI)
8207 11:49:47.608076 u2DelayCellOfst[7]=20 cells (6 PI)
8208 11:49:47.611483 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8209 11:49:47.614826 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8210 11:49:47.618000 == TX Byte 1 ==
8211 11:49:47.621376 u2DelayCellOfst[8]=0 cells (0 PI)
8212 11:49:47.621459 u2DelayCellOfst[9]=0 cells (0 PI)
8213 11:49:47.625263 u2DelayCellOfst[10]=10 cells (3 PI)
8214 11:49:47.628133 u2DelayCellOfst[11]=3 cells (1 PI)
8215 11:49:47.631542 u2DelayCellOfst[12]=13 cells (4 PI)
8216 11:49:47.634559 u2DelayCellOfst[13]=10 cells (3 PI)
8217 11:49:47.638163 u2DelayCellOfst[14]=17 cells (5 PI)
8218 11:49:47.641451 u2DelayCellOfst[15]=10 cells (3 PI)
8219 11:49:47.644774 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8220 11:49:47.651328 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8221 11:49:47.651411 DramC Write-DBI on
8222 11:49:47.651477 ==
8223 11:49:47.655005 Dram Type= 6, Freq= 0, CH_0, rank 1
8224 11:49:47.657820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 11:49:47.661312 ==
8226 11:49:47.661399
8227 11:49:47.661463
8228 11:49:47.661523 TX Vref Scan disable
8229 11:49:47.665191 == TX Byte 0 ==
8230 11:49:47.668163 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8231 11:49:47.671493 == TX Byte 1 ==
8232 11:49:47.674997 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8233 11:49:47.678082 DramC Write-DBI off
8234 11:49:47.678165
8235 11:49:47.678230 [DATLAT]
8236 11:49:47.678291 Freq=1600, CH0 RK1
8237 11:49:47.678351
8238 11:49:47.681460 DATLAT Default: 0xf
8239 11:49:47.681543 0, 0xFFFF, sum = 0
8240 11:49:47.684945 1, 0xFFFF, sum = 0
8241 11:49:47.688175 2, 0xFFFF, sum = 0
8242 11:49:47.688259 3, 0xFFFF, sum = 0
8243 11:49:47.691939 4, 0xFFFF, sum = 0
8244 11:49:47.692024 5, 0xFFFF, sum = 0
8245 11:49:47.695077 6, 0xFFFF, sum = 0
8246 11:49:47.695161 7, 0xFFFF, sum = 0
8247 11:49:47.698069 8, 0xFFFF, sum = 0
8248 11:49:47.698153 9, 0xFFFF, sum = 0
8249 11:49:47.701485 10, 0xFFFF, sum = 0
8250 11:49:47.701578 11, 0xFFFF, sum = 0
8251 11:49:47.704558 12, 0xFFFF, sum = 0
8252 11:49:47.704643 13, 0xFFFF, sum = 0
8253 11:49:47.708122 14, 0x0, sum = 1
8254 11:49:47.708208 15, 0x0, sum = 2
8255 11:49:47.711445 16, 0x0, sum = 3
8256 11:49:47.711532 17, 0x0, sum = 4
8257 11:49:47.714658 best_step = 15
8258 11:49:47.714773
8259 11:49:47.714854 ==
8260 11:49:47.718169 Dram Type= 6, Freq= 0, CH_0, rank 1
8261 11:49:47.721219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 11:49:47.721307 ==
8263 11:49:47.724688 RX Vref Scan: 0
8264 11:49:47.724771
8265 11:49:47.724837 RX Vref 0 -> 0, step: 1
8266 11:49:47.724899
8267 11:49:47.727996 RX Delay 11 -> 252, step: 4
8268 11:49:47.731340 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8269 11:49:47.737965 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8270 11:49:47.741420 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8271 11:49:47.744763 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8272 11:49:47.747773 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8273 11:49:47.751302 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8274 11:49:47.758184 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8275 11:49:47.761144 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8276 11:49:47.764533 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8277 11:49:47.767851 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8278 11:49:47.770950 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8279 11:49:47.777563 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8280 11:49:47.781115 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8281 11:49:47.784563 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8282 11:49:47.787655 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8283 11:49:47.791029 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8284 11:49:47.794956 ==
8285 11:49:47.797586 Dram Type= 6, Freq= 0, CH_0, rank 1
8286 11:49:47.801199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 11:49:47.801283 ==
8288 11:49:47.801349 DQS Delay:
8289 11:49:47.804587 DQS0 = 0, DQS1 = 0
8290 11:49:47.804671 DQM Delay:
8291 11:49:47.807966 DQM0 = 133, DQM1 = 123
8292 11:49:47.808049 DQ Delay:
8293 11:49:47.810884 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8294 11:49:47.814539 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8295 11:49:47.817472 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =120
8296 11:49:47.820845 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8297 11:49:47.820928
8298 11:49:47.820994
8299 11:49:47.821053
8300 11:49:47.824195 [DramC_TX_OE_Calibration] TA2
8301 11:49:47.827925 Original DQ_B0 (3 6) =30, OEN = 27
8302 11:49:47.830934 Original DQ_B1 (3 6) =30, OEN = 27
8303 11:49:47.834234 24, 0x0, End_B0=24 End_B1=24
8304 11:49:47.837814 25, 0x0, End_B0=25 End_B1=25
8305 11:49:47.837899 26, 0x0, End_B0=26 End_B1=26
8306 11:49:47.841001 27, 0x0, End_B0=27 End_B1=27
8307 11:49:47.844329 28, 0x0, End_B0=28 End_B1=28
8308 11:49:47.847663 29, 0x0, End_B0=29 End_B1=29
8309 11:49:47.847748 30, 0x0, End_B0=30 End_B1=30
8310 11:49:47.850859 31, 0x4141, End_B0=30 End_B1=30
8311 11:49:47.854539 Byte0 end_step=30 best_step=27
8312 11:49:47.857746 Byte1 end_step=30 best_step=27
8313 11:49:47.860812 Byte0 TX OE(2T, 0.5T) = (3, 3)
8314 11:49:47.864109 Byte1 TX OE(2T, 0.5T) = (3, 3)
8315 11:49:47.864193
8316 11:49:47.864258
8317 11:49:47.870586 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8318 11:49:47.874286 CH0 RK1: MR19=303, MR18=200D
8319 11:49:47.880649 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8320 11:49:47.883993 [RxdqsGatingPostProcess] freq 1600
8321 11:49:47.890921 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8322 11:49:47.891004 best DQS0 dly(2T, 0.5T) = (1, 1)
8323 11:49:47.894042 best DQS1 dly(2T, 0.5T) = (1, 1)
8324 11:49:47.897521 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8325 11:49:47.900826 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8326 11:49:47.903967 best DQS0 dly(2T, 0.5T) = (1, 1)
8327 11:49:47.907628 best DQS1 dly(2T, 0.5T) = (1, 1)
8328 11:49:47.911105 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8329 11:49:47.914090 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8330 11:49:47.917647 Pre-setting of DQS Precalculation
8331 11:49:47.920728 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8332 11:49:47.920812 ==
8333 11:49:47.923889 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 11:49:47.930590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 11:49:47.930675 ==
8336 11:49:47.933762 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 11:49:47.940445 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 11:49:47.943689 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 11:49:47.950293 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 11:49:47.958095 [CA 0] Center 40 (11~70) winsize 60
8341 11:49:47.961387 [CA 1] Center 40 (11~70) winsize 60
8342 11:49:47.964831 [CA 2] Center 37 (8~66) winsize 59
8343 11:49:47.967596 [CA 3] Center 36 (7~66) winsize 60
8344 11:49:47.970930 [CA 4] Center 36 (6~67) winsize 62
8345 11:49:47.974771 [CA 5] Center 36 (6~66) winsize 61
8346 11:49:47.974854
8347 11:49:47.977652 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8348 11:49:47.977736
8349 11:49:47.981099 [CATrainingPosCal] consider 1 rank data
8350 11:49:47.984425 u2DelayCellTimex100 = 285/100 ps
8351 11:49:47.987651 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8352 11:49:47.994321 CA1 delay=40 (11~70),Diff = 4 PI (13 cell)
8353 11:49:47.997563 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8354 11:49:48.000989 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8355 11:49:48.004268 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
8356 11:49:48.007832 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8357 11:49:48.007916
8358 11:49:48.010977 CA PerBit enable=1, Macro0, CA PI delay=36
8359 11:49:48.011061
8360 11:49:48.014366 [CBTSetCACLKResult] CA Dly = 36
8361 11:49:48.017650 CS Dly: 9 (0~40)
8362 11:49:48.020889 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 11:49:48.024265 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 11:49:48.024388 ==
8365 11:49:48.027759 Dram Type= 6, Freq= 0, CH_1, rank 1
8366 11:49:48.031092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 11:49:48.031208 ==
8368 11:49:48.037575 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8369 11:49:48.040853 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8370 11:49:48.047556 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8371 11:49:48.050933 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8372 11:49:48.061134 [CA 0] Center 42 (13~72) winsize 60
8373 11:49:48.064469 [CA 1] Center 42 (12~72) winsize 61
8374 11:49:48.067985 [CA 2] Center 38 (9~68) winsize 60
8375 11:49:48.071299 [CA 3] Center 37 (8~67) winsize 60
8376 11:49:48.074405 [CA 4] Center 38 (9~67) winsize 59
8377 11:49:48.078040 [CA 5] Center 37 (7~67) winsize 61
8378 11:49:48.078463
8379 11:49:48.081339 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8380 11:49:48.081721
8381 11:49:48.084469 [CATrainingPosCal] consider 2 rank data
8382 11:49:48.087629 u2DelayCellTimex100 = 285/100 ps
8383 11:49:48.091489 CA0 delay=41 (13~70),Diff = 5 PI (17 cell)
8384 11:49:48.097726 CA1 delay=41 (12~70),Diff = 5 PI (17 cell)
8385 11:49:48.101315 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8386 11:49:48.104372 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8387 11:49:48.107891 CA4 delay=38 (9~67),Diff = 2 PI (6 cell)
8388 11:49:48.110918 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8389 11:49:48.111330
8390 11:49:48.114506 CA PerBit enable=1, Macro0, CA PI delay=36
8391 11:49:48.114923
8392 11:49:48.117819 [CBTSetCACLKResult] CA Dly = 36
8393 11:49:48.120971 CS Dly: 9 (0~41)
8394 11:49:48.124642 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8395 11:49:48.127783 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8396 11:49:48.128200
8397 11:49:48.130772 ----->DramcWriteLeveling(PI) begin...
8398 11:49:48.131372 ==
8399 11:49:48.134683 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 11:49:48.137355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 11:49:48.140690 ==
8402 11:49:48.141105 Write leveling (Byte 0): 25 => 25
8403 11:49:48.144083 Write leveling (Byte 1): 27 => 27
8404 11:49:48.147670 DramcWriteLeveling(PI) end<-----
8405 11:49:48.148085
8406 11:49:48.148417 ==
8407 11:49:48.150746 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 11:49:48.157429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 11:49:48.157850 ==
8410 11:49:48.160630 [Gating] SW mode calibration
8411 11:49:48.167645 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8412 11:49:48.170669 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8413 11:49:48.177883 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 11:49:48.180781 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 11:49:48.184418 1 4 8 | B1->B0 | 2828 2d2d | 0 1 | (0 0) (1 1)
8416 11:49:48.190531 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 11:49:48.193904 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 11:49:48.197445 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 11:49:48.204303 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 11:49:48.207465 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 11:49:48.210493 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 11:49:48.213909 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8423 11:49:48.220501 1 5 8 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (1 0)
8424 11:49:48.223918 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8425 11:49:48.227425 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 11:49:48.233770 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 11:49:48.237361 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 11:49:48.240501 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 11:49:48.247410 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 11:49:48.250540 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 11:49:48.254042 1 6 8 | B1->B0 | 3535 4040 | 0 0 | (0 0) (0 0)
8432 11:49:48.260786 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 11:49:48.263692 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 11:49:48.267280 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 11:49:48.273718 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 11:49:48.277272 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 11:49:48.280611 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 11:49:48.287479 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8439 11:49:48.290708 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8440 11:49:48.293671 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8441 11:49:48.300263 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:49:48.303828 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:49:48.307318 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:49:48.314090 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:49:48.317392 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:49:48.320672 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 11:49:48.323710 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 11:49:48.330509 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 11:49:48.334096 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 11:49:48.337065 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 11:49:48.343664 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 11:49:48.346872 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 11:49:48.350362 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 11:49:48.356917 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8455 11:49:48.360408 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8456 11:49:48.364181 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8457 11:49:48.367404 Total UI for P1: 0, mck2ui 16
8458 11:49:48.370528 best dqsien dly found for B0: ( 1, 9, 6)
8459 11:49:48.377556 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 11:49:48.377976 Total UI for P1: 0, mck2ui 16
8461 11:49:48.384055 best dqsien dly found for B1: ( 1, 9, 12)
8462 11:49:48.387058 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8463 11:49:48.390155 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8464 11:49:48.390613
8465 11:49:48.393528 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8466 11:49:48.396676 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8467 11:49:48.399981 [Gating] SW calibration Done
8468 11:49:48.400408 ==
8469 11:49:48.403717 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 11:49:48.407164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 11:49:48.407584 ==
8472 11:49:48.410062 RX Vref Scan: 0
8473 11:49:48.410566
8474 11:49:48.410929 RX Vref 0 -> 0, step: 1
8475 11:49:48.411250
8476 11:49:48.413636 RX Delay 0 -> 252, step: 8
8477 11:49:48.416612 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8478 11:49:48.424038 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8479 11:49:48.426808 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8480 11:49:48.430452 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8481 11:49:48.433765 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8482 11:49:48.436989 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8483 11:49:48.440301 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8484 11:49:48.446948 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8485 11:49:48.449993 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8486 11:49:48.453427 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8487 11:49:48.457299 iDelay=200, Bit 10, Center 135 (88 ~ 183) 96
8488 11:49:48.459846 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8489 11:49:48.466933 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8490 11:49:48.469930 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8491 11:49:48.473273 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8492 11:49:48.476614 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8493 11:49:48.477058 ==
8494 11:49:48.480378 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 11:49:48.486809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 11:49:48.487408 ==
8497 11:49:48.487773 DQS Delay:
8498 11:49:48.489933 DQS0 = 0, DQS1 = 0
8499 11:49:48.490356 DQM Delay:
8500 11:49:48.490750 DQM0 = 137, DQM1 = 132
8501 11:49:48.493359 DQ Delay:
8502 11:49:48.496430 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8503 11:49:48.499899 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8504 11:49:48.503387 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8505 11:49:48.506809 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8506 11:49:48.507237
8507 11:49:48.507571
8508 11:49:48.507895 ==
8509 11:49:48.509903 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 11:49:48.513113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 11:49:48.516442 ==
8512 11:49:48.516867
8513 11:49:48.517199
8514 11:49:48.517508 TX Vref Scan disable
8515 11:49:48.520377 == TX Byte 0 ==
8516 11:49:48.523136 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8517 11:49:48.526334 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8518 11:49:48.529769 == TX Byte 1 ==
8519 11:49:48.533195 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8520 11:49:48.536104 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8521 11:49:48.539812 ==
8522 11:49:48.540342 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 11:49:48.546342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 11:49:48.546799 ==
8525 11:49:48.558039
8526 11:49:48.561261 TX Vref early break, caculate TX vref
8527 11:49:48.564908 TX Vref=16, minBit 8, minWin=22, winSum=374
8528 11:49:48.567964 TX Vref=18, minBit 10, minWin=22, winSum=383
8529 11:49:48.571419 TX Vref=20, minBit 10, minWin=23, winSum=394
8530 11:49:48.574778 TX Vref=22, minBit 10, minWin=23, winSum=401
8531 11:49:48.578308 TX Vref=24, minBit 10, minWin=24, winSum=412
8532 11:49:48.584714 TX Vref=26, minBit 15, minWin=24, winSum=418
8533 11:49:48.587809 TX Vref=28, minBit 0, minWin=26, winSum=426
8534 11:49:48.591359 TX Vref=30, minBit 12, minWin=25, winSum=420
8535 11:49:48.594706 TX Vref=32, minBit 10, minWin=24, winSum=407
8536 11:49:48.598151 TX Vref=34, minBit 13, minWin=23, winSum=403
8537 11:49:48.604357 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8538 11:49:48.604516
8539 11:49:48.607788 Final TX Range 0 Vref 28
8540 11:49:48.607924
8541 11:49:48.608029 ==
8542 11:49:48.611271 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 11:49:48.614628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 11:49:48.614746 ==
8545 11:49:48.614839
8546 11:49:48.614925
8547 11:49:48.617739 TX Vref Scan disable
8548 11:49:48.624420 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8549 11:49:48.624525 == TX Byte 0 ==
8550 11:49:48.627544 u2DelayCellOfst[0]=13 cells (4 PI)
8551 11:49:48.631413 u2DelayCellOfst[1]=10 cells (3 PI)
8552 11:49:48.634279 u2DelayCellOfst[2]=0 cells (0 PI)
8553 11:49:48.637717 u2DelayCellOfst[3]=6 cells (2 PI)
8554 11:49:48.640964 u2DelayCellOfst[4]=6 cells (2 PI)
8555 11:49:48.644183 u2DelayCellOfst[5]=17 cells (5 PI)
8556 11:49:48.647410 u2DelayCellOfst[6]=17 cells (5 PI)
8557 11:49:48.650940 u2DelayCellOfst[7]=3 cells (1 PI)
8558 11:49:48.654013 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8559 11:49:48.657903 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8560 11:49:48.661038 == TX Byte 1 ==
8561 11:49:48.664389 u2DelayCellOfst[8]=0 cells (0 PI)
8562 11:49:48.664514 u2DelayCellOfst[9]=3 cells (1 PI)
8563 11:49:48.667489 u2DelayCellOfst[10]=10 cells (3 PI)
8564 11:49:48.670683 u2DelayCellOfst[11]=3 cells (1 PI)
8565 11:49:48.674230 u2DelayCellOfst[12]=17 cells (5 PI)
8566 11:49:48.677819 u2DelayCellOfst[13]=17 cells (5 PI)
8567 11:49:48.680719 u2DelayCellOfst[14]=20 cells (6 PI)
8568 11:49:48.684284 u2DelayCellOfst[15]=17 cells (5 PI)
8569 11:49:48.687602 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8570 11:49:48.694233 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8571 11:49:48.694587 DramC Write-DBI on
8572 11:49:48.694828 ==
8573 11:49:48.697662 Dram Type= 6, Freq= 0, CH_1, rank 0
8574 11:49:48.704405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8575 11:49:48.704827 ==
8576 11:49:48.705222
8577 11:49:48.705582
8578 11:49:48.705885 TX Vref Scan disable
8579 11:49:48.708152 == TX Byte 0 ==
8580 11:49:48.711688 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8581 11:49:48.714810 == TX Byte 1 ==
8582 11:49:48.717963 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8583 11:49:48.721430 DramC Write-DBI off
8584 11:49:48.721695
8585 11:49:48.721758 [DATLAT]
8586 11:49:48.721818 Freq=1600, CH1 RK0
8587 11:49:48.721876
8588 11:49:48.724235 DATLAT Default: 0xf
8589 11:49:48.724317 0, 0xFFFF, sum = 0
8590 11:49:48.727476 1, 0xFFFF, sum = 0
8591 11:49:48.727559 2, 0xFFFF, sum = 0
8592 11:49:48.730835 3, 0xFFFF, sum = 0
8593 11:49:48.734138 4, 0xFFFF, sum = 0
8594 11:49:48.734227 5, 0xFFFF, sum = 0
8595 11:49:48.737594 6, 0xFFFF, sum = 0
8596 11:49:48.737690 7, 0xFFFF, sum = 0
8597 11:49:48.740812 8, 0xFFFF, sum = 0
8598 11:49:48.740895 9, 0xFFFF, sum = 0
8599 11:49:48.744282 10, 0xFFFF, sum = 0
8600 11:49:48.744371 11, 0xFFFF, sum = 0
8601 11:49:48.747447 12, 0xFFFF, sum = 0
8602 11:49:48.747536 13, 0xFFFF, sum = 0
8603 11:49:48.750856 14, 0x0, sum = 1
8604 11:49:48.750951 15, 0x0, sum = 2
8605 11:49:48.754269 16, 0x0, sum = 3
8606 11:49:48.754373 17, 0x0, sum = 4
8607 11:49:48.757363 best_step = 15
8608 11:49:48.757465
8609 11:49:48.757545 ==
8610 11:49:48.761336 Dram Type= 6, Freq= 0, CH_1, rank 0
8611 11:49:48.764179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8612 11:49:48.764301 ==
8613 11:49:48.767450 RX Vref Scan: 1
8614 11:49:48.767589
8615 11:49:48.767695 Set Vref Range= 24 -> 127
8616 11:49:48.767794
8617 11:49:48.770402 RX Vref 24 -> 127, step: 1
8618 11:49:48.770536
8619 11:49:48.774049 RX Delay 19 -> 252, step: 4
8620 11:49:48.774252
8621 11:49:48.777340 Set Vref, RX VrefLevel [Byte0]: 24
8622 11:49:48.780623 [Byte1]: 24
8623 11:49:48.780946
8624 11:49:48.784075 Set Vref, RX VrefLevel [Byte0]: 25
8625 11:49:48.787232 [Byte1]: 25
8626 11:49:48.790576
8627 11:49:48.790994 Set Vref, RX VrefLevel [Byte0]: 26
8628 11:49:48.793963 [Byte1]: 26
8629 11:49:48.798237
8630 11:49:48.798824 Set Vref, RX VrefLevel [Byte0]: 27
8631 11:49:48.801672 [Byte1]: 27
8632 11:49:48.806020
8633 11:49:48.806536 Set Vref, RX VrefLevel [Byte0]: 28
8634 11:49:48.809514 [Byte1]: 28
8635 11:49:48.813387
8636 11:49:48.813804 Set Vref, RX VrefLevel [Byte0]: 29
8637 11:49:48.816739 [Byte1]: 29
8638 11:49:48.821072
8639 11:49:48.821488 Set Vref, RX VrefLevel [Byte0]: 30
8640 11:49:48.824460 [Byte1]: 30
8641 11:49:48.828571
8642 11:49:48.828989 Set Vref, RX VrefLevel [Byte0]: 31
8643 11:49:48.831871 [Byte1]: 31
8644 11:49:48.836216
8645 11:49:48.836632 Set Vref, RX VrefLevel [Byte0]: 32
8646 11:49:48.839346 [Byte1]: 32
8647 11:49:48.843922
8648 11:49:48.844598 Set Vref, RX VrefLevel [Byte0]: 33
8649 11:49:48.847238 [Byte1]: 33
8650 11:49:48.851106
8651 11:49:48.851520 Set Vref, RX VrefLevel [Byte0]: 34
8652 11:49:48.854657 [Byte1]: 34
8653 11:49:48.858996
8654 11:49:48.859411 Set Vref, RX VrefLevel [Byte0]: 35
8655 11:49:48.862185 [Byte1]: 35
8656 11:49:48.866360
8657 11:49:48.866807 Set Vref, RX VrefLevel [Byte0]: 36
8658 11:49:48.870146 [Byte1]: 36
8659 11:49:48.873859
8660 11:49:48.874304 Set Vref, RX VrefLevel [Byte0]: 37
8661 11:49:48.877629 [Byte1]: 37
8662 11:49:48.881519
8663 11:49:48.881941 Set Vref, RX VrefLevel [Byte0]: 38
8664 11:49:48.885033 [Byte1]: 38
8665 11:49:48.889087
8666 11:49:48.889630 Set Vref, RX VrefLevel [Byte0]: 39
8667 11:49:48.892551 [Byte1]: 39
8668 11:49:48.896510
8669 11:49:48.896935 Set Vref, RX VrefLevel [Byte0]: 40
8670 11:49:48.899774 [Byte1]: 40
8671 11:49:48.904165
8672 11:49:48.904591 Set Vref, RX VrefLevel [Byte0]: 41
8673 11:49:48.907808 [Byte1]: 41
8674 11:49:48.911794
8675 11:49:48.912219 Set Vref, RX VrefLevel [Byte0]: 42
8676 11:49:48.914967 [Byte1]: 42
8677 11:49:48.919608
8678 11:49:48.920050 Set Vref, RX VrefLevel [Byte0]: 43
8679 11:49:48.922542 [Byte1]: 43
8680 11:49:48.926737
8681 11:49:48.927173 Set Vref, RX VrefLevel [Byte0]: 44
8682 11:49:48.929887 [Byte1]: 44
8683 11:49:48.934680
8684 11:49:48.935122 Set Vref, RX VrefLevel [Byte0]: 45
8685 11:49:48.937529 [Byte1]: 45
8686 11:49:48.942317
8687 11:49:48.942787 Set Vref, RX VrefLevel [Byte0]: 46
8688 11:49:48.945466 [Byte1]: 46
8689 11:49:48.949994
8690 11:49:48.950470 Set Vref, RX VrefLevel [Byte0]: 47
8691 11:49:48.952781 [Byte1]: 47
8692 11:49:48.957074
8693 11:49:48.957510 Set Vref, RX VrefLevel [Byte0]: 48
8694 11:49:48.960581 [Byte1]: 48
8695 11:49:48.964997
8696 11:49:48.965435 Set Vref, RX VrefLevel [Byte0]: 49
8697 11:49:48.968022 [Byte1]: 49
8698 11:49:48.972451
8699 11:49:48.972888 Set Vref, RX VrefLevel [Byte0]: 50
8700 11:49:48.975686 [Byte1]: 50
8701 11:49:48.980003
8702 11:49:48.980443 Set Vref, RX VrefLevel [Byte0]: 51
8703 11:49:48.983473 [Byte1]: 51
8704 11:49:48.987451
8705 11:49:48.987891 Set Vref, RX VrefLevel [Byte0]: 52
8706 11:49:48.990898 [Byte1]: 52
8707 11:49:48.995020
8708 11:49:48.995457 Set Vref, RX VrefLevel [Byte0]: 53
8709 11:49:48.998692 [Byte1]: 53
8710 11:49:49.002532
8711 11:49:49.002969 Set Vref, RX VrefLevel [Byte0]: 54
8712 11:49:49.005839 [Byte1]: 54
8713 11:49:49.010006
8714 11:49:49.010464 Set Vref, RX VrefLevel [Byte0]: 55
8715 11:49:49.013485 [Byte1]: 55
8716 11:49:49.017608
8717 11:49:49.018047 Set Vref, RX VrefLevel [Byte0]: 56
8718 11:49:49.021053 [Byte1]: 56
8719 11:49:49.025484
8720 11:49:49.025923 Set Vref, RX VrefLevel [Byte0]: 57
8721 11:49:49.029128 [Byte1]: 57
8722 11:49:49.032927
8723 11:49:49.033357 Set Vref, RX VrefLevel [Byte0]: 58
8724 11:49:49.036093 [Byte1]: 58
8725 11:49:49.040552
8726 11:49:49.040980 Set Vref, RX VrefLevel [Byte0]: 59
8727 11:49:49.044157 [Byte1]: 59
8728 11:49:49.048324
8729 11:49:49.048749 Set Vref, RX VrefLevel [Byte0]: 60
8730 11:49:49.051378 [Byte1]: 60
8731 11:49:49.055709
8732 11:49:49.056133 Set Vref, RX VrefLevel [Byte0]: 61
8733 11:49:49.058976 [Byte1]: 61
8734 11:49:49.063491
8735 11:49:49.063917 Set Vref, RX VrefLevel [Byte0]: 62
8736 11:49:49.066660 [Byte1]: 62
8737 11:49:49.070992
8738 11:49:49.071415 Set Vref, RX VrefLevel [Byte0]: 63
8739 11:49:49.074485 [Byte1]: 63
8740 11:49:49.078311
8741 11:49:49.078808 Set Vref, RX VrefLevel [Byte0]: 64
8742 11:49:49.081875 [Byte1]: 64
8743 11:49:49.085906
8744 11:49:49.086501 Set Vref, RX VrefLevel [Byte0]: 65
8745 11:49:49.089178 [Byte1]: 65
8746 11:49:49.093403
8747 11:49:49.093974 Set Vref, RX VrefLevel [Byte0]: 66
8748 11:49:49.097311 [Byte1]: 66
8749 11:49:49.101355
8750 11:49:49.101939 Set Vref, RX VrefLevel [Byte0]: 67
8751 11:49:49.104423 [Byte1]: 67
8752 11:49:49.108808
8753 11:49:49.109384 Set Vref, RX VrefLevel [Byte0]: 68
8754 11:49:49.111923 [Byte1]: 68
8755 11:49:49.116333
8756 11:49:49.116760 Set Vref, RX VrefLevel [Byte0]: 69
8757 11:49:49.119622 [Byte1]: 69
8758 11:49:49.123721
8759 11:49:49.124296 Set Vref, RX VrefLevel [Byte0]: 70
8760 11:49:49.127078 [Byte1]: 70
8761 11:49:49.131356
8762 11:49:49.132050 Set Vref, RX VrefLevel [Byte0]: 71
8763 11:49:49.134540 [Byte1]: 71
8764 11:49:49.139198
8765 11:49:49.139686 Set Vref, RX VrefLevel [Byte0]: 72
8766 11:49:49.142061 [Byte1]: 72
8767 11:49:49.146418
8768 11:49:49.146941 Set Vref, RX VrefLevel [Byte0]: 73
8769 11:49:49.149920 [Byte1]: 73
8770 11:49:49.154049
8771 11:49:49.154676 Set Vref, RX VrefLevel [Byte0]: 74
8772 11:49:49.157378 [Byte1]: 74
8773 11:49:49.161581
8774 11:49:49.162038 Set Vref, RX VrefLevel [Byte0]: 75
8775 11:49:49.164744 [Byte1]: 75
8776 11:49:49.169213
8777 11:49:49.169640 Final RX Vref Byte 0 = 60 to rank0
8778 11:49:49.172943 Final RX Vref Byte 1 = 63 to rank0
8779 11:49:49.175840 Final RX Vref Byte 0 = 60 to rank1
8780 11:49:49.179387 Final RX Vref Byte 1 = 63 to rank1==
8781 11:49:49.182378 Dram Type= 6, Freq= 0, CH_1, rank 0
8782 11:49:49.189093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 11:49:49.189176 ==
8784 11:49:49.189241 DQS Delay:
8785 11:49:49.189300 DQS0 = 0, DQS1 = 0
8786 11:49:49.192166 DQM Delay:
8787 11:49:49.192247 DQM0 = 134, DQM1 = 129
8788 11:49:49.195383 DQ Delay:
8789 11:49:49.198850 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8790 11:49:49.202031 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8791 11:49:49.205548 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122
8792 11:49:49.209265 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8793 11:49:49.209346
8794 11:49:49.209410
8795 11:49:49.209468
8796 11:49:49.212353 [DramC_TX_OE_Calibration] TA2
8797 11:49:49.215326 Original DQ_B0 (3 6) =30, OEN = 27
8798 11:49:49.218798 Original DQ_B1 (3 6) =30, OEN = 27
8799 11:49:49.222323 24, 0x0, End_B0=24 End_B1=24
8800 11:49:49.222446 25, 0x0, End_B0=25 End_B1=25
8801 11:49:49.225602 26, 0x0, End_B0=26 End_B1=26
8802 11:49:49.229462 27, 0x0, End_B0=27 End_B1=27
8803 11:49:49.232538 28, 0x0, End_B0=28 End_B1=28
8804 11:49:49.232621 29, 0x0, End_B0=29 End_B1=29
8805 11:49:49.235988 30, 0x0, End_B0=30 End_B1=30
8806 11:49:49.238862 31, 0x4141, End_B0=30 End_B1=30
8807 11:49:49.242317 Byte0 end_step=30 best_step=27
8808 11:49:49.245456 Byte1 end_step=30 best_step=27
8809 11:49:49.248837 Byte0 TX OE(2T, 0.5T) = (3, 3)
8810 11:49:49.248920 Byte1 TX OE(2T, 0.5T) = (3, 3)
8811 11:49:49.252123
8812 11:49:49.252209
8813 11:49:49.258811 [DQSOSCAuto] RK0, (LSB)MR18= 0x1928, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 397 ps
8814 11:49:49.262239 CH1 RK0: MR19=303, MR18=1928
8815 11:49:49.269466 CH1_RK0: MR19=0x303, MR18=0x1928, DQSOSC=389, MR23=63, INC=24, DEC=16
8816 11:49:49.269894
8817 11:49:49.272755 ----->DramcWriteLeveling(PI) begin...
8818 11:49:49.273185 ==
8819 11:49:49.276036 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 11:49:49.279329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 11:49:49.279755 ==
8822 11:49:49.282933 Write leveling (Byte 0): 24 => 24
8823 11:49:49.285837 Write leveling (Byte 1): 27 => 27
8824 11:49:49.289287 DramcWriteLeveling(PI) end<-----
8825 11:49:49.289710
8826 11:49:49.290044 ==
8827 11:49:49.292561 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 11:49:49.296139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 11:49:49.296563 ==
8830 11:49:49.299423 [Gating] SW mode calibration
8831 11:49:49.305694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8832 11:49:49.312370 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8833 11:49:49.315852 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 11:49:49.319105 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 11:49:49.325672 1 4 8 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
8836 11:49:49.328627 1 4 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8837 11:49:49.332422 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 11:49:49.338964 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 11:49:49.342042 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 11:49:49.345513 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 11:49:49.352504 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 11:49:49.355552 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8843 11:49:49.358615 1 5 8 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 0)
8844 11:49:49.365067 1 5 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
8845 11:49:49.368307 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 11:49:49.372585 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 11:49:49.378522 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 11:49:49.382078 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 11:49:49.385155 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 11:49:49.391769 1 6 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8851 11:49:49.394773 1 6 8 | B1->B0 | 4342 2525 | 1 0 | (0 0) (0 0)
8852 11:49:49.398328 1 6 12 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)
8853 11:49:49.404894 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 11:49:49.408484 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 11:49:49.411700 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 11:49:49.418185 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 11:49:49.421489 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 11:49:49.424852 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 11:49:49.431593 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8860 11:49:49.434708 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8861 11:49:49.438081 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 11:49:49.444748 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 11:49:49.447976 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 11:49:49.451335 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 11:49:49.454930 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 11:49:49.461439 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 11:49:49.464854 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 11:49:49.468002 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 11:49:49.474816 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 11:49:49.478038 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 11:49:49.481217 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 11:49:49.487873 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 11:49:49.491422 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 11:49:49.494883 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8875 11:49:49.501360 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8876 11:49:49.504661 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8877 11:49:49.508183 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 11:49:49.511219 Total UI for P1: 0, mck2ui 16
8879 11:49:49.514512 best dqsien dly found for B0: ( 1, 9, 8)
8880 11:49:49.517977 Total UI for P1: 0, mck2ui 16
8881 11:49:49.521372 best dqsien dly found for B1: ( 1, 9, 8)
8882 11:49:49.524535 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8883 11:49:49.528013 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8884 11:49:49.528432
8885 11:49:49.534474 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8886 11:49:49.537666 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8887 11:49:49.538091 [Gating] SW calibration Done
8888 11:49:49.541551 ==
8889 11:49:49.542068 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 11:49:49.547953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 11:49:49.548490 ==
8892 11:49:49.548829 RX Vref Scan: 0
8893 11:49:49.549144
8894 11:49:49.550907 RX Vref 0 -> 0, step: 1
8895 11:49:49.551325
8896 11:49:49.554193 RX Delay 0 -> 252, step: 8
8897 11:49:49.557951 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8898 11:49:49.561078 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8899 11:49:49.564692 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8900 11:49:49.570827 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8901 11:49:49.574577 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8902 11:49:49.578229 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8903 11:49:49.581221 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8904 11:49:49.584522 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8905 11:49:49.591062 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8906 11:49:49.594144 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8907 11:49:49.597757 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8908 11:49:49.601007 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8909 11:49:49.604515 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8910 11:49:49.610763 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8911 11:49:49.614514 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8912 11:49:49.617950 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8913 11:49:49.618557 ==
8914 11:49:49.621144 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 11:49:49.624662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 11:49:49.625226 ==
8917 11:49:49.627540 DQS Delay:
8918 11:49:49.628005 DQS0 = 0, DQS1 = 0
8919 11:49:49.631056 DQM Delay:
8920 11:49:49.631706 DQM0 = 136, DQM1 = 132
8921 11:49:49.634012 DQ Delay:
8922 11:49:49.637525 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8923 11:49:49.640965 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8924 11:49:49.644221 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8925 11:49:49.648110 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8926 11:49:49.648707
8927 11:49:49.649300
8928 11:49:49.649785 ==
8929 11:49:49.650861 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 11:49:49.654007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 11:49:49.654499 ==
8932 11:49:49.654869
8933 11:49:49.655260
8934 11:49:49.657414 TX Vref Scan disable
8935 11:49:49.660877 == TX Byte 0 ==
8936 11:49:49.664015 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8937 11:49:49.667651 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8938 11:49:49.670978 == TX Byte 1 ==
8939 11:49:49.674003 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8940 11:49:49.678066 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8941 11:49:49.678671 ==
8942 11:49:49.680615 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 11:49:49.687055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 11:49:49.687611 ==
8945 11:49:49.698635
8946 11:49:49.701764 TX Vref early break, caculate TX vref
8947 11:49:49.705366 TX Vref=16, minBit 9, minWin=23, winSum=387
8948 11:49:49.708328 TX Vref=18, minBit 10, minWin=23, winSum=392
8949 11:49:49.711761 TX Vref=20, minBit 9, minWin=24, winSum=405
8950 11:49:49.715511 TX Vref=22, minBit 9, minWin=24, winSum=412
8951 11:49:49.718532 TX Vref=24, minBit 11, minWin=25, winSum=423
8952 11:49:49.724759 TX Vref=26, minBit 9, minWin=25, winSum=426
8953 11:49:49.728578 TX Vref=28, minBit 11, minWin=25, winSum=427
8954 11:49:49.731520 TX Vref=30, minBit 10, minWin=25, winSum=422
8955 11:49:49.734737 TX Vref=32, minBit 0, minWin=25, winSum=414
8956 11:49:49.738066 TX Vref=34, minBit 10, minWin=23, winSum=398
8957 11:49:49.745449 [TxChooseVref] Worse bit 11, Min win 25, Win sum 427, Final Vref 28
8958 11:49:49.746017
8959 11:49:49.748791 Final TX Range 0 Vref 28
8960 11:49:49.749375
8961 11:49:49.749745 ==
8962 11:49:49.751488 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 11:49:49.755181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 11:49:49.755751 ==
8965 11:49:49.756118
8966 11:49:49.756461
8967 11:49:49.758034 TX Vref Scan disable
8968 11:49:49.765089 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8969 11:49:49.765666 == TX Byte 0 ==
8970 11:49:49.767997 u2DelayCellOfst[0]=13 cells (4 PI)
8971 11:49:49.771470 u2DelayCellOfst[1]=10 cells (3 PI)
8972 11:49:49.774736 u2DelayCellOfst[2]=0 cells (0 PI)
8973 11:49:49.778122 u2DelayCellOfst[3]=3 cells (1 PI)
8974 11:49:49.781170 u2DelayCellOfst[4]=6 cells (2 PI)
8975 11:49:49.784448 u2DelayCellOfst[5]=17 cells (5 PI)
8976 11:49:49.787748 u2DelayCellOfst[6]=17 cells (5 PI)
8977 11:49:49.791237 u2DelayCellOfst[7]=3 cells (1 PI)
8978 11:49:49.794341 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8979 11:49:49.798140 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8980 11:49:49.801033 == TX Byte 1 ==
8981 11:49:49.804318 u2DelayCellOfst[8]=0 cells (0 PI)
8982 11:49:49.807509 u2DelayCellOfst[9]=3 cells (1 PI)
8983 11:49:49.807973 u2DelayCellOfst[10]=10 cells (3 PI)
8984 11:49:49.810973 u2DelayCellOfst[11]=3 cells (1 PI)
8985 11:49:49.814476 u2DelayCellOfst[12]=17 cells (5 PI)
8986 11:49:49.817836 u2DelayCellOfst[13]=17 cells (5 PI)
8987 11:49:49.821043 u2DelayCellOfst[14]=20 cells (6 PI)
8988 11:49:49.824572 u2DelayCellOfst[15]=20 cells (6 PI)
8989 11:49:49.830715 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8990 11:49:49.834309 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8991 11:49:49.834937 DramC Write-DBI on
8992 11:49:49.835309 ==
8993 11:49:49.837645 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 11:49:49.844093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 11:49:49.844658 ==
8996 11:49:49.845091
8997 11:49:49.845445
8998 11:49:49.845776 TX Vref Scan disable
8999 11:49:49.848263 == TX Byte 0 ==
9000 11:49:49.851267 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9001 11:49:49.855244 == TX Byte 1 ==
9002 11:49:49.858552 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9003 11:49:49.861569 DramC Write-DBI off
9004 11:49:49.862033
9005 11:49:49.862442 [DATLAT]
9006 11:49:49.862806 Freq=1600, CH1 RK1
9007 11:49:49.863377
9008 11:49:49.864801 DATLAT Default: 0xf
9009 11:49:49.865291 0, 0xFFFF, sum = 0
9010 11:49:49.868205 1, 0xFFFF, sum = 0
9011 11:49:49.868682 2, 0xFFFF, sum = 0
9012 11:49:49.871616 3, 0xFFFF, sum = 0
9013 11:49:49.874844 4, 0xFFFF, sum = 0
9014 11:49:49.875515 5, 0xFFFF, sum = 0
9015 11:49:49.878088 6, 0xFFFF, sum = 0
9016 11:49:49.878771 7, 0xFFFF, sum = 0
9017 11:49:49.881679 8, 0xFFFF, sum = 0
9018 11:49:49.882252 9, 0xFFFF, sum = 0
9019 11:49:49.884675 10, 0xFFFF, sum = 0
9020 11:49:49.885145 11, 0xFFFF, sum = 0
9021 11:49:49.888113 12, 0xFFFF, sum = 0
9022 11:49:49.888593 13, 0xFFFF, sum = 0
9023 11:49:49.891676 14, 0x0, sum = 1
9024 11:49:49.892245 15, 0x0, sum = 2
9025 11:49:49.894951 16, 0x0, sum = 3
9026 11:49:49.895420 17, 0x0, sum = 4
9027 11:49:49.898300 best_step = 15
9028 11:49:49.898803
9029 11:49:49.899168 ==
9030 11:49:49.901643 Dram Type= 6, Freq= 0, CH_1, rank 1
9031 11:49:49.905025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9032 11:49:49.905494 ==
9033 11:49:49.905862 RX Vref Scan: 0
9034 11:49:49.906203
9035 11:49:49.908359 RX Vref 0 -> 0, step: 1
9036 11:49:49.908842
9037 11:49:49.911500 RX Delay 19 -> 252, step: 4
9038 11:49:49.915141 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9039 11:49:49.918433 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9040 11:49:49.925174 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9041 11:49:49.928511 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9042 11:49:49.931741 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9043 11:49:49.935112 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9044 11:49:49.938412 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9045 11:49:49.944870 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
9046 11:49:49.948299 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9047 11:49:49.951374 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9048 11:49:49.955180 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9049 11:49:49.958229 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9050 11:49:49.965111 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9051 11:49:49.968085 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9052 11:49:49.971665 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9053 11:49:49.974518 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9054 11:49:49.974981 ==
9055 11:49:49.978097 Dram Type= 6, Freq= 0, CH_1, rank 1
9056 11:49:49.984789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9057 11:49:49.985266 ==
9058 11:49:49.985635 DQS Delay:
9059 11:49:49.986035 DQS0 = 0, DQS1 = 0
9060 11:49:49.988236 DQM Delay:
9061 11:49:49.988705 DQM0 = 133, DQM1 = 130
9062 11:49:49.991159 DQ Delay:
9063 11:49:49.994687 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9064 11:49:49.997849 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
9065 11:49:50.001053 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =124
9066 11:49:50.005080 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9067 11:49:50.005532
9068 11:49:50.005898
9069 11:49:50.006442
9070 11:49:50.007883 [DramC_TX_OE_Calibration] TA2
9071 11:49:50.011525 Original DQ_B0 (3 6) =30, OEN = 27
9072 11:49:50.014892 Original DQ_B1 (3 6) =30, OEN = 27
9073 11:49:50.018231 24, 0x0, End_B0=24 End_B1=24
9074 11:49:50.018838 25, 0x0, End_B0=25 End_B1=25
9075 11:49:50.021329 26, 0x0, End_B0=26 End_B1=26
9076 11:49:50.024979 27, 0x0, End_B0=27 End_B1=27
9077 11:49:50.027935 28, 0x0, End_B0=28 End_B1=28
9078 11:49:50.028370 29, 0x0, End_B0=29 End_B1=29
9079 11:49:50.031176 30, 0x0, End_B0=30 End_B1=30
9080 11:49:50.034695 31, 0x4141, End_B0=30 End_B1=30
9081 11:49:50.038291 Byte0 end_step=30 best_step=27
9082 11:49:50.041808 Byte1 end_step=30 best_step=27
9083 11:49:50.044697 Byte0 TX OE(2T, 0.5T) = (3, 3)
9084 11:49:50.045130 Byte1 TX OE(2T, 0.5T) = (3, 3)
9085 11:49:50.045468
9086 11:49:50.048698
9087 11:49:50.054727 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9088 11:49:50.058186 CH1 RK1: MR19=303, MR18=1D07
9089 11:49:50.064799 CH1_RK1: MR19=0x303, MR18=0x1D07, DQSOSC=395, MR23=63, INC=23, DEC=15
9090 11:49:50.068181 [RxdqsGatingPostProcess] freq 1600
9091 11:49:50.071030 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9092 11:49:50.074446 best DQS0 dly(2T, 0.5T) = (1, 1)
9093 11:49:50.077720 best DQS1 dly(2T, 0.5T) = (1, 1)
9094 11:49:50.080998 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9095 11:49:50.084615 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9096 11:49:50.088000 best DQS0 dly(2T, 0.5T) = (1, 1)
9097 11:49:50.090920 best DQS1 dly(2T, 0.5T) = (1, 1)
9098 11:49:50.094176 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9099 11:49:50.097600 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9100 11:49:50.100937 Pre-setting of DQS Precalculation
9101 11:49:50.104674 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9102 11:49:50.110705 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9103 11:49:50.117648 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9104 11:49:50.118220
9105 11:49:50.120907
9106 11:49:50.121565 [Calibration Summary] 3200 Mbps
9107 11:49:50.124212 CH 0, Rank 0
9108 11:49:50.124718 SW Impedance : PASS
9109 11:49:50.127633 DUTY Scan : NO K
9110 11:49:50.130850 ZQ Calibration : PASS
9111 11:49:50.131394 Jitter Meter : NO K
9112 11:49:50.134339 CBT Training : PASS
9113 11:49:50.137872 Write leveling : PASS
9114 11:49:50.138489 RX DQS gating : PASS
9115 11:49:50.141354 RX DQ/DQS(RDDQC) : PASS
9116 11:49:50.144293 TX DQ/DQS : PASS
9117 11:49:50.144808 RX DATLAT : PASS
9118 11:49:50.147362 RX DQ/DQS(Engine): PASS
9119 11:49:50.151098 TX OE : PASS
9120 11:49:50.151521 All Pass.
9121 11:49:50.151855
9122 11:49:50.152165 CH 0, Rank 1
9123 11:49:50.154322 SW Impedance : PASS
9124 11:49:50.154766 DUTY Scan : NO K
9125 11:49:50.157822 ZQ Calibration : PASS
9126 11:49:50.160673 Jitter Meter : NO K
9127 11:49:50.161097 CBT Training : PASS
9128 11:49:50.163930 Write leveling : PASS
9129 11:49:50.167438 RX DQS gating : PASS
9130 11:49:50.167859 RX DQ/DQS(RDDQC) : PASS
9131 11:49:50.170894 TX DQ/DQS : PASS
9132 11:49:50.174097 RX DATLAT : PASS
9133 11:49:50.174664 RX DQ/DQS(Engine): PASS
9134 11:49:50.177204 TX OE : PASS
9135 11:49:50.177629 All Pass.
9136 11:49:50.177956
9137 11:49:50.180813 CH 1, Rank 0
9138 11:49:50.181379 SW Impedance : PASS
9139 11:49:50.184301 DUTY Scan : NO K
9140 11:49:50.187321 ZQ Calibration : PASS
9141 11:49:50.187741 Jitter Meter : NO K
9142 11:49:50.190710 CBT Training : PASS
9143 11:49:50.194111 Write leveling : PASS
9144 11:49:50.194649 RX DQS gating : PASS
9145 11:49:50.197318 RX DQ/DQS(RDDQC) : PASS
9146 11:49:50.200834 TX DQ/DQS : PASS
9147 11:49:50.201385 RX DATLAT : PASS
9148 11:49:50.204343 RX DQ/DQS(Engine): PASS
9149 11:49:50.204877 TX OE : PASS
9150 11:49:50.207410 All Pass.
9151 11:49:50.207851
9152 11:49:50.208183 CH 1, Rank 1
9153 11:49:50.210747 SW Impedance : PASS
9154 11:49:50.211170 DUTY Scan : NO K
9155 11:49:50.213899 ZQ Calibration : PASS
9156 11:49:50.217216 Jitter Meter : NO K
9157 11:49:50.217735 CBT Training : PASS
9158 11:49:50.220707 Write leveling : PASS
9159 11:49:50.223744 RX DQS gating : PASS
9160 11:49:50.224231 RX DQ/DQS(RDDQC) : PASS
9161 11:49:50.227131 TX DQ/DQS : PASS
9162 11:49:50.230823 RX DATLAT : PASS
9163 11:49:50.231240 RX DQ/DQS(Engine): PASS
9164 11:49:50.233923 TX OE : PASS
9165 11:49:50.234342 All Pass.
9166 11:49:50.234722
9167 11:49:50.237497 DramC Write-DBI on
9168 11:49:50.240613 PER_BANK_REFRESH: Hybrid Mode
9169 11:49:50.241164 TX_TRACKING: ON
9170 11:49:50.250470 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9171 11:49:50.257238 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9172 11:49:50.263780 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9173 11:49:50.266956 [FAST_K] Save calibration result to emmc
9174 11:49:50.270449 sync common calibartion params.
9175 11:49:50.273660 sync cbt_mode0:1, 1:1
9176 11:49:50.276827 dram_init: ddr_geometry: 2
9177 11:49:50.277348 dram_init: ddr_geometry: 2
9178 11:49:50.280426 dram_init: ddr_geometry: 2
9179 11:49:50.283656 0:dram_rank_size:100000000
9180 11:49:50.286854 1:dram_rank_size:100000000
9181 11:49:50.290357 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9182 11:49:50.293579 DFS_SHUFFLE_HW_MODE: ON
9183 11:49:50.296753 dramc_set_vcore_voltage set vcore to 725000
9184 11:49:50.300033 Read voltage for 1600, 0
9185 11:49:50.300487 Vio18 = 0
9186 11:49:50.300952 Vcore = 725000
9187 11:49:50.303746 Vdram = 0
9188 11:49:50.304163 Vddq = 0
9189 11:49:50.304494 Vmddr = 0
9190 11:49:50.306828 switch to 3200 Mbps bootup
9191 11:49:50.310244 [DramcRunTimeConfig]
9192 11:49:50.310918 PHYPLL
9193 11:49:50.311456 DPM_CONTROL_AFTERK: ON
9194 11:49:50.313489 PER_BANK_REFRESH: ON
9195 11:49:50.317129 REFRESH_OVERHEAD_REDUCTION: ON
9196 11:49:50.317754 CMD_PICG_NEW_MODE: OFF
9197 11:49:50.320080 XRTWTW_NEW_MODE: ON
9198 11:49:50.320723 XRTRTR_NEW_MODE: ON
9199 11:49:50.323267 TX_TRACKING: ON
9200 11:49:50.323838 RDSEL_TRACKING: OFF
9201 11:49:50.326818 DQS Precalculation for DVFS: ON
9202 11:49:50.330112 RX_TRACKING: OFF
9203 11:49:50.330708 HW_GATING DBG: ON
9204 11:49:50.333263 ZQCS_ENABLE_LP4: ON
9205 11:49:50.333763 RX_PICG_NEW_MODE: ON
9206 11:49:50.336891 TX_PICG_NEW_MODE: ON
9207 11:49:50.340047 ENABLE_RX_DCM_DPHY: ON
9208 11:49:50.343188 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9209 11:49:50.343783 DUMMY_READ_FOR_TRACKING: OFF
9210 11:49:50.346630 !!! SPM_CONTROL_AFTERK: OFF
9211 11:49:50.350105 !!! SPM could not control APHY
9212 11:49:50.353822 IMPEDANCE_TRACKING: ON
9213 11:49:50.354239 TEMP_SENSOR: ON
9214 11:49:50.354620 HW_SAVE_FOR_SR: OFF
9215 11:49:50.356482 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9216 11:49:50.363124 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9217 11:49:50.363633 Read ODT Tracking: ON
9218 11:49:50.366521 Refresh Rate DeBounce: ON
9219 11:49:50.367137 DFS_NO_QUEUE_FLUSH: ON
9220 11:49:50.369731 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9221 11:49:50.373369 ENABLE_DFS_RUNTIME_MRW: OFF
9222 11:49:50.376402 DDR_RESERVE_NEW_MODE: ON
9223 11:49:50.376922 MR_CBT_SWITCH_FREQ: ON
9224 11:49:50.379593 =========================
9225 11:49:50.399515 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9226 11:49:50.402436 dram_init: ddr_geometry: 2
9227 11:49:50.420803 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9228 11:49:50.423781 dram_init: dram init end (result: 0)
9229 11:49:50.430379 DRAM-K: Full calibration passed in 24531 msecs
9230 11:49:50.433832 MRC: failed to locate region type 0.
9231 11:49:50.434405 DRAM rank0 size:0x100000000,
9232 11:49:50.437439 DRAM rank1 size=0x100000000
9233 11:49:50.447273 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9234 11:49:50.453980 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9235 11:49:50.460050 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9236 11:49:50.466649 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9237 11:49:50.469949 DRAM rank0 size:0x100000000,
9238 11:49:50.473051 DRAM rank1 size=0x100000000
9239 11:49:50.473150 CBMEM:
9240 11:49:50.476392 IMD: root @ 0xfffff000 254 entries.
9241 11:49:50.480008 IMD: root @ 0xffffec00 62 entries.
9242 11:49:50.482964 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9243 11:49:50.489645 WARNING: RO_VPD is uninitialized or empty.
9244 11:49:50.493204 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9245 11:49:50.500513 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9246 11:49:50.513108 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9247 11:49:50.525281 BS: romstage times (exec / console): total (unknown) / 24027 ms
9248 11:49:50.525845
9249 11:49:50.526181
9250 11:49:50.535083 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9251 11:49:50.538328 ARM64: Exception handlers installed.
9252 11:49:50.541655 ARM64: Testing exception
9253 11:49:50.544976 ARM64: Done test exception
9254 11:49:50.545517 Enumerating buses...
9255 11:49:50.548326 Show all devs... Before device enumeration.
9256 11:49:50.551878 Root Device: enabled 1
9257 11:49:50.554930 CPU_CLUSTER: 0: enabled 1
9258 11:49:50.555491 CPU: 00: enabled 1
9259 11:49:50.558417 Compare with tree...
9260 11:49:50.558886 Root Device: enabled 1
9261 11:49:50.561646 CPU_CLUSTER: 0: enabled 1
9262 11:49:50.564772 CPU: 00: enabled 1
9263 11:49:50.565331 Root Device scanning...
9264 11:49:50.568042 scan_static_bus for Root Device
9265 11:49:50.571216 CPU_CLUSTER: 0 enabled
9266 11:49:50.574514 scan_static_bus for Root Device done
9267 11:49:50.577890 scan_bus: bus Root Device finished in 8 msecs
9268 11:49:50.578538 done
9269 11:49:50.584901 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9270 11:49:50.588041 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9271 11:49:50.594360 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9272 11:49:50.597951 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9273 11:49:50.601163 Allocating resources...
9274 11:49:50.604602 Reading resources...
9275 11:49:50.607914 Root Device read_resources bus 0 link: 0
9276 11:49:50.608376 DRAM rank0 size:0x100000000,
9277 11:49:50.611369 DRAM rank1 size=0x100000000
9278 11:49:50.614867 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9279 11:49:50.617644 CPU: 00 missing read_resources
9280 11:49:50.620878 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9281 11:49:50.628014 Root Device read_resources bus 0 link: 0 done
9282 11:49:50.628433 Done reading resources.
9283 11:49:50.634481 Show resources in subtree (Root Device)...After reading.
9284 11:49:50.637602 Root Device child on link 0 CPU_CLUSTER: 0
9285 11:49:50.641154 CPU_CLUSTER: 0 child on link 0 CPU: 00
9286 11:49:50.650965 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9287 11:49:50.651544 CPU: 00
9288 11:49:50.654427 Root Device assign_resources, bus 0 link: 0
9289 11:49:50.657692 CPU_CLUSTER: 0 missing set_resources
9290 11:49:50.664395 Root Device assign_resources, bus 0 link: 0 done
9291 11:49:50.664724 Done setting resources.
9292 11:49:50.670875 Show resources in subtree (Root Device)...After assigning values.
9293 11:49:50.673971 Root Device child on link 0 CPU_CLUSTER: 0
9294 11:49:50.677681 CPU_CLUSTER: 0 child on link 0 CPU: 00
9295 11:49:50.687102 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9296 11:49:50.687216 CPU: 00
9297 11:49:50.690963 Done allocating resources.
9298 11:49:50.693858 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9299 11:49:50.697381 Enabling resources...
9300 11:49:50.697481 done.
9301 11:49:50.703922 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9302 11:49:50.704024 Initializing devices...
9303 11:49:50.707642 Root Device init
9304 11:49:50.707752 init hardware done!
9305 11:49:50.710409 0x00000018: ctrlr->caps
9306 11:49:50.713933 52.000 MHz: ctrlr->f_max
9307 11:49:50.714037 0.400 MHz: ctrlr->f_min
9308 11:49:50.717167 0x40ff8080: ctrlr->voltages
9309 11:49:50.717270 sclk: 390625
9310 11:49:50.720672 Bus Width = 1
9311 11:49:50.720774 sclk: 390625
9312 11:49:50.720865 Bus Width = 1
9313 11:49:50.723932 Early init status = 3
9314 11:49:50.730419 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9315 11:49:50.733958 in-header: 03 fc 00 00 01 00 00 00
9316 11:49:50.737235 in-data: 00
9317 11:49:50.740672 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9318 11:49:50.745744 in-header: 03 fd 00 00 00 00 00 00
9319 11:49:50.749098 in-data:
9320 11:49:50.751622 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9321 11:49:50.756416 in-header: 03 fc 00 00 01 00 00 00
9322 11:49:50.759550 in-data: 00
9323 11:49:50.763335 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9324 11:49:50.768716 in-header: 03 fd 00 00 00 00 00 00
9325 11:49:50.772426 in-data:
9326 11:49:50.775280 [SSUSB] Setting up USB HOST controller...
9327 11:49:50.778363 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9328 11:49:50.781971 [SSUSB] phy power-on done.
9329 11:49:50.785369 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9330 11:49:50.791963 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9331 11:49:50.795002 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9332 11:49:50.801683 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9333 11:49:50.808228 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9334 11:49:50.815297 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9335 11:49:50.821719 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9336 11:49:50.828320 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9337 11:49:50.831786 SPM: binary array size = 0x9dc
9338 11:49:50.835154 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9339 11:49:50.841720 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9340 11:49:50.848102 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9341 11:49:50.851478 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9342 11:49:50.858197 configure_display: Starting display init
9343 11:49:50.891889 anx7625_power_on_init: Init interface.
9344 11:49:50.895182 anx7625_disable_pd_protocol: Disabled PD feature.
9345 11:49:50.898529 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9346 11:49:50.926365 anx7625_start_dp_work: Secure OCM version=00
9347 11:49:50.929569 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9348 11:49:50.944385 sp_tx_get_edid_block: EDID Block = 1
9349 11:49:51.046732 Extracted contents:
9350 11:49:51.050309 header: 00 ff ff ff ff ff ff 00
9351 11:49:51.053391 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9352 11:49:51.057173 version: 01 04
9353 11:49:51.060243 basic params: 95 1f 11 78 0a
9354 11:49:51.063414 chroma info: 76 90 94 55 54 90 27 21 50 54
9355 11:49:51.067003 established: 00 00 00
9356 11:49:51.073659 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9357 11:49:51.076985 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9358 11:49:51.083521 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9359 11:49:51.090345 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9360 11:49:51.096678 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9361 11:49:51.099795 extensions: 00
9362 11:49:51.099869 checksum: fb
9363 11:49:51.099933
9364 11:49:51.103362 Manufacturer: IVO Model 57d Serial Number 0
9365 11:49:51.106312 Made week 0 of 2020
9366 11:49:51.106412 EDID version: 1.4
9367 11:49:51.109975 Digital display
9368 11:49:51.113191 6 bits per primary color channel
9369 11:49:51.113295 DisplayPort interface
9370 11:49:51.116540 Maximum image size: 31 cm x 17 cm
9371 11:49:51.119724 Gamma: 220%
9372 11:49:51.119796 Check DPMS levels
9373 11:49:51.122936 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9374 11:49:51.129740 First detailed timing is preferred timing
9375 11:49:51.129840 Established timings supported:
9376 11:49:51.132785 Standard timings supported:
9377 11:49:51.136264 Detailed timings
9378 11:49:51.139689 Hex of detail: 383680a07038204018303c0035ae10000019
9379 11:49:51.142940 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9380 11:49:51.149740 0780 0798 07c8 0820 hborder 0
9381 11:49:51.152925 0438 043b 0447 0458 vborder 0
9382 11:49:51.156089 -hsync -vsync
9383 11:49:51.156184 Did detailed timing
9384 11:49:51.162544 Hex of detail: 000000000000000000000000000000000000
9385 11:49:51.166022 Manufacturer-specified data, tag 0
9386 11:49:51.169761 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9387 11:49:51.172585 ASCII string: InfoVision
9388 11:49:51.175643 Hex of detail: 000000fe00523134304e574635205248200a
9389 11:49:51.179178 ASCII string: R140NWF5 RH
9390 11:49:51.179251 Checksum
9391 11:49:51.182672 Checksum: 0xfb (valid)
9392 11:49:51.185755 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9393 11:49:51.189807 DSI data_rate: 832800000 bps
9394 11:49:51.195759 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9395 11:49:51.199029 anx7625_parse_edid: pixelclock(138800).
9396 11:49:51.202295 hactive(1920), hsync(48), hfp(24), hbp(88)
9397 11:49:51.205743 vactive(1080), vsync(12), vfp(3), vbp(17)
9398 11:49:51.209014 anx7625_dsi_config: config dsi.
9399 11:49:51.215572 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9400 11:49:51.229203 anx7625_dsi_config: success to config DSI
9401 11:49:51.232339 anx7625_dp_start: MIPI phy setup OK.
9402 11:49:51.235881 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9403 11:49:51.238984 mtk_ddp_mode_set invalid vrefresh 60
9404 11:49:51.242485 main_disp_path_setup
9405 11:49:51.242586 ovl_layer_smi_id_en
9406 11:49:51.245968 ovl_layer_smi_id_en
9407 11:49:51.246065 ccorr_config
9408 11:49:51.246153 aal_config
9409 11:49:51.249146 gamma_config
9410 11:49:51.249216 postmask_config
9411 11:49:51.252317 dither_config
9412 11:49:51.255472 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9413 11:49:51.262194 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9414 11:49:51.266018 Root Device init finished in 555 msecs
9415 11:49:51.266115 CPU_CLUSTER: 0 init
9416 11:49:51.275366 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9417 11:49:51.278951 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9418 11:49:51.282042 APU_MBOX 0x190000b0 = 0x10001
9419 11:49:51.285280 APU_MBOX 0x190001b0 = 0x10001
9420 11:49:51.288839 APU_MBOX 0x190005b0 = 0x10001
9421 11:49:51.292218 APU_MBOX 0x190006b0 = 0x10001
9422 11:49:51.295453 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9423 11:49:51.308101 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9424 11:49:51.320326 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9425 11:49:51.327090 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9426 11:49:51.338551 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9427 11:49:51.347772 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9428 11:49:51.351125 CPU_CLUSTER: 0 init finished in 81 msecs
9429 11:49:51.354474 Devices initialized
9430 11:49:51.357650 Show all devs... After init.
9431 11:49:51.357724 Root Device: enabled 1
9432 11:49:51.361009 CPU_CLUSTER: 0: enabled 1
9433 11:49:51.364218 CPU: 00: enabled 1
9434 11:49:51.367499 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9435 11:49:51.370878 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9436 11:49:51.374081 ELOG: NV offset 0x57f000 size 0x1000
9437 11:49:51.380750 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9438 11:49:51.387739 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9439 11:49:51.390960 ELOG: Event(17) added with size 13 at 2023-11-24 11:49:16 UTC
9440 11:49:51.397477 out: cmd=0x121: 03 db 21 01 00 00 00 00
9441 11:49:51.400528 in-header: 03 15 00 00 2c 00 00 00
9442 11:49:51.410435 in-data: 4a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9443 11:49:51.417314 ELOG: Event(A1) added with size 10 at 2023-11-24 11:49:16 UTC
9444 11:49:51.423623 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9445 11:49:51.430940 ELOG: Event(A0) added with size 9 at 2023-11-24 11:49:16 UTC
9446 11:49:51.433586 elog_add_boot_reason: Logged dev mode boot
9447 11:49:51.440418 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9448 11:49:51.440520 Finalize devices...
9449 11:49:51.443868 Devices finalized
9450 11:49:51.447202 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9451 11:49:51.450193 Writing coreboot table at 0xffe64000
9452 11:49:51.453748 0. 000000000010a000-0000000000113fff: RAMSTAGE
9453 11:49:51.457272 1. 0000000040000000-00000000400fffff: RAM
9454 11:49:51.463633 2. 0000000040100000-000000004032afff: RAMSTAGE
9455 11:49:51.466856 3. 000000004032b000-00000000545fffff: RAM
9456 11:49:51.470089 4. 0000000054600000-000000005465ffff: BL31
9457 11:49:51.473841 5. 0000000054660000-00000000ffe63fff: RAM
9458 11:49:51.480285 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9459 11:49:51.483628 7. 0000000100000000-000000023fffffff: RAM
9460 11:49:51.486951 Passing 5 GPIOs to payload:
9461 11:49:51.490133 NAME | PORT | POLARITY | VALUE
9462 11:49:51.496888 EC in RW | 0x000000aa | low | undefined
9463 11:49:51.499999 EC interrupt | 0x00000005 | low | undefined
9464 11:49:51.503508 TPM interrupt | 0x000000ab | high | undefined
9465 11:49:51.509896 SD card detect | 0x00000011 | high | undefined
9466 11:49:51.513248 speaker enable | 0x00000093 | high | undefined
9467 11:49:51.516610 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9468 11:49:51.519997 in-header: 03 f9 00 00 02 00 00 00
9469 11:49:51.523136 in-data: 02 00
9470 11:49:51.523237 ADC[4]: Raw value=901401 ID=7
9471 11:49:51.526572 ADC[3]: Raw value=213179 ID=1
9472 11:49:51.529781 RAM Code: 0x71
9473 11:49:51.529856 ADC[6]: Raw value=74502 ID=0
9474 11:49:51.533289 ADC[5]: Raw value=212072 ID=1
9475 11:49:51.536638 SKU Code: 0x1
9476 11:49:51.539766 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f943
9477 11:49:51.543015 coreboot table: 964 bytes.
9478 11:49:51.546619 IMD ROOT 0. 0xfffff000 0x00001000
9479 11:49:51.549836 IMD SMALL 1. 0xffffe000 0x00001000
9480 11:49:51.553006 RO MCACHE 2. 0xffffc000 0x00001104
9481 11:49:51.556462 CONSOLE 3. 0xfff7c000 0x00080000
9482 11:49:51.559956 FMAP 4. 0xfff7b000 0x00000452
9483 11:49:51.563367 TIME STAMP 5. 0xfff7a000 0x00000910
9484 11:49:51.566671 VBOOT WORK 6. 0xfff66000 0x00014000
9485 11:49:51.569821 RAMOOPS 7. 0xffe66000 0x00100000
9486 11:49:51.573241 COREBOOT 8. 0xffe64000 0x00002000
9487 11:49:51.573328 IMD small region:
9488 11:49:51.579826 IMD ROOT 0. 0xffffec00 0x00000400
9489 11:49:51.583093 VPD 1. 0xffffeb80 0x0000006c
9490 11:49:51.586623 MMC STATUS 2. 0xffffeb60 0x00000004
9491 11:49:51.589603 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9492 11:49:51.593095 Probing TPM: done!
9493 11:49:51.596807 Connected to device vid:did:rid of 1ae0:0028:00
9494 11:49:51.606815 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9495 11:49:51.610148 Initialized TPM device CR50 revision 0
9496 11:49:51.613643 Checking cr50 for pending updates
9497 11:49:51.617236 Reading cr50 TPM mode
9498 11:49:51.626315 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9499 11:49:51.632584 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9500 11:49:51.672649 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9501 11:49:51.675870 Checking segment from ROM address 0x40100000
9502 11:49:51.679755 Checking segment from ROM address 0x4010001c
9503 11:49:51.686078 Loading segment from ROM address 0x40100000
9504 11:49:51.686162 code (compression=0)
9505 11:49:51.693105 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9506 11:49:51.703268 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9507 11:49:51.703688 it's not compressed!
9508 11:49:51.710092 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9509 11:49:51.713089 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9510 11:49:51.733624 Loading segment from ROM address 0x4010001c
9511 11:49:51.734115 Entry Point 0x80000000
9512 11:49:51.737203 Loaded segments
9513 11:49:51.740463 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9514 11:49:51.746823 Jumping to boot code at 0x80000000(0xffe64000)
9515 11:49:51.753837 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9516 11:49:51.759811 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9517 11:49:51.767716 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9518 11:49:51.770919 Checking segment from ROM address 0x40100000
9519 11:49:51.774532 Checking segment from ROM address 0x4010001c
9520 11:49:51.780995 Loading segment from ROM address 0x40100000
9521 11:49:51.781099 code (compression=1)
9522 11:49:51.787701 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9523 11:49:51.797724 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9524 11:49:51.797810 using LZMA
9525 11:49:51.806080 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9526 11:49:51.812603 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9527 11:49:51.816218 Loading segment from ROM address 0x4010001c
9528 11:49:51.816316 Entry Point 0x54601000
9529 11:49:51.819425 Loaded segments
9530 11:49:51.822701 NOTICE: MT8192 bl31_setup
9531 11:49:51.830069 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9532 11:49:51.833170 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9533 11:49:51.836123 WARNING: region 0:
9534 11:49:51.839569 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 11:49:51.839642 WARNING: region 1:
9536 11:49:51.845938 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9537 11:49:51.849401 WARNING: region 2:
9538 11:49:51.852708 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9539 11:49:51.856174 WARNING: region 3:
9540 11:49:51.859668 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9541 11:49:51.863485 WARNING: region 4:
9542 11:49:51.869371 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9543 11:49:51.869469 WARNING: region 5:
9544 11:49:51.872987 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 11:49:51.876486 WARNING: region 6:
9546 11:49:51.879488 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 11:49:51.882800 WARNING: region 7:
9548 11:49:51.886182 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 11:49:51.892722 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9550 11:49:51.896079 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9551 11:49:51.899566 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9552 11:49:51.906153 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9553 11:49:51.909734 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9554 11:49:51.912716 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9555 11:49:51.919378 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9556 11:49:51.922878 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9557 11:49:51.929642 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9558 11:49:51.932946 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9559 11:49:51.936504 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9560 11:49:51.942901 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9561 11:49:51.946506 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9562 11:49:51.949839 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9563 11:49:51.956594 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9564 11:49:51.959886 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9565 11:49:51.963100 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9566 11:49:51.969910 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9567 11:49:51.973163 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9568 11:49:51.976500 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9569 11:49:51.983061 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9570 11:49:51.986378 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9571 11:49:51.993484 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9572 11:49:51.996590 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9573 11:49:51.999861 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9574 11:49:52.006646 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9575 11:49:52.010126 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9576 11:49:52.016711 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9577 11:49:52.020288 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9578 11:49:52.023482 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9579 11:49:52.029786 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9580 11:49:52.033558 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9581 11:49:52.036482 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9582 11:49:52.043863 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9583 11:49:52.047055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9584 11:49:52.050066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9585 11:49:52.053678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9586 11:49:52.060571 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9587 11:49:52.063271 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9588 11:49:52.066864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9589 11:49:52.070338 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9590 11:49:52.076794 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9591 11:49:52.079978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9592 11:49:52.083284 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9593 11:49:52.086943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9594 11:49:52.093240 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9595 11:49:52.096617 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9596 11:49:52.100353 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9597 11:49:52.106926 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9598 11:49:52.110232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9599 11:49:52.113570 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9600 11:49:52.120769 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9601 11:49:52.124209 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9602 11:49:52.130578 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9603 11:49:52.134204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9604 11:49:52.137398 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9605 11:49:52.144123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9606 11:49:52.147646 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9607 11:49:52.154164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9608 11:49:52.157603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9609 11:49:52.164170 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9610 11:49:52.167341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9611 11:49:52.170929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9612 11:49:52.177680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9613 11:49:52.181038 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9614 11:49:52.187509 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9615 11:49:52.190799 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9616 11:49:52.197346 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9617 11:49:52.200789 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9618 11:49:52.203941 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9619 11:49:52.210811 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9620 11:49:52.214754 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9621 11:49:52.220787 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9622 11:49:52.223712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9623 11:49:52.230273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9624 11:49:52.233987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9625 11:49:52.237119 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9626 11:49:52.244094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9627 11:49:52.247192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9628 11:49:52.253743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9629 11:49:52.257111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9630 11:49:52.263743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9631 11:49:52.267024 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9632 11:49:52.274129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9633 11:49:52.277070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9634 11:49:52.280693 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9635 11:49:52.287387 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9636 11:49:52.290813 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9637 11:49:52.297783 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9638 11:49:52.300760 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9639 11:49:52.304041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9640 11:49:52.310572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9641 11:49:52.313871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9642 11:49:52.320459 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9643 11:49:52.323903 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9644 11:49:52.330886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9645 11:49:52.333849 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9646 11:49:52.337318 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9647 11:49:52.340809 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9648 11:49:52.347664 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9649 11:49:52.350629 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9650 11:49:52.354283 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9651 11:49:52.360758 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9652 11:49:52.364332 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9653 11:49:52.371199 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9654 11:49:52.374147 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9655 11:49:52.377255 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9656 11:49:52.384323 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9657 11:49:52.387548 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9658 11:49:52.394564 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9659 11:49:52.397718 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9660 11:49:52.400887 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9661 11:49:52.407389 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9662 11:49:52.410676 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9663 11:49:52.417509 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9664 11:49:52.420787 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9665 11:49:52.424089 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9666 11:49:52.427509 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9667 11:49:52.434423 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9668 11:49:52.437435 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9669 11:49:52.441234 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9670 11:49:52.444516 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9671 11:49:52.451544 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9672 11:49:52.454525 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9673 11:49:52.458073 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9674 11:49:52.464850 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9675 11:49:52.467834 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9676 11:49:52.471151 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9677 11:49:52.477835 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9678 11:49:52.481621 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9679 11:49:52.488358 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9680 11:49:52.491994 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9681 11:49:52.494896 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9682 11:49:52.501617 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9683 11:49:52.504993 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9684 11:49:52.508305 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9685 11:49:52.514648 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9686 11:49:52.518106 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9687 11:49:52.524650 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9688 11:49:52.527916 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9689 11:49:52.531404 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9690 11:49:52.538201 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9691 11:49:52.541285 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9692 11:49:52.544588 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9693 11:49:52.551238 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9694 11:49:52.554836 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9695 11:49:52.561656 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9696 11:49:52.564475 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9697 11:49:52.568071 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9698 11:49:52.574441 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9699 11:49:52.577878 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9700 11:49:52.581487 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9701 11:49:52.588005 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9702 11:49:52.591384 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9703 11:49:52.598327 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9704 11:49:52.602121 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9705 11:49:52.604998 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9706 11:49:52.612244 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9707 11:49:52.615152 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9708 11:49:52.621608 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9709 11:49:52.625431 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9710 11:49:52.628788 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9711 11:49:52.635565 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9712 11:49:52.638646 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9713 11:49:52.642045 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9714 11:49:52.648826 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9715 11:49:52.651908 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9716 11:49:52.658674 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9717 11:49:52.661823 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9718 11:49:52.665107 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9719 11:49:52.671881 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9720 11:49:52.675176 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9721 11:49:52.682167 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9722 11:49:52.685053 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9723 11:49:52.688595 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9724 11:49:52.695172 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9725 11:49:52.698277 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9726 11:49:52.704729 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9727 11:49:52.707823 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9728 11:49:52.711758 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9729 11:49:52.717992 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9730 11:49:52.721355 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9731 11:49:52.728736 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9732 11:49:52.731743 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9733 11:49:52.734859 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9734 11:49:52.741173 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9735 11:49:52.744496 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9736 11:49:52.748156 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9737 11:49:52.754760 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9738 11:49:52.758006 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9739 11:49:52.764523 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9740 11:49:52.767812 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9741 11:49:52.774526 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9742 11:49:52.777941 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9743 11:49:52.780980 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9744 11:49:52.787676 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9745 11:49:52.790919 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9746 11:49:52.797559 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9747 11:49:52.800713 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9748 11:49:52.807455 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9749 11:49:52.811261 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9750 11:49:52.814138 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9751 11:49:52.820596 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9752 11:49:52.824148 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9753 11:49:52.830449 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9754 11:49:52.833936 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9755 11:49:52.840946 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9756 11:49:52.844628 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9757 11:49:52.847349 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9758 11:49:52.854029 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9759 11:49:52.857067 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9760 11:49:52.863906 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9761 11:49:52.867169 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9762 11:49:52.870704 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9763 11:49:52.877157 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9764 11:49:52.880271 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9765 11:49:52.887258 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9766 11:49:52.890328 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9767 11:49:52.897382 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9768 11:49:52.900650 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9769 11:49:52.904076 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9770 11:49:52.910498 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9771 11:49:52.913639 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9772 11:49:52.920711 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9773 11:49:52.923710 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9774 11:49:52.927072 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9775 11:49:52.933587 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9776 11:49:52.936909 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9777 11:49:52.943552 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9778 11:49:52.947064 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9779 11:49:52.950190 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9780 11:49:52.953600 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9781 11:49:52.956608 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9782 11:49:52.963473 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9783 11:49:52.966708 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9784 11:49:52.970287 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9785 11:49:52.976491 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9786 11:49:52.979892 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9787 11:49:52.986798 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9788 11:49:52.989893 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9789 11:49:52.993053 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9790 11:49:52.999883 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9791 11:49:53.003129 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9792 11:49:53.006331 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9793 11:49:53.013109 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9794 11:49:53.016518 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9795 11:49:53.023001 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9796 11:49:53.026370 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9797 11:49:53.029716 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9798 11:49:53.036219 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9799 11:49:53.039568 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9800 11:49:53.043214 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9801 11:49:53.049508 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9802 11:49:53.052795 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9803 11:49:53.056292 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9804 11:49:53.062920 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9805 11:49:53.066375 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9806 11:49:53.073286 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9807 11:49:53.076496 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9808 11:49:53.079785 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9809 11:49:53.086518 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9810 11:49:53.089741 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9811 11:49:53.093061 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9812 11:49:53.100270 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9813 11:49:53.103245 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9814 11:49:53.106911 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9815 11:49:53.113313 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9816 11:49:53.116973 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9817 11:49:53.119735 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9818 11:49:53.126274 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9819 11:49:53.129541 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9820 11:49:53.133101 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9821 11:49:53.136184 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9822 11:49:53.139586 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9823 11:49:53.146712 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9824 11:49:53.149701 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9825 11:49:53.153042 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9826 11:49:53.159656 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9827 11:49:53.163039 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9828 11:49:53.166295 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9829 11:49:53.169821 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9830 11:49:53.176591 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9831 11:49:53.179537 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9832 11:49:53.182971 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9833 11:49:53.189588 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9834 11:49:53.192543 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9835 11:49:53.199252 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9836 11:49:53.202646 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9837 11:49:53.209377 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9838 11:49:53.212581 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9839 11:49:53.215917 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9840 11:49:53.222831 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9841 11:49:53.225813 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9842 11:49:53.232187 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9843 11:49:53.235551 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9844 11:49:53.242997 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9845 11:49:53.245835 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9846 11:49:53.249378 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9847 11:49:53.255754 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9848 11:49:53.259079 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9849 11:49:53.265737 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9850 11:49:53.269112 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9851 11:49:53.272085 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9852 11:49:53.278834 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9853 11:49:53.281872 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9854 11:49:53.288396 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9855 11:49:53.291898 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9856 11:49:53.294972 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9857 11:49:53.302131 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9858 11:49:53.305645 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9859 11:49:53.311866 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9860 11:49:53.315024 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9861 11:49:53.321587 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9862 11:49:53.325202 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9863 11:49:53.328461 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9864 11:49:53.335166 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9865 11:49:53.338602 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9866 11:49:53.344861 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9867 11:49:53.348219 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9868 11:49:53.351974 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9869 11:49:53.358554 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9870 11:49:53.361852 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9871 11:49:53.368406 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9872 11:49:53.372057 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9873 11:49:53.374652 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9874 11:49:53.381520 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9875 11:49:53.384884 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9876 11:49:53.391841 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9877 11:49:53.394720 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9878 11:49:53.398413 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9879 11:49:53.405038 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9880 11:49:53.408112 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9881 11:49:53.414796 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9882 11:49:53.418145 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9883 11:49:53.421789 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9884 11:49:53.427984 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9885 11:49:53.431293 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9886 11:49:53.438150 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9887 11:49:53.441815 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9888 11:49:53.445001 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9889 11:49:53.451876 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9890 11:49:53.455173 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9891 11:49:53.461680 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9892 11:49:53.465063 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9893 11:49:53.471305 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9894 11:49:53.474616 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9895 11:49:53.477831 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9896 11:49:53.484953 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9897 11:49:53.488073 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9898 11:49:53.494544 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9899 11:49:53.497940 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9900 11:49:53.500990 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9901 11:49:53.507572 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9902 11:49:53.511573 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9903 11:49:53.518177 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9904 11:49:53.521425 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9905 11:49:53.524730 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9906 11:49:53.531024 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9907 11:49:53.534690 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9908 11:49:53.541076 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9909 11:49:53.544327 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9910 11:49:53.551254 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9911 11:49:53.554530 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9912 11:49:53.557893 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9913 11:49:53.564416 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9914 11:49:53.567552 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9915 11:49:53.574555 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9916 11:49:53.577683 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9917 11:49:53.584167 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9918 11:49:53.587421 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9919 11:49:53.594099 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9920 11:49:53.597267 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9921 11:49:53.600737 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9922 11:49:53.607428 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9923 11:49:53.610981 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9924 11:49:53.617426 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9925 11:49:53.620609 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9926 11:49:53.627126 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9927 11:49:53.630678 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9928 11:49:53.634141 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9929 11:49:53.640959 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9930 11:49:53.643980 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9931 11:49:53.650586 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9932 11:49:53.654536 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9933 11:49:53.660805 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9934 11:49:53.663611 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9935 11:49:53.670055 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9936 11:49:53.673390 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9937 11:49:53.676751 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9938 11:49:53.683917 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9939 11:49:53.686886 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9940 11:49:53.693548 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9941 11:49:53.696828 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9942 11:49:53.703621 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9943 11:49:53.706571 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9944 11:49:53.710523 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9945 11:49:53.716518 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9946 11:49:53.720047 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9947 11:49:53.726274 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9948 11:49:53.729856 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9949 11:49:53.736664 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9950 11:49:53.739457 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9951 11:49:53.743389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9952 11:49:53.749640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9953 11:49:53.752982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9954 11:49:53.760186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9955 11:49:53.763159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9956 11:49:53.769965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9957 11:49:53.773553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9958 11:49:53.779719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9959 11:49:53.782926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9960 11:49:53.789437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9961 11:49:53.793029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9962 11:49:53.799351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9963 11:49:53.802850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9964 11:49:53.809197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9965 11:49:53.812785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9966 11:49:53.816390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9967 11:49:53.822350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9968 11:49:53.825951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9969 11:49:53.832735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9970 11:49:53.835920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9971 11:49:53.842672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9972 11:49:53.845864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9973 11:49:53.852468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9974 11:49:53.855978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9975 11:49:53.862359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9976 11:49:53.865581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9977 11:49:53.872516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9978 11:49:53.879411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9979 11:49:53.882275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9980 11:49:53.888918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9981 11:49:53.892058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9982 11:49:53.899225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9983 11:49:53.902195 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9984 11:49:53.902368 INFO: [APUAPC] vio 0
9985 11:49:53.910217 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9986 11:49:53.913293 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9987 11:49:53.916351 INFO: [APUAPC] D0_APC_0: 0x400510
9988 11:49:53.919564 INFO: [APUAPC] D0_APC_1: 0x0
9989 11:49:53.922887 INFO: [APUAPC] D0_APC_2: 0x1540
9990 11:49:53.926446 INFO: [APUAPC] D0_APC_3: 0x0
9991 11:49:53.930129 INFO: [APUAPC] D1_APC_0: 0xffffffff
9992 11:49:53.933021 INFO: [APUAPC] D1_APC_1: 0xffffffff
9993 11:49:53.936565 INFO: [APUAPC] D1_APC_2: 0x3fffff
9994 11:49:53.939987 INFO: [APUAPC] D1_APC_3: 0x0
9995 11:49:53.943452 INFO: [APUAPC] D2_APC_0: 0xffffffff
9996 11:49:53.946350 INFO: [APUAPC] D2_APC_1: 0xffffffff
9997 11:49:53.950214 INFO: [APUAPC] D2_APC_2: 0x3fffff
9998 11:49:53.953115 INFO: [APUAPC] D2_APC_3: 0x0
9999 11:49:53.956416 INFO: [APUAPC] D3_APC_0: 0xffffffff
10000 11:49:53.959655 INFO: [APUAPC] D3_APC_1: 0xffffffff
10001 11:49:53.963362 INFO: [APUAPC] D3_APC_2: 0x3fffff
10002 11:49:53.963853 INFO: [APUAPC] D3_APC_3: 0x0
10003 11:49:53.966561 INFO: [APUAPC] D4_APC_0: 0xffffffff
10004 11:49:53.973492 INFO: [APUAPC] D4_APC_1: 0xffffffff
10005 11:49:53.976683 INFO: [APUAPC] D4_APC_2: 0x3fffff
10006 11:49:53.977248 INFO: [APUAPC] D4_APC_3: 0x0
10007 11:49:53.979488 INFO: [APUAPC] D5_APC_0: 0xffffffff
10008 11:49:53.982958 INFO: [APUAPC] D5_APC_1: 0xffffffff
10009 11:49:53.986266 INFO: [APUAPC] D5_APC_2: 0x3fffff
10010 11:49:53.990304 INFO: [APUAPC] D5_APC_3: 0x0
10011 11:49:53.993044 INFO: [APUAPC] D6_APC_0: 0xffffffff
10012 11:49:53.996592 INFO: [APUAPC] D6_APC_1: 0xffffffff
10013 11:49:53.999599 INFO: [APUAPC] D6_APC_2: 0x3fffff
10014 11:49:54.002874 INFO: [APUAPC] D6_APC_3: 0x0
10015 11:49:54.006063 INFO: [APUAPC] D7_APC_0: 0xffffffff
10016 11:49:54.009389 INFO: [APUAPC] D7_APC_1: 0xffffffff
10017 11:49:54.012704 INFO: [APUAPC] D7_APC_2: 0x3fffff
10018 11:49:54.016128 INFO: [APUAPC] D7_APC_3: 0x0
10019 11:49:54.019817 INFO: [APUAPC] D8_APC_0: 0xffffffff
10020 11:49:54.023537 INFO: [APUAPC] D8_APC_1: 0xffffffff
10021 11:49:54.026026 INFO: [APUAPC] D8_APC_2: 0x3fffff
10022 11:49:54.029839 INFO: [APUAPC] D8_APC_3: 0x0
10023 11:49:54.032821 INFO: [APUAPC] D9_APC_0: 0xffffffff
10024 11:49:54.036635 INFO: [APUAPC] D9_APC_1: 0xffffffff
10025 11:49:54.039352 INFO: [APUAPC] D9_APC_2: 0x3fffff
10026 11:49:54.043355 INFO: [APUAPC] D9_APC_3: 0x0
10027 11:49:54.046135 INFO: [APUAPC] D10_APC_0: 0xffffffff
10028 11:49:54.049340 INFO: [APUAPC] D10_APC_1: 0xffffffff
10029 11:49:54.052872 INFO: [APUAPC] D10_APC_2: 0x3fffff
10030 11:49:54.055876 INFO: [APUAPC] D10_APC_3: 0x0
10031 11:49:54.059391 INFO: [APUAPC] D11_APC_0: 0xffffffff
10032 11:49:54.062805 INFO: [APUAPC] D11_APC_1: 0xffffffff
10033 11:49:54.066045 INFO: [APUAPC] D11_APC_2: 0x3fffff
10034 11:49:54.069555 INFO: [APUAPC] D11_APC_3: 0x0
10035 11:49:54.072693 INFO: [APUAPC] D12_APC_0: 0xffffffff
10036 11:49:54.075906 INFO: [APUAPC] D12_APC_1: 0xffffffff
10037 11:49:54.079581 INFO: [APUAPC] D12_APC_2: 0x3fffff
10038 11:49:54.082362 INFO: [APUAPC] D12_APC_3: 0x0
10039 11:49:54.085906 INFO: [APUAPC] D13_APC_0: 0xffffffff
10040 11:49:54.089289 INFO: [APUAPC] D13_APC_1: 0xffffffff
10041 11:49:54.092527 INFO: [APUAPC] D13_APC_2: 0x3fffff
10042 11:49:54.095708 INFO: [APUAPC] D13_APC_3: 0x0
10043 11:49:54.099263 INFO: [APUAPC] D14_APC_0: 0xffffffff
10044 11:49:54.102565 INFO: [APUAPC] D14_APC_1: 0xffffffff
10045 11:49:54.105749 INFO: [APUAPC] D14_APC_2: 0x3fffff
10046 11:49:54.108873 INFO: [APUAPC] D14_APC_3: 0x0
10047 11:49:54.112243 INFO: [APUAPC] D15_APC_0: 0xffffffff
10048 11:49:54.115755 INFO: [APUAPC] D15_APC_1: 0xffffffff
10049 11:49:54.118873 INFO: [APUAPC] D15_APC_2: 0x3fffff
10050 11:49:54.122500 INFO: [APUAPC] D15_APC_3: 0x0
10051 11:49:54.126091 INFO: [APUAPC] APC_CON: 0x4
10052 11:49:54.128943 INFO: [NOCDAPC] D0_APC_0: 0x0
10053 11:49:54.132553 INFO: [NOCDAPC] D0_APC_1: 0x0
10054 11:49:54.135744 INFO: [NOCDAPC] D1_APC_0: 0x0
10055 11:49:54.136169 INFO: [NOCDAPC] D1_APC_1: 0xfff
10056 11:49:54.139052 INFO: [NOCDAPC] D2_APC_0: 0x0
10057 11:49:54.142266 INFO: [NOCDAPC] D2_APC_1: 0xfff
10058 11:49:54.145812 INFO: [NOCDAPC] D3_APC_0: 0x0
10059 11:49:54.149249 INFO: [NOCDAPC] D3_APC_1: 0xfff
10060 11:49:54.152557 INFO: [NOCDAPC] D4_APC_0: 0x0
10061 11:49:54.155804 INFO: [NOCDAPC] D4_APC_1: 0xfff
10062 11:49:54.158978 INFO: [NOCDAPC] D5_APC_0: 0x0
10063 11:49:54.162775 INFO: [NOCDAPC] D5_APC_1: 0xfff
10064 11:49:54.165719 INFO: [NOCDAPC] D6_APC_0: 0x0
10065 11:49:54.169121 INFO: [NOCDAPC] D6_APC_1: 0xfff
10066 11:49:54.169624 INFO: [NOCDAPC] D7_APC_0: 0x0
10067 11:49:54.172335 INFO: [NOCDAPC] D7_APC_1: 0xfff
10068 11:49:54.175539 INFO: [NOCDAPC] D8_APC_0: 0x0
10069 11:49:54.178892 INFO: [NOCDAPC] D8_APC_1: 0xfff
10070 11:49:54.182365 INFO: [NOCDAPC] D9_APC_0: 0x0
10071 11:49:54.185465 INFO: [NOCDAPC] D9_APC_1: 0xfff
10072 11:49:54.188929 INFO: [NOCDAPC] D10_APC_0: 0x0
10073 11:49:54.192227 INFO: [NOCDAPC] D10_APC_1: 0xfff
10074 11:49:54.195139 INFO: [NOCDAPC] D11_APC_0: 0x0
10075 11:49:54.198686 INFO: [NOCDAPC] D11_APC_1: 0xfff
10076 11:49:54.201898 INFO: [NOCDAPC] D12_APC_0: 0x0
10077 11:49:54.205717 INFO: [NOCDAPC] D12_APC_1: 0xfff
10078 11:49:54.208649 INFO: [NOCDAPC] D13_APC_0: 0x0
10079 11:49:54.208754 INFO: [NOCDAPC] D13_APC_1: 0xfff
10080 11:49:54.212242 INFO: [NOCDAPC] D14_APC_0: 0x0
10081 11:49:54.215430 INFO: [NOCDAPC] D14_APC_1: 0xfff
10082 11:49:54.219046 INFO: [NOCDAPC] D15_APC_0: 0x0
10083 11:49:54.222114 INFO: [NOCDAPC] D15_APC_1: 0xfff
10084 11:49:54.225933 INFO: [NOCDAPC] APC_CON: 0x4
10085 11:49:54.229019 INFO: [APUAPC] set_apusys_apc done
10086 11:49:54.232210 INFO: [DEVAPC] devapc_init done
10087 11:49:54.236056 INFO: GICv3 without legacy support detected.
10088 11:49:54.239060 INFO: ARM GICv3 driver initialized in EL3
10089 11:49:54.245290 INFO: Maximum SPI INTID supported: 639
10090 11:49:54.248530 INFO: BL31: Initializing runtime services
10091 11:49:54.254987 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10092 11:49:54.255068 INFO: SPM: enable CPC mode
10093 11:49:54.262168 INFO: mcdi ready for mcusys-off-idle and system suspend
10094 11:49:54.265150 INFO: BL31: Preparing for EL3 exit to normal world
10095 11:49:54.268703 INFO: Entry point address = 0x80000000
10096 11:49:54.271912 INFO: SPSR = 0x8
10097 11:49:54.277503
10098 11:49:54.277614
10099 11:49:54.277708
10100 11:49:54.280810 Starting depthcharge on Spherion...
10101 11:49:54.280892
10102 11:49:54.280957 Wipe memory regions:
10103 11:49:54.281017
10104 11:49:54.281685 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10105 11:49:54.281787 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10106 11:49:54.281874 Setting prompt string to ['asurada:']
10107 11:49:54.281956 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10108 11:49:54.283905 [0x00000040000000, 0x00000054600000)
10109 11:49:54.406679
10110 11:49:54.407292 [0x00000054660000, 0x00000080000000)
10111 11:49:54.666890
10112 11:49:54.667447 [0x000000821a7280, 0x000000ffe64000)
10113 11:49:55.410803
10114 11:49:55.411366 [0x00000100000000, 0x00000240000000)
10115 11:49:57.297525
10116 11:49:57.300554 Initializing XHCI USB controller at 0x11200000.
10117 11:49:58.338088
10118 11:49:58.341957 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10119 11:49:58.342571
10120 11:49:58.342989
10121 11:49:58.343404
10122 11:49:58.344216 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10124 11:49:58.445555 asurada: tftpboot 192.168.201.1 12074061/tftp-deploy-vlhdt09n/kernel/image.itb 12074061/tftp-deploy-vlhdt09n/kernel/cmdline
10125 11:49:58.446317 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10126 11:49:58.447039 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10127 11:49:58.451086 tftpboot 192.168.201.1 12074061/tftp-deploy-vlhdt09n/kernel/image.ittp-deploy-vlhdt09n/kernel/cmdline
10128 11:49:58.451564
10129 11:49:58.451932 Waiting for link
10130 11:49:58.611941
10131 11:49:58.612510 R8152: Initializing
10132 11:49:58.612887
10133 11:49:58.614925 Version 9 (ocp_data = 6010)
10134 11:49:58.615392
10135 11:49:58.618373 R8152: Done initializing
10136 11:49:58.619032
10137 11:49:58.619413 Adding net device
10138 11:50:00.559853
10139 11:50:00.560427 done.
10140 11:50:00.560802
10141 11:50:00.561145 MAC: 00:e0:4c:72:2d:d6
10142 11:50:00.561478
10143 11:50:00.563054 Sending DHCP discover... done.
10144 11:50:00.563523
10145 11:50:00.566084 Waiting for reply... done.
10146 11:50:00.566701
10147 11:50:00.569957 Sending DHCP request... done.
10148 11:50:00.570576
10149 11:50:00.572865 Waiting for reply... done.
10150 11:50:00.573439
10151 11:50:00.573814 My ip is 192.168.201.21
10152 11:50:00.574164
10153 11:50:00.576298 The DHCP server ip is 192.168.201.1
10154 11:50:00.576879
10155 11:50:00.579824 TFTP server IP predefined by user: 192.168.201.1
10156 11:50:00.582922
10157 11:50:00.586071 Bootfile predefined by user: 12074061/tftp-deploy-vlhdt09n/kernel/image.itb
10158 11:50:00.589447
10159 11:50:00.589912 Sending tftp read request... done.
10160 11:50:00.590284
10161 11:50:00.596876 Waiting for the transfer...
10162 11:50:00.597450
10163 11:50:00.890866 00000000 ################################################################
10164 11:50:00.891009
10165 11:50:01.144524 00080000 ################################################################
10166 11:50:01.144662
10167 11:50:01.416628 00100000 ################################################################
10168 11:50:01.416765
10169 11:50:01.696486 00180000 ################################################################
10170 11:50:01.696625
10171 11:50:01.968970 00200000 ################################################################
10172 11:50:01.969123
10173 11:50:02.262440 00280000 ################################################################
10174 11:50:02.262583
10175 11:50:02.553917 00300000 ################################################################
10176 11:50:02.554081
10177 11:50:02.853641 00380000 ################################################################
10178 11:50:02.853789
10179 11:50:03.110215 00400000 ################################################################
10180 11:50:03.110395
10181 11:50:03.385444 00480000 ################################################################
10182 11:50:03.385587
10183 11:50:03.662890 00500000 ################################################################
10184 11:50:03.663064
10185 11:50:03.906709 00580000 ################################################################
10186 11:50:03.906859
10187 11:50:04.151413 00600000 ################################################################
10188 11:50:04.151564
10189 11:50:04.397122 00680000 ################################################################
10190 11:50:04.397272
10191 11:50:04.640656 00700000 ################################################################
10192 11:50:04.640811
10193 11:50:04.884647 00780000 ################################################################
10194 11:50:04.884797
10195 11:50:05.127365 00800000 ################################################################
10196 11:50:05.127514
10197 11:50:05.370279 00880000 ################################################################
10198 11:50:05.370496
10199 11:50:05.614154 00900000 ################################################################
10200 11:50:05.614333
10201 11:50:05.857524 00980000 ################################################################
10202 11:50:05.857680
10203 11:50:06.099817 00a00000 ################################################################
10204 11:50:06.100001
10205 11:50:06.343793 00a80000 ################################################################
10206 11:50:06.343947
10207 11:50:06.586999 00b00000 ################################################################
10208 11:50:06.587180
10209 11:50:06.831001 00b80000 ################################################################
10210 11:50:06.831153
10211 11:50:07.074973 00c00000 ################################################################
10212 11:50:07.075121
10213 11:50:07.320882 00c80000 ################################################################
10214 11:50:07.321030
10215 11:50:07.565927 00d00000 ################################################################
10216 11:50:07.566080
10217 11:50:07.810121 00d80000 ################################################################
10218 11:50:07.810283
10219 11:50:08.054464 00e00000 ################################################################
10220 11:50:08.054610
10221 11:50:08.298471 00e80000 ################################################################
10222 11:50:08.298622
10223 11:50:08.542908 00f00000 ################################################################
10224 11:50:08.543060
10225 11:50:08.787882 00f80000 ################################################################
10226 11:50:08.788033
10227 11:50:09.033056 01000000 ################################################################
10228 11:50:09.033233
10229 11:50:09.277118 01080000 ################################################################
10230 11:50:09.277275
10231 11:50:09.522100 01100000 ################################################################
10232 11:50:09.522294
10233 11:50:09.768156 01180000 ################################################################
10234 11:50:09.768346
10235 11:50:10.013277 01200000 ################################################################
10236 11:50:10.013421
10237 11:50:10.257308 01280000 ################################################################
10238 11:50:10.257461
10239 11:50:10.501145 01300000 ################################################################
10240 11:50:10.501297
10241 11:50:10.744550 01380000 ################################################################
10242 11:50:10.744705
10243 11:50:10.987622 01400000 ################################################################
10244 11:50:10.987774
10245 11:50:11.231322 01480000 ################################################################
10246 11:50:11.231473
10247 11:50:11.475512 01500000 ################################################################
10248 11:50:11.475665
10249 11:50:11.722218 01580000 ################################################################
10250 11:50:11.722396
10251 11:50:11.966169 01600000 ################################################################
10252 11:50:11.966319
10253 11:50:12.210223 01680000 ################################################################
10254 11:50:12.210376
10255 11:50:12.453974 01700000 ################################################################
10256 11:50:12.454122
10257 11:50:12.697713 01780000 ################################################################
10258 11:50:12.697864
10259 11:50:12.940692 01800000 ################################################################
10260 11:50:12.940846
10261 11:50:13.185584 01880000 ################################################################
10262 11:50:13.185737
10263 11:50:13.430320 01900000 ################################################################
10264 11:50:13.430486
10265 11:50:13.674332 01980000 ################################################################
10266 11:50:13.674544
10267 11:50:13.918256 01a00000 ################################################################
10268 11:50:13.918416
10269 11:50:14.162408 01a80000 ################################################################
10270 11:50:14.162570
10271 11:50:14.412620 01b00000 ################################################################
10272 11:50:14.412772
10273 11:50:14.673710 01b80000 ################################################################
10274 11:50:14.673862
10275 11:50:14.901181 01c00000 ############################################################# done.
10276 11:50:14.904355
10277 11:50:14.904459 The bootfile was 29857562 bytes long.
10278 11:50:14.907424
10279 11:50:14.907511 Sending tftp read request... done.
10280 11:50:14.907579
10281 11:50:14.911011 Waiting for the transfer...
10282 11:50:14.911097
10283 11:50:14.914285 00000000 # done.
10284 11:50:14.914405
10285 11:50:14.921055 Command line loaded dynamically from TFTP file: 12074061/tftp-deploy-vlhdt09n/kernel/cmdline
10286 11:50:14.921142
10287 11:50:14.944113 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12074061/extract-nfsrootfs-mw13pg1y,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10288 11:50:14.944209
10289 11:50:14.944277 Loading FIT.
10290 11:50:14.944341
10291 11:50:14.947353 Image ramdisk-1 has 18760003 bytes.
10292 11:50:14.947439
10293 11:50:14.950637 Image fdt-1 has 47278 bytes.
10294 11:50:14.950751
10295 11:50:14.953979 Image kernel-1 has 11048246 bytes.
10296 11:50:14.954065
10297 11:50:14.960677 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10298 11:50:14.960763
10299 11:50:14.980768 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10300 11:50:14.980859
10301 11:50:14.984043 Choosing best match conf-1 for compat google,spherion-rev2.
10302 11:50:14.989221
10303 11:50:14.993815 Connected to device vid:did:rid of 1ae0:0028:00
10304 11:50:15.001922
10305 11:50:15.005224 tpm_get_response: command 0x17b, return code 0x0
10306 11:50:15.005308
10307 11:50:15.008590 ec_init: CrosEC protocol v3 supported (256, 248)
10308 11:50:15.012545
10309 11:50:15.016660 tpm_cleanup: add release locality here.
10310 11:50:15.016744
10311 11:50:15.016810 Shutting down all USB controllers.
10312 11:50:15.016872
10313 11:50:15.019705 Removing current net device
10314 11:50:15.019789
10315 11:50:15.026305 Exiting depthcharge with code 4 at timestamp: 50076858
10316 11:50:15.026447
10317 11:50:15.029424 LZMA decompressing kernel-1 to 0x821a6718
10318 11:50:15.029510
10319 11:50:15.032474 LZMA decompressing kernel-1 to 0x40000000
10320 11:50:16.422698
10321 11:50:16.423257 jumping to kernel
10322 11:50:16.424989 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10323 11:50:16.425556 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10324 11:50:16.425971 Setting prompt string to ['Linux version [0-9]']
10325 11:50:16.426351 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10326 11:50:16.426771 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10327 11:50:16.503598
10328 11:50:16.507325 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10329 11:50:16.510660 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10330 11:50:16.511254 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10331 11:50:16.511657 Setting prompt string to []
10332 11:50:16.512072 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10333 11:50:16.512470 Using line separator: #'\n'#
10334 11:50:16.512805 No login prompt set.
10335 11:50:16.513216 Parsing kernel messages
10336 11:50:16.513563 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10337 11:50:16.514139 [login-action] Waiting for messages, (timeout 00:04:03)
10338 11:50:16.530102 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10339 11:50:16.533674 [ 0.000000] random: crng init done
10340 11:50:16.540214 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10341 11:50:16.540785 [ 0.000000] efi: UEFI not found.
10342 11:50:16.549803 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10343 11:50:16.556252 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10344 11:50:16.566531 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10345 11:50:16.576179 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10346 11:50:16.583122 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10347 11:50:16.586638 [ 0.000000] printk: bootconsole [mtk8250] enabled
10348 11:50:16.595274 [ 0.000000] NUMA: No NUMA configuration found
10349 11:50:16.601828 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10350 11:50:16.609086 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10351 11:50:16.609652 [ 0.000000] Zone ranges:
10352 11:50:16.615265 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10353 11:50:16.618755 [ 0.000000] DMA32 empty
10354 11:50:16.625194 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10355 11:50:16.628564 [ 0.000000] Movable zone start for each node
10356 11:50:16.632168 [ 0.000000] Early memory node ranges
10357 11:50:16.639100 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10358 11:50:16.645418 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10359 11:50:16.651952 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10360 11:50:16.658230 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10361 11:50:16.664798 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10362 11:50:16.671427 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10363 11:50:16.727698 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10364 11:50:16.734833 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10365 11:50:16.741196 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10366 11:50:16.744673 [ 0.000000] psci: probing for conduit method from DT.
10367 11:50:16.751217 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10368 11:50:16.754721 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10369 11:50:16.761044 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10370 11:50:16.764474 [ 0.000000] psci: SMC Calling Convention v1.2
10371 11:50:16.771141 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10372 11:50:16.774086 [ 0.000000] Detected VIPT I-cache on CPU0
10373 11:50:16.780903 [ 0.000000] CPU features: detected: GIC system register CPU interface
10374 11:50:16.787828 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10375 11:50:16.794464 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10376 11:50:16.801670 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10377 11:50:16.808132 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10378 11:50:16.814476 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10379 11:50:16.821258 [ 0.000000] alternatives: applying boot alternatives
10380 11:50:16.824751 [ 0.000000] Fallback order for Node 0: 0
10381 11:50:16.834632 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10382 11:50:16.835199 [ 0.000000] Policy zone: Normal
10383 11:50:16.857489 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12074061/extract-nfsrootfs-mw13pg1y,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10384 11:50:16.870649 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10385 11:50:16.880200 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10386 11:50:16.890133 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10387 11:50:16.896972 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10388 11:50:16.900494 <6>[ 0.000000] software IO TLB: area num 8.
10389 11:50:16.957216 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10390 11:50:17.106322 <6>[ 0.000000] Memory: 7951300K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 401468K reserved, 32768K cma-reserved)
10391 11:50:17.112472 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10392 11:50:17.119326 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10393 11:50:17.122642 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10394 11:50:17.129515 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10395 11:50:17.136906 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10396 11:50:17.139582 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10397 11:50:17.148763 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10398 11:50:17.155701 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10399 11:50:17.162319 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10400 11:50:17.168757 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10401 11:50:17.172456 <6>[ 0.000000] GICv3: 608 SPIs implemented
10402 11:50:17.175108 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10403 11:50:17.181687 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10404 11:50:17.185079 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10405 11:50:17.191852 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10406 11:50:17.205192 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10407 11:50:17.218157 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10408 11:50:17.224791 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10409 11:50:17.232422 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10410 11:50:17.245799 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10411 11:50:17.252191 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10412 11:50:17.259234 <6>[ 0.009234] Console: colour dummy device 80x25
10413 11:50:17.269510 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10414 11:50:17.275653 <6>[ 0.024401] pid_max: default: 32768 minimum: 301
10415 11:50:17.279306 <6>[ 0.029304] LSM: Security Framework initializing
10416 11:50:17.286050 <6>[ 0.034241] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10417 11:50:17.295631 <6>[ 0.042055] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10418 11:50:17.302030 <6>[ 0.051461] cblist_init_generic: Setting adjustable number of callback queues.
10419 11:50:17.308698 <6>[ 0.058949] cblist_init_generic: Setting shift to 3 and lim to 1.
10420 11:50:17.318707 <6>[ 0.065327] cblist_init_generic: Setting adjustable number of callback queues.
10421 11:50:17.325207 <6>[ 0.072753] cblist_init_generic: Setting shift to 3 and lim to 1.
10422 11:50:17.328840 <6>[ 0.079152] rcu: Hierarchical SRCU implementation.
10423 11:50:17.335346 <6>[ 0.084199] rcu: Max phase no-delay instances is 1000.
10424 11:50:17.342059 <6>[ 0.091221] EFI services will not be available.
10425 11:50:17.345145 <6>[ 0.096177] smp: Bringing up secondary CPUs ...
10426 11:50:17.353160 <6>[ 0.101223] Detected VIPT I-cache on CPU1
10427 11:50:17.360278 <6>[ 0.101293] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10428 11:50:17.367019 <6>[ 0.101325] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10429 11:50:17.370128 <6>[ 0.101658] Detected VIPT I-cache on CPU2
10430 11:50:17.376738 <6>[ 0.101708] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10431 11:50:17.383466 <6>[ 0.101725] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10432 11:50:17.390344 <6>[ 0.101986] Detected VIPT I-cache on CPU3
10433 11:50:17.396726 <6>[ 0.102032] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10434 11:50:17.403214 <6>[ 0.102046] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10435 11:50:17.406369 <6>[ 0.102349] CPU features: detected: Spectre-v4
10436 11:50:17.413350 <6>[ 0.102356] CPU features: detected: Spectre-BHB
10437 11:50:17.416626 <6>[ 0.102361] Detected PIPT I-cache on CPU4
10438 11:50:17.423013 <6>[ 0.102418] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10439 11:50:17.429707 <6>[ 0.102435] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10440 11:50:17.436360 <6>[ 0.102716] Detected PIPT I-cache on CPU5
10441 11:50:17.443275 <6>[ 0.102772] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10442 11:50:17.449700 <6>[ 0.102788] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10443 11:50:17.452792 <6>[ 0.103061] Detected PIPT I-cache on CPU6
10444 11:50:17.459586 <6>[ 0.103126] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10445 11:50:17.466342 <6>[ 0.103142] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10446 11:50:17.472939 <6>[ 0.103437] Detected PIPT I-cache on CPU7
10447 11:50:17.479704 <6>[ 0.103501] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10448 11:50:17.486561 <6>[ 0.103517] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10449 11:50:17.489618 <6>[ 0.103564] smp: Brought up 1 node, 8 CPUs
10450 11:50:17.496622 <6>[ 0.244917] SMP: Total of 8 processors activated.
10451 11:50:17.499062 <6>[ 0.249838] CPU features: detected: 32-bit EL0 Support
10452 11:50:17.509274 <6>[ 0.255233] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10453 11:50:17.516415 <6>[ 0.264034] CPU features: detected: Common not Private translations
10454 11:50:17.519007 <6>[ 0.270509] CPU features: detected: CRC32 instructions
10455 11:50:17.525736 <6>[ 0.275860] CPU features: detected: RCpc load-acquire (LDAPR)
10456 11:50:17.532445 <6>[ 0.281857] CPU features: detected: LSE atomic instructions
10457 11:50:17.538922 <6>[ 0.287638] CPU features: detected: Privileged Access Never
10458 11:50:17.542123 <6>[ 0.293454] CPU features: detected: RAS Extension Support
10459 11:50:17.552155 <6>[ 0.299063] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10460 11:50:17.555479 <6>[ 0.306287] CPU: All CPU(s) started at EL2
10461 11:50:17.562191 <6>[ 0.310603] alternatives: applying system-wide alternatives
10462 11:50:17.571002 <6>[ 0.321306] devtmpfs: initialized
10463 11:50:17.583212 <6>[ 0.330292] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10464 11:50:17.593381 <6>[ 0.340255] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10465 11:50:17.599943 <6>[ 0.348322] pinctrl core: initialized pinctrl subsystem
10466 11:50:17.603719 <6>[ 0.354989] DMI not present or invalid.
10467 11:50:17.609955 <6>[ 0.359399] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10468 11:50:17.619997 <6>[ 0.366269] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10469 11:50:17.626600 <6>[ 0.373851] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10470 11:50:17.636245 <6>[ 0.382068] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10471 11:50:17.639616 <6>[ 0.390311] audit: initializing netlink subsys (disabled)
10472 11:50:17.649200 <5>[ 0.396002] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10473 11:50:17.655972 <6>[ 0.396707] thermal_sys: Registered thermal governor 'step_wise'
10474 11:50:17.662981 <6>[ 0.403969] thermal_sys: Registered thermal governor 'power_allocator'
10475 11:50:17.665960 <6>[ 0.410223] cpuidle: using governor menu
10476 11:50:17.672647 <6>[ 0.421178] NET: Registered PF_QIPCRTR protocol family
10477 11:50:17.679194 <6>[ 0.426673] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10478 11:50:17.685998 <6>[ 0.433774] ASID allocator initialised with 32768 entries
10479 11:50:17.689137 <6>[ 0.440337] Serial: AMBA PL011 UART driver
10480 11:50:17.699066 <4>[ 0.449127] Trying to register duplicate clock ID: 134
10481 11:50:17.753034 <6>[ 0.506701] KASLR enabled
10482 11:50:17.767687 <6>[ 0.514408] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10483 11:50:17.774075 <6>[ 0.521425] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10484 11:50:17.780432 <6>[ 0.527915] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10485 11:50:17.787415 <6>[ 0.534924] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10486 11:50:17.794506 <6>[ 0.541412] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10487 11:50:17.800784 <6>[ 0.548415] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10488 11:50:17.807498 <6>[ 0.554903] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10489 11:50:17.814093 <6>[ 0.561907] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10490 11:50:17.817211 <6>[ 0.569403] ACPI: Interpreter disabled.
10491 11:50:17.825891 <6>[ 0.575815] iommu: Default domain type: Translated
10492 11:50:17.832645 <6>[ 0.580926] iommu: DMA domain TLB invalidation policy: strict mode
10493 11:50:17.835666 <5>[ 0.587582] SCSI subsystem initialized
10494 11:50:17.842024 <6>[ 0.591747] usbcore: registered new interface driver usbfs
10495 11:50:17.848535 <6>[ 0.597481] usbcore: registered new interface driver hub
10496 11:50:17.851678 <6>[ 0.603029] usbcore: registered new device driver usb
10497 11:50:17.858899 <6>[ 0.609135] pps_core: LinuxPPS API ver. 1 registered
10498 11:50:17.868723 <6>[ 0.614330] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10499 11:50:17.872216 <6>[ 0.623679] PTP clock support registered
10500 11:50:17.875743 <6>[ 0.627921] EDAC MC: Ver: 3.0.0
10501 11:50:17.883488 <6>[ 0.633084] FPGA manager framework
10502 11:50:17.886425 <6>[ 0.636763] Advanced Linux Sound Architecture Driver Initialized.
10503 11:50:17.890462 <6>[ 0.643532] vgaarb: loaded
10504 11:50:17.896939 <6>[ 0.646718] clocksource: Switched to clocksource arch_sys_counter
10505 11:50:17.903275 <5>[ 0.653149] VFS: Disk quotas dquot_6.6.0
10506 11:50:17.910243 <6>[ 0.657336] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10507 11:50:17.913039 <6>[ 0.664520] pnp: PnP ACPI: disabled
10508 11:50:17.921165 <6>[ 0.671188] NET: Registered PF_INET protocol family
10509 11:50:17.931232 <6>[ 0.676775] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10510 11:50:17.942292 <6>[ 0.689063] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10511 11:50:17.952139 <6>[ 0.697876] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10512 11:50:17.958740 <6>[ 0.705842] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10513 11:50:17.965851 <6>[ 0.714543] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10514 11:50:17.977642 <6>[ 0.724253] TCP: Hash tables configured (established 65536 bind 65536)
10515 11:50:17.984011 <6>[ 0.731111] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10516 11:50:17.991260 <6>[ 0.738311] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10517 11:50:17.997556 <6>[ 0.746010] NET: Registered PF_UNIX/PF_LOCAL protocol family
10518 11:50:18.003878 <6>[ 0.752186] RPC: Registered named UNIX socket transport module.
10519 11:50:18.007163 <6>[ 0.758335] RPC: Registered udp transport module.
10520 11:50:18.013618 <6>[ 0.763269] RPC: Registered tcp transport module.
10521 11:50:18.020537 <6>[ 0.768199] RPC: Registered tcp NFSv4.1 backchannel transport module.
10522 11:50:18.023872 <6>[ 0.774870] PCI: CLS 0 bytes, default 64
10523 11:50:18.027082 <6>[ 0.779271] Unpacking initramfs...
10524 11:50:18.052311 <6>[ 0.798804] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10525 11:50:18.061933 <6>[ 0.807461] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10526 11:50:18.065507 <6>[ 0.816311] kvm [1]: IPA Size Limit: 40 bits
10527 11:50:18.071837 <6>[ 0.820840] kvm [1]: GICv3: no GICV resource entry
10528 11:50:18.075602 <6>[ 0.825861] kvm [1]: disabling GICv2 emulation
10529 11:50:18.081867 <6>[ 0.830547] kvm [1]: GIC system register CPU interface enabled
10530 11:50:18.085396 <6>[ 0.836709] kvm [1]: vgic interrupt IRQ18
10531 11:50:18.092125 <6>[ 0.841064] kvm [1]: VHE mode initialized successfully
10532 11:50:18.099188 <5>[ 0.847516] Initialise system trusted keyrings
10533 11:50:18.105464 <6>[ 0.852378] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10534 11:50:18.112581 <6>[ 0.862388] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10535 11:50:18.118770 <5>[ 0.868811] NFS: Registering the id_resolver key type
10536 11:50:18.122261 <5>[ 0.874113] Key type id_resolver registered
10537 11:50:18.129081 <5>[ 0.878528] Key type id_legacy registered
10538 11:50:18.135453 <6>[ 0.882802] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10539 11:50:18.142141 <6>[ 0.889724] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10540 11:50:18.148271 <6>[ 0.897433] 9p: Installing v9fs 9p2000 file system support
10541 11:50:18.184361 <5>[ 0.934622] Key type asymmetric registered
10542 11:50:18.187449 <5>[ 0.938953] Asymmetric key parser 'x509' registered
10543 11:50:18.197783 <6>[ 0.944095] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10544 11:50:18.201022 <6>[ 0.951712] io scheduler mq-deadline registered
10545 11:50:18.204007 <6>[ 0.956489] io scheduler kyber registered
10546 11:50:18.223240 <6>[ 0.973626] EINJ: ACPI disabled.
10547 11:50:18.255968 <4>[ 0.999535] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10548 11:50:18.266194 <4>[ 1.010197] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10549 11:50:18.281187 <6>[ 1.031153] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10550 11:50:18.289102 <6>[ 1.039318] printk: console [ttyS0] disabled
10551 11:50:18.317013 <6>[ 1.063961] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10552 11:50:18.323372 <6>[ 1.073437] printk: console [ttyS0] enabled
10553 11:50:18.326906 <6>[ 1.073437] printk: console [ttyS0] enabled
10554 11:50:18.333355 <6>[ 1.082333] printk: bootconsole [mtk8250] disabled
10555 11:50:18.336810 <6>[ 1.082333] printk: bootconsole [mtk8250] disabled
10556 11:50:18.343668 <6>[ 1.093587] SuperH (H)SCI(F) driver initialized
10557 11:50:18.346725 <6>[ 1.098874] msm_serial: driver initialized
10558 11:50:18.360758 <6>[ 1.107854] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10559 11:50:18.370903 <6>[ 1.116401] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10560 11:50:18.377526 <6>[ 1.124943] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10561 11:50:18.387282 <6>[ 1.133572] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10562 11:50:18.397223 <6>[ 1.142280] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10563 11:50:18.403856 <6>[ 1.151000] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10564 11:50:18.413756 <6>[ 1.159541] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10565 11:50:18.420777 <6>[ 1.168350] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10566 11:50:18.430487 <6>[ 1.176894] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10567 11:50:18.442469 <6>[ 1.192438] loop: module loaded
10568 11:50:18.449025 <6>[ 1.198507] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10569 11:50:18.471960 <4>[ 1.221897] mtk-pmic-keys: Failed to locate of_node [id: -1]
10570 11:50:18.478177 <6>[ 1.228808] megasas: 07.719.03.00-rc1
10571 11:50:18.487952 <6>[ 1.238359] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10572 11:50:18.495668 <6>[ 1.246104] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10573 11:50:18.512374 <6>[ 1.262693] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10574 11:50:18.568873 <6>[ 1.312302] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10575 11:50:18.814679 <6>[ 1.564831] Freeing initrd memory: 18316K
10576 11:50:18.826567 <6>[ 1.576600] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10577 11:50:18.837589 <6>[ 1.587530] tun: Universal TUN/TAP device driver, 1.6
10578 11:50:18.840726 <6>[ 1.593592] thunder_xcv, ver 1.0
10579 11:50:18.843901 <6>[ 1.597094] thunder_bgx, ver 1.0
10580 11:50:18.847274 <6>[ 1.600592] nicpf, ver 1.0
10581 11:50:18.857849 <6>[ 1.604595] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10582 11:50:18.860928 <6>[ 1.612071] hns3: Copyright (c) 2017 Huawei Corporation.
10583 11:50:18.864053 <6>[ 1.617661] hclge is initializing
10584 11:50:18.871055 <6>[ 1.621241] e1000: Intel(R) PRO/1000 Network Driver
10585 11:50:18.877667 <6>[ 1.626371] e1000: Copyright (c) 1999-2006 Intel Corporation.
10586 11:50:18.881263 <6>[ 1.632384] e1000e: Intel(R) PRO/1000 Network Driver
10587 11:50:18.887847 <6>[ 1.637599] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10588 11:50:18.894702 <6>[ 1.643784] igb: Intel(R) Gigabit Ethernet Network Driver
10589 11:50:18.901250 <6>[ 1.649434] igb: Copyright (c) 2007-2014 Intel Corporation.
10590 11:50:18.907737 <6>[ 1.655269] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10591 11:50:18.911077 <6>[ 1.661787] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10592 11:50:18.917922 <6>[ 1.668253] sky2: driver version 1.30
10593 11:50:18.924240 <6>[ 1.673250] VFIO - User Level meta-driver version: 0.3
10594 11:50:18.931406 <6>[ 1.681545] usbcore: registered new interface driver usb-storage
10595 11:50:18.937888 <6>[ 1.687989] usbcore: registered new device driver onboard-usb-hub
10596 11:50:18.946910 <6>[ 1.697135] mt6397-rtc mt6359-rtc: registered as rtc0
10597 11:50:18.956962 <6>[ 1.702598] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:49:44 UTC (1700826584)
10598 11:50:18.959923 <6>[ 1.712160] i2c_dev: i2c /dev entries driver
10599 11:50:18.976584 <6>[ 1.723845] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10600 11:50:18.996948 <6>[ 1.746852] cpu cpu0: EM: created perf domain
10601 11:50:18.999870 <6>[ 1.751775] cpu cpu4: EM: created perf domain
10602 11:50:19.007115 <6>[ 1.757369] sdhci: Secure Digital Host Controller Interface driver
10603 11:50:19.013579 <6>[ 1.763802] sdhci: Copyright(c) Pierre Ossman
10604 11:50:19.020383 <6>[ 1.768758] Synopsys Designware Multimedia Card Interface Driver
10605 11:50:19.027054 <6>[ 1.775392] sdhci-pltfm: SDHCI platform and OF driver helper
10606 11:50:19.030442 <6>[ 1.775471] mmc0: CQHCI version 5.10
10607 11:50:19.036712 <6>[ 1.785690] ledtrig-cpu: registered to indicate activity on CPUs
10608 11:50:19.044324 <6>[ 1.792772] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10609 11:50:19.050203 <6>[ 1.799827] usbcore: registered new interface driver usbhid
10610 11:50:19.053513 <6>[ 1.805651] usbhid: USB HID core driver
10611 11:50:19.060237 <6>[ 1.809860] spi_master spi0: will run message pump with realtime priority
10612 11:50:19.102741 <6>[ 1.846185] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10613 11:50:19.118108 <6>[ 1.861406] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10614 11:50:19.126558 <6>[ 1.876493] cros-ec-spi spi0.0: Chrome EC device registered
10615 11:50:19.133191 <6>[ 1.882596] mmc0: Command Queue Engine enabled
10616 11:50:19.139519 <6>[ 1.887353] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10617 11:50:19.142691 <6>[ 1.895008] mmcblk0: mmc0:0001 DA4128 116 GiB
10618 11:50:19.153813 <6>[ 1.904295] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10619 11:50:19.161693 <6>[ 1.912053] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10620 11:50:19.171953 <6>[ 1.917099] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10621 11:50:19.175218 <6>[ 1.917999] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10622 11:50:19.181815 <6>[ 1.927929] NET: Registered PF_PACKET protocol family
10623 11:50:19.188127 <6>[ 1.932592] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10624 11:50:19.191795 <6>[ 1.937187] 9pnet: Installing 9P2000 support
10625 11:50:19.198327 <5>[ 1.948209] Key type dns_resolver registered
10626 11:50:19.202521 <6>[ 1.953194] registered taskstats version 1
10627 11:50:19.208491 <5>[ 1.957579] Loading compiled-in X.509 certificates
10628 11:50:19.236507 <4>[ 1.979865] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10629 11:50:19.246147 <4>[ 1.990799] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10630 11:50:19.252589 <3>[ 2.001354] debugfs: File 'uA_load' in directory '/' already present!
10631 11:50:19.259342 <3>[ 2.008113] debugfs: File 'min_uV' in directory '/' already present!
10632 11:50:19.265871 <3>[ 2.014741] debugfs: File 'max_uV' in directory '/' already present!
10633 11:50:19.272705 <3>[ 2.021366] debugfs: File 'constraint_flags' in directory '/' already present!
10634 11:50:19.285115 <3>[ 2.032010] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10635 11:50:19.294857 <6>[ 2.044926] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10636 11:50:19.301398 <6>[ 2.051721] xhci-mtk 11200000.usb: xHCI Host Controller
10637 11:50:19.308117 <6>[ 2.057243] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10638 11:50:19.318532 <6>[ 2.065085] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10639 11:50:19.324790 <6>[ 2.074506] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10640 11:50:19.331533 <6>[ 2.080578] xhci-mtk 11200000.usb: xHCI Host Controller
10641 11:50:19.337900 <6>[ 2.086056] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10642 11:50:19.345266 <6>[ 2.093703] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10643 11:50:19.351570 <6>[ 2.101509] hub 1-0:1.0: USB hub found
10644 11:50:19.355041 <6>[ 2.105529] hub 1-0:1.0: 1 port detected
10645 11:50:19.361545 <6>[ 2.109826] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10646 11:50:19.368680 <6>[ 2.118558] hub 2-0:1.0: USB hub found
10647 11:50:19.371649 <6>[ 2.122578] hub 2-0:1.0: 1 port detected
10648 11:50:19.380165 <6>[ 2.130848] mtk-msdc 11f70000.mmc: Got CD GPIO
10649 11:50:19.390360 <6>[ 2.137211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10650 11:50:19.397109 <6>[ 2.145245] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10651 11:50:19.406830 <4>[ 2.153135] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10652 11:50:19.413629 <6>[ 2.162662] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10653 11:50:19.423780 <6>[ 2.170740] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10654 11:50:19.430258 <6>[ 2.178763] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10655 11:50:19.440560 <6>[ 2.186692] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10656 11:50:19.447092 <6>[ 2.194510] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10657 11:50:19.457307 <6>[ 2.202328] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10658 11:50:19.463923 <6>[ 2.212656] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10659 11:50:19.474164 <6>[ 2.221019] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10660 11:50:19.481120 <6>[ 2.229362] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10661 11:50:19.491296 <6>[ 2.237705] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10662 11:50:19.497592 <6>[ 2.246044] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10663 11:50:19.507559 <6>[ 2.254392] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10664 11:50:19.514790 <6>[ 2.262731] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10665 11:50:19.523969 <6>[ 2.271071] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10666 11:50:19.534212 <6>[ 2.279421] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10667 11:50:19.540898 <6>[ 2.287762] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10668 11:50:19.547848 <6>[ 2.296102] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10669 11:50:19.557477 <6>[ 2.304439] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10670 11:50:19.567711 <6>[ 2.312778] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10671 11:50:19.574331 <6>[ 2.321118] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10672 11:50:19.584119 <6>[ 2.329456] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10673 11:50:19.590610 <6>[ 2.338254] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10674 11:50:19.597108 <6>[ 2.345538] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10675 11:50:19.603818 <6>[ 2.352472] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10676 11:50:19.610168 <6>[ 2.359369] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10677 11:50:19.617032 <6>[ 2.366366] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10678 11:50:19.627002 <6>[ 2.373218] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10679 11:50:19.637058 <6>[ 2.382347] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10680 11:50:19.646872 <6>[ 2.391466] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10681 11:50:19.653994 <6>[ 2.400760] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10682 11:50:19.663545 <6>[ 2.410233] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10683 11:50:19.673398 <6>[ 2.419701] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10684 11:50:19.683369 <6>[ 2.428821] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10685 11:50:19.693610 <6>[ 2.438288] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10686 11:50:19.700070 <6>[ 2.447407] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10687 11:50:19.710149 <6>[ 2.456700] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10688 11:50:19.723057 <6>[ 2.466860] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10689 11:50:19.733370 <6>[ 2.478481] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10690 11:50:19.739784 <6>[ 2.488195] Trying to probe devices needed for running init ...
10691 11:50:19.783788 <6>[ 2.530982] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10692 11:50:19.938888 <6>[ 2.688893] hub 1-1:1.0: USB hub found
10693 11:50:19.941644 <6>[ 2.693409] hub 1-1:1.0: 4 ports detected
10694 11:50:19.951927 <6>[ 2.702193] hub 1-1:1.0: USB hub found
10695 11:50:19.954684 <6>[ 2.706525] hub 1-1:1.0: 4 ports detected
10696 11:50:20.064072 <6>[ 2.811272] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10697 11:50:20.089525 <6>[ 2.840099] hub 2-1:1.0: USB hub found
10698 11:50:20.092717 <6>[ 2.844576] hub 2-1:1.0: 3 ports detected
10699 11:50:20.101813 <6>[ 2.852353] hub 2-1:1.0: USB hub found
10700 11:50:20.105231 <6>[ 2.856801] hub 2-1:1.0: 3 ports detected
10701 11:50:20.279611 <6>[ 3.027035] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10702 11:50:20.412132 <6>[ 3.162898] hub 1-1.4:1.0: USB hub found
10703 11:50:20.415509 <6>[ 3.167563] hub 1-1.4:1.0: 2 ports detected
10704 11:50:20.425324 <6>[ 3.175752] hub 1-1.4:1.0: USB hub found
10705 11:50:20.428154 <6>[ 3.180351] hub 1-1.4:1.0: 2 ports detected
10706 11:50:20.492199 <6>[ 3.239162] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10707 11:50:20.727621 <6>[ 3.475031] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10708 11:50:20.919855 <6>[ 3.667031] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10709 11:50:32.012195 <6>[ 14.767992] ALSA device list:
10710 11:50:32.018653 <6>[ 14.771279] No soundcards found.
10711 11:50:32.026809 <6>[ 14.779186] Freeing unused kernel memory: 8384K
10712 11:50:32.030230 <6>[ 14.784201] Run /init as init process
10713 11:50:32.041762 Loading, please wait...
10714 11:50:32.068298 Starting systemd-udevd version 252.6-1
10715 11:50:32.366024 <6>[ 15.115121] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10716 11:50:32.393887 <6>[ 15.146181] remoteproc remoteproc0: scp is available
10717 11:50:32.400307 <6>[ 15.147055] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10718 11:50:32.410556 <3>[ 15.147080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 11:50:32.417590 <3>[ 15.147108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 11:50:32.427090 <3>[ 15.147125] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 11:50:32.433553 <3>[ 15.147756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 11:50:32.443461 <3>[ 15.147780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 11:50:32.450339 <3>[ 15.147789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 11:50:32.457510 <3>[ 15.147806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 11:50:32.467584 <3>[ 15.147814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 11:50:32.470873 <6>[ 15.151620] remoteproc remoteproc0: powering up scp
10727 11:50:32.480812 <3>[ 15.152951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 11:50:32.488024 <3>[ 15.154009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 11:50:32.495023 <3>[ 15.154020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 11:50:32.504624 <3>[ 15.154026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 11:50:32.511249 <3>[ 15.154078] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 11:50:32.521061 <3>[ 15.154081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 11:50:32.527755 <3>[ 15.154088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 11:50:32.537672 <3>[ 15.154105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 11:50:32.544797 <3>[ 15.154113] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 11:50:32.554137 <3>[ 15.154176] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 11:50:32.560754 <4>[ 15.154336] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10738 11:50:32.567549 <4>[ 15.154463] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10739 11:50:32.574544 <6>[ 15.154895] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10740 11:50:32.584099 <6>[ 15.159064] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10741 11:50:32.590709 <6>[ 15.167117] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10742 11:50:32.597737 <6>[ 15.167154] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10743 11:50:32.603793 <6>[ 15.189035] mc: Linux media interface: v0.10
10744 11:50:32.610302 <6>[ 15.191485] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10745 11:50:32.620367 <4>[ 15.199280] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10746 11:50:32.623779 <4>[ 15.199280] Fallback method does not support PEC.
10747 11:50:32.630418 <6>[ 15.210445] usbcore: registered new interface driver r8152
10748 11:50:32.640301 <3>[ 15.214691] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10749 11:50:32.646829 <3>[ 15.247127] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10750 11:50:32.656934 <6>[ 15.267264] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10751 11:50:32.663293 <6>[ 15.294792] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10752 11:50:32.673323 <6>[ 15.294909] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10753 11:50:32.680220 <6>[ 15.294918] remoteproc remoteproc0: remote processor scp is now up
10754 11:50:32.686722 <6>[ 15.338228] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10755 11:50:32.693054 <6>[ 15.341534] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10756 11:50:32.699711 <6>[ 15.349661] pci_bus 0000:00: root bus resource [bus 00-ff]
10757 11:50:32.706248 <6>[ 15.356584] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10758 11:50:32.716373 <6>[ 15.357927] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10759 11:50:32.726311 <6>[ 15.358398] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10760 11:50:32.732905 <6>[ 15.359812] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10761 11:50:32.743054 <6>[ 15.359818] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10762 11:50:32.749445 <6>[ 15.359857] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10763 11:50:32.759223 <6>[ 15.377378] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10764 11:50:32.765934 <4>[ 15.378004] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10765 11:50:32.775825 <4>[ 15.378013] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10766 11:50:32.782220 <6>[ 15.382803] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10767 11:50:32.788906 <6>[ 15.388941] videodev: Linux video capture interface: v2.00
10768 11:50:32.792307 <6>[ 15.396893] pci 0000:00:00.0: supports D1 D2
10769 11:50:32.798778 <6>[ 15.397034] usbcore: registered new interface driver cdc_ether
10770 11:50:32.805421 <6>[ 15.406221] usbcore: registered new interface driver r8153_ecm
10771 11:50:32.812296 <6>[ 15.414930] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10772 11:50:32.815610 <6>[ 15.415688] Bluetooth: Core ver 2.22
10773 11:50:32.822176 <6>[ 15.415756] NET: Registered PF_BLUETOOTH protocol family
10774 11:50:32.829458 <6>[ 15.415759] Bluetooth: HCI device and connection manager initialized
10775 11:50:32.832377 <6>[ 15.415796] Bluetooth: HCI socket layer initialized
10776 11:50:32.838483 <6>[ 15.415810] Bluetooth: L2CAP socket layer initialized
10777 11:50:32.841959 <6>[ 15.415824] Bluetooth: SCO socket layer initialized
10778 11:50:32.851809 <6>[ 15.458258] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10779 11:50:32.855367 <6>[ 15.458828] r8152 2-1.3:1.0 eth0: v1.12.13
10780 11:50:32.861744 <6>[ 15.466071] usbcore: registered new interface driver btusb
10781 11:50:32.868701 <6>[ 15.466531] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10782 11:50:32.875131 <6>[ 15.466744] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10783 11:50:32.881728 <6>[ 15.466776] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10784 11:50:32.891648 <6>[ 15.466795] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10785 11:50:32.898299 <6>[ 15.466811] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10786 11:50:32.901629 <6>[ 15.466927] pci 0000:01:00.0: supports D1 D2
10787 11:50:32.908239 <6>[ 15.466929] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10788 11:50:32.918202 <4>[ 15.466997] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10789 11:50:32.925055 <3>[ 15.467005] Bluetooth: hci0: Failed to load firmware file (-2)
10790 11:50:32.931721 <3>[ 15.467008] Bluetooth: hci0: Failed to set up firmware (-2)
10791 11:50:32.941173 <4>[ 15.467011] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10792 11:50:32.947964 <6>[ 15.469766] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10793 11:50:32.960868 <6>[ 15.476722] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10794 11:50:32.967394 <6>[ 15.478892] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10795 11:50:32.973878 <6>[ 15.478920] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10796 11:50:32.983841 <6>[ 15.478923] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10797 11:50:32.990415 <6>[ 15.478931] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10798 11:50:33.000518 <6>[ 15.478944] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10799 11:50:33.007158 <6>[ 15.478957] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10800 11:50:33.013899 <6>[ 15.478969] pci 0000:00:00.0: PCI bridge to [bus 01]
10801 11:50:33.020611 <6>[ 15.478974] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10802 11:50:33.027700 <6>[ 15.479091] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10803 11:50:33.033439 <6>[ 15.479521] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10804 11:50:33.040022 <6>[ 15.479998] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10805 11:50:33.046784 <6>[ 15.491844] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10806 11:50:33.050112 <6>[ 15.501402] usbcore: registered new interface driver uvcvideo
10807 11:50:33.068192 <5>[ 15.817594] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10808 11:50:33.099356 <5>[ 15.848366] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10809 11:50:33.105680 <4>[ 15.855276] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10810 11:50:33.112110 <6>[ 15.864163] cfg80211: failed to load regulatory.db
10811 11:50:33.167136 <6>[ 15.916235] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10812 11:50:33.173342 <6>[ 15.923766] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10813 11:50:33.198092 <6>[ 15.950792] mt7921e 0000:01:00.0: ASIC revision: 79610010
10814 11:50:33.305423 <4>[ 16.051598] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10815 11:50:33.312683 Begin: Loading essential drivers ... done.
10816 11:50:33.316344 Begin: Running /scripts/init-premount ... done.
10817 11:50:33.322603 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10818 11:50:33.332145 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10819 11:50:33.335506 Device /sys/class/net/enx00e04c722dd6 found
10820 11:50:33.335617 done.
10821 11:50:33.366272 Begin: Waiting up to 180 secs for any network device to become available ... done.
10822 11:50:33.428728 <4>[ 16.174560] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10823 11:50:33.435166 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10824 11:50:33.548539 <4>[ 16.294564] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10825 11:50:33.668223 <4>[ 16.414242] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10826 11:50:33.788228 <4>[ 16.534285] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10827 11:50:33.908064 <4>[ 16.654218] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10828 11:50:34.028330 <4>[ 16.774316] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10829 11:50:34.148172 <4>[ 16.894144] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10830 11:50:34.268125 <4>[ 17.014212] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10831 11:50:34.330243 <6>[ 17.082842] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10832 11:50:34.388207 <4>[ 17.134126] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10833 11:50:34.449912 IP-Config: no response after 2 secs - giving up
10834 11:50:34.499448 <3>[ 17.252346] mt7921e 0000:01:00.0: hardware init failed
10835 11:50:34.517462 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10836 11:50:34.535121 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10837 11:50:34.542330 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10838 11:50:34.548466 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10839 11:50:34.555636 host : mt8192-asurada-spherion-r0-cbg-1
10840 11:50:34.561417 domain : lava-rack
10841 11:50:34.564831 rootserver: 192.168.201.1 rootpath:
10842 11:50:34.568206 filename :
10843 11:50:34.640120 done.
10844 11:50:34.646702 Begin: Running /scripts/nfs-bottom ... done.
10845 11:50:34.670135 Begin: Running /scripts/init-bottom ... done.
10846 11:50:35.964926 <6>[ 18.717993] NET: Registered PF_INET6 protocol family
10847 11:50:35.971902 <6>[ 18.724913] Segment Routing with IPv6
10848 11:50:35.975291 <6>[ 18.728894] In-situ OAM (IOAM) with IPv6
10849 11:50:36.147644 <30>[ 18.873771] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10850 11:50:36.154061 <30>[ 18.906119] systemd[1]: Detected architecture arm64.
10851 11:50:36.160466
10852 11:50:36.163761 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10853 11:50:36.163879
10854 11:50:36.190685 <30>[ 18.943827] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10855 11:50:37.141520 <30>[ 19.891439] systemd[1]: Queued start job for default target graphical.target.
10856 11:50:37.197928 <30>[ 19.947682] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10857 11:50:37.204662 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10858 11:50:37.222978 <30>[ 19.972461] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10859 11:50:37.232690 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10860 11:50:37.250822 <30>[ 20.000697] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10861 11:50:37.261102 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10862 11:50:37.279444 <30>[ 20.029109] systemd[1]: Created slice user.slice - User and Session Slice.
10863 11:50:37.285812 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10864 11:50:37.309191 <30>[ 20.055387] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10865 11:50:37.316159 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10866 11:50:37.336842 <30>[ 20.083230] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10867 11:50:37.343385 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10868 11:50:37.371256 <30>[ 20.111209] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10869 11:50:37.381447 <30>[ 20.131130] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10870 11:50:37.387872 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10871 11:50:37.405320 <30>[ 20.155041] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10872 11:50:37.415446 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10873 11:50:37.430130 <30>[ 20.183156] systemd[1]: Reached target paths.target - Path Units.
10874 11:50:37.436790 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10875 11:50:37.457721 <30>[ 20.207447] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10876 11:50:37.463989 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10877 11:50:37.478021 <30>[ 20.230990] systemd[1]: Reached target slices.target - Slice Units.
10878 11:50:37.487984 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10879 11:50:37.503032 <30>[ 20.255505] systemd[1]: Reached target swap.target - Swaps.
10880 11:50:37.509075 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10881 11:50:37.529919 <30>[ 20.279534] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10882 11:50:37.539694 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10883 11:50:37.557403 <30>[ 20.307279] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10884 11:50:37.567374 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10885 11:50:37.586893 <30>[ 20.336744] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10886 11:50:37.596965 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10887 11:50:37.614289 <30>[ 20.364318] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10888 11:50:37.624207 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10889 11:50:37.642256 <30>[ 20.391631] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10890 11:50:37.648204 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10891 11:50:37.666687 <30>[ 20.416379] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10892 11:50:37.676273 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10893 11:50:37.696834 <30>[ 20.446094] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10894 11:50:37.706031 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10895 11:50:37.721907 <30>[ 20.471498] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10896 11:50:37.731353 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10897 11:50:37.789387 <30>[ 20.539193] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10898 11:50:37.796106 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10899 11:50:37.818164 <30>[ 20.567734] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10900 11:50:37.824508 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10901 11:50:37.849973 <30>[ 20.599826] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10902 11:50:37.856867 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10903 11:50:37.884234 <30>[ 20.627585] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10904 11:50:37.929969 <30>[ 20.679769] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10905 11:50:37.939870 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10906 11:50:37.962696 <30>[ 20.712430] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10907 11:50:37.969330 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10908 11:50:37.994931 <30>[ 20.744714] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10909 11:50:38.001450 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10910 11:50:38.027214 <30>[ 20.776537] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10911 11:50:38.036737 Startin<6>[ 20.785722] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10912 11:50:38.043165 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10913 11:50:38.067379 <30>[ 20.817018] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10914 11:50:38.073889 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10915 11:50:38.098618 <30>[ 20.848586] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10916 11:50:38.105376 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10917 11:50:38.129501 <30>[ 20.879382] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10918 11:50:38.136214 Starting [0;1;39mmodpr<6>[ 20.889437] fuse: init (API version 7.37)
10919 11:50:38.139360 obe@loop.ser…e[0m - Load Kernel Module loop...
10920 11:50:38.170764 <30>[ 20.920621] systemd[1]: Starting systemd-journald.service - Journal Service...
10921 11:50:38.177758 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10922 11:50:38.198823 <30>[ 20.948550] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10923 11:50:38.205148 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10924 11:50:38.277214 <30>[ 21.023806] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10925 11:50:38.283747 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10926 11:50:38.305443 <30>[ 21.055195] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10927 11:50:38.315119 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10928 11:50:38.335444 <3>[ 21.085199] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 11:50:38.345389 <30>[ 21.087243] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10930 11:50:38.351880 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10931 11:50:38.372645 <3>[ 21.122505] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 11:50:38.379335 <30>[ 21.122965] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10933 11:50:38.389122 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10934 11:50:38.409300 <30>[ 21.159307] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10935 11:50:38.416087 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10936 11:50:38.434085 <30>[ 21.183635] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10937 11:50:38.440507 <3>[ 21.185274] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 11:50:38.450590 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10939 11:50:38.470585 <30>[ 21.220242] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10940 11:50:38.480322 <3>[ 21.220982] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 11:50:38.487122 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10942 11:50:38.506357 <30>[ 21.255994] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10943 11:50:38.513125 <3>[ 21.259334] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 11:50:38.523333 <30>[ 21.263901] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10945 11:50:38.530038 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10946 11:50:38.542112 <3>[ 21.291812] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 11:50:38.552601 <30>[ 21.302022] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10948 11:50:38.558990 <30>[ 21.309969] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10949 11:50:38.568653 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10950 11:50:38.586550 <3>[ 21.336544] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 11:50:38.597070 <30>[ 21.347014] systemd[1]: modprobe@drm.service: Deactivated successfully.
10952 11:50:38.603438 <30>[ 21.354703] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10953 11:50:38.613519 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10954 11:50:38.630297 <3>[ 21.379967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 11:50:38.640783 <30>[ 21.390377] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10956 11:50:38.650266 <30>[ 21.398586] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10957 11:50:38.656804 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10958 11:50:38.677078 <3>[ 21.426246] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 11:50:38.687004 <30>[ 21.436975] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10960 11:50:38.693597 <30>[ 21.444794] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10961 11:50:38.703881 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10962 11:50:38.727522 <30>[ 21.477060] systemd[1]: modprobe@loop.service: Deactivated successfully.
10963 11:50:38.734146 <30>[ 21.485094] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10964 11:50:38.744037 [[0;32m OK [<3>[ 21.494039] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 11:50:38.760700 <4>[ 21.494733] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10966 11:50:38.771478 0m] Finished [0<3>[ 21.519020] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10967 11:50:38.774276 ;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10968 11:50:38.800384 <30>[ 21.549414] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10969 11:50:38.807105 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10970 11:50:38.829718 <30>[ 21.575675] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10971 11:50:38.836272 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10972 11:50:38.853505 <30>[ 21.603683] systemd[1]: Started systemd-journald.service - Journal Service.
10973 11:50:38.860143 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10974 11:50:38.885291 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10975 11:50:38.906585 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10976 11:50:38.931956 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10977 11:50:38.989598 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10978 11:50:39.010435 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10979 11:50:39.069936 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10980 11:50:39.096634 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10981 11:50:39.137141 <46>[ 21.886965] systemd-journald[304]: Received client request to flush runtime journal.
10982 11:50:39.162197 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10983 11:50:39.394541 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10984 11:50:39.723832 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10985 11:50:39.742278 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10986 11:50:39.763240 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10987 11:50:39.946658 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10988 11:50:39.970874 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10989 11:50:40.002172 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10990 11:50:40.609416 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10991 11:50:40.638977 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10992 11:50:40.661753 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10993 11:50:40.685243 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10994 11:50:40.738011 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10995 11:50:40.761309 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10996 11:50:40.786751 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10997 11:50:40.819990 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10998 11:50:40.833706 See 'systemctl status systemd-binfmt.service' for details.
10999 11:50:40.967458 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11000 11:50:41.039040 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11001 11:50:41.066625 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11002 11:50:41.119572 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11003 11:50:41.211625 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11004 11:50:41.238656 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11005 11:50:41.465500 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11006 11:50:41.524299 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11007 11:50:41.541102 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11008 11:50:41.594992 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11009 11:50:41.619088 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11010 11:50:41.641582 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11011 11:50:41.661468 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11012 11:50:41.677921 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11013 11:50:41.698250 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11014 11:50:41.721279 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11015 11:50:41.737014 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11016 11:50:41.753210 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11017 11:50:41.774897 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11018 11:50:41.795432 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11019 11:50:41.813376 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11020 11:50:41.871665 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11021 11:50:41.896075 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11022 11:50:41.912905 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11023 11:50:41.930889 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11024 11:50:41.948828 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11025 11:50:41.965202 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11026 11:50:42.010531 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11027 11:50:42.041527 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11028 11:50:42.153933 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11029 11:50:42.178592 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11030 11:50:42.201091 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11031 11:50:42.333765 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11032 11:50:42.353343 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11033 11:50:42.370767 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11034 11:50:42.418425 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11035 11:50:42.455932 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11036 11:50:42.474178 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11037 11:50:42.490558 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11038 11:50:42.527989 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11039 11:50:42.557523 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11040 11:50:42.579885 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11041 11:50:42.643380 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11042 11:50:42.669790 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11043 11:50:42.704294 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11044 11:50:42.744877 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11045 11:50:42.824216
11046 11:50:42.824393
11047 11:50:42.827368 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11048 11:50:42.827473
11049 11:50:42.830729 debian-bookworm-arm64 login: root (automatic login)
11050 11:50:42.830831
11051 11:50:42.830928
11052 11:50:43.093106 Linux debian-bookworm-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
11053 11:50:43.093294
11054 11:50:43.099017 The programs included with the Debian GNU/Linux system are free software;
11055 11:50:43.105676 the exact distribution terms for each program are described in the
11056 11:50:43.109010 individual files in /usr/share/doc/*/copyright.
11057 11:50:43.109122
11058 11:50:43.115656 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11059 11:50:43.119095 permitted by applicable law.
11060 11:50:43.933156 Matched prompt #10: / #
11062 11:50:43.933555 Setting prompt string to ['/ #']
11063 11:50:43.933681 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11065 11:50:43.933983 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11066 11:50:43.934100 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11067 11:50:43.934201 Setting prompt string to ['/ #']
11068 11:50:43.934291 Forcing a shell prompt, looking for ['/ #']
11070 11:50:43.984567 / #
11071 11:50:43.984772 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11072 11:50:43.984895 Waiting using forced prompt support (timeout 00:02:30)
11073 11:50:43.989413
11074 11:50:43.989723 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11075 11:50:43.989821 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11077 11:50:44.090154 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12074061/extract-nfsrootfs-mw13pg1y'
11078 11:50:44.095628 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12074061/extract-nfsrootfs-mw13pg1y'
11080 11:50:44.196231 / # export NFS_SERVER_IP='192.168.201.1'
11081 11:50:44.201412 export NFS_SERVER_IP='192.168.201.1'
11082 11:50:44.201713 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11083 11:50:44.201820 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11084 11:50:44.201920 end: 2 depthcharge-action (duration 00:01:25) [common]
11085 11:50:44.202009 start: 3 lava-test-retry (timeout 00:07:47) [common]
11086 11:50:44.202114 start: 3.1 lava-test-shell (timeout 00:07:47) [common]
11087 11:50:44.202201 Using namespace: common
11089 11:50:44.302541 / # #
11090 11:50:44.302730 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11091 11:50:44.308017 #
11092 11:50:44.308286 Using /lava-12074061
11094 11:50:44.408636 / # export SHELL=/bin/bash
11095 11:50:44.414289 export SHELL=/bin/bash
11097 11:50:44.515086 / # . /lava-12074061/environment
11098 11:50:44.521118 . /lava-12074061/environment
11100 11:50:44.628410 / # /lava-12074061/bin/lava-test-runner /lava-12074061/0
11101 11:50:44.628956 Test shell timeout: 10s (minimum of the action and connection timeout)
11102 11:50:44.634337 /lava-12074061/bin/lava-test-runner /lava-12074061/0
11103 11:50:44.862437 + export TESTRUN_ID=0_timesync-off
11104 11:50:44.865757 + TESTRUN_ID=0_timesync-off
11105 11:50:44.868943 + cd /lava-12074061/0/tests/0_timesync-off
11106 11:50:44.872600 ++ cat uuid
11107 11:50:44.872705 + UUID=12074061_1.6.2.3.1
11108 11:50:44.875601 + set +x
11109 11:50:44.878915 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12074061_1.6.2.3.1>
11110 11:50:44.879201 Received signal: <STARTRUN> 0_timesync-off 12074061_1.6.2.3.1
11111 11:50:44.879312 Starting test lava.0_timesync-off (12074061_1.6.2.3.1)
11112 11:50:44.879441 Skipping test definition patterns.
11113 11:50:44.882272 + systemctl stop systemd-timesyncd
11114 11:50:44.950707 + set +x
11115 11:50:44.953861 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12074061_1.6.2.3.1>
11116 11:50:44.954127 Received signal: <ENDRUN> 0_timesync-off 12074061_1.6.2.3.1
11117 11:50:44.954255 Ending use of test pattern.
11118 11:50:44.954356 Ending test lava.0_timesync-off (12074061_1.6.2.3.1), duration 0.08
11120 11:50:45.005709 + export TESTRUN_ID=1_kselftest-alsa
11121 11:50:45.008788 + TESTRUN_ID=1_kselftest-alsa
11122 11:50:45.016235 + cd /lava-12074061/0/tests/1_kselftest-alsa
11123 11:50:45.016346 ++ cat uuid
11124 11:50:45.018536 + UUID=12074061_1.6.2.3.5
11125 11:50:45.018612 + set +x
11126 11:50:45.021973 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12074061_1.6.2.3.5>
11127 11:50:45.022259 Received signal: <STARTRUN> 1_kselftest-alsa 12074061_1.6.2.3.5
11128 11:50:45.022356 Starting test lava.1_kselftest-alsa (12074061_1.6.2.3.5)
11129 11:50:45.022505 Skipping test definition patterns.
11130 11:50:45.025637 + cd ./automated/linux/kselftest/
11131 11:50:45.055154 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11132 11:50:45.081619 INFO: install_deps skipped
11133 11:50:45.566154 --2023-11-24 11:50:10-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11134 11:50:45.582625 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11135 11:50:45.716504 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11136 11:50:45.848747 HTTP request sent, awaiting response... 200 OK
11137 11:50:45.851797 Length: 2961876 (2.8M) [application/octet-stream]
11138 11:50:45.855057 Saving to: 'kselftest.tar.xz'
11139 11:50:45.855143
11140 11:50:45.855208
11141 11:50:46.114686 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11142 11:50:46.397729 kselftest.tar.xz 1%[ ] 46.39K 180KB/s
11143 11:50:46.827070 kselftest.tar.xz 7%[> ] 219.84K 413KB/s
11144 11:50:47.101752 kselftest.tar.xz 27%[====> ] 796.78K 837KB/s
11145 11:50:47.181376 kselftest.tar.xz 83%[===============> ] 2.37M 1.94MB/s
11146 11:50:47.187663 kselftest.tar.xz 100%[===================>] 2.82M 2.18MB/s in 1.3s
11147 11:50:47.187766
11148 11:50:47.444991 2023-11-24 11:50:12 (2.18 MB/s) - 'kselftest.tar.xz' saved [2961876/2961876]
11149 11:50:47.445139
11150 11:50:53.101619 skiplist:
11151 11:50:53.104965 ========================================
11152 11:50:53.108330 ========================================
11153 11:50:53.154230 alsa:mixer-test
11154 11:50:53.173681 ============== Tests to run ===============
11155 11:50:53.173779 alsa:mixer-test
11156 11:50:53.176410 ===========End Tests to run ===============
11157 11:50:53.180462 shardfile-alsa pass
11158 11:50:53.275966 <12>[ 36.031023] kselftest: Running tests in alsa
11159 11:50:53.284574 TAP version 13
11160 11:50:53.298057 1..1
11161 11:50:53.312905 # selftests: alsa: mixer-test
11162 11:50:53.792934 # TAP version 13
11163 11:50:53.793092 # 1..0
11164 11:50:53.799488 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11165 11:50:53.802955 ok 1 selftests: alsa: mixer-test
11166 11:50:54.513799 alsa_mixer-test pass
11167 11:50:54.557122 + ../../utils/send-to-lava.sh ./output/result.txt
11168 11:50:54.622604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11169 11:50:54.622913 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11171 11:50:54.662690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11172 11:50:54.662780 + set +x
11173 11:50:54.663035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11175 11:50:54.669406 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12074061_1.6.2.3.5>
11176 11:50:54.669659 Received signal: <ENDRUN> 1_kselftest-alsa 12074061_1.6.2.3.5
11177 11:50:54.669735 Ending use of test pattern.
11178 11:50:54.669796 Ending test lava.1_kselftest-alsa (12074061_1.6.2.3.5), duration 9.65
11180 11:50:54.673117 <LAVA_TEST_RUNNER EXIT>
11181 11:50:54.673366 ok: lava_test_shell seems to have completed
11182 11:50:54.673464 alsa_mixer-test: pass
shardfile-alsa: pass
11183 11:50:54.673553 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11184 11:50:54.673635 end: 3 lava-test-retry (duration 00:00:10) [common]
11185 11:50:54.673734 start: 4 finalize (timeout 00:07:37) [common]
11186 11:50:54.673828 start: 4.1 power-off (timeout 00:00:30) [common]
11187 11:50:54.673985 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11188 11:50:54.749114 >> Command sent successfully.
11189 11:50:54.751462 Returned 0 in 0 seconds
11190 11:50:54.851853 end: 4.1 power-off (duration 00:00:00) [common]
11192 11:50:54.852166 start: 4.2 read-feedback (timeout 00:07:37) [common]
11193 11:50:54.852427 Listened to connection for namespace 'common' for up to 1s
11194 11:50:55.853405 Finalising connection for namespace 'common'
11195 11:50:55.853611 Disconnecting from shell: Finalise
11196 11:50:55.853706 / #
11197 11:50:55.954113 end: 4.2 read-feedback (duration 00:00:01) [common]
11198 11:50:55.954265 end: 4 finalize (duration 00:00:01) [common]
11199 11:50:55.954382 Cleaning after the job
11200 11:50:55.954519 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/ramdisk
11201 11:50:55.956846 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/kernel
11202 11:50:55.966538 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/dtb
11203 11:50:55.966709 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/nfsrootfs
11204 11:50:56.040049 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074061/tftp-deploy-vlhdt09n/modules
11205 11:50:56.045532 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074061
11206 11:50:56.567095 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074061
11207 11:50:56.567281 Job finished correctly