Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 36
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 11:44:30.201392 lava-dispatcher, installed at version: 2023.10
2 11:44:30.201588 start: 0 validate
3 11:44:30.201714 Start time: 2023-11-24 11:44:30.201707+00:00 (UTC)
4 11:44:30.201832 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:44:30.201960 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:44:30.470541 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:44:30.471301 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:44:49.269465 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:44:49.270330 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:44:49.540193 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:44:49.540917 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:44:49.804631 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:44:49.805392 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:44:53.316034 validate duration: 23.11
16 11:44:53.316301 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:44:53.316401 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:44:53.316501 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:44:53.316626 Not decompressing ramdisk as can be used compressed.
20 11:44:53.316710 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 11:44:53.316774 saving as /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/ramdisk/initrd.cpio.gz
22 11:44:53.316838 total size: 4665395 (4 MB)
23 11:44:53.317902 progress 0 % (0 MB)
24 11:44:53.319349 progress 5 % (0 MB)
25 11:44:53.320606 progress 10 % (0 MB)
26 11:44:53.321847 progress 15 % (0 MB)
27 11:44:53.323093 progress 20 % (0 MB)
28 11:44:53.324310 progress 25 % (1 MB)
29 11:44:53.325556 progress 30 % (1 MB)
30 11:44:53.326822 progress 35 % (1 MB)
31 11:44:53.328033 progress 40 % (1 MB)
32 11:44:53.329420 progress 45 % (2 MB)
33 11:44:53.330748 progress 50 % (2 MB)
34 11:44:53.331965 progress 55 % (2 MB)
35 11:44:53.333176 progress 60 % (2 MB)
36 11:44:53.334409 progress 65 % (2 MB)
37 11:44:53.335628 progress 70 % (3 MB)
38 11:44:53.336832 progress 75 % (3 MB)
39 11:44:53.338035 progress 80 % (3 MB)
40 11:44:53.339447 progress 85 % (3 MB)
41 11:44:53.340652 progress 90 % (4 MB)
42 11:44:53.341855 progress 95 % (4 MB)
43 11:44:53.343119 progress 100 % (4 MB)
44 11:44:53.343276 4 MB downloaded in 0.03 s (168.30 MB/s)
45 11:44:53.343431 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:44:53.343671 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:44:53.343760 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:44:53.343846 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:44:53.343978 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:44:53.344051 saving as /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/kernel/Image
52 11:44:53.344114 total size: 49107456 (46 MB)
53 11:44:53.344175 No compression specified
54 11:44:53.345271 progress 0 % (0 MB)
55 11:44:53.357743 progress 5 % (2 MB)
56 11:44:53.370142 progress 10 % (4 MB)
57 11:44:53.382576 progress 15 % (7 MB)
58 11:44:53.395318 progress 20 % (9 MB)
59 11:44:53.408325 progress 25 % (11 MB)
60 11:44:53.420882 progress 30 % (14 MB)
61 11:44:53.433465 progress 35 % (16 MB)
62 11:44:53.446071 progress 40 % (18 MB)
63 11:44:53.458736 progress 45 % (21 MB)
64 11:44:53.471142 progress 50 % (23 MB)
65 11:44:53.483526 progress 55 % (25 MB)
66 11:44:53.495920 progress 60 % (28 MB)
67 11:44:53.508754 progress 65 % (30 MB)
68 11:44:53.521303 progress 70 % (32 MB)
69 11:44:53.534026 progress 75 % (35 MB)
70 11:44:53.546720 progress 80 % (37 MB)
71 11:44:53.559207 progress 85 % (39 MB)
72 11:44:53.571573 progress 90 % (42 MB)
73 11:44:53.583839 progress 95 % (44 MB)
74 11:44:53.595979 progress 100 % (46 MB)
75 11:44:53.596202 46 MB downloaded in 0.25 s (185.78 MB/s)
76 11:44:53.596356 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:44:53.596595 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:44:53.596684 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:44:53.596774 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:44:53.596909 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:44:53.596980 saving as /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/dtb/mt8192-asurada-spherion-r0.dtb
83 11:44:53.597042 total size: 47278 (0 MB)
84 11:44:53.597104 No compression specified
85 11:44:53.598235 progress 69 % (0 MB)
86 11:44:53.598585 progress 100 % (0 MB)
87 11:44:53.598746 0 MB downloaded in 0.00 s (26.50 MB/s)
88 11:44:53.598873 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:44:53.599101 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:44:53.599190 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:44:53.599275 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:44:53.599385 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 11:44:53.599454 saving as /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/nfsrootfs/full.rootfs.tar
95 11:44:53.599515 total size: 200813988 (191 MB)
96 11:44:53.599577 Using unxz to decompress xz
97 11:44:53.603176 progress 0 % (0 MB)
98 11:44:54.142359 progress 5 % (9 MB)
99 11:44:54.671649 progress 10 % (19 MB)
100 11:44:55.268557 progress 15 % (28 MB)
101 11:44:55.658707 progress 20 % (38 MB)
102 11:44:55.990212 progress 25 % (47 MB)
103 11:44:56.592020 progress 30 % (57 MB)
104 11:44:57.149291 progress 35 % (67 MB)
105 11:44:57.740389 progress 40 % (76 MB)
106 11:44:58.301013 progress 45 % (86 MB)
107 11:44:58.884384 progress 50 % (95 MB)
108 11:44:59.513328 progress 55 % (105 MB)
109 11:45:00.174529 progress 60 % (114 MB)
110 11:45:00.295718 progress 65 % (124 MB)
111 11:45:00.446173 progress 70 % (134 MB)
112 11:45:00.559065 progress 75 % (143 MB)
113 11:45:00.640469 progress 80 % (153 MB)
114 11:45:00.710029 progress 85 % (162 MB)
115 11:45:00.814458 progress 90 % (172 MB)
116 11:45:01.103030 progress 95 % (181 MB)
117 11:45:01.690800 progress 100 % (191 MB)
118 11:45:01.696302 191 MB downloaded in 8.10 s (23.65 MB/s)
119 11:45:01.696559 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:45:01.696829 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:45:01.696929 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:45:01.697020 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:45:01.697172 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:45:01.697252 saving as /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/modules/modules.tar
126 11:45:01.697317 total size: 8624756 (8 MB)
127 11:45:01.697385 Using unxz to decompress xz
128 11:45:01.701012 progress 0 % (0 MB)
129 11:45:01.722194 progress 5 % (0 MB)
130 11:45:01.746459 progress 10 % (0 MB)
131 11:45:01.770913 progress 15 % (1 MB)
132 11:45:01.795199 progress 20 % (1 MB)
133 11:45:01.820117 progress 25 % (2 MB)
134 11:45:01.846235 progress 30 % (2 MB)
135 11:45:01.873113 progress 35 % (2 MB)
136 11:45:01.896928 progress 40 % (3 MB)
137 11:45:01.921818 progress 45 % (3 MB)
138 11:45:01.947220 progress 50 % (4 MB)
139 11:45:01.971707 progress 55 % (4 MB)
140 11:45:01.996518 progress 60 % (4 MB)
141 11:45:02.024227 progress 65 % (5 MB)
142 11:45:02.049509 progress 70 % (5 MB)
143 11:45:02.073255 progress 75 % (6 MB)
144 11:45:02.100514 progress 80 % (6 MB)
145 11:45:02.126311 progress 85 % (7 MB)
146 11:45:02.151499 progress 90 % (7 MB)
147 11:45:02.182964 progress 95 % (7 MB)
148 11:45:02.210815 progress 100 % (8 MB)
149 11:45:02.215749 8 MB downloaded in 0.52 s (15.87 MB/s)
150 11:45:02.216010 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:45:02.216304 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:45:02.216399 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:45:02.216503 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:45:05.441115 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12074003/extract-nfsrootfs-50snkza6
156 11:45:05.441326 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:45:05.441431 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 11:45:05.441598 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi
159 11:45:05.441724 makedir: /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin
160 11:45:05.441823 makedir: /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/tests
161 11:45:05.441920 makedir: /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/results
162 11:45:05.442020 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-add-keys
163 11:45:05.442161 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-add-sources
164 11:45:05.442286 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-background-process-start
165 11:45:05.442453 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-background-process-stop
166 11:45:05.442578 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-common-functions
167 11:45:05.442697 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-echo-ipv4
168 11:45:05.442820 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-install-packages
169 11:45:05.442939 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-installed-packages
170 11:45:05.443056 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-os-build
171 11:45:05.443175 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-probe-channel
172 11:45:05.443293 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-probe-ip
173 11:45:05.443411 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-target-ip
174 11:45:05.443529 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-target-mac
175 11:45:05.443646 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-target-storage
176 11:45:05.443767 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-test-case
177 11:45:05.443886 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-test-event
178 11:45:05.444006 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-test-feedback
179 11:45:05.444125 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-test-raise
180 11:45:05.444242 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-test-reference
181 11:45:05.444362 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-test-runner
182 11:45:05.444488 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-test-set
183 11:45:05.444608 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-test-shell
184 11:45:05.444731 Updating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-add-keys (debian)
185 11:45:05.444879 Updating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-add-sources (debian)
186 11:45:05.445024 Updating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-install-packages (debian)
187 11:45:05.445164 Updating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-installed-packages (debian)
188 11:45:05.445302 Updating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/bin/lava-os-build (debian)
189 11:45:05.445423 Creating /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/environment
190 11:45:05.445521 LAVA metadata
191 11:45:05.445589 - LAVA_JOB_ID=12074003
192 11:45:05.445653 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:45:05.445752 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 11:45:05.445818 skipped lava-vland-overlay
195 11:45:05.445892 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:45:05.445970 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 11:45:05.446031 skipped lava-multinode-overlay
198 11:45:05.446103 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:45:05.446180 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 11:45:05.446254 Loading test definitions
201 11:45:05.446342 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 11:45:05.446642 Using /lava-12074003 at stage 0
203 11:45:05.446917 uuid=12074003_1.6.2.3.1 testdef=None
204 11:45:05.447007 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:45:05.447093 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 11:45:05.447531 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:45:05.447756 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 11:45:05.448298 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:45:05.448533 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 11:45:05.449076 runner path: /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/0/tests/0_timesync-off test_uuid 12074003_1.6.2.3.1
213 11:45:05.449229 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:45:05.449455 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 11:45:05.449527 Using /lava-12074003 at stage 0
217 11:45:05.449622 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:45:05.449701 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/0/tests/1_kselftest-arm64'
219 11:45:19.469867 Running '/usr/bin/git checkout kernelci.org
220 11:45:19.613991 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 11:45:19.614735 uuid=12074003_1.6.2.3.5 testdef=None
222 11:45:19.614888 end: 1.6.2.3.5 git-repo-action (duration 00:00:14) [common]
224 11:45:19.615151 start: 1.6.2.3.6 test-overlay (timeout 00:09:34) [common]
225 11:45:19.615904 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:45:19.616139 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:34) [common]
228 11:45:19.617120 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:45:19.617360 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:34) [common]
231 11:45:19.618473 runner path: /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/0/tests/1_kselftest-arm64 test_uuid 12074003_1.6.2.3.5
232 11:45:19.618570 BOARD='mt8192-asurada-spherion-r0'
233 11:45:19.618637 BRANCH='cip-gitlab'
234 11:45:19.618698 SKIPFILE='/dev/null'
235 11:45:19.618757 SKIP_INSTALL='True'
236 11:45:19.618816 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:45:19.618875 TST_CASENAME=''
238 11:45:19.618930 TST_CMDFILES='arm64'
239 11:45:19.619068 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:45:19.619276 Creating lava-test-runner.conf files
242 11:45:19.619342 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074003/lava-overlay-k2e4y_qi/lava-12074003/0 for stage 0
243 11:45:19.619435 - 0_timesync-off
244 11:45:19.619537 - 1_kselftest-arm64
245 11:45:19.619659 end: 1.6.2.3 test-definition (duration 00:00:14) [common]
246 11:45:19.619757 start: 1.6.2.4 compress-overlay (timeout 00:09:34) [common]
247 11:45:27.194065 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:45:27.194280 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:26) [common]
249 11:45:27.194379 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:45:27.194566 end: 1.6.2 lava-overlay (duration 00:00:22) [common]
251 11:45:27.194660 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:26) [common]
252 11:45:27.310564 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:45:27.310942 start: 1.6.4 extract-modules (timeout 00:09:26) [common]
254 11:45:27.311055 extracting modules file /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074003/extract-nfsrootfs-50snkza6
255 11:45:27.519081 extracting modules file /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074003/extract-overlay-ramdisk-ipqy1dso/ramdisk
256 11:45:27.734021 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:45:27.734210 start: 1.6.5 apply-overlay-tftp (timeout 00:09:26) [common]
258 11:45:27.734308 [common] Applying overlay to NFS
259 11:45:27.734387 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074003/compress-overlay-_65aa1pw/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074003/extract-nfsrootfs-50snkza6
260 11:45:28.654574 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:45:28.654756 start: 1.6.6 configure-preseed-file (timeout 00:09:25) [common]
262 11:45:28.654853 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:45:28.654947 start: 1.6.7 compress-ramdisk (timeout 00:09:25) [common]
264 11:45:28.655033 Building ramdisk /var/lib/lava/dispatcher/tmp/12074003/extract-overlay-ramdisk-ipqy1dso/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074003/extract-overlay-ramdisk-ipqy1dso/ramdisk
265 11:45:28.963143 >> 119398 blocks
266 11:45:30.917753 rename /var/lib/lava/dispatcher/tmp/12074003/extract-overlay-ramdisk-ipqy1dso/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/ramdisk/ramdisk.cpio.gz
267 11:45:30.918191 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:45:30.918323 start: 1.6.8 prepare-kernel (timeout 00:09:22) [common]
269 11:45:30.918473 start: 1.6.8.1 prepare-fit (timeout 00:09:22) [common]
270 11:45:30.918580 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/kernel/Image'
271 11:45:43.342527 Returned 0 in 12 seconds
272 11:45:43.443571 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/kernel/image.itb
273 11:45:43.798503 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:45:43.798853 output: Created: Fri Nov 24 11:45:43 2023
275 11:45:43.798933 output: Image 0 (kernel-1)
276 11:45:43.799001 output: Description:
277 11:45:43.799064 output: Created: Fri Nov 24 11:45:43 2023
278 11:45:43.799128 output: Type: Kernel Image
279 11:45:43.799191 output: Compression: lzma compressed
280 11:45:43.799250 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
281 11:45:43.799310 output: Architecture: AArch64
282 11:45:43.799370 output: OS: Linux
283 11:45:43.799431 output: Load Address: 0x00000000
284 11:45:43.799490 output: Entry Point: 0x00000000
285 11:45:43.799547 output: Hash algo: crc32
286 11:45:43.799603 output: Hash value: 43cfb6ad
287 11:45:43.799662 output: Image 1 (fdt-1)
288 11:45:43.799718 output: Description: mt8192-asurada-spherion-r0
289 11:45:43.799772 output: Created: Fri Nov 24 11:45:43 2023
290 11:45:43.799826 output: Type: Flat Device Tree
291 11:45:43.799881 output: Compression: uncompressed
292 11:45:43.799936 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:45:43.799990 output: Architecture: AArch64
294 11:45:43.800044 output: Hash algo: crc32
295 11:45:43.800098 output: Hash value: cc4352de
296 11:45:43.800151 output: Image 2 (ramdisk-1)
297 11:45:43.800205 output: Description: unavailable
298 11:45:43.800259 output: Created: Fri Nov 24 11:45:43 2023
299 11:45:43.800313 output: Type: RAMDisk Image
300 11:45:43.800368 output: Compression: Unknown Compression
301 11:45:43.800422 output: Data Size: 17801538 Bytes = 17384.31 KiB = 16.98 MiB
302 11:45:43.800477 output: Architecture: AArch64
303 11:45:43.800531 output: OS: Linux
304 11:45:43.800585 output: Load Address: unavailable
305 11:45:43.800638 output: Entry Point: unavailable
306 11:45:43.800692 output: Hash algo: crc32
307 11:45:43.800745 output: Hash value: 65fb7484
308 11:45:43.800799 output: Default Configuration: 'conf-1'
309 11:45:43.800853 output: Configuration 0 (conf-1)
310 11:45:43.800907 output: Description: mt8192-asurada-spherion-r0
311 11:45:43.800961 output: Kernel: kernel-1
312 11:45:43.801015 output: Init Ramdisk: ramdisk-1
313 11:45:43.801068 output: FDT: fdt-1
314 11:45:43.801122 output: Loadables: kernel-1
315 11:45:43.801176 output:
316 11:45:43.801370 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 11:45:43.801471 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 11:45:43.801573 end: 1.6 prepare-tftp-overlay (duration 00:00:42) [common]
319 11:45:43.801666 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:10) [common]
320 11:45:43.801750 No LXC device requested
321 11:45:43.801829 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:45:43.801916 start: 1.8 deploy-device-env (timeout 00:09:10) [common]
323 11:45:43.801994 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:45:43.802063 Checking files for TFTP limit of 4294967296 bytes.
325 11:45:43.802607 end: 1 tftp-deploy (duration 00:00:50) [common]
326 11:45:43.802719 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:45:43.802815 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:45:43.802943 substitutions:
329 11:45:43.803013 - {DTB}: 12074003/tftp-deploy-updl6c3y/dtb/mt8192-asurada-spherion-r0.dtb
330 11:45:43.803080 - {INITRD}: 12074003/tftp-deploy-updl6c3y/ramdisk/ramdisk.cpio.gz
331 11:45:43.803141 - {KERNEL}: 12074003/tftp-deploy-updl6c3y/kernel/Image
332 11:45:43.803200 - {LAVA_MAC}: None
333 11:45:43.803259 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12074003/extract-nfsrootfs-50snkza6
334 11:45:43.803318 - {NFS_SERVER_IP}: 192.168.201.1
335 11:45:43.803376 - {PRESEED_CONFIG}: None
336 11:45:43.803433 - {PRESEED_LOCAL}: None
337 11:45:43.803488 - {RAMDISK}: 12074003/tftp-deploy-updl6c3y/ramdisk/ramdisk.cpio.gz
338 11:45:43.803543 - {ROOT_PART}: None
339 11:45:43.803599 - {ROOT}: None
340 11:45:43.803655 - {SERVER_IP}: 192.168.201.1
341 11:45:43.803711 - {TEE}: None
342 11:45:43.803767 Parsed boot commands:
343 11:45:43.803822 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:45:43.803998 Parsed boot commands: tftpboot 192.168.201.1 12074003/tftp-deploy-updl6c3y/kernel/image.itb 12074003/tftp-deploy-updl6c3y/kernel/cmdline
345 11:45:43.804087 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:45:43.804176 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:45:43.804270 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:45:43.804358 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:45:43.804430 Not connected, no need to disconnect.
350 11:45:43.804504 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:45:43.804585 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:45:43.804653 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 11:45:43.807970 Setting prompt string to ['lava-test: # ']
354 11:45:43.808303 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:45:43.808419 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:45:43.808529 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:45:43.808623 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:45:43.808821 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 11:45:48.941534 >> Command sent successfully.
360 11:45:48.943893 Returned 0 in 5 seconds
361 11:45:49.044257 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:45:49.044596 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:45:49.044707 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:45:49.044799 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:45:49.044871 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:45:49.044946 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:45:49.045231 [Enter `^Ec?' for help]
369 11:45:49.218933
370 11:45:49.219078
371 11:45:49.219157 F0: 102B 0000
372 11:45:49.219225
373 11:45:49.219289 F3: 1001 0000 [0200]
374 11:45:49.219357
375 11:45:49.223254 F3: 1001 0000
376 11:45:49.223336
377 11:45:49.223403 F7: 102D 0000
378 11:45:49.223475
379 11:45:49.223540 F1: 0000 0000
380 11:45:49.223600
381 11:45:49.226872 V0: 0000 0000 [0001]
382 11:45:49.226954
383 11:45:49.227021 00: 0007 8000
384 11:45:49.227088
385 11:45:49.230476 01: 0000 0000
386 11:45:49.230561
387 11:45:49.230625 BP: 0C00 0209 [0000]
388 11:45:49.230696
389 11:45:49.230763 G0: 1182 0000
390 11:45:49.234272
391 11:45:49.234343 EC: 0000 0021 [4000]
392 11:45:49.234429
393 11:45:49.234512 S7: 0000 0000 [0000]
394 11:45:49.238202
395 11:45:49.238315 CC: 0000 0000 [0001]
396 11:45:49.238428
397 11:45:49.238496 T0: 0000 0040 [010F]
398 11:45:49.241460
399 11:45:49.241545 Jump to BL
400 11:45:49.241612
401 11:45:49.266064
402 11:45:49.266161
403 11:45:49.266244
404 11:45:49.272867 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:45:49.276686 ARM64: Exception handlers installed.
406 11:45:49.280110 ARM64: Testing exception
407 11:45:49.283976 ARM64: Done test exception
408 11:45:49.291458 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:45:49.302008 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:45:49.309012 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:45:49.316276 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:45:49.326131 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:45:49.332866 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:45:49.342921 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:45:49.349766 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:45:49.368701 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:45:49.371884 WDT: Last reset was cold boot
418 11:45:49.375422 SPI1(PAD0) initialized at 2873684 Hz
419 11:45:49.379115 SPI5(PAD0) initialized at 992727 Hz
420 11:45:49.382147 VBOOT: Loading verstage.
421 11:45:49.388636 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:45:49.392478 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:45:49.395738 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:45:49.398949 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:45:49.405957 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:45:49.412680 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:45:49.423778 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 11:45:49.423865
429 11:45:49.423941
430 11:45:49.433995 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:45:49.437274 ARM64: Exception handlers installed.
432 11:45:49.440663 ARM64: Testing exception
433 11:45:49.440775 ARM64: Done test exception
434 11:45:49.447013 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:45:49.450572 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:45:49.464703 Probing TPM: . done!
437 11:45:49.464791 TPM ready after 0 ms
438 11:45:49.471445 Connected to device vid:did:rid of 1ae0:0028:00
439 11:45:49.478609 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 11:45:49.534015 Initialized TPM device CR50 revision 0
441 11:45:49.546152 tlcl_send_startup: Startup return code is 0
442 11:45:49.546244 TPM: setup succeeded
443 11:45:49.557803 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:45:49.566554 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:45:49.576956 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:45:49.586252 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:45:49.589451 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:45:49.598656 in-header: 03 07 00 00 08 00 00 00
449 11:45:49.601402 in-data: aa e4 47 04 13 02 00 00
450 11:45:49.605151 Chrome EC: UHEPI supported
451 11:45:49.612342 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:45:49.616337 in-header: 03 ad 00 00 08 00 00 00
453 11:45:49.619760 in-data: 00 20 20 08 00 00 00 00
454 11:45:49.619847 Phase 1
455 11:45:49.623692 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:45:49.631404 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:45:49.635167 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:45:49.639092 Recovery requested (1009000e)
459 11:45:49.647951 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:45:49.653605 tlcl_extend: response is 0
461 11:45:49.662441 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:45:49.668619 tlcl_extend: response is 0
463 11:45:49.675758 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:45:49.695550 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 11:45:49.702331 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:45:49.702462
467 11:45:49.702532
468 11:45:49.712446 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:45:49.715943 ARM64: Exception handlers installed.
470 11:45:49.716030 ARM64: Testing exception
471 11:45:49.719357 ARM64: Done test exception
472 11:45:49.740937 pmic_efuse_setting: Set efuses in 11 msecs
473 11:45:49.744243 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:45:49.750985 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:45:49.754640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:45:49.758003 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:45:49.764499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:45:49.767831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:45:49.775728 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:45:49.779451 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:45:49.782975 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:45:49.786788 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:45:49.794747 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:45:49.797943 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:45:49.802030 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:45:49.805047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:45:49.812260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:45:49.818488 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:45:49.825878 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:45:49.829375 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:45:49.837207 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:45:49.840799 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:45:49.847560 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:45:49.851130 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:45:49.858204 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:45:49.865816 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:45:49.868494 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:45:49.875047 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:45:49.878731 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:45:49.885128 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:45:49.888276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:45:49.895059 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:45:49.898694 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:45:49.905074 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:45:49.908483 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:45:49.915205 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:45:49.918515 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:45:49.925040 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:45:49.928488 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:45:49.936096 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:45:49.938866 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:45:49.945268 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:45:49.948439 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:45:49.951760 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:45:49.959086 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:45:49.962848 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:45:49.966636 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:45:49.969710 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:45:49.973558 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:45:49.979861 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:45:49.983298 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:45:49.986358 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:45:49.990068 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:45:49.996340 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:45:50.003076 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:45:50.013447 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:45:50.016582 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:45:50.023732 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:45:50.033491 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:45:50.036768 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:45:50.043193 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:45:50.046815 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:45:50.053341 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 11:45:50.060043 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:45:50.063152 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:45:50.066498 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:45:50.078218 [RTC]rtc_get_frequency_meter,154: input=15, output=773
538 11:45:50.086978 [RTC]rtc_get_frequency_meter,154: input=23, output=958
539 11:45:50.096787 [RTC]rtc_get_frequency_meter,154: input=19, output=867
540 11:45:50.106156 [RTC]rtc_get_frequency_meter,154: input=17, output=818
541 11:45:50.116696 [RTC]rtc_get_frequency_meter,154: input=16, output=794
542 11:45:50.120305 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 11:45:50.123778 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 11:45:50.127676 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 11:45:50.131721 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 11:45:50.135695 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 11:45:50.139089 ADC[4]: Raw value=902876 ID=7
548 11:45:50.143047 ADC[3]: Raw value=213179 ID=1
549 11:45:50.143134 RAM Code: 0x71
550 11:45:50.150306 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 11:45:50.153756 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 11:45:50.161250 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 11:45:50.168554 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 11:45:50.172855 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 11:45:50.175785 in-header: 03 07 00 00 08 00 00 00
556 11:45:50.179325 in-data: aa e4 47 04 13 02 00 00
557 11:45:50.182666 Chrome EC: UHEPI supported
558 11:45:50.189401 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 11:45:50.192709 in-header: 03 ed 00 00 08 00 00 00
560 11:45:50.195841 in-data: 80 20 60 08 00 00 00 00
561 11:45:50.199219 MRC: failed to locate region type 0.
562 11:45:50.205924 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 11:45:50.206011 DRAM-K: Running full calibration
564 11:45:50.212576 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 11:45:50.216194 header.status = 0x0
566 11:45:50.219244 header.version = 0x6 (expected: 0x6)
567 11:45:50.222370 header.size = 0xd00 (expected: 0xd00)
568 11:45:50.222498 header.flags = 0x0
569 11:45:50.229383 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 11:45:50.248485 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
571 11:45:50.255188 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 11:45:50.258483 dram_init: ddr_geometry: 2
573 11:45:50.258570 [EMI] MDL number = 2
574 11:45:50.261795 [EMI] Get MDL freq = 0
575 11:45:50.261881 dram_init: ddr_type: 0
576 11:45:50.265225 is_discrete_lpddr4: 1
577 11:45:50.268581 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 11:45:50.268668
579 11:45:50.268735
580 11:45:50.271976 [Bian_co] ETT version 0.0.0.1
581 11:45:50.275536 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 11:45:50.275626
583 11:45:50.282354 dramc_set_vcore_voltage set vcore to 650000
584 11:45:50.282484 Read voltage for 800, 4
585 11:45:50.282554 Vio18 = 0
586 11:45:50.285493 Vcore = 650000
587 11:45:50.285579 Vdram = 0
588 11:45:50.285647 Vddq = 0
589 11:45:50.289038 Vmddr = 0
590 11:45:50.289124 dram_init: config_dvfs: 1
591 11:45:50.295446 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 11:45:50.298849 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 11:45:50.305718 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
594 11:45:50.308924 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
595 11:45:50.312320 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 11:45:50.315803 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 11:45:50.318806 MEM_TYPE=3, freq_sel=18
598 11:45:50.322309 sv_algorithm_assistance_LP4_1600
599 11:45:50.325850 ============ PULL DRAM RESETB DOWN ============
600 11:45:50.328744 ========== PULL DRAM RESETB DOWN end =========
601 11:45:50.332243 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 11:45:50.335798 ===================================
603 11:45:50.338967 LPDDR4 DRAM CONFIGURATION
604 11:45:50.342038 ===================================
605 11:45:50.345631 EX_ROW_EN[0] = 0x0
606 11:45:50.345717 EX_ROW_EN[1] = 0x0
607 11:45:50.349016 LP4Y_EN = 0x0
608 11:45:50.349103 WORK_FSP = 0x0
609 11:45:50.352258 WL = 0x2
610 11:45:50.352344 RL = 0x2
611 11:45:50.355964 BL = 0x2
612 11:45:50.356051 RPST = 0x0
613 11:45:50.358978 RD_PRE = 0x0
614 11:45:50.359064 WR_PRE = 0x1
615 11:45:50.362611 WR_PST = 0x0
616 11:45:50.362697 DBI_WR = 0x0
617 11:45:50.365698 DBI_RD = 0x0
618 11:45:50.369037 OTF = 0x1
619 11:45:50.369154 ===================================
620 11:45:50.372544 ===================================
621 11:45:50.375657 ANA top config
622 11:45:50.378886 ===================================
623 11:45:50.382510 DLL_ASYNC_EN = 0
624 11:45:50.382597 ALL_SLAVE_EN = 1
625 11:45:50.385880 NEW_RANK_MODE = 1
626 11:45:50.388997 DLL_IDLE_MODE = 1
627 11:45:50.392291 LP45_APHY_COMB_EN = 1
628 11:45:50.395700 TX_ODT_DIS = 1
629 11:45:50.395786 NEW_8X_MODE = 1
630 11:45:50.398959 ===================================
631 11:45:50.402525 ===================================
632 11:45:50.405847 data_rate = 1600
633 11:45:50.409346 CKR = 1
634 11:45:50.412504 DQ_P2S_RATIO = 8
635 11:45:50.415565 ===================================
636 11:45:50.419079 CA_P2S_RATIO = 8
637 11:45:50.419165 DQ_CA_OPEN = 0
638 11:45:50.422261 DQ_SEMI_OPEN = 0
639 11:45:50.425752 CA_SEMI_OPEN = 0
640 11:45:50.429224 CA_FULL_RATE = 0
641 11:45:50.432502 DQ_CKDIV4_EN = 1
642 11:45:50.435716 CA_CKDIV4_EN = 1
643 11:45:50.435832 CA_PREDIV_EN = 0
644 11:45:50.439396 PH8_DLY = 0
645 11:45:50.442620 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 11:45:50.445971 DQ_AAMCK_DIV = 4
647 11:45:50.449284 CA_AAMCK_DIV = 4
648 11:45:50.449370 CA_ADMCK_DIV = 4
649 11:45:50.452794 DQ_TRACK_CA_EN = 0
650 11:45:50.456094 CA_PICK = 800
651 11:45:50.459481 CA_MCKIO = 800
652 11:45:50.462618 MCKIO_SEMI = 0
653 11:45:50.465816 PLL_FREQ = 3068
654 11:45:50.469310 DQ_UI_PI_RATIO = 32
655 11:45:50.469397 CA_UI_PI_RATIO = 0
656 11:45:50.472646 ===================================
657 11:45:50.476418 ===================================
658 11:45:50.479413 memory_type:LPDDR4
659 11:45:50.482641 GP_NUM : 10
660 11:45:50.482727 SRAM_EN : 1
661 11:45:50.486359 MD32_EN : 0
662 11:45:50.489742 ===================================
663 11:45:50.493738 [ANA_INIT] >>>>>>>>>>>>>>
664 11:45:50.493824 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 11:45:50.497664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 11:45:50.501289 ===================================
667 11:45:50.504772 data_rate = 1600,PCW = 0X7600
668 11:45:50.508553 ===================================
669 11:45:50.512075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 11:45:50.515777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 11:45:50.522886 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 11:45:50.527000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 11:45:50.529960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 11:45:50.533508 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 11:45:50.533596 [ANA_INIT] flow start
676 11:45:50.536804 [ANA_INIT] PLL >>>>>>>>
677 11:45:50.540032 [ANA_INIT] PLL <<<<<<<<
678 11:45:50.543543 [ANA_INIT] MIDPI >>>>>>>>
679 11:45:50.543629 [ANA_INIT] MIDPI <<<<<<<<
680 11:45:50.546673 [ANA_INIT] DLL >>>>>>>>
681 11:45:50.551123 [ANA_INIT] flow end
682 11:45:50.554439 ============ LP4 DIFF to SE enter ============
683 11:45:50.558066 ============ LP4 DIFF to SE exit ============
684 11:45:50.558159 [ANA_INIT] <<<<<<<<<<<<<
685 11:45:50.562074 [Flow] Enable top DCM control >>>>>
686 11:45:50.565308 [Flow] Enable top DCM control <<<<<
687 11:45:50.569033 Enable DLL master slave shuffle
688 11:45:50.573025 ==============================================================
689 11:45:50.576870 Gating Mode config
690 11:45:50.580447 ==============================================================
691 11:45:50.583707 Config description:
692 11:45:50.594787 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 11:45:50.598158 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 11:45:50.605489 SELPH_MODE 0: By rank 1: By Phase
695 11:45:50.608880 ==============================================================
696 11:45:50.612612 GAT_TRACK_EN = 1
697 11:45:50.616818 RX_GATING_MODE = 2
698 11:45:50.620118 RX_GATING_TRACK_MODE = 2
699 11:45:50.624135 SELPH_MODE = 1
700 11:45:50.624222 PICG_EARLY_EN = 1
701 11:45:50.627583 VALID_LAT_VALUE = 1
702 11:45:50.634716 ==============================================================
703 11:45:50.638372 Enter into Gating configuration >>>>
704 11:45:50.638481 Exit from Gating configuration <<<<
705 11:45:50.642793 Enter into DVFS_PRE_config >>>>>
706 11:45:50.653635 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 11:45:50.657362 Exit from DVFS_PRE_config <<<<<
708 11:45:50.661055 Enter into PICG configuration >>>>
709 11:45:50.664842 Exit from PICG configuration <<<<
710 11:45:50.668195 [RX_INPUT] configuration >>>>>
711 11:45:50.668282 [RX_INPUT] configuration <<<<<
712 11:45:50.675638 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 11:45:50.679624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 11:45:50.687108 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 11:45:50.694361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 11:45:50.698152 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 11:45:50.706146 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 11:45:50.710057 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 11:45:50.713562 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 11:45:50.717081 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 11:45:50.721159 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 11:45:50.724590 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 11:45:50.728420 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 11:45:50.731791 ===================================
725 11:45:50.735363 LPDDR4 DRAM CONFIGURATION
726 11:45:50.739386 ===================================
727 11:45:50.739480 EX_ROW_EN[0] = 0x0
728 11:45:50.743189 EX_ROW_EN[1] = 0x0
729 11:45:50.743266 LP4Y_EN = 0x0
730 11:45:50.746364 WORK_FSP = 0x0
731 11:45:50.746482 WL = 0x2
732 11:45:50.750449 RL = 0x2
733 11:45:50.750533 BL = 0x2
734 11:45:50.754285 RPST = 0x0
735 11:45:50.754369 RD_PRE = 0x0
736 11:45:50.757500 WR_PRE = 0x1
737 11:45:50.757585 WR_PST = 0x0
738 11:45:50.761325 DBI_WR = 0x0
739 11:45:50.761442 DBI_RD = 0x0
740 11:45:50.765437 OTF = 0x1
741 11:45:50.765522 ===================================
742 11:45:50.768928 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 11:45:50.776208 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 11:45:50.780279 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 11:45:50.784027 ===================================
746 11:45:50.784139 LPDDR4 DRAM CONFIGURATION
747 11:45:50.787400 ===================================
748 11:45:50.791230 EX_ROW_EN[0] = 0x10
749 11:45:50.791338 EX_ROW_EN[1] = 0x0
750 11:45:50.794847 LP4Y_EN = 0x0
751 11:45:50.794932 WORK_FSP = 0x0
752 11:45:50.799026 WL = 0x2
753 11:45:50.799110 RL = 0x2
754 11:45:50.802006 BL = 0x2
755 11:45:50.802120 RPST = 0x0
756 11:45:50.805949 RD_PRE = 0x0
757 11:45:50.806034 WR_PRE = 0x1
758 11:45:50.806101 WR_PST = 0x0
759 11:45:50.809864 DBI_WR = 0x0
760 11:45:50.809948 DBI_RD = 0x0
761 11:45:50.813512 OTF = 0x1
762 11:45:50.817300 ===================================
763 11:45:50.821109 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 11:45:50.826416 nWR fixed to 40
765 11:45:50.830014 [ModeRegInit_LP4] CH0 RK0
766 11:45:50.830099 [ModeRegInit_LP4] CH0 RK1
767 11:45:50.833625 [ModeRegInit_LP4] CH1 RK0
768 11:45:50.833710 [ModeRegInit_LP4] CH1 RK1
769 11:45:50.837222 match AC timing 13
770 11:45:50.841210 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 11:45:50.845165 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 11:45:50.848641 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 11:45:50.856119 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 11:45:50.859485 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 11:45:50.859571 [EMI DOE] emi_dcm 0
776 11:45:50.866310 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 11:45:50.866427 ==
778 11:45:50.869674 Dram Type= 6, Freq= 0, CH_0, rank 0
779 11:45:50.872849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 11:45:50.872940 ==
781 11:45:50.879730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 11:45:50.883033 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 11:45:50.893266 [CA 0] Center 38 (7~69) winsize 63
784 11:45:50.896725 [CA 1] Center 38 (7~69) winsize 63
785 11:45:50.900061 [CA 2] Center 35 (5~66) winsize 62
786 11:45:50.903848 [CA 3] Center 35 (5~66) winsize 62
787 11:45:50.906767 [CA 4] Center 34 (4~65) winsize 62
788 11:45:50.910136 [CA 5] Center 33 (3~64) winsize 62
789 11:45:50.910220
790 11:45:50.913497 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 11:45:50.913581
792 11:45:50.916982 [CATrainingPosCal] consider 1 rank data
793 11:45:50.920111 u2DelayCellTimex100 = 270/100 ps
794 11:45:50.923908 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 11:45:50.927031 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 11:45:50.930685 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 11:45:50.937218 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 11:45:50.940690 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 11:45:50.943857 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 11:45:50.943941
801 11:45:50.947187 CA PerBit enable=1, Macro0, CA PI delay=33
802 11:45:50.947272
803 11:45:50.950569 [CBTSetCACLKResult] CA Dly = 33
804 11:45:50.950653 CS Dly: 5 (0~36)
805 11:45:50.950720 ==
806 11:45:50.953901 Dram Type= 6, Freq= 0, CH_0, rank 1
807 11:45:50.960509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 11:45:50.960595 ==
809 11:45:50.964115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 11:45:50.970312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 11:45:50.980079 [CA 0] Center 38 (7~69) winsize 63
812 11:45:50.983203 [CA 1] Center 38 (7~69) winsize 63
813 11:45:50.986827 [CA 2] Center 36 (6~67) winsize 62
814 11:45:50.989997 [CA 3] Center 35 (5~66) winsize 62
815 11:45:50.993528 [CA 4] Center 35 (4~66) winsize 63
816 11:45:50.996515 [CA 5] Center 34 (4~65) winsize 62
817 11:45:50.996599
818 11:45:50.999858 [CmdBusTrainingLP45] Vref(ca) range 1: 34
819 11:45:50.999943
820 11:45:51.003573 [CATrainingPosCal] consider 2 rank data
821 11:45:51.006770 u2DelayCellTimex100 = 270/100 ps
822 11:45:51.009805 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 11:45:51.013175 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 11:45:51.020001 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 11:45:51.023147 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 11:45:51.026982 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 11:45:51.030345 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 11:45:51.030476
829 11:45:51.033613 CA PerBit enable=1, Macro0, CA PI delay=34
830 11:45:51.033698
831 11:45:51.036850 [CBTSetCACLKResult] CA Dly = 34
832 11:45:51.036935 CS Dly: 6 (0~38)
833 11:45:51.037002
834 11:45:51.040106 ----->DramcWriteLeveling(PI) begin...
835 11:45:51.043366 ==
836 11:45:51.043451 Dram Type= 6, Freq= 0, CH_0, rank 0
837 11:45:51.050104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 11:45:51.050189 ==
839 11:45:51.053597 Write leveling (Byte 0): 32 => 32
840 11:45:51.056660 Write leveling (Byte 1): 28 => 28
841 11:45:51.056744 DramcWriteLeveling(PI) end<-----
842 11:45:51.060518
843 11:45:51.060629 ==
844 11:45:51.063696 Dram Type= 6, Freq= 0, CH_0, rank 0
845 11:45:51.067034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 11:45:51.067113 ==
847 11:45:51.070099 [Gating] SW mode calibration
848 11:45:51.077674 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 11:45:51.081398 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 11:45:51.085159 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 11:45:51.089083 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
852 11:45:51.095816 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:45:51.099036 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:45:51.102984 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:45:51.106270 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:45:51.112982 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:45:51.116417 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:45:51.119650 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:45:51.126578 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:45:51.129614 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:45:51.132993 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:45:51.140001 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:45:51.143175 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:45:51.146159 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:45:51.152849 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:45:51.156124 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 11:45:51.159542 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
868 11:45:51.166827 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
869 11:45:51.169832 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:45:51.172907 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:45:51.180233 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 11:45:51.183161 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:45:51.186909 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:45:51.189568 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:45:51.196438 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
876 11:45:51.199793 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
877 11:45:51.202999 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
878 11:45:51.210096 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 11:45:51.212997 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 11:45:51.216866 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 11:45:51.223403 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:45:51.226723 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
883 11:45:51.229930 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
884 11:45:51.236764 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
885 11:45:51.239880 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 11:45:51.243258 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 11:45:51.250180 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 11:45:51.253200 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 11:45:51.256608 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:45:51.263315 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:45:51.266684 0 11 4 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
892 11:45:51.270130 0 11 8 | B1->B0 | 2f2f 4646 | 1 0 | (1 1) (0 0)
893 11:45:51.273377 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
894 11:45:51.280170 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 11:45:51.283182 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 11:45:51.286755 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 11:45:51.293382 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:45:51.296577 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:45:51.300272 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 11:45:51.306744 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
901 11:45:51.310354 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:45:51.313794 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:45:51.320267 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:45:51.323694 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:45:51.327105 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:45:51.330558 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:45:51.336983 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:45:51.340686 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:45:51.344027 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:45:51.350375 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:45:51.353739 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:45:51.357193 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:45:51.363621 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:45:51.366906 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:45:51.370609 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 11:45:51.377356 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 11:45:51.377439 Total UI for P1: 0, mck2ui 16
918 11:45:51.384029 best dqsien dly found for B0: ( 0, 14, 4)
919 11:45:51.384116 Total UI for P1: 0, mck2ui 16
920 11:45:51.387439 best dqsien dly found for B1: ( 0, 14, 6)
921 11:45:51.393775 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
922 11:45:51.397123 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
923 11:45:51.397201
924 11:45:51.400848 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
925 11:45:51.403873 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
926 11:45:51.407410 [Gating] SW calibration Done
927 11:45:51.407489 ==
928 11:45:51.410864 Dram Type= 6, Freq= 0, CH_0, rank 0
929 11:45:51.414245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 11:45:51.414328 ==
931 11:45:51.414420 RX Vref Scan: 0
932 11:45:51.414495
933 11:45:51.417665 RX Vref 0 -> 0, step: 1
934 11:45:51.417747
935 11:45:51.420632 RX Delay -130 -> 252, step: 16
936 11:45:51.424171 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
937 11:45:51.427598 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
938 11:45:51.433973 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
939 11:45:51.437589 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
940 11:45:51.440681 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
941 11:45:51.444404 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
942 11:45:51.447837 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
943 11:45:51.454373 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
944 11:45:51.457853 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
945 11:45:51.461090 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
946 11:45:51.464429 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
947 11:45:51.467740 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
948 11:45:51.474368 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
949 11:45:51.477622 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
950 11:45:51.480813 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
951 11:45:51.484673 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
952 11:45:51.484767 ==
953 11:45:51.488051 Dram Type= 6, Freq= 0, CH_0, rank 0
954 11:45:51.491278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
955 11:45:51.494711 ==
956 11:45:51.494790 DQS Delay:
957 11:45:51.494864 DQS0 = 0, DQS1 = 0
958 11:45:51.497692 DQM Delay:
959 11:45:51.497767 DQM0 = 96, DQM1 = 84
960 11:45:51.501400 DQ Delay:
961 11:45:51.501480 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
962 11:45:51.504710 DQ4 =93, DQ5 =93, DQ6 =109, DQ7 =101
963 11:45:51.507843 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =85
964 11:45:51.511235 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
965 11:45:51.511329
966 11:45:51.514347
967 11:45:51.514478 ==
968 11:45:51.517763 Dram Type= 6, Freq= 0, CH_0, rank 0
969 11:45:51.521265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 11:45:51.521352 ==
971 11:45:51.521438
972 11:45:51.521519
973 11:45:51.524643 TX Vref Scan disable
974 11:45:51.524729 == TX Byte 0 ==
975 11:45:51.531033 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
976 11:45:51.534969 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
977 11:45:51.535056 == TX Byte 1 ==
978 11:45:51.541378 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
979 11:45:51.544647 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
980 11:45:51.544733 ==
981 11:45:51.547889 Dram Type= 6, Freq= 0, CH_0, rank 0
982 11:45:51.551070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 11:45:51.551157 ==
984 11:45:51.565004 TX Vref=22, minBit 8, minWin=26, winSum=436
985 11:45:51.568131 TX Vref=24, minBit 6, minWin=27, winSum=444
986 11:45:51.571698 TX Vref=26, minBit 10, minWin=27, winSum=447
987 11:45:51.575126 TX Vref=28, minBit 0, minWin=28, winSum=452
988 11:45:51.578330 TX Vref=30, minBit 8, minWin=27, winSum=452
989 11:45:51.585370 TX Vref=32, minBit 11, minWin=27, winSum=455
990 11:45:51.588708 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 28
991 11:45:51.588793
992 11:45:51.592206 Final TX Range 1 Vref 28
993 11:45:51.592318
994 11:45:51.592413 ==
995 11:45:51.595451 Dram Type= 6, Freq= 0, CH_0, rank 0
996 11:45:51.599055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 11:45:51.599141 ==
998 11:45:51.599208
999 11:45:51.601958
1000 11:45:51.602042 TX Vref Scan disable
1001 11:45:51.605360 == TX Byte 0 ==
1002 11:45:51.608499 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1003 11:45:51.611804 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1004 11:45:51.615227 == TX Byte 1 ==
1005 11:45:51.618292 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1006 11:45:51.621766 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1007 11:45:51.624983
1008 11:45:51.625093 [DATLAT]
1009 11:45:51.625190 Freq=800, CH0 RK0
1010 11:45:51.625287
1011 11:45:51.628544 DATLAT Default: 0xa
1012 11:45:51.628654 0, 0xFFFF, sum = 0
1013 11:45:51.631873 1, 0xFFFF, sum = 0
1014 11:45:51.631980 2, 0xFFFF, sum = 0
1015 11:45:51.635181 3, 0xFFFF, sum = 0
1016 11:45:51.635279 4, 0xFFFF, sum = 0
1017 11:45:51.638696 5, 0xFFFF, sum = 0
1018 11:45:51.638809 6, 0xFFFF, sum = 0
1019 11:45:51.641906 7, 0xFFFF, sum = 0
1020 11:45:51.645424 8, 0xFFFF, sum = 0
1021 11:45:51.645510 9, 0x0, sum = 1
1022 11:45:51.645582 10, 0x0, sum = 2
1023 11:45:51.648659 11, 0x0, sum = 3
1024 11:45:51.648772 12, 0x0, sum = 4
1025 11:45:51.652015 best_step = 10
1026 11:45:51.652129
1027 11:45:51.652224 ==
1028 11:45:51.655201 Dram Type= 6, Freq= 0, CH_0, rank 0
1029 11:45:51.658701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1030 11:45:51.658785 ==
1031 11:45:51.662007 RX Vref Scan: 1
1032 11:45:51.662095
1033 11:45:51.662161 Set Vref Range= 32 -> 127
1034 11:45:51.662222
1035 11:45:51.665126 RX Vref 32 -> 127, step: 1
1036 11:45:51.665234
1037 11:45:51.668528 RX Delay -79 -> 252, step: 8
1038 11:45:51.668636
1039 11:45:51.672152 Set Vref, RX VrefLevel [Byte0]: 32
1040 11:45:51.675345 [Byte1]: 32
1041 11:45:51.675428
1042 11:45:51.678689 Set Vref, RX VrefLevel [Byte0]: 33
1043 11:45:51.681807 [Byte1]: 33
1044 11:45:51.685329
1045 11:45:51.685437 Set Vref, RX VrefLevel [Byte0]: 34
1046 11:45:51.689111 [Byte1]: 34
1047 11:45:51.692652
1048 11:45:51.692761 Set Vref, RX VrefLevel [Byte0]: 35
1049 11:45:51.696242 [Byte1]: 35
1050 11:45:51.700410
1051 11:45:51.700519 Set Vref, RX VrefLevel [Byte0]: 36
1052 11:45:51.703880 [Byte1]: 36
1053 11:45:51.707801
1054 11:45:51.707885 Set Vref, RX VrefLevel [Byte0]: 37
1055 11:45:51.711332 [Byte1]: 37
1056 11:45:51.715707
1057 11:45:51.715816 Set Vref, RX VrefLevel [Byte0]: 38
1058 11:45:51.718970 [Byte1]: 38
1059 11:45:51.723732
1060 11:45:51.723844 Set Vref, RX VrefLevel [Byte0]: 39
1061 11:45:51.727022 [Byte1]: 39
1062 11:45:51.730731
1063 11:45:51.730840 Set Vref, RX VrefLevel [Byte0]: 40
1064 11:45:51.733917 [Byte1]: 40
1065 11:45:51.738304
1066 11:45:51.738394 Set Vref, RX VrefLevel [Byte0]: 41
1067 11:45:51.741494 [Byte1]: 41
1068 11:45:51.746097
1069 11:45:51.746205 Set Vref, RX VrefLevel [Byte0]: 42
1070 11:45:51.749651 [Byte1]: 42
1071 11:45:51.753968
1072 11:45:51.754077 Set Vref, RX VrefLevel [Byte0]: 43
1073 11:45:51.757202 [Byte1]: 43
1074 11:45:51.761071
1075 11:45:51.761154 Set Vref, RX VrefLevel [Byte0]: 44
1076 11:45:51.764675 [Byte1]: 44
1077 11:45:51.768621
1078 11:45:51.768734 Set Vref, RX VrefLevel [Byte0]: 45
1079 11:45:51.771758 [Byte1]: 45
1080 11:45:51.777115
1081 11:45:51.777225 Set Vref, RX VrefLevel [Byte0]: 46
1082 11:45:51.779905 [Byte1]: 46
1083 11:45:51.783902
1084 11:45:51.784005 Set Vref, RX VrefLevel [Byte0]: 47
1085 11:45:51.786797 [Byte1]: 47
1086 11:45:51.790809
1087 11:45:51.790892 Set Vref, RX VrefLevel [Byte0]: 48
1088 11:45:51.794420 [Byte1]: 48
1089 11:45:51.798500
1090 11:45:51.798609 Set Vref, RX VrefLevel [Byte0]: 49
1091 11:45:51.801686 [Byte1]: 49
1092 11:45:51.805865
1093 11:45:51.805973 Set Vref, RX VrefLevel [Byte0]: 50
1094 11:45:51.809146 [Byte1]: 50
1095 11:45:51.813825
1096 11:45:51.813934 Set Vref, RX VrefLevel [Byte0]: 51
1097 11:45:51.816885 [Byte1]: 51
1098 11:45:51.820916
1099 11:45:51.821025 Set Vref, RX VrefLevel [Byte0]: 52
1100 11:45:51.824147 [Byte1]: 52
1101 11:45:51.828437
1102 11:45:51.828547 Set Vref, RX VrefLevel [Byte0]: 53
1103 11:45:51.831942 [Byte1]: 53
1104 11:45:51.836279
1105 11:45:51.836387 Set Vref, RX VrefLevel [Byte0]: 54
1106 11:45:51.839295 [Byte1]: 54
1107 11:45:51.843554
1108 11:45:51.843657 Set Vref, RX VrefLevel [Byte0]: 55
1109 11:45:51.847302 [Byte1]: 55
1110 11:45:51.851561
1111 11:45:51.851670 Set Vref, RX VrefLevel [Byte0]: 56
1112 11:45:51.854732 [Byte1]: 56
1113 11:45:51.859064
1114 11:45:51.859171 Set Vref, RX VrefLevel [Byte0]: 57
1115 11:45:51.862272 [Byte1]: 57
1116 11:45:51.866497
1117 11:45:51.866608 Set Vref, RX VrefLevel [Byte0]: 58
1118 11:45:51.869910 [Byte1]: 58
1119 11:45:51.873823
1120 11:45:51.873928 Set Vref, RX VrefLevel [Byte0]: 59
1121 11:45:51.877138 [Byte1]: 59
1122 11:45:51.881451
1123 11:45:51.881564 Set Vref, RX VrefLevel [Byte0]: 60
1124 11:45:51.884734 [Byte1]: 60
1125 11:45:51.889098
1126 11:45:51.892266 Set Vref, RX VrefLevel [Byte0]: 61
1127 11:45:51.895437 [Byte1]: 61
1128 11:45:51.895521
1129 11:45:51.899093 Set Vref, RX VrefLevel [Byte0]: 62
1130 11:45:51.902146 [Byte1]: 62
1131 11:45:51.902244
1132 11:45:51.905709 Set Vref, RX VrefLevel [Byte0]: 63
1133 11:45:51.909288 [Byte1]: 63
1134 11:45:51.909397
1135 11:45:51.912527 Set Vref, RX VrefLevel [Byte0]: 64
1136 11:45:51.916041 [Byte1]: 64
1137 11:45:51.919396
1138 11:45:51.919479 Set Vref, RX VrefLevel [Byte0]: 65
1139 11:45:51.922596 [Byte1]: 65
1140 11:45:51.926677
1141 11:45:51.926795 Set Vref, RX VrefLevel [Byte0]: 66
1142 11:45:51.930082 [Byte1]: 66
1143 11:45:51.934309
1144 11:45:51.934459 Set Vref, RX VrefLevel [Byte0]: 67
1145 11:45:51.937700 [Byte1]: 67
1146 11:45:51.941878
1147 11:45:51.941990 Set Vref, RX VrefLevel [Byte0]: 68
1148 11:45:51.945264 [Byte1]: 68
1149 11:45:51.949551
1150 11:45:51.949670 Set Vref, RX VrefLevel [Byte0]: 69
1151 11:45:51.952667 [Byte1]: 69
1152 11:45:51.956849
1153 11:45:51.956958 Set Vref, RX VrefLevel [Byte0]: 70
1154 11:45:51.960697 [Byte1]: 70
1155 11:45:51.964726
1156 11:45:51.964809 Set Vref, RX VrefLevel [Byte0]: 71
1157 11:45:51.968120 [Byte1]: 71
1158 11:45:51.972071
1159 11:45:51.972189 Set Vref, RX VrefLevel [Byte0]: 72
1160 11:45:51.975269 [Byte1]: 72
1161 11:45:51.979896
1162 11:45:51.979979 Set Vref, RX VrefLevel [Byte0]: 73
1163 11:45:51.982857 [Byte1]: 73
1164 11:45:51.987218
1165 11:45:51.987302 Set Vref, RX VrefLevel [Byte0]: 74
1166 11:45:51.990755 [Byte1]: 74
1167 11:45:51.995050
1168 11:45:51.995133 Set Vref, RX VrefLevel [Byte0]: 75
1169 11:45:51.997948 [Byte1]: 75
1170 11:45:52.002257
1171 11:45:52.002366 Set Vref, RX VrefLevel [Byte0]: 76
1172 11:45:52.005546 [Byte1]: 76
1173 11:45:52.010138
1174 11:45:52.010247 Final RX Vref Byte 0 = 60 to rank0
1175 11:45:52.013342 Final RX Vref Byte 1 = 57 to rank0
1176 11:45:52.016424 Final RX Vref Byte 0 = 60 to rank1
1177 11:45:52.019731 Final RX Vref Byte 1 = 57 to rank1==
1178 11:45:52.023166 Dram Type= 6, Freq= 0, CH_0, rank 0
1179 11:45:52.030217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1180 11:45:52.030327 ==
1181 11:45:52.030453 DQS Delay:
1182 11:45:52.030517 DQS0 = 0, DQS1 = 0
1183 11:45:52.032956 DQM Delay:
1184 11:45:52.033070 DQM0 = 93, DQM1 = 83
1185 11:45:52.036485 DQ Delay:
1186 11:45:52.039932 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1187 11:45:52.043043 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1188 11:45:52.043128 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1189 11:45:52.049993 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1190 11:45:52.050101
1191 11:45:52.050195
1192 11:45:52.057049 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a35, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1193 11:45:52.060144 CH0 RK0: MR19=606, MR18=3A35
1194 11:45:52.066486 CH0_RK0: MR19=0x606, MR18=0x3A35, DQSOSC=395, MR23=63, INC=94, DEC=63
1195 11:45:52.066571
1196 11:45:52.070211 ----->DramcWriteLeveling(PI) begin...
1197 11:45:52.070322 ==
1198 11:45:52.073366 Dram Type= 6, Freq= 0, CH_0, rank 1
1199 11:45:52.076660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1200 11:45:52.076745 ==
1201 11:45:52.080296 Write leveling (Byte 0): 33 => 33
1202 11:45:52.083679 Write leveling (Byte 1): 33 => 33
1203 11:45:52.087009 DramcWriteLeveling(PI) end<-----
1204 11:45:52.087111
1205 11:45:52.087203 ==
1206 11:45:52.089869 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 11:45:52.093632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1208 11:45:52.093716 ==
1209 11:45:52.096724 [Gating] SW mode calibration
1210 11:45:52.103397 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1211 11:45:52.110266 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1212 11:45:52.113422 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1213 11:45:52.116944 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1214 11:45:52.123393 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:45:52.126754 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:45:52.130213 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:45:52.136816 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:45:52.140625 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:45:52.143408 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:45:52.187559 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:45:52.187976 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:45:52.188276 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:45:52.188387 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:45:52.188497 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:45:52.188796 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:45:52.188905 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:45:52.189012 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:45:52.189115 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:45:52.189217 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1230 11:45:52.218724 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:45:52.219246 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:45:52.219534 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:45:52.219632 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:45:52.219924 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:45:52.220072 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:45:52.223311 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:45:52.226572 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:45:52.226672 0 9 8 | B1->B0 | 2d2d 3333 | 0 0 | (0 0) (0 0)
1239 11:45:52.233180 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 11:45:52.236688 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 11:45:52.239929 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 11:45:52.246635 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 11:45:52.249805 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 11:45:52.253271 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 11:45:52.260126 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1246 11:45:52.263045 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1247 11:45:52.266491 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:45:52.273132 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:45:52.276493 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:45:52.279850 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:45:52.282937 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:45:52.289851 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:45:52.293118 0 11 4 | B1->B0 | 2424 3030 | 0 1 | (0 0) (0 0)
1254 11:45:52.296494 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1255 11:45:52.302912 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 11:45:52.306769 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 11:45:52.309891 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 11:45:52.316333 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 11:45:52.319749 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 11:45:52.323381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 11:45:52.330419 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1262 11:45:52.334545 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1263 11:45:52.338324 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 11:45:52.341704 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 11:45:52.344907 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 11:45:52.351868 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 11:45:52.355859 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:45:52.358912 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:45:52.362541 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:45:52.368970 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:45:52.372699 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:45:52.375796 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:45:52.382760 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:45:52.385730 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:45:52.389356 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:45:52.395941 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:45:52.399130 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1278 11:45:52.402379 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1279 11:45:52.409362 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 11:45:52.409446 Total UI for P1: 0, mck2ui 16
1281 11:45:52.412386 best dqsien dly found for B0: ( 0, 14, 6)
1282 11:45:52.416057 Total UI for P1: 0, mck2ui 16
1283 11:45:52.419508 best dqsien dly found for B1: ( 0, 14, 6)
1284 11:45:52.422586 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1285 11:45:52.428991 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1286 11:45:52.429074
1287 11:45:52.432819 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1288 11:45:52.435762 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1289 11:45:52.439327 [Gating] SW calibration Done
1290 11:45:52.439410 ==
1291 11:45:52.442726 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 11:45:52.445990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 11:45:52.446073 ==
1294 11:45:52.446139 RX Vref Scan: 0
1295 11:45:52.446198
1296 11:45:52.449374 RX Vref 0 -> 0, step: 1
1297 11:45:52.449456
1298 11:45:52.452697 RX Delay -130 -> 252, step: 16
1299 11:45:52.456321 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1300 11:45:52.459392 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1301 11:45:52.466313 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1302 11:45:52.469685 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1303 11:45:52.472621 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1304 11:45:52.476411 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1305 11:45:52.479720 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1306 11:45:52.482963 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1307 11:45:52.489476 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1308 11:45:52.492706 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1309 11:45:52.496228 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1310 11:45:52.499754 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1311 11:45:52.502704 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1312 11:45:52.509674 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1313 11:45:52.513307 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1314 11:45:52.516226 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1315 11:45:52.516309 ==
1316 11:45:52.520082 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 11:45:52.523163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 11:45:52.526210 ==
1319 11:45:52.526318 DQS Delay:
1320 11:45:52.526413 DQS0 = 0, DQS1 = 0
1321 11:45:52.529769 DQM Delay:
1322 11:45:52.529851 DQM0 = 93, DQM1 = 80
1323 11:45:52.529916 DQ Delay:
1324 11:45:52.532782 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =77
1325 11:45:52.536413 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =109
1326 11:45:52.539506 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1327 11:45:52.542902 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1328 11:45:52.542984
1329 11:45:52.546070
1330 11:45:52.546177 ==
1331 11:45:52.550027 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 11:45:52.553260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 11:45:52.553369 ==
1334 11:45:52.553463
1335 11:45:52.553551
1336 11:45:52.556404 TX Vref Scan disable
1337 11:45:52.556513 == TX Byte 0 ==
1338 11:45:52.559953 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1339 11:45:52.566498 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1340 11:45:52.566582 == TX Byte 1 ==
1341 11:45:52.573148 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1342 11:45:52.576575 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1343 11:45:52.576659 ==
1344 11:45:52.579960 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 11:45:52.582999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 11:45:52.583082 ==
1347 11:45:52.596622 TX Vref=22, minBit 3, minWin=27, winSum=444
1348 11:45:52.599710 TX Vref=24, minBit 8, minWin=27, winSum=449
1349 11:45:52.603027 TX Vref=26, minBit 8, minWin=27, winSum=451
1350 11:45:52.606622 TX Vref=28, minBit 8, minWin=27, winSum=456
1351 11:45:52.609831 TX Vref=30, minBit 8, minWin=27, winSum=454
1352 11:45:52.612923 TX Vref=32, minBit 6, minWin=28, winSum=456
1353 11:45:52.619726 [TxChooseVref] Worse bit 6, Min win 28, Win sum 456, Final Vref 32
1354 11:45:52.619809
1355 11:45:52.622842 Final TX Range 1 Vref 32
1356 11:45:52.622943
1357 11:45:52.623009 ==
1358 11:45:52.626007 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 11:45:52.629454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 11:45:52.629536 ==
1361 11:45:52.633056
1362 11:45:52.633137
1363 11:45:52.633200 TX Vref Scan disable
1364 11:45:52.636165 == TX Byte 0 ==
1365 11:45:52.639726 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1366 11:45:52.643383 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1367 11:45:52.646199 == TX Byte 1 ==
1368 11:45:52.649397 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1369 11:45:52.652813 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1370 11:45:52.656266
1371 11:45:52.656346 [DATLAT]
1372 11:45:52.656409 Freq=800, CH0 RK1
1373 11:45:52.656468
1374 11:45:52.659648 DATLAT Default: 0xa
1375 11:45:52.659728 0, 0xFFFF, sum = 0
1376 11:45:52.662977 1, 0xFFFF, sum = 0
1377 11:45:52.663059 2, 0xFFFF, sum = 0
1378 11:45:52.666154 3, 0xFFFF, sum = 0
1379 11:45:52.666236 4, 0xFFFF, sum = 0
1380 11:45:52.669633 5, 0xFFFF, sum = 0
1381 11:45:52.669715 6, 0xFFFF, sum = 0
1382 11:45:52.673066 7, 0xFFFF, sum = 0
1383 11:45:52.676295 8, 0xFFFF, sum = 0
1384 11:45:52.676378 9, 0x0, sum = 1
1385 11:45:52.676443 10, 0x0, sum = 2
1386 11:45:52.679860 11, 0x0, sum = 3
1387 11:45:52.679942 12, 0x0, sum = 4
1388 11:45:52.683129 best_step = 10
1389 11:45:52.683209
1390 11:45:52.683272 ==
1391 11:45:52.686151 Dram Type= 6, Freq= 0, CH_0, rank 1
1392 11:45:52.689839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 11:45:52.689920 ==
1394 11:45:52.692893 RX Vref Scan: 0
1395 11:45:52.692973
1396 11:45:52.693036 RX Vref 0 -> 0, step: 1
1397 11:45:52.693095
1398 11:45:52.696217 RX Delay -95 -> 252, step: 8
1399 11:45:52.703258 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1400 11:45:52.706639 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1401 11:45:52.709677 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1402 11:45:52.713635 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1403 11:45:52.716648 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1404 11:45:52.719923 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1405 11:45:52.726882 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1406 11:45:52.730096 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1407 11:45:52.733243 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1408 11:45:52.736900 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1409 11:45:52.739845 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1410 11:45:52.746628 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1411 11:45:52.749938 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1412 11:45:52.753387 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1413 11:45:52.756762 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1414 11:45:52.763491 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1415 11:45:52.763572 ==
1416 11:45:52.766842 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 11:45:52.769947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 11:45:52.770028 ==
1419 11:45:52.770091 DQS Delay:
1420 11:45:52.773709 DQS0 = 0, DQS1 = 0
1421 11:45:52.773791 DQM Delay:
1422 11:45:52.776592 DQM0 = 90, DQM1 = 82
1423 11:45:52.776672 DQ Delay:
1424 11:45:52.779834 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1425 11:45:52.783251 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1426 11:45:52.786765 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =80
1427 11:45:52.789963 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1428 11:45:52.790046
1429 11:45:52.790110
1430 11:45:52.796644 [DQSOSCAuto] RK1, (LSB)MR18= 0x4620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1431 11:45:52.799979 CH0 RK1: MR19=606, MR18=4620
1432 11:45:52.806634 CH0_RK1: MR19=0x606, MR18=0x4620, DQSOSC=392, MR23=63, INC=96, DEC=64
1433 11:45:52.809914 [RxdqsGatingPostProcess] freq 800
1434 11:45:52.816537 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1435 11:45:52.816620 Pre-setting of DQS Precalculation
1436 11:45:52.823236 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1437 11:45:52.823327 ==
1438 11:45:52.826802 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 11:45:52.830033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 11:45:52.830146 ==
1441 11:45:52.836846 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1442 11:45:52.843282 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1443 11:45:52.851405 [CA 0] Center 36 (6~67) winsize 62
1444 11:45:52.854716 [CA 1] Center 36 (6~67) winsize 62
1445 11:45:52.858017 [CA 2] Center 35 (5~65) winsize 61
1446 11:45:52.861454 [CA 3] Center 34 (4~65) winsize 62
1447 11:45:52.865009 [CA 4] Center 34 (4~64) winsize 61
1448 11:45:52.868273 [CA 5] Center 33 (3~64) winsize 62
1449 11:45:52.868357
1450 11:45:52.871373 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1451 11:45:52.871456
1452 11:45:52.874900 [CATrainingPosCal] consider 1 rank data
1453 11:45:52.878119 u2DelayCellTimex100 = 270/100 ps
1454 11:45:52.881389 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1455 11:45:52.884727 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1456 11:45:52.891556 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1457 11:45:52.894607 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1458 11:45:52.898071 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1459 11:45:52.901248 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1460 11:45:52.901338
1461 11:45:52.904600 CA PerBit enable=1, Macro0, CA PI delay=33
1462 11:45:52.904693
1463 11:45:52.908040 [CBTSetCACLKResult] CA Dly = 33
1464 11:45:52.908127 CS Dly: 5 (0~36)
1465 11:45:52.908194 ==
1466 11:45:52.911329 Dram Type= 6, Freq= 0, CH_1, rank 1
1467 11:45:52.917817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1468 11:45:52.917907 ==
1469 11:45:52.921267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1470 11:45:52.928097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1471 11:45:52.937938 [CA 0] Center 37 (7~67) winsize 61
1472 11:45:52.940847 [CA 1] Center 36 (6~67) winsize 62
1473 11:45:52.944401 [CA 2] Center 34 (4~65) winsize 62
1474 11:45:52.947674 [CA 3] Center 34 (4~65) winsize 62
1475 11:45:52.950891 [CA 4] Center 35 (5~65) winsize 61
1476 11:45:52.954301 [CA 5] Center 34 (4~65) winsize 62
1477 11:45:52.954373
1478 11:45:52.957574 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1479 11:45:52.957645
1480 11:45:52.960996 [CATrainingPosCal] consider 2 rank data
1481 11:45:52.964355 u2DelayCellTimex100 = 270/100 ps
1482 11:45:52.967775 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1483 11:45:52.970939 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1484 11:45:52.974370 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1485 11:45:52.980869 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 11:45:52.984281 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
1487 11:45:52.987908 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1488 11:45:52.987980
1489 11:45:52.991080 CA PerBit enable=1, Macro0, CA PI delay=34
1490 11:45:52.991153
1491 11:45:52.994766 [CBTSetCACLKResult] CA Dly = 34
1492 11:45:52.994841 CS Dly: 5 (0~37)
1493 11:45:52.994903
1494 11:45:52.998871 ----->DramcWriteLeveling(PI) begin...
1495 11:45:52.998954 ==
1496 11:45:53.002980 Dram Type= 6, Freq= 0, CH_1, rank 0
1497 11:45:53.006369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1498 11:45:53.006490 ==
1499 11:45:53.009963 Write leveling (Byte 0): 29 => 29
1500 11:45:53.013828 Write leveling (Byte 1): 29 => 29
1501 11:45:53.017504 DramcWriteLeveling(PI) end<-----
1502 11:45:53.017587
1503 11:45:53.017652 ==
1504 11:45:53.021591 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 11:45:53.025387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 11:45:53.025495 ==
1507 11:45:53.025570 [Gating] SW mode calibration
1508 11:45:53.035252 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1509 11:45:53.038292 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1510 11:45:53.041705 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1511 11:45:53.048346 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1512 11:45:53.052253 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:45:53.055570 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:45:53.062422 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:45:53.065475 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:45:53.069140 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:45:53.075846 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:45:53.078964 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:45:53.082191 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:45:53.089017 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:45:53.092490 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:45:53.095814 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:45:53.102741 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:45:53.105618 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:45:53.108621 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:45:53.115407 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1527 11:45:53.118957 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1528 11:45:53.122230 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:45:53.125398 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:45:53.132225 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:45:53.135568 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:45:53.138778 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:45:53.145492 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:45:53.148951 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:45:53.152207 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1536 11:45:53.158938 0 9 8 | B1->B0 | 3333 3030 | 1 0 | (1 1) (0 0)
1537 11:45:53.162229 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 11:45:53.165384 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 11:45:53.172474 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 11:45:53.176061 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 11:45:53.178765 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 11:45:53.185827 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 11:45:53.189136 0 10 4 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (1 1)
1544 11:45:53.192537 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:45:53.199224 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:45:53.202503 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:45:53.205796 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:45:53.209603 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 11:45:53.216096 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:45:53.219344 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:45:53.222268 0 11 4 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
1552 11:45:53.228967 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1553 11:45:53.232895 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 11:45:53.235766 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 11:45:53.242554 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 11:45:53.246178 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 11:45:53.249388 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 11:45:53.255739 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1559 11:45:53.259491 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1560 11:45:53.262644 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 11:45:53.269311 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 11:45:53.272516 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 11:45:53.276239 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 11:45:53.279319 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 11:45:53.285812 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:45:53.289180 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:45:53.292864 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:45:53.299362 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:45:53.302692 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:45:53.306053 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:45:53.313240 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:45:53.316319 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:45:53.319731 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:45:53.326314 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1575 11:45:53.329526 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1576 11:45:53.332704 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 11:45:53.336263 Total UI for P1: 0, mck2ui 16
1578 11:45:53.339710 best dqsien dly found for B0: ( 0, 14, 2)
1579 11:45:53.342757 Total UI for P1: 0, mck2ui 16
1580 11:45:53.346255 best dqsien dly found for B1: ( 0, 14, 2)
1581 11:45:53.349659 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1582 11:45:53.353267 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1583 11:45:53.353687
1584 11:45:53.356535 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1585 11:45:53.359890 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1586 11:45:53.363287 [Gating] SW calibration Done
1587 11:45:53.363712 ==
1588 11:45:53.366544 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 11:45:53.370015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 11:45:53.373475 ==
1591 11:45:53.373988 RX Vref Scan: 0
1592 11:45:53.374344
1593 11:45:53.376553 RX Vref 0 -> 0, step: 1
1594 11:45:53.377066
1595 11:45:53.380053 RX Delay -130 -> 252, step: 16
1596 11:45:53.383454 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1597 11:45:53.386379 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1598 11:45:53.390053 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1599 11:45:53.392988 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1600 11:45:53.399766 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1601 11:45:53.403779 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1602 11:45:53.406993 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1603 11:45:53.409990 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1604 11:45:53.413497 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1605 11:45:53.416753 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1606 11:45:53.423278 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1607 11:45:53.426798 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1608 11:45:53.430148 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1609 11:45:53.433069 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1610 11:45:53.440117 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1611 11:45:53.443551 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1612 11:45:53.443975 ==
1613 11:45:53.446542 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 11:45:53.450126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 11:45:53.450595 ==
1616 11:45:53.450939 DQS Delay:
1617 11:45:53.453299 DQS0 = 0, DQS1 = 0
1618 11:45:53.453724 DQM Delay:
1619 11:45:53.456590 DQM0 = 93, DQM1 = 84
1620 11:45:53.457017 DQ Delay:
1621 11:45:53.459720 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1622 11:45:53.463232 DQ4 =85, DQ5 =101, DQ6 =109, DQ7 =93
1623 11:45:53.466702 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1624 11:45:53.470058 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1625 11:45:53.470606
1626 11:45:53.471145
1627 11:45:53.471656 ==
1628 11:45:53.473394 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 11:45:53.476785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 11:45:53.480040 ==
1631 11:45:53.480520
1632 11:45:53.481062
1633 11:45:53.481588 TX Vref Scan disable
1634 11:45:53.483725 == TX Byte 0 ==
1635 11:45:53.487074 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1636 11:45:53.490566 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1637 11:45:53.493545 == TX Byte 1 ==
1638 11:45:53.496888 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1639 11:45:53.500199 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1640 11:45:53.503685 ==
1641 11:45:53.504085 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 11:45:53.509883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 11:45:53.510286 ==
1644 11:45:53.522456 TX Vref=22, minBit 9, minWin=26, winSum=443
1645 11:45:53.525377 TX Vref=24, minBit 10, minWin=26, winSum=449
1646 11:45:53.529004 TX Vref=26, minBit 8, minWin=27, winSum=452
1647 11:45:53.531966 TX Vref=28, minBit 8, minWin=27, winSum=455
1648 11:45:53.535555 TX Vref=30, minBit 9, minWin=27, winSum=458
1649 11:45:53.542371 TX Vref=32, minBit 8, minWin=27, winSum=455
1650 11:45:53.545378 [TxChooseVref] Worse bit 9, Min win 27, Win sum 458, Final Vref 30
1651 11:45:53.545813
1652 11:45:53.548471 Final TX Range 1 Vref 30
1653 11:45:53.548906
1654 11:45:53.549441 ==
1655 11:45:53.551956 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 11:45:53.555525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 11:45:53.555962 ==
1658 11:45:53.556308
1659 11:45:53.558593
1660 11:45:53.559045 TX Vref Scan disable
1661 11:45:53.562087 == TX Byte 0 ==
1662 11:45:53.565401 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1663 11:45:53.568744 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1664 11:45:53.572303 == TX Byte 1 ==
1665 11:45:53.576028 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1666 11:45:53.579298 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1667 11:45:53.579745
1668 11:45:53.582633 [DATLAT]
1669 11:45:53.583006 Freq=800, CH1 RK0
1670 11:45:53.583338
1671 11:45:53.585937 DATLAT Default: 0xa
1672 11:45:53.586370 0, 0xFFFF, sum = 0
1673 11:45:53.589667 1, 0xFFFF, sum = 0
1674 11:45:53.590107 2, 0xFFFF, sum = 0
1675 11:45:53.592647 3, 0xFFFF, sum = 0
1676 11:45:53.593087 4, 0xFFFF, sum = 0
1677 11:45:53.596069 5, 0xFFFF, sum = 0
1678 11:45:53.596509 6, 0xFFFF, sum = 0
1679 11:45:53.599425 7, 0xFFFF, sum = 0
1680 11:45:53.599867 8, 0xFFFF, sum = 0
1681 11:45:53.602986 9, 0x0, sum = 1
1682 11:45:53.603428 10, 0x0, sum = 2
1683 11:45:53.606035 11, 0x0, sum = 3
1684 11:45:53.606506 12, 0x0, sum = 4
1685 11:45:53.609336 best_step = 10
1686 11:45:53.609765
1687 11:45:53.610109 ==
1688 11:45:53.613557 Dram Type= 6, Freq= 0, CH_1, rank 0
1689 11:45:53.615924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1690 11:45:53.616360 ==
1691 11:45:53.616706 RX Vref Scan: 1
1692 11:45:53.619476
1693 11:45:53.619908 Set Vref Range= 32 -> 127
1694 11:45:53.620255
1695 11:45:53.623009 RX Vref 32 -> 127, step: 1
1696 11:45:53.623442
1697 11:45:53.625965 RX Delay -79 -> 252, step: 8
1698 11:45:53.626430
1699 11:45:53.629281 Set Vref, RX VrefLevel [Byte0]: 32
1700 11:45:53.632672 [Byte1]: 32
1701 11:45:53.633105
1702 11:45:53.636030 Set Vref, RX VrefLevel [Byte0]: 33
1703 11:45:53.639711 [Byte1]: 33
1704 11:45:53.640145
1705 11:45:53.643124 Set Vref, RX VrefLevel [Byte0]: 34
1706 11:45:53.646261 [Byte1]: 34
1707 11:45:53.650096
1708 11:45:53.650557 Set Vref, RX VrefLevel [Byte0]: 35
1709 11:45:53.652975 [Byte1]: 35
1710 11:45:53.657614
1711 11:45:53.658223 Set Vref, RX VrefLevel [Byte0]: 36
1712 11:45:53.660418 [Byte1]: 36
1713 11:45:53.664803
1714 11:45:53.665377 Set Vref, RX VrefLevel [Byte0]: 37
1715 11:45:53.668191 [Byte1]: 37
1716 11:45:53.672473
1717 11:45:53.673023 Set Vref, RX VrefLevel [Byte0]: 38
1718 11:45:53.675922 [Byte1]: 38
1719 11:45:53.680196
1720 11:45:53.680714 Set Vref, RX VrefLevel [Byte0]: 39
1721 11:45:53.683318 [Byte1]: 39
1722 11:45:53.687838
1723 11:45:53.688265 Set Vref, RX VrefLevel [Byte0]: 40
1724 11:45:53.690987 [Byte1]: 40
1725 11:45:53.695274
1726 11:45:53.695696 Set Vref, RX VrefLevel [Byte0]: 41
1727 11:45:53.698125 [Byte1]: 41
1728 11:45:53.702603
1729 11:45:53.703023 Set Vref, RX VrefLevel [Byte0]: 42
1730 11:45:53.706165 [Byte1]: 42
1731 11:45:53.710564
1732 11:45:53.710987 Set Vref, RX VrefLevel [Byte0]: 43
1733 11:45:53.713769 [Byte1]: 43
1734 11:45:53.717869
1735 11:45:53.718292 Set Vref, RX VrefLevel [Byte0]: 44
1736 11:45:53.721081 [Byte1]: 44
1737 11:45:53.725080
1738 11:45:53.725502 Set Vref, RX VrefLevel [Byte0]: 45
1739 11:45:53.728913 [Byte1]: 45
1740 11:45:53.732921
1741 11:45:53.733341 Set Vref, RX VrefLevel [Byte0]: 46
1742 11:45:53.736088 [Byte1]: 46
1743 11:45:53.740614
1744 11:45:53.743692 Set Vref, RX VrefLevel [Byte0]: 47
1745 11:45:53.744117 [Byte1]: 47
1746 11:45:53.748320
1747 11:45:53.748758 Set Vref, RX VrefLevel [Byte0]: 48
1748 11:45:53.751257 [Byte1]: 48
1749 11:45:53.755783
1750 11:45:53.756306 Set Vref, RX VrefLevel [Byte0]: 49
1751 11:45:53.758752 [Byte1]: 49
1752 11:45:53.763238
1753 11:45:53.763701 Set Vref, RX VrefLevel [Byte0]: 50
1754 11:45:53.766575 [Byte1]: 50
1755 11:45:53.770025
1756 11:45:53.770107 Set Vref, RX VrefLevel [Byte0]: 51
1757 11:45:53.773373 [Byte1]: 51
1758 11:45:53.777901
1759 11:45:53.777985 Set Vref, RX VrefLevel [Byte0]: 52
1760 11:45:53.781046 [Byte1]: 52
1761 11:45:53.785322
1762 11:45:53.785405 Set Vref, RX VrefLevel [Byte0]: 53
1763 11:45:53.788996 [Byte1]: 53
1764 11:45:53.792944
1765 11:45:53.793029 Set Vref, RX VrefLevel [Byte0]: 54
1766 11:45:53.796381 [Byte1]: 54
1767 11:45:53.800543
1768 11:45:53.800625 Set Vref, RX VrefLevel [Byte0]: 55
1769 11:45:53.804193 [Byte1]: 55
1770 11:45:53.807839
1771 11:45:53.807922 Set Vref, RX VrefLevel [Byte0]: 56
1772 11:45:53.811258 [Byte1]: 56
1773 11:45:53.815527
1774 11:45:53.815609 Set Vref, RX VrefLevel [Byte0]: 57
1775 11:45:53.818877 [Byte1]: 57
1776 11:45:53.823171
1777 11:45:53.823254 Set Vref, RX VrefLevel [Byte0]: 58
1778 11:45:53.826589 [Byte1]: 58
1779 11:45:53.830600
1780 11:45:53.830682 Set Vref, RX VrefLevel [Byte0]: 59
1781 11:45:53.834129 [Byte1]: 59
1782 11:45:53.838316
1783 11:45:53.838404 Set Vref, RX VrefLevel [Byte0]: 60
1784 11:45:53.841788 [Byte1]: 60
1785 11:45:53.845896
1786 11:45:53.845978 Set Vref, RX VrefLevel [Byte0]: 61
1787 11:45:53.848917 [Byte1]: 61
1788 11:45:53.853322
1789 11:45:53.853441 Set Vref, RX VrefLevel [Byte0]: 62
1790 11:45:53.856445 [Byte1]: 62
1791 11:45:53.860986
1792 11:45:53.861094 Set Vref, RX VrefLevel [Byte0]: 63
1793 11:45:53.864021 [Byte1]: 63
1794 11:45:53.868509
1795 11:45:53.868591 Set Vref, RX VrefLevel [Byte0]: 64
1796 11:45:53.871691 [Byte1]: 64
1797 11:45:53.876196
1798 11:45:53.876280 Set Vref, RX VrefLevel [Byte0]: 65
1799 11:45:53.879097 [Byte1]: 65
1800 11:45:53.883352
1801 11:45:53.883435 Set Vref, RX VrefLevel [Byte0]: 66
1802 11:45:53.886800 [Byte1]: 66
1803 11:45:53.891235
1804 11:45:53.891318 Set Vref, RX VrefLevel [Byte0]: 67
1805 11:45:53.894307 [Byte1]: 67
1806 11:45:53.898735
1807 11:45:53.898817 Set Vref, RX VrefLevel [Byte0]: 68
1808 11:45:53.901702 [Byte1]: 68
1809 11:45:53.905954
1810 11:45:53.906037 Set Vref, RX VrefLevel [Byte0]: 69
1811 11:45:53.909540 [Byte1]: 69
1812 11:45:53.913959
1813 11:45:53.914041 Set Vref, RX VrefLevel [Byte0]: 70
1814 11:45:53.917150 [Byte1]: 70
1815 11:45:53.921345
1816 11:45:53.921428 Set Vref, RX VrefLevel [Byte0]: 71
1817 11:45:53.924765 [Byte1]: 71
1818 11:45:53.928924
1819 11:45:53.929007 Set Vref, RX VrefLevel [Byte0]: 72
1820 11:45:53.932229 [Byte1]: 72
1821 11:45:53.936264
1822 11:45:53.936346 Set Vref, RX VrefLevel [Byte0]: 73
1823 11:45:53.939960 [Byte1]: 73
1824 11:45:53.944122
1825 11:45:53.944204 Set Vref, RX VrefLevel [Byte0]: 74
1826 11:45:53.947255 [Byte1]: 74
1827 11:45:53.951695
1828 11:45:53.951782 Set Vref, RX VrefLevel [Byte0]: 75
1829 11:45:53.954738 [Byte1]: 75
1830 11:45:53.959010
1831 11:45:53.959093 Final RX Vref Byte 0 = 49 to rank0
1832 11:45:53.962243 Final RX Vref Byte 1 = 62 to rank0
1833 11:45:53.965518 Final RX Vref Byte 0 = 49 to rank1
1834 11:45:53.969089 Final RX Vref Byte 1 = 62 to rank1==
1835 11:45:53.972303 Dram Type= 6, Freq= 0, CH_1, rank 0
1836 11:45:53.979017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1837 11:45:53.979103 ==
1838 11:45:53.979169 DQS Delay:
1839 11:45:53.979230 DQS0 = 0, DQS1 = 0
1840 11:45:53.982239 DQM Delay:
1841 11:45:53.982322 DQM0 = 92, DQM1 = 83
1842 11:45:53.985642 DQ Delay:
1843 11:45:53.988986 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
1844 11:45:53.992390 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1845 11:45:53.992472 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1846 11:45:53.998881 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
1847 11:45:53.998989
1848 11:45:53.999058
1849 11:45:54.005833 [DQSOSCAuto] RK0, (LSB)MR18= 0x3552, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1850 11:45:54.008870 CH1 RK0: MR19=606, MR18=3552
1851 11:45:54.015723 CH1_RK0: MR19=0x606, MR18=0x3552, DQSOSC=389, MR23=63, INC=97, DEC=65
1852 11:45:54.015807
1853 11:45:54.019346 ----->DramcWriteLeveling(PI) begin...
1854 11:45:54.019431 ==
1855 11:45:54.022573 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 11:45:54.025778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 11:45:54.025861 ==
1858 11:45:54.028731 Write leveling (Byte 0): 26 => 26
1859 11:45:54.031992 Write leveling (Byte 1): 30 => 30
1860 11:45:54.035647 DramcWriteLeveling(PI) end<-----
1861 11:45:54.035730
1862 11:45:54.035796 ==
1863 11:45:54.039039 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 11:45:54.042718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 11:45:54.042801 ==
1866 11:45:54.045303 [Gating] SW mode calibration
1867 11:45:54.052255 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1868 11:45:54.059089 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1869 11:45:54.062056 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1870 11:45:54.065500 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:45:54.071971 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:45:54.075445 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:45:54.078938 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:45:54.085717 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:45:54.088726 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:45:54.092447 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:45:54.098945 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:45:54.102328 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:45:54.105494 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:45:54.112463 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:45:54.115675 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:45:54.119122 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:45:54.122244 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:45:54.129133 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:45:54.132541 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1886 11:45:54.135636 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1887 11:45:54.142340 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:45:54.146051 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:45:54.149029 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:45:54.156109 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:45:54.159447 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:45:54.162518 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:45:54.169673 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:45:54.172385 0 9 4 | B1->B0 | 2424 2323 | 1 0 | (1 1) (1 1)
1895 11:45:54.176028 0 9 8 | B1->B0 | 3434 2f2f | 1 0 | (0 0) (0 0)
1896 11:45:54.182371 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 11:45:54.185998 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 11:45:54.189132 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 11:45:54.192655 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 11:45:54.199147 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 11:45:54.202889 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 11:45:54.206084 0 10 4 | B1->B0 | 2e2e 3030 | 0 0 | (0 0) (0 0)
1903 11:45:54.212481 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
1904 11:45:54.215823 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:45:54.219100 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:45:54.225923 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:45:54.229654 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:45:54.232849 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:45:54.239458 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:45:54.243185 0 11 4 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (0 0)
1911 11:45:54.246192 0 11 8 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
1912 11:45:54.252578 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 11:45:54.256120 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 11:45:54.644470 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 11:45:54.644707 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 11:45:54.644875 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 11:45:54.644998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 11:45:54.645088 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1919 11:45:54.645175 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 11:45:54.645248 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 11:45:54.645333 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 11:45:54.645406 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 11:45:54.645479 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 11:45:54.645563 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 11:45:54.645620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:45:54.645680 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:45:54.645764 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:45:54.645843 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:45:54.645901 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:45:54.645959 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:45:54.646026 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:45:54.646102 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:45:54.646181 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1934 11:45:54.646284 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1935 11:45:54.646371 Total UI for P1: 0, mck2ui 16
1936 11:45:54.646464 best dqsien dly found for B0: ( 0, 14, 0)
1937 11:45:54.646525 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 11:45:54.646582 Total UI for P1: 0, mck2ui 16
1939 11:45:54.646638 best dqsien dly found for B1: ( 0, 14, 2)
1940 11:45:54.646700 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1941 11:45:54.646759 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1942 11:45:54.646814
1943 11:45:54.646870 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1944 11:45:54.646932 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1945 11:45:54.646990 [Gating] SW calibration Done
1946 11:45:54.647047 ==
1947 11:45:54.647103 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 11:45:54.647165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 11:45:54.647224 ==
1950 11:45:54.647278 RX Vref Scan: 0
1951 11:45:54.647333
1952 11:45:54.647394 RX Vref 0 -> 0, step: 1
1953 11:45:54.647452
1954 11:45:54.647507 RX Delay -130 -> 252, step: 16
1955 11:45:54.647575 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1956 11:45:54.647682 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1957 11:45:54.647749 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1958 11:45:54.647802 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1959 11:45:54.647893 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1960 11:45:54.647948 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1961 11:45:54.648030 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1962 11:45:54.648106 iDelay=222, Bit 7, Center 85 (-18 ~ 189) 208
1963 11:45:54.648163 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1964 11:45:54.648218 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1965 11:45:54.648272 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1966 11:45:54.648334 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1967 11:45:54.648391 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1968 11:45:54.648473 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1969 11:45:54.648558 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1970 11:45:54.648616 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1971 11:45:54.648694 ==
1972 11:45:54.648796 Dram Type= 6, Freq= 0, CH_1, rank 1
1973 11:45:54.648855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1974 11:45:54.648912 ==
1975 11:45:54.648984 DQS Delay:
1976 11:45:54.649053 DQS0 = 0, DQS1 = 0
1977 11:45:54.649127 DQM Delay:
1978 11:45:54.649199 DQM0 = 90, DQM1 = 84
1979 11:45:54.649254 DQ Delay:
1980 11:45:54.649322 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1981 11:45:54.649403 DQ4 =85, DQ5 =109, DQ6 =93, DQ7 =85
1982 11:45:54.649459 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1983 11:45:54.649521 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1984 11:45:54.649596
1985 11:45:54.649653
1986 11:45:54.649708 ==
1987 11:45:54.649786 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 11:45:54.649845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 11:45:54.649902 ==
1990 11:45:54.649956
1991 11:45:54.650017
1992 11:45:54.650074 TX Vref Scan disable
1993 11:45:54.650128 == TX Byte 0 ==
1994 11:45:54.650183 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1995 11:45:54.650263 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1996 11:45:54.650321 == TX Byte 1 ==
1997 11:45:54.650377 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1998 11:45:54.650462 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1999 11:45:54.650520 ==
2000 11:45:54.650575 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 11:45:54.650630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 11:45:54.650685 ==
2003 11:45:54.650764 TX Vref=22, minBit 8, minWin=27, winSum=451
2004 11:45:54.650826 TX Vref=24, minBit 8, minWin=27, winSum=448
2005 11:45:54.650884 TX Vref=26, minBit 1, minWin=28, winSum=454
2006 11:45:54.650949 TX Vref=28, minBit 13, minWin=27, winSum=456
2007 11:45:54.651012 TX Vref=30, minBit 8, minWin=28, winSum=462
2008 11:45:54.651070 TX Vref=32, minBit 9, minWin=27, winSum=457
2009 11:45:54.651128 [TxChooseVref] Worse bit 8, Min win 28, Win sum 462, Final Vref 30
2010 11:45:54.651195
2011 11:45:54.651258 Final TX Range 1 Vref 30
2012 11:45:54.651316
2013 11:45:54.651375 ==
2014 11:45:54.651442 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 11:45:54.651501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 11:45:54.651559 ==
2017 11:45:54.651623
2018 11:45:54.651685
2019 11:45:54.651746 TX Vref Scan disable
2020 11:45:54.651817 == TX Byte 0 ==
2021 11:45:54.651885 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2022 11:45:54.651947 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2023 11:45:54.652006 == TX Byte 1 ==
2024 11:45:54.652064 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2025 11:45:54.652132 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2026 11:45:54.652192
2027 11:45:54.652250 [DATLAT]
2028 11:45:54.652314 Freq=800, CH1 RK1
2029 11:45:54.652377
2030 11:45:54.652435 DATLAT Default: 0xa
2031 11:45:54.652493 0, 0xFFFF, sum = 0
2032 11:45:54.652559 1, 0xFFFF, sum = 0
2033 11:45:54.652622 2, 0xFFFF, sum = 0
2034 11:45:54.652684 3, 0xFFFF, sum = 0
2035 11:45:54.652743 4, 0xFFFF, sum = 0
2036 11:45:54.652809 5, 0xFFFF, sum = 0
2037 11:45:54.652872 6, 0xFFFF, sum = 0
2038 11:45:54.652931 7, 0xFFFF, sum = 0
2039 11:45:54.652989 8, 0xFFFF, sum = 0
2040 11:45:54.653279 9, 0x0, sum = 1
2041 11:45:54.653350 10, 0x0, sum = 2
2042 11:45:54.653412 11, 0x0, sum = 3
2043 11:45:54.653477 12, 0x0, sum = 4
2044 11:45:54.653542 best_step = 10
2045 11:45:54.653602
2046 11:45:54.653660 ==
2047 11:45:54.653726 Dram Type= 6, Freq= 0, CH_1, rank 1
2048 11:45:54.653789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2049 11:45:54.653848 ==
2050 11:45:54.653907 RX Vref Scan: 0
2051 11:45:54.653972
2052 11:45:54.654033 RX Vref 0 -> 0, step: 1
2053 11:45:54.654093
2054 11:45:54.654150 RX Delay -95 -> 252, step: 8
2055 11:45:54.654217 iDelay=209, Bit 0, Center 96 (1 ~ 192) 192
2056 11:45:54.659813 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2057 11:45:54.660112 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2058 11:45:54.660196 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2059 11:45:54.661642 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2060 11:45:54.665043 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2061 11:45:54.671921 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2062 11:45:54.675592 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2063 11:45:54.678489 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2064 11:45:54.681832 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2065 11:45:54.685630 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2066 11:45:54.688614 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2067 11:45:54.695293 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2068 11:45:54.698865 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2069 11:45:54.702069 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2070 11:45:54.705345 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2071 11:45:54.705470 ==
2072 11:45:54.708844 Dram Type= 6, Freq= 0, CH_1, rank 1
2073 11:45:54.715466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2074 11:45:54.715576 ==
2075 11:45:54.715671 DQS Delay:
2076 11:45:54.718873 DQS0 = 0, DQS1 = 0
2077 11:45:54.718976 DQM Delay:
2078 11:45:54.719071 DQM0 = 93, DQM1 = 85
2079 11:45:54.721768 DQ Delay:
2080 11:45:54.725291 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
2081 11:45:54.728886 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2082 11:45:54.732024 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =84
2083 11:45:54.735148 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
2084 11:45:54.735235
2085 11:45:54.735302
2086 11:45:54.742065 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
2087 11:45:54.745216 CH1 RK1: MR19=606, MR18=3F14
2088 11:45:54.752094 CH1_RK1: MR19=0x606, MR18=0x3F14, DQSOSC=393, MR23=63, INC=95, DEC=63
2089 11:45:54.755189 [RxdqsGatingPostProcess] freq 800
2090 11:45:54.758875 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2091 11:45:54.762135 Pre-setting of DQS Precalculation
2092 11:45:54.768719 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2093 11:45:54.775150 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2094 11:45:54.781756 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2095 11:45:54.781873
2096 11:45:54.781991
2097 11:45:54.785204 [Calibration Summary] 1600 Mbps
2098 11:45:54.785314 CH 0, Rank 0
2099 11:45:54.788528 SW Impedance : PASS
2100 11:45:54.792074 DUTY Scan : NO K
2101 11:45:54.792157 ZQ Calibration : PASS
2102 11:45:54.795659 Jitter Meter : NO K
2103 11:45:54.798805 CBT Training : PASS
2104 11:45:54.798893 Write leveling : PASS
2105 11:45:54.802222 RX DQS gating : PASS
2106 11:45:54.802310 RX DQ/DQS(RDDQC) : PASS
2107 11:45:54.805747 TX DQ/DQS : PASS
2108 11:45:54.808983 RX DATLAT : PASS
2109 11:45:54.809070 RX DQ/DQS(Engine): PASS
2110 11:45:54.812281 TX OE : NO K
2111 11:45:54.812368 All Pass.
2112 11:45:54.812437
2113 11:45:54.815966 CH 0, Rank 1
2114 11:45:54.816052 SW Impedance : PASS
2115 11:45:54.818914 DUTY Scan : NO K
2116 11:45:54.822068 ZQ Calibration : PASS
2117 11:45:54.822154 Jitter Meter : NO K
2118 11:45:54.825616 CBT Training : PASS
2119 11:45:54.828613 Write leveling : PASS
2120 11:45:54.828699 RX DQS gating : PASS
2121 11:45:54.832576 RX DQ/DQS(RDDQC) : PASS
2122 11:45:54.835346 TX DQ/DQS : PASS
2123 11:45:54.835434 RX DATLAT : PASS
2124 11:45:54.838852 RX DQ/DQS(Engine): PASS
2125 11:45:54.838966 TX OE : NO K
2126 11:45:54.842495 All Pass.
2127 11:45:54.842589
2128 11:45:54.842659 CH 1, Rank 0
2129 11:45:54.845574 SW Impedance : PASS
2130 11:45:54.845692 DUTY Scan : NO K
2131 11:45:54.848929 ZQ Calibration : PASS
2132 11:45:54.852563 Jitter Meter : NO K
2133 11:45:54.852679 CBT Training : PASS
2134 11:45:54.855488 Write leveling : PASS
2135 11:45:54.859021 RX DQS gating : PASS
2136 11:45:54.859115 RX DQ/DQS(RDDQC) : PASS
2137 11:45:54.862161 TX DQ/DQS : PASS
2138 11:45:54.865798 RX DATLAT : PASS
2139 11:45:54.865922 RX DQ/DQS(Engine): PASS
2140 11:45:54.868955 TX OE : NO K
2141 11:45:54.869050 All Pass.
2142 11:45:54.869122
2143 11:45:54.872220 CH 1, Rank 1
2144 11:45:54.872333 SW Impedance : PASS
2145 11:45:54.875742 DUTY Scan : NO K
2146 11:45:54.879143 ZQ Calibration : PASS
2147 11:45:54.879249 Jitter Meter : NO K
2148 11:45:54.882272 CBT Training : PASS
2149 11:45:54.882402 Write leveling : PASS
2150 11:45:54.885469 RX DQS gating : PASS
2151 11:45:54.889155 RX DQ/DQS(RDDQC) : PASS
2152 11:45:54.889266 TX DQ/DQS : PASS
2153 11:45:54.892499 RX DATLAT : PASS
2154 11:45:54.895837 RX DQ/DQS(Engine): PASS
2155 11:45:54.895946 TX OE : NO K
2156 11:45:54.898881 All Pass.
2157 11:45:54.898987
2158 11:45:54.899082 DramC Write-DBI off
2159 11:45:54.902217 PER_BANK_REFRESH: Hybrid Mode
2160 11:45:54.906004 TX_TRACKING: ON
2161 11:45:54.909039 [GetDramInforAfterCalByMRR] Vendor 6.
2162 11:45:54.912483 [GetDramInforAfterCalByMRR] Revision 606.
2163 11:45:54.915711 [GetDramInforAfterCalByMRR] Revision 2 0.
2164 11:45:54.915816 MR0 0x3b3b
2165 11:45:54.915914 MR8 0x5151
2166 11:45:54.918927 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2167 11:45:54.922126
2168 11:45:54.922231 MR0 0x3b3b
2169 11:45:54.922328 MR8 0x5151
2170 11:45:54.925568 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2171 11:45:54.925651
2172 11:45:54.935931 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2173 11:45:54.939298 [FAST_K] Save calibration result to emmc
2174 11:45:54.942803 [FAST_K] Save calibration result to emmc
2175 11:45:54.945953 dram_init: config_dvfs: 1
2176 11:45:54.948981 dramc_set_vcore_voltage set vcore to 662500
2177 11:45:54.952351 Read voltage for 1200, 2
2178 11:45:54.952463 Vio18 = 0
2179 11:45:54.952561 Vcore = 662500
2180 11:45:54.955664 Vdram = 0
2181 11:45:54.955766 Vddq = 0
2182 11:45:54.955851 Vmddr = 0
2183 11:45:54.962291 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2184 11:45:54.965917 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2185 11:45:54.968971 MEM_TYPE=3, freq_sel=15
2186 11:45:54.972944 sv_algorithm_assistance_LP4_1600
2187 11:45:54.975949 ============ PULL DRAM RESETB DOWN ============
2188 11:45:54.979390 ========== PULL DRAM RESETB DOWN end =========
2189 11:45:54.985860 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2190 11:45:54.989107 ===================================
2191 11:45:54.989226 LPDDR4 DRAM CONFIGURATION
2192 11:45:54.992563 ===================================
2193 11:45:54.995753 EX_ROW_EN[0] = 0x0
2194 11:45:54.999254 EX_ROW_EN[1] = 0x0
2195 11:45:54.999351 LP4Y_EN = 0x0
2196 11:45:55.002396 WORK_FSP = 0x0
2197 11:45:55.002483 WL = 0x4
2198 11:45:55.006062 RL = 0x4
2199 11:45:55.006145 BL = 0x2
2200 11:45:55.009298 RPST = 0x0
2201 11:45:55.009376 RD_PRE = 0x0
2202 11:45:55.012698 WR_PRE = 0x1
2203 11:45:55.012774 WR_PST = 0x0
2204 11:45:55.015667 DBI_WR = 0x0
2205 11:45:55.015758 DBI_RD = 0x0
2206 11:45:55.019028 OTF = 0x1
2207 11:45:55.022735 ===================================
2208 11:45:55.026075 ===================================
2209 11:45:55.026161 ANA top config
2210 11:45:55.029451 ===================================
2211 11:45:55.032986 DLL_ASYNC_EN = 0
2212 11:45:55.036095 ALL_SLAVE_EN = 0
2213 11:45:55.036187 NEW_RANK_MODE = 1
2214 11:45:55.039143 DLL_IDLE_MODE = 1
2215 11:45:55.042761 LP45_APHY_COMB_EN = 1
2216 11:45:55.045899 TX_ODT_DIS = 1
2217 11:45:55.049360 NEW_8X_MODE = 1
2218 11:45:55.052363 ===================================
2219 11:45:55.052451 ===================================
2220 11:45:55.055862 data_rate = 2400
2221 11:45:55.059057 CKR = 1
2222 11:45:55.062684 DQ_P2S_RATIO = 8
2223 11:45:55.065789 ===================================
2224 11:45:55.069378 CA_P2S_RATIO = 8
2225 11:45:55.072538 DQ_CA_OPEN = 0
2226 11:45:55.075886 DQ_SEMI_OPEN = 0
2227 11:45:55.076009 CA_SEMI_OPEN = 0
2228 11:45:55.079093 CA_FULL_RATE = 0
2229 11:45:55.082663 DQ_CKDIV4_EN = 0
2230 11:45:55.086124 CA_CKDIV4_EN = 0
2231 11:45:55.089198 CA_PREDIV_EN = 0
2232 11:45:55.089285 PH8_DLY = 17
2233 11:45:55.092575 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2234 11:45:55.096083 DQ_AAMCK_DIV = 4
2235 11:45:55.099430 CA_AAMCK_DIV = 4
2236 11:45:55.102732 CA_ADMCK_DIV = 4
2237 11:45:55.105983 DQ_TRACK_CA_EN = 0
2238 11:45:55.106063 CA_PICK = 1200
2239 11:45:55.109280 CA_MCKIO = 1200
2240 11:45:55.112567 MCKIO_SEMI = 0
2241 11:45:55.115882 PLL_FREQ = 2366
2242 11:45:55.119222 DQ_UI_PI_RATIO = 32
2243 11:45:55.123194 CA_UI_PI_RATIO = 0
2244 11:45:55.125864 ===================================
2245 11:45:55.129540 ===================================
2246 11:45:55.132991 memory_type:LPDDR4
2247 11:45:55.133076 GP_NUM : 10
2248 11:45:55.136042 SRAM_EN : 1
2249 11:45:55.136121 MD32_EN : 0
2250 11:45:55.139300 ===================================
2251 11:45:55.142701 [ANA_INIT] >>>>>>>>>>>>>>
2252 11:45:55.146280 <<<<<< [CONFIGURE PHASE]: ANA_TX
2253 11:45:55.149588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2254 11:45:55.153075 ===================================
2255 11:45:55.156276 data_rate = 2400,PCW = 0X5b00
2256 11:45:55.159264 ===================================
2257 11:45:55.162917 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2258 11:45:55.165925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 11:45:55.172716 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2260 11:45:55.176073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2261 11:45:55.179324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2262 11:45:55.182976 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2263 11:45:55.186069 [ANA_INIT] flow start
2264 11:45:55.189533 [ANA_INIT] PLL >>>>>>>>
2265 11:45:55.189636 [ANA_INIT] PLL <<<<<<<<
2266 11:45:55.192921 [ANA_INIT] MIDPI >>>>>>>>
2267 11:45:55.195888 [ANA_INIT] MIDPI <<<<<<<<
2268 11:45:55.199460 [ANA_INIT] DLL >>>>>>>>
2269 11:45:55.199538 [ANA_INIT] DLL <<<<<<<<
2270 11:45:55.202734 [ANA_INIT] flow end
2271 11:45:55.206457 ============ LP4 DIFF to SE enter ============
2272 11:45:55.209467 ============ LP4 DIFF to SE exit ============
2273 11:45:55.212921 [ANA_INIT] <<<<<<<<<<<<<
2274 11:45:55.216133 [Flow] Enable top DCM control >>>>>
2275 11:45:55.219570 [Flow] Enable top DCM control <<<<<
2276 11:45:55.222814 Enable DLL master slave shuffle
2277 11:45:55.226095 ==============================================================
2278 11:45:55.229621 Gating Mode config
2279 11:45:55.235952 ==============================================================
2280 11:45:55.236054 Config description:
2281 11:45:55.245958 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2282 11:45:55.253325 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2283 11:45:55.259593 SELPH_MODE 0: By rank 1: By Phase
2284 11:45:55.262917 ==============================================================
2285 11:45:55.266370 GAT_TRACK_EN = 1
2286 11:45:55.269719 RX_GATING_MODE = 2
2287 11:45:55.272985 RX_GATING_TRACK_MODE = 2
2288 11:45:55.276543 SELPH_MODE = 1
2289 11:45:55.279721 PICG_EARLY_EN = 1
2290 11:45:55.283130 VALID_LAT_VALUE = 1
2291 11:45:55.286736 ==============================================================
2292 11:45:55.289569 Enter into Gating configuration >>>>
2293 11:45:55.293197 Exit from Gating configuration <<<<
2294 11:45:55.296079 Enter into DVFS_PRE_config >>>>>
2295 11:45:55.309678 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2296 11:45:55.309770 Exit from DVFS_PRE_config <<<<<
2297 11:45:55.312849 Enter into PICG configuration >>>>
2298 11:45:55.316375 Exit from PICG configuration <<<<
2299 11:45:55.319636 [RX_INPUT] configuration >>>>>
2300 11:45:55.322882 [RX_INPUT] configuration <<<<<
2301 11:45:55.329363 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2302 11:45:55.333065 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2303 11:45:55.339411 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2304 11:45:55.346231 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2305 11:45:55.353029 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 11:45:55.359683 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 11:45:55.362939 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2308 11:45:55.366322 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2309 11:45:55.369718 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2310 11:45:55.376351 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2311 11:45:55.379536 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2312 11:45:55.382981 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2313 11:45:55.386340 ===================================
2314 11:45:55.389644 LPDDR4 DRAM CONFIGURATION
2315 11:45:55.392980 ===================================
2316 11:45:55.393095 EX_ROW_EN[0] = 0x0
2317 11:45:55.396526 EX_ROW_EN[1] = 0x0
2318 11:45:55.396637 LP4Y_EN = 0x0
2319 11:45:55.399530 WORK_FSP = 0x0
2320 11:45:55.399616 WL = 0x4
2321 11:45:55.402982 RL = 0x4
2322 11:45:55.403064 BL = 0x2
2323 11:45:55.406797 RPST = 0x0
2324 11:45:55.409790 RD_PRE = 0x0
2325 11:45:55.409881 WR_PRE = 0x1
2326 11:45:55.412912 WR_PST = 0x0
2327 11:45:55.412988 DBI_WR = 0x0
2328 11:45:55.416192 DBI_RD = 0x0
2329 11:45:55.416295 OTF = 0x1
2330 11:45:55.419561 ===================================
2331 11:45:55.423228 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2332 11:45:55.426747 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2333 11:45:55.432727 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2334 11:45:55.436588 ===================================
2335 11:45:55.439577 LPDDR4 DRAM CONFIGURATION
2336 11:45:55.442954 ===================================
2337 11:45:55.443039 EX_ROW_EN[0] = 0x10
2338 11:45:55.446517 EX_ROW_EN[1] = 0x0
2339 11:45:55.446597 LP4Y_EN = 0x0
2340 11:45:55.449457 WORK_FSP = 0x0
2341 11:45:55.449539 WL = 0x4
2342 11:45:55.452895 RL = 0x4
2343 11:45:55.452974 BL = 0x2
2344 11:45:55.456351 RPST = 0x0
2345 11:45:55.456426 RD_PRE = 0x0
2346 11:45:55.459574 WR_PRE = 0x1
2347 11:45:55.459656 WR_PST = 0x0
2348 11:45:55.462961 DBI_WR = 0x0
2349 11:45:55.463040 DBI_RD = 0x0
2350 11:45:55.466647 OTF = 0x1
2351 11:45:55.469799 ===================================
2352 11:45:55.476124 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2353 11:45:55.476209 ==
2354 11:45:55.479814 Dram Type= 6, Freq= 0, CH_0, rank 0
2355 11:45:55.483165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2356 11:45:55.483251 ==
2357 11:45:55.486346 [Duty_Offset_Calibration]
2358 11:45:55.486453 B0:2 B1:0 CA:1
2359 11:45:55.486539
2360 11:45:55.489363 [DutyScan_Calibration_Flow] k_type=0
2361 11:45:55.499487
2362 11:45:55.499575 ==CLK 0==
2363 11:45:55.502823 Final CLK duty delay cell = -4
2364 11:45:55.506017 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2365 11:45:55.509668 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2366 11:45:55.513105 [-4] AVG Duty = 4953%(X100)
2367 11:45:55.513200
2368 11:45:55.516510 CH0 CLK Duty spec in!! Max-Min= 156%
2369 11:45:55.519631 [DutyScan_Calibration_Flow] ====Done====
2370 11:45:55.519715
2371 11:45:55.523099 [DutyScan_Calibration_Flow] k_type=1
2372 11:45:55.538273
2373 11:45:55.538350 ==DQS 0 ==
2374 11:45:55.541791 Final DQS duty delay cell = 0
2375 11:45:55.545034 [0] MAX Duty = 5187%(X100), DQS PI = 30
2376 11:45:55.548327 [0] MIN Duty = 4938%(X100), DQS PI = 0
2377 11:45:55.548403 [0] AVG Duty = 5062%(X100)
2378 11:45:55.551823
2379 11:45:55.551896 ==DQS 1 ==
2380 11:45:55.555320 Final DQS duty delay cell = -4
2381 11:45:55.558344 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2382 11:45:55.562092 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2383 11:45:55.565117 [-4] AVG Duty = 5031%(X100)
2384 11:45:55.565199
2385 11:45:55.568499 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2386 11:45:55.568609
2387 11:45:55.571693 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2388 11:45:55.575106 [DutyScan_Calibration_Flow] ====Done====
2389 11:45:55.575209
2390 11:45:55.578217 [DutyScan_Calibration_Flow] k_type=3
2391 11:45:55.595712
2392 11:45:55.595802 ==DQM 0 ==
2393 11:45:55.598323 Final DQM duty delay cell = 0
2394 11:45:55.601815 [0] MAX Duty = 5062%(X100), DQS PI = 24
2395 11:45:55.605170 [0] MIN Duty = 4844%(X100), DQS PI = 2
2396 11:45:55.605249 [0] AVG Duty = 4953%(X100)
2397 11:45:55.608595
2398 11:45:55.608668 ==DQM 1 ==
2399 11:45:55.611591 Final DQM duty delay cell = 0
2400 11:45:55.615207 [0] MAX Duty = 5218%(X100), DQS PI = 50
2401 11:45:55.618293 [0] MIN Duty = 5000%(X100), DQS PI = 22
2402 11:45:55.618371 [0] AVG Duty = 5109%(X100)
2403 11:45:55.621659
2404 11:45:55.624960 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2405 11:45:55.625031
2406 11:45:55.628294 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2407 11:45:55.631838 [DutyScan_Calibration_Flow] ====Done====
2408 11:45:55.631908
2409 11:45:55.635175 [DutyScan_Calibration_Flow] k_type=2
2410 11:45:55.651038
2411 11:45:55.651123 ==DQ 0 ==
2412 11:45:55.654379 Final DQ duty delay cell = -4
2413 11:45:55.657617 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2414 11:45:55.660903 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2415 11:45:55.664244 [-4] AVG Duty = 4953%(X100)
2416 11:45:55.664329
2417 11:45:55.664392 ==DQ 1 ==
2418 11:45:55.667913 Final DQ duty delay cell = 0
2419 11:45:55.671010 [0] MAX Duty = 4938%(X100), DQS PI = 4
2420 11:45:55.674587 [0] MIN Duty = 4907%(X100), DQS PI = 0
2421 11:45:55.674673 [0] AVG Duty = 4922%(X100)
2422 11:45:55.674750
2423 11:45:55.677853 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2424 11:45:55.681177
2425 11:45:55.684465 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2426 11:45:55.687917 [DutyScan_Calibration_Flow] ====Done====
2427 11:45:55.688001 ==
2428 11:45:55.691207 Dram Type= 6, Freq= 0, CH_1, rank 0
2429 11:45:55.694378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2430 11:45:55.694478 ==
2431 11:45:55.698087 [Duty_Offset_Calibration]
2432 11:45:55.698166 B0:0 B1:-1 CA:2
2433 11:45:55.698232
2434 11:45:55.700959 [DutyScan_Calibration_Flow] k_type=0
2435 11:45:55.711089
2436 11:45:55.711170 ==CLK 0==
2437 11:45:55.714662 Final CLK duty delay cell = 0
2438 11:45:55.717650 [0] MAX Duty = 5156%(X100), DQS PI = 16
2439 11:45:55.721316 [0] MIN Duty = 4938%(X100), DQS PI = 44
2440 11:45:55.721425 [0] AVG Duty = 5047%(X100)
2441 11:45:55.724398
2442 11:45:55.724506 CH1 CLK Duty spec in!! Max-Min= 218%
2443 11:45:55.731288 [DutyScan_Calibration_Flow] ====Done====
2444 11:45:55.731366
2445 11:45:55.734751 [DutyScan_Calibration_Flow] k_type=1
2446 11:45:55.750532
2447 11:45:55.750618 ==DQS 0 ==
2448 11:45:55.753749 Final DQS duty delay cell = 0
2449 11:45:55.757046 [0] MAX Duty = 5093%(X100), DQS PI = 24
2450 11:45:55.760465 [0] MIN Duty = 4969%(X100), DQS PI = 0
2451 11:45:55.760573 [0] AVG Duty = 5031%(X100)
2452 11:45:55.763617
2453 11:45:55.763690 ==DQS 1 ==
2454 11:45:55.767360 Final DQS duty delay cell = 0
2455 11:45:55.770426 [0] MAX Duty = 5156%(X100), DQS PI = 0
2456 11:45:55.774117 [0] MIN Duty = 4875%(X100), DQS PI = 34
2457 11:45:55.774219 [0] AVG Duty = 5015%(X100)
2458 11:45:55.774320
2459 11:45:55.777270 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2460 11:45:55.780353
2461 11:45:55.783831 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2462 11:45:55.787833 [DutyScan_Calibration_Flow] ====Done====
2463 11:45:55.787921
2464 11:45:55.790485 [DutyScan_Calibration_Flow] k_type=3
2465 11:45:55.807200
2466 11:45:55.807311 ==DQM 0 ==
2467 11:45:55.810791 Final DQM duty delay cell = 4
2468 11:45:55.813652 [4] MAX Duty = 5093%(X100), DQS PI = 20
2469 11:45:55.816642 [4] MIN Duty = 4938%(X100), DQS PI = 48
2470 11:45:55.820059 [4] AVG Duty = 5015%(X100)
2471 11:45:55.820139
2472 11:45:55.820233 ==DQM 1 ==
2473 11:45:55.823430 Final DQM duty delay cell = -4
2474 11:45:55.826799 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2475 11:45:55.830486 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2476 11:45:55.833871 [-4] AVG Duty = 4875%(X100)
2477 11:45:55.833983
2478 11:45:55.837121 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2479 11:45:55.837236
2480 11:45:55.840559 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2481 11:45:55.843677 [DutyScan_Calibration_Flow] ====Done====
2482 11:45:55.843763
2483 11:45:55.846745 [DutyScan_Calibration_Flow] k_type=2
2484 11:45:55.863981
2485 11:45:55.864061 ==DQ 0 ==
2486 11:45:55.867161 Final DQ duty delay cell = 0
2487 11:45:55.870380 [0] MAX Duty = 5062%(X100), DQS PI = 20
2488 11:45:55.873989 [0] MIN Duty = 4938%(X100), DQS PI = 44
2489 11:45:55.874101 [0] AVG Duty = 5000%(X100)
2490 11:45:55.877163
2491 11:45:55.877240 ==DQ 1 ==
2492 11:45:55.880515 Final DQ duty delay cell = 0
2493 11:45:55.884291 [0] MAX Duty = 5031%(X100), DQS PI = 2
2494 11:45:55.887463 [0] MIN Duty = 4813%(X100), DQS PI = 36
2495 11:45:55.887575 [0] AVG Duty = 4922%(X100)
2496 11:45:55.887676
2497 11:45:55.890843 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2498 11:45:55.890951
2499 11:45:55.893917 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2500 11:45:55.900705 [DutyScan_Calibration_Flow] ====Done====
2501 11:45:55.903971 nWR fixed to 30
2502 11:45:55.904058 [ModeRegInit_LP4] CH0 RK0
2503 11:45:55.907366 [ModeRegInit_LP4] CH0 RK1
2504 11:45:55.910762 [ModeRegInit_LP4] CH1 RK0
2505 11:45:55.910871 [ModeRegInit_LP4] CH1 RK1
2506 11:45:55.913867 match AC timing 7
2507 11:45:55.917072 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2508 11:45:55.920349 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2509 11:45:55.927051 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2510 11:45:55.930364 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2511 11:45:55.936857 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2512 11:45:55.936961 ==
2513 11:45:55.940557 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 11:45:55.943805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 11:45:55.943882 ==
2516 11:45:55.950871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2517 11:45:55.953544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2518 11:45:55.963890 [CA 0] Center 38 (7~69) winsize 63
2519 11:45:55.967072 [CA 1] Center 38 (7~69) winsize 63
2520 11:45:55.970485 [CA 2] Center 34 (4~65) winsize 62
2521 11:45:55.973546 [CA 3] Center 34 (4~65) winsize 62
2522 11:45:55.977171 [CA 4] Center 34 (4~64) winsize 61
2523 11:45:55.980150 [CA 5] Center 33 (3~63) winsize 61
2524 11:45:55.980240
2525 11:45:55.983825 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2526 11:45:55.983901
2527 11:45:55.987116 [CATrainingPosCal] consider 1 rank data
2528 11:45:55.990189 u2DelayCellTimex100 = 270/100 ps
2529 11:45:55.993712 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2530 11:45:55.996939 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2531 11:45:56.004047 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
2532 11:45:56.007029 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2533 11:45:56.010512 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2534 11:45:56.013876 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2535 11:45:56.013956
2536 11:45:56.017528 CA PerBit enable=1, Macro0, CA PI delay=33
2537 11:45:56.017616
2538 11:45:56.020170 [CBTSetCACLKResult] CA Dly = 33
2539 11:45:56.020256 CS Dly: 6 (0~37)
2540 11:45:56.020322 ==
2541 11:45:56.023579 Dram Type= 6, Freq= 0, CH_0, rank 1
2542 11:45:56.030768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 11:45:56.030855 ==
2544 11:45:56.033814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2545 11:45:56.040389 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2546 11:45:56.049397 [CA 0] Center 38 (7~69) winsize 63
2547 11:45:56.052806 [CA 1] Center 38 (7~69) winsize 63
2548 11:45:56.056147 [CA 2] Center 35 (5~66) winsize 62
2549 11:45:56.059568 [CA 3] Center 35 (4~66) winsize 63
2550 11:45:56.062786 [CA 4] Center 34 (4~65) winsize 62
2551 11:45:56.066199 [CA 5] Center 33 (3~64) winsize 62
2552 11:45:56.066285
2553 11:45:56.069414 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2554 11:45:56.069501
2555 11:45:56.073032 [CATrainingPosCal] consider 2 rank data
2556 11:45:56.075943 u2DelayCellTimex100 = 270/100 ps
2557 11:45:56.079632 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2558 11:45:56.082891 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2559 11:45:56.089425 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2560 11:45:56.092759 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2561 11:45:56.096007 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2562 11:45:56.099402 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2563 11:45:56.099516
2564 11:45:56.102753 CA PerBit enable=1, Macro0, CA PI delay=33
2565 11:45:56.102828
2566 11:45:56.105826 [CBTSetCACLKResult] CA Dly = 33
2567 11:45:56.105914 CS Dly: 7 (0~39)
2568 11:45:56.105983
2569 11:45:56.109425 ----->DramcWriteLeveling(PI) begin...
2570 11:45:56.112543 ==
2571 11:45:56.112630 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 11:45:56.119376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 11:45:56.119483 ==
2574 11:45:56.122764 Write leveling (Byte 0): 36 => 36
2575 11:45:56.126417 Write leveling (Byte 1): 31 => 31
2576 11:45:56.126503 DramcWriteLeveling(PI) end<-----
2577 11:45:56.129363
2578 11:45:56.129443 ==
2579 11:45:56.132540 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 11:45:56.136078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 11:45:56.136157 ==
2582 11:45:56.139815 [Gating] SW mode calibration
2583 11:45:56.146040 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2584 11:45:56.149533 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2585 11:45:56.155978 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2586 11:45:56.159598 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2587 11:45:56.162682 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 11:45:56.169283 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 11:45:56.172819 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 11:45:56.176307 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 11:45:56.182698 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2592 11:45:56.186215 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2593 11:45:56.189708 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
2594 11:45:56.196363 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 11:45:56.199799 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 11:45:56.202724 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 11:45:56.206327 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 11:45:56.212825 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 11:45:56.216513 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2600 11:45:56.219637 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2601 11:45:56.226188 1 1 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
2602 11:45:56.229758 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 11:45:56.232846 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 11:45:56.239818 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 11:45:56.243171 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 11:45:56.246046 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 11:45:56.252924 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 11:45:56.256307 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2609 11:45:56.259955 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2610 11:45:56.266133 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2611 11:45:56.269529 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 11:45:56.273402 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 11:45:56.279624 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 11:45:56.283151 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 11:45:56.286412 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 11:45:56.289868 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 11:45:56.296778 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:45:56.299741 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:45:56.303234 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:45:56.309592 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:45:56.313419 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:45:56.316535 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:45:56.323007 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 11:45:56.326605 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2625 11:45:56.330018 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 11:45:56.333236 Total UI for P1: 0, mck2ui 16
2627 11:45:56.336718 best dqsien dly found for B0: ( 1, 3, 26)
2628 11:45:56.339994 Total UI for P1: 0, mck2ui 16
2629 11:45:56.343096 best dqsien dly found for B1: ( 1, 3, 28)
2630 11:45:56.346420 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2631 11:45:56.350002 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2632 11:45:56.350083
2633 11:45:56.353134 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2634 11:45:56.359945 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2635 11:45:56.360053 [Gating] SW calibration Done
2636 11:45:56.360151 ==
2637 11:45:56.363186 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 11:45:56.370390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 11:45:56.370481 ==
2640 11:45:56.370553 RX Vref Scan: 0
2641 11:45:56.370617
2642 11:45:56.373314 RX Vref 0 -> 0, step: 1
2643 11:45:56.373396
2644 11:45:56.376806 RX Delay -40 -> 252, step: 8
2645 11:45:56.380180 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2646 11:45:56.383564 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2647 11:45:56.386805 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2648 11:45:56.393527 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2649 11:45:56.396582 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2650 11:45:56.400107 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2651 11:45:56.403190 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2652 11:45:56.406694 iDelay=208, Bit 7, Center 131 (56 ~ 207) 152
2653 11:45:56.410209 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2654 11:45:56.416623 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2655 11:45:56.420241 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2656 11:45:56.423568 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2657 11:45:56.426778 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2658 11:45:56.433642 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2659 11:45:56.437153 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2660 11:45:56.440289 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2661 11:45:56.440372 ==
2662 11:45:56.443673 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 11:45:56.446649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 11:45:56.446727 ==
2665 11:45:56.450292 DQS Delay:
2666 11:45:56.450374 DQS0 = 0, DQS1 = 0
2667 11:45:56.450449 DQM Delay:
2668 11:45:56.453435 DQM0 = 123, DQM1 = 110
2669 11:45:56.453515 DQ Delay:
2670 11:45:56.456786 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2671 11:45:56.460318 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =131
2672 11:45:56.463461 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2673 11:45:56.470376 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2674 11:45:56.470465
2675 11:45:56.470532
2676 11:45:56.470598 ==
2677 11:45:56.473480 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 11:45:56.476694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 11:45:56.476773 ==
2680 11:45:56.476839
2681 11:45:56.476900
2682 11:45:56.480243 TX Vref Scan disable
2683 11:45:56.480326 == TX Byte 0 ==
2684 11:45:56.486971 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2685 11:45:56.490224 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2686 11:45:56.490302 == TX Byte 1 ==
2687 11:45:56.496826 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2688 11:45:56.500553 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2689 11:45:56.500631 ==
2690 11:45:56.503867 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 11:45:56.506899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 11:45:56.506978 ==
2693 11:45:56.519480 TX Vref=22, minBit 0, minWin=23, winSum=399
2694 11:45:56.522968 TX Vref=24, minBit 6, minWin=24, winSum=403
2695 11:45:56.526426 TX Vref=26, minBit 5, minWin=24, winSum=409
2696 11:45:56.530144 TX Vref=28, minBit 5, minWin=25, winSum=416
2697 11:45:56.532869 TX Vref=30, minBit 0, minWin=25, winSum=419
2698 11:45:56.536299 TX Vref=32, minBit 1, minWin=25, winSum=413
2699 11:45:56.543051 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 30
2700 11:45:56.543141
2701 11:45:56.546379 Final TX Range 1 Vref 30
2702 11:45:56.546470
2703 11:45:56.546534 ==
2704 11:45:56.549522 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 11:45:56.553117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 11:45:56.553197 ==
2707 11:45:56.553270
2708 11:45:56.556176
2709 11:45:56.556250 TX Vref Scan disable
2710 11:45:56.559548 == TX Byte 0 ==
2711 11:45:56.563029 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2712 11:45:56.566496 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2713 11:45:56.569857 == TX Byte 1 ==
2714 11:45:56.572999 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2715 11:45:56.576300 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2716 11:45:56.576394
2717 11:45:56.579941 [DATLAT]
2718 11:45:56.580069 Freq=1200, CH0 RK0
2719 11:45:56.580172
2720 11:45:56.583075 DATLAT Default: 0xd
2721 11:45:56.583178 0, 0xFFFF, sum = 0
2722 11:45:56.586396 1, 0xFFFF, sum = 0
2723 11:45:56.586524 2, 0xFFFF, sum = 0
2724 11:45:56.589693 3, 0xFFFF, sum = 0
2725 11:45:56.589784 4, 0xFFFF, sum = 0
2726 11:45:56.593252 5, 0xFFFF, sum = 0
2727 11:45:56.593342 6, 0xFFFF, sum = 0
2728 11:45:56.596657 7, 0xFFFF, sum = 0
2729 11:45:56.596747 8, 0xFFFF, sum = 0
2730 11:45:56.599804 9, 0xFFFF, sum = 0
2731 11:45:56.603434 10, 0xFFFF, sum = 0
2732 11:45:56.603525 11, 0xFFFF, sum = 0
2733 11:45:56.603616 12, 0x0, sum = 1
2734 11:45:56.606764 13, 0x0, sum = 2
2735 11:45:56.606854 14, 0x0, sum = 3
2736 11:45:56.610033 15, 0x0, sum = 4
2737 11:45:56.610122 best_step = 13
2738 11:45:56.610210
2739 11:45:56.610313 ==
2740 11:45:56.613105 Dram Type= 6, Freq= 0, CH_0, rank 0
2741 11:45:56.620002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2742 11:45:56.620093 ==
2743 11:45:56.620182 RX Vref Scan: 1
2744 11:45:56.620265
2745 11:45:56.623784 Set Vref Range= 32 -> 127
2746 11:45:56.623873
2747 11:45:56.627337 RX Vref 32 -> 127, step: 1
2748 11:45:56.627426
2749 11:45:56.630123 RX Delay -13 -> 252, step: 4
2750 11:45:56.630229
2751 11:45:56.633540 Set Vref, RX VrefLevel [Byte0]: 32
2752 11:45:56.633645 [Byte1]: 32
2753 11:45:56.637997
2754 11:45:56.638086 Set Vref, RX VrefLevel [Byte0]: 33
2755 11:45:56.641100 [Byte1]: 33
2756 11:45:56.645880
2757 11:45:56.646012 Set Vref, RX VrefLevel [Byte0]: 34
2758 11:45:56.648995 [Byte1]: 34
2759 11:45:56.653935
2760 11:45:56.654029 Set Vref, RX VrefLevel [Byte0]: 35
2761 11:45:56.656903 [Byte1]: 35
2762 11:45:56.661575
2763 11:45:56.661671 Set Vref, RX VrefLevel [Byte0]: 36
2764 11:45:56.664873 [Byte1]: 36
2765 11:45:56.669669
2766 11:45:56.669760 Set Vref, RX VrefLevel [Byte0]: 37
2767 11:45:56.672842 [Byte1]: 37
2768 11:45:56.677541
2769 11:45:56.677647 Set Vref, RX VrefLevel [Byte0]: 38
2770 11:45:56.680739 [Byte1]: 38
2771 11:45:56.685322
2772 11:45:56.685432 Set Vref, RX VrefLevel [Byte0]: 39
2773 11:45:56.688726 [Byte1]: 39
2774 11:45:56.693188
2775 11:45:56.693293 Set Vref, RX VrefLevel [Byte0]: 40
2776 11:45:56.696336 [Byte1]: 40
2777 11:45:56.701078
2778 11:45:56.701181 Set Vref, RX VrefLevel [Byte0]: 41
2779 11:45:56.704279 [Byte1]: 41
2780 11:45:56.709192
2781 11:45:56.709272 Set Vref, RX VrefLevel [Byte0]: 42
2782 11:45:56.712382 [Byte1]: 42
2783 11:45:56.717085
2784 11:45:56.717164 Set Vref, RX VrefLevel [Byte0]: 43
2785 11:45:56.720239 [Byte1]: 43
2786 11:45:56.725010
2787 11:45:56.725116 Set Vref, RX VrefLevel [Byte0]: 44
2788 11:45:56.728216 [Byte1]: 44
2789 11:45:56.733101
2790 11:45:56.733178 Set Vref, RX VrefLevel [Byte0]: 45
2791 11:45:56.736396 [Byte1]: 45
2792 11:45:56.740666
2793 11:45:56.740771 Set Vref, RX VrefLevel [Byte0]: 46
2794 11:45:56.744045 [Byte1]: 46
2795 11:45:56.748324
2796 11:45:56.748406 Set Vref, RX VrefLevel [Byte0]: 47
2797 11:45:56.751916 [Byte1]: 47
2798 11:45:56.756411
2799 11:45:56.756490 Set Vref, RX VrefLevel [Byte0]: 48
2800 11:45:56.759722 [Byte1]: 48
2801 11:45:56.764277
2802 11:45:56.764358 Set Vref, RX VrefLevel [Byte0]: 49
2803 11:45:56.767350 [Byte1]: 49
2804 11:45:56.772140
2805 11:45:56.772215 Set Vref, RX VrefLevel [Byte0]: 50
2806 11:45:56.775573 [Byte1]: 50
2807 11:45:56.779731
2808 11:45:56.783454 Set Vref, RX VrefLevel [Byte0]: 51
2809 11:45:56.786340 [Byte1]: 51
2810 11:45:56.786439
2811 11:45:56.790065 Set Vref, RX VrefLevel [Byte0]: 52
2812 11:45:56.792887 [Byte1]: 52
2813 11:45:56.792992
2814 11:45:56.796552 Set Vref, RX VrefLevel [Byte0]: 53
2815 11:45:56.799625 [Byte1]: 53
2816 11:45:56.803840
2817 11:45:56.803938 Set Vref, RX VrefLevel [Byte0]: 54
2818 11:45:56.806729 [Byte1]: 54
2819 11:45:56.811281
2820 11:45:56.811353 Set Vref, RX VrefLevel [Byte0]: 55
2821 11:45:56.815396 [Byte1]: 55
2822 11:45:56.819358
2823 11:45:56.819432 Set Vref, RX VrefLevel [Byte0]: 56
2824 11:45:56.822678 [Byte1]: 56
2825 11:45:56.827400
2826 11:45:56.827475 Set Vref, RX VrefLevel [Byte0]: 57
2827 11:45:56.830689 [Byte1]: 57
2828 11:45:56.835092
2829 11:45:56.835190 Set Vref, RX VrefLevel [Byte0]: 58
2830 11:45:56.838542 [Byte1]: 58
2831 11:45:56.842964
2832 11:45:56.843043 Set Vref, RX VrefLevel [Byte0]: 59
2833 11:45:56.846211 [Byte1]: 59
2834 11:45:56.850921
2835 11:45:56.850998 Set Vref, RX VrefLevel [Byte0]: 60
2836 11:45:56.854624 [Byte1]: 60
2837 11:45:56.859273
2838 11:45:56.859378 Set Vref, RX VrefLevel [Byte0]: 61
2839 11:45:56.862501 [Byte1]: 61
2840 11:45:56.866702
2841 11:45:56.866781 Set Vref, RX VrefLevel [Byte0]: 62
2842 11:45:56.870219 [Byte1]: 62
2843 11:45:56.874744
2844 11:45:56.874850 Set Vref, RX VrefLevel [Byte0]: 63
2845 11:45:56.877842 [Byte1]: 63
2846 11:45:56.882654
2847 11:45:56.882741 Set Vref, RX VrefLevel [Byte0]: 64
2848 11:45:56.886144 [Byte1]: 64
2849 11:45:56.890281
2850 11:45:56.890391 Set Vref, RX VrefLevel [Byte0]: 65
2851 11:45:56.893917 [Byte1]: 65
2852 11:45:56.898135
2853 11:45:56.898241 Set Vref, RX VrefLevel [Byte0]: 66
2854 11:45:56.901770 [Byte1]: 66
2855 11:45:56.906133
2856 11:45:56.906207 Set Vref, RX VrefLevel [Byte0]: 67
2857 11:45:56.909353 [Byte1]: 67
2858 11:45:56.914028
2859 11:45:56.914133 Set Vref, RX VrefLevel [Byte0]: 68
2860 11:45:56.917506 [Byte1]: 68
2861 11:45:56.921844
2862 11:45:56.921949 Final RX Vref Byte 0 = 57 to rank0
2863 11:45:56.925416 Final RX Vref Byte 1 = 49 to rank0
2864 11:45:56.928791 Final RX Vref Byte 0 = 57 to rank1
2865 11:45:56.931905 Final RX Vref Byte 1 = 49 to rank1==
2866 11:45:56.935343 Dram Type= 6, Freq= 0, CH_0, rank 0
2867 11:45:56.942288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 11:45:56.942419 ==
2869 11:45:56.942493 DQS Delay:
2870 11:45:56.942560 DQS0 = 0, DQS1 = 0
2871 11:45:56.945204 DQM Delay:
2872 11:45:56.945310 DQM0 = 122, DQM1 = 109
2873 11:45:56.948664 DQ Delay:
2874 11:45:56.951859 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2875 11:45:56.955232 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2876 11:45:56.958712 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2877 11:45:56.962361 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =118
2878 11:45:56.962450
2879 11:45:56.962521
2880 11:45:56.968559 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2881 11:45:56.971984 CH0 RK0: MR19=404, MR18=B08
2882 11:45:56.978340 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2883 11:45:56.978446
2884 11:45:56.981857 ----->DramcWriteLeveling(PI) begin...
2885 11:45:56.981970 ==
2886 11:45:56.985528 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 11:45:56.988408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 11:45:56.988528 ==
2889 11:45:56.991795 Write leveling (Byte 0): 35 => 35
2890 11:45:56.995509 Write leveling (Byte 1): 29 => 29
2891 11:45:56.998551 DramcWriteLeveling(PI) end<-----
2892 11:45:56.998648
2893 11:45:56.998716 ==
2894 11:45:57.001845 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 11:45:57.005705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 11:45:57.009116 ==
2897 11:45:57.009196 [Gating] SW mode calibration
2898 11:45:57.018747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2899 11:45:57.021974 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2900 11:45:57.025563 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2901 11:45:57.031942 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 11:45:57.035446 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 11:45:57.038758 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 11:45:57.045487 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 11:45:57.048783 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 11:45:57.052390 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 11:45:57.058851 0 15 28 | B1->B0 | 2c2c 2a2a | 0 0 | (1 0) (1 0)
2908 11:45:57.061968 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 11:45:57.065286 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 11:45:57.072040 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 11:45:57.075513 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 11:45:57.078773 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 11:45:57.085587 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 11:45:57.088687 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2915 11:45:57.092260 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2916 11:45:57.095614 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 11:45:57.102235 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 11:45:57.105485 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 11:45:57.108696 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 11:45:57.115572 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 11:45:57.118723 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:45:57.122571 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 11:45:57.128899 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2924 11:45:57.132109 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2925 11:45:57.135624 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 11:45:57.142140 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 11:45:57.145907 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:45:57.149032 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:45:57.155690 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:45:57.159390 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:45:57.162393 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:45:57.165753 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:45:57.172207 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:45:57.176128 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:45:57.179190 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:45:57.185887 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:45:57.189151 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:45:57.192589 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:45:57.199112 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2940 11:45:57.202557 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 11:45:57.205752 Total UI for P1: 0, mck2ui 16
2942 11:45:57.208975 best dqsien dly found for B0: ( 1, 3, 28)
2943 11:45:57.212517 Total UI for P1: 0, mck2ui 16
2944 11:45:57.215761 best dqsien dly found for B1: ( 1, 3, 28)
2945 11:45:57.219289 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2946 11:45:57.222534 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2947 11:45:57.222640
2948 11:45:57.226085 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2949 11:45:57.229459 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2950 11:45:57.232627 [Gating] SW calibration Done
2951 11:45:57.232709 ==
2952 11:45:57.235896 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 11:45:57.239250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 11:45:57.239358 ==
2955 11:45:57.242557 RX Vref Scan: 0
2956 11:45:57.242637
2957 11:45:57.245881 RX Vref 0 -> 0, step: 1
2958 11:45:57.245957
2959 11:45:57.246024 RX Delay -40 -> 252, step: 8
2960 11:45:57.252402 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2961 11:45:57.255808 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2962 11:45:57.259251 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2963 11:45:57.262773 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2964 11:45:57.265968 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2965 11:45:57.272582 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2966 11:45:57.275812 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2967 11:45:57.279164 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2968 11:45:57.282517 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2969 11:45:57.286095 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2970 11:45:57.292763 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2971 11:45:57.296084 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2972 11:45:57.299264 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2973 11:45:57.302771 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2974 11:45:57.305948 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2975 11:45:57.312673 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2976 11:45:57.312780 ==
2977 11:45:57.315826 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 11:45:57.319252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 11:45:57.319328 ==
2980 11:45:57.319395 DQS Delay:
2981 11:45:57.322761 DQS0 = 0, DQS1 = 0
2982 11:45:57.322839 DQM Delay:
2983 11:45:57.326144 DQM0 = 120, DQM1 = 108
2984 11:45:57.326243 DQ Delay:
2985 11:45:57.329362 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2986 11:45:57.332859 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2987 11:45:57.336166 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2988 11:45:57.339253 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2989 11:45:57.339354
2990 11:45:57.339448
2991 11:45:57.339537 ==
2992 11:45:57.342991 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 11:45:57.349631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 11:45:57.349745 ==
2995 11:45:57.349840
2996 11:45:57.349945
2997 11:45:57.350049 TX Vref Scan disable
2998 11:45:57.353153 == TX Byte 0 ==
2999 11:45:57.356469 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3000 11:45:57.363001 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3001 11:45:57.363091 == TX Byte 1 ==
3002 11:45:57.366487 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3003 11:45:57.369959 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3004 11:45:57.372847 ==
3005 11:45:57.376471 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 11:45:57.379902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 11:45:57.380007 ==
3008 11:45:57.391313 TX Vref=22, minBit 4, minWin=24, winSum=401
3009 11:45:57.394903 TX Vref=24, minBit 5, minWin=24, winSum=405
3010 11:45:57.398054 TX Vref=26, minBit 0, minWin=24, winSum=408
3011 11:45:57.401197 TX Vref=28, minBit 0, minWin=25, winSum=415
3012 11:45:57.405110 TX Vref=30, minBit 2, minWin=25, winSum=418
3013 11:45:57.408143 TX Vref=32, minBit 0, minWin=25, winSum=414
3014 11:45:57.415101 [TxChooseVref] Worse bit 2, Min win 25, Win sum 418, Final Vref 30
3015 11:45:57.415210
3016 11:45:57.418022 Final TX Range 1 Vref 30
3017 11:45:57.418136
3018 11:45:57.418240 ==
3019 11:45:57.421289 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 11:45:57.424764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 11:45:57.424868 ==
3022 11:45:57.424961
3023 11:45:57.425051
3024 11:45:57.427947 TX Vref Scan disable
3025 11:45:57.431709 == TX Byte 0 ==
3026 11:45:57.434753 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3027 11:45:57.438045 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3028 11:45:57.441575 == TX Byte 1 ==
3029 11:45:57.444927 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3030 11:45:57.448042 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3031 11:45:57.448124
3032 11:45:57.451403 [DATLAT]
3033 11:45:57.451480 Freq=1200, CH0 RK1
3034 11:45:57.451547
3035 11:45:57.454811 DATLAT Default: 0xd
3036 11:45:57.454888 0, 0xFFFF, sum = 0
3037 11:45:57.458125 1, 0xFFFF, sum = 0
3038 11:45:57.458228 2, 0xFFFF, sum = 0
3039 11:45:57.461394 3, 0xFFFF, sum = 0
3040 11:45:57.461496 4, 0xFFFF, sum = 0
3041 11:45:57.464783 5, 0xFFFF, sum = 0
3042 11:45:57.464859 6, 0xFFFF, sum = 0
3043 11:45:57.468137 7, 0xFFFF, sum = 0
3044 11:45:57.468211 8, 0xFFFF, sum = 0
3045 11:45:57.471682 9, 0xFFFF, sum = 0
3046 11:45:57.474784 10, 0xFFFF, sum = 0
3047 11:45:57.474859 11, 0xFFFF, sum = 0
3048 11:45:57.477946 12, 0x0, sum = 1
3049 11:45:57.478019 13, 0x0, sum = 2
3050 11:45:57.478094 14, 0x0, sum = 3
3051 11:45:57.481630 15, 0x0, sum = 4
3052 11:45:57.481737 best_step = 13
3053 11:45:57.481830
3054 11:45:57.481921 ==
3055 11:45:57.485401 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 11:45:57.491340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 11:45:57.491442 ==
3058 11:45:57.491536 RX Vref Scan: 0
3059 11:45:57.491628
3060 11:45:57.494905 RX Vref 0 -> 0, step: 1
3061 11:45:57.494978
3062 11:45:57.498087 RX Delay -21 -> 252, step: 4
3063 11:45:57.501433 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3064 11:45:57.504668 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3065 11:45:57.511449 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3066 11:45:57.514975 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3067 11:45:57.518371 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3068 11:45:57.521714 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3069 11:45:57.525098 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3070 11:45:57.531787 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3071 11:45:57.534955 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3072 11:45:57.538294 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3073 11:45:57.541893 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3074 11:45:57.545249 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3075 11:45:57.548205 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3076 11:45:57.555143 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3077 11:45:57.558568 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3078 11:45:57.561756 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3079 11:45:57.561862 ==
3080 11:45:57.565135 Dram Type= 6, Freq= 0, CH_0, rank 1
3081 11:45:57.568310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 11:45:57.571515 ==
3083 11:45:57.571594 DQS Delay:
3084 11:45:57.571662 DQS0 = 0, DQS1 = 0
3085 11:45:57.575060 DQM Delay:
3086 11:45:57.575161 DQM0 = 119, DQM1 = 107
3087 11:45:57.578397 DQ Delay:
3088 11:45:57.581843 DQ0 =116, DQ1 =122, DQ2 =116, DQ3 =114
3089 11:45:57.584997 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3090 11:45:57.588720 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3091 11:45:57.592129 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3092 11:45:57.592210
3093 11:45:57.592274
3094 11:45:57.598820 [DQSOSCAuto] RK1, (LSB)MR18= 0xef6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3095 11:45:57.601701 CH0 RK1: MR19=403, MR18=EF6
3096 11:45:57.608700 CH0_RK1: MR19=0x403, MR18=0xEF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3097 11:45:57.611980 [RxdqsGatingPostProcess] freq 1200
3098 11:45:57.615511 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3099 11:45:57.618356 best DQS0 dly(2T, 0.5T) = (0, 11)
3100 11:45:57.622193 best DQS1 dly(2T, 0.5T) = (0, 11)
3101 11:45:57.625487 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3102 11:45:57.628734 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3103 11:45:57.632091 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 11:45:57.635699 best DQS1 dly(2T, 0.5T) = (0, 11)
3105 11:45:57.638778 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 11:45:57.641936 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3107 11:45:57.645782 Pre-setting of DQS Precalculation
3108 11:45:57.648943 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3109 11:45:57.649024 ==
3110 11:45:57.652214 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 11:45:57.658944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 11:45:57.659053 ==
3113 11:45:57.662134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3114 11:45:57.668760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3115 11:45:57.677314 [CA 0] Center 37 (7~67) winsize 61
3116 11:45:57.680428 [CA 1] Center 37 (7~68) winsize 62
3117 11:45:57.684127 [CA 2] Center 34 (4~65) winsize 62
3118 11:45:57.687139 [CA 3] Center 33 (3~64) winsize 62
3119 11:45:57.690726 [CA 4] Center 33 (3~64) winsize 62
3120 11:45:57.693996 [CA 5] Center 33 (3~63) winsize 61
3121 11:45:57.694104
3122 11:45:57.697413 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3123 11:45:57.697518
3124 11:45:57.700787 [CATrainingPosCal] consider 1 rank data
3125 11:45:57.703961 u2DelayCellTimex100 = 270/100 ps
3126 11:45:57.707250 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3127 11:45:57.711143 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3128 11:45:57.714239 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3129 11:45:57.720940 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3130 11:45:57.723983 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3131 11:45:57.727669 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3132 11:45:57.727774
3133 11:45:57.730688 CA PerBit enable=1, Macro0, CA PI delay=33
3134 11:45:57.730765
3135 11:45:57.733892 [CBTSetCACLKResult] CA Dly = 33
3136 11:45:57.734002 CS Dly: 5 (0~36)
3137 11:45:57.734104 ==
3138 11:45:57.737143 Dram Type= 6, Freq= 0, CH_1, rank 1
3139 11:45:57.744136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 11:45:57.744254 ==
3141 11:45:57.747256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3142 11:45:57.753989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3143 11:45:57.763171 [CA 0] Center 38 (8~68) winsize 61
3144 11:45:57.766120 [CA 1] Center 37 (7~68) winsize 62
3145 11:45:57.769725 [CA 2] Center 35 (4~66) winsize 63
3146 11:45:57.773016 [CA 3] Center 34 (4~65) winsize 62
3147 11:45:57.776313 [CA 4] Center 34 (4~64) winsize 61
3148 11:45:57.779517 [CA 5] Center 33 (3~64) winsize 62
3149 11:45:57.779619
3150 11:45:57.782794 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3151 11:45:57.782910
3152 11:45:57.786271 [CATrainingPosCal] consider 2 rank data
3153 11:45:57.789531 u2DelayCellTimex100 = 270/100 ps
3154 11:45:57.793181 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3155 11:45:57.796516 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3156 11:45:57.803024 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3157 11:45:57.806541 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3158 11:45:57.809516 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 11:45:57.813270 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3160 11:45:57.813376
3161 11:45:57.816404 CA PerBit enable=1, Macro0, CA PI delay=33
3162 11:45:57.816504
3163 11:45:57.819723 [CBTSetCACLKResult] CA Dly = 33
3164 11:45:57.819801 CS Dly: 6 (0~38)
3165 11:45:57.819872
3166 11:45:57.823554 ----->DramcWriteLeveling(PI) begin...
3167 11:45:57.823664 ==
3168 11:45:57.826600 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 11:45:57.833020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 11:45:57.833110 ==
3171 11:45:57.836454 Write leveling (Byte 0): 24 => 24
3172 11:45:57.839523 Write leveling (Byte 1): 27 => 27
3173 11:45:57.839629 DramcWriteLeveling(PI) end<-----
3174 11:45:57.842973
3175 11:45:57.843054 ==
3176 11:45:57.846239 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 11:45:57.849525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 11:45:57.849632 ==
3179 11:45:57.852976 [Gating] SW mode calibration
3180 11:45:57.859961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3181 11:45:57.863134 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3182 11:45:57.869616 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 11:45:57.872892 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 11:45:57.876173 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 11:45:57.883255 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 11:45:57.886413 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 11:45:57.889983 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3188 11:45:57.896234 0 15 24 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (0 1)
3189 11:45:57.899849 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3190 11:45:57.903663 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 11:45:57.909803 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 11:45:57.913116 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 11:45:57.916452 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 11:45:57.923254 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 11:45:57.926435 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3196 11:45:57.929840 1 0 24 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
3197 11:45:57.933219 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 11:45:57.939917 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 11:45:57.943254 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 11:45:57.946510 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 11:45:57.953527 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 11:45:57.956498 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:45:57.959858 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3204 11:45:57.966457 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3205 11:45:57.970135 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3206 11:45:57.973229 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 11:45:57.979964 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 11:45:57.983311 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 11:45:57.986555 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 11:45:57.993133 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:45:57.997094 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:45:58.000051 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:45:58.003273 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:45:58.010307 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:45:58.013661 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:45:58.016878 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:45:58.023239 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:45:58.026510 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:45:58.030127 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3220 11:45:58.036991 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3221 11:45:58.040298 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 11:45:58.043473 Total UI for P1: 0, mck2ui 16
3223 11:45:58.046522 best dqsien dly found for B0: ( 1, 3, 22)
3224 11:45:58.049954 Total UI for P1: 0, mck2ui 16
3225 11:45:58.053564 best dqsien dly found for B1: ( 1, 3, 24)
3226 11:45:58.056865 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3227 11:45:58.060104 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3228 11:45:58.060206
3229 11:45:58.063515 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3230 11:45:58.066869 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3231 11:45:58.070725 [Gating] SW calibration Done
3232 11:45:58.070805 ==
3233 11:45:58.073600 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 11:45:58.076800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 11:45:58.076909 ==
3236 11:45:58.080682 RX Vref Scan: 0
3237 11:45:58.080787
3238 11:45:58.083498 RX Vref 0 -> 0, step: 1
3239 11:45:58.083617
3240 11:45:58.083713 RX Delay -40 -> 252, step: 8
3241 11:45:58.090341 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3242 11:45:58.093682 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3243 11:45:58.096908 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3244 11:45:58.100656 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3245 11:45:58.103765 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3246 11:45:58.110350 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3247 11:45:58.113733 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3248 11:45:58.117076 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3249 11:45:58.120679 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3250 11:45:58.123985 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3251 11:45:58.126962 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3252 11:45:58.133718 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3253 11:45:58.137208 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3254 11:45:58.140448 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3255 11:45:58.143611 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3256 11:45:58.150510 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3257 11:45:58.150606 ==
3258 11:45:58.154185 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 11:45:58.156940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 11:45:58.157051 ==
3261 11:45:58.157146 DQS Delay:
3262 11:45:58.160247 DQS0 = 0, DQS1 = 0
3263 11:45:58.160349 DQM Delay:
3264 11:45:58.163789 DQM0 = 120, DQM1 = 112
3265 11:45:58.163864 DQ Delay:
3266 11:45:58.167200 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3267 11:45:58.170534 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3268 11:45:58.174147 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3269 11:45:58.177139 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3270 11:45:58.177241
3271 11:45:58.177344
3272 11:45:58.177435 ==
3273 11:45:58.180302 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 11:45:58.187192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 11:45:58.187302 ==
3276 11:45:58.187396
3277 11:45:58.187491
3278 11:45:58.187581 TX Vref Scan disable
3279 11:45:58.190605 == TX Byte 0 ==
3280 11:45:58.193912 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3281 11:45:58.201071 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3282 11:45:58.201176 == TX Byte 1 ==
3283 11:45:58.204299 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3284 11:45:58.207496 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3285 11:45:58.210908 ==
3286 11:45:58.214288 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 11:45:58.217342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 11:45:58.217447 ==
3289 11:45:58.228665 TX Vref=22, minBit 1, minWin=24, winSum=399
3290 11:45:58.231730 TX Vref=24, minBit 1, minWin=24, winSum=404
3291 11:45:58.234981 TX Vref=26, minBit 10, minWin=23, winSum=409
3292 11:45:58.238617 TX Vref=28, minBit 3, minWin=25, winSum=413
3293 11:45:58.241735 TX Vref=30, minBit 14, minWin=24, winSum=419
3294 11:45:58.248549 TX Vref=32, minBit 10, minWin=25, winSum=419
3295 11:45:58.251655 [TxChooseVref] Worse bit 10, Min win 25, Win sum 419, Final Vref 32
3296 11:45:58.251731
3297 11:45:58.255429 Final TX Range 1 Vref 32
3298 11:45:58.255510
3299 11:45:58.255583 ==
3300 11:45:58.258279 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 11:45:58.261697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3302 11:45:58.264814 ==
3303 11:45:58.264922
3304 11:45:58.265014
3305 11:45:58.265107 TX Vref Scan disable
3306 11:45:58.268354 == TX Byte 0 ==
3307 11:45:58.272110 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3308 11:45:58.275485 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3309 11:45:58.278630 == TX Byte 1 ==
3310 11:45:58.281641 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3311 11:45:58.285077 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3312 11:45:58.288390
3313 11:45:58.288494 [DATLAT]
3314 11:45:58.288592 Freq=1200, CH1 RK0
3315 11:45:58.288687
3316 11:45:58.291879 DATLAT Default: 0xd
3317 11:45:58.291984 0, 0xFFFF, sum = 0
3318 11:45:58.295253 1, 0xFFFF, sum = 0
3319 11:45:58.295367 2, 0xFFFF, sum = 0
3320 11:45:58.298439 3, 0xFFFF, sum = 0
3321 11:45:58.298531 4, 0xFFFF, sum = 0
3322 11:45:58.301697 5, 0xFFFF, sum = 0
3323 11:45:58.305021 6, 0xFFFF, sum = 0
3324 11:45:58.305126 7, 0xFFFF, sum = 0
3325 11:45:58.309224 8, 0xFFFF, sum = 0
3326 11:45:58.309331 9, 0xFFFF, sum = 0
3327 11:45:58.311624 10, 0xFFFF, sum = 0
3328 11:45:58.311705 11, 0xFFFF, sum = 0
3329 11:45:58.315072 12, 0x0, sum = 1
3330 11:45:58.315148 13, 0x0, sum = 2
3331 11:45:58.318649 14, 0x0, sum = 3
3332 11:45:58.318725 15, 0x0, sum = 4
3333 11:45:58.318794 best_step = 13
3334 11:45:58.318862
3335 11:45:58.321651 ==
3336 11:45:58.325169 Dram Type= 6, Freq= 0, CH_1, rank 0
3337 11:45:58.328608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3338 11:45:58.328721 ==
3339 11:45:58.328818 RX Vref Scan: 1
3340 11:45:58.328911
3341 11:45:58.331647 Set Vref Range= 32 -> 127
3342 11:45:58.331749
3343 11:45:58.335145 RX Vref 32 -> 127, step: 1
3344 11:45:58.335219
3345 11:45:58.338721 RX Delay -13 -> 252, step: 4
3346 11:45:58.338825
3347 11:45:58.342150 Set Vref, RX VrefLevel [Byte0]: 32
3348 11:45:58.345009 [Byte1]: 32
3349 11:45:58.345116
3350 11:45:58.348665 Set Vref, RX VrefLevel [Byte0]: 33
3351 11:45:58.351858 [Byte1]: 33
3352 11:45:58.351954
3353 11:45:58.355207 Set Vref, RX VrefLevel [Byte0]: 34
3354 11:45:58.358268 [Byte1]: 34
3355 11:45:58.362816
3356 11:45:58.362892 Set Vref, RX VrefLevel [Byte0]: 35
3357 11:45:58.366103 [Byte1]: 35
3358 11:45:58.370561
3359 11:45:58.370637 Set Vref, RX VrefLevel [Byte0]: 36
3360 11:45:58.374018 [Byte1]: 36
3361 11:45:58.378558
3362 11:45:58.378670 Set Vref, RX VrefLevel [Byte0]: 37
3363 11:45:58.381725 [Byte1]: 37
3364 11:45:58.386346
3365 11:45:58.386515 Set Vref, RX VrefLevel [Byte0]: 38
3366 11:45:58.389828 [Byte1]: 38
3367 11:45:58.394362
3368 11:45:58.394523 Set Vref, RX VrefLevel [Byte0]: 39
3369 11:45:58.397522 [Byte1]: 39
3370 11:45:58.402246
3371 11:45:58.402353 Set Vref, RX VrefLevel [Byte0]: 40
3372 11:45:58.405650 [Byte1]: 40
3373 11:45:58.410173
3374 11:45:58.410276 Set Vref, RX VrefLevel [Byte0]: 41
3375 11:45:58.413627 [Byte1]: 41
3376 11:45:58.417739
3377 11:45:58.417885 Set Vref, RX VrefLevel [Byte0]: 42
3378 11:45:58.421155 [Byte1]: 42
3379 11:45:58.425828
3380 11:45:58.425975 Set Vref, RX VrefLevel [Byte0]: 43
3381 11:45:58.429259 [Byte1]: 43
3382 11:45:58.433801
3383 11:45:58.433921 Set Vref, RX VrefLevel [Byte0]: 44
3384 11:45:58.437151 [Byte1]: 44
3385 11:45:58.441502
3386 11:45:58.441610 Set Vref, RX VrefLevel [Byte0]: 45
3387 11:45:58.444855 [Byte1]: 45
3388 11:45:58.449526
3389 11:45:58.449634 Set Vref, RX VrefLevel [Byte0]: 46
3390 11:45:58.452511 [Byte1]: 46
3391 11:45:58.457337
3392 11:45:58.457435 Set Vref, RX VrefLevel [Byte0]: 47
3393 11:45:58.460789 [Byte1]: 47
3394 11:45:58.465048
3395 11:45:58.465148 Set Vref, RX VrefLevel [Byte0]: 48
3396 11:45:58.468365 [Byte1]: 48
3397 11:45:58.473130
3398 11:45:58.473235 Set Vref, RX VrefLevel [Byte0]: 49
3399 11:45:58.476432 [Byte1]: 49
3400 11:45:58.481008
3401 11:45:58.481112 Set Vref, RX VrefLevel [Byte0]: 50
3402 11:45:58.484495 [Byte1]: 50
3403 11:45:58.488928
3404 11:45:58.489033 Set Vref, RX VrefLevel [Byte0]: 51
3405 11:45:58.492047 [Byte1]: 51
3406 11:45:58.496896
3407 11:45:58.497009 Set Vref, RX VrefLevel [Byte0]: 52
3408 11:45:58.500359 [Byte1]: 52
3409 11:45:58.504576
3410 11:45:58.504685 Set Vref, RX VrefLevel [Byte0]: 53
3411 11:45:58.508175 [Byte1]: 53
3412 11:45:58.512723
3413 11:45:58.512841 Set Vref, RX VrefLevel [Byte0]: 54
3414 11:45:58.515870 [Byte1]: 54
3415 11:45:58.520689
3416 11:45:58.520797 Set Vref, RX VrefLevel [Byte0]: 55
3417 11:45:58.523919 [Byte1]: 55
3418 11:45:58.528571
3419 11:45:58.528674 Set Vref, RX VrefLevel [Byte0]: 56
3420 11:45:58.531569 [Byte1]: 56
3421 11:45:58.536750
3422 11:45:58.536859 Set Vref, RX VrefLevel [Byte0]: 57
3423 11:45:58.539764 [Byte1]: 57
3424 11:45:58.544088
3425 11:45:58.544193 Set Vref, RX VrefLevel [Byte0]: 58
3426 11:45:58.547365 [Byte1]: 58
3427 11:45:58.552057
3428 11:45:58.552160 Set Vref, RX VrefLevel [Byte0]: 59
3429 11:45:58.555335 [Byte1]: 59
3430 11:45:58.560003
3431 11:45:58.560106 Set Vref, RX VrefLevel [Byte0]: 60
3432 11:45:58.563477 [Byte1]: 60
3433 11:45:58.567594
3434 11:45:58.567666 Set Vref, RX VrefLevel [Byte0]: 61
3435 11:45:58.571106 [Byte1]: 61
3436 11:45:58.575677
3437 11:45:58.575775 Set Vref, RX VrefLevel [Byte0]: 62
3438 11:45:58.578804 [Byte1]: 62
3439 11:45:58.583545
3440 11:45:58.583655 Set Vref, RX VrefLevel [Byte0]: 63
3441 11:45:58.586852 [Byte1]: 63
3442 11:45:58.591496
3443 11:45:58.591607 Set Vref, RX VrefLevel [Byte0]: 64
3444 11:45:58.594690 [Byte1]: 64
3445 11:45:58.599742
3446 11:45:58.599850 Set Vref, RX VrefLevel [Byte0]: 65
3447 11:45:58.602829 [Byte1]: 65
3448 11:45:58.607402
3449 11:45:58.607498 Set Vref, RX VrefLevel [Byte0]: 66
3450 11:45:58.610430 [Byte1]: 66
3451 11:45:58.614995
3452 11:45:58.615102 Set Vref, RX VrefLevel [Byte0]: 67
3453 11:45:58.618640 [Byte1]: 67
3454 11:45:58.623107
3455 11:45:58.623178 Final RX Vref Byte 0 = 50 to rank0
3456 11:45:58.626463 Final RX Vref Byte 1 = 52 to rank0
3457 11:45:58.630255 Final RX Vref Byte 0 = 50 to rank1
3458 11:45:58.633088 Final RX Vref Byte 1 = 52 to rank1==
3459 11:45:58.636542 Dram Type= 6, Freq= 0, CH_1, rank 0
3460 11:45:58.643240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3461 11:45:58.643348 ==
3462 11:45:58.643447 DQS Delay:
3463 11:45:58.643544 DQS0 = 0, DQS1 = 0
3464 11:45:58.646246 DQM Delay:
3465 11:45:58.646363 DQM0 = 119, DQM1 = 112
3466 11:45:58.649635 DQ Delay:
3467 11:45:58.652979 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =116
3468 11:45:58.656313 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3469 11:45:58.659996 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104
3470 11:45:58.663191 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3471 11:45:58.663289
3472 11:45:58.663365
3473 11:45:58.669965 [DQSOSCAuto] RK0, (LSB)MR18= 0x115, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3474 11:45:58.672943 CH1 RK0: MR19=404, MR18=115
3475 11:45:58.679643 CH1_RK0: MR19=0x404, MR18=0x115, DQSOSC=401, MR23=63, INC=40, DEC=27
3476 11:45:58.679749
3477 11:45:58.683424 ----->DramcWriteLeveling(PI) begin...
3478 11:45:58.683530 ==
3479 11:45:58.686638 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 11:45:58.689639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3481 11:45:58.689735 ==
3482 11:45:58.693202 Write leveling (Byte 0): 25 => 25
3483 11:45:58.696560 Write leveling (Byte 1): 28 => 28
3484 11:45:58.699958 DramcWriteLeveling(PI) end<-----
3485 11:45:58.700060
3486 11:45:58.700186 ==
3487 11:45:58.703447 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 11:45:58.706379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 11:45:58.709742 ==
3490 11:45:58.709842 [Gating] SW mode calibration
3491 11:45:58.719784 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3492 11:45:58.723285 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3493 11:45:58.726538 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 11:45:58.733327 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 11:45:58.736939 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 11:45:58.739815 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 11:45:58.746678 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 11:45:58.749966 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 11:45:58.753263 0 15 24 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 0)
3500 11:45:58.759771 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3501 11:45:58.763123 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 11:45:58.766572 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 11:45:58.773202 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 11:45:58.776740 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 11:45:58.780149 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 11:45:58.783613 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 11:45:58.790232 1 0 24 | B1->B0 | 3f3f 2f2f | 0 1 | (0 0) (0 0)
3508 11:45:58.793749 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3509 11:45:58.797202 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 11:45:58.803426 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 11:45:58.806860 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 11:45:58.810152 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 11:45:58.816803 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 11:45:58.820068 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 11:45:58.823246 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3516 11:45:58.830406 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3517 11:45:58.833321 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 11:45:58.836855 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 11:45:58.843460 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 11:45:58.846847 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 11:45:58.850113 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 11:45:58.856653 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 11:45:58.859990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 11:45:58.863233 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 11:45:58.866737 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 11:45:58.873362 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 11:45:58.876513 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 11:45:58.880166 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 11:45:58.887018 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 11:45:58.889924 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3531 11:45:58.893036 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3532 11:45:58.899952 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 11:45:58.903448 Total UI for P1: 0, mck2ui 16
3534 11:45:58.906758 best dqsien dly found for B0: ( 1, 3, 24)
3535 11:45:58.909682 Total UI for P1: 0, mck2ui 16
3536 11:45:58.913014 best dqsien dly found for B1: ( 1, 3, 22)
3537 11:45:58.916631 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3538 11:45:58.919640 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3539 11:45:58.919725
3540 11:45:58.923212 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3541 11:45:58.926451 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3542 11:45:58.929956 [Gating] SW calibration Done
3543 11:45:58.930040 ==
3544 11:45:58.933006 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 11:45:58.936459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 11:45:58.936608 ==
3547 11:45:58.939950 RX Vref Scan: 0
3548 11:45:58.940034
3549 11:45:58.940102 RX Vref 0 -> 0, step: 1
3550 11:45:58.942870
3551 11:45:58.942955 RX Delay -40 -> 252, step: 8
3552 11:45:58.949621 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3553 11:45:58.952775 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3554 11:45:58.956034 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3555 11:45:58.959455 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3556 11:45:58.962689 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3557 11:45:58.969231 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3558 11:45:58.972592 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3559 11:45:58.975888 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3560 11:45:58.979510 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3561 11:45:58.982593 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3562 11:45:58.989787 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3563 11:45:58.992745 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3564 11:45:58.996064 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3565 11:45:58.999607 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3566 11:45:59.002644 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3567 11:45:59.009157 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3568 11:45:59.009257 ==
3569 11:45:59.012549 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 11:45:59.016032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 11:45:59.016118 ==
3572 11:45:59.016185 DQS Delay:
3573 11:45:59.019062 DQS0 = 0, DQS1 = 0
3574 11:45:59.019148 DQM Delay:
3575 11:45:59.022608 DQM0 = 119, DQM1 = 112
3576 11:45:59.022693 DQ Delay:
3577 11:45:59.025998 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3578 11:45:59.029899 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3579 11:45:59.032867 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3580 11:45:59.036043 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3581 11:45:59.036128
3582 11:45:59.036195
3583 11:45:59.039403 ==
3584 11:45:59.039488 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 11:45:59.045835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 11:45:59.045922 ==
3587 11:45:59.045989
3588 11:45:59.046095
3589 11:45:59.049157 TX Vref Scan disable
3590 11:45:59.049242 == TX Byte 0 ==
3591 11:45:59.052936 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3592 11:45:59.059507 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3593 11:45:59.059592 == TX Byte 1 ==
3594 11:45:59.062703 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3595 11:45:59.069447 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3596 11:45:59.069532 ==
3597 11:45:59.072225 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 11:45:59.075551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 11:45:59.075636 ==
3600 11:45:59.087781 TX Vref=22, minBit 3, minWin=24, winSum=407
3601 11:45:59.091242 TX Vref=24, minBit 1, minWin=25, winSum=414
3602 11:45:59.094359 TX Vref=26, minBit 1, minWin=25, winSum=422
3603 11:45:59.097834 TX Vref=28, minBit 3, minWin=25, winSum=426
3604 11:45:59.101105 TX Vref=30, minBit 1, minWin=26, winSum=427
3605 11:45:59.104520 TX Vref=32, minBit 9, minWin=25, winSum=423
3606 11:45:59.111211 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
3607 11:45:59.111292
3608 11:45:59.114758 Final TX Range 1 Vref 30
3609 11:45:59.114836
3610 11:45:59.114901 ==
3611 11:45:59.117833 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 11:45:59.121092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 11:45:59.121174 ==
3614 11:45:59.121238
3615 11:45:59.121299
3616 11:45:59.124542 TX Vref Scan disable
3617 11:45:59.127717 == TX Byte 0 ==
3618 11:45:59.131009 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3619 11:45:59.134519 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3620 11:45:59.137641 == TX Byte 1 ==
3621 11:45:59.140868 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3622 11:45:59.144356 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3623 11:45:59.144439
3624 11:45:59.147783 [DATLAT]
3625 11:45:59.147860 Freq=1200, CH1 RK1
3626 11:45:59.147926
3627 11:45:59.151115 DATLAT Default: 0xd
3628 11:45:59.151218 0, 0xFFFF, sum = 0
3629 11:45:59.154670 1, 0xFFFF, sum = 0
3630 11:45:59.154788 2, 0xFFFF, sum = 0
3631 11:45:59.157584 3, 0xFFFF, sum = 0
3632 11:45:59.157680 4, 0xFFFF, sum = 0
3633 11:45:59.161185 5, 0xFFFF, sum = 0
3634 11:45:59.161264 6, 0xFFFF, sum = 0
3635 11:45:59.164505 7, 0xFFFF, sum = 0
3636 11:45:59.167573 8, 0xFFFF, sum = 0
3637 11:45:59.167670 9, 0xFFFF, sum = 0
3638 11:45:59.170971 10, 0xFFFF, sum = 0
3639 11:45:59.171048 11, 0xFFFF, sum = 0
3640 11:45:59.174554 12, 0x0, sum = 1
3641 11:45:59.174642 13, 0x0, sum = 2
3642 11:45:59.177665 14, 0x0, sum = 3
3643 11:45:59.177743 15, 0x0, sum = 4
3644 11:45:59.177806 best_step = 13
3645 11:45:59.177868
3646 11:45:59.180992 ==
3647 11:45:59.184126 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 11:45:59.187474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 11:45:59.187553 ==
3650 11:45:59.187622 RX Vref Scan: 0
3651 11:45:59.187685
3652 11:45:59.190466 RX Vref 0 -> 0, step: 1
3653 11:45:59.190587
3654 11:45:59.193999 RX Delay -13 -> 252, step: 4
3655 11:45:59.197408 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3656 11:45:59.203930 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3657 11:45:59.207433 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3658 11:45:59.211041 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3659 11:45:59.213781 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3660 11:45:59.217287 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3661 11:45:59.224283 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3662 11:45:59.227055 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3663 11:45:59.230431 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3664 11:45:59.233701 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3665 11:45:59.237322 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3666 11:45:59.243604 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3667 11:45:59.247272 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3668 11:45:59.250516 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3669 11:45:59.253924 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3670 11:45:59.257054 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3671 11:45:59.260623 ==
3672 11:45:59.260707 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 11:45:59.267068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 11:45:59.267153 ==
3675 11:45:59.267220 DQS Delay:
3676 11:45:59.270798 DQS0 = 0, DQS1 = 0
3677 11:45:59.270882 DQM Delay:
3678 11:45:59.273633 DQM0 = 119, DQM1 = 113
3679 11:45:59.273717 DQ Delay:
3680 11:45:59.277084 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3681 11:45:59.280863 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3682 11:45:59.284120 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3683 11:45:59.287288 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3684 11:45:59.287374
3685 11:45:59.287441
3686 11:45:59.297177 [DQSOSCAuto] RK1, (LSB)MR18= 0xaee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3687 11:45:59.297265 CH1 RK1: MR19=403, MR18=AEE
3688 11:45:59.303742 CH1_RK1: MR19=0x403, MR18=0xAEE, DQSOSC=406, MR23=63, INC=39, DEC=26
3689 11:45:59.307048 [RxdqsGatingPostProcess] freq 1200
3690 11:45:59.313606 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3691 11:45:59.317102 best DQS0 dly(2T, 0.5T) = (0, 11)
3692 11:45:59.320596 best DQS1 dly(2T, 0.5T) = (0, 11)
3693 11:45:59.323842 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3694 11:45:59.327099 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3695 11:45:59.330345 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 11:45:59.330439 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 11:45:59.333988 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 11:45:59.337034 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 11:45:59.340249 Pre-setting of DQS Precalculation
3700 11:45:59.347354 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3701 11:45:59.353582 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3702 11:45:59.360755 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3703 11:45:59.360842
3704 11:45:59.360910
3705 11:45:59.363429 [Calibration Summary] 2400 Mbps
3706 11:45:59.363515 CH 0, Rank 0
3707 11:45:59.366930 SW Impedance : PASS
3708 11:45:59.370214 DUTY Scan : NO K
3709 11:45:59.370292 ZQ Calibration : PASS
3710 11:45:59.373386 Jitter Meter : NO K
3711 11:45:59.376808 CBT Training : PASS
3712 11:45:59.376882 Write leveling : PASS
3713 11:45:59.379994 RX DQS gating : PASS
3714 11:45:59.383549 RX DQ/DQS(RDDQC) : PASS
3715 11:45:59.383625 TX DQ/DQS : PASS
3716 11:45:59.386737 RX DATLAT : PASS
3717 11:45:59.390103 RX DQ/DQS(Engine): PASS
3718 11:45:59.390210 TX OE : NO K
3719 11:45:59.393268 All Pass.
3720 11:45:59.393369
3721 11:45:59.393452 CH 0, Rank 1
3722 11:45:59.396600 SW Impedance : PASS
3723 11:45:59.396688 DUTY Scan : NO K
3724 11:45:59.400260 ZQ Calibration : PASS
3725 11:45:59.403674 Jitter Meter : NO K
3726 11:45:59.403763 CBT Training : PASS
3727 11:45:59.406802 Write leveling : PASS
3728 11:45:59.406882 RX DQS gating : PASS
3729 11:45:59.410306 RX DQ/DQS(RDDQC) : PASS
3730 11:45:59.413584 TX DQ/DQS : PASS
3731 11:45:59.413673 RX DATLAT : PASS
3732 11:45:59.416686 RX DQ/DQS(Engine): PASS
3733 11:45:59.419972 TX OE : NO K
3734 11:45:59.420061 All Pass.
3735 11:45:59.420148
3736 11:45:59.420230 CH 1, Rank 0
3737 11:45:59.423519 SW Impedance : PASS
3738 11:45:59.426655 DUTY Scan : NO K
3739 11:45:59.426743 ZQ Calibration : PASS
3740 11:45:59.430055 Jitter Meter : NO K
3741 11:45:59.433310 CBT Training : PASS
3742 11:45:59.433398 Write leveling : PASS
3743 11:45:59.436748 RX DQS gating : PASS
3744 11:45:59.440180 RX DQ/DQS(RDDQC) : PASS
3745 11:45:59.440267 TX DQ/DQS : PASS
3746 11:45:59.443150 RX DATLAT : PASS
3747 11:45:59.446780 RX DQ/DQS(Engine): PASS
3748 11:45:59.446893 TX OE : NO K
3749 11:45:59.449691 All Pass.
3750 11:45:59.449779
3751 11:45:59.449865 CH 1, Rank 1
3752 11:45:59.453332 SW Impedance : PASS
3753 11:45:59.453420 DUTY Scan : NO K
3754 11:45:59.456573 ZQ Calibration : PASS
3755 11:45:59.459779 Jitter Meter : NO K
3756 11:45:59.459865 CBT Training : PASS
3757 11:45:59.463086 Write leveling : PASS
3758 11:45:59.463201 RX DQS gating : PASS
3759 11:45:59.466611 RX DQ/DQS(RDDQC) : PASS
3760 11:45:59.470159 TX DQ/DQS : PASS
3761 11:45:59.470246 RX DATLAT : PASS
3762 11:45:59.473062 RX DQ/DQS(Engine): PASS
3763 11:45:59.476669 TX OE : NO K
3764 11:45:59.476774 All Pass.
3765 11:45:59.476867
3766 11:45:59.479726 DramC Write-DBI off
3767 11:45:59.479804 PER_BANK_REFRESH: Hybrid Mode
3768 11:45:59.483143 TX_TRACKING: ON
3769 11:45:59.489750 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3770 11:45:59.496203 [FAST_K] Save calibration result to emmc
3771 11:45:59.499462 dramc_set_vcore_voltage set vcore to 650000
3772 11:45:59.499568 Read voltage for 600, 5
3773 11:45:59.502929 Vio18 = 0
3774 11:45:59.503005 Vcore = 650000
3775 11:45:59.503067 Vdram = 0
3776 11:45:59.506443 Vddq = 0
3777 11:45:59.506532 Vmddr = 0
3778 11:45:59.509786 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3779 11:45:59.516261 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3780 11:45:59.519919 MEM_TYPE=3, freq_sel=19
3781 11:45:59.522776 sv_algorithm_assistance_LP4_1600
3782 11:45:59.526653 ============ PULL DRAM RESETB DOWN ============
3783 11:45:59.529530 ========== PULL DRAM RESETB DOWN end =========
3784 11:45:59.536179 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3785 11:45:59.539597 ===================================
3786 11:45:59.539697 LPDDR4 DRAM CONFIGURATION
3787 11:45:59.542886 ===================================
3788 11:45:59.546088 EX_ROW_EN[0] = 0x0
3789 11:45:59.546189 EX_ROW_EN[1] = 0x0
3790 11:45:59.549465 LP4Y_EN = 0x0
3791 11:45:59.549573 WORK_FSP = 0x0
3792 11:45:59.552994 WL = 0x2
3793 11:45:59.553096 RL = 0x2
3794 11:45:59.556199 BL = 0x2
3795 11:45:59.559586 RPST = 0x0
3796 11:45:59.559687 RD_PRE = 0x0
3797 11:45:59.562597 WR_PRE = 0x1
3798 11:45:59.562696 WR_PST = 0x0
3799 11:45:59.565864 DBI_WR = 0x0
3800 11:45:59.565940 DBI_RD = 0x0
3801 11:45:59.569502 OTF = 0x1
3802 11:45:59.572684 ===================================
3803 11:45:59.575844 ===================================
3804 11:45:59.575943 ANA top config
3805 11:45:59.579576 ===================================
3806 11:45:59.582733 DLL_ASYNC_EN = 0
3807 11:45:59.586012 ALL_SLAVE_EN = 1
3808 11:45:59.586123 NEW_RANK_MODE = 1
3809 11:45:59.589485 DLL_IDLE_MODE = 1
3810 11:45:59.592477 LP45_APHY_COMB_EN = 1
3811 11:45:59.595966 TX_ODT_DIS = 1
3812 11:45:59.596041 NEW_8X_MODE = 1
3813 11:45:59.599304 ===================================
3814 11:45:59.602364 ===================================
3815 11:45:59.606298 data_rate = 1200
3816 11:45:59.609473 CKR = 1
3817 11:45:59.612714 DQ_P2S_RATIO = 8
3818 11:45:59.615949 ===================================
3819 11:45:59.619013 CA_P2S_RATIO = 8
3820 11:45:59.622537 DQ_CA_OPEN = 0
3821 11:45:59.622622 DQ_SEMI_OPEN = 0
3822 11:45:59.626045 CA_SEMI_OPEN = 0
3823 11:45:59.629336 CA_FULL_RATE = 0
3824 11:45:59.632811 DQ_CKDIV4_EN = 1
3825 11:45:59.635941 CA_CKDIV4_EN = 1
3826 11:45:59.639554 CA_PREDIV_EN = 0
3827 11:45:59.639639 PH8_DLY = 0
3828 11:45:59.642780 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3829 11:45:59.645752 DQ_AAMCK_DIV = 4
3830 11:45:59.649493 CA_AAMCK_DIV = 4
3831 11:45:59.653050 CA_ADMCK_DIV = 4
3832 11:45:59.656020 DQ_TRACK_CA_EN = 0
3833 11:45:59.656092 CA_PICK = 600
3834 11:45:59.659197 CA_MCKIO = 600
3835 11:45:59.662980 MCKIO_SEMI = 0
3836 11:45:59.666545 PLL_FREQ = 2288
3837 11:45:59.669337 DQ_UI_PI_RATIO = 32
3838 11:45:59.672576 CA_UI_PI_RATIO = 0
3839 11:45:59.675710 ===================================
3840 11:45:59.679043 ===================================
3841 11:45:59.679143 memory_type:LPDDR4
3842 11:45:59.682600 GP_NUM : 10
3843 11:45:59.685677 SRAM_EN : 1
3844 11:45:59.685787 MD32_EN : 0
3845 11:45:59.688858 ===================================
3846 11:45:59.692635 [ANA_INIT] >>>>>>>>>>>>>>
3847 11:45:59.695806 <<<<<< [CONFIGURE PHASE]: ANA_TX
3848 11:45:59.699036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3849 11:45:59.702499 ===================================
3850 11:45:59.705886 data_rate = 1200,PCW = 0X5800
3851 11:45:59.708857 ===================================
3852 11:45:59.712070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3853 11:45:59.715332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 11:45:59.722319 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3855 11:45:59.725458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3856 11:45:59.732080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3857 11:45:59.735941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3858 11:45:59.736014 [ANA_INIT] flow start
3859 11:45:59.738724 [ANA_INIT] PLL >>>>>>>>
3860 11:45:59.742340 [ANA_INIT] PLL <<<<<<<<
3861 11:45:59.742473 [ANA_INIT] MIDPI >>>>>>>>
3862 11:45:59.745542 [ANA_INIT] MIDPI <<<<<<<<
3863 11:45:59.749040 [ANA_INIT] DLL >>>>>>>>
3864 11:45:59.749126 [ANA_INIT] flow end
3865 11:45:59.751911 ============ LP4 DIFF to SE enter ============
3866 11:45:59.758987 ============ LP4 DIFF to SE exit ============
3867 11:45:59.759084 [ANA_INIT] <<<<<<<<<<<<<
3868 11:45:59.762089 [Flow] Enable top DCM control >>>>>
3869 11:45:59.765306 [Flow] Enable top DCM control <<<<<
3870 11:45:59.768820 Enable DLL master slave shuffle
3871 11:45:59.775344 ==============================================================
3872 11:45:59.778540 Gating Mode config
3873 11:45:59.781849 ==============================================================
3874 11:45:59.785345 Config description:
3875 11:45:59.795345 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3876 11:45:59.801780 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3877 11:45:59.804960 SELPH_MODE 0: By rank 1: By Phase
3878 11:45:59.811858 ==============================================================
3879 11:45:59.815236 GAT_TRACK_EN = 1
3880 11:45:59.818234 RX_GATING_MODE = 2
3881 11:45:59.821763 RX_GATING_TRACK_MODE = 2
3882 11:45:59.821864 SELPH_MODE = 1
3883 11:45:59.824609 PICG_EARLY_EN = 1
3884 11:45:59.828265 VALID_LAT_VALUE = 1
3885 11:45:59.835309 ==============================================================
3886 11:45:59.838392 Enter into Gating configuration >>>>
3887 11:45:59.841697 Exit from Gating configuration <<<<
3888 11:45:59.844702 Enter into DVFS_PRE_config >>>>>
3889 11:45:59.854395 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3890 11:45:59.857913 Exit from DVFS_PRE_config <<<<<
3891 11:45:59.861313 Enter into PICG configuration >>>>
3892 11:45:59.864712 Exit from PICG configuration <<<<
3893 11:45:59.867933 [RX_INPUT] configuration >>>>>
3894 11:45:59.871562 [RX_INPUT] configuration <<<<<
3895 11:45:59.874769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3896 11:45:59.881229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3897 11:45:59.887975 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 11:45:59.894724 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 11:45:59.897845 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 11:45:59.904663 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 11:45:59.908344 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3902 11:45:59.914642 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3903 11:45:59.917900 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3904 11:45:59.921148 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3905 11:45:59.924545 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3906 11:45:59.931030 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3907 11:45:59.934721 ===================================
3908 11:45:59.937927 LPDDR4 DRAM CONFIGURATION
3909 11:45:59.941228 ===================================
3910 11:45:59.941336 EX_ROW_EN[0] = 0x0
3911 11:45:59.944302 EX_ROW_EN[1] = 0x0
3912 11:45:59.944400 LP4Y_EN = 0x0
3913 11:45:59.947866 WORK_FSP = 0x0
3914 11:45:59.947941 WL = 0x2
3915 11:45:59.950932 RL = 0x2
3916 11:45:59.951003 BL = 0x2
3917 11:45:59.954491 RPST = 0x0
3918 11:45:59.954580 RD_PRE = 0x0
3919 11:45:59.957947 WR_PRE = 0x1
3920 11:45:59.958047 WR_PST = 0x0
3921 11:45:59.960955 DBI_WR = 0x0
3922 11:45:59.961058 DBI_RD = 0x0
3923 11:45:59.964581 OTF = 0x1
3924 11:45:59.967620 ===================================
3925 11:45:59.971040 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3926 11:45:59.974311 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3927 11:45:59.980848 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 11:45:59.984177 ===================================
3929 11:45:59.984269 LPDDR4 DRAM CONFIGURATION
3930 11:45:59.987620 ===================================
3931 11:45:59.991030 EX_ROW_EN[0] = 0x10
3932 11:45:59.994198 EX_ROW_EN[1] = 0x0
3933 11:45:59.994321 LP4Y_EN = 0x0
3934 11:45:59.997633 WORK_FSP = 0x0
3935 11:45:59.997779 WL = 0x2
3936 11:46:00.000870 RL = 0x2
3937 11:46:00.001011 BL = 0x2
3938 11:46:00.004136 RPST = 0x0
3939 11:46:00.004286 RD_PRE = 0x0
3940 11:46:00.007561 WR_PRE = 0x1
3941 11:46:00.007845 WR_PST = 0x0
3942 11:46:00.010926 DBI_WR = 0x0
3943 11:46:00.011037 DBI_RD = 0x0
3944 11:46:00.014065 OTF = 0x1
3945 11:46:00.017303 ===================================
3946 11:46:00.024332 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3947 11:46:00.027349 nWR fixed to 30
3948 11:46:00.027463 [ModeRegInit_LP4] CH0 RK0
3949 11:46:00.030987 [ModeRegInit_LP4] CH0 RK1
3950 11:46:00.034043 [ModeRegInit_LP4] CH1 RK0
3951 11:46:00.037483 [ModeRegInit_LP4] CH1 RK1
3952 11:46:00.037558 match AC timing 17
3953 11:46:00.044283 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3954 11:46:00.047486 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3955 11:46:00.050715 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3956 11:46:00.057630 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3957 11:46:00.061026 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3958 11:46:00.061128 ==
3959 11:46:00.064212 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 11:46:00.067620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 11:46:00.067711 ==
3962 11:46:00.074153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 11:46:00.080512 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3964 11:46:00.083948 [CA 0] Center 36 (5~67) winsize 63
3965 11:46:00.087106 [CA 1] Center 36 (6~67) winsize 62
3966 11:46:00.090671 [CA 2] Center 34 (4~65) winsize 62
3967 11:46:00.094016 [CA 3] Center 34 (4~65) winsize 62
3968 11:46:00.097091 [CA 4] Center 33 (3~64) winsize 62
3969 11:46:00.100406 [CA 5] Center 33 (2~64) winsize 63
3970 11:46:00.100505
3971 11:46:00.104291 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3972 11:46:00.104389
3973 11:46:00.107208 [CATrainingPosCal] consider 1 rank data
3974 11:46:00.110241 u2DelayCellTimex100 = 270/100 ps
3975 11:46:00.113932 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3976 11:46:00.116965 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3977 11:46:00.120629 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3978 11:46:00.123525 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3979 11:46:00.127599 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 11:46:00.130282 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3981 11:46:00.130413
3982 11:46:00.137287 CA PerBit enable=1, Macro0, CA PI delay=33
3983 11:46:00.137408
3984 11:46:00.137542 [CBTSetCACLKResult] CA Dly = 33
3985 11:46:00.140651 CS Dly: 5 (0~36)
3986 11:46:00.140767 ==
3987 11:46:00.143570 Dram Type= 6, Freq= 0, CH_0, rank 1
3988 11:46:00.147397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 11:46:00.147500 ==
3990 11:46:00.153856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 11:46:00.160593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3992 11:46:00.163580 [CA 0] Center 36 (6~67) winsize 62
3993 11:46:00.167270 [CA 1] Center 36 (6~67) winsize 62
3994 11:46:00.170279 [CA 2] Center 34 (4~65) winsize 62
3995 11:46:00.173612 [CA 3] Center 34 (3~65) winsize 63
3996 11:46:00.176962 [CA 4] Center 34 (3~65) winsize 63
3997 11:46:00.180613 [CA 5] Center 33 (3~64) winsize 62
3998 11:46:00.180715
3999 11:46:00.184046 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4000 11:46:00.184148
4001 11:46:00.187218 [CATrainingPosCal] consider 2 rank data
4002 11:46:00.190581 u2DelayCellTimex100 = 270/100 ps
4003 11:46:00.193958 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4004 11:46:00.197361 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4005 11:46:00.200734 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 11:46:00.203704 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4007 11:46:00.207113 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 11:46:00.210580 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4009 11:46:00.210665
4010 11:46:00.217136 CA PerBit enable=1, Macro0, CA PI delay=33
4011 11:46:00.217222
4012 11:46:00.217289 [CBTSetCACLKResult] CA Dly = 33
4013 11:46:00.220659 CS Dly: 6 (0~38)
4014 11:46:00.220743
4015 11:46:00.223754 ----->DramcWriteLeveling(PI) begin...
4016 11:46:00.223840 ==
4017 11:46:00.227049 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 11:46:00.230618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 11:46:00.230703 ==
4020 11:46:00.233730 Write leveling (Byte 0): 34 => 34
4021 11:46:00.237467 Write leveling (Byte 1): 31 => 31
4022 11:46:00.240365 DramcWriteLeveling(PI) end<-----
4023 11:46:00.240450
4024 11:46:00.240517 ==
4025 11:46:00.244024 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 11:46:00.247249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 11:46:00.247334 ==
4028 11:46:00.250593 [Gating] SW mode calibration
4029 11:46:00.257402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4030 11:46:00.264184 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4031 11:46:00.267400 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 11:46:00.274260 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 11:46:00.277511 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 11:46:00.280748 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
4035 11:46:00.287026 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4036 11:46:00.290452 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 11:46:00.293687 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 11:46:00.300252 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 11:46:00.303733 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 11:46:00.306822 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 11:46:00.313605 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4042 11:46:00.316967 0 10 12 | B1->B0 | 2828 4141 | 1 1 | (0 0) (0 0)
4043 11:46:00.320297 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4044 11:46:00.327132 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 11:46:00.330185 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 11:46:00.333474 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 11:46:00.337032 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 11:46:00.343714 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 11:46:00.346946 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 11:46:00.350187 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 11:46:00.357176 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4052 11:46:00.360548 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 11:46:00.363619 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 11:46:00.370524 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 11:46:00.373689 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 11:46:00.377088 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 11:46:00.383447 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 11:46:00.386847 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 11:46:00.390319 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 11:46:00.396891 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:46:00.400254 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:46:00.403699 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 11:46:00.409964 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:46:00.413619 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 11:46:00.416783 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 11:46:00.423242 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4067 11:46:00.426735 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4068 11:46:00.430014 Total UI for P1: 0, mck2ui 16
4069 11:46:00.433431 best dqsien dly found for B0: ( 0, 13, 12)
4070 11:46:00.436440 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 11:46:00.439877 Total UI for P1: 0, mck2ui 16
4072 11:46:00.443180 best dqsien dly found for B1: ( 0, 13, 14)
4073 11:46:00.446892 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4074 11:46:00.450021 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4075 11:46:00.450107
4076 11:46:00.453393 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4077 11:46:00.460280 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4078 11:46:00.460365 [Gating] SW calibration Done
4079 11:46:00.460433 ==
4080 11:46:00.463116 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 11:46:00.470112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 11:46:00.470200 ==
4083 11:46:00.470269 RX Vref Scan: 0
4084 11:46:00.470333
4085 11:46:00.473303 RX Vref 0 -> 0, step: 1
4086 11:46:00.473388
4087 11:46:00.477046 RX Delay -230 -> 252, step: 16
4088 11:46:00.480093 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4089 11:46:00.483360 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4090 11:46:00.490223 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4091 11:46:00.493227 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4092 11:46:00.496630 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4093 11:46:00.499700 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4094 11:46:00.503038 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4095 11:46:00.509529 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4096 11:46:00.512939 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4097 11:46:00.516252 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4098 11:46:00.519644 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4099 11:46:00.526255 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4100 11:46:00.530365 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4101 11:46:00.532967 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4102 11:46:00.536578 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4103 11:46:00.543011 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4104 11:46:00.543099 ==
4105 11:46:00.546258 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 11:46:00.549357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 11:46:00.549443 ==
4108 11:46:00.549509 DQS Delay:
4109 11:46:00.552855 DQS0 = 0, DQS1 = 0
4110 11:46:00.552940 DQM Delay:
4111 11:46:00.556439 DQM0 = 50, DQM1 = 40
4112 11:46:00.556543 DQ Delay:
4113 11:46:00.559501 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4114 11:46:00.562857 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4115 11:46:00.566169 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4116 11:46:00.569189 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4117 11:46:00.569262
4118 11:46:00.569354
4119 11:46:00.569416 ==
4120 11:46:00.572507 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 11:46:00.576013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 11:46:00.576095 ==
4123 11:46:00.576160
4124 11:46:00.576222
4125 11:46:00.579640 TX Vref Scan disable
4126 11:46:00.582512 == TX Byte 0 ==
4127 11:46:00.585989 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4128 11:46:00.589602 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4129 11:46:00.592485 == TX Byte 1 ==
4130 11:46:00.595880 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4131 11:46:00.599376 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4132 11:46:00.599454 ==
4133 11:46:00.602864 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 11:46:00.609430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 11:46:00.609511 ==
4136 11:46:00.609581
4137 11:46:00.609643
4138 11:46:00.609703 TX Vref Scan disable
4139 11:46:00.613692 == TX Byte 0 ==
4140 11:46:00.617035 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4141 11:46:00.623450 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4142 11:46:00.623532 == TX Byte 1 ==
4143 11:46:00.627226 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4144 11:46:00.633598 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4145 11:46:00.633678
4146 11:46:00.633743 [DATLAT]
4147 11:46:00.633809 Freq=600, CH0 RK0
4148 11:46:00.633870
4149 11:46:00.636800 DATLAT Default: 0x9
4150 11:46:00.636873 0, 0xFFFF, sum = 0
4151 11:46:00.640423 1, 0xFFFF, sum = 0
4152 11:46:00.640502 2, 0xFFFF, sum = 0
4153 11:46:00.643824 3, 0xFFFF, sum = 0
4154 11:46:00.643902 4, 0xFFFF, sum = 0
4155 11:46:00.646887 5, 0xFFFF, sum = 0
4156 11:46:00.650210 6, 0xFFFF, sum = 0
4157 11:46:00.650303 7, 0xFFFF, sum = 0
4158 11:46:00.650379 8, 0x0, sum = 1
4159 11:46:00.653779 9, 0x0, sum = 2
4160 11:46:00.653892 10, 0x0, sum = 3
4161 11:46:00.657464 11, 0x0, sum = 4
4162 11:46:00.657557 best_step = 9
4163 11:46:00.657630
4164 11:46:00.657693 ==
4165 11:46:00.660458 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 11:46:00.666812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 11:46:00.666915 ==
4168 11:46:00.666984 RX Vref Scan: 1
4169 11:46:00.667054
4170 11:46:00.670425 RX Vref 0 -> 0, step: 1
4171 11:46:00.670506
4172 11:46:00.673470 RX Delay -179 -> 252, step: 8
4173 11:46:00.673565
4174 11:46:00.676683 Set Vref, RX VrefLevel [Byte0]: 57
4175 11:46:00.680244 [Byte1]: 49
4176 11:46:00.680368
4177 11:46:00.683354 Final RX Vref Byte 0 = 57 to rank0
4178 11:46:00.686818 Final RX Vref Byte 1 = 49 to rank0
4179 11:46:00.690056 Final RX Vref Byte 0 = 57 to rank1
4180 11:46:00.693221 Final RX Vref Byte 1 = 49 to rank1==
4181 11:46:00.696838 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 11:46:00.700202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 11:46:00.700286 ==
4184 11:46:00.703084 DQS Delay:
4185 11:46:00.703159 DQS0 = 0, DQS1 = 0
4186 11:46:00.706498 DQM Delay:
4187 11:46:00.706587 DQM0 = 50, DQM1 = 37
4188 11:46:00.706652 DQ Delay:
4189 11:46:00.710000 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =44
4190 11:46:00.713126 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4191 11:46:00.716772 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4192 11:46:00.719837 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4193 11:46:00.719926
4194 11:46:00.719995
4195 11:46:00.730241 [DQSOSCAuto] RK0, (LSB)MR18= 0x5852, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4196 11:46:00.733205 CH0 RK0: MR19=808, MR18=5852
4197 11:46:00.736279 CH0_RK0: MR19=0x808, MR18=0x5852, DQSOSC=393, MR23=63, INC=169, DEC=113
4198 11:46:00.740030
4199 11:46:00.742752 ----->DramcWriteLeveling(PI) begin...
4200 11:46:00.742866 ==
4201 11:46:00.746172 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 11:46:00.749635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 11:46:00.749731 ==
4204 11:46:00.752722 Write leveling (Byte 0): 32 => 32
4205 11:46:00.756185 Write leveling (Byte 1): 31 => 31
4206 11:46:00.759683 DramcWriteLeveling(PI) end<-----
4207 11:46:00.759769
4208 11:46:00.759854 ==
4209 11:46:00.763032 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 11:46:00.766055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 11:46:00.766148 ==
4212 11:46:00.769462 [Gating] SW mode calibration
4213 11:46:00.775866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4214 11:46:00.782574 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4215 11:46:00.786110 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 11:46:00.789562 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 11:46:00.796104 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 11:46:00.799365 0 9 12 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
4219 11:46:00.802670 0 9 16 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
4220 11:46:00.809385 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 11:46:00.812917 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 11:46:00.815854 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 11:46:00.822694 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 11:46:00.826146 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 11:46:00.829338 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 11:46:00.835905 0 10 12 | B1->B0 | 2929 2828 | 0 0 | (0 0) (0 0)
4227 11:46:00.839169 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4228 11:46:00.842846 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 11:46:00.845795 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 11:46:00.852567 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 11:46:00.856124 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 11:46:00.859443 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 11:46:00.865954 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 11:46:00.868979 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4235 11:46:00.872504 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4236 11:46:00.879195 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 11:46:00.882396 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 11:46:00.885880 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:46:00.892547 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:46:00.895946 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:46:00.899192 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:46:00.905845 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:46:00.909115 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:46:00.912320 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:46:00.919253 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:46:00.922765 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:46:00.925887 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:46:00.932792 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:46:00.935905 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:46:00.939074 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:46:00.942513 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:46:00.945823 Total UI for P1: 0, mck2ui 16
4253 11:46:00.949177 best dqsien dly found for B0: ( 0, 13, 14)
4254 11:46:00.952621 Total UI for P1: 0, mck2ui 16
4255 11:46:00.955788 best dqsien dly found for B1: ( 0, 13, 14)
4256 11:46:00.959302 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4257 11:46:00.965693 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4258 11:46:00.965780
4259 11:46:00.969220 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4260 11:46:00.972659 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4261 11:46:00.975846 [Gating] SW calibration Done
4262 11:46:00.975932 ==
4263 11:46:00.979301 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 11:46:00.982505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 11:46:00.982613 ==
4266 11:46:00.985916 RX Vref Scan: 0
4267 11:46:00.985994
4268 11:46:00.986060 RX Vref 0 -> 0, step: 1
4269 11:46:00.986127
4270 11:46:00.989208 RX Delay -230 -> 252, step: 16
4271 11:46:00.992188 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4272 11:46:00.999030 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4273 11:46:01.002781 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4274 11:46:01.006002 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4275 11:46:01.008809 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4276 11:46:01.012360 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4277 11:46:01.018993 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4278 11:46:01.022207 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4279 11:46:01.025640 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4280 11:46:01.029142 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4281 11:46:01.035392 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4282 11:46:01.038853 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4283 11:46:01.042186 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4284 11:46:01.045665 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4285 11:46:01.051818 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4286 11:46:01.055407 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4287 11:46:01.055529 ==
4288 11:46:01.058635 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 11:46:01.061998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 11:46:01.062084 ==
4291 11:46:01.065322 DQS Delay:
4292 11:46:01.065401 DQS0 = 0, DQS1 = 0
4293 11:46:01.065470 DQM Delay:
4294 11:46:01.068864 DQM0 = 51, DQM1 = 41
4295 11:46:01.068944 DQ Delay:
4296 11:46:01.071987 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4297 11:46:01.075258 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4298 11:46:01.078599 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4299 11:46:01.082059 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4300 11:46:01.082137
4301 11:46:01.082200
4302 11:46:01.082264 ==
4303 11:46:01.085595 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 11:46:01.088605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 11:46:01.091861 ==
4306 11:46:01.091939
4307 11:46:01.092004
4308 11:46:01.092069 TX Vref Scan disable
4309 11:46:01.095367 == TX Byte 0 ==
4310 11:46:01.098454 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4311 11:46:01.102026 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4312 11:46:01.105195 == TX Byte 1 ==
4313 11:46:01.108702 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4314 11:46:01.112189 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4315 11:46:01.115577 ==
4316 11:46:01.119058 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 11:46:01.121914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 11:46:01.121989 ==
4319 11:46:01.122052
4320 11:46:01.122113
4321 11:46:01.125165 TX Vref Scan disable
4322 11:46:01.125244 == TX Byte 0 ==
4323 11:46:01.132146 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4324 11:46:01.135288 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4325 11:46:01.135385 == TX Byte 1 ==
4326 11:46:01.142313 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4327 11:46:01.145083 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4328 11:46:01.145169
4329 11:46:01.145242 [DATLAT]
4330 11:46:01.149015 Freq=600, CH0 RK1
4331 11:46:01.149116
4332 11:46:01.149210 DATLAT Default: 0x9
4333 11:46:01.151856 0, 0xFFFF, sum = 0
4334 11:46:01.151938 1, 0xFFFF, sum = 0
4335 11:46:01.155343 2, 0xFFFF, sum = 0
4336 11:46:01.155434 3, 0xFFFF, sum = 0
4337 11:46:01.158683 4, 0xFFFF, sum = 0
4338 11:46:01.158763 5, 0xFFFF, sum = 0
4339 11:46:01.161872 6, 0xFFFF, sum = 0
4340 11:46:01.165153 7, 0xFFFF, sum = 0
4341 11:46:01.165231 8, 0x0, sum = 1
4342 11:46:01.165297 9, 0x0, sum = 2
4343 11:46:01.168499 10, 0x0, sum = 3
4344 11:46:01.168580 11, 0x0, sum = 4
4345 11:46:01.171671 best_step = 9
4346 11:46:01.171755
4347 11:46:01.171825 ==
4348 11:46:01.174922 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 11:46:01.178562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 11:46:01.178648 ==
4351 11:46:01.181902 RX Vref Scan: 0
4352 11:46:01.182006
4353 11:46:01.182075 RX Vref 0 -> 0, step: 1
4354 11:46:01.182147
4355 11:46:01.185093 RX Delay -179 -> 252, step: 8
4356 11:46:01.192496 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4357 11:46:01.195823 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4358 11:46:01.199126 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4359 11:46:01.202103 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4360 11:46:01.205449 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4361 11:46:01.211928 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4362 11:46:01.215554 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4363 11:46:01.219046 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4364 11:46:01.222546 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4365 11:46:01.225672 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4366 11:46:01.232162 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4367 11:46:01.235745 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4368 11:46:01.238899 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4369 11:46:01.242099 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4370 11:46:01.248802 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4371 11:46:01.252290 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4372 11:46:01.252401 ==
4373 11:46:01.255555 Dram Type= 6, Freq= 0, CH_0, rank 1
4374 11:46:01.259014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 11:46:01.259103 ==
4376 11:46:01.262684 DQS Delay:
4377 11:46:01.262768 DQS0 = 0, DQS1 = 0
4378 11:46:01.262865 DQM Delay:
4379 11:46:01.265503 DQM0 = 48, DQM1 = 40
4380 11:46:01.265616 DQ Delay:
4381 11:46:01.268592 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4382 11:46:01.272067 DQ4 =52, DQ5 =40, DQ6 =56, DQ7 =52
4383 11:46:01.275694 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4384 11:46:01.278717 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =48
4385 11:46:01.278826
4386 11:46:01.278924
4387 11:46:01.288528 [DQSOSCAuto] RK1, (LSB)MR18= 0x6734, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4388 11:46:01.288651 CH0 RK1: MR19=808, MR18=6734
4389 11:46:01.295236 CH0_RK1: MR19=0x808, MR18=0x6734, DQSOSC=390, MR23=63, INC=172, DEC=114
4390 11:46:01.298719 [RxdqsGatingPostProcess] freq 600
4391 11:46:01.304892 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4392 11:46:01.308756 Pre-setting of DQS Precalculation
4393 11:46:01.311869 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4394 11:46:01.311951 ==
4395 11:46:01.315270 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 11:46:01.321962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 11:46:01.322067 ==
4398 11:46:01.325251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 11:46:01.331858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4400 11:46:01.334960 [CA 0] Center 35 (5~65) winsize 61
4401 11:46:01.338590 [CA 1] Center 35 (5~66) winsize 62
4402 11:46:01.341480 [CA 2] Center 34 (4~65) winsize 62
4403 11:46:01.345296 [CA 3] Center 34 (3~65) winsize 63
4404 11:46:01.348350 [CA 4] Center 34 (3~65) winsize 63
4405 11:46:01.351526 [CA 5] Center 33 (3~64) winsize 62
4406 11:46:01.351612
4407 11:46:01.355114 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4408 11:46:01.355188
4409 11:46:01.358083 [CATrainingPosCal] consider 1 rank data
4410 11:46:01.361510 u2DelayCellTimex100 = 270/100 ps
4411 11:46:01.364775 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4412 11:46:01.371297 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4413 11:46:01.374705 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 11:46:01.378322 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4415 11:46:01.381241 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4416 11:46:01.384725 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 11:46:01.384825
4418 11:46:01.387954 CA PerBit enable=1, Macro0, CA PI delay=33
4419 11:46:01.388064
4420 11:46:01.391327 [CBTSetCACLKResult] CA Dly = 33
4421 11:46:01.391400 CS Dly: 5 (0~36)
4422 11:46:01.394735 ==
4423 11:46:01.398128 Dram Type= 6, Freq= 0, CH_1, rank 1
4424 11:46:01.401331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 11:46:01.401441 ==
4426 11:46:01.404769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4427 11:46:01.411090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4428 11:46:01.415298 [CA 0] Center 35 (5~66) winsize 62
4429 11:46:01.418573 [CA 1] Center 35 (5~66) winsize 62
4430 11:46:01.421851 [CA 2] Center 34 (4~65) winsize 62
4431 11:46:01.424880 [CA 3] Center 34 (4~65) winsize 62
4432 11:46:01.428255 [CA 4] Center 34 (4~64) winsize 61
4433 11:46:01.431682 [CA 5] Center 33 (3~64) winsize 62
4434 11:46:01.431790
4435 11:46:01.434854 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4436 11:46:01.434930
4437 11:46:01.438628 [CATrainingPosCal] consider 2 rank data
4438 11:46:01.441469 u2DelayCellTimex100 = 270/100 ps
4439 11:46:01.445202 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4440 11:46:01.451600 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4441 11:46:01.455129 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 11:46:01.458027 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 11:46:01.461254 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4444 11:46:01.465137 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 11:46:01.465222
4446 11:46:01.468263 CA PerBit enable=1, Macro0, CA PI delay=33
4447 11:46:01.468347
4448 11:46:01.471807 [CBTSetCACLKResult] CA Dly = 33
4449 11:46:01.471890 CS Dly: 5 (0~37)
4450 11:46:01.471956
4451 11:46:01.474833 ----->DramcWriteLeveling(PI) begin...
4452 11:46:01.478402 ==
4453 11:46:01.481287 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 11:46:01.484881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 11:46:01.484976 ==
4456 11:46:01.488057 Write leveling (Byte 0): 31 => 31
4457 11:46:01.491310 Write leveling (Byte 1): 31 => 31
4458 11:46:01.494526 DramcWriteLeveling(PI) end<-----
4459 11:46:01.494632
4460 11:46:01.494725 ==
4461 11:46:01.498111 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 11:46:01.501074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 11:46:01.501188 ==
4464 11:46:01.504686 [Gating] SW mode calibration
4465 11:46:01.511442 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4466 11:46:01.518041 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4467 11:46:01.521451 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 11:46:01.524558 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 11:46:01.531310 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4470 11:46:01.534695 0 9 12 | B1->B0 | 2d2d 2e2e | 0 1 | (0 1) (1 0)
4471 11:46:01.537982 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 11:46:01.544363 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 11:46:01.547744 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 11:46:01.551251 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 11:46:01.554690 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 11:46:01.561163 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 11:46:01.564237 0 10 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4478 11:46:01.568280 0 10 12 | B1->B0 | 4040 4141 | 1 1 | (0 0) (0 0)
4479 11:46:01.574132 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 11:46:01.577976 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 11:46:01.580831 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 11:46:01.587553 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 11:46:01.591046 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 11:46:01.594225 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 11:46:01.601247 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4486 11:46:01.604212 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4487 11:46:01.607354 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 11:46:01.614168 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 11:46:01.617816 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 11:46:01.621048 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 11:46:01.627605 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 11:46:01.630539 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 11:46:01.634028 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 11:46:01.640905 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 11:46:01.643911 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 11:46:01.647300 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 11:46:01.653843 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 11:46:01.657989 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:46:01.660681 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 11:46:01.667185 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 11:46:01.670599 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4502 11:46:01.674175 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4503 11:46:01.677389 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:46:01.680555 Total UI for P1: 0, mck2ui 16
4505 11:46:01.684312 best dqsien dly found for B0: ( 0, 13, 10)
4506 11:46:01.687615 Total UI for P1: 0, mck2ui 16
4507 11:46:01.690737 best dqsien dly found for B1: ( 0, 13, 12)
4508 11:46:01.694017 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4509 11:46:01.700787 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4510 11:46:01.700874
4511 11:46:01.704104 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4512 11:46:01.707709 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4513 11:46:01.710547 [Gating] SW calibration Done
4514 11:46:01.710629 ==
4515 11:46:01.713948 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 11:46:01.717615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 11:46:01.717705 ==
4518 11:46:01.720855 RX Vref Scan: 0
4519 11:46:01.720959
4520 11:46:01.721057 RX Vref 0 -> 0, step: 1
4521 11:46:01.721150
4522 11:46:01.724030 RX Delay -230 -> 252, step: 16
4523 11:46:01.727321 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4524 11:46:01.733695 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4525 11:46:01.737084 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4526 11:46:01.740328 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4527 11:46:01.743697 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4528 11:46:01.747147 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4529 11:46:01.753719 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4530 11:46:01.756904 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4531 11:46:01.760367 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4532 11:46:01.763775 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4533 11:46:01.770176 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4534 11:46:01.773875 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4535 11:46:01.777190 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4536 11:46:01.780265 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4537 11:46:01.783757 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4538 11:46:01.790241 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4539 11:46:01.790355 ==
4540 11:46:01.793982 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 11:46:01.797194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 11:46:01.797300 ==
4543 11:46:01.797396 DQS Delay:
4544 11:46:01.800678 DQS0 = 0, DQS1 = 0
4545 11:46:01.800778 DQM Delay:
4546 11:46:01.803863 DQM0 = 52, DQM1 = 45
4547 11:46:01.803965 DQ Delay:
4548 11:46:01.807071 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4549 11:46:01.810403 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4550 11:46:01.813562 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4551 11:46:01.817141 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4552 11:46:01.817248
4553 11:46:01.817342
4554 11:46:01.817433 ==
4555 11:46:01.820363 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 11:46:01.823526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 11:46:01.826888 ==
4558 11:46:01.826994
4559 11:46:01.827088
4560 11:46:01.827180 TX Vref Scan disable
4561 11:46:01.830877 == TX Byte 0 ==
4562 11:46:01.833606 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4563 11:46:01.836933 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4564 11:46:01.840383 == TX Byte 1 ==
4565 11:46:01.843369 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4566 11:46:01.846826 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4567 11:46:01.850087 ==
4568 11:46:01.853564 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 11:46:01.856881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 11:46:01.856996 ==
4571 11:46:01.857094
4572 11:46:01.857199
4573 11:46:01.860216 TX Vref Scan disable
4574 11:46:01.860323 == TX Byte 0 ==
4575 11:46:01.866486 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4576 11:46:01.869996 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4577 11:46:01.870108 == TX Byte 1 ==
4578 11:46:01.876719 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4579 11:46:01.880179 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4580 11:46:01.880282
4581 11:46:01.880378 [DATLAT]
4582 11:46:01.883297 Freq=600, CH1 RK0
4583 11:46:01.883406
4584 11:46:01.883517 DATLAT Default: 0x9
4585 11:46:01.886636 0, 0xFFFF, sum = 0
4586 11:46:01.886717 1, 0xFFFF, sum = 0
4587 11:46:01.890059 2, 0xFFFF, sum = 0
4588 11:46:01.890175 3, 0xFFFF, sum = 0
4589 11:46:01.893482 4, 0xFFFF, sum = 0
4590 11:46:01.893568 5, 0xFFFF, sum = 0
4591 11:46:01.896656 6, 0xFFFF, sum = 0
4592 11:46:01.899931 7, 0xFFFF, sum = 0
4593 11:46:01.900012 8, 0x0, sum = 1
4594 11:46:01.900092 9, 0x0, sum = 2
4595 11:46:01.903239 10, 0x0, sum = 3
4596 11:46:01.903356 11, 0x0, sum = 4
4597 11:46:01.906526 best_step = 9
4598 11:46:01.906640
4599 11:46:01.906736 ==
4600 11:46:01.909783 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 11:46:01.913359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 11:46:01.913463 ==
4603 11:46:01.916584 RX Vref Scan: 1
4604 11:46:01.916658
4605 11:46:01.916721 RX Vref 0 -> 0, step: 1
4606 11:46:01.916784
4607 11:46:01.919865 RX Delay -163 -> 252, step: 8
4608 11:46:01.919940
4609 11:46:01.923217 Set Vref, RX VrefLevel [Byte0]: 50
4610 11:46:01.926530 [Byte1]: 52
4611 11:46:01.930396
4612 11:46:01.930475 Final RX Vref Byte 0 = 50 to rank0
4613 11:46:01.933731 Final RX Vref Byte 1 = 52 to rank0
4614 11:46:01.936984 Final RX Vref Byte 0 = 50 to rank1
4615 11:46:01.940540 Final RX Vref Byte 1 = 52 to rank1==
4616 11:46:01.943782 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 11:46:01.950252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 11:46:01.950362 ==
4619 11:46:01.950475 DQS Delay:
4620 11:46:01.950570 DQS0 = 0, DQS1 = 0
4621 11:46:01.953415 DQM Delay:
4622 11:46:01.953522 DQM0 = 49, DQM1 = 41
4623 11:46:01.956835 DQ Delay:
4624 11:46:01.960369 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4625 11:46:01.963662 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4626 11:46:01.963750 DQ8 =32, DQ9 =28, DQ10 =44, DQ11 =32
4627 11:46:01.970176 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4628 11:46:01.970263
4629 11:46:01.970332
4630 11:46:01.976816 [DQSOSCAuto] RK0, (LSB)MR18= 0x486f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4631 11:46:01.980492 CH1 RK0: MR19=808, MR18=486F
4632 11:46:01.986933 CH1_RK0: MR19=0x808, MR18=0x486F, DQSOSC=389, MR23=63, INC=173, DEC=115
4633 11:46:01.987021
4634 11:46:01.990450 ----->DramcWriteLeveling(PI) begin...
4635 11:46:01.990540 ==
4636 11:46:01.993520 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 11:46:01.996784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 11:46:01.996862 ==
4639 11:46:02.000128 Write leveling (Byte 0): 29 => 29
4640 11:46:02.003645 Write leveling (Byte 1): 30 => 30
4641 11:46:02.006483 DramcWriteLeveling(PI) end<-----
4642 11:46:02.006600
4643 11:46:02.006702 ==
4644 11:46:02.009991 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 11:46:02.013264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 11:46:02.013343 ==
4647 11:46:02.016957 [Gating] SW mode calibration
4648 11:46:02.023355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4649 11:46:02.029719 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4650 11:46:02.033616 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 11:46:02.039861 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 11:46:02.043736 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4653 11:46:02.046416 0 9 12 | B1->B0 | 2e2e 3131 | 0 0 | (0 1) (0 1)
4654 11:46:02.049782 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 11:46:02.056850 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 11:46:02.059704 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 11:46:02.062901 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 11:46:02.069833 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 11:46:02.072868 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 11:46:02.076670 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 11:46:02.083338 0 10 12 | B1->B0 | 3939 2f2f | 0 0 | (0 0) (0 0)
4662 11:46:02.086224 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 11:46:02.089485 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 11:46:02.096568 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 11:46:02.099545 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 11:46:02.102790 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 11:46:02.109707 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 11:46:02.112897 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 11:46:02.116022 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4670 11:46:02.122870 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 11:46:02.126014 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 11:46:02.129525 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 11:46:02.136450 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 11:46:02.139522 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 11:46:02.142840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 11:46:02.149618 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 11:46:02.153067 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 11:46:02.156291 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 11:46:02.162802 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 11:46:02.165973 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 11:46:02.169671 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 11:46:02.175836 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 11:46:02.179294 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 11:46:02.182711 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4685 11:46:02.189392 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4686 11:46:02.189480 Total UI for P1: 0, mck2ui 16
4687 11:46:02.195763 best dqsien dly found for B0: ( 0, 13, 8)
4688 11:46:02.198917 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 11:46:02.202406 Total UI for P1: 0, mck2ui 16
4690 11:46:02.205626 best dqsien dly found for B1: ( 0, 13, 12)
4691 11:46:02.209185 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4692 11:46:02.212567 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4693 11:46:02.212654
4694 11:46:02.215872 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4695 11:46:02.219213 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4696 11:46:02.222623 [Gating] SW calibration Done
4697 11:46:02.222712 ==
4698 11:46:02.225837 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 11:46:02.228953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 11:46:02.229040 ==
4701 11:46:02.232407 RX Vref Scan: 0
4702 11:46:02.232520
4703 11:46:02.235754 RX Vref 0 -> 0, step: 1
4704 11:46:02.235840
4705 11:46:02.235942 RX Delay -230 -> 252, step: 16
4706 11:46:02.242616 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4707 11:46:02.245916 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4708 11:46:02.249172 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4709 11:46:02.252677 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4710 11:46:02.258977 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4711 11:46:02.262409 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4712 11:46:02.265584 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4713 11:46:02.269114 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4714 11:46:02.272344 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4715 11:46:02.279123 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4716 11:46:02.282504 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4717 11:46:02.285614 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4718 11:46:02.289229 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4719 11:46:02.295903 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4720 11:46:02.299317 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4721 11:46:02.302509 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4722 11:46:02.302609 ==
4723 11:46:02.306059 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 11:46:02.308943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 11:46:02.309036 ==
4726 11:46:02.312253 DQS Delay:
4727 11:46:02.312360 DQS0 = 0, DQS1 = 0
4728 11:46:02.316030 DQM Delay:
4729 11:46:02.316121 DQM0 = 52, DQM1 = 46
4730 11:46:02.316184 DQ Delay:
4731 11:46:02.319104 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4732 11:46:02.322344 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4733 11:46:02.326238 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4734 11:46:02.329256 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4735 11:46:02.329360
4736 11:46:02.329454
4737 11:46:02.332069 ==
4738 11:46:02.332164 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 11:46:02.339096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 11:46:02.339206 ==
4741 11:46:02.339274
4742 11:46:02.339335
4743 11:46:02.342344 TX Vref Scan disable
4744 11:46:02.342490 == TX Byte 0 ==
4745 11:46:02.345526 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4746 11:46:02.352084 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4747 11:46:02.352164 == TX Byte 1 ==
4748 11:46:02.355367 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4749 11:46:02.362090 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4750 11:46:02.362202 ==
4751 11:46:02.365000 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 11:46:02.368525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 11:46:02.368602 ==
4754 11:46:02.368709
4755 11:46:02.368783
4756 11:46:02.371806 TX Vref Scan disable
4757 11:46:02.375163 == TX Byte 0 ==
4758 11:46:02.378180 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4759 11:46:02.381803 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4760 11:46:02.385625 == TX Byte 1 ==
4761 11:46:02.388433 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4762 11:46:02.391554 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4763 11:46:02.391677
4764 11:46:02.394704 [DATLAT]
4765 11:46:02.394817 Freq=600, CH1 RK1
4766 11:46:02.394927
4767 11:46:02.398174 DATLAT Default: 0x9
4768 11:46:02.398279 0, 0xFFFF, sum = 0
4769 11:46:02.401787 1, 0xFFFF, sum = 0
4770 11:46:02.401868 2, 0xFFFF, sum = 0
4771 11:46:02.404979 3, 0xFFFF, sum = 0
4772 11:46:02.405085 4, 0xFFFF, sum = 0
4773 11:46:02.408043 5, 0xFFFF, sum = 0
4774 11:46:02.408151 6, 0xFFFF, sum = 0
4775 11:46:02.411736 7, 0xFFFF, sum = 0
4776 11:46:02.411842 8, 0x0, sum = 1
4777 11:46:02.415013 9, 0x0, sum = 2
4778 11:46:02.415117 10, 0x0, sum = 3
4779 11:46:02.418154 11, 0x0, sum = 4
4780 11:46:02.418273 best_step = 9
4781 11:46:02.418371
4782 11:46:02.418503 ==
4783 11:46:02.421722 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 11:46:02.424875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 11:46:02.428369 ==
4786 11:46:02.428468 RX Vref Scan: 0
4787 11:46:02.428535
4788 11:46:02.431518 RX Vref 0 -> 0, step: 1
4789 11:46:02.431596
4790 11:46:02.434649 RX Delay -163 -> 252, step: 8
4791 11:46:02.438227 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4792 11:46:02.441343 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4793 11:46:02.448313 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4794 11:46:02.451584 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4795 11:46:02.454600 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4796 11:46:02.458229 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4797 11:46:02.461642 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4798 11:46:02.467837 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4799 11:46:02.471251 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4800 11:46:02.474806 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4801 11:46:02.478116 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4802 11:46:02.481401 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4803 11:46:02.488123 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4804 11:46:02.491325 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4805 11:46:02.494912 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4806 11:46:02.498073 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4807 11:46:02.498150 ==
4808 11:46:02.501503 Dram Type= 6, Freq= 0, CH_1, rank 1
4809 11:46:02.508189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4810 11:46:02.508267 ==
4811 11:46:02.508334 DQS Delay:
4812 11:46:02.511283 DQS0 = 0, DQS1 = 0
4813 11:46:02.511371 DQM Delay:
4814 11:46:02.511441 DQM0 = 49, DQM1 = 45
4815 11:46:02.514565 DQ Delay:
4816 11:46:02.517912 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4817 11:46:02.521163 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4818 11:46:02.524475 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4819 11:46:02.527723 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4820 11:46:02.527795
4821 11:46:02.527861
4822 11:46:02.535271 [DQSOSCAuto] RK1, (LSB)MR18= 0x561d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4823 11:46:02.538051 CH1 RK1: MR19=808, MR18=561D
4824 11:46:02.544523 CH1_RK1: MR19=0x808, MR18=0x561D, DQSOSC=393, MR23=63, INC=169, DEC=113
4825 11:46:02.548333 [RxdqsGatingPostProcess] freq 600
4826 11:46:02.551363 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4827 11:46:02.554776 Pre-setting of DQS Precalculation
4828 11:46:02.561184 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4829 11:46:02.568101 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4830 11:46:02.575057 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4831 11:46:02.575143
4832 11:46:02.575229
4833 11:46:02.578208 [Calibration Summary] 1200 Mbps
4834 11:46:02.578311 CH 0, Rank 0
4835 11:46:02.581102 SW Impedance : PASS
4836 11:46:02.584320 DUTY Scan : NO K
4837 11:46:02.584409 ZQ Calibration : PASS
4838 11:46:02.587728 Jitter Meter : NO K
4839 11:46:02.590999 CBT Training : PASS
4840 11:46:02.591115 Write leveling : PASS
4841 11:46:02.594509 RX DQS gating : PASS
4842 11:46:02.597785 RX DQ/DQS(RDDQC) : PASS
4843 11:46:02.597873 TX DQ/DQS : PASS
4844 11:46:02.600966 RX DATLAT : PASS
4845 11:46:02.601054 RX DQ/DQS(Engine): PASS
4846 11:46:02.604691 TX OE : NO K
4847 11:46:02.604855 All Pass.
4848 11:46:02.604942
4849 11:46:02.607773 CH 0, Rank 1
4850 11:46:02.607861 SW Impedance : PASS
4851 11:46:02.611139 DUTY Scan : NO K
4852 11:46:02.614402 ZQ Calibration : PASS
4853 11:46:02.614491 Jitter Meter : NO K
4854 11:46:02.617687 CBT Training : PASS
4855 11:46:02.620872 Write leveling : PASS
4856 11:46:02.620962 RX DQS gating : PASS
4857 11:46:02.624544 RX DQ/DQS(RDDQC) : PASS
4858 11:46:02.627785 TX DQ/DQS : PASS
4859 11:46:02.627873 RX DATLAT : PASS
4860 11:46:02.630952 RX DQ/DQS(Engine): PASS
4861 11:46:02.634076 TX OE : NO K
4862 11:46:02.634181 All Pass.
4863 11:46:02.634288
4864 11:46:02.634397 CH 1, Rank 0
4865 11:46:02.637804 SW Impedance : PASS
4866 11:46:02.641068 DUTY Scan : NO K
4867 11:46:02.641155 ZQ Calibration : PASS
4868 11:46:02.644489 Jitter Meter : NO K
4869 11:46:02.648000 CBT Training : PASS
4870 11:46:02.648131 Write leveling : PASS
4871 11:46:02.650708 RX DQS gating : PASS
4872 11:46:02.654483 RX DQ/DQS(RDDQC) : PASS
4873 11:46:02.654580 TX DQ/DQS : PASS
4874 11:46:02.657565 RX DATLAT : PASS
4875 11:46:02.657652 RX DQ/DQS(Engine): PASS
4876 11:46:02.661109 TX OE : NO K
4877 11:46:02.661227 All Pass.
4878 11:46:02.661334
4879 11:46:02.664408 CH 1, Rank 1
4880 11:46:02.664527 SW Impedance : PASS
4881 11:46:02.667325 DUTY Scan : NO K
4882 11:46:02.670884 ZQ Calibration : PASS
4883 11:46:02.670996 Jitter Meter : NO K
4884 11:46:02.673829 CBT Training : PASS
4885 11:46:02.677550 Write leveling : PASS
4886 11:46:02.677633 RX DQS gating : PASS
4887 11:46:02.680712 RX DQ/DQS(RDDQC) : PASS
4888 11:46:02.684155 TX DQ/DQS : PASS
4889 11:46:02.684272 RX DATLAT : PASS
4890 11:46:02.687528 RX DQ/DQS(Engine): PASS
4891 11:46:02.690954 TX OE : NO K
4892 11:46:02.691063 All Pass.
4893 11:46:02.691159
4894 11:46:02.694023 DramC Write-DBI off
4895 11:46:02.694131 PER_BANK_REFRESH: Hybrid Mode
4896 11:46:02.697517 TX_TRACKING: ON
4897 11:46:02.703775 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4898 11:46:02.707233 [FAST_K] Save calibration result to emmc
4899 11:46:02.713788 dramc_set_vcore_voltage set vcore to 662500
4900 11:46:02.713900 Read voltage for 933, 3
4901 11:46:02.717004 Vio18 = 0
4902 11:46:02.717114 Vcore = 662500
4903 11:46:02.717214 Vdram = 0
4904 11:46:02.720595 Vddq = 0
4905 11:46:02.720671 Vmddr = 0
4906 11:46:02.723887 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4907 11:46:02.730518 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4908 11:46:02.733871 MEM_TYPE=3, freq_sel=17
4909 11:46:02.737287 sv_algorithm_assistance_LP4_1600
4910 11:46:02.740757 ============ PULL DRAM RESETB DOWN ============
4911 11:46:02.744138 ========== PULL DRAM RESETB DOWN end =========
4912 11:46:02.747308 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4913 11:46:02.750406 ===================================
4914 11:46:02.753756 LPDDR4 DRAM CONFIGURATION
4915 11:46:02.757152 ===================================
4916 11:46:02.760627 EX_ROW_EN[0] = 0x0
4917 11:46:02.760708 EX_ROW_EN[1] = 0x0
4918 11:46:02.763610 LP4Y_EN = 0x0
4919 11:46:02.763681 WORK_FSP = 0x0
4920 11:46:02.766944 WL = 0x3
4921 11:46:02.767014 RL = 0x3
4922 11:46:02.770414 BL = 0x2
4923 11:46:02.770485 RPST = 0x0
4924 11:46:02.773687 RD_PRE = 0x0
4925 11:46:02.773763 WR_PRE = 0x1
4926 11:46:02.777229 WR_PST = 0x0
4927 11:46:02.777299 DBI_WR = 0x0
4928 11:46:02.780384 DBI_RD = 0x0
4929 11:46:02.780452 OTF = 0x1
4930 11:46:02.783658 ===================================
4931 11:46:02.787206 ===================================
4932 11:46:02.790559 ANA top config
4933 11:46:02.794049 ===================================
4934 11:46:02.797371 DLL_ASYNC_EN = 0
4935 11:46:02.797447 ALL_SLAVE_EN = 1
4936 11:46:02.800429 NEW_RANK_MODE = 1
4937 11:46:02.803745 DLL_IDLE_MODE = 1
4938 11:46:02.806994 LP45_APHY_COMB_EN = 1
4939 11:46:02.810147 TX_ODT_DIS = 1
4940 11:46:02.810216 NEW_8X_MODE = 1
4941 11:46:02.813673 ===================================
4942 11:46:02.816967 ===================================
4943 11:46:02.820218 data_rate = 1866
4944 11:46:02.823728 CKR = 1
4945 11:46:02.826743 DQ_P2S_RATIO = 8
4946 11:46:02.830255 ===================================
4947 11:46:02.833627 CA_P2S_RATIO = 8
4948 11:46:02.836635 DQ_CA_OPEN = 0
4949 11:46:02.836722 DQ_SEMI_OPEN = 0
4950 11:46:02.840310 CA_SEMI_OPEN = 0
4951 11:46:02.843766 CA_FULL_RATE = 0
4952 11:46:02.846615 DQ_CKDIV4_EN = 1
4953 11:46:02.850355 CA_CKDIV4_EN = 1
4954 11:46:02.850454 CA_PREDIV_EN = 0
4955 11:46:02.853292 PH8_DLY = 0
4956 11:46:02.856778 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4957 11:46:02.860566 DQ_AAMCK_DIV = 4
4958 11:46:02.863430 CA_AAMCK_DIV = 4
4959 11:46:02.866843 CA_ADMCK_DIV = 4
4960 11:46:02.866929 DQ_TRACK_CA_EN = 0
4961 11:46:02.870210 CA_PICK = 933
4962 11:46:02.873740 CA_MCKIO = 933
4963 11:46:02.876865 MCKIO_SEMI = 0
4964 11:46:02.879962 PLL_FREQ = 3732
4965 11:46:02.883838 DQ_UI_PI_RATIO = 32
4966 11:46:02.886996 CA_UI_PI_RATIO = 0
4967 11:46:02.890380 ===================================
4968 11:46:02.893903 ===================================
4969 11:46:02.894004 memory_type:LPDDR4
4970 11:46:02.896811 GP_NUM : 10
4971 11:46:02.900227 SRAM_EN : 1
4972 11:46:02.900311 MD32_EN : 0
4973 11:46:02.903549 ===================================
4974 11:46:02.906666 [ANA_INIT] >>>>>>>>>>>>>>
4975 11:46:02.910495 <<<<<< [CONFIGURE PHASE]: ANA_TX
4976 11:46:02.913661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4977 11:46:02.916844 ===================================
4978 11:46:02.920105 data_rate = 1866,PCW = 0X8f00
4979 11:46:02.923506 ===================================
4980 11:46:02.926692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4981 11:46:02.930104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 11:46:02.936708 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 11:46:02.940081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4984 11:46:02.943216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4985 11:46:02.946538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4986 11:46:02.950424 [ANA_INIT] flow start
4987 11:46:02.953507 [ANA_INIT] PLL >>>>>>>>
4988 11:46:02.953592 [ANA_INIT] PLL <<<<<<<<
4989 11:46:02.956645 [ANA_INIT] MIDPI >>>>>>>>
4990 11:46:02.959756 [ANA_INIT] MIDPI <<<<<<<<
4991 11:46:02.959841 [ANA_INIT] DLL >>>>>>>>
4992 11:46:02.963096 [ANA_INIT] flow end
4993 11:46:02.966650 ============ LP4 DIFF to SE enter ============
4994 11:46:02.973566 ============ LP4 DIFF to SE exit ============
4995 11:46:02.973666 [ANA_INIT] <<<<<<<<<<<<<
4996 11:46:02.976353 [Flow] Enable top DCM control >>>>>
4997 11:46:02.979895 [Flow] Enable top DCM control <<<<<
4998 11:46:02.983020 Enable DLL master slave shuffle
4999 11:46:02.989917 ==============================================================
5000 11:46:02.990010 Gating Mode config
5001 11:46:02.996300 ==============================================================
5002 11:46:02.999643 Config description:
5003 11:46:03.006222 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5004 11:46:03.013032 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5005 11:46:03.019501 SELPH_MODE 0: By rank 1: By Phase
5006 11:46:03.026136 ==============================================================
5007 11:46:03.026221 GAT_TRACK_EN = 1
5008 11:46:03.029629 RX_GATING_MODE = 2
5009 11:46:03.032972 RX_GATING_TRACK_MODE = 2
5010 11:46:03.036153 SELPH_MODE = 1
5011 11:46:03.039384 PICG_EARLY_EN = 1
5012 11:46:03.042704 VALID_LAT_VALUE = 1
5013 11:46:03.049584 ==============================================================
5014 11:46:03.052822 Enter into Gating configuration >>>>
5015 11:46:03.056070 Exit from Gating configuration <<<<
5016 11:46:03.059307 Enter into DVFS_PRE_config >>>>>
5017 11:46:03.069269 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5018 11:46:03.072482 Exit from DVFS_PRE_config <<<<<
5019 11:46:03.075793 Enter into PICG configuration >>>>
5020 11:46:03.079320 Exit from PICG configuration <<<<
5021 11:46:03.082699 [RX_INPUT] configuration >>>>>
5022 11:46:03.082805 [RX_INPUT] configuration <<<<<
5023 11:46:03.089366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5024 11:46:03.096187 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5025 11:46:03.102324 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5026 11:46:03.105771 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5027 11:46:03.112305 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 11:46:03.119222 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 11:46:03.122469 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5030 11:46:03.125830 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5031 11:46:03.132049 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5032 11:46:03.135619 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5033 11:46:03.138829 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5034 11:46:03.145666 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5035 11:46:03.148822 ===================================
5036 11:46:03.148971 LPDDR4 DRAM CONFIGURATION
5037 11:46:03.152474 ===================================
5038 11:46:03.155253 EX_ROW_EN[0] = 0x0
5039 11:46:03.158804 EX_ROW_EN[1] = 0x0
5040 11:46:03.158932 LP4Y_EN = 0x0
5041 11:46:03.162128 WORK_FSP = 0x0
5042 11:46:03.162225 WL = 0x3
5043 11:46:03.165873 RL = 0x3
5044 11:46:03.165968 BL = 0x2
5045 11:46:03.168999 RPST = 0x0
5046 11:46:03.169112 RD_PRE = 0x0
5047 11:46:03.171994 WR_PRE = 0x1
5048 11:46:03.172089 WR_PST = 0x0
5049 11:46:03.175278 DBI_WR = 0x0
5050 11:46:03.175372 DBI_RD = 0x0
5051 11:46:03.179012 OTF = 0x1
5052 11:46:03.182057 ===================================
5053 11:46:03.185187 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5054 11:46:03.188627 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5055 11:46:03.195407 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5056 11:46:03.198711 ===================================
5057 11:46:03.198787 LPDDR4 DRAM CONFIGURATION
5058 11:46:03.201803 ===================================
5059 11:46:03.205282 EX_ROW_EN[0] = 0x10
5060 11:46:03.205384 EX_ROW_EN[1] = 0x0
5061 11:46:03.208809 LP4Y_EN = 0x0
5062 11:46:03.211901 WORK_FSP = 0x0
5063 11:46:03.212000 WL = 0x3
5064 11:46:03.215145 RL = 0x3
5065 11:46:03.215244 BL = 0x2
5066 11:46:03.218578 RPST = 0x0
5067 11:46:03.218678 RD_PRE = 0x0
5068 11:46:03.221873 WR_PRE = 0x1
5069 11:46:03.221972 WR_PST = 0x0
5070 11:46:03.225317 DBI_WR = 0x0
5071 11:46:03.225418 DBI_RD = 0x0
5072 11:46:03.228705 OTF = 0x1
5073 11:46:03.232022 ===================================
5074 11:46:03.238376 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5075 11:46:03.241961 nWR fixed to 30
5076 11:46:03.242064 [ModeRegInit_LP4] CH0 RK0
5077 11:46:03.245097 [ModeRegInit_LP4] CH0 RK1
5078 11:46:03.248206 [ModeRegInit_LP4] CH1 RK0
5079 11:46:03.248307 [ModeRegInit_LP4] CH1 RK1
5080 11:46:03.251716 match AC timing 9
5081 11:46:03.254984 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5082 11:46:03.258401 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5083 11:46:03.264838 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5084 11:46:03.268326 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5085 11:46:03.275160 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5086 11:46:03.275266 ==
5087 11:46:03.278615 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 11:46:03.281729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 11:46:03.281835 ==
5090 11:46:03.288409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 11:46:03.291603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5092 11:46:03.295656 [CA 0] Center 37 (7~68) winsize 62
5093 11:46:03.299275 [CA 1] Center 37 (7~68) winsize 62
5094 11:46:03.302541 [CA 2] Center 35 (5~66) winsize 62
5095 11:46:03.305887 [CA 3] Center 34 (4~65) winsize 62
5096 11:46:03.308986 [CA 4] Center 34 (4~64) winsize 61
5097 11:46:03.312773 [CA 5] Center 33 (3~64) winsize 62
5098 11:46:03.312878
5099 11:46:03.316291 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5100 11:46:03.316395
5101 11:46:03.319041 [CATrainingPosCal] consider 1 rank data
5102 11:46:03.322595 u2DelayCellTimex100 = 270/100 ps
5103 11:46:03.325808 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5104 11:46:03.329365 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5105 11:46:03.335932 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5106 11:46:03.339207 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5107 11:46:03.342503 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5108 11:46:03.345900 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5109 11:46:03.346005
5110 11:46:03.349349 CA PerBit enable=1, Macro0, CA PI delay=33
5111 11:46:03.349431
5112 11:46:03.352707 [CBTSetCACLKResult] CA Dly = 33
5113 11:46:03.352816 CS Dly: 6 (0~37)
5114 11:46:03.356154 ==
5115 11:46:03.356256 Dram Type= 6, Freq= 0, CH_0, rank 1
5116 11:46:03.362365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 11:46:03.362485 ==
5118 11:46:03.365648 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5119 11:46:03.372621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5120 11:46:03.375948 [CA 0] Center 38 (7~69) winsize 63
5121 11:46:03.379450 [CA 1] Center 38 (8~69) winsize 62
5122 11:46:03.382742 [CA 2] Center 36 (6~66) winsize 61
5123 11:46:03.386143 [CA 3] Center 35 (5~66) winsize 62
5124 11:46:03.389507 [CA 4] Center 34 (4~65) winsize 62
5125 11:46:03.392660 [CA 5] Center 34 (4~64) winsize 61
5126 11:46:03.392769
5127 11:46:03.396011 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5128 11:46:03.396116
5129 11:46:03.399232 [CATrainingPosCal] consider 2 rank data
5130 11:46:03.402592 u2DelayCellTimex100 = 270/100 ps
5131 11:46:03.406092 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5132 11:46:03.409229 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5133 11:46:03.415793 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5134 11:46:03.419349 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5135 11:46:03.422683 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5136 11:46:03.425875 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5137 11:46:03.425990
5138 11:46:03.429159 CA PerBit enable=1, Macro0, CA PI delay=34
5139 11:46:03.429276
5140 11:46:03.432572 [CBTSetCACLKResult] CA Dly = 34
5141 11:46:03.432685 CS Dly: 7 (0~39)
5142 11:46:03.432788
5143 11:46:03.435726 ----->DramcWriteLeveling(PI) begin...
5144 11:46:03.438968 ==
5145 11:46:03.442518 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 11:46:03.445653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 11:46:03.445776 ==
5148 11:46:03.449005 Write leveling (Byte 0): 32 => 32
5149 11:46:03.452105 Write leveling (Byte 1): 30 => 30
5150 11:46:03.455496 DramcWriteLeveling(PI) end<-----
5151 11:46:03.455588
5152 11:46:03.455656 ==
5153 11:46:03.458998 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 11:46:03.462620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 11:46:03.462733 ==
5156 11:46:03.465676 [Gating] SW mode calibration
5157 11:46:03.472099 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5158 11:46:03.479129 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5159 11:46:03.482391 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5160 11:46:03.485563 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 11:46:03.492107 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 11:46:03.495668 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 11:46:03.498967 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 11:46:03.505370 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 11:46:03.508834 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
5166 11:46:03.511928 0 14 28 | B1->B0 | 3131 2525 | 1 0 | (1 0) (0 0)
5167 11:46:03.515331 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5168 11:46:03.521982 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 11:46:03.525329 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 11:46:03.529031 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 11:46:03.535337 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 11:46:03.538780 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 11:46:03.542389 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
5174 11:46:03.548894 0 15 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
5175 11:46:03.551897 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5176 11:46:03.555537 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 11:46:03.562091 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 11:46:03.565425 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 11:46:03.568968 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 11:46:03.575553 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 11:46:03.579202 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5182 11:46:03.582399 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5183 11:46:03.588780 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 11:46:03.592342 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 11:46:03.595398 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 11:46:03.601854 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 11:46:03.605101 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 11:46:03.608615 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 11:46:03.612171 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 11:46:03.618892 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 11:46:03.622261 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 11:46:03.625360 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 11:46:03.631916 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 11:46:03.635829 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 11:46:03.638859 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 11:46:03.645139 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 11:46:03.648464 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5198 11:46:03.651856 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5199 11:46:03.658820 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5200 11:46:03.661944 Total UI for P1: 0, mck2ui 16
5201 11:46:03.665090 best dqsien dly found for B0: ( 1, 2, 26)
5202 11:46:03.668410 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 11:46:03.671758 Total UI for P1: 0, mck2ui 16
5204 11:46:03.675260 best dqsien dly found for B1: ( 1, 2, 30)
5205 11:46:03.678375 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5206 11:46:03.681816 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5207 11:46:03.681903
5208 11:46:03.684971 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5209 11:46:03.688398 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5210 11:46:03.692114 [Gating] SW calibration Done
5211 11:46:03.692202 ==
5212 11:46:03.695224 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 11:46:03.698776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 11:46:03.701471 ==
5215 11:46:03.701584 RX Vref Scan: 0
5216 11:46:03.701680
5217 11:46:03.705075 RX Vref 0 -> 0, step: 1
5218 11:46:03.705161
5219 11:46:03.708500 RX Delay -80 -> 252, step: 8
5220 11:46:03.711725 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5221 11:46:03.715154 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5222 11:46:03.718252 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5223 11:46:03.721816 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5224 11:46:03.728376 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5225 11:46:03.731899 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5226 11:46:03.734767 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5227 11:46:03.738283 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5228 11:46:03.741763 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5229 11:46:03.744786 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5230 11:46:03.751503 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5231 11:46:03.754949 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5232 11:46:03.758292 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5233 11:46:03.761584 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5234 11:46:03.764861 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5235 11:46:03.768000 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5236 11:46:03.768108 ==
5237 11:46:03.771362 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 11:46:03.778008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 11:46:03.778117 ==
5240 11:46:03.778221 DQS Delay:
5241 11:46:03.781155 DQS0 = 0, DQS1 = 0
5242 11:46:03.781265 DQM Delay:
5243 11:46:03.784613 DQM0 = 105, DQM1 = 91
5244 11:46:03.784706 DQ Delay:
5245 11:46:03.787780 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5246 11:46:03.791552 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5247 11:46:03.794512 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5248 11:46:03.798144 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =99
5249 11:46:03.798224
5250 11:46:03.798318
5251 11:46:03.798411 ==
5252 11:46:03.801355 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 11:46:03.804708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 11:46:03.804801 ==
5255 11:46:03.804868
5256 11:46:03.804930
5257 11:46:03.808088 TX Vref Scan disable
5258 11:46:03.811339 == TX Byte 0 ==
5259 11:46:03.814893 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5260 11:46:03.818026 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5261 11:46:03.821319 == TX Byte 1 ==
5262 11:46:03.824756 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5263 11:46:03.828108 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5264 11:46:03.828210 ==
5265 11:46:03.831568 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 11:46:03.837638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 11:46:03.837717 ==
5268 11:46:03.837782
5269 11:46:03.837847
5270 11:46:03.837907 TX Vref Scan disable
5271 11:46:03.841846 == TX Byte 0 ==
5272 11:46:03.844876 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5273 11:46:03.848658 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5274 11:46:03.851621 == TX Byte 1 ==
5275 11:46:03.855049 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5276 11:46:03.858223 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5277 11:46:03.861762
5278 11:46:03.861864 [DATLAT]
5279 11:46:03.861960 Freq=933, CH0 RK0
5280 11:46:03.862053
5281 11:46:03.865006 DATLAT Default: 0xd
5282 11:46:03.865107 0, 0xFFFF, sum = 0
5283 11:46:03.868388 1, 0xFFFF, sum = 0
5284 11:46:03.868470 2, 0xFFFF, sum = 0
5285 11:46:03.871727 3, 0xFFFF, sum = 0
5286 11:46:03.871830 4, 0xFFFF, sum = 0
5287 11:46:03.875242 5, 0xFFFF, sum = 0
5288 11:46:03.878755 6, 0xFFFF, sum = 0
5289 11:46:03.878834 7, 0xFFFF, sum = 0
5290 11:46:03.882091 8, 0xFFFF, sum = 0
5291 11:46:03.882202 9, 0xFFFF, sum = 0
5292 11:46:03.882297 10, 0x0, sum = 1
5293 11:46:03.885098 11, 0x0, sum = 2
5294 11:46:03.885202 12, 0x0, sum = 3
5295 11:46:03.888241 13, 0x0, sum = 4
5296 11:46:03.888344 best_step = 11
5297 11:46:03.888438
5298 11:46:03.888528 ==
5299 11:46:03.891951 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 11:46:03.898648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 11:46:03.898728 ==
5302 11:46:03.898793 RX Vref Scan: 1
5303 11:46:03.898852
5304 11:46:03.901987 RX Vref 0 -> 0, step: 1
5305 11:46:03.902064
5306 11:46:03.905241 RX Delay -53 -> 252, step: 4
5307 11:46:03.905341
5308 11:46:03.908380 Set Vref, RX VrefLevel [Byte0]: 57
5309 11:46:03.911625 [Byte1]: 49
5310 11:46:03.911727
5311 11:46:03.914897 Final RX Vref Byte 0 = 57 to rank0
5312 11:46:03.918494 Final RX Vref Byte 1 = 49 to rank0
5313 11:46:03.921556 Final RX Vref Byte 0 = 57 to rank1
5314 11:46:03.924959 Final RX Vref Byte 1 = 49 to rank1==
5315 11:46:03.928233 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 11:46:03.931424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 11:46:03.931524 ==
5318 11:46:03.935076 DQS Delay:
5319 11:46:03.935151 DQS0 = 0, DQS1 = 0
5320 11:46:03.938467 DQM Delay:
5321 11:46:03.938541 DQM0 = 107, DQM1 = 92
5322 11:46:03.938605 DQ Delay:
5323 11:46:03.941762 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5324 11:46:03.945213 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5325 11:46:03.951192 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5326 11:46:03.954978 DQ12 =94, DQ13 =94, DQ14 =102, DQ15 =100
5327 11:46:03.955055
5328 11:46:03.955119
5329 11:46:03.961119 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5330 11:46:03.964588 CH0 RK0: MR19=505, MR18=2824
5331 11:46:03.971145 CH0_RK0: MR19=0x505, MR18=0x2824, DQSOSC=409, MR23=63, INC=64, DEC=43
5332 11:46:03.971248
5333 11:46:03.974919 ----->DramcWriteLeveling(PI) begin...
5334 11:46:03.974996 ==
5335 11:46:03.978241 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 11:46:03.981533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 11:46:03.981635 ==
5338 11:46:03.985015 Write leveling (Byte 0): 34 => 34
5339 11:46:03.987999 Write leveling (Byte 1): 31 => 31
5340 11:46:03.991760 DramcWriteLeveling(PI) end<-----
5341 11:46:03.991840
5342 11:46:03.991904 ==
5343 11:46:03.994665 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 11:46:03.997904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 11:46:03.998025 ==
5346 11:46:04.001345 [Gating] SW mode calibration
5347 11:46:04.007910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5348 11:46:04.014916 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5349 11:46:04.018067 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 11:46:04.020991 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 11:46:04.028042 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 11:46:04.031644 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 11:46:04.034739 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 11:46:04.041095 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 11:46:04.044822 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5356 11:46:04.047981 0 14 28 | B1->B0 | 3030 2929 | 0 0 | (0 1) (0 1)
5357 11:46:04.054718 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 11:46:04.057874 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 11:46:04.061235 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 11:46:04.067803 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 11:46:04.071307 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 11:46:04.074691 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 11:46:04.081180 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
5364 11:46:04.084539 0 15 28 | B1->B0 | 3838 3e3e | 0 0 | (0 0) (1 1)
5365 11:46:04.087780 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 11:46:04.094563 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 11:46:04.098151 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 11:46:04.101101 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 11:46:04.107955 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 11:46:04.111004 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 11:46:04.114609 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 11:46:04.120881 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5373 11:46:04.124580 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 11:46:04.127910 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 11:46:04.131280 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:46:04.137523 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:46:04.140956 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:46:04.144297 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:46:04.151199 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:46:04.154089 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:46:04.157524 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:46:04.164622 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 11:46:04.167647 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:46:04.170814 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 11:46:04.177686 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 11:46:04.181092 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:46:04.184050 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5388 11:46:04.191032 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5389 11:46:04.194137 Total UI for P1: 0, mck2ui 16
5390 11:46:04.197693 best dqsien dly found for B0: ( 1, 2, 24)
5391 11:46:04.200595 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 11:46:04.204185 Total UI for P1: 0, mck2ui 16
5393 11:46:04.207522 best dqsien dly found for B1: ( 1, 2, 28)
5394 11:46:04.210805 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5395 11:46:04.214475 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5396 11:46:04.214576
5397 11:46:04.217569 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5398 11:46:04.220734 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5399 11:46:04.223983 [Gating] SW calibration Done
5400 11:46:04.224091 ==
5401 11:46:04.227525 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 11:46:04.230650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 11:46:04.233809 ==
5404 11:46:04.233913 RX Vref Scan: 0
5405 11:46:04.234007
5406 11:46:04.237599 RX Vref 0 -> 0, step: 1
5407 11:46:04.237705
5408 11:46:04.240592 RX Delay -80 -> 252, step: 8
5409 11:46:04.244155 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5410 11:46:04.247267 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5411 11:46:04.250526 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5412 11:46:04.254004 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5413 11:46:04.257089 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5414 11:46:04.263923 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5415 11:46:04.266994 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5416 11:46:04.270612 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5417 11:46:04.273835 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5418 11:46:04.277150 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5419 11:46:04.280613 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5420 11:46:04.286989 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5421 11:46:04.290221 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5422 11:46:04.293680 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5423 11:46:04.296978 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5424 11:46:04.300615 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5425 11:46:04.300723 ==
5426 11:46:04.304044 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 11:46:04.310283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 11:46:04.310415 ==
5429 11:46:04.310524 DQS Delay:
5430 11:46:04.313564 DQS0 = 0, DQS1 = 0
5431 11:46:04.313667 DQM Delay:
5432 11:46:04.313764 DQM0 = 103, DQM1 = 90
5433 11:46:04.317001 DQ Delay:
5434 11:46:04.320228 DQ0 =99, DQ1 =103, DQ2 =99, DQ3 =99
5435 11:46:04.323666 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =111
5436 11:46:04.326927 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5437 11:46:04.330158 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5438 11:46:04.330260
5439 11:46:04.330353
5440 11:46:04.330495 ==
5441 11:46:04.333189 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 11:46:04.337049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 11:46:04.337156 ==
5444 11:46:04.337251
5445 11:46:04.337338
5446 11:46:04.339990 TX Vref Scan disable
5447 11:46:04.343452 == TX Byte 0 ==
5448 11:46:04.346708 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5449 11:46:04.350004 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5450 11:46:04.353375 == TX Byte 1 ==
5451 11:46:04.356664 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5452 11:46:04.359944 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5453 11:46:04.360059 ==
5454 11:46:04.363523 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 11:46:04.366964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 11:46:04.369998 ==
5457 11:46:04.370100
5458 11:46:04.370202
5459 11:46:04.370292 TX Vref Scan disable
5460 11:46:04.373903 == TX Byte 0 ==
5461 11:46:04.377254 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5462 11:46:04.380538 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5463 11:46:04.383779 == TX Byte 1 ==
5464 11:46:04.387269 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5465 11:46:04.390325 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5466 11:46:04.393527
5467 11:46:04.393637 [DATLAT]
5468 11:46:04.393731 Freq=933, CH0 RK1
5469 11:46:04.393826
5470 11:46:04.396935 DATLAT Default: 0xb
5471 11:46:04.397045 0, 0xFFFF, sum = 0
5472 11:46:04.400334 1, 0xFFFF, sum = 0
5473 11:46:04.400444 2, 0xFFFF, sum = 0
5474 11:46:04.403664 3, 0xFFFF, sum = 0
5475 11:46:04.403779 4, 0xFFFF, sum = 0
5476 11:46:04.406852 5, 0xFFFF, sum = 0
5477 11:46:04.410663 6, 0xFFFF, sum = 0
5478 11:46:04.410769 7, 0xFFFF, sum = 0
5479 11:46:04.413486 8, 0xFFFF, sum = 0
5480 11:46:04.413586 9, 0xFFFF, sum = 0
5481 11:46:04.416772 10, 0x0, sum = 1
5482 11:46:04.416875 11, 0x0, sum = 2
5483 11:46:04.416974 12, 0x0, sum = 3
5484 11:46:04.420518 13, 0x0, sum = 4
5485 11:46:04.420618 best_step = 11
5486 11:46:04.420711
5487 11:46:04.420799 ==
5488 11:46:04.424026 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 11:46:04.429983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 11:46:04.430095 ==
5491 11:46:04.430190 RX Vref Scan: 0
5492 11:46:04.430282
5493 11:46:04.433833 RX Vref 0 -> 0, step: 1
5494 11:46:04.433922
5495 11:46:04.437066 RX Delay -53 -> 252, step: 4
5496 11:46:04.440431 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5497 11:46:04.447024 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5498 11:46:04.450256 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5499 11:46:04.453568 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5500 11:46:04.456714 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5501 11:46:04.460224 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5502 11:46:04.463649 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5503 11:46:04.470363 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5504 11:46:04.473683 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5505 11:46:04.476675 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5506 11:46:04.480316 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5507 11:46:04.483415 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5508 11:46:04.490142 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5509 11:46:04.493521 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5510 11:46:04.496846 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5511 11:46:04.499995 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5512 11:46:04.500115 ==
5513 11:46:04.503846 Dram Type= 6, Freq= 0, CH_0, rank 1
5514 11:46:04.507065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 11:46:04.510218 ==
5516 11:46:04.510323 DQS Delay:
5517 11:46:04.510461 DQS0 = 0, DQS1 = 0
5518 11:46:04.513651 DQM Delay:
5519 11:46:04.513752 DQM0 = 104, DQM1 = 92
5520 11:46:04.516878 DQ Delay:
5521 11:46:04.520547 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5522 11:46:04.523469 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5523 11:46:04.526727 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5524 11:46:04.530056 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =98
5525 11:46:04.530145
5526 11:46:04.530239
5527 11:46:04.536697 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5528 11:46:04.540029 CH0 RK1: MR19=505, MR18=2C0B
5529 11:46:04.547029 CH0_RK1: MR19=0x505, MR18=0x2C0B, DQSOSC=408, MR23=63, INC=65, DEC=43
5530 11:46:04.550076 [RxdqsGatingPostProcess] freq 933
5531 11:46:04.553398 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5532 11:46:04.556682 best DQS0 dly(2T, 0.5T) = (0, 10)
5533 11:46:04.560230 best DQS1 dly(2T, 0.5T) = (0, 10)
5534 11:46:04.563493 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5535 11:46:04.566769 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5536 11:46:04.570575 best DQS0 dly(2T, 0.5T) = (0, 10)
5537 11:46:04.573579 best DQS1 dly(2T, 0.5T) = (0, 10)
5538 11:46:04.576712 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5539 11:46:04.579896 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5540 11:46:04.583235 Pre-setting of DQS Precalculation
5541 11:46:04.586773 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5542 11:46:04.586881 ==
5543 11:46:04.590101 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 11:46:04.596514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 11:46:04.596626 ==
5546 11:46:04.599879 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 11:46:04.606501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5548 11:46:04.609908 [CA 0] Center 37 (7~68) winsize 62
5549 11:46:04.613452 [CA 1] Center 37 (7~68) winsize 62
5550 11:46:04.616528 [CA 2] Center 35 (5~65) winsize 61
5551 11:46:04.620172 [CA 3] Center 34 (4~65) winsize 62
5552 11:46:04.623586 [CA 4] Center 35 (5~65) winsize 61
5553 11:46:04.626588 [CA 5] Center 34 (4~64) winsize 61
5554 11:46:04.626680
5555 11:46:04.630077 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5556 11:46:04.630186
5557 11:46:04.633190 [CATrainingPosCal] consider 1 rank data
5558 11:46:04.636789 u2DelayCellTimex100 = 270/100 ps
5559 11:46:04.640113 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5560 11:46:04.643475 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5561 11:46:04.649846 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5562 11:46:04.653369 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5563 11:46:04.656591 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5564 11:46:04.660031 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5565 11:46:04.660143
5566 11:46:04.663382 CA PerBit enable=1, Macro0, CA PI delay=34
5567 11:46:04.663494
5568 11:46:04.666592 [CBTSetCACLKResult] CA Dly = 34
5569 11:46:04.666705 CS Dly: 6 (0~37)
5570 11:46:04.666798 ==
5571 11:46:04.669984 Dram Type= 6, Freq= 0, CH_1, rank 1
5572 11:46:04.676507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 11:46:04.676615 ==
5574 11:46:04.679744 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5575 11:46:04.686363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5576 11:46:04.690160 [CA 0] Center 37 (7~68) winsize 62
5577 11:46:04.693526 [CA 1] Center 37 (7~68) winsize 62
5578 11:46:04.696446 [CA 2] Center 35 (5~66) winsize 62
5579 11:46:04.700057 [CA 3] Center 35 (5~65) winsize 61
5580 11:46:04.703410 [CA 4] Center 35 (5~65) winsize 61
5581 11:46:04.706332 [CA 5] Center 34 (4~64) winsize 61
5582 11:46:04.706460
5583 11:46:04.710049 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5584 11:46:04.710150
5585 11:46:04.713453 [CATrainingPosCal] consider 2 rank data
5586 11:46:04.716441 u2DelayCellTimex100 = 270/100 ps
5587 11:46:04.719854 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5588 11:46:04.723240 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5589 11:46:04.729586 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5590 11:46:04.733157 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5591 11:46:04.736569 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5592 11:46:04.739728 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5593 11:46:04.739807
5594 11:46:04.742962 CA PerBit enable=1, Macro0, CA PI delay=34
5595 11:46:04.743043
5596 11:46:04.746260 [CBTSetCACLKResult] CA Dly = 34
5597 11:46:04.746341 CS Dly: 7 (0~39)
5598 11:46:04.746428
5599 11:46:04.749727 ----->DramcWriteLeveling(PI) begin...
5600 11:46:04.753119 ==
5601 11:46:04.756388 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 11:46:04.759406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 11:46:04.759482 ==
5604 11:46:04.762893 Write leveling (Byte 0): 25 => 25
5605 11:46:04.766465 Write leveling (Byte 1): 26 => 26
5606 11:46:04.769380 DramcWriteLeveling(PI) end<-----
5607 11:46:04.769479
5608 11:46:04.769560 ==
5609 11:46:04.772555 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 11:46:04.776348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 11:46:04.776425 ==
5612 11:46:04.780008 [Gating] SW mode calibration
5613 11:46:04.786098 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5614 11:46:04.789481 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5615 11:46:04.796513 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 11:46:04.799494 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 11:46:04.802848 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 11:46:04.809643 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 11:46:04.812758 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 11:46:04.816425 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 11:46:04.823198 0 14 24 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 1)
5622 11:46:04.826280 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5623 11:46:04.829859 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 11:46:04.836477 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 11:46:04.840302 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 11:46:04.843234 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 11:46:04.849600 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 11:46:04.853105 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 11:46:04.856309 0 15 24 | B1->B0 | 2828 2d2d | 0 1 | (0 0) (0 0)
5630 11:46:04.862788 0 15 28 | B1->B0 | 3a3a 3f3f | 0 1 | (0 0) (0 0)
5631 11:46:04.866542 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 11:46:04.869534 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 11:46:04.876029 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 11:46:04.879606 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 11:46:04.882901 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 11:46:04.889673 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 11:46:04.892781 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5638 11:46:04.895864 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5639 11:46:04.899440 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 11:46:04.905988 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 11:46:04.909661 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 11:46:04.912975 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 11:46:04.919413 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 11:46:04.922842 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 11:46:04.926072 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 11:46:04.932979 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 11:46:04.936045 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:46:04.939029 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:46:04.945735 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:46:04.949389 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 11:46:04.952458 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 11:46:04.959065 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:46:04.962523 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5654 11:46:04.965783 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5655 11:46:04.969439 Total UI for P1: 0, mck2ui 16
5656 11:46:04.972542 best dqsien dly found for B0: ( 1, 2, 24)
5657 11:46:04.978909 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 11:46:04.978991 Total UI for P1: 0, mck2ui 16
5659 11:46:04.986138 best dqsien dly found for B1: ( 1, 2, 26)
5660 11:46:04.989188 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5661 11:46:04.992350 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5662 11:46:04.992426
5663 11:46:04.995920 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5664 11:46:04.998928 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5665 11:46:05.002795 [Gating] SW calibration Done
5666 11:46:05.002873 ==
5667 11:46:05.005960 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 11:46:05.008985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 11:46:05.009089 ==
5670 11:46:05.012509 RX Vref Scan: 0
5671 11:46:05.012612
5672 11:46:05.012726 RX Vref 0 -> 0, step: 1
5673 11:46:05.012818
5674 11:46:05.015765 RX Delay -80 -> 252, step: 8
5675 11:46:05.018939 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5676 11:46:05.025477 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5677 11:46:05.029272 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5678 11:46:05.032167 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5679 11:46:05.035442 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5680 11:46:05.039035 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5681 11:46:05.042258 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5682 11:46:05.048816 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5683 11:46:05.052078 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5684 11:46:05.055215 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5685 11:46:05.058535 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5686 11:46:05.061793 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5687 11:46:05.065496 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5688 11:46:05.072173 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5689 11:46:05.075616 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5690 11:46:05.078671 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5691 11:46:05.078747 ==
5692 11:46:05.081845 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 11:46:05.085484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 11:46:05.085587 ==
5695 11:46:05.088878 DQS Delay:
5696 11:46:05.088983 DQS0 = 0, DQS1 = 0
5697 11:46:05.092139 DQM Delay:
5698 11:46:05.092220 DQM0 = 101, DQM1 = 95
5699 11:46:05.092286 DQ Delay:
5700 11:46:05.095484 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5701 11:46:05.098586 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5702 11:46:05.102186 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5703 11:46:05.105369 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5704 11:46:05.105473
5705 11:46:05.108652
5706 11:46:05.108752 ==
5707 11:46:05.112000 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 11:46:05.115511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 11:46:05.115586 ==
5710 11:46:05.115650
5711 11:46:05.115714
5712 11:46:05.118550 TX Vref Scan disable
5713 11:46:05.118648 == TX Byte 0 ==
5714 11:46:05.125491 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5715 11:46:05.128598 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5716 11:46:05.128700 == TX Byte 1 ==
5717 11:46:05.135356 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5718 11:46:05.138727 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5719 11:46:05.138833 ==
5720 11:46:05.141682 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 11:46:05.145074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 11:46:05.145182 ==
5723 11:46:05.145279
5724 11:46:05.145372
5725 11:46:05.148531 TX Vref Scan disable
5726 11:46:05.152149 == TX Byte 0 ==
5727 11:46:05.155513 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5728 11:46:05.158546 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5729 11:46:05.161930 == TX Byte 1 ==
5730 11:46:05.165136 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5731 11:46:05.168543 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5732 11:46:05.168619
5733 11:46:05.172084 [DATLAT]
5734 11:46:05.172183 Freq=933, CH1 RK0
5735 11:46:05.172279
5736 11:46:05.175144 DATLAT Default: 0xd
5737 11:46:05.175219 0, 0xFFFF, sum = 0
5738 11:46:05.178541 1, 0xFFFF, sum = 0
5739 11:46:05.178615 2, 0xFFFF, sum = 0
5740 11:46:05.181894 3, 0xFFFF, sum = 0
5741 11:46:05.181993 4, 0xFFFF, sum = 0
5742 11:46:05.185341 5, 0xFFFF, sum = 0
5743 11:46:05.185442 6, 0xFFFF, sum = 0
5744 11:46:05.188546 7, 0xFFFF, sum = 0
5745 11:46:05.188647 8, 0xFFFF, sum = 0
5746 11:46:05.191722 9, 0xFFFF, sum = 0
5747 11:46:05.191796 10, 0x0, sum = 1
5748 11:46:05.195346 11, 0x0, sum = 2
5749 11:46:05.195430 12, 0x0, sum = 3
5750 11:46:05.198528 13, 0x0, sum = 4
5751 11:46:05.198606 best_step = 11
5752 11:46:05.198669
5753 11:46:05.198728 ==
5754 11:46:05.201681 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 11:46:05.205045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 11:46:05.208347 ==
5757 11:46:05.208443 RX Vref Scan: 1
5758 11:46:05.208533
5759 11:46:05.211791 RX Vref 0 -> 0, step: 1
5760 11:46:05.211868
5761 11:46:05.215037 RX Delay -53 -> 252, step: 4
5762 11:46:05.215116
5763 11:46:05.215179 Set Vref, RX VrefLevel [Byte0]: 50
5764 11:46:05.218433 [Byte1]: 52
5765 11:46:05.223567
5766 11:46:05.223643 Final RX Vref Byte 0 = 50 to rank0
5767 11:46:05.226846 Final RX Vref Byte 1 = 52 to rank0
5768 11:46:05.230516 Final RX Vref Byte 0 = 50 to rank1
5769 11:46:05.233175 Final RX Vref Byte 1 = 52 to rank1==
5770 11:46:05.236807 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 11:46:05.243468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 11:46:05.243555 ==
5773 11:46:05.243622 DQS Delay:
5774 11:46:05.246596 DQS0 = 0, DQS1 = 0
5775 11:46:05.246680 DQM Delay:
5776 11:46:05.246747 DQM0 = 104, DQM1 = 96
5777 11:46:05.249784 DQ Delay:
5778 11:46:05.252870 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5779 11:46:05.256550 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5780 11:46:05.259897 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =90
5781 11:46:05.263146 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5782 11:46:05.263229
5783 11:46:05.263296
5784 11:46:05.269958 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5785 11:46:05.273519 CH1 RK0: MR19=505, MR18=1A33
5786 11:46:05.279662 CH1_RK0: MR19=0x505, MR18=0x1A33, DQSOSC=405, MR23=63, INC=66, DEC=44
5787 11:46:05.279747
5788 11:46:05.283378 ----->DramcWriteLeveling(PI) begin...
5789 11:46:05.283464 ==
5790 11:46:05.286375 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 11:46:05.289806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 11:46:05.293366 ==
5793 11:46:05.293453 Write leveling (Byte 0): 27 => 27
5794 11:46:05.296521 Write leveling (Byte 1): 27 => 27
5795 11:46:05.299848 DramcWriteLeveling(PI) end<-----
5796 11:46:05.299967
5797 11:46:05.300047 ==
5798 11:46:05.303219 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 11:46:05.309801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 11:46:05.309886 ==
5801 11:46:05.309953 [Gating] SW mode calibration
5802 11:46:05.319604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5803 11:46:05.323153 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5804 11:46:05.329786 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 11:46:05.332965 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 11:46:05.336338 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 11:46:05.339687 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 11:46:05.346661 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 11:46:05.349896 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 11:46:05.352888 0 14 24 | B1->B0 | 3030 3333 | 0 1 | (0 0) (1 0)
5811 11:46:05.359749 0 14 28 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (1 1)
5812 11:46:05.363018 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 11:46:05.366511 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 11:46:05.372992 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 11:46:05.376376 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 11:46:05.379514 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 11:46:05.386206 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 11:46:05.389765 0 15 24 | B1->B0 | 2c2c 2323 | 1 1 | (0 0) (0 0)
5819 11:46:05.392888 0 15 28 | B1->B0 | 4444 4141 | 1 0 | (0 0) (0 0)
5820 11:46:05.399865 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 11:46:05.402744 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 11:46:05.406543 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 11:46:05.412656 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 11:46:05.416518 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 11:46:05.419663 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 11:46:05.426396 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5827 11:46:05.429768 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5828 11:46:05.432929 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 11:46:05.436173 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 11:46:05.442949 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 11:46:05.446044 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 11:46:05.449429 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 11:46:05.456208 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 11:46:05.459311 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 11:46:05.463004 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 11:46:05.469591 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 11:46:05.472847 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 11:46:05.476158 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 11:46:05.482817 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 11:46:05.486025 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 11:46:05.489696 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 11:46:05.495990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5843 11:46:05.499553 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5844 11:46:05.502775 Total UI for P1: 0, mck2ui 16
5845 11:46:05.506244 best dqsien dly found for B1: ( 1, 2, 24)
5846 11:46:05.509389 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 11:46:05.512793 Total UI for P1: 0, mck2ui 16
5848 11:46:05.515720 best dqsien dly found for B0: ( 1, 2, 26)
5849 11:46:05.519345 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5850 11:46:05.522756 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5851 11:46:05.522840
5852 11:46:05.529054 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5853 11:46:05.532832 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5854 11:46:05.532917 [Gating] SW calibration Done
5855 11:46:05.536088 ==
5856 11:46:05.536172 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 11:46:05.542538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 11:46:05.542622 ==
5859 11:46:05.542688 RX Vref Scan: 0
5860 11:46:05.542750
5861 11:46:05.545993 RX Vref 0 -> 0, step: 1
5862 11:46:05.546078
5863 11:46:05.549554 RX Delay -80 -> 252, step: 8
5864 11:46:05.552545 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5865 11:46:05.556146 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5866 11:46:05.559273 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5867 11:46:05.566093 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5868 11:46:05.569204 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5869 11:46:05.572268 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5870 11:46:05.575783 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5871 11:46:05.579374 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5872 11:46:05.582391 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5873 11:46:05.589249 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5874 11:46:05.592365 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5875 11:46:05.595801 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5876 11:46:05.599123 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5877 11:46:05.602520 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5878 11:46:05.605575 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5879 11:46:05.612924 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5880 11:46:05.613022 ==
5881 11:46:05.615745 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 11:46:05.619172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 11:46:05.619256 ==
5884 11:46:05.619353 DQS Delay:
5885 11:46:05.622201 DQS0 = 0, DQS1 = 0
5886 11:46:05.622299 DQM Delay:
5887 11:46:05.625490 DQM0 = 101, DQM1 = 96
5888 11:46:05.625573 DQ Delay:
5889 11:46:05.629018 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5890 11:46:05.632655 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5891 11:46:05.635948 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5892 11:46:05.638978 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5893 11:46:05.639090
5894 11:46:05.639156
5895 11:46:05.639218 ==
5896 11:46:05.642527 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 11:46:05.645706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 11:46:05.648954 ==
5899 11:46:05.649039
5900 11:46:05.649106
5901 11:46:05.649181 TX Vref Scan disable
5902 11:46:05.652676 == TX Byte 0 ==
5903 11:46:05.655637 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5904 11:46:05.659216 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5905 11:46:05.662488 == TX Byte 1 ==
5906 11:46:05.665681 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5907 11:46:05.669163 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5908 11:46:05.669247 ==
5909 11:46:05.672405 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 11:46:05.679098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 11:46:05.679183 ==
5912 11:46:05.679249
5913 11:46:05.679311
5914 11:46:05.679369 TX Vref Scan disable
5915 11:46:05.683142 == TX Byte 0 ==
5916 11:46:05.686369 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5917 11:46:05.693213 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5918 11:46:05.693337 == TX Byte 1 ==
5919 11:46:05.696397 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5920 11:46:05.703412 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5921 11:46:05.703520
5922 11:46:05.703612 [DATLAT]
5923 11:46:05.703718 Freq=933, CH1 RK1
5924 11:46:05.703808
5925 11:46:05.706351 DATLAT Default: 0xb
5926 11:46:05.706483 0, 0xFFFF, sum = 0
5927 11:46:05.709696 1, 0xFFFF, sum = 0
5928 11:46:05.709796 2, 0xFFFF, sum = 0
5929 11:46:05.713384 3, 0xFFFF, sum = 0
5930 11:46:05.716348 4, 0xFFFF, sum = 0
5931 11:46:05.716458 5, 0xFFFF, sum = 0
5932 11:46:05.719673 6, 0xFFFF, sum = 0
5933 11:46:05.719775 7, 0xFFFF, sum = 0
5934 11:46:05.723306 8, 0xFFFF, sum = 0
5935 11:46:05.723413 9, 0xFFFF, sum = 0
5936 11:46:05.726322 10, 0x0, sum = 1
5937 11:46:05.726450 11, 0x0, sum = 2
5938 11:46:05.726542 12, 0x0, sum = 3
5939 11:46:05.729751 13, 0x0, sum = 4
5940 11:46:05.729852 best_step = 11
5941 11:46:05.729950
5942 11:46:05.733182 ==
5943 11:46:05.733281 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 11:46:05.739668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 11:46:05.739769 ==
5946 11:46:05.739859 RX Vref Scan: 0
5947 11:46:05.739955
5948 11:46:05.743595 RX Vref 0 -> 0, step: 1
5949 11:46:05.743700
5950 11:46:05.746592 RX Delay -45 -> 252, step: 4
5951 11:46:05.749737 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5952 11:46:05.756896 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5953 11:46:05.760191 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5954 11:46:05.763176 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5955 11:46:05.766832 iDelay=199, Bit 4, Center 108 (27 ~ 190) 164
5956 11:46:05.769920 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5957 11:46:05.776158 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5958 11:46:05.779960 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5959 11:46:05.782807 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5960 11:46:05.786260 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5961 11:46:05.789535 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5962 11:46:05.792916 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5963 11:46:05.799604 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5964 11:46:05.802764 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5965 11:46:05.806259 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5966 11:46:05.809375 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5967 11:46:05.809471 ==
5968 11:46:05.812868 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 11:46:05.819645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 11:46:05.819718 ==
5971 11:46:05.819780 DQS Delay:
5972 11:46:05.822649 DQS0 = 0, DQS1 = 0
5973 11:46:05.822717 DQM Delay:
5974 11:46:05.822777 DQM0 = 105, DQM1 = 97
5975 11:46:05.826139 DQ Delay:
5976 11:46:05.829578 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =102
5977 11:46:05.833046 DQ4 =108, DQ5 =114, DQ6 =112, DQ7 =104
5978 11:46:05.836050 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =90
5979 11:46:05.839737 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =108
5980 11:46:05.839818
5981 11:46:05.839880
5982 11:46:05.846108 [DQSOSCAuto] RK1, (LSB)MR18= 0x2704, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
5983 11:46:05.849495 CH1 RK1: MR19=505, MR18=2704
5984 11:46:05.855907 CH1_RK1: MR19=0x505, MR18=0x2704, DQSOSC=409, MR23=63, INC=64, DEC=43
5985 11:46:05.859553 [RxdqsGatingPostProcess] freq 933
5986 11:46:05.865813 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5987 11:46:05.869534 best DQS0 dly(2T, 0.5T) = (0, 10)
5988 11:46:05.869633 best DQS1 dly(2T, 0.5T) = (0, 10)
5989 11:46:05.872917 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5990 11:46:05.876003 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5991 11:46:05.879566 best DQS0 dly(2T, 0.5T) = (0, 10)
5992 11:46:05.882493 best DQS1 dly(2T, 0.5T) = (0, 10)
5993 11:46:05.885839 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5994 11:46:05.889120 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5995 11:46:05.892731 Pre-setting of DQS Precalculation
5996 11:46:05.899369 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5997 11:46:05.905822 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5998 11:46:05.912624 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5999 11:46:05.912699
6000 11:46:05.912767
6001 11:46:05.915675 [Calibration Summary] 1866 Mbps
6002 11:46:05.915747 CH 0, Rank 0
6003 11:46:05.919032 SW Impedance : PASS
6004 11:46:05.922425 DUTY Scan : NO K
6005 11:46:05.922531 ZQ Calibration : PASS
6006 11:46:05.925625 Jitter Meter : NO K
6007 11:46:05.929109 CBT Training : PASS
6008 11:46:05.929205 Write leveling : PASS
6009 11:46:05.932507 RX DQS gating : PASS
6010 11:46:05.932601 RX DQ/DQS(RDDQC) : PASS
6011 11:46:05.935486 TX DQ/DQS : PASS
6012 11:46:05.939384 RX DATLAT : PASS
6013 11:46:05.939452 RX DQ/DQS(Engine): PASS
6014 11:46:05.942583 TX OE : NO K
6015 11:46:05.942651 All Pass.
6016 11:46:05.942710
6017 11:46:05.945598 CH 0, Rank 1
6018 11:46:05.945691 SW Impedance : PASS
6019 11:46:05.948858 DUTY Scan : NO K
6020 11:46:05.952434 ZQ Calibration : PASS
6021 11:46:05.952540 Jitter Meter : NO K
6022 11:46:05.955794 CBT Training : PASS
6023 11:46:05.959339 Write leveling : PASS
6024 11:46:05.959407 RX DQS gating : PASS
6025 11:46:05.962414 RX DQ/DQS(RDDQC) : PASS
6026 11:46:05.966189 TX DQ/DQS : PASS
6027 11:46:05.966285 RX DATLAT : PASS
6028 11:46:05.969133 RX DQ/DQS(Engine): PASS
6029 11:46:05.972603 TX OE : NO K
6030 11:46:05.972697 All Pass.
6031 11:46:05.972789
6032 11:46:05.972875 CH 1, Rank 0
6033 11:46:05.976188 SW Impedance : PASS
6034 11:46:05.979317 DUTY Scan : NO K
6035 11:46:05.979412 ZQ Calibration : PASS
6036 11:46:05.982646 Jitter Meter : NO K
6037 11:46:05.982739 CBT Training : PASS
6038 11:46:05.985934 Write leveling : PASS
6039 11:46:05.988982 RX DQS gating : PASS
6040 11:46:05.989084 RX DQ/DQS(RDDQC) : PASS
6041 11:46:05.992609 TX DQ/DQS : PASS
6042 11:46:05.995833 RX DATLAT : PASS
6043 11:46:05.995937 RX DQ/DQS(Engine): PASS
6044 11:46:05.999185 TX OE : NO K
6045 11:46:05.999283 All Pass.
6046 11:46:05.999373
6047 11:46:06.002111 CH 1, Rank 1
6048 11:46:06.002212 SW Impedance : PASS
6049 11:46:06.006098 DUTY Scan : NO K
6050 11:46:06.009067 ZQ Calibration : PASS
6051 11:46:06.009146 Jitter Meter : NO K
6052 11:46:06.012342 CBT Training : PASS
6053 11:46:06.015428 Write leveling : PASS
6054 11:46:06.015526 RX DQS gating : PASS
6055 11:46:06.018810 RX DQ/DQS(RDDQC) : PASS
6056 11:46:06.022331 TX DQ/DQS : PASS
6057 11:46:06.022469 RX DATLAT : PASS
6058 11:46:06.025727 RX DQ/DQS(Engine): PASS
6059 11:46:06.025823 TX OE : NO K
6060 11:46:06.028456 All Pass.
6061 11:46:06.028550
6062 11:46:06.028641 DramC Write-DBI off
6063 11:46:06.032532 PER_BANK_REFRESH: Hybrid Mode
6064 11:46:06.035229 TX_TRACKING: ON
6065 11:46:06.041853 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6066 11:46:06.045734 [FAST_K] Save calibration result to emmc
6067 11:46:06.051983 dramc_set_vcore_voltage set vcore to 650000
6068 11:46:06.052097 Read voltage for 400, 6
6069 11:46:06.055502 Vio18 = 0
6070 11:46:06.055576 Vcore = 650000
6071 11:46:06.055677 Vdram = 0
6072 11:46:06.055738 Vddq = 0
6073 11:46:06.058447 Vmddr = 0
6074 11:46:06.061852 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6075 11:46:06.068488 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6076 11:46:06.071809 MEM_TYPE=3, freq_sel=20
6077 11:46:06.075357 sv_algorithm_assistance_LP4_800
6078 11:46:06.078361 ============ PULL DRAM RESETB DOWN ============
6079 11:46:06.081854 ========== PULL DRAM RESETB DOWN end =========
6080 11:46:06.085135 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6081 11:46:06.088094 ===================================
6082 11:46:06.091684 LPDDR4 DRAM CONFIGURATION
6083 11:46:06.094942 ===================================
6084 11:46:06.098249 EX_ROW_EN[0] = 0x0
6085 11:46:06.098350 EX_ROW_EN[1] = 0x0
6086 11:46:06.101563 LP4Y_EN = 0x0
6087 11:46:06.101661 WORK_FSP = 0x0
6088 11:46:06.104839 WL = 0x2
6089 11:46:06.104936 RL = 0x2
6090 11:46:06.107968 BL = 0x2
6091 11:46:06.108066 RPST = 0x0
6092 11:46:06.111806 RD_PRE = 0x0
6093 11:46:06.111906 WR_PRE = 0x1
6094 11:46:06.114844 WR_PST = 0x0
6095 11:46:06.114915 DBI_WR = 0x0
6096 11:46:06.117994 DBI_RD = 0x0
6097 11:46:06.122093 OTF = 0x1
6098 11:46:06.124926 ===================================
6099 11:46:06.125028 ===================================
6100 11:46:06.128124 ANA top config
6101 11:46:06.131406 ===================================
6102 11:46:06.135222 DLL_ASYNC_EN = 0
6103 11:46:06.135322 ALL_SLAVE_EN = 1
6104 11:46:06.138145 NEW_RANK_MODE = 1
6105 11:46:06.141607 DLL_IDLE_MODE = 1
6106 11:46:06.144803 LP45_APHY_COMB_EN = 1
6107 11:46:06.148016 TX_ODT_DIS = 1
6108 11:46:06.148113 NEW_8X_MODE = 1
6109 11:46:06.151811 ===================================
6110 11:46:06.154614 ===================================
6111 11:46:06.157986 data_rate = 800
6112 11:46:06.161545 CKR = 1
6113 11:46:06.164846 DQ_P2S_RATIO = 4
6114 11:46:06.168339 ===================================
6115 11:46:06.171546 CA_P2S_RATIO = 4
6116 11:46:06.174562 DQ_CA_OPEN = 0
6117 11:46:06.174663 DQ_SEMI_OPEN = 1
6118 11:46:06.178306 CA_SEMI_OPEN = 1
6119 11:46:06.181548 CA_FULL_RATE = 0
6120 11:46:06.184740 DQ_CKDIV4_EN = 0
6121 11:46:06.188118 CA_CKDIV4_EN = 1
6122 11:46:06.188236 CA_PREDIV_EN = 0
6123 11:46:06.191493 PH8_DLY = 0
6124 11:46:06.194674 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6125 11:46:06.198009 DQ_AAMCK_DIV = 0
6126 11:46:06.201327 CA_AAMCK_DIV = 0
6127 11:46:06.204869 CA_ADMCK_DIV = 4
6128 11:46:06.204973 DQ_TRACK_CA_EN = 0
6129 11:46:06.207810 CA_PICK = 800
6130 11:46:06.211262 CA_MCKIO = 400
6131 11:46:06.214372 MCKIO_SEMI = 400
6132 11:46:06.217857 PLL_FREQ = 3016
6133 11:46:06.221550 DQ_UI_PI_RATIO = 32
6134 11:46:06.224741 CA_UI_PI_RATIO = 32
6135 11:46:06.227813 ===================================
6136 11:46:06.231492 ===================================
6137 11:46:06.231578 memory_type:LPDDR4
6138 11:46:06.234444 GP_NUM : 10
6139 11:46:06.237983 SRAM_EN : 1
6140 11:46:06.238093 MD32_EN : 0
6141 11:46:06.241641 ===================================
6142 11:46:06.244756 [ANA_INIT] >>>>>>>>>>>>>>
6143 11:46:06.248003 <<<<<< [CONFIGURE PHASE]: ANA_TX
6144 11:46:06.251679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6145 11:46:06.254799 ===================================
6146 11:46:06.257652 data_rate = 800,PCW = 0X7400
6147 11:46:06.260830 ===================================
6148 11:46:06.264577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6149 11:46:06.267760 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 11:46:06.281430 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6151 11:46:06.284596 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6152 11:46:06.287819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6153 11:46:06.291600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6154 11:46:06.294630 [ANA_INIT] flow start
6155 11:46:06.297968 [ANA_INIT] PLL >>>>>>>>
6156 11:46:06.298054 [ANA_INIT] PLL <<<<<<<<
6157 11:46:06.301217 [ANA_INIT] MIDPI >>>>>>>>
6158 11:46:06.304545 [ANA_INIT] MIDPI <<<<<<<<
6159 11:46:06.304631 [ANA_INIT] DLL >>>>>>>>
6160 11:46:06.307655 [ANA_INIT] flow end
6161 11:46:06.311192 ============ LP4 DIFF to SE enter ============
6162 11:46:06.314514 ============ LP4 DIFF to SE exit ============
6163 11:46:06.317542 [ANA_INIT] <<<<<<<<<<<<<
6164 11:46:06.321177 [Flow] Enable top DCM control >>>>>
6165 11:46:06.324353 [Flow] Enable top DCM control <<<<<
6166 11:46:06.327524 Enable DLL master slave shuffle
6167 11:46:06.334135 ==============================================================
6168 11:46:06.334221 Gating Mode config
6169 11:46:06.341073 ==============================================================
6170 11:46:06.341159 Config description:
6171 11:46:06.350776 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6172 11:46:06.357765 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6173 11:46:06.364076 SELPH_MODE 0: By rank 1: By Phase
6174 11:46:06.367484 ==============================================================
6175 11:46:06.370762 GAT_TRACK_EN = 0
6176 11:46:06.374040 RX_GATING_MODE = 2
6177 11:46:06.377454 RX_GATING_TRACK_MODE = 2
6178 11:46:06.380521 SELPH_MODE = 1
6179 11:46:06.383904 PICG_EARLY_EN = 1
6180 11:46:06.387273 VALID_LAT_VALUE = 1
6181 11:46:06.394178 ==============================================================
6182 11:46:06.397303 Enter into Gating configuration >>>>
6183 11:46:06.401117 Exit from Gating configuration <<<<
6184 11:46:06.401204 Enter into DVFS_PRE_config >>>>>
6185 11:46:06.413853 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6186 11:46:06.417679 Exit from DVFS_PRE_config <<<<<
6187 11:46:06.420769 Enter into PICG configuration >>>>
6188 11:46:06.424291 Exit from PICG configuration <<<<
6189 11:46:06.424379 [RX_INPUT] configuration >>>>>
6190 11:46:06.427422 [RX_INPUT] configuration <<<<<
6191 11:46:06.434118 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6192 11:46:06.437531 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6193 11:46:06.443885 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6194 11:46:06.450969 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6195 11:46:06.457787 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6196 11:46:06.464341 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6197 11:46:06.467792 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6198 11:46:06.470668 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6199 11:46:06.474406 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6200 11:46:06.480637 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6201 11:46:06.483981 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6202 11:46:06.487474 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6203 11:46:06.491132 ===================================
6204 11:46:06.493817 LPDDR4 DRAM CONFIGURATION
6205 11:46:06.497541 ===================================
6206 11:46:06.500684 EX_ROW_EN[0] = 0x0
6207 11:46:06.500823 EX_ROW_EN[1] = 0x0
6208 11:46:06.503865 LP4Y_EN = 0x0
6209 11:46:06.503997 WORK_FSP = 0x0
6210 11:46:06.507141 WL = 0x2
6211 11:46:06.507271 RL = 0x2
6212 11:46:06.510790 BL = 0x2
6213 11:46:06.510893 RPST = 0x0
6214 11:46:06.513999 RD_PRE = 0x0
6215 11:46:06.514109 WR_PRE = 0x1
6216 11:46:06.517282 WR_PST = 0x0
6217 11:46:06.517384 DBI_WR = 0x0
6218 11:46:06.520852 DBI_RD = 0x0
6219 11:46:06.520951 OTF = 0x1
6220 11:46:06.524112 ===================================
6221 11:46:06.527501 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6222 11:46:06.534008 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6223 11:46:06.537613 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 11:46:06.540905 ===================================
6225 11:46:06.544084 LPDDR4 DRAM CONFIGURATION
6226 11:46:06.547295 ===================================
6227 11:46:06.547367 EX_ROW_EN[0] = 0x10
6228 11:46:06.550802 EX_ROW_EN[1] = 0x0
6229 11:46:06.553906 LP4Y_EN = 0x0
6230 11:46:06.553993 WORK_FSP = 0x0
6231 11:46:06.557473 WL = 0x2
6232 11:46:06.557557 RL = 0x2
6233 11:46:06.560635 BL = 0x2
6234 11:46:06.560720 RPST = 0x0
6235 11:46:06.563617 RD_PRE = 0x0
6236 11:46:06.563703 WR_PRE = 0x1
6237 11:46:06.567278 WR_PST = 0x0
6238 11:46:06.567364 DBI_WR = 0x0
6239 11:46:06.570592 DBI_RD = 0x0
6240 11:46:06.570677 OTF = 0x1
6241 11:46:06.573480 ===================================
6242 11:46:06.580111 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6243 11:46:06.584785 nWR fixed to 30
6244 11:46:06.588153 [ModeRegInit_LP4] CH0 RK0
6245 11:46:06.588238 [ModeRegInit_LP4] CH0 RK1
6246 11:46:06.591319 [ModeRegInit_LP4] CH1 RK0
6247 11:46:06.594901 [ModeRegInit_LP4] CH1 RK1
6248 11:46:06.594986 match AC timing 19
6249 11:46:06.601601 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6250 11:46:06.605017 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6251 11:46:06.608449 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6252 11:46:06.614624 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6253 11:46:06.617906 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6254 11:46:06.617991 ==
6255 11:46:06.621097 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 11:46:06.624635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 11:46:06.624720 ==
6258 11:46:06.631162 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 11:46:06.637731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6260 11:46:06.641371 [CA 0] Center 36 (8~64) winsize 57
6261 11:46:06.644697 [CA 1] Center 36 (8~64) winsize 57
6262 11:46:06.647714 [CA 2] Center 36 (8~64) winsize 57
6263 11:46:06.650966 [CA 3] Center 36 (8~64) winsize 57
6264 11:46:06.651052 [CA 4] Center 36 (8~64) winsize 57
6265 11:46:06.654419 [CA 5] Center 36 (8~64) winsize 57
6266 11:46:06.654532
6267 11:46:06.661150 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6268 11:46:06.661235
6269 11:46:06.664080 [CATrainingPosCal] consider 1 rank data
6270 11:46:06.667988 u2DelayCellTimex100 = 270/100 ps
6271 11:46:06.671004 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 11:46:06.674178 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 11:46:06.677633 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 11:46:06.681022 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 11:46:06.684065 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 11:46:06.687795 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 11:46:06.687879
6278 11:46:06.691132 CA PerBit enable=1, Macro0, CA PI delay=36
6279 11:46:06.691217
6280 11:46:06.694442 [CBTSetCACLKResult] CA Dly = 36
6281 11:46:06.697992 CS Dly: 1 (0~32)
6282 11:46:06.698077 ==
6283 11:46:06.701130 Dram Type= 6, Freq= 0, CH_0, rank 1
6284 11:46:06.704349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 11:46:06.704435 ==
6286 11:46:06.710861 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6287 11:46:06.714148 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6288 11:46:06.717591 [CA 0] Center 36 (8~64) winsize 57
6289 11:46:06.720828 [CA 1] Center 36 (8~64) winsize 57
6290 11:46:06.724017 [CA 2] Center 36 (8~64) winsize 57
6291 11:46:06.727517 [CA 3] Center 36 (8~64) winsize 57
6292 11:46:06.730727 [CA 4] Center 36 (8~64) winsize 57
6293 11:46:06.734202 [CA 5] Center 36 (8~64) winsize 57
6294 11:46:06.734287
6295 11:46:06.737511 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6296 11:46:06.737625
6297 11:46:06.740851 [CATrainingPosCal] consider 2 rank data
6298 11:46:06.744266 u2DelayCellTimex100 = 270/100 ps
6299 11:46:06.747757 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 11:46:06.750992 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 11:46:06.754443 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 11:46:06.760680 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 11:46:06.764402 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 11:46:06.767273 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:46:06.767358
6306 11:46:06.770570 CA PerBit enable=1, Macro0, CA PI delay=36
6307 11:46:06.770655
6308 11:46:06.774594 [CBTSetCACLKResult] CA Dly = 36
6309 11:46:06.774679 CS Dly: 1 (0~32)
6310 11:46:06.774746
6311 11:46:06.777425 ----->DramcWriteLeveling(PI) begin...
6312 11:46:06.777511 ==
6313 11:46:06.780608 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 11:46:06.787328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 11:46:06.787414 ==
6316 11:46:06.790704 Write leveling (Byte 0): 40 => 8
6317 11:46:06.794139 Write leveling (Byte 1): 32 => 0
6318 11:46:06.794223 DramcWriteLeveling(PI) end<-----
6319 11:46:06.794291
6320 11:46:06.797331 ==
6321 11:46:06.800747 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 11:46:06.804147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 11:46:06.804233 ==
6324 11:46:06.807280 [Gating] SW mode calibration
6325 11:46:06.814571 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6326 11:46:06.817856 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6327 11:46:06.824336 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 11:46:06.827506 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6329 11:46:06.830694 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 11:46:06.837309 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 11:46:06.840950 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 11:46:06.843922 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 11:46:06.850377 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 11:46:06.853722 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 11:46:06.857285 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 11:46:06.860548 Total UI for P1: 0, mck2ui 16
6337 11:46:06.863749 best dqsien dly found for B0: ( 0, 14, 24)
6338 11:46:06.867162 Total UI for P1: 0, mck2ui 16
6339 11:46:06.870418 best dqsien dly found for B1: ( 0, 14, 24)
6340 11:46:06.873572 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6341 11:46:06.877322 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6342 11:46:06.877407
6343 11:46:06.883853 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 11:46:06.887405 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6345 11:46:06.887490 [Gating] SW calibration Done
6346 11:46:06.890401 ==
6347 11:46:06.893957 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 11:46:06.897696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 11:46:06.897808 ==
6350 11:46:06.897903 RX Vref Scan: 0
6351 11:46:06.897995
6352 11:46:06.900524 RX Vref 0 -> 0, step: 1
6353 11:46:06.900609
6354 11:46:06.903716 RX Delay -410 -> 252, step: 16
6355 11:46:06.906910 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6356 11:46:06.910180 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6357 11:46:06.917067 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6358 11:46:06.920552 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6359 11:46:06.923472 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6360 11:46:06.927204 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6361 11:46:06.933641 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6362 11:46:06.937073 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6363 11:46:06.940380 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6364 11:46:06.943326 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6365 11:46:06.950031 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6366 11:46:06.953622 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6367 11:46:06.956782 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6368 11:46:06.960139 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6369 11:46:06.966892 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6370 11:46:06.970046 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6371 11:46:06.970130 ==
6372 11:46:06.973710 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 11:46:06.976727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 11:46:06.976811 ==
6375 11:46:06.979928 DQS Delay:
6376 11:46:06.980010 DQS0 = 27, DQS1 = 43
6377 11:46:06.983267 DQM Delay:
6378 11:46:06.983350 DQM0 = 13, DQM1 = 13
6379 11:46:06.983416 DQ Delay:
6380 11:46:06.986632 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6381 11:46:06.990007 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6382 11:46:06.993085 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6383 11:46:06.996757 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6384 11:46:06.996841
6385 11:46:06.996907
6386 11:46:06.996967 ==
6387 11:46:07.000136 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 11:46:07.006706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 11:46:07.006789 ==
6390 11:46:07.006854
6391 11:46:07.006914
6392 11:46:07.006971 TX Vref Scan disable
6393 11:46:07.010081 == TX Byte 0 ==
6394 11:46:07.013104 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 11:46:07.016461 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 11:46:07.020074 == TX Byte 1 ==
6397 11:46:07.023697 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6398 11:46:07.026914 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6399 11:46:07.030167 ==
6400 11:46:07.030251 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 11:46:07.036584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 11:46:07.036668 ==
6403 11:46:07.036734
6404 11:46:07.036794
6405 11:46:07.039921 TX Vref Scan disable
6406 11:46:07.040004 == TX Byte 0 ==
6407 11:46:07.043432 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 11:46:07.046637 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 11:46:07.049889 == TX Byte 1 ==
6410 11:46:07.053196 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6411 11:46:07.056545 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6412 11:46:07.060027
6413 11:46:07.060111 [DATLAT]
6414 11:46:07.060218 Freq=400, CH0 RK0
6415 11:46:07.060285
6416 11:46:07.063155 DATLAT Default: 0xf
6417 11:46:07.063239 0, 0xFFFF, sum = 0
6418 11:46:07.066679 1, 0xFFFF, sum = 0
6419 11:46:07.066765 2, 0xFFFF, sum = 0
6420 11:46:07.070077 3, 0xFFFF, sum = 0
6421 11:46:07.070163 4, 0xFFFF, sum = 0
6422 11:46:07.073010 5, 0xFFFF, sum = 0
6423 11:46:07.076436 6, 0xFFFF, sum = 0
6424 11:46:07.076525 7, 0xFFFF, sum = 0
6425 11:46:07.079887 8, 0xFFFF, sum = 0
6426 11:46:07.079974 9, 0xFFFF, sum = 0
6427 11:46:07.083351 10, 0xFFFF, sum = 0
6428 11:46:07.083437 11, 0xFFFF, sum = 0
6429 11:46:07.086325 12, 0xFFFF, sum = 0
6430 11:46:07.086458 13, 0x0, sum = 1
6431 11:46:07.090101 14, 0x0, sum = 2
6432 11:46:07.090187 15, 0x0, sum = 3
6433 11:46:07.093449 16, 0x0, sum = 4
6434 11:46:07.093536 best_step = 14
6435 11:46:07.093603
6436 11:46:07.093667 ==
6437 11:46:07.096627 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 11:46:07.099692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 11:46:07.099780 ==
6440 11:46:07.103109 RX Vref Scan: 1
6441 11:46:07.103195
6442 11:46:07.106660 RX Vref 0 -> 0, step: 1
6443 11:46:07.106747
6444 11:46:07.106833 RX Delay -327 -> 252, step: 8
6445 11:46:07.106913
6446 11:46:07.109604 Set Vref, RX VrefLevel [Byte0]: 57
6447 11:46:07.113374 [Byte1]: 49
6448 11:46:07.118732
6449 11:46:07.118818 Final RX Vref Byte 0 = 57 to rank0
6450 11:46:07.121855 Final RX Vref Byte 1 = 49 to rank0
6451 11:46:07.125174 Final RX Vref Byte 0 = 57 to rank1
6452 11:46:07.128766 Final RX Vref Byte 1 = 49 to rank1==
6453 11:46:07.132059 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 11:46:07.135324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 11:46:07.138831 ==
6456 11:46:07.138917 DQS Delay:
6457 11:46:07.139001 DQS0 = 28, DQS1 = 48
6458 11:46:07.142190 DQM Delay:
6459 11:46:07.142276 DQM0 = 11, DQM1 = 15
6460 11:46:07.145229 DQ Delay:
6461 11:46:07.145315 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6462 11:46:07.148701 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6463 11:46:07.152074 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6464 11:46:07.155198 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6465 11:46:07.155285
6466 11:46:07.158779
6467 11:46:07.165420 [DQSOSCAuto] RK0, (LSB)MR18= 0xb2aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6468 11:46:07.168379 CH0 RK0: MR19=C0C, MR18=B2AA
6469 11:46:07.175385 CH0_RK0: MR19=0xC0C, MR18=0xB2AA, DQSOSC=387, MR23=63, INC=394, DEC=262
6470 11:46:07.175472 ==
6471 11:46:07.178285 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 11:46:07.181706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 11:46:07.181793 ==
6474 11:46:07.184965 [Gating] SW mode calibration
6475 11:46:07.191489 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6476 11:46:07.198528 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6477 11:46:07.201865 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 11:46:07.204928 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6479 11:46:07.208533 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 11:46:07.214904 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 11:46:07.218172 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 11:46:07.224705 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 11:46:07.228583 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 11:46:07.231749 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 11:46:07.234857 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 11:46:07.238230 Total UI for P1: 0, mck2ui 16
6487 11:46:07.241403 best dqsien dly found for B0: ( 0, 14, 24)
6488 11:46:07.244976 Total UI for P1: 0, mck2ui 16
6489 11:46:07.247990 best dqsien dly found for B1: ( 0, 14, 24)
6490 11:46:07.251396 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6491 11:46:07.254935 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6492 11:46:07.257948
6493 11:46:07.261265 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 11:46:07.264936 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6495 11:46:07.268149 [Gating] SW calibration Done
6496 11:46:07.268234 ==
6497 11:46:07.271376 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 11:46:07.274717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 11:46:07.274804 ==
6500 11:46:07.274889 RX Vref Scan: 0
6501 11:46:07.274990
6502 11:46:07.277972 RX Vref 0 -> 0, step: 1
6503 11:46:07.278081
6504 11:46:07.281395 RX Delay -410 -> 252, step: 16
6505 11:46:07.284813 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6506 11:46:07.291609 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6507 11:46:07.294802 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6508 11:46:07.298095 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6509 11:46:07.301433 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6510 11:46:07.307967 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6511 11:46:07.311234 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6512 11:46:07.314378 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6513 11:46:07.318085 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6514 11:46:07.324747 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6515 11:46:07.328134 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6516 11:46:07.331314 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6517 11:46:07.334902 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6518 11:46:07.341118 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6519 11:46:07.344417 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6520 11:46:07.347739 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6521 11:46:07.347825 ==
6522 11:46:07.351025 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 11:46:07.354418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 11:46:07.357924 ==
6525 11:46:07.358010 DQS Delay:
6526 11:46:07.358094 DQS0 = 27, DQS1 = 43
6527 11:46:07.361231 DQM Delay:
6528 11:46:07.361316 DQM0 = 14, DQM1 = 15
6529 11:46:07.364841 DQ Delay:
6530 11:46:07.364951 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =16
6531 11:46:07.368277 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6532 11:46:07.371695 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6533 11:46:07.374509 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6534 11:46:07.374584
6535 11:46:07.374663
6536 11:46:07.374727 ==
6537 11:46:07.378023 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 11:46:07.384867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 11:46:07.384976 ==
6540 11:46:07.385068
6541 11:46:07.385165
6542 11:46:07.385253 TX Vref Scan disable
6543 11:46:07.387781 == TX Byte 0 ==
6544 11:46:07.391287 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6545 11:46:07.394852 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6546 11:46:07.397886 == TX Byte 1 ==
6547 11:46:07.401556 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6548 11:46:07.404626 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6549 11:46:07.404725 ==
6550 11:46:07.407977 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 11:46:07.414439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 11:46:07.414552 ==
6553 11:46:07.414651
6554 11:46:07.414741
6555 11:46:07.414828 TX Vref Scan disable
6556 11:46:07.418309 == TX Byte 0 ==
6557 11:46:07.421108 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6558 11:46:07.424756 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6559 11:46:07.427899 == TX Byte 1 ==
6560 11:46:07.431237 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6561 11:46:07.434559 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6562 11:46:07.434663
6563 11:46:07.438098 [DATLAT]
6564 11:46:07.438201 Freq=400, CH0 RK1
6565 11:46:07.438290
6566 11:46:07.441763 DATLAT Default: 0xe
6567 11:46:07.441849 0, 0xFFFF, sum = 0
6568 11:46:07.444742 1, 0xFFFF, sum = 0
6569 11:46:07.444828 2, 0xFFFF, sum = 0
6570 11:46:07.448156 3, 0xFFFF, sum = 0
6571 11:46:07.448241 4, 0xFFFF, sum = 0
6572 11:46:07.451092 5, 0xFFFF, sum = 0
6573 11:46:07.451193 6, 0xFFFF, sum = 0
6574 11:46:07.454900 7, 0xFFFF, sum = 0
6575 11:46:07.454986 8, 0xFFFF, sum = 0
6576 11:46:07.457880 9, 0xFFFF, sum = 0
6577 11:46:07.461040 10, 0xFFFF, sum = 0
6578 11:46:07.461172 11, 0xFFFF, sum = 0
6579 11:46:07.464583 12, 0xFFFF, sum = 0
6580 11:46:07.464659 13, 0x0, sum = 1
6581 11:46:07.468121 14, 0x0, sum = 2
6582 11:46:07.468197 15, 0x0, sum = 3
6583 11:46:07.468259 16, 0x0, sum = 4
6584 11:46:07.470985 best_step = 14
6585 11:46:07.471055
6586 11:46:07.471116 ==
6587 11:46:07.474886 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 11:46:07.478147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 11:46:07.478222 ==
6590 11:46:07.481464 RX Vref Scan: 0
6591 11:46:07.481537
6592 11:46:07.481598 RX Vref 0 -> 0, step: 1
6593 11:46:07.484496
6594 11:46:07.484567 RX Delay -327 -> 252, step: 8
6595 11:46:07.492825 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6596 11:46:07.496361 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6597 11:46:07.500061 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6598 11:46:07.503467 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6599 11:46:07.509530 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6600 11:46:07.512760 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6601 11:46:07.516278 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6602 11:46:07.519646 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6603 11:46:07.526230 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6604 11:46:07.529883 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6605 11:46:07.532574 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6606 11:46:07.536524 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6607 11:46:07.542725 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6608 11:46:07.546125 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6609 11:46:07.549185 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6610 11:46:07.556048 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6611 11:46:07.556127 ==
6612 11:46:07.559606 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 11:46:07.562595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 11:46:07.562672 ==
6615 11:46:07.562735 DQS Delay:
6616 11:46:07.566016 DQS0 = 28, DQS1 = 40
6617 11:46:07.566085 DQM Delay:
6618 11:46:07.569151 DQM0 = 11, DQM1 = 13
6619 11:46:07.569220 DQ Delay:
6620 11:46:07.572537 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6621 11:46:07.576021 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6622 11:46:07.579515 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6623 11:46:07.582590 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6624 11:46:07.582664
6625 11:46:07.582725
6626 11:46:07.589198 [DQSOSCAuto] RK1, (LSB)MR18= 0xb76b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6627 11:46:07.592763 CH0 RK1: MR19=C0C, MR18=B76B
6628 11:46:07.599306 CH0_RK1: MR19=0xC0C, MR18=0xB76B, DQSOSC=387, MR23=63, INC=394, DEC=262
6629 11:46:07.602512 [RxdqsGatingPostProcess] freq 400
6630 11:46:07.608975 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6631 11:46:07.609070 best DQS0 dly(2T, 0.5T) = (0, 10)
6632 11:46:07.612262 best DQS1 dly(2T, 0.5T) = (0, 10)
6633 11:46:07.615647 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6634 11:46:07.619345 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6635 11:46:07.622639 best DQS0 dly(2T, 0.5T) = (0, 10)
6636 11:46:07.625784 best DQS1 dly(2T, 0.5T) = (0, 10)
6637 11:46:07.628943 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6638 11:46:07.632637 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6639 11:46:07.635955 Pre-setting of DQS Precalculation
6640 11:46:07.639297 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6641 11:46:07.642329 ==
6642 11:46:07.645565 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 11:46:07.649360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 11:46:07.649445 ==
6645 11:46:07.652150 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 11:46:07.659047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6647 11:46:07.662316 [CA 0] Center 36 (8~64) winsize 57
6648 11:46:07.665563 [CA 1] Center 36 (8~64) winsize 57
6649 11:46:07.668670 [CA 2] Center 36 (8~64) winsize 57
6650 11:46:07.672242 [CA 3] Center 36 (8~64) winsize 57
6651 11:46:07.675510 [CA 4] Center 36 (8~64) winsize 57
6652 11:46:07.678671 [CA 5] Center 36 (8~64) winsize 57
6653 11:46:07.678757
6654 11:46:07.682567 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6655 11:46:07.682653
6656 11:46:07.685593 [CATrainingPosCal] consider 1 rank data
6657 11:46:07.689123 u2DelayCellTimex100 = 270/100 ps
6658 11:46:07.692278 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 11:46:07.695752 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 11:46:07.699336 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 11:46:07.702333 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 11:46:07.705534 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 11:46:07.712455 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 11:46:07.712541
6665 11:46:07.715553 CA PerBit enable=1, Macro0, CA PI delay=36
6666 11:46:07.715638
6667 11:46:07.718795 [CBTSetCACLKResult] CA Dly = 36
6668 11:46:07.718880 CS Dly: 1 (0~32)
6669 11:46:07.718947 ==
6670 11:46:07.722104 Dram Type= 6, Freq= 0, CH_1, rank 1
6671 11:46:07.725663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 11:46:07.728951 ==
6673 11:46:07.732209 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6674 11:46:07.738857 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6675 11:46:07.742021 [CA 0] Center 36 (8~64) winsize 57
6676 11:46:07.745652 [CA 1] Center 36 (8~64) winsize 57
6677 11:46:07.748939 [CA 2] Center 36 (8~64) winsize 57
6678 11:46:07.752255 [CA 3] Center 36 (8~64) winsize 57
6679 11:46:07.755557 [CA 4] Center 36 (8~64) winsize 57
6680 11:46:07.758803 [CA 5] Center 36 (8~64) winsize 57
6681 11:46:07.758888
6682 11:46:07.761956 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6683 11:46:07.762041
6684 11:46:07.765734 [CATrainingPosCal] consider 2 rank data
6685 11:46:07.769057 u2DelayCellTimex100 = 270/100 ps
6686 11:46:07.771827 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 11:46:07.775556 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 11:46:07.778642 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 11:46:07.781972 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 11:46:07.785343 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 11:46:07.788773 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:46:07.788858
6693 11:46:07.791957 CA PerBit enable=1, Macro0, CA PI delay=36
6694 11:46:07.792042
6695 11:46:07.795188 [CBTSetCACLKResult] CA Dly = 36
6696 11:46:07.798797 CS Dly: 1 (0~32)
6697 11:46:07.798882
6698 11:46:07.802272 ----->DramcWriteLeveling(PI) begin...
6699 11:46:07.802409 ==
6700 11:46:07.805306 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 11:46:07.808750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 11:46:07.808855 ==
6703 11:46:07.812122 Write leveling (Byte 0): 40 => 8
6704 11:46:07.815601 Write leveling (Byte 1): 32 => 0
6705 11:46:07.818957 DramcWriteLeveling(PI) end<-----
6706 11:46:07.819030
6707 11:46:07.819104 ==
6708 11:46:07.822167 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 11:46:07.825482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 11:46:07.825581 ==
6711 11:46:07.828658 [Gating] SW mode calibration
6712 11:46:07.835594 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6713 11:46:07.841991 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6714 11:46:07.845025 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 11:46:07.852353 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6716 11:46:07.854990 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 11:46:07.858347 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 11:46:07.861933 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 11:46:07.868753 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 11:46:07.871570 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 11:46:07.875196 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 11:46:07.881470 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 11:46:07.884828 Total UI for P1: 0, mck2ui 16
6724 11:46:07.888522 best dqsien dly found for B0: ( 0, 14, 24)
6725 11:46:07.891830 Total UI for P1: 0, mck2ui 16
6726 11:46:07.894673 best dqsien dly found for B1: ( 0, 14, 24)
6727 11:46:07.897984 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6728 11:46:07.901943 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6729 11:46:07.902077
6730 11:46:07.904870 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 11:46:07.908215 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6732 11:46:07.911204 [Gating] SW calibration Done
6733 11:46:07.911305 ==
6734 11:46:07.914418 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 11:46:07.917806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 11:46:07.917910 ==
6737 11:46:07.921326 RX Vref Scan: 0
6738 11:46:07.921475
6739 11:46:07.924760 RX Vref 0 -> 0, step: 1
6740 11:46:07.924834
6741 11:46:07.924895 RX Delay -410 -> 252, step: 16
6742 11:46:07.931540 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6743 11:46:07.934681 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6744 11:46:07.938272 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6745 11:46:07.941570 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6746 11:46:07.948197 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6747 11:46:07.951701 iDelay=230, Bit 5, Center -11 (-234 ~ 213) 448
6748 11:46:07.955380 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6749 11:46:07.958156 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6750 11:46:07.964911 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6751 11:46:07.968556 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6752 11:46:07.971626 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6753 11:46:07.974962 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6754 11:46:07.981650 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6755 11:46:07.985032 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6756 11:46:07.988139 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6757 11:46:07.995050 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6758 11:46:07.995173 ==
6759 11:46:07.998292 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 11:46:08.001393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 11:46:08.001478 ==
6762 11:46:08.001545 DQS Delay:
6763 11:46:08.005111 DQS0 = 27, DQS1 = 43
6764 11:46:08.005195 DQM Delay:
6765 11:46:08.007974 DQM0 = 8, DQM1 = 18
6766 11:46:08.008058 DQ Delay:
6767 11:46:08.011978 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6768 11:46:08.014970 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6769 11:46:08.018147 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6770 11:46:08.021714 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6771 11:46:08.021830
6772 11:46:08.021924
6773 11:46:08.022021 ==
6774 11:46:08.024536 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 11:46:08.028098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 11:46:08.028179 ==
6777 11:46:08.028243
6778 11:46:08.028316
6779 11:46:08.031594 TX Vref Scan disable
6780 11:46:08.031679 == TX Byte 0 ==
6781 11:46:08.037956 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 11:46:08.041652 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 11:46:08.041738 == TX Byte 1 ==
6784 11:46:08.048259 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6785 11:46:08.051589 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6786 11:46:08.051675 ==
6787 11:46:08.054789 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 11:46:08.058073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 11:46:08.058159 ==
6790 11:46:08.058227
6791 11:46:08.058289
6792 11:46:08.061335 TX Vref Scan disable
6793 11:46:08.061420 == TX Byte 0 ==
6794 11:46:08.067878 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 11:46:08.071218 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 11:46:08.071320 == TX Byte 1 ==
6797 11:46:08.077736 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6798 11:46:08.081320 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6799 11:46:08.081405
6800 11:46:08.081472 [DATLAT]
6801 11:46:08.084298 Freq=400, CH1 RK0
6802 11:46:08.084383
6803 11:46:08.084450 DATLAT Default: 0xf
6804 11:46:08.087608 0, 0xFFFF, sum = 0
6805 11:46:08.087694 1, 0xFFFF, sum = 0
6806 11:46:08.091094 2, 0xFFFF, sum = 0
6807 11:46:08.091180 3, 0xFFFF, sum = 0
6808 11:46:08.094637 4, 0xFFFF, sum = 0
6809 11:46:08.094723 5, 0xFFFF, sum = 0
6810 11:46:08.097667 6, 0xFFFF, sum = 0
6811 11:46:08.101298 7, 0xFFFF, sum = 0
6812 11:46:08.101384 8, 0xFFFF, sum = 0
6813 11:46:08.104397 9, 0xFFFF, sum = 0
6814 11:46:08.104483 10, 0xFFFF, sum = 0
6815 11:46:08.107608 11, 0xFFFF, sum = 0
6816 11:46:08.107694 12, 0xFFFF, sum = 0
6817 11:46:08.110878 13, 0x0, sum = 1
6818 11:46:08.110964 14, 0x0, sum = 2
6819 11:46:08.114801 15, 0x0, sum = 3
6820 11:46:08.114886 16, 0x0, sum = 4
6821 11:46:08.114955 best_step = 14
6822 11:46:08.118032
6823 11:46:08.118116 ==
6824 11:46:08.121191 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 11:46:08.124561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 11:46:08.124647 ==
6827 11:46:08.124715 RX Vref Scan: 1
6828 11:46:08.124777
6829 11:46:08.127939 RX Vref 0 -> 0, step: 1
6830 11:46:08.128024
6831 11:46:08.131181 RX Delay -327 -> 252, step: 8
6832 11:46:08.131320
6833 11:46:08.134148 Set Vref, RX VrefLevel [Byte0]: 50
6834 11:46:08.137707 [Byte1]: 52
6835 11:46:08.141417
6836 11:46:08.141501 Final RX Vref Byte 0 = 50 to rank0
6837 11:46:08.144729 Final RX Vref Byte 1 = 52 to rank0
6838 11:46:08.147908 Final RX Vref Byte 0 = 50 to rank1
6839 11:46:08.151410 Final RX Vref Byte 1 = 52 to rank1==
6840 11:46:08.154605 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 11:46:08.161420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 11:46:08.161506 ==
6843 11:46:08.161573 DQS Delay:
6844 11:46:08.164885 DQS0 = 32, DQS1 = 40
6845 11:46:08.164969 DQM Delay:
6846 11:46:08.165037 DQM0 = 11, DQM1 = 13
6847 11:46:08.168068 DQ Delay:
6848 11:46:08.171345 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6849 11:46:08.171456 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6850 11:46:08.174923 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =8
6851 11:46:08.178109 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6852 11:46:08.178194
6853 11:46:08.178261
6854 11:46:08.188283 [DQSOSCAuto] RK0, (LSB)MR18= 0x9dd8, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6855 11:46:08.191505 CH1 RK0: MR19=C0C, MR18=9DD8
6856 11:46:08.198007 CH1_RK0: MR19=0xC0C, MR18=0x9DD8, DQSOSC=383, MR23=63, INC=402, DEC=268
6857 11:46:08.198094 ==
6858 11:46:08.201517 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 11:46:08.204921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 11:46:08.205007 ==
6861 11:46:08.208164 [Gating] SW mode calibration
6862 11:46:08.214926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6863 11:46:08.218146 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6864 11:46:08.224817 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 11:46:08.228386 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6866 11:46:08.231540 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 11:46:08.238254 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 11:46:08.241455 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 11:46:08.245027 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 11:46:08.251509 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 11:46:08.254730 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 11:46:08.258375 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 11:46:08.261258 Total UI for P1: 0, mck2ui 16
6874 11:46:08.264886 best dqsien dly found for B0: ( 0, 14, 24)
6875 11:46:08.268015 Total UI for P1: 0, mck2ui 16
6876 11:46:08.271390 best dqsien dly found for B1: ( 0, 14, 24)
6877 11:46:08.274630 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6878 11:46:08.277789 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6879 11:46:08.277873
6880 11:46:08.284390 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 11:46:08.287972 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6882 11:46:08.288057 [Gating] SW calibration Done
6883 11:46:08.291290 ==
6884 11:46:08.294781 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 11:46:08.297957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 11:46:08.298045 ==
6887 11:46:08.298112 RX Vref Scan: 0
6888 11:46:08.298173
6889 11:46:08.301248 RX Vref 0 -> 0, step: 1
6890 11:46:08.301321
6891 11:46:08.304631 RX Delay -410 -> 252, step: 16
6892 11:46:08.308286 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6893 11:46:08.311473 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6894 11:46:08.318282 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6895 11:46:08.321389 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6896 11:46:08.324758 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6897 11:46:08.328037 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6898 11:46:08.334726 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6899 11:46:08.337937 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6900 11:46:08.340958 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6901 11:46:08.344709 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6902 11:46:08.351375 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6903 11:46:08.354429 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6904 11:46:08.357986 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6905 11:46:08.360912 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6906 11:46:08.367718 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6907 11:46:08.371060 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6908 11:46:08.371147 ==
6909 11:46:08.374494 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 11:46:08.377636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 11:46:08.377723 ==
6912 11:46:08.380757 DQS Delay:
6913 11:46:08.380844 DQS0 = 35, DQS1 = 43
6914 11:46:08.384097 DQM Delay:
6915 11:46:08.384183 DQM0 = 18, DQM1 = 19
6916 11:46:08.387414 DQ Delay:
6917 11:46:08.387500 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6918 11:46:08.390908 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6919 11:46:08.394163 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6920 11:46:08.397795 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6921 11:46:08.397892
6922 11:46:08.397959
6923 11:46:08.400924 ==
6924 11:46:08.401033 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 11:46:08.407503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 11:46:08.407580 ==
6927 11:46:08.407644
6928 11:46:08.407703
6929 11:46:08.410826 TX Vref Scan disable
6930 11:46:08.410901 == TX Byte 0 ==
6931 11:46:08.414261 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6932 11:46:08.417336 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6933 11:46:08.420712 == TX Byte 1 ==
6934 11:46:08.424513 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6935 11:46:08.427505 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6936 11:46:08.430614 ==
6937 11:46:08.430686 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 11:46:08.437337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 11:46:08.437436 ==
6940 11:46:08.437535
6941 11:46:08.437623
6942 11:46:08.441195 TX Vref Scan disable
6943 11:46:08.441300 == TX Byte 0 ==
6944 11:46:08.444308 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6945 11:46:08.447379 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6946 11:46:08.450808 == TX Byte 1 ==
6947 11:46:08.454076 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6948 11:46:08.457572 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6949 11:46:08.457673
6950 11:46:08.460771 [DATLAT]
6951 11:46:08.460844 Freq=400, CH1 RK1
6952 11:46:08.460907
6953 11:46:08.464146 DATLAT Default: 0xe
6954 11:46:08.464245 0, 0xFFFF, sum = 0
6955 11:46:08.467389 1, 0xFFFF, sum = 0
6956 11:46:08.467489 2, 0xFFFF, sum = 0
6957 11:46:08.470925 3, 0xFFFF, sum = 0
6958 11:46:08.471002 4, 0xFFFF, sum = 0
6959 11:46:08.474347 5, 0xFFFF, sum = 0
6960 11:46:08.474467 6, 0xFFFF, sum = 0
6961 11:46:08.477379 7, 0xFFFF, sum = 0
6962 11:46:08.480755 8, 0xFFFF, sum = 0
6963 11:46:08.480855 9, 0xFFFF, sum = 0
6964 11:46:08.483982 10, 0xFFFF, sum = 0
6965 11:46:08.484082 11, 0xFFFF, sum = 0
6966 11:46:08.487190 12, 0xFFFF, sum = 0
6967 11:46:08.487266 13, 0x0, sum = 1
6968 11:46:08.490640 14, 0x0, sum = 2
6969 11:46:08.490739 15, 0x0, sum = 3
6970 11:46:08.494296 16, 0x0, sum = 4
6971 11:46:08.494730 best_step = 14
6972 11:46:08.495041
6973 11:46:08.495334 ==
6974 11:46:08.497722 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 11:46:08.500937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 11:46:08.501521 ==
6977 11:46:08.504733 RX Vref Scan: 0
6978 11:46:08.505404
6979 11:46:08.507947 RX Vref 0 -> 0, step: 1
6980 11:46:08.508640
6981 11:46:08.509192 RX Delay -327 -> 252, step: 8
6982 11:46:08.516535 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6983 11:46:08.519880 iDelay=217, Bit 1, Center -24 (-239 ~ 192) 432
6984 11:46:08.523071 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6985 11:46:08.526088 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6986 11:46:08.532771 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6987 11:46:08.536145 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6988 11:46:08.539291 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6989 11:46:08.542684 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6990 11:46:08.549145 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6991 11:46:08.552869 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6992 11:46:08.556264 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6993 11:46:08.562760 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6994 11:46:08.566215 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6995 11:46:08.569623 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6996 11:46:08.572816 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6997 11:46:08.579548 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6998 11:46:08.580028 ==
6999 11:46:08.582956 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 11:46:08.585966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 11:46:08.586504 ==
7002 11:46:08.586893 DQS Delay:
7003 11:46:08.589244 DQS0 = 32, DQS1 = 36
7004 11:46:08.589724 DQM Delay:
7005 11:46:08.593029 DQM0 = 12, DQM1 = 10
7006 11:46:08.593508 DQ Delay:
7007 11:46:08.595894 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7008 11:46:08.599097 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =8
7009 11:46:08.602656 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7010 11:46:08.606103 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7011 11:46:08.606616
7012 11:46:08.606990
7013 11:46:08.613200 [DQSOSCAuto] RK1, (LSB)MR18= 0xaa54, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7014 11:46:08.615826 CH1 RK1: MR19=C0C, MR18=AA54
7015 11:46:08.622795 CH1_RK1: MR19=0xC0C, MR18=0xAA54, DQSOSC=388, MR23=63, INC=392, DEC=261
7016 11:46:08.625982 [RxdqsGatingPostProcess] freq 400
7017 11:46:08.633079 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7018 11:46:08.633666 best DQS0 dly(2T, 0.5T) = (0, 10)
7019 11:46:08.636288 best DQS1 dly(2T, 0.5T) = (0, 10)
7020 11:46:08.639390 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7021 11:46:08.642848 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7022 11:46:08.645722 best DQS0 dly(2T, 0.5T) = (0, 10)
7023 11:46:08.649648 best DQS1 dly(2T, 0.5T) = (0, 10)
7024 11:46:08.652650 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7025 11:46:08.656038 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7026 11:46:08.659036 Pre-setting of DQS Precalculation
7027 11:46:08.662790 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7028 11:46:08.672626 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7029 11:46:08.679068 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7030 11:46:08.679543
7031 11:46:08.679915
7032 11:46:08.682408 [Calibration Summary] 800 Mbps
7033 11:46:08.682883 CH 0, Rank 0
7034 11:46:08.685907 SW Impedance : PASS
7035 11:46:08.686377 DUTY Scan : NO K
7036 11:46:08.689040 ZQ Calibration : PASS
7037 11:46:08.692717 Jitter Meter : NO K
7038 11:46:08.693186 CBT Training : PASS
7039 11:46:08.696220 Write leveling : PASS
7040 11:46:08.698931 RX DQS gating : PASS
7041 11:46:08.699458 RX DQ/DQS(RDDQC) : PASS
7042 11:46:08.702500 TX DQ/DQS : PASS
7043 11:46:08.705799 RX DATLAT : PASS
7044 11:46:08.706267 RX DQ/DQS(Engine): PASS
7045 11:46:08.709454 TX OE : NO K
7046 11:46:08.710049 All Pass.
7047 11:46:08.710489
7048 11:46:08.712655 CH 0, Rank 1
7049 11:46:08.713228 SW Impedance : PASS
7050 11:46:08.715634 DUTY Scan : NO K
7051 11:46:08.719352 ZQ Calibration : PASS
7052 11:46:08.719909 Jitter Meter : NO K
7053 11:46:08.722606 CBT Training : PASS
7054 11:46:08.726468 Write leveling : NO K
7055 11:46:08.727067 RX DQS gating : PASS
7056 11:46:08.728918 RX DQ/DQS(RDDQC) : PASS
7057 11:46:08.729389 TX DQ/DQS : PASS
7058 11:46:08.732591 RX DATLAT : PASS
7059 11:46:08.735811 RX DQ/DQS(Engine): PASS
7060 11:46:08.736391 TX OE : NO K
7061 11:46:08.739077 All Pass.
7062 11:46:08.739549
7063 11:46:08.739925 CH 1, Rank 0
7064 11:46:08.742307 SW Impedance : PASS
7065 11:46:08.742800 DUTY Scan : NO K
7066 11:46:08.745838 ZQ Calibration : PASS
7067 11:46:08.749205 Jitter Meter : NO K
7068 11:46:08.749790 CBT Training : PASS
7069 11:46:08.752566 Write leveling : PASS
7070 11:46:08.756339 RX DQS gating : PASS
7071 11:46:08.756878 RX DQ/DQS(RDDQC) : PASS
7072 11:46:08.759175 TX DQ/DQS : PASS
7073 11:46:08.762161 RX DATLAT : PASS
7074 11:46:08.762708 RX DQ/DQS(Engine): PASS
7075 11:46:08.766426 TX OE : NO K
7076 11:46:08.767004 All Pass.
7077 11:46:08.767383
7078 11:46:08.769124 CH 1, Rank 1
7079 11:46:08.769626 SW Impedance : PASS
7080 11:46:08.772517 DUTY Scan : NO K
7081 11:46:08.773139 ZQ Calibration : PASS
7082 11:46:08.775917 Jitter Meter : NO K
7083 11:46:08.778900 CBT Training : PASS
7084 11:46:08.779408 Write leveling : NO K
7085 11:46:08.782475 RX DQS gating : PASS
7086 11:46:08.786332 RX DQ/DQS(RDDQC) : PASS
7087 11:46:08.786969 TX DQ/DQS : PASS
7088 11:46:08.788987 RX DATLAT : PASS
7089 11:46:08.792602 RX DQ/DQS(Engine): PASS
7090 11:46:08.793073 TX OE : NO K
7091 11:46:08.795802 All Pass.
7092 11:46:08.796271
7093 11:46:08.796641 DramC Write-DBI off
7094 11:46:08.799290 PER_BANK_REFRESH: Hybrid Mode
7095 11:46:08.799764 TX_TRACKING: ON
7096 11:46:08.809068 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7097 11:46:08.813007 [FAST_K] Save calibration result to emmc
7098 11:46:08.816045 dramc_set_vcore_voltage set vcore to 725000
7099 11:46:08.819051 Read voltage for 1600, 0
7100 11:46:08.819526 Vio18 = 0
7101 11:46:08.822233 Vcore = 725000
7102 11:46:08.822752 Vdram = 0
7103 11:46:08.823130 Vddq = 0
7104 11:46:08.823478 Vmddr = 0
7105 11:46:08.829266 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7106 11:46:08.836370 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7107 11:46:08.836949 MEM_TYPE=3, freq_sel=13
7108 11:46:08.839017 sv_algorithm_assistance_LP4_3733
7109 11:46:08.842889 ============ PULL DRAM RESETB DOWN ============
7110 11:46:08.849196 ========== PULL DRAM RESETB DOWN end =========
7111 11:46:08.852523 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7112 11:46:08.855696 ===================================
7113 11:46:08.858891 LPDDR4 DRAM CONFIGURATION
7114 11:46:08.862546 ===================================
7115 11:46:08.863128 EX_ROW_EN[0] = 0x0
7116 11:46:08.866179 EX_ROW_EN[1] = 0x0
7117 11:46:08.866816 LP4Y_EN = 0x0
7118 11:46:08.869182 WORK_FSP = 0x1
7119 11:46:08.872643 WL = 0x5
7120 11:46:08.873217 RL = 0x5
7121 11:46:08.875607 BL = 0x2
7122 11:46:08.876085 RPST = 0x0
7123 11:46:08.879015 RD_PRE = 0x0
7124 11:46:08.879592 WR_PRE = 0x1
7125 11:46:08.882572 WR_PST = 0x1
7126 11:46:08.883145 DBI_WR = 0x0
7127 11:46:08.885641 DBI_RD = 0x0
7128 11:46:08.886111 OTF = 0x1
7129 11:46:08.888880 ===================================
7130 11:46:08.892144 ===================================
7131 11:46:08.895776 ANA top config
7132 11:46:08.898606 ===================================
7133 11:46:08.899083 DLL_ASYNC_EN = 0
7134 11:46:08.901925 ALL_SLAVE_EN = 0
7135 11:46:08.905830 NEW_RANK_MODE = 1
7136 11:46:08.908980 DLL_IDLE_MODE = 1
7137 11:46:08.909455 LP45_APHY_COMB_EN = 1
7138 11:46:08.912158 TX_ODT_DIS = 0
7139 11:46:08.915255 NEW_8X_MODE = 1
7140 11:46:08.919079 ===================================
7141 11:46:08.922008 ===================================
7142 11:46:08.925530 data_rate = 3200
7143 11:46:08.928735 CKR = 1
7144 11:46:08.932309 DQ_P2S_RATIO = 8
7145 11:46:08.935204 ===================================
7146 11:46:08.935693 CA_P2S_RATIO = 8
7147 11:46:08.938419 DQ_CA_OPEN = 0
7148 11:46:08.942054 DQ_SEMI_OPEN = 0
7149 11:46:08.945244 CA_SEMI_OPEN = 0
7150 11:46:08.948743 CA_FULL_RATE = 0
7151 11:46:08.951858 DQ_CKDIV4_EN = 0
7152 11:46:08.952453 CA_CKDIV4_EN = 0
7153 11:46:08.955162 CA_PREDIV_EN = 0
7154 11:46:08.958550 PH8_DLY = 12
7155 11:46:08.962047 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7156 11:46:08.965271 DQ_AAMCK_DIV = 4
7157 11:46:08.968450 CA_AAMCK_DIV = 4
7158 11:46:08.969050 CA_ADMCK_DIV = 4
7159 11:46:08.972010 DQ_TRACK_CA_EN = 0
7160 11:46:08.975083 CA_PICK = 1600
7161 11:46:08.978837 CA_MCKIO = 1600
7162 11:46:08.982058 MCKIO_SEMI = 0
7163 11:46:08.985293 PLL_FREQ = 3068
7164 11:46:08.988304 DQ_UI_PI_RATIO = 32
7165 11:46:08.988790 CA_UI_PI_RATIO = 0
7166 11:46:08.991675 ===================================
7167 11:46:08.994888 ===================================
7168 11:46:08.998586 memory_type:LPDDR4
7169 11:46:09.001820 GP_NUM : 10
7170 11:46:09.002298 SRAM_EN : 1
7171 11:46:09.004873 MD32_EN : 0
7172 11:46:09.008118 ===================================
7173 11:46:09.012015 [ANA_INIT] >>>>>>>>>>>>>>
7174 11:46:09.014882 <<<<<< [CONFIGURE PHASE]: ANA_TX
7175 11:46:09.018684 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7176 11:46:09.021944 ===================================
7177 11:46:09.022434 data_rate = 3200,PCW = 0X7600
7178 11:46:09.025017 ===================================
7179 11:46:09.028308 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7180 11:46:09.035246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 11:46:09.041698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7182 11:46:09.044708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7183 11:46:09.048561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7184 11:46:09.051634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7185 11:46:09.055016 [ANA_INIT] flow start
7186 11:46:09.055641 [ANA_INIT] PLL >>>>>>>>
7187 11:46:09.058141 [ANA_INIT] PLL <<<<<<<<
7188 11:46:09.061559 [ANA_INIT] MIDPI >>>>>>>>
7189 11:46:09.065445 [ANA_INIT] MIDPI <<<<<<<<
7190 11:46:09.066066 [ANA_INIT] DLL >>>>>>>>
7191 11:46:09.068444 [ANA_INIT] DLL <<<<<<<<
7192 11:46:09.071795 [ANA_INIT] flow end
7193 11:46:09.074745 ============ LP4 DIFF to SE enter ============
7194 11:46:09.078088 ============ LP4 DIFF to SE exit ============
7195 11:46:09.081652 [ANA_INIT] <<<<<<<<<<<<<
7196 11:46:09.085023 [Flow] Enable top DCM control >>>>>
7197 11:46:09.088163 [Flow] Enable top DCM control <<<<<
7198 11:46:09.091299 Enable DLL master slave shuffle
7199 11:46:09.094992 ==============================================================
7200 11:46:09.098060 Gating Mode config
7201 11:46:09.101645 ==============================================================
7202 11:46:09.104962 Config description:
7203 11:46:09.114557 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7204 11:46:09.121017 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7205 11:46:09.124993 SELPH_MODE 0: By rank 1: By Phase
7206 11:46:09.131353 ==============================================================
7207 11:46:09.135028 GAT_TRACK_EN = 1
7208 11:46:09.138228 RX_GATING_MODE = 2
7209 11:46:09.141289 RX_GATING_TRACK_MODE = 2
7210 11:46:09.144440 SELPH_MODE = 1
7211 11:46:09.148289 PICG_EARLY_EN = 1
7212 11:46:09.148844 VALID_LAT_VALUE = 1
7213 11:46:09.155121 ==============================================================
7214 11:46:09.158003 Enter into Gating configuration >>>>
7215 11:46:09.161480 Exit from Gating configuration <<<<
7216 11:46:09.165030 Enter into DVFS_PRE_config >>>>>
7217 11:46:09.174366 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7218 11:46:09.177815 Exit from DVFS_PRE_config <<<<<
7219 11:46:09.181522 Enter into PICG configuration >>>>
7220 11:46:09.184480 Exit from PICG configuration <<<<
7221 11:46:09.188193 [RX_INPUT] configuration >>>>>
7222 11:46:09.191506 [RX_INPUT] configuration <<<<<
7223 11:46:09.194615 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7224 11:46:09.201460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7225 11:46:09.208157 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7226 11:46:09.214878 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7227 11:46:09.221603 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7228 11:46:09.224572 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7229 11:46:09.231361 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7230 11:46:09.234545 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7231 11:46:09.237953 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7232 11:46:09.241265 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7233 11:46:09.247861 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7234 11:46:09.251184 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7235 11:46:09.254793 ===================================
7236 11:46:09.258183 LPDDR4 DRAM CONFIGURATION
7237 11:46:09.261389 ===================================
7238 11:46:09.261866 EX_ROW_EN[0] = 0x0
7239 11:46:09.264761 EX_ROW_EN[1] = 0x0
7240 11:46:09.265234 LP4Y_EN = 0x0
7241 11:46:09.267810 WORK_FSP = 0x1
7242 11:46:09.268310 WL = 0x5
7243 11:46:09.271290 RL = 0x5
7244 11:46:09.272074 BL = 0x2
7245 11:46:09.274478 RPST = 0x0
7246 11:46:09.275212 RD_PRE = 0x0
7247 11:46:09.277861 WR_PRE = 0x1
7248 11:46:09.278643 WR_PST = 0x1
7249 11:46:09.281400 DBI_WR = 0x0
7250 11:46:09.281873 DBI_RD = 0x0
7251 11:46:09.284563 OTF = 0x1
7252 11:46:09.288373 ===================================
7253 11:46:09.291175 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7254 11:46:09.294605 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7255 11:46:09.301409 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 11:46:09.304969 ===================================
7257 11:46:09.305446 LPDDR4 DRAM CONFIGURATION
7258 11:46:09.307901 ===================================
7259 11:46:09.311711 EX_ROW_EN[0] = 0x10
7260 11:46:09.314511 EX_ROW_EN[1] = 0x0
7261 11:46:09.314987 LP4Y_EN = 0x0
7262 11:46:09.317783 WORK_FSP = 0x1
7263 11:46:09.318259 WL = 0x5
7264 11:46:09.321299 RL = 0x5
7265 11:46:09.321868 BL = 0x2
7266 11:46:09.324410 RPST = 0x0
7267 11:46:09.324887 RD_PRE = 0x0
7268 11:46:09.327869 WR_PRE = 0x1
7269 11:46:09.328441 WR_PST = 0x1
7270 11:46:09.331224 DBI_WR = 0x0
7271 11:46:09.331701 DBI_RD = 0x0
7272 11:46:09.334725 OTF = 0x1
7273 11:46:09.337845 ===================================
7274 11:46:09.344544 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7275 11:46:09.345043 ==
7276 11:46:09.347936 Dram Type= 6, Freq= 0, CH_0, rank 0
7277 11:46:09.351227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7278 11:46:09.351850 ==
7279 11:46:09.354506 [Duty_Offset_Calibration]
7280 11:46:09.354982 B0:2 B1:0 CA:1
7281 11:46:09.355356
7282 11:46:09.357548 [DutyScan_Calibration_Flow] k_type=0
7283 11:46:09.368231
7284 11:46:09.368771 ==CLK 0==
7285 11:46:09.371286 Final CLK duty delay cell = -4
7286 11:46:09.374189 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7287 11:46:09.377569 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7288 11:46:09.381092 [-4] AVG Duty = 4937%(X100)
7289 11:46:09.381567
7290 11:46:09.384376 CH0 CLK Duty spec in!! Max-Min= 187%
7291 11:46:09.387901 [DutyScan_Calibration_Flow] ====Done====
7292 11:46:09.388376
7293 11:46:09.390969 [DutyScan_Calibration_Flow] k_type=1
7294 11:46:09.407257
7295 11:46:09.407819 ==DQS 0 ==
7296 11:46:09.410448 Final DQS duty delay cell = 0
7297 11:46:09.413704 [0] MAX Duty = 5249%(X100), DQS PI = 32
7298 11:46:09.417153 [0] MIN Duty = 4969%(X100), DQS PI = 0
7299 11:46:09.417654 [0] AVG Duty = 5109%(X100)
7300 11:46:09.420528
7301 11:46:09.421116 ==DQS 1 ==
7302 11:46:09.423578 Final DQS duty delay cell = -4
7303 11:46:09.426857 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7304 11:46:09.430132 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7305 11:46:09.433628 [-4] AVG Duty = 5000%(X100)
7306 11:46:09.434212
7307 11:46:09.436731 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7308 11:46:09.437210
7309 11:46:09.440319 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7310 11:46:09.443694 [DutyScan_Calibration_Flow] ====Done====
7311 11:46:09.444173
7312 11:46:09.446832 [DutyScan_Calibration_Flow] k_type=3
7313 11:46:09.464604
7314 11:46:09.465174 ==DQM 0 ==
7315 11:46:09.468174 Final DQM duty delay cell = 0
7316 11:46:09.471091 [0] MAX Duty = 5124%(X100), DQS PI = 26
7317 11:46:09.474916 [0] MIN Duty = 4813%(X100), DQS PI = 50
7318 11:46:09.477918 [0] AVG Duty = 4968%(X100)
7319 11:46:09.478534
7320 11:46:09.478918 ==DQM 1 ==
7321 11:46:09.481217 Final DQM duty delay cell = 0
7322 11:46:09.484910 [0] MAX Duty = 5249%(X100), DQS PI = 30
7323 11:46:09.488055 [0] MIN Duty = 5000%(X100), DQS PI = 20
7324 11:46:09.491047 [0] AVG Duty = 5124%(X100)
7325 11:46:09.491526
7326 11:46:09.494697 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7327 11:46:09.495174
7328 11:46:09.497896 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7329 11:46:09.500897 [DutyScan_Calibration_Flow] ====Done====
7330 11:46:09.501414
7331 11:46:09.504176 [DutyScan_Calibration_Flow] k_type=2
7332 11:46:09.521643
7333 11:46:09.522186 ==DQ 0 ==
7334 11:46:09.525370 Final DQ duty delay cell = 0
7335 11:46:09.528553 [0] MAX Duty = 5124%(X100), DQS PI = 32
7336 11:46:09.531508 [0] MIN Duty = 5000%(X100), DQS PI = 16
7337 11:46:09.531985 [0] AVG Duty = 5062%(X100)
7338 11:46:09.535283
7339 11:46:09.535824 ==DQ 1 ==
7340 11:46:09.538619 Final DQ duty delay cell = 0
7341 11:46:09.541992 [0] MAX Duty = 4969%(X100), DQS PI = 42
7342 11:46:09.545358 [0] MIN Duty = 4875%(X100), DQS PI = 0
7343 11:46:09.545908 [0] AVG Duty = 4922%(X100)
7344 11:46:09.546289
7345 11:46:09.548150 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7346 11:46:09.551862
7347 11:46:09.552429 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7348 11:46:09.558706 [DutyScan_Calibration_Flow] ====Done====
7349 11:46:09.559308 ==
7350 11:46:09.561663 Dram Type= 6, Freq= 0, CH_1, rank 0
7351 11:46:09.564993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7352 11:46:09.565581 ==
7353 11:46:09.568572 [Duty_Offset_Calibration]
7354 11:46:09.569047 B0:0 B1:-1 CA:2
7355 11:46:09.569424
7356 11:46:09.571359 [DutyScan_Calibration_Flow] k_type=0
7357 11:46:09.581757
7358 11:46:09.582332 ==CLK 0==
7359 11:46:09.585307 Final CLK duty delay cell = 0
7360 11:46:09.588666 [0] MAX Duty = 5156%(X100), DQS PI = 10
7361 11:46:09.592078 [0] MIN Duty = 4906%(X100), DQS PI = 46
7362 11:46:09.592539 [0] AVG Duty = 5031%(X100)
7363 11:46:09.595319
7364 11:46:09.598322 CH1 CLK Duty spec in!! Max-Min= 250%
7365 11:46:09.601545 [DutyScan_Calibration_Flow] ====Done====
7366 11:46:09.602004
7367 11:46:09.604744 [DutyScan_Calibration_Flow] k_type=1
7368 11:46:09.621629
7369 11:46:09.622299 ==DQS 0 ==
7370 11:46:09.624826 Final DQS duty delay cell = 0
7371 11:46:09.628623 [0] MAX Duty = 5093%(X100), DQS PI = 26
7372 11:46:09.631547 [0] MIN Duty = 4969%(X100), DQS PI = 58
7373 11:46:09.634710 [0] AVG Duty = 5031%(X100)
7374 11:46:09.635314
7375 11:46:09.635835 ==DQS 1 ==
7376 11:46:09.637883 Final DQS duty delay cell = 0
7377 11:46:09.641572 [0] MAX Duty = 5187%(X100), DQS PI = 62
7378 11:46:09.644893 [0] MIN Duty = 4844%(X100), DQS PI = 32
7379 11:46:09.648203 [0] AVG Duty = 5015%(X100)
7380 11:46:09.648770
7381 11:46:09.651584 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7382 11:46:09.652050
7383 11:46:09.655521 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7384 11:46:09.658300 [DutyScan_Calibration_Flow] ====Done====
7385 11:46:09.658854
7386 11:46:09.661299 [DutyScan_Calibration_Flow] k_type=3
7387 11:46:09.679300
7388 11:46:09.679829 ==DQM 0 ==
7389 11:46:09.682842 Final DQM duty delay cell = 4
7390 11:46:09.686112 [4] MAX Duty = 5125%(X100), DQS PI = 8
7391 11:46:09.689221 [4] MIN Duty = 5000%(X100), DQS PI = 32
7392 11:46:09.689777 [4] AVG Duty = 5062%(X100)
7393 11:46:09.692681
7394 11:46:09.693238 ==DQM 1 ==
7395 11:46:09.696041 Final DQM duty delay cell = 0
7396 11:46:09.699288 [0] MAX Duty = 5281%(X100), DQS PI = 60
7397 11:46:09.702491 [0] MIN Duty = 4876%(X100), DQS PI = 34
7398 11:46:09.702964 [0] AVG Duty = 5078%(X100)
7399 11:46:09.705739
7400 11:46:09.709184 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7401 11:46:09.709654
7402 11:46:09.712877 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7403 11:46:09.716079 [DutyScan_Calibration_Flow] ====Done====
7404 11:46:09.716640
7405 11:46:09.719288 [DutyScan_Calibration_Flow] k_type=2
7406 11:46:09.736137
7407 11:46:09.736694 ==DQ 0 ==
7408 11:46:09.740120 Final DQ duty delay cell = 0
7409 11:46:09.743307 [0] MAX Duty = 5093%(X100), DQS PI = 22
7410 11:46:09.746340 [0] MIN Duty = 4969%(X100), DQS PI = 48
7411 11:46:09.746938 [0] AVG Duty = 5031%(X100)
7412 11:46:09.750089
7413 11:46:09.750755 ==DQ 1 ==
7414 11:46:09.753377 Final DQ duty delay cell = 0
7415 11:46:09.756348 [0] MAX Duty = 5062%(X100), DQS PI = 0
7416 11:46:09.759933 [0] MIN Duty = 4813%(X100), DQS PI = 34
7417 11:46:09.760450 [0] AVG Duty = 4937%(X100)
7418 11:46:09.760840
7419 11:46:09.763050 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7420 11:46:09.763624
7421 11:46:09.766686 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7422 11:46:09.772593 [DutyScan_Calibration_Flow] ====Done====
7423 11:46:09.775953 nWR fixed to 30
7424 11:46:09.776434 [ModeRegInit_LP4] CH0 RK0
7425 11:46:09.779654 [ModeRegInit_LP4] CH0 RK1
7426 11:46:09.782578 [ModeRegInit_LP4] CH1 RK0
7427 11:46:09.783068 [ModeRegInit_LP4] CH1 RK1
7428 11:46:09.786326 match AC timing 5
7429 11:46:09.789188 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7430 11:46:09.792710 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7431 11:46:09.799721 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7432 11:46:09.802984 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7433 11:46:09.809434 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7434 11:46:09.809912 [MiockJmeterHQA]
7435 11:46:09.810281
7436 11:46:09.812665 [DramcMiockJmeter] u1RxGatingPI = 0
7437 11:46:09.816035 0 : 4368, 4140
7438 11:46:09.816615 4 : 4253, 4027
7439 11:46:09.816999 8 : 4368, 4140
7440 11:46:09.819099 12 : 4252, 4027
7441 11:46:09.819658 16 : 4363, 4137
7442 11:46:09.822731 20 : 4255, 4029
7443 11:46:09.823213 24 : 4363, 4137
7444 11:46:09.825789 28 : 4252, 4027
7445 11:46:09.826265 32 : 4253, 4027
7446 11:46:09.826674 36 : 4365, 4140
7447 11:46:09.829807 40 : 4250, 4027
7448 11:46:09.830423 44 : 4250, 4027
7449 11:46:09.833127 48 : 4250, 4027
7450 11:46:09.833705 52 : 4252, 4029
7451 11:46:09.835823 56 : 4252, 4029
7452 11:46:09.836298 60 : 4363, 4137
7453 11:46:09.839463 64 : 4360, 4138
7454 11:46:09.840043 68 : 4361, 4138
7455 11:46:09.840425 72 : 4252, 4029
7456 11:46:09.842485 76 : 4252, 4029
7457 11:46:09.842963 80 : 4253, 4026
7458 11:46:09.845925 84 : 4250, 4027
7459 11:46:09.846429 88 : 4361, 4016
7460 11:46:09.849426 92 : 4250, 0
7461 11:46:09.850007 96 : 4250, 0
7462 11:46:09.850420 100 : 4361, 0
7463 11:46:09.852807 104 : 4361, 0
7464 11:46:09.853389 108 : 4250, 0
7465 11:46:09.853772 112 : 4360, 0
7466 11:46:09.856450 116 : 4250, 0
7467 11:46:09.857029 120 : 4250, 0
7468 11:46:09.859130 124 : 4250, 0
7469 11:46:09.859630 128 : 4250, 0
7470 11:46:09.860007 132 : 4253, 0
7471 11:46:09.862733 136 : 4250, 0
7472 11:46:09.863213 140 : 4250, 0
7473 11:46:09.866531 144 : 4255, 0
7474 11:46:09.867110 148 : 4360, 0
7475 11:46:09.867494 152 : 4252, 0
7476 11:46:09.869583 156 : 4361, 0
7477 11:46:09.870163 160 : 4250, 0
7478 11:46:09.872526 164 : 4250, 0
7479 11:46:09.873003 168 : 4361, 0
7480 11:46:09.873378 172 : 4250, 0
7481 11:46:09.876153 176 : 4250, 0
7482 11:46:09.876736 180 : 4361, 0
7483 11:46:09.877116 184 : 4250, 0
7484 11:46:09.879417 188 : 4250, 0
7485 11:46:09.879895 192 : 4250, 0
7486 11:46:09.882547 196 : 4254, 0
7487 11:46:09.883130 200 : 4360, 1
7488 11:46:09.883512 204 : 4250, 2019
7489 11:46:09.885927 208 : 4255, 4030
7490 11:46:09.886545 212 : 4255, 4031
7491 11:46:09.889428 216 : 4363, 4140
7492 11:46:09.890017 220 : 4361, 4137
7493 11:46:09.892384 224 : 4250, 4027
7494 11:46:09.892862 228 : 4250, 4027
7495 11:46:09.896007 232 : 4363, 4140
7496 11:46:09.896596 236 : 4250, 4027
7497 11:46:09.899037 240 : 4250, 4027
7498 11:46:09.899581 244 : 4250, 4027
7499 11:46:09.902590 248 : 4252, 4030
7500 11:46:09.903173 252 : 4250, 4027
7501 11:46:09.905606 256 : 4361, 4138
7502 11:46:09.906088 260 : 4361, 4137
7503 11:46:09.906527 264 : 4250, 4027
7504 11:46:09.909536 268 : 4251, 4027
7505 11:46:09.910015 272 : 4250, 4027
7506 11:46:09.913347 276 : 4250, 4026
7507 11:46:09.913939 280 : 4250, 4026
7508 11:46:09.915837 284 : 4363, 4140
7509 11:46:09.916416 288 : 4250, 4027
7510 11:46:09.919495 292 : 4253, 4026
7511 11:46:09.920074 296 : 4363, 4139
7512 11:46:09.922588 300 : 4250, 4027
7513 11:46:09.923072 304 : 4250, 4027
7514 11:46:09.926050 308 : 4361, 4138
7515 11:46:09.926671 312 : 4361, 4121
7516 11:46:09.929292 316 : 4250, 2405
7517 11:46:09.929871 320 : 4250, 29
7518 11:46:09.930259
7519 11:46:09.932561 MIOCK jitter meter ch=0
7520 11:46:09.933133
7521 11:46:09.935666 1T = (320-92) = 228 dly cells
7522 11:46:09.939800 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7523 11:46:09.940535 ==
7524 11:46:09.942562 Dram Type= 6, Freq= 0, CH_0, rank 0
7525 11:46:09.949100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7526 11:46:09.949698 ==
7527 11:46:09.952341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7528 11:46:09.959125 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7529 11:46:09.962358 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7530 11:46:09.968780 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7531 11:46:09.976418 [CA 0] Center 42 (12~72) winsize 61
7532 11:46:09.979964 [CA 1] Center 42 (12~72) winsize 61
7533 11:46:09.983211 [CA 2] Center 37 (7~67) winsize 61
7534 11:46:09.986710 [CA 3] Center 37 (7~67) winsize 61
7535 11:46:09.989904 [CA 4] Center 36 (6~66) winsize 61
7536 11:46:09.993039 [CA 5] Center 35 (5~65) winsize 61
7537 11:46:09.993577
7538 11:46:09.996659 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7539 11:46:09.997238
7540 11:46:09.999575 [CATrainingPosCal] consider 1 rank data
7541 11:46:10.003216 u2DelayCellTimex100 = 285/100 ps
7542 11:46:10.006431 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7543 11:46:10.013181 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7544 11:46:10.016535 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7545 11:46:10.019493 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7546 11:46:10.023388 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7547 11:46:10.026495 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7548 11:46:10.026970
7549 11:46:10.029648 CA PerBit enable=1, Macro0, CA PI delay=35
7550 11:46:10.030118
7551 11:46:10.033490 [CBTSetCACLKResult] CA Dly = 35
7552 11:46:10.034030 CS Dly: 8 (0~39)
7553 11:46:10.039812 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7554 11:46:10.043115 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7555 11:46:10.043658 ==
7556 11:46:10.046312 Dram Type= 6, Freq= 0, CH_0, rank 1
7557 11:46:10.050169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 11:46:10.050780 ==
7559 11:46:10.056592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7560 11:46:10.059604 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7561 11:46:10.066352 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7562 11:46:10.069664 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7563 11:46:10.079682 [CA 0] Center 43 (13~74) winsize 62
7564 11:46:10.082724 [CA 1] Center 43 (13~73) winsize 61
7565 11:46:10.086239 [CA 2] Center 38 (9~68) winsize 60
7566 11:46:10.089596 [CA 3] Center 38 (9~68) winsize 60
7567 11:46:10.093096 [CA 4] Center 37 (7~67) winsize 61
7568 11:46:10.096141 [CA 5] Center 36 (6~66) winsize 61
7569 11:46:10.096611
7570 11:46:10.099630 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7571 11:46:10.100100
7572 11:46:10.102967 [CATrainingPosCal] consider 2 rank data
7573 11:46:10.106312 u2DelayCellTimex100 = 285/100 ps
7574 11:46:10.109498 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7575 11:46:10.115999 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7576 11:46:10.119461 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7577 11:46:10.123171 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7578 11:46:10.126137 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7579 11:46:10.129280 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7580 11:46:10.129750
7581 11:46:10.133093 CA PerBit enable=1, Macro0, CA PI delay=35
7582 11:46:10.133565
7583 11:46:10.135949 [CBTSetCACLKResult] CA Dly = 35
7584 11:46:10.139381 CS Dly: 10 (0~43)
7585 11:46:10.142648 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7586 11:46:10.146300 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7587 11:46:10.146819
7588 11:46:10.149657 ----->DramcWriteLeveling(PI) begin...
7589 11:46:10.150208 ==
7590 11:46:10.152490 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 11:46:10.159059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 11:46:10.159625 ==
7593 11:46:10.162532 Write leveling (Byte 0): 36 => 36
7594 11:46:10.163005 Write leveling (Byte 1): 31 => 31
7595 11:46:10.165775 DramcWriteLeveling(PI) end<-----
7596 11:46:10.166322
7597 11:46:10.166731 ==
7598 11:46:10.169050 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 11:46:10.176195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 11:46:10.176735 ==
7601 11:46:10.179242 [Gating] SW mode calibration
7602 11:46:10.186148 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7603 11:46:10.189076 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7604 11:46:10.195729 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 11:46:10.199189 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7606 11:46:10.202656 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
7607 11:46:10.209292 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7608 11:46:10.212468 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7609 11:46:10.215874 1 4 20 | B1->B0 | 2f2e 3434 | 1 1 | (0 0) (1 1)
7610 11:46:10.222063 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 11:46:10.225629 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 11:46:10.228941 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 11:46:10.235336 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 11:46:10.238885 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7615 11:46:10.242024 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7616 11:46:10.248855 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
7617 11:46:10.252459 1 5 20 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
7618 11:46:10.255596 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 11:46:10.258756 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 11:46:10.265810 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 11:46:10.269195 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 11:46:10.272065 1 6 8 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
7623 11:46:10.279116 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7624 11:46:10.281906 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7625 11:46:10.285356 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7626 11:46:10.291767 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 11:46:10.295066 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 11:46:10.298300 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 11:46:10.304916 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 11:46:10.308678 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 11:46:10.311821 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7632 11:46:10.318467 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7633 11:46:10.321978 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7634 11:46:10.325256 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 11:46:10.331443 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 11:46:10.335055 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 11:46:10.338422 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 11:46:10.345300 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 11:46:10.348586 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 11:46:10.352058 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 11:46:10.358539 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 11:46:10.361782 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 11:46:10.365153 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 11:46:10.371844 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 11:46:10.374846 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 11:46:10.378646 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7647 11:46:10.385550 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7648 11:46:10.388638 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7649 11:46:10.391816 Total UI for P1: 0, mck2ui 16
7650 11:46:10.395082 best dqsien dly found for B0: ( 1, 9, 10)
7651 11:46:10.398294 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7652 11:46:10.401710 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 11:46:10.405350 Total UI for P1: 0, mck2ui 16
7654 11:46:10.408310 best dqsien dly found for B1: ( 1, 9, 20)
7655 11:46:10.411820 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7656 11:46:10.418136 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7657 11:46:10.418784
7658 11:46:10.421711 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7659 11:46:10.424736 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7660 11:46:10.427971 [Gating] SW calibration Done
7661 11:46:10.428447 ==
7662 11:46:10.431252 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 11:46:10.434798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 11:46:10.435405 ==
7665 11:46:10.438266 RX Vref Scan: 0
7666 11:46:10.438889
7667 11:46:10.439416 RX Vref 0 -> 0, step: 1
7668 11:46:10.439789
7669 11:46:10.441307 RX Delay 0 -> 252, step: 8
7670 11:46:10.444992 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7671 11:46:10.448199 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7672 11:46:10.454673 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7673 11:46:10.458060 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7674 11:46:10.461291 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7675 11:46:10.464845 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7676 11:46:10.468516 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7677 11:46:10.474753 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7678 11:46:10.478253 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7679 11:46:10.481433 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7680 11:46:10.484955 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7681 11:46:10.488083 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7682 11:46:10.494812 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7683 11:46:10.497762 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7684 11:46:10.501530 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7685 11:46:10.504507 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7686 11:46:10.504982 ==
7687 11:46:10.507733 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 11:46:10.514770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 11:46:10.515320 ==
7690 11:46:10.515695 DQS Delay:
7691 11:46:10.516038 DQS0 = 0, DQS1 = 0
7692 11:46:10.517791 DQM Delay:
7693 11:46:10.518259 DQM0 = 138, DQM1 = 127
7694 11:46:10.521166 DQ Delay:
7695 11:46:10.524554 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7696 11:46:10.527958 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7697 11:46:10.531033 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7698 11:46:10.534535 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7699 11:46:10.535009
7700 11:46:10.535531
7701 11:46:10.535953 ==
7702 11:46:10.537840 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 11:46:10.541322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 11:46:10.544678 ==
7705 11:46:10.545146
7706 11:46:10.545516
7707 11:46:10.545861 TX Vref Scan disable
7708 11:46:10.547750 == TX Byte 0 ==
7709 11:46:10.551353 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7710 11:46:10.554069 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7711 11:46:10.557606 == TX Byte 1 ==
7712 11:46:10.561101 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7713 11:46:10.564075 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7714 11:46:10.564549 ==
7715 11:46:10.567349 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 11:46:10.574210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 11:46:10.574796 ==
7718 11:46:10.585249
7719 11:46:10.588980 TX Vref early break, caculate TX vref
7720 11:46:10.592198 TX Vref=16, minBit 12, minWin=22, winSum=378
7721 11:46:10.595434 TX Vref=18, minBit 6, minWin=23, winSum=389
7722 11:46:10.598588 TX Vref=20, minBit 12, minWin=23, winSum=396
7723 11:46:10.602112 TX Vref=22, minBit 1, minWin=25, winSum=411
7724 11:46:10.605248 TX Vref=24, minBit 6, minWin=25, winSum=420
7725 11:46:10.611917 TX Vref=26, minBit 12, minWin=25, winSum=423
7726 11:46:10.614937 TX Vref=28, minBit 0, minWin=25, winSum=431
7727 11:46:10.618235 TX Vref=30, minBit 0, minWin=25, winSum=418
7728 11:46:10.621880 TX Vref=32, minBit 2, minWin=24, winSum=407
7729 11:46:10.628442 [TxChooseVref] Worse bit 0, Min win 25, Win sum 431, Final Vref 28
7730 11:46:10.628990
7731 11:46:10.631813 Final TX Range 0 Vref 28
7732 11:46:10.632413
7733 11:46:10.632792 ==
7734 11:46:10.635249 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 11:46:10.638697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 11:46:10.639171 ==
7737 11:46:10.639541
7738 11:46:10.639886
7739 11:46:10.641677 TX Vref Scan disable
7740 11:46:10.645027 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7741 11:46:10.648456 == TX Byte 0 ==
7742 11:46:10.651854 u2DelayCellOfst[0]=13 cells (4 PI)
7743 11:46:10.655668 u2DelayCellOfst[1]=17 cells (5 PI)
7744 11:46:10.658295 u2DelayCellOfst[2]=10 cells (3 PI)
7745 11:46:10.661582 u2DelayCellOfst[3]=10 cells (3 PI)
7746 11:46:10.665200 u2DelayCellOfst[4]=10 cells (3 PI)
7747 11:46:10.665671 u2DelayCellOfst[5]=0 cells (0 PI)
7748 11:46:10.668455 u2DelayCellOfst[6]=17 cells (5 PI)
7749 11:46:10.672091 u2DelayCellOfst[7]=13 cells (4 PI)
7750 11:46:10.678679 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7751 11:46:10.682021 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7752 11:46:10.682570 == TX Byte 1 ==
7753 11:46:10.685400 u2DelayCellOfst[8]=0 cells (0 PI)
7754 11:46:10.688691 u2DelayCellOfst[9]=0 cells (0 PI)
7755 11:46:10.691693 u2DelayCellOfst[10]=6 cells (2 PI)
7756 11:46:10.695003 u2DelayCellOfst[11]=3 cells (1 PI)
7757 11:46:10.698544 u2DelayCellOfst[12]=13 cells (4 PI)
7758 11:46:10.701968 u2DelayCellOfst[13]=10 cells (3 PI)
7759 11:46:10.705185 u2DelayCellOfst[14]=13 cells (4 PI)
7760 11:46:10.708652 u2DelayCellOfst[15]=10 cells (3 PI)
7761 11:46:10.711803 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7762 11:46:10.715304 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7763 11:46:10.718296 DramC Write-DBI on
7764 11:46:10.718912 ==
7765 11:46:10.721773 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 11:46:10.724952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 11:46:10.725532 ==
7768 11:46:10.725908
7769 11:46:10.726251
7770 11:46:10.728859 TX Vref Scan disable
7771 11:46:10.731919 == TX Byte 0 ==
7772 11:46:10.735176 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7773 11:46:10.738208 == TX Byte 1 ==
7774 11:46:10.741824 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7775 11:46:10.742443 DramC Write-DBI off
7776 11:46:10.742831
7777 11:46:10.744976 [DATLAT]
7778 11:46:10.745449 Freq=1600, CH0 RK0
7779 11:46:10.745823
7780 11:46:10.748006 DATLAT Default: 0xf
7781 11:46:10.748508 0, 0xFFFF, sum = 0
7782 11:46:10.751506 1, 0xFFFF, sum = 0
7783 11:46:10.751984 2, 0xFFFF, sum = 0
7784 11:46:10.754669 3, 0xFFFF, sum = 0
7785 11:46:10.755203 4, 0xFFFF, sum = 0
7786 11:46:10.758142 5, 0xFFFF, sum = 0
7787 11:46:10.758791 6, 0xFFFF, sum = 0
7788 11:46:10.761386 7, 0xFFFF, sum = 0
7789 11:46:10.761891 8, 0xFFFF, sum = 0
7790 11:46:10.764948 9, 0xFFFF, sum = 0
7791 11:46:10.767927 10, 0xFFFF, sum = 0
7792 11:46:10.768416 11, 0xFFFF, sum = 0
7793 11:46:10.771203 12, 0xFFFF, sum = 0
7794 11:46:10.771688 13, 0xFFFF, sum = 0
7795 11:46:10.774956 14, 0x0, sum = 1
7796 11:46:10.775441 15, 0x0, sum = 2
7797 11:46:10.778484 16, 0x0, sum = 3
7798 11:46:10.779188 17, 0x0, sum = 4
7799 11:46:10.779588 best_step = 15
7800 11:46:10.781116
7801 11:46:10.781593 ==
7802 11:46:10.785389 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 11:46:10.788550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 11:46:10.789153 ==
7805 11:46:10.789537 RX Vref Scan: 1
7806 11:46:10.789890
7807 11:46:10.791792 Set Vref Range= 24 -> 127
7808 11:46:10.792386
7809 11:46:10.794756 RX Vref 24 -> 127, step: 1
7810 11:46:10.795363
7811 11:46:10.798487 RX Delay 19 -> 252, step: 4
7812 11:46:10.799072
7813 11:46:10.801516 Set Vref, RX VrefLevel [Byte0]: 24
7814 11:46:10.805371 [Byte1]: 24
7815 11:46:10.805961
7816 11:46:10.807845 Set Vref, RX VrefLevel [Byte0]: 25
7817 11:46:10.811377 [Byte1]: 25
7818 11:46:10.811858
7819 11:46:10.814527 Set Vref, RX VrefLevel [Byte0]: 26
7820 11:46:10.817978 [Byte1]: 26
7821 11:46:10.821085
7822 11:46:10.821565 Set Vref, RX VrefLevel [Byte0]: 27
7823 11:46:10.825223 [Byte1]: 27
7824 11:46:10.828597
7825 11:46:10.829074 Set Vref, RX VrefLevel [Byte0]: 28
7826 11:46:10.832198 [Byte1]: 28
7827 11:46:10.836488
7828 11:46:10.837044 Set Vref, RX VrefLevel [Byte0]: 29
7829 11:46:10.840201 [Byte1]: 29
7830 11:46:10.844007
7831 11:46:10.844480 Set Vref, RX VrefLevel [Byte0]: 30
7832 11:46:10.847276 [Byte1]: 30
7833 11:46:10.851802
7834 11:46:10.852385 Set Vref, RX VrefLevel [Byte0]: 31
7835 11:46:10.855075 [Byte1]: 31
7836 11:46:10.859388
7837 11:46:10.859876 Set Vref, RX VrefLevel [Byte0]: 32
7838 11:46:10.862654 [Byte1]: 32
7839 11:46:10.867159
7840 11:46:10.867694 Set Vref, RX VrefLevel [Byte0]: 33
7841 11:46:10.869903 [Byte1]: 33
7842 11:46:10.874580
7843 11:46:10.875049 Set Vref, RX VrefLevel [Byte0]: 34
7844 11:46:10.877928 [Byte1]: 34
7845 11:46:10.881856
7846 11:46:10.882324 Set Vref, RX VrefLevel [Byte0]: 35
7847 11:46:10.885725 [Byte1]: 35
7848 11:46:10.889782
7849 11:46:10.890331 Set Vref, RX VrefLevel [Byte0]: 36
7850 11:46:10.892674 [Byte1]: 36
7851 11:46:10.897301
7852 11:46:10.897767 Set Vref, RX VrefLevel [Byte0]: 37
7853 11:46:10.900440 [Byte1]: 37
7854 11:46:10.905229
7855 11:46:10.905809 Set Vref, RX VrefLevel [Byte0]: 38
7856 11:46:10.907774 [Byte1]: 38
7857 11:46:10.912201
7858 11:46:10.912675 Set Vref, RX VrefLevel [Byte0]: 39
7859 11:46:10.915800 [Byte1]: 39
7860 11:46:10.919996
7861 11:46:10.920567 Set Vref, RX VrefLevel [Byte0]: 40
7862 11:46:10.922848 [Byte1]: 40
7863 11:46:10.927754
7864 11:46:10.928327 Set Vref, RX VrefLevel [Byte0]: 41
7865 11:46:10.930562 [Byte1]: 41
7866 11:46:10.935271
7867 11:46:10.935853 Set Vref, RX VrefLevel [Byte0]: 42
7868 11:46:10.938160 [Byte1]: 42
7869 11:46:10.942744
7870 11:46:10.943294 Set Vref, RX VrefLevel [Byte0]: 43
7871 11:46:10.945904 [Byte1]: 43
7872 11:46:10.950125
7873 11:46:10.950704 Set Vref, RX VrefLevel [Byte0]: 44
7874 11:46:10.953702 [Byte1]: 44
7875 11:46:10.958050
7876 11:46:10.958645 Set Vref, RX VrefLevel [Byte0]: 45
7877 11:46:10.960885 [Byte1]: 45
7878 11:46:10.965109
7879 11:46:10.965578 Set Vref, RX VrefLevel [Byte0]: 46
7880 11:46:10.968613 [Byte1]: 46
7881 11:46:10.972938
7882 11:46:10.973490 Set Vref, RX VrefLevel [Byte0]: 47
7883 11:46:10.976220 [Byte1]: 47
7884 11:46:10.980757
7885 11:46:10.981297 Set Vref, RX VrefLevel [Byte0]: 48
7886 11:46:10.983928 [Byte1]: 48
7887 11:46:10.988250
7888 11:46:10.988811 Set Vref, RX VrefLevel [Byte0]: 49
7889 11:46:10.991032 [Byte1]: 49
7890 11:46:10.995221
7891 11:46:10.995809 Set Vref, RX VrefLevel [Byte0]: 50
7892 11:46:10.999121 [Byte1]: 50
7893 11:46:11.002931
7894 11:46:11.003557 Set Vref, RX VrefLevel [Byte0]: 51
7895 11:46:11.006557 [Byte1]: 51
7896 11:46:11.010928
7897 11:46:11.011489 Set Vref, RX VrefLevel [Byte0]: 52
7898 11:46:11.014205 [Byte1]: 52
7899 11:46:11.018296
7900 11:46:11.018833 Set Vref, RX VrefLevel [Byte0]: 53
7901 11:46:11.021789 [Byte1]: 53
7902 11:46:11.026070
7903 11:46:11.026568 Set Vref, RX VrefLevel [Byte0]: 54
7904 11:46:11.029231 [Byte1]: 54
7905 11:46:11.033511
7906 11:46:11.034056 Set Vref, RX VrefLevel [Byte0]: 55
7907 11:46:11.037206 [Byte1]: 55
7908 11:46:11.041483
7909 11:46:11.042056 Set Vref, RX VrefLevel [Byte0]: 56
7910 11:46:11.044044 [Byte1]: 56
7911 11:46:11.048452
7912 11:46:11.049014 Set Vref, RX VrefLevel [Byte0]: 57
7913 11:46:11.051883 [Byte1]: 57
7914 11:46:11.056220
7915 11:46:11.056793 Set Vref, RX VrefLevel [Byte0]: 58
7916 11:46:11.059396 [Byte1]: 58
7917 11:46:11.063475
7918 11:46:11.063964 Set Vref, RX VrefLevel [Byte0]: 59
7919 11:46:11.066982 [Byte1]: 59
7920 11:46:11.071556
7921 11:46:11.072096 Set Vref, RX VrefLevel [Byte0]: 60
7922 11:46:11.074849 [Byte1]: 60
7923 11:46:11.079304
7924 11:46:11.079874 Set Vref, RX VrefLevel [Byte0]: 61
7925 11:46:11.081920 [Byte1]: 61
7926 11:46:11.086994
7927 11:46:11.087466 Set Vref, RX VrefLevel [Byte0]: 62
7928 11:46:11.089999 [Byte1]: 62
7929 11:46:11.094069
7930 11:46:11.094574 Set Vref, RX VrefLevel [Byte0]: 63
7931 11:46:11.097676 [Byte1]: 63
7932 11:46:11.101750
7933 11:46:11.102328 Set Vref, RX VrefLevel [Byte0]: 64
7934 11:46:11.104999 [Byte1]: 64
7935 11:46:11.109128
7936 11:46:11.109700 Set Vref, RX VrefLevel [Byte0]: 65
7937 11:46:11.112183 [Byte1]: 65
7938 11:46:11.116605
7939 11:46:11.117137 Set Vref, RX VrefLevel [Byte0]: 66
7940 11:46:11.120136 [Byte1]: 66
7941 11:46:11.124298
7942 11:46:11.124870 Set Vref, RX VrefLevel [Byte0]: 67
7943 11:46:11.127809 [Byte1]: 67
7944 11:46:11.131669
7945 11:46:11.132139 Set Vref, RX VrefLevel [Byte0]: 68
7946 11:46:11.135428 [Byte1]: 68
7947 11:46:11.139401
7948 11:46:11.139972 Set Vref, RX VrefLevel [Byte0]: 69
7949 11:46:11.142543 [Byte1]: 69
7950 11:46:11.147073
7951 11:46:11.147635 Set Vref, RX VrefLevel [Byte0]: 70
7952 11:46:11.150295 [Byte1]: 70
7953 11:46:11.154420
7954 11:46:11.155088 Set Vref, RX VrefLevel [Byte0]: 71
7955 11:46:11.157600 [Byte1]: 71
7956 11:46:11.161842
7957 11:46:11.162437 Set Vref, RX VrefLevel [Byte0]: 72
7958 11:46:11.165022 [Byte1]: 72
7959 11:46:11.170239
7960 11:46:11.170854 Set Vref, RX VrefLevel [Byte0]: 73
7961 11:46:11.173036 [Byte1]: 73
7962 11:46:11.177058
7963 11:46:11.177540 Set Vref, RX VrefLevel [Byte0]: 74
7964 11:46:11.180524 [Byte1]: 74
7965 11:46:11.184469
7966 11:46:11.185096 Set Vref, RX VrefLevel [Byte0]: 75
7967 11:46:11.188252 [Byte1]: 75
7968 11:46:11.192449
7969 11:46:11.192899 Set Vref, RX VrefLevel [Byte0]: 76
7970 11:46:11.195568 [Byte1]: 76
7971 11:46:11.199730
7972 11:46:11.200198 Set Vref, RX VrefLevel [Byte0]: 77
7973 11:46:11.203090 [Byte1]: 77
7974 11:46:11.207755
7975 11:46:11.208511 Set Vref, RX VrefLevel [Byte0]: 78
7976 11:46:11.210906 [Byte1]: 78
7977 11:46:11.215145
7978 11:46:11.215615 Set Vref, RX VrefLevel [Byte0]: 79
7979 11:46:11.218632 [Byte1]: 79
7980 11:46:11.222434
7981 11:46:11.222885 Set Vref, RX VrefLevel [Byte0]: 80
7982 11:46:11.225963 [Byte1]: 80
7983 11:46:11.230597
7984 11:46:11.231113 Final RX Vref Byte 0 = 61 to rank0
7985 11:46:11.233857 Final RX Vref Byte 1 = 63 to rank0
7986 11:46:11.237507 Final RX Vref Byte 0 = 61 to rank1
7987 11:46:11.240331 Final RX Vref Byte 1 = 63 to rank1==
7988 11:46:11.243545 Dram Type= 6, Freq= 0, CH_0, rank 0
7989 11:46:11.250531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 11:46:11.251109 ==
7991 11:46:11.251639 DQS Delay:
7992 11:46:11.252179 DQS0 = 0, DQS1 = 0
7993 11:46:11.253639 DQM Delay:
7994 11:46:11.254107 DQM0 = 136, DQM1 = 125
7995 11:46:11.256946 DQ Delay:
7996 11:46:11.260137 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7997 11:46:11.263299 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =144
7998 11:46:11.266855 DQ8 =116, DQ9 =114, DQ10 =126, DQ11 =118
7999 11:46:11.270234 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
8000 11:46:11.270838
8001 11:46:11.271214
8002 11:46:11.271559
8003 11:46:11.273227 [DramC_TX_OE_Calibration] TA2
8004 11:46:11.276833 Original DQ_B0 (3 6) =30, OEN = 27
8005 11:46:11.279948 Original DQ_B1 (3 6) =30, OEN = 27
8006 11:46:11.283520 24, 0x0, End_B0=24 End_B1=24
8007 11:46:11.283999 25, 0x0, End_B0=25 End_B1=25
8008 11:46:11.286802 26, 0x0, End_B0=26 End_B1=26
8009 11:46:11.290240 27, 0x0, End_B0=27 End_B1=27
8010 11:46:11.293691 28, 0x0, End_B0=28 End_B1=28
8011 11:46:11.294260 29, 0x0, End_B0=29 End_B1=29
8012 11:46:11.296672 30, 0x0, End_B0=30 End_B1=30
8013 11:46:11.300008 31, 0x4141, End_B0=30 End_B1=30
8014 11:46:11.303599 Byte0 end_step=30 best_step=27
8015 11:46:11.306471 Byte1 end_step=30 best_step=27
8016 11:46:11.310001 Byte0 TX OE(2T, 0.5T) = (3, 3)
8017 11:46:11.310791 Byte1 TX OE(2T, 0.5T) = (3, 3)
8018 11:46:11.313265
8019 11:46:11.313886
8020 11:46:11.319607 [DQSOSCAuto] RK0, (LSB)MR18= 0x211f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
8021 11:46:11.323331 CH0 RK0: MR19=303, MR18=211F
8022 11:46:11.329654 CH0_RK0: MR19=0x303, MR18=0x211F, DQSOSC=393, MR23=63, INC=23, DEC=15
8023 11:46:11.330132
8024 11:46:11.332917 ----->DramcWriteLeveling(PI) begin...
8025 11:46:11.333396 ==
8026 11:46:11.336597 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 11:46:11.339989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 11:46:11.340468 ==
8029 11:46:11.343006 Write leveling (Byte 0): 38 => 38
8030 11:46:11.346857 Write leveling (Byte 1): 28 => 28
8031 11:46:11.349730 DramcWriteLeveling(PI) end<-----
8032 11:46:11.350203
8033 11:46:11.350626 ==
8034 11:46:11.353304 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 11:46:11.356828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 11:46:11.357394 ==
8037 11:46:11.359739 [Gating] SW mode calibration
8038 11:46:11.366688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8039 11:46:11.373278 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8040 11:46:11.376641 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 11:46:11.379870 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 11:46:11.386991 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 11:46:11.390314 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8044 11:46:11.393014 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 11:46:11.400005 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 11:46:11.403123 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 11:46:11.406451 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 11:46:11.413304 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 11:46:11.416297 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 11:46:11.419533 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8051 11:46:11.426358 1 5 12 | B1->B0 | 3333 2828 | 1 0 | (1 0) (1 0)
8052 11:46:11.429872 1 5 16 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8053 11:46:11.433010 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 11:46:11.440010 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 11:46:11.443043 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 11:46:11.446315 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 11:46:11.452820 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 11:46:11.456063 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8059 11:46:11.459594 1 6 12 | B1->B0 | 2d2d 4444 | 1 0 | (0 0) (0 0)
8060 11:46:11.466623 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 11:46:11.469382 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 11:46:11.472840 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 11:46:11.479445 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 11:46:11.482506 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 11:46:11.486179 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 11:46:11.489514 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 11:46:11.495859 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8068 11:46:11.499405 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8069 11:46:11.502569 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 11:46:11.509314 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 11:46:11.512597 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 11:46:11.516554 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 11:46:11.522709 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 11:46:11.525702 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 11:46:11.529269 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 11:46:11.535825 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 11:46:11.539113 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 11:46:11.542521 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 11:46:11.549307 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 11:46:11.552848 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 11:46:11.555870 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 11:46:11.562658 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 11:46:11.566095 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8084 11:46:11.569186 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8085 11:46:11.572894 Total UI for P1: 0, mck2ui 16
8086 11:46:11.575770 best dqsien dly found for B0: ( 1, 9, 12)
8087 11:46:11.582453 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 11:46:11.583033 Total UI for P1: 0, mck2ui 16
8089 11:46:11.585935 best dqsien dly found for B1: ( 1, 9, 14)
8090 11:46:11.592977 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8091 11:46:11.595770 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8092 11:46:11.596242
8093 11:46:11.599105 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8094 11:46:11.602039 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8095 11:46:11.605939 [Gating] SW calibration Done
8096 11:46:11.606566 ==
8097 11:46:11.608727 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 11:46:11.611991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 11:46:11.612466 ==
8100 11:46:11.615389 RX Vref Scan: 0
8101 11:46:11.615876
8102 11:46:11.616276 RX Vref 0 -> 0, step: 1
8103 11:46:11.616638
8104 11:46:11.618974 RX Delay 0 -> 252, step: 8
8105 11:46:11.622182 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8106 11:46:11.628971 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8107 11:46:11.632520 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8108 11:46:11.635538 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8109 11:46:11.638952 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8110 11:46:11.642230 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8111 11:46:11.649000 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8112 11:46:11.652008 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8113 11:46:11.655379 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8114 11:46:11.658540 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8115 11:46:11.662431 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8116 11:46:11.668605 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8117 11:46:11.672668 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8118 11:46:11.675749 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8119 11:46:11.678931 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8120 11:46:11.682009 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8121 11:46:11.685458 ==
8122 11:46:11.685936 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 11:46:11.692120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 11:46:11.692665 ==
8125 11:46:11.693047 DQS Delay:
8126 11:46:11.695254 DQS0 = 0, DQS1 = 0
8127 11:46:11.695734 DQM Delay:
8128 11:46:11.698663 DQM0 = 136, DQM1 = 126
8129 11:46:11.699142 DQ Delay:
8130 11:46:11.702076 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8131 11:46:11.705048 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8132 11:46:11.708467 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8133 11:46:11.711699 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8134 11:46:11.712268
8135 11:46:11.712645
8136 11:46:11.712994 ==
8137 11:46:11.715101 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 11:46:11.721991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 11:46:11.722584 ==
8140 11:46:11.722960
8141 11:46:11.723303
8142 11:46:11.723630 TX Vref Scan disable
8143 11:46:11.725237 == TX Byte 0 ==
8144 11:46:11.728441 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8145 11:46:11.735071 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8146 11:46:11.735616 == TX Byte 1 ==
8147 11:46:11.738461 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8148 11:46:11.745124 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8149 11:46:11.745596 ==
8150 11:46:11.748270 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 11:46:11.751906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 11:46:11.752420 ==
8153 11:46:11.765489
8154 11:46:11.768900 TX Vref early break, caculate TX vref
8155 11:46:11.772303 TX Vref=16, minBit 0, minWin=23, winSum=391
8156 11:46:11.775250 TX Vref=18, minBit 2, minWin=24, winSum=403
8157 11:46:11.778353 TX Vref=20, minBit 0, minWin=25, winSum=409
8158 11:46:11.782131 TX Vref=22, minBit 0, minWin=25, winSum=415
8159 11:46:11.785075 TX Vref=24, minBit 0, minWin=25, winSum=426
8160 11:46:11.791720 TX Vref=26, minBit 0, minWin=25, winSum=433
8161 11:46:11.795344 TX Vref=28, minBit 0, minWin=26, winSum=430
8162 11:46:11.798471 TX Vref=30, minBit 0, minWin=26, winSum=423
8163 11:46:11.801847 TX Vref=32, minBit 0, minWin=25, winSum=414
8164 11:46:11.805087 TX Vref=34, minBit 4, minWin=24, winSum=405
8165 11:46:11.811664 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8166 11:46:11.812192
8167 11:46:11.815284 Final TX Range 0 Vref 28
8168 11:46:11.815976
8169 11:46:11.816417 ==
8170 11:46:11.818331 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 11:46:11.821614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 11:46:11.822187 ==
8173 11:46:11.822633
8174 11:46:11.822991
8175 11:46:11.824978 TX Vref Scan disable
8176 11:46:11.831723 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8177 11:46:11.832265 == TX Byte 0 ==
8178 11:46:11.835185 u2DelayCellOfst[0]=13 cells (4 PI)
8179 11:46:11.838512 u2DelayCellOfst[1]=20 cells (6 PI)
8180 11:46:11.841594 u2DelayCellOfst[2]=13 cells (4 PI)
8181 11:46:11.844870 u2DelayCellOfst[3]=13 cells (4 PI)
8182 11:46:11.848433 u2DelayCellOfst[4]=10 cells (3 PI)
8183 11:46:11.851449 u2DelayCellOfst[5]=0 cells (0 PI)
8184 11:46:11.854793 u2DelayCellOfst[6]=20 cells (6 PI)
8185 11:46:11.858456 u2DelayCellOfst[7]=20 cells (6 PI)
8186 11:46:11.861638 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8187 11:46:11.864943 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8188 11:46:11.868025 == TX Byte 1 ==
8189 11:46:11.868625 u2DelayCellOfst[8]=0 cells (0 PI)
8190 11:46:11.871474 u2DelayCellOfst[9]=3 cells (1 PI)
8191 11:46:11.874811 u2DelayCellOfst[10]=10 cells (3 PI)
8192 11:46:11.878004 u2DelayCellOfst[11]=3 cells (1 PI)
8193 11:46:11.881470 u2DelayCellOfst[12]=13 cells (4 PI)
8194 11:46:11.884819 u2DelayCellOfst[13]=10 cells (3 PI)
8195 11:46:11.887842 u2DelayCellOfst[14]=13 cells (4 PI)
8196 11:46:11.891904 u2DelayCellOfst[15]=10 cells (3 PI)
8197 11:46:11.895036 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8198 11:46:11.901716 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8199 11:46:11.902315 DramC Write-DBI on
8200 11:46:11.902759 ==
8201 11:46:11.904766 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 11:46:11.911335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 11:46:11.911922 ==
8204 11:46:11.912420
8205 11:46:11.912881
8206 11:46:11.913370 TX Vref Scan disable
8207 11:46:11.915502 == TX Byte 0 ==
8208 11:46:11.918659 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8209 11:46:11.921769 == TX Byte 1 ==
8210 11:46:11.925236 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8211 11:46:11.928306 DramC Write-DBI off
8212 11:46:11.928789
8213 11:46:11.929265 [DATLAT]
8214 11:46:11.929765 Freq=1600, CH0 RK1
8215 11:46:11.930192
8216 11:46:11.931850 DATLAT Default: 0xf
8217 11:46:11.932426 0, 0xFFFF, sum = 0
8218 11:46:11.935063 1, 0xFFFF, sum = 0
8219 11:46:11.938560 2, 0xFFFF, sum = 0
8220 11:46:11.939053 3, 0xFFFF, sum = 0
8221 11:46:11.942176 4, 0xFFFF, sum = 0
8222 11:46:11.942810 5, 0xFFFF, sum = 0
8223 11:46:11.945466 6, 0xFFFF, sum = 0
8224 11:46:11.946065 7, 0xFFFF, sum = 0
8225 11:46:11.948183 8, 0xFFFF, sum = 0
8226 11:46:11.948679 9, 0xFFFF, sum = 0
8227 11:46:11.951544 10, 0xFFFF, sum = 0
8228 11:46:11.952039 11, 0xFFFF, sum = 0
8229 11:46:11.955089 12, 0xFFFF, sum = 0
8230 11:46:11.955580 13, 0xFFFF, sum = 0
8231 11:46:11.958426 14, 0x0, sum = 1
8232 11:46:11.958996 15, 0x0, sum = 2
8233 11:46:11.961574 16, 0x0, sum = 3
8234 11:46:11.962069 17, 0x0, sum = 4
8235 11:46:11.965083 best_step = 15
8236 11:46:11.965580
8237 11:46:11.966058 ==
8238 11:46:11.968129 Dram Type= 6, Freq= 0, CH_0, rank 1
8239 11:46:11.971577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8240 11:46:11.972069 ==
8241 11:46:11.972552 RX Vref Scan: 0
8242 11:46:11.975089
8243 11:46:11.975570 RX Vref 0 -> 0, step: 1
8244 11:46:11.976051
8245 11:46:11.978242 RX Delay 11 -> 252, step: 4
8246 11:46:11.981558 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8247 11:46:11.988527 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8248 11:46:11.991519 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8249 11:46:11.995059 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8250 11:46:11.998364 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8251 11:46:12.001923 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8252 11:46:12.008284 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8253 11:46:12.011898 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8254 11:46:12.014817 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8255 11:46:12.018083 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8256 11:46:12.021717 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8257 11:46:12.028411 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8258 11:46:12.031692 iDelay=191, Bit 12, Center 128 (79 ~ 178) 100
8259 11:46:12.035097 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8260 11:46:12.038656 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8261 11:46:12.041322 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8262 11:46:12.044680 ==
8263 11:46:12.045173 Dram Type= 6, Freq= 0, CH_0, rank 1
8264 11:46:12.051362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 11:46:12.051923 ==
8266 11:46:12.052453 DQS Delay:
8267 11:46:12.054732 DQS0 = 0, DQS1 = 0
8268 11:46:12.055218 DQM Delay:
8269 11:46:12.058006 DQM0 = 132, DQM1 = 123
8270 11:46:12.058528 DQ Delay:
8271 11:46:12.061564 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8272 11:46:12.064748 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8273 11:46:12.067723 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8274 11:46:12.071670 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8275 11:46:12.072202
8276 11:46:12.072698
8277 11:46:12.073157
8278 11:46:12.074881 [DramC_TX_OE_Calibration] TA2
8279 11:46:12.077909 Original DQ_B0 (3 6) =30, OEN = 27
8280 11:46:12.080953 Original DQ_B1 (3 6) =30, OEN = 27
8281 11:46:12.084625 24, 0x0, End_B0=24 End_B1=24
8282 11:46:12.087774 25, 0x0, End_B0=25 End_B1=25
8283 11:46:12.088255 26, 0x0, End_B0=26 End_B1=26
8284 11:46:12.091208 27, 0x0, End_B0=27 End_B1=27
8285 11:46:12.094321 28, 0x0, End_B0=28 End_B1=28
8286 11:46:12.097812 29, 0x0, End_B0=29 End_B1=29
8287 11:46:12.098354 30, 0x0, End_B0=30 End_B1=30
8288 11:46:12.100945 31, 0x4141, End_B0=30 End_B1=30
8289 11:46:12.104474 Byte0 end_step=30 best_step=27
8290 11:46:12.107522 Byte1 end_step=30 best_step=27
8291 11:46:12.111594 Byte0 TX OE(2T, 0.5T) = (3, 3)
8292 11:46:12.114464 Byte1 TX OE(2T, 0.5T) = (3, 3)
8293 11:46:12.115033
8294 11:46:12.115422
8295 11:46:12.121403 [DQSOSCAuto] RK1, (LSB)MR18= 0x210d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8296 11:46:12.124417 CH0 RK1: MR19=303, MR18=210D
8297 11:46:12.130996 CH0_RK1: MR19=0x303, MR18=0x210D, DQSOSC=393, MR23=63, INC=23, DEC=15
8298 11:46:12.134568 [RxdqsGatingPostProcess] freq 1600
8299 11:46:12.137984 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8300 11:46:12.141470 best DQS0 dly(2T, 0.5T) = (1, 1)
8301 11:46:12.144187 best DQS1 dly(2T, 0.5T) = (1, 1)
8302 11:46:12.148179 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8303 11:46:12.151068 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8304 11:46:12.154298 best DQS0 dly(2T, 0.5T) = (1, 1)
8305 11:46:12.157656 best DQS1 dly(2T, 0.5T) = (1, 1)
8306 11:46:12.161013 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8307 11:46:12.164302 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8308 11:46:12.167279 Pre-setting of DQS Precalculation
8309 11:46:12.170731 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8310 11:46:12.171209 ==
8311 11:46:12.174413 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 11:46:12.180997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 11:46:12.181537 ==
8314 11:46:12.184237 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8315 11:46:12.187587 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8316 11:46:12.194234 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8317 11:46:12.200741 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8318 11:46:12.208620 [CA 0] Center 40 (11~70) winsize 60
8319 11:46:12.211764 [CA 1] Center 41 (11~71) winsize 61
8320 11:46:12.214783 [CA 2] Center 37 (8~67) winsize 60
8321 11:46:12.218460 [CA 3] Center 36 (6~66) winsize 61
8322 11:46:12.221551 [CA 4] Center 36 (7~66) winsize 60
8323 11:46:12.224921 [CA 5] Center 36 (6~66) winsize 61
8324 11:46:12.225498
8325 11:46:12.228154 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8326 11:46:12.228813
8327 11:46:12.231190 [CATrainingPosCal] consider 1 rank data
8328 11:46:12.234424 u2DelayCellTimex100 = 285/100 ps
8329 11:46:12.241326 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8330 11:46:12.244953 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8331 11:46:12.248193 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8332 11:46:12.251365 CA3 delay=36 (6~66),Diff = 0 PI (0 cell)
8333 11:46:12.254437 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8334 11:46:12.257550 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8335 11:46:12.258039
8336 11:46:12.261213 CA PerBit enable=1, Macro0, CA PI delay=36
8337 11:46:12.261787
8338 11:46:12.264242 [CBTSetCACLKResult] CA Dly = 36
8339 11:46:12.267711 CS Dly: 9 (0~40)
8340 11:46:12.271680 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8341 11:46:12.274722 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8342 11:46:12.275298 ==
8343 11:46:12.277537 Dram Type= 6, Freq= 0, CH_1, rank 1
8344 11:46:12.281494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 11:46:12.284263 ==
8346 11:46:12.287297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8347 11:46:12.291104 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8348 11:46:12.297389 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8349 11:46:12.304066 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8350 11:46:12.311817 [CA 0] Center 42 (13~72) winsize 60
8351 11:46:12.314715 [CA 1] Center 42 (12~72) winsize 61
8352 11:46:12.317854 [CA 2] Center 38 (9~68) winsize 60
8353 11:46:12.321315 [CA 3] Center 37 (8~67) winsize 60
8354 11:46:12.324897 [CA 4] Center 38 (9~68) winsize 60
8355 11:46:12.328222 [CA 5] Center 37 (8~67) winsize 60
8356 11:46:12.328796
8357 11:46:12.331024 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8358 11:46:12.331504
8359 11:46:12.334315 [CATrainingPosCal] consider 2 rank data
8360 11:46:12.337880 u2DelayCellTimex100 = 285/100 ps
8361 11:46:12.341033 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8362 11:46:12.347959 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8363 11:46:12.350905 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8364 11:46:12.354683 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8365 11:46:12.357643 CA4 delay=37 (9~66),Diff = 0 PI (0 cell)
8366 11:46:12.361222 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8367 11:46:12.361479
8368 11:46:12.364358 CA PerBit enable=1, Macro0, CA PI delay=37
8369 11:46:12.364596
8370 11:46:12.367507 [CBTSetCACLKResult] CA Dly = 37
8371 11:46:12.367699 CS Dly: 10 (0~42)
8372 11:46:12.373980 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8373 11:46:12.377433 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8374 11:46:12.377568
8375 11:46:12.381196 ----->DramcWriteLeveling(PI) begin...
8376 11:46:12.381523 ==
8377 11:46:12.384511 Dram Type= 6, Freq= 0, CH_1, rank 0
8378 11:46:12.387564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8379 11:46:12.390975 ==
8380 11:46:12.391294 Write leveling (Byte 0): 24 => 24
8381 11:46:12.394224 Write leveling (Byte 1): 28 => 28
8382 11:46:12.397526 DramcWriteLeveling(PI) end<-----
8383 11:46:12.397843
8384 11:46:12.398091 ==
8385 11:46:12.400922 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 11:46:12.407695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 11:46:12.408137 ==
8388 11:46:12.408432 [Gating] SW mode calibration
8389 11:46:12.417771 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8390 11:46:12.421129 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8391 11:46:12.424091 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 11:46:12.430907 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 11:46:12.434544 1 4 8 | B1->B0 | 2929 2f2f | 0 1 | (0 0) (1 1)
8394 11:46:12.437703 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 11:46:12.444729 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 11:46:12.448031 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 11:46:12.450937 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 11:46:12.458224 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 11:46:12.461100 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 11:46:12.464393 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8401 11:46:12.471298 1 5 8 | B1->B0 | 2d2d 2929 | 1 1 | (1 0) (1 0)
8402 11:46:12.474305 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8403 11:46:12.477753 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 11:46:12.484429 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 11:46:12.487374 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 11:46:12.491123 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 11:46:12.497852 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 11:46:12.500901 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8409 11:46:12.504547 1 6 8 | B1->B0 | 4040 4444 | 1 0 | (0 0) (0 0)
8410 11:46:12.510698 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 11:46:12.514186 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 11:46:12.517788 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 11:46:12.524174 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 11:46:12.527491 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 11:46:12.530574 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 11:46:12.537653 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8417 11:46:12.540895 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8418 11:46:12.544331 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8419 11:46:12.547401 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 11:46:12.554022 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 11:46:12.557305 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 11:46:12.560821 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 11:46:12.567176 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 11:46:12.571090 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 11:46:12.574137 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 11:46:12.580908 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 11:46:12.584363 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 11:46:12.587328 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 11:46:12.594513 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 11:46:12.597494 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 11:46:12.600485 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 11:46:12.607195 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8433 11:46:12.610878 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8434 11:46:12.613761 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8435 11:46:12.617036 Total UI for P1: 0, mck2ui 16
8436 11:46:12.620762 best dqsien dly found for B0: ( 1, 9, 6)
8437 11:46:12.627108 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 11:46:12.627584 Total UI for P1: 0, mck2ui 16
8439 11:46:12.633933 best dqsien dly found for B1: ( 1, 9, 10)
8440 11:46:12.637855 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8441 11:46:12.640612 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8442 11:46:12.641223
8443 11:46:12.643942 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8444 11:46:12.647055 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8445 11:46:12.650682 [Gating] SW calibration Done
8446 11:46:12.651151 ==
8447 11:46:12.654029 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 11:46:12.657157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 11:46:12.657738 ==
8450 11:46:12.660691 RX Vref Scan: 0
8451 11:46:12.661270
8452 11:46:12.661649 RX Vref 0 -> 0, step: 1
8453 11:46:12.661995
8454 11:46:12.663909 RX Delay 0 -> 252, step: 8
8455 11:46:12.666976 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8456 11:46:12.670435 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8457 11:46:12.676944 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8458 11:46:12.680264 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8459 11:46:12.683761 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8460 11:46:12.686855 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8461 11:46:12.690430 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8462 11:46:12.697184 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8463 11:46:12.700707 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8464 11:46:12.703640 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8465 11:46:12.707318 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8466 11:46:12.710217 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8467 11:46:12.716942 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8468 11:46:12.720393 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8469 11:46:12.723910 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8470 11:46:12.727119 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8471 11:46:12.727623 ==
8472 11:46:12.730499 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 11:46:12.736681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 11:46:12.737161 ==
8475 11:46:12.737540 DQS Delay:
8476 11:46:12.740191 DQS0 = 0, DQS1 = 0
8477 11:46:12.740662 DQM Delay:
8478 11:46:12.741039 DQM0 = 137, DQM1 = 130
8479 11:46:12.743273 DQ Delay:
8480 11:46:12.746535 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8481 11:46:12.749843 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8482 11:46:12.753497 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8483 11:46:12.756752 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8484 11:46:12.757231
8485 11:46:12.757603
8486 11:46:12.757952 ==
8487 11:46:12.760307 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 11:46:12.763317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 11:46:12.766654 ==
8490 11:46:12.767126
8491 11:46:12.767519
8492 11:46:12.767873 TX Vref Scan disable
8493 11:46:12.770008 == TX Byte 0 ==
8494 11:46:12.773106 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8495 11:46:12.776777 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8496 11:46:12.779875 == TX Byte 1 ==
8497 11:46:12.783961 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8498 11:46:12.786841 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8499 11:46:12.787320 ==
8500 11:46:12.790223 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 11:46:12.796966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 11:46:12.797542 ==
8503 11:46:12.808628
8504 11:46:12.811953 TX Vref early break, caculate TX vref
8505 11:46:12.815051 TX Vref=16, minBit 10, minWin=21, winSum=369
8506 11:46:12.818499 TX Vref=18, minBit 10, minWin=21, winSum=377
8507 11:46:12.821641 TX Vref=20, minBit 10, minWin=23, winSum=390
8508 11:46:12.824868 TX Vref=22, minBit 10, minWin=23, winSum=400
8509 11:46:12.831807 TX Vref=24, minBit 10, minWin=24, winSum=408
8510 11:46:12.835057 TX Vref=26, minBit 10, minWin=24, winSum=419
8511 11:46:12.838425 TX Vref=28, minBit 10, minWin=25, winSum=418
8512 11:46:12.841773 TX Vref=30, minBit 8, minWin=24, winSum=409
8513 11:46:12.845064 TX Vref=32, minBit 8, minWin=24, winSum=401
8514 11:46:12.848230 TX Vref=34, minBit 9, minWin=23, winSum=386
8515 11:46:12.855032 [TxChooseVref] Worse bit 10, Min win 25, Win sum 418, Final Vref 28
8516 11:46:12.855615
8517 11:46:12.858436 Final TX Range 0 Vref 28
8518 11:46:12.859099
8519 11:46:12.859693 ==
8520 11:46:12.861788 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 11:46:12.865368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 11:46:12.865938 ==
8523 11:46:12.866489
8524 11:46:12.867027
8525 11:46:12.868380 TX Vref Scan disable
8526 11:46:12.874962 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8527 11:46:12.875507 == TX Byte 0 ==
8528 11:46:12.878306 u2DelayCellOfst[0]=17 cells (5 PI)
8529 11:46:12.881912 u2DelayCellOfst[1]=10 cells (3 PI)
8530 11:46:12.885014 u2DelayCellOfst[2]=0 cells (0 PI)
8531 11:46:12.888528 u2DelayCellOfst[3]=3 cells (1 PI)
8532 11:46:12.891779 u2DelayCellOfst[4]=6 cells (2 PI)
8533 11:46:12.894956 u2DelayCellOfst[5]=17 cells (5 PI)
8534 11:46:12.898243 u2DelayCellOfst[6]=17 cells (5 PI)
8535 11:46:12.901742 u2DelayCellOfst[7]=6 cells (2 PI)
8536 11:46:12.904866 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8537 11:46:12.908495 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8538 11:46:12.911838 == TX Byte 1 ==
8539 11:46:12.914805 u2DelayCellOfst[8]=0 cells (0 PI)
8540 11:46:12.915278 u2DelayCellOfst[9]=0 cells (0 PI)
8541 11:46:12.918183 u2DelayCellOfst[10]=10 cells (3 PI)
8542 11:46:12.921589 u2DelayCellOfst[11]=0 cells (0 PI)
8543 11:46:12.924626 u2DelayCellOfst[12]=13 cells (4 PI)
8544 11:46:12.928843 u2DelayCellOfst[13]=17 cells (5 PI)
8545 11:46:12.931847 u2DelayCellOfst[14]=17 cells (5 PI)
8546 11:46:12.934780 u2DelayCellOfst[15]=13 cells (4 PI)
8547 11:46:12.937986 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8548 11:46:12.944856 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8549 11:46:12.945432 DramC Write-DBI on
8550 11:46:12.945807 ==
8551 11:46:12.947894 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 11:46:12.954701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 11:46:12.955235 ==
8554 11:46:12.955612
8555 11:46:12.955960
8556 11:46:12.956290 TX Vref Scan disable
8557 11:46:12.958223 == TX Byte 0 ==
8558 11:46:12.961552 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8559 11:46:12.964816 == TX Byte 1 ==
8560 11:46:12.968195 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8561 11:46:12.971535 DramC Write-DBI off
8562 11:46:12.972009
8563 11:46:12.972376 [DATLAT]
8564 11:46:12.972719 Freq=1600, CH1 RK0
8565 11:46:12.973141
8566 11:46:12.974707 DATLAT Default: 0xf
8567 11:46:12.975245 0, 0xFFFF, sum = 0
8568 11:46:12.978231 1, 0xFFFF, sum = 0
8569 11:46:12.981815 2, 0xFFFF, sum = 0
8570 11:46:12.982293 3, 0xFFFF, sum = 0
8571 11:46:12.985080 4, 0xFFFF, sum = 0
8572 11:46:12.985561 5, 0xFFFF, sum = 0
8573 11:46:12.988425 6, 0xFFFF, sum = 0
8574 11:46:12.989011 7, 0xFFFF, sum = 0
8575 11:46:12.991581 8, 0xFFFF, sum = 0
8576 11:46:12.992064 9, 0xFFFF, sum = 0
8577 11:46:12.995303 10, 0xFFFF, sum = 0
8578 11:46:12.995891 11, 0xFFFF, sum = 0
8579 11:46:12.998197 12, 0xFFFF, sum = 0
8580 11:46:12.998702 13, 0xFFFF, sum = 0
8581 11:46:13.001631 14, 0x0, sum = 1
8582 11:46:13.002220 15, 0x0, sum = 2
8583 11:46:13.005039 16, 0x0, sum = 3
8584 11:46:13.005631 17, 0x0, sum = 4
8585 11:46:13.008851 best_step = 15
8586 11:46:13.009429
8587 11:46:13.009809 ==
8588 11:46:13.011750 Dram Type= 6, Freq= 0, CH_1, rank 0
8589 11:46:13.015016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8590 11:46:13.015572 ==
8591 11:46:13.015953 RX Vref Scan: 1
8592 11:46:13.018307
8593 11:46:13.018807 Set Vref Range= 24 -> 127
8594 11:46:13.019189
8595 11:46:13.021560 RX Vref 24 -> 127, step: 1
8596 11:46:13.022040
8597 11:46:13.024969 RX Delay 19 -> 252, step: 4
8598 11:46:13.025448
8599 11:46:13.027970 Set Vref, RX VrefLevel [Byte0]: 24
8600 11:46:13.031689 [Byte1]: 24
8601 11:46:13.032271
8602 11:46:13.034887 Set Vref, RX VrefLevel [Byte0]: 25
8603 11:46:13.038093 [Byte1]: 25
8604 11:46:13.038630
8605 11:46:13.041770 Set Vref, RX VrefLevel [Byte0]: 26
8606 11:46:13.045283 [Byte1]: 26
8607 11:46:13.048944
8608 11:46:13.049563 Set Vref, RX VrefLevel [Byte0]: 27
8609 11:46:13.051909 [Byte1]: 27
8610 11:46:13.056549
8611 11:46:13.057244 Set Vref, RX VrefLevel [Byte0]: 28
8612 11:46:13.059565 [Byte1]: 28
8613 11:46:13.063741
8614 11:46:13.067063 Set Vref, RX VrefLevel [Byte0]: 29
8615 11:46:13.067558 [Byte1]: 29
8616 11:46:13.071135
8617 11:46:13.071605 Set Vref, RX VrefLevel [Byte0]: 30
8618 11:46:13.074478 [Byte1]: 30
8619 11:46:13.078895
8620 11:46:13.079464 Set Vref, RX VrefLevel [Byte0]: 31
8621 11:46:13.082027 [Byte1]: 31
8622 11:46:13.086491
8623 11:46:13.086958 Set Vref, RX VrefLevel [Byte0]: 32
8624 11:46:13.089899 [Byte1]: 32
8625 11:46:13.093940
8626 11:46:13.094428 Set Vref, RX VrefLevel [Byte0]: 33
8627 11:46:13.097511 [Byte1]: 33
8628 11:46:13.101489
8629 11:46:13.102002 Set Vref, RX VrefLevel [Byte0]: 34
8630 11:46:13.105257 [Byte1]: 34
8631 11:46:13.109311
8632 11:46:13.109953 Set Vref, RX VrefLevel [Byte0]: 35
8633 11:46:13.112448 [Byte1]: 35
8634 11:46:13.116947
8635 11:46:13.117521 Set Vref, RX VrefLevel [Byte0]: 36
8636 11:46:13.120030 [Byte1]: 36
8637 11:46:13.124222
8638 11:46:13.124692 Set Vref, RX VrefLevel [Byte0]: 37
8639 11:46:13.127814 [Byte1]: 37
8640 11:46:13.132090
8641 11:46:13.132655 Set Vref, RX VrefLevel [Byte0]: 38
8642 11:46:13.135420 [Byte1]: 38
8643 11:46:13.139842
8644 11:46:13.140412 Set Vref, RX VrefLevel [Byte0]: 39
8645 11:46:13.142848 [Byte1]: 39
8646 11:46:13.147185
8647 11:46:13.147755 Set Vref, RX VrefLevel [Byte0]: 40
8648 11:46:13.150142 [Byte1]: 40
8649 11:46:13.154902
8650 11:46:13.155466 Set Vref, RX VrefLevel [Byte0]: 41
8651 11:46:13.158054 [Byte1]: 41
8652 11:46:13.162338
8653 11:46:13.162964 Set Vref, RX VrefLevel [Byte0]: 42
8654 11:46:13.165582 [Byte1]: 42
8655 11:46:13.169976
8656 11:46:13.170470 Set Vref, RX VrefLevel [Byte0]: 43
8657 11:46:13.173277 [Byte1]: 43
8658 11:46:13.177466
8659 11:46:13.178030 Set Vref, RX VrefLevel [Byte0]: 44
8660 11:46:13.180606 [Byte1]: 44
8661 11:46:13.185024
8662 11:46:13.185607 Set Vref, RX VrefLevel [Byte0]: 45
8663 11:46:13.188357 [Byte1]: 45
8664 11:46:13.192353
8665 11:46:13.192915 Set Vref, RX VrefLevel [Byte0]: 46
8666 11:46:13.195660 [Byte1]: 46
8667 11:46:13.199815
8668 11:46:13.200386 Set Vref, RX VrefLevel [Byte0]: 47
8669 11:46:13.203231 [Byte1]: 47
8670 11:46:13.207715
8671 11:46:13.208292 Set Vref, RX VrefLevel [Byte0]: 48
8672 11:46:13.210927 [Byte1]: 48
8673 11:46:13.215288
8674 11:46:13.215871 Set Vref, RX VrefLevel [Byte0]: 49
8675 11:46:13.218363 [Byte1]: 49
8676 11:46:13.222748
8677 11:46:13.223238 Set Vref, RX VrefLevel [Byte0]: 50
8678 11:46:13.225926 [Byte1]: 50
8679 11:46:13.230775
8680 11:46:13.231345 Set Vref, RX VrefLevel [Byte0]: 51
8681 11:46:13.233526 [Byte1]: 51
8682 11:46:13.238136
8683 11:46:13.238749 Set Vref, RX VrefLevel [Byte0]: 52
8684 11:46:13.241392 [Byte1]: 52
8685 11:46:13.245567
8686 11:46:13.246102 Set Vref, RX VrefLevel [Byte0]: 53
8687 11:46:13.248764 [Byte1]: 53
8688 11:46:13.253075
8689 11:46:13.253545 Set Vref, RX VrefLevel [Byte0]: 54
8690 11:46:13.256391 [Byte1]: 54
8691 11:46:13.260853
8692 11:46:13.261424 Set Vref, RX VrefLevel [Byte0]: 55
8693 11:46:13.263788 [Byte1]: 55
8694 11:46:13.268276
8695 11:46:13.268842 Set Vref, RX VrefLevel [Byte0]: 56
8696 11:46:13.271494 [Byte1]: 56
8697 11:46:13.276031
8698 11:46:13.276570 Set Vref, RX VrefLevel [Byte0]: 57
8699 11:46:13.278844 [Byte1]: 57
8700 11:46:13.283089
8701 11:46:13.283651 Set Vref, RX VrefLevel [Byte0]: 58
8702 11:46:13.286483 [Byte1]: 58
8703 11:46:13.291011
8704 11:46:13.291479 Set Vref, RX VrefLevel [Byte0]: 59
8705 11:46:13.294480 [Byte1]: 59
8706 11:46:13.298465
8707 11:46:13.298938 Set Vref, RX VrefLevel [Byte0]: 60
8708 11:46:13.302004 [Byte1]: 60
8709 11:46:13.305988
8710 11:46:13.306494 Set Vref, RX VrefLevel [Byte0]: 61
8711 11:46:13.309391 [Byte1]: 61
8712 11:46:13.313727
8713 11:46:13.314265 Set Vref, RX VrefLevel [Byte0]: 62
8714 11:46:13.316912 [Byte1]: 62
8715 11:46:13.321575
8716 11:46:13.322144 Set Vref, RX VrefLevel [Byte0]: 63
8717 11:46:13.324488 [Byte1]: 63
8718 11:46:13.328869
8719 11:46:13.329485 Set Vref, RX VrefLevel [Byte0]: 64
8720 11:46:13.332009 [Byte1]: 64
8721 11:46:13.336678
8722 11:46:13.337216 Set Vref, RX VrefLevel [Byte0]: 65
8723 11:46:13.339498 [Byte1]: 65
8724 11:46:13.344325
8725 11:46:13.345049 Set Vref, RX VrefLevel [Byte0]: 66
8726 11:46:13.347387 [Byte1]: 66
8727 11:46:13.351681
8728 11:46:13.352277 Set Vref, RX VrefLevel [Byte0]: 67
8729 11:46:13.354963 [Byte1]: 67
8730 11:46:13.359291
8731 11:46:13.359896 Set Vref, RX VrefLevel [Byte0]: 68
8732 11:46:13.362259 [Byte1]: 68
8733 11:46:13.366895
8734 11:46:13.367388 Set Vref, RX VrefLevel [Byte0]: 69
8735 11:46:13.369779 [Byte1]: 69
8736 11:46:13.374229
8737 11:46:13.374746 Set Vref, RX VrefLevel [Byte0]: 70
8738 11:46:13.377572 [Byte1]: 70
8739 11:46:13.381582
8740 11:46:13.382062 Set Vref, RX VrefLevel [Byte0]: 71
8741 11:46:13.384767 [Byte1]: 71
8742 11:46:13.389373
8743 11:46:13.389850 Set Vref, RX VrefLevel [Byte0]: 72
8744 11:46:13.392842 [Byte1]: 72
8745 11:46:13.396892
8746 11:46:13.397368 Set Vref, RX VrefLevel [Byte0]: 73
8747 11:46:13.399980 [Byte1]: 73
8748 11:46:13.404199
8749 11:46:13.404679 Set Vref, RX VrefLevel [Byte0]: 74
8750 11:46:13.407727 [Byte1]: 74
8751 11:46:13.412432
8752 11:46:13.413015 Set Vref, RX VrefLevel [Byte0]: 75
8753 11:46:13.415250 [Byte1]: 75
8754 11:46:13.419796
8755 11:46:13.420374 Set Vref, RX VrefLevel [Byte0]: 76
8756 11:46:13.422948 [Byte1]: 76
8757 11:46:13.427293
8758 11:46:13.427770 Set Vref, RX VrefLevel [Byte0]: 77
8759 11:46:13.430524 [Byte1]: 77
8760 11:46:13.434874
8761 11:46:13.435349 Set Vref, RX VrefLevel [Byte0]: 78
8762 11:46:13.437819 [Byte1]: 78
8763 11:46:13.442326
8764 11:46:13.442926 Final RX Vref Byte 0 = 58 to rank0
8765 11:46:13.445536 Final RX Vref Byte 1 = 64 to rank0
8766 11:46:13.449135 Final RX Vref Byte 0 = 58 to rank1
8767 11:46:13.452562 Final RX Vref Byte 1 = 64 to rank1==
8768 11:46:13.455777 Dram Type= 6, Freq= 0, CH_1, rank 0
8769 11:46:13.459308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 11:46:13.462819 ==
8771 11:46:13.463388 DQS Delay:
8772 11:46:13.463764 DQS0 = 0, DQS1 = 0
8773 11:46:13.465589 DQM Delay:
8774 11:46:13.466062 DQM0 = 134, DQM1 = 129
8775 11:46:13.469047 DQ Delay:
8776 11:46:13.472812 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8777 11:46:13.475623 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8778 11:46:13.479391 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122
8779 11:46:13.482449 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8780 11:46:13.482924
8781 11:46:13.483298
8782 11:46:13.483646
8783 11:46:13.485483 [DramC_TX_OE_Calibration] TA2
8784 11:46:13.488864 Original DQ_B0 (3 6) =30, OEN = 27
8785 11:46:13.492217 Original DQ_B1 (3 6) =30, OEN = 27
8786 11:46:13.495822 24, 0x0, End_B0=24 End_B1=24
8787 11:46:13.496306 25, 0x0, End_B0=25 End_B1=25
8788 11:46:13.499484 26, 0x0, End_B0=26 End_B1=26
8789 11:46:13.502341 27, 0x0, End_B0=27 End_B1=27
8790 11:46:13.505477 28, 0x0, End_B0=28 End_B1=28
8791 11:46:13.505953 29, 0x0, End_B0=29 End_B1=29
8792 11:46:13.508817 30, 0x0, End_B0=30 End_B1=30
8793 11:46:13.512351 31, 0x5151, End_B0=30 End_B1=30
8794 11:46:13.515839 Byte0 end_step=30 best_step=27
8795 11:46:13.518980 Byte1 end_step=30 best_step=27
8796 11:46:13.522234 Byte0 TX OE(2T, 0.5T) = (3, 3)
8797 11:46:13.522730 Byte1 TX OE(2T, 0.5T) = (3, 3)
8798 11:46:13.523121
8799 11:46:13.525753
8800 11:46:13.532639 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8801 11:46:13.536101 CH1 RK0: MR19=303, MR18=1826
8802 11:46:13.542210 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8803 11:46:13.542816
8804 11:46:13.545489 ----->DramcWriteLeveling(PI) begin...
8805 11:46:13.545964 ==
8806 11:46:13.549198 Dram Type= 6, Freq= 0, CH_1, rank 1
8807 11:46:13.552363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8808 11:46:13.552837 ==
8809 11:46:13.555686 Write leveling (Byte 0): 23 => 23
8810 11:46:13.558982 Write leveling (Byte 1): 28 => 28
8811 11:46:13.562486 DramcWriteLeveling(PI) end<-----
8812 11:46:13.563059
8813 11:46:13.563432 ==
8814 11:46:13.565893 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 11:46:13.569007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 11:46:13.569482 ==
8817 11:46:13.572711 [Gating] SW mode calibration
8818 11:46:13.579293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8819 11:46:13.585749 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8820 11:46:13.589414 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 11:46:13.592709 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 11:46:13.598988 1 4 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
8823 11:46:13.602468 1 4 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8824 11:46:13.605416 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 11:46:13.612159 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 11:46:13.615639 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 11:46:13.618819 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 11:46:13.625748 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 11:46:13.628944 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8830 11:46:13.632323 1 5 8 | B1->B0 | 2525 3434 | 1 1 | (1 0) (1 0)
8831 11:46:13.635933 1 5 12 | B1->B0 | 2323 3232 | 0 1 | (1 0) (1 0)
8832 11:46:13.642303 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 11:46:13.645467 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 11:46:13.648863 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 11:46:13.655744 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 11:46:13.658740 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 11:46:13.662163 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 11:46:13.668984 1 6 8 | B1->B0 | 4444 2323 | 0 0 | (0 0) (0 0)
8839 11:46:13.672606 1 6 12 | B1->B0 | 4646 3636 | 0 1 | (0 0) (0 0)
8840 11:46:13.675879 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 11:46:13.682369 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 11:46:13.686315 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 11:46:13.689161 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 11:46:13.695196 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 11:46:13.698744 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 11:46:13.701888 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8847 11:46:13.709013 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8848 11:46:13.711847 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 11:46:13.715494 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 11:46:13.721739 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 11:46:13.725125 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 11:46:13.728792 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 11:46:13.735179 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 11:46:13.738825 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 11:46:13.742074 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 11:46:13.748741 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 11:46:13.752189 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:46:13.755488 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 11:46:13.758598 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 11:46:13.765007 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 11:46:13.768616 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8862 11:46:13.772030 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8863 11:46:13.778601 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8864 11:46:13.781825 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 11:46:13.785420 Total UI for P1: 0, mck2ui 16
8866 11:46:13.788890 best dqsien dly found for B0: ( 1, 9, 10)
8867 11:46:13.791895 Total UI for P1: 0, mck2ui 16
8868 11:46:13.795191 best dqsien dly found for B1: ( 1, 9, 8)
8869 11:46:13.798824 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8870 11:46:13.801795 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8871 11:46:13.802431
8872 11:46:13.805575 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8873 11:46:13.808803 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8874 11:46:13.811850 [Gating] SW calibration Done
8875 11:46:13.812421 ==
8876 11:46:13.815200 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 11:46:13.821693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 11:46:13.822167 ==
8879 11:46:13.822588 RX Vref Scan: 0
8880 11:46:13.823063
8881 11:46:13.825219 RX Vref 0 -> 0, step: 1
8882 11:46:13.825691
8883 11:46:13.828664 RX Delay 0 -> 252, step: 8
8884 11:46:13.831746 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8885 11:46:13.835064 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8886 11:46:13.838201 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8887 11:46:13.841532 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8888 11:46:13.848663 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8889 11:46:13.851921 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8890 11:46:13.855017 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8891 11:46:13.858553 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8892 11:46:13.861868 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8893 11:46:13.865133 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8894 11:46:13.871444 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8895 11:46:13.874874 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8896 11:46:13.878453 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8897 11:46:13.881758 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8898 11:46:13.887891 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8899 11:46:13.891379 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8900 11:46:13.891944 ==
8901 11:46:13.895042 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 11:46:13.898537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 11:46:13.899119 ==
8904 11:46:13.901489 DQS Delay:
8905 11:46:13.901963 DQS0 = 0, DQS1 = 0
8906 11:46:13.902346 DQM Delay:
8907 11:46:13.904985 DQM0 = 136, DQM1 = 131
8908 11:46:13.905562 DQ Delay:
8909 11:46:13.908538 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8910 11:46:13.911665 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8911 11:46:13.914824 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8912 11:46:13.921521 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8913 11:46:13.922102
8914 11:46:13.922540
8915 11:46:13.922896 ==
8916 11:46:13.925197 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 11:46:13.927965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 11:46:13.928610 ==
8919 11:46:13.929068
8920 11:46:13.929429
8921 11:46:13.931176 TX Vref Scan disable
8922 11:46:13.931682 == TX Byte 0 ==
8923 11:46:13.938063 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8924 11:46:13.941395 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8925 11:46:13.941873 == TX Byte 1 ==
8926 11:46:13.947783 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8927 11:46:13.950972 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8928 11:46:13.951454 ==
8929 11:46:13.954521 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 11:46:13.958219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 11:46:13.958867 ==
8932 11:46:13.971645
8933 11:46:13.975387 TX Vref early break, caculate TX vref
8934 11:46:13.978741 TX Vref=16, minBit 9, minWin=22, winSum=384
8935 11:46:13.981955 TX Vref=18, minBit 9, minWin=23, winSum=391
8936 11:46:13.985431 TX Vref=20, minBit 9, minWin=23, winSum=398
8937 11:46:13.988547 TX Vref=22, minBit 9, minWin=24, winSum=410
8938 11:46:13.992045 TX Vref=24, minBit 10, minWin=25, winSum=418
8939 11:46:13.998727 TX Vref=26, minBit 10, minWin=25, winSum=420
8940 11:46:14.001992 TX Vref=28, minBit 13, minWin=25, winSum=418
8941 11:46:14.005579 TX Vref=30, minBit 10, minWin=24, winSum=414
8942 11:46:14.009060 TX Vref=32, minBit 10, minWin=24, winSum=403
8943 11:46:14.012081 TX Vref=34, minBit 10, minWin=23, winSum=394
8944 11:46:14.018476 [TxChooseVref] Worse bit 10, Min win 25, Win sum 420, Final Vref 26
8945 11:46:14.019068
8946 11:46:14.022240 Final TX Range 0 Vref 26
8947 11:46:14.022871
8948 11:46:14.023253 ==
8949 11:46:14.025008 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 11:46:14.028629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 11:46:14.029327 ==
8952 11:46:14.029741
8953 11:46:14.030100
8954 11:46:14.031396 TX Vref Scan disable
8955 11:46:14.038514 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8956 11:46:14.038991 == TX Byte 0 ==
8957 11:46:14.041932 u2DelayCellOfst[0]=17 cells (5 PI)
8958 11:46:14.045026 u2DelayCellOfst[1]=10 cells (3 PI)
8959 11:46:14.048160 u2DelayCellOfst[2]=0 cells (0 PI)
8960 11:46:14.051836 u2DelayCellOfst[3]=3 cells (1 PI)
8961 11:46:14.055131 u2DelayCellOfst[4]=6 cells (2 PI)
8962 11:46:14.058559 u2DelayCellOfst[5]=17 cells (5 PI)
8963 11:46:14.061667 u2DelayCellOfst[6]=17 cells (5 PI)
8964 11:46:14.065002 u2DelayCellOfst[7]=3 cells (1 PI)
8965 11:46:14.068254 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8966 11:46:14.071416 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8967 11:46:14.074927 == TX Byte 1 ==
8968 11:46:14.078649 u2DelayCellOfst[8]=0 cells (0 PI)
8969 11:46:14.079217 u2DelayCellOfst[9]=6 cells (2 PI)
8970 11:46:14.081914 u2DelayCellOfst[10]=10 cells (3 PI)
8971 11:46:14.085149 u2DelayCellOfst[11]=3 cells (1 PI)
8972 11:46:14.088427 u2DelayCellOfst[12]=13 cells (4 PI)
8973 11:46:14.091803 u2DelayCellOfst[13]=17 cells (5 PI)
8974 11:46:14.094935 u2DelayCellOfst[14]=20 cells (6 PI)
8975 11:46:14.098568 u2DelayCellOfst[15]=20 cells (6 PI)
8976 11:46:14.101392 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8977 11:46:14.108733 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8978 11:46:14.109306 DramC Write-DBI on
8979 11:46:14.109690 ==
8980 11:46:14.111554 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 11:46:14.115180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 11:46:14.118308 ==
8983 11:46:14.118918
8984 11:46:14.119299
8985 11:46:14.119646 TX Vref Scan disable
8986 11:46:14.122322 == TX Byte 0 ==
8987 11:46:14.124859 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8988 11:46:14.128521 == TX Byte 1 ==
8989 11:46:14.131793 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8990 11:46:14.134925 DramC Write-DBI off
8991 11:46:14.135402
8992 11:46:14.135776 [DATLAT]
8993 11:46:14.136130 Freq=1600, CH1 RK1
8994 11:46:14.136471
8995 11:46:14.138462 DATLAT Default: 0xf
8996 11:46:14.138936 0, 0xFFFF, sum = 0
8997 11:46:14.141786 1, 0xFFFF, sum = 0
8998 11:46:14.145277 2, 0xFFFF, sum = 0
8999 11:46:14.145848 3, 0xFFFF, sum = 0
9000 11:46:14.148305 4, 0xFFFF, sum = 0
9001 11:46:14.148878 5, 0xFFFF, sum = 0
9002 11:46:14.151825 6, 0xFFFF, sum = 0
9003 11:46:14.152309 7, 0xFFFF, sum = 0
9004 11:46:14.155053 8, 0xFFFF, sum = 0
9005 11:46:14.155535 9, 0xFFFF, sum = 0
9006 11:46:14.158079 10, 0xFFFF, sum = 0
9007 11:46:14.158707 11, 0xFFFF, sum = 0
9008 11:46:14.161924 12, 0xFFFF, sum = 0
9009 11:46:14.162550 13, 0xFFFF, sum = 0
9010 11:46:14.164907 14, 0x0, sum = 1
9011 11:46:14.165389 15, 0x0, sum = 2
9012 11:46:14.168155 16, 0x0, sum = 3
9013 11:46:14.168672 17, 0x0, sum = 4
9014 11:46:14.171354 best_step = 15
9015 11:46:14.171845
9016 11:46:14.172224 ==
9017 11:46:14.175278 Dram Type= 6, Freq= 0, CH_1, rank 1
9018 11:46:14.178300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9019 11:46:14.178916 ==
9020 11:46:14.181967 RX Vref Scan: 0
9021 11:46:14.182579
9022 11:46:14.182963 RX Vref 0 -> 0, step: 1
9023 11:46:14.183321
9024 11:46:14.185178 RX Delay 19 -> 252, step: 4
9025 11:46:14.188531 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9026 11:46:14.195231 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9027 11:46:14.198448 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9028 11:46:14.201459 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9029 11:46:14.205024 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9030 11:46:14.207967 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9031 11:46:14.211534 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9032 11:46:14.218013 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
9033 11:46:14.221559 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
9034 11:46:14.224965 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9035 11:46:14.228053 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9036 11:46:14.231851 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9037 11:46:14.238109 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9038 11:46:14.241678 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9039 11:46:14.244473 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9040 11:46:14.248195 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9041 11:46:14.248772 ==
9042 11:46:14.251708 Dram Type= 6, Freq= 0, CH_1, rank 1
9043 11:46:14.258231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9044 11:46:14.258858 ==
9045 11:46:14.259243 DQS Delay:
9046 11:46:14.261373 DQS0 = 0, DQS1 = 0
9047 11:46:14.261841 DQM Delay:
9048 11:46:14.262212 DQM0 = 133, DQM1 = 130
9049 11:46:14.264621 DQ Delay:
9050 11:46:14.268233 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9051 11:46:14.271486 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
9052 11:46:14.274819 DQ8 =114, DQ9 =120, DQ10 =130, DQ11 =126
9053 11:46:14.278238 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
9054 11:46:14.278876
9055 11:46:14.279257
9056 11:46:14.279606
9057 11:46:14.281321 [DramC_TX_OE_Calibration] TA2
9058 11:46:14.284695 Original DQ_B0 (3 6) =30, OEN = 27
9059 11:46:14.288434 Original DQ_B1 (3 6) =30, OEN = 27
9060 11:46:14.291645 24, 0x0, End_B0=24 End_B1=24
9061 11:46:14.292234 25, 0x0, End_B0=25 End_B1=25
9062 11:46:14.294643 26, 0x0, End_B0=26 End_B1=26
9063 11:46:14.298083 27, 0x0, End_B0=27 End_B1=27
9064 11:46:14.301735 28, 0x0, End_B0=28 End_B1=28
9065 11:46:14.305002 29, 0x0, End_B0=29 End_B1=29
9066 11:46:14.305581 30, 0x0, End_B0=30 End_B1=30
9067 11:46:14.308275 31, 0x4141, End_B0=30 End_B1=30
9068 11:46:14.311707 Byte0 end_step=30 best_step=27
9069 11:46:14.314548 Byte1 end_step=30 best_step=27
9070 11:46:14.318197 Byte0 TX OE(2T, 0.5T) = (3, 3)
9071 11:46:14.321611 Byte1 TX OE(2T, 0.5T) = (3, 3)
9072 11:46:14.322180
9073 11:46:14.322603
9074 11:46:14.328063 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9075 11:46:14.331057 CH1 RK1: MR19=303, MR18=1B07
9076 11:46:14.337923 CH1_RK1: MR19=0x303, MR18=0x1B07, DQSOSC=396, MR23=63, INC=23, DEC=15
9077 11:46:14.341322 [RxdqsGatingPostProcess] freq 1600
9078 11:46:14.344353 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9079 11:46:14.348004 best DQS0 dly(2T, 0.5T) = (1, 1)
9080 11:46:14.351209 best DQS1 dly(2T, 0.5T) = (1, 1)
9081 11:46:14.354616 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9082 11:46:14.358105 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9083 11:46:14.361478 best DQS0 dly(2T, 0.5T) = (1, 1)
9084 11:46:14.364494 best DQS1 dly(2T, 0.5T) = (1, 1)
9085 11:46:14.367562 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9086 11:46:14.370825 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9087 11:46:14.374294 Pre-setting of DQS Precalculation
9088 11:46:14.377361 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9089 11:46:14.384070 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9090 11:46:14.394465 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9091 11:46:14.395043
9092 11:46:14.395423
9093 11:46:14.395775 [Calibration Summary] 3200 Mbps
9094 11:46:14.397216 CH 0, Rank 0
9095 11:46:14.397696 SW Impedance : PASS
9096 11:46:14.400454 DUTY Scan : NO K
9097 11:46:14.403862 ZQ Calibration : PASS
9098 11:46:14.404392 Jitter Meter : NO K
9099 11:46:14.407239 CBT Training : PASS
9100 11:46:14.410541 Write leveling : PASS
9101 11:46:14.411291 RX DQS gating : PASS
9102 11:46:14.413982 RX DQ/DQS(RDDQC) : PASS
9103 11:46:14.417238 TX DQ/DQS : PASS
9104 11:46:14.417914 RX DATLAT : PASS
9105 11:46:14.420441 RX DQ/DQS(Engine): PASS
9106 11:46:14.423705 TX OE : PASS
9107 11:46:14.424297 All Pass.
9108 11:46:14.424958
9109 11:46:14.425590 CH 0, Rank 1
9110 11:46:14.427074 SW Impedance : PASS
9111 11:46:14.430061 DUTY Scan : NO K
9112 11:46:14.430655 ZQ Calibration : PASS
9113 11:46:14.433835 Jitter Meter : NO K
9114 11:46:14.436918 CBT Training : PASS
9115 11:46:14.437394 Write leveling : PASS
9116 11:46:14.440670 RX DQS gating : PASS
9117 11:46:14.443775 RX DQ/DQS(RDDQC) : PASS
9118 11:46:14.444349 TX DQ/DQS : PASS
9119 11:46:14.446991 RX DATLAT : PASS
9120 11:46:14.447466 RX DQ/DQS(Engine): PASS
9121 11:46:14.450348 TX OE : PASS
9122 11:46:14.450876 All Pass.
9123 11:46:14.451258
9124 11:46:14.453563 CH 1, Rank 0
9125 11:46:14.454037 SW Impedance : PASS
9126 11:46:14.457167 DUTY Scan : NO K
9127 11:46:14.460518 ZQ Calibration : PASS
9128 11:46:14.461093 Jitter Meter : NO K
9129 11:46:14.464066 CBT Training : PASS
9130 11:46:14.467206 Write leveling : PASS
9131 11:46:14.467686 RX DQS gating : PASS
9132 11:46:14.470536 RX DQ/DQS(RDDQC) : PASS
9133 11:46:14.474095 TX DQ/DQS : PASS
9134 11:46:14.474723 RX DATLAT : PASS
9135 11:46:14.477334 RX DQ/DQS(Engine): PASS
9136 11:46:14.480063 TX OE : PASS
9137 11:46:14.480544 All Pass.
9138 11:46:14.480924
9139 11:46:14.481273 CH 1, Rank 1
9140 11:46:14.483662 SW Impedance : PASS
9141 11:46:14.486717 DUTY Scan : NO K
9142 11:46:14.487195 ZQ Calibration : PASS
9143 11:46:14.490418 Jitter Meter : NO K
9144 11:46:14.493475 CBT Training : PASS
9145 11:46:14.493951 Write leveling : PASS
9146 11:46:14.497073 RX DQS gating : PASS
9147 11:46:14.500158 RX DQ/DQS(RDDQC) : PASS
9148 11:46:14.500635 TX DQ/DQS : PASS
9149 11:46:14.503424 RX DATLAT : PASS
9150 11:46:14.503901 RX DQ/DQS(Engine): PASS
9151 11:46:14.506827 TX OE : PASS
9152 11:46:14.507307 All Pass.
9153 11:46:14.507683
9154 11:46:14.510336 DramC Write-DBI on
9155 11:46:14.513765 PER_BANK_REFRESH: Hybrid Mode
9156 11:46:14.514338 TX_TRACKING: ON
9157 11:46:14.523569 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9158 11:46:14.530336 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9159 11:46:14.536937 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9160 11:46:14.543225 [FAST_K] Save calibration result to emmc
9161 11:46:14.543709 sync common calibartion params.
9162 11:46:14.546831 sync cbt_mode0:1, 1:1
9163 11:46:14.550220 dram_init: ddr_geometry: 2
9164 11:46:14.550740 dram_init: ddr_geometry: 2
9165 11:46:14.553549 dram_init: ddr_geometry: 2
9166 11:46:14.557003 0:dram_rank_size:100000000
9167 11:46:14.560231 1:dram_rank_size:100000000
9168 11:46:14.563722 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9169 11:46:14.567235 DFS_SHUFFLE_HW_MODE: ON
9170 11:46:14.570167 dramc_set_vcore_voltage set vcore to 725000
9171 11:46:14.573403 Read voltage for 1600, 0
9172 11:46:14.573903 Vio18 = 0
9173 11:46:14.574283 Vcore = 725000
9174 11:46:14.576749 Vdram = 0
9175 11:46:14.577321 Vddq = 0
9176 11:46:14.577700 Vmddr = 0
9177 11:46:14.580180 switch to 3200 Mbps bootup
9178 11:46:14.583398 [DramcRunTimeConfig]
9179 11:46:14.583971 PHYPLL
9180 11:46:14.584352 DPM_CONTROL_AFTERK: ON
9181 11:46:14.587191 PER_BANK_REFRESH: ON
9182 11:46:14.590642 REFRESH_OVERHEAD_REDUCTION: ON
9183 11:46:14.591324 CMD_PICG_NEW_MODE: OFF
9184 11:46:14.593241 XRTWTW_NEW_MODE: ON
9185 11:46:14.596653 XRTRTR_NEW_MODE: ON
9186 11:46:14.597226 TX_TRACKING: ON
9187 11:46:14.599777 RDSEL_TRACKING: OFF
9188 11:46:14.600255 DQS Precalculation for DVFS: ON
9189 11:46:14.603276 RX_TRACKING: OFF
9190 11:46:14.603754 HW_GATING DBG: ON
9191 11:46:14.607002 ZQCS_ENABLE_LP4: ON
9192 11:46:14.607571 RX_PICG_NEW_MODE: ON
9193 11:46:14.610025 TX_PICG_NEW_MODE: ON
9194 11:46:14.613323 ENABLE_RX_DCM_DPHY: ON
9195 11:46:14.617059 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9196 11:46:14.617632 DUMMY_READ_FOR_TRACKING: OFF
9197 11:46:14.620100 !!! SPM_CONTROL_AFTERK: OFF
9198 11:46:14.623650 !!! SPM could not control APHY
9199 11:46:14.627008 IMPEDANCE_TRACKING: ON
9200 11:46:14.627581 TEMP_SENSOR: ON
9201 11:46:14.630150 HW_SAVE_FOR_SR: OFF
9202 11:46:14.630761 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9203 11:46:14.636983 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9204 11:46:14.637642 Read ODT Tracking: ON
9205 11:46:14.640304 Refresh Rate DeBounce: ON
9206 11:46:14.643502 DFS_NO_QUEUE_FLUSH: ON
9207 11:46:14.644087 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9208 11:46:14.646758 ENABLE_DFS_RUNTIME_MRW: OFF
9209 11:46:14.649997 DDR_RESERVE_NEW_MODE: ON
9210 11:46:14.653208 MR_CBT_SWITCH_FREQ: ON
9211 11:46:14.653798 =========================
9212 11:46:14.672888 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9213 11:46:14.676259 dram_init: ddr_geometry: 2
9214 11:46:14.694558 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9215 11:46:14.697950 dram_init: dram init end (result: 0)
9216 11:46:14.704009 DRAM-K: Full calibration passed in 24484 msecs
9217 11:46:14.707582 MRC: failed to locate region type 0.
9218 11:46:14.708065 DRAM rank0 size:0x100000000,
9219 11:46:14.710981 DRAM rank1 size=0x100000000
9220 11:46:14.720999 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9221 11:46:14.727719 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9222 11:46:14.734114 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9223 11:46:14.740752 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9224 11:46:14.744171 DRAM rank0 size:0x100000000,
9225 11:46:14.747404 DRAM rank1 size=0x100000000
9226 11:46:14.747981 CBMEM:
9227 11:46:14.750822 IMD: root @ 0xfffff000 254 entries.
9228 11:46:14.754312 IMD: root @ 0xffffec00 62 entries.
9229 11:46:14.757360 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9230 11:46:14.760902 WARNING: RO_VPD is uninitialized or empty.
9231 11:46:14.767299 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9232 11:46:14.774244 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9233 11:46:14.787631 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9234 11:46:14.798712 BS: romstage times (exec / console): total (unknown) / 23991 ms
9235 11:46:14.799285
9236 11:46:14.799658
9237 11:46:14.808591 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9238 11:46:14.811979 ARM64: Exception handlers installed.
9239 11:46:14.815499 ARM64: Testing exception
9240 11:46:14.818304 ARM64: Done test exception
9241 11:46:14.818812 Enumerating buses...
9242 11:46:14.821708 Show all devs... Before device enumeration.
9243 11:46:14.825385 Root Device: enabled 1
9244 11:46:14.828606 CPU_CLUSTER: 0: enabled 1
9245 11:46:14.829181 CPU: 00: enabled 1
9246 11:46:14.831760 Compare with tree...
9247 11:46:14.832231 Root Device: enabled 1
9248 11:46:14.834896 CPU_CLUSTER: 0: enabled 1
9249 11:46:14.838241 CPU: 00: enabled 1
9250 11:46:14.838765 Root Device scanning...
9251 11:46:14.841781 scan_static_bus for Root Device
9252 11:46:14.845173 CPU_CLUSTER: 0 enabled
9253 11:46:14.848356 scan_static_bus for Root Device done
9254 11:46:14.851906 scan_bus: bus Root Device finished in 8 msecs
9255 11:46:14.852638 done
9256 11:46:14.857956 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9257 11:46:14.861990 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9258 11:46:14.868629 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9259 11:46:14.871441 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9260 11:46:14.875028 Allocating resources...
9261 11:46:14.878247 Reading resources...
9262 11:46:14.881606 Root Device read_resources bus 0 link: 0
9263 11:46:14.882183 DRAM rank0 size:0x100000000,
9264 11:46:14.884563 DRAM rank1 size=0x100000000
9265 11:46:14.888244 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9266 11:46:14.891104 CPU: 00 missing read_resources
9267 11:46:14.894745 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9268 11:46:14.901570 Root Device read_resources bus 0 link: 0 done
9269 11:46:14.902138 Done reading resources.
9270 11:46:14.907969 Show resources in subtree (Root Device)...After reading.
9271 11:46:14.911722 Root Device child on link 0 CPU_CLUSTER: 0
9272 11:46:14.914592 CPU_CLUSTER: 0 child on link 0 CPU: 00
9273 11:46:14.924551 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9274 11:46:14.925257 CPU: 00
9275 11:46:14.928191 Root Device assign_resources, bus 0 link: 0
9276 11:46:14.931591 CPU_CLUSTER: 0 missing set_resources
9277 11:46:14.938123 Root Device assign_resources, bus 0 link: 0 done
9278 11:46:14.938641 Done setting resources.
9279 11:46:14.944736 Show resources in subtree (Root Device)...After assigning values.
9280 11:46:14.947938 Root Device child on link 0 CPU_CLUSTER: 0
9281 11:46:14.951302 CPU_CLUSTER: 0 child on link 0 CPU: 00
9282 11:46:14.961191 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9283 11:46:14.961767 CPU: 00
9284 11:46:14.964785 Done allocating resources.
9285 11:46:14.967683 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9286 11:46:14.971516 Enabling resources...
9287 11:46:14.971994 done.
9288 11:46:14.978141 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9289 11:46:14.978746 Initializing devices...
9290 11:46:14.981224 Root Device init
9291 11:46:14.981772 init hardware done!
9292 11:46:14.984460 0x00000018: ctrlr->caps
9293 11:46:14.987902 52.000 MHz: ctrlr->f_max
9294 11:46:14.988392 0.400 MHz: ctrlr->f_min
9295 11:46:14.991151 0x40ff8080: ctrlr->voltages
9296 11:46:14.991711 sclk: 390625
9297 11:46:14.994769 Bus Width = 1
9298 11:46:14.995336 sclk: 390625
9299 11:46:14.995716 Bus Width = 1
9300 11:46:14.998094 Early init status = 3
9301 11:46:15.004767 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9302 11:46:15.007780 in-header: 03 fc 00 00 01 00 00 00
9303 11:46:15.011356 in-data: 00
9304 11:46:15.014612 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9305 11:46:15.018888 in-header: 03 fd 00 00 00 00 00 00
9306 11:46:15.022587 in-data:
9307 11:46:15.025635 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9308 11:46:15.030124 in-header: 03 fc 00 00 01 00 00 00
9309 11:46:15.033325 in-data: 00
9310 11:46:15.036924 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9311 11:46:15.042311 in-header: 03 fd 00 00 00 00 00 00
9312 11:46:15.045644 in-data:
9313 11:46:15.049387 [SSUSB] Setting up USB HOST controller...
9314 11:46:15.052684 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9315 11:46:15.055525 [SSUSB] phy power-on done.
9316 11:46:15.059128 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9317 11:46:15.066036 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9318 11:46:15.069260 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9319 11:46:15.075969 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9320 11:46:15.082258 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9321 11:46:15.089073 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9322 11:46:15.095662 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9323 11:46:15.102317 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9324 11:46:15.105865 SPM: binary array size = 0x9dc
9325 11:46:15.109083 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9326 11:46:15.115470 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9327 11:46:15.122367 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9328 11:46:15.125495 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9329 11:46:15.129142 configure_display: Starting display init
9330 11:46:15.165597 anx7625_power_on_init: Init interface.
9331 11:46:15.169120 anx7625_disable_pd_protocol: Disabled PD feature.
9332 11:46:15.172448 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9333 11:46:15.200210 anx7625_start_dp_work: Secure OCM version=00
9334 11:46:15.203356 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9335 11:46:15.218342 sp_tx_get_edid_block: EDID Block = 1
9336 11:46:15.320763 Extracted contents:
9337 11:46:15.324172 header: 00 ff ff ff ff ff ff 00
9338 11:46:15.327280 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9339 11:46:15.330791 version: 01 04
9340 11:46:15.334133 basic params: 95 1f 11 78 0a
9341 11:46:15.337634 chroma info: 76 90 94 55 54 90 27 21 50 54
9342 11:46:15.340894 established: 00 00 00
9343 11:46:15.347474 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9344 11:46:15.350783 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9345 11:46:15.357322 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9346 11:46:15.363949 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9347 11:46:15.370493 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9348 11:46:15.374048 extensions: 00
9349 11:46:15.374805 checksum: fb
9350 11:46:15.375326
9351 11:46:15.376929 Manufacturer: IVO Model 57d Serial Number 0
9352 11:46:15.380696 Made week 0 of 2020
9353 11:46:15.381267 EDID version: 1.4
9354 11:46:15.383692 Digital display
9355 11:46:15.387192 6 bits per primary color channel
9356 11:46:15.387753 DisplayPort interface
9357 11:46:15.390948 Maximum image size: 31 cm x 17 cm
9358 11:46:15.394087 Gamma: 220%
9359 11:46:15.394731 Check DPMS levels
9360 11:46:15.397025 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9361 11:46:15.399973 First detailed timing is preferred timing
9362 11:46:15.403982 Established timings supported:
9363 11:46:15.406887 Standard timings supported:
9364 11:46:15.410038 Detailed timings
9365 11:46:15.413612 Hex of detail: 383680a07038204018303c0035ae10000019
9366 11:46:15.416740 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9367 11:46:15.423992 0780 0798 07c8 0820 hborder 0
9368 11:46:15.427207 0438 043b 0447 0458 vborder 0
9369 11:46:15.430190 -hsync -vsync
9370 11:46:15.430631 Did detailed timing
9371 11:46:15.433454 Hex of detail: 000000000000000000000000000000000000
9372 11:46:15.436618 Manufacturer-specified data, tag 0
9373 11:46:15.443320 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9374 11:46:15.443645 ASCII string: InfoVision
9375 11:46:15.449919 Hex of detail: 000000fe00523134304e574635205248200a
9376 11:46:15.453110 ASCII string: R140NWF5 RH
9377 11:46:15.453602 Checksum
9378 11:46:15.454004 Checksum: 0xfb (valid)
9379 11:46:15.459829 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9380 11:46:15.463268 DSI data_rate: 832800000 bps
9381 11:46:15.466806 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9382 11:46:15.473023 anx7625_parse_edid: pixelclock(138800).
9383 11:46:15.476358 hactive(1920), hsync(48), hfp(24), hbp(88)
9384 11:46:15.480159 vactive(1080), vsync(12), vfp(3), vbp(17)
9385 11:46:15.483671 anx7625_dsi_config: config dsi.
9386 11:46:15.489795 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9387 11:46:15.502472 anx7625_dsi_config: success to config DSI
9388 11:46:15.506124 anx7625_dp_start: MIPI phy setup OK.
9389 11:46:15.509300 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9390 11:46:15.512756 mtk_ddp_mode_set invalid vrefresh 60
9391 11:46:15.515897 main_disp_path_setup
9392 11:46:15.516367 ovl_layer_smi_id_en
9393 11:46:15.519099 ovl_layer_smi_id_en
9394 11:46:15.519574 ccorr_config
9395 11:46:15.519970 aal_config
9396 11:46:15.522495 gamma_config
9397 11:46:15.522975 postmask_config
9398 11:46:15.525711 dither_config
9399 11:46:15.529103 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9400 11:46:15.535631 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9401 11:46:15.538701 Root Device init finished in 555 msecs
9402 11:46:15.542183 CPU_CLUSTER: 0 init
9403 11:46:15.548749 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9404 11:46:15.552055 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9405 11:46:15.555441 APU_MBOX 0x190000b0 = 0x10001
9406 11:46:15.558866 APU_MBOX 0x190001b0 = 0x10001
9407 11:46:15.561757 APU_MBOX 0x190005b0 = 0x10001
9408 11:46:15.565468 APU_MBOX 0x190006b0 = 0x10001
9409 11:46:15.568763 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9410 11:46:15.581178 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9411 11:46:15.594029 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9412 11:46:15.600681 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9413 11:46:15.612059 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9414 11:46:15.621147 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9415 11:46:15.624780 CPU_CLUSTER: 0 init finished in 81 msecs
9416 11:46:15.627607 Devices initialized
9417 11:46:15.630972 Show all devs... After init.
9418 11:46:15.631056 Root Device: enabled 1
9419 11:46:15.634571 CPU_CLUSTER: 0: enabled 1
9420 11:46:15.637506 CPU: 00: enabled 1
9421 11:46:15.640611 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9422 11:46:15.644147 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9423 11:46:15.647538 ELOG: NV offset 0x57f000 size 0x1000
9424 11:46:15.654394 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9425 11:46:15.660829 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9426 11:46:15.664374 ELOG: Event(17) added with size 13 at 2023-11-24 11:45:41 UTC
9427 11:46:15.667641 out: cmd=0x121: 03 db 21 01 00 00 00 00
9428 11:46:15.671282 in-header: 03 46 00 00 2c 00 00 00
9429 11:46:15.684510 in-data: 19 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9430 11:46:15.691393 ELOG: Event(A1) added with size 10 at 2023-11-24 11:45:41 UTC
9431 11:46:15.697847 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9432 11:46:15.704862 ELOG: Event(A0) added with size 9 at 2023-11-24 11:45:41 UTC
9433 11:46:15.708495 elog_add_boot_reason: Logged dev mode boot
9434 11:46:15.711446 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9435 11:46:15.714793 Finalize devices...
9436 11:46:15.715230 Devices finalized
9437 11:46:15.721432 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9438 11:46:15.724822 Writing coreboot table at 0xffe64000
9439 11:46:15.728273 0. 000000000010a000-0000000000113fff: RAMSTAGE
9440 11:46:15.731292 1. 0000000040000000-00000000400fffff: RAM
9441 11:46:15.734647 2. 0000000040100000-000000004032afff: RAMSTAGE
9442 11:46:15.741548 3. 000000004032b000-00000000545fffff: RAM
9443 11:46:15.744503 4. 0000000054600000-000000005465ffff: BL31
9444 11:46:15.747993 5. 0000000054660000-00000000ffe63fff: RAM
9445 11:46:15.751418 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9446 11:46:15.757933 7. 0000000100000000-000000023fffffff: RAM
9447 11:46:15.758487 Passing 5 GPIOs to payload:
9448 11:46:15.764523 NAME | PORT | POLARITY | VALUE
9449 11:46:15.768058 EC in RW | 0x000000aa | low | undefined
9450 11:46:15.774332 EC interrupt | 0x00000005 | low | undefined
9451 11:46:15.778016 TPM interrupt | 0x000000ab | high | undefined
9452 11:46:15.781464 SD card detect | 0x00000011 | high | undefined
9453 11:46:15.787719 speaker enable | 0x00000093 | high | undefined
9454 11:46:15.790904 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9455 11:46:15.794343 in-header: 03 f9 00 00 02 00 00 00
9456 11:46:15.794807 in-data: 02 00
9457 11:46:15.797439 ADC[4]: Raw value=901401 ID=7
9458 11:46:15.800745 ADC[3]: Raw value=213179 ID=1
9459 11:46:15.801146 RAM Code: 0x71
9460 11:46:15.803952 ADC[6]: Raw value=74502 ID=0
9461 11:46:15.807936 ADC[5]: Raw value=212072 ID=1
9462 11:46:15.808369 SKU Code: 0x1
9463 11:46:15.814296 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f943
9464 11:46:15.817529 coreboot table: 964 bytes.
9465 11:46:15.821008 IMD ROOT 0. 0xfffff000 0x00001000
9466 11:46:15.824061 IMD SMALL 1. 0xffffe000 0x00001000
9467 11:46:15.827872 RO MCACHE 2. 0xffffc000 0x00001104
9468 11:46:15.831346 CONSOLE 3. 0xfff7c000 0x00080000
9469 11:46:15.834248 FMAP 4. 0xfff7b000 0x00000452
9470 11:46:15.837628 TIME STAMP 5. 0xfff7a000 0x00000910
9471 11:46:15.840878 VBOOT WORK 6. 0xfff66000 0x00014000
9472 11:46:15.844091 RAMOOPS 7. 0xffe66000 0x00100000
9473 11:46:15.847848 COREBOOT 8. 0xffe64000 0x00002000
9474 11:46:15.848272 IMD small region:
9475 11:46:15.850541 IMD ROOT 0. 0xffffec00 0x00000400
9476 11:46:15.854120 VPD 1. 0xffffeb80 0x0000006c
9477 11:46:15.857543 MMC STATUS 2. 0xffffeb60 0x00000004
9478 11:46:15.864389 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9479 11:46:15.867855 Probing TPM: done!
9480 11:46:15.870799 Connected to device vid:did:rid of 1ae0:0028:00
9481 11:46:15.880911 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9482 11:46:15.884489 Initialized TPM device CR50 revision 0
9483 11:46:15.888365 Checking cr50 for pending updates
9484 11:46:15.891363 Reading cr50 TPM mode
9485 11:46:15.900240 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9486 11:46:15.906376 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9487 11:46:15.946423 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9488 11:46:15.949671 Checking segment from ROM address 0x40100000
9489 11:46:15.953128 Checking segment from ROM address 0x4010001c
9490 11:46:15.959647 Loading segment from ROM address 0x40100000
9491 11:46:15.960084 code (compression=0)
9492 11:46:15.970018 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9493 11:46:15.976493 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9494 11:46:15.976930 it's not compressed!
9495 11:46:15.983086 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9496 11:46:15.986466 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9497 11:46:16.007020 Loading segment from ROM address 0x4010001c
9498 11:46:16.007453 Entry Point 0x80000000
9499 11:46:16.009912 Loaded segments
9500 11:46:16.013442 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9501 11:46:16.020402 Jumping to boot code at 0x80000000(0xffe64000)
9502 11:46:16.027066 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9503 11:46:16.033249 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9504 11:46:16.041613 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9505 11:46:16.044471 Checking segment from ROM address 0x40100000
9506 11:46:16.048078 Checking segment from ROM address 0x4010001c
9507 11:46:16.054743 Loading segment from ROM address 0x40100000
9508 11:46:16.055179 code (compression=1)
9509 11:46:16.061183 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9510 11:46:16.071251 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9511 11:46:16.071687 using LZMA
9512 11:46:16.079600 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9513 11:46:16.086424 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9514 11:46:16.089301 Loading segment from ROM address 0x4010001c
9515 11:46:16.089737 Entry Point 0x54601000
9516 11:46:16.093011 Loaded segments
9517 11:46:16.096437 NOTICE: MT8192 bl31_setup
9518 11:46:16.103143 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9519 11:46:16.106865 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9520 11:46:16.110093 WARNING: region 0:
9521 11:46:16.113205 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 11:46:16.113641 WARNING: region 1:
9523 11:46:16.119875 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9524 11:46:16.123296 WARNING: region 2:
9525 11:46:16.126688 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9526 11:46:16.130117 WARNING: region 3:
9527 11:46:16.133617 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9528 11:46:16.136979 WARNING: region 4:
9529 11:46:16.140197 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9530 11:46:16.143431 WARNING: region 5:
9531 11:46:16.146708 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 11:46:16.150286 WARNING: region 6:
9533 11:46:16.153630 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9534 11:46:16.154068 WARNING: region 7:
9535 11:46:16.160175 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 11:46:16.166984 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9537 11:46:16.169658 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9538 11:46:16.173205 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9539 11:46:16.179691 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9540 11:46:16.182870 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9541 11:46:16.186293 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9542 11:46:16.193255 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9543 11:46:16.196412 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9544 11:46:16.199481 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9545 11:46:16.206109 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9546 11:46:16.209503 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9547 11:46:16.216159 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9548 11:46:16.219872 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9549 11:46:16.223232 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9550 11:46:16.229779 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9551 11:46:16.233254 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9552 11:46:16.236574 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9553 11:46:16.242971 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9554 11:46:16.246900 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9555 11:46:16.252900 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9556 11:46:16.256324 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9557 11:46:16.259959 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9558 11:46:16.266223 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9559 11:46:16.269970 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9560 11:46:16.276715 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9561 11:46:16.279768 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9562 11:46:16.283334 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9563 11:46:16.290073 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9564 11:46:16.293335 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9565 11:46:16.296566 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9566 11:46:16.303610 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9567 11:46:16.306671 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9568 11:46:16.309890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9569 11:46:16.316877 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9570 11:46:16.319948 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9571 11:46:16.323585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9572 11:46:16.326798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9573 11:46:16.333707 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9574 11:46:16.336809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9575 11:46:16.340173 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9576 11:46:16.343469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9577 11:46:16.350409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9578 11:46:16.353341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9579 11:46:16.356915 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9580 11:46:16.360438 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9581 11:46:16.366803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9582 11:46:16.370077 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9583 11:46:16.373438 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9584 11:46:16.380572 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9585 11:46:16.383933 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9586 11:46:16.386970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9587 11:46:16.393808 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9588 11:46:16.396900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9589 11:46:16.403908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9590 11:46:16.406769 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9591 11:46:16.413600 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9592 11:46:16.416729 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9593 11:46:16.420251 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9594 11:46:16.427224 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9595 11:46:16.430208 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9596 11:46:16.437179 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9597 11:46:16.440404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9598 11:46:16.447263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9599 11:46:16.450475 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9600 11:46:16.453796 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9601 11:46:16.460469 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9602 11:46:16.463807 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9603 11:46:16.470470 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9604 11:46:16.473598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9605 11:46:16.480547 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9606 11:46:16.484140 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9607 11:46:16.487318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9608 11:46:16.494343 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9609 11:46:16.497334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9610 11:46:16.504257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9611 11:46:16.507204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9612 11:46:16.510791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9613 11:46:16.517259 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9614 11:46:16.520673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9615 11:46:16.527665 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9616 11:46:16.530820 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9617 11:46:16.537474 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9618 11:46:16.540751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9619 11:46:16.547496 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9620 11:46:16.550937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9621 11:46:16.554236 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9622 11:46:16.561173 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9623 11:46:16.564259 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9624 11:46:16.571294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9625 11:46:16.574417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9626 11:46:16.577369 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9627 11:46:16.584475 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9628 11:46:16.587959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9629 11:46:16.594261 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9630 11:46:16.597625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9631 11:46:16.604505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9632 11:46:16.607641 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9633 11:46:16.611290 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9634 11:46:16.614518 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9635 11:46:16.620980 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9636 11:46:16.624769 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9637 11:46:16.627931 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9638 11:46:16.634502 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9639 11:46:16.638074 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9640 11:46:16.641122 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9641 11:46:16.647861 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9642 11:46:16.651086 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9643 11:46:16.657786 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9644 11:46:16.661438 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9645 11:46:16.664434 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9646 11:46:16.671269 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9647 11:46:16.674704 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9648 11:46:16.681293 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9649 11:46:16.684980 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9650 11:46:16.688239 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9651 11:46:16.694711 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9652 11:46:16.698142 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9653 11:46:16.701560 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9654 11:46:16.707723 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9655 11:46:16.711474 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9656 11:46:16.714714 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9657 11:46:16.718273 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9658 11:46:16.721695 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9659 11:46:16.728016 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9660 11:46:16.731590 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9661 11:46:16.738347 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9662 11:46:16.741402 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9663 11:46:16.745115 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9664 11:46:16.751957 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9665 11:46:16.755131 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9666 11:46:16.758058 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9667 11:46:16.764754 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9668 11:46:16.768070 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9669 11:46:16.775038 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9670 11:46:16.778238 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9671 11:46:16.782173 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9672 11:46:16.788162 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9673 11:46:16.791816 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9674 11:46:16.797985 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9675 11:46:16.801243 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9676 11:46:16.804800 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9677 11:46:16.811420 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9678 11:46:16.815034 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9679 11:46:16.821592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9680 11:46:16.825095 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9681 11:46:16.828566 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9682 11:46:16.834804 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9683 11:46:16.838169 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9684 11:46:16.841567 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9685 11:46:16.848165 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9686 11:46:16.851872 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9687 11:46:16.858144 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9688 11:46:16.861340 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9689 11:46:16.864632 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9690 11:46:16.871140 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9691 11:46:16.874585 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9692 11:46:16.880883 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9693 11:46:16.884354 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9694 11:46:16.887788 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9695 11:46:16.894803 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9696 11:46:16.898106 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9697 11:46:16.901647 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9698 11:46:16.908076 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9699 11:46:16.911635 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9700 11:46:16.917787 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9701 11:46:16.921165 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9702 11:46:16.924499 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9703 11:46:16.931111 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9704 11:46:16.934470 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9705 11:46:16.941087 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9706 11:46:16.944301 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9707 11:46:16.947980 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9708 11:46:16.954679 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9709 11:46:16.957777 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9710 11:46:16.964251 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9711 11:46:16.967680 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9712 11:46:16.970807 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9713 11:46:16.977563 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9714 11:46:16.981277 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9715 11:46:16.984208 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9716 11:46:16.990704 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9717 11:46:16.994095 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9718 11:46:17.000878 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9719 11:46:17.003936 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9720 11:46:17.010606 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9721 11:46:17.013618 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9722 11:46:17.016915 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9723 11:46:17.023329 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9724 11:46:17.026642 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9725 11:46:17.033444 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9726 11:46:17.036727 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9727 11:46:17.040311 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9728 11:46:17.046948 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9729 11:46:17.049994 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9730 11:46:17.056834 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9731 11:46:17.060230 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9732 11:46:17.063443 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9733 11:46:17.070059 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9734 11:46:17.073170 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9735 11:46:17.079959 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9736 11:46:17.083359 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9737 11:46:17.089995 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9738 11:46:17.093126 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9739 11:46:17.096311 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9740 11:46:17.102883 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9741 11:46:17.106262 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9742 11:46:17.113395 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9743 11:46:17.116201 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9744 11:46:17.119605 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9745 11:46:17.126056 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9746 11:46:17.129648 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9747 11:46:17.136384 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9748 11:46:17.139839 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9749 11:46:17.146050 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9750 11:46:17.149321 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9751 11:46:17.152913 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9752 11:46:17.159642 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9753 11:46:17.162546 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9754 11:46:17.169761 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9755 11:46:17.172854 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9756 11:46:17.179671 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9757 11:46:17.183245 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9758 11:46:17.186411 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9759 11:46:17.193241 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9760 11:46:17.196457 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9761 11:46:17.202935 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9762 11:46:17.206532 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9763 11:46:17.210224 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9764 11:46:17.216393 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9765 11:46:17.219591 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9766 11:46:17.222813 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9767 11:46:17.226271 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9768 11:46:17.233425 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9769 11:46:17.236283 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9770 11:46:17.239796 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9771 11:46:17.246275 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9772 11:46:17.250146 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9773 11:46:17.253236 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9774 11:46:17.260288 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9775 11:46:17.263559 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9776 11:46:17.266727 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9777 11:46:17.272909 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9778 11:46:17.276332 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9779 11:46:17.280392 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9780 11:46:17.286366 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9781 11:46:17.290312 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9782 11:46:17.296277 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9783 11:46:17.300125 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9784 11:46:17.302853 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9785 11:46:17.309722 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9786 11:46:17.313211 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9787 11:46:17.319862 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9788 11:46:17.322834 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9789 11:46:17.326104 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9790 11:46:17.332497 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9791 11:46:17.335907 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9792 11:46:17.339140 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9793 11:46:17.345997 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9794 11:46:17.349451 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9795 11:46:17.352401 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9796 11:46:17.359013 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9797 11:46:17.362484 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9798 11:46:17.369060 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9799 11:46:17.372210 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9800 11:46:17.375633 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9801 11:46:17.382283 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9802 11:46:17.385779 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9803 11:46:17.392042 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9804 11:46:17.395407 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9805 11:46:17.399035 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9806 11:46:17.401983 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9807 11:46:17.405276 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9808 11:46:17.412050 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9809 11:46:17.415665 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9810 11:46:17.418780 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9811 11:46:17.422072 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9812 11:46:17.428442 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9813 11:46:17.432093 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9814 11:46:17.435227 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9815 11:46:17.438452 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9816 11:46:17.444884 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9817 11:46:17.448541 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9818 11:46:17.451592 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9819 11:46:17.458490 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9820 11:46:17.461773 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9821 11:46:17.468724 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9822 11:46:17.472058 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9823 11:46:17.478295 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9824 11:46:17.482043 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9825 11:46:17.485076 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9826 11:46:17.492172 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9827 11:46:17.495256 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9828 11:46:17.498652 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9829 11:46:17.504878 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9830 11:46:17.508091 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9831 11:46:17.514895 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9832 11:46:17.518143 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9833 11:46:17.524744 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9834 11:46:17.528332 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9835 11:46:17.531310 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9836 11:46:17.538100 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9837 11:46:17.541062 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9838 11:46:17.547792 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9839 11:46:17.551095 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9840 11:46:17.554762 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9841 11:46:17.561532 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9842 11:46:17.564468 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9843 11:46:17.571452 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9844 11:46:17.574468 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9845 11:46:17.577670 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9846 11:46:17.584247 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9847 11:46:17.587742 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9848 11:46:17.594662 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9849 11:46:17.597747 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9850 11:46:17.600986 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9851 11:46:17.607909 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9852 11:46:17.611229 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9853 11:46:17.617598 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9854 11:46:17.620819 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9855 11:46:17.627474 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9856 11:46:17.631133 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9857 11:46:17.634086 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9858 11:46:17.640938 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9859 11:46:17.643952 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9860 11:46:17.650839 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9861 11:46:17.654319 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9862 11:46:17.657210 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9863 11:46:17.663759 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9864 11:46:17.667675 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9865 11:46:17.673734 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9866 11:46:17.677314 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9867 11:46:17.680624 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9868 11:46:17.687452 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9869 11:46:17.690875 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9870 11:46:17.696980 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9871 11:46:17.700641 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9872 11:46:17.706887 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9873 11:46:17.710451 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9874 11:46:17.713676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9875 11:46:17.719886 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9876 11:46:17.723747 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9877 11:46:17.729789 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9878 11:46:17.733250 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9879 11:46:17.736521 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9880 11:46:17.743519 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9881 11:46:17.746482 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9882 11:46:17.753543 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9883 11:46:17.756814 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9884 11:46:17.760464 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9885 11:46:17.766915 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9886 11:46:17.769979 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9887 11:46:17.776861 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9888 11:46:17.779770 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9889 11:46:17.783453 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9890 11:46:17.789789 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9891 11:46:17.793103 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9892 11:46:17.800153 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9893 11:46:17.803293 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9894 11:46:17.809728 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9895 11:46:17.813166 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9896 11:46:17.819825 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9897 11:46:17.823102 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9898 11:46:17.826474 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9899 11:46:17.833100 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9900 11:46:17.836260 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9901 11:46:17.842804 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9902 11:46:17.846295 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9903 11:46:17.852807 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9904 11:46:17.856307 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9905 11:46:17.859395 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9906 11:46:17.866306 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9907 11:46:17.869491 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9908 11:46:17.875983 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9909 11:46:17.879482 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9910 11:46:17.886177 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9911 11:46:17.889250 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9912 11:46:17.895749 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9913 11:46:17.899153 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9914 11:46:17.902726 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9915 11:46:17.909434 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9916 11:46:17.912685 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9917 11:46:17.919467 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9918 11:46:17.922310 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9919 11:46:17.929502 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9920 11:46:17.932576 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9921 11:46:17.935735 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9922 11:46:17.942501 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9923 11:46:17.945578 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9924 11:46:17.952089 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9925 11:46:17.955311 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9926 11:46:17.961905 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9927 11:46:17.965806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9928 11:46:17.971881 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9929 11:46:17.975467 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9930 11:46:17.978782 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9931 11:46:17.985528 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9932 11:46:17.988432 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9933 11:46:17.995131 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9934 11:46:17.999149 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9935 11:46:18.005290 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9936 11:46:18.008425 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9937 11:46:18.012064 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9938 11:46:18.018666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9939 11:46:18.021769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9940 11:46:18.028612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9941 11:46:18.032257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9942 11:46:18.038402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9943 11:46:18.041844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9944 11:46:18.048557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9945 11:46:18.051865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9946 11:46:18.055077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9947 11:46:18.061675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9948 11:46:18.065091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9949 11:46:18.071639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9950 11:46:18.074777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9951 11:46:18.081434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9952 11:46:18.084630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9953 11:46:18.091251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9954 11:46:18.094675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9955 11:46:18.101427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9956 11:46:18.104860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9957 11:46:18.111349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9958 11:46:18.114452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9959 11:46:18.121045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9960 11:46:18.124632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9961 11:46:18.130926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9962 11:46:18.134400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9963 11:46:18.141440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9964 11:46:18.144272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9965 11:46:18.150766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9966 11:46:18.154327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9967 11:46:18.160815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9968 11:46:18.164524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9969 11:46:18.170908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9970 11:46:18.173992 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9971 11:46:18.177345 INFO: [APUAPC] vio 0
9972 11:46:18.180821 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9973 11:46:18.187469 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9974 11:46:18.190649 INFO: [APUAPC] D0_APC_0: 0x400510
9975 11:46:18.193988 INFO: [APUAPC] D0_APC_1: 0x0
9976 11:46:18.197383 INFO: [APUAPC] D0_APC_2: 0x1540
9977 11:46:18.197456 INFO: [APUAPC] D0_APC_3: 0x0
9978 11:46:18.200863 INFO: [APUAPC] D1_APC_0: 0xffffffff
9979 11:46:18.203864 INFO: [APUAPC] D1_APC_1: 0xffffffff
9980 11:46:18.207328 INFO: [APUAPC] D1_APC_2: 0x3fffff
9981 11:46:18.210496 INFO: [APUAPC] D1_APC_3: 0x0
9982 11:46:18.213908 INFO: [APUAPC] D2_APC_0: 0xffffffff
9983 11:46:18.217046 INFO: [APUAPC] D2_APC_1: 0xffffffff
9984 11:46:18.220609 INFO: [APUAPC] D2_APC_2: 0x3fffff
9985 11:46:18.223904 INFO: [APUAPC] D2_APC_3: 0x0
9986 11:46:18.227078 INFO: [APUAPC] D3_APC_0: 0xffffffff
9987 11:46:18.230617 INFO: [APUAPC] D3_APC_1: 0xffffffff
9988 11:46:18.233840 INFO: [APUAPC] D3_APC_2: 0x3fffff
9989 11:46:18.236841 INFO: [APUAPC] D3_APC_3: 0x0
9990 11:46:18.240491 INFO: [APUAPC] D4_APC_0: 0xffffffff
9991 11:46:18.243756 INFO: [APUAPC] D4_APC_1: 0xffffffff
9992 11:46:18.246952 INFO: [APUAPC] D4_APC_2: 0x3fffff
9993 11:46:18.250275 INFO: [APUAPC] D4_APC_3: 0x0
9994 11:46:18.253780 INFO: [APUAPC] D5_APC_0: 0xffffffff
9995 11:46:18.256986 INFO: [APUAPC] D5_APC_1: 0xffffffff
9996 11:46:18.260316 INFO: [APUAPC] D5_APC_2: 0x3fffff
9997 11:46:18.263483 INFO: [APUAPC] D5_APC_3: 0x0
9998 11:46:18.266896 INFO: [APUAPC] D6_APC_0: 0xffffffff
9999 11:46:18.270004 INFO: [APUAPC] D6_APC_1: 0xffffffff
10000 11:46:18.273429 INFO: [APUAPC] D6_APC_2: 0x3fffff
10001 11:46:18.276643 INFO: [APUAPC] D6_APC_3: 0x0
10002 11:46:18.280035 INFO: [APUAPC] D7_APC_0: 0xffffffff
10003 11:46:18.283620 INFO: [APUAPC] D7_APC_1: 0xffffffff
10004 11:46:18.286483 INFO: [APUAPC] D7_APC_2: 0x3fffff
10005 11:46:18.290191 INFO: [APUAPC] D7_APC_3: 0x0
10006 11:46:18.293388 INFO: [APUAPC] D8_APC_0: 0xffffffff
10007 11:46:18.297038 INFO: [APUAPC] D8_APC_1: 0xffffffff
10008 11:46:18.300250 INFO: [APUAPC] D8_APC_2: 0x3fffff
10009 11:46:18.303404 INFO: [APUAPC] D8_APC_3: 0x0
10010 11:46:18.307394 INFO: [APUAPC] D9_APC_0: 0xffffffff
10011 11:46:18.310338 INFO: [APUAPC] D9_APC_1: 0xffffffff
10012 11:46:18.313533 INFO: [APUAPC] D9_APC_2: 0x3fffff
10013 11:46:18.316954 INFO: [APUAPC] D9_APC_3: 0x0
10014 11:46:18.320234 INFO: [APUAPC] D10_APC_0: 0xffffffff
10015 11:46:18.323880 INFO: [APUAPC] D10_APC_1: 0xffffffff
10016 11:46:18.326976 INFO: [APUAPC] D10_APC_2: 0x3fffff
10017 11:46:18.330273 INFO: [APUAPC] D10_APC_3: 0x0
10018 11:46:18.333373 INFO: [APUAPC] D11_APC_0: 0xffffffff
10019 11:46:18.336589 INFO: [APUAPC] D11_APC_1: 0xffffffff
10020 11:46:18.340380 INFO: [APUAPC] D11_APC_2: 0x3fffff
10021 11:46:18.343471 INFO: [APUAPC] D11_APC_3: 0x0
10022 11:46:18.346586 INFO: [APUAPC] D12_APC_0: 0xffffffff
10023 11:46:18.349859 INFO: [APUAPC] D12_APC_1: 0xffffffff
10024 11:46:18.353172 INFO: [APUAPC] D12_APC_2: 0x3fffff
10025 11:46:18.356547 INFO: [APUAPC] D12_APC_3: 0x0
10026 11:46:18.359906 INFO: [APUAPC] D13_APC_0: 0xffffffff
10027 11:46:18.363052 INFO: [APUAPC] D13_APC_1: 0xffffffff
10028 11:46:18.366710 INFO: [APUAPC] D13_APC_2: 0x3fffff
10029 11:46:18.369989 INFO: [APUAPC] D13_APC_3: 0x0
10030 11:46:18.372976 INFO: [APUAPC] D14_APC_0: 0xffffffff
10031 11:46:18.376706 INFO: [APUAPC] D14_APC_1: 0xffffffff
10032 11:46:18.379841 INFO: [APUAPC] D14_APC_2: 0x3fffff
10033 11:46:18.383045 INFO: [APUAPC] D14_APC_3: 0x0
10034 11:46:18.386646 INFO: [APUAPC] D15_APC_0: 0xffffffff
10035 11:46:18.390049 INFO: [APUAPC] D15_APC_1: 0xffffffff
10036 11:46:18.393215 INFO: [APUAPC] D15_APC_2: 0x3fffff
10037 11:46:18.396342 INFO: [APUAPC] D15_APC_3: 0x0
10038 11:46:18.399571 INFO: [APUAPC] APC_CON: 0x4
10039 11:46:18.403051 INFO: [NOCDAPC] D0_APC_0: 0x0
10040 11:46:18.403134 INFO: [NOCDAPC] D0_APC_1: 0x0
10041 11:46:18.406654 INFO: [NOCDAPC] D1_APC_0: 0x0
10042 11:46:18.409477 INFO: [NOCDAPC] D1_APC_1: 0xfff
10043 11:46:18.413205 INFO: [NOCDAPC] D2_APC_0: 0x0
10044 11:46:18.416447 INFO: [NOCDAPC] D2_APC_1: 0xfff
10045 11:46:18.419611 INFO: [NOCDAPC] D3_APC_0: 0x0
10046 11:46:18.422753 INFO: [NOCDAPC] D3_APC_1: 0xfff
10047 11:46:18.426304 INFO: [NOCDAPC] D4_APC_0: 0x0
10048 11:46:18.429614 INFO: [NOCDAPC] D4_APC_1: 0xfff
10049 11:46:18.432837 INFO: [NOCDAPC] D5_APC_0: 0x0
10050 11:46:18.432908 INFO: [NOCDAPC] D5_APC_1: 0xfff
10051 11:46:18.436122 INFO: [NOCDAPC] D6_APC_0: 0x0
10052 11:46:18.439646 INFO: [NOCDAPC] D6_APC_1: 0xfff
10053 11:46:18.442758 INFO: [NOCDAPC] D7_APC_0: 0x0
10054 11:46:18.446374 INFO: [NOCDAPC] D7_APC_1: 0xfff
10055 11:46:18.449381 INFO: [NOCDAPC] D8_APC_0: 0x0
10056 11:46:18.452968 INFO: [NOCDAPC] D8_APC_1: 0xfff
10057 11:46:18.456404 INFO: [NOCDAPC] D9_APC_0: 0x0
10058 11:46:18.459828 INFO: [NOCDAPC] D9_APC_1: 0xfff
10059 11:46:18.462607 INFO: [NOCDAPC] D10_APC_0: 0x0
10060 11:46:18.465990 INFO: [NOCDAPC] D10_APC_1: 0xfff
10061 11:46:18.469952 INFO: [NOCDAPC] D11_APC_0: 0x0
10062 11:46:18.470026 INFO: [NOCDAPC] D11_APC_1: 0xfff
10063 11:46:18.472753 INFO: [NOCDAPC] D12_APC_0: 0x0
10064 11:46:18.476525 INFO: [NOCDAPC] D12_APC_1: 0xfff
10065 11:46:18.479471 INFO: [NOCDAPC] D13_APC_0: 0x0
10066 11:46:18.482934 INFO: [NOCDAPC] D13_APC_1: 0xfff
10067 11:46:18.486355 INFO: [NOCDAPC] D14_APC_0: 0x0
10068 11:46:18.489529 INFO: [NOCDAPC] D14_APC_1: 0xfff
10069 11:46:18.492946 INFO: [NOCDAPC] D15_APC_0: 0x0
10070 11:46:18.495865 INFO: [NOCDAPC] D15_APC_1: 0xfff
10071 11:46:18.499369 INFO: [NOCDAPC] APC_CON: 0x4
10072 11:46:18.502843 INFO: [APUAPC] set_apusys_apc done
10073 11:46:18.506281 INFO: [DEVAPC] devapc_init done
10074 11:46:18.509226 INFO: GICv3 without legacy support detected.
10075 11:46:18.512720 INFO: ARM GICv3 driver initialized in EL3
10076 11:46:18.516238 INFO: Maximum SPI INTID supported: 639
10077 11:46:18.522709 INFO: BL31: Initializing runtime services
10078 11:46:18.525883 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10079 11:46:18.529507 INFO: SPM: enable CPC mode
10080 11:46:18.536040 INFO: mcdi ready for mcusys-off-idle and system suspend
10081 11:46:18.539206 INFO: BL31: Preparing for EL3 exit to normal world
10082 11:46:18.542751 INFO: Entry point address = 0x80000000
10083 11:46:18.545741 INFO: SPSR = 0x8
10084 11:46:18.550781
10085 11:46:18.550898
10086 11:46:18.551008
10087 11:46:18.554460 Starting depthcharge on Spherion...
10088 11:46:18.554545
10089 11:46:18.554612 Wipe memory regions:
10090 11:46:18.554674
10091 11:46:18.555294 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10092 11:46:18.555399 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10093 11:46:18.555485 Setting prompt string to ['asurada:']
10094 11:46:18.555565 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10095 11:46:18.557452 [0x00000040000000, 0x00000054600000)
10096 11:46:18.680054
10097 11:46:18.680204 [0x00000054660000, 0x00000080000000)
10098 11:46:18.940194
10099 11:46:18.940349 [0x000000821a7280, 0x000000ffe64000)
10100 11:46:19.685282
10101 11:46:19.685811 [0x00000100000000, 0x00000240000000)
10102 11:46:21.575637
10103 11:46:21.578997 Initializing XHCI USB controller at 0x11200000.
10104 11:46:22.617099
10105 11:46:22.620269 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10106 11:46:22.620756
10107 11:46:22.621160
10108 11:46:22.621542
10109 11:46:22.622356 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10111 11:46:22.723620 asurada: tftpboot 192.168.201.1 12074003/tftp-deploy-updl6c3y/kernel/image.itb 12074003/tftp-deploy-updl6c3y/kernel/cmdline
10112 11:46:22.723930 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10113 11:46:22.724123 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10114 11:46:22.728631 tftpboot 192.168.201.1 12074003/tftp-deploy-updl6c3y/kernel/image.itp-deploy-updl6c3y/kernel/cmdline
10115 11:46:22.728986
10116 11:46:22.729194 Waiting for link
10117 11:46:22.888713
10118 11:46:22.888877 R8152: Initializing
10119 11:46:22.888982
10120 11:46:22.892035 Version 9 (ocp_data = 6010)
10121 11:46:22.892150
10122 11:46:22.895560 R8152: Done initializing
10123 11:46:22.895646
10124 11:46:22.895713 Adding net device
10125 11:46:24.838109
10126 11:46:24.838737 done.
10127 11:46:24.839138
10128 11:46:24.839581 MAC: 00:e0:4c:72:2d:d6
10129 11:46:24.840101
10130 11:46:24.841344 Sending DHCP discover... done.
10131 11:46:24.841824
10132 11:46:27.955883 Waiting for reply... done.
10133 11:46:27.956030
10134 11:46:27.956105 Sending DHCP request... done.
10135 11:46:27.958127
10136 11:46:27.978020 Waiting for reply... done.
10137 11:46:27.978145
10138 11:46:27.978246 My ip is 192.168.201.21
10139 11:46:27.978341
10140 11:46:27.981453 The DHCP server ip is 192.168.201.1
10141 11:46:27.981880
10142 11:46:27.988364 TFTP server IP predefined by user: 192.168.201.1
10143 11:46:27.988820
10144 11:46:27.995023 Bootfile predefined by user: 12074003/tftp-deploy-updl6c3y/kernel/image.itb
10145 11:46:27.995607
10146 11:46:27.996055 Sending tftp read request... done.
10147 11:46:27.998183
10148 11:46:27.998792 Waiting for the transfer...
10149 11:46:27.999208
10150 11:46:28.332622 00000000 ################################################################
10151 11:46:28.332770
10152 11:46:28.618297 00080000 ################################################################
10153 11:46:28.618471
10154 11:46:28.888509 00100000 ################################################################
10155 11:46:28.888673
10156 11:46:29.136012 00180000 ################################################################
10157 11:46:29.136157
10158 11:46:29.391471 00200000 ################################################################
10159 11:46:29.391616
10160 11:46:29.645630 00280000 ################################################################
10161 11:46:29.645769
10162 11:46:29.909494 00300000 ################################################################
10163 11:46:29.909635
10164 11:46:30.193382 00380000 ################################################################
10165 11:46:30.193519
10166 11:46:30.489806 00400000 ################################################################
10167 11:46:30.489943
10168 11:46:30.776604 00480000 ################################################################
10169 11:46:30.776744
10170 11:46:31.040173 00500000 ################################################################
10171 11:46:31.040318
10172 11:46:31.290965 00580000 ################################################################
10173 11:46:31.291110
10174 11:46:31.555356 00600000 ################################################################
10175 11:46:31.555510
10176 11:46:31.810722 00680000 ################################################################
10177 11:46:31.810867
10178 11:46:32.087219 00700000 ################################################################
10179 11:46:32.087378
10180 11:46:32.359276 00780000 ################################################################
10181 11:46:32.359414
10182 11:46:32.609926 00800000 ################################################################
10183 11:46:32.610062
10184 11:46:32.857585 00880000 ################################################################
10185 11:46:32.857736
10186 11:46:33.107865 00900000 ################################################################
10187 11:46:33.108068
10188 11:46:33.376092 00980000 ################################################################
10189 11:46:33.376229
10190 11:46:33.635176 00a00000 ################################################################
10191 11:46:33.635330
10192 11:46:33.885020 00a80000 ################################################################
10193 11:46:33.885168
10194 11:46:34.135317 00b00000 ################################################################
10195 11:46:34.135471
10196 11:46:34.405188 00b80000 ################################################################
10197 11:46:34.405327
10198 11:46:34.666064 00c00000 ################################################################
10199 11:46:34.666202
10200 11:46:34.914347 00c80000 ################################################################
10201 11:46:34.914543
10202 11:46:35.166537 00d00000 ################################################################
10203 11:46:35.166694
10204 11:46:35.418354 00d80000 ################################################################
10205 11:46:35.418564
10206 11:46:35.669501 00e00000 ################################################################
10207 11:46:35.669653
10208 11:46:35.924848 00e80000 ################################################################
10209 11:46:35.924990
10210 11:46:36.167533 00f00000 ################################################################
10211 11:46:36.167684
10212 11:46:36.413780 00f80000 ################################################################
10213 11:46:36.413971
10214 11:46:36.658562 01000000 ################################################################
10215 11:46:36.658710
10216 11:46:36.910185 01080000 ################################################################
10217 11:46:36.910365
10218 11:46:37.166324 01100000 ################################################################
10219 11:46:37.166504
10220 11:46:37.416565 01180000 ################################################################
10221 11:46:37.416733
10222 11:46:37.663080 01200000 ################################################################
10223 11:46:37.663233
10224 11:46:37.918851 01280000 ################################################################
10225 11:46:37.919012
10226 11:46:38.170380 01300000 ################################################################
10227 11:46:38.170522
10228 11:46:38.416520 01380000 ################################################################
10229 11:46:38.416705
10230 11:46:38.676641 01400000 ################################################################
10231 11:46:38.676820
10232 11:46:38.920579 01480000 ################################################################
10233 11:46:38.920748
10234 11:46:39.175007 01500000 ################################################################
10235 11:46:39.175163
10236 11:46:39.444585 01580000 ################################################################
10237 11:46:39.444750
10238 11:46:39.729163 01600000 ################################################################
10239 11:46:39.729326
10240 11:46:40.010475 01680000 ################################################################
10241 11:46:40.010618
10242 11:46:40.269817 01700000 ################################################################
10243 11:46:40.269998
10244 11:46:40.518286 01780000 ################################################################
10245 11:46:40.518451
10246 11:46:40.766110 01800000 ################################################################
10247 11:46:40.766254
10248 11:46:41.018002 01880000 ################################################################
10249 11:46:41.018136
10250 11:46:41.269876 01900000 ################################################################
10251 11:46:41.270045
10252 11:46:41.523054 01980000 ################################################################
10253 11:46:41.523197
10254 11:46:41.775906 01a00000 ################################################################
10255 11:46:41.776046
10256 11:46:42.028161 01a80000 ################################################################
10257 11:46:42.028324
10258 11:46:42.279296 01b00000 ################################################################
10259 11:46:42.279439
10260 11:46:42.307475 01b80000 ######## done.
10261 11:46:42.310698
10262 11:46:42.310805 The bootfile was 28899098 bytes long.
10263 11:46:42.314187
10264 11:46:42.314273 Sending tftp read request... done.
10265 11:46:42.314341
10266 11:46:42.317360 Waiting for the transfer...
10267 11:46:42.317446
10268 11:46:42.320790 00000000 # done.
10269 11:46:42.320878
10270 11:46:42.327332 Command line loaded dynamically from TFTP file: 12074003/tftp-deploy-updl6c3y/kernel/cmdline
10271 11:46:42.327425
10272 11:46:42.350569 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12074003/extract-nfsrootfs-50snkza6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10273 11:46:42.350736
10274 11:46:42.350848 Loading FIT.
10275 11:46:42.350953
10276 11:46:42.353938 Image ramdisk-1 has 17801538 bytes.
10277 11:46:42.354080
10278 11:46:42.357200 Image fdt-1 has 47278 bytes.
10279 11:46:42.357360
10280 11:46:42.360316 Image kernel-1 has 11048246 bytes.
10281 11:46:42.360488
10282 11:46:42.367070 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10283 11:46:42.367336
10284 11:46:42.387338 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10285 11:46:42.387441
10286 11:46:42.390378 Choosing best match conf-1 for compat google,spherion-rev2.
10287 11:46:42.395678
10288 11:46:42.400333 Connected to device vid:did:rid of 1ae0:0028:00
10289 11:46:42.408592
10290 11:46:42.411694 tpm_get_response: command 0x17b, return code 0x0
10291 11:46:42.411849
10292 11:46:42.414790 ec_init: CrosEC protocol v3 supported (256, 248)
10293 11:46:42.419522
10294 11:46:42.422714 tpm_cleanup: add release locality here.
10295 11:46:42.423008
10296 11:46:42.423186 Shutting down all USB controllers.
10297 11:46:42.425702
10298 11:46:42.425911 Removing current net device
10299 11:46:42.426074
10300 11:46:42.432876 Exiting depthcharge with code 4 at timestamp: 53162830
10301 11:46:42.433264
10302 11:46:42.436190 LZMA decompressing kernel-1 to 0x821a6718
10303 11:46:42.436492
10304 11:46:42.439526 LZMA decompressing kernel-1 to 0x40000000
10305 11:46:43.827876
10306 11:46:43.828550 jumping to kernel
10307 11:46:43.830529 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10308 11:46:43.831073 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
10309 11:46:43.831494 Setting prompt string to ['Linux version [0-9]']
10310 11:46:43.831882 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10311 11:46:43.832264 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10312 11:46:43.909642
10313 11:46:43.913036 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10314 11:46:43.916702 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
10315 11:46:43.917327 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10316 11:46:43.917735 Setting prompt string to []
10317 11:46:43.918158 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10318 11:46:43.918632 Using line separator: #'\n'#
10319 11:46:43.918978 No login prompt set.
10320 11:46:43.919322 Parsing kernel messages
10321 11:46:43.919636 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10322 11:46:43.920203 [login-action] Waiting for messages, (timeout 00:04:00)
10323 11:46:43.936016 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10324 11:46:43.939343 [ 0.000000] random: crng init done
10325 11:46:43.945796 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10326 11:46:43.949787 [ 0.000000] efi: UEFI not found.
10327 11:46:43.955774 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10328 11:46:43.962127 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10329 11:46:43.972344 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10330 11:46:43.981810 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10331 11:46:43.988792 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10332 11:46:43.995950 [ 0.000000] printk: bootconsole [mtk8250] enabled
10333 11:46:44.002506 [ 0.000000] NUMA: No NUMA configuration found
10334 11:46:44.009190 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10335 11:46:44.012526 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10336 11:46:44.015419 [ 0.000000] Zone ranges:
10337 11:46:44.022478 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10338 11:46:44.025673 [ 0.000000] DMA32 empty
10339 11:46:44.032329 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10340 11:46:44.035380 [ 0.000000] Movable zone start for each node
10341 11:46:44.038769 [ 0.000000] Early memory node ranges
10342 11:46:44.045963 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10343 11:46:44.052176 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10344 11:46:44.059251 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10345 11:46:44.062170 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10346 11:46:44.068863 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10347 11:46:44.075198 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10348 11:46:44.133508 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10349 11:46:44.140632 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10350 11:46:44.147270 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10351 11:46:44.150284 [ 0.000000] psci: probing for conduit method from DT.
10352 11:46:44.157131 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10353 11:46:44.160529 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10354 11:46:44.166946 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10355 11:46:44.170161 [ 0.000000] psci: SMC Calling Convention v1.2
10356 11:46:44.176714 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10357 11:46:44.180127 [ 0.000000] Detected VIPT I-cache on CPU0
10358 11:46:44.186940 [ 0.000000] CPU features: detected: GIC system register CPU interface
10359 11:46:44.193644 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10360 11:46:44.200271 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10361 11:46:44.206490 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10362 11:46:44.213320 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10363 11:46:44.223075 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10364 11:46:44.226258 [ 0.000000] alternatives: applying boot alternatives
10365 11:46:44.233031 [ 0.000000] Fallback order for Node 0: 0
10366 11:46:44.239382 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10367 11:46:44.242662 [ 0.000000] Policy zone: Normal
10368 11:46:44.266257 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12074003/extract-nfsrootfs-50snkza6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10369 11:46:44.276105 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10370 11:46:44.286725 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10371 11:46:44.296692 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10372 11:46:44.303356 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10373 11:46:44.306334 <6>[ 0.000000] software IO TLB: area num 8.
10374 11:46:44.362732 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10375 11:46:44.511918 <6>[ 0.000000] Memory: 7952236K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400532K reserved, 32768K cma-reserved)
10376 11:46:44.518664 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10377 11:46:44.525486 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10378 11:46:44.528597 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10379 11:46:44.535259 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10380 11:46:44.541861 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10381 11:46:44.545159 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10382 11:46:44.555212 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10383 11:46:44.561792 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10384 11:46:44.564843 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10385 11:46:44.572587 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10386 11:46:44.575964 <6>[ 0.000000] GICv3: 608 SPIs implemented
10387 11:46:44.583028 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10388 11:46:44.586020 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10389 11:46:44.589443 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10390 11:46:44.599644 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10391 11:46:44.609566 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10392 11:46:44.622941 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10393 11:46:44.629219 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10394 11:46:44.638425 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10395 11:46:44.651569 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10396 11:46:44.657927 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10397 11:46:44.664602 <6>[ 0.009230] Console: colour dummy device 80x25
10398 11:46:44.674720 <6>[ 0.013955] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10399 11:46:44.678130 <6>[ 0.024398] pid_max: default: 32768 minimum: 301
10400 11:46:44.684592 <6>[ 0.029271] LSM: Security Framework initializing
10401 11:46:44.691303 <6>[ 0.034209] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10402 11:46:44.701668 <6>[ 0.042071] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 11:46:44.708128 <6>[ 0.051473] cblist_init_generic: Setting adjustable number of callback queues.
10404 11:46:44.714703 <6>[ 0.058961] cblist_init_generic: Setting shift to 3 and lim to 1.
10405 11:46:44.724652 <6>[ 0.065323] cblist_init_generic: Setting adjustable number of callback queues.
10406 11:46:44.728156 <6>[ 0.072749] cblist_init_generic: Setting shift to 3 and lim to 1.
10407 11:46:44.734595 <6>[ 0.079150] rcu: Hierarchical SRCU implementation.
10408 11:46:44.741338 <6>[ 0.084165] rcu: Max phase no-delay instances is 1000.
10409 11:46:44.747967 <6>[ 0.091222] EFI services will not be available.
10410 11:46:44.751265 <6>[ 0.096176] smp: Bringing up secondary CPUs ...
10411 11:46:44.758972 <6>[ 0.101223] Detected VIPT I-cache on CPU1
10412 11:46:44.765761 <6>[ 0.101293] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10413 11:46:44.772339 <6>[ 0.101325] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10414 11:46:44.775446 <6>[ 0.101664] Detected VIPT I-cache on CPU2
10415 11:46:44.782237 <6>[ 0.101717] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10416 11:46:44.788666 <6>[ 0.101735] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10417 11:46:44.795395 <6>[ 0.101993] Detected VIPT I-cache on CPU3
10418 11:46:44.802020 <6>[ 0.102038] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10419 11:46:44.808525 <6>[ 0.102051] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10420 11:46:44.812275 <6>[ 0.102352] CPU features: detected: Spectre-v4
10421 11:46:44.818453 <6>[ 0.102359] CPU features: detected: Spectre-BHB
10422 11:46:44.821941 <6>[ 0.102364] Detected PIPT I-cache on CPU4
10423 11:46:44.828891 <6>[ 0.102422] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10424 11:46:44.835536 <6>[ 0.102439] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10425 11:46:44.842143 <6>[ 0.102736] Detected PIPT I-cache on CPU5
10426 11:46:44.849066 <6>[ 0.102802] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10427 11:46:44.855272 <6>[ 0.102818] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10428 11:46:44.858709 <6>[ 0.103097] Detected PIPT I-cache on CPU6
10429 11:46:44.865241 <6>[ 0.103157] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10430 11:46:44.872320 <6>[ 0.103172] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10431 11:46:44.878564 <6>[ 0.103456] Detected PIPT I-cache on CPU7
10432 11:46:44.885544 <6>[ 0.103517] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10433 11:46:44.892094 <6>[ 0.103533] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10434 11:46:44.895257 <6>[ 0.103580] smp: Brought up 1 node, 8 CPUs
10435 11:46:44.902089 <6>[ 0.244884] SMP: Total of 8 processors activated.
10436 11:46:44.905632 <6>[ 0.249805] CPU features: detected: 32-bit EL0 Support
10437 11:46:44.915489 <6>[ 0.255168] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10438 11:46:44.922183 <6>[ 0.263968] CPU features: detected: Common not Private translations
10439 11:46:44.925384 <6>[ 0.270444] CPU features: detected: CRC32 instructions
10440 11:46:44.932316 <6>[ 0.275795] CPU features: detected: RCpc load-acquire (LDAPR)
10441 11:46:44.938491 <6>[ 0.281755] CPU features: detected: LSE atomic instructions
10442 11:46:44.945284 <6>[ 0.287536] CPU features: detected: Privileged Access Never
10443 11:46:44.948827 <6>[ 0.293316] CPU features: detected: RAS Extension Support
10444 11:46:44.955461 <6>[ 0.298925] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10445 11:46:44.962447 <6>[ 0.306143] CPU: All CPU(s) started at EL2
10446 11:46:44.968599 <6>[ 0.310460] alternatives: applying system-wide alternatives
10447 11:46:44.976884 <6>[ 0.321158] devtmpfs: initialized
10448 11:46:44.989429 <6>[ 0.330135] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10449 11:46:44.999467 <6>[ 0.340099] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10450 11:46:45.005884 <6>[ 0.348360] pinctrl core: initialized pinctrl subsystem
10451 11:46:45.009579 <6>[ 0.355143] DMI not present or invalid.
10452 11:46:45.015875 <6>[ 0.359558] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10453 11:46:45.025703 <6>[ 0.366451] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10454 11:46:45.032748 <6>[ 0.374031] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10455 11:46:45.042486 <6>[ 0.382257] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10456 11:46:45.045816 <6>[ 0.390501] audit: initializing netlink subsys (disabled)
10457 11:46:45.055787 <5>[ 0.396192] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10458 11:46:45.062800 <6>[ 0.396934] thermal_sys: Registered thermal governor 'step_wise'
10459 11:46:45.068795 <6>[ 0.404160] thermal_sys: Registered thermal governor 'power_allocator'
10460 11:46:45.072382 <6>[ 0.410417] cpuidle: using governor menu
10461 11:46:45.078829 <6>[ 0.421380] NET: Registered PF_QIPCRTR protocol family
10462 11:46:45.085403 <6>[ 0.426876] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10463 11:46:45.092032 <6>[ 0.433979] ASID allocator initialised with 32768 entries
10464 11:46:45.095397 <6>[ 0.440595] Serial: AMBA PL011 UART driver
10465 11:46:45.105425 <4>[ 0.449773] Trying to register duplicate clock ID: 134
10466 11:46:45.162460 <6>[ 0.509978] KASLR enabled
10467 11:46:45.176882 <6>[ 0.517711] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10468 11:46:45.183388 <6>[ 0.524725] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10469 11:46:45.190149 <6>[ 0.531212] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10470 11:46:45.196873 <6>[ 0.538216] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10471 11:46:45.203104 <6>[ 0.544703] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10472 11:46:45.210084 <6>[ 0.551706] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10473 11:46:45.216594 <6>[ 0.558193] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10474 11:46:45.223126 <6>[ 0.565200] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10475 11:46:45.226699 <6>[ 0.572664] ACPI: Interpreter disabled.
10476 11:46:45.235055 <6>[ 0.579149] iommu: Default domain type: Translated
10477 11:46:45.241850 <6>[ 0.584261] iommu: DMA domain TLB invalidation policy: strict mode
10478 11:46:45.245103 <5>[ 0.590918] SCSI subsystem initialized
10479 11:46:45.251806 <6>[ 0.595082] usbcore: registered new interface driver usbfs
10480 11:46:45.257761 <6>[ 0.600813] usbcore: registered new interface driver hub
10481 11:46:45.261480 <6>[ 0.606363] usbcore: registered new device driver usb
10482 11:46:45.268183 <6>[ 0.612508] pps_core: LinuxPPS API ver. 1 registered
10483 11:46:45.277749 <6>[ 0.617702] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10484 11:46:45.281119 <6>[ 0.627049] PTP clock support registered
10485 11:46:45.284371 <6>[ 0.631294] EDAC MC: Ver: 3.0.0
10486 11:46:45.291699 <6>[ 0.636489] FPGA manager framework
10487 11:46:45.298984 <6>[ 0.640169] Advanced Linux Sound Architecture Driver Initialized.
10488 11:46:45.302054 <6>[ 0.646943] vgaarb: loaded
10489 11:46:45.308749 <6>[ 0.650132] clocksource: Switched to clocksource arch_sys_counter
10490 11:46:45.312000 <5>[ 0.656555] VFS: Disk quotas dquot_6.6.0
10491 11:46:45.318948 <6>[ 0.660737] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10492 11:46:45.322220 <6>[ 0.667922] pnp: PnP ACPI: disabled
10493 11:46:45.330882 <6>[ 0.674556] NET: Registered PF_INET protocol family
10494 11:46:45.340446 <6>[ 0.680140] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10495 11:46:45.351529 <6>[ 0.692415] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10496 11:46:45.361136 <6>[ 0.701227] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10497 11:46:45.367941 <6>[ 0.709197] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10498 11:46:45.374192 <6>[ 0.717898] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10499 11:46:45.386668 <6>[ 0.727645] TCP: Hash tables configured (established 65536 bind 65536)
10500 11:46:45.392941 <6>[ 0.734504] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10501 11:46:45.399730 <6>[ 0.741703] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10502 11:46:45.406408 <6>[ 0.749401] NET: Registered PF_UNIX/PF_LOCAL protocol family
10503 11:46:45.412966 <6>[ 0.755579] RPC: Registered named UNIX socket transport module.
10504 11:46:45.416435 <6>[ 0.761733] RPC: Registered udp transport module.
10505 11:46:45.423104 <6>[ 0.766665] RPC: Registered tcp transport module.
10506 11:46:45.429341 <6>[ 0.771598] RPC: Registered tcp NFSv4.1 backchannel transport module.
10507 11:46:45.432726 <6>[ 0.778264] PCI: CLS 0 bytes, default 64
10508 11:46:45.436101 <6>[ 0.782659] Unpacking initramfs...
10509 11:46:45.461350 <6>[ 0.802218] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10510 11:46:45.471477 <6>[ 0.810874] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10511 11:46:45.474430 <6>[ 0.819749] kvm [1]: IPA Size Limit: 40 bits
10512 11:46:45.481315 <6>[ 0.824276] kvm [1]: GICv3: no GICV resource entry
10513 11:46:45.484437 <6>[ 0.829297] kvm [1]: disabling GICv2 emulation
10514 11:46:45.491055 <6>[ 0.833987] kvm [1]: GIC system register CPU interface enabled
10515 11:46:45.494381 <6>[ 0.840152] kvm [1]: vgic interrupt IRQ18
10516 11:46:45.501146 <6>[ 0.844504] kvm [1]: VHE mode initialized successfully
10517 11:46:45.507630 <5>[ 0.851021] Initialise system trusted keyrings
10518 11:46:45.514032 <6>[ 0.855893] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10519 11:46:45.521470 <6>[ 0.865905] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10520 11:46:45.528237 <5>[ 0.872352] NFS: Registering the id_resolver key type
10521 11:46:45.531650 <5>[ 0.877655] Key type id_resolver registered
10522 11:46:45.538776 <5>[ 0.882072] Key type id_legacy registered
10523 11:46:45.544495 <6>[ 0.886347] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10524 11:46:45.551383 <6>[ 0.893270] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10525 11:46:45.558304 <6>[ 0.900978] 9p: Installing v9fs 9p2000 file system support
10526 11:46:45.594770 <5>[ 0.938852] Key type asymmetric registered
10527 11:46:45.597780 <5>[ 0.943182] Asymmetric key parser 'x509' registered
10528 11:46:45.607609 <6>[ 0.948323] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10529 11:46:45.611246 <6>[ 0.955937] io scheduler mq-deadline registered
10530 11:46:45.614649 <6>[ 0.960718] io scheduler kyber registered
10531 11:46:45.633979 <6>[ 0.978331] EINJ: ACPI disabled.
10532 11:46:45.667638 <4>[ 1.005323] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10533 11:46:45.677514 <4>[ 1.015994] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10534 11:46:45.692960 <6>[ 1.037186] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10535 11:46:45.700794 <6>[ 1.045284] printk: console [ttyS0] disabled
10536 11:46:45.728819 <6>[ 1.069956] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10537 11:46:45.735907 <6>[ 1.079433] printk: console [ttyS0] enabled
10538 11:46:45.739221 <6>[ 1.079433] printk: console [ttyS0] enabled
10539 11:46:45.745806 <6>[ 1.088329] printk: bootconsole [mtk8250] disabled
10540 11:46:45.748763 <6>[ 1.088329] printk: bootconsole [mtk8250] disabled
10541 11:46:45.755655 <6>[ 1.099581] SuperH (H)SCI(F) driver initialized
10542 11:46:45.758847 <6>[ 1.104894] msm_serial: driver initialized
10543 11:46:45.773144 <6>[ 1.114034] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10544 11:46:45.782902 <6>[ 1.122590] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10545 11:46:45.789783 <6>[ 1.131139] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10546 11:46:45.799723 <6>[ 1.139770] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10547 11:46:45.806230 <6>[ 1.148478] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10548 11:46:45.816149 <6>[ 1.157192] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10549 11:46:45.826327 <6>[ 1.165735] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10550 11:46:45.832819 <6>[ 1.174542] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10551 11:46:45.842631 <6>[ 1.183086] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10552 11:46:45.854844 <6>[ 1.198986] loop: module loaded
10553 11:46:45.861346 <6>[ 1.205105] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10554 11:46:45.884374 <4>[ 1.228589] mtk-pmic-keys: Failed to locate of_node [id: -1]
10555 11:46:45.891251 <6>[ 1.235504] megasas: 07.719.03.00-rc1
10556 11:46:45.900589 <6>[ 1.245081] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10557 11:46:45.909302 <6>[ 1.253508] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10558 11:46:45.925968 <6>[ 1.270052] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10559 11:46:45.982123 <6>[ 1.319887] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10560 11:46:46.175593 <6>[ 1.519605] Freeing initrd memory: 17380K
10561 11:46:46.185721 <6>[ 1.530076] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10562 11:46:46.196708 <6>[ 1.541036] tun: Universal TUN/TAP device driver, 1.6
10563 11:46:46.200307 <6>[ 1.547137] thunder_xcv, ver 1.0
10564 11:46:46.203449 <6>[ 1.550640] thunder_bgx, ver 1.0
10565 11:46:46.206751 <6>[ 1.554134] nicpf, ver 1.0
10566 11:46:46.217139 <6>[ 1.558188] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10567 11:46:46.220947 <6>[ 1.565667] hns3: Copyright (c) 2017 Huawei Corporation.
10568 11:46:46.223853 <6>[ 1.571254] hclge is initializing
10569 11:46:46.230688 <6>[ 1.574834] e1000: Intel(R) PRO/1000 Network Driver
10570 11:46:46.237501 <6>[ 1.579964] e1000: Copyright (c) 1999-2006 Intel Corporation.
10571 11:46:46.240408 <6>[ 1.585979] e1000e: Intel(R) PRO/1000 Network Driver
10572 11:46:46.247483 <6>[ 1.591195] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10573 11:46:46.253649 <6>[ 1.597380] igb: Intel(R) Gigabit Ethernet Network Driver
10574 11:46:46.260347 <6>[ 1.603030] igb: Copyright (c) 2007-2014 Intel Corporation.
10575 11:46:46.267070 <6>[ 1.608866] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10576 11:46:46.273734 <6>[ 1.615383] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10577 11:46:46.276851 <6>[ 1.621854] sky2: driver version 1.30
10578 11:46:46.283895 <6>[ 1.626892] VFIO - User Level meta-driver version: 0.3
10579 11:46:46.290981 <6>[ 1.635261] usbcore: registered new interface driver usb-storage
10580 11:46:46.297483 <6>[ 1.641705] usbcore: registered new device driver onboard-usb-hub
10581 11:46:46.306865 <6>[ 1.650929] mt6397-rtc mt6359-rtc: registered as rtc0
10582 11:46:46.316902 <6>[ 1.656398] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:46:12 UTC (1700826372)
10583 11:46:46.320295 <6>[ 1.666024] i2c_dev: i2c /dev entries driver
10584 11:46:46.337303 <6>[ 1.677959] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10585 11:46:46.356537 <6>[ 1.700958] cpu cpu0: EM: created perf domain
10586 11:46:46.359604 <6>[ 1.705899] cpu cpu4: EM: created perf domain
10587 11:46:46.366994 <6>[ 1.711461] sdhci: Secure Digital Host Controller Interface driver
10588 11:46:46.374140 <6>[ 1.717894] sdhci: Copyright(c) Pierre Ossman
10589 11:46:46.380373 <6>[ 1.722854] Synopsys Designware Multimedia Card Interface Driver
10590 11:46:46.387078 <6>[ 1.729497] sdhci-pltfm: SDHCI platform and OF driver helper
10591 11:46:46.390514 <6>[ 1.729517] mmc0: CQHCI version 5.10
10592 11:46:46.397174 <6>[ 1.739748] ledtrig-cpu: registered to indicate activity on CPUs
10593 11:46:46.404067 <6>[ 1.746770] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10594 11:46:46.410380 <6>[ 1.753838] usbcore: registered new interface driver usbhid
10595 11:46:46.413721 <6>[ 1.759662] usbhid: USB HID core driver
10596 11:46:46.420628 <6>[ 1.763875] spi_master spi0: will run message pump with realtime priority
10597 11:46:46.468183 <6>[ 1.805718] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10598 11:46:46.486958 <6>[ 1.821057] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10599 11:46:46.490085 <6>[ 1.834686] mmc0: Command Queue Engine enabled
10600 11:46:46.496924 <6>[ 1.839473] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10601 11:46:46.503462 <6>[ 1.846695] mmcblk0: mmc0:0001 DA4128 116 GiB
10602 11:46:46.506857 <6>[ 1.851655] cros-ec-spi spi0.0: Chrome EC device registered
10603 11:46:46.516056 <6>[ 1.860490] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10604 11:46:46.523924 <6>[ 1.868283] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10605 11:46:46.530556 <6>[ 1.874500] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10606 11:46:46.537440 <6>[ 1.880393] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10607 11:46:46.553844 <6>[ 1.895079] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10608 11:46:46.561714 <6>[ 1.905964] NET: Registered PF_PACKET protocol family
10609 11:46:46.564967 <6>[ 1.911369] 9pnet: Installing 9P2000 support
10610 11:46:46.571667 <5>[ 1.915933] Key type dns_resolver registered
10611 11:46:46.574958 <6>[ 1.920934] registered taskstats version 1
10612 11:46:46.581734 <5>[ 1.925316] Loading compiled-in X.509 certificates
10613 11:46:46.611278 <4>[ 1.949428] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10614 11:46:46.621425 <4>[ 1.960168] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10615 11:46:46.628020 <3>[ 1.970707] debugfs: File 'uA_load' in directory '/' already present!
10616 11:46:46.634829 <3>[ 1.977407] debugfs: File 'min_uV' in directory '/' already present!
10617 11:46:46.641403 <3>[ 1.984014] debugfs: File 'max_uV' in directory '/' already present!
10618 11:46:46.648068 <3>[ 1.990621] debugfs: File 'constraint_flags' in directory '/' already present!
10619 11:46:46.659410 <3>[ 2.000371] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10620 11:46:46.668426 <6>[ 2.012693] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10621 11:46:46.675667 <6>[ 2.019618] xhci-mtk 11200000.usb: xHCI Host Controller
10622 11:46:46.681971 <6>[ 2.025112] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10623 11:46:46.691935 <6>[ 2.032957] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10624 11:46:46.698779 <6>[ 2.042371] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10625 11:46:46.705159 <6>[ 2.048439] xhci-mtk 11200000.usb: xHCI Host Controller
10626 11:46:46.711921 <6>[ 2.053916] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10627 11:46:46.718444 <6>[ 2.061560] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10628 11:46:46.725040 <6>[ 2.069206] hub 1-0:1.0: USB hub found
10629 11:46:46.728540 <6>[ 2.073217] hub 1-0:1.0: 1 port detected
10630 11:46:46.735452 <6>[ 2.077481] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10631 11:46:46.741959 <6>[ 2.086021] hub 2-0:1.0: USB hub found
10632 11:46:46.745123 <6>[ 2.090027] hub 2-0:1.0: 1 port detected
10633 11:46:46.752779 <6>[ 2.097438] mtk-msdc 11f70000.mmc: Got CD GPIO
10634 11:46:46.763625 <6>[ 2.104748] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10635 11:46:46.770081 <6>[ 2.112774] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10636 11:46:46.780039 <4>[ 2.120688] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10637 11:46:46.790528 <6>[ 2.130214] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10638 11:46:46.797005 <6>[ 2.138290] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10639 11:46:46.803783 <6>[ 2.146459] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10640 11:46:46.813729 <6>[ 2.154398] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10641 11:46:46.820461 <6>[ 2.162217] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10642 11:46:46.830299 <6>[ 2.170035] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10643 11:46:46.840248 <6>[ 2.180466] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10644 11:46:46.847241 <6>[ 2.188852] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10645 11:46:46.856983 <6>[ 2.197192] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10646 11:46:46.863736 <6>[ 2.205530] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10647 11:46:46.873574 <6>[ 2.213871] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10648 11:46:46.880431 <6>[ 2.222213] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10649 11:46:46.890058 <6>[ 2.230553] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10650 11:46:46.897461 <6>[ 2.238891] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10651 11:46:46.906984 <6>[ 2.247230] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10652 11:46:46.913639 <6>[ 2.255573] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10653 11:46:46.923711 <6>[ 2.263913] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10654 11:46:46.930134 <6>[ 2.272251] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10655 11:46:46.940108 <6>[ 2.280589] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10656 11:46:46.946792 <6>[ 2.288928] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10657 11:46:46.956684 <6>[ 2.297267] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10658 11:46:46.963325 <6>[ 2.305977] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10659 11:46:46.969740 <6>[ 2.313122] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10660 11:46:46.976384 <6>[ 2.319890] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10661 11:46:46.983237 <6>[ 2.326660] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10662 11:46:46.989740 <6>[ 2.333599] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10663 11:46:46.999350 <6>[ 2.340440] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10664 11:46:47.009372 <6>[ 2.349566] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10665 11:46:47.019698 <6>[ 2.358694] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10666 11:46:47.029101 <6>[ 2.367987] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10667 11:46:47.035937 <6>[ 2.377458] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10668 11:46:47.046031 <6>[ 2.386925] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10669 11:46:47.056019 <6>[ 2.396045] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10670 11:46:47.065994 <6>[ 2.405512] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10671 11:46:47.075990 <6>[ 2.414630] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10672 11:46:47.085760 <6>[ 2.423923] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10673 11:46:47.095765 <6>[ 2.434083] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10674 11:46:47.105637 <6>[ 2.445572] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10675 11:46:47.112338 <6>[ 2.455347] Trying to probe devices needed for running init ...
10676 11:46:47.153309 <6>[ 2.494410] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10677 11:46:47.308125 <6>[ 2.652406] hub 1-1:1.0: USB hub found
10678 11:46:47.311131 <6>[ 2.656903] hub 1-1:1.0: 4 ports detected
10679 11:46:47.320460 <6>[ 2.665098] hub 1-1:1.0: USB hub found
10680 11:46:47.323826 <6>[ 2.669531] hub 1-1:1.0: 4 ports detected
10681 11:46:47.433615 <6>[ 2.774756] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10682 11:46:47.459806 <6>[ 2.804219] hub 2-1:1.0: USB hub found
10683 11:46:47.463033 <6>[ 2.808717] hub 2-1:1.0: 3 ports detected
10684 11:46:47.472417 <6>[ 2.816857] hub 2-1:1.0: USB hub found
10685 11:46:47.476225 <6>[ 2.821301] hub 2-1:1.0: 3 ports detected
10686 11:46:47.649474 <6>[ 2.990446] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10687 11:46:47.781880 <6>[ 3.126450] hub 1-1.4:1.0: USB hub found
10688 11:46:47.785078 <6>[ 3.131042] hub 1-1.4:1.0: 2 ports detected
10689 11:46:47.794087 <6>[ 3.138383] hub 1-1.4:1.0: USB hub found
10690 11:46:47.797033 <6>[ 3.142924] hub 1-1.4:1.0: 2 ports detected
10691 11:46:47.865284 <6>[ 3.206637] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10692 11:46:48.093532 <6>[ 3.434473] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10693 11:46:48.285347 <6>[ 3.626446] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10694 11:46:59.385845 <6>[ 14.735410] ALSA device list:
10695 11:46:59.392507 <6>[ 14.738701] No soundcards found.
10696 11:46:59.400661 <6>[ 14.746618] Freeing unused kernel memory: 8384K
10697 11:46:59.403707 <6>[ 14.751607] Run /init as init process
10698 11:46:59.415630 Loading, please wait...
10699 11:46:59.435882 Starting version 247.3-7+deb11u2
10700 11:46:59.628017 <6>[ 14.970283] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10701 11:46:59.654596 <3>[ 14.996966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 11:46:59.661102 <3>[ 15.005431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 11:46:59.671450 <3>[ 15.013547] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 11:46:59.685802 <6>[ 15.031577] remoteproc remoteproc0: scp is available
10705 11:46:59.692710 <6>[ 15.037085] remoteproc remoteproc0: powering up scp
10706 11:46:59.699161 <6>[ 15.042299] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10707 11:46:59.709105 <3>[ 15.047797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 11:46:59.712269 <6>[ 15.050869] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10709 11:46:59.722208 <6>[ 15.051961] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10710 11:46:59.729137 <6>[ 15.051984] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10711 11:46:59.738802 <6>[ 15.051994] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10712 11:46:59.744992 <3>[ 15.058924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 11:46:59.751830 <6>[ 15.068560] mc: Linux media interface: v0.10
10714 11:46:59.758348 <3>[ 15.072127] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 11:46:59.765118 <6>[ 15.101531] videodev: Linux video capture interface: v2.00
10716 11:46:59.771727 <3>[ 15.102141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 11:46:59.781634 <4>[ 15.110973] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10718 11:46:59.788108 <3>[ 15.115969] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 11:46:59.798340 <3>[ 15.124960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 11:46:59.804866 <4>[ 15.144034] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10721 11:46:59.811404 <6>[ 15.149943] usbcore: registered new interface driver r8152
10722 11:46:59.818490 <3>[ 15.153314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 11:46:59.824620 <3>[ 15.153346] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 11:46:59.834571 <3>[ 15.153351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 11:46:59.841217 <6>[ 15.157491] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10726 11:46:59.851197 <3>[ 15.161520] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 11:46:59.857825 <6>[ 15.171883] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10728 11:46:59.864390 <3>[ 15.177484] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 11:46:59.871442 <6>[ 15.185449] pci_bus 0000:00: root bus resource [bus 00-ff]
10730 11:46:59.877836 <6>[ 15.189805] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10731 11:46:59.887759 <6>[ 15.189846] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10732 11:46:59.891388 <6>[ 15.189855] remoteproc remoteproc0: remote processor scp is now up
10733 11:46:59.901176 <3>[ 15.192779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 11:46:59.908066 <3>[ 15.192790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 11:46:59.917588 <3>[ 15.192796] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 11:46:59.925299 <6>[ 15.200996] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10737 11:46:59.932115 <3>[ 15.207940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 11:46:59.941876 <6>[ 15.209197] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10739 11:46:59.948960 <6>[ 15.210986] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10740 11:46:59.958871 <6>[ 15.215966] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10741 11:46:59.968758 <6>[ 15.251200] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10742 11:46:59.975877 <6>[ 15.251933] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10743 11:46:59.982522 <4>[ 15.252542] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10744 11:46:59.989015 <4>[ 15.252542] Fallback method does not support PEC.
10745 11:46:59.995575 <6>[ 15.254417] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10746 11:47:00.005675 <6>[ 15.260311] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10747 11:47:00.012108 <6>[ 15.267885] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10748 11:47:00.015716 <6>[ 15.267958] pci 0000:00:00.0: supports D1 D2
10749 11:47:00.025619 <4>[ 15.278359] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10750 11:47:00.035526 <3>[ 15.280688] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10751 11:47:00.041837 <6>[ 15.283093] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10752 11:47:00.048438 <6>[ 15.284030] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10753 11:47:00.058503 <6>[ 15.291492] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10754 11:47:00.065081 <6>[ 15.299685] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10755 11:47:00.075052 <3>[ 15.301304] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10756 11:47:00.082006 <4>[ 15.309534] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10757 11:47:00.087979 <6>[ 15.319613] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10758 11:47:00.094867 <6>[ 15.347276] Bluetooth: Core ver 2.22
10759 11:47:00.098045 <6>[ 15.347298] usbcore: registered new interface driver cdc_ether
10760 11:47:00.107853 <6>[ 15.355659] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10761 11:47:00.114801 <6>[ 15.355882] usbcore: registered new interface driver r8153_ecm
10762 11:47:00.117903 <6>[ 15.363189] NET: Registered PF_BLUETOOTH protocol family
10763 11:47:00.124648 <6>[ 15.367656] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10764 11:47:00.134230 <6>[ 15.368739] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10765 11:47:00.143974 <6>[ 15.369730] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10766 11:47:00.150898 <6>[ 15.369820] usbcore: registered new interface driver uvcvideo
10767 11:47:00.157677 <6>[ 15.376677] Bluetooth: HCI device and connection manager initialized
10768 11:47:00.164247 <6>[ 15.376697] Bluetooth: HCI socket layer initialized
10769 11:47:00.167133 <6>[ 15.385581] pci 0000:01:00.0: supports D1 D2
10770 11:47:00.170595 <6>[ 15.386272] r8152 2-1.3:1.0 eth0: v1.12.13
10771 11:47:00.177425 <6>[ 15.391714] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10772 11:47:00.183976 <6>[ 15.392319] Bluetooth: L2CAP socket layer initialized
10773 11:47:00.190486 <6>[ 15.400567] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10774 11:47:00.197255 <6>[ 15.401406] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10775 11:47:00.200777 <6>[ 15.409871] Bluetooth: SCO socket layer initialized
10776 11:47:00.206816 <6>[ 15.410197] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10777 11:47:00.216892 <6>[ 15.410225] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10778 11:47:00.223607 <6>[ 15.410228] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10779 11:47:00.233410 <6>[ 15.410236] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10780 11:47:00.240006 <6>[ 15.410249] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10781 11:47:00.250292 <6>[ 15.410262] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10782 11:47:00.253589 <6>[ 15.410274] pci 0000:00:00.0: PCI bridge to [bus 01]
10783 11:47:00.263237 <6>[ 15.410279] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10784 11:47:00.266381 <6>[ 15.410396] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10785 11:47:00.273181 <6>[ 15.410859] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10786 11:47:00.280144 <6>[ 15.411384] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10787 11:47:00.288744 <6>[ 15.634998] usbcore: registered new interface driver btusb
10788 11:47:00.299258 <4>[ 15.635921] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10789 11:47:00.305591 <3>[ 15.651306] Bluetooth: hci0: Failed to load firmware file (-2)
10790 11:47:00.312071 <3>[ 15.657397] Bluetooth: hci0: Failed to set up firmware (-2)
10791 11:47:00.322274 <4>[ 15.663244] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10792 11:47:00.358156 <5>[ 15.701089] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10793 11:47:00.377527 <5>[ 15.720053] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10794 11:47:00.383559 <4>[ 15.727019] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10795 11:47:00.390286 <6>[ 15.735925] cfg80211: failed to load regulatory.db
10796 11:47:00.452395 <6>[ 15.795220] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10797 11:47:00.459175 <6>[ 15.802839] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10798 11:47:00.480729 <6>[ 15.826485] mt7921e 0000:01:00.0: ASIC revision: 79610010
10799 11:47:00.579681 <4>[ 15.919456] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10800 11:47:00.583249 Begin: Loading essential drivers ... done.
10801 11:47:00.586413 Begin: Running /scripts/init-premount ... done.
10802 11:47:00.593004 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10803 11:47:00.602702 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10804 11:47:00.606339 Device /sys/class/net/enx00e04c722dd6 found
10805 11:47:00.609756 done.
10806 11:47:00.647448 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10807 11:47:00.701090 <4>[ 16.040822] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 11:47:00.817247 <4>[ 16.157209] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 11:47:00.938137 <4>[ 16.277974] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 11:47:01.058352 <4>[ 16.398086] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10811 11:47:01.178493 <4>[ 16.517998] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 11:47:01.298740 <4>[ 16.638187] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 11:47:01.418366 <4>[ 16.758047] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10814 11:47:01.538640 <4>[ 16.878187] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10815 11:47:01.658544 <4>[ 16.997968] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10816 11:47:01.704466 <6>[ 17.050754] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10817 11:47:01.769477 <3>[ 17.115970] mt7921e 0000:01:00.0: hardware init failed
10818 11:47:01.809853 IP-Config: no response after 2 secs - giving up
10819 11:47:01.848474 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10820 11:47:02.958626 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10821 11:47:02.965617 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10822 11:47:02.971594 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10823 11:47:02.978501 host : mt8192-asurada-spherion-r0-cbg-1
10824 11:47:02.984821 domain : lava-rack
10825 11:47:02.991608 rootserver: 192.168.201.1 rootpath:
10826 11:47:02.992121 filename :
10827 11:47:03.083144 done.
10828 11:47:03.086631 Begin: Running /scripts/nfs-bottom ... done.
10829 11:47:03.109842 Begin: Running /scripts/init-bottom ... done.
10830 11:47:04.302835 <6>[ 19.649175] NET: Registered PF_INET6 protocol family
10831 11:47:04.310140 <6>[ 19.656698] Segment Routing with IPv6
10832 11:47:04.313334 <6>[ 19.660712] In-situ OAM (IOAM) with IPv6
10833 11:47:04.433633 <30>[ 19.763056] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10834 11:47:04.440804 <30>[ 19.787453] systemd[1]: Detected architecture arm64.
10835 11:47:04.460138
10836 11:47:04.463755 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10837 11:47:04.463840
10838 11:47:04.481679 <30>[ 19.828571] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10839 11:47:05.350195 <30>[ 20.693301] systemd[1]: Queued start job for default target Graphical Interface.
10840 11:47:05.378479 <30>[ 20.724778] systemd[1]: Created slice system-getty.slice.
10841 11:47:05.385452 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10842 11:47:05.401273 <30>[ 20.747848] systemd[1]: Created slice system-modprobe.slice.
10843 11:47:05.408073 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10844 11:47:05.426048 <30>[ 20.772539] systemd[1]: Created slice system-serial\x2dgetty.slice.
10845 11:47:05.436403 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10846 11:47:05.449412 <30>[ 20.795476] systemd[1]: Created slice User and Session Slice.
10847 11:47:05.455456 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10848 11:47:05.475981 <30>[ 20.819253] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10849 11:47:05.486525 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10850 11:47:05.504229 <30>[ 20.847179] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10851 11:47:05.510880 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10852 11:47:05.535088 <30>[ 20.874592] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10853 11:47:05.541346 <30>[ 20.886753] systemd[1]: Reached target Local Encrypted Volumes.
10854 11:47:05.547927 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10855 11:47:05.564494 <30>[ 20.910868] systemd[1]: Reached target Paths.
10856 11:47:05.567976 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10857 11:47:05.584208 <30>[ 20.930424] systemd[1]: Reached target Remote File Systems.
10858 11:47:05.590565 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10859 11:47:05.608452 <30>[ 20.954697] systemd[1]: Reached target Slices.
10860 11:47:05.614953 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10861 11:47:05.628428 <30>[ 20.974661] systemd[1]: Reached target Swap.
10862 11:47:05.632159 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10863 11:47:05.651819 <30>[ 20.994913] systemd[1]: Listening on initctl Compatibility Named Pipe.
10864 11:47:05.658595 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10865 11:47:05.664941 <30>[ 21.011086] systemd[1]: Listening on Journal Audit Socket.
10866 11:47:05.672230 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10867 11:47:05.689523 <30>[ 21.035719] systemd[1]: Listening on Journal Socket (/dev/log).
10868 11:47:05.695933 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10869 11:47:05.712860 <30>[ 21.058954] systemd[1]: Listening on Journal Socket.
10870 11:47:05.719068 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10871 11:47:05.736838 <30>[ 21.079996] systemd[1]: Listening on Network Service Netlink Socket.
10872 11:47:05.743261 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10873 11:47:05.759288 <30>[ 21.105535] systemd[1]: Listening on udev Control Socket.
10874 11:47:05.765746 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10875 11:47:05.780375 <30>[ 21.126854] systemd[1]: Listening on udev Kernel Socket.
10876 11:47:05.787136 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10877 11:47:05.836204 <30>[ 21.182825] systemd[1]: Mounting Huge Pages File System...
10878 11:47:05.842955 Mounting [0;1;39mHuge Pages File System[0m...
10879 11:47:05.858066 <30>[ 21.204852] systemd[1]: Mounting POSIX Message Queue File System...
10880 11:47:05.865661 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10881 11:47:05.882869 <30>[ 21.229531] systemd[1]: Mounting Kernel Debug File System...
10882 11:47:05.889557 Mounting [0;1;39mKernel Debug File System[0m...
10883 11:47:05.907549 <30>[ 21.250972] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10884 11:47:05.921948 <30>[ 21.265095] systemd[1]: Starting Create list of static device nodes for the current kernel...
10885 11:47:05.928553 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10886 11:47:05.949103 <30>[ 21.295762] systemd[1]: Starting Load Kernel Module configfs...
10887 11:47:05.955533 Starting [0;1;39mLoad Kernel Module configfs[0m...
10888 11:47:05.976478 <30>[ 21.323205] systemd[1]: Starting Load Kernel Module drm...
10889 11:47:05.983178 Starting [0;1;39mLoad Kernel Module drm[0m...
10890 11:47:06.000342 <30>[ 21.347285] systemd[1]: Starting Load Kernel Module fuse...
10891 11:47:06.007024 Starting [0;1;39mLoad Kernel Module fuse[0m...
10892 11:47:06.036359 <6>[ 21.383289] fuse: init (API version 7.37)
10893 11:47:06.046177 <30>[ 21.384356] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10894 11:47:06.084963 <30>[ 21.431223] systemd[1]: Starting Journal Service...
10895 11:47:06.091104 Starting [0;1;39mJournal Service[0m...
10896 11:47:06.113641 <30>[ 21.460139] systemd[1]: Starting Load Kernel Modules...
10897 11:47:06.120220 Starting [0;1;39mLoad Kernel Modules[0m...
10898 11:47:06.144949 <30>[ 21.488518] systemd[1]: Starting Remount Root and Kernel File Systems...
10899 11:47:06.151372 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10900 11:47:06.166841 <30>[ 21.514032] systemd[1]: Starting Coldplug All udev Devices...
10901 11:47:06.173439 Starting [0;1;39mColdplug All udev Devices[0m...
10902 11:47:06.190637 <30>[ 21.537633] systemd[1]: Mounted Huge Pages File System.
10903 11:47:06.196963 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10904 11:47:06.212128 <30>[ 21.559277] systemd[1]: Mounted POSIX Message Queue File System.
10905 11:47:06.218962 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10906 11:47:06.236220 <30>[ 21.582771] systemd[1]: Mounted Kernel Debug File System.
10907 11:47:06.246328 [[0;32m OK [<3>[ 21.589010] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 11:47:06.252836 0m] Mounted [0;1;39mKernel Debug File System[0m.
10909 11:47:06.273035 <30>[ 21.616289] systemd[1]: Finished Create list of static device nodes for the current kernel.
10910 11:47:06.282632 <3>[ 21.619360] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 11:47:06.289467 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10912 11:47:06.305300 <30>[ 21.652051] systemd[1]: modprobe@configfs.service: Succeeded.
10913 11:47:06.312167 <30>[ 21.658918] systemd[1]: Finished Load Kernel Module configfs.
10914 11:47:06.325627 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 21.668590] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 11:47:06.328722 l Module configfs[0m.
10916 11:47:06.344721 <30>[ 21.691336] systemd[1]: modprobe@drm.service: Succeeded.
10917 11:47:06.351658 <30>[ 21.697856] systemd[1]: Finished Load Kernel Module drm.
10918 11:47:06.361530 <3>[ 21.698618] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 11:47:06.364804 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10920 11:47:06.380479 <30>[ 21.727143] systemd[1]: modprobe@fuse.service: Succeeded.
10921 11:47:06.390661 <3>[ 21.733353] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 11:47:06.397431 <30>[ 21.734029] systemd[1]: Finished Load Kernel Module fuse.
10923 11:47:06.400538 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10924 11:47:06.419709 <3>[ 21.763394] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 11:47:06.426309 <30>[ 21.763732] systemd[1]: Finished Load Kernel Modules.
10926 11:47:06.432600 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10927 11:47:06.449691 <3>[ 21.793553] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 11:47:06.460678 <30>[ 21.804139] systemd[1]: Finished Remount Root and Kernel File Systems.
10929 11:47:06.467007 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10930 11:47:06.479142 <3>[ 21.822911] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 11:47:06.499763 <30>[ 21.846386] systemd[1]: Mounting FUSE Control File System...
10932 11:47:06.513045 Mountin<3>[ 21.854612] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 11:47:06.516304 g [0;1;39mFUSE Control File System[0m...
10934 11:47:06.535652 <30>[ 21.882246] systemd[1]: Mounting Kernel Configuration File System...
10935 11:47:06.545412 <3>[ 21.884753] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 11:47:06.552422 Mounting [0;1;39mKernel Configuration File System[0m...
10937 11:47:06.580565 <30>[ 21.923953] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10938 11:47:06.590545 <30>[ 21.932950] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10939 11:47:06.620434 <30>[ 21.967155] systemd[1]: Starting Load/Save Random Seed...
10940 11:47:06.627321 Starting [0;1;39mLoad/Save Random Seed[0m...
10941 11:47:06.654680 <4>[ 21.991228] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10942 11:47:06.661395 <30>[ 21.992838] systemd[1]: Starting Apply Kernel Variables...
10943 11:47:06.667801 <3>[ 22.007148] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10944 11:47:06.674542 Starting [0;1;39mApply Kernel Variables[0m...
10945 11:47:06.696509 <30>[ 22.043442] systemd[1]: Starting Create System Users...
10946 11:47:06.703220 Starting [0;1;39mCreate System Users[0m...
10947 11:47:06.717459 <30>[ 22.064096] systemd[1]: Started Journal Service.
10948 11:47:06.724178 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10949 11:47:06.744017 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10950 11:47:06.755483 See 'systemctl status systemd-udev-trigger.service' for details.
10951 11:47:06.772566 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10952 11:47:06.788050 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10953 11:47:06.804533 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10954 11:47:06.825196 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10955 11:47:06.845495 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10956 11:47:06.884441 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10957 11:47:06.901889 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10958 11:47:06.938380 <46>[ 22.281863] systemd-journald[293]: Received client request to flush runtime journal.
10959 11:47:06.985103 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10960 11:47:07.000132 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10961 11:47:07.019148 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10962 11:47:07.083504 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10963 11:47:08.350688 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10964 11:47:08.392351 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10965 11:47:08.446208 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10966 11:47:08.496619 Starting [0;1;39mNetwork Service[0m...
10967 11:47:08.820610 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10968 11:47:08.845290 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10969 11:47:08.895755 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10970 11:47:09.176566 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10971 11:47:09.195328 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10972 11:47:09.236598 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10973 11:47:09.257997 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10974 11:47:09.272553 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10975 11:47:09.293263 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10976 11:47:09.309166 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10977 11:47:09.368549 Starting [0;1;39mNetwork Name Resolution[0m...
10978 11:47:09.396873 Starting [0;1;39mNetwork Time Synchronization[0m...
10979 11:47:09.414776 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10980 11:47:09.475665 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10981 11:47:09.619721 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10982 11:47:09.640004 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10983 11:47:09.659290 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10984 11:47:09.675436 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10985 11:47:09.695583 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10986 11:47:09.850419 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10987 11:47:09.903024 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10988 11:47:09.929652 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10989 11:47:09.961483 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10990 11:47:09.975113 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10991 11:47:10.231229 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10992 11:47:10.242975 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10993 11:47:10.259273 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10994 11:47:10.316095 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10995 11:47:10.740427 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10996 11:47:11.156032 Starting [0;1;39mUser Login Management[0m...
10997 11:47:11.173692 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10998 11:47:11.194827 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10999 11:47:11.217564 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11000 11:47:11.255613 Starting [0;1;39mPermit User Sessions[0m...
11001 11:47:11.355014 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11002 11:47:11.372387 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11003 11:47:11.420195 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11004 11:47:11.444069 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11005 11:47:11.459099 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11006 11:47:11.476617 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11007 11:47:11.496986 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11008 11:47:11.515476 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11009 11:47:11.560043 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11010 11:47:11.608972 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11011 11:47:11.719636
11012 11:47:11.719792
11013 11:47:11.722994 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11014 11:47:11.723079
11015 11:47:11.726307 debian-bullseye-arm64 login: root (automatic login)
11016 11:47:11.726450
11017 11:47:11.726537
11018 11:47:12.041496 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
11019 11:47:12.041650
11020 11:47:12.048069 The programs included with the Debian GNU/Linux system are free software;
11021 11:47:12.054853 the exact distribution terms for each program are described in the
11022 11:47:12.058673 individual files in /usr/share/doc/*/copyright.
11023 11:47:12.058761
11024 11:47:12.064856 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11025 11:47:12.068029 permitted by applicable law.
11026 11:47:12.826684 Matched prompt #10: / #
11028 11:47:12.826976 Setting prompt string to ['/ #']
11029 11:47:12.827076 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11031 11:47:12.827274 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11032 11:47:12.827363 start: 2.2.6 expect-shell-connection (timeout 00:03:31) [common]
11033 11:47:12.827436 Setting prompt string to ['/ #']
11034 11:47:12.827498 Forcing a shell prompt, looking for ['/ #']
11036 11:47:12.877722 / #
11037 11:47:12.877829 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11038 11:47:12.877908 Waiting using forced prompt support (timeout 00:02:30)
11039 11:47:12.882834
11040 11:47:12.883111 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11041 11:47:12.883212 start: 2.2.7 export-device-env (timeout 00:03:31) [common]
11043 11:47:12.983579 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12074003/extract-nfsrootfs-50snkza6'
11044 11:47:12.988601 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12074003/extract-nfsrootfs-50snkza6'
11046 11:47:13.089165 / # export NFS_SERVER_IP='192.168.201.1'
11047 11:47:13.094689 export NFS_SERVER_IP='192.168.201.1'
11048 11:47:13.094992 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11049 11:47:13.095102 end: 2.2 depthcharge-retry (duration 00:01:29) [common]
11050 11:47:13.095198 end: 2 depthcharge-action (duration 00:01:29) [common]
11051 11:47:13.095291 start: 3 lava-test-retry (timeout 00:07:40) [common]
11052 11:47:13.095381 start: 3.1 lava-test-shell (timeout 00:07:40) [common]
11053 11:47:13.095456 Using namespace: common
11055 11:47:13.195807 / # #
11056 11:47:13.195955 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11057 11:47:13.200930 #
11058 11:47:13.201196 Using /lava-12074003
11060 11:47:13.301544 / # export SHELL=/bin/bash
11061 11:47:13.306869 export SHELL=/bin/bash
11063 11:47:13.407417 / # . /lava-12074003/environment
11064 11:47:13.412541 . /lava-12074003/environment
11066 11:47:13.518666 / # /lava-12074003/bin/lava-test-runner /lava-12074003/0
11067 11:47:13.518790 Test shell timeout: 10s (minimum of the action and connection timeout)
11068 11:47:13.524057 /lava-12074003/bin/lava-test-runner /lava-12074003/0
11069 11:47:13.760157 + export TESTRUN_ID=0_timesync-off
11070 11:47:13.763409 + TESTRUN_ID=0_timesync-off
11071 11:47:13.766990 + cd /lava-12074003/0/tests/0_timesync-off
11072 11:47:13.769683 ++ cat uuid
11073 11:47:13.773355 + UUID=12074003_1.6.2.3.1
11074 11:47:13.773441 + set +x
11075 11:47:13.780217 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12074003_1.6.2.3.1>
11076 11:47:13.780479 Received signal: <STARTRUN> 0_timesync-off 12074003_1.6.2.3.1
11077 11:47:13.780557 Starting test lava.0_timesync-off (12074003_1.6.2.3.1)
11078 11:47:13.780645 Skipping test definition patterns.
11079 11:47:13.783769 + systemctl stop systemd-timesyncd
11080 11:47:13.825058 + set +x
11081 11:47:13.828760 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12074003_1.6.2.3.1>
11082 11:47:13.829021 Received signal: <ENDRUN> 0_timesync-off 12074003_1.6.2.3.1
11083 11:47:13.829108 Ending use of test pattern.
11084 11:47:13.829174 Ending test lava.0_timesync-off (12074003_1.6.2.3.1), duration 0.05
11086 11:47:13.902739 + export TESTRUN_ID=1_kselftest-arm64
11087 11:47:13.902841 + TESTRUN_ID=1_kselftest-arm64
11088 11:47:13.909358 + cd /lava-12074003/0/tests/1_kselftest-arm64
11089 11:47:13.909481 ++ cat uuid
11090 11:47:13.912444 + UUID=12074003_1.6.2.3.5
11091 11:47:13.912521 + set +x
11092 11:47:13.919060 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12074003_1.6.2.3.5>
11093 11:47:13.919273 Received signal: <STARTRUN> 1_kselftest-arm64 12074003_1.6.2.3.5
11094 11:47:13.919356 Starting test lava.1_kselftest-arm64 (12074003_1.6.2.3.5)
11095 11:47:13.919440 Skipping test definition patterns.
11096 11:47:13.922583 + cd ./automated/linux/kselftest/
11097 11:47:13.948657 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11098 11:47:13.980003 INFO: install_deps skipped
11099 11:47:14.094071 --2023-11-24 11:46:39-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11100 11:47:14.119349 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11101 11:47:14.252052 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11102 11:47:14.385559 HTTP request sent, awaiting response... 200 OK
11103 11:47:14.388474 Length: 2961876 (2.8M) [application/octet-stream]
11104 11:47:14.392124 Saving to: 'kselftest.tar.xz'
11105 11:47:14.392207
11106 11:47:14.392274
11107 11:47:14.651957 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11108 11:47:14.917272 kselftest.tar.xz 1%[ ] 47.81K 181KB/s
11109 11:47:15.231790 kselftest.tar.xz 7%[> ] 214.67K 405KB/s
11110 11:47:15.510368 kselftest.tar.xz 28%[====> ] 826.96K 979KB/s
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11113 11:47:15.637946
11114 11:47:15.894535 2023-11-24 11:46:41 (2.27 MB/s) - 'kselftest.tar.xz' saved [2961876/2961876]
11115 11:47:15.894692
11116 11:47:21.124438 skiplist:
11117 11:47:21.127582 ========================================
11118 11:47:21.130701 ========================================
11119 11:47:21.173539 arm64:tags_test
11120 11:47:21.177439 arm64:run_tags_test.sh
11121 11:47:21.177527 arm64:fake_sigreturn_bad_magic
11122 11:47:21.180435 arm64:fake_sigreturn_bad_size
11123 11:47:21.183999 arm64:fake_sigreturn_bad_size_for_magic0
11124 11:47:21.186843 arm64:fake_sigreturn_duplicated_fpsimd
11125 11:47:21.190635 arm64:fake_sigreturn_misaligned_sp
11126 11:47:21.193672 arm64:fake_sigreturn_missing_fpsimd
11127 11:47:21.196794 arm64:fake_sigreturn_sme_change_vl
11128 11:47:21.200364 arm64:fake_sigreturn_sve_change_vl
11129 11:47:21.203760 arm64:mangle_pstate_invalid_compat_toggle
11130 11:47:21.206863 arm64:mangle_pstate_invalid_daif_bits
11131 11:47:21.210424 arm64:mangle_pstate_invalid_mode_el1h
11132 11:47:21.213894 arm64:mangle_pstate_invalid_mode_el1t
11133 11:47:21.217025 arm64:mangle_pstate_invalid_mode_el2h
11134 11:47:21.220696 arm64:mangle_pstate_invalid_mode_el2t
11135 11:47:21.224046 arm64:mangle_pstate_invalid_mode_el3h
11136 11:47:21.227121 arm64:mangle_pstate_invalid_mode_el3t
11137 11:47:21.230219 arm64:sme_trap_no_sm
11138 11:47:21.233921 arm64:sme_trap_non_streaming
11139 11:47:21.234365 arm64:sme_trap_za
11140 11:47:21.237028 arm64:sme_vl
11141 11:47:21.237471 arm64:ssve_regs
11142 11:47:21.240601 arm64:sve_regs
11143 11:47:21.241161 arm64:sve_vl
11144 11:47:21.241611 arm64:za_no_regs
11145 11:47:21.243686 arm64:za_regs
11146 11:47:21.244072 arm64:pac
11147 11:47:21.246974 arm64:fp-stress
11148 11:47:21.247512 arm64:sve-ptrace
11149 11:47:21.250204 arm64:sve-probe-vls
11150 11:47:21.250735 arm64:vec-syscfg
11151 11:47:21.251176 arm64:za-fork
11152 11:47:21.253381 arm64:za-ptrace
11153 11:47:21.256981 arm64:check_buffer_fill
11154 11:47:21.257413 arm64:check_child_memory
11155 11:47:21.260142 arm64:check_gcr_el1_cswitch
11156 11:47:21.263609 arm64:check_ksm_options
11157 11:47:21.264044 arm64:check_mmap_options
11158 11:47:21.266733 arm64:check_prctl
11159 11:47:21.270015 arm64:check_tags_inclusion
11160 11:47:21.270481 arm64:check_user_mem
11161 11:47:21.270833 arm64:btitest
11162 11:47:21.274124 arm64:nobtitest
11163 11:47:21.274651 arm64:hwcap
11164 11:47:21.276602 arm64:ptrace
11165 11:47:21.277060 arm64:syscall-abi
11166 11:47:21.277407 arm64:tpidr2
11167 11:47:21.283242 ============== Tests to run ===============
11168 11:47:21.283822 arm64:tags_test
11169 11:47:21.286716 arm64:run_tags_test.sh
11170 11:47:21.289955 arm64:fake_sigreturn_bad_magic
11171 11:47:21.290427 arm64:fake_sigreturn_bad_size
11172 11:47:21.293633 arm64:fake_sigreturn_bad_size_for_magic0
11173 11:47:21.296609 arm64:fake_sigreturn_duplicated_fpsimd
11174 11:47:21.300099 arm64:fake_sigreturn_misaligned_sp
11175 11:47:21.303702 arm64:fake_sigreturn_missing_fpsimd
11176 11:47:21.306734 arm64:fake_sigreturn_sme_change_vl
11177 11:47:21.310111 arm64:fake_sigreturn_sve_change_vl
11178 11:47:21.313692 arm64:mangle_pstate_invalid_compat_toggle
11179 11:47:21.316446 arm64:mangle_pstate_invalid_daif_bits
11180 11:47:21.319843 arm64:mangle_pstate_invalid_mode_el1h
11181 11:47:21.323011 arm64:mangle_pstate_invalid_mode_el1t
11182 11:47:21.329735 arm64:mangle_pstate_invalid_mode_el2h
11183 11:47:21.333507 arm64:mangle_pstate_invalid_mode_el2t
11184 11:47:21.336469 arm64:mangle_pstate_invalid_mode_el3h
11185 11:47:21.339748 arm64:mangle_pstate_invalid_mode_el3t
11186 11:47:21.340174 arm64:sme_trap_no_sm
11187 11:47:21.342949 arm64:sme_trap_non_streaming
11188 11:47:21.343375 arm64:sme_trap_za
11189 11:47:21.346496 arm64:sme_vl
11190 11:47:21.346922 arm64:ssve_regs
11191 11:47:21.349846 arm64:sve_regs
11192 11:47:21.350269 arm64:sve_vl
11193 11:47:21.350638 arm64:za_no_regs
11194 11:47:21.353041 arm64:za_regs
11195 11:47:21.353467 arm64:pac
11196 11:47:21.356405 arm64:fp-stress
11197 11:47:21.356918 arm64:sve-ptrace
11198 11:47:21.359698 arm64:sve-probe-vls
11199 11:47:21.360125 arm64:vec-syscfg
11200 11:47:21.363419 arm64:za-fork
11201 11:47:21.363844 arm64:za-ptrace
11202 11:47:21.366215 arm64:check_buffer_fill
11203 11:47:21.366689 arm64:check_child_memory
11204 11:47:21.369633 arm64:check_gcr_el1_cswitch
11205 11:47:21.373265 arm64:check_ksm_options
11206 11:47:21.373791 arm64:check_mmap_options
11207 11:47:21.376103 arm64:check_prctl
11208 11:47:21.379846 arm64:check_tags_inclusion
11209 11:47:21.380414 arm64:check_user_mem
11210 11:47:21.382877 arm64:btitest
11211 11:47:21.383371 arm64:nobtitest
11212 11:47:21.383746 arm64:hwcap
11213 11:47:21.386374 arm64:ptrace
11214 11:47:21.386884 arm64:syscall-abi
11215 11:47:21.389625 arm64:tpidr2
11216 11:47:21.392358 ===========End Tests to run ===============
11217 11:47:21.392834 shardfile-arm64 pass
11218 11:47:21.667183 <12>[ 37.015770] kselftest: Running tests in arm64
11219 11:47:21.677731 TAP version 13
11220 11:47:21.692235 1..48
11221 11:47:21.710182 # selftests: arm64: tags_test
11222 11:47:22.150640 ok 1 selftests: arm64: tags_test
11223 11:47:22.170494 # selftests: arm64: run_tags_test.sh
11224 11:47:22.239640 # --------------------
11225 11:47:22.242852 # running tags test
11226 11:47:22.243323 # --------------------
11227 11:47:22.246506 # [PASS]
11228 11:47:22.249653 ok 2 selftests: arm64: run_tags_test.sh
11229 11:47:22.265402 # selftests: arm64: fake_sigreturn_bad_magic
11230 11:47:22.332898 # Registered handlers for all signals.
11231 11:47:22.333462 # Detected MINSTKSIGSZ:4720
11232 11:47:22.336481 # Testcase initialized.
11233 11:47:22.339732 # uc context validated.
11234 11:47:22.342992 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11235 11:47:22.345785 # Handled SIG_COPYCTX
11236 11:47:22.346318 # Available space:3568
11237 11:47:22.352463 # Using badly built context - ERR: BAD MAGIC !
11238 11:47:22.359054 # SIG_OK -- SP:0xFFFFEF60E620 si_addr@:0xffffef60e620 si_code:2 token@:0xffffef60d3c0 offset:-4704
11239 11:47:22.362880 # ==>> completed. PASS(1)
11240 11:47:22.369231 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11241 11:47:22.376056 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEF60D3C0
11242 11:47:22.382979 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11243 11:47:22.385773 # selftests: arm64: fake_sigreturn_bad_size
11244 11:47:22.411387 # Registered handlers for all signals.
11245 11:47:22.411949 # Detected MINSTKSIGSZ:4720
11246 11:47:22.414582 # Testcase initialized.
11247 11:47:22.417972 # uc context validated.
11248 11:47:22.421155 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11249 11:47:22.424465 # Handled SIG_COPYCTX
11250 11:47:22.424963 # Available space:3568
11251 11:47:22.428151 # uc context validated.
11252 11:47:22.434892 # Using badly built context - ERR: Bad size for esr_context
11253 11:47:22.441121 # SIG_OK -- SP:0xFFFFCC6C11D0 si_addr@:0xffffcc6c11d0 si_code:2 token@:0xffffcc6bff70 offset:-4704
11254 11:47:22.444613 # ==>> completed. PASS(1)
11255 11:47:22.450995 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11256 11:47:22.457943 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCC6BFF70
11257 11:47:22.460979 ok 4 selftests: arm64: fake_sigreturn_bad_size
11258 11:47:22.467380 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11259 11:47:22.495058 # Registered handlers for all signals.
11260 11:47:22.495681 # Detected MINSTKSIGSZ:4720
11261 11:47:22.497444 # Testcase initialized.
11262 11:47:22.500772 # uc context validated.
11263 11:47:22.504097 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11264 11:47:22.507567 # Handled SIG_COPYCTX
11265 11:47:22.508048 # Available space:3568
11266 11:47:22.514449 # Using badly built context - ERR: Bad size for terminator
11267 11:47:22.524154 # SIG_OK -- SP:0xFFFFF52FCCD0 si_addr@:0xfffff52fccd0 si_code:2 token@:0xfffff52fba70 offset:-4704
11268 11:47:22.524669 # ==>> completed. PASS(1)
11269 11:47:22.534197 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11270 11:47:22.540306 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF52FBA70
11271 11:47:22.544069 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11272 11:47:22.550427 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11273 11:47:22.572149 # Registered handlers for all signals.
11274 11:47:22.572394 # Detected MINSTKSIGSZ:4720
11275 11:47:22.575249 # Testcase initialized.
11276 11:47:22.578895 # uc context validated.
11277 11:47:22.581976 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11278 11:47:22.585105 # Handled SIG_COPYCTX
11279 11:47:22.585364 # Available space:3568
11280 11:47:22.591878 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11281 11:47:22.601774 # SIG_OK -- SP:0xFFFFD79BC840 si_addr@:0xffffd79bc840 si_code:2 token@:0xffffd79bb5e0 offset:-4704
11282 11:47:22.602259 # ==>> completed. PASS(1)
11283 11:47:22.611861 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11284 11:47:22.618604 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD79BB5E0
11285 11:47:22.621781 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11286 11:47:22.624747 # selftests: arm64: fake_sigreturn_misaligned_sp
11287 11:47:22.643344 # Registered handlers for all signals.
11288 11:47:22.643885 # Detected MINSTKSIGSZ:4720
11289 11:47:22.647044 # Testcase initialized.
11290 11:47:22.650181 # uc context validated.
11291 11:47:22.653439 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11292 11:47:22.656941 # Handled SIG_COPYCTX
11293 11:47:22.663361 # SIG_OK -- SP:0xFFFFFF8169D3 si_addr@:0xffffff8169d3 si_code:2 token@:0xffffff8169d3 offset:0
11294 11:47:22.666870 # ==>> completed. PASS(1)
11295 11:47:22.673144 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11296 11:47:22.680033 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFF8169D3
11297 11:47:22.686518 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11298 11:47:22.689748 # selftests: arm64: fake_sigreturn_missing_fpsimd
11299 11:47:22.717921 # Registered handlers for all signals.
11300 11:47:22.718497 # Detected MINSTKSIGSZ:4720
11301 11:47:22.721107 # Testcase initialized.
11302 11:47:22.725180 # uc context validated.
11303 11:47:22.727995 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11304 11:47:22.730951 # Handled SIG_COPYCTX
11305 11:47:22.734493 # Mangling template header. Spare space:4096
11306 11:47:22.737711 # Using badly built context - ERR: Missing FPSIMD
11307 11:47:22.747907 # SIG_OK -- SP:0xFFFFD3D759B0 si_addr@:0xffffd3d759b0 si_code:2 token@:0xffffd3d74750 offset:-4704
11308 11:47:22.751077 # ==>> completed. PASS(1)
11309 11:47:22.757892 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11310 11:47:22.764481 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD3D74750
11311 11:47:22.768253 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11312 11:47:22.774577 # selftests: arm64: fake_sigreturn_sme_change_vl
11313 11:47:22.797868 # Registered handlers for all signals.
11314 11:47:22.798502 # Detected MINSTKSIGSZ:4720
11315 11:47:22.801098 # ==>> completed. SKIP.
11316 11:47:22.807503 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11317 11:47:22.811188 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11318 11:47:22.818496 # selftests: arm64: fake_sigreturn_sve_change_vl
11319 11:47:22.889243 # Registered handlers for all signals.
11320 11:47:22.889751 # Detected MINSTKSIGSZ:4720
11321 11:47:22.892269 # ==>> completed. SKIP.
11322 11:47:22.899067 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11323 11:47:22.902109 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11324 11:47:22.914429 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11325 11:47:22.967885 # Registered handlers for all signals.
11326 11:47:22.968434 # Detected MINSTKSIGSZ:4720
11327 11:47:22.971100 # Testcase initialized.
11328 11:47:22.974334 # uc context validated.
11329 11:47:22.974799 # Handled SIG_TRIG
11330 11:47:22.983998 # SIG_OK -- SP:0xFFFFFC518870 si_addr@:0xfffffc518870 si_code:2 token@:(nil) offset:-281474914945136
11331 11:47:22.987395 # ==>> completed. PASS(1)
11332 11:47:22.994085 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11333 11:47:23.000365 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11334 11:47:23.003954 # selftests: arm64: mangle_pstate_invalid_daif_bits
11335 11:47:23.037106 # Registered handlers for all signals.
11336 11:47:23.037362 # Detected MINSTKSIGSZ:4720
11337 11:47:23.040612 # Testcase initialized.
11338 11:47:23.043616 # uc context validated.
11339 11:47:23.043921 # Handled SIG_TRIG
11340 11:47:23.053495 # SIG_OK -- SP:0xFFFFD1E30280 si_addr@:0xffffd1e30280 si_code:2 token@:(nil) offset:-281474203058816
11341 11:47:23.057133 # ==>> completed. PASS(1)
11342 11:47:23.063707 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11343 11:47:23.067015 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11344 11:47:23.073421 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11345 11:47:23.111373 # Registered handlers for all signals.
11346 11:47:23.111913 # Detected MINSTKSIGSZ:4720
11347 11:47:23.114703 # Testcase initialized.
11348 11:47:23.118243 # uc context validated.
11349 11:47:23.118757 # Handled SIG_TRIG
11350 11:47:23.127998 # SIG_OK -- SP:0xFFFFF091FD70 si_addr@:0xfffff091fd70 si_code:2 token@:(nil) offset:-281474717842800
11351 11:47:23.131274 # ==>> completed. PASS(1)
11352 11:47:23.137902 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11353 11:47:23.141059 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11354 11:47:23.147645 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11355 11:47:23.195544 # Registered handlers for all signals.
11356 11:47:23.196105 # Detected MINSTKSIGSZ:4720
11357 11:47:23.198965 # Testcase initialized.
11358 11:47:23.202728 # uc context validated.
11359 11:47:23.203303 # Handled SIG_TRIG
11360 11:47:23.212436 # SIG_OK -- SP:0xFFFFE0189740 si_addr@:0xffffe0189740 si_code:2 token@:(nil) offset:-281474441451328
11361 11:47:23.215468 # ==>> completed. PASS(1)
11362 11:47:23.222652 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11363 11:47:23.225249 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11364 11:47:23.231730 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11365 11:47:23.282306 # Registered handlers for all signals.
11366 11:47:23.282918 # Detected MINSTKSIGSZ:4720
11367 11:47:23.285676 # Testcase initialized.
11368 11:47:23.289265 # uc context validated.
11369 11:47:23.289816 # Handled SIG_TRIG
11370 11:47:23.298874 # SIG_OK -- SP:0xFFFFEAE914F0 si_addr@:0xffffeae914f0 si_code:2 token@:(nil) offset:-281474622887152
11371 11:47:23.302698 # ==>> completed. PASS(1)
11372 11:47:23.308688 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11373 11:47:23.312270 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11374 11:47:23.318594 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11375 11:47:23.362606 # Registered handlers for all signals.
11376 11:47:23.363145 # Detected MINSTKSIGSZ:4720
11377 11:47:23.366356 # Testcase initialized.
11378 11:47:23.369663 # uc context validated.
11379 11:47:23.370281 # Handled SIG_TRIG
11380 11:47:23.379120 # SIG_OK -- SP:0xFFFFD527B300 si_addr@:0xffffd527b300 si_code:2 token@:(nil) offset:-281474257892096
11381 11:47:23.382248 # ==>> completed. PASS(1)
11382 11:47:23.388890 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11383 11:47:23.392575 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11384 11:47:23.399151 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11385 11:47:23.441087 # Registered handlers for all signals.
11386 11:47:23.441659 # Detected MINSTKSIGSZ:4720
11387 11:47:23.444411 # Testcase initialized.
11388 11:47:23.447657 # uc context validated.
11389 11:47:23.448139 # Handled SIG_TRIG
11390 11:47:23.457569 # SIG_OK -- SP:0xFFFFDABC1B00 si_addr@:0xffffdabc1b00 si_code:2 token@:(nil) offset:-281474351504128
11391 11:47:23.460780 # ==>> completed. PASS(1)
11392 11:47:23.467519 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11393 11:47:23.470946 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11394 11:47:23.477610 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11395 11:47:23.526631 # Registered handlers for all signals.
11396 11:47:23.527321 # Detected MINSTKSIGSZ:4720
11397 11:47:23.530165 # Testcase initialized.
11398 11:47:23.533321 # uc context validated.
11399 11:47:23.533822 # Handled SIG_TRIG
11400 11:47:23.543137 # SIG_OK -- SP:0xFFFFCC205B10 si_addr@:0xffffcc205b10 si_code:2 token@:(nil) offset:-281474106415888
11401 11:47:23.546628 # ==>> completed. PASS(1)
11402 11:47:23.553133 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11403 11:47:23.556348 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11404 11:47:23.559475 # selftests: arm64: sme_trap_no_sm
11405 11:47:23.608673 # Registered handlers for all signals.
11406 11:47:23.609280 # Detected MINSTKSIGSZ:4720
11407 11:47:23.611862 # ==>> completed. SKIP.
11408 11:47:23.621769 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11409 11:47:23.625142 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11410 11:47:23.628458 # selftests: arm64: sme_trap_non_streaming
11411 11:47:23.685785 # Registered handlers for all signals.
11412 11:47:23.686313 # Detected MINSTKSIGSZ:4720
11413 11:47:23.689029 # ==>> completed. SKIP.
11414 11:47:23.698995 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11415 11:47:23.705734 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11416 11:47:23.708975 # selftests: arm64: sme_trap_za
11417 11:47:23.759552 # Registered handlers for all signals.
11418 11:47:23.760138 # Detected MINSTKSIGSZ:4720
11419 11:47:23.763149 # Testcase initialized.
11420 11:47:23.773004 # SIG_OK -- SP:0xFFFFFDB53FA0 si_addr@:0xaaaae4982510 si_code:1 token@:(nil) offset:-187650956338448
11421 11:47:23.773673 # ==>> completed. PASS(1)
11422 11:47:23.782871 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11423 11:47:23.786154 ok 21 selftests: arm64: sme_trap_za
11424 11:47:23.786806 # selftests: arm64: sme_vl
11425 11:47:23.850500 # Registered handlers for all signals.
11426 11:47:23.851054 # Detected MINSTKSIGSZ:4720
11427 11:47:23.853871 # ==>> completed. SKIP.
11428 11:47:23.860176 # # SME VL :: Check that we get the right SME VL reported
11429 11:47:23.863572 ok 22 selftests: arm64: sme_vl # SKIP
11430 11:47:23.867463 # selftests: arm64: ssve_regs
11431 11:47:23.929990 # Registered handlers for all signals.
11432 11:47:23.930605 # Detected MINSTKSIGSZ:4720
11433 11:47:23.933318 # ==>> completed. SKIP.
11434 11:47:23.939978 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11435 11:47:23.946502 ok 23 selftests: arm64: ssve_regs # SKIP
11436 11:47:23.951352 # selftests: arm64: sve_regs
11437 11:47:24.005816 # Registered handlers for all signals.
11438 11:47:24.006052 # Detected MINSTKSIGSZ:4720
11439 11:47:24.008812 # ==>> completed. SKIP.
11440 11:47:24.015765 # # SVE registers :: Check that we get the right SVE registers reported
11441 11:47:24.018965 ok 24 selftests: arm64: sve_regs # SKIP
11442 11:47:24.021943 # selftests: arm64: sve_vl
11443 11:47:24.094875 # Registered handlers for all signals.
11444 11:47:24.095419 # Detected MINSTKSIGSZ:4720
11445 11:47:24.098204 # ==>> completed. SKIP.
11446 11:47:24.104852 # # SVE VL :: Check that we get the right SVE VL reported
11447 11:47:24.107828 ok 25 selftests: arm64: sve_vl # SKIP
11448 11:47:24.120055 # selftests: arm64: za_no_regs
11449 11:47:24.167967 # Registered handlers for all signals.
11450 11:47:24.168531 # Detected MINSTKSIGSZ:4720
11451 11:47:24.171298 # ==>> completed. SKIP.
11452 11:47:24.178113 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11453 11:47:24.181418 ok 26 selftests: arm64: za_no_regs # SKIP
11454 11:47:24.187331 # selftests: arm64: za_regs
11455 11:47:24.239975 # Registered handlers for all signals.
11456 11:47:24.240517 # Detected MINSTKSIGSZ:4720
11457 11:47:24.243040 # ==>> completed. SKIP.
11458 11:47:24.249944 # # ZA register :: Check that we get the right ZA registers reported
11459 11:47:24.252987 ok 27 selftests: arm64: za_regs # SKIP
11460 11:47:24.259114 # selftests: arm64: pac
11461 11:47:24.312359 # TAP version 13
11462 11:47:24.312899 # 1..7
11463 11:47:24.315343 # # Starting 7 tests from 1 test cases.
11464 11:47:24.318876 # # RUN global.corrupt_pac ...
11465 11:47:24.322054 # # SKIP PAUTH not enabled
11466 11:47:24.325085 # # OK global.corrupt_pac
11467 11:47:24.328435 # ok 1 # SKIP PAUTH not enabled
11468 11:47:24.334902 # # RUN global.pac_instructions_not_nop ...
11469 11:47:24.338354 # # SKIP PAUTH not enabled
11470 11:47:24.341892 # # OK global.pac_instructions_not_nop
11471 11:47:24.344714 # ok 2 # SKIP PAUTH not enabled
11472 11:47:24.351796 # # RUN global.pac_instructions_not_nop_generic ...
11473 11:47:24.355193 # # SKIP Generic PAUTH not enabled
11474 11:47:24.357974 # # OK global.pac_instructions_not_nop_generic
11475 11:47:24.364602 # ok 3 # SKIP Generic PAUTH not enabled
11476 11:47:24.367934 # # RUN global.single_thread_different_keys ...
11477 11:47:24.371600 # # SKIP PAUTH not enabled
11478 11:47:24.377828 # # OK global.single_thread_different_keys
11479 11:47:24.378502 # ok 4 # SKIP PAUTH not enabled
11480 11:47:24.384642 # # RUN global.exec_changed_keys ...
11481 11:47:24.388166 # # SKIP PAUTH not enabled
11482 11:47:24.391184 # # OK global.exec_changed_keys
11483 11:47:24.394719 # ok 5 # SKIP PAUTH not enabled
11484 11:47:24.397907 # # RUN global.context_switch_keep_keys ...
11485 11:47:24.400977 # # SKIP PAUTH not enabled
11486 11:47:24.407853 # # OK global.context_switch_keep_keys
11487 11:47:24.408665 # ok 6 # SKIP PAUTH not enabled
11488 11:47:24.414599 # # RUN global.context_switch_keep_keys_generic ...
11489 11:47:24.417694 # # SKIP Generic PAUTH not enabled
11490 11:47:24.424485 # # OK global.context_switch_keep_keys_generic
11491 11:47:24.427569 # ok 7 # SKIP Generic PAUTH not enabled
11492 11:47:24.431149 # # PASSED: 7 / 7 tests passed.
11493 11:47:24.434124 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11494 11:47:24.437391 ok 28 selftests: arm64: pac
11495 11:47:24.440732 # selftests: arm64: fp-stress
11496 11:47:30.805017 <6>[ 46.158208] vpu: disabling
11497 11:47:30.808142 <6>[ 46.161258] vproc2: disabling
11498 11:47:30.811554 <6>[ 46.164529] vproc1: disabling
11499 11:47:30.814920 <6>[ 46.167802] vaud18: disabling
11500 11:47:30.821571 <6>[ 46.171220] vsram_others: disabling
11501 11:47:30.825060 <6>[ 46.175104] va09: disabling
11502 11:47:30.828195 <6>[ 46.178217] vsram_md: disabling
11503 11:47:30.828286 <6>[ 46.181707] Vgpu: disabling
11504 11:47:34.382890 # TAP version 13
11505 11:47:34.383042 # 1..16
11506 11:47:34.386174 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11507 11:47:34.389435 # # Will run for 10s
11508 11:47:34.389519 # # Started FPSIMD-0-0
11509 11:47:34.393020 # # Started FPSIMD-0-1
11510 11:47:34.396303 # # Started FPSIMD-1-0
11511 11:47:34.396386 # # Started FPSIMD-1-1
11512 11:47:34.399187 # # Started FPSIMD-2-0
11513 11:47:34.402338 # # Started FPSIMD-2-1
11514 11:47:34.402448 # # Started FPSIMD-3-0
11515 11:47:34.406108 # # Started FPSIMD-3-1
11516 11:47:34.406191 # # Started FPSIMD-4-0
11517 11:47:34.409264 # # Started FPSIMD-4-1
11518 11:47:34.412434 # # Started FPSIMD-5-0
11519 11:47:34.412515 # # Started FPSIMD-5-1
11520 11:47:34.415934 # # Started FPSIMD-6-0
11521 11:47:34.418945 # # Started FPSIMD-6-1
11522 11:47:34.419053 # # Started FPSIMD-7-0
11523 11:47:34.422494 # # Started FPSIMD-7-1
11524 11:47:34.425596 # # FPSIMD-1-1: Vector length: 128 bits
11525 11:47:34.428890 # # FPSIMD-1-1: PID: 1159
11526 11:47:34.432616 # # FPSIMD-0-0: Vector length: 128 bits
11527 11:47:34.432695 # # FPSIMD-0-0: PID: 1156
11528 11:47:34.435593 # # FPSIMD-2-1: Vector length: 128 bits
11529 11:47:34.439002 # # FPSIMD-2-1: PID: 1161
11530 11:47:34.442162 # # FPSIMD-1-0: Vector length: 128 bits
11531 11:47:34.445458 # # FPSIMD-1-0: PID: 1158
11532 11:47:34.448710 # # FPSIMD-0-1: Vector length: 128 bits
11533 11:47:34.452043 # # FPSIMD-0-1: PID: 1157
11534 11:47:34.455426 # # FPSIMD-2-0: Vector length: 128 bits
11535 11:47:34.455509 # # FPSIMD-2-0: PID: 1160
11536 11:47:34.461896 # # FPSIMD-5-0: Vector length: 128 bits
11537 11:47:34.461978 # # FPSIMD-5-0: PID: 1166
11538 11:47:34.465544 # # FPSIMD-4-1: Vector length: 128 bits
11539 11:47:34.468984 # # FPSIMD-4-1: PID: 1165
11540 11:47:34.472188 # # FPSIMD-3-1: Vector length: 128 bits
11541 11:47:34.475277 # # FPSIMD-3-1: PID: 1163
11542 11:47:34.478740 # # FPSIMD-3-0: Vector length: 128 bits
11543 11:47:34.481982 # # FPSIMD-3-0: PID: 1162
11544 11:47:34.485396 # # FPSIMD-6-1: Vector length: 128 bits
11545 11:47:34.485478 # # FPSIMD-6-1: PID: 1169
11546 11:47:34.488489 # # FPSIMD-4-0: Vector length: 128 bits
11547 11:47:34.492375 # # FPSIMD-4-0: PID: 1164
11548 11:47:34.495230 # # FPSIMD-5-1: Vector length: 128 bits
11549 11:47:34.498320 # # FPSIMD-5-1: PID: 1167
11550 11:47:34.501908 # # FPSIMD-6-0: Vector length: 128 bits
11551 11:47:34.505195 # # FPSIMD-6-0: PID: 1168
11552 11:47:34.508631 # # FPSIMD-7-1: Vector length: 128 bits
11553 11:47:34.511602 # # FPSIMD-7-1: PID: 1171
11554 11:47:34.514943 # # FPSIMD-7-0: Vector length: 128 bits
11555 11:47:34.515026 # # FPSIMD-7-0: PID: 1170
11556 11:47:34.518286 # # Finishing up...
11557 11:47:34.525263 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1805490, signals=10
11558 11:47:34.531549 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1376353, signals=10
11559 11:47:34.538339 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1120795, signals=10
11560 11:47:34.548288 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1079625, signals=10
11561 11:47:34.554813 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1079238, signals=10
11562 11:47:34.561348 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=2183995, signals=10
11563 11:47:34.567923 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1410220, signals=10
11564 11:47:34.571223 # ok 1 FPSIMD-0-0
11565 11:47:34.571306 # ok 2 FPSIMD-0-1
11566 11:47:34.574532 # ok 3 FPSIMD-1-0
11567 11:47:34.574657 # ok 4 FPSIMD-1-1
11568 11:47:34.577762 # ok 5 FPSIMD-2-0
11569 11:47:34.577846 # ok 6 FPSIMD-2-1
11570 11:47:34.581415 # ok 7 FPSIMD-3-0
11571 11:47:34.581498 # ok 8 FPSIMD-3-1
11572 11:47:34.584904 # ok 9 FPSIMD-4-0
11573 11:47:34.584987 # ok 10 FPSIMD-4-1
11574 11:47:34.587815 # ok 11 FPSIMD-5-0
11575 11:47:34.587898 # ok 12 FPSIMD-5-1
11576 11:47:34.591000 # ok 13 FPSIMD-6-0
11577 11:47:34.591082 # ok 14 FPSIMD-6-1
11578 11:47:34.594577 # ok 15 FPSIMD-7-0
11579 11:47:34.594660 # ok 16 FPSIMD-7-1
11580 11:47:34.600959 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1647806, signals=9
11581 11:47:34.611188 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1154703, signals=9
11582 11:47:34.617772 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=964845, signals=10
11583 11:47:34.624173 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1082958, signals=10
11584 11:47:34.631274 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1299568, signals=10
11585 11:47:34.637478 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1200763, signals=10
11586 11:47:34.644054 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=969975, signals=10
11587 11:47:34.653897 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1008146, signals=9
11588 11:47:34.660915 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=987168, signals=10
11589 11:47:34.663987 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11590 11:47:34.667268 ok 29 selftests: arm64: fp-stress
11591 11:47:34.670870 # selftests: arm64: sve-ptrace
11592 11:47:34.670952 # TAP version 13
11593 11:47:34.673810 # 1..4104
11594 11:47:34.677372 # ok 2 # SKIP SVE not available
11595 11:47:34.680832 # # Planned tests != run tests (4104 != 1)
11596 11:47:34.683961 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11597 11:47:34.687276 ok 30 selftests: arm64: sve-ptrace # SKIP
11598 11:47:34.690739 # selftests: arm64: sve-probe-vls
11599 11:47:34.693921 # TAP version 13
11600 11:47:34.694023 # 1..2
11601 11:47:34.697389 # ok 2 # SKIP SVE not available
11602 11:47:34.700522 # # Planned tests != run tests (2 != 1)
11603 11:47:34.703856 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11604 11:47:34.710312 ok 31 selftests: arm64: sve-probe-vls # SKIP
11605 11:47:34.710421 # selftests: arm64: vec-syscfg
11606 11:47:34.713971 # TAP version 13
11607 11:47:34.714088 # 1..20
11608 11:47:34.716958 # ok 1 # SKIP SVE not supported
11609 11:47:34.720374 # ok 2 # SKIP SVE not supported
11610 11:47:34.724033 # ok 3 # SKIP SVE not supported
11611 11:47:34.727119 # ok 4 # SKIP SVE not supported
11612 11:47:34.730251 # ok 5 # SKIP SVE not supported
11613 11:47:34.730337 # ok 6 # SKIP SVE not supported
11614 11:47:34.733568 # ok 7 # SKIP SVE not supported
11615 11:47:34.736927 # ok 8 # SKIP SVE not supported
11616 11:47:34.740065 # ok 9 # SKIP SVE not supported
11617 11:47:34.743865 # ok 10 # SKIP SVE not supported
11618 11:47:34.746927 # ok 11 # SKIP SME not supported
11619 11:47:34.750234 # ok 12 # SKIP SME not supported
11620 11:47:34.753358 # ok 13 # SKIP SME not supported
11621 11:47:34.753443 # ok 14 # SKIP SME not supported
11622 11:47:34.756821 # ok 15 # SKIP SME not supported
11623 11:47:34.760451 # ok 16 # SKIP SME not supported
11624 11:47:34.763298 # ok 17 # SKIP SME not supported
11625 11:47:34.766891 # ok 18 # SKIP SME not supported
11626 11:47:34.769936 # ok 19 # SKIP SME not supported
11627 11:47:34.773531 # ok 20 # SKIP SME not supported
11628 11:47:34.776486 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11629 11:47:34.779773 ok 32 selftests: arm64: vec-syscfg
11630 11:47:34.783166 # selftests: arm64: za-fork
11631 11:47:34.786883 # TAP version 13
11632 11:47:34.786968 # 1..1
11633 11:47:34.787052 # # PID: 1246
11634 11:47:34.789905 # # SME support not present
11635 11:47:34.789990 # ok 0 skipped
11636 11:47:34.796559 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11637 11:47:34.799690 ok 33 selftests: arm64: za-fork
11638 11:47:34.802905 # selftests: arm64: za-ptrace
11639 11:47:34.802990 # TAP version 13
11640 11:47:34.803074 # 1..1
11641 11:47:34.806118 # ok 2 # SKIP SME not available
11642 11:47:34.812962 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11643 11:47:34.816138 ok 34 selftests: arm64: za-ptrace # SKIP
11644 11:47:34.819558 # selftests: arm64: check_buffer_fill
11645 11:47:34.839236 # # SKIP: MTE features unavailable
11646 11:47:34.847304 ok 35 selftests: arm64: check_buffer_fill # SKIP
11647 11:47:34.861883 # selftests: arm64: check_child_memory
11648 11:47:34.920387 # # SKIP: MTE features unavailable
11649 11:47:34.928048 ok 36 selftests: arm64: check_child_memory # SKIP
11650 11:47:34.942524 # selftests: arm64: check_gcr_el1_cswitch
11651 11:47:34.986903 # # SKIP: MTE features unavailable
11652 11:47:34.994253 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11653 11:47:35.004548 # selftests: arm64: check_ksm_options
11654 11:47:35.050482 # # SKIP: MTE features unavailable
11655 11:47:35.058049 ok 38 selftests: arm64: check_ksm_options # SKIP
11656 11:47:35.071274 # selftests: arm64: check_mmap_options
11657 11:47:35.134705 # # SKIP: MTE features unavailable
11658 11:47:35.142707 ok 39 selftests: arm64: check_mmap_options # SKIP
11659 11:47:35.154878 # selftests: arm64: check_prctl
11660 11:47:35.190339 # TAP version 13
11661 11:47:35.190460 # 1..5
11662 11:47:35.193934 # ok 1 check_basic_read
11663 11:47:35.194021 # ok 2 NONE
11664 11:47:35.196870 # ok 3 # SKIP SYNC
11665 11:47:35.196956 # ok 4 # SKIP ASYNC
11666 11:47:35.200495 # ok 5 # SKIP SYNC+ASYNC
11667 11:47:35.203756 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11668 11:47:35.207253 ok 40 selftests: arm64: check_prctl
11669 11:47:35.213439 # selftests: arm64: check_tags_inclusion
11670 11:47:35.264824 # # SKIP: MTE features unavailable
11671 11:47:35.271596 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11672 11:47:35.280685 # selftests: arm64: check_user_mem
11673 11:47:35.337838 # # SKIP: MTE features unavailable
11674 11:47:35.345530 ok 42 selftests: arm64: check_user_mem # SKIP
11675 11:47:35.355474 # selftests: arm64: btitest
11676 11:47:35.418371 # TAP version 13
11677 11:47:35.418483 # 1..18
11678 11:47:35.421978 # # HWCAP_PACA not present
11679 11:47:35.425008 # # HWCAP2_BTI not present
11680 11:47:35.425085 # # Test binary built for BTI
11681 11:47:35.431890 # ok 1 nohint_func/call_using_br_x0 # SKIP
11682 11:47:35.434922 # ok 1 nohint_func/call_using_br_x16 # SKIP
11683 11:47:35.438522 # ok 1 nohint_func/call_using_blr # SKIP
11684 11:47:35.441613 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11685 11:47:35.444673 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11686 11:47:35.448229 # ok 1 bti_none_func/call_using_blr # SKIP
11687 11:47:35.454892 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11688 11:47:35.458096 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11689 11:47:35.461278 # ok 1 bti_c_func/call_using_blr # SKIP
11690 11:47:35.464734 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11691 11:47:35.467918 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11692 11:47:35.471285 # ok 1 bti_j_func/call_using_blr # SKIP
11693 11:47:35.474439 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11694 11:47:35.481283 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11695 11:47:35.484454 # ok 1 bti_jc_func/call_using_blr # SKIP
11696 11:47:35.487849 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11697 11:47:35.491096 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11698 11:47:35.494366 # ok 1 paciasp_func/call_using_blr # SKIP
11699 11:47:35.501240 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11700 11:47:35.504660 # # WARNING - EXPECTED TEST COUNT WRONG
11701 11:47:35.507747 ok 43 selftests: arm64: btitest
11702 11:47:35.507832 # selftests: arm64: nobtitest
11703 11:47:35.510835 # TAP version 13
11704 11:47:35.510919 # 1..18
11705 11:47:35.514313 # # HWCAP_PACA not present
11706 11:47:35.517526 # # HWCAP2_BTI not present
11707 11:47:35.521014 # # Test binary not built for BTI
11708 11:47:35.524478 # ok 1 nohint_func/call_using_br_x0 # SKIP
11709 11:47:35.527355 # ok 1 nohint_func/call_using_br_x16 # SKIP
11710 11:47:35.530500 # ok 1 nohint_func/call_using_blr # SKIP
11711 11:47:35.533901 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11712 11:47:35.537110 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11713 11:47:35.544163 # ok 1 bti_none_func/call_using_blr # SKIP
11714 11:47:35.547203 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11715 11:47:35.550337 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11716 11:47:35.553925 # ok 1 bti_c_func/call_using_blr # SKIP
11717 11:47:35.557272 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11718 11:47:35.560571 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11719 11:47:35.563470 # ok 1 bti_j_func/call_using_blr # SKIP
11720 11:47:35.570259 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11721 11:47:35.573391 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11722 11:47:35.577059 # ok 1 bti_jc_func/call_using_blr # SKIP
11723 11:47:35.580264 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11724 11:47:35.583787 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11725 11:47:35.586706 # ok 1 paciasp_func/call_using_blr # SKIP
11726 11:47:35.593220 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11727 11:47:35.596898 # # WARNING - EXPECTED TEST COUNT WRONG
11728 11:47:35.600071 ok 44 selftests: arm64: nobtitest
11729 11:47:35.603024 # selftests: arm64: hwcap
11730 11:47:35.603099 # TAP version 13
11731 11:47:35.603162 # 1..28
11732 11:47:35.606478 # ok 1 cpuinfo_match_RNG
11733 11:47:35.609666 # # SIGILL reported for RNG
11734 11:47:35.609738 # ok 2 # SKIP sigill_RNG
11735 11:47:35.612950 # ok 3 cpuinfo_match_SME
11736 11:47:35.616442 # ok 4 sigill_SME
11737 11:47:35.616547 # ok 5 cpuinfo_match_SVE
11738 11:47:35.619678 # ok 6 sigill_SVE
11739 11:47:35.623248 # ok 7 cpuinfo_match_SVE 2
11740 11:47:35.623331 # # SIGILL reported for SVE 2
11741 11:47:35.626353 # ok 8 # SKIP sigill_SVE 2
11742 11:47:35.629574 # ok 9 cpuinfo_match_SVE AES
11743 11:47:35.632712 # # SIGILL reported for SVE AES
11744 11:47:35.636300 # ok 10 # SKIP sigill_SVE AES
11745 11:47:35.636383 # ok 11 cpuinfo_match_SVE2 PMULL
11746 11:47:35.639502 # # SIGILL reported for SVE2 PMULL
11747 11:47:35.642709 # ok 12 # SKIP sigill_SVE2 PMULL
11748 11:47:35.646247 # ok 13 cpuinfo_match_SVE2 BITPERM
11749 11:47:35.649308 # # SIGILL reported for SVE2 BITPERM
11750 11:47:35.652594 # ok 14 # SKIP sigill_SVE2 BITPERM
11751 11:47:35.655913 # ok 15 cpuinfo_match_SVE2 SHA3
11752 11:47:35.659542 # # SIGILL reported for SVE2 SHA3
11753 11:47:35.662665 # ok 16 # SKIP sigill_SVE2 SHA3
11754 11:47:35.666222 # ok 17 cpuinfo_match_SVE2 SM4
11755 11:47:35.669320 # # SIGILL reported for SVE2 SM4
11756 11:47:35.669405 # ok 18 # SKIP sigill_SVE2 SM4
11757 11:47:35.672745 # ok 19 cpuinfo_match_SVE2 I8MM
11758 11:47:35.675766 # # SIGILL reported for SVE2 I8MM
11759 11:47:35.679244 # ok 20 # SKIP sigill_SVE2 I8MM
11760 11:47:35.682493 # ok 21 cpuinfo_match_SVE2 F32MM
11761 11:47:35.685810 # # SIGILL reported for SVE2 F32MM
11762 11:47:35.689272 # ok 22 # SKIP sigill_SVE2 F32MM
11763 11:47:35.692484 # ok 23 cpuinfo_match_SVE2 F64MM
11764 11:47:35.695682 # # SIGILL reported for SVE2 F64MM
11765 11:47:35.699235 # ok 24 # SKIP sigill_SVE2 F64MM
11766 11:47:35.699319 # ok 25 cpuinfo_match_SVE2 BF16
11767 11:47:35.702147 # # SIGILL reported for SVE2 BF16
11768 11:47:35.706126 # ok 26 # SKIP sigill_SVE2 BF16
11769 11:47:35.708978 # ok 27 cpuinfo_match_SVE2 EBF16
11770 11:47:35.712163 # ok 28 # SKIP sigill_SVE2 EBF16
11771 11:47:35.718633 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11772 11:47:35.718718 ok 45 selftests: arm64: hwcap
11773 11:47:35.722131 # selftests: arm64: ptrace
11774 11:47:35.725614 # TAP version 13
11775 11:47:35.725698 # 1..7
11776 11:47:35.728633 # # Parent is 1488, child is 1489
11777 11:47:35.728717 # ok 1 read_tpidr_one
11778 11:47:35.731782 # ok 2 write_tpidr_one
11779 11:47:35.735446 # ok 3 verify_tpidr_one
11780 11:47:35.735530 # ok 4 count_tpidrs
11781 11:47:35.738560 # ok 5 tpidr2_write
11782 11:47:35.738643 # ok 6 tpidr2_read
11783 11:47:35.741993 # ok 7 write_tpidr_only
11784 11:47:35.744962 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11785 11:47:35.748451 ok 46 selftests: arm64: ptrace
11786 11:47:35.751892 # selftests: arm64: syscall-abi
11787 11:47:35.755023 # TAP version 13
11788 11:47:35.755107 # 1..2
11789 11:47:35.755173 # ok 1 getpid() FPSIMD
11790 11:47:35.758326 # ok 2 sched_yield() FPSIMD
11791 11:47:35.764980 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11792 11:47:35.768485 ok 47 selftests: arm64: syscall-abi
11793 11:47:35.768570 # selftests: arm64: tpidr2
11794 11:47:35.797058 # TAP version 13
11795 11:47:35.797174 # 1..5
11796 11:47:35.800740 # # PID: 1525
11797 11:47:35.800825 # # SME support not present
11798 11:47:35.803537 # ok 0 skipped, TPIDR2 not supported
11799 11:47:35.807083 # ok 1 skipped, TPIDR2 not supported
11800 11:47:35.810361 # ok 2 skipped, TPIDR2 not supported
11801 11:47:35.813833 # ok 3 skipped, TPIDR2 not supported
11802 11:47:35.816989 # ok 4 skipped, TPIDR2 not supported
11803 11:47:35.823459 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11804 11:47:35.826901 ok 48 selftests: arm64: tpidr2
11805 11:47:36.507501 arm64_tags_test pass
11806 11:47:36.511292 arm64_run_tags_test_sh pass
11807 11:47:36.514477 arm64_fake_sigreturn_bad_magic pass
11808 11:47:36.517530 arm64_fake_sigreturn_bad_size pass
11809 11:47:36.520798 arm64_fake_sigreturn_bad_size_for_magic0 pass
11810 11:47:36.524233 arm64_fake_sigreturn_duplicated_fpsimd pass
11811 11:47:36.527587 arm64_fake_sigreturn_misaligned_sp pass
11812 11:47:36.530654 arm64_fake_sigreturn_missing_fpsimd pass
11813 11:47:36.534229 arm64_fake_sigreturn_sme_change_vl skip
11814 11:47:36.537488 arm64_fake_sigreturn_sve_change_vl skip
11815 11:47:36.543978 arm64_mangle_pstate_invalid_compat_toggle pass
11816 11:47:36.547240 arm64_mangle_pstate_invalid_daif_bits pass
11817 11:47:36.550498 arm64_mangle_pstate_invalid_mode_el1h pass
11818 11:47:36.554021 arm64_mangle_pstate_invalid_mode_el1t pass
11819 11:47:36.557287 arm64_mangle_pstate_invalid_mode_el2h pass
11820 11:47:36.563682 arm64_mangle_pstate_invalid_mode_el2t pass
11821 11:47:36.567408 arm64_mangle_pstate_invalid_mode_el3h pass
11822 11:47:36.570538 arm64_mangle_pstate_invalid_mode_el3t pass
11823 11:47:36.574182 arm64_sme_trap_no_sm skip
11824 11:47:36.574266 arm64_sme_trap_non_streaming skip
11825 11:47:36.577112 arm64_sme_trap_za pass
11826 11:47:36.580403 arm64_sme_vl skip
11827 11:47:36.580488 arm64_ssve_regs skip
11828 11:47:36.583678 arm64_sve_regs skip
11829 11:47:36.583762 arm64_sve_vl skip
11830 11:47:36.587278 arm64_za_no_regs skip
11831 11:47:36.587361 arm64_za_regs skip
11832 11:47:36.590260 arm64_pac_pauth_not_enabled skip
11833 11:47:36.593586 arm64_pac_pauth_not_enabled skip
11834 11:47:36.597058 arm64_pac_generic_pauth_not_enabled skip
11835 11:47:36.600618 arm64_pac_pauth_not_enabled skip
11836 11:47:36.603686 arm64_pac_pauth_not_enabled skip
11837 11:47:36.606916 arm64_pac_pauth_not_enabled skip
11838 11:47:36.610412 arm64_pac_generic_pauth_not_enabled skip
11839 11:47:36.610509 arm64_pac pass
11840 11:47:36.613653 arm64_fp-stress_FPSIMD-0-0 pass
11841 11:47:36.617212 arm64_fp-stress_FPSIMD-0-1 pass
11842 11:47:36.620222 arm64_fp-stress_FPSIMD-1-0 pass
11843 11:47:36.623804 arm64_fp-stress_FPSIMD-1-1 pass
11844 11:47:36.627034 arm64_fp-stress_FPSIMD-2-0 pass
11845 11:47:36.630242 arm64_fp-stress_FPSIMD-2-1 pass
11846 11:47:36.630326 arm64_fp-stress_FPSIMD-3-0 pass
11847 11:47:36.633602 arm64_fp-stress_FPSIMD-3-1 pass
11848 11:47:36.637168 arm64_fp-stress_FPSIMD-4-0 pass
11849 11:47:36.640202 arm64_fp-stress_FPSIMD-4-1 pass
11850 11:47:36.643573 arm64_fp-stress_FPSIMD-5-0 pass
11851 11:47:36.647272 arm64_fp-stress_FPSIMD-5-1 pass
11852 11:47:36.650346 arm64_fp-stress_FPSIMD-6-0 pass
11853 11:47:36.650461 arm64_fp-stress_FPSIMD-6-1 pass
11854 11:47:36.653555 arm64_fp-stress_FPSIMD-7-0 pass
11855 11:47:36.656935 arm64_fp-stress_FPSIMD-7-1 pass
11856 11:47:36.660459 arm64_fp-stress pass
11857 11:47:36.663539 arm64_sve-ptrace_sve_not_available skip
11858 11:47:36.663622 arm64_sve-ptrace skip
11859 11:47:36.670181 arm64_sve-probe-vls_sve_not_available skip
11860 11:47:36.670281 arm64_sve-probe-vls skip
11861 11:47:36.673365 arm64_vec-syscfg_sve_not_supported skip
11862 11:47:36.676744 arm64_vec-syscfg_sve_not_supported skip
11863 11:47:36.680223 arm64_vec-syscfg_sve_not_supported skip
11864 11:47:36.686802 arm64_vec-syscfg_sve_not_supported skip
11865 11:47:36.690178 arm64_vec-syscfg_sve_not_supported skip
11866 11:47:36.693575 arm64_vec-syscfg_sve_not_supported skip
11867 11:47:36.696805 arm64_vec-syscfg_sve_not_supported skip
11868 11:47:36.700343 arm64_vec-syscfg_sve_not_supported skip
11869 11:47:36.703364 arm64_vec-syscfg_sve_not_supported skip
11870 11:47:36.706926 arm64_vec-syscfg_sve_not_supported skip
11871 11:47:36.710258 arm64_vec-syscfg_sme_not_supported skip
11872 11:47:36.713445 arm64_vec-syscfg_sme_not_supported skip
11873 11:47:36.716865 arm64_vec-syscfg_sme_not_supported skip
11874 11:47:36.720147 arm64_vec-syscfg_sme_not_supported skip
11875 11:47:36.723387 arm64_vec-syscfg_sme_not_supported skip
11876 11:47:36.726798 arm64_vec-syscfg_sme_not_supported skip
11877 11:47:36.730189 arm64_vec-syscfg_sme_not_supported skip
11878 11:47:36.733538 arm64_vec-syscfg_sme_not_supported skip
11879 11:47:36.740030 arm64_vec-syscfg_sme_not_supported skip
11880 11:47:36.743422 arm64_vec-syscfg_sme_not_supported skip
11881 11:47:36.743506 arm64_vec-syscfg pass
11882 11:47:36.746581 arm64_za-fork_skipped pass
11883 11:47:36.746681 arm64_za-fork pass
11884 11:47:36.753244 arm64_za-ptrace_sme_not_available skip
11885 11:47:36.753328 arm64_za-ptrace skip
11886 11:47:36.756411 arm64_check_buffer_fill skip
11887 11:47:36.759775 arm64_check_child_memory skip
11888 11:47:36.763212 arm64_check_gcr_el1_cswitch skip
11889 11:47:36.763296 arm64_check_ksm_options skip
11890 11:47:36.766358 arm64_check_mmap_options skip
11891 11:47:36.770179 arm64_check_prctl_check_basic_read pass
11892 11:47:36.773190 arm64_check_prctl_NONE pass
11893 11:47:36.776689 arm64_check_prctl_sync skip
11894 11:47:36.779938 arm64_check_prctl_async skip
11895 11:47:36.780021 arm64_check_prctl_sync_async skip
11896 11:47:36.783024 arm64_check_prctl pass
11897 11:47:36.786209 arm64_check_tags_inclusion skip
11898 11:47:36.789617 arm64_check_user_mem skip
11899 11:47:36.792972 arm64_btitest_nohint_func_call_using_br_x0 skip
11900 11:47:36.796127 arm64_btitest_nohint_func_call_using_br_x16 skip
11901 11:47:36.803381 arm64_btitest_nohint_func_call_using_blr skip
11902 11:47:36.806186 arm64_btitest_bti_none_func_call_using_br_x0 skip
11903 11:47:36.809446 arm64_btitest_bti_none_func_call_using_br_x16 skip
11904 11:47:36.816170 arm64_btitest_bti_none_func_call_using_blr skip
11905 11:47:36.819514 arm64_btitest_bti_c_func_call_using_br_x0 skip
11906 11:47:36.822751 arm64_btitest_bti_c_func_call_using_br_x16 skip
11907 11:47:36.825927 arm64_btitest_bti_c_func_call_using_blr skip
11908 11:47:36.832745 arm64_btitest_bti_j_func_call_using_br_x0 skip
11909 11:47:36.835751 arm64_btitest_bti_j_func_call_using_br_x16 skip
11910 11:47:36.839058 arm64_btitest_bti_j_func_call_using_blr skip
11911 11:47:36.842317 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11912 11:47:36.848871 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11913 11:47:36.852164 arm64_btitest_bti_jc_func_call_using_blr skip
11914 11:47:36.855492 arm64_btitest_paciasp_func_call_using_br_x0 skip
11915 11:47:36.861894 arm64_btitest_paciasp_func_call_using_br_x16 skip
11916 11:47:36.865227 arm64_btitest_paciasp_func_call_using_blr skip
11917 11:47:36.865310 arm64_btitest pass
11918 11:47:36.871959 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11919 11:47:36.875579 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11920 11:47:36.878838 arm64_nobtitest_nohint_func_call_using_blr skip
11921 11:47:36.885226 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11922 11:47:36.888653 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11923 11:47:36.895683 arm64_nobtitest_bti_none_func_call_using_blr skip
11924 11:47:36.898458 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11925 11:47:36.901762 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11926 11:47:36.905210 arm64_nobtitest_bti_c_func_call_using_blr skip
11927 11:47:36.911687 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11928 11:47:36.914983 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11929 11:47:36.918277 arm64_nobtitest_bti_j_func_call_using_blr skip
11930 11:47:36.925026 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11931 11:47:36.928455 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11932 11:47:36.931408 arm64_nobtitest_bti_jc_func_call_using_blr skip
11933 11:47:36.937976 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11934 11:47:36.941423 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11935 11:47:36.944588 arm64_nobtitest_paciasp_func_call_using_blr skip
11936 11:47:36.947964 arm64_nobtitest pass
11937 11:47:36.951178 arm64_hwcap_cpuinfo_match_RNG pass
11938 11:47:36.954744 arm64_hwcap_sigill_rng skip
11939 11:47:36.957946 arm64_hwcap_cpuinfo_match_SME pass
11940 11:47:36.958028 arm64_hwcap_sigill_SME pass
11941 11:47:36.961358 arm64_hwcap_cpuinfo_match_SVE pass
11942 11:47:36.964454 arm64_hwcap_sigill_SVE pass
11943 11:47:36.968234 arm64_hwcap_cpuinfo_match_SVE_2 pass
11944 11:47:36.971321 arm64_hwcap_sigill_sve_2 skip
11945 11:47:36.974393 arm64_hwcap_cpuinfo_match_SVE_AES pass
11946 11:47:36.977648 arm64_hwcap_sigill_sve_aes skip
11947 11:47:36.981296 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11948 11:47:36.984370 arm64_hwcap_sigill_sve2_pmull skip
11949 11:47:36.987721 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11950 11:47:36.991409 arm64_hwcap_sigill_sve2_bitperm skip
11951 11:47:36.994490 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11952 11:47:36.997883 arm64_hwcap_sigill_sve2_sha3 skip
11953 11:47:37.001164 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11954 11:47:37.004754 arm64_hwcap_sigill_sve2_sm4 skip
11955 11:47:37.007464 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11956 11:47:37.010893 arm64_hwcap_sigill_sve2_i8mm skip
11957 11:47:37.014570 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11958 11:47:37.017266 arm64_hwcap_sigill_sve2_f32mm skip
11959 11:47:37.020864 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11960 11:47:37.024231 arm64_hwcap_sigill_sve2_f64mm skip
11961 11:47:37.027346 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11962 11:47:37.030715 arm64_hwcap_sigill_sve2_bf16 skip
11963 11:47:37.033844 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11964 11:47:37.037522 arm64_hwcap_sigill_sve2_ebf16 skip
11965 11:47:37.040457 arm64_hwcap pass
11966 11:47:37.043963 arm64_ptrace_read_tpidr_one pass
11967 11:47:37.047326 arm64_ptrace_write_tpidr_one pass
11968 11:47:37.050335 arm64_ptrace_verify_tpidr_one pass
11969 11:47:37.050443 arm64_ptrace_count_tpidrs pass
11970 11:47:37.053997 arm64_ptrace_tpidr2_write pass
11971 11:47:37.057157 arm64_ptrace_tpidr2_read pass
11972 11:47:37.060281 arm64_ptrace_write_tpidr_only pass
11973 11:47:37.063574 arm64_ptrace pass
11974 11:47:37.066929 arm64_syscall-abi_getpid_FPSIMD pass
11975 11:47:37.070315 arm64_syscall-abi_sched_yield_FPSIMD pass
11976 11:47:37.070457 arm64_syscall-abi pass
11977 11:47:37.076718 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11978 11:47:37.079999 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11979 11:47:37.083748 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11980 11:47:37.086913 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11981 11:47:37.093505 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11982 11:47:37.093588 arm64_tpidr2 pass
11983 11:47:37.097124 + ../../utils/send-to-lava.sh ./output/result.txt
11984 11:47:37.103607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11985 11:47:37.103885 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11987 11:47:37.110210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11988 11:47:37.110490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11990 11:47:37.116915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11991 11:47:37.117197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11993 11:47:37.123023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11994 11:47:37.123279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11996 11:47:37.129839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11997 11:47:37.130103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11999 11:47:37.136312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12000 11:47:37.136565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12002 11:47:37.146118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12003 11:47:37.146370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12005 11:47:37.171125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12006 11:47:37.171379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12008 11:47:37.214556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12009 11:47:37.214825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12011 11:47:37.256351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12012 11:47:37.256608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12014 11:47:37.297714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12015 11:47:37.297992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12017 11:47:37.333999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12018 11:47:37.334294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12020 11:47:37.374911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12021 11:47:37.375163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12023 11:47:37.411091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12024 11:47:37.411387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12026 11:47:37.446925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12027 11:47:37.447206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12029 11:47:37.485886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12030 11:47:37.486184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12032 11:47:37.523708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12033 11:47:37.523999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12035 11:47:37.557778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12036 11:47:37.558059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12038 11:47:37.593559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12039 11:47:37.593845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12041 11:47:37.621896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12042 11:47:37.622181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12044 11:47:37.662847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12046 11:47:37.666000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12047 11:47:37.698895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12048 11:47:37.699158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12050 11:47:37.734624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12051 11:47:37.734883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12053 11:47:37.767418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12054 11:47:37.767695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12056 11:47:37.802721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12057 11:47:37.802987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12059 11:47:37.838890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12060 11:47:37.839153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12062 11:47:37.870769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12063 11:47:37.871024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12065 11:47:37.902145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12066 11:47:37.902444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12068 11:47:37.934116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12070 11:47:37.937020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12071 11:47:37.970679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12073 11:47:37.973875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12074 11:47:38.014682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12075 11:47:38.014948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12077 11:47:38.043754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12079 11:47:38.046109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12080 11:47:38.080309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12082 11:47:38.083737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12083 11:47:38.115463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12085 11:47:38.118732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12086 11:47:38.162222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12087 11:47:38.162484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12089 11:47:38.202063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12090 11:47:38.202327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12092 11:47:38.239277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12093 11:47:38.239536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12095 11:47:38.275318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12096 11:47:38.275577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12098 11:47:38.315153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12099 11:47:38.315416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12101 11:47:38.354366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12102 11:47:38.354636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12104 11:47:38.388870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12105 11:47:38.389139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12107 11:47:38.423473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12108 11:47:38.423736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12110 11:47:38.463231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12111 11:47:38.463505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12113 11:47:38.499948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12114 11:47:38.500224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12116 11:47:38.535132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12117 11:47:38.535387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12119 11:47:38.570344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12120 11:47:38.570619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12122 11:47:38.608500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12123 11:47:38.608770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12125 11:47:38.642546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12126 11:47:38.642828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12128 11:47:38.682562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12129 11:47:38.682824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12131 11:47:38.720730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12132 11:47:38.721023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12134 11:47:38.758290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12135 11:47:38.758615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12137 11:47:38.796169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12138 11:47:38.796465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12140 11:47:38.829714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12141 11:47:38.829987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12143 11:47:38.870711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12144 11:47:38.870967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12146 11:47:38.908878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12147 11:47:38.909140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12149 11:47:38.952830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12150 11:47:38.953110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12152 11:47:38.990174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12153 11:47:38.990471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12155 11:47:39.035596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12156 11:47:39.035859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12158 11:47:39.075622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12159 11:47:39.075883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12161 11:47:39.111432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12162 11:47:39.111695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12164 11:47:39.148707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12165 11:47:39.148975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12167 11:47:39.185957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12168 11:47:39.186223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12170 11:47:39.222573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12171 11:47:39.222831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12173 11:47:39.256063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12174 11:47:39.256321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12176 11:47:39.297773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12177 11:47:39.298040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12179 11:47:39.338913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12180 11:47:39.339172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12182 11:47:39.380514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12183 11:47:39.380776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12185 11:47:39.421748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12186 11:47:39.422016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12188 11:47:39.457985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12189 11:47:39.458244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12191 11:47:39.497302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12192 11:47:39.497609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12194 11:47:39.533814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12195 11:47:39.534073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12197 11:47:39.573939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12198 11:47:39.574194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12200 11:47:39.610980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12201 11:47:39.611243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12203 11:47:39.647995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12204 11:47:39.648253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12206 11:47:39.686922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12207 11:47:39.687181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12209 11:47:39.725684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12210 11:47:39.725946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12212 11:47:39.758405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12213 11:47:39.758662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12215 11:47:39.789522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12216 11:47:39.789788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12218 11:47:39.826074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12219 11:47:39.826345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12221 11:47:39.861427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12222 11:47:39.861687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12224 11:47:39.900888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12225 11:47:39.901152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12227 11:47:39.937876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12228 11:47:39.938141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12230 11:47:39.978610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12231 11:47:39.978866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12233 11:47:40.019193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12234 11:47:40.019460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12236 11:47:40.054528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12237 11:47:40.054788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12239 11:47:40.090217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12240 11:47:40.090476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12242 11:47:40.123346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12243 11:47:40.123603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12245 11:47:40.163222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12246 11:47:40.163487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12248 11:47:40.192552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12249 11:47:40.192814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12251 11:47:40.225154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12252 11:47:40.225415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12254 11:47:40.257010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12255 11:47:40.257268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12257 11:47:40.294499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12259 11:47:40.297264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12260 11:47:40.330228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12261 11:47:40.330514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12263 11:47:40.366991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12264 11:47:40.367251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12266 11:47:40.405759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12267 11:47:40.406022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12269 11:47:40.447437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12270 11:47:40.447706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12272 11:47:40.486888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12273 11:47:40.487153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12275 11:47:40.528621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12276 11:47:40.528909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12278 11:47:40.563578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12279 11:47:40.563840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12281 11:47:40.604112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12282 11:47:40.604374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12284 11:47:40.637437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12285 11:47:40.637722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12287 11:47:40.670930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12288 11:47:40.671187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12290 11:47:40.709163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12291 11:47:40.709429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12293 11:47:40.741993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12294 11:47:40.742279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12296 11:47:40.779632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12297 11:47:40.779895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12299 11:47:40.822298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12300 11:47:40.822623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12302 11:47:40.858680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12303 11:47:40.858971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12305 11:47:40.894356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12306 11:47:40.894662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12308 11:47:40.930747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12309 11:47:40.931035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12311 11:47:40.965264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12312 11:47:40.965519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12314 11:47:41.007260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12315 11:47:41.007529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12317 11:47:41.049964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12318 11:47:41.050253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12320 11:47:41.086568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12321 11:47:41.086830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12323 11:47:41.119517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12324 11:47:41.119804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12326 11:47:41.159111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12327 11:47:41.159400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12329 11:47:41.198192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12330 11:47:41.198508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12332 11:47:41.236892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12333 11:47:41.237156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12335 11:47:41.273220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12336 11:47:41.273507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12338 11:47:41.304238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12339 11:47:41.304502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12341 11:47:41.341626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12342 11:47:41.341919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12344 11:47:41.380517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12345 11:47:41.380774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12347 11:47:41.420200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12348 11:47:41.420471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12350 11:47:41.460235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12351 11:47:41.460524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12353 11:47:41.501583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12354 11:47:41.501869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12356 11:47:41.534304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12357 11:47:41.534641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12359 11:47:41.569366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12360 11:47:41.569647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12362 11:47:41.607267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12363 11:47:41.607556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12365 11:47:41.643929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12366 11:47:41.644195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12368 11:47:41.690001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12369 11:47:41.690269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12371 11:47:41.730617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12372 11:47:41.730908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12374 11:47:41.768576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12375 11:47:41.768866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12377 11:47:41.804499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12378 11:47:41.804758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12380 11:47:41.832115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12381 11:47:41.832373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12383 11:47:41.875881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12384 11:47:41.876146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12386 11:47:41.913868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12387 11:47:41.914132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12389 11:47:41.953662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12390 11:47:41.953926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12392 11:47:41.987491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12393 11:47:41.987751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12395 11:47:42.029614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12396 11:47:42.029880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12398 11:47:42.062685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12399 11:47:42.062947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12401 11:47:42.104260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12402 11:47:42.104524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12404 11:47:42.144019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12405 11:47:42.144281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12407 11:47:42.187063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12408 11:47:42.187330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12410 11:47:42.220255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12411 11:47:42.220515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12413 11:47:42.260249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12414 11:47:42.260511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12416 11:47:42.300928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12418 11:47:42.303897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12419 11:47:42.345107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12420 11:47:42.345402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12422 11:47:42.382282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12423 11:47:42.382610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12425 11:47:42.417542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12426 11:47:42.417806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12428 11:47:42.452627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12430 11:47:42.455908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12431 11:47:42.489505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12432 11:47:42.489767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12434 11:47:42.523949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12436 11:47:42.526748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12437 11:47:42.560571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12438 11:47:42.560855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12440 11:47:42.596823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12442 11:47:42.599814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12443 11:47:42.633293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12444 11:47:42.633639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12446 11:47:42.673973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12447 11:47:42.674300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12449 11:47:42.713631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12450 11:47:42.713910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12452 11:47:42.749600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12453 11:47:42.749870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12455 11:47:42.793461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12456 11:47:42.793761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12458 11:47:42.832859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12460 11:47:42.835975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12461 11:47:42.874350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12462 11:47:42.874645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12464 11:47:42.913500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12465 11:47:42.913809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12467 11:47:42.942567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12468 11:47:42.942828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12470 11:47:42.976341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12472 11:47:42.979277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12473 11:47:43.012649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12475 11:47:43.015799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12476 11:47:43.053540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12477 11:47:43.053802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12479 11:47:43.088829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12480 11:47:43.089087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12482 11:47:43.123662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12483 11:47:43.123921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12485 11:47:43.159466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12486 11:47:43.159728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12488 11:47:43.193974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12489 11:47:43.194229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12491 11:47:43.226751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12492 11:47:43.227012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12494 11:47:43.269847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12495 11:47:43.270109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12497 11:47:43.305191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12498 11:47:43.305451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12500 11:47:43.342080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12501 11:47:43.342346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12503 11:47:43.377096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12504 11:47:43.377357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12506 11:47:43.410173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12507 11:47:43.410424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12509 11:47:43.446376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12510 11:47:43.446672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12512 11:47:43.481170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12513 11:47:43.481430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12515 11:47:43.518286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12516 11:47:43.518546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12518 11:47:43.549108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12519 11:47:43.549196 + set +x
12520 11:47:43.549433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12522 11:47:43.556044 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12074003_1.6.2.3.5>
12523 11:47:43.556297 Received signal: <ENDRUN> 1_kselftest-arm64 12074003_1.6.2.3.5
12524 11:47:43.556373 Ending use of test pattern.
12525 11:47:43.556436 Ending test lava.1_kselftest-arm64 (12074003_1.6.2.3.5), duration 29.64
12527 11:47:43.559039 <LAVA_TEST_RUNNER EXIT>
12528 11:47:43.559291 ok: lava_test_shell seems to have completed
12529 11:47:43.560306 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12530 11:47:43.560453 end: 3.1 lava-test-shell (duration 00:00:30) [common]
12531 11:47:43.560539 end: 3 lava-test-retry (duration 00:00:30) [common]
12532 11:47:43.560627 start: 4 finalize (timeout 00:07:10) [common]
12533 11:47:43.560714 start: 4.1 power-off (timeout 00:00:30) [common]
12534 11:47:43.560871 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
12535 11:47:43.634987 >> Command sent successfully.
12536 11:47:43.637270 Returned 0 in 0 seconds
12537 11:47:43.737658 end: 4.1 power-off (duration 00:00:00) [common]
12539 11:47:43.737989 start: 4.2 read-feedback (timeout 00:07:10) [common]
12540 11:47:43.738253 Listened to connection for namespace 'common' for up to 1s
12541 11:47:44.738504 Finalising connection for namespace 'common'
12542 11:47:44.738685 Disconnecting from shell: Finalise
12543 11:47:44.738810 / #
12544 11:47:44.839419 end: 4.2 read-feedback (duration 00:00:01) [common]
12545 11:47:44.840177 end: 4 finalize (duration 00:00:01) [common]
12546 11:47:44.840885 Cleaning after the job
12547 11:47:44.841420 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/ramdisk
12548 11:47:44.850926 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/kernel
12549 11:47:44.879118 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/dtb
12550 11:47:44.879456 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/nfsrootfs
12551 11:47:44.954084 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074003/tftp-deploy-updl6c3y/modules
12552 11:47:44.959768 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074003
12553 11:47:45.528394 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074003
12554 11:47:45.528584 Job finished correctly