Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 38
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 11:44:03.186457 lava-dispatcher, installed at version: 2023.10
2 11:44:03.186660 start: 0 validate
3 11:44:03.186791 Start time: 2023-11-24 11:44:03.186782+00:00 (UTC)
4 11:44:03.186907 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:44:03.187036 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:44:03.458983 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:44:03.459238 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:44:20.474906 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:44:20.475669 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:44:20.747661 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:44:20.748363 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:44:21.011031 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:44:21.011217 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:44:25.016024 validate duration: 21.83
16 11:44:25.016281 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:44:25.016380 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:44:25.016471 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:44:25.016588 Not decompressing ramdisk as can be used compressed.
20 11:44:25.016672 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 11:44:25.016735 saving as /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/ramdisk/initrd.cpio.gz
22 11:44:25.016800 total size: 4665395 (4 MB)
23 11:44:25.017861 progress 0 % (0 MB)
24 11:44:25.019355 progress 5 % (0 MB)
25 11:44:25.020619 progress 10 % (0 MB)
26 11:44:25.021888 progress 15 % (0 MB)
27 11:44:25.023176 progress 20 % (0 MB)
28 11:44:25.024434 progress 25 % (1 MB)
29 11:44:25.025666 progress 30 % (1 MB)
30 11:44:25.026940 progress 35 % (1 MB)
31 11:44:25.028214 progress 40 % (1 MB)
32 11:44:25.029635 progress 45 % (2 MB)
33 11:44:25.030906 progress 50 % (2 MB)
34 11:44:25.032133 progress 55 % (2 MB)
35 11:44:25.033360 progress 60 % (2 MB)
36 11:44:25.034663 progress 65 % (2 MB)
37 11:44:25.035976 progress 70 % (3 MB)
38 11:44:25.037209 progress 75 % (3 MB)
39 11:44:25.038478 progress 80 % (3 MB)
40 11:44:25.039875 progress 85 % (3 MB)
41 11:44:25.041095 progress 90 % (4 MB)
42 11:44:25.042415 progress 95 % (4 MB)
43 11:44:25.043660 progress 100 % (4 MB)
44 11:44:25.043814 4 MB downloaded in 0.03 s (164.70 MB/s)
45 11:44:25.043964 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:44:25.044223 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:44:25.044323 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:44:25.044408 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:44:25.044545 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:44:25.044618 saving as /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/kernel/Image
52 11:44:25.044679 total size: 49107456 (46 MB)
53 11:44:25.044740 No compression specified
54 11:44:25.045823 progress 0 % (0 MB)
55 11:44:25.058579 progress 5 % (2 MB)
56 11:44:25.071553 progress 10 % (4 MB)
57 11:44:25.084452 progress 15 % (7 MB)
58 11:44:25.097339 progress 20 % (9 MB)
59 11:44:25.110039 progress 25 % (11 MB)
60 11:44:25.122794 progress 30 % (14 MB)
61 11:44:25.135590 progress 35 % (16 MB)
62 11:44:25.148627 progress 40 % (18 MB)
63 11:44:25.161590 progress 45 % (21 MB)
64 11:44:25.174470 progress 50 % (23 MB)
65 11:44:25.187309 progress 55 % (25 MB)
66 11:44:25.200174 progress 60 % (28 MB)
67 11:44:25.213059 progress 65 % (30 MB)
68 11:44:25.225820 progress 70 % (32 MB)
69 11:44:25.238509 progress 75 % (35 MB)
70 11:44:25.251480 progress 80 % (37 MB)
71 11:44:25.264229 progress 85 % (39 MB)
72 11:44:25.277323 progress 90 % (42 MB)
73 11:44:25.290506 progress 95 % (44 MB)
74 11:44:25.303143 progress 100 % (46 MB)
75 11:44:25.303387 46 MB downloaded in 0.26 s (181.03 MB/s)
76 11:44:25.303538 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:44:25.303774 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:44:25.303860 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:44:25.303947 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:44:25.304073 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:44:25.304143 saving as /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/dtb/mt8192-asurada-spherion-r0.dtb
83 11:44:25.304205 total size: 47278 (0 MB)
84 11:44:25.304266 No compression specified
85 11:44:25.305338 progress 69 % (0 MB)
86 11:44:25.305612 progress 100 % (0 MB)
87 11:44:25.305768 0 MB downloaded in 0.00 s (28.89 MB/s)
88 11:44:25.305889 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:44:25.306111 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:44:25.306199 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:44:25.306324 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:44:25.306439 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 11:44:25.306507 saving as /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/nfsrootfs/full.rootfs.tar
95 11:44:25.306571 total size: 200813988 (191 MB)
96 11:44:25.306633 Using unxz to decompress xz
97 11:44:25.310876 progress 0 % (0 MB)
98 11:44:25.861130 progress 5 % (9 MB)
99 11:44:26.410619 progress 10 % (19 MB)
100 11:44:27.019504 progress 15 % (28 MB)
101 11:44:27.408250 progress 20 % (38 MB)
102 11:44:27.753868 progress 25 % (47 MB)
103 11:44:28.392564 progress 30 % (57 MB)
104 11:44:28.976606 progress 35 % (67 MB)
105 11:44:29.595812 progress 40 % (76 MB)
106 11:44:30.186464 progress 45 % (86 MB)
107 11:44:30.795679 progress 50 % (95 MB)
108 11:44:31.453398 progress 55 % (105 MB)
109 11:44:32.152449 progress 60 % (114 MB)
110 11:44:32.295308 progress 65 % (124 MB)
111 11:44:32.463444 progress 70 % (134 MB)
112 11:44:32.583967 progress 75 % (143 MB)
113 11:44:32.676482 progress 80 % (153 MB)
114 11:44:32.751678 progress 85 % (162 MB)
115 11:44:32.858493 progress 90 % (172 MB)
116 11:44:33.166020 progress 95 % (181 MB)
117 11:44:33.783514 progress 100 % (191 MB)
118 11:44:33.788963 191 MB downloaded in 8.48 s (22.58 MB/s)
119 11:44:33.789319 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:44:33.789671 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:44:33.789763 start: 1.5 download-retry (timeout 00:09:51) [common]
123 11:44:33.789854 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 11:44:33.790003 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:44:33.790100 saving as /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/modules/modules.tar
126 11:44:33.790195 total size: 8624756 (8 MB)
127 11:44:33.790297 Using unxz to decompress xz
128 11:44:34.060296 progress 0 % (0 MB)
129 11:44:34.081714 progress 5 % (0 MB)
130 11:44:34.105752 progress 10 % (0 MB)
131 11:44:34.131513 progress 15 % (1 MB)
132 11:44:34.156262 progress 20 % (1 MB)
133 11:44:34.181370 progress 25 % (2 MB)
134 11:44:34.209210 progress 30 % (2 MB)
135 11:44:34.236403 progress 35 % (2 MB)
136 11:44:34.260692 progress 40 % (3 MB)
137 11:44:34.285778 progress 45 % (3 MB)
138 11:44:34.311935 progress 50 % (4 MB)
139 11:44:34.337189 progress 55 % (4 MB)
140 11:44:34.363009 progress 60 % (4 MB)
141 11:44:34.391637 progress 65 % (5 MB)
142 11:44:34.417422 progress 70 % (5 MB)
143 11:44:34.441844 progress 75 % (6 MB)
144 11:44:34.470014 progress 80 % (6 MB)
145 11:44:34.496845 progress 85 % (7 MB)
146 11:44:34.522666 progress 90 % (7 MB)
147 11:44:34.555204 progress 95 % (7 MB)
148 11:44:34.584238 progress 100 % (8 MB)
149 11:44:34.589322 8 MB downloaded in 0.80 s (10.29 MB/s)
150 11:44:34.589699 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:44:34.590104 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:44:34.590236 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 11:44:34.590385 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 11:44:38.273557 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12074008/extract-nfsrootfs-s4qkpdjn
156 11:44:38.273784 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:44:38.273887 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 11:44:38.274068 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o
159 11:44:38.274204 makedir: /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin
160 11:44:38.274355 makedir: /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/tests
161 11:44:38.274455 makedir: /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/results
162 11:44:38.274560 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-add-keys
163 11:44:38.274713 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-add-sources
164 11:44:38.274846 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-background-process-start
165 11:44:38.274975 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-background-process-stop
166 11:44:38.275102 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-common-functions
167 11:44:38.275229 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-echo-ipv4
168 11:44:38.275354 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-install-packages
169 11:44:38.275480 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-installed-packages
170 11:44:38.275605 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-os-build
171 11:44:38.275731 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-probe-channel
172 11:44:38.275857 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-probe-ip
173 11:44:38.275982 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-target-ip
174 11:44:38.276105 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-target-mac
175 11:44:38.276228 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-target-storage
176 11:44:38.276355 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-test-case
177 11:44:38.276483 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-test-event
178 11:44:38.276624 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-test-feedback
179 11:44:38.276752 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-test-raise
180 11:44:38.276891 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-test-reference
181 11:44:38.277021 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-test-runner
182 11:44:38.277146 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-test-set
183 11:44:38.277273 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-test-shell
184 11:44:38.277399 Updating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-add-keys (debian)
185 11:44:38.277578 Updating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-add-sources (debian)
186 11:44:38.277756 Updating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-install-packages (debian)
187 11:44:38.277930 Updating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-installed-packages (debian)
188 11:44:38.278086 Updating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/bin/lava-os-build (debian)
189 11:44:38.278225 Creating /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/environment
190 11:44:38.278466 LAVA metadata
191 11:44:38.278541 - LAVA_JOB_ID=12074008
192 11:44:38.278605 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:44:38.278721 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 11:44:38.278789 skipped lava-vland-overlay
195 11:44:38.278866 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:44:38.278947 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 11:44:38.279007 skipped lava-multinode-overlay
198 11:44:38.279078 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:44:38.279156 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 11:44:38.279232 Loading test definitions
201 11:44:38.279340 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 11:44:38.279429 Using /lava-12074008 at stage 0
203 11:44:38.279740 uuid=12074008_1.6.2.3.1 testdef=None
204 11:44:38.279829 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:44:38.279944 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 11:44:38.280422 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:44:38.280645 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 11:44:38.281308 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:44:38.281540 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 11:44:38.282155 runner path: /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/0/tests/0_timesync-off test_uuid 12074008_1.6.2.3.1
213 11:44:38.282338 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:44:38.282561 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 11:44:38.282635 Using /lava-12074008 at stage 0
217 11:44:38.282766 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:44:38.282846 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/0/tests/1_kselftest-dt'
219 11:44:55.407248 Running '/usr/bin/git checkout kernelci.org
220 11:44:55.559353 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 11:44:55.560101 uuid=12074008_1.6.2.3.5 testdef=None
222 11:44:55.560262 end: 1.6.2.3.5 git-repo-action (duration 00:00:17) [common]
224 11:44:55.560522 start: 1.6.2.3.6 test-overlay (timeout 00:09:29) [common]
225 11:44:55.561298 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:44:55.561539 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:29) [common]
228 11:44:55.562552 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:44:55.562791 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:29) [common]
231 11:44:55.563793 runner path: /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/0/tests/1_kselftest-dt test_uuid 12074008_1.6.2.3.5
232 11:44:55.563890 BOARD='mt8192-asurada-spherion-r0'
233 11:44:55.563956 BRANCH='cip-gitlab'
234 11:44:55.564019 SKIPFILE='/dev/null'
235 11:44:55.564080 SKIP_INSTALL='True'
236 11:44:55.564138 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:44:55.564232 TST_CASENAME=''
238 11:44:55.564293 TST_CMDFILES='dt'
239 11:44:55.564441 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:44:55.564650 Creating lava-test-runner.conf files
242 11:44:55.564717 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12074008/lava-overlay-gk7n9q0o/lava-12074008/0 for stage 0
243 11:44:55.564813 - 0_timesync-off
244 11:44:55.564885 - 1_kselftest-dt
245 11:44:55.565004 end: 1.6.2.3 test-definition (duration 00:00:17) [common]
246 11:44:55.565096 start: 1.6.2.4 compress-overlay (timeout 00:09:29) [common]
247 11:45:03.176819 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:45:03.177030 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:22) [common]
249 11:45:03.177124 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:45:03.177227 end: 1.6.2 lava-overlay (duration 00:00:25) [common]
251 11:45:03.177323 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:22) [common]
252 11:45:03.305621 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:45:03.306086 start: 1.6.4 extract-modules (timeout 00:09:22) [common]
254 11:45:03.306245 extracting modules file /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074008/extract-nfsrootfs-s4qkpdjn
255 11:45:03.615505 extracting modules file /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12074008/extract-overlay-ramdisk-c15m01ya/ramdisk
256 11:45:03.870557 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 11:45:03.870746 start: 1.6.5 apply-overlay-tftp (timeout 00:09:21) [common]
258 11:45:03.870846 [common] Applying overlay to NFS
259 11:45:03.870927 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12074008/compress-overlay-u5n6fpys/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12074008/extract-nfsrootfs-s4qkpdjn
260 11:45:04.976283 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:45:04.976459 start: 1.6.6 configure-preseed-file (timeout 00:09:20) [common]
262 11:45:04.976564 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:45:04.976658 start: 1.6.7 compress-ramdisk (timeout 00:09:20) [common]
264 11:45:04.976745 Building ramdisk /var/lib/lava/dispatcher/tmp/12074008/extract-overlay-ramdisk-c15m01ya/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12074008/extract-overlay-ramdisk-c15m01ya/ramdisk
265 11:45:05.285233 >> 119398 blocks
266 11:45:07.328858 rename /var/lib/lava/dispatcher/tmp/12074008/extract-overlay-ramdisk-c15m01ya/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/ramdisk/ramdisk.cpio.gz
267 11:45:07.329312 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:45:07.329443 start: 1.6.8 prepare-kernel (timeout 00:09:18) [common]
269 11:45:07.329548 start: 1.6.8.1 prepare-fit (timeout 00:09:18) [common]
270 11:45:07.329659 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/kernel/Image'
271 11:45:20.064244 Returned 0 in 12 seconds
272 11:45:20.165183 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/kernel/image.itb
273 11:45:20.542023 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:45:20.542443 output: Created: Fri Nov 24 11:45:20 2023
275 11:45:20.542522 output: Image 0 (kernel-1)
276 11:45:20.542592 output: Description:
277 11:45:20.542656 output: Created: Fri Nov 24 11:45:20 2023
278 11:45:20.542721 output: Type: Kernel Image
279 11:45:20.542780 output: Compression: lzma compressed
280 11:45:20.542842 output: Data Size: 11048246 Bytes = 10789.30 KiB = 10.54 MiB
281 11:45:20.542901 output: Architecture: AArch64
282 11:45:20.542960 output: OS: Linux
283 11:45:20.543020 output: Load Address: 0x00000000
284 11:45:20.543076 output: Entry Point: 0x00000000
285 11:45:20.543134 output: Hash algo: crc32
286 11:45:20.543193 output: Hash value: 43cfb6ad
287 11:45:20.543250 output: Image 1 (fdt-1)
288 11:45:20.543305 output: Description: mt8192-asurada-spherion-r0
289 11:45:20.543359 output: Created: Fri Nov 24 11:45:20 2023
290 11:45:20.543413 output: Type: Flat Device Tree
291 11:45:20.543466 output: Compression: uncompressed
292 11:45:20.543519 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:45:20.543572 output: Architecture: AArch64
294 11:45:20.543625 output: Hash algo: crc32
295 11:45:20.543678 output: Hash value: cc4352de
296 11:45:20.543730 output: Image 2 (ramdisk-1)
297 11:45:20.543782 output: Description: unavailable
298 11:45:20.543835 output: Created: Fri Nov 24 11:45:20 2023
299 11:45:20.543888 output: Type: RAMDisk Image
300 11:45:20.543940 output: Compression: Unknown Compression
301 11:45:20.543992 output: Data Size: 17791746 Bytes = 17374.75 KiB = 16.97 MiB
302 11:45:20.544045 output: Architecture: AArch64
303 11:45:20.544098 output: OS: Linux
304 11:45:20.544151 output: Load Address: unavailable
305 11:45:20.544204 output: Entry Point: unavailable
306 11:45:20.544257 output: Hash algo: crc32
307 11:45:20.544310 output: Hash value: 52c26b08
308 11:45:20.544363 output: Default Configuration: 'conf-1'
309 11:45:20.544416 output: Configuration 0 (conf-1)
310 11:45:20.544469 output: Description: mt8192-asurada-spherion-r0
311 11:45:20.544521 output: Kernel: kernel-1
312 11:45:20.544574 output: Init Ramdisk: ramdisk-1
313 11:45:20.544626 output: FDT: fdt-1
314 11:45:20.544679 output: Loadables: kernel-1
315 11:45:20.544732 output:
316 11:45:20.544936 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 11:45:20.545036 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 11:45:20.545137 end: 1.6 prepare-tftp-overlay (duration 00:00:46) [common]
319 11:45:20.545229 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:04) [common]
320 11:45:20.545312 No LXC device requested
321 11:45:20.545391 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:45:20.545474 start: 1.8 deploy-device-env (timeout 00:09:04) [common]
323 11:45:20.545553 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:45:20.545624 Checking files for TFTP limit of 4294967296 bytes.
325 11:45:20.546134 end: 1 tftp-deploy (duration 00:00:56) [common]
326 11:45:20.546238 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:45:20.546377 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:45:20.546508 substitutions:
329 11:45:20.546578 - {DTB}: 12074008/tftp-deploy-ndrpbirt/dtb/mt8192-asurada-spherion-r0.dtb
330 11:45:20.546644 - {INITRD}: 12074008/tftp-deploy-ndrpbirt/ramdisk/ramdisk.cpio.gz
331 11:45:20.546703 - {KERNEL}: 12074008/tftp-deploy-ndrpbirt/kernel/Image
332 11:45:20.546761 - {LAVA_MAC}: None
333 11:45:20.546818 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12074008/extract-nfsrootfs-s4qkpdjn
334 11:45:20.546875 - {NFS_SERVER_IP}: 192.168.201.1
335 11:45:20.546934 - {PRESEED_CONFIG}: None
336 11:45:20.546989 - {PRESEED_LOCAL}: None
337 11:45:20.547044 - {RAMDISK}: 12074008/tftp-deploy-ndrpbirt/ramdisk/ramdisk.cpio.gz
338 11:45:20.547099 - {ROOT_PART}: None
339 11:45:20.547154 - {ROOT}: None
340 11:45:20.547209 - {SERVER_IP}: 192.168.201.1
341 11:45:20.547263 - {TEE}: None
342 11:45:20.547317 Parsed boot commands:
343 11:45:20.547369 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:45:20.547556 Parsed boot commands: tftpboot 192.168.201.1 12074008/tftp-deploy-ndrpbirt/kernel/image.itb 12074008/tftp-deploy-ndrpbirt/kernel/cmdline
345 11:45:20.547646 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:45:20.547731 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:45:20.547821 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:45:20.547906 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:45:20.547980 Not connected, no need to disconnect.
350 11:45:20.548054 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:45:20.548134 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:45:20.548201 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 11:45:20.552321 Setting prompt string to ['lava-test: # ']
354 11:45:20.552717 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:45:20.552829 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:45:20.552931 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:45:20.553024 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:45:20.553252 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 11:45:25.690314 >> Command sent successfully.
360 11:45:25.692668 Returned 0 in 5 seconds
361 11:45:25.793146 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:45:25.793786 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:45:25.794007 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:45:25.794189 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:45:25.794349 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:45:25.794497 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:45:25.795045 [Enter `^Ec?' for help]
369 11:45:25.966728
370 11:45:25.967282
371 11:45:25.967632 F0: 102B 0000
372 11:45:25.968230
373 11:45:25.969395 F3: 1001 0000 [0200]
374 11:45:25.969817
375 11:45:25.970151 F3: 1001 0000
376 11:45:25.970518
377 11:45:25.970825 F7: 102D 0000
378 11:45:25.971122
379 11:45:25.972723 F1: 0000 0000
380 11:45:25.973148
381 11:45:25.973485 V0: 0000 0000 [0001]
382 11:45:25.973813
383 11:45:25.976348 00: 0007 8000
384 11:45:25.976792
385 11:45:25.977128 01: 0000 0000
386 11:45:25.977449
387 11:45:25.979929 BP: 0C00 0209 [0000]
388 11:45:25.980351
389 11:45:25.980684 G0: 1182 0000
390 11:45:25.980993
391 11:45:25.983180 EC: 0000 0021 [4000]
392 11:45:25.983707
393 11:45:25.984059 S7: 0000 0000 [0000]
394 11:45:25.984418
395 11:45:25.987313 CC: 0000 0000 [0001]
396 11:45:25.987771
397 11:45:25.988105 T0: 0000 0040 [010F]
398 11:45:25.988421
399 11:45:25.988717 Jump to BL
400 11:45:25.989009
401 11:45:26.013352
402 11:45:26.013792
403 11:45:26.014156
404 11:45:26.020523 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:45:26.023968 ARM64: Exception handlers installed.
406 11:45:26.028206 ARM64: Testing exception
407 11:45:26.030721 ARM64: Done test exception
408 11:45:26.037865 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:45:26.047371 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:45:26.054895 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:45:26.064872 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:45:26.071456 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:45:26.081428 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:45:26.091844 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:45:26.098564 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:45:26.116525 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:45:26.119711 WDT: Last reset was cold boot
418 11:45:26.122417 SPI1(PAD0) initialized at 2873684 Hz
419 11:45:26.126364 SPI5(PAD0) initialized at 992727 Hz
420 11:45:26.129141 VBOOT: Loading verstage.
421 11:45:26.136172 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:45:26.139553 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:45:26.142545 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:45:26.145784 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:45:26.153775 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:45:26.160118 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:45:26.171159 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 11:45:26.171802
429 11:45:26.172310
430 11:45:26.181344 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:45:26.184829 ARM64: Exception handlers installed.
432 11:45:26.187843 ARM64: Testing exception
433 11:45:26.188284 ARM64: Done test exception
434 11:45:26.194420 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:45:26.198594 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:45:26.212476 Probing TPM: . done!
437 11:45:26.212906 TPM ready after 0 ms
438 11:45:26.219506 Connected to device vid:did:rid of 1ae0:0028:00
439 11:45:26.226220 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 11:45:26.284007 Initialized TPM device CR50 revision 0
441 11:45:26.295373 tlcl_send_startup: Startup return code is 0
442 11:45:26.295852 TPM: setup succeeded
443 11:45:26.306974 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:45:26.315606 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:45:26.328583 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:45:26.336250 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:45:26.339467 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:45:26.347344 in-header: 03 07 00 00 08 00 00 00
449 11:45:26.350785 in-data: aa e4 47 04 13 02 00 00
450 11:45:26.354723 Chrome EC: UHEPI supported
451 11:45:26.361571 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:45:26.365647 in-header: 03 95 00 00 08 00 00 00
453 11:45:26.369495 in-data: 18 20 20 08 00 00 00 00
454 11:45:26.370120 Phase 1
455 11:45:26.373047 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:45:26.380250 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:45:26.383767 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:45:26.387238 Recovery requested (1009000e)
459 11:45:26.396247 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:45:26.401867 tlcl_extend: response is 0
461 11:45:26.411035 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:45:26.416874 tlcl_extend: response is 0
463 11:45:26.423517 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:45:26.443325 read SPI 0x210d4 0x2173b: 15139 us, 9050 KB/s, 72.400 Mbps
465 11:45:26.450203 BS: bootblock times (exec / console): total (unknown) / 149 ms
466 11:45:26.450685
467 11:45:26.451025
468 11:45:26.459940 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:45:26.463550 ARM64: Exception handlers installed.
470 11:45:26.466970 ARM64: Testing exception
471 11:45:26.467521 ARM64: Done test exception
472 11:45:26.488900 pmic_efuse_setting: Set efuses in 11 msecs
473 11:45:26.492178 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:45:26.498733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:45:26.502294 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:45:26.509232 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:45:26.512838 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:45:26.516278 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:45:26.523446 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:45:26.527430 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:45:26.530747 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:45:26.538377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:45:26.542152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:45:26.545856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:45:26.549356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:45:26.553190 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:45:26.560868 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:45:26.567703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:45:26.571506 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:45:26.578935 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:45:26.582162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:45:26.591530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:45:26.597312 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:45:26.600658 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:45:26.607852 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:45:26.611660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:45:26.618674 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:45:26.622353 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:45:26.629582 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:45:26.633114 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:45:26.636504 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:45:26.643839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:45:26.647459 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:45:26.650811 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:45:26.658108 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:45:26.661554 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:45:26.669060 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:45:26.672855 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:45:26.676629 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:45:26.683801 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:45:26.687501 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:45:26.691122 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:45:26.698542 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:45:26.702021 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:45:26.705745 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:45:26.709376 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:45:26.713196 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:45:26.720390 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:45:26.724140 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:45:26.727825 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:45:26.731540 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:45:26.734686 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:45:26.738862 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:45:26.742549 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:45:26.753793 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:45:26.760839 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:45:26.764352 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:45:26.771558 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:45:26.782689 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:45:26.786093 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:45:26.789782 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:45:26.793322 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:45:26.802158 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x2
534 11:45:26.805549 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:45:26.814193 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 11:45:26.817498 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:45:26.826134 [RTC]rtc_get_frequency_meter,154: input=15, output=852
538 11:45:26.836060 [RTC]rtc_get_frequency_meter,154: input=7, output=724
539 11:45:26.845521 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 11:45:26.855015 [RTC]rtc_get_frequency_meter,154: input=13, output=820
541 11:45:26.864045 [RTC]rtc_get_frequency_meter,154: input=12, output=804
542 11:45:26.873641 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 11:45:26.884440 [RTC]rtc_get_frequency_meter,154: input=12, output=804
544 11:45:26.887851 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 11:45:26.891822 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 11:45:26.895200 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:45:26.903170 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:45:26.906732 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:45:26.910480 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:45:26.910889 ADC[4]: Raw value=904064 ID=7
551 11:45:26.913809 ADC[3]: Raw value=213546 ID=1
552 11:45:26.917532 RAM Code: 0x71
553 11:45:26.921025 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:45:26.925204 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:45:26.935811 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:45:26.939036 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:45:26.942750 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:45:26.947659 in-header: 03 07 00 00 08 00 00 00
559 11:45:26.951106 in-data: aa e4 47 04 13 02 00 00
560 11:45:26.954305 Chrome EC: UHEPI supported
561 11:45:26.962165 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:45:26.965098 in-header: 03 95 00 00 08 00 00 00
563 11:45:26.965494 in-data: 18 20 20 08 00 00 00 00
564 11:45:26.968791 MRC: failed to locate region type 0.
565 11:45:26.976339 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:45:26.980356 DRAM-K: Running full calibration
567 11:45:26.987479 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:45:26.988004 header.status = 0x0
569 11:45:26.990875 header.version = 0x6 (expected: 0x6)
570 11:45:26.994830 header.size = 0xd00 (expected: 0xd00)
571 11:45:26.995288 header.flags = 0x0
572 11:45:27.001823 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:45:27.019609 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 11:45:27.027346 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:45:27.030790 dram_init: ddr_geometry: 2
576 11:45:27.031197 [EMI] MDL number = 2
577 11:45:27.034940 [EMI] Get MDL freq = 0
578 11:45:27.035521 dram_init: ddr_type: 0
579 11:45:27.038400 is_discrete_lpddr4: 1
580 11:45:27.041612 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:45:27.042236
582 11:45:27.042717
583 11:45:27.046193 [Bian_co] ETT version 0.0.0.1
584 11:45:27.049261 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:45:27.049892
586 11:45:27.052872 dramc_set_vcore_voltage set vcore to 650000
587 11:45:27.056237 Read voltage for 800, 4
588 11:45:27.056730 Vio18 = 0
589 11:45:27.057133 Vcore = 650000
590 11:45:27.057568 Vdram = 0
591 11:45:27.060532 Vddq = 0
592 11:45:27.061156 Vmddr = 0
593 11:45:27.063942 dram_init: config_dvfs: 1
594 11:45:27.067241 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:45:27.073198 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:45:27.077272 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 11:45:27.080388 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 11:45:27.083735 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 11:45:27.087332 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 11:45:27.091206 MEM_TYPE=3, freq_sel=18
601 11:45:27.094694 sv_algorithm_assistance_LP4_1600
602 11:45:27.098617 ============ PULL DRAM RESETB DOWN ============
603 11:45:27.102230 ========== PULL DRAM RESETB DOWN end =========
604 11:45:27.105746 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:45:27.108623 ===================================
606 11:45:27.111880 LPDDR4 DRAM CONFIGURATION
607 11:45:27.115790 ===================================
608 11:45:27.116206 EX_ROW_EN[0] = 0x0
609 11:45:27.119113 EX_ROW_EN[1] = 0x0
610 11:45:27.122028 LP4Y_EN = 0x0
611 11:45:27.122617 WORK_FSP = 0x0
612 11:45:27.125347 WL = 0x2
613 11:45:27.125838 RL = 0x2
614 11:45:27.128608 BL = 0x2
615 11:45:27.129222 RPST = 0x0
616 11:45:27.132116 RD_PRE = 0x0
617 11:45:27.132572 WR_PRE = 0x1
618 11:45:27.135451 WR_PST = 0x0
619 11:45:27.135868 DBI_WR = 0x0
620 11:45:27.138953 DBI_RD = 0x0
621 11:45:27.139371 OTF = 0x1
622 11:45:27.141941 ===================================
623 11:45:27.145020 ===================================
624 11:45:27.148371 ANA top config
625 11:45:27.151479 ===================================
626 11:45:27.151559 DLL_ASYNC_EN = 0
627 11:45:27.154774 ALL_SLAVE_EN = 1
628 11:45:27.158432 NEW_RANK_MODE = 1
629 11:45:27.161535 DLL_IDLE_MODE = 1
630 11:45:27.164531 LP45_APHY_COMB_EN = 1
631 11:45:27.164612 TX_ODT_DIS = 1
632 11:45:27.167882 NEW_8X_MODE = 1
633 11:45:27.171259 ===================================
634 11:45:27.174617 ===================================
635 11:45:27.178206 data_rate = 1600
636 11:45:27.181023 CKR = 1
637 11:45:27.184708 DQ_P2S_RATIO = 8
638 11:45:27.188063 ===================================
639 11:45:27.188136 CA_P2S_RATIO = 8
640 11:45:27.191928 DQ_CA_OPEN = 0
641 11:45:27.195453 DQ_SEMI_OPEN = 0
642 11:45:27.198907 CA_SEMI_OPEN = 0
643 11:45:27.202286 CA_FULL_RATE = 0
644 11:45:27.202371 DQ_CKDIV4_EN = 1
645 11:45:27.205378 CA_CKDIV4_EN = 1
646 11:45:27.208823 CA_PREDIV_EN = 0
647 11:45:27.212331 PH8_DLY = 0
648 11:45:27.215777 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:45:27.215850 DQ_AAMCK_DIV = 4
650 11:45:27.218663 CA_AAMCK_DIV = 4
651 11:45:27.221905 CA_ADMCK_DIV = 4
652 11:45:27.225677 DQ_TRACK_CA_EN = 0
653 11:45:27.228861 CA_PICK = 800
654 11:45:27.232134 CA_MCKIO = 800
655 11:45:27.235619 MCKIO_SEMI = 0
656 11:45:27.235692 PLL_FREQ = 3068
657 11:45:27.239306 DQ_UI_PI_RATIO = 32
658 11:45:27.243473 CA_UI_PI_RATIO = 0
659 11:45:27.247071 ===================================
660 11:45:27.250791 ===================================
661 11:45:27.250869 memory_type:LPDDR4
662 11:45:27.254581 GP_NUM : 10
663 11:45:27.254661 SRAM_EN : 1
664 11:45:27.258595 MD32_EN : 0
665 11:45:27.261892 ===================================
666 11:45:27.261968 [ANA_INIT] >>>>>>>>>>>>>>
667 11:45:27.266113 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:45:27.269627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:45:27.273079 ===================================
670 11:45:27.276074 data_rate = 1600,PCW = 0X7600
671 11:45:27.279586 ===================================
672 11:45:27.282932 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:45:27.289512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:45:27.292610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:45:27.299382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:45:27.302883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:45:27.305969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:45:27.306077 [ANA_INIT] flow start
679 11:45:27.309454 [ANA_INIT] PLL >>>>>>>>
680 11:45:27.312904 [ANA_INIT] PLL <<<<<<<<
681 11:45:27.313005 [ANA_INIT] MIDPI >>>>>>>>
682 11:45:27.315451 [ANA_INIT] MIDPI <<<<<<<<
683 11:45:27.319019 [ANA_INIT] DLL >>>>>>>>
684 11:45:27.319092 [ANA_INIT] flow end
685 11:45:27.325975 ============ LP4 DIFF to SE enter ============
686 11:45:27.329013 ============ LP4 DIFF to SE exit ============
687 11:45:27.332188 [ANA_INIT] <<<<<<<<<<<<<
688 11:45:27.335512 [Flow] Enable top DCM control >>>>>
689 11:45:27.338896 [Flow] Enable top DCM control <<<<<
690 11:45:27.338993 Enable DLL master slave shuffle
691 11:45:27.345206 ==============================================================
692 11:45:27.349091 Gating Mode config
693 11:45:27.352182 ==============================================================
694 11:45:27.355194 Config description:
695 11:45:27.365195 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:45:27.372171 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:45:27.375400 SELPH_MODE 0: By rank 1: By Phase
698 11:45:27.381901 ==============================================================
699 11:45:27.385353 GAT_TRACK_EN = 1
700 11:45:27.388956 RX_GATING_MODE = 2
701 11:45:27.391808 RX_GATING_TRACK_MODE = 2
702 11:45:27.395657 SELPH_MODE = 1
703 11:45:27.395728 PICG_EARLY_EN = 1
704 11:45:27.398696 VALID_LAT_VALUE = 1
705 11:45:27.405491 ==============================================================
706 11:45:27.408315 Enter into Gating configuration >>>>
707 11:45:27.412039 Exit from Gating configuration <<<<
708 11:45:27.415218 Enter into DVFS_PRE_config >>>>>
709 11:45:27.424923 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:45:27.428462 Exit from DVFS_PRE_config <<<<<
711 11:45:27.431873 Enter into PICG configuration >>>>
712 11:45:27.434790 Exit from PICG configuration <<<<
713 11:45:27.438119 [RX_INPUT] configuration >>>>>
714 11:45:27.441631 [RX_INPUT] configuration <<<<<
715 11:45:27.445075 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:45:27.451333 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:45:27.458208 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:45:27.464824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:45:27.471277 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:45:27.477976 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:45:27.481377 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:45:27.484733 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:45:27.488389 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:45:27.491213 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:45:27.498283 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:45:27.501030 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:45:27.504479 ===================================
728 11:45:27.508558 LPDDR4 DRAM CONFIGURATION
729 11:45:27.511569 ===================================
730 11:45:27.511651 EX_ROW_EN[0] = 0x0
731 11:45:27.514832 EX_ROW_EN[1] = 0x0
732 11:45:27.514914 LP4Y_EN = 0x0
733 11:45:27.517861 WORK_FSP = 0x0
734 11:45:27.517934 WL = 0x2
735 11:45:27.521315 RL = 0x2
736 11:45:27.521420 BL = 0x2
737 11:45:27.524575 RPST = 0x0
738 11:45:27.528225 RD_PRE = 0x0
739 11:45:27.528332 WR_PRE = 0x1
740 11:45:27.531389 WR_PST = 0x0
741 11:45:27.531490 DBI_WR = 0x0
742 11:45:27.534832 DBI_RD = 0x0
743 11:45:27.534920 OTF = 0x1
744 11:45:27.537790 ===================================
745 11:45:27.541001 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:45:27.544728 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:45:27.551321 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:45:27.554542 ===================================
749 11:45:27.557579 LPDDR4 DRAM CONFIGURATION
750 11:45:27.561647 ===================================
751 11:45:27.561737 EX_ROW_EN[0] = 0x10
752 11:45:27.564446 EX_ROW_EN[1] = 0x0
753 11:45:27.564519 LP4Y_EN = 0x0
754 11:45:27.567874 WORK_FSP = 0x0
755 11:45:27.567945 WL = 0x2
756 11:45:27.571138 RL = 0x2
757 11:45:27.571208 BL = 0x2
758 11:45:27.574438 RPST = 0x0
759 11:45:27.574534 RD_PRE = 0x0
760 11:45:27.578111 WR_PRE = 0x1
761 11:45:27.578208 WR_PST = 0x0
762 11:45:27.581391 DBI_WR = 0x0
763 11:45:27.581463 DBI_RD = 0x0
764 11:45:27.584546 OTF = 0x1
765 11:45:27.587905 ===================================
766 11:45:27.594586 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:45:27.597641 nWR fixed to 40
768 11:45:27.601472 [ModeRegInit_LP4] CH0 RK0
769 11:45:27.601547 [ModeRegInit_LP4] CH0 RK1
770 11:45:27.604651 [ModeRegInit_LP4] CH1 RK0
771 11:45:27.608187 [ModeRegInit_LP4] CH1 RK1
772 11:45:27.608290 match AC timing 13
773 11:45:27.614493 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:45:27.617646 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:45:27.621024 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:45:27.627914 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:45:27.631233 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:45:27.631335 [EMI DOE] emi_dcm 0
779 11:45:27.637405 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:45:27.637477 ==
781 11:45:27.640903 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:45:27.644184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:45:27.644255 ==
784 11:45:27.651127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:45:27.657594 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:45:27.665012 [CA 0] Center 37 (7~68) winsize 62
787 11:45:27.668711 [CA 1] Center 37 (6~68) winsize 63
788 11:45:27.672006 [CA 2] Center 34 (4~65) winsize 62
789 11:45:27.675424 [CA 3] Center 34 (4~65) winsize 62
790 11:45:27.678337 [CA 4] Center 33 (3~64) winsize 62
791 11:45:27.681964 [CA 5] Center 33 (3~64) winsize 62
792 11:45:27.682038
793 11:45:27.685058 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:45:27.685131
795 11:45:27.688588 [CATrainingPosCal] consider 1 rank data
796 11:45:27.691445 u2DelayCellTimex100 = 270/100 ps
797 11:45:27.694818 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 11:45:27.701653 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 11:45:27.705374 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 11:45:27.708408 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 11:45:27.711692 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 11:45:27.715299 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:45:27.715373
804 11:45:27.718497 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:45:27.718586
806 11:45:27.721923 [CBTSetCACLKResult] CA Dly = 33
807 11:45:27.722021 CS Dly: 5 (0~36)
808 11:45:27.724765 ==
809 11:45:27.728104 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:45:27.731679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:45:27.731757 ==
812 11:45:27.734736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:45:27.741433 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:45:27.751280 [CA 0] Center 38 (7~69) winsize 63
815 11:45:27.754579 [CA 1] Center 37 (7~68) winsize 62
816 11:45:27.758101 [CA 2] Center 35 (4~66) winsize 63
817 11:45:27.761280 [CA 3] Center 34 (4~65) winsize 62
818 11:45:27.764849 [CA 4] Center 34 (3~65) winsize 63
819 11:45:27.768207 [CA 5] Center 33 (3~64) winsize 62
820 11:45:27.768293
821 11:45:27.771280 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 11:45:27.771352
823 11:45:27.774604 [CATrainingPosCal] consider 2 rank data
824 11:45:27.777965 u2DelayCellTimex100 = 270/100 ps
825 11:45:27.781457 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 11:45:27.787867 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 11:45:27.791419 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 11:45:27.794589 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 11:45:27.798114 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 11:45:27.801555 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:45:27.801653
832 11:45:27.804584 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:45:27.804680
834 11:45:27.807818 [CBTSetCACLKResult] CA Dly = 33
835 11:45:27.807934 CS Dly: 6 (0~38)
836 11:45:27.811204
837 11:45:27.814595 ----->DramcWriteLeveling(PI) begin...
838 11:45:27.814671 ==
839 11:45:27.818548 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:45:27.822430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:45:27.822517 ==
842 11:45:27.825632 Write leveling (Byte 0): 32 => 32
843 11:45:27.825704 Write leveling (Byte 1): 27 => 27
844 11:45:27.829691 DramcWriteLeveling(PI) end<-----
845 11:45:27.829790
846 11:45:27.829878 ==
847 11:45:27.833261 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:45:27.836711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:45:27.836816 ==
850 11:45:27.840078 [Gating] SW mode calibration
851 11:45:27.847245 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:45:27.853762 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:45:27.857236 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:45:27.860748 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 11:45:27.867008 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 11:45:27.870812 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:45:27.874324 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:45:27.880503 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:45:27.884281 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:45:27.887170 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:45:27.894031 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:45:27.897459 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:45:27.900245 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:45:27.906929 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:45:27.910415 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:45:27.913879 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:45:27.920288 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:45:27.923722 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:45:27.927106 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:45:27.933720 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
871 11:45:27.936953 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 11:45:27.940566 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:45:27.943471 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:45:27.950176 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:45:27.953612 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:45:27.956603 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:45:27.963417 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:45:27.967012 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:45:27.970175 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
880 11:45:27.976451 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
881 11:45:27.980024 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:45:27.983234 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:45:27.990448 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:45:27.993134 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:45:27.996588 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:45:28.003997 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
887 11:45:28.006903 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
888 11:45:28.010183 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
889 11:45:28.017237 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:45:28.020283 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:45:28.023182 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:45:28.029896 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:45:28.033844 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:45:28.036340 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
895 11:45:28.043149 0 11 8 | B1->B0 | 2a2a 4242 | 0 0 | (0 0) (0 0)
896 11:45:28.046296 0 11 12 | B1->B0 | 3d3c 4646 | 1 0 | (0 0) (0 0)
897 11:45:28.049699 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:45:28.056191 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:45:28.059674 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:45:28.063271 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:45:28.069389 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:45:28.072957 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 11:45:28.076029 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 11:45:28.082874 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:45:28.086292 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:45:28.089662 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:45:28.096600 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:45:28.099417 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:45:28.102749 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:45:28.109135 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:45:28.112626 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:45:28.115786 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:45:28.122719 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:45:28.125981 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:45:28.129235 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:45:28.132889 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:45:28.139011 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:45:28.142819 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 11:45:28.145621 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 11:45:28.149138 Total UI for P1: 0, mck2ui 16
921 11:45:28.152486 best dqsien dly found for B0: ( 0, 14, 4)
922 11:45:28.158996 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 11:45:28.162391 Total UI for P1: 0, mck2ui 16
924 11:45:28.165827 best dqsien dly found for B1: ( 0, 14, 8)
925 11:45:28.169245 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 11:45:28.172829 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 11:45:28.172910
928 11:45:28.176119 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 11:45:28.179021 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 11:45:28.182751 [Gating] SW calibration Done
931 11:45:28.182833 ==
932 11:45:28.185413 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:45:28.189042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:45:28.189127 ==
935 11:45:28.193373 RX Vref Scan: 0
936 11:45:28.193482
937 11:45:28.193615 RX Vref 0 -> 0, step: 1
938 11:45:28.193682
939 11:45:28.196200 RX Delay -130 -> 252, step: 16
940 11:45:28.199763 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 11:45:28.202743 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 11:45:28.209753 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
943 11:45:28.213001 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
944 11:45:28.216304 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 11:45:28.219824 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 11:45:28.222638 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 11:45:28.229319 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 11:45:28.232560 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 11:45:28.235967 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
950 11:45:28.239464 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 11:45:28.246228 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 11:45:28.249075 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 11:45:28.252507 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 11:45:28.256072 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 11:45:28.259490 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 11:45:28.263005 ==
957 11:45:28.263104 Dram Type= 6, Freq= 0, CH_0, rank 0
958 11:45:28.269528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 11:45:28.269603 ==
960 11:45:28.269667 DQS Delay:
961 11:45:28.272275 DQS0 = 0, DQS1 = 0
962 11:45:28.272345 DQM Delay:
963 11:45:28.275751 DQM0 = 91, DQM1 = 76
964 11:45:28.275826 DQ Delay:
965 11:45:28.279471 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
966 11:45:28.282233 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
967 11:45:28.285776 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
968 11:45:28.289334 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 11:45:28.289417
970 11:45:28.289483
971 11:45:28.289543 ==
972 11:45:28.292681 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:45:28.295930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:45:28.296008 ==
975 11:45:28.296071
976 11:45:28.296128
977 11:45:28.299199 TX Vref Scan disable
978 11:45:28.302772 == TX Byte 0 ==
979 11:45:28.306159 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 11:45:28.309265 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 11:45:28.312301 == TX Byte 1 ==
982 11:45:28.316153 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
983 11:45:28.319339 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
984 11:45:28.319414 ==
985 11:45:28.322646 Dram Type= 6, Freq= 0, CH_0, rank 0
986 11:45:28.326153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 11:45:28.328964 ==
988 11:45:28.340590 TX Vref=22, minBit 9, minWin=26, winSum=441
989 11:45:28.344089 TX Vref=24, minBit 2, minWin=27, winSum=443
990 11:45:28.347574 TX Vref=26, minBit 1, minWin=27, winSum=447
991 11:45:28.350458 TX Vref=28, minBit 4, minWin=27, winSum=448
992 11:45:28.353956 TX Vref=30, minBit 8, minWin=27, winSum=449
993 11:45:28.360890 TX Vref=32, minBit 1, minWin=27, winSum=447
994 11:45:28.364451 [TxChooseVref] Worse bit 8, Min win 27, Win sum 449, Final Vref 30
995 11:45:28.364534
996 11:45:28.367510 Final TX Range 1 Vref 30
997 11:45:28.367593
998 11:45:28.367658 ==
999 11:45:28.370970 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 11:45:28.373920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 11:45:28.374002 ==
1002 11:45:28.377376
1003 11:45:28.377457
1004 11:45:28.377523 TX Vref Scan disable
1005 11:45:28.380860 == TX Byte 0 ==
1006 11:45:28.384276 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 11:45:28.390896 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 11:45:28.390982 == TX Byte 1 ==
1009 11:45:28.393883 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1010 11:45:28.400423 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1011 11:45:28.400509
1012 11:45:28.400596 [DATLAT]
1013 11:45:28.400679 Freq=800, CH0 RK0
1014 11:45:28.400761
1015 11:45:28.403907 DATLAT Default: 0xa
1016 11:45:28.404022 0, 0xFFFF, sum = 0
1017 11:45:28.407159 1, 0xFFFF, sum = 0
1018 11:45:28.410563 2, 0xFFFF, sum = 0
1019 11:45:28.410653 3, 0xFFFF, sum = 0
1020 11:45:28.413503 4, 0xFFFF, sum = 0
1021 11:45:28.413590 5, 0xFFFF, sum = 0
1022 11:45:28.417401 6, 0xFFFF, sum = 0
1023 11:45:28.417487 7, 0xFFFF, sum = 0
1024 11:45:28.420299 8, 0xFFFF, sum = 0
1025 11:45:28.420390 9, 0x0, sum = 1
1026 11:45:28.423623 10, 0x0, sum = 2
1027 11:45:28.423708 11, 0x0, sum = 3
1028 11:45:28.423795 12, 0x0, sum = 4
1029 11:45:28.427040 best_step = 10
1030 11:45:28.427123
1031 11:45:28.427209 ==
1032 11:45:28.430248 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 11:45:28.433531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 11:45:28.433616 ==
1035 11:45:28.436926 RX Vref Scan: 1
1036 11:45:28.437010
1037 11:45:28.440362 Set Vref Range= 32 -> 127
1038 11:45:28.440451
1039 11:45:28.440536 RX Vref 32 -> 127, step: 1
1040 11:45:28.440618
1041 11:45:28.443868 RX Delay -95 -> 252, step: 8
1042 11:45:28.443952
1043 11:45:28.447254 Set Vref, RX VrefLevel [Byte0]: 32
1044 11:45:28.450098 [Byte1]: 32
1045 11:45:28.453804
1046 11:45:28.453904 Set Vref, RX VrefLevel [Byte0]: 33
1047 11:45:28.457027 [Byte1]: 33
1048 11:45:28.461019
1049 11:45:28.461103 Set Vref, RX VrefLevel [Byte0]: 34
1050 11:45:28.464633 [Byte1]: 34
1051 11:45:28.468717
1052 11:45:28.468800 Set Vref, RX VrefLevel [Byte0]: 35
1053 11:45:28.472185 [Byte1]: 35
1054 11:45:28.476268
1055 11:45:28.476379 Set Vref, RX VrefLevel [Byte0]: 36
1056 11:45:28.479807 [Byte1]: 36
1057 11:45:28.483784
1058 11:45:28.483905 Set Vref, RX VrefLevel [Byte0]: 37
1059 11:45:28.487357 [Byte1]: 37
1060 11:45:28.491613
1061 11:45:28.491684 Set Vref, RX VrefLevel [Byte0]: 38
1062 11:45:28.494991 [Byte1]: 38
1063 11:45:28.499830
1064 11:45:28.499939 Set Vref, RX VrefLevel [Byte0]: 39
1065 11:45:28.502554 [Byte1]: 39
1066 11:45:28.506314
1067 11:45:28.510441 Set Vref, RX VrefLevel [Byte0]: 40
1068 11:45:28.510532 [Byte1]: 40
1069 11:45:28.515050
1070 11:45:28.515134 Set Vref, RX VrefLevel [Byte0]: 41
1071 11:45:28.518092 [Byte1]: 41
1072 11:45:28.521895
1073 11:45:28.521979 Set Vref, RX VrefLevel [Byte0]: 42
1074 11:45:28.525186 [Byte1]: 42
1075 11:45:28.529630
1076 11:45:28.529714 Set Vref, RX VrefLevel [Byte0]: 43
1077 11:45:28.532726 [Byte1]: 43
1078 11:45:28.537051
1079 11:45:28.537135 Set Vref, RX VrefLevel [Byte0]: 44
1080 11:45:28.540492 [Byte1]: 44
1081 11:45:28.544755
1082 11:45:28.544839 Set Vref, RX VrefLevel [Byte0]: 45
1083 11:45:28.547745 [Byte1]: 45
1084 11:45:28.552250
1085 11:45:28.552364 Set Vref, RX VrefLevel [Byte0]: 46
1086 11:45:28.555321 [Byte1]: 46
1087 11:45:28.559638
1088 11:45:28.559722 Set Vref, RX VrefLevel [Byte0]: 47
1089 11:45:28.562922 [Byte1]: 47
1090 11:45:28.567167
1091 11:45:28.567251 Set Vref, RX VrefLevel [Byte0]: 48
1092 11:45:28.570804 [Byte1]: 48
1093 11:45:28.575050
1094 11:45:28.575134 Set Vref, RX VrefLevel [Byte0]: 49
1095 11:45:28.578452 [Byte1]: 49
1096 11:45:28.582769
1097 11:45:28.582853 Set Vref, RX VrefLevel [Byte0]: 50
1098 11:45:28.586192 [Byte1]: 50
1099 11:45:28.589937
1100 11:45:28.590021 Set Vref, RX VrefLevel [Byte0]: 51
1101 11:45:28.593317 [Byte1]: 51
1102 11:45:28.597827
1103 11:45:28.597911 Set Vref, RX VrefLevel [Byte0]: 52
1104 11:45:28.601017 [Byte1]: 52
1105 11:45:28.605518
1106 11:45:28.605602 Set Vref, RX VrefLevel [Byte0]: 53
1107 11:45:28.608623 [Byte1]: 53
1108 11:45:28.613073
1109 11:45:28.613157 Set Vref, RX VrefLevel [Byte0]: 54
1110 11:45:28.616545 [Byte1]: 54
1111 11:45:28.620751
1112 11:45:28.620834 Set Vref, RX VrefLevel [Byte0]: 55
1113 11:45:28.623822 [Byte1]: 55
1114 11:45:28.628686
1115 11:45:28.628770 Set Vref, RX VrefLevel [Byte0]: 56
1116 11:45:28.631352 [Byte1]: 56
1117 11:45:28.636266
1118 11:45:28.636350 Set Vref, RX VrefLevel [Byte0]: 57
1119 11:45:28.639585 [Byte1]: 57
1120 11:45:28.643283
1121 11:45:28.643367 Set Vref, RX VrefLevel [Byte0]: 58
1122 11:45:28.646794 [Byte1]: 58
1123 11:45:28.650886
1124 11:45:28.650972 Set Vref, RX VrefLevel [Byte0]: 59
1125 11:45:28.654512 [Byte1]: 59
1126 11:45:28.658923
1127 11:45:28.661829 Set Vref, RX VrefLevel [Byte0]: 60
1128 11:45:28.661914 [Byte1]: 60
1129 11:45:28.665999
1130 11:45:28.666084 Set Vref, RX VrefLevel [Byte0]: 61
1131 11:45:28.669233 [Byte1]: 61
1132 11:45:28.673584
1133 11:45:28.673668 Set Vref, RX VrefLevel [Byte0]: 62
1134 11:45:28.676994 [Byte1]: 62
1135 11:45:28.681435
1136 11:45:28.681518 Set Vref, RX VrefLevel [Byte0]: 63
1137 11:45:28.684858 [Byte1]: 63
1138 11:45:28.688980
1139 11:45:28.689064 Set Vref, RX VrefLevel [Byte0]: 64
1140 11:45:28.692542 [Byte1]: 64
1141 11:45:28.696606
1142 11:45:28.696690 Set Vref, RX VrefLevel [Byte0]: 65
1143 11:45:28.700071 [Byte1]: 65
1144 11:45:28.703988
1145 11:45:28.704071 Set Vref, RX VrefLevel [Byte0]: 66
1146 11:45:28.707814 [Byte1]: 66
1147 11:45:28.712187
1148 11:45:28.712271 Set Vref, RX VrefLevel [Byte0]: 67
1149 11:45:28.714870 [Byte1]: 67
1150 11:45:28.719362
1151 11:45:28.719445 Set Vref, RX VrefLevel [Byte0]: 68
1152 11:45:28.722659 [Byte1]: 68
1153 11:45:28.727008
1154 11:45:28.727091 Set Vref, RX VrefLevel [Byte0]: 69
1155 11:45:28.730289 [Byte1]: 69
1156 11:45:28.734761
1157 11:45:28.734844 Set Vref, RX VrefLevel [Byte0]: 70
1158 11:45:28.737683 [Byte1]: 70
1159 11:45:28.742142
1160 11:45:28.742231 Set Vref, RX VrefLevel [Byte0]: 71
1161 11:45:28.745183 [Byte1]: 71
1162 11:45:28.749488
1163 11:45:28.749587 Set Vref, RX VrefLevel [Byte0]: 72
1164 11:45:28.753379 [Byte1]: 72
1165 11:45:28.757291
1166 11:45:28.760241 Set Vref, RX VrefLevel [Byte0]: 73
1167 11:45:28.763616 [Byte1]: 73
1168 11:45:28.763697
1169 11:45:28.766997 Set Vref, RX VrefLevel [Byte0]: 74
1170 11:45:28.770534 [Byte1]: 74
1171 11:45:28.770616
1172 11:45:28.773496 Set Vref, RX VrefLevel [Byte0]: 75
1173 11:45:28.777084 [Byte1]: 75
1174 11:45:28.777166
1175 11:45:28.780113 Set Vref, RX VrefLevel [Byte0]: 76
1176 11:45:28.783417 [Byte1]: 76
1177 11:45:28.787389
1178 11:45:28.787469 Final RX Vref Byte 0 = 53 to rank0
1179 11:45:28.791009 Final RX Vref Byte 1 = 60 to rank0
1180 11:45:28.794218 Final RX Vref Byte 0 = 53 to rank1
1181 11:45:28.797342 Final RX Vref Byte 1 = 60 to rank1==
1182 11:45:28.800861 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 11:45:28.807372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 11:45:28.807454 ==
1185 11:45:28.807520 DQS Delay:
1186 11:45:28.807580 DQS0 = 0, DQS1 = 0
1187 11:45:28.810926 DQM Delay:
1188 11:45:28.811007 DQM0 = 88, DQM1 = 76
1189 11:45:28.813819 DQ Delay:
1190 11:45:28.817777 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1191 11:45:28.820863 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1192 11:45:28.823824 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1193 11:45:28.827217 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1194 11:45:28.827323
1195 11:45:28.827413
1196 11:45:28.834193 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1197 11:45:28.836995 CH0 RK0: MR19=606, MR18=2F29
1198 11:45:28.843914 CH0_RK0: MR19=0x606, MR18=0x2F29, DQSOSC=397, MR23=63, INC=93, DEC=62
1199 11:45:28.844002
1200 11:45:28.847602 ----->DramcWriteLeveling(PI) begin...
1201 11:45:28.847674 ==
1202 11:45:28.850422 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 11:45:28.853912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 11:45:28.854018 ==
1205 11:45:28.857095 Write leveling (Byte 0): 31 => 31
1206 11:45:28.860512 Write leveling (Byte 1): 27 => 27
1207 11:45:28.864120 DramcWriteLeveling(PI) end<-----
1208 11:45:28.864219
1209 11:45:28.864308 ==
1210 11:45:28.867160 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 11:45:28.870397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 11:45:28.870467 ==
1213 11:45:28.873525 [Gating] SW mode calibration
1214 11:45:28.880070 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 11:45:28.924213 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 11:45:28.924554 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 11:45:28.924808 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 11:45:28.925090 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1219 11:45:28.925194 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:45:28.925286 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:45:28.925873 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:45:28.926208 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:45:28.926513 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:45:28.954817 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:45:28.954899 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:45:28.955174 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:45:28.955241 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:45:28.955484 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:45:28.955730 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:45:28.955793 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:45:28.958427 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:45:28.961741 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1233 11:45:28.965400 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1234 11:45:28.968674 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1235 11:45:28.975104 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1236 11:45:28.978546 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:45:28.982042 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:45:28.988425 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:45:28.991421 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:45:28.995058 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:45:29.001782 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1242 11:45:29.004925 0 9 8 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
1243 11:45:29.008416 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 11:45:29.014813 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 11:45:29.018076 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 11:45:29.021750 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 11:45:29.028126 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:45:29.031606 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:45:29.035052 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
1250 11:45:29.042001 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (0 1) (0 0)
1251 11:45:29.044772 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1252 11:45:29.048216 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:45:29.054609 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:45:29.057957 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:45:29.061619 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:45:29.065301 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:45:29.072907 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1258 11:45:29.076519 0 11 8 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
1259 11:45:29.080062 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1260 11:45:29.083362 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 11:45:29.089652 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 11:45:29.093688 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:45:29.097024 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:45:29.100536 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:45:29.106987 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1266 11:45:29.110243 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1267 11:45:29.113533 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:45:29.120236 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:45:29.123789 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:45:29.127128 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:45:29.133745 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:45:29.136764 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:45:29.139952 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:45:29.146662 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:45:29.150210 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:45:29.153240 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:45:29.160058 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:45:29.163702 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:45:29.166729 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:45:29.173383 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:45:29.176354 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1282 11:45:29.179897 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1283 11:45:29.183146 Total UI for P1: 0, mck2ui 16
1284 11:45:29.186495 best dqsien dly found for B0: ( 0, 14, 4)
1285 11:45:29.193415 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 11:45:29.193486 Total UI for P1: 0, mck2ui 16
1287 11:45:29.200155 best dqsien dly found for B1: ( 0, 14, 8)
1288 11:45:29.203390 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1289 11:45:29.206332 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1290 11:45:29.206406
1291 11:45:29.210038 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1292 11:45:29.213549 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1293 11:45:29.216449 [Gating] SW calibration Done
1294 11:45:29.216554 ==
1295 11:45:29.219483 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 11:45:29.223182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 11:45:29.223270 ==
1298 11:45:29.226447 RX Vref Scan: 0
1299 11:45:29.226541
1300 11:45:29.226638 RX Vref 0 -> 0, step: 1
1301 11:45:29.226726
1302 11:45:29.229640 RX Delay -130 -> 252, step: 16
1303 11:45:29.233009 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1304 11:45:29.239635 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1305 11:45:29.243309 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1306 11:45:29.246287 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1307 11:45:29.249431 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1308 11:45:29.252780 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1309 11:45:29.259740 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1310 11:45:29.262837 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1311 11:45:29.265920 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1312 11:45:29.269327 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1313 11:45:29.272737 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1314 11:45:29.279613 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1315 11:45:29.282578 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1316 11:45:29.285875 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1317 11:45:29.289189 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1318 11:45:29.296310 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1319 11:45:29.296391 ==
1320 11:45:29.299721 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 11:45:29.302505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 11:45:29.302586 ==
1323 11:45:29.302651 DQS Delay:
1324 11:45:29.305853 DQS0 = 0, DQS1 = 0
1325 11:45:29.305964 DQM Delay:
1326 11:45:29.309051 DQM0 = 87, DQM1 = 78
1327 11:45:29.309154 DQ Delay:
1328 11:45:29.312588 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1329 11:45:29.315980 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1330 11:45:29.318919 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1331 11:45:29.322230 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1332 11:45:29.322334
1333 11:45:29.322398
1334 11:45:29.322458 ==
1335 11:45:29.325628 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 11:45:29.329104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 11:45:29.329186 ==
1338 11:45:29.329251
1339 11:45:29.329311
1340 11:45:29.332510 TX Vref Scan disable
1341 11:45:29.335541 == TX Byte 0 ==
1342 11:45:29.338792 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1343 11:45:29.342075 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1344 11:45:29.345723 == TX Byte 1 ==
1345 11:45:29.348646 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1346 11:45:29.352073 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1347 11:45:29.352155 ==
1348 11:45:29.355398 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 11:45:29.362293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 11:45:29.362390 ==
1351 11:45:29.374628 TX Vref=22, minBit 0, minWin=27, winSum=439
1352 11:45:29.378064 TX Vref=24, minBit 1, minWin=27, winSum=442
1353 11:45:29.380889 TX Vref=26, minBit 2, minWin=27, winSum=446
1354 11:45:29.384399 TX Vref=28, minBit 1, minWin=27, winSum=453
1355 11:45:29.387732 TX Vref=30, minBit 1, minWin=27, winSum=450
1356 11:45:29.393873 TX Vref=32, minBit 1, minWin=27, winSum=452
1357 11:45:29.397416 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 28
1358 11:45:29.397498
1359 11:45:29.400944 Final TX Range 1 Vref 28
1360 11:45:29.401025
1361 11:45:29.401089 ==
1362 11:45:29.403860 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 11:45:29.407342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 11:45:29.407424 ==
1365 11:45:29.410912
1366 11:45:29.410992
1367 11:45:29.411055 TX Vref Scan disable
1368 11:45:29.414191 == TX Byte 0 ==
1369 11:45:29.417548 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1370 11:45:29.424047 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1371 11:45:29.424128 == TX Byte 1 ==
1372 11:45:29.427486 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1373 11:45:29.430744 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1374 11:45:29.434387
1375 11:45:29.434467 [DATLAT]
1376 11:45:29.434531 Freq=800, CH0 RK1
1377 11:45:29.434591
1378 11:45:29.437683 DATLAT Default: 0xa
1379 11:45:29.437763 0, 0xFFFF, sum = 0
1380 11:45:29.440556 1, 0xFFFF, sum = 0
1381 11:45:29.440638 2, 0xFFFF, sum = 0
1382 11:45:29.443942 3, 0xFFFF, sum = 0
1383 11:45:29.444023 4, 0xFFFF, sum = 0
1384 11:45:29.447187 5, 0xFFFF, sum = 0
1385 11:45:29.450735 6, 0xFFFF, sum = 0
1386 11:45:29.450817 7, 0xFFFF, sum = 0
1387 11:45:29.454158 8, 0xFFFF, sum = 0
1388 11:45:29.454264 9, 0x0, sum = 1
1389 11:45:29.454346 10, 0x0, sum = 2
1390 11:45:29.457346 11, 0x0, sum = 3
1391 11:45:29.457427 12, 0x0, sum = 4
1392 11:45:29.460958 best_step = 10
1393 11:45:29.461038
1394 11:45:29.461101 ==
1395 11:45:29.464112 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 11:45:29.466988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 11:45:29.467069 ==
1398 11:45:29.470379 RX Vref Scan: 0
1399 11:45:29.470459
1400 11:45:29.470522 RX Vref 0 -> 0, step: 1
1401 11:45:29.473835
1402 11:45:29.473915 RX Delay -95 -> 252, step: 8
1403 11:45:29.481049 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1404 11:45:29.484904 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1405 11:45:29.487468 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1406 11:45:29.490815 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1407 11:45:29.494191 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1408 11:45:29.500602 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1409 11:45:29.503956 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1410 11:45:29.507417 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1411 11:45:29.510816 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1412 11:45:29.514487 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1413 11:45:29.521150 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1414 11:45:29.524008 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1415 11:45:29.527374 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1416 11:45:29.530836 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1417 11:45:29.534030 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1418 11:45:29.541004 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1419 11:45:29.541085 ==
1420 11:45:29.544086 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 11:45:29.547978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 11:45:29.548059 ==
1423 11:45:29.548122 DQS Delay:
1424 11:45:29.550552 DQS0 = 0, DQS1 = 0
1425 11:45:29.550632 DQM Delay:
1426 11:45:29.554062 DQM0 = 86, DQM1 = 77
1427 11:45:29.554142 DQ Delay:
1428 11:45:29.557273 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1429 11:45:29.560670 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1430 11:45:29.563926 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1431 11:45:29.567252 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1432 11:45:29.567348
1433 11:45:29.567411
1434 11:45:29.577115 [DQSOSCAuto] RK1, (LSB)MR18= 0x2723, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1435 11:45:29.577197 CH0 RK1: MR19=606, MR18=2723
1436 11:45:29.583721 CH0_RK1: MR19=0x606, MR18=0x2723, DQSOSC=400, MR23=63, INC=92, DEC=61
1437 11:45:29.586867 [RxdqsGatingPostProcess] freq 800
1438 11:45:29.593450 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 11:45:29.597116 Pre-setting of DQS Precalculation
1440 11:45:29.599983 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 11:45:29.600068 ==
1442 11:45:29.603172 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 11:45:29.609850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 11:45:29.609959 ==
1445 11:45:29.613332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 11:45:29.619667 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 11:45:29.629110 [CA 0] Center 37 (6~68) winsize 63
1448 11:45:29.632653 [CA 1] Center 37 (6~68) winsize 63
1449 11:45:29.636177 [CA 2] Center 35 (5~65) winsize 61
1450 11:45:29.638989 [CA 3] Center 34 (4~65) winsize 62
1451 11:45:29.642380 [CA 4] Center 34 (4~65) winsize 62
1452 11:45:29.645592 [CA 5] Center 34 (3~65) winsize 63
1453 11:45:29.645673
1454 11:45:29.649087 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 11:45:29.649168
1456 11:45:29.652952 [CATrainingPosCal] consider 1 rank data
1457 11:45:29.655803 u2DelayCellTimex100 = 270/100 ps
1458 11:45:29.659094 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1459 11:45:29.662699 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1460 11:45:29.668969 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1461 11:45:29.672512 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1462 11:45:29.676281 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 11:45:29.679402 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1464 11:45:29.679498
1465 11:45:29.682265 CA PerBit enable=1, Macro0, CA PI delay=34
1466 11:45:29.682363
1467 11:45:29.685570 [CBTSetCACLKResult] CA Dly = 34
1468 11:45:29.685643 CS Dly: 4 (0~35)
1469 11:45:29.689154 ==
1470 11:45:29.689251 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 11:45:29.695848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 11:45:29.695923 ==
1473 11:45:29.698804 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 11:45:29.705791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 11:45:29.715506 [CA 0] Center 36 (6~67) winsize 62
1476 11:45:29.718944 [CA 1] Center 36 (6~67) winsize 62
1477 11:45:29.721872 [CA 2] Center 34 (4~65) winsize 62
1478 11:45:29.725623 [CA 3] Center 34 (3~65) winsize 63
1479 11:45:29.728920 [CA 4] Center 34 (4~65) winsize 62
1480 11:45:29.732355 [CA 5] Center 33 (3~64) winsize 62
1481 11:45:29.732440
1482 11:45:29.735853 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1483 11:45:29.735932
1484 11:45:29.739435 [CATrainingPosCal] consider 2 rank data
1485 11:45:29.743459 u2DelayCellTimex100 = 270/100 ps
1486 11:45:29.747551 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1487 11:45:29.750838 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1488 11:45:29.754736 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1489 11:45:29.758179 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1490 11:45:29.761528 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1491 11:45:29.765705 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1492 11:45:29.765803
1493 11:45:29.768483 CA PerBit enable=1, Macro0, CA PI delay=33
1494 11:45:29.768579
1495 11:45:29.771976 [CBTSetCACLKResult] CA Dly = 33
1496 11:45:29.772075 CS Dly: 5 (0~37)
1497 11:45:29.772175
1498 11:45:29.775476 ----->DramcWriteLeveling(PI) begin...
1499 11:45:29.778917 ==
1500 11:45:29.781877 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 11:45:29.785409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 11:45:29.785500 ==
1503 11:45:29.789065 Write leveling (Byte 0): 28 => 28
1504 11:45:29.791982 Write leveling (Byte 1): 27 => 27
1505 11:45:29.795563 DramcWriteLeveling(PI) end<-----
1506 11:45:29.795671
1507 11:45:29.795761 ==
1508 11:45:29.798611 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 11:45:29.802059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 11:45:29.802159 ==
1511 11:45:29.805282 [Gating] SW mode calibration
1512 11:45:29.811925 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 11:45:29.818092 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 11:45:29.821713 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 11:45:29.825015 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1516 11:45:29.831932 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:45:29.834960 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:45:29.838232 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:45:29.845057 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:45:29.848009 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:45:29.851763 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:45:29.854735 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:45:29.861330 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:45:29.864795 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:45:29.867876 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:45:29.874715 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:45:29.878342 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:45:29.881260 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:45:29.888228 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:45:29.891721 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1531 11:45:29.895005 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1532 11:45:29.901648 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:45:29.904576 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:45:29.908011 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:45:29.914932 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:45:29.918036 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:45:29.921431 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:45:29.927533 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:45:29.931346 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:45:29.934003 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1541 11:45:29.941214 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 11:45:29.944368 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 11:45:29.947595 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 11:45:29.954597 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 11:45:29.957624 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:45:29.960889 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:45:29.967481 0 10 4 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (0 0)
1548 11:45:29.970741 0 10 8 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
1549 11:45:29.974135 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:45:29.980877 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:45:29.984300 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:45:29.987345 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:45:29.993971 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:45:29.997735 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:45:30.000709 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1556 11:45:30.004244 0 11 8 | B1->B0 | 3b3b 4343 | 1 0 | (0 0) (0 0)
1557 11:45:30.010853 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 11:45:30.014001 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 11:45:30.017129 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:45:30.023972 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 11:45:30.027279 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:45:30.030762 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:45:30.037605 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1564 11:45:30.040614 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1565 11:45:30.044027 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:45:30.050522 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:45:30.053971 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:45:30.057105 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:45:30.063835 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:45:30.067413 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:45:30.070336 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:45:30.076957 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:45:30.080190 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:45:30.083147 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:45:30.090113 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:45:30.093226 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:45:30.096609 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:45:30.103397 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1579 11:45:30.106829 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:45:30.110052 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1581 11:45:30.113375 Total UI for P1: 0, mck2ui 16
1582 11:45:30.116827 best dqsien dly found for B0: ( 0, 14, 6)
1583 11:45:30.123432 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 11:45:30.123523 Total UI for P1: 0, mck2ui 16
1585 11:45:30.129769 best dqsien dly found for B1: ( 0, 14, 8)
1586 11:45:30.133160 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1587 11:45:30.136741 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1588 11:45:30.136823
1589 11:45:30.140155 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1590 11:45:30.143129 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1591 11:45:30.146730 [Gating] SW calibration Done
1592 11:45:30.146802 ==
1593 11:45:30.150127 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 11:45:30.153488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 11:45:30.153560 ==
1596 11:45:30.156484 RX Vref Scan: 0
1597 11:45:30.156553
1598 11:45:30.156622 RX Vref 0 -> 0, step: 1
1599 11:45:30.156685
1600 11:45:30.159760 RX Delay -130 -> 252, step: 16
1601 11:45:30.163179 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1602 11:45:30.169642 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1603 11:45:30.173624 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1604 11:45:30.176347 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1605 11:45:30.179891 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1606 11:45:30.182965 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1607 11:45:30.189822 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1608 11:45:30.192603 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1609 11:45:30.196056 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1610 11:45:30.199655 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1611 11:45:30.203476 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1612 11:45:30.209753 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1613 11:45:30.212681 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1614 11:45:30.216200 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1615 11:45:30.219208 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1616 11:45:30.226051 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1617 11:45:30.226131 ==
1618 11:45:30.229404 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 11:45:30.232574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 11:45:30.232655 ==
1621 11:45:30.232737 DQS Delay:
1622 11:45:30.236126 DQS0 = 0, DQS1 = 0
1623 11:45:30.236211 DQM Delay:
1624 11:45:30.239612 DQM0 = 86, DQM1 = 79
1625 11:45:30.239687 DQ Delay:
1626 11:45:30.242472 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1627 11:45:30.246059 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1628 11:45:30.249394 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1629 11:45:30.252354 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1630 11:45:30.252429
1631 11:45:30.252510
1632 11:45:30.252595 ==
1633 11:45:30.255848 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 11:45:30.259355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 11:45:30.259430 ==
1636 11:45:30.259511
1637 11:45:30.262413
1638 11:45:30.262487 TX Vref Scan disable
1639 11:45:30.265776 == TX Byte 0 ==
1640 11:45:30.269136 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1641 11:45:30.272529 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1642 11:45:30.276196 == TX Byte 1 ==
1643 11:45:30.279382 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1644 11:45:30.282217 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1645 11:45:30.282321 ==
1646 11:45:30.286078 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 11:45:30.292609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 11:45:30.292690 ==
1649 11:45:30.304586 TX Vref=22, minBit 0, minWin=27, winSum=441
1650 11:45:30.307521 TX Vref=24, minBit 0, minWin=27, winSum=449
1651 11:45:30.310898 TX Vref=26, minBit 1, minWin=27, winSum=452
1652 11:45:30.314730 TX Vref=28, minBit 1, minWin=27, winSum=454
1653 11:45:30.318655 TX Vref=30, minBit 1, minWin=27, winSum=452
1654 11:45:30.322013 TX Vref=32, minBit 1, minWin=27, winSum=453
1655 11:45:30.328600 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 28
1656 11:45:30.328680
1657 11:45:30.331347 Final TX Range 1 Vref 28
1658 11:45:30.331422
1659 11:45:30.331509 ==
1660 11:45:30.334857 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 11:45:30.338288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 11:45:30.338372 ==
1663 11:45:30.338455
1664 11:45:30.338535
1665 11:45:30.341684 TX Vref Scan disable
1666 11:45:30.344728 == TX Byte 0 ==
1667 11:45:30.348359 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1668 11:45:30.351200 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1669 11:45:30.354463 == TX Byte 1 ==
1670 11:45:30.358053 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1671 11:45:30.361635 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1672 11:45:30.361709
1673 11:45:30.364608 [DATLAT]
1674 11:45:30.364680 Freq=800, CH1 RK0
1675 11:45:30.364760
1676 11:45:30.367950 DATLAT Default: 0xa
1677 11:45:30.368026 0, 0xFFFF, sum = 0
1678 11:45:30.371712 1, 0xFFFF, sum = 0
1679 11:45:30.371788 2, 0xFFFF, sum = 0
1680 11:45:30.374819 3, 0xFFFF, sum = 0
1681 11:45:30.374895 4, 0xFFFF, sum = 0
1682 11:45:30.378139 5, 0xFFFF, sum = 0
1683 11:45:30.378239 6, 0xFFFF, sum = 0
1684 11:45:30.381052 7, 0xFFFF, sum = 0
1685 11:45:30.381133 8, 0xFFFF, sum = 0
1686 11:45:30.384625 9, 0x0, sum = 1
1687 11:45:30.384712 10, 0x0, sum = 2
1688 11:45:30.387936 11, 0x0, sum = 3
1689 11:45:30.388023 12, 0x0, sum = 4
1690 11:45:30.391480 best_step = 10
1691 11:45:30.391556
1692 11:45:30.391638 ==
1693 11:45:30.394283 Dram Type= 6, Freq= 0, CH_1, rank 0
1694 11:45:30.397755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1695 11:45:30.397833 ==
1696 11:45:30.401289 RX Vref Scan: 1
1697 11:45:30.401365
1698 11:45:30.401446 Set Vref Range= 32 -> 127
1699 11:45:30.401528
1700 11:45:30.404196 RX Vref 32 -> 127, step: 1
1701 11:45:30.404281
1702 11:45:30.407720 RX Delay -95 -> 252, step: 8
1703 11:45:30.407795
1704 11:45:30.411088 Set Vref, RX VrefLevel [Byte0]: 32
1705 11:45:30.414505 [Byte1]: 32
1706 11:45:30.414580
1707 11:45:30.417707 Set Vref, RX VrefLevel [Byte0]: 33
1708 11:45:30.421164 [Byte1]: 33
1709 11:45:30.424384
1710 11:45:30.424493 Set Vref, RX VrefLevel [Byte0]: 34
1711 11:45:30.427849 [Byte1]: 34
1712 11:45:30.431897
1713 11:45:30.431978 Set Vref, RX VrefLevel [Byte0]: 35
1714 11:45:30.435070 [Byte1]: 35
1715 11:45:30.439433
1716 11:45:30.439518 Set Vref, RX VrefLevel [Byte0]: 36
1717 11:45:30.443097 [Byte1]: 36
1718 11:45:30.446984
1719 11:45:30.447061 Set Vref, RX VrefLevel [Byte0]: 37
1720 11:45:30.450449 [Byte1]: 37
1721 11:45:30.454978
1722 11:45:30.455058 Set Vref, RX VrefLevel [Byte0]: 38
1723 11:45:30.458109 [Byte1]: 38
1724 11:45:30.462490
1725 11:45:30.462565 Set Vref, RX VrefLevel [Byte0]: 39
1726 11:45:30.465444 [Byte1]: 39
1727 11:45:30.470014
1728 11:45:30.470137 Set Vref, RX VrefLevel [Byte0]: 40
1729 11:45:30.472989 [Byte1]: 40
1730 11:45:30.477460
1731 11:45:30.477581 Set Vref, RX VrefLevel [Byte0]: 41
1732 11:45:30.480973 [Byte1]: 41
1733 11:45:30.485344
1734 11:45:30.485442 Set Vref, RX VrefLevel [Byte0]: 42
1735 11:45:30.488301 [Byte1]: 42
1736 11:45:30.492672
1737 11:45:30.492774 Set Vref, RX VrefLevel [Byte0]: 43
1738 11:45:30.495741 [Byte1]: 43
1739 11:45:30.500185
1740 11:45:30.500293 Set Vref, RX VrefLevel [Byte0]: 44
1741 11:45:30.503706 [Byte1]: 44
1742 11:45:30.507973
1743 11:45:30.508069 Set Vref, RX VrefLevel [Byte0]: 45
1744 11:45:30.511218 [Byte1]: 45
1745 11:45:30.515734
1746 11:45:30.515836 Set Vref, RX VrefLevel [Byte0]: 46
1747 11:45:30.519492 [Byte1]: 46
1748 11:45:30.523284
1749 11:45:30.523381 Set Vref, RX VrefLevel [Byte0]: 47
1750 11:45:30.526746 [Byte1]: 47
1751 11:45:30.530754
1752 11:45:30.530837 Set Vref, RX VrefLevel [Byte0]: 48
1753 11:45:30.537001 [Byte1]: 48
1754 11:45:30.537081
1755 11:45:30.540721 Set Vref, RX VrefLevel [Byte0]: 49
1756 11:45:30.544195 [Byte1]: 49
1757 11:45:30.544278
1758 11:45:30.547081 Set Vref, RX VrefLevel [Byte0]: 50
1759 11:45:30.550625 [Byte1]: 50
1760 11:45:30.550703
1761 11:45:30.553595 Set Vref, RX VrefLevel [Byte0]: 51
1762 11:45:30.557434 [Byte1]: 51
1763 11:45:30.560903
1764 11:45:30.560982 Set Vref, RX VrefLevel [Byte0]: 52
1765 11:45:30.564519 [Byte1]: 52
1766 11:45:30.568591
1767 11:45:30.568673 Set Vref, RX VrefLevel [Byte0]: 53
1768 11:45:30.572069 [Byte1]: 53
1769 11:45:30.576259
1770 11:45:30.576332 Set Vref, RX VrefLevel [Byte0]: 54
1771 11:45:30.579885 [Byte1]: 54
1772 11:45:30.584005
1773 11:45:30.584083 Set Vref, RX VrefLevel [Byte0]: 55
1774 11:45:30.587554 [Byte1]: 55
1775 11:45:30.591467
1776 11:45:30.591543 Set Vref, RX VrefLevel [Byte0]: 56
1777 11:45:30.594907 [Byte1]: 56
1778 11:45:30.599014
1779 11:45:30.599098 Set Vref, RX VrefLevel [Byte0]: 57
1780 11:45:30.602409 [Byte1]: 57
1781 11:45:30.606539
1782 11:45:30.606619 Set Vref, RX VrefLevel [Byte0]: 58
1783 11:45:30.609905 [Byte1]: 58
1784 11:45:30.614574
1785 11:45:30.614657 Set Vref, RX VrefLevel [Byte0]: 59
1786 11:45:30.617628 [Byte1]: 59
1787 11:45:30.621768
1788 11:45:30.621842 Set Vref, RX VrefLevel [Byte0]: 60
1789 11:45:30.624976 [Byte1]: 60
1790 11:45:30.629706
1791 11:45:30.629790 Set Vref, RX VrefLevel [Byte0]: 61
1792 11:45:30.635665 [Byte1]: 61
1793 11:45:30.635752
1794 11:45:30.639236 Set Vref, RX VrefLevel [Byte0]: 62
1795 11:45:30.642765 [Byte1]: 62
1796 11:45:30.642846
1797 11:45:30.645927 Set Vref, RX VrefLevel [Byte0]: 63
1798 11:45:30.649158 [Byte1]: 63
1799 11:45:30.649256
1800 11:45:30.652769 Set Vref, RX VrefLevel [Byte0]: 64
1801 11:45:30.656057 [Byte1]: 64
1802 11:45:30.659931
1803 11:45:30.660003 Set Vref, RX VrefLevel [Byte0]: 65
1804 11:45:30.663272 [Byte1]: 65
1805 11:45:30.667351
1806 11:45:30.667425 Set Vref, RX VrefLevel [Byte0]: 66
1807 11:45:30.670981 [Byte1]: 66
1808 11:45:30.675430
1809 11:45:30.675527 Set Vref, RX VrefLevel [Byte0]: 67
1810 11:45:30.678336 [Byte1]: 67
1811 11:45:30.682896
1812 11:45:30.682973 Set Vref, RX VrefLevel [Byte0]: 68
1813 11:45:30.685903 [Byte1]: 68
1814 11:45:30.690398
1815 11:45:30.690482 Set Vref, RX VrefLevel [Byte0]: 69
1816 11:45:30.693775 [Byte1]: 69
1817 11:45:30.698077
1818 11:45:30.698172 Set Vref, RX VrefLevel [Byte0]: 70
1819 11:45:30.701343 [Byte1]: 70
1820 11:45:30.705276
1821 11:45:30.705371 Set Vref, RX VrefLevel [Byte0]: 71
1822 11:45:30.708932 [Byte1]: 71
1823 11:45:30.713040
1824 11:45:30.713140 Set Vref, RX VrefLevel [Byte0]: 72
1825 11:45:30.716339 [Byte1]: 72
1826 11:45:30.720769
1827 11:45:30.720841 Set Vref, RX VrefLevel [Byte0]: 73
1828 11:45:30.723763 [Byte1]: 73
1829 11:45:30.728266
1830 11:45:30.728334 Set Vref, RX VrefLevel [Byte0]: 74
1831 11:45:30.731596 [Byte1]: 74
1832 11:45:30.736143
1833 11:45:30.736218 Set Vref, RX VrefLevel [Byte0]: 75
1834 11:45:30.739365 [Byte1]: 75
1835 11:45:30.743337
1836 11:45:30.743424 Final RX Vref Byte 0 = 60 to rank0
1837 11:45:30.746949 Final RX Vref Byte 1 = 53 to rank0
1838 11:45:30.750355 Final RX Vref Byte 0 = 60 to rank1
1839 11:45:30.753297 Final RX Vref Byte 1 = 53 to rank1==
1840 11:45:30.756826 Dram Type= 6, Freq= 0, CH_1, rank 0
1841 11:45:30.763217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 11:45:30.763293 ==
1843 11:45:30.763356 DQS Delay:
1844 11:45:30.763415 DQS0 = 0, DQS1 = 0
1845 11:45:30.766889 DQM Delay:
1846 11:45:30.766958 DQM0 = 86, DQM1 = 80
1847 11:45:30.769952 DQ Delay:
1848 11:45:30.773461 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1849 11:45:30.776461 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1850 11:45:30.780030 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1851 11:45:30.783574 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1852 11:45:30.783669
1853 11:45:30.783758
1854 11:45:30.789825 [DQSOSCAuto] RK0, (LSB)MR18= 0x182b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1855 11:45:30.793289 CH1 RK0: MR19=606, MR18=182B
1856 11:45:30.799514 CH1_RK0: MR19=0x606, MR18=0x182B, DQSOSC=398, MR23=63, INC=93, DEC=62
1857 11:45:30.799605
1858 11:45:30.802974 ----->DramcWriteLeveling(PI) begin...
1859 11:45:30.803049 ==
1860 11:45:30.806494 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 11:45:30.809938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 11:45:30.810018 ==
1863 11:45:30.813260 Write leveling (Byte 0): 25 => 25
1864 11:45:30.816325 Write leveling (Byte 1): 26 => 26
1865 11:45:30.819642 DramcWriteLeveling(PI) end<-----
1866 11:45:30.819717
1867 11:45:30.819801 ==
1868 11:45:30.823019 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 11:45:30.826359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1870 11:45:30.826434 ==
1871 11:45:30.829865 [Gating] SW mode calibration
1872 11:45:30.835931 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1873 11:45:30.842657 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1874 11:45:30.845892 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1875 11:45:30.853022 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1876 11:45:30.856364 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:45:30.859247 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:45:30.863047 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:45:30.869277 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:45:30.872844 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:45:30.876191 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:45:30.882974 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:45:30.886040 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:45:30.889316 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:45:30.896175 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:45:30.899586 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:45:30.902409 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:45:30.909016 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:45:30.912494 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:45:30.915459 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:45:30.922392 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1892 11:45:30.925789 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1893 11:45:30.928949 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:45:30.935710 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:45:30.939177 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:45:30.942442 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:45:30.949038 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:45:30.952255 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:45:30.955878 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1900 11:45:30.962165 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1901 11:45:30.965456 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 11:45:30.968742 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 11:45:30.975637 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 11:45:30.978905 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 11:45:30.982309 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 11:45:30.988667 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 11:45:30.992129 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1908 11:45:30.995459 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1909 11:45:31.002238 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:45:31.005382 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:45:31.008590 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:45:31.014966 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 11:45:31.018402 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 11:45:31.022015 0 11 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
1915 11:45:31.029064 0 11 4 | B1->B0 | 2424 3939 | 0 0 | (0 0) (0 0)
1916 11:45:31.031443 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1917 11:45:31.035326 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 11:45:31.041756 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 11:45:31.045321 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 11:45:31.048114 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 11:45:31.051718 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 11:45:31.058152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1923 11:45:31.061351 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1924 11:45:31.065014 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1925 11:45:31.071192 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:45:31.074738 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:45:31.077973 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:45:31.084533 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:45:31.087847 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:45:31.091276 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:45:31.098283 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:45:31.101430 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:45:31.104471 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:45:31.111321 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:45:31.114454 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:45:31.117892 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:45:31.124302 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:45:31.127845 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1939 11:45:31.131172 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1940 11:45:31.134682 Total UI for P1: 0, mck2ui 16
1941 11:45:31.137576 best dqsien dly found for B0: ( 0, 14, 0)
1942 11:45:31.144491 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1943 11:45:31.147819 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 11:45:31.151199 Total UI for P1: 0, mck2ui 16
1945 11:45:31.154542 best dqsien dly found for B1: ( 0, 14, 6)
1946 11:45:31.157895 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1947 11:45:31.161258 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1948 11:45:31.161329
1949 11:45:31.164335 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1950 11:45:31.167617 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1951 11:45:31.170680 [Gating] SW calibration Done
1952 11:45:31.170754 ==
1953 11:45:31.173965 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 11:45:31.177431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 11:45:31.181021 ==
1956 11:45:31.181099 RX Vref Scan: 0
1957 11:45:31.181162
1958 11:45:31.183786 RX Vref 0 -> 0, step: 1
1959 11:45:31.183865
1960 11:45:31.187195 RX Delay -130 -> 252, step: 16
1961 11:45:31.190730 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1962 11:45:31.193930 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1963 11:45:31.197648 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1964 11:45:31.200411 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1965 11:45:31.207261 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1966 11:45:31.210930 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1967 11:45:31.214159 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1968 11:45:31.216997 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1969 11:45:31.220660 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1970 11:45:31.227623 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1971 11:45:31.230222 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1972 11:45:31.233846 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1973 11:45:31.236904 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1974 11:45:31.240240 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1975 11:45:31.246840 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1976 11:45:31.250143 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1977 11:45:31.250213 ==
1978 11:45:31.253752 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 11:45:31.257265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 11:45:31.257334 ==
1981 11:45:31.260002 DQS Delay:
1982 11:45:31.260065 DQS0 = 0, DQS1 = 0
1983 11:45:31.260123 DQM Delay:
1984 11:45:31.263853 DQM0 = 82, DQM1 = 79
1985 11:45:31.263924 DQ Delay:
1986 11:45:31.267093 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1987 11:45:31.270387 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1988 11:45:31.273653 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1989 11:45:31.277406 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1990 11:45:31.277470
1991 11:45:31.277533
1992 11:45:31.277589 ==
1993 11:45:31.280100 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 11:45:31.287341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 11:45:31.287425 ==
1996 11:45:31.287489
1997 11:45:31.287548
1998 11:45:31.287609 TX Vref Scan disable
1999 11:45:31.290524 == TX Byte 0 ==
2000 11:45:31.294235 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2001 11:45:31.300226 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2002 11:45:31.300298 == TX Byte 1 ==
2003 11:45:31.303958 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2004 11:45:31.310493 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2005 11:45:31.310571 ==
2006 11:45:31.313932 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 11:45:31.316851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 11:45:31.316919 ==
2009 11:45:31.329597 TX Vref=22, minBit 1, minWin=27, winSum=444
2010 11:45:31.332977 TX Vref=24, minBit 1, minWin=27, winSum=450
2011 11:45:31.336623 TX Vref=26, minBit 1, minWin=27, winSum=451
2012 11:45:31.339831 TX Vref=28, minBit 0, minWin=27, winSum=454
2013 11:45:31.342763 TX Vref=30, minBit 6, minWin=27, winSum=458
2014 11:45:31.349541 TX Vref=32, minBit 4, minWin=27, winSum=456
2015 11:45:31.352600 [TxChooseVref] Worse bit 6, Min win 27, Win sum 458, Final Vref 30
2016 11:45:31.352679
2017 11:45:31.355930 Final TX Range 1 Vref 30
2018 11:45:31.356005
2019 11:45:31.356092 ==
2020 11:45:31.359209 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 11:45:31.362461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 11:45:31.365393 ==
2023 11:45:31.365467
2024 11:45:31.365548
2025 11:45:31.365632 TX Vref Scan disable
2026 11:45:31.369130 == TX Byte 0 ==
2027 11:45:31.372446 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2028 11:45:31.379354 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2029 11:45:31.379432 == TX Byte 1 ==
2030 11:45:31.382690 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2031 11:45:31.389080 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2032 11:45:31.389165
2033 11:45:31.389249 [DATLAT]
2034 11:45:31.389327 Freq=800, CH1 RK1
2035 11:45:31.389409
2036 11:45:31.392793 DATLAT Default: 0xa
2037 11:45:31.392878 0, 0xFFFF, sum = 0
2038 11:45:31.395710 1, 0xFFFF, sum = 0
2039 11:45:31.398985 2, 0xFFFF, sum = 0
2040 11:45:31.399060 3, 0xFFFF, sum = 0
2041 11:45:31.402557 4, 0xFFFF, sum = 0
2042 11:45:31.402638 5, 0xFFFF, sum = 0
2043 11:45:31.405896 6, 0xFFFF, sum = 0
2044 11:45:31.405978 7, 0xFFFF, sum = 0
2045 11:45:31.409068 8, 0xFFFF, sum = 0
2046 11:45:31.409142 9, 0x0, sum = 1
2047 11:45:31.412423 10, 0x0, sum = 2
2048 11:45:31.412504 11, 0x0, sum = 3
2049 11:45:31.412586 12, 0x0, sum = 4
2050 11:45:31.415508 best_step = 10
2051 11:45:31.415581
2052 11:45:31.415661 ==
2053 11:45:31.419018 Dram Type= 6, Freq= 0, CH_1, rank 1
2054 11:45:31.422600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2055 11:45:31.422676 ==
2056 11:45:31.425514 RX Vref Scan: 0
2057 11:45:31.425591
2058 11:45:31.429046 RX Vref 0 -> 0, step: 1
2059 11:45:31.429123
2060 11:45:31.429212 RX Delay -95 -> 252, step: 8
2061 11:45:31.436132 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2062 11:45:31.439133 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2063 11:45:31.442518 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2064 11:45:31.445997 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2065 11:45:31.449444 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2066 11:45:31.455882 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2067 11:45:31.459338 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2068 11:45:31.462487 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2069 11:45:31.465801 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2070 11:45:31.469213 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2071 11:45:31.475549 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2072 11:45:31.479168 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2073 11:45:31.482341 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2074 11:45:31.485956 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2075 11:45:31.492396 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2076 11:45:31.496035 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2077 11:45:31.496129 ==
2078 11:45:31.498776 Dram Type= 6, Freq= 0, CH_1, rank 1
2079 11:45:31.502457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2080 11:45:31.502532 ==
2081 11:45:31.502607 DQS Delay:
2082 11:45:31.505860 DQS0 = 0, DQS1 = 0
2083 11:45:31.505929 DQM Delay:
2084 11:45:31.508798 DQM0 = 86, DQM1 = 81
2085 11:45:31.508877 DQ Delay:
2086 11:45:31.512407 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2087 11:45:31.515547 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2088 11:45:31.519173 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2089 11:45:31.522613 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2090 11:45:31.522689
2091 11:45:31.522776
2092 11:45:31.532033 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2093 11:45:31.532122 CH1 RK1: MR19=606, MR18=1C38
2094 11:45:31.538725 CH1_RK1: MR19=0x606, MR18=0x1C38, DQSOSC=395, MR23=63, INC=94, DEC=63
2095 11:45:31.542388 [RxdqsGatingPostProcess] freq 800
2096 11:45:31.548714 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2097 11:45:31.552109 Pre-setting of DQS Precalculation
2098 11:45:31.555469 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2099 11:45:31.562539 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2100 11:45:31.572293 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2101 11:45:31.572375
2102 11:45:31.572458
2103 11:45:31.575541 [Calibration Summary] 1600 Mbps
2104 11:45:31.575624 CH 0, Rank 0
2105 11:45:31.578941 SW Impedance : PASS
2106 11:45:31.579038 DUTY Scan : NO K
2107 11:45:31.582322 ZQ Calibration : PASS
2108 11:45:31.582398 Jitter Meter : NO K
2109 11:45:31.585259 CBT Training : PASS
2110 11:45:31.588969 Write leveling : PASS
2111 11:45:31.589053 RX DQS gating : PASS
2112 11:45:31.591995 RX DQ/DQS(RDDQC) : PASS
2113 11:45:31.595227 TX DQ/DQS : PASS
2114 11:45:31.595303 RX DATLAT : PASS
2115 11:45:31.598495 RX DQ/DQS(Engine): PASS
2116 11:45:31.602472 TX OE : NO K
2117 11:45:31.602555 All Pass.
2118 11:45:31.602621
2119 11:45:31.602681 CH 0, Rank 1
2120 11:45:31.605279 SW Impedance : PASS
2121 11:45:31.608780 DUTY Scan : NO K
2122 11:45:31.608892 ZQ Calibration : PASS
2123 11:45:31.612236 Jitter Meter : NO K
2124 11:45:31.616015 CBT Training : PASS
2125 11:45:31.616116 Write leveling : PASS
2126 11:45:31.618657 RX DQS gating : PASS
2127 11:45:31.618740 RX DQ/DQS(RDDQC) : PASS
2128 11:45:31.622043 TX DQ/DQS : PASS
2129 11:45:31.625306 RX DATLAT : PASS
2130 11:45:31.625385 RX DQ/DQS(Engine): PASS
2131 11:45:31.628937 TX OE : NO K
2132 11:45:31.629017 All Pass.
2133 11:45:31.629098
2134 11:45:31.632030 CH 1, Rank 0
2135 11:45:31.632103 SW Impedance : PASS
2136 11:45:31.635330 DUTY Scan : NO K
2137 11:45:31.639242 ZQ Calibration : PASS
2138 11:45:31.639320 Jitter Meter : NO K
2139 11:45:31.642340 CBT Training : PASS
2140 11:45:31.645814 Write leveling : PASS
2141 11:45:31.645891 RX DQS gating : PASS
2142 11:45:31.648844 RX DQ/DQS(RDDQC) : PASS
2143 11:45:31.652450 TX DQ/DQS : PASS
2144 11:45:31.652610 RX DATLAT : PASS
2145 11:45:31.655708 RX DQ/DQS(Engine): PASS
2146 11:45:31.655779 TX OE : NO K
2147 11:45:31.659000 All Pass.
2148 11:45:31.659079
2149 11:45:31.659142 CH 1, Rank 1
2150 11:45:31.662248 SW Impedance : PASS
2151 11:45:31.662358 DUTY Scan : NO K
2152 11:45:31.665904 ZQ Calibration : PASS
2153 11:45:31.668881 Jitter Meter : NO K
2154 11:45:31.668952 CBT Training : PASS
2155 11:45:31.672234 Write leveling : PASS
2156 11:45:31.675805 RX DQS gating : PASS
2157 11:45:31.675883 RX DQ/DQS(RDDQC) : PASS
2158 11:45:31.678542 TX DQ/DQS : PASS
2159 11:45:31.682575 RX DATLAT : PASS
2160 11:45:31.682659 RX DQ/DQS(Engine): PASS
2161 11:45:31.685263 TX OE : NO K
2162 11:45:31.685343 All Pass.
2163 11:45:31.685419
2164 11:45:31.688822 DramC Write-DBI off
2165 11:45:31.692160 PER_BANK_REFRESH: Hybrid Mode
2166 11:45:31.692238 TX_TRACKING: ON
2167 11:45:31.695238 [GetDramInforAfterCalByMRR] Vendor 6.
2168 11:45:31.698479 [GetDramInforAfterCalByMRR] Revision 606.
2169 11:45:31.702065 [GetDramInforAfterCalByMRR] Revision 2 0.
2170 11:45:31.705381 MR0 0x3b3b
2171 11:45:31.705457 MR8 0x5151
2172 11:45:31.708645 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 11:45:31.708724
2174 11:45:31.711808 MR0 0x3b3b
2175 11:45:31.711890 MR8 0x5151
2176 11:45:31.715305 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2177 11:45:31.715390
2178 11:45:31.725160 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2179 11:45:31.728491 [FAST_K] Save calibration result to emmc
2180 11:45:31.732197 [FAST_K] Save calibration result to emmc
2181 11:45:31.735333 dram_init: config_dvfs: 1
2182 11:45:31.738906 dramc_set_vcore_voltage set vcore to 662500
2183 11:45:31.738979 Read voltage for 1200, 2
2184 11:45:31.741735 Vio18 = 0
2185 11:45:31.741809 Vcore = 662500
2186 11:45:31.741870 Vdram = 0
2187 11:45:31.745026 Vddq = 0
2188 11:45:31.745096 Vmddr = 0
2189 11:45:31.748304 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2190 11:45:31.755081 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2191 11:45:31.758100 MEM_TYPE=3, freq_sel=15
2192 11:45:31.761736 sv_algorithm_assistance_LP4_1600
2193 11:45:31.765056 ============ PULL DRAM RESETB DOWN ============
2194 11:45:31.768383 ========== PULL DRAM RESETB DOWN end =========
2195 11:45:31.774965 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2196 11:45:31.775040 ===================================
2197 11:45:31.778657 LPDDR4 DRAM CONFIGURATION
2198 11:45:31.781396 ===================================
2199 11:45:31.784846 EX_ROW_EN[0] = 0x0
2200 11:45:31.784919 EX_ROW_EN[1] = 0x0
2201 11:45:31.788255 LP4Y_EN = 0x0
2202 11:45:31.788332 WORK_FSP = 0x0
2203 11:45:31.792136 WL = 0x4
2204 11:45:31.792206 RL = 0x4
2205 11:45:31.795277 BL = 0x2
2206 11:45:31.795347 RPST = 0x0
2207 11:45:31.798042 RD_PRE = 0x0
2208 11:45:31.801447 WR_PRE = 0x1
2209 11:45:31.801521 WR_PST = 0x0
2210 11:45:31.804994 DBI_WR = 0x0
2211 11:45:31.805067 DBI_RD = 0x0
2212 11:45:31.808523 OTF = 0x1
2213 11:45:31.811802 ===================================
2214 11:45:31.814683 ===================================
2215 11:45:31.814755 ANA top config
2216 11:45:31.818478 ===================================
2217 11:45:31.821525 DLL_ASYNC_EN = 0
2218 11:45:31.824985 ALL_SLAVE_EN = 0
2219 11:45:31.825053 NEW_RANK_MODE = 1
2220 11:45:31.828160 DLL_IDLE_MODE = 1
2221 11:45:31.831222 LP45_APHY_COMB_EN = 1
2222 11:45:31.834575 TX_ODT_DIS = 1
2223 11:45:31.834650 NEW_8X_MODE = 1
2224 11:45:31.838118 ===================================
2225 11:45:31.841762 ===================================
2226 11:45:31.844736 data_rate = 2400
2227 11:45:31.848033 CKR = 1
2228 11:45:31.851428 DQ_P2S_RATIO = 8
2229 11:45:31.854696 ===================================
2230 11:45:31.858962 CA_P2S_RATIO = 8
2231 11:45:31.861509 DQ_CA_OPEN = 0
2232 11:45:31.861582 DQ_SEMI_OPEN = 0
2233 11:45:31.864793 CA_SEMI_OPEN = 0
2234 11:45:31.868069 CA_FULL_RATE = 0
2235 11:45:31.871430 DQ_CKDIV4_EN = 0
2236 11:45:31.874822 CA_CKDIV4_EN = 0
2237 11:45:31.878217 CA_PREDIV_EN = 0
2238 11:45:31.878321 PH8_DLY = 17
2239 11:45:31.881324 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2240 11:45:31.884554 DQ_AAMCK_DIV = 4
2241 11:45:31.887998 CA_AAMCK_DIV = 4
2242 11:45:31.891298 CA_ADMCK_DIV = 4
2243 11:45:31.894708 DQ_TRACK_CA_EN = 0
2244 11:45:31.894782 CA_PICK = 1200
2245 11:45:31.897758 CA_MCKIO = 1200
2246 11:45:31.901132 MCKIO_SEMI = 0
2247 11:45:31.904637 PLL_FREQ = 2366
2248 11:45:31.908149 DQ_UI_PI_RATIO = 32
2249 11:45:31.911279 CA_UI_PI_RATIO = 0
2250 11:45:31.914834 ===================================
2251 11:45:31.918094 ===================================
2252 11:45:31.921449 memory_type:LPDDR4
2253 11:45:31.921522 GP_NUM : 10
2254 11:45:31.924682 SRAM_EN : 1
2255 11:45:31.924754 MD32_EN : 0
2256 11:45:31.927549 ===================================
2257 11:45:31.931087 [ANA_INIT] >>>>>>>>>>>>>>
2258 11:45:31.934387 <<<<<< [CONFIGURE PHASE]: ANA_TX
2259 11:45:31.937718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2260 11:45:31.940710 ===================================
2261 11:45:31.944109 data_rate = 2400,PCW = 0X5b00
2262 11:45:31.947443 ===================================
2263 11:45:31.951064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2264 11:45:31.954168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2265 11:45:31.960781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2266 11:45:31.967574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2267 11:45:31.970813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2268 11:45:31.974109 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2269 11:45:31.974211 [ANA_INIT] flow start
2270 11:45:31.977455 [ANA_INIT] PLL >>>>>>>>
2271 11:45:31.981112 [ANA_INIT] PLL <<<<<<<<
2272 11:45:31.981190 [ANA_INIT] MIDPI >>>>>>>>
2273 11:45:31.984426 [ANA_INIT] MIDPI <<<<<<<<
2274 11:45:31.987247 [ANA_INIT] DLL >>>>>>>>
2275 11:45:31.987347 [ANA_INIT] DLL <<<<<<<<
2276 11:45:31.990801 [ANA_INIT] flow end
2277 11:45:31.994040 ============ LP4 DIFF to SE enter ============
2278 11:45:31.997462 ============ LP4 DIFF to SE exit ============
2279 11:45:32.000965 [ANA_INIT] <<<<<<<<<<<<<
2280 11:45:32.003736 [Flow] Enable top DCM control >>>>>
2281 11:45:32.007367 [Flow] Enable top DCM control <<<<<
2282 11:45:32.010316 Enable DLL master slave shuffle
2283 11:45:32.016832 ==============================================================
2284 11:45:32.016923 Gating Mode config
2285 11:45:32.023776 ==============================================================
2286 11:45:32.026696 Config description:
2287 11:45:32.033608 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2288 11:45:32.040146 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2289 11:45:32.046712 SELPH_MODE 0: By rank 1: By Phase
2290 11:45:32.053684 ==============================================================
2291 11:45:32.056696 GAT_TRACK_EN = 1
2292 11:45:32.056780 RX_GATING_MODE = 2
2293 11:45:32.060304 RX_GATING_TRACK_MODE = 2
2294 11:45:32.063325 SELPH_MODE = 1
2295 11:45:32.066710 PICG_EARLY_EN = 1
2296 11:45:32.070133 VALID_LAT_VALUE = 1
2297 11:45:32.077527 ==============================================================
2298 11:45:32.079797 Enter into Gating configuration >>>>
2299 11:45:32.083180 Exit from Gating configuration <<<<
2300 11:45:32.086823 Enter into DVFS_PRE_config >>>>>
2301 11:45:32.096524 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2302 11:45:32.099588 Exit from DVFS_PRE_config <<<<<
2303 11:45:32.103056 Enter into PICG configuration >>>>
2304 11:45:32.106669 Exit from PICG configuration <<<<
2305 11:45:32.109582 [RX_INPUT] configuration >>>>>
2306 11:45:32.113145 [RX_INPUT] configuration <<<<<
2307 11:45:32.116487 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2308 11:45:32.122898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2309 11:45:32.129177 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2310 11:45:32.132557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2311 11:45:32.139220 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2312 11:45:32.146056 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2313 11:45:32.149572 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2314 11:45:32.156076 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2315 11:45:32.159192 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2316 11:45:32.162648 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2317 11:45:32.166044 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2318 11:45:32.172183 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2319 11:45:32.175634 ===================================
2320 11:45:32.175717 LPDDR4 DRAM CONFIGURATION
2321 11:45:32.178980 ===================================
2322 11:45:32.182240 EX_ROW_EN[0] = 0x0
2323 11:45:32.185794 EX_ROW_EN[1] = 0x0
2324 11:45:32.185876 LP4Y_EN = 0x0
2325 11:45:32.188918 WORK_FSP = 0x0
2326 11:45:32.189026 WL = 0x4
2327 11:45:32.192134 RL = 0x4
2328 11:45:32.192218 BL = 0x2
2329 11:45:32.195702 RPST = 0x0
2330 11:45:32.195792 RD_PRE = 0x0
2331 11:45:32.199364 WR_PRE = 0x1
2332 11:45:32.199444 WR_PST = 0x0
2333 11:45:32.202410 DBI_WR = 0x0
2334 11:45:32.202496 DBI_RD = 0x0
2335 11:45:32.205545 OTF = 0x1
2336 11:45:32.208842 ===================================
2337 11:45:32.212382 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2338 11:45:32.215836 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2339 11:45:32.221731 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2340 11:45:32.225165 ===================================
2341 11:45:32.225250 LPDDR4 DRAM CONFIGURATION
2342 11:45:32.228709 ===================================
2343 11:45:32.232097 EX_ROW_EN[0] = 0x10
2344 11:45:32.234982 EX_ROW_EN[1] = 0x0
2345 11:45:32.235055 LP4Y_EN = 0x0
2346 11:45:32.238644 WORK_FSP = 0x0
2347 11:45:32.238715 WL = 0x4
2348 11:45:32.242146 RL = 0x4
2349 11:45:32.242267 BL = 0x2
2350 11:45:32.245247 RPST = 0x0
2351 11:45:32.245356 RD_PRE = 0x0
2352 11:45:32.248798 WR_PRE = 0x1
2353 11:45:32.248884 WR_PST = 0x0
2354 11:45:32.251870 DBI_WR = 0x0
2355 11:45:32.251951 DBI_RD = 0x0
2356 11:45:32.255573 OTF = 0x1
2357 11:45:32.258369 ===================================
2358 11:45:32.265343 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2359 11:45:32.265458 ==
2360 11:45:32.268333 Dram Type= 6, Freq= 0, CH_0, rank 0
2361 11:45:32.271951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2362 11:45:32.272062 ==
2363 11:45:32.275208 [Duty_Offset_Calibration]
2364 11:45:32.275314 B0:2 B1:0 CA:4
2365 11:45:32.275417
2366 11:45:32.278559 [DutyScan_Calibration_Flow] k_type=0
2367 11:45:32.288696
2368 11:45:32.288802 ==CLK 0==
2369 11:45:32.292058 Final CLK duty delay cell = 0
2370 11:45:32.295777 [0] MAX Duty = 5156%(X100), DQS PI = 14
2371 11:45:32.298307 [0] MIN Duty = 4969%(X100), DQS PI = 8
2372 11:45:32.298383 [0] AVG Duty = 5062%(X100)
2373 11:45:32.301928
2374 11:45:32.305185 CH0 CLK Duty spec in!! Max-Min= 187%
2375 11:45:32.308521 [DutyScan_Calibration_Flow] ====Done====
2376 11:45:32.308595
2377 11:45:32.311725 [DutyScan_Calibration_Flow] k_type=1
2378 11:45:32.328184
2379 11:45:32.328264 ==DQS 0 ==
2380 11:45:32.330992 Final DQS duty delay cell = 0
2381 11:45:32.334381 [0] MAX Duty = 5156%(X100), DQS PI = 16
2382 11:45:32.337798 [0] MIN Duty = 5093%(X100), DQS PI = 0
2383 11:45:32.337867 [0] AVG Duty = 5124%(X100)
2384 11:45:32.341231
2385 11:45:32.341304 ==DQS 1 ==
2386 11:45:32.344406 Final DQS duty delay cell = 0
2387 11:45:32.347804 [0] MAX Duty = 5125%(X100), DQS PI = 48
2388 11:45:32.351186 [0] MIN Duty = 5000%(X100), DQS PI = 0
2389 11:45:32.354066 [0] AVG Duty = 5062%(X100)
2390 11:45:32.354136
2391 11:45:32.357782 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2392 11:45:32.357854
2393 11:45:32.361710 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2394 11:45:32.364524 [DutyScan_Calibration_Flow] ====Done====
2395 11:45:32.364599
2396 11:45:32.367519 [DutyScan_Calibration_Flow] k_type=3
2397 11:45:32.384718
2398 11:45:32.384834 ==DQM 0 ==
2399 11:45:32.387599 Final DQM duty delay cell = 0
2400 11:45:32.390735 [0] MAX Duty = 5125%(X100), DQS PI = 20
2401 11:45:32.394033 [0] MIN Duty = 4844%(X100), DQS PI = 52
2402 11:45:32.397192 [0] AVG Duty = 4984%(X100)
2403 11:45:32.397271
2404 11:45:32.397332 ==DQM 1 ==
2405 11:45:32.400745 Final DQM duty delay cell = 0
2406 11:45:32.404472 [0] MAX Duty = 5000%(X100), DQS PI = 6
2407 11:45:32.407259 [0] MIN Duty = 4875%(X100), DQS PI = 20
2408 11:45:32.410639 [0] AVG Duty = 4937%(X100)
2409 11:45:32.410714
2410 11:45:32.414168 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2411 11:45:32.414273
2412 11:45:32.417674 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2413 11:45:32.420746 [DutyScan_Calibration_Flow] ====Done====
2414 11:45:32.420849
2415 11:45:32.423641 [DutyScan_Calibration_Flow] k_type=2
2416 11:45:32.440764
2417 11:45:32.440878 ==DQ 0 ==
2418 11:45:32.443963 Final DQ duty delay cell = 0
2419 11:45:32.447505 [0] MAX Duty = 5125%(X100), DQS PI = 18
2420 11:45:32.450715 [0] MIN Duty = 5000%(X100), DQS PI = 8
2421 11:45:32.450786 [0] AVG Duty = 5062%(X100)
2422 11:45:32.450848
2423 11:45:32.454469 ==DQ 1 ==
2424 11:45:32.457365 Final DQ duty delay cell = 0
2425 11:45:32.460751 [0] MAX Duty = 5156%(X100), DQS PI = 4
2426 11:45:32.463953 [0] MIN Duty = 4938%(X100), DQS PI = 14
2427 11:45:32.464035 [0] AVG Duty = 5047%(X100)
2428 11:45:32.464127
2429 11:45:32.467204 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2430 11:45:32.470609
2431 11:45:32.474231 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2432 11:45:32.477684 [DutyScan_Calibration_Flow] ====Done====
2433 11:45:32.477771 ==
2434 11:45:32.480707 Dram Type= 6, Freq= 0, CH_1, rank 0
2435 11:45:32.484147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2436 11:45:32.484255 ==
2437 11:45:32.487256 [Duty_Offset_Calibration]
2438 11:45:32.487365 B0:0 B1:-1 CA:3
2439 11:45:32.487460
2440 11:45:32.490652 [DutyScan_Calibration_Flow] k_type=0
2441 11:45:32.499804
2442 11:45:32.499918 ==CLK 0==
2443 11:45:32.503210 Final CLK duty delay cell = -4
2444 11:45:32.506264 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2445 11:45:32.509657 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2446 11:45:32.513169 [-4] AVG Duty = 4938%(X100)
2447 11:45:32.513275
2448 11:45:32.516529 CH1 CLK Duty spec in!! Max-Min= 124%
2449 11:45:32.519737 [DutyScan_Calibration_Flow] ====Done====
2450 11:45:32.519808
2451 11:45:32.523259 [DutyScan_Calibration_Flow] k_type=1
2452 11:45:32.538935
2453 11:45:32.539015 ==DQS 0 ==
2454 11:45:32.542195 Final DQS duty delay cell = 0
2455 11:45:32.545442 [0] MAX Duty = 5187%(X100), DQS PI = 28
2456 11:45:32.548556 [0] MIN Duty = 4907%(X100), DQS PI = 38
2457 11:45:32.552284 [0] AVG Duty = 5047%(X100)
2458 11:45:32.552366
2459 11:45:32.552430 ==DQS 1 ==
2460 11:45:32.555284 Final DQS duty delay cell = -4
2461 11:45:32.558455 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2462 11:45:32.562173 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2463 11:45:32.565804 [-4] AVG Duty = 4937%(X100)
2464 11:45:32.565885
2465 11:45:32.568755 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2466 11:45:32.568836
2467 11:45:32.572535 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2468 11:45:32.575078 [DutyScan_Calibration_Flow] ====Done====
2469 11:45:32.575159
2470 11:45:32.578576 [DutyScan_Calibration_Flow] k_type=3
2471 11:45:32.595607
2472 11:45:32.595763 ==DQM 0 ==
2473 11:45:32.598866 Final DQM duty delay cell = 0
2474 11:45:32.602575 [0] MAX Duty = 5031%(X100), DQS PI = 26
2475 11:45:32.605817 [0] MIN Duty = 4782%(X100), DQS PI = 38
2476 11:45:32.605916 [0] AVG Duty = 4906%(X100)
2477 11:45:32.608746
2478 11:45:32.608832 ==DQM 1 ==
2479 11:45:32.612406 Final DQM duty delay cell = 0
2480 11:45:32.615351 [0] MAX Duty = 5000%(X100), DQS PI = 36
2481 11:45:32.618764 [0] MIN Duty = 4844%(X100), DQS PI = 0
2482 11:45:32.622443 [0] AVG Duty = 4922%(X100)
2483 11:45:32.622517
2484 11:45:32.625773 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2485 11:45:32.625848
2486 11:45:32.628492 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2487 11:45:32.631965 [DutyScan_Calibration_Flow] ====Done====
2488 11:45:32.632039
2489 11:45:32.635196 [DutyScan_Calibration_Flow] k_type=2
2490 11:45:32.651416
2491 11:45:32.651497 ==DQ 0 ==
2492 11:45:32.654734 Final DQ duty delay cell = -4
2493 11:45:32.657933 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2494 11:45:32.661240 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2495 11:45:32.664440 [-4] AVG Duty = 4922%(X100)
2496 11:45:32.664521
2497 11:45:32.664590 ==DQ 1 ==
2498 11:45:32.667725 Final DQ duty delay cell = 0
2499 11:45:32.671109 [0] MAX Duty = 5031%(X100), DQS PI = 32
2500 11:45:32.674788 [0] MIN Duty = 4844%(X100), DQS PI = 0
2501 11:45:32.677621 [0] AVG Duty = 4937%(X100)
2502 11:45:32.677722
2503 11:45:32.680973 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2504 11:45:32.681055
2505 11:45:32.684331 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2506 11:45:32.687714 [DutyScan_Calibration_Flow] ====Done====
2507 11:45:32.691290 nWR fixed to 30
2508 11:45:32.694622 [ModeRegInit_LP4] CH0 RK0
2509 11:45:32.694705 [ModeRegInit_LP4] CH0 RK1
2510 11:45:32.697534 [ModeRegInit_LP4] CH1 RK0
2511 11:45:32.700877 [ModeRegInit_LP4] CH1 RK1
2512 11:45:32.700950 match AC timing 7
2513 11:45:32.707811 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2514 11:45:32.711410 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2515 11:45:32.714301 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2516 11:45:32.720906 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2517 11:45:32.724432 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2518 11:45:32.724510 ==
2519 11:45:32.727880 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 11:45:32.730733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 11:45:32.730812 ==
2522 11:45:32.737603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2523 11:45:32.744238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2524 11:45:32.751303 [CA 0] Center 39 (9~70) winsize 62
2525 11:45:32.754895 [CA 1] Center 38 (8~69) winsize 62
2526 11:45:32.758085 [CA 2] Center 35 (5~66) winsize 62
2527 11:45:32.761555 [CA 3] Center 35 (5~66) winsize 62
2528 11:45:32.765120 [CA 4] Center 33 (3~64) winsize 62
2529 11:45:32.767980 [CA 5] Center 33 (3~63) winsize 61
2530 11:45:32.768052
2531 11:45:32.771585 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2532 11:45:32.771656
2533 11:45:32.775216 [CATrainingPosCal] consider 1 rank data
2534 11:45:32.778247 u2DelayCellTimex100 = 270/100 ps
2535 11:45:32.781387 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2536 11:45:32.787726 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2537 11:45:32.791231 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2538 11:45:32.794953 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2539 11:45:32.798160 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2540 11:45:32.801300 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2541 11:45:32.801381
2542 11:45:32.804588 CA PerBit enable=1, Macro0, CA PI delay=33
2543 11:45:32.804669
2544 11:45:32.808004 [CBTSetCACLKResult] CA Dly = 33
2545 11:45:32.808084 CS Dly: 7 (0~38)
2546 11:45:32.811563 ==
2547 11:45:32.814393 Dram Type= 6, Freq= 0, CH_0, rank 1
2548 11:45:32.817867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2549 11:45:32.817973 ==
2550 11:45:32.821328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2551 11:45:32.827810 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2552 11:45:32.837443 [CA 0] Center 39 (9~70) winsize 62
2553 11:45:32.840538 [CA 1] Center 39 (9~70) winsize 62
2554 11:45:32.843831 [CA 2] Center 35 (5~66) winsize 62
2555 11:45:32.846871 [CA 3] Center 35 (5~66) winsize 62
2556 11:45:32.850224 [CA 4] Center 34 (4~65) winsize 62
2557 11:45:32.853693 [CA 5] Center 33 (3~64) winsize 62
2558 11:45:32.853859
2559 11:45:32.857002 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2560 11:45:32.857072
2561 11:45:32.860172 [CATrainingPosCal] consider 2 rank data
2562 11:45:32.863696 u2DelayCellTimex100 = 270/100 ps
2563 11:45:32.866975 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2564 11:45:32.873570 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2565 11:45:32.877365 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2566 11:45:32.880127 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2567 11:45:32.883572 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2568 11:45:32.886836 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2569 11:45:32.886944
2570 11:45:32.890140 CA PerBit enable=1, Macro0, CA PI delay=33
2571 11:45:32.890240
2572 11:45:32.893689 [CBTSetCACLKResult] CA Dly = 33
2573 11:45:32.893791 CS Dly: 8 (0~41)
2574 11:45:32.896860
2575 11:45:32.900179 ----->DramcWriteLeveling(PI) begin...
2576 11:45:32.900255 ==
2577 11:45:32.903317 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 11:45:32.907489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 11:45:32.907564 ==
2580 11:45:32.910388 Write leveling (Byte 0): 31 => 31
2581 11:45:32.913754 Write leveling (Byte 1): 27 => 27
2582 11:45:32.916683 DramcWriteLeveling(PI) end<-----
2583 11:45:32.916756
2584 11:45:32.916818 ==
2585 11:45:32.919985 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 11:45:32.923708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 11:45:32.923779 ==
2588 11:45:32.926846 [Gating] SW mode calibration
2589 11:45:32.933183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2590 11:45:32.940082 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2591 11:45:32.943604 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2592 11:45:32.946954 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2593 11:45:32.953395 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 11:45:32.956343 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 11:45:32.959716 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 11:45:32.966282 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 11:45:32.969831 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2598 11:45:32.973108 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2599 11:45:32.979729 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2600 11:45:32.983189 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 11:45:32.985967 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 11:45:32.993255 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 11:45:32.996320 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 11:45:32.999548 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 11:45:33.006425 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2606 11:45:33.009411 1 0 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
2607 11:45:33.012695 1 1 0 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2608 11:45:33.016129 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2609 11:45:33.023002 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 11:45:33.026833 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 11:45:33.029386 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 11:45:33.035888 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 11:45:33.039442 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2614 11:45:33.042668 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2615 11:45:33.048989 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2616 11:45:33.052308 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 11:45:33.055894 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:45:33.063209 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:45:33.065802 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:45:33.069197 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:45:33.076444 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:45:33.079495 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:45:33.082638 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 11:45:33.089261 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:45:33.092720 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:45:33.096178 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 11:45:33.102466 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:45:33.105957 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:45:33.109085 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2630 11:45:33.115822 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2631 11:45:33.115896 Total UI for P1: 0, mck2ui 16
2632 11:45:33.122380 best dqsien dly found for B0: ( 1, 3, 24)
2633 11:45:33.125893 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2634 11:45:33.129322 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 11:45:33.132575 Total UI for P1: 0, mck2ui 16
2636 11:45:33.135663 best dqsien dly found for B1: ( 1, 3, 30)
2637 11:45:33.139363 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2638 11:45:33.142394 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2639 11:45:33.142464
2640 11:45:33.145764 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2641 11:45:33.152138 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2642 11:45:33.152211 [Gating] SW calibration Done
2643 11:45:33.152273 ==
2644 11:45:33.155633 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 11:45:33.162481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 11:45:33.162553 ==
2647 11:45:33.162612 RX Vref Scan: 0
2648 11:45:33.162668
2649 11:45:33.165444 RX Vref 0 -> 0, step: 1
2650 11:45:33.165507
2651 11:45:33.168357 RX Delay -40 -> 252, step: 8
2652 11:45:33.171778 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2653 11:45:33.175290 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2654 11:45:33.178520 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2655 11:45:33.185523 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2656 11:45:33.188457 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2657 11:45:33.191906 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2658 11:45:33.195047 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2659 11:45:33.198578 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2660 11:45:33.205370 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2661 11:45:33.208713 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2662 11:45:33.211779 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2663 11:45:33.215185 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2664 11:45:33.218690 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2665 11:45:33.224981 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2666 11:45:33.228545 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2667 11:45:33.231903 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2668 11:45:33.231978 ==
2669 11:45:33.235215 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 11:45:33.238710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 11:45:33.242201 ==
2672 11:45:33.242308 DQS Delay:
2673 11:45:33.242370 DQS0 = 0, DQS1 = 0
2674 11:45:33.245447 DQM Delay:
2675 11:45:33.245522 DQM0 = 120, DQM1 = 107
2676 11:45:33.248637 DQ Delay:
2677 11:45:33.251426 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2678 11:45:33.255132 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2679 11:45:33.257996 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2680 11:45:33.261470 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2681 11:45:33.261538
2682 11:45:33.261619
2683 11:45:33.261677 ==
2684 11:45:33.264937 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 11:45:33.268684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 11:45:33.268751 ==
2687 11:45:33.268810
2688 11:45:33.268866
2689 11:45:33.271402 TX Vref Scan disable
2690 11:45:33.275084 == TX Byte 0 ==
2691 11:45:33.278427 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2692 11:45:33.281363 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2693 11:45:33.284908 == TX Byte 1 ==
2694 11:45:33.288134 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2695 11:45:33.291565 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2696 11:45:33.291639 ==
2697 11:45:33.294975 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 11:45:33.301121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 11:45:33.301196 ==
2700 11:45:33.311982 TX Vref=22, minBit 3, minWin=24, winSum=406
2701 11:45:33.315011 TX Vref=24, minBit 10, minWin=25, winSum=419
2702 11:45:33.318489 TX Vref=26, minBit 0, minWin=26, winSum=427
2703 11:45:33.321915 TX Vref=28, minBit 4, minWin=25, winSum=422
2704 11:45:33.325398 TX Vref=30, minBit 1, minWin=26, winSum=426
2705 11:45:33.331797 TX Vref=32, minBit 4, minWin=26, winSum=426
2706 11:45:33.335254 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
2707 11:45:33.335328
2708 11:45:33.338608 Final TX Range 1 Vref 26
2709 11:45:33.338704
2710 11:45:33.338768 ==
2711 11:45:33.341616 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 11:45:33.344963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 11:45:33.348135 ==
2714 11:45:33.348236
2715 11:45:33.348296
2716 11:45:33.348358 TX Vref Scan disable
2717 11:45:33.351894 == TX Byte 0 ==
2718 11:45:33.354893 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2719 11:45:33.361801 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2720 11:45:33.361916 == TX Byte 1 ==
2721 11:45:33.365091 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2722 11:45:33.371748 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2723 11:45:33.371825
2724 11:45:33.371888 [DATLAT]
2725 11:45:33.371946 Freq=1200, CH0 RK0
2726 11:45:33.372003
2727 11:45:33.375285 DATLAT Default: 0xd
2728 11:45:33.375353 0, 0xFFFF, sum = 0
2729 11:45:33.378805 1, 0xFFFF, sum = 0
2730 11:45:33.378885 2, 0xFFFF, sum = 0
2731 11:45:33.381934 3, 0xFFFF, sum = 0
2732 11:45:33.382004 4, 0xFFFF, sum = 0
2733 11:45:33.385478 5, 0xFFFF, sum = 0
2734 11:45:33.388156 6, 0xFFFF, sum = 0
2735 11:45:33.388226 7, 0xFFFF, sum = 0
2736 11:45:33.391647 8, 0xFFFF, sum = 0
2737 11:45:33.391720 9, 0xFFFF, sum = 0
2738 11:45:33.395209 10, 0xFFFF, sum = 0
2739 11:45:33.395286 11, 0xFFFF, sum = 0
2740 11:45:33.398724 12, 0x0, sum = 1
2741 11:45:33.398802 13, 0x0, sum = 2
2742 11:45:33.401871 14, 0x0, sum = 3
2743 11:45:33.401943 15, 0x0, sum = 4
2744 11:45:33.402003 best_step = 13
2745 11:45:33.402072
2746 11:45:33.404844 ==
2747 11:45:33.408239 Dram Type= 6, Freq= 0, CH_0, rank 0
2748 11:45:33.411741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2749 11:45:33.411814 ==
2750 11:45:33.411874 RX Vref Scan: 1
2751 11:45:33.411931
2752 11:45:33.414861 Set Vref Range= 32 -> 127
2753 11:45:33.414933
2754 11:45:33.418274 RX Vref 32 -> 127, step: 1
2755 11:45:33.418358
2756 11:45:33.421836 RX Delay -21 -> 252, step: 4
2757 11:45:33.421936
2758 11:45:33.424672 Set Vref, RX VrefLevel [Byte0]: 32
2759 11:45:33.428190 [Byte1]: 32
2760 11:45:33.428261
2761 11:45:33.431687 Set Vref, RX VrefLevel [Byte0]: 33
2762 11:45:33.434713 [Byte1]: 33
2763 11:45:33.438350
2764 11:45:33.438422 Set Vref, RX VrefLevel [Byte0]: 34
2765 11:45:33.441541 [Byte1]: 34
2766 11:45:33.446155
2767 11:45:33.446287 Set Vref, RX VrefLevel [Byte0]: 35
2768 11:45:33.449622 [Byte1]: 35
2769 11:45:33.454193
2770 11:45:33.454314 Set Vref, RX VrefLevel [Byte0]: 36
2771 11:45:33.457118 [Byte1]: 36
2772 11:45:33.462081
2773 11:45:33.462152 Set Vref, RX VrefLevel [Byte0]: 37
2774 11:45:33.465579 [Byte1]: 37
2775 11:45:33.470102
2776 11:45:33.470174 Set Vref, RX VrefLevel [Byte0]: 38
2777 11:45:33.473167 [Byte1]: 38
2778 11:45:33.477854
2779 11:45:33.477927 Set Vref, RX VrefLevel [Byte0]: 39
2780 11:45:33.481378 [Byte1]: 39
2781 11:45:33.486032
2782 11:45:33.486136 Set Vref, RX VrefLevel [Byte0]: 40
2783 11:45:33.489465 [Byte1]: 40
2784 11:45:33.493555
2785 11:45:33.493653 Set Vref, RX VrefLevel [Byte0]: 41
2786 11:45:33.497256 [Byte1]: 41
2787 11:45:33.501996
2788 11:45:33.502095 Set Vref, RX VrefLevel [Byte0]: 42
2789 11:45:33.504885 [Byte1]: 42
2790 11:45:33.510032
2791 11:45:33.510132 Set Vref, RX VrefLevel [Byte0]: 43
2792 11:45:33.512718 [Byte1]: 43
2793 11:45:33.517468
2794 11:45:33.517543 Set Vref, RX VrefLevel [Byte0]: 44
2795 11:45:33.520950 [Byte1]: 44
2796 11:45:33.525590
2797 11:45:33.525686 Set Vref, RX VrefLevel [Byte0]: 45
2798 11:45:33.528355 [Byte1]: 45
2799 11:45:33.533145
2800 11:45:33.533214 Set Vref, RX VrefLevel [Byte0]: 46
2801 11:45:33.536580 [Byte1]: 46
2802 11:45:33.541123
2803 11:45:33.541193 Set Vref, RX VrefLevel [Byte0]: 47
2804 11:45:33.544613 [Byte1]: 47
2805 11:45:33.549157
2806 11:45:33.549235 Set Vref, RX VrefLevel [Byte0]: 48
2807 11:45:33.552651 [Byte1]: 48
2808 11:45:33.557559
2809 11:45:33.557631 Set Vref, RX VrefLevel [Byte0]: 49
2810 11:45:33.560492 [Byte1]: 49
2811 11:45:33.564812
2812 11:45:33.564881 Set Vref, RX VrefLevel [Byte0]: 50
2813 11:45:33.568281 [Byte1]: 50
2814 11:45:33.572971
2815 11:45:33.573066 Set Vref, RX VrefLevel [Byte0]: 51
2816 11:45:33.576102 [Byte1]: 51
2817 11:45:33.581210
2818 11:45:33.581281 Set Vref, RX VrefLevel [Byte0]: 52
2819 11:45:33.584587 [Byte1]: 52
2820 11:45:33.588791
2821 11:45:33.588862 Set Vref, RX VrefLevel [Byte0]: 53
2822 11:45:33.591971 [Byte1]: 53
2823 11:45:33.596545
2824 11:45:33.596622 Set Vref, RX VrefLevel [Byte0]: 54
2825 11:45:33.600121 [Byte1]: 54
2826 11:45:33.604574
2827 11:45:33.604646 Set Vref, RX VrefLevel [Byte0]: 55
2828 11:45:33.608117 [Byte1]: 55
2829 11:45:33.612506
2830 11:45:33.612597 Set Vref, RX VrefLevel [Byte0]: 56
2831 11:45:33.616139 [Byte1]: 56
2832 11:45:33.620438
2833 11:45:33.620509 Set Vref, RX VrefLevel [Byte0]: 57
2834 11:45:33.623568 [Byte1]: 57
2835 11:45:33.628208
2836 11:45:33.628278 Set Vref, RX VrefLevel [Byte0]: 58
2837 11:45:33.632083 [Byte1]: 58
2838 11:45:33.636474
2839 11:45:33.636553 Set Vref, RX VrefLevel [Byte0]: 59
2840 11:45:33.639447 [Byte1]: 59
2841 11:45:33.644429
2842 11:45:33.644502 Set Vref, RX VrefLevel [Byte0]: 60
2843 11:45:33.647550 [Byte1]: 60
2844 11:45:33.652437
2845 11:45:33.652538 Set Vref, RX VrefLevel [Byte0]: 61
2846 11:45:33.655262 [Byte1]: 61
2847 11:45:33.660208
2848 11:45:33.660280 Set Vref, RX VrefLevel [Byte0]: 62
2849 11:45:33.663327 [Byte1]: 62
2850 11:45:33.667917
2851 11:45:33.667988 Set Vref, RX VrefLevel [Byte0]: 63
2852 11:45:33.671171 [Byte1]: 63
2853 11:45:33.676090
2854 11:45:33.676162 Set Vref, RX VrefLevel [Byte0]: 64
2855 11:45:33.679634 [Byte1]: 64
2856 11:45:33.684337
2857 11:45:33.684413 Set Vref, RX VrefLevel [Byte0]: 65
2858 11:45:33.687556 [Byte1]: 65
2859 11:45:33.691425
2860 11:45:33.695209 Set Vref, RX VrefLevel [Byte0]: 66
2861 11:45:33.698483 [Byte1]: 66
2862 11:45:33.698554
2863 11:45:33.701432 Set Vref, RX VrefLevel [Byte0]: 67
2864 11:45:33.705019 [Byte1]: 67
2865 11:45:33.705085
2866 11:45:33.708356 Final RX Vref Byte 0 = 56 to rank0
2867 11:45:33.711255 Final RX Vref Byte 1 = 50 to rank0
2868 11:45:33.714787 Final RX Vref Byte 0 = 56 to rank1
2869 11:45:33.718197 Final RX Vref Byte 1 = 50 to rank1==
2870 11:45:33.721714 Dram Type= 6, Freq= 0, CH_0, rank 0
2871 11:45:33.724667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 11:45:33.724761 ==
2873 11:45:33.728144 DQS Delay:
2874 11:45:33.728212 DQS0 = 0, DQS1 = 0
2875 11:45:33.731536 DQM Delay:
2876 11:45:33.731605 DQM0 = 119, DQM1 = 106
2877 11:45:33.734712 DQ Delay:
2878 11:45:33.738223 DQ0 =120, DQ1 =118, DQ2 =116, DQ3 =116
2879 11:45:33.741321 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2880 11:45:33.744648 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =100
2881 11:45:33.748030 DQ12 =116, DQ13 =110, DQ14 =116, DQ15 =114
2882 11:45:33.748104
2883 11:45:33.748165
2884 11:45:33.755104 [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2885 11:45:33.757791 CH0 RK0: MR19=403, MR18=4FF
2886 11:45:33.764549 CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2887 11:45:33.764621
2888 11:45:33.767834 ----->DramcWriteLeveling(PI) begin...
2889 11:45:33.767906 ==
2890 11:45:33.771415 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 11:45:33.774410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 11:45:33.774493 ==
2893 11:45:33.778169 Write leveling (Byte 0): 32 => 32
2894 11:45:33.780921 Write leveling (Byte 1): 27 => 27
2895 11:45:33.784208 DramcWriteLeveling(PI) end<-----
2896 11:45:33.784314
2897 11:45:33.784451 ==
2898 11:45:33.787610 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 11:45:33.790913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 11:45:33.794455 ==
2901 11:45:33.794529 [Gating] SW mode calibration
2902 11:45:33.804606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2903 11:45:33.808136 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2904 11:45:33.810819 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2905 11:45:33.817355 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2906 11:45:33.821203 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 11:45:33.823928 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 11:45:33.830635 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 11:45:33.834169 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 11:45:33.837275 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2911 11:45:33.844367 0 15 28 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
2912 11:45:33.847427 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2913 11:45:33.850499 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 11:45:33.857012 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 11:45:33.860264 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 11:45:33.863744 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 11:45:33.870135 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 11:45:33.873725 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
2919 11:45:33.877435 1 0 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
2920 11:45:33.883489 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 11:45:33.886902 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:45:33.890215 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 11:45:33.896918 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 11:45:33.900010 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 11:45:33.903412 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 11:45:33.910332 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2927 11:45:33.913437 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2928 11:45:33.916564 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:45:33.923385 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:45:33.926470 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:45:33.929972 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:45:33.936777 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:45:33.939695 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:45:33.943344 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:45:33.949663 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:45:33.953330 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:45:33.956653 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:45:33.963166 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:45:33.966570 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 11:45:33.969867 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 11:45:33.976373 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 11:45:33.979929 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2943 11:45:33.983189 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2944 11:45:33.986221 Total UI for P1: 0, mck2ui 16
2945 11:45:33.989679 best dqsien dly found for B0: ( 1, 3, 24)
2946 11:45:33.993168 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 11:45:33.996417 Total UI for P1: 0, mck2ui 16
2948 11:45:33.999787 best dqsien dly found for B1: ( 1, 3, 28)
2949 11:45:34.003425 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2950 11:45:34.009337 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2951 11:45:34.009490
2952 11:45:34.012840 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2953 11:45:34.015983 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2954 11:45:34.019160 [Gating] SW calibration Done
2955 11:45:34.019241 ==
2956 11:45:34.022511 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 11:45:34.025720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 11:45:34.025815 ==
2959 11:45:34.029419 RX Vref Scan: 0
2960 11:45:34.029501
2961 11:45:34.029566 RX Vref 0 -> 0, step: 1
2962 11:45:34.029626
2963 11:45:34.032701 RX Delay -40 -> 252, step: 8
2964 11:45:34.036056 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2965 11:45:34.042513 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2966 11:45:34.045815 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2967 11:45:34.049283 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2968 11:45:34.052365 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2969 11:45:34.055945 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2970 11:45:34.062382 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2971 11:45:34.065770 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2972 11:45:34.069219 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2973 11:45:34.072156 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2974 11:45:34.076113 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2975 11:45:34.078861 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2976 11:45:34.085621 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2977 11:45:34.089094 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2978 11:45:34.091918 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2979 11:45:34.095490 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2980 11:45:34.098805 ==
2981 11:45:34.098885 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 11:45:34.105702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 11:45:34.105783 ==
2984 11:45:34.105847 DQS Delay:
2985 11:45:34.108567 DQS0 = 0, DQS1 = 0
2986 11:45:34.108638 DQM Delay:
2987 11:45:34.112081 DQM0 = 119, DQM1 = 106
2988 11:45:34.112177 DQ Delay:
2989 11:45:34.115610 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2990 11:45:34.118541 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2991 11:45:34.122103 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2992 11:45:34.125421 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2993 11:45:34.125511
2994 11:45:34.125574
2995 11:45:34.125631 ==
2996 11:45:34.128667 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 11:45:34.135453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 11:45:34.135591 ==
2999 11:45:34.135693
3000 11:45:34.135781
3001 11:45:34.135867 TX Vref Scan disable
3002 11:45:34.138521 == TX Byte 0 ==
3003 11:45:34.141728 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3004 11:45:34.148353 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3005 11:45:34.148429 == TX Byte 1 ==
3006 11:45:34.151892 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3007 11:45:34.155355 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3008 11:45:34.158985 ==
3009 11:45:34.161772 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 11:45:34.165238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 11:45:34.165334 ==
3012 11:45:34.176764 TX Vref=22, minBit 12, minWin=25, winSum=416
3013 11:45:34.179934 TX Vref=24, minBit 10, minWin=25, winSum=420
3014 11:45:34.183433 TX Vref=26, minBit 1, minWin=26, winSum=421
3015 11:45:34.186827 TX Vref=28, minBit 14, minWin=25, winSum=426
3016 11:45:34.189857 TX Vref=30, minBit 0, minWin=26, winSum=427
3017 11:45:34.196909 TX Vref=32, minBit 14, minWin=25, winSum=424
3018 11:45:34.199791 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 30
3019 11:45:34.199865
3020 11:45:34.203372 Final TX Range 1 Vref 30
3021 11:45:34.203493
3022 11:45:34.203554 ==
3023 11:45:34.206517 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 11:45:34.210177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 11:45:34.213042 ==
3026 11:45:34.213121
3027 11:45:34.213205
3028 11:45:34.213266 TX Vref Scan disable
3029 11:45:34.217218 == TX Byte 0 ==
3030 11:45:34.220093 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3031 11:45:34.226522 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3032 11:45:34.226595 == TX Byte 1 ==
3033 11:45:34.230044 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3034 11:45:34.236566 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3035 11:45:34.236640
3036 11:45:34.236737 [DATLAT]
3037 11:45:34.236824 Freq=1200, CH0 RK1
3038 11:45:34.236913
3039 11:45:34.239705 DATLAT Default: 0xd
3040 11:45:34.239776 0, 0xFFFF, sum = 0
3041 11:45:34.243416 1, 0xFFFF, sum = 0
3042 11:45:34.246794 2, 0xFFFF, sum = 0
3043 11:45:34.246869 3, 0xFFFF, sum = 0
3044 11:45:34.250138 4, 0xFFFF, sum = 0
3045 11:45:34.250208 5, 0xFFFF, sum = 0
3046 11:45:34.253199 6, 0xFFFF, sum = 0
3047 11:45:34.253266 7, 0xFFFF, sum = 0
3048 11:45:34.256341 8, 0xFFFF, sum = 0
3049 11:45:34.256412 9, 0xFFFF, sum = 0
3050 11:45:34.260141 10, 0xFFFF, sum = 0
3051 11:45:34.260214 11, 0xFFFF, sum = 0
3052 11:45:34.263050 12, 0x0, sum = 1
3053 11:45:34.263119 13, 0x0, sum = 2
3054 11:45:34.266494 14, 0x0, sum = 3
3055 11:45:34.266579 15, 0x0, sum = 4
3056 11:45:34.269731 best_step = 13
3057 11:45:34.269817
3058 11:45:34.269876 ==
3059 11:45:34.273007 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 11:45:34.276539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 11:45:34.276630 ==
3062 11:45:34.276698 RX Vref Scan: 0
3063 11:45:34.279669
3064 11:45:34.279743 RX Vref 0 -> 0, step: 1
3065 11:45:34.279815
3066 11:45:34.282759 RX Delay -21 -> 252, step: 4
3067 11:45:34.289866 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3068 11:45:34.292939 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3069 11:45:34.296547 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3070 11:45:34.299563 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3071 11:45:34.302831 iDelay=195, Bit 4, Center 122 (59 ~ 186) 128
3072 11:45:34.306276 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3073 11:45:34.313152 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3074 11:45:34.316766 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3075 11:45:34.319626 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3076 11:45:34.322898 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3077 11:45:34.326213 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3078 11:45:34.332717 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3079 11:45:34.336291 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3080 11:45:34.339728 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3081 11:45:34.343115 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3082 11:45:34.349493 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3083 11:45:34.349567 ==
3084 11:45:34.352649 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 11:45:34.356069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 11:45:34.356144 ==
3087 11:45:34.356205 DQS Delay:
3088 11:45:34.359468 DQS0 = 0, DQS1 = 0
3089 11:45:34.359534 DQM Delay:
3090 11:45:34.362693 DQM0 = 118, DQM1 = 106
3091 11:45:34.362766 DQ Delay:
3092 11:45:34.366092 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3093 11:45:34.369759 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
3094 11:45:34.372758 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3095 11:45:34.376250 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =114
3096 11:45:34.376323
3097 11:45:34.376384
3098 11:45:34.386051 [DQSOSCAuto] RK1, (LSB)MR18= 0xfaf8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
3099 11:45:34.389202 CH0 RK1: MR19=303, MR18=FAF8
3100 11:45:34.392364 CH0_RK1: MR19=0x303, MR18=0xFAF8, DQSOSC=412, MR23=63, INC=38, DEC=25
3101 11:45:34.396402 [RxdqsGatingPostProcess] freq 1200
3102 11:45:34.402581 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3103 11:45:34.405655 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 11:45:34.409387 best DQS1 dly(2T, 0.5T) = (0, 11)
3105 11:45:34.413139 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 11:45:34.415989 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3107 11:45:34.419249 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 11:45:34.422610 best DQS1 dly(2T, 0.5T) = (0, 11)
3109 11:45:34.425877 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 11:45:34.428873 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3111 11:45:34.428984 Pre-setting of DQS Precalculation
3112 11:45:34.435602 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3113 11:45:34.435721 ==
3114 11:45:34.438883 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 11:45:34.442779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 11:45:34.442864 ==
3117 11:45:34.449105 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 11:45:34.455619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3119 11:45:34.463480 [CA 0] Center 38 (8~68) winsize 61
3120 11:45:34.466998 [CA 1] Center 37 (7~68) winsize 62
3121 11:45:34.469957 [CA 2] Center 35 (5~65) winsize 61
3122 11:45:34.473066 [CA 3] Center 34 (4~64) winsize 61
3123 11:45:34.476413 [CA 4] Center 34 (4~65) winsize 62
3124 11:45:34.479699 [CA 5] Center 33 (3~63) winsize 61
3125 11:45:34.479776
3126 11:45:34.483213 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3127 11:45:34.483288
3128 11:45:34.486121 [CATrainingPosCal] consider 1 rank data
3129 11:45:34.489663 u2DelayCellTimex100 = 270/100 ps
3130 11:45:34.493181 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3131 11:45:34.496689 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 11:45:34.503138 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3133 11:45:34.506319 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 11:45:34.509917 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3135 11:45:34.512861 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3136 11:45:34.512944
3137 11:45:34.516832 CA PerBit enable=1, Macro0, CA PI delay=33
3138 11:45:34.516914
3139 11:45:34.519886 [CBTSetCACLKResult] CA Dly = 33
3140 11:45:34.519969 CS Dly: 4 (0~35)
3141 11:45:34.523158 ==
3142 11:45:34.523240 Dram Type= 6, Freq= 0, CH_1, rank 1
3143 11:45:34.530115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 11:45:34.530198 ==
3145 11:45:34.533183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 11:45:34.539884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3147 11:45:34.549181 [CA 0] Center 37 (7~68) winsize 62
3148 11:45:34.552410 [CA 1] Center 38 (8~68) winsize 61
3149 11:45:34.555542 [CA 2] Center 34 (4~65) winsize 62
3150 11:45:34.559045 [CA 3] Center 33 (3~64) winsize 62
3151 11:45:34.562569 [CA 4] Center 34 (4~64) winsize 61
3152 11:45:34.565374 [CA 5] Center 33 (3~64) winsize 62
3153 11:45:34.565455
3154 11:45:34.569131 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3155 11:45:34.569212
3156 11:45:34.571707 [CATrainingPosCal] consider 2 rank data
3157 11:45:34.575278 u2DelayCellTimex100 = 270/100 ps
3158 11:45:34.578401 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3159 11:45:34.585221 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3160 11:45:34.588726 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3161 11:45:34.592375 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 11:45:34.595331 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 11:45:34.598856 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3164 11:45:34.598937
3165 11:45:34.601745 CA PerBit enable=1, Macro0, CA PI delay=33
3166 11:45:34.601825
3167 11:45:34.605466 [CBTSetCACLKResult] CA Dly = 33
3168 11:45:34.605547 CS Dly: 6 (0~39)
3169 11:45:34.608555
3170 11:45:34.611788 ----->DramcWriteLeveling(PI) begin...
3171 11:45:34.611883 ==
3172 11:45:34.614975 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 11:45:34.618174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 11:45:34.618280 ==
3175 11:45:34.621605 Write leveling (Byte 0): 25 => 25
3176 11:45:34.624707 Write leveling (Byte 1): 28 => 28
3177 11:45:34.628204 DramcWriteLeveling(PI) end<-----
3178 11:45:34.628284
3179 11:45:34.628347 ==
3180 11:45:34.631403 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 11:45:34.634575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 11:45:34.634656 ==
3183 11:45:34.638180 [Gating] SW mode calibration
3184 11:45:34.644772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3185 11:45:34.651430 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3186 11:45:34.655009 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
3187 11:45:34.658427 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 11:45:34.664392 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 11:45:34.667994 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 11:45:34.671425 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 11:45:34.677709 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 11:45:34.681221 0 15 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
3193 11:45:34.684834 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3194 11:45:34.691418 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 11:45:34.694469 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 11:45:34.697890 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 11:45:34.704413 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 11:45:34.707914 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 11:45:34.711247 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 11:45:34.717662 1 0 24 | B1->B0 | 2323 2727 | 1 0 | (0 0) (0 0)
3201 11:45:34.721192 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
3202 11:45:34.724723 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:45:34.727591 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 11:45:34.734225 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 11:45:34.737598 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:45:34.741009 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 11:45:34.747711 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 11:45:34.751155 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 11:45:34.754043 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3210 11:45:34.761069 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:45:34.764738 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:45:34.767954 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:45:34.774181 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:45:34.777427 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:45:34.780662 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:45:34.787549 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:45:34.790787 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:45:34.793716 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:45:34.800581 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:45:34.803957 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:45:34.807357 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 11:45:34.813823 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 11:45:34.817280 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 11:45:34.820809 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 11:45:34.827170 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3226 11:45:34.830642 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 11:45:34.833898 Total UI for P1: 0, mck2ui 16
3228 11:45:34.837020 best dqsien dly found for B0: ( 1, 3, 26)
3229 11:45:34.840684 Total UI for P1: 0, mck2ui 16
3230 11:45:34.843606 best dqsien dly found for B1: ( 1, 3, 26)
3231 11:45:34.847210 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3232 11:45:34.850068 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3233 11:45:34.850165
3234 11:45:34.853864 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3235 11:45:34.856955 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3236 11:45:34.860426 [Gating] SW calibration Done
3237 11:45:34.860532 ==
3238 11:45:34.863866 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 11:45:34.867149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 11:45:34.870178 ==
3241 11:45:34.870308 RX Vref Scan: 0
3242 11:45:34.870374
3243 11:45:34.873535 RX Vref 0 -> 0, step: 1
3244 11:45:34.873609
3245 11:45:34.876801 RX Delay -40 -> 252, step: 8
3246 11:45:34.880341 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3247 11:45:34.884028 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3248 11:45:34.886723 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3249 11:45:34.890525 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3250 11:45:34.896449 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3251 11:45:34.899839 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3252 11:45:34.903311 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3253 11:45:34.906546 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3254 11:45:34.910053 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3255 11:45:34.916605 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3256 11:45:34.919981 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3257 11:45:34.923267 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3258 11:45:34.926763 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3259 11:45:34.929657 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3260 11:45:34.936382 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3261 11:45:34.939768 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3262 11:45:34.939852 ==
3263 11:45:34.943113 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 11:45:34.946786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 11:45:34.946874 ==
3266 11:45:34.949672 DQS Delay:
3267 11:45:34.949758 DQS0 = 0, DQS1 = 0
3268 11:45:34.949820 DQM Delay:
3269 11:45:34.953148 DQM0 = 115, DQM1 = 112
3270 11:45:34.953255 DQ Delay:
3271 11:45:34.956763 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3272 11:45:34.959584 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3273 11:45:34.963134 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3274 11:45:34.969811 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3275 11:45:34.969908
3276 11:45:34.970008
3277 11:45:34.970096 ==
3278 11:45:34.972999 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 11:45:34.976702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 11:45:34.976808 ==
3281 11:45:34.976898
3282 11:45:34.976994
3283 11:45:34.979760 TX Vref Scan disable
3284 11:45:34.979899 == TX Byte 0 ==
3285 11:45:34.986169 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3286 11:45:34.989786 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3287 11:45:34.989889 == TX Byte 1 ==
3288 11:45:34.996416 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3289 11:45:34.999677 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3290 11:45:34.999778 ==
3291 11:45:35.002628 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 11:45:35.005977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 11:45:35.006084 ==
3294 11:45:35.019060 TX Vref=22, minBit 8, minWin=24, winSum=409
3295 11:45:35.022341 TX Vref=24, minBit 3, minWin=25, winSum=419
3296 11:45:35.025744 TX Vref=26, minBit 7, minWin=25, winSum=419
3297 11:45:35.028884 TX Vref=28, minBit 7, minWin=26, winSum=426
3298 11:45:35.032283 TX Vref=30, minBit 0, minWin=26, winSum=425
3299 11:45:35.035798 TX Vref=32, minBit 0, minWin=26, winSum=425
3300 11:45:35.042179 [TxChooseVref] Worse bit 7, Min win 26, Win sum 426, Final Vref 28
3301 11:45:35.042328
3302 11:45:35.045470 Final TX Range 1 Vref 28
3303 11:45:35.045546
3304 11:45:35.045629 ==
3305 11:45:35.048889 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 11:45:35.052530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 11:45:35.052606 ==
3308 11:45:35.052669
3309 11:45:35.055398
3310 11:45:35.055467 TX Vref Scan disable
3311 11:45:35.058854 == TX Byte 0 ==
3312 11:45:35.062435 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3313 11:45:35.065822 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3314 11:45:35.068670 == TX Byte 1 ==
3315 11:45:35.072295 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3316 11:45:35.075940 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3317 11:45:35.078767
3318 11:45:35.078840 [DATLAT]
3319 11:45:35.078902 Freq=1200, CH1 RK0
3320 11:45:35.078963
3321 11:45:35.082259 DATLAT Default: 0xd
3322 11:45:35.082331 0, 0xFFFF, sum = 0
3323 11:45:35.085562 1, 0xFFFF, sum = 0
3324 11:45:35.085635 2, 0xFFFF, sum = 0
3325 11:45:35.088483 3, 0xFFFF, sum = 0
3326 11:45:35.091760 4, 0xFFFF, sum = 0
3327 11:45:35.091852 5, 0xFFFF, sum = 0
3328 11:45:35.095709 6, 0xFFFF, sum = 0
3329 11:45:35.095788 7, 0xFFFF, sum = 0
3330 11:45:35.098759 8, 0xFFFF, sum = 0
3331 11:45:35.098844 9, 0xFFFF, sum = 0
3332 11:45:35.102479 10, 0xFFFF, sum = 0
3333 11:45:35.102603 11, 0xFFFF, sum = 0
3334 11:45:35.105570 12, 0x0, sum = 1
3335 11:45:35.105682 13, 0x0, sum = 2
3336 11:45:35.108463 14, 0x0, sum = 3
3337 11:45:35.108569 15, 0x0, sum = 4
3338 11:45:35.108661 best_step = 13
3339 11:45:35.111942
3340 11:45:35.112046 ==
3341 11:45:35.115220 Dram Type= 6, Freq= 0, CH_1, rank 0
3342 11:45:35.118734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3343 11:45:35.118808 ==
3344 11:45:35.118870 RX Vref Scan: 1
3345 11:45:35.118929
3346 11:45:35.121728 Set Vref Range= 32 -> 127
3347 11:45:35.121797
3348 11:45:35.124914 RX Vref 32 -> 127, step: 1
3349 11:45:35.125016
3350 11:45:35.128791 RX Delay -13 -> 252, step: 4
3351 11:45:35.128888
3352 11:45:35.131710 Set Vref, RX VrefLevel [Byte0]: 32
3353 11:45:35.135121 [Byte1]: 32
3354 11:45:35.135220
3355 11:45:35.138748 Set Vref, RX VrefLevel [Byte0]: 33
3356 11:45:35.141827 [Byte1]: 33
3357 11:45:35.145059
3358 11:45:35.145158 Set Vref, RX VrefLevel [Byte0]: 34
3359 11:45:35.148670 [Byte1]: 34
3360 11:45:35.152941
3361 11:45:35.153015 Set Vref, RX VrefLevel [Byte0]: 35
3362 11:45:35.156111 [Byte1]: 35
3363 11:45:35.160963
3364 11:45:35.161043 Set Vref, RX VrefLevel [Byte0]: 36
3365 11:45:35.164371 [Byte1]: 36
3366 11:45:35.169038
3367 11:45:35.169110 Set Vref, RX VrefLevel [Byte0]: 37
3368 11:45:35.175928 [Byte1]: 37
3369 11:45:35.176003
3370 11:45:35.178367 Set Vref, RX VrefLevel [Byte0]: 38
3371 11:45:35.181909 [Byte1]: 38
3372 11:45:35.181981
3373 11:45:35.185306 Set Vref, RX VrefLevel [Byte0]: 39
3374 11:45:35.188810 [Byte1]: 39
3375 11:45:35.192820
3376 11:45:35.192898 Set Vref, RX VrefLevel [Byte0]: 40
3377 11:45:35.195607 [Byte1]: 40
3378 11:45:35.200438
3379 11:45:35.200510 Set Vref, RX VrefLevel [Byte0]: 41
3380 11:45:35.203558 [Byte1]: 41
3381 11:45:35.208405
3382 11:45:35.208476 Set Vref, RX VrefLevel [Byte0]: 42
3383 11:45:35.211385 [Byte1]: 42
3384 11:45:35.215966
3385 11:45:35.216034 Set Vref, RX VrefLevel [Byte0]: 43
3386 11:45:35.219459 [Byte1]: 43
3387 11:45:35.224227
3388 11:45:35.224295 Set Vref, RX VrefLevel [Byte0]: 44
3389 11:45:35.227339 [Byte1]: 44
3390 11:45:35.231681
3391 11:45:35.231749 Set Vref, RX VrefLevel [Byte0]: 45
3392 11:45:35.235395 [Byte1]: 45
3393 11:45:35.239601
3394 11:45:35.239676 Set Vref, RX VrefLevel [Byte0]: 46
3395 11:45:35.243134 [Byte1]: 46
3396 11:45:35.247787
3397 11:45:35.247884 Set Vref, RX VrefLevel [Byte0]: 47
3398 11:45:35.250768 [Byte1]: 47
3399 11:45:35.255688
3400 11:45:35.255755 Set Vref, RX VrefLevel [Byte0]: 48
3401 11:45:35.258726 [Byte1]: 48
3402 11:45:35.263699
3403 11:45:35.263765 Set Vref, RX VrefLevel [Byte0]: 49
3404 11:45:35.266600 [Byte1]: 49
3405 11:45:35.271200
3406 11:45:35.271269 Set Vref, RX VrefLevel [Byte0]: 50
3407 11:45:35.274260 [Byte1]: 50
3408 11:45:35.279013
3409 11:45:35.279084 Set Vref, RX VrefLevel [Byte0]: 51
3410 11:45:35.282350 [Byte1]: 51
3411 11:45:35.287109
3412 11:45:35.287211 Set Vref, RX VrefLevel [Byte0]: 52
3413 11:45:35.290150 [Byte1]: 52
3414 11:45:35.295155
3415 11:45:35.295232 Set Vref, RX VrefLevel [Byte0]: 53
3416 11:45:35.298126 [Byte1]: 53
3417 11:45:35.302445
3418 11:45:35.302518 Set Vref, RX VrefLevel [Byte0]: 54
3419 11:45:35.306176 [Byte1]: 54
3420 11:45:35.310644
3421 11:45:35.310724 Set Vref, RX VrefLevel [Byte0]: 55
3422 11:45:35.313991 [Byte1]: 55
3423 11:45:35.318445
3424 11:45:35.318518 Set Vref, RX VrefLevel [Byte0]: 56
3425 11:45:35.321956 [Byte1]: 56
3426 11:45:35.326841
3427 11:45:35.326914 Set Vref, RX VrefLevel [Byte0]: 57
3428 11:45:35.329992 [Byte1]: 57
3429 11:45:35.334110
3430 11:45:35.334208 Set Vref, RX VrefLevel [Byte0]: 58
3431 11:45:35.338122 [Byte1]: 58
3432 11:45:35.342559
3433 11:45:35.342637 Set Vref, RX VrefLevel [Byte0]: 59
3434 11:45:35.345186 [Byte1]: 59
3435 11:45:35.350058
3436 11:45:35.350157 Set Vref, RX VrefLevel [Byte0]: 60
3437 11:45:35.353366 [Byte1]: 60
3438 11:45:35.358044
3439 11:45:35.358149 Set Vref, RX VrefLevel [Byte0]: 61
3440 11:45:35.361031 [Byte1]: 61
3441 11:45:35.365782
3442 11:45:35.365862 Set Vref, RX VrefLevel [Byte0]: 62
3443 11:45:35.369264 [Byte1]: 62
3444 11:45:35.373986
3445 11:45:35.374060 Set Vref, RX VrefLevel [Byte0]: 63
3446 11:45:35.376935 [Byte1]: 63
3447 11:45:35.381450
3448 11:45:35.381523 Set Vref, RX VrefLevel [Byte0]: 64
3449 11:45:35.384976 [Byte1]: 64
3450 11:45:35.389431
3451 11:45:35.389536 Set Vref, RX VrefLevel [Byte0]: 65
3452 11:45:35.393143 [Byte1]: 65
3453 11:45:35.397350
3454 11:45:35.397456 Final RX Vref Byte 0 = 52 to rank0
3455 11:45:35.400882 Final RX Vref Byte 1 = 52 to rank0
3456 11:45:35.403768 Final RX Vref Byte 0 = 52 to rank1
3457 11:45:35.407198 Final RX Vref Byte 1 = 52 to rank1==
3458 11:45:35.410818 Dram Type= 6, Freq= 0, CH_1, rank 0
3459 11:45:35.416933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 11:45:35.417037 ==
3461 11:45:35.417129 DQS Delay:
3462 11:45:35.417218 DQS0 = 0, DQS1 = 0
3463 11:45:35.420611 DQM Delay:
3464 11:45:35.420709 DQM0 = 115, DQM1 = 113
3465 11:45:35.423777 DQ Delay:
3466 11:45:35.427238 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3467 11:45:35.430693 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3468 11:45:35.433698 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3469 11:45:35.437212 DQ12 =122, DQ13 =120, DQ14 =118, DQ15 =122
3470 11:45:35.437288
3471 11:45:35.437358
3472 11:45:35.446862 [DQSOSCAuto] RK0, (LSB)MR18= 0xf400, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3473 11:45:35.446941 CH1 RK0: MR19=304, MR18=F400
3474 11:45:35.453977 CH1_RK0: MR19=0x304, MR18=0xF400, DQSOSC=410, MR23=63, INC=39, DEC=26
3475 11:45:35.454055
3476 11:45:35.457036 ----->DramcWriteLeveling(PI) begin...
3477 11:45:35.457131 ==
3478 11:45:35.460290 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 11:45:35.467054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 11:45:35.467138 ==
3481 11:45:35.470183 Write leveling (Byte 0): 24 => 24
3482 11:45:35.470314 Write leveling (Byte 1): 28 => 28
3483 11:45:35.473312 DramcWriteLeveling(PI) end<-----
3484 11:45:35.473407
3485 11:45:35.476856 ==
3486 11:45:35.476955 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 11:45:35.483593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 11:45:35.483663 ==
3489 11:45:35.486643 [Gating] SW mode calibration
3490 11:45:35.493465 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3491 11:45:35.496735 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3492 11:45:35.504021 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3493 11:45:35.507192 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 11:45:35.510050 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 11:45:35.517008 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 11:45:35.520209 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 11:45:35.523764 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3498 11:45:35.530139 0 15 24 | B1->B0 | 3434 2626 | 0 0 | (0 1) (0 0)
3499 11:45:35.533630 0 15 28 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
3500 11:45:35.536468 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 11:45:35.543529 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 11:45:35.546407 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 11:45:35.550078 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 11:45:35.556835 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 11:45:35.560058 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3506 11:45:35.563534 1 0 24 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
3507 11:45:35.569807 1 0 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3508 11:45:35.573320 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 11:45:35.576213 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 11:45:35.582902 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 11:45:35.586166 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 11:45:35.589870 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 11:45:35.596353 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 11:45:35.599487 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3515 11:45:35.602773 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3516 11:45:35.609655 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3517 11:45:35.612885 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 11:45:35.615939 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 11:45:35.622109 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 11:45:35.625866 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 11:45:35.628723 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 11:45:35.635555 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 11:45:35.638342 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 11:45:35.642017 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 11:45:35.648842 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 11:45:35.651641 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 11:45:35.655088 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 11:45:35.661838 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 11:45:35.665251 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3530 11:45:35.668123 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3531 11:45:35.671977 Total UI for P1: 0, mck2ui 16
3532 11:45:35.674926 best dqsien dly found for B0: ( 1, 3, 20)
3533 11:45:35.681182 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3534 11:45:35.684923 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 11:45:35.688251 Total UI for P1: 0, mck2ui 16
3536 11:45:35.691139 best dqsien dly found for B1: ( 1, 3, 26)
3537 11:45:35.694720 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3538 11:45:35.697580 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3539 11:45:35.697652
3540 11:45:35.700890 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3541 11:45:35.704204 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3542 11:45:35.707612 [Gating] SW calibration Done
3543 11:45:35.707684 ==
3544 11:45:35.710753 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 11:45:35.717645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 11:45:35.717721 ==
3547 11:45:35.717784 RX Vref Scan: 0
3548 11:45:35.717843
3549 11:45:35.721026 RX Vref 0 -> 0, step: 1
3550 11:45:35.721134
3551 11:45:35.724105 RX Delay -40 -> 252, step: 8
3552 11:45:35.727219 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3553 11:45:35.730503 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3554 11:45:35.733596 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3555 11:45:35.740387 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3556 11:45:35.743693 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3557 11:45:35.747288 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3558 11:45:35.750155 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3559 11:45:35.753631 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3560 11:45:35.760127 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3561 11:45:35.763852 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3562 11:45:35.766508 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3563 11:45:35.769703 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3564 11:45:35.773095 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3565 11:45:35.779637 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3566 11:45:35.783206 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3567 11:45:35.786428 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3568 11:45:35.786503 ==
3569 11:45:35.790133 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 11:45:35.792903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 11:45:35.796458 ==
3572 11:45:35.796533 DQS Delay:
3573 11:45:35.796595 DQS0 = 0, DQS1 = 0
3574 11:45:35.799580 DQM Delay:
3575 11:45:35.799657 DQM0 = 115, DQM1 = 111
3576 11:45:35.803046 DQ Delay:
3577 11:45:35.806234 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3578 11:45:35.809404 DQ4 =119, DQ5 =127, DQ6 =119, DQ7 =115
3579 11:45:35.813299 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3580 11:45:35.816489 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3581 11:45:35.816574
3582 11:45:35.816636
3583 11:45:35.816694 ==
3584 11:45:35.819419 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 11:45:35.822928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 11:45:35.823010 ==
3587 11:45:35.823078
3588 11:45:35.825967
3589 11:45:35.826040 TX Vref Scan disable
3590 11:45:35.829385 == TX Byte 0 ==
3591 11:45:35.832749 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3592 11:45:35.836014 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3593 11:45:35.839402 == TX Byte 1 ==
3594 11:45:35.842461 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3595 11:45:35.845548 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3596 11:45:35.845625 ==
3597 11:45:35.849050 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 11:45:35.855722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 11:45:35.855800 ==
3600 11:45:35.866670 TX Vref=22, minBit 2, minWin=25, winSum=415
3601 11:45:35.869854 TX Vref=24, minBit 9, minWin=25, winSum=419
3602 11:45:35.872957 TX Vref=26, minBit 9, minWin=25, winSum=422
3603 11:45:35.876451 TX Vref=28, minBit 2, minWin=26, winSum=431
3604 11:45:35.879339 TX Vref=30, minBit 1, minWin=26, winSum=430
3605 11:45:35.886198 TX Vref=32, minBit 8, minWin=26, winSum=432
3606 11:45:35.889241 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 32
3607 11:45:35.889344
3608 11:45:35.892783 Final TX Range 1 Vref 32
3609 11:45:35.892883
3610 11:45:35.892972 ==
3611 11:45:35.896310 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 11:45:35.902985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 11:45:35.903059 ==
3614 11:45:35.903125
3615 11:45:35.903183
3616 11:45:35.903239 TX Vref Scan disable
3617 11:45:35.906245 == TX Byte 0 ==
3618 11:45:35.910112 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3619 11:45:35.916212 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3620 11:45:35.916310 == TX Byte 1 ==
3621 11:45:35.919826 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3622 11:45:35.926152 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3623 11:45:35.926289
3624 11:45:35.926379 [DATLAT]
3625 11:45:35.926468 Freq=1200, CH1 RK1
3626 11:45:35.926554
3627 11:45:35.929647 DATLAT Default: 0xd
3628 11:45:35.932434 0, 0xFFFF, sum = 0
3629 11:45:35.932533 1, 0xFFFF, sum = 0
3630 11:45:35.936122 2, 0xFFFF, sum = 0
3631 11:45:35.936192 3, 0xFFFF, sum = 0
3632 11:45:35.939138 4, 0xFFFF, sum = 0
3633 11:45:35.939239 5, 0xFFFF, sum = 0
3634 11:45:35.942552 6, 0xFFFF, sum = 0
3635 11:45:35.942634 7, 0xFFFF, sum = 0
3636 11:45:35.945921 8, 0xFFFF, sum = 0
3637 11:45:35.945993 9, 0xFFFF, sum = 0
3638 11:45:35.949303 10, 0xFFFF, sum = 0
3639 11:45:35.949397 11, 0xFFFF, sum = 0
3640 11:45:35.952476 12, 0x0, sum = 1
3641 11:45:35.952551 13, 0x0, sum = 2
3642 11:45:35.955957 14, 0x0, sum = 3
3643 11:45:35.956029 15, 0x0, sum = 4
3644 11:45:35.959205 best_step = 13
3645 11:45:35.959275
3646 11:45:35.959333 ==
3647 11:45:35.962529 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 11:45:35.965448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 11:45:35.965516 ==
3650 11:45:35.968886 RX Vref Scan: 0
3651 11:45:35.968954
3652 11:45:35.969010 RX Vref 0 -> 0, step: 1
3653 11:45:35.969066
3654 11:45:35.972221 RX Delay -13 -> 252, step: 4
3655 11:45:35.978846 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3656 11:45:35.981921 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3657 11:45:35.985611 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3658 11:45:35.988661 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3659 11:45:35.992560 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3660 11:45:35.998428 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3661 11:45:36.001916 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3662 11:45:36.005466 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3663 11:45:36.008570 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3664 11:45:36.011910 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3665 11:45:36.018562 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3666 11:45:36.021913 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3667 11:45:36.024821 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3668 11:45:36.028234 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3669 11:45:36.034712 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3670 11:45:36.037700 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3671 11:45:36.037770 ==
3672 11:45:36.041108 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 11:45:36.044616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 11:45:36.044690 ==
3675 11:45:36.047612 DQS Delay:
3676 11:45:36.047684 DQS0 = 0, DQS1 = 0
3677 11:45:36.047745 DQM Delay:
3678 11:45:36.051011 DQM0 = 115, DQM1 = 112
3679 11:45:36.051085 DQ Delay:
3680 11:45:36.054420 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =114
3681 11:45:36.057768 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =112
3682 11:45:36.064444 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3683 11:45:36.067650 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3684 11:45:36.067805
3685 11:45:36.067898
3686 11:45:36.073850 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3687 11:45:36.077312 CH1 RK1: MR19=304, MR18=F709
3688 11:45:36.083799 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3689 11:45:36.087273 [RxdqsGatingPostProcess] freq 1200
3690 11:45:36.093829 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3691 11:45:36.097535 best DQS0 dly(2T, 0.5T) = (0, 11)
3692 11:45:36.097711 best DQS1 dly(2T, 0.5T) = (0, 11)
3693 11:45:36.100261 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3694 11:45:36.103650 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3695 11:45:36.107733 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 11:45:36.110181 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 11:45:36.113876 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 11:45:36.116692 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 11:45:36.120216 Pre-setting of DQS Precalculation
3700 11:45:36.126769 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3701 11:45:36.133081 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3702 11:45:36.139652 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3703 11:45:36.139743
3704 11:45:36.139828
3705 11:45:36.142980 [Calibration Summary] 2400 Mbps
3706 11:45:36.143060 CH 0, Rank 0
3707 11:45:36.146187 SW Impedance : PASS
3708 11:45:36.149682 DUTY Scan : NO K
3709 11:45:36.149762 ZQ Calibration : PASS
3710 11:45:36.152711 Jitter Meter : NO K
3711 11:45:36.156111 CBT Training : PASS
3712 11:45:36.156189 Write leveling : PASS
3713 11:45:36.159469 RX DQS gating : PASS
3714 11:45:36.163072 RX DQ/DQS(RDDQC) : PASS
3715 11:45:36.163156 TX DQ/DQS : PASS
3716 11:45:36.166146 RX DATLAT : PASS
3717 11:45:36.169423 RX DQ/DQS(Engine): PASS
3718 11:45:36.169502 TX OE : NO K
3719 11:45:36.172806 All Pass.
3720 11:45:36.172883
3721 11:45:36.172968 CH 0, Rank 1
3722 11:45:36.176005 SW Impedance : PASS
3723 11:45:36.176083 DUTY Scan : NO K
3724 11:45:36.179115 ZQ Calibration : PASS
3725 11:45:36.182438 Jitter Meter : NO K
3726 11:45:36.182515 CBT Training : PASS
3727 11:45:36.185816 Write leveling : PASS
3728 11:45:36.189192 RX DQS gating : PASS
3729 11:45:36.189275 RX DQ/DQS(RDDQC) : PASS
3730 11:45:36.192632 TX DQ/DQS : PASS
3731 11:45:36.192709 RX DATLAT : PASS
3732 11:45:36.195931 RX DQ/DQS(Engine): PASS
3733 11:45:36.199426 TX OE : NO K
3734 11:45:36.199505 All Pass.
3735 11:45:36.199573
3736 11:45:36.202669 CH 1, Rank 0
3737 11:45:36.202745 SW Impedance : PASS
3738 11:45:36.205887 DUTY Scan : NO K
3739 11:45:36.205961 ZQ Calibration : PASS
3740 11:45:36.208862 Jitter Meter : NO K
3741 11:45:36.212423 CBT Training : PASS
3742 11:45:36.212499 Write leveling : PASS
3743 11:45:36.215406 RX DQS gating : PASS
3744 11:45:36.218922 RX DQ/DQS(RDDQC) : PASS
3745 11:45:36.219008 TX DQ/DQS : PASS
3746 11:45:36.222014 RX DATLAT : PASS
3747 11:45:36.225900 RX DQ/DQS(Engine): PASS
3748 11:45:36.225986 TX OE : NO K
3749 11:45:36.228881 All Pass.
3750 11:45:36.228957
3751 11:45:36.229039 CH 1, Rank 1
3752 11:45:36.232186 SW Impedance : PASS
3753 11:45:36.232260 DUTY Scan : NO K
3754 11:45:36.235728 ZQ Calibration : PASS
3755 11:45:36.238700 Jitter Meter : NO K
3756 11:45:36.238771 CBT Training : PASS
3757 11:45:36.242064 Write leveling : PASS
3758 11:45:36.245631 RX DQS gating : PASS
3759 11:45:36.245705 RX DQ/DQS(RDDQC) : PASS
3760 11:45:36.248255 TX DQ/DQS : PASS
3761 11:45:36.251655 RX DATLAT : PASS
3762 11:45:36.251731 RX DQ/DQS(Engine): PASS
3763 11:45:36.255008 TX OE : NO K
3764 11:45:36.255085 All Pass.
3765 11:45:36.255168
3766 11:45:36.258175 DramC Write-DBI off
3767 11:45:36.261734 PER_BANK_REFRESH: Hybrid Mode
3768 11:45:36.261822 TX_TRACKING: ON
3769 11:45:36.272109 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3770 11:45:36.275015 [FAST_K] Save calibration result to emmc
3771 11:45:36.278107 dramc_set_vcore_voltage set vcore to 650000
3772 11:45:36.281501 Read voltage for 600, 5
3773 11:45:36.281577 Vio18 = 0
3774 11:45:36.281661 Vcore = 650000
3775 11:45:36.284979 Vdram = 0
3776 11:45:36.285054 Vddq = 0
3777 11:45:36.285132 Vmddr = 0
3778 11:45:36.291714 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3779 11:45:36.294591 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3780 11:45:36.297610 MEM_TYPE=3, freq_sel=19
3781 11:45:36.301125 sv_algorithm_assistance_LP4_1600
3782 11:45:36.304518 ============ PULL DRAM RESETB DOWN ============
3783 11:45:36.311614 ========== PULL DRAM RESETB DOWN end =========
3784 11:45:36.314196 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3785 11:45:36.317882 ===================================
3786 11:45:36.321139 LPDDR4 DRAM CONFIGURATION
3787 11:45:36.324613 ===================================
3788 11:45:36.324689 EX_ROW_EN[0] = 0x0
3789 11:45:36.327292 EX_ROW_EN[1] = 0x0
3790 11:45:36.327380 LP4Y_EN = 0x0
3791 11:45:36.330780 WORK_FSP = 0x0
3792 11:45:36.330873 WL = 0x2
3793 11:45:36.335136 RL = 0x2
3794 11:45:36.335211 BL = 0x2
3795 11:45:36.337501 RPST = 0x0
3796 11:45:36.337575 RD_PRE = 0x0
3797 11:45:36.340888 WR_PRE = 0x1
3798 11:45:36.344143 WR_PST = 0x0
3799 11:45:36.344221 DBI_WR = 0x0
3800 11:45:36.347524 DBI_RD = 0x0
3801 11:45:36.347597 OTF = 0x1
3802 11:45:36.350420 ===================================
3803 11:45:36.353808 ===================================
3804 11:45:36.357306 ANA top config
3805 11:45:36.360187 ===================================
3806 11:45:36.360269 DLL_ASYNC_EN = 0
3807 11:45:36.363771 ALL_SLAVE_EN = 1
3808 11:45:36.367421 NEW_RANK_MODE = 1
3809 11:45:36.370758 DLL_IDLE_MODE = 1
3810 11:45:36.370837 LP45_APHY_COMB_EN = 1
3811 11:45:36.373507 TX_ODT_DIS = 1
3812 11:45:36.376864 NEW_8X_MODE = 1
3813 11:45:36.380717 ===================================
3814 11:45:36.383430 ===================================
3815 11:45:36.386924 data_rate = 1200
3816 11:45:36.390195 CKR = 1
3817 11:45:36.393622 DQ_P2S_RATIO = 8
3818 11:45:36.396721 ===================================
3819 11:45:36.396799 CA_P2S_RATIO = 8
3820 11:45:36.399870 DQ_CA_OPEN = 0
3821 11:45:36.403201 DQ_SEMI_OPEN = 0
3822 11:45:36.406544 CA_SEMI_OPEN = 0
3823 11:45:36.409887 CA_FULL_RATE = 0
3824 11:45:36.413257 DQ_CKDIV4_EN = 1
3825 11:45:36.413355 CA_CKDIV4_EN = 1
3826 11:45:36.416460 CA_PREDIV_EN = 0
3827 11:45:36.419529 PH8_DLY = 0
3828 11:45:36.422708 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3829 11:45:36.426200 DQ_AAMCK_DIV = 4
3830 11:45:36.430020 CA_AAMCK_DIV = 4
3831 11:45:36.432979 CA_ADMCK_DIV = 4
3832 11:45:36.433078 DQ_TRACK_CA_EN = 0
3833 11:45:36.436202 CA_PICK = 600
3834 11:45:36.439431 CA_MCKIO = 600
3835 11:45:36.442483 MCKIO_SEMI = 0
3836 11:45:36.445794 PLL_FREQ = 2288
3837 11:45:36.449043 DQ_UI_PI_RATIO = 32
3838 11:45:36.452732 CA_UI_PI_RATIO = 0
3839 11:45:36.455816 ===================================
3840 11:45:36.458893 ===================================
3841 11:45:36.458998 memory_type:LPDDR4
3842 11:45:36.462461 GP_NUM : 10
3843 11:45:36.465647 SRAM_EN : 1
3844 11:45:36.465748 MD32_EN : 0
3845 11:45:36.469421 ===================================
3846 11:45:36.471951 [ANA_INIT] >>>>>>>>>>>>>>
3847 11:45:36.475389 <<<<<< [CONFIGURE PHASE]: ANA_TX
3848 11:45:36.478754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3849 11:45:36.482085 ===================================
3850 11:45:36.485585 data_rate = 1200,PCW = 0X5800
3851 11:45:36.488334 ===================================
3852 11:45:36.491635 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3853 11:45:36.495665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 11:45:36.501581 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3855 11:45:36.505239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3856 11:45:36.508610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3857 11:45:36.514740 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3858 11:45:36.514822 [ANA_INIT] flow start
3859 11:45:36.518462 [ANA_INIT] PLL >>>>>>>>
3860 11:45:36.521287 [ANA_INIT] PLL <<<<<<<<
3861 11:45:36.521388 [ANA_INIT] MIDPI >>>>>>>>
3862 11:45:36.524698 [ANA_INIT] MIDPI <<<<<<<<
3863 11:45:36.528040 [ANA_INIT] DLL >>>>>>>>
3864 11:45:36.528147 [ANA_INIT] flow end
3865 11:45:36.534521 ============ LP4 DIFF to SE enter ============
3866 11:45:36.537988 ============ LP4 DIFF to SE exit ============
3867 11:45:36.540941 [ANA_INIT] <<<<<<<<<<<<<
3868 11:45:36.541044 [Flow] Enable top DCM control >>>>>
3869 11:45:36.544618 [Flow] Enable top DCM control <<<<<
3870 11:45:36.547496 Enable DLL master slave shuffle
3871 11:45:36.554513 ==============================================================
3872 11:45:36.557526 Gating Mode config
3873 11:45:36.560856 ==============================================================
3874 11:45:36.564437 Config description:
3875 11:45:36.573928 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3876 11:45:36.580515 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3877 11:45:36.584342 SELPH_MODE 0: By rank 1: By Phase
3878 11:45:36.591174 ==============================================================
3879 11:45:36.594014 GAT_TRACK_EN = 1
3880 11:45:36.597296 RX_GATING_MODE = 2
3881 11:45:36.600421 RX_GATING_TRACK_MODE = 2
3882 11:45:36.603397 SELPH_MODE = 1
3883 11:45:36.607115 PICG_EARLY_EN = 1
3884 11:45:36.607222 VALID_LAT_VALUE = 1
3885 11:45:36.613363 ==============================================================
3886 11:45:36.616903 Enter into Gating configuration >>>>
3887 11:45:36.620159 Exit from Gating configuration <<<<
3888 11:45:36.623518 Enter into DVFS_PRE_config >>>>>
3889 11:45:36.633070 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3890 11:45:36.636779 Exit from DVFS_PRE_config <<<<<
3891 11:45:36.639689 Enter into PICG configuration >>>>
3892 11:45:36.643133 Exit from PICG configuration <<<<
3893 11:45:36.646790 [RX_INPUT] configuration >>>>>
3894 11:45:36.649723 [RX_INPUT] configuration <<<<<
3895 11:45:36.656214 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3896 11:45:36.659555 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3897 11:45:36.666576 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 11:45:36.673249 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 11:45:36.679403 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 11:45:36.686560 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 11:45:36.689297 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3902 11:45:36.693063 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3903 11:45:36.696176 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3904 11:45:36.702649 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3905 11:45:36.706205 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3906 11:45:36.709425 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3907 11:45:36.712749 ===================================
3908 11:45:36.715798 LPDDR4 DRAM CONFIGURATION
3909 11:45:36.719496 ===================================
3910 11:45:36.719619 EX_ROW_EN[0] = 0x0
3911 11:45:36.722454 EX_ROW_EN[1] = 0x0
3912 11:45:36.725778 LP4Y_EN = 0x0
3913 11:45:36.725883 WORK_FSP = 0x0
3914 11:45:36.729248 WL = 0x2
3915 11:45:36.729351 RL = 0x2
3916 11:45:36.732482 BL = 0x2
3917 11:45:36.732559 RPST = 0x0
3918 11:45:36.735719 RD_PRE = 0x0
3919 11:45:36.735797 WR_PRE = 0x1
3920 11:45:36.739273 WR_PST = 0x0
3921 11:45:36.739350 DBI_WR = 0x0
3922 11:45:36.742369 DBI_RD = 0x0
3923 11:45:36.742445 OTF = 0x1
3924 11:45:36.745632 ===================================
3925 11:45:36.748887 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3926 11:45:36.755710 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3927 11:45:36.759093 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 11:45:36.762146 ===================================
3929 11:45:36.765434 LPDDR4 DRAM CONFIGURATION
3930 11:45:36.768924 ===================================
3931 11:45:36.769027 EX_ROW_EN[0] = 0x10
3932 11:45:36.772279 EX_ROW_EN[1] = 0x0
3933 11:45:36.775310 LP4Y_EN = 0x0
3934 11:45:36.775389 WORK_FSP = 0x0
3935 11:45:36.778805 WL = 0x2
3936 11:45:36.778897 RL = 0x2
3937 11:45:36.781771 BL = 0x2
3938 11:45:36.781879 RPST = 0x0
3939 11:45:36.785147 RD_PRE = 0x0
3940 11:45:36.785250 WR_PRE = 0x1
3941 11:45:36.788361 WR_PST = 0x0
3942 11:45:36.788462 DBI_WR = 0x0
3943 11:45:36.791658 DBI_RD = 0x0
3944 11:45:36.791767 OTF = 0x1
3945 11:45:36.795093 ===================================
3946 11:45:36.801831 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3947 11:45:36.806526 nWR fixed to 30
3948 11:45:36.809748 [ModeRegInit_LP4] CH0 RK0
3949 11:45:36.809851 [ModeRegInit_LP4] CH0 RK1
3950 11:45:36.813037 [ModeRegInit_LP4] CH1 RK0
3951 11:45:36.816213 [ModeRegInit_LP4] CH1 RK1
3952 11:45:36.816320 match AC timing 17
3953 11:45:36.822609 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3954 11:45:36.826097 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3955 11:45:36.829414 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3956 11:45:36.835956 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3957 11:45:36.839164 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3958 11:45:36.839269 ==
3959 11:45:36.842385 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 11:45:36.845769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 11:45:36.845872 ==
3962 11:45:36.852307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 11:45:36.858893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3964 11:45:36.862517 [CA 0] Center 36 (6~67) winsize 62
3965 11:45:36.865894 [CA 1] Center 36 (6~67) winsize 62
3966 11:45:36.868898 [CA 2] Center 34 (4~65) winsize 62
3967 11:45:36.872532 [CA 3] Center 34 (4~65) winsize 62
3968 11:45:36.875941 [CA 4] Center 33 (3~64) winsize 62
3969 11:45:36.878765 [CA 5] Center 33 (3~64) winsize 62
3970 11:45:36.878874
3971 11:45:36.882431 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3972 11:45:36.882507
3973 11:45:36.885785 [CATrainingPosCal] consider 1 rank data
3974 11:45:36.888734 u2DelayCellTimex100 = 270/100 ps
3975 11:45:36.892196 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3976 11:45:36.895352 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3977 11:45:36.898412 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3978 11:45:36.905258 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3979 11:45:36.908474 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 11:45:36.911555 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 11:45:36.911663
3982 11:45:36.915007 CA PerBit enable=1, Macro0, CA PI delay=33
3983 11:45:36.915110
3984 11:45:36.918610 [CBTSetCACLKResult] CA Dly = 33
3985 11:45:36.918684 CS Dly: 5 (0~36)
3986 11:45:36.918761 ==
3987 11:45:36.921518 Dram Type= 6, Freq= 0, CH_0, rank 1
3988 11:45:36.928883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 11:45:36.928990 ==
3990 11:45:36.931488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 11:45:36.938402 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3992 11:45:36.941873 [CA 0] Center 36 (6~67) winsize 62
3993 11:45:36.944890 [CA 1] Center 36 (6~67) winsize 62
3994 11:45:36.948204 [CA 2] Center 34 (4~65) winsize 62
3995 11:45:36.951408 [CA 3] Center 34 (4~65) winsize 62
3996 11:45:36.955003 [CA 4] Center 34 (3~65) winsize 63
3997 11:45:36.958121 [CA 5] Center 33 (3~64) winsize 62
3998 11:45:36.958240
3999 11:45:36.961416 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4000 11:45:36.961529
4001 11:45:36.964919 [CATrainingPosCal] consider 2 rank data
4002 11:45:36.967772 u2DelayCellTimex100 = 270/100 ps
4003 11:45:36.971419 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4004 11:45:36.977803 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4005 11:45:36.981039 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 11:45:36.984610 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4007 11:45:36.987541 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 11:45:36.991045 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4009 11:45:36.991150
4010 11:45:36.994177 CA PerBit enable=1, Macro0, CA PI delay=33
4011 11:45:36.994324
4012 11:45:36.997244 [CBTSetCACLKResult] CA Dly = 33
4013 11:45:37.000665 CS Dly: 5 (0~36)
4014 11:45:37.000757
4015 11:45:37.003829 ----->DramcWriteLeveling(PI) begin...
4016 11:45:37.003915 ==
4017 11:45:37.007393 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 11:45:37.010607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 11:45:37.010681 ==
4020 11:45:37.013832 Write leveling (Byte 0): 33 => 33
4021 11:45:37.017261 Write leveling (Byte 1): 29 => 29
4022 11:45:37.020267 DramcWriteLeveling(PI) end<-----
4023 11:45:37.020339
4024 11:45:37.020417 ==
4025 11:45:37.023839 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 11:45:37.027378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 11:45:37.027452 ==
4028 11:45:37.030137 [Gating] SW mode calibration
4029 11:45:37.037030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4030 11:45:37.043891 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4031 11:45:37.046836 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 11:45:37.053438 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 11:45:37.056227 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 11:45:37.059642 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4035 11:45:37.066480 0 9 16 | B1->B0 | 2f2f 2a2a | 0 0 | (0 1) (0 0)
4036 11:45:37.069495 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 11:45:37.073292 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 11:45:37.079578 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 11:45:37.082485 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 11:45:37.085975 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 11:45:37.092513 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 11:45:37.095881 0 10 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
4043 11:45:37.099217 0 10 16 | B1->B0 | 3b3b 4343 | 1 0 | (0 0) (0 0)
4044 11:45:37.106187 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 11:45:37.109396 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 11:45:37.112358 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 11:45:37.119549 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 11:45:37.122322 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 11:45:37.126099 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 11:45:37.132457 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 11:45:37.135775 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 11:45:37.138547 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 11:45:37.145389 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 11:45:37.148544 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 11:45:37.151642 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 11:45:37.158669 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 11:45:37.161597 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 11:45:37.165068 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 11:45:37.171894 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 11:45:37.175013 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:45:37.178377 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:45:37.184962 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 11:45:37.187928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:45:37.191741 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 11:45:37.197727 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 11:45:37.201093 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 11:45:37.204273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4068 11:45:37.211055 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 11:45:37.211139 Total UI for P1: 0, mck2ui 16
4070 11:45:37.217908 best dqsien dly found for B0: ( 0, 13, 16)
4071 11:45:37.218015 Total UI for P1: 0, mck2ui 16
4072 11:45:37.224287 best dqsien dly found for B1: ( 0, 13, 18)
4073 11:45:37.227651 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4074 11:45:37.231042 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4075 11:45:37.231129
4076 11:45:37.234752 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4077 11:45:37.237317 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4078 11:45:37.240898 [Gating] SW calibration Done
4079 11:45:37.240974 ==
4080 11:45:37.244489 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 11:45:37.247626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 11:45:37.247702 ==
4083 11:45:37.250550 RX Vref Scan: 0
4084 11:45:37.250624
4085 11:45:37.254120 RX Vref 0 -> 0, step: 1
4086 11:45:37.254225
4087 11:45:37.254348 RX Delay -230 -> 252, step: 16
4088 11:45:37.260715 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4089 11:45:37.264473 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4090 11:45:37.267352 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4091 11:45:37.270753 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4092 11:45:37.277074 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4093 11:45:37.280146 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4094 11:45:37.283988 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4095 11:45:37.287008 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4096 11:45:37.293734 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4097 11:45:37.297050 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4098 11:45:37.300078 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4099 11:45:37.303447 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4100 11:45:37.310039 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4101 11:45:37.313437 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4102 11:45:37.316257 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4103 11:45:37.319887 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4104 11:45:37.319962 ==
4105 11:45:37.323330 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 11:45:37.329852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 11:45:37.329930 ==
4108 11:45:37.330033 DQS Delay:
4109 11:45:37.333286 DQS0 = 0, DQS1 = 0
4110 11:45:37.333359 DQM Delay:
4111 11:45:37.333438 DQM0 = 43, DQM1 = 34
4112 11:45:37.335984 DQ Delay:
4113 11:45:37.339701 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4114 11:45:37.342721 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4115 11:45:37.346018 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4116 11:45:37.349517 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4117 11:45:37.349620
4118 11:45:37.349714
4119 11:45:37.349801 ==
4120 11:45:37.352771 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 11:45:37.355847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 11:45:37.355950 ==
4123 11:45:37.356042
4124 11:45:37.356133
4125 11:45:37.359593 TX Vref Scan disable
4126 11:45:37.362748 == TX Byte 0 ==
4127 11:45:37.365934 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4128 11:45:37.369190 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4129 11:45:37.372370 == TX Byte 1 ==
4130 11:45:37.375578 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4131 11:45:37.378721 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4132 11:45:37.378825 ==
4133 11:45:37.382046 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 11:45:37.388498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 11:45:37.388603 ==
4136 11:45:37.388695
4137 11:45:37.388790
4138 11:45:37.388876 TX Vref Scan disable
4139 11:45:37.392962 == TX Byte 0 ==
4140 11:45:37.396872 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4141 11:45:37.402742 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4142 11:45:37.402849 == TX Byte 1 ==
4143 11:45:37.406131 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4144 11:45:37.412662 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4145 11:45:37.412741
4146 11:45:37.412823 [DATLAT]
4147 11:45:37.412900 Freq=600, CH0 RK0
4148 11:45:37.412975
4149 11:45:37.416310 DATLAT Default: 0x9
4150 11:45:37.419055 0, 0xFFFF, sum = 0
4151 11:45:37.419131 1, 0xFFFF, sum = 0
4152 11:45:37.422472 2, 0xFFFF, sum = 0
4153 11:45:37.422552 3, 0xFFFF, sum = 0
4154 11:45:37.425946 4, 0xFFFF, sum = 0
4155 11:45:37.426021 5, 0xFFFF, sum = 0
4156 11:45:37.429427 6, 0xFFFF, sum = 0
4157 11:45:37.429504 7, 0xFFFF, sum = 0
4158 11:45:37.432397 8, 0x0, sum = 1
4159 11:45:37.432472 9, 0x0, sum = 2
4160 11:45:37.436300 10, 0x0, sum = 3
4161 11:45:37.436373 11, 0x0, sum = 4
4162 11:45:37.436453 best_step = 9
4163 11:45:37.436527
4164 11:45:37.439404 ==
4165 11:45:37.442452 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 11:45:37.445625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 11:45:37.445704 ==
4168 11:45:37.445785 RX Vref Scan: 1
4169 11:45:37.445863
4170 11:45:37.448921 RX Vref 0 -> 0, step: 1
4171 11:45:37.448993
4172 11:45:37.452395 RX Delay -195 -> 252, step: 8
4173 11:45:37.452482
4174 11:45:37.455854 Set Vref, RX VrefLevel [Byte0]: 56
4175 11:45:37.458772 [Byte1]: 50
4176 11:45:37.458850
4177 11:45:37.462354 Final RX Vref Byte 0 = 56 to rank0
4178 11:45:37.465699 Final RX Vref Byte 1 = 50 to rank0
4179 11:45:37.468804 Final RX Vref Byte 0 = 56 to rank1
4180 11:45:37.471902 Final RX Vref Byte 1 = 50 to rank1==
4181 11:45:37.475481 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 11:45:37.482001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 11:45:37.482081 ==
4184 11:45:37.482179 DQS Delay:
4185 11:45:37.482301 DQS0 = 0, DQS1 = 0
4186 11:45:37.485154 DQM Delay:
4187 11:45:37.485227 DQM0 = 44, DQM1 = 36
4188 11:45:37.489103 DQ Delay:
4189 11:45:37.492188 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4190 11:45:37.495034 DQ4 =48, DQ5 =36, DQ6 =56, DQ7 =48
4191 11:45:37.495122 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4192 11:45:37.501991 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4193 11:45:37.502107
4194 11:45:37.502201
4195 11:45:37.508735 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4196 11:45:37.511865 CH0 RK0: MR19=808, MR18=4D44
4197 11:45:37.518236 CH0_RK0: MR19=0x808, MR18=0x4D44, DQSOSC=395, MR23=63, INC=168, DEC=112
4198 11:45:37.518356
4199 11:45:37.521342 ----->DramcWriteLeveling(PI) begin...
4200 11:45:37.521419 ==
4201 11:45:37.524786 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 11:45:37.528337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 11:45:37.528442 ==
4204 11:45:37.531805 Write leveling (Byte 0): 31 => 31
4205 11:45:37.534633 Write leveling (Byte 1): 31 => 31
4206 11:45:37.537948 DramcWriteLeveling(PI) end<-----
4207 11:45:37.538046
4208 11:45:37.538139 ==
4209 11:45:37.541572 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 11:45:37.544700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 11:45:37.548160 ==
4212 11:45:37.548265 [Gating] SW mode calibration
4213 11:45:37.557943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4214 11:45:37.560892 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4215 11:45:37.564333 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 11:45:37.571146 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 11:45:37.574054 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4218 11:45:37.577376 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
4219 11:45:37.584058 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4220 11:45:37.587758 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 11:45:37.591242 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 11:45:37.597246 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 11:45:37.601116 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 11:45:37.604261 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 11:45:37.610549 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 11:45:37.614133 0 10 12 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (0 0)
4227 11:45:37.617071 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4228 11:45:37.623803 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 11:45:37.626858 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 11:45:37.630409 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 11:45:37.637079 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 11:45:37.640145 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 11:45:37.643268 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 11:45:37.650137 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4235 11:45:37.653382 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4236 11:45:37.656455 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 11:45:37.663376 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 11:45:37.666862 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:45:37.670133 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:45:37.676255 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:45:37.679874 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:45:37.682952 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:45:37.689813 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:45:37.693103 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:45:37.696113 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:45:37.702591 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:45:37.706031 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:45:37.709567 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:45:37.716112 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:45:37.719144 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4251 11:45:37.722515 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:45:37.725705 Total UI for P1: 0, mck2ui 16
4253 11:45:37.729369 best dqsien dly found for B0: ( 0, 13, 12)
4254 11:45:37.732131 Total UI for P1: 0, mck2ui 16
4255 11:45:37.735597 best dqsien dly found for B1: ( 0, 13, 12)
4256 11:45:37.739092 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4257 11:45:37.742749 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4258 11:45:37.745841
4259 11:45:37.748895 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4260 11:45:37.752325 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4261 11:45:37.755657 [Gating] SW calibration Done
4262 11:45:37.755788 ==
4263 11:45:37.758835 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 11:45:37.762393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 11:45:37.762468 ==
4266 11:45:37.765106 RX Vref Scan: 0
4267 11:45:37.765205
4268 11:45:37.765295 RX Vref 0 -> 0, step: 1
4269 11:45:37.765368
4270 11:45:37.768956 RX Delay -230 -> 252, step: 16
4271 11:45:37.772514 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4272 11:45:37.778515 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4273 11:45:37.781602 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4274 11:45:37.785057 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4275 11:45:37.788306 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4276 11:45:37.795008 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4277 11:45:37.798612 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4278 11:45:37.801422 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4279 11:45:37.804730 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4280 11:45:37.808493 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4281 11:45:37.814498 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4282 11:45:37.817926 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4283 11:45:37.821548 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4284 11:45:37.824968 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4285 11:45:37.831097 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4286 11:45:37.834335 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4287 11:45:37.834411 ==
4288 11:45:37.837498 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 11:45:37.841030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 11:45:37.841130 ==
4291 11:45:37.844173 DQS Delay:
4292 11:45:37.844282 DQS0 = 0, DQS1 = 0
4293 11:45:37.847664 DQM Delay:
4294 11:45:37.847767 DQM0 = 46, DQM1 = 36
4295 11:45:37.847858 DQ Delay:
4296 11:45:37.851047 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4297 11:45:37.853914 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4298 11:45:37.857313 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4299 11:45:37.860865 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4300 11:45:37.860966
4301 11:45:37.864042
4302 11:45:37.864151 ==
4303 11:45:37.867010 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 11:45:37.870826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 11:45:37.870902 ==
4306 11:45:37.870972
4307 11:45:37.871031
4308 11:45:37.873781 TX Vref Scan disable
4309 11:45:37.873889 == TX Byte 0 ==
4310 11:45:37.880283 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4311 11:45:37.883616 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4312 11:45:37.883726 == TX Byte 1 ==
4313 11:45:37.890559 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4314 11:45:37.893904 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4315 11:45:37.894006 ==
4316 11:45:37.896604 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 11:45:37.899938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 11:45:37.900041 ==
4319 11:45:37.900143
4320 11:45:37.900232
4321 11:45:37.903301 TX Vref Scan disable
4322 11:45:37.906725 == TX Byte 0 ==
4323 11:45:37.909660 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4324 11:45:37.916553 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4325 11:45:37.916659 == TX Byte 1 ==
4326 11:45:37.920004 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4327 11:45:37.926438 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4328 11:45:37.926522
4329 11:45:37.926587 [DATLAT]
4330 11:45:37.926671 Freq=600, CH0 RK1
4331 11:45:37.926739
4332 11:45:37.929787 DATLAT Default: 0x9
4333 11:45:37.929897 0, 0xFFFF, sum = 0
4334 11:45:37.932876 1, 0xFFFF, sum = 0
4335 11:45:37.936358 2, 0xFFFF, sum = 0
4336 11:45:37.936460 3, 0xFFFF, sum = 0
4337 11:45:37.939443 4, 0xFFFF, sum = 0
4338 11:45:37.939546 5, 0xFFFF, sum = 0
4339 11:45:37.942668 6, 0xFFFF, sum = 0
4340 11:45:37.942746 7, 0xFFFF, sum = 0
4341 11:45:37.946440 8, 0x0, sum = 1
4342 11:45:37.946518 9, 0x0, sum = 2
4343 11:45:37.949667 10, 0x0, sum = 3
4344 11:45:37.949744 11, 0x0, sum = 4
4345 11:45:37.949808 best_step = 9
4346 11:45:37.949898
4347 11:45:37.953275 ==
4348 11:45:37.953367 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 11:45:37.959147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 11:45:37.959248 ==
4351 11:45:37.959343 RX Vref Scan: 0
4352 11:45:37.959431
4353 11:45:37.962717 RX Vref 0 -> 0, step: 1
4354 11:45:37.962791
4355 11:45:37.966064 RX Delay -179 -> 252, step: 8
4356 11:45:37.972304 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4357 11:45:37.975573 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4358 11:45:37.979019 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4359 11:45:37.982431 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4360 11:45:37.985504 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4361 11:45:37.992675 iDelay=205, Bit 5, Center 36 (-107 ~ 180) 288
4362 11:45:37.995730 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4363 11:45:37.998933 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4364 11:45:38.002165 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4365 11:45:38.008768 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4366 11:45:38.012201 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4367 11:45:38.015586 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4368 11:45:38.019092 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4369 11:45:38.025465 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4370 11:45:38.028394 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4371 11:45:38.031879 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4372 11:45:38.031952 ==
4373 11:45:38.034905 Dram Type= 6, Freq= 0, CH_0, rank 1
4374 11:45:38.038282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 11:45:38.038366 ==
4376 11:45:38.041370 DQS Delay:
4377 11:45:38.041442 DQS0 = 0, DQS1 = 0
4378 11:45:38.044991 DQM Delay:
4379 11:45:38.045061 DQM0 = 44, DQM1 = 37
4380 11:45:38.048372 DQ Delay:
4381 11:45:38.048442 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4382 11:45:38.051518 DQ4 =48, DQ5 =36, DQ6 =56, DQ7 =48
4383 11:45:38.054811 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4384 11:45:38.058317 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4385 11:45:38.058389
4386 11:45:38.061157
4387 11:45:38.068067 [DQSOSCAuto] RK1, (LSB)MR18= 0x433f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4388 11:45:38.070997 CH0 RK1: MR19=808, MR18=433F
4389 11:45:38.077988 CH0_RK1: MR19=0x808, MR18=0x433F, DQSOSC=397, MR23=63, INC=166, DEC=110
4390 11:45:38.080871 [RxdqsGatingPostProcess] freq 600
4391 11:45:38.084451 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4392 11:45:38.087729 Pre-setting of DQS Precalculation
4393 11:45:38.094187 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4394 11:45:38.094323 ==
4395 11:45:38.097509 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 11:45:38.100705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 11:45:38.100779 ==
4398 11:45:38.107758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 11:45:38.111046 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4400 11:45:38.115428 [CA 0] Center 36 (6~66) winsize 61
4401 11:45:38.118653 [CA 1] Center 35 (5~66) winsize 62
4402 11:45:38.121505 [CA 2] Center 34 (4~65) winsize 62
4403 11:45:38.124897 [CA 3] Center 34 (4~65) winsize 62
4404 11:45:38.128282 [CA 4] Center 34 (4~65) winsize 62
4405 11:45:38.131589 [CA 5] Center 33 (3~64) winsize 62
4406 11:45:38.131688
4407 11:45:38.135114 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4408 11:45:38.135193
4409 11:45:38.138636 [CATrainingPosCal] consider 1 rank data
4410 11:45:38.141757 u2DelayCellTimex100 = 270/100 ps
4411 11:45:38.144690 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4412 11:45:38.151330 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4413 11:45:38.154988 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 11:45:38.157989 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 11:45:38.161302 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 11:45:38.164879 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 11:45:38.164957
4418 11:45:38.168352 CA PerBit enable=1, Macro0, CA PI delay=33
4419 11:45:38.168425
4420 11:45:38.171382 [CBTSetCACLKResult] CA Dly = 33
4421 11:45:38.174678 CS Dly: 4 (0~35)
4422 11:45:38.174780 ==
4423 11:45:38.178179 Dram Type= 6, Freq= 0, CH_1, rank 1
4424 11:45:38.181627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 11:45:38.181729 ==
4426 11:45:38.187948 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4427 11:45:38.191311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4428 11:45:38.195116 [CA 0] Center 35 (5~66) winsize 62
4429 11:45:38.198631 [CA 1] Center 36 (6~66) winsize 61
4430 11:45:38.201962 [CA 2] Center 34 (4~65) winsize 62
4431 11:45:38.205049 [CA 3] Center 33 (3~64) winsize 62
4432 11:45:38.208506 [CA 4] Center 34 (4~64) winsize 61
4433 11:45:38.211570 [CA 5] Center 33 (3~64) winsize 62
4434 11:45:38.211647
4435 11:45:38.214816 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4436 11:45:38.214914
4437 11:45:38.218320 [CATrainingPosCal] consider 2 rank data
4438 11:45:38.221481 u2DelayCellTimex100 = 270/100 ps
4439 11:45:38.225279 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4440 11:45:38.231634 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4441 11:45:38.234781 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 11:45:38.237973 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4443 11:45:38.241317 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4444 11:45:38.244720 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 11:45:38.244822
4446 11:45:38.247671 CA PerBit enable=1, Macro0, CA PI delay=33
4447 11:45:38.247763
4448 11:45:38.251200 [CBTSetCACLKResult] CA Dly = 33
4449 11:45:38.254461 CS Dly: 5 (0~37)
4450 11:45:38.254560
4451 11:45:38.257899 ----->DramcWriteLeveling(PI) begin...
4452 11:45:38.258008 ==
4453 11:45:38.261067 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 11:45:38.264319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 11:45:38.264396 ==
4456 11:45:38.267578 Write leveling (Byte 0): 27 => 27
4457 11:45:38.271155 Write leveling (Byte 1): 30 => 30
4458 11:45:38.274056 DramcWriteLeveling(PI) end<-----
4459 11:45:38.274164
4460 11:45:38.274275 ==
4461 11:45:38.277494 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 11:45:38.281014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 11:45:38.281126 ==
4464 11:45:38.283992 [Gating] SW mode calibration
4465 11:45:38.291160 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4466 11:45:38.297153 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4467 11:45:38.300523 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 11:45:38.307011 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 11:45:38.310397 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 11:45:38.313863 0 9 12 | B1->B0 | 3131 3232 | 1 1 | (1 1) (1 1)
4471 11:45:38.320916 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 11:45:38.323728 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 11:45:38.326599 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 11:45:38.333603 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 11:45:38.336626 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 11:45:38.339930 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 11:45:38.346348 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 11:45:38.350425 0 10 12 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
4479 11:45:38.352960 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 11:45:38.359354 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 11:45:38.362903 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 11:45:38.366355 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 11:45:38.372693 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 11:45:38.376182 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 11:45:38.379577 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 11:45:38.386054 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4487 11:45:38.389579 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 11:45:38.392535 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 11:45:38.399373 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 11:45:38.402760 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 11:45:38.406141 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 11:45:38.412341 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 11:45:38.415951 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 11:45:38.418803 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 11:45:38.425710 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 11:45:38.428811 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 11:45:38.431999 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 11:45:38.439134 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:45:38.441961 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 11:45:38.445406 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 11:45:38.451881 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:45:38.454979 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 11:45:38.458445 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:45:38.462383 Total UI for P1: 0, mck2ui 16
4505 11:45:38.465305 best dqsien dly found for B0: ( 0, 13, 14)
4506 11:45:38.468539 Total UI for P1: 0, mck2ui 16
4507 11:45:38.471465 best dqsien dly found for B1: ( 0, 13, 14)
4508 11:45:38.475224 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4509 11:45:38.478453 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4510 11:45:38.478530
4511 11:45:38.484838 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4512 11:45:38.488349 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4513 11:45:38.491255 [Gating] SW calibration Done
4514 11:45:38.491358 ==
4515 11:45:38.494706 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 11:45:38.498104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 11:45:38.498207 ==
4518 11:45:38.498337 RX Vref Scan: 0
4519 11:45:38.498402
4520 11:45:38.501042 RX Vref 0 -> 0, step: 1
4521 11:45:38.501118
4522 11:45:38.504444 RX Delay -230 -> 252, step: 16
4523 11:45:38.508166 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4524 11:45:38.514643 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4525 11:45:38.518199 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4526 11:45:38.520865 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4527 11:45:38.524307 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4528 11:45:38.527888 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4529 11:45:38.534285 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4530 11:45:38.537553 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4531 11:45:38.540908 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4532 11:45:38.544068 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4533 11:45:38.550623 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4534 11:45:38.553782 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4535 11:45:38.557419 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4536 11:45:38.560278 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4537 11:45:38.567155 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4538 11:45:38.570140 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4539 11:45:38.570244 ==
4540 11:45:38.573485 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 11:45:38.576958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 11:45:38.577064 ==
4543 11:45:38.579946 DQS Delay:
4544 11:45:38.580049 DQS0 = 0, DQS1 = 0
4545 11:45:38.580144 DQM Delay:
4546 11:45:38.583368 DQM0 = 44, DQM1 = 39
4547 11:45:38.583472 DQ Delay:
4548 11:45:38.587169 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4549 11:45:38.590444 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4550 11:45:38.593538 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4551 11:45:38.596864 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4552 11:45:38.596970
4553 11:45:38.597064
4554 11:45:38.597163 ==
4555 11:45:38.600366 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 11:45:38.606696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 11:45:38.606783 ==
4558 11:45:38.606869
4559 11:45:38.606952
4560 11:45:38.609550 TX Vref Scan disable
4561 11:45:38.609625 == TX Byte 0 ==
4562 11:45:38.613115 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4563 11:45:38.619438 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4564 11:45:38.619518 == TX Byte 1 ==
4565 11:45:38.626648 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4566 11:45:38.629652 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4567 11:45:38.629737 ==
4568 11:45:38.632656 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 11:45:38.636171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 11:45:38.636257 ==
4571 11:45:38.636342
4572 11:45:38.636421
4573 11:45:38.639594 TX Vref Scan disable
4574 11:45:38.642952 == TX Byte 0 ==
4575 11:45:38.646126 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4576 11:45:38.649456 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4577 11:45:38.652403 == TX Byte 1 ==
4578 11:45:38.656007 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4579 11:45:38.659250 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4580 11:45:38.662919
4581 11:45:38.662997 [DATLAT]
4582 11:45:38.663063 Freq=600, CH1 RK0
4583 11:45:38.663124
4584 11:45:38.665628 DATLAT Default: 0x9
4585 11:45:38.665696 0, 0xFFFF, sum = 0
4586 11:45:38.669043 1, 0xFFFF, sum = 0
4587 11:45:38.669153 2, 0xFFFF, sum = 0
4588 11:45:38.672422 3, 0xFFFF, sum = 0
4589 11:45:38.672532 4, 0xFFFF, sum = 0
4590 11:45:38.676043 5, 0xFFFF, sum = 0
4591 11:45:38.678699 6, 0xFFFF, sum = 0
4592 11:45:38.678777 7, 0xFFFF, sum = 0
4593 11:45:38.682381 8, 0x0, sum = 1
4594 11:45:38.682455 9, 0x0, sum = 2
4595 11:45:38.682519 10, 0x0, sum = 3
4596 11:45:38.685217 11, 0x0, sum = 4
4597 11:45:38.685320 best_step = 9
4598 11:45:38.685409
4599 11:45:38.685496 ==
4600 11:45:38.688834 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 11:45:38.695579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 11:45:38.695685 ==
4603 11:45:38.695778 RX Vref Scan: 1
4604 11:45:38.695878
4605 11:45:38.698647 RX Vref 0 -> 0, step: 1
4606 11:45:38.698727
4607 11:45:38.702070 RX Delay -179 -> 252, step: 8
4608 11:45:38.702169
4609 11:45:38.705388 Set Vref, RX VrefLevel [Byte0]: 52
4610 11:45:38.708616 [Byte1]: 52
4611 11:45:38.708721
4612 11:45:38.712004 Final RX Vref Byte 0 = 52 to rank0
4613 11:45:38.714750 Final RX Vref Byte 1 = 52 to rank0
4614 11:45:38.718402 Final RX Vref Byte 0 = 52 to rank1
4615 11:45:38.721822 Final RX Vref Byte 1 = 52 to rank1==
4616 11:45:38.725163 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 11:45:38.728625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 11:45:38.728724 ==
4619 11:45:38.731729 DQS Delay:
4620 11:45:38.731828 DQS0 = 0, DQS1 = 0
4621 11:45:38.734880 DQM Delay:
4622 11:45:38.734951 DQM0 = 41, DQM1 = 33
4623 11:45:38.735016 DQ Delay:
4624 11:45:38.737836 DQ0 =48, DQ1 =40, DQ2 =28, DQ3 =40
4625 11:45:38.741319 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =32
4626 11:45:38.744685 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4627 11:45:38.748331 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4628 11:45:38.748431
4629 11:45:38.751071
4630 11:45:38.758184 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4631 11:45:38.761044 CH1 RK0: MR19=808, MR18=2B45
4632 11:45:38.767776 CH1_RK0: MR19=0x808, MR18=0x2B45, DQSOSC=396, MR23=63, INC=167, DEC=111
4633 11:45:38.767882
4634 11:45:38.771011 ----->DramcWriteLeveling(PI) begin...
4635 11:45:38.771085 ==
4636 11:45:38.774504 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 11:45:38.777700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 11:45:38.777777 ==
4639 11:45:38.781408 Write leveling (Byte 0): 30 => 30
4640 11:45:38.784721 Write leveling (Byte 1): 31 => 31
4641 11:45:38.787892 DramcWriteLeveling(PI) end<-----
4642 11:45:38.787998
4643 11:45:38.788097 ==
4644 11:45:38.790679 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 11:45:38.794535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 11:45:38.794619 ==
4647 11:45:38.797789 [Gating] SW mode calibration
4648 11:45:38.804330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4649 11:45:38.810880 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4650 11:45:38.813927 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 11:45:38.820309 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 11:45:38.823864 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4653 11:45:38.827339 0 9 12 | B1->B0 | 3131 2e2e | 1 0 | (1 0) (0 0)
4654 11:45:38.833591 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4655 11:45:38.837038 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 11:45:38.840277 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 11:45:38.847269 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 11:45:38.850055 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 11:45:38.853774 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 11:45:38.859838 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4661 11:45:38.863350 0 10 12 | B1->B0 | 2e2e 3838 | 0 0 | (0 0) (0 0)
4662 11:45:38.866629 0 10 16 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
4663 11:45:38.873344 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 11:45:38.876703 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 11:45:38.879532 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 11:45:38.885986 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 11:45:38.889756 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 11:45:38.892859 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 11:45:38.899337 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 11:45:38.902711 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 11:45:38.905715 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 11:45:38.912774 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 11:45:38.915748 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 11:45:38.919222 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 11:45:38.925558 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 11:45:38.928869 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 11:45:38.932077 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 11:45:38.938895 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 11:45:38.942043 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 11:45:38.945197 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 11:45:38.951636 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 11:45:38.955385 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 11:45:38.958524 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 11:45:38.965545 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4685 11:45:38.968342 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4686 11:45:38.971453 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 11:45:38.974787 Total UI for P1: 0, mck2ui 16
4688 11:45:38.978199 best dqsien dly found for B0: ( 0, 13, 10)
4689 11:45:38.981697 Total UI for P1: 0, mck2ui 16
4690 11:45:38.985031 best dqsien dly found for B1: ( 0, 13, 12)
4691 11:45:38.988461 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4692 11:45:38.991183 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4693 11:45:38.995095
4694 11:45:38.998132 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4695 11:45:39.001248 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4696 11:45:39.004629 [Gating] SW calibration Done
4697 11:45:39.004712 ==
4698 11:45:39.007657 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 11:45:39.011264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 11:45:39.011373 ==
4701 11:45:39.011472 RX Vref Scan: 0
4702 11:45:39.014776
4703 11:45:39.014851 RX Vref 0 -> 0, step: 1
4704 11:45:39.014912
4705 11:45:39.017726 RX Delay -230 -> 252, step: 16
4706 11:45:39.021256 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4707 11:45:39.027437 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4708 11:45:39.030857 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4709 11:45:39.033835 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4710 11:45:39.038059 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4711 11:45:39.043881 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4712 11:45:39.047641 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4713 11:45:39.050770 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4714 11:45:39.054066 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4715 11:45:39.057311 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4716 11:45:39.064332 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4717 11:45:39.067024 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4718 11:45:39.070361 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4719 11:45:39.073740 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4720 11:45:39.080501 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4721 11:45:39.083413 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4722 11:45:39.083518 ==
4723 11:45:39.086637 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 11:45:39.089925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 11:45:39.090029 ==
4726 11:45:39.093350 DQS Delay:
4727 11:45:39.093458 DQS0 = 0, DQS1 = 0
4728 11:45:39.096794 DQM Delay:
4729 11:45:39.096894 DQM0 = 43, DQM1 = 40
4730 11:45:39.096990 DQ Delay:
4731 11:45:39.099813 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4732 11:45:39.103040 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4733 11:45:39.106926 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4734 11:45:39.110057 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4735 11:45:39.110164
4736 11:45:39.110280
4737 11:45:39.113401 ==
4738 11:45:39.116258 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 11:45:39.119793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 11:45:39.119893 ==
4741 11:45:39.119982
4742 11:45:39.120068
4743 11:45:39.123391 TX Vref Scan disable
4744 11:45:39.123486 == TX Byte 0 ==
4745 11:45:39.129673 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4746 11:45:39.133119 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4747 11:45:39.133218 == TX Byte 1 ==
4748 11:45:39.139087 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4749 11:45:39.142506 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4750 11:45:39.142593 ==
4751 11:45:39.145958 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 11:45:39.149487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 11:45:39.149590 ==
4754 11:45:39.149681
4755 11:45:39.149767
4756 11:45:39.152755 TX Vref Scan disable
4757 11:45:39.156360 == TX Byte 0 ==
4758 11:45:39.158976 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4759 11:45:39.162588 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4760 11:45:39.165935 == TX Byte 1 ==
4761 11:45:39.169480 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4762 11:45:39.172694 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4763 11:45:39.175376
4764 11:45:39.175451 [DATLAT]
4765 11:45:39.175528 Freq=600, CH1 RK1
4766 11:45:39.175617
4767 11:45:39.179106 DATLAT Default: 0x9
4768 11:45:39.179180 0, 0xFFFF, sum = 0
4769 11:45:39.182288 1, 0xFFFF, sum = 0
4770 11:45:39.182401 2, 0xFFFF, sum = 0
4771 11:45:39.185646 3, 0xFFFF, sum = 0
4772 11:45:39.189044 4, 0xFFFF, sum = 0
4773 11:45:39.189147 5, 0xFFFF, sum = 0
4774 11:45:39.191914 6, 0xFFFF, sum = 0
4775 11:45:39.192021 7, 0xFFFF, sum = 0
4776 11:45:39.195714 8, 0x0, sum = 1
4777 11:45:39.195792 9, 0x0, sum = 2
4778 11:45:39.195856 10, 0x0, sum = 3
4779 11:45:39.199060 11, 0x0, sum = 4
4780 11:45:39.199139 best_step = 9
4781 11:45:39.199214
4782 11:45:39.199277 ==
4783 11:45:39.202048 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 11:45:39.208596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 11:45:39.208678 ==
4786 11:45:39.208744 RX Vref Scan: 0
4787 11:45:39.208811
4788 11:45:39.212125 RX Vref 0 -> 0, step: 1
4789 11:45:39.212203
4790 11:45:39.215131 RX Delay -179 -> 252, step: 8
4791 11:45:39.218704 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4792 11:45:39.225227 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4793 11:45:39.228966 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4794 11:45:39.231863 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4795 11:45:39.235259 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4796 11:45:39.241777 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4797 11:45:39.244772 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4798 11:45:39.248114 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4799 11:45:39.251284 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4800 11:45:39.258656 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4801 11:45:39.261013 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4802 11:45:39.264373 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4803 11:45:39.268287 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4804 11:45:39.274507 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4805 11:45:39.277384 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4806 11:45:39.280958 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4807 11:45:39.281037 ==
4808 11:45:39.284364 Dram Type= 6, Freq= 0, CH_1, rank 1
4809 11:45:39.287684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4810 11:45:39.290551 ==
4811 11:45:39.290634 DQS Delay:
4812 11:45:39.290718 DQS0 = 0, DQS1 = 0
4813 11:45:39.293917 DQM Delay:
4814 11:45:39.293999 DQM0 = 37, DQM1 = 35
4815 11:45:39.297376 DQ Delay:
4816 11:45:39.300413 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =32
4817 11:45:39.300496 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4818 11:45:39.303981 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4819 11:45:39.310430 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4820 11:45:39.310524
4821 11:45:39.310617
4822 11:45:39.317131 [DQSOSCAuto] RK1, (LSB)MR18= 0x355b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4823 11:45:39.320795 CH1 RK1: MR19=808, MR18=355B
4824 11:45:39.327181 CH1_RK1: MR19=0x808, MR18=0x355B, DQSOSC=392, MR23=63, INC=170, DEC=113
4825 11:45:39.330415 [RxdqsGatingPostProcess] freq 600
4826 11:45:39.333370 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4827 11:45:39.336813 Pre-setting of DQS Precalculation
4828 11:45:39.343421 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4829 11:45:39.349767 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4830 11:45:39.356368 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4831 11:45:39.356458
4832 11:45:39.356520
4833 11:45:39.359836 [Calibration Summary] 1200 Mbps
4834 11:45:39.359940 CH 0, Rank 0
4835 11:45:39.363486 SW Impedance : PASS
4836 11:45:39.366358 DUTY Scan : NO K
4837 11:45:39.366440 ZQ Calibration : PASS
4838 11:45:39.369735 Jitter Meter : NO K
4839 11:45:39.372823 CBT Training : PASS
4840 11:45:39.372925 Write leveling : PASS
4841 11:45:39.376243 RX DQS gating : PASS
4842 11:45:39.380001 RX DQ/DQS(RDDQC) : PASS
4843 11:45:39.380103 TX DQ/DQS : PASS
4844 11:45:39.383488 RX DATLAT : PASS
4845 11:45:39.386132 RX DQ/DQS(Engine): PASS
4846 11:45:39.386256 TX OE : NO K
4847 11:45:39.389671 All Pass.
4848 11:45:39.389783
4849 11:45:39.389872 CH 0, Rank 1
4850 11:45:39.392375 SW Impedance : PASS
4851 11:45:39.392491 DUTY Scan : NO K
4852 11:45:39.395591 ZQ Calibration : PASS
4853 11:45:39.399012 Jitter Meter : NO K
4854 11:45:39.399122 CBT Training : PASS
4855 11:45:39.402564 Write leveling : PASS
4856 11:45:39.405556 RX DQS gating : PASS
4857 11:45:39.405634 RX DQ/DQS(RDDQC) : PASS
4858 11:45:39.408819 TX DQ/DQS : PASS
4859 11:45:39.412330 RX DATLAT : PASS
4860 11:45:39.412433 RX DQ/DQS(Engine): PASS
4861 11:45:39.415843 TX OE : NO K
4862 11:45:39.415943 All Pass.
4863 11:45:39.416033
4864 11:45:39.419221 CH 1, Rank 0
4865 11:45:39.419320 SW Impedance : PASS
4866 11:45:39.422398 DUTY Scan : NO K
4867 11:45:39.426155 ZQ Calibration : PASS
4868 11:45:39.426265 Jitter Meter : NO K
4869 11:45:39.428959 CBT Training : PASS
4870 11:45:39.432273 Write leveling : PASS
4871 11:45:39.432377 RX DQS gating : PASS
4872 11:45:39.435169 RX DQ/DQS(RDDQC) : PASS
4873 11:45:39.438361 TX DQ/DQS : PASS
4874 11:45:39.438435 RX DATLAT : PASS
4875 11:45:39.442014 RX DQ/DQS(Engine): PASS
4876 11:45:39.442115 TX OE : NO K
4877 11:45:39.445780 All Pass.
4878 11:45:39.445884
4879 11:45:39.445975 CH 1, Rank 1
4880 11:45:39.448369 SW Impedance : PASS
4881 11:45:39.448470 DUTY Scan : NO K
4882 11:45:39.452053 ZQ Calibration : PASS
4883 11:45:39.455346 Jitter Meter : NO K
4884 11:45:39.455445 CBT Training : PASS
4885 11:45:39.458185 Write leveling : PASS
4886 11:45:39.461564 RX DQS gating : PASS
4887 11:45:39.461666 RX DQ/DQS(RDDQC) : PASS
4888 11:45:39.464787 TX DQ/DQS : PASS
4889 11:45:39.468350 RX DATLAT : PASS
4890 11:45:39.468428 RX DQ/DQS(Engine): PASS
4891 11:45:39.471865 TX OE : NO K
4892 11:45:39.471965 All Pass.
4893 11:45:39.472042
4894 11:45:39.474664 DramC Write-DBI off
4895 11:45:39.478109 PER_BANK_REFRESH: Hybrid Mode
4896 11:45:39.478192 TX_TRACKING: ON
4897 11:45:39.488019 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4898 11:45:39.491564 [FAST_K] Save calibration result to emmc
4899 11:45:39.494428 dramc_set_vcore_voltage set vcore to 662500
4900 11:45:39.497837 Read voltage for 933, 3
4901 11:45:39.497941 Vio18 = 0
4902 11:45:39.498046 Vcore = 662500
4903 11:45:39.501584 Vdram = 0
4904 11:45:39.501662 Vddq = 0
4905 11:45:39.501748 Vmddr = 0
4906 11:45:39.507629 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4907 11:45:39.510909 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4908 11:45:39.514106 MEM_TYPE=3, freq_sel=17
4909 11:45:39.517569 sv_algorithm_assistance_LP4_1600
4910 11:45:39.520906 ============ PULL DRAM RESETB DOWN ============
4911 11:45:39.527354 ========== PULL DRAM RESETB DOWN end =========
4912 11:45:39.530969 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4913 11:45:39.534460 ===================================
4914 11:45:39.537572 LPDDR4 DRAM CONFIGURATION
4915 11:45:39.540587 ===================================
4916 11:45:39.540696 EX_ROW_EN[0] = 0x0
4917 11:45:39.544246 EX_ROW_EN[1] = 0x0
4918 11:45:39.544349 LP4Y_EN = 0x0
4919 11:45:39.547565 WORK_FSP = 0x0
4920 11:45:39.547673 WL = 0x3
4921 11:45:39.550559 RL = 0x3
4922 11:45:39.550639 BL = 0x2
4923 11:45:39.553927 RPST = 0x0
4924 11:45:39.557200 RD_PRE = 0x0
4925 11:45:39.557303 WR_PRE = 0x1
4926 11:45:39.560367 WR_PST = 0x0
4927 11:45:39.560468 DBI_WR = 0x0
4928 11:45:39.563821 DBI_RD = 0x0
4929 11:45:39.563924 OTF = 0x1
4930 11:45:39.567357 ===================================
4931 11:45:39.570646 ===================================
4932 11:45:39.573419 ANA top config
4933 11:45:39.576984 ===================================
4934 11:45:39.577099 DLL_ASYNC_EN = 0
4935 11:45:39.580483 ALL_SLAVE_EN = 1
4936 11:45:39.583991 NEW_RANK_MODE = 1
4937 11:45:39.586848 DLL_IDLE_MODE = 1
4938 11:45:39.586923 LP45_APHY_COMB_EN = 1
4939 11:45:39.590201 TX_ODT_DIS = 1
4940 11:45:39.593783 NEW_8X_MODE = 1
4941 11:45:39.596928 ===================================
4942 11:45:39.600212 ===================================
4943 11:45:39.603596 data_rate = 1866
4944 11:45:39.606409 CKR = 1
4945 11:45:39.609657 DQ_P2S_RATIO = 8
4946 11:45:39.613582 ===================================
4947 11:45:39.613669 CA_P2S_RATIO = 8
4948 11:45:39.616383 DQ_CA_OPEN = 0
4949 11:45:39.620105 DQ_SEMI_OPEN = 0
4950 11:45:39.623278 CA_SEMI_OPEN = 0
4951 11:45:39.626168 CA_FULL_RATE = 0
4952 11:45:39.629628 DQ_CKDIV4_EN = 1
4953 11:45:39.629734 CA_CKDIV4_EN = 1
4954 11:45:39.632979 CA_PREDIV_EN = 0
4955 11:45:39.635971 PH8_DLY = 0
4956 11:45:39.639284 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4957 11:45:39.642631 DQ_AAMCK_DIV = 4
4958 11:45:39.646178 CA_AAMCK_DIV = 4
4959 11:45:39.649373 CA_ADMCK_DIV = 4
4960 11:45:39.649524 DQ_TRACK_CA_EN = 0
4961 11:45:39.652474 CA_PICK = 933
4962 11:45:39.655845 CA_MCKIO = 933
4963 11:45:39.659304 MCKIO_SEMI = 0
4964 11:45:39.662370 PLL_FREQ = 3732
4965 11:45:39.665876 DQ_UI_PI_RATIO = 32
4966 11:45:39.669056 CA_UI_PI_RATIO = 0
4967 11:45:39.672270 ===================================
4968 11:45:39.675797 ===================================
4969 11:45:39.675902 memory_type:LPDDR4
4970 11:45:39.678748 GP_NUM : 10
4971 11:45:39.682142 SRAM_EN : 1
4972 11:45:39.682241 MD32_EN : 0
4973 11:45:39.685573 ===================================
4974 11:45:39.688561 [ANA_INIT] >>>>>>>>>>>>>>
4975 11:45:39.691922 <<<<<< [CONFIGURE PHASE]: ANA_TX
4976 11:45:39.695284 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4977 11:45:39.699176 ===================================
4978 11:45:39.701839 data_rate = 1866,PCW = 0X8f00
4979 11:45:39.705406 ===================================
4980 11:45:39.708440 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4981 11:45:39.711779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 11:45:39.718387 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 11:45:39.721869 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4984 11:45:39.725362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4985 11:45:39.731725 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4986 11:45:39.731801 [ANA_INIT] flow start
4987 11:45:39.735347 [ANA_INIT] PLL >>>>>>>>
4988 11:45:39.738298 [ANA_INIT] PLL <<<<<<<<
4989 11:45:39.738373 [ANA_INIT] MIDPI >>>>>>>>
4990 11:45:39.741410 [ANA_INIT] MIDPI <<<<<<<<
4991 11:45:39.745230 [ANA_INIT] DLL >>>>>>>>
4992 11:45:39.745327 [ANA_INIT] flow end
4993 11:45:39.748086 ============ LP4 DIFF to SE enter ============
4994 11:45:39.754663 ============ LP4 DIFF to SE exit ============
4995 11:45:39.754767 [ANA_INIT] <<<<<<<<<<<<<
4996 11:45:39.758077 [Flow] Enable top DCM control >>>>>
4997 11:45:39.761016 [Flow] Enable top DCM control <<<<<
4998 11:45:39.764570 Enable DLL master slave shuffle
4999 11:45:39.770875 ==============================================================
5000 11:45:39.774384 Gating Mode config
5001 11:45:39.777706 ==============================================================
5002 11:45:39.780666 Config description:
5003 11:45:39.790739 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5004 11:45:39.797887 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5005 11:45:39.800779 SELPH_MODE 0: By rank 1: By Phase
5006 11:45:39.807685 ==============================================================
5007 11:45:39.810534 GAT_TRACK_EN = 1
5008 11:45:39.814013 RX_GATING_MODE = 2
5009 11:45:39.816979 RX_GATING_TRACK_MODE = 2
5010 11:45:39.820758 SELPH_MODE = 1
5011 11:45:39.820853 PICG_EARLY_EN = 1
5012 11:45:39.823592 VALID_LAT_VALUE = 1
5013 11:45:39.830382 ==============================================================
5014 11:45:39.833707 Enter into Gating configuration >>>>
5015 11:45:39.837019 Exit from Gating configuration <<<<
5016 11:45:39.840360 Enter into DVFS_PRE_config >>>>>
5017 11:45:39.850619 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5018 11:45:39.853413 Exit from DVFS_PRE_config <<<<<
5019 11:45:39.857067 Enter into PICG configuration >>>>
5020 11:45:39.860126 Exit from PICG configuration <<<<
5021 11:45:39.863445 [RX_INPUT] configuration >>>>>
5022 11:45:39.866718 [RX_INPUT] configuration <<<<<
5023 11:45:39.873577 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5024 11:45:39.876359 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5025 11:45:39.883332 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5026 11:45:39.889920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5027 11:45:39.896746 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 11:45:39.902762 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 11:45:39.906091 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5030 11:45:39.909590 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5031 11:45:39.912917 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5032 11:45:39.919593 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5033 11:45:39.923080 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5034 11:45:39.926061 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5035 11:45:39.929306 ===================================
5036 11:45:39.932708 LPDDR4 DRAM CONFIGURATION
5037 11:45:39.936009 ===================================
5038 11:45:39.936105 EX_ROW_EN[0] = 0x0
5039 11:45:39.939807 EX_ROW_EN[1] = 0x0
5040 11:45:39.942766 LP4Y_EN = 0x0
5041 11:45:39.942863 WORK_FSP = 0x0
5042 11:45:39.946451 WL = 0x3
5043 11:45:39.946522 RL = 0x3
5044 11:45:39.949383 BL = 0x2
5045 11:45:39.949492 RPST = 0x0
5046 11:45:39.952800 RD_PRE = 0x0
5047 11:45:39.952879 WR_PRE = 0x1
5048 11:45:39.955680 WR_PST = 0x0
5049 11:45:39.955748 DBI_WR = 0x0
5050 11:45:39.959338 DBI_RD = 0x0
5051 11:45:39.959440 OTF = 0x1
5052 11:45:39.962559 ===================================
5053 11:45:39.965468 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5054 11:45:39.971986 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5055 11:45:39.976110 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5056 11:45:39.978905 ===================================
5057 11:45:39.982167 LPDDR4 DRAM CONFIGURATION
5058 11:45:39.985857 ===================================
5059 11:45:39.988671 EX_ROW_EN[0] = 0x10
5060 11:45:39.988739 EX_ROW_EN[1] = 0x0
5061 11:45:39.992176 LP4Y_EN = 0x0
5062 11:45:39.992247 WORK_FSP = 0x0
5063 11:45:39.995492 WL = 0x3
5064 11:45:39.995592 RL = 0x3
5065 11:45:39.998467 BL = 0x2
5066 11:45:39.998541 RPST = 0x0
5067 11:45:40.001785 RD_PRE = 0x0
5068 11:45:40.001881 WR_PRE = 0x1
5069 11:45:40.005072 WR_PST = 0x0
5070 11:45:40.005212 DBI_WR = 0x0
5071 11:45:40.008428 DBI_RD = 0x0
5072 11:45:40.008523 OTF = 0x1
5073 11:45:40.011826 ===================================
5074 11:45:40.018093 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5075 11:45:40.023278 nWR fixed to 30
5076 11:45:40.026466 [ModeRegInit_LP4] CH0 RK0
5077 11:45:40.026565 [ModeRegInit_LP4] CH0 RK1
5078 11:45:40.029453 [ModeRegInit_LP4] CH1 RK0
5079 11:45:40.032876 [ModeRegInit_LP4] CH1 RK1
5080 11:45:40.032973 match AC timing 9
5081 11:45:40.039883 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5082 11:45:40.042929 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5083 11:45:40.046259 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5084 11:45:40.052822 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5085 11:45:40.056551 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5086 11:45:40.056625 ==
5087 11:45:40.059501 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 11:45:40.062748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 11:45:40.062868 ==
5090 11:45:40.069425 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 11:45:40.076121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5092 11:45:40.079253 [CA 0] Center 38 (8~69) winsize 62
5093 11:45:40.082104 [CA 1] Center 37 (7~68) winsize 62
5094 11:45:40.085198 [CA 2] Center 35 (5~65) winsize 61
5095 11:45:40.089105 [CA 3] Center 34 (4~65) winsize 62
5096 11:45:40.092114 [CA 4] Center 33 (2~64) winsize 63
5097 11:45:40.095183 [CA 5] Center 32 (2~63) winsize 62
5098 11:45:40.095290
5099 11:45:40.098526 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5100 11:45:40.098605
5101 11:45:40.101980 [CATrainingPosCal] consider 1 rank data
5102 11:45:40.104964 u2DelayCellTimex100 = 270/100 ps
5103 11:45:40.108350 CA0 delay=38 (8~69),Diff = 6 PI (37 cell)
5104 11:45:40.111742 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5105 11:45:40.118527 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5106 11:45:40.121770 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5107 11:45:40.125035 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5108 11:45:40.128005 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5109 11:45:40.128078
5110 11:45:40.131651 CA PerBit enable=1, Macro0, CA PI delay=32
5111 11:45:40.131723
5112 11:45:40.134538 [CBTSetCACLKResult] CA Dly = 32
5113 11:45:40.134675 CS Dly: 5 (0~36)
5114 11:45:40.138171 ==
5115 11:45:40.141513 Dram Type= 6, Freq= 0, CH_0, rank 1
5116 11:45:40.144488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 11:45:40.144568 ==
5118 11:45:40.148050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5119 11:45:40.154186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5120 11:45:40.157992 [CA 0] Center 38 (8~69) winsize 62
5121 11:45:40.161685 [CA 1] Center 38 (7~69) winsize 63
5122 11:45:40.164959 [CA 2] Center 35 (5~65) winsize 61
5123 11:45:40.168224 [CA 3] Center 34 (4~65) winsize 62
5124 11:45:40.170992 [CA 4] Center 33 (3~64) winsize 62
5125 11:45:40.174377 [CA 5] Center 32 (2~63) winsize 62
5126 11:45:40.174451
5127 11:45:40.177828 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5128 11:45:40.177928
5129 11:45:40.184393 [CATrainingPosCal] consider 2 rank data
5130 11:45:40.184469 u2DelayCellTimex100 = 270/100 ps
5131 11:45:40.190810 CA0 delay=38 (8~69),Diff = 6 PI (37 cell)
5132 11:45:40.194400 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5133 11:45:40.198044 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5134 11:45:40.200709 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5135 11:45:40.204184 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5136 11:45:40.207508 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5137 11:45:40.207584
5138 11:45:40.210443 CA PerBit enable=1, Macro0, CA PI delay=32
5139 11:45:40.210515
5140 11:45:40.214083 [CBTSetCACLKResult] CA Dly = 32
5141 11:45:40.217632 CS Dly: 6 (0~39)
5142 11:45:40.217706
5143 11:45:40.220355 ----->DramcWriteLeveling(PI) begin...
5144 11:45:40.220456 ==
5145 11:45:40.223785 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 11:45:40.227259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 11:45:40.227359 ==
5148 11:45:40.230151 Write leveling (Byte 0): 29 => 29
5149 11:45:40.233620 Write leveling (Byte 1): 28 => 28
5150 11:45:40.236846 DramcWriteLeveling(PI) end<-----
5151 11:45:40.236947
5152 11:45:40.237036 ==
5153 11:45:40.240091 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 11:45:40.243434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 11:45:40.243535 ==
5156 11:45:40.246669 [Gating] SW mode calibration
5157 11:45:40.253373 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5158 11:45:40.260033 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5159 11:45:40.263462 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5160 11:45:40.269883 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 11:45:40.273275 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 11:45:40.276334 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 11:45:40.283163 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 11:45:40.286207 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 11:45:40.289479 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5166 11:45:40.295941 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 1)
5167 11:45:40.299355 0 15 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
5168 11:45:40.302854 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 11:45:40.309442 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 11:45:40.312417 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 11:45:40.315585 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 11:45:40.322374 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 11:45:40.325682 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 11:45:40.329255 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5175 11:45:40.335606 1 0 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5176 11:45:40.338948 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 11:45:40.342235 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 11:45:40.348630 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 11:45:40.352007 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 11:45:40.355344 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 11:45:40.362163 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 11:45:40.365144 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5183 11:45:40.368692 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5184 11:45:40.375148 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5185 11:45:40.378684 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 11:45:40.381884 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 11:45:40.388326 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 11:45:40.391294 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 11:45:40.394923 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 11:45:40.401946 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 11:45:40.404736 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 11:45:40.408261 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 11:45:40.414466 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 11:45:40.417805 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 11:45:40.421096 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 11:45:40.427992 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 11:45:40.431168 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 11:45:40.434842 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5199 11:45:40.437796 Total UI for P1: 0, mck2ui 16
5200 11:45:40.440864 best dqsien dly found for B0: ( 1, 2, 26)
5201 11:45:40.447595 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5202 11:45:40.451023 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 11:45:40.454165 Total UI for P1: 0, mck2ui 16
5204 11:45:40.457313 best dqsien dly found for B1: ( 1, 2, 30)
5205 11:45:40.460632 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5206 11:45:40.464119 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5207 11:45:40.464240
5208 11:45:40.467542 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5209 11:45:40.470517 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5210 11:45:40.473670 [Gating] SW calibration Done
5211 11:45:40.473774 ==
5212 11:45:40.477390 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 11:45:40.483538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 11:45:40.483648 ==
5215 11:45:40.483740 RX Vref Scan: 0
5216 11:45:40.483830
5217 11:45:40.486778 RX Vref 0 -> 0, step: 1
5218 11:45:40.486854
5219 11:45:40.490458 RX Delay -80 -> 252, step: 8
5220 11:45:40.493504 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5221 11:45:40.497085 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5222 11:45:40.500005 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5223 11:45:40.503773 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5224 11:45:40.510071 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5225 11:45:40.513456 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5226 11:45:40.516372 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5227 11:45:40.519914 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5228 11:45:40.523559 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5229 11:45:40.530449 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5230 11:45:40.532998 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5231 11:45:40.536035 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5232 11:45:40.539493 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5233 11:45:40.546210 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5234 11:45:40.549069 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5235 11:45:40.552559 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5236 11:45:40.552641 ==
5237 11:45:40.555778 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 11:45:40.559019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 11:45:40.559100 ==
5240 11:45:40.562682 DQS Delay:
5241 11:45:40.562760 DQS0 = 0, DQS1 = 0
5242 11:45:40.562825 DQM Delay:
5243 11:45:40.565994 DQM0 = 103, DQM1 = 88
5244 11:45:40.566102 DQ Delay:
5245 11:45:40.568918 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5246 11:45:40.572594 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =107
5247 11:45:40.575856 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5248 11:45:40.578602 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5249 11:45:40.578703
5250 11:45:40.582123
5251 11:45:40.582231 ==
5252 11:45:40.585243 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 11:45:40.588853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 11:45:40.588953 ==
5255 11:45:40.589053
5256 11:45:40.589143
5257 11:45:40.592262 TX Vref Scan disable
5258 11:45:40.592364 == TX Byte 0 ==
5259 11:45:40.598765 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5260 11:45:40.602104 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5261 11:45:40.602214 == TX Byte 1 ==
5262 11:45:40.608472 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5263 11:45:40.611943 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5264 11:45:40.612048 ==
5265 11:45:40.614828 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 11:45:40.618463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 11:45:40.618546 ==
5268 11:45:40.618610
5269 11:45:40.618675
5270 11:45:40.621745 TX Vref Scan disable
5271 11:45:40.625288 == TX Byte 0 ==
5272 11:45:40.628172 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5273 11:45:40.631597 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5274 11:45:40.635314 == TX Byte 1 ==
5275 11:45:40.638122 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5276 11:45:40.641164 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5277 11:45:40.641265
5278 11:45:40.644848 [DATLAT]
5279 11:45:40.644950 Freq=933, CH0 RK0
5280 11:45:40.645039
5281 11:45:40.648137 DATLAT Default: 0xd
5282 11:45:40.648234 0, 0xFFFF, sum = 0
5283 11:45:40.651161 1, 0xFFFF, sum = 0
5284 11:45:40.651276 2, 0xFFFF, sum = 0
5285 11:45:40.654580 3, 0xFFFF, sum = 0
5286 11:45:40.654687 4, 0xFFFF, sum = 0
5287 11:45:40.658055 5, 0xFFFF, sum = 0
5288 11:45:40.661234 6, 0xFFFF, sum = 0
5289 11:45:40.661334 7, 0xFFFF, sum = 0
5290 11:45:40.664377 8, 0xFFFF, sum = 0
5291 11:45:40.664509 9, 0xFFFF, sum = 0
5292 11:45:40.667451 10, 0x0, sum = 1
5293 11:45:40.667555 11, 0x0, sum = 2
5294 11:45:40.670981 12, 0x0, sum = 3
5295 11:45:40.671054 13, 0x0, sum = 4
5296 11:45:40.671124 best_step = 11
5297 11:45:40.671186
5298 11:45:40.674015 ==
5299 11:45:40.677627 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 11:45:40.680597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 11:45:40.680719 ==
5302 11:45:40.680826 RX Vref Scan: 1
5303 11:45:40.680914
5304 11:45:40.683948 RX Vref 0 -> 0, step: 1
5305 11:45:40.684047
5306 11:45:40.687099 RX Delay -61 -> 252, step: 4
5307 11:45:40.687170
5308 11:45:40.690664 Set Vref, RX VrefLevel [Byte0]: 56
5309 11:45:40.694022 [Byte1]: 50
5310 11:45:40.694121
5311 11:45:40.697399 Final RX Vref Byte 0 = 56 to rank0
5312 11:45:40.700578 Final RX Vref Byte 1 = 50 to rank0
5313 11:45:40.703956 Final RX Vref Byte 0 = 56 to rank1
5314 11:45:40.707293 Final RX Vref Byte 1 = 50 to rank1==
5315 11:45:40.710338 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 11:45:40.717069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 11:45:40.717149 ==
5318 11:45:40.717213 DQS Delay:
5319 11:45:40.720716 DQS0 = 0, DQS1 = 0
5320 11:45:40.720817 DQM Delay:
5321 11:45:40.720907 DQM0 = 103, DQM1 = 90
5322 11:45:40.723618 DQ Delay:
5323 11:45:40.726958 DQ0 =104, DQ1 =104, DQ2 =98, DQ3 =98
5324 11:45:40.729831 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =108
5325 11:45:40.733288 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =86
5326 11:45:40.736777 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =98
5327 11:45:40.736881
5328 11:45:40.736976
5329 11:45:40.743117 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5330 11:45:40.746494 CH0 RK0: MR19=505, MR18=1A14
5331 11:45:40.756752 CH0_RK0: MR19=0x505, MR18=0x1A14, DQSOSC=413, MR23=63, INC=63, DEC=42
5332 11:45:40.756936
5333 11:45:40.757217 ----->DramcWriteLeveling(PI) begin...
5334 11:45:40.757316 ==
5335 11:45:40.759313 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 11:45:40.762778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 11:45:40.766334 ==
5338 11:45:40.766434 Write leveling (Byte 0): 30 => 30
5339 11:45:40.769066 Write leveling (Byte 1): 26 => 26
5340 11:45:40.772565 DramcWriteLeveling(PI) end<-----
5341 11:45:40.772664
5342 11:45:40.772759 ==
5343 11:45:40.776072 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 11:45:40.782333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 11:45:40.782409 ==
5346 11:45:40.785723 [Gating] SW mode calibration
5347 11:45:40.792345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5348 11:45:40.795744 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5349 11:45:40.802389 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (0 0)
5350 11:45:40.805597 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 11:45:40.808715 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 11:45:40.815470 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 11:45:40.818669 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 11:45:40.822143 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 11:45:40.828668 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5356 11:45:40.832263 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
5357 11:45:40.835019 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5358 11:45:40.841951 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 11:45:40.845053 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 11:45:40.848027 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 11:45:40.854861 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 11:45:40.858209 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 11:45:40.861207 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5364 11:45:40.868156 0 15 28 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (0 0)
5365 11:45:40.871652 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5366 11:45:40.875067 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 11:45:40.881339 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 11:45:40.884729 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 11:45:40.888265 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 11:45:40.894504 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 11:45:40.897716 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5372 11:45:40.901303 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 11:45:40.907853 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5374 11:45:40.910857 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 11:45:40.914159 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:45:40.920790 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:45:40.923764 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:45:40.927270 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:45:40.934047 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:45:40.937416 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:45:40.940341 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:45:40.947168 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 11:45:40.950626 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:45:40.953902 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 11:45:40.960393 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 11:45:40.964045 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:45:40.966706 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5388 11:45:40.973615 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5389 11:45:40.976414 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5390 11:45:40.979713 Total UI for P1: 0, mck2ui 16
5391 11:45:40.983384 best dqsien dly found for B0: ( 1, 2, 26)
5392 11:45:40.986204 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 11:45:40.989838 Total UI for P1: 0, mck2ui 16
5394 11:45:40.993138 best dqsien dly found for B1: ( 1, 2, 30)
5395 11:45:40.996737 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5396 11:45:40.999875 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5397 11:45:41.003012
5398 11:45:41.006530 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5399 11:45:41.009522 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5400 11:45:41.012614 [Gating] SW calibration Done
5401 11:45:41.012695 ==
5402 11:45:41.015947 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 11:45:41.019439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 11:45:41.019520 ==
5405 11:45:41.022727 RX Vref Scan: 0
5406 11:45:41.022807
5407 11:45:41.022870 RX Vref 0 -> 0, step: 1
5408 11:45:41.022929
5409 11:45:41.026084 RX Delay -80 -> 252, step: 8
5410 11:45:41.029423 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5411 11:45:41.032559 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5412 11:45:41.039391 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5413 11:45:41.042597 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5414 11:45:41.045831 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5415 11:45:41.048819 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5416 11:45:41.052605 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5417 11:45:41.059328 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5418 11:45:41.062210 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5419 11:45:41.065887 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5420 11:45:41.068506 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5421 11:45:41.071871 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5422 11:45:41.075361 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5423 11:45:41.081662 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5424 11:45:41.085157 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5425 11:45:41.088737 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5426 11:45:41.088818 ==
5427 11:45:41.092010 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 11:45:41.095211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 11:45:41.095292 ==
5430 11:45:41.098574 DQS Delay:
5431 11:45:41.098655 DQS0 = 0, DQS1 = 0
5432 11:45:41.101403 DQM Delay:
5433 11:45:41.101484 DQM0 = 99, DQM1 = 88
5434 11:45:41.101547 DQ Delay:
5435 11:45:41.104917 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5436 11:45:41.108411 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5437 11:45:41.111376 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5438 11:45:41.117956 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5439 11:45:41.118037
5440 11:45:41.118100
5441 11:45:41.118159 ==
5442 11:45:41.121047 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 11:45:41.124704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 11:45:41.124785 ==
5445 11:45:41.124850
5446 11:45:41.124909
5447 11:45:41.128101 TX Vref Scan disable
5448 11:45:41.128182 == TX Byte 0 ==
5449 11:45:41.134568 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5450 11:45:41.137529 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5451 11:45:41.137610 == TX Byte 1 ==
5452 11:45:41.144522 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5453 11:45:41.147659 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5454 11:45:41.147756 ==
5455 11:45:41.150672 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 11:45:41.154128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 11:45:41.154225 ==
5458 11:45:41.157104
5459 11:45:41.157199
5460 11:45:41.157276 TX Vref Scan disable
5461 11:45:41.161134 == TX Byte 0 ==
5462 11:45:41.163920 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5463 11:45:41.170875 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5464 11:45:41.170995 == TX Byte 1 ==
5465 11:45:41.174271 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5466 11:45:41.180410 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5467 11:45:41.180491
5468 11:45:41.180555 [DATLAT]
5469 11:45:41.180615 Freq=933, CH0 RK1
5470 11:45:41.180672
5471 11:45:41.183706 DATLAT Default: 0xb
5472 11:45:41.183786 0, 0xFFFF, sum = 0
5473 11:45:41.187308 1, 0xFFFF, sum = 0
5474 11:45:41.190944 2, 0xFFFF, sum = 0
5475 11:45:41.191027 3, 0xFFFF, sum = 0
5476 11:45:41.193786 4, 0xFFFF, sum = 0
5477 11:45:41.193868 5, 0xFFFF, sum = 0
5478 11:45:41.197408 6, 0xFFFF, sum = 0
5479 11:45:41.197490 7, 0xFFFF, sum = 0
5480 11:45:41.200676 8, 0xFFFF, sum = 0
5481 11:45:41.200759 9, 0xFFFF, sum = 0
5482 11:45:41.203487 10, 0x0, sum = 1
5483 11:45:41.203568 11, 0x0, sum = 2
5484 11:45:41.206910 12, 0x0, sum = 3
5485 11:45:41.206992 13, 0x0, sum = 4
5486 11:45:41.207056 best_step = 11
5487 11:45:41.210425
5488 11:45:41.210505 ==
5489 11:45:41.213922 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 11:45:41.216845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 11:45:41.216927 ==
5492 11:45:41.216991 RX Vref Scan: 0
5493 11:45:41.217051
5494 11:45:41.220385 RX Vref 0 -> 0, step: 1
5495 11:45:41.220465
5496 11:45:41.223806 RX Delay -61 -> 252, step: 4
5497 11:45:41.230531 iDelay=195, Bit 0, Center 100 (15 ~ 186) 172
5498 11:45:41.233565 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5499 11:45:41.236763 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5500 11:45:41.239966 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5501 11:45:41.243388 iDelay=195, Bit 4, Center 104 (19 ~ 190) 172
5502 11:45:41.249909 iDelay=195, Bit 5, Center 94 (11 ~ 178) 168
5503 11:45:41.253350 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5504 11:45:41.255953 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5505 11:45:41.259439 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5506 11:45:41.262871 iDelay=195, Bit 9, Center 80 (-5 ~ 166) 172
5507 11:45:41.269150 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5508 11:45:41.272776 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5509 11:45:41.275861 iDelay=195, Bit 12, Center 98 (15 ~ 182) 168
5510 11:45:41.279493 iDelay=195, Bit 13, Center 96 (11 ~ 182) 172
5511 11:45:41.282588 iDelay=195, Bit 14, Center 100 (15 ~ 186) 172
5512 11:45:41.288926 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5513 11:45:41.289031 ==
5514 11:45:41.292494 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 11:45:41.295958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 11:45:41.296063 ==
5517 11:45:41.296154 DQS Delay:
5518 11:45:41.299138 DQS0 = 0, DQS1 = 0
5519 11:45:41.299209 DQM Delay:
5520 11:45:41.302046 DQM0 = 101, DQM1 = 91
5521 11:45:41.302141 DQ Delay:
5522 11:45:41.305449 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =98
5523 11:45:41.308999 DQ4 =104, DQ5 =94, DQ6 =110, DQ7 =108
5524 11:45:41.312036 DQ8 =82, DQ9 =80, DQ10 =92, DQ11 =84
5525 11:45:41.315612 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =96
5526 11:45:41.315692
5527 11:45:41.315762
5528 11:45:41.325574 [DQSOSCAuto] RK1, (LSB)MR18= 0x1713, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5529 11:45:41.325680 CH0 RK1: MR19=505, MR18=1713
5530 11:45:41.331961 CH0_RK1: MR19=0x505, MR18=0x1713, DQSOSC=414, MR23=63, INC=63, DEC=42
5531 11:45:41.335818 [RxdqsGatingPostProcess] freq 933
5532 11:45:41.342145 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5533 11:45:41.345763 best DQS0 dly(2T, 0.5T) = (0, 10)
5534 11:45:41.348658 best DQS1 dly(2T, 0.5T) = (0, 10)
5535 11:45:41.352003 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5536 11:45:41.355193 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5537 11:45:41.358565 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 11:45:41.362037 best DQS1 dly(2T, 0.5T) = (0, 10)
5539 11:45:41.362117 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 11:45:41.365164 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5541 11:45:41.368899 Pre-setting of DQS Precalculation
5542 11:45:41.375153 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5543 11:45:41.375240 ==
5544 11:45:41.379056 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 11:45:41.381731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 11:45:41.381824 ==
5547 11:45:41.388509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 11:45:41.395223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5549 11:45:41.398557 [CA 0] Center 36 (6~67) winsize 62
5550 11:45:41.402456 [CA 1] Center 36 (6~67) winsize 62
5551 11:45:41.404723 [CA 2] Center 34 (4~65) winsize 62
5552 11:45:41.407881 [CA 3] Center 34 (4~65) winsize 62
5553 11:45:41.411443 [CA 4] Center 34 (4~65) winsize 62
5554 11:45:41.414887 [CA 5] Center 33 (3~64) winsize 62
5555 11:45:41.414967
5556 11:45:41.417836 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5557 11:45:41.417916
5558 11:45:41.421326 [CATrainingPosCal] consider 1 rank data
5559 11:45:41.424828 u2DelayCellTimex100 = 270/100 ps
5560 11:45:41.427671 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 11:45:41.431178 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5562 11:45:41.434129 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5563 11:45:41.437735 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5564 11:45:41.440950 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5565 11:45:41.447773 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5566 11:45:41.447859
5567 11:45:41.450563 CA PerBit enable=1, Macro0, CA PI delay=33
5568 11:45:41.450637
5569 11:45:41.454705 [CBTSetCACLKResult] CA Dly = 33
5570 11:45:41.454781 CS Dly: 5 (0~36)
5571 11:45:41.454845 ==
5572 11:45:41.457601 Dram Type= 6, Freq= 0, CH_1, rank 1
5573 11:45:41.460502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 11:45:41.463871 ==
5575 11:45:41.467250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5576 11:45:41.473828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5577 11:45:41.477317 [CA 0] Center 36 (6~67) winsize 62
5578 11:45:41.480590 [CA 1] Center 36 (6~67) winsize 62
5579 11:45:41.483829 [CA 2] Center 34 (4~65) winsize 62
5580 11:45:41.486906 [CA 3] Center 33 (3~64) winsize 62
5581 11:45:41.490351 [CA 4] Center 33 (3~64) winsize 62
5582 11:45:41.493677 [CA 5] Center 33 (3~64) winsize 62
5583 11:45:41.493775
5584 11:45:41.497138 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5585 11:45:41.497216
5586 11:45:41.499937 [CATrainingPosCal] consider 2 rank data
5587 11:45:41.503635 u2DelayCellTimex100 = 270/100 ps
5588 11:45:41.506624 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5589 11:45:41.509782 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5590 11:45:41.516512 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5591 11:45:41.519887 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5592 11:45:41.523266 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5593 11:45:41.526729 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5594 11:45:41.526806
5595 11:45:41.529635 CA PerBit enable=1, Macro0, CA PI delay=33
5596 11:45:41.529735
5597 11:45:41.533019 [CBTSetCACLKResult] CA Dly = 33
5598 11:45:41.533121 CS Dly: 6 (0~38)
5599 11:45:41.536405
5600 11:45:41.539321 ----->DramcWriteLeveling(PI) begin...
5601 11:45:41.539404 ==
5602 11:45:41.542642 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 11:45:41.546585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 11:45:41.546665 ==
5605 11:45:41.549546 Write leveling (Byte 0): 26 => 26
5606 11:45:41.553218 Write leveling (Byte 1): 26 => 26
5607 11:45:41.556628 DramcWriteLeveling(PI) end<-----
5608 11:45:41.556728
5609 11:45:41.556823 ==
5610 11:45:41.559711 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 11:45:41.562857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 11:45:41.562963 ==
5613 11:45:41.565904 [Gating] SW mode calibration
5614 11:45:41.572946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5615 11:45:41.579451 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5616 11:45:41.582637 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5617 11:45:41.585846 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 11:45:41.592494 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 11:45:41.595882 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 11:45:41.599031 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 11:45:41.605951 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 11:45:41.609078 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5623 11:45:41.612715 0 14 28 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
5624 11:45:41.618893 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5625 11:45:41.622451 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 11:45:41.625742 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 11:45:41.632333 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 11:45:41.635417 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 11:45:41.638867 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 11:45:41.645601 0 15 24 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
5631 11:45:41.648842 0 15 28 | B1->B0 | 3636 3d3d | 0 0 | (1 1) (0 0)
5632 11:45:41.651842 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 11:45:41.658609 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 11:45:41.661881 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 11:45:41.665291 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 11:45:41.672032 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 11:45:41.675062 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 11:45:41.678084 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 11:45:41.685173 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 11:45:41.688174 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 11:45:41.691265 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 11:45:41.698095 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 11:45:41.701229 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 11:45:41.704618 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 11:45:41.710984 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 11:45:41.714878 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 11:45:41.717642 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:45:41.724596 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:45:41.727676 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:45:41.731193 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 11:45:41.737567 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 11:45:41.740660 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:45:41.744150 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 11:45:41.750408 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5655 11:45:41.753763 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5656 11:45:41.757420 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 11:45:41.760258 Total UI for P1: 0, mck2ui 16
5658 11:45:41.763860 best dqsien dly found for B0: ( 1, 2, 26)
5659 11:45:41.767024 Total UI for P1: 0, mck2ui 16
5660 11:45:41.770383 best dqsien dly found for B1: ( 1, 2, 26)
5661 11:45:41.773615 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5662 11:45:41.776866 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5663 11:45:41.776968
5664 11:45:41.783542 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5665 11:45:41.786587 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5666 11:45:41.789988 [Gating] SW calibration Done
5667 11:45:41.790085 ==
5668 11:45:41.793488 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 11:45:41.796708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 11:45:41.796783 ==
5671 11:45:41.796852 RX Vref Scan: 0
5672 11:45:41.796913
5673 11:45:41.800011 RX Vref 0 -> 0, step: 1
5674 11:45:41.800089
5675 11:45:41.803402 RX Delay -80 -> 252, step: 8
5676 11:45:41.806594 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5677 11:45:41.809991 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5678 11:45:41.816109 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5679 11:45:41.820025 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5680 11:45:41.822688 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5681 11:45:41.826226 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5682 11:45:41.829666 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5683 11:45:41.832834 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5684 11:45:41.839592 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5685 11:45:41.842526 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5686 11:45:41.846136 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5687 11:45:41.849489 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5688 11:45:41.852662 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5689 11:45:41.859438 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5690 11:45:41.862732 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5691 11:45:41.865924 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5692 11:45:41.865996 ==
5693 11:45:41.869167 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 11:45:41.872549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 11:45:41.872623 ==
5696 11:45:41.875509 DQS Delay:
5697 11:45:41.875579 DQS0 = 0, DQS1 = 0
5698 11:45:41.878836 DQM Delay:
5699 11:45:41.878907 DQM0 = 99, DQM1 = 95
5700 11:45:41.878966 DQ Delay:
5701 11:45:41.882563 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5702 11:45:41.885470 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5703 11:45:41.889033 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5704 11:45:41.895909 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5705 11:45:41.895985
5706 11:45:41.896050
5707 11:45:41.896108 ==
5708 11:45:41.899304 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 11:45:41.902145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 11:45:41.902243 ==
5711 11:45:41.902357
5712 11:45:41.902415
5713 11:45:41.905470 TX Vref Scan disable
5714 11:45:41.905539 == TX Byte 0 ==
5715 11:45:41.911816 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5716 11:45:41.915326 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5717 11:45:41.915403 == TX Byte 1 ==
5718 11:45:41.922100 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5719 11:45:41.925061 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5720 11:45:41.925162 ==
5721 11:45:41.928603 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 11:45:41.931665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 11:45:41.931742 ==
5724 11:45:41.934905
5725 11:45:41.934982
5726 11:45:41.935043 TX Vref Scan disable
5727 11:45:41.938493 == TX Byte 0 ==
5728 11:45:41.941408 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5729 11:45:41.947823 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5730 11:45:41.947928 == TX Byte 1 ==
5731 11:45:41.951480 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5732 11:45:41.957675 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5733 11:45:41.957780
5734 11:45:41.957871 [DATLAT]
5735 11:45:41.957959 Freq=933, CH1 RK0
5736 11:45:41.958049
5737 11:45:41.961008 DATLAT Default: 0xd
5738 11:45:41.964483 0, 0xFFFF, sum = 0
5739 11:45:41.964638 1, 0xFFFF, sum = 0
5740 11:45:41.967637 2, 0xFFFF, sum = 0
5741 11:45:41.967711 3, 0xFFFF, sum = 0
5742 11:45:41.970960 4, 0xFFFF, sum = 0
5743 11:45:41.971031 5, 0xFFFF, sum = 0
5744 11:45:41.974097 6, 0xFFFF, sum = 0
5745 11:45:41.974198 7, 0xFFFF, sum = 0
5746 11:45:41.977672 8, 0xFFFF, sum = 0
5747 11:45:41.977745 9, 0xFFFF, sum = 0
5748 11:45:41.981256 10, 0x0, sum = 1
5749 11:45:41.981354 11, 0x0, sum = 2
5750 11:45:41.984166 12, 0x0, sum = 3
5751 11:45:41.984263 13, 0x0, sum = 4
5752 11:45:41.987651 best_step = 11
5753 11:45:41.987723
5754 11:45:41.987783 ==
5755 11:45:41.990963 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 11:45:41.994185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 11:45:41.994319 ==
5758 11:45:41.994411 RX Vref Scan: 1
5759 11:45:41.994497
5760 11:45:41.997800 RX Vref 0 -> 0, step: 1
5761 11:45:41.997898
5762 11:45:42.000800 RX Delay -53 -> 252, step: 4
5763 11:45:42.000894
5764 11:45:42.004198 Set Vref, RX VrefLevel [Byte0]: 52
5765 11:45:42.007474 [Byte1]: 52
5766 11:45:42.010846
5767 11:45:42.010928 Final RX Vref Byte 0 = 52 to rank0
5768 11:45:42.013990 Final RX Vref Byte 1 = 52 to rank0
5769 11:45:42.017517 Final RX Vref Byte 0 = 52 to rank1
5770 11:45:42.020664 Final RX Vref Byte 1 = 52 to rank1==
5771 11:45:42.023849 Dram Type= 6, Freq= 0, CH_1, rank 0
5772 11:45:42.030158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 11:45:42.030301 ==
5774 11:45:42.030397 DQS Delay:
5775 11:45:42.033676 DQS0 = 0, DQS1 = 0
5776 11:45:42.033771 DQM Delay:
5777 11:45:42.033860 DQM0 = 98, DQM1 = 94
5778 11:45:42.037087 DQ Delay:
5779 11:45:42.040606 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =98
5780 11:45:42.043589 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =92
5781 11:45:42.046890 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5782 11:45:42.050363 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5783 11:45:42.050469
5784 11:45:42.050562
5785 11:45:42.056856 [DQSOSCAuto] RK0, (LSB)MR18= 0x616, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 420 ps
5786 11:45:42.060368 CH1 RK0: MR19=505, MR18=616
5787 11:45:42.066633 CH1_RK0: MR19=0x505, MR18=0x616, DQSOSC=414, MR23=63, INC=63, DEC=42
5788 11:45:42.066740
5789 11:45:42.070209 ----->DramcWriteLeveling(PI) begin...
5790 11:45:42.070330 ==
5791 11:45:42.073673 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 11:45:42.076895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 11:45:42.076998 ==
5794 11:45:42.080327 Write leveling (Byte 0): 25 => 25
5795 11:45:42.083198 Write leveling (Byte 1): 27 => 27
5796 11:45:42.086549 DramcWriteLeveling(PI) end<-----
5797 11:45:42.086648
5798 11:45:42.086712 ==
5799 11:45:42.089998 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 11:45:42.093233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 11:45:42.096396 ==
5802 11:45:42.096470 [Gating] SW mode calibration
5803 11:45:42.106194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5804 11:45:42.109864 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5805 11:45:42.112963 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5806 11:45:42.119600 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 11:45:42.122737 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 11:45:42.125887 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 11:45:42.132443 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 11:45:42.135873 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 11:45:42.139118 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5812 11:45:42.145701 0 14 28 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
5813 11:45:42.149096 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 11:45:42.152362 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 11:45:42.158963 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 11:45:42.162419 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 11:45:42.165656 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 11:45:42.172411 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 11:45:42.175391 0 15 24 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
5820 11:45:42.178770 0 15 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5821 11:45:42.185788 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 11:45:42.188864 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 11:45:42.191828 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 11:45:42.198566 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 11:45:42.201855 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 11:45:42.205600 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 11:45:42.211509 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 11:45:42.214972 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5829 11:45:42.218017 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5830 11:45:42.224805 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 11:45:42.228200 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 11:45:42.231415 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 11:45:42.237939 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 11:45:42.241401 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 11:45:42.244872 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 11:45:42.251015 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 11:45:42.254471 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 11:45:42.257980 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 11:45:42.264415 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 11:45:42.267396 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 11:45:42.274117 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 11:45:42.277645 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 11:45:42.280669 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 11:45:42.287550 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5845 11:45:42.287658 Total UI for P1: 0, mck2ui 16
5846 11:45:42.290732 best dqsien dly found for B0: ( 1, 2, 26)
5847 11:45:42.297134 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5848 11:45:42.300877 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 11:45:42.304298 Total UI for P1: 0, mck2ui 16
5850 11:45:42.307069 best dqsien dly found for B1: ( 1, 2, 30)
5851 11:45:42.310571 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5852 11:45:42.313529 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5853 11:45:42.313611
5854 11:45:42.317073 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5855 11:45:42.323575 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5856 11:45:42.323657 [Gating] SW calibration Done
5857 11:45:42.323728 ==
5858 11:45:42.327064 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 11:45:42.333604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 11:45:42.333682 ==
5861 11:45:42.333751 RX Vref Scan: 0
5862 11:45:42.333811
5863 11:45:42.336838 RX Vref 0 -> 0, step: 1
5864 11:45:42.336910
5865 11:45:42.340038 RX Delay -80 -> 252, step: 8
5866 11:45:42.343743 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5867 11:45:42.346627 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5868 11:45:42.349994 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5869 11:45:42.356370 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5870 11:45:42.359985 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5871 11:45:42.362987 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5872 11:45:42.366716 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5873 11:45:42.369736 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5874 11:45:42.373192 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5875 11:45:42.379532 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5876 11:45:42.383096 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5877 11:45:42.386416 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5878 11:45:42.389326 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5879 11:45:42.393314 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5880 11:45:42.399593 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5881 11:45:42.402478 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5882 11:45:42.402554 ==
5883 11:45:42.406150 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 11:45:42.409465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 11:45:42.409540 ==
5886 11:45:42.409602 DQS Delay:
5887 11:45:42.412408 DQS0 = 0, DQS1 = 0
5888 11:45:42.412479 DQM Delay:
5889 11:45:42.415868 DQM0 = 97, DQM1 = 94
5890 11:45:42.415946 DQ Delay:
5891 11:45:42.419501 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5892 11:45:42.422491 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5893 11:45:42.425964 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5894 11:45:42.429772 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5895 11:45:42.429870
5896 11:45:42.429959
5897 11:45:42.430049 ==
5898 11:45:42.432463 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 11:45:42.439140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 11:45:42.439220 ==
5901 11:45:42.439285
5902 11:45:42.439347
5903 11:45:42.439404 TX Vref Scan disable
5904 11:45:42.443029 == TX Byte 0 ==
5905 11:45:42.445847 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5906 11:45:42.452767 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5907 11:45:42.452873 == TX Byte 1 ==
5908 11:45:42.455721 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5909 11:45:42.462373 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5910 11:45:42.462477 ==
5911 11:45:42.465850 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 11:45:42.469963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 11:45:42.470039 ==
5914 11:45:42.470108
5915 11:45:42.470197
5916 11:45:42.472189 TX Vref Scan disable
5917 11:45:42.476321 == TX Byte 0 ==
5918 11:45:42.478908 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5919 11:45:42.481951 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5920 11:45:42.485302 == TX Byte 1 ==
5921 11:45:42.488810 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5922 11:45:42.491712 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5923 11:45:42.491790
5924 11:45:42.491853 [DATLAT]
5925 11:45:42.495203 Freq=933, CH1 RK1
5926 11:45:42.495303
5927 11:45:42.498863 DATLAT Default: 0xb
5928 11:45:42.498939 0, 0xFFFF, sum = 0
5929 11:45:42.502157 1, 0xFFFF, sum = 0
5930 11:45:42.502262 2, 0xFFFF, sum = 0
5931 11:45:42.505056 3, 0xFFFF, sum = 0
5932 11:45:42.505128 4, 0xFFFF, sum = 0
5933 11:45:42.508733 5, 0xFFFF, sum = 0
5934 11:45:42.508832 6, 0xFFFF, sum = 0
5935 11:45:42.512028 7, 0xFFFF, sum = 0
5936 11:45:42.512101 8, 0xFFFF, sum = 0
5937 11:45:42.515136 9, 0xFFFF, sum = 0
5938 11:45:42.515212 10, 0x0, sum = 1
5939 11:45:42.518578 11, 0x0, sum = 2
5940 11:45:42.518650 12, 0x0, sum = 3
5941 11:45:42.522024 13, 0x0, sum = 4
5942 11:45:42.522126 best_step = 11
5943 11:45:42.522214
5944 11:45:42.522335 ==
5945 11:45:42.524935 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 11:45:42.528476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 11:45:42.528550 ==
5948 11:45:42.531893 RX Vref Scan: 0
5949 11:45:42.531995
5950 11:45:42.534769 RX Vref 0 -> 0, step: 1
5951 11:45:42.534866
5952 11:45:42.534955 RX Delay -53 -> 252, step: 4
5953 11:45:42.543397 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5954 11:45:42.546310 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5955 11:45:42.549515 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5956 11:45:42.552774 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5957 11:45:42.556144 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5958 11:45:42.562928 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5959 11:45:42.566254 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5960 11:45:42.569194 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5961 11:45:42.572410 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5962 11:45:42.575556 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5963 11:45:42.582446 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5964 11:45:42.585668 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5965 11:45:42.589096 iDelay=199, Bit 12, Center 98 (7 ~ 190) 184
5966 11:45:42.592076 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5967 11:45:42.595569 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5968 11:45:42.602120 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5969 11:45:42.602201 ==
5970 11:45:42.605961 Dram Type= 6, Freq= 0, CH_1, rank 1
5971 11:45:42.608979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5972 11:45:42.609082 ==
5973 11:45:42.609174 DQS Delay:
5974 11:45:42.612096 DQS0 = 0, DQS1 = 0
5975 11:45:42.612167 DQM Delay:
5976 11:45:42.615465 DQM0 = 97, DQM1 = 91
5977 11:45:42.615541 DQ Delay:
5978 11:45:42.618537 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
5979 11:45:42.621784 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =94
5980 11:45:42.625220 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5981 11:45:42.628453 DQ12 =98, DQ13 =100, DQ14 =96, DQ15 =100
5982 11:45:42.628551
5983 11:45:42.628643
5984 11:45:42.638683 [DQSOSCAuto] RK1, (LSB)MR18= 0xd23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5985 11:45:42.638763 CH1 RK1: MR19=505, MR18=D23
5986 11:45:42.644771 CH1_RK1: MR19=0x505, MR18=0xD23, DQSOSC=410, MR23=63, INC=64, DEC=42
5987 11:45:42.648180 [RxdqsGatingPostProcess] freq 933
5988 11:45:42.655323 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5989 11:45:42.658108 best DQS0 dly(2T, 0.5T) = (0, 10)
5990 11:45:42.661275 best DQS1 dly(2T, 0.5T) = (0, 10)
5991 11:45:42.664795 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5992 11:45:42.667762 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5993 11:45:42.671244 best DQS0 dly(2T, 0.5T) = (0, 10)
5994 11:45:42.671326 best DQS1 dly(2T, 0.5T) = (0, 10)
5995 11:45:42.674679 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5996 11:45:42.678122 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5997 11:45:42.681331 Pre-setting of DQS Precalculation
5998 11:45:42.687752 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5999 11:45:42.694842 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6000 11:45:42.700888 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6001 11:45:42.700968
6002 11:45:42.701031
6003 11:45:42.704941 [Calibration Summary] 1866 Mbps
6004 11:45:42.708026 CH 0, Rank 0
6005 11:45:42.708099 SW Impedance : PASS
6006 11:45:42.711430 DUTY Scan : NO K
6007 11:45:42.714454 ZQ Calibration : PASS
6008 11:45:42.714529 Jitter Meter : NO K
6009 11:45:42.717572 CBT Training : PASS
6010 11:45:42.720765 Write leveling : PASS
6011 11:45:42.720838 RX DQS gating : PASS
6012 11:45:42.724069 RX DQ/DQS(RDDQC) : PASS
6013 11:45:42.724149 TX DQ/DQS : PASS
6014 11:45:42.727502 RX DATLAT : PASS
6015 11:45:42.730410 RX DQ/DQS(Engine): PASS
6016 11:45:42.730509 TX OE : NO K
6017 11:45:42.733975 All Pass.
6018 11:45:42.734073
6019 11:45:42.734162 CH 0, Rank 1
6020 11:45:42.737398 SW Impedance : PASS
6021 11:45:42.737476 DUTY Scan : NO K
6022 11:45:42.740422 ZQ Calibration : PASS
6023 11:45:42.743808 Jitter Meter : NO K
6024 11:45:42.743882 CBT Training : PASS
6025 11:45:42.747213 Write leveling : PASS
6026 11:45:42.750643 RX DQS gating : PASS
6027 11:45:42.750742 RX DQ/DQS(RDDQC) : PASS
6028 11:45:42.753593 TX DQ/DQS : PASS
6029 11:45:42.756997 RX DATLAT : PASS
6030 11:45:42.757074 RX DQ/DQS(Engine): PASS
6031 11:45:42.760339 TX OE : NO K
6032 11:45:42.760415 All Pass.
6033 11:45:42.760477
6034 11:45:42.763825 CH 1, Rank 0
6035 11:45:42.763896 SW Impedance : PASS
6036 11:45:42.766584 DUTY Scan : NO K
6037 11:45:42.770168 ZQ Calibration : PASS
6038 11:45:42.770274 Jitter Meter : NO K
6039 11:45:42.773603 CBT Training : PASS
6040 11:45:42.776611 Write leveling : PASS
6041 11:45:42.776712 RX DQS gating : PASS
6042 11:45:42.780334 RX DQ/DQS(RDDQC) : PASS
6043 11:45:42.783497 TX DQ/DQS : PASS
6044 11:45:42.783570 RX DATLAT : PASS
6045 11:45:42.786676 RX DQ/DQS(Engine): PASS
6046 11:45:42.790340 TX OE : NO K
6047 11:45:42.790416 All Pass.
6048 11:45:42.790478
6049 11:45:42.790536 CH 1, Rank 1
6050 11:45:42.793515 SW Impedance : PASS
6051 11:45:42.796717 DUTY Scan : NO K
6052 11:45:42.796797 ZQ Calibration : PASS
6053 11:45:42.799866 Jitter Meter : NO K
6054 11:45:42.799957 CBT Training : PASS
6055 11:45:42.803182 Write leveling : PASS
6056 11:45:42.806870 RX DQS gating : PASS
6057 11:45:42.806944 RX DQ/DQS(RDDQC) : PASS
6058 11:45:42.809801 TX DQ/DQS : PASS
6059 11:45:42.813110 RX DATLAT : PASS
6060 11:45:42.813183 RX DQ/DQS(Engine): PASS
6061 11:45:42.816563 TX OE : NO K
6062 11:45:42.816635 All Pass.
6063 11:45:42.816700
6064 11:45:42.819561 DramC Write-DBI off
6065 11:45:42.822839 PER_BANK_REFRESH: Hybrid Mode
6066 11:45:42.822913 TX_TRACKING: ON
6067 11:45:42.832634 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6068 11:45:42.836242 [FAST_K] Save calibration result to emmc
6069 11:45:42.839385 dramc_set_vcore_voltage set vcore to 650000
6070 11:45:42.842443 Read voltage for 400, 6
6071 11:45:42.842518 Vio18 = 0
6072 11:45:42.846116 Vcore = 650000
6073 11:45:42.846217 Vdram = 0
6074 11:45:42.846338 Vddq = 0
6075 11:45:42.846398 Vmddr = 0
6076 11:45:42.852441 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6077 11:45:42.859170 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6078 11:45:42.859255 MEM_TYPE=3, freq_sel=20
6079 11:45:42.862233 sv_algorithm_assistance_LP4_800
6080 11:45:42.865743 ============ PULL DRAM RESETB DOWN ============
6081 11:45:42.872158 ========== PULL DRAM RESETB DOWN end =========
6082 11:45:42.875743 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6083 11:45:42.879006 ===================================
6084 11:45:42.882083 LPDDR4 DRAM CONFIGURATION
6085 11:45:42.885454 ===================================
6086 11:45:42.885562 EX_ROW_EN[0] = 0x0
6087 11:45:42.888700 EX_ROW_EN[1] = 0x0
6088 11:45:42.888774 LP4Y_EN = 0x0
6089 11:45:42.892182 WORK_FSP = 0x0
6090 11:45:42.895477 WL = 0x2
6091 11:45:42.895576 RL = 0x2
6092 11:45:42.898945 BL = 0x2
6093 11:45:42.899018 RPST = 0x0
6094 11:45:42.902026 RD_PRE = 0x0
6095 11:45:42.902124 WR_PRE = 0x1
6096 11:45:42.905734 WR_PST = 0x0
6097 11:45:42.905809 DBI_WR = 0x0
6098 11:45:42.908417 DBI_RD = 0x0
6099 11:45:42.908492 OTF = 0x1
6100 11:45:42.912132 ===================================
6101 11:45:42.914832 ===================================
6102 11:45:42.918481 ANA top config
6103 11:45:42.921372 ===================================
6104 11:45:42.921468 DLL_ASYNC_EN = 0
6105 11:45:42.925097 ALL_SLAVE_EN = 1
6106 11:45:42.928369 NEW_RANK_MODE = 1
6107 11:45:42.931407 DLL_IDLE_MODE = 1
6108 11:45:42.935172 LP45_APHY_COMB_EN = 1
6109 11:45:42.935250 TX_ODT_DIS = 1
6110 11:45:42.938197 NEW_8X_MODE = 1
6111 11:45:42.941737 ===================================
6112 11:45:42.944614 ===================================
6113 11:45:42.948027 data_rate = 800
6114 11:45:42.950981 CKR = 1
6115 11:45:42.954194 DQ_P2S_RATIO = 4
6116 11:45:42.958040 ===================================
6117 11:45:42.961052 CA_P2S_RATIO = 4
6118 11:45:42.961126 DQ_CA_OPEN = 0
6119 11:45:42.964511 DQ_SEMI_OPEN = 1
6120 11:45:42.967686 CA_SEMI_OPEN = 1
6121 11:45:42.971135 CA_FULL_RATE = 0
6122 11:45:42.974531 DQ_CKDIV4_EN = 0
6123 11:45:42.977627 CA_CKDIV4_EN = 1
6124 11:45:42.977727 CA_PREDIV_EN = 0
6125 11:45:42.981050 PH8_DLY = 0
6126 11:45:42.984325 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6127 11:45:42.987810 DQ_AAMCK_DIV = 0
6128 11:45:42.990498 CA_AAMCK_DIV = 0
6129 11:45:42.993956 CA_ADMCK_DIV = 4
6130 11:45:42.994051 DQ_TRACK_CA_EN = 0
6131 11:45:42.997213 CA_PICK = 800
6132 11:45:43.000616 CA_MCKIO = 400
6133 11:45:43.003951 MCKIO_SEMI = 400
6134 11:45:43.007388 PLL_FREQ = 3016
6135 11:45:43.010350 DQ_UI_PI_RATIO = 32
6136 11:45:43.013899 CA_UI_PI_RATIO = 32
6137 11:45:43.017132 ===================================
6138 11:45:43.020559 ===================================
6139 11:45:43.020633 memory_type:LPDDR4
6140 11:45:43.023885 GP_NUM : 10
6141 11:45:43.026980 SRAM_EN : 1
6142 11:45:43.027062 MD32_EN : 0
6143 11:45:43.030301 ===================================
6144 11:45:43.033411 [ANA_INIT] >>>>>>>>>>>>>>
6145 11:45:43.036885 <<<<<< [CONFIGURE PHASE]: ANA_TX
6146 11:45:43.040306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6147 11:45:43.043999 ===================================
6148 11:45:43.046646 data_rate = 800,PCW = 0X7400
6149 11:45:43.050168 ===================================
6150 11:45:43.053532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6151 11:45:43.056738 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6152 11:45:43.070235 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6153 11:45:43.073613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6154 11:45:43.076867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6155 11:45:43.079672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6156 11:45:43.082820 [ANA_INIT] flow start
6157 11:45:43.086716 [ANA_INIT] PLL >>>>>>>>
6158 11:45:43.086914 [ANA_INIT] PLL <<<<<<<<
6159 11:45:43.089489 [ANA_INIT] MIDPI >>>>>>>>
6160 11:45:43.092724 [ANA_INIT] MIDPI <<<<<<<<
6161 11:45:43.095963 [ANA_INIT] DLL >>>>>>>>
6162 11:45:43.096070 [ANA_INIT] flow end
6163 11:45:43.099542 ============ LP4 DIFF to SE enter ============
6164 11:45:43.106324 ============ LP4 DIFF to SE exit ============
6165 11:45:43.106402 [ANA_INIT] <<<<<<<<<<<<<
6166 11:45:43.109819 [Flow] Enable top DCM control >>>>>
6167 11:45:43.112574 [Flow] Enable top DCM control <<<<<
6168 11:45:43.115647 Enable DLL master slave shuffle
6169 11:45:43.122318 ==============================================================
6170 11:45:43.122426 Gating Mode config
6171 11:45:43.128663 ==============================================================
6172 11:45:43.132086 Config description:
6173 11:45:43.141873 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6174 11:45:43.148966 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6175 11:45:43.151884 SELPH_MODE 0: By rank 1: By Phase
6176 11:45:43.158487 ==============================================================
6177 11:45:43.162029 GAT_TRACK_EN = 0
6178 11:45:43.165542 RX_GATING_MODE = 2
6179 11:45:43.168907 RX_GATING_TRACK_MODE = 2
6180 11:45:43.168989 SELPH_MODE = 1
6181 11:45:43.171943 PICG_EARLY_EN = 1
6182 11:45:43.175180 VALID_LAT_VALUE = 1
6183 11:45:43.181913 ==============================================================
6184 11:45:43.185027 Enter into Gating configuration >>>>
6185 11:45:43.188529 Exit from Gating configuration <<<<
6186 11:45:43.191726 Enter into DVFS_PRE_config >>>>>
6187 11:45:43.201386 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6188 11:45:43.204937 Exit from DVFS_PRE_config <<<<<
6189 11:45:43.208593 Enter into PICG configuration >>>>
6190 11:45:43.211517 Exit from PICG configuration <<<<
6191 11:45:43.214839 [RX_INPUT] configuration >>>>>
6192 11:45:43.218098 [RX_INPUT] configuration <<<<<
6193 11:45:43.221774 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6194 11:45:43.228652 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6195 11:45:43.234811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6196 11:45:43.241380 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6197 11:45:43.247919 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6198 11:45:43.254413 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6199 11:45:43.257507 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6200 11:45:43.260981 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6201 11:45:43.264298 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6202 11:45:43.270647 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6203 11:45:43.274229 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6204 11:45:43.277582 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6205 11:45:43.281089 ===================================
6206 11:45:43.284048 LPDDR4 DRAM CONFIGURATION
6207 11:45:43.287413 ===================================
6208 11:45:43.287587 EX_ROW_EN[0] = 0x0
6209 11:45:43.290919 EX_ROW_EN[1] = 0x0
6210 11:45:43.294018 LP4Y_EN = 0x0
6211 11:45:43.294295 WORK_FSP = 0x0
6212 11:45:43.297513 WL = 0x2
6213 11:45:43.297828 RL = 0x2
6214 11:45:43.300833 BL = 0x2
6215 11:45:43.301073 RPST = 0x0
6216 11:45:43.304309 RD_PRE = 0x0
6217 11:45:43.304618 WR_PRE = 0x1
6218 11:45:43.307447 WR_PST = 0x0
6219 11:45:43.307836 DBI_WR = 0x0
6220 11:45:43.310877 DBI_RD = 0x0
6221 11:45:43.311282 OTF = 0x1
6222 11:45:43.313817 ===================================
6223 11:45:43.317132 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6224 11:45:43.323622 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6225 11:45:43.327106 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6226 11:45:43.330525 ===================================
6227 11:45:43.333622 LPDDR4 DRAM CONFIGURATION
6228 11:45:43.336861 ===================================
6229 11:45:43.337491 EX_ROW_EN[0] = 0x10
6230 11:45:43.340170 EX_ROW_EN[1] = 0x0
6231 11:45:43.344003 LP4Y_EN = 0x0
6232 11:45:43.344422 WORK_FSP = 0x0
6233 11:45:43.346781 WL = 0x2
6234 11:45:43.347199 RL = 0x2
6235 11:45:43.350217 BL = 0x2
6236 11:45:43.350693 RPST = 0x0
6237 11:45:43.353609 RD_PRE = 0x0
6238 11:45:43.354028 WR_PRE = 0x1
6239 11:45:43.356784 WR_PST = 0x0
6240 11:45:43.357200 DBI_WR = 0x0
6241 11:45:43.359799 DBI_RD = 0x0
6242 11:45:43.360217 OTF = 0x1
6243 11:45:43.363201 ===================================
6244 11:45:43.369917 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6245 11:45:43.374326 nWR fixed to 30
6246 11:45:43.377919 [ModeRegInit_LP4] CH0 RK0
6247 11:45:43.378404 [ModeRegInit_LP4] CH0 RK1
6248 11:45:43.380837 [ModeRegInit_LP4] CH1 RK0
6249 11:45:43.384204 [ModeRegInit_LP4] CH1 RK1
6250 11:45:43.384759 match AC timing 19
6251 11:45:43.391091 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6252 11:45:43.394536 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6253 11:45:43.397424 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6254 11:45:43.404423 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6255 11:45:43.407344 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6256 11:45:43.407930 ==
6257 11:45:43.411009 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 11:45:43.413954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 11:45:43.414465 ==
6260 11:45:43.420324 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6261 11:45:43.426945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6262 11:45:43.430314 [CA 0] Center 36 (8~64) winsize 57
6263 11:45:43.434198 [CA 1] Center 36 (8~64) winsize 57
6264 11:45:43.436645 [CA 2] Center 36 (8~64) winsize 57
6265 11:45:43.440319 [CA 3] Center 36 (8~64) winsize 57
6266 11:45:43.443694 [CA 4] Center 36 (8~64) winsize 57
6267 11:45:43.446554 [CA 5] Center 36 (8~64) winsize 57
6268 11:45:43.447492
6269 11:45:43.450302 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6270 11:45:43.451090
6271 11:45:43.453031 [CATrainingPosCal] consider 1 rank data
6272 11:45:43.456943 u2DelayCellTimex100 = 270/100 ps
6273 11:45:43.460114 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 11:45:43.463291 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 11:45:43.466534 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 11:45:43.469673 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 11:45:43.473295 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 11:45:43.476604 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 11:45:43.477087
6280 11:45:43.483287 CA PerBit enable=1, Macro0, CA PI delay=36
6281 11:45:43.483905
6282 11:45:43.486157 [CBTSetCACLKResult] CA Dly = 36
6283 11:45:43.486824 CS Dly: 1 (0~32)
6284 11:45:43.487340 ==
6285 11:45:43.489584 Dram Type= 6, Freq= 0, CH_0, rank 1
6286 11:45:43.493061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 11:45:43.493702 ==
6288 11:45:43.499237 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6289 11:45:43.506194 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6290 11:45:43.509482 [CA 0] Center 36 (8~64) winsize 57
6291 11:45:43.512247 [CA 1] Center 36 (8~64) winsize 57
6292 11:45:43.515902 [CA 2] Center 36 (8~64) winsize 57
6293 11:45:43.519453 [CA 3] Center 36 (8~64) winsize 57
6294 11:45:43.522292 [CA 4] Center 36 (8~64) winsize 57
6295 11:45:43.525724 [CA 5] Center 36 (8~64) winsize 57
6296 11:45:43.526146
6297 11:45:43.528878 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6298 11:45:43.529295
6299 11:45:43.532456 [CATrainingPosCal] consider 2 rank data
6300 11:45:43.535901 u2DelayCellTimex100 = 270/100 ps
6301 11:45:43.538738 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 11:45:43.542399 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 11:45:43.545724 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 11:45:43.548722 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:45:43.551929 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 11:45:43.555465 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 11:45:43.555905
6308 11:45:43.561654 CA PerBit enable=1, Macro0, CA PI delay=36
6309 11:45:43.562080
6310 11:45:43.562492 [CBTSetCACLKResult] CA Dly = 36
6311 11:45:43.565217 CS Dly: 1 (0~32)
6312 11:45:43.565688
6313 11:45:43.568603 ----->DramcWriteLeveling(PI) begin...
6314 11:45:43.569030 ==
6315 11:45:43.571815 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 11:45:43.574989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 11:45:43.575560 ==
6318 11:45:43.578858 Write leveling (Byte 0): 40 => 8
6319 11:45:43.581421 Write leveling (Byte 1): 40 => 8
6320 11:45:43.585564 DramcWriteLeveling(PI) end<-----
6321 11:45:43.586117
6322 11:45:43.586624 ==
6323 11:45:43.588511 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 11:45:43.591975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 11:45:43.595467 ==
6326 11:45:43.595981 [Gating] SW mode calibration
6327 11:45:43.604804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6328 11:45:43.607992 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6329 11:45:43.611487 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6330 11:45:43.617559 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6331 11:45:43.621194 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6332 11:45:43.624498 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 11:45:43.631112 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 11:45:43.634203 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 11:45:43.637797 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 11:45:43.644076 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 11:45:43.647550 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 11:45:43.650869 Total UI for P1: 0, mck2ui 16
6339 11:45:43.654142 best dqsien dly found for B0: ( 0, 14, 24)
6340 11:45:43.657325 Total UI for P1: 0, mck2ui 16
6341 11:45:43.660868 best dqsien dly found for B1: ( 0, 14, 24)
6342 11:45:43.663661 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6343 11:45:43.667127 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6344 11:45:43.667654
6345 11:45:43.673344 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6346 11:45:43.676901 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6347 11:45:43.677380 [Gating] SW calibration Done
6348 11:45:43.680644 ==
6349 11:45:43.683297 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 11:45:43.686921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 11:45:43.687451 ==
6352 11:45:43.687833 RX Vref Scan: 0
6353 11:45:43.688248
6354 11:45:43.689853 RX Vref 0 -> 0, step: 1
6355 11:45:43.690381
6356 11:45:43.693135 RX Delay -410 -> 252, step: 16
6357 11:45:43.696462 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6358 11:45:43.702947 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6359 11:45:43.706242 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6360 11:45:43.710108 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6361 11:45:43.712653 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6362 11:45:43.719614 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6363 11:45:43.722997 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6364 11:45:43.725953 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6365 11:45:43.729623 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6366 11:45:43.736045 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6367 11:45:43.739354 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6368 11:45:43.742719 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6369 11:45:43.746222 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6370 11:45:43.752992 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6371 11:45:43.755763 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6372 11:45:43.759340 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6373 11:45:43.759764 ==
6374 11:45:43.762175 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 11:45:43.769198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 11:45:43.769613 ==
6377 11:45:43.769941 DQS Delay:
6378 11:45:43.772171 DQS0 = 35, DQS1 = 59
6379 11:45:43.772582 DQM Delay:
6380 11:45:43.772909 DQM0 = 4, DQM1 = 18
6381 11:45:43.775608 DQ Delay:
6382 11:45:43.778617 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6383 11:45:43.778697 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6384 11:45:43.781621 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6385 11:45:43.785153 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6386 11:45:43.788206
6387 11:45:43.788285
6388 11:45:43.788347 ==
6389 11:45:43.791703 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 11:45:43.795137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 11:45:43.795217 ==
6392 11:45:43.795280
6393 11:45:43.795338
6394 11:45:43.798472 TX Vref Scan disable
6395 11:45:43.798551 == TX Byte 0 ==
6396 11:45:43.801363 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 11:45:43.808560 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 11:45:43.808640 == TX Byte 1 ==
6399 11:45:43.811854 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 11:45:43.817780 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 11:45:43.817860 ==
6402 11:45:43.821025 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 11:45:43.824344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 11:45:43.824424 ==
6405 11:45:43.824487
6406 11:45:43.824546
6407 11:45:43.827818 TX Vref Scan disable
6408 11:45:43.827898 == TX Byte 0 ==
6409 11:45:43.834726 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6410 11:45:43.837522 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6411 11:45:43.837627 == TX Byte 1 ==
6412 11:45:43.844594 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6413 11:45:43.848016 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6414 11:45:43.848097
6415 11:45:43.848160 [DATLAT]
6416 11:45:43.850879 Freq=400, CH0 RK0
6417 11:45:43.850959
6418 11:45:43.851022 DATLAT Default: 0xf
6419 11:45:43.854899 0, 0xFFFF, sum = 0
6420 11:45:43.854981 1, 0xFFFF, sum = 0
6421 11:45:43.857516 2, 0xFFFF, sum = 0
6422 11:45:43.857597 3, 0xFFFF, sum = 0
6423 11:45:43.860968 4, 0xFFFF, sum = 0
6424 11:45:43.861077 5, 0xFFFF, sum = 0
6425 11:45:43.864502 6, 0xFFFF, sum = 0
6426 11:45:43.864584 7, 0xFFFF, sum = 0
6427 11:45:43.867556 8, 0xFFFF, sum = 0
6428 11:45:43.867637 9, 0xFFFF, sum = 0
6429 11:45:43.871123 10, 0xFFFF, sum = 0
6430 11:45:43.873840 11, 0xFFFF, sum = 0
6431 11:45:43.873946 12, 0xFFFF, sum = 0
6432 11:45:43.877316 13, 0x0, sum = 1
6433 11:45:43.877398 14, 0x0, sum = 2
6434 11:45:43.880833 15, 0x0, sum = 3
6435 11:45:43.880915 16, 0x0, sum = 4
6436 11:45:43.880980 best_step = 14
6437 11:45:43.881038
6438 11:45:43.884119 ==
6439 11:45:43.887441 Dram Type= 6, Freq= 0, CH_0, rank 0
6440 11:45:43.890460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 11:45:43.890536 ==
6442 11:45:43.890599 RX Vref Scan: 1
6443 11:45:43.890668
6444 11:45:43.893864 RX Vref 0 -> 0, step: 1
6445 11:45:43.893933
6446 11:45:43.897371 RX Delay -359 -> 252, step: 8
6447 11:45:43.897440
6448 11:45:43.900307 Set Vref, RX VrefLevel [Byte0]: 56
6449 11:45:43.903323 [Byte1]: 50
6450 11:45:43.907621
6451 11:45:43.907705 Final RX Vref Byte 0 = 56 to rank0
6452 11:45:43.911121 Final RX Vref Byte 1 = 50 to rank0
6453 11:45:43.913911 Final RX Vref Byte 0 = 56 to rank1
6454 11:45:43.917581 Final RX Vref Byte 1 = 50 to rank1==
6455 11:45:43.920937 Dram Type= 6, Freq= 0, CH_0, rank 0
6456 11:45:43.927189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 11:45:43.927270 ==
6458 11:45:43.927333 DQS Delay:
6459 11:45:43.930704 DQS0 = 44, DQS1 = 60
6460 11:45:43.930784 DQM Delay:
6461 11:45:43.930847 DQM0 = 10, DQM1 = 17
6462 11:45:43.934169 DQ Delay:
6463 11:45:43.937735 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6464 11:45:43.940878 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6465 11:45:43.943851 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6466 11:45:43.946854 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =28
6467 11:45:43.946947
6468 11:45:43.947019
6469 11:45:43.953896 [DQSOSCAuto] RK0, (LSB)MR18= 0x8f83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6470 11:45:43.957255 CH0 RK0: MR19=C0C, MR18=8F83
6471 11:45:43.963482 CH0_RK0: MR19=0xC0C, MR18=0x8F83, DQSOSC=391, MR23=63, INC=386, DEC=257
6472 11:45:43.963617 ==
6473 11:45:43.966968 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 11:45:43.970154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 11:45:43.970318 ==
6476 11:45:43.973513 [Gating] SW mode calibration
6477 11:45:43.980077 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6478 11:45:43.986930 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6479 11:45:43.990216 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6480 11:45:43.993537 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6481 11:45:43.999977 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6482 11:45:44.003371 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 11:45:44.006765 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 11:45:44.013247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 11:45:44.016754 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 11:45:44.022842 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 11:45:44.026612 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 11:45:44.029352 Total UI for P1: 0, mck2ui 16
6489 11:45:44.032566 best dqsien dly found for B0: ( 0, 14, 24)
6490 11:45:44.036564 Total UI for P1: 0, mck2ui 16
6491 11:45:44.039423 best dqsien dly found for B1: ( 0, 14, 24)
6492 11:45:44.042798 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6493 11:45:44.046164 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6494 11:45:44.046618
6495 11:45:44.049392 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6496 11:45:44.052475 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6497 11:45:44.056269 [Gating] SW calibration Done
6498 11:45:44.056684 ==
6499 11:45:44.059167 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 11:45:44.062429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 11:45:44.065643 ==
6502 11:45:44.066156 RX Vref Scan: 0
6503 11:45:44.066535
6504 11:45:44.069632 RX Vref 0 -> 0, step: 1
6505 11:45:44.070047
6506 11:45:44.072210 RX Delay -410 -> 252, step: 16
6507 11:45:44.075417 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6508 11:45:44.078983 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6509 11:45:44.082224 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6510 11:45:44.088843 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6511 11:45:44.092207 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6512 11:45:44.095475 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6513 11:45:44.098800 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6514 11:45:44.105299 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6515 11:45:44.108708 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6516 11:45:44.112086 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6517 11:45:44.115444 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6518 11:45:44.121561 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6519 11:45:44.125445 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6520 11:45:44.128185 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6521 11:45:44.135062 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6522 11:45:44.138275 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6523 11:45:44.138830 ==
6524 11:45:44.141838 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 11:45:44.145375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 11:45:44.145825 ==
6527 11:45:44.148462 DQS Delay:
6528 11:45:44.148875 DQS0 = 35, DQS1 = 59
6529 11:45:44.149207 DQM Delay:
6530 11:45:44.151607 DQM0 = 6, DQM1 = 17
6531 11:45:44.152021 DQ Delay:
6532 11:45:44.155197 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6533 11:45:44.158430 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6534 11:45:44.162101 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6535 11:45:44.165159 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6536 11:45:44.165575
6537 11:45:44.165969
6538 11:45:44.166342 ==
6539 11:45:44.168007 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 11:45:44.171425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 11:45:44.174792 ==
6542 11:45:44.175206
6543 11:45:44.175532
6544 11:45:44.175837 TX Vref Scan disable
6545 11:45:44.178274 == TX Byte 0 ==
6546 11:45:44.180951 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6547 11:45:44.185073 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6548 11:45:44.188011 == TX Byte 1 ==
6549 11:45:44.191331 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6550 11:45:44.194373 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6551 11:45:44.194867 ==
6552 11:45:44.197565 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 11:45:44.204461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 11:45:44.205008 ==
6555 11:45:44.205433
6556 11:45:44.205784
6557 11:45:44.206202 TX Vref Scan disable
6558 11:45:44.207929 == TX Byte 0 ==
6559 11:45:44.211395 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6560 11:45:44.214408 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6561 11:45:44.217975 == TX Byte 1 ==
6562 11:45:44.221055 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6563 11:45:44.224187 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6564 11:45:44.224601
6565 11:45:44.227671 [DATLAT]
6566 11:45:44.228084 Freq=400, CH0 RK1
6567 11:45:44.228415
6568 11:45:44.230855 DATLAT Default: 0xe
6569 11:45:44.231269 0, 0xFFFF, sum = 0
6570 11:45:44.234124 1, 0xFFFF, sum = 0
6571 11:45:44.234617 2, 0xFFFF, sum = 0
6572 11:45:44.237566 3, 0xFFFF, sum = 0
6573 11:45:44.237985 4, 0xFFFF, sum = 0
6574 11:45:44.240752 5, 0xFFFF, sum = 0
6575 11:45:44.241173 6, 0xFFFF, sum = 0
6576 11:45:44.244100 7, 0xFFFF, sum = 0
6577 11:45:44.244519 8, 0xFFFF, sum = 0
6578 11:45:44.247264 9, 0xFFFF, sum = 0
6579 11:45:44.247686 10, 0xFFFF, sum = 0
6580 11:45:44.250793 11, 0xFFFF, sum = 0
6581 11:45:44.254128 12, 0xFFFF, sum = 0
6582 11:45:44.254597 13, 0x0, sum = 1
6583 11:45:44.257185 14, 0x0, sum = 2
6584 11:45:44.257605 15, 0x0, sum = 3
6585 11:45:44.257946 16, 0x0, sum = 4
6586 11:45:44.260594 best_step = 14
6587 11:45:44.261005
6588 11:45:44.261329 ==
6589 11:45:44.263771 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 11:45:44.267560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 11:45:44.267980 ==
6592 11:45:44.270749 RX Vref Scan: 0
6593 11:45:44.271164
6594 11:45:44.271492 RX Vref 0 -> 0, step: 1
6595 11:45:44.273826
6596 11:45:44.274339 RX Delay -359 -> 252, step: 8
6597 11:45:44.282304 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6598 11:45:44.285777 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6599 11:45:44.288782 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6600 11:45:44.295694 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6601 11:45:44.299080 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6602 11:45:44.303284 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6603 11:45:44.305380 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6604 11:45:44.311729 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6605 11:45:44.315339 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6606 11:45:44.318605 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6607 11:45:44.322009 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6608 11:45:44.328532 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6609 11:45:44.331524 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6610 11:45:44.334845 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6611 11:45:44.341714 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6612 11:45:44.345148 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6613 11:45:44.345566 ==
6614 11:45:44.347846 Dram Type= 6, Freq= 0, CH_0, rank 1
6615 11:45:44.351235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 11:45:44.351651 ==
6617 11:45:44.354443 DQS Delay:
6618 11:45:44.354936 DQS0 = 44, DQS1 = 60
6619 11:45:44.355299 DQM Delay:
6620 11:45:44.358229 DQM0 = 9, DQM1 = 15
6621 11:45:44.358651 DQ Delay:
6622 11:45:44.360870 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6623 11:45:44.364304 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6624 11:45:44.367687 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6625 11:45:44.371063 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6626 11:45:44.371621
6627 11:45:44.372003
6628 11:45:44.380841 [DQSOSCAuto] RK1, (LSB)MR18= 0x8a84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6629 11:45:44.381491 CH0 RK1: MR19=C0C, MR18=8A84
6630 11:45:44.387370 CH0_RK1: MR19=0xC0C, MR18=0x8A84, DQSOSC=392, MR23=63, INC=384, DEC=256
6631 11:45:44.390457 [RxdqsGatingPostProcess] freq 400
6632 11:45:44.397091 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6633 11:45:44.400637 best DQS0 dly(2T, 0.5T) = (0, 10)
6634 11:45:44.404144 best DQS1 dly(2T, 0.5T) = (0, 10)
6635 11:45:44.407446 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6636 11:45:44.410296 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6637 11:45:44.413679 best DQS0 dly(2T, 0.5T) = (0, 10)
6638 11:45:44.416981 best DQS1 dly(2T, 0.5T) = (0, 10)
6639 11:45:44.420527 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6640 11:45:44.423387 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6641 11:45:44.426967 Pre-setting of DQS Precalculation
6642 11:45:44.430183 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6643 11:45:44.430732 ==
6644 11:45:44.433734 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 11:45:44.436977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 11:45:44.437396 ==
6647 11:45:44.443486 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6648 11:45:44.449747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6649 11:45:44.452903 [CA 0] Center 36 (8~64) winsize 57
6650 11:45:44.456223 [CA 1] Center 36 (8~64) winsize 57
6651 11:45:44.459563 [CA 2] Center 36 (8~64) winsize 57
6652 11:45:44.462636 [CA 3] Center 36 (8~64) winsize 57
6653 11:45:44.466030 [CA 4] Center 36 (8~64) winsize 57
6654 11:45:44.469511 [CA 5] Center 36 (8~64) winsize 57
6655 11:45:44.469592
6656 11:45:44.472576 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6657 11:45:44.472656
6658 11:45:44.475965 [CATrainingPosCal] consider 1 rank data
6659 11:45:44.479154 u2DelayCellTimex100 = 270/100 ps
6660 11:45:44.482244 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 11:45:44.485793 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 11:45:44.489027 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 11:45:44.492277 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 11:45:44.496197 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 11:45:44.498929 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 11:45:44.499022
6667 11:45:44.505634 CA PerBit enable=1, Macro0, CA PI delay=36
6668 11:45:44.505734
6669 11:45:44.505813 [CBTSetCACLKResult] CA Dly = 36
6670 11:45:44.508857 CS Dly: 1 (0~32)
6671 11:45:44.509003 ==
6672 11:45:44.511940 Dram Type= 6, Freq= 0, CH_1, rank 1
6673 11:45:44.515415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 11:45:44.515571 ==
6675 11:45:44.521916 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6676 11:45:44.529017 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6677 11:45:44.531921 [CA 0] Center 36 (8~64) winsize 57
6678 11:45:44.535255 [CA 1] Center 36 (8~64) winsize 57
6679 11:45:44.538637 [CA 2] Center 36 (8~64) winsize 57
6680 11:45:44.542045 [CA 3] Center 36 (8~64) winsize 57
6681 11:45:44.542352 [CA 4] Center 36 (8~64) winsize 57
6682 11:45:44.545550 [CA 5] Center 36 (8~64) winsize 57
6683 11:45:44.545845
6684 11:45:44.551928 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6685 11:45:44.552334
6686 11:45:44.555321 [CATrainingPosCal] consider 2 rank data
6687 11:45:44.558547 u2DelayCellTimex100 = 270/100 ps
6688 11:45:44.561756 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 11:45:44.565082 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 11:45:44.568703 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 11:45:44.572051 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:45:44.574607 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 11:45:44.578358 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 11:45:44.578774
6695 11:45:44.581424 CA PerBit enable=1, Macro0, CA PI delay=36
6696 11:45:44.584679
6697 11:45:44.585092 [CBTSetCACLKResult] CA Dly = 36
6698 11:45:44.587922 CS Dly: 1 (0~32)
6699 11:45:44.588335
6700 11:45:44.591248 ----->DramcWriteLeveling(PI) begin...
6701 11:45:44.591671 ==
6702 11:45:44.594832 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 11:45:44.597713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 11:45:44.598342 ==
6705 11:45:44.600923 Write leveling (Byte 0): 40 => 8
6706 11:45:44.604520 Write leveling (Byte 1): 40 => 8
6707 11:45:44.608048 DramcWriteLeveling(PI) end<-----
6708 11:45:44.608462
6709 11:45:44.608789 ==
6710 11:45:44.611054 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 11:45:44.614824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 11:45:44.617442 ==
6713 11:45:44.617978 [Gating] SW mode calibration
6714 11:45:44.627746 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6715 11:45:44.630792 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6716 11:45:44.634049 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6717 11:45:44.640508 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6718 11:45:44.643757 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6719 11:45:44.647387 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 11:45:44.653585 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 11:45:44.657157 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 11:45:44.660458 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 11:45:44.666549 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 11:45:44.670425 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 11:45:44.673573 Total UI for P1: 0, mck2ui 16
6726 11:45:44.676961 best dqsien dly found for B0: ( 0, 14, 24)
6727 11:45:44.680294 Total UI for P1: 0, mck2ui 16
6728 11:45:44.683063 best dqsien dly found for B1: ( 0, 14, 24)
6729 11:45:44.686985 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6730 11:45:44.690050 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6731 11:45:44.690503
6732 11:45:44.693038 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6733 11:45:44.700110 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6734 11:45:44.700524 [Gating] SW calibration Done
6735 11:45:44.700858 ==
6736 11:45:44.702888 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 11:45:44.709446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 11:45:44.709868 ==
6739 11:45:44.710202 RX Vref Scan: 0
6740 11:45:44.710569
6741 11:45:44.712922 RX Vref 0 -> 0, step: 1
6742 11:45:44.713335
6743 11:45:44.716337 RX Delay -410 -> 252, step: 16
6744 11:45:44.719581 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6745 11:45:44.722811 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6746 11:45:44.729595 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6747 11:45:44.732546 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6748 11:45:44.736290 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6749 11:45:44.739257 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6750 11:45:44.745975 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6751 11:45:44.749353 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6752 11:45:44.752710 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6753 11:45:44.755980 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6754 11:45:44.762097 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6755 11:45:44.765847 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6756 11:45:44.769373 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6757 11:45:44.775997 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6758 11:45:44.779107 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6759 11:45:44.782124 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6760 11:45:44.782590 ==
6761 11:45:44.785733 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 11:45:44.789025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 11:45:44.792015 ==
6764 11:45:44.792427 DQS Delay:
6765 11:45:44.792834 DQS0 = 35, DQS1 = 51
6766 11:45:44.795522 DQM Delay:
6767 11:45:44.795937 DQM0 = 6, DQM1 = 13
6768 11:45:44.799068 DQ Delay:
6769 11:45:44.799481 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6770 11:45:44.801763 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6771 11:45:44.805464 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6772 11:45:44.808237 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6773 11:45:44.808654
6774 11:45:44.808999
6775 11:45:44.811513 ==
6776 11:45:44.815527 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 11:45:44.818303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 11:45:44.818724 ==
6779 11:45:44.819112
6780 11:45:44.819429
6781 11:45:44.821999 TX Vref Scan disable
6782 11:45:44.822484 == TX Byte 0 ==
6783 11:45:44.824826 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 11:45:44.831920 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 11:45:44.832340 == TX Byte 1 ==
6786 11:45:44.835169 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 11:45:44.841513 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 11:45:44.841927 ==
6789 11:45:44.844838 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 11:45:44.847847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 11:45:44.848264 ==
6792 11:45:44.848596
6793 11:45:44.848957
6794 11:45:44.851733 TX Vref Scan disable
6795 11:45:44.852180 == TX Byte 0 ==
6796 11:45:44.854673 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6797 11:45:44.861294 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6798 11:45:44.861831 == TX Byte 1 ==
6799 11:45:44.864363 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6800 11:45:44.870925 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6801 11:45:44.871403
6802 11:45:44.871736 [DATLAT]
6803 11:45:44.874395 Freq=400, CH1 RK0
6804 11:45:44.874791
6805 11:45:44.875117 DATLAT Default: 0xf
6806 11:45:44.877407 0, 0xFFFF, sum = 0
6807 11:45:44.877828 1, 0xFFFF, sum = 0
6808 11:45:44.880973 2, 0xFFFF, sum = 0
6809 11:45:44.881397 3, 0xFFFF, sum = 0
6810 11:45:44.883886 4, 0xFFFF, sum = 0
6811 11:45:44.884326 5, 0xFFFF, sum = 0
6812 11:45:44.887551 6, 0xFFFF, sum = 0
6813 11:45:44.887974 7, 0xFFFF, sum = 0
6814 11:45:44.890909 8, 0xFFFF, sum = 0
6815 11:45:44.891330 9, 0xFFFF, sum = 0
6816 11:45:44.893976 10, 0xFFFF, sum = 0
6817 11:45:44.896966 11, 0xFFFF, sum = 0
6818 11:45:44.897384 12, 0xFFFF, sum = 0
6819 11:45:44.900760 13, 0x0, sum = 1
6820 11:45:44.901184 14, 0x0, sum = 2
6821 11:45:44.901522 15, 0x0, sum = 3
6822 11:45:44.903926 16, 0x0, sum = 4
6823 11:45:44.904345 best_step = 14
6824 11:45:44.904687
6825 11:45:44.907412 ==
6826 11:45:44.907878 Dram Type= 6, Freq= 0, CH_1, rank 0
6827 11:45:44.914224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 11:45:44.914681 ==
6829 11:45:44.915014 RX Vref Scan: 1
6830 11:45:44.915320
6831 11:45:44.917320 RX Vref 0 -> 0, step: 1
6832 11:45:44.917803
6833 11:45:44.920056 RX Delay -343 -> 252, step: 8
6834 11:45:44.920594
6835 11:45:44.923922 Set Vref, RX VrefLevel [Byte0]: 52
6836 11:45:44.926761 [Byte1]: 52
6837 11:45:44.930679
6838 11:45:44.931182 Final RX Vref Byte 0 = 52 to rank0
6839 11:45:44.934080 Final RX Vref Byte 1 = 52 to rank0
6840 11:45:44.936909 Final RX Vref Byte 0 = 52 to rank1
6841 11:45:44.940782 Final RX Vref Byte 1 = 52 to rank1==
6842 11:45:44.943704 Dram Type= 6, Freq= 0, CH_1, rank 0
6843 11:45:44.950465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 11:45:44.950882 ==
6845 11:45:44.951212 DQS Delay:
6846 11:45:44.953906 DQS0 = 44, DQS1 = 52
6847 11:45:44.954522 DQM Delay:
6848 11:45:44.955002 DQM0 = 11, DQM1 = 10
6849 11:45:44.956744 DQ Delay:
6850 11:45:44.960396 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6851 11:45:44.964098 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6852 11:45:44.964514 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6853 11:45:44.966695 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6854 11:45:44.967108
6855 11:45:44.970307
6856 11:45:44.977062 [DQSOSCAuto] RK0, (LSB)MR18= 0x678e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 396 ps
6857 11:45:44.979893 CH1 RK0: MR19=C0C, MR18=678E
6858 11:45:44.986759 CH1_RK0: MR19=0xC0C, MR18=0x678E, DQSOSC=392, MR23=63, INC=384, DEC=256
6859 11:45:44.987193 ==
6860 11:45:44.990200 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 11:45:44.992958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 11:45:44.993374 ==
6863 11:45:44.996327 [Gating] SW mode calibration
6864 11:45:45.003300 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6865 11:45:45.010102 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6866 11:45:45.013224 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6867 11:45:45.016073 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6868 11:45:45.022968 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6869 11:45:45.026131 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 11:45:45.029471 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 11:45:45.036334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 11:45:45.039449 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 11:45:45.042861 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 11:45:45.049527 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 11:45:45.050174 Total UI for P1: 0, mck2ui 16
6876 11:45:45.055794 best dqsien dly found for B0: ( 0, 14, 24)
6877 11:45:45.056257 Total UI for P1: 0, mck2ui 16
6878 11:45:45.062523 best dqsien dly found for B1: ( 0, 14, 24)
6879 11:45:45.065819 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6880 11:45:45.069205 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6881 11:45:45.069761
6882 11:45:45.072750 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6883 11:45:45.075942 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6884 11:45:45.078484 [Gating] SW calibration Done
6885 11:45:45.078908 ==
6886 11:45:45.081988 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 11:45:45.085508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 11:45:45.085955 ==
6889 11:45:45.088866 RX Vref Scan: 0
6890 11:45:45.089328
6891 11:45:45.091773 RX Vref 0 -> 0, step: 1
6892 11:45:45.092192
6893 11:45:45.092524 RX Delay -410 -> 252, step: 16
6894 11:45:45.098958 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6895 11:45:45.101443 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6896 11:45:45.105095 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6897 11:45:45.111619 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6898 11:45:45.115265 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6899 11:45:45.118335 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6900 11:45:45.121337 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6901 11:45:45.128277 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6902 11:45:45.131143 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6903 11:45:45.134527 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6904 11:45:45.138327 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6905 11:45:45.144761 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6906 11:45:45.148057 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6907 11:45:45.151463 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6908 11:45:45.154497 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6909 11:45:45.161395 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6910 11:45:45.161810 ==
6911 11:45:45.164265 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 11:45:45.167966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 11:45:45.168402 ==
6914 11:45:45.168768 DQS Delay:
6915 11:45:45.171544 DQS0 = 43, DQS1 = 51
6916 11:45:45.172027 DQM Delay:
6917 11:45:45.174093 DQM0 = 9, DQM1 = 13
6918 11:45:45.174556 DQ Delay:
6919 11:45:45.178300 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6920 11:45:45.181250 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6921 11:45:45.184450 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6922 11:45:45.187305 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6923 11:45:45.187767
6924 11:45:45.188113
6925 11:45:45.188420 ==
6926 11:45:45.190565 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 11:45:45.194185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 11:45:45.194643 ==
6929 11:45:45.197485
6930 11:45:45.197896
6931 11:45:45.198225 TX Vref Scan disable
6932 11:45:45.200913 == TX Byte 0 ==
6933 11:45:45.203872 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6934 11:45:45.207217 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6935 11:45:45.210491 == TX Byte 1 ==
6936 11:45:45.213568 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6937 11:45:45.216982 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6938 11:45:45.217397 ==
6939 11:45:45.220287 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 11:45:45.223729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 11:45:45.227301 ==
6942 11:45:45.227714
6943 11:45:45.228041
6944 11:45:45.228350 TX Vref Scan disable
6945 11:45:45.230575 == TX Byte 0 ==
6946 11:45:45.233770 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6947 11:45:45.236809 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6948 11:45:45.240052 == TX Byte 1 ==
6949 11:45:45.243736 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6950 11:45:45.246878 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6951 11:45:45.247403
6952 11:45:45.249924 [DATLAT]
6953 11:45:45.250377 Freq=400, CH1 RK1
6954 11:45:45.250715
6955 11:45:45.253076 DATLAT Default: 0xe
6956 11:45:45.253489 0, 0xFFFF, sum = 0
6957 11:45:45.256651 1, 0xFFFF, sum = 0
6958 11:45:45.257074 2, 0xFFFF, sum = 0
6959 11:45:45.259732 3, 0xFFFF, sum = 0
6960 11:45:45.260153 4, 0xFFFF, sum = 0
6961 11:45:45.263291 5, 0xFFFF, sum = 0
6962 11:45:45.263712 6, 0xFFFF, sum = 0
6963 11:45:45.265920 7, 0xFFFF, sum = 0
6964 11:45:45.266522 8, 0xFFFF, sum = 0
6965 11:45:45.269440 9, 0xFFFF, sum = 0
6966 11:45:45.269858 10, 0xFFFF, sum = 0
6967 11:45:45.272618 11, 0xFFFF, sum = 0
6968 11:45:45.275926 12, 0xFFFF, sum = 0
6969 11:45:45.276347 13, 0x0, sum = 1
6970 11:45:45.279317 14, 0x0, sum = 2
6971 11:45:45.279816 15, 0x0, sum = 3
6972 11:45:45.280155 16, 0x0, sum = 4
6973 11:45:45.283089 best_step = 14
6974 11:45:45.283518
6975 11:45:45.283863 ==
6976 11:45:45.286015 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 11:45:45.289230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 11:45:45.289647 ==
6979 11:45:45.292867 RX Vref Scan: 0
6980 11:45:45.293279
6981 11:45:45.293610 RX Vref 0 -> 0, step: 1
6982 11:45:45.295901
6983 11:45:45.296319 RX Delay -343 -> 252, step: 8
6984 11:45:45.304682 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6985 11:45:45.307598 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6986 11:45:45.311327 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6987 11:45:45.317901 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6988 11:45:45.321167 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6989 11:45:45.324604 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6990 11:45:45.327761 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6991 11:45:45.334025 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6992 11:45:45.337319 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6993 11:45:45.341098 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6994 11:45:45.344476 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6995 11:45:45.350809 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6996 11:45:45.353952 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6997 11:45:45.357176 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6998 11:45:45.360817 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6999 11:45:45.367114 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
7000 11:45:45.367529 ==
7001 11:45:45.370876 Dram Type= 6, Freq= 0, CH_1, rank 1
7002 11:45:45.373691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7003 11:45:45.374334 ==
7004 11:45:45.377050 DQS Delay:
7005 11:45:45.377468 DQS0 = 48, DQS1 = 52
7006 11:45:45.377795 DQM Delay:
7007 11:45:45.380216 DQM0 = 11, DQM1 = 10
7008 11:45:45.380663 DQ Delay:
7009 11:45:45.383687 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
7010 11:45:45.387098 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
7011 11:45:45.389978 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7012 11:45:45.393323 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7013 11:45:45.393746
7014 11:45:45.394114
7015 11:45:45.403795 [DQSOSCAuto] RK1, (LSB)MR18= 0x78b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
7016 11:45:45.404230 CH1 RK1: MR19=C0C, MR18=78B0
7017 11:45:45.410295 CH1_RK1: MR19=0xC0C, MR18=0x78B0, DQSOSC=387, MR23=63, INC=394, DEC=262
7018 11:45:45.413225 [RxdqsGatingPostProcess] freq 400
7019 11:45:45.419551 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7020 11:45:45.422895 best DQS0 dly(2T, 0.5T) = (0, 10)
7021 11:45:45.426338 best DQS1 dly(2T, 0.5T) = (0, 10)
7022 11:45:45.429513 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7023 11:45:45.433439 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7024 11:45:45.436325 best DQS0 dly(2T, 0.5T) = (0, 10)
7025 11:45:45.436745 best DQS1 dly(2T, 0.5T) = (0, 10)
7026 11:45:45.439834 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7027 11:45:45.443225 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7028 11:45:45.446444 Pre-setting of DQS Precalculation
7029 11:45:45.452929 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7030 11:45:45.459539 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7031 11:45:45.466206 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7032 11:45:45.466765
7033 11:45:45.467213
7034 11:45:45.469239 [Calibration Summary] 800 Mbps
7035 11:45:45.472854 CH 0, Rank 0
7036 11:45:45.473423 SW Impedance : PASS
7037 11:45:45.475771 DUTY Scan : NO K
7038 11:45:45.479265 ZQ Calibration : PASS
7039 11:45:45.479685 Jitter Meter : NO K
7040 11:45:45.482675 CBT Training : PASS
7041 11:45:45.485787 Write leveling : PASS
7042 11:45:45.486206 RX DQS gating : PASS
7043 11:45:45.489283 RX DQ/DQS(RDDQC) : PASS
7044 11:45:45.489700 TX DQ/DQS : PASS
7045 11:45:45.492636 RX DATLAT : PASS
7046 11:45:45.495530 RX DQ/DQS(Engine): PASS
7047 11:45:45.495949 TX OE : NO K
7048 11:45:45.499347 All Pass.
7049 11:45:45.499760
7050 11:45:45.500092 CH 0, Rank 1
7051 11:45:45.502198 SW Impedance : PASS
7052 11:45:45.502649 DUTY Scan : NO K
7053 11:45:45.505717 ZQ Calibration : PASS
7054 11:45:45.509075 Jitter Meter : NO K
7055 11:45:45.509493 CBT Training : PASS
7056 11:45:45.512242 Write leveling : NO K
7057 11:45:45.515561 RX DQS gating : PASS
7058 11:45:45.515982 RX DQ/DQS(RDDQC) : PASS
7059 11:45:45.518721 TX DQ/DQS : PASS
7060 11:45:45.522173 RX DATLAT : PASS
7061 11:45:45.522648 RX DQ/DQS(Engine): PASS
7062 11:45:45.525489 TX OE : NO K
7063 11:45:45.525908 All Pass.
7064 11:45:45.526239
7065 11:45:45.528142 CH 1, Rank 0
7066 11:45:45.528555 SW Impedance : PASS
7067 11:45:45.531705 DUTY Scan : NO K
7068 11:45:45.535117 ZQ Calibration : PASS
7069 11:45:45.535598 Jitter Meter : NO K
7070 11:45:45.538567 CBT Training : PASS
7071 11:45:45.541570 Write leveling : PASS
7072 11:45:45.541986 RX DQS gating : PASS
7073 11:45:45.544981 RX DQ/DQS(RDDQC) : PASS
7074 11:45:45.548588 TX DQ/DQS : PASS
7075 11:45:45.549008 RX DATLAT : PASS
7076 11:45:45.551351 RX DQ/DQS(Engine): PASS
7077 11:45:45.555048 TX OE : NO K
7078 11:45:45.555467 All Pass.
7079 11:45:45.555898
7080 11:45:45.556226 CH 1, Rank 1
7081 11:45:45.558221 SW Impedance : PASS
7082 11:45:45.561567 DUTY Scan : NO K
7083 11:45:45.562018 ZQ Calibration : PASS
7084 11:45:45.564541 Jitter Meter : NO K
7085 11:45:45.568202 CBT Training : PASS
7086 11:45:45.568619 Write leveling : NO K
7087 11:45:45.571337 RX DQS gating : PASS
7088 11:45:45.574507 RX DQ/DQS(RDDQC) : PASS
7089 11:45:45.574925 TX DQ/DQS : PASS
7090 11:45:45.577778 RX DATLAT : PASS
7091 11:45:45.578194 RX DQ/DQS(Engine): PASS
7092 11:45:45.581370 TX OE : NO K
7093 11:45:45.581825 All Pass.
7094 11:45:45.582157
7095 11:45:45.584874 DramC Write-DBI off
7096 11:45:45.588482 PER_BANK_REFRESH: Hybrid Mode
7097 11:45:45.588903 TX_TRACKING: ON
7098 11:45:45.597372 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7099 11:45:45.601083 [FAST_K] Save calibration result to emmc
7100 11:45:45.604453 dramc_set_vcore_voltage set vcore to 725000
7101 11:45:45.607397 Read voltage for 1600, 0
7102 11:45:45.607816 Vio18 = 0
7103 11:45:45.610989 Vcore = 725000
7104 11:45:45.611411 Vdram = 0
7105 11:45:45.611746 Vddq = 0
7106 11:45:45.612051 Vmddr = 0
7107 11:45:45.617726 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7108 11:45:45.623796 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7109 11:45:45.624217 MEM_TYPE=3, freq_sel=13
7110 11:45:45.627153 sv_algorithm_assistance_LP4_3733
7111 11:45:45.630392 ============ PULL DRAM RESETB DOWN ============
7112 11:45:45.636798 ========== PULL DRAM RESETB DOWN end =========
7113 11:45:45.640222 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7114 11:45:45.643673 ===================================
7115 11:45:45.647151 LPDDR4 DRAM CONFIGURATION
7116 11:45:45.650785 ===================================
7117 11:45:45.651299 EX_ROW_EN[0] = 0x0
7118 11:45:45.653578 EX_ROW_EN[1] = 0x0
7119 11:45:45.657228 LP4Y_EN = 0x0
7120 11:45:45.657781 WORK_FSP = 0x1
7121 11:45:45.660756 WL = 0x5
7122 11:45:45.661327 RL = 0x5
7123 11:45:45.663392 BL = 0x2
7124 11:45:45.663974 RPST = 0x0
7125 11:45:45.667069 RD_PRE = 0x0
7126 11:45:45.667487 WR_PRE = 0x1
7127 11:45:45.669961 WR_PST = 0x1
7128 11:45:45.670521 DBI_WR = 0x0
7129 11:45:45.673446 DBI_RD = 0x0
7130 11:45:45.673853 OTF = 0x1
7131 11:45:45.677042 ===================================
7132 11:45:45.680221 ===================================
7133 11:45:45.683169 ANA top config
7134 11:45:45.686615 ===================================
7135 11:45:45.690142 DLL_ASYNC_EN = 0
7136 11:45:45.690756 ALL_SLAVE_EN = 0
7137 11:45:45.693107 NEW_RANK_MODE = 1
7138 11:45:45.696645 DLL_IDLE_MODE = 1
7139 11:45:45.699378 LP45_APHY_COMB_EN = 1
7140 11:45:45.700020 TX_ODT_DIS = 0
7141 11:45:45.703000 NEW_8X_MODE = 1
7142 11:45:45.706201 ===================================
7143 11:45:45.709383 ===================================
7144 11:45:45.712799 data_rate = 3200
7145 11:45:45.716179 CKR = 1
7146 11:45:45.719730 DQ_P2S_RATIO = 8
7147 11:45:45.722421 ===================================
7148 11:45:45.726064 CA_P2S_RATIO = 8
7149 11:45:45.729439 DQ_CA_OPEN = 0
7150 11:45:45.729851 DQ_SEMI_OPEN = 0
7151 11:45:45.732245 CA_SEMI_OPEN = 0
7152 11:45:45.735740 CA_FULL_RATE = 0
7153 11:45:45.738942 DQ_CKDIV4_EN = 0
7154 11:45:45.742681 CA_CKDIV4_EN = 0
7155 11:45:45.745710 CA_PREDIV_EN = 0
7156 11:45:45.746306 PH8_DLY = 12
7157 11:45:45.749020 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7158 11:45:45.752291 DQ_AAMCK_DIV = 4
7159 11:45:45.757897 CA_AAMCK_DIV = 4
7160 11:45:45.758874 CA_ADMCK_DIV = 4
7161 11:45:45.762164 DQ_TRACK_CA_EN = 0
7162 11:45:45.765645 CA_PICK = 1600
7163 11:45:45.766061 CA_MCKIO = 1600
7164 11:45:45.768954 MCKIO_SEMI = 0
7165 11:45:45.772448 PLL_FREQ = 3068
7166 11:45:45.775286 DQ_UI_PI_RATIO = 32
7167 11:45:45.778970 CA_UI_PI_RATIO = 0
7168 11:45:45.781675 ===================================
7169 11:45:45.785138 ===================================
7170 11:45:45.788501 memory_type:LPDDR4
7171 11:45:45.788927 GP_NUM : 10
7172 11:45:45.792150 SRAM_EN : 1
7173 11:45:45.792572 MD32_EN : 0
7174 11:45:45.795070 ===================================
7175 11:45:45.798644 [ANA_INIT] >>>>>>>>>>>>>>
7176 11:45:45.801540 <<<<<< [CONFIGURE PHASE]: ANA_TX
7177 11:45:45.805003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7178 11:45:45.808210 ===================================
7179 11:45:45.811181 data_rate = 3200,PCW = 0X7600
7180 11:45:45.815116 ===================================
7181 11:45:45.817878 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7182 11:45:45.824477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7183 11:45:45.827807 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7184 11:45:45.834701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7185 11:45:45.837524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7186 11:45:45.841017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7187 11:45:45.841463 [ANA_INIT] flow start
7188 11:45:45.844240 [ANA_INIT] PLL >>>>>>>>
7189 11:45:45.847647 [ANA_INIT] PLL <<<<<<<<
7190 11:45:45.851069 [ANA_INIT] MIDPI >>>>>>>>
7191 11:45:45.851547 [ANA_INIT] MIDPI <<<<<<<<
7192 11:45:45.854063 [ANA_INIT] DLL >>>>>>>>
7193 11:45:45.857742 [ANA_INIT] DLL <<<<<<<<
7194 11:45:45.858337 [ANA_INIT] flow end
7195 11:45:45.860841 ============ LP4 DIFF to SE enter ============
7196 11:45:45.867200 ============ LP4 DIFF to SE exit ============
7197 11:45:45.867630 [ANA_INIT] <<<<<<<<<<<<<
7198 11:45:45.870754 [Flow] Enable top DCM control >>>>>
7199 11:45:45.873784 [Flow] Enable top DCM control <<<<<
7200 11:45:45.877288 Enable DLL master slave shuffle
7201 11:45:45.883641 ==============================================================
7202 11:45:45.886995 Gating Mode config
7203 11:45:45.890514 ==============================================================
7204 11:45:45.894033 Config description:
7205 11:45:45.903768 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7206 11:45:45.910189 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7207 11:45:45.913612 SELPH_MODE 0: By rank 1: By Phase
7208 11:45:45.920206 ==============================================================
7209 11:45:45.923616 GAT_TRACK_EN = 1
7210 11:45:45.926756 RX_GATING_MODE = 2
7211 11:45:45.930094 RX_GATING_TRACK_MODE = 2
7212 11:45:45.933331 SELPH_MODE = 1
7213 11:45:45.933753 PICG_EARLY_EN = 1
7214 11:45:45.936922 VALID_LAT_VALUE = 1
7215 11:45:45.943048 ==============================================================
7216 11:45:45.946288 Enter into Gating configuration >>>>
7217 11:45:45.949920 Exit from Gating configuration <<<<
7218 11:45:45.953094 Enter into DVFS_PRE_config >>>>>
7219 11:45:45.962848 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7220 11:45:45.966133 Exit from DVFS_PRE_config <<<<<
7221 11:45:45.969545 Enter into PICG configuration >>>>
7222 11:45:45.973199 Exit from PICG configuration <<<<
7223 11:45:45.976215 [RX_INPUT] configuration >>>>>
7224 11:45:45.979605 [RX_INPUT] configuration <<<<<
7225 11:45:45.985895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7226 11:45:45.989244 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7227 11:45:45.995866 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7228 11:45:46.002306 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7229 11:45:46.009043 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7230 11:45:46.015386 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7231 11:45:46.019023 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7232 11:45:46.021888 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7233 11:45:46.025404 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7234 11:45:46.032185 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7235 11:45:46.035088 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7236 11:45:46.038380 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7237 11:45:46.041862 ===================================
7238 11:45:46.044991 LPDDR4 DRAM CONFIGURATION
7239 11:45:46.048352 ===================================
7240 11:45:46.050965 EX_ROW_EN[0] = 0x0
7241 11:45:46.051046 EX_ROW_EN[1] = 0x0
7242 11:45:46.054803 LP4Y_EN = 0x0
7243 11:45:46.054884 WORK_FSP = 0x1
7244 11:45:46.058142 WL = 0x5
7245 11:45:46.058226 RL = 0x5
7246 11:45:46.061149 BL = 0x2
7247 11:45:46.061230 RPST = 0x0
7248 11:45:46.064279 RD_PRE = 0x0
7249 11:45:46.064366 WR_PRE = 0x1
7250 11:45:46.067785 WR_PST = 0x1
7251 11:45:46.067878 DBI_WR = 0x0
7252 11:45:46.070626 DBI_RD = 0x0
7253 11:45:46.074382 OTF = 0x1
7254 11:45:46.077662 ===================================
7255 11:45:46.080520 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7256 11:45:46.084571 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7257 11:45:46.087405 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7258 11:45:46.090971 ===================================
7259 11:45:46.094153 LPDDR4 DRAM CONFIGURATION
7260 11:45:46.097330 ===================================
7261 11:45:46.101087 EX_ROW_EN[0] = 0x10
7262 11:45:46.101500 EX_ROW_EN[1] = 0x0
7263 11:45:46.104148 LP4Y_EN = 0x0
7264 11:45:46.104562 WORK_FSP = 0x1
7265 11:45:46.107588 WL = 0x5
7266 11:45:46.108001 RL = 0x5
7267 11:45:46.111017 BL = 0x2
7268 11:45:46.111430 RPST = 0x0
7269 11:45:46.114146 RD_PRE = 0x0
7270 11:45:46.114595 WR_PRE = 0x1
7271 11:45:46.117306 WR_PST = 0x1
7272 11:45:46.120732 DBI_WR = 0x0
7273 11:45:46.121145 DBI_RD = 0x0
7274 11:45:46.123514 OTF = 0x1
7275 11:45:46.127147 ===================================
7276 11:45:46.130853 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7277 11:45:46.133579 ==
7278 11:45:46.137058 Dram Type= 6, Freq= 0, CH_0, rank 0
7279 11:45:46.140146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7280 11:45:46.140568 ==
7281 11:45:46.143558 [Duty_Offset_Calibration]
7282 11:45:46.143981 B0:2 B1:0 CA:4
7283 11:45:46.144316
7284 11:45:46.146581 [DutyScan_Calibration_Flow] k_type=0
7285 11:45:46.155866
7286 11:45:46.156283 ==CLK 0==
7287 11:45:46.159546 Final CLK duty delay cell = -4
7288 11:45:46.162932 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7289 11:45:46.165901 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7290 11:45:46.169233 [-4] AVG Duty = 4937%(X100)
7291 11:45:46.169660
7292 11:45:46.172528 CH0 CLK Duty spec in!! Max-Min= 187%
7293 11:45:46.175876 [DutyScan_Calibration_Flow] ====Done====
7294 11:45:46.176304
7295 11:45:46.179052 [DutyScan_Calibration_Flow] k_type=1
7296 11:45:46.196079
7297 11:45:46.196578 ==DQS 0 ==
7298 11:45:46.199624 Final DQS duty delay cell = 0
7299 11:45:46.203084 [0] MAX Duty = 5218%(X100), DQS PI = 38
7300 11:45:46.206226 [0] MIN Duty = 5062%(X100), DQS PI = 14
7301 11:45:46.209526 [0] AVG Duty = 5140%(X100)
7302 11:45:46.209966
7303 11:45:46.210519 ==DQS 1 ==
7304 11:45:46.212808 Final DQS duty delay cell = 0
7305 11:45:46.215721 [0] MAX Duty = 5187%(X100), DQS PI = 2
7306 11:45:46.219031 [0] MIN Duty = 4969%(X100), DQS PI = 10
7307 11:45:46.222541 [0] AVG Duty = 5078%(X100)
7308 11:45:46.223013
7309 11:45:46.225684 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7310 11:45:46.226107
7311 11:45:46.228590 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7312 11:45:46.232002 [DutyScan_Calibration_Flow] ====Done====
7313 11:45:46.232462
7314 11:45:46.235732 [DutyScan_Calibration_Flow] k_type=3
7315 11:45:46.253355
7316 11:45:46.253856 ==DQM 0 ==
7317 11:45:46.256877 Final DQM duty delay cell = 0
7318 11:45:46.259934 [0] MAX Duty = 5124%(X100), DQS PI = 22
7319 11:45:46.263062 [0] MIN Duty = 4875%(X100), DQS PI = 56
7320 11:45:46.266177 [0] AVG Duty = 4999%(X100)
7321 11:45:46.266713
7322 11:45:46.267089 ==DQM 1 ==
7323 11:45:46.269796 Final DQM duty delay cell = 0
7324 11:45:46.273275 [0] MAX Duty = 5000%(X100), DQS PI = 2
7325 11:45:46.276079 [0] MIN Duty = 4844%(X100), DQS PI = 16
7326 11:45:46.279732 [0] AVG Duty = 4922%(X100)
7327 11:45:46.280194
7328 11:45:46.282809 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7329 11:45:46.283287
7330 11:45:46.286127 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7331 11:45:46.289399 [DutyScan_Calibration_Flow] ====Done====
7332 11:45:46.289795
7333 11:45:46.292745 [DutyScan_Calibration_Flow] k_type=2
7334 11:45:46.310514
7335 11:45:46.310596 ==DQ 0 ==
7336 11:45:46.313670 Final DQ duty delay cell = 0
7337 11:45:46.316686 [0] MAX Duty = 5124%(X100), DQS PI = 20
7338 11:45:46.320284 [0] MIN Duty = 4938%(X100), DQS PI = 12
7339 11:45:46.320357 [0] AVG Duty = 5031%(X100)
7340 11:45:46.323111
7341 11:45:46.323186 ==DQ 1 ==
7342 11:45:46.326708 Final DQ duty delay cell = 0
7343 11:45:46.329977 [0] MAX Duty = 5187%(X100), DQS PI = 2
7344 11:45:46.333180 [0] MIN Duty = 4938%(X100), DQS PI = 12
7345 11:45:46.333280 [0] AVG Duty = 5062%(X100)
7346 11:45:46.336517
7347 11:45:46.340011 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7348 11:45:46.340112
7349 11:45:46.342761 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7350 11:45:46.346121 [DutyScan_Calibration_Flow] ====Done====
7351 11:45:46.346226 ==
7352 11:45:46.349315 Dram Type= 6, Freq= 0, CH_1, rank 0
7353 11:45:46.353046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7354 11:45:46.353149 ==
7355 11:45:46.355934 [Duty_Offset_Calibration]
7356 11:45:46.356004 B0:0 B1:-1 CA:3
7357 11:45:46.356063
7358 11:45:46.359591 [DutyScan_Calibration_Flow] k_type=0
7359 11:45:46.369322
7360 11:45:46.369399 ==CLK 0==
7361 11:45:46.372724 Final CLK duty delay cell = -4
7362 11:45:46.375975 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7363 11:45:46.379537 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7364 11:45:46.382820 [-4] AVG Duty = 4922%(X100)
7365 11:45:46.382888
7366 11:45:46.385943 CH1 CLK Duty spec in!! Max-Min= 156%
7367 11:45:46.389144 [DutyScan_Calibration_Flow] ====Done====
7368 11:45:46.389220
7369 11:45:46.392754 [DutyScan_Calibration_Flow] k_type=1
7370 11:45:46.408846
7371 11:45:46.408925 ==DQS 0 ==
7372 11:45:46.412060 Final DQS duty delay cell = 0
7373 11:45:46.415170 [0] MAX Duty = 5250%(X100), DQS PI = 28
7374 11:45:46.418212 [0] MIN Duty = 4907%(X100), DQS PI = 58
7375 11:45:46.421856 [0] AVG Duty = 5078%(X100)
7376 11:45:46.421962
7377 11:45:46.422052 ==DQS 1 ==
7378 11:45:46.424970 Final DQS duty delay cell = -4
7379 11:45:46.428245 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7380 11:45:46.431522 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7381 11:45:46.434994 [-4] AVG Duty = 4906%(X100)
7382 11:45:46.435065
7383 11:45:46.438503 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7384 11:45:46.438570
7385 11:45:46.441737 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7386 11:45:46.445097 [DutyScan_Calibration_Flow] ====Done====
7387 11:45:46.445166
7388 11:45:46.448090 [DutyScan_Calibration_Flow] k_type=3
7389 11:45:46.466088
7390 11:45:46.466164 ==DQM 0 ==
7391 11:45:46.469074 Final DQM duty delay cell = 0
7392 11:45:46.472513 [0] MAX Duty = 5062%(X100), DQS PI = 30
7393 11:45:46.476149 [0] MIN Duty = 4782%(X100), DQS PI = 38
7394 11:45:46.479127 [0] AVG Duty = 4922%(X100)
7395 11:45:46.479197
7396 11:45:46.479255 ==DQM 1 ==
7397 11:45:46.482491 Final DQM duty delay cell = 0
7398 11:45:46.485812 [0] MAX Duty = 4969%(X100), DQS PI = 30
7399 11:45:46.488577 [0] MIN Duty = 4813%(X100), DQS PI = 0
7400 11:45:46.492171 [0] AVG Duty = 4891%(X100)
7401 11:45:46.492249
7402 11:45:46.495650 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7403 11:45:46.495724
7404 11:45:46.499081 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7405 11:45:46.501868 [DutyScan_Calibration_Flow] ====Done====
7406 11:45:46.501941
7407 11:45:46.505363 [DutyScan_Calibration_Flow] k_type=2
7408 11:45:46.522150
7409 11:45:46.522292 ==DQ 0 ==
7410 11:45:46.525659 Final DQ duty delay cell = -4
7411 11:45:46.528711 [-4] MAX Duty = 4938%(X100), DQS PI = 8
7412 11:45:46.531566 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7413 11:45:46.535159 [-4] AVG Duty = 4875%(X100)
7414 11:45:46.535236
7415 11:45:46.535298 ==DQ 1 ==
7416 11:45:46.538159 Final DQ duty delay cell = 0
7417 11:45:46.541523 [0] MAX Duty = 5062%(X100), DQS PI = 32
7418 11:45:46.545123 [0] MIN Duty = 4875%(X100), DQS PI = 56
7419 11:45:46.548122 [0] AVG Duty = 4968%(X100)
7420 11:45:46.548197
7421 11:45:46.551293 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7422 11:45:46.551366
7423 11:45:46.554471 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7424 11:45:46.557694 [DutyScan_Calibration_Flow] ====Done====
7425 11:45:46.561114 nWR fixed to 30
7426 11:45:46.564691 [ModeRegInit_LP4] CH0 RK0
7427 11:45:46.564775 [ModeRegInit_LP4] CH0 RK1
7428 11:45:46.567700 [ModeRegInit_LP4] CH1 RK0
7429 11:45:46.571047 [ModeRegInit_LP4] CH1 RK1
7430 11:45:46.571116 match AC timing 5
7431 11:45:46.577447 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7432 11:45:46.581004 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7433 11:45:46.584263 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7434 11:45:46.591069 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7435 11:45:46.594096 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7436 11:45:46.597507 [MiockJmeterHQA]
7437 11:45:46.597582
7438 11:45:46.600804 [DramcMiockJmeter] u1RxGatingPI = 0
7439 11:45:46.600877 0 : 4365, 4140
7440 11:45:46.600938 4 : 4253, 4027
7441 11:45:46.603960 8 : 4253, 4026
7442 11:45:46.604054 12 : 4250, 4027
7443 11:45:46.607397 16 : 4255, 4029
7444 11:45:46.607499 20 : 4255, 4030
7445 11:45:46.610504 24 : 4255, 4029
7446 11:45:46.610575 28 : 4253, 4027
7447 11:45:46.613661 32 : 4254, 4029
7448 11:45:46.613729 36 : 4252, 4027
7449 11:45:46.613788 40 : 4253, 4026
7450 11:45:46.617177 44 : 4366, 4140
7451 11:45:46.617253 48 : 4253, 4026
7452 11:45:46.620704 52 : 4255, 4029
7453 11:45:46.620771 56 : 4252, 4027
7454 11:45:46.623954 60 : 4363, 4138
7455 11:45:46.624050 64 : 4250, 4027
7456 11:45:46.627720 68 : 4250, 4027
7457 11:45:46.627794 72 : 4250, 4027
7458 11:45:46.627853 76 : 4250, 4027
7459 11:45:46.630215 80 : 4252, 4027
7460 11:45:46.630302 84 : 4252, 4029
7461 11:45:46.633713 88 : 4360, 4138
7462 11:45:46.633816 92 : 4250, 4027
7463 11:45:46.637164 96 : 4250, 3139
7464 11:45:46.637241 100 : 4250, 0
7465 11:45:46.637309 104 : 4361, 0
7466 11:45:46.640257 108 : 4255, 0
7467 11:45:46.640324 112 : 4250, 0
7468 11:45:46.643837 116 : 4250, 0
7469 11:45:46.643946 120 : 4250, 0
7470 11:45:46.644039 124 : 4361, 0
7471 11:45:46.646613 128 : 4255, 0
7472 11:45:46.646701 132 : 4250, 0
7473 11:45:46.650515 136 : 4363, 0
7474 11:45:46.650597 140 : 4361, 0
7475 11:45:46.650663 144 : 4363, 0
7476 11:45:46.653552 148 : 4250, 0
7477 11:45:46.653634 152 : 4250, 0
7478 11:45:46.653698 156 : 4250, 0
7479 11:45:46.656905 160 : 4252, 0
7480 11:45:46.656987 164 : 4250, 0
7481 11:45:46.660269 168 : 4250, 0
7482 11:45:46.660351 172 : 4252, 0
7483 11:45:46.660416 176 : 4363, 0
7484 11:45:46.663164 180 : 4250, 0
7485 11:45:46.663246 184 : 4361, 0
7486 11:45:46.666470 188 : 4252, 0
7487 11:45:46.666614 192 : 4361, 0
7488 11:45:46.666679 196 : 4250, 0
7489 11:45:46.669754 200 : 4250, 0
7490 11:45:46.669835 204 : 4250, 0
7491 11:45:46.673149 208 : 4361, 0
7492 11:45:46.673231 212 : 4254, 0
7493 11:45:46.673295 216 : 4250, 0
7494 11:45:46.676691 220 : 4250, 499
7495 11:45:46.676772 224 : 4361, 4113
7496 11:45:46.679490 228 : 4254, 4030
7497 11:45:46.679572 232 : 4360, 4137
7498 11:45:46.683360 236 : 4250, 4027
7499 11:45:46.683441 240 : 4250, 4026
7500 11:45:46.686238 244 : 4250, 4027
7501 11:45:46.686356 248 : 4255, 4032
7502 11:45:46.689659 252 : 4250, 4027
7503 11:45:46.689740 256 : 4250, 4027
7504 11:45:46.693008 260 : 4250, 4027
7505 11:45:46.693091 264 : 4255, 4032
7506 11:45:46.693155 268 : 4250, 4027
7507 11:45:46.696323 272 : 4366, 4140
7508 11:45:46.696404 276 : 4361, 4137
7509 11:45:46.699774 280 : 4250, 4027
7510 11:45:46.699855 284 : 4250, 4027
7511 11:45:46.702667 288 : 4255, 4030
7512 11:45:46.702748 292 : 4250, 4026
7513 11:45:46.705990 296 : 4250, 4027
7514 11:45:46.706070 300 : 4250, 4027
7515 11:45:46.709580 304 : 4250, 4027
7516 11:45:46.709662 308 : 4250, 4027
7517 11:45:46.712518 312 : 4250, 4027
7518 11:45:46.712599 316 : 4250, 4027
7519 11:45:46.715916 320 : 4250, 4027
7520 11:45:46.715998 324 : 4361, 4138
7521 11:45:46.719308 328 : 4361, 4137
7522 11:45:46.719389 332 : 4247, 3893
7523 11:45:46.722132 336 : 4365, 1846
7524 11:45:46.722214
7525 11:45:46.722320 MIOCK jitter meter ch=0
7526 11:45:46.722380
7527 11:45:46.725556 1T = (336-100) = 236 dly cells
7528 11:45:46.732433 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7529 11:45:46.732514 ==
7530 11:45:46.735679 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 11:45:46.738957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 11:45:46.739038 ==
7533 11:45:46.745656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7534 11:45:46.748738 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7535 11:45:46.752141 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7536 11:45:46.758526 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7537 11:45:46.768309 [CA 0] Center 44 (14~74) winsize 61
7538 11:45:46.771829 [CA 1] Center 43 (13~74) winsize 62
7539 11:45:46.775117 [CA 2] Center 39 (10~68) winsize 59
7540 11:45:46.778106 [CA 3] Center 38 (9~68) winsize 60
7541 11:45:46.781450 [CA 4] Center 36 (6~66) winsize 61
7542 11:45:46.784871 [CA 5] Center 36 (6~66) winsize 61
7543 11:45:46.784952
7544 11:45:46.788334 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7545 11:45:46.788415
7546 11:45:46.794756 [CATrainingPosCal] consider 1 rank data
7547 11:45:46.794837 u2DelayCellTimex100 = 275/100 ps
7548 11:45:46.801656 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7549 11:45:46.804987 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7550 11:45:46.807831 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7551 11:45:46.811373 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7552 11:45:46.814830 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7553 11:45:46.817686 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7554 11:45:46.817766
7555 11:45:46.821289 CA PerBit enable=1, Macro0, CA PI delay=36
7556 11:45:46.821370
7557 11:45:46.824240 [CBTSetCACLKResult] CA Dly = 36
7558 11:45:46.827724 CS Dly: 10 (0~41)
7559 11:45:46.831392 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7560 11:45:46.834244 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7561 11:45:46.834364 ==
7562 11:45:46.837612 Dram Type= 6, Freq= 0, CH_0, rank 1
7563 11:45:46.844385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 11:45:46.844466 ==
7565 11:45:46.847267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7566 11:45:46.854415 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7567 11:45:46.857133 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7568 11:45:46.864178 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7569 11:45:46.871958 [CA 0] Center 43 (13~74) winsize 62
7570 11:45:46.875303 [CA 1] Center 43 (13~73) winsize 61
7571 11:45:46.878707 [CA 2] Center 38 (9~68) winsize 60
7572 11:45:46.882138 [CA 3] Center 38 (9~68) winsize 60
7573 11:45:46.885282 [CA 4] Center 37 (7~67) winsize 61
7574 11:45:46.888867 [CA 5] Center 36 (6~66) winsize 61
7575 11:45:46.888948
7576 11:45:46.891984 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7577 11:45:46.892066
7578 11:45:46.898350 [CATrainingPosCal] consider 2 rank data
7579 11:45:46.898430 u2DelayCellTimex100 = 275/100 ps
7580 11:45:46.904972 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7581 11:45:46.908696 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7582 11:45:46.911510 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7583 11:45:46.915022 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7584 11:45:46.918528 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7585 11:45:46.921387 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7586 11:45:46.921467
7587 11:45:46.924868 CA PerBit enable=1, Macro0, CA PI delay=36
7588 11:45:46.924948
7589 11:45:46.928212 [CBTSetCACLKResult] CA Dly = 36
7590 11:45:46.931651 CS Dly: 11 (0~43)
7591 11:45:46.934508 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7592 11:45:46.937934 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7593 11:45:46.938014
7594 11:45:46.941211 ----->DramcWriteLeveling(PI) begin...
7595 11:45:46.944783 ==
7596 11:45:46.944863 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 11:45:46.950876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 11:45:46.950956 ==
7599 11:45:46.954369 Write leveling (Byte 0): 35 => 35
7600 11:45:46.957382 Write leveling (Byte 1): 27 => 27
7601 11:45:46.960968 DramcWriteLeveling(PI) end<-----
7602 11:45:46.961046
7603 11:45:46.961108 ==
7604 11:45:46.964317 Dram Type= 6, Freq= 0, CH_0, rank 0
7605 11:45:46.967632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 11:45:46.967703 ==
7607 11:45:46.970947 [Gating] SW mode calibration
7608 11:45:46.977475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7609 11:45:46.984334 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7610 11:45:46.987577 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 11:45:46.990927 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 11:45:46.994562 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7613 11:45:47.000829 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7614 11:45:47.003757 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7615 11:45:47.007575 1 4 20 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
7616 11:45:47.013580 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 11:45:47.017108 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 11:45:47.023640 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 11:45:47.027134 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7620 11:45:47.030132 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7621 11:45:47.037006 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
7622 11:45:47.039783 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7623 11:45:47.043312 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7624 11:45:47.049717 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7625 11:45:47.053553 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 11:45:47.056337 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 11:45:47.063278 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 11:45:47.066199 1 6 8 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
7629 11:45:47.069695 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7630 11:45:47.076628 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7631 11:45:47.079726 1 6 20 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7632 11:45:47.082946 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 11:45:47.089222 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 11:45:47.092895 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 11:45:47.096096 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 11:45:47.102692 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7637 11:45:47.105643 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7638 11:45:47.109177 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7639 11:45:47.115554 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7640 11:45:47.118804 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7641 11:45:47.122392 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 11:45:47.128655 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 11:45:47.131849 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 11:45:47.135315 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 11:45:47.141910 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 11:45:47.145082 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 11:45:47.148679 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 11:45:47.154884 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 11:45:47.158162 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 11:45:47.161656 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 11:45:47.168291 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 11:45:47.171338 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7653 11:45:47.174768 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7654 11:45:47.181388 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7655 11:45:47.181461 Total UI for P1: 0, mck2ui 16
7656 11:45:47.188284 best dqsien dly found for B0: ( 1, 9, 10)
7657 11:45:47.191290 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7658 11:45:47.194819 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7659 11:45:47.201584 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 11:45:47.201677 Total UI for P1: 0, mck2ui 16
7661 11:45:47.207530 best dqsien dly found for B1: ( 1, 9, 24)
7662 11:45:47.210905 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7663 11:45:47.214442 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7664 11:45:47.214599
7665 11:45:47.218163 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7666 11:45:47.221240 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7667 11:45:47.224234 [Gating] SW calibration Done
7668 11:45:47.224391 ==
7669 11:45:47.227850 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 11:45:47.230802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 11:45:47.230968 ==
7672 11:45:47.234582 RX Vref Scan: 0
7673 11:45:47.234754
7674 11:45:47.237171 RX Vref 0 -> 0, step: 1
7675 11:45:47.237381
7676 11:45:47.237549 RX Delay 0 -> 252, step: 8
7677 11:45:47.243943 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7678 11:45:47.247441 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7679 11:45:47.250896 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7680 11:45:47.254342 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7681 11:45:47.257388 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7682 11:45:47.264107 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7683 11:45:47.266986 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7684 11:45:47.270306 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7685 11:45:47.273556 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7686 11:45:47.276738 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7687 11:45:47.283513 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7688 11:45:47.287188 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7689 11:45:47.290683 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7690 11:45:47.293654 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7691 11:45:47.300312 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7692 11:45:47.303201 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7693 11:45:47.303648 ==
7694 11:45:47.306465 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 11:45:47.309871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 11:45:47.310426 ==
7697 11:45:47.313679 DQS Delay:
7698 11:45:47.314290 DQS0 = 0, DQS1 = 0
7699 11:45:47.314733 DQM Delay:
7700 11:45:47.316704 DQM0 = 131, DQM1 = 126
7701 11:45:47.317177 DQ Delay:
7702 11:45:47.320072 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7703 11:45:47.323362 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7704 11:45:47.326213 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7705 11:45:47.332959 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7706 11:45:47.333406
7707 11:45:47.333746
7708 11:45:47.334073 ==
7709 11:45:47.336346 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 11:45:47.339615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 11:45:47.339976 ==
7712 11:45:47.340301
7713 11:45:47.340594
7714 11:45:47.343130 TX Vref Scan disable
7715 11:45:47.343581 == TX Byte 0 ==
7716 11:45:47.349871 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7717 11:45:47.352936 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7718 11:45:47.356313 == TX Byte 1 ==
7719 11:45:47.359419 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7720 11:45:47.362947 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7721 11:45:47.363391 ==
7722 11:45:47.366342 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 11:45:47.369318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 11:45:47.369876 ==
7725 11:45:47.385726
7726 11:45:47.389070 TX Vref early break, caculate TX vref
7727 11:45:47.392367 TX Vref=16, minBit 1, minWin=22, winSum=367
7728 11:45:47.395590 TX Vref=18, minBit 8, minWin=22, winSum=381
7729 11:45:47.399104 TX Vref=20, minBit 1, minWin=23, winSum=392
7730 11:45:47.401748 TX Vref=22, minBit 1, minWin=23, winSum=399
7731 11:45:47.405284 TX Vref=24, minBit 7, minWin=24, winSum=411
7732 11:45:47.411872 TX Vref=26, minBit 1, minWin=25, winSum=413
7733 11:45:47.415703 TX Vref=28, minBit 4, minWin=24, winSum=421
7734 11:45:47.418842 TX Vref=30, minBit 4, minWin=24, winSum=414
7735 11:45:47.421953 TX Vref=32, minBit 4, minWin=24, winSum=409
7736 11:45:47.425376 TX Vref=34, minBit 1, minWin=24, winSum=399
7737 11:45:47.428437 TX Vref=36, minBit 0, minWin=23, winSum=388
7738 11:45:47.435130 [TxChooseVref] Worse bit 1, Min win 25, Win sum 413, Final Vref 26
7739 11:45:47.435545
7740 11:45:47.438140 Final TX Range 0 Vref 26
7741 11:45:47.438604
7742 11:45:47.438931 ==
7743 11:45:47.441409 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 11:45:47.445237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 11:45:47.445653 ==
7746 11:45:47.448371
7747 11:45:47.448797
7748 11:45:47.449262 TX Vref Scan disable
7749 11:45:47.454885 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7750 11:45:47.455362 == TX Byte 0 ==
7751 11:45:47.457722 u2DelayCellOfst[0]=14 cells (4 PI)
7752 11:45:47.461293 u2DelayCellOfst[1]=17 cells (5 PI)
7753 11:45:47.464698 u2DelayCellOfst[2]=10 cells (3 PI)
7754 11:45:47.467738 u2DelayCellOfst[3]=14 cells (4 PI)
7755 11:45:47.471143 u2DelayCellOfst[4]=7 cells (2 PI)
7756 11:45:47.474556 u2DelayCellOfst[5]=0 cells (0 PI)
7757 11:45:47.477349 u2DelayCellOfst[6]=17 cells (5 PI)
7758 11:45:47.480898 u2DelayCellOfst[7]=21 cells (6 PI)
7759 11:45:47.484371 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7760 11:45:47.490966 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7761 11:45:47.491383 == TX Byte 1 ==
7762 11:45:47.493851 u2DelayCellOfst[8]=0 cells (0 PI)
7763 11:45:47.497296 u2DelayCellOfst[9]=0 cells (0 PI)
7764 11:45:47.500679 u2DelayCellOfst[10]=3 cells (1 PI)
7765 11:45:47.503605 u2DelayCellOfst[11]=0 cells (0 PI)
7766 11:45:47.506837 u2DelayCellOfst[12]=10 cells (3 PI)
7767 11:45:47.510177 u2DelayCellOfst[13]=10 cells (3 PI)
7768 11:45:47.513516 u2DelayCellOfst[14]=14 cells (4 PI)
7769 11:45:47.516925 u2DelayCellOfst[15]=10 cells (3 PI)
7770 11:45:47.520161 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7771 11:45:47.523662 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7772 11:45:47.526682 DramC Write-DBI on
7773 11:45:47.526759 ==
7774 11:45:47.530203 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 11:45:47.533396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 11:45:47.533468 ==
7777 11:45:47.533532
7778 11:45:47.533592
7779 11:45:47.536908 TX Vref Scan disable
7780 11:45:47.539793 == TX Byte 0 ==
7781 11:45:47.543207 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7782 11:45:47.543277 == TX Byte 1 ==
7783 11:45:47.549966 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7784 11:45:47.550053 DramC Write-DBI off
7785 11:45:47.550117
7786 11:45:47.550176 [DATLAT]
7787 11:45:47.552858 Freq=1600, CH0 RK0
7788 11:45:47.552938
7789 11:45:47.556620 DATLAT Default: 0xf
7790 11:45:47.556700 0, 0xFFFF, sum = 0
7791 11:45:47.559447 1, 0xFFFF, sum = 0
7792 11:45:47.559528 2, 0xFFFF, sum = 0
7793 11:45:47.562963 3, 0xFFFF, sum = 0
7794 11:45:47.563076 4, 0xFFFF, sum = 0
7795 11:45:47.566395 5, 0xFFFF, sum = 0
7796 11:45:47.566477 6, 0xFFFF, sum = 0
7797 11:45:47.569296 7, 0xFFFF, sum = 0
7798 11:45:47.569378 8, 0xFFFF, sum = 0
7799 11:45:47.572848 9, 0xFFFF, sum = 0
7800 11:45:47.572930 10, 0xFFFF, sum = 0
7801 11:45:47.575906 11, 0xFFFF, sum = 0
7802 11:45:47.575987 12, 0xFFFF, sum = 0
7803 11:45:47.579574 13, 0xFFFF, sum = 0
7804 11:45:47.579665 14, 0x0, sum = 1
7805 11:45:47.582693 15, 0x0, sum = 2
7806 11:45:47.582774 16, 0x0, sum = 3
7807 11:45:47.585890 17, 0x0, sum = 4
7808 11:45:47.585972 best_step = 15
7809 11:45:47.586036
7810 11:45:47.586096 ==
7811 11:45:47.588975 Dram Type= 6, Freq= 0, CH_0, rank 0
7812 11:45:47.595934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7813 11:45:47.596016 ==
7814 11:45:47.596080 RX Vref Scan: 1
7815 11:45:47.596140
7816 11:45:47.599339 Set Vref Range= 24 -> 127
7817 11:45:47.599419
7818 11:45:47.602170 RX Vref 24 -> 127, step: 1
7819 11:45:47.602260
7820 11:45:47.605749 RX Delay 11 -> 252, step: 4
7821 11:45:47.605829
7822 11:45:47.609172 Set Vref, RX VrefLevel [Byte0]: 24
7823 11:45:47.612329 [Byte1]: 24
7824 11:45:47.612410
7825 11:45:47.615892 Set Vref, RX VrefLevel [Byte0]: 25
7826 11:45:47.619449 [Byte1]: 25
7827 11:45:47.619530
7828 11:45:47.622213 Set Vref, RX VrefLevel [Byte0]: 26
7829 11:45:47.626089 [Byte1]: 26
7830 11:45:47.628817
7831 11:45:47.628896 Set Vref, RX VrefLevel [Byte0]: 27
7832 11:45:47.631850 [Byte1]: 27
7833 11:45:47.636519
7834 11:45:47.636621 Set Vref, RX VrefLevel [Byte0]: 28
7835 11:45:47.639585 [Byte1]: 28
7836 11:45:47.644462
7837 11:45:47.644542 Set Vref, RX VrefLevel [Byte0]: 29
7838 11:45:47.647175 [Byte1]: 29
7839 11:45:47.651825
7840 11:45:47.651905 Set Vref, RX VrefLevel [Byte0]: 30
7841 11:45:47.654780 [Byte1]: 30
7842 11:45:47.659483
7843 11:45:47.659563 Set Vref, RX VrefLevel [Byte0]: 31
7844 11:45:47.662314 [Byte1]: 31
7845 11:45:47.666871
7846 11:45:47.666951 Set Vref, RX VrefLevel [Byte0]: 32
7847 11:45:47.670363 [Byte1]: 32
7848 11:45:47.674537
7849 11:45:47.674617 Set Vref, RX VrefLevel [Byte0]: 33
7850 11:45:47.677954 [Byte1]: 33
7851 11:45:47.682534
7852 11:45:47.682613 Set Vref, RX VrefLevel [Byte0]: 34
7853 11:45:47.685468 [Byte1]: 34
7854 11:45:47.690338
7855 11:45:47.690419 Set Vref, RX VrefLevel [Byte0]: 35
7856 11:45:47.692822 [Byte1]: 35
7857 11:45:47.697307
7858 11:45:47.697393 Set Vref, RX VrefLevel [Byte0]: 36
7859 11:45:47.700430 [Byte1]: 36
7860 11:45:47.705052
7861 11:45:47.705132 Set Vref, RX VrefLevel [Byte0]: 37
7862 11:45:47.708379 [Byte1]: 37
7863 11:45:47.712381
7864 11:45:47.712461 Set Vref, RX VrefLevel [Byte0]: 38
7865 11:45:47.715955 [Byte1]: 38
7866 11:45:47.720153
7867 11:45:47.720234 Set Vref, RX VrefLevel [Byte0]: 39
7868 11:45:47.723748 [Byte1]: 39
7869 11:45:47.727772
7870 11:45:47.727882 Set Vref, RX VrefLevel [Byte0]: 40
7871 11:45:47.731388 [Byte1]: 40
7872 11:45:47.735661
7873 11:45:47.735741 Set Vref, RX VrefLevel [Byte0]: 41
7874 11:45:47.738955 [Byte1]: 41
7875 11:45:47.743178
7876 11:45:47.743258 Set Vref, RX VrefLevel [Byte0]: 42
7877 11:45:47.746149 [Byte1]: 42
7878 11:45:47.750785
7879 11:45:47.750865 Set Vref, RX VrefLevel [Byte0]: 43
7880 11:45:47.754134 [Byte1]: 43
7881 11:45:47.758036
7882 11:45:47.758121 Set Vref, RX VrefLevel [Byte0]: 44
7883 11:45:47.761532 [Byte1]: 44
7884 11:45:47.766281
7885 11:45:47.766375 Set Vref, RX VrefLevel [Byte0]: 45
7886 11:45:47.769068 [Byte1]: 45
7887 11:45:47.773962
7888 11:45:47.774042 Set Vref, RX VrefLevel [Byte0]: 46
7889 11:45:47.777004 [Byte1]: 46
7890 11:45:47.780999
7891 11:45:47.781079 Set Vref, RX VrefLevel [Byte0]: 47
7892 11:45:47.784445 [Byte1]: 47
7893 11:45:47.788681
7894 11:45:47.788761 Set Vref, RX VrefLevel [Byte0]: 48
7895 11:45:47.792149 [Byte1]: 48
7896 11:45:47.796385
7897 11:45:47.796465 Set Vref, RX VrefLevel [Byte0]: 49
7898 11:45:47.802572 [Byte1]: 49
7899 11:45:47.802653
7900 11:45:47.805919 Set Vref, RX VrefLevel [Byte0]: 50
7901 11:45:47.809321 [Byte1]: 50
7902 11:45:47.809402
7903 11:45:47.813019 Set Vref, RX VrefLevel [Byte0]: 51
7904 11:45:47.816031 [Byte1]: 51
7905 11:45:47.819798
7906 11:45:47.819877 Set Vref, RX VrefLevel [Byte0]: 52
7907 11:45:47.822704 [Byte1]: 52
7908 11:45:47.827215
7909 11:45:47.827295 Set Vref, RX VrefLevel [Byte0]: 53
7910 11:45:47.830050 [Byte1]: 53
7911 11:45:47.834991
7912 11:45:47.835071 Set Vref, RX VrefLevel [Byte0]: 54
7913 11:45:47.837631 [Byte1]: 54
7914 11:45:47.842196
7915 11:45:47.842299 Set Vref, RX VrefLevel [Byte0]: 55
7916 11:45:47.845183 [Byte1]: 55
7917 11:45:47.849715
7918 11:45:47.849795 Set Vref, RX VrefLevel [Byte0]: 56
7919 11:45:47.853396 [Byte1]: 56
7920 11:45:47.857638
7921 11:45:47.858086 Set Vref, RX VrefLevel [Byte0]: 57
7922 11:45:47.861113 [Byte1]: 57
7923 11:45:47.865215
7924 11:45:47.865625 Set Vref, RX VrefLevel [Byte0]: 58
7925 11:45:47.868388 [Byte1]: 58
7926 11:45:47.873275
7927 11:45:47.873819 Set Vref, RX VrefLevel [Byte0]: 59
7928 11:45:47.876020 [Byte1]: 59
7929 11:45:47.880655
7930 11:45:47.881067 Set Vref, RX VrefLevel [Byte0]: 60
7931 11:45:47.884063 [Byte1]: 60
7932 11:45:47.887995
7933 11:45:47.888408 Set Vref, RX VrefLevel [Byte0]: 61
7934 11:45:47.891229 [Byte1]: 61
7935 11:45:47.895812
7936 11:45:47.896363 Set Vref, RX VrefLevel [Byte0]: 62
7937 11:45:47.899364 [Byte1]: 62
7938 11:45:47.903467
7939 11:45:47.903880 Set Vref, RX VrefLevel [Byte0]: 63
7940 11:45:47.906728 [Byte1]: 63
7941 11:45:47.911157
7942 11:45:47.911604 Set Vref, RX VrefLevel [Byte0]: 64
7943 11:45:47.914149 [Byte1]: 64
7944 11:45:47.918613
7945 11:45:47.919020 Set Vref, RX VrefLevel [Byte0]: 65
7946 11:45:47.922120 [Byte1]: 65
7947 11:45:47.926248
7948 11:45:47.926735 Set Vref, RX VrefLevel [Byte0]: 66
7949 11:45:47.929574 [Byte1]: 66
7950 11:45:47.933961
7951 11:45:47.934429 Set Vref, RX VrefLevel [Byte0]: 67
7952 11:45:47.937136 [Byte1]: 67
7953 11:45:47.941350
7954 11:45:47.941780 Set Vref, RX VrefLevel [Byte0]: 68
7955 11:45:47.945184 [Byte1]: 68
7956 11:45:47.949045
7957 11:45:47.949455 Set Vref, RX VrefLevel [Byte0]: 69
7958 11:45:47.952596 [Byte1]: 69
7959 11:45:47.956774
7960 11:45:47.957184 Set Vref, RX VrefLevel [Byte0]: 70
7961 11:45:47.960287 [Byte1]: 70
7962 11:45:47.964271
7963 11:45:47.964713 Set Vref, RX VrefLevel [Byte0]: 71
7964 11:45:47.967545 [Byte1]: 71
7965 11:45:47.971608
7966 11:45:47.972019 Set Vref, RX VrefLevel [Byte0]: 72
7967 11:45:47.974785 [Byte1]: 72
7968 11:45:47.979152
7969 11:45:47.979585 Final RX Vref Byte 0 = 54 to rank0
7970 11:45:47.983006 Final RX Vref Byte 1 = 64 to rank0
7971 11:45:47.985951 Final RX Vref Byte 0 = 54 to rank1
7972 11:45:47.989275 Final RX Vref Byte 1 = 64 to rank1==
7973 11:45:47.992606 Dram Type= 6, Freq= 0, CH_0, rank 0
7974 11:45:47.998991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7975 11:45:47.999407 ==
7976 11:45:47.999735 DQS Delay:
7977 11:45:48.002563 DQS0 = 0, DQS1 = 0
7978 11:45:48.002976 DQM Delay:
7979 11:45:48.003302 DQM0 = 129, DQM1 = 124
7980 11:45:48.006069 DQ Delay:
7981 11:45:48.008949 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =124
7982 11:45:48.012448 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7983 11:45:48.015850 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =120
7984 11:45:48.018822 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =128
7985 11:45:48.019244
7986 11:45:48.019577
7987 11:45:48.019885
7988 11:45:48.022318 [DramC_TX_OE_Calibration] TA2
7989 11:45:48.025842 Original DQ_B0 (3 6) =30, OEN = 27
7990 11:45:48.028901 Original DQ_B1 (3 6) =30, OEN = 27
7991 11:45:48.032265 24, 0x0, End_B0=24 End_B1=24
7992 11:45:48.036025 25, 0x0, End_B0=25 End_B1=25
7993 11:45:48.036451 26, 0x0, End_B0=26 End_B1=26
7994 11:45:48.038909 27, 0x0, End_B0=27 End_B1=27
7995 11:45:48.041829 28, 0x0, End_B0=28 End_B1=28
7996 11:45:48.045598 29, 0x0, End_B0=29 End_B1=29
7997 11:45:48.046021 30, 0x0, End_B0=30 End_B1=30
7998 11:45:48.048438 31, 0x4141, End_B0=30 End_B1=30
7999 11:45:48.051767 Byte0 end_step=30 best_step=27
8000 11:45:48.054825 Byte1 end_step=30 best_step=27
8001 11:45:48.058219 Byte0 TX OE(2T, 0.5T) = (3, 3)
8002 11:45:48.061515 Byte1 TX OE(2T, 0.5T) = (3, 3)
8003 11:45:48.061933
8004 11:45:48.062300
8005 11:45:48.068397 [DQSOSCAuto] RK0, (LSB)MR18= 0x1512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8006 11:45:48.071685 CH0 RK0: MR19=303, MR18=1512
8007 11:45:48.078371 CH0_RK0: MR19=0x303, MR18=0x1512, DQSOSC=399, MR23=63, INC=23, DEC=15
8008 11:45:48.078797
8009 11:45:48.081317 ----->DramcWriteLeveling(PI) begin...
8010 11:45:48.081742 ==
8011 11:45:48.084766 Dram Type= 6, Freq= 0, CH_0, rank 1
8012 11:45:48.088022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 11:45:48.088444 ==
8014 11:45:48.091304 Write leveling (Byte 0): 34 => 34
8015 11:45:48.094529 Write leveling (Byte 1): 26 => 26
8016 11:45:48.097628 DramcWriteLeveling(PI) end<-----
8017 11:45:48.098044
8018 11:45:48.098423 ==
8019 11:45:48.101295 Dram Type= 6, Freq= 0, CH_0, rank 1
8020 11:45:48.107619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8021 11:45:48.108041 ==
8022 11:45:48.108373 [Gating] SW mode calibration
8023 11:45:48.118117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8024 11:45:48.121025 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8025 11:45:48.127820 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 11:45:48.131037 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 11:45:48.133993 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8028 11:45:48.141133 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8029 11:45:48.144179 1 4 16 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8030 11:45:48.147573 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 11:45:48.153774 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 11:45:48.157215 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8033 11:45:48.161297 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8034 11:45:48.167008 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 11:45:48.169982 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8036 11:45:48.173501 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8037 11:45:48.180568 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8038 11:45:48.183096 1 5 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
8039 11:45:48.186594 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 11:45:48.193162 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 11:45:48.196691 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 11:45:48.200346 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8043 11:45:48.206772 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8044 11:45:48.209682 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8045 11:45:48.212978 1 6 16 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
8046 11:45:48.219520 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 11:45:48.222581 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 11:45:48.226162 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 11:45:48.232686 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 11:45:48.235968 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8051 11:45:48.238891 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8052 11:45:48.246139 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8053 11:45:48.249396 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8054 11:45:48.252308 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8055 11:45:48.259204 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8056 11:45:48.262440 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 11:45:48.265851 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 11:45:48.272223 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 11:45:48.275593 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 11:45:48.279001 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 11:45:48.285122 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 11:45:48.288543 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 11:45:48.292125 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 11:45:48.298447 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 11:45:48.302392 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 11:45:48.304907 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8067 11:45:48.311843 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8068 11:45:48.315050 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8069 11:45:48.318142 Total UI for P1: 0, mck2ui 16
8070 11:45:48.321619 best dqsien dly found for B0: ( 1, 9, 6)
8071 11:45:48.324721 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8072 11:45:48.331347 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8073 11:45:48.334658 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 11:45:48.338036 Total UI for P1: 0, mck2ui 16
8075 11:45:48.341504 best dqsien dly found for B1: ( 1, 9, 18)
8076 11:45:48.344947 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8077 11:45:48.347908 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8078 11:45:48.348328
8079 11:45:48.351318 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8080 11:45:48.354767 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8081 11:45:48.358197 [Gating] SW calibration Done
8082 11:45:48.358658 ==
8083 11:45:48.361255 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 11:45:48.364575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 11:45:48.367733 ==
8086 11:45:48.368150 RX Vref Scan: 0
8087 11:45:48.368482
8088 11:45:48.371024 RX Vref 0 -> 0, step: 1
8089 11:45:48.371441
8090 11:45:48.374743 RX Delay 0 -> 252, step: 8
8091 11:45:48.377638 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8092 11:45:48.380961 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8093 11:45:48.384547 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8094 11:45:48.387777 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8095 11:45:48.394054 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8096 11:45:48.397239 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8097 11:45:48.400904 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8098 11:45:48.404131 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8099 11:45:48.407349 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8100 11:45:48.413696 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8101 11:45:48.417399 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8102 11:45:48.420684 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8103 11:45:48.423727 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8104 11:45:48.430219 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8105 11:45:48.433809 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8106 11:45:48.437107 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8107 11:45:48.437528 ==
8108 11:45:48.440579 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 11:45:48.443620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 11:45:48.444041 ==
8111 11:45:48.446798 DQS Delay:
8112 11:45:48.447216 DQS0 = 0, DQS1 = 0
8113 11:45:48.450126 DQM Delay:
8114 11:45:48.450569 DQM0 = 132, DQM1 = 125
8115 11:45:48.450904 DQ Delay:
8116 11:45:48.456626 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8117 11:45:48.460396 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8118 11:45:48.463067 DQ8 =115, DQ9 =111, DQ10 =131, DQ11 =119
8119 11:45:48.466749 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8120 11:45:48.467168
8121 11:45:48.467500
8122 11:45:48.467805 ==
8123 11:45:48.469634 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 11:45:48.473461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 11:45:48.474037 ==
8126 11:45:48.474432
8127 11:45:48.474753
8128 11:45:48.476239 TX Vref Scan disable
8129 11:45:48.479791 == TX Byte 0 ==
8130 11:45:48.483131 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8131 11:45:48.486543 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8132 11:45:48.489412 == TX Byte 1 ==
8133 11:45:48.492995 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8134 11:45:48.496013 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8135 11:45:48.496434 ==
8136 11:45:48.499778 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 11:45:48.506039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 11:45:48.506482 ==
8139 11:45:48.519594
8140 11:45:48.522935 TX Vref early break, caculate TX vref
8141 11:45:48.526455 TX Vref=16, minBit 1, minWin=23, winSum=379
8142 11:45:48.529813 TX Vref=18, minBit 8, minWin=23, winSum=393
8143 11:45:48.532735 TX Vref=20, minBit 2, minWin=24, winSum=398
8144 11:45:48.536233 TX Vref=22, minBit 1, minWin=25, winSum=404
8145 11:45:48.539649 TX Vref=24, minBit 1, minWin=25, winSum=411
8146 11:45:48.545648 TX Vref=26, minBit 4, minWin=25, winSum=418
8147 11:45:48.548923 TX Vref=28, minBit 4, minWin=25, winSum=415
8148 11:45:48.552780 TX Vref=30, minBit 1, minWin=25, winSum=412
8149 11:45:48.556192 TX Vref=32, minBit 1, minWin=24, winSum=405
8150 11:45:48.559444 TX Vref=34, minBit 0, minWin=24, winSum=397
8151 11:45:48.562704 TX Vref=36, minBit 8, minWin=23, winSum=391
8152 11:45:48.569127 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 26
8153 11:45:48.569551
8154 11:45:48.572883 Final TX Range 0 Vref 26
8155 11:45:48.573307
8156 11:45:48.573636 ==
8157 11:45:48.576104 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 11:45:48.578966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 11:45:48.582750 ==
8160 11:45:48.583165
8161 11:45:48.583498
8162 11:45:48.583806 TX Vref Scan disable
8163 11:45:48.589395 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8164 11:45:48.589908 == TX Byte 0 ==
8165 11:45:48.592513 u2DelayCellOfst[0]=14 cells (4 PI)
8166 11:45:48.595336 u2DelayCellOfst[1]=17 cells (5 PI)
8167 11:45:48.598823 u2DelayCellOfst[2]=10 cells (3 PI)
8168 11:45:48.602235 u2DelayCellOfst[3]=14 cells (4 PI)
8169 11:45:48.605098 u2DelayCellOfst[4]=10 cells (3 PI)
8170 11:45:48.608625 u2DelayCellOfst[5]=0 cells (0 PI)
8171 11:45:48.611845 u2DelayCellOfst[6]=17 cells (5 PI)
8172 11:45:48.615405 u2DelayCellOfst[7]=17 cells (5 PI)
8173 11:45:48.618759 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8174 11:45:48.625139 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8175 11:45:48.625566 == TX Byte 1 ==
8176 11:45:48.628106 u2DelayCellOfst[8]=0 cells (0 PI)
8177 11:45:48.631507 u2DelayCellOfst[9]=0 cells (0 PI)
8178 11:45:48.634895 u2DelayCellOfst[10]=3 cells (1 PI)
8179 11:45:48.638473 u2DelayCellOfst[11]=0 cells (0 PI)
8180 11:45:48.641292 u2DelayCellOfst[12]=10 cells (3 PI)
8181 11:45:48.644597 u2DelayCellOfst[13]=10 cells (3 PI)
8182 11:45:48.648040 u2DelayCellOfst[14]=14 cells (4 PI)
8183 11:45:48.651661 u2DelayCellOfst[15]=10 cells (3 PI)
8184 11:45:48.655158 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8185 11:45:48.658041 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8186 11:45:48.661162 DramC Write-DBI on
8187 11:45:48.661709 ==
8188 11:45:48.664540 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 11:45:48.667995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 11:45:48.668417 ==
8191 11:45:48.668768
8192 11:45:48.669078
8193 11:45:48.671529 TX Vref Scan disable
8194 11:45:48.674603 == TX Byte 0 ==
8195 11:45:48.677596 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8196 11:45:48.678016 == TX Byte 1 ==
8197 11:45:48.684314 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8198 11:45:48.684732 DramC Write-DBI off
8199 11:45:48.685063
8200 11:45:48.685368 [DATLAT]
8201 11:45:48.687703 Freq=1600, CH0 RK1
8202 11:45:48.688120
8203 11:45:48.690829 DATLAT Default: 0xf
8204 11:45:48.691391 0, 0xFFFF, sum = 0
8205 11:45:48.694362 1, 0xFFFF, sum = 0
8206 11:45:48.694792 2, 0xFFFF, sum = 0
8207 11:45:48.697554 3, 0xFFFF, sum = 0
8208 11:45:48.697979 4, 0xFFFF, sum = 0
8209 11:45:48.700746 5, 0xFFFF, sum = 0
8210 11:45:48.701171 6, 0xFFFF, sum = 0
8211 11:45:48.703927 7, 0xFFFF, sum = 0
8212 11:45:48.704351 8, 0xFFFF, sum = 0
8213 11:45:48.707247 9, 0xFFFF, sum = 0
8214 11:45:48.707669 10, 0xFFFF, sum = 0
8215 11:45:48.710816 11, 0xFFFF, sum = 0
8216 11:45:48.714186 12, 0xFFFF, sum = 0
8217 11:45:48.714653 13, 0xFFFF, sum = 0
8218 11:45:48.717102 14, 0x0, sum = 1
8219 11:45:48.717526 15, 0x0, sum = 2
8220 11:45:48.717864 16, 0x0, sum = 3
8221 11:45:48.720527 17, 0x0, sum = 4
8222 11:45:48.720953 best_step = 15
8223 11:45:48.721288
8224 11:45:48.721608 ==
8225 11:45:48.724049 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 11:45:48.730383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 11:45:48.730807 ==
8228 11:45:48.731139 RX Vref Scan: 0
8229 11:45:48.731450
8230 11:45:48.733756 RX Vref 0 -> 0, step: 1
8231 11:45:48.734174
8232 11:45:48.737242 RX Delay 11 -> 252, step: 4
8233 11:45:48.740034 iDelay=187, Bit 0, Center 126 (79 ~ 174) 96
8234 11:45:48.743684 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8235 11:45:48.749890 iDelay=187, Bit 2, Center 126 (75 ~ 178) 104
8236 11:45:48.753814 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8237 11:45:48.756957 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8238 11:45:48.760265 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8239 11:45:48.763707 iDelay=187, Bit 6, Center 138 (91 ~ 186) 96
8240 11:45:48.770362 iDelay=187, Bit 7, Center 136 (87 ~ 186) 100
8241 11:45:48.773615 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8242 11:45:48.776656 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8243 11:45:48.779852 iDelay=187, Bit 10, Center 128 (75 ~ 182) 108
8244 11:45:48.783528 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8245 11:45:48.789807 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8246 11:45:48.793004 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8247 11:45:48.796312 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8248 11:45:48.800033 iDelay=187, Bit 15, Center 128 (75 ~ 182) 108
8249 11:45:48.800573 ==
8250 11:45:48.803009 Dram Type= 6, Freq= 0, CH_0, rank 1
8251 11:45:48.809648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 11:45:48.810068 ==
8253 11:45:48.810452 DQS Delay:
8254 11:45:48.812522 DQS0 = 0, DQS1 = 0
8255 11:45:48.812939 DQM Delay:
8256 11:45:48.815952 DQM0 = 129, DQM1 = 123
8257 11:45:48.816371 DQ Delay:
8258 11:45:48.819372 DQ0 =126, DQ1 =132, DQ2 =126, DQ3 =126
8259 11:45:48.822425 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
8260 11:45:48.826279 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =118
8261 11:45:48.829969 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =128
8262 11:45:48.830428
8263 11:45:48.830763
8264 11:45:48.831071
8265 11:45:48.832842 [DramC_TX_OE_Calibration] TA2
8266 11:45:48.835370 Original DQ_B0 (3 6) =30, OEN = 27
8267 11:45:48.839330 Original DQ_B1 (3 6) =30, OEN = 27
8268 11:45:48.842124 24, 0x0, End_B0=24 End_B1=24
8269 11:45:48.845847 25, 0x0, End_B0=25 End_B1=25
8270 11:45:48.846305 26, 0x0, End_B0=26 End_B1=26
8271 11:45:48.848787 27, 0x0, End_B0=27 End_B1=27
8272 11:45:48.852265 28, 0x0, End_B0=28 End_B1=28
8273 11:45:48.855758 29, 0x0, End_B0=29 End_B1=29
8274 11:45:48.858635 30, 0x0, End_B0=30 End_B1=30
8275 11:45:48.859064 31, 0x4545, End_B0=30 End_B1=30
8276 11:45:48.862193 Byte0 end_step=30 best_step=27
8277 11:45:48.865196 Byte1 end_step=30 best_step=27
8278 11:45:48.868750 Byte0 TX OE(2T, 0.5T) = (3, 3)
8279 11:45:48.872044 Byte1 TX OE(2T, 0.5T) = (3, 3)
8280 11:45:48.872464
8281 11:45:48.872799
8282 11:45:48.878706 [DQSOSCAuto] RK1, (LSB)MR18= 0x1210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8283 11:45:48.881653 CH0 RK1: MR19=303, MR18=1210
8284 11:45:48.888210 CH0_RK1: MR19=0x303, MR18=0x1210, DQSOSC=400, MR23=63, INC=23, DEC=15
8285 11:45:48.891730 [RxdqsGatingPostProcess] freq 1600
8286 11:45:48.898774 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8287 11:45:48.901653 best DQS0 dly(2T, 0.5T) = (1, 1)
8288 11:45:48.902069 best DQS1 dly(2T, 0.5T) = (1, 1)
8289 11:45:48.904870 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8290 11:45:48.908686 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8291 11:45:48.911616 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 11:45:48.914964 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 11:45:48.918231 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 11:45:48.921328 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 11:45:48.925019 Pre-setting of DQS Precalculation
8296 11:45:48.930919 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8297 11:45:48.931407 ==
8298 11:45:48.934347 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 11:45:48.937739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 11:45:48.938158 ==
8301 11:45:48.944475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8302 11:45:48.947859 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8303 11:45:48.951290 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8304 11:45:48.957570 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8305 11:45:48.966088 [CA 0] Center 42 (12~72) winsize 61
8306 11:45:48.969332 [CA 1] Center 42 (12~72) winsize 61
8307 11:45:48.972560 [CA 2] Center 38 (9~67) winsize 59
8308 11:45:48.976235 [CA 3] Center 37 (8~66) winsize 59
8309 11:45:48.979061 [CA 4] Center 38 (8~68) winsize 61
8310 11:45:48.982498 [CA 5] Center 36 (7~66) winsize 60
8311 11:45:48.982925
8312 11:45:48.986001 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8313 11:45:48.986558
8314 11:45:48.989510 [CATrainingPosCal] consider 1 rank data
8315 11:45:48.992611 u2DelayCellTimex100 = 275/100 ps
8316 11:45:48.999248 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8317 11:45:49.002807 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8318 11:45:49.005664 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8319 11:45:49.009092 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8320 11:45:49.012103 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8321 11:45:49.015507 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8322 11:45:49.015926
8323 11:45:49.018995 CA PerBit enable=1, Macro0, CA PI delay=36
8324 11:45:49.019415
8325 11:45:49.022150 [CBTSetCACLKResult] CA Dly = 36
8326 11:45:49.025234 CS Dly: 8 (0~39)
8327 11:45:49.028397 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8328 11:45:49.031874 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8329 11:45:49.032314 ==
8330 11:45:49.035314 Dram Type= 6, Freq= 0, CH_1, rank 1
8331 11:45:49.041778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 11:45:49.042199 ==
8333 11:45:49.045179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8334 11:45:49.051597 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8335 11:45:49.054959 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8336 11:45:49.061466 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8337 11:45:49.069102 [CA 0] Center 42 (12~72) winsize 61
8338 11:45:49.072632 [CA 1] Center 42 (13~72) winsize 60
8339 11:45:49.075795 [CA 2] Center 38 (8~68) winsize 61
8340 11:45:49.078947 [CA 3] Center 37 (7~67) winsize 61
8341 11:45:49.082667 [CA 4] Center 37 (7~67) winsize 61
8342 11:45:49.086080 [CA 5] Center 37 (7~67) winsize 61
8343 11:45:49.086551
8344 11:45:49.089233 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8345 11:45:49.089655
8346 11:45:49.092575 [CATrainingPosCal] consider 2 rank data
8347 11:45:49.095889 u2DelayCellTimex100 = 275/100 ps
8348 11:45:49.099169 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8349 11:45:49.106067 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8350 11:45:49.108798 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8351 11:45:49.112275 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8352 11:45:49.115693 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8353 11:45:49.119014 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8354 11:45:49.119445
8355 11:45:49.122088 CA PerBit enable=1, Macro0, CA PI delay=36
8356 11:45:49.122570
8357 11:45:49.125608 [CBTSetCACLKResult] CA Dly = 36
8358 11:45:49.129341 CS Dly: 9 (0~42)
8359 11:45:49.131858 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8360 11:45:49.135037 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8361 11:45:49.135479
8362 11:45:49.138324 ----->DramcWriteLeveling(PI) begin...
8363 11:45:49.138739 ==
8364 11:45:49.141665 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 11:45:49.148486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 11:45:49.148911 ==
8367 11:45:49.151705 Write leveling (Byte 0): 27 => 27
8368 11:45:49.154910 Write leveling (Byte 1): 27 => 27
8369 11:45:49.155327 DramcWriteLeveling(PI) end<-----
8370 11:45:49.155659
8371 11:45:49.158374 ==
8372 11:45:49.161926 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 11:45:49.164921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 11:45:49.165345 ==
8375 11:45:49.168345 [Gating] SW mode calibration
8376 11:45:49.175155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8377 11:45:49.178336 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8378 11:45:49.184582 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 11:45:49.188188 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 11:45:49.191191 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 11:45:49.197971 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8382 11:45:49.201305 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 11:45:49.204341 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 11:45:49.211074 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 11:45:49.214331 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 11:45:49.217591 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 11:45:49.224217 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 11:45:49.227047 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8389 11:45:49.230741 1 5 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
8390 11:45:49.236937 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8391 11:45:49.240337 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 11:45:49.243633 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 11:45:49.250329 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 11:45:49.253911 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 11:45:49.260103 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 11:45:49.263313 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 11:45:49.266770 1 6 12 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
8398 11:45:49.273559 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 11:45:49.276698 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 11:45:49.280082 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 11:45:49.286591 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 11:45:49.290025 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 11:45:49.293127 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 11:45:49.299798 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 11:45:49.303246 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8406 11:45:49.305870 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8407 11:45:49.312782 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 11:45:49.315957 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 11:45:49.319111 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 11:45:49.326046 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 11:45:49.329223 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 11:45:49.333033 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 11:45:49.339169 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 11:45:49.342553 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 11:45:49.346050 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 11:45:49.352524 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 11:45:49.355360 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 11:45:49.358778 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 11:45:49.365189 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 11:45:49.368567 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8421 11:45:49.371996 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8422 11:45:49.378642 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8423 11:45:49.379162 Total UI for P1: 0, mck2ui 16
8424 11:45:49.385107 best dqsien dly found for B0: ( 1, 9, 10)
8425 11:45:49.388770 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 11:45:49.391805 Total UI for P1: 0, mck2ui 16
8427 11:45:49.395024 best dqsien dly found for B1: ( 1, 9, 14)
8428 11:45:49.398357 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8429 11:45:49.401425 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8430 11:45:49.401845
8431 11:45:49.404991 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8432 11:45:49.407837 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8433 11:45:49.411615 [Gating] SW calibration Done
8434 11:45:49.412033 ==
8435 11:45:49.414743 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 11:45:49.421178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 11:45:49.421601 ==
8438 11:45:49.421935 RX Vref Scan: 0
8439 11:45:49.422248
8440 11:45:49.424414 RX Vref 0 -> 0, step: 1
8441 11:45:49.424830
8442 11:45:49.427992 RX Delay 0 -> 252, step: 8
8443 11:45:49.430889 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8444 11:45:49.434423 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8445 11:45:49.438018 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8446 11:45:49.440903 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8447 11:45:49.447743 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8448 11:45:49.450608 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8449 11:45:49.454046 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8450 11:45:49.457132 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8451 11:45:49.464168 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8452 11:45:49.467033 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8453 11:45:49.470480 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8454 11:45:49.473894 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8455 11:45:49.477287 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8456 11:45:49.483399 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8457 11:45:49.486791 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8458 11:45:49.490163 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8459 11:45:49.490638 ==
8460 11:45:49.493341 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 11:45:49.497133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 11:45:49.500488 ==
8463 11:45:49.501009 DQS Delay:
8464 11:45:49.501350 DQS0 = 0, DQS1 = 0
8465 11:45:49.503889 DQM Delay:
8466 11:45:49.504406 DQM0 = 134, DQM1 = 129
8467 11:45:49.506661 DQ Delay:
8468 11:45:49.509993 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8469 11:45:49.513072 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8470 11:45:49.516578 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =123
8471 11:45:49.519816 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8472 11:45:49.520241
8473 11:45:49.520575
8474 11:45:49.520884 ==
8475 11:45:49.523160 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 11:45:49.526753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 11:45:49.527174 ==
8478 11:45:49.527505
8479 11:45:49.529756
8480 11:45:49.530171 TX Vref Scan disable
8481 11:45:49.533231 == TX Byte 0 ==
8482 11:45:49.536503 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8483 11:45:49.539800 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8484 11:45:49.542798 == TX Byte 1 ==
8485 11:45:49.546189 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8486 11:45:49.550133 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8487 11:45:49.550606 ==
8488 11:45:49.552959 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 11:45:49.559378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 11:45:49.559800 ==
8491 11:45:49.572432
8492 11:45:49.575361 TX Vref early break, caculate TX vref
8493 11:45:49.578827 TX Vref=16, minBit 8, minWin=21, winSum=369
8494 11:45:49.582321 TX Vref=18, minBit 8, minWin=22, winSum=376
8495 11:45:49.585310 TX Vref=20, minBit 8, minWin=22, winSum=382
8496 11:45:49.588856 TX Vref=22, minBit 8, minWin=23, winSum=393
8497 11:45:49.592063 TX Vref=24, minBit 9, minWin=24, winSum=408
8498 11:45:49.598954 TX Vref=26, minBit 3, minWin=24, winSum=407
8499 11:45:49.601946 TX Vref=28, minBit 8, minWin=25, winSum=419
8500 11:45:49.605599 TX Vref=30, minBit 10, minWin=25, winSum=415
8501 11:45:49.608523 TX Vref=32, minBit 0, minWin=24, winSum=406
8502 11:45:49.612011 TX Vref=34, minBit 0, minWin=24, winSum=398
8503 11:45:49.615473 TX Vref=36, minBit 8, minWin=23, winSum=385
8504 11:45:49.621522 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 28
8505 11:45:49.621944
8506 11:45:49.625283 Final TX Range 0 Vref 28
8507 11:45:49.625701
8508 11:45:49.626032 ==
8509 11:45:49.628473 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 11:45:49.631478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 11:45:49.634909 ==
8512 11:45:49.635338
8513 11:45:49.635669
8514 11:45:49.635977 TX Vref Scan disable
8515 11:45:49.641325 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8516 11:45:49.641742 == TX Byte 0 ==
8517 11:45:49.644680 u2DelayCellOfst[0]=14 cells (4 PI)
8518 11:45:49.648194 u2DelayCellOfst[1]=10 cells (3 PI)
8519 11:45:49.651298 u2DelayCellOfst[2]=0 cells (0 PI)
8520 11:45:49.654611 u2DelayCellOfst[3]=7 cells (2 PI)
8521 11:45:49.657966 u2DelayCellOfst[4]=10 cells (3 PI)
8522 11:45:49.661259 u2DelayCellOfst[5]=17 cells (5 PI)
8523 11:45:49.664389 u2DelayCellOfst[6]=17 cells (5 PI)
8524 11:45:49.668041 u2DelayCellOfst[7]=7 cells (2 PI)
8525 11:45:49.671027 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8526 11:45:49.674535 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8527 11:45:49.677589 == TX Byte 1 ==
8528 11:45:49.681429 u2DelayCellOfst[8]=0 cells (0 PI)
8529 11:45:49.684210 u2DelayCellOfst[9]=7 cells (2 PI)
8530 11:45:49.687570 u2DelayCellOfst[10]=10 cells (3 PI)
8531 11:45:49.691269 u2DelayCellOfst[11]=7 cells (2 PI)
8532 11:45:49.693960 u2DelayCellOfst[12]=14 cells (4 PI)
8533 11:45:49.697349 u2DelayCellOfst[13]=17 cells (5 PI)
8534 11:45:49.700679 u2DelayCellOfst[14]=17 cells (5 PI)
8535 11:45:49.701099 u2DelayCellOfst[15]=17 cells (5 PI)
8536 11:45:49.707333 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8537 11:45:49.710363 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8538 11:45:49.713847 DramC Write-DBI on
8539 11:45:49.714461 ==
8540 11:45:49.717219 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 11:45:49.720663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 11:45:49.721084 ==
8543 11:45:49.721414
8544 11:45:49.721724
8545 11:45:49.723742 TX Vref Scan disable
8546 11:45:49.724162 == TX Byte 0 ==
8547 11:45:49.730417 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8548 11:45:49.730852 == TX Byte 1 ==
8549 11:45:49.736858 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8550 11:45:49.737281 DramC Write-DBI off
8551 11:45:49.737668
8552 11:45:49.738079 [DATLAT]
8553 11:45:49.740012 Freq=1600, CH1 RK0
8554 11:45:49.740458
8555 11:45:49.740792 DATLAT Default: 0xf
8556 11:45:49.743644 0, 0xFFFF, sum = 0
8557 11:45:49.746802 1, 0xFFFF, sum = 0
8558 11:45:49.747230 2, 0xFFFF, sum = 0
8559 11:45:49.750183 3, 0xFFFF, sum = 0
8560 11:45:49.750681 4, 0xFFFF, sum = 0
8561 11:45:49.753755 5, 0xFFFF, sum = 0
8562 11:45:49.754383 6, 0xFFFF, sum = 0
8563 11:45:49.756461 7, 0xFFFF, sum = 0
8564 11:45:49.756930 8, 0xFFFF, sum = 0
8565 11:45:49.759831 9, 0xFFFF, sum = 0
8566 11:45:49.760273 10, 0xFFFF, sum = 0
8567 11:45:49.763059 11, 0xFFFF, sum = 0
8568 11:45:49.763479 12, 0xFFFF, sum = 0
8569 11:45:49.766302 13, 0xFFFF, sum = 0
8570 11:45:49.766750 14, 0x0, sum = 1
8571 11:45:49.769779 15, 0x0, sum = 2
8572 11:45:49.770197 16, 0x0, sum = 3
8573 11:45:49.772847 17, 0x0, sum = 4
8574 11:45:49.773279 best_step = 15
8575 11:45:49.773604
8576 11:45:49.773931 ==
8577 11:45:49.776392 Dram Type= 6, Freq= 0, CH_1, rank 0
8578 11:45:49.782984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8579 11:45:49.783436 ==
8580 11:45:49.783769 RX Vref Scan: 1
8581 11:45:49.784081
8582 11:45:49.785932 Set Vref Range= 24 -> 127
8583 11:45:49.786408
8584 11:45:49.789440 RX Vref 24 -> 127, step: 1
8585 11:45:49.789854
8586 11:45:49.793094 RX Delay 11 -> 252, step: 4
8587 11:45:49.793512
8588 11:45:49.796262 Set Vref, RX VrefLevel [Byte0]: 24
8589 11:45:49.799487 [Byte1]: 24
8590 11:45:49.799906
8591 11:45:49.802568 Set Vref, RX VrefLevel [Byte0]: 25
8592 11:45:49.805923 [Byte1]: 25
8593 11:45:49.806391
8594 11:45:49.809241 Set Vref, RX VrefLevel [Byte0]: 26
8595 11:45:49.812162 [Byte1]: 26
8596 11:45:49.815692
8597 11:45:49.816106 Set Vref, RX VrefLevel [Byte0]: 27
8598 11:45:49.819204 [Byte1]: 27
8599 11:45:49.823503
8600 11:45:49.823918 Set Vref, RX VrefLevel [Byte0]: 28
8601 11:45:49.827019 [Byte1]: 28
8602 11:45:49.830726
8603 11:45:49.831141 Set Vref, RX VrefLevel [Byte0]: 29
8604 11:45:49.834152 [Byte1]: 29
8605 11:45:49.838883
8606 11:45:49.839301 Set Vref, RX VrefLevel [Byte0]: 30
8607 11:45:49.841678 [Byte1]: 30
8608 11:45:49.846502
8609 11:45:49.846920 Set Vref, RX VrefLevel [Byte0]: 31
8610 11:45:49.849660 [Byte1]: 31
8611 11:45:49.854210
8612 11:45:49.854676 Set Vref, RX VrefLevel [Byte0]: 32
8613 11:45:49.857227 [Byte1]: 32
8614 11:45:49.861614
8615 11:45:49.862036 Set Vref, RX VrefLevel [Byte0]: 33
8616 11:45:49.864508 [Byte1]: 33
8617 11:45:49.869200
8618 11:45:49.869792 Set Vref, RX VrefLevel [Byte0]: 34
8619 11:45:49.872481 [Byte1]: 34
8620 11:45:49.876702
8621 11:45:49.877135 Set Vref, RX VrefLevel [Byte0]: 35
8622 11:45:49.879906 [Byte1]: 35
8623 11:45:49.884371
8624 11:45:49.884885 Set Vref, RX VrefLevel [Byte0]: 36
8625 11:45:49.887673 [Byte1]: 36
8626 11:45:49.892253
8627 11:45:49.892690 Set Vref, RX VrefLevel [Byte0]: 37
8628 11:45:49.895850 [Byte1]: 37
8629 11:45:49.899699
8630 11:45:49.900116 Set Vref, RX VrefLevel [Byte0]: 38
8631 11:45:49.903070 [Byte1]: 38
8632 11:45:49.907507
8633 11:45:49.908026 Set Vref, RX VrefLevel [Byte0]: 39
8634 11:45:49.910804 [Byte1]: 39
8635 11:45:49.914854
8636 11:45:49.915270 Set Vref, RX VrefLevel [Byte0]: 40
8637 11:45:49.917856 [Byte1]: 40
8638 11:45:49.922589
8639 11:45:49.923113 Set Vref, RX VrefLevel [Byte0]: 41
8640 11:45:49.925975 [Byte1]: 41
8641 11:45:49.929830
8642 11:45:49.930246 Set Vref, RX VrefLevel [Byte0]: 42
8643 11:45:49.933211 [Byte1]: 42
8644 11:45:49.937585
8645 11:45:49.940808 Set Vref, RX VrefLevel [Byte0]: 43
8646 11:45:49.944319 [Byte1]: 43
8647 11:45:49.944832
8648 11:45:49.947523 Set Vref, RX VrefLevel [Byte0]: 44
8649 11:45:49.950818 [Byte1]: 44
8650 11:45:49.951359
8651 11:45:49.953664 Set Vref, RX VrefLevel [Byte0]: 45
8652 11:45:49.957285 [Byte1]: 45
8653 11:45:49.960411
8654 11:45:49.960825 Set Vref, RX VrefLevel [Byte0]: 46
8655 11:45:49.964203 [Byte1]: 46
8656 11:45:49.967989
8657 11:45:49.968405 Set Vref, RX VrefLevel [Byte0]: 47
8658 11:45:49.971341 [Byte1]: 47
8659 11:45:49.975790
8660 11:45:49.976203 Set Vref, RX VrefLevel [Byte0]: 48
8661 11:45:49.978796 [Byte1]: 48
8662 11:45:49.983279
8663 11:45:49.983696 Set Vref, RX VrefLevel [Byte0]: 49
8664 11:45:49.986755 [Byte1]: 49
8665 11:45:49.990751
8666 11:45:49.991167 Set Vref, RX VrefLevel [Byte0]: 50
8667 11:45:49.994177 [Byte1]: 50
8668 11:45:49.998324
8669 11:45:49.998748 Set Vref, RX VrefLevel [Byte0]: 51
8670 11:45:50.002156 [Byte1]: 51
8671 11:45:50.006234
8672 11:45:50.006690 Set Vref, RX VrefLevel [Byte0]: 52
8673 11:45:50.009422 [Byte1]: 52
8674 11:45:50.013988
8675 11:45:50.014448 Set Vref, RX VrefLevel [Byte0]: 53
8676 11:45:50.017199 [Byte1]: 53
8677 11:45:50.021496
8678 11:45:50.021911 Set Vref, RX VrefLevel [Byte0]: 54
8679 11:45:50.024950 [Byte1]: 54
8680 11:45:50.028875
8681 11:45:50.029293 Set Vref, RX VrefLevel [Byte0]: 55
8682 11:45:50.032368 [Byte1]: 55
8683 11:45:50.036446
8684 11:45:50.036861 Set Vref, RX VrefLevel [Byte0]: 56
8685 11:45:50.039659 [Byte1]: 56
8686 11:45:50.044681
8687 11:45:50.045211 Set Vref, RX VrefLevel [Byte0]: 57
8688 11:45:50.047505 [Byte1]: 57
8689 11:45:50.052613
8690 11:45:50.053116 Set Vref, RX VrefLevel [Byte0]: 58
8691 11:45:50.054799 [Byte1]: 58
8692 11:45:50.059454
8693 11:45:50.059872 Set Vref, RX VrefLevel [Byte0]: 59
8694 11:45:50.062387 [Byte1]: 59
8695 11:45:50.066760
8696 11:45:50.067180 Set Vref, RX VrefLevel [Byte0]: 60
8697 11:45:50.070473 [Byte1]: 60
8698 11:45:50.074373
8699 11:45:50.074795 Set Vref, RX VrefLevel [Byte0]: 61
8700 11:45:50.077819 [Byte1]: 61
8701 11:45:50.082548
8702 11:45:50.082965 Set Vref, RX VrefLevel [Byte0]: 62
8703 11:45:50.085799 [Byte1]: 62
8704 11:45:50.089588
8705 11:45:50.090005 Set Vref, RX VrefLevel [Byte0]: 63
8706 11:45:50.093355 [Byte1]: 63
8707 11:45:50.097672
8708 11:45:50.098090 Set Vref, RX VrefLevel [Byte0]: 64
8709 11:45:50.100850 [Byte1]: 64
8710 11:45:50.105374
8711 11:45:50.105906 Set Vref, RX VrefLevel [Byte0]: 65
8712 11:45:50.108562 [Byte1]: 65
8713 11:45:50.112508
8714 11:45:50.112924 Set Vref, RX VrefLevel [Byte0]: 66
8715 11:45:50.116389 [Byte1]: 66
8716 11:45:50.120429
8717 11:45:50.120852 Set Vref, RX VrefLevel [Byte0]: 67
8718 11:45:50.123536 [Byte1]: 67
8719 11:45:50.127926
8720 11:45:50.128349 Set Vref, RX VrefLevel [Byte0]: 68
8721 11:45:50.130858 [Byte1]: 68
8722 11:45:50.135442
8723 11:45:50.135863 Set Vref, RX VrefLevel [Byte0]: 69
8724 11:45:50.138956 [Byte1]: 69
8725 11:45:50.142998
8726 11:45:50.143512 Set Vref, RX VrefLevel [Byte0]: 70
8727 11:45:50.146333 [Byte1]: 70
8728 11:45:50.151181
8729 11:45:50.151600 Final RX Vref Byte 0 = 60 to rank0
8730 11:45:50.154471 Final RX Vref Byte 1 = 61 to rank0
8731 11:45:50.157332 Final RX Vref Byte 0 = 60 to rank1
8732 11:45:50.160411 Final RX Vref Byte 1 = 61 to rank1==
8733 11:45:50.163752 Dram Type= 6, Freq= 0, CH_1, rank 0
8734 11:45:50.170574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8735 11:45:50.170997 ==
8736 11:45:50.171335 DQS Delay:
8737 11:45:50.173929 DQS0 = 0, DQS1 = 0
8738 11:45:50.174467 DQM Delay:
8739 11:45:50.174818 DQM0 = 132, DQM1 = 128
8740 11:45:50.176772 DQ Delay:
8741 11:45:50.180266 DQ0 =138, DQ1 =128, DQ2 =118, DQ3 =132
8742 11:45:50.183641 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =128
8743 11:45:50.187004 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8744 11:45:50.189965 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8745 11:45:50.190427
8746 11:45:50.190916
8747 11:45:50.191323
8748 11:45:50.193385 [DramC_TX_OE_Calibration] TA2
8749 11:45:50.196857 Original DQ_B0 (3 6) =30, OEN = 27
8750 11:45:50.200398 Original DQ_B1 (3 6) =30, OEN = 27
8751 11:45:50.203786 24, 0x0, End_B0=24 End_B1=24
8752 11:45:50.206753 25, 0x0, End_B0=25 End_B1=25
8753 11:45:50.207180 26, 0x0, End_B0=26 End_B1=26
8754 11:45:50.209824 27, 0x0, End_B0=27 End_B1=27
8755 11:45:50.213360 28, 0x0, End_B0=28 End_B1=28
8756 11:45:50.216865 29, 0x0, End_B0=29 End_B1=29
8757 11:45:50.217288 30, 0x0, End_B0=30 End_B1=30
8758 11:45:50.220349 31, 0x4141, End_B0=30 End_B1=30
8759 11:45:50.223097 Byte0 end_step=30 best_step=27
8760 11:45:50.227122 Byte1 end_step=30 best_step=27
8761 11:45:50.229573 Byte0 TX OE(2T, 0.5T) = (3, 3)
8762 11:45:50.232903 Byte1 TX OE(2T, 0.5T) = (3, 3)
8763 11:45:50.233323
8764 11:45:50.233654
8765 11:45:50.239419 [DQSOSCAuto] RK0, (LSB)MR18= 0x913, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
8766 11:45:50.242888 CH1 RK0: MR19=303, MR18=913
8767 11:45:50.249523 CH1_RK0: MR19=0x303, MR18=0x913, DQSOSC=400, MR23=63, INC=23, DEC=15
8768 11:45:50.250057
8769 11:45:50.252704 ----->DramcWriteLeveling(PI) begin...
8770 11:45:50.253242 ==
8771 11:45:50.256137 Dram Type= 6, Freq= 0, CH_1, rank 1
8772 11:45:50.259128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8773 11:45:50.259553 ==
8774 11:45:50.262812 Write leveling (Byte 0): 25 => 25
8775 11:45:50.265658 Write leveling (Byte 1): 26 => 26
8776 11:45:50.269073 DramcWriteLeveling(PI) end<-----
8777 11:45:50.269494
8778 11:45:50.269825 ==
8779 11:45:50.272762 Dram Type= 6, Freq= 0, CH_1, rank 1
8780 11:45:50.275886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 11:45:50.279115 ==
8782 11:45:50.279565 [Gating] SW mode calibration
8783 11:45:50.288932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8784 11:45:50.291982 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8785 11:45:50.295435 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 11:45:50.302319 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 11:45:50.305486 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8788 11:45:50.308899 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
8789 11:45:50.315204 1 4 16 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
8790 11:45:50.318561 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 11:45:50.321807 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 11:45:50.328549 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 11:45:50.331853 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 11:45:50.335354 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 11:45:50.341697 1 5 8 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
8796 11:45:50.345159 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8797 11:45:50.347858 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8798 11:45:50.354970 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 11:45:50.358163 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 11:45:50.361166 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 11:45:50.368020 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 11:45:50.370925 1 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8803 11:45:50.378108 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8804 11:45:50.380846 1 6 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8805 11:45:50.384076 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 11:45:50.390844 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 11:45:50.394363 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 11:45:50.397564 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 11:45:50.404101 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 11:45:50.407192 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8811 11:45:50.410807 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8812 11:45:50.413853 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8813 11:45:50.420574 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8814 11:45:50.423714 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 11:45:50.427653 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 11:45:50.433976 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 11:45:50.437082 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 11:45:50.440646 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 11:45:50.447228 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 11:45:50.451019 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 11:45:50.453443 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 11:45:50.460252 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 11:45:50.463902 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 11:45:50.466547 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 11:45:50.473807 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 11:45:50.476835 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8827 11:45:50.479887 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8828 11:45:50.487040 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8829 11:45:50.489751 Total UI for P1: 0, mck2ui 16
8830 11:45:50.493606 best dqsien dly found for B0: ( 1, 9, 6)
8831 11:45:50.496840 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 11:45:50.499521 Total UI for P1: 0, mck2ui 16
8833 11:45:50.503207 best dqsien dly found for B1: ( 1, 9, 12)
8834 11:45:50.506371 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8835 11:45:50.509719 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8836 11:45:50.510138
8837 11:45:50.512649 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8838 11:45:50.519079 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8839 11:45:50.519639 [Gating] SW calibration Done
8840 11:45:50.522669 ==
8841 11:45:50.523090 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 11:45:50.529223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 11:45:50.529725 ==
8844 11:45:50.530097 RX Vref Scan: 0
8845 11:45:50.530644
8846 11:45:50.532361 RX Vref 0 -> 0, step: 1
8847 11:45:50.532780
8848 11:45:50.536067 RX Delay 0 -> 252, step: 8
8849 11:45:50.538872 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8850 11:45:50.542185 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8851 11:45:50.545580 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8852 11:45:50.552538 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8853 11:45:50.555770 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8854 11:45:50.558981 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8855 11:45:50.562175 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8856 11:45:50.565280 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8857 11:45:50.572162 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8858 11:45:50.575094 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8859 11:45:50.578540 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8860 11:45:50.582046 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8861 11:45:50.588418 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8862 11:45:50.592072 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8863 11:45:50.594900 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8864 11:45:50.598207 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8865 11:45:50.598706 ==
8866 11:45:50.601974 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 11:45:50.608283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 11:45:50.608805 ==
8869 11:45:50.609143 DQS Delay:
8870 11:45:50.611217 DQS0 = 0, DQS1 = 0
8871 11:45:50.611692 DQM Delay:
8872 11:45:50.612197 DQM0 = 133, DQM1 = 130
8873 11:45:50.614844 DQ Delay:
8874 11:45:50.618222 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8875 11:45:50.621504 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =135
8876 11:45:50.624608 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8877 11:45:50.627982 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8878 11:45:50.628401
8879 11:45:50.628734
8880 11:45:50.629043 ==
8881 11:45:50.631360 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 11:45:50.637534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 11:45:50.637957 ==
8884 11:45:50.638323
8885 11:45:50.638642
8886 11:45:50.638940 TX Vref Scan disable
8887 11:45:50.641403 == TX Byte 0 ==
8888 11:45:50.644244 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8889 11:45:50.650915 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8890 11:45:50.651482 == TX Byte 1 ==
8891 11:45:50.654346 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8892 11:45:50.660856 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8893 11:45:50.661277 ==
8894 11:45:50.664425 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 11:45:50.667105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 11:45:50.667660 ==
8897 11:45:50.680576
8898 11:45:50.684370 TX Vref early break, caculate TX vref
8899 11:45:50.687481 TX Vref=16, minBit 9, minWin=21, winSum=375
8900 11:45:50.690912 TX Vref=18, minBit 9, minWin=22, winSum=388
8901 11:45:50.694283 TX Vref=20, minBit 9, minWin=22, winSum=389
8902 11:45:50.697257 TX Vref=22, minBit 9, minWin=23, winSum=397
8903 11:45:50.700548 TX Vref=24, minBit 9, minWin=24, winSum=403
8904 11:45:50.707176 TX Vref=26, minBit 9, minWin=24, winSum=410
8905 11:45:50.710505 TX Vref=28, minBit 3, minWin=25, winSum=418
8906 11:45:50.714029 TX Vref=30, minBit 8, minWin=25, winSum=415
8907 11:45:50.716859 TX Vref=32, minBit 8, minWin=24, winSum=407
8908 11:45:50.720200 TX Vref=34, minBit 9, minWin=24, winSum=407
8909 11:45:50.723774 TX Vref=36, minBit 0, minWin=23, winSum=396
8910 11:45:50.729912 [TxChooseVref] Worse bit 3, Min win 25, Win sum 418, Final Vref 28
8911 11:45:50.730365
8912 11:45:50.733399 Final TX Range 0 Vref 28
8913 11:45:50.733951
8914 11:45:50.734498 ==
8915 11:45:50.737041 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 11:45:50.740273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 11:45:50.740696 ==
8918 11:45:50.743060
8919 11:45:50.743474
8920 11:45:50.743858 TX Vref Scan disable
8921 11:45:50.749789 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8922 11:45:50.750211 == TX Byte 0 ==
8923 11:45:50.752926 u2DelayCellOfst[0]=14 cells (4 PI)
8924 11:45:50.759544 u2DelayCellOfst[1]=10 cells (3 PI)
8925 11:45:50.760324 u2DelayCellOfst[2]=0 cells (0 PI)
8926 11:45:50.763437 u2DelayCellOfst[3]=3 cells (1 PI)
8927 11:45:50.766002 u2DelayCellOfst[4]=7 cells (2 PI)
8928 11:45:50.769537 u2DelayCellOfst[5]=17 cells (5 PI)
8929 11:45:50.773109 u2DelayCellOfst[6]=17 cells (5 PI)
8930 11:45:50.776153 u2DelayCellOfst[7]=7 cells (2 PI)
8931 11:45:50.779509 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8932 11:45:50.782551 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8933 11:45:50.785932 == TX Byte 1 ==
8934 11:45:50.789443 u2DelayCellOfst[8]=0 cells (0 PI)
8935 11:45:50.792892 u2DelayCellOfst[9]=0 cells (0 PI)
8936 11:45:50.796128 u2DelayCellOfst[10]=10 cells (3 PI)
8937 11:45:50.800004 u2DelayCellOfst[11]=7 cells (2 PI)
8938 11:45:50.802465 u2DelayCellOfst[12]=14 cells (4 PI)
8939 11:45:50.806074 u2DelayCellOfst[13]=14 cells (4 PI)
8940 11:45:50.809300 u2DelayCellOfst[14]=17 cells (5 PI)
8941 11:45:50.809869 u2DelayCellOfst[15]=17 cells (5 PI)
8942 11:45:50.816015 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8943 11:45:50.818851 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8944 11:45:50.822650 DramC Write-DBI on
8945 11:45:50.823170 ==
8946 11:45:50.825394 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 11:45:50.828946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 11:45:50.829366 ==
8949 11:45:50.829697
8950 11:45:50.830004
8951 11:45:50.831897 TX Vref Scan disable
8952 11:45:50.832445 == TX Byte 0 ==
8953 11:45:50.838815 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8954 11:45:50.839239 == TX Byte 1 ==
8955 11:45:50.845375 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8956 11:45:50.845795 DramC Write-DBI off
8957 11:45:50.846128
8958 11:45:50.846505 [DATLAT]
8959 11:45:50.848509 Freq=1600, CH1 RK1
8960 11:45:50.848927
8961 11:45:50.851871 DATLAT Default: 0xf
8962 11:45:50.852480 0, 0xFFFF, sum = 0
8963 11:45:50.854895 1, 0xFFFF, sum = 0
8964 11:45:50.855319 2, 0xFFFF, sum = 0
8965 11:45:50.858414 3, 0xFFFF, sum = 0
8966 11:45:50.858840 4, 0xFFFF, sum = 0
8967 11:45:50.861897 5, 0xFFFF, sum = 0
8968 11:45:50.862378 6, 0xFFFF, sum = 0
8969 11:45:50.865326 7, 0xFFFF, sum = 0
8970 11:45:50.865941 8, 0xFFFF, sum = 0
8971 11:45:50.869000 9, 0xFFFF, sum = 0
8972 11:45:50.869431 10, 0xFFFF, sum = 0
8973 11:45:50.871999 11, 0xFFFF, sum = 0
8974 11:45:50.872446 12, 0xFFFF, sum = 0
8975 11:45:50.874838 13, 0xFFFF, sum = 0
8976 11:45:50.875298 14, 0x0, sum = 1
8977 11:45:50.877868 15, 0x0, sum = 2
8978 11:45:50.878469 16, 0x0, sum = 3
8979 11:45:50.881456 17, 0x0, sum = 4
8980 11:45:50.881880 best_step = 15
8981 11:45:50.882221
8982 11:45:50.882595 ==
8983 11:45:50.884941 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 11:45:50.891202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 11:45:50.891703 ==
8986 11:45:50.892045 RX Vref Scan: 0
8987 11:45:50.892358
8988 11:45:50.894692 RX Vref 0 -> 0, step: 1
8989 11:45:50.895110
8990 11:45:50.898077 RX Delay 19 -> 252, step: 4
8991 11:45:50.900944 iDelay=195, Bit 0, Center 136 (83 ~ 190) 108
8992 11:45:50.904596 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8993 11:45:50.911093 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8994 11:45:50.914375 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8995 11:45:50.917731 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8996 11:45:50.921360 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8997 11:45:50.924459 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8998 11:45:50.930806 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8999 11:45:50.934336 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9000 11:45:50.937504 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9001 11:45:50.940753 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
9002 11:45:50.944450 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9003 11:45:50.950852 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9004 11:45:50.953918 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9005 11:45:50.957011 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9006 11:45:50.960334 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9007 11:45:50.960756 ==
9008 11:45:50.963789 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 11:45:50.970158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 11:45:50.970694 ==
9011 11:45:50.971073 DQS Delay:
9012 11:45:50.973913 DQS0 = 0, DQS1 = 0
9013 11:45:50.974414 DQM Delay:
9014 11:45:50.977083 DQM0 = 131, DQM1 = 128
9015 11:45:50.977580 DQ Delay:
9016 11:45:50.980230 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =128
9017 11:45:50.983695 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
9018 11:45:50.986691 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
9019 11:45:50.989895 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9020 11:45:50.990499
9021 11:45:50.990926
9022 11:45:50.991257
9023 11:45:50.993476 [DramC_TX_OE_Calibration] TA2
9024 11:45:50.996335 Original DQ_B0 (3 6) =30, OEN = 27
9025 11:45:50.999987 Original DQ_B1 (3 6) =30, OEN = 27
9026 11:45:51.003013 24, 0x0, End_B0=24 End_B1=24
9027 11:45:51.006547 25, 0x0, End_B0=25 End_B1=25
9028 11:45:51.007045 26, 0x0, End_B0=26 End_B1=26
9029 11:45:51.010030 27, 0x0, End_B0=27 End_B1=27
9030 11:45:51.013047 28, 0x0, End_B0=28 End_B1=28
9031 11:45:51.016467 29, 0x0, End_B0=29 End_B1=29
9032 11:45:51.019916 30, 0x0, End_B0=30 End_B1=30
9033 11:45:51.020522 31, 0x4141, End_B0=30 End_B1=30
9034 11:45:51.022795 Byte0 end_step=30 best_step=27
9035 11:45:51.026591 Byte1 end_step=30 best_step=27
9036 11:45:51.029363 Byte0 TX OE(2T, 0.5T) = (3, 3)
9037 11:45:51.033122 Byte1 TX OE(2T, 0.5T) = (3, 3)
9038 11:45:51.033629
9039 11:45:51.034031
9040 11:45:51.039410 [DQSOSCAuto] RK1, (LSB)MR18= 0x101d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9041 11:45:51.042545 CH1 RK1: MR19=303, MR18=101D
9042 11:45:51.049302 CH1_RK1: MR19=0x303, MR18=0x101D, DQSOSC=395, MR23=63, INC=23, DEC=15
9043 11:45:51.052582 [RxdqsGatingPostProcess] freq 1600
9044 11:45:51.059395 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9045 11:45:51.062308 best DQS0 dly(2T, 0.5T) = (1, 1)
9046 11:45:51.062814 best DQS1 dly(2T, 0.5T) = (1, 1)
9047 11:45:51.065419 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9048 11:45:51.069353 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9049 11:45:51.072400 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 11:45:51.075323 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 11:45:51.078921 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 11:45:51.082226 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 11:45:51.085589 Pre-setting of DQS Precalculation
9054 11:45:51.091905 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9055 11:45:51.098594 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9056 11:45:51.105520 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9057 11:45:51.106049
9058 11:45:51.106446
9059 11:45:51.108784 [Calibration Summary] 3200 Mbps
9060 11:45:51.109197 CH 0, Rank 0
9061 11:45:51.111792 SW Impedance : PASS
9062 11:45:51.115018 DUTY Scan : NO K
9063 11:45:51.115431 ZQ Calibration : PASS
9064 11:45:51.118601 Jitter Meter : NO K
9065 11:45:51.121902 CBT Training : PASS
9066 11:45:51.122370 Write leveling : PASS
9067 11:45:51.125342 RX DQS gating : PASS
9068 11:45:51.128410 RX DQ/DQS(RDDQC) : PASS
9069 11:45:51.128831 TX DQ/DQS : PASS
9070 11:45:51.131363 RX DATLAT : PASS
9071 11:45:51.131783 RX DQ/DQS(Engine): PASS
9072 11:45:51.134858 TX OE : PASS
9073 11:45:51.135283 All Pass.
9074 11:45:51.135616
9075 11:45:51.138418 CH 0, Rank 1
9076 11:45:51.141198 SW Impedance : PASS
9077 11:45:51.141615 DUTY Scan : NO K
9078 11:45:51.144738 ZQ Calibration : PASS
9079 11:45:51.145157 Jitter Meter : NO K
9080 11:45:51.148112 CBT Training : PASS
9081 11:45:51.151152 Write leveling : PASS
9082 11:45:51.151572 RX DQS gating : PASS
9083 11:45:51.154797 RX DQ/DQS(RDDQC) : PASS
9084 11:45:51.157593 TX DQ/DQS : PASS
9085 11:45:51.158015 RX DATLAT : PASS
9086 11:45:51.161124 RX DQ/DQS(Engine): PASS
9087 11:45:51.164278 TX OE : PASS
9088 11:45:51.164699 All Pass.
9089 11:45:51.165035
9090 11:45:51.165344 CH 1, Rank 0
9091 11:45:51.167348 SW Impedance : PASS
9092 11:45:51.171055 DUTY Scan : NO K
9093 11:45:51.171607 ZQ Calibration : PASS
9094 11:45:51.174331 Jitter Meter : NO K
9095 11:45:51.177349 CBT Training : PASS
9096 11:45:51.177766 Write leveling : PASS
9097 11:45:51.180428 RX DQS gating : PASS
9098 11:45:51.184014 RX DQ/DQS(RDDQC) : PASS
9099 11:45:51.184480 TX DQ/DQS : PASS
9100 11:45:51.187389 RX DATLAT : PASS
9101 11:45:51.191209 RX DQ/DQS(Engine): PASS
9102 11:45:51.191726 TX OE : PASS
9103 11:45:51.194010 All Pass.
9104 11:45:51.194475
9105 11:45:51.194813 CH 1, Rank 1
9106 11:45:51.197277 SW Impedance : PASS
9107 11:45:51.197692 DUTY Scan : NO K
9108 11:45:51.200456 ZQ Calibration : PASS
9109 11:45:51.204073 Jitter Meter : NO K
9110 11:45:51.204583 CBT Training : PASS
9111 11:45:51.206919 Write leveling : PASS
9112 11:45:51.210371 RX DQS gating : PASS
9113 11:45:51.210876 RX DQ/DQS(RDDQC) : PASS
9114 11:45:51.213322 TX DQ/DQS : PASS
9115 11:45:51.217059 RX DATLAT : PASS
9116 11:45:51.217560 RX DQ/DQS(Engine): PASS
9117 11:45:51.220010 TX OE : PASS
9118 11:45:51.220426 All Pass.
9119 11:45:51.220755
9120 11:45:51.223802 DramC Write-DBI on
9121 11:45:51.227254 PER_BANK_REFRESH: Hybrid Mode
9122 11:45:51.227674 TX_TRACKING: ON
9123 11:45:51.236636 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9124 11:45:51.242945 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9125 11:45:51.249534 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9126 11:45:51.256049 [FAST_K] Save calibration result to emmc
9127 11:45:51.256465 sync common calibartion params.
9128 11:45:51.259872 sync cbt_mode0:1, 1:1
9129 11:45:51.262955 dram_init: ddr_geometry: 2
9130 11:45:51.263421 dram_init: ddr_geometry: 2
9131 11:45:51.265833 dram_init: ddr_geometry: 2
9132 11:45:51.269054 0:dram_rank_size:100000000
9133 11:45:51.272436 1:dram_rank_size:100000000
9134 11:45:51.275871 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9135 11:45:51.278906 DFS_SHUFFLE_HW_MODE: ON
9136 11:45:51.282379 dramc_set_vcore_voltage set vcore to 725000
9137 11:45:51.285636 Read voltage for 1600, 0
9138 11:45:51.286093 Vio18 = 0
9139 11:45:51.289471 Vcore = 725000
9140 11:45:51.289881 Vdram = 0
9141 11:45:51.290209 Vddq = 0
9142 11:45:51.290565 Vmddr = 0
9143 11:45:51.292267 switch to 3200 Mbps bootup
9144 11:45:51.295685 [DramcRunTimeConfig]
9145 11:45:51.296099 PHYPLL
9146 11:45:51.298830 DPM_CONTROL_AFTERK: ON
9147 11:45:51.299241 PER_BANK_REFRESH: ON
9148 11:45:51.301906 REFRESH_OVERHEAD_REDUCTION: ON
9149 11:45:51.305681 CMD_PICG_NEW_MODE: OFF
9150 11:45:51.306194 XRTWTW_NEW_MODE: ON
9151 11:45:51.308759 XRTRTR_NEW_MODE: ON
9152 11:45:51.309277 TX_TRACKING: ON
9153 11:45:51.311822 RDSEL_TRACKING: OFF
9154 11:45:51.315510 DQS Precalculation for DVFS: ON
9155 11:45:51.316034 RX_TRACKING: OFF
9156 11:45:51.318592 HW_GATING DBG: ON
9157 11:45:51.319009 ZQCS_ENABLE_LP4: ON
9158 11:45:51.322029 RX_PICG_NEW_MODE: ON
9159 11:45:51.322521 TX_PICG_NEW_MODE: ON
9160 11:45:51.325512 ENABLE_RX_DCM_DPHY: ON
9161 11:45:51.328460 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9162 11:45:51.332021 DUMMY_READ_FOR_TRACKING: OFF
9163 11:45:51.332609 !!! SPM_CONTROL_AFTERK: OFF
9164 11:45:51.334780 !!! SPM could not control APHY
9165 11:45:51.338114 IMPEDANCE_TRACKING: ON
9166 11:45:51.338555 TEMP_SENSOR: ON
9167 11:45:51.341684 HW_SAVE_FOR_SR: OFF
9168 11:45:51.345182 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9169 11:45:51.347948 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9170 11:45:51.348432 Read ODT Tracking: ON
9171 11:45:51.351395 Refresh Rate DeBounce: ON
9172 11:45:51.354917 DFS_NO_QUEUE_FLUSH: ON
9173 11:45:51.357994 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9174 11:45:51.361571 ENABLE_DFS_RUNTIME_MRW: OFF
9175 11:45:51.361984 DDR_RESERVE_NEW_MODE: ON
9176 11:45:51.364551 MR_CBT_SWITCH_FREQ: ON
9177 11:45:51.368076 =========================
9178 11:45:51.385015 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9179 11:45:51.388553 dram_init: ddr_geometry: 2
9180 11:45:51.407472 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9181 11:45:51.410212 dram_init: dram init end (result: 0)
9182 11:45:51.416895 DRAM-K: Full calibration passed in 24425 msecs
9183 11:45:51.420309 MRC: failed to locate region type 0.
9184 11:45:51.420722 DRAM rank0 size:0x100000000,
9185 11:45:51.423082 DRAM rank1 size=0x100000000
9186 11:45:51.433538 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9187 11:45:51.440082 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9188 11:45:51.446125 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9189 11:45:51.456159 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9190 11:45:51.456578 DRAM rank0 size:0x100000000,
9191 11:45:51.459860 DRAM rank1 size=0x100000000
9192 11:45:51.460274 CBMEM:
9193 11:45:51.462740 IMD: root @ 0xfffff000 254 entries.
9194 11:45:51.466080 IMD: root @ 0xffffec00 62 entries.
9195 11:45:51.469560 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9196 11:45:51.476172 WARNING: RO_VPD is uninitialized or empty.
9197 11:45:51.479019 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9198 11:45:51.487153 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9199 11:45:51.499696 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9200 11:45:51.510830 BS: romstage times (exec / console): total (unknown) / 23956 ms
9201 11:45:51.511251
9202 11:45:51.511581
9203 11:45:51.520967 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9204 11:45:51.524258 ARM64: Exception handlers installed.
9205 11:45:51.527312 ARM64: Testing exception
9206 11:45:51.530632 ARM64: Done test exception
9207 11:45:51.531048 Enumerating buses...
9208 11:45:51.534096 Show all devs... Before device enumeration.
9209 11:45:51.536913 Root Device: enabled 1
9210 11:45:51.540610 CPU_CLUSTER: 0: enabled 1
9211 11:45:51.541023 CPU: 00: enabled 1
9212 11:45:51.543891 Compare with tree...
9213 11:45:51.544302 Root Device: enabled 1
9214 11:45:51.547013 CPU_CLUSTER: 0: enabled 1
9215 11:45:51.550729 CPU: 00: enabled 1
9216 11:45:51.551157 Root Device scanning...
9217 11:45:51.553670 scan_static_bus for Root Device
9218 11:45:51.556691 CPU_CLUSTER: 0 enabled
9219 11:45:51.560194 scan_static_bus for Root Device done
9220 11:45:51.563551 scan_bus: bus Root Device finished in 8 msecs
9221 11:45:51.564001 done
9222 11:45:51.569844 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9223 11:45:51.573496 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9224 11:45:51.580155 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9225 11:45:51.586622 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9226 11:45:51.587038 Allocating resources...
9227 11:45:51.589789 Reading resources...
9228 11:45:51.593000 Root Device read_resources bus 0 link: 0
9229 11:45:51.596352 DRAM rank0 size:0x100000000,
9230 11:45:51.596767 DRAM rank1 size=0x100000000
9231 11:45:51.602806 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9232 11:45:51.603224 CPU: 00 missing read_resources
9233 11:45:51.609655 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9234 11:45:51.612773 Root Device read_resources bus 0 link: 0 done
9235 11:45:51.616447 Done reading resources.
9236 11:45:51.619348 Show resources in subtree (Root Device)...After reading.
9237 11:45:51.622948 Root Device child on link 0 CPU_CLUSTER: 0
9238 11:45:51.626408 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 11:45:51.635636 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 11:45:51.636058 CPU: 00
9241 11:45:51.642527 Root Device assign_resources, bus 0 link: 0
9242 11:45:51.645837 CPU_CLUSTER: 0 missing set_resources
9243 11:45:51.649187 Root Device assign_resources, bus 0 link: 0 done
9244 11:45:51.652484 Done setting resources.
9245 11:45:51.655600 Show resources in subtree (Root Device)...After assigning values.
9246 11:45:51.661877 Root Device child on link 0 CPU_CLUSTER: 0
9247 11:45:51.665333 CPU_CLUSTER: 0 child on link 0 CPU: 00
9248 11:45:51.671964 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9249 11:45:51.675665 CPU: 00
9250 11:45:51.676075 Done allocating resources.
9251 11:45:51.681642 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9252 11:45:51.685201 Enabling resources...
9253 11:45:51.685669 done.
9254 11:45:51.688207 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9255 11:45:51.691580 Initializing devices...
9256 11:45:51.692044 Root Device init
9257 11:45:51.694919 init hardware done!
9258 11:45:51.697995 0x00000018: ctrlr->caps
9259 11:45:51.698514 52.000 MHz: ctrlr->f_max
9260 11:45:51.701797 0.400 MHz: ctrlr->f_min
9261 11:45:51.705115 0x40ff8080: ctrlr->voltages
9262 11:45:51.705533 sclk: 390625
9263 11:45:51.705893 Bus Width = 1
9264 11:45:51.707986 sclk: 390625
9265 11:45:51.708433 Bus Width = 1
9266 11:45:51.711655 Early init status = 3
9267 11:45:51.714420 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9268 11:45:51.718515 in-header: 03 fb 00 00 01 00 00 00
9269 11:45:51.722045 in-data: 01
9270 11:45:51.724878 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9271 11:45:51.728698 in-header: 03 fb 00 00 01 00 00 00
9272 11:45:51.732283 in-data: 01
9273 11:45:51.735552 [SSUSB] Setting up USB HOST controller...
9274 11:45:51.738557 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9275 11:45:51.742166 [SSUSB] phy power-on done.
9276 11:45:51.745474 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9277 11:45:51.751983 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9278 11:45:51.755381 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9279 11:45:51.761631 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9280 11:45:51.768189 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9281 11:45:51.775266 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9282 11:45:51.781675 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9283 11:45:51.788342 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9284 11:45:51.791777 SPM: binary array size = 0x9dc
9285 11:45:51.795187 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9286 11:45:51.801720 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9287 11:45:51.807958 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9288 11:45:51.814866 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9289 11:45:51.817841 configure_display: Starting display init
9290 11:45:51.852173 anx7625_power_on_init: Init interface.
9291 11:45:51.855749 anx7625_disable_pd_protocol: Disabled PD feature.
9292 11:45:51.858816 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9293 11:45:51.886714 anx7625_start_dp_work: Secure OCM version=00
9294 11:45:51.889821 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9295 11:45:51.904828 sp_tx_get_edid_block: EDID Block = 1
9296 11:45:52.007445 Extracted contents:
9297 11:45:52.010983 header: 00 ff ff ff ff ff ff 00
9298 11:45:52.014286 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9299 11:45:52.017185 version: 01 04
9300 11:45:52.020784 basic params: 95 1f 11 78 0a
9301 11:45:52.024137 chroma info: 76 90 94 55 54 90 27 21 50 54
9302 11:45:52.027102 established: 00 00 00
9303 11:45:52.034046 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9304 11:45:52.040000 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9305 11:45:52.044141 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9306 11:45:52.050322 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9307 11:45:52.056936 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9308 11:45:52.060461 extensions: 00
9309 11:45:52.060981 checksum: fb
9310 11:45:52.061320
9311 11:45:52.066523 Manufacturer: IVO Model 57d Serial Number 0
9312 11:45:52.066943 Made week 0 of 2020
9313 11:45:52.069963 EDID version: 1.4
9314 11:45:52.070443 Digital display
9315 11:45:52.073400 6 bits per primary color channel
9316 11:45:52.073827 DisplayPort interface
9317 11:45:52.076280 Maximum image size: 31 cm x 17 cm
9318 11:45:52.079646 Gamma: 220%
9319 11:45:52.080067 Check DPMS levels
9320 11:45:52.086709 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9321 11:45:52.089515 First detailed timing is preferred timing
9322 11:45:52.092860 Established timings supported:
9323 11:45:52.093277 Standard timings supported:
9324 11:45:52.096432 Detailed timings
9325 11:45:52.099625 Hex of detail: 383680a07038204018303c0035ae10000019
9326 11:45:52.106155 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9327 11:45:52.109869 0780 0798 07c8 0820 hborder 0
9328 11:45:52.112783 0438 043b 0447 0458 vborder 0
9329 11:45:52.116065 -hsync -vsync
9330 11:45:52.116577 Did detailed timing
9331 11:45:52.122731 Hex of detail: 000000000000000000000000000000000000
9332 11:45:52.126315 Manufacturer-specified data, tag 0
9333 11:45:52.129405 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9334 11:45:52.132654 ASCII string: InfoVision
9335 11:45:52.135519 Hex of detail: 000000fe00523134304e574635205248200a
9336 11:45:52.138884 ASCII string: R140NWF5 RH
9337 11:45:52.139351 Checksum
9338 11:45:52.142348 Checksum: 0xfb (valid)
9339 11:45:52.145740 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9340 11:45:52.148906 DSI data_rate: 832800000 bps
9341 11:45:52.155510 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9342 11:45:52.159100 anx7625_parse_edid: pixelclock(138800).
9343 11:45:52.162311 hactive(1920), hsync(48), hfp(24), hbp(88)
9344 11:45:52.165507 vactive(1080), vsync(12), vfp(3), vbp(17)
9345 11:45:52.168620 anx7625_dsi_config: config dsi.
9346 11:45:52.175450 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9347 11:45:52.189537 anx7625_dsi_config: success to config DSI
9348 11:45:52.192575 anx7625_dp_start: MIPI phy setup OK.
9349 11:45:52.195865 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9350 11:45:52.199168 mtk_ddp_mode_set invalid vrefresh 60
9351 11:45:52.202809 main_disp_path_setup
9352 11:45:52.203229 ovl_layer_smi_id_en
9353 11:45:52.206211 ovl_layer_smi_id_en
9354 11:45:52.206690 ccorr_config
9355 11:45:52.207023 aal_config
9356 11:45:52.209288 gamma_config
9357 11:45:52.209712 postmask_config
9358 11:45:52.213105 dither_config
9359 11:45:52.215682 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9360 11:45:52.222173 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9361 11:45:52.225783 Root Device init finished in 529 msecs
9362 11:45:52.228939 CPU_CLUSTER: 0 init
9363 11:45:52.235546 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9364 11:45:52.241883 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9365 11:45:52.242355 APU_MBOX 0x190000b0 = 0x10001
9366 11:45:52.245239 APU_MBOX 0x190001b0 = 0x10001
9367 11:45:52.248774 APU_MBOX 0x190005b0 = 0x10001
9368 11:45:52.252145 APU_MBOX 0x190006b0 = 0x10001
9369 11:45:52.258431 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9370 11:45:52.268486 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9371 11:45:52.280735 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9372 11:45:52.286969 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9373 11:45:52.298888 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9374 11:45:52.308452 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9375 11:45:52.311711 CPU_CLUSTER: 0 init finished in 81 msecs
9376 11:45:52.314740 Devices initialized
9377 11:45:52.318525 Show all devs... After init.
9378 11:45:52.318941 Root Device: enabled 1
9379 11:45:52.321257 CPU_CLUSTER: 0: enabled 1
9380 11:45:52.325053 CPU: 00: enabled 1
9381 11:45:52.328578 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9382 11:45:52.331355 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9383 11:45:52.334746 ELOG: NV offset 0x57f000 size 0x1000
9384 11:45:52.341624 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9385 11:45:52.348066 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9386 11:45:52.351337 ELOG: Event(17) added with size 13 at 2023-11-24 11:45:53 UTC
9387 11:45:52.357580 out: cmd=0x121: 03 db 21 01 00 00 00 00
9388 11:45:52.360896 in-header: 03 46 00 00 2c 00 00 00
9389 11:45:52.371215 in-data: 19 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9390 11:45:52.377583 ELOG: Event(A1) added with size 10 at 2023-11-24 11:45:53 UTC
9391 11:45:52.383856 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9392 11:45:52.391007 ELOG: Event(A0) added with size 9 at 2023-11-24 11:45:53 UTC
9393 11:45:52.394300 elog_add_boot_reason: Logged dev mode boot
9394 11:45:52.400965 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9395 11:45:52.401491 Finalize devices...
9396 11:45:52.403771 Devices finalized
9397 11:45:52.407047 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9398 11:45:52.410303 Writing coreboot table at 0xffe64000
9399 11:45:52.413600 0. 000000000010a000-0000000000113fff: RAMSTAGE
9400 11:45:52.420326 1. 0000000040000000-00000000400fffff: RAM
9401 11:45:52.423447 2. 0000000040100000-000000004032afff: RAMSTAGE
9402 11:45:52.427087 3. 000000004032b000-00000000545fffff: RAM
9403 11:45:52.430055 4. 0000000054600000-000000005465ffff: BL31
9404 11:45:52.433574 5. 0000000054660000-00000000ffe63fff: RAM
9405 11:45:52.439994 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9406 11:45:52.443121 7. 0000000100000000-000000023fffffff: RAM
9407 11:45:52.446729 Passing 5 GPIOs to payload:
9408 11:45:52.450074 NAME | PORT | POLARITY | VALUE
9409 11:45:52.456638 EC in RW | 0x000000aa | low | undefined
9410 11:45:52.459712 EC interrupt | 0x00000005 | low | undefined
9411 11:45:52.466674 TPM interrupt | 0x000000ab | high | undefined
9412 11:45:52.470207 SD card detect | 0x00000011 | high | undefined
9413 11:45:52.473429 speaker enable | 0x00000093 | high | undefined
9414 11:45:52.476234 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9415 11:45:52.479931 in-header: 03 f9 00 00 02 00 00 00
9416 11:45:52.482767 in-data: 02 00
9417 11:45:52.486159 ADC[4]: Raw value=901847 ID=7
9418 11:45:52.489624 ADC[3]: Raw value=213916 ID=1
9419 11:45:52.490130 RAM Code: 0x71
9420 11:45:52.493357 ADC[6]: Raw value=74630 ID=0
9421 11:45:52.496410 ADC[5]: Raw value=213916 ID=1
9422 11:45:52.496851 SKU Code: 0x1
9423 11:45:52.502802 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum dd3
9424 11:45:52.503228 coreboot table: 964 bytes.
9425 11:45:52.505835 IMD ROOT 0. 0xfffff000 0x00001000
9426 11:45:52.509495 IMD SMALL 1. 0xffffe000 0x00001000
9427 11:45:52.512878 RO MCACHE 2. 0xffffc000 0x00001104
9428 11:45:52.515777 CONSOLE 3. 0xfff7c000 0x00080000
9429 11:45:52.519579 FMAP 4. 0xfff7b000 0x00000452
9430 11:45:52.522352 TIME STAMP 5. 0xfff7a000 0x00000910
9431 11:45:52.526028 VBOOT WORK 6. 0xfff66000 0x00014000
9432 11:45:52.528940 RAMOOPS 7. 0xffe66000 0x00100000
9433 11:45:52.532167 COREBOOT 8. 0xffe64000 0x00002000
9434 11:45:52.536185 IMD small region:
9435 11:45:52.538781 IMD ROOT 0. 0xffffec00 0x00000400
9436 11:45:52.541952 VPD 1. 0xffffeb80 0x0000006c
9437 11:45:52.545467 MMC STATUS 2. 0xffffeb60 0x00000004
9438 11:45:52.551758 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9439 11:45:52.552179 Probing TPM: done!
9440 11:45:52.558521 Connected to device vid:did:rid of 1ae0:0028:00
9441 11:45:52.565383 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9442 11:45:52.568526 Initialized TPM device CR50 revision 0
9443 11:45:52.572482 Checking cr50 for pending updates
9444 11:45:52.577666 Reading cr50 TPM mode
9445 11:45:52.586207 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9446 11:45:52.592737 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9447 11:45:52.633228 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9448 11:45:52.636659 Checking segment from ROM address 0x40100000
9449 11:45:52.639893 Checking segment from ROM address 0x4010001c
9450 11:45:52.646424 Loading segment from ROM address 0x40100000
9451 11:45:52.646916 code (compression=0)
9452 11:45:52.656444 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9453 11:45:52.662694 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9454 11:45:52.663191 it's not compressed!
9455 11:45:52.669415 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9456 11:45:52.676251 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9457 11:45:52.693582 Loading segment from ROM address 0x4010001c
9458 11:45:52.694000 Entry Point 0x80000000
9459 11:45:52.696860 Loaded segments
9460 11:45:52.700329 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9461 11:45:52.706487 Jumping to boot code at 0x80000000(0xffe64000)
9462 11:45:52.713425 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9463 11:45:52.720015 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9464 11:45:52.728492 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9465 11:45:52.731682 Checking segment from ROM address 0x40100000
9466 11:45:52.735045 Checking segment from ROM address 0x4010001c
9467 11:45:52.741324 Loading segment from ROM address 0x40100000
9468 11:45:52.741762 code (compression=1)
9469 11:45:52.748004 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9470 11:45:52.757855 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9471 11:45:52.758319 using LZMA
9472 11:45:52.766235 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9473 11:45:52.773698 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9474 11:45:52.776303 Loading segment from ROM address 0x4010001c
9475 11:45:52.776728 Entry Point 0x54601000
9476 11:45:52.779371 Loaded segments
9477 11:45:52.782827 NOTICE: MT8192 bl31_setup
9478 11:45:52.790015 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9479 11:45:52.793621 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9480 11:45:52.796330 WARNING: region 0:
9481 11:45:52.799939 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 11:45:52.800471 WARNING: region 1:
9483 11:45:52.806734 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9484 11:45:52.809620 WARNING: region 2:
9485 11:45:52.813072 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9486 11:45:52.816541 WARNING: region 3:
9487 11:45:52.819855 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 11:45:52.823169 WARNING: region 4:
9489 11:45:52.829715 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 11:45:52.830244 WARNING: region 5:
9491 11:45:52.833415 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 11:45:52.836301 WARNING: region 6:
9493 11:45:52.839960 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 11:45:52.843283 WARNING: region 7:
9495 11:45:52.846327 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 11:45:52.852655 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9497 11:45:52.856139 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9498 11:45:52.862772 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9499 11:45:52.866288 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9500 11:45:52.869816 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9501 11:45:52.876111 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9502 11:45:52.879897 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9503 11:45:52.882681 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9504 11:45:52.889916 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9505 11:45:52.892914 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9506 11:45:52.896087 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9507 11:45:52.903152 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9508 11:45:52.905984 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9509 11:45:52.912658 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9510 11:45:52.915813 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9511 11:45:52.919168 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9512 11:45:52.925475 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9513 11:45:52.928808 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9514 11:45:52.935811 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9515 11:45:52.938688 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9516 11:45:52.942772 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9517 11:45:52.948941 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9518 11:45:52.952377 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9519 11:45:52.955588 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9520 11:45:52.962170 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9521 11:45:52.965546 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9522 11:45:52.972420 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9523 11:45:52.975236 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9524 11:45:52.982241 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9525 11:45:52.985895 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9526 11:45:52.989301 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9527 11:45:52.995235 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9528 11:45:52.998576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9529 11:45:53.001684 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9530 11:45:53.005702 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9531 11:45:53.012297 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9532 11:45:53.015177 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9533 11:45:53.018590 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9534 11:45:53.022120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9535 11:45:53.028814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9536 11:45:53.032030 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9537 11:45:53.034876 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9538 11:45:53.038620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9539 11:45:53.045031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9540 11:45:53.048402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9541 11:45:53.051884 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9542 11:45:53.058783 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9543 11:45:53.061584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9544 11:45:53.065111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9545 11:45:53.071906 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9546 11:45:53.075137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9547 11:45:53.078512 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9548 11:45:53.084686 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9549 11:45:53.088468 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9550 11:45:53.094784 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9551 11:45:53.098164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9552 11:45:53.104659 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9553 11:45:53.108280 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9554 11:45:53.115319 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9555 11:45:53.117929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9556 11:45:53.121599 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9557 11:45:53.128166 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9558 11:45:53.131183 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9559 11:45:53.137729 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9560 11:45:53.141280 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9561 11:45:53.147971 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9562 11:45:53.151120 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9563 11:45:53.157790 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9564 11:45:53.161216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9565 11:45:53.164483 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9566 11:45:53.171050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9567 11:45:53.174476 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9568 11:45:53.180973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9569 11:45:53.184470 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9570 11:45:53.190943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9571 11:45:53.193927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9572 11:45:53.200954 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9573 11:45:53.204402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9574 11:45:53.207996 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9575 11:45:53.214065 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9576 11:45:53.217768 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9577 11:45:53.224223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9578 11:45:53.227563 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9579 11:45:53.234035 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9580 11:45:53.237709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9581 11:45:53.241214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9582 11:45:53.247229 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9583 11:45:53.251003 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9584 11:45:53.257273 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9585 11:45:53.261067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9586 11:45:53.267345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9587 11:45:53.271017 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9588 11:45:53.277271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9589 11:45:53.280642 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9590 11:45:53.284092 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9591 11:45:53.290487 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9592 11:45:53.293564 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9593 11:45:53.296917 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9594 11:45:53.303493 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9595 11:45:53.307077 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9596 11:45:53.310646 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9597 11:45:53.316971 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9598 11:45:53.320440 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9599 11:45:53.323899 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9600 11:45:53.330436 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9601 11:45:53.333950 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9602 11:45:53.340429 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9603 11:45:53.343383 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9604 11:45:53.346808 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9605 11:45:53.353531 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9606 11:45:53.357094 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9607 11:45:53.363198 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9608 11:45:53.366893 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9609 11:45:53.370545 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9610 11:45:53.376677 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9611 11:45:53.380142 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9612 11:45:53.383015 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9613 11:45:53.389913 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9614 11:45:53.393329 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9615 11:45:53.396305 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9616 11:45:53.403338 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9617 11:45:53.406550 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9618 11:45:53.409805 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9619 11:45:53.412966 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9620 11:45:53.419669 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9621 11:45:53.423109 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9622 11:45:53.429829 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9623 11:45:53.432839 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9624 11:45:53.436644 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9625 11:45:53.442855 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9626 11:45:53.446379 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9627 11:45:53.449421 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9628 11:45:53.456211 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9629 11:45:53.459732 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9630 11:45:53.466149 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9631 11:45:53.469199 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9632 11:45:53.472908 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9633 11:45:53.479705 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9634 11:45:53.482575 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9635 11:45:53.489841 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9636 11:45:53.492930 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9637 11:45:53.495964 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9638 11:45:53.503020 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9639 11:45:53.505904 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9640 11:45:53.512912 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9641 11:45:53.515950 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9642 11:45:53.519282 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9643 11:45:53.525891 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9644 11:45:53.529282 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9645 11:45:53.535915 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9646 11:45:53.539638 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9647 11:45:53.542787 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9648 11:45:53.549174 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9649 11:45:53.552507 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9650 11:45:53.555705 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9651 11:45:53.562367 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9652 11:45:53.565641 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9653 11:45:53.572107 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9654 11:45:53.575642 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9655 11:45:53.579251 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9656 11:45:53.585912 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9657 11:45:53.589081 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9658 11:45:53.595523 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9659 11:45:53.598796 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9660 11:45:53.601782 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9661 11:45:53.608888 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9662 11:45:53.612320 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9663 11:45:53.618603 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9664 11:45:53.621974 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9665 11:45:53.625023 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9666 11:45:53.631501 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9667 11:45:53.634911 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9668 11:45:53.641618 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9669 11:45:53.644648 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9670 11:45:53.648225 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9671 11:45:53.654793 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9672 11:45:53.657722 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9673 11:45:53.664686 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9674 11:45:53.667874 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9675 11:45:53.671185 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9676 11:45:53.677842 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9677 11:45:53.681189 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9678 11:45:53.687574 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9679 11:45:53.691030 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9680 11:45:53.697245 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9681 11:45:53.700752 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9682 11:45:53.704168 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9683 11:45:53.710594 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9684 11:45:53.713499 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9685 11:45:53.720649 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9686 11:45:53.724089 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9687 11:45:53.726965 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9688 11:45:53.733431 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9689 11:45:53.736682 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9690 11:45:53.743730 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9691 11:45:53.746508 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9692 11:45:53.753702 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9693 11:45:53.756438 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9694 11:45:53.763063 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9695 11:45:53.766423 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9696 11:45:53.769661 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9697 11:45:53.776388 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9698 11:45:53.779908 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9699 11:45:53.786392 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9700 11:45:53.789287 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9701 11:45:53.795856 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9702 11:45:53.799294 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9703 11:45:53.802485 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9704 11:45:53.809531 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9705 11:45:53.812493 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9706 11:45:53.818913 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9707 11:45:53.822287 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9708 11:45:53.829197 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9709 11:45:53.832255 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9710 11:45:53.835584 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9711 11:45:53.841972 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9712 11:45:53.845674 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9713 11:45:53.852331 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9714 11:45:53.855337 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9715 11:45:53.861978 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9716 11:45:53.864996 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9717 11:45:53.868439 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9718 11:45:53.875498 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9719 11:45:53.878195 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9720 11:45:53.884879 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9721 11:45:53.888241 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9722 11:45:53.891609 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9723 11:45:53.898937 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9724 11:45:53.901406 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9725 11:45:53.907885 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9726 11:45:53.911665 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9727 11:45:53.915105 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9728 11:45:53.917646 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9729 11:45:53.921314 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9730 11:45:53.927867 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9731 11:45:53.931624 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9732 11:45:53.937667 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9733 11:45:53.941067 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9734 11:45:53.944475 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9735 11:45:53.951309 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9736 11:45:53.954074 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9737 11:45:53.960615 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9738 11:45:53.963750 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9739 11:45:53.967508 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9740 11:45:53.973968 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9741 11:45:53.977210 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9742 11:45:53.980836 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9743 11:45:53.987047 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9744 11:45:53.990215 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9745 11:45:53.997355 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9746 11:45:53.999934 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9747 11:45:54.003790 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9748 11:45:54.010196 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9749 11:45:54.013187 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9750 11:45:54.016588 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9751 11:45:54.023408 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9752 11:45:54.026597 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9753 11:45:54.033181 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9754 11:45:54.036386 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9755 11:45:54.039865 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9756 11:45:54.046391 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9757 11:45:54.049752 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9758 11:45:54.056321 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9759 11:45:54.059825 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9760 11:45:54.062645 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9761 11:45:54.069376 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9762 11:45:54.072826 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9763 11:45:54.076035 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9764 11:45:54.082696 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9765 11:45:54.085995 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9766 11:45:54.088985 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9767 11:45:54.092523 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9768 11:45:54.098984 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9769 11:45:54.102098 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9770 11:45:54.105483 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9771 11:45:54.109346 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9772 11:45:54.115595 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9773 11:45:54.118471 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9774 11:45:54.121872 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9775 11:45:54.125219 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9776 11:45:54.132161 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9777 11:45:54.135043 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9778 11:45:54.138574 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9779 11:45:54.144951 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9780 11:45:54.148323 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9781 11:45:54.154789 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9782 11:45:54.158314 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9783 11:45:54.164949 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9784 11:45:54.167944 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9785 11:45:54.171578 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9786 11:45:54.178231 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9787 11:45:54.181447 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9788 11:45:54.187929 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9789 11:45:54.191121 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9790 11:45:54.197427 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9791 11:45:54.200972 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9792 11:45:54.204487 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9793 11:45:54.210748 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9794 11:45:54.214210 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9795 11:45:54.220827 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9796 11:45:54.224381 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9797 11:45:54.230999 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9798 11:45:54.234146 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9799 11:45:54.236943 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9800 11:45:54.244057 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9801 11:45:54.246776 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9802 11:45:54.253327 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9803 11:45:54.256683 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9804 11:45:54.260200 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9805 11:45:54.266544 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9806 11:45:54.270154 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9807 11:45:54.276601 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9808 11:45:54.280291 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9809 11:45:54.283091 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9810 11:45:54.289891 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9811 11:45:54.292984 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9812 11:45:54.299649 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9813 11:45:54.302984 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9814 11:45:54.309660 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9815 11:45:54.312620 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9816 11:45:54.319415 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9817 11:45:54.323238 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9818 11:45:54.325752 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9819 11:45:54.332470 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9820 11:45:54.336002 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9821 11:45:54.342481 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9822 11:45:54.345730 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9823 11:45:54.352055 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9824 11:45:54.355693 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9825 11:45:54.359185 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9826 11:45:54.365599 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9827 11:45:54.369102 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9828 11:45:54.375184 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9829 11:45:54.378791 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9830 11:45:54.381768 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9831 11:45:54.388201 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9832 11:45:54.391688 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9833 11:45:54.398129 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9834 11:45:54.401524 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9835 11:45:54.404758 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9836 11:45:54.411901 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9837 11:45:54.414990 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9838 11:45:54.421101 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9839 11:45:54.424758 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9840 11:45:54.431055 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9841 11:45:54.434461 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9842 11:45:54.437415 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9843 11:45:54.444039 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9844 11:45:54.447356 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9845 11:45:54.454019 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9846 11:45:54.457286 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9847 11:45:54.463905 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9848 11:45:54.467364 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9849 11:45:54.470921 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9850 11:45:54.477305 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9851 11:45:54.480316 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9852 11:45:54.486729 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9853 11:45:54.490304 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9854 11:45:54.496942 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9855 11:45:54.500122 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9856 11:45:54.507141 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9857 11:45:54.510033 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9858 11:45:54.513564 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9859 11:45:54.519805 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9860 11:45:54.523439 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9861 11:45:54.529748 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9862 11:45:54.533198 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9863 11:45:54.539719 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9864 11:45:54.543347 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9865 11:45:54.546357 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9866 11:45:54.553167 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9867 11:45:54.556312 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9868 11:45:54.563162 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9869 11:45:54.566331 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9870 11:45:54.572862 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9871 11:45:54.576160 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9872 11:45:54.582857 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9873 11:45:54.586224 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9874 11:45:54.592842 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9875 11:45:54.595635 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9876 11:45:54.599156 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9877 11:45:54.605826 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9878 11:45:54.608723 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9879 11:45:54.615516 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9880 11:45:54.618707 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9881 11:45:54.625531 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9882 11:45:54.628657 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9883 11:45:54.635155 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9884 11:45:54.638793 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9885 11:45:54.641801 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9886 11:45:54.648125 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9887 11:45:54.651292 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9888 11:45:54.658238 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9889 11:45:54.661443 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9890 11:45:54.668048 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9891 11:45:54.671486 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9892 11:45:54.677906 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9893 11:45:54.681498 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9894 11:45:54.684541 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9895 11:45:54.691518 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9896 11:45:54.694348 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9897 11:45:54.701248 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9898 11:45:54.704735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9899 11:45:54.707601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9900 11:45:54.714679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9901 11:45:54.717905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9902 11:45:54.724313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9903 11:45:54.727780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9904 11:45:54.734347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9905 11:45:54.737779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9906 11:45:54.744078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9907 11:45:54.747828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9908 11:45:54.753987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9909 11:45:54.757928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9910 11:45:54.764225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9911 11:45:54.767485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9912 11:45:54.773894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9913 11:45:54.777019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9914 11:45:54.783773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9915 11:45:54.787570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9916 11:45:54.793686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9917 11:45:54.796890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9918 11:45:54.803494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9919 11:45:54.807102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9920 11:45:54.813543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9921 11:45:54.817178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9922 11:45:54.823543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9923 11:45:54.826869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9924 11:45:54.833396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9925 11:45:54.836915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9926 11:45:54.843192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9927 11:45:54.846750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9928 11:45:54.853376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9929 11:45:54.857005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9930 11:45:54.862941 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9931 11:45:54.863502 INFO: [APUAPC] vio 0
9932 11:45:54.869834 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9933 11:45:54.873331 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9934 11:45:54.876489 INFO: [APUAPC] D0_APC_0: 0x400510
9935 11:45:54.879909 INFO: [APUAPC] D0_APC_1: 0x0
9936 11:45:54.883188 INFO: [APUAPC] D0_APC_2: 0x1540
9937 11:45:54.886153 INFO: [APUAPC] D0_APC_3: 0x0
9938 11:45:54.889767 INFO: [APUAPC] D1_APC_0: 0xffffffff
9939 11:45:54.892815 INFO: [APUAPC] D1_APC_1: 0xffffffff
9940 11:45:54.896093 INFO: [APUAPC] D1_APC_2: 0x3fffff
9941 11:45:54.899443 INFO: [APUAPC] D1_APC_3: 0x0
9942 11:45:54.902668 INFO: [APUAPC] D2_APC_0: 0xffffffff
9943 11:45:54.906130 INFO: [APUAPC] D2_APC_1: 0xffffffff
9944 11:45:54.909575 INFO: [APUAPC] D2_APC_2: 0x3fffff
9945 11:45:54.912677 INFO: [APUAPC] D2_APC_3: 0x0
9946 11:45:54.915836 INFO: [APUAPC] D3_APC_0: 0xffffffff
9947 11:45:54.919261 INFO: [APUAPC] D3_APC_1: 0xffffffff
9948 11:45:54.922599 INFO: [APUAPC] D3_APC_2: 0x3fffff
9949 11:45:54.925510 INFO: [APUAPC] D3_APC_3: 0x0
9950 11:45:54.929036 INFO: [APUAPC] D4_APC_0: 0xffffffff
9951 11:45:54.932385 INFO: [APUAPC] D4_APC_1: 0xffffffff
9952 11:45:54.935447 INFO: [APUAPC] D4_APC_2: 0x3fffff
9953 11:45:54.938901 INFO: [APUAPC] D4_APC_3: 0x0
9954 11:45:54.942415 INFO: [APUAPC] D5_APC_0: 0xffffffff
9955 11:45:54.945318 INFO: [APUAPC] D5_APC_1: 0xffffffff
9956 11:45:54.948767 INFO: [APUAPC] D5_APC_2: 0x3fffff
9957 11:45:54.952229 INFO: [APUAPC] D5_APC_3: 0x0
9958 11:45:54.955326 INFO: [APUAPC] D6_APC_0: 0xffffffff
9959 11:45:54.958609 INFO: [APUAPC] D6_APC_1: 0xffffffff
9960 11:45:54.961787 INFO: [APUAPC] D6_APC_2: 0x3fffff
9961 11:45:54.965721 INFO: [APUAPC] D6_APC_3: 0x0
9962 11:45:54.968575 INFO: [APUAPC] D7_APC_0: 0xffffffff
9963 11:45:54.971804 INFO: [APUAPC] D7_APC_1: 0xffffffff
9964 11:45:54.975301 INFO: [APUAPC] D7_APC_2: 0x3fffff
9965 11:45:54.978759 INFO: [APUAPC] D7_APC_3: 0x0
9966 11:45:54.981471 INFO: [APUAPC] D8_APC_0: 0xffffffff
9967 11:45:54.984952 INFO: [APUAPC] D8_APC_1: 0xffffffff
9968 11:45:54.988656 INFO: [APUAPC] D8_APC_2: 0x3fffff
9969 11:45:54.989076 INFO: [APUAPC] D8_APC_3: 0x0
9970 11:45:54.994788 INFO: [APUAPC] D9_APC_0: 0xffffffff
9971 11:45:54.998358 INFO: [APUAPC] D9_APC_1: 0xffffffff
9972 11:45:55.001387 INFO: [APUAPC] D9_APC_2: 0x3fffff
9973 11:45:55.001851 INFO: [APUAPC] D9_APC_3: 0x0
9974 11:45:55.004960 INFO: [APUAPC] D10_APC_0: 0xffffffff
9975 11:45:55.011438 INFO: [APUAPC] D10_APC_1: 0xffffffff
9976 11:45:55.014454 INFO: [APUAPC] D10_APC_2: 0x3fffff
9977 11:45:55.014887 INFO: [APUAPC] D10_APC_3: 0x0
9978 11:45:55.021056 INFO: [APUAPC] D11_APC_0: 0xffffffff
9979 11:45:55.024750 INFO: [APUAPC] D11_APC_1: 0xffffffff
9980 11:45:55.028166 INFO: [APUAPC] D11_APC_2: 0x3fffff
9981 11:45:55.031130 INFO: [APUAPC] D11_APC_3: 0x0
9982 11:45:55.034188 INFO: [APUAPC] D12_APC_0: 0xffffffff
9983 11:45:55.037464 INFO: [APUAPC] D12_APC_1: 0xffffffff
9984 11:45:55.041334 INFO: [APUAPC] D12_APC_2: 0x3fffff
9985 11:45:55.043959 INFO: [APUAPC] D12_APC_3: 0x0
9986 11:45:55.047554 INFO: [APUAPC] D13_APC_0: 0xffffffff
9987 11:45:55.050963 INFO: [APUAPC] D13_APC_1: 0xffffffff
9988 11:45:55.053878 INFO: [APUAPC] D13_APC_2: 0x3fffff
9989 11:45:55.057306 INFO: [APUAPC] D13_APC_3: 0x0
9990 11:45:55.060861 INFO: [APUAPC] D14_APC_0: 0xffffffff
9991 11:45:55.063748 INFO: [APUAPC] D14_APC_1: 0xffffffff
9992 11:45:55.066755 INFO: [APUAPC] D14_APC_2: 0x3fffff
9993 11:45:55.070361 INFO: [APUAPC] D14_APC_3: 0x0
9994 11:45:55.073513 INFO: [APUAPC] D15_APC_0: 0xffffffff
9995 11:45:55.076963 INFO: [APUAPC] D15_APC_1: 0xffffffff
9996 11:45:55.079996 INFO: [APUAPC] D15_APC_2: 0x3fffff
9997 11:45:55.083381 INFO: [APUAPC] D15_APC_3: 0x0
9998 11:45:55.086811 INFO: [APUAPC] APC_CON: 0x4
9999 11:45:55.090333 INFO: [NOCDAPC] D0_APC_0: 0x0
10000 11:45:55.090755 INFO: [NOCDAPC] D0_APC_1: 0x0
10001 11:45:55.093219 INFO: [NOCDAPC] D1_APC_0: 0x0
10002 11:45:55.096831 INFO: [NOCDAPC] D1_APC_1: 0xfff
10003 11:45:55.099712 INFO: [NOCDAPC] D2_APC_0: 0x0
10004 11:45:55.103000 INFO: [NOCDAPC] D2_APC_1: 0xfff
10005 11:45:55.106233 INFO: [NOCDAPC] D3_APC_0: 0x0
10006 11:45:55.109520 INFO: [NOCDAPC] D3_APC_1: 0xfff
10007 11:45:55.113248 INFO: [NOCDAPC] D4_APC_0: 0x0
10008 11:45:55.116599 INFO: [NOCDAPC] D4_APC_1: 0xfff
10009 11:45:55.119305 INFO: [NOCDAPC] D5_APC_0: 0x0
10010 11:45:55.122911 INFO: [NOCDAPC] D5_APC_1: 0xfff
10011 11:45:55.126423 INFO: [NOCDAPC] D6_APC_0: 0x0
10012 11:45:55.126845 INFO: [NOCDAPC] D6_APC_1: 0xfff
10013 11:45:55.129291 INFO: [NOCDAPC] D7_APC_0: 0x0
10014 11:45:55.132648 INFO: [NOCDAPC] D7_APC_1: 0xfff
10015 11:45:55.135958 INFO: [NOCDAPC] D8_APC_0: 0x0
10016 11:45:55.139177 INFO: [NOCDAPC] D8_APC_1: 0xfff
10017 11:45:55.142553 INFO: [NOCDAPC] D9_APC_0: 0x0
10018 11:45:55.145758 INFO: [NOCDAPC] D9_APC_1: 0xfff
10019 11:45:55.149165 INFO: [NOCDAPC] D10_APC_0: 0x0
10020 11:45:55.152586 INFO: [NOCDAPC] D10_APC_1: 0xfff
10021 11:45:55.155710 INFO: [NOCDAPC] D11_APC_0: 0x0
10022 11:45:55.159034 INFO: [NOCDAPC] D11_APC_1: 0xfff
10023 11:45:55.162416 INFO: [NOCDAPC] D12_APC_0: 0x0
10024 11:45:55.165920 INFO: [NOCDAPC] D12_APC_1: 0xfff
10025 11:45:55.168846 INFO: [NOCDAPC] D13_APC_0: 0x0
10026 11:45:55.172407 INFO: [NOCDAPC] D13_APC_1: 0xfff
10027 11:45:55.172828 INFO: [NOCDAPC] D14_APC_0: 0x0
10028 11:45:55.175711 INFO: [NOCDAPC] D14_APC_1: 0xfff
10029 11:45:55.178554 INFO: [NOCDAPC] D15_APC_0: 0x0
10030 11:45:55.182085 INFO: [NOCDAPC] D15_APC_1: 0xfff
10031 11:45:55.185415 INFO: [NOCDAPC] APC_CON: 0x4
10032 11:45:55.188818 INFO: [APUAPC] set_apusys_apc done
10033 11:45:55.191887 INFO: [DEVAPC] devapc_init done
10034 11:45:55.195459 INFO: GICv3 without legacy support detected.
10035 11:45:55.201601 INFO: ARM GICv3 driver initialized in EL3
10036 11:45:55.205271 INFO: Maximum SPI INTID supported: 639
10037 11:45:55.208691 INFO: BL31: Initializing runtime services
10038 11:45:55.215440 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10039 11:45:55.215865 INFO: SPM: enable CPC mode
10040 11:45:55.221605 INFO: mcdi ready for mcusys-off-idle and system suspend
10041 11:45:55.224875 INFO: BL31: Preparing for EL3 exit to normal world
10042 11:45:55.231650 INFO: Entry point address = 0x80000000
10043 11:45:55.232097 INFO: SPSR = 0x8
10044 11:45:55.238049
10045 11:45:55.238499
10046 11:45:55.238830
10047 11:45:55.241370 Starting depthcharge on Spherion...
10048 11:45:55.241817
10049 11:45:55.242155 Wipe memory regions:
10050 11:45:55.242525
10051 11:45:55.245125 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10052 11:45:55.245640 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10053 11:45:55.246040 Setting prompt string to ['asurada:']
10054 11:45:55.246484 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10055 11:45:55.247143 [0x00000040000000, 0x00000054600000)
10056 11:45:55.367346
10057 11:45:55.367862 [0x00000054660000, 0x00000080000000)
10058 11:45:55.627556
10059 11:45:55.628051 [0x000000821a7280, 0x000000ffe64000)
10060 11:45:56.372769
10061 11:45:56.373283 [0x00000100000000, 0x00000240000000)
10062 11:45:58.262792
10063 11:45:58.266042 Initializing XHCI USB controller at 0x11200000.
10064 11:45:59.305007
10065 11:45:59.308572 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10066 11:45:59.308993
10067 11:45:59.309327
10068 11:45:59.309691
10069 11:45:59.310510 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10071 11:45:59.412056 asurada: tftpboot 192.168.201.1 12074008/tftp-deploy-ndrpbirt/kernel/image.itb 12074008/tftp-deploy-ndrpbirt/kernel/cmdline
10072 11:45:59.412608 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 11:45:59.413101 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10074 11:45:59.417299 tftpboot 192.168.201.1 12074008/tftp-deploy-ndrpbirt/kernel/image.ittp-deploy-ndrpbirt/kernel/cmdline
10075 11:45:59.417903
10076 11:45:59.418435 Waiting for link
10077 11:45:59.577953
10078 11:45:59.578552 R8152: Initializing
10079 11:45:59.579041
10080 11:45:59.581089 Version 6 (ocp_data = 5c30)
10081 11:45:59.581541
10082 11:45:59.584539 R8152: Done initializing
10083 11:45:59.584974
10084 11:45:59.585329 Adding net device
10085 11:46:01.561680
10086 11:46:01.562174 done.
10087 11:46:01.562549
10088 11:46:01.562862 MAC: 00:24:32:30:7c:7b
10089 11:46:01.563164
10090 11:46:01.565047 Sending DHCP discover... done.
10091 11:46:01.565511
10092 11:46:01.568657 Waiting for reply... done.
10093 11:46:01.569076
10094 11:46:01.572266 Sending DHCP request... done.
10095 11:46:01.572695
10096 11:46:01.577844 Waiting for reply... done.
10097 11:46:01.578302
10098 11:46:01.578651 My ip is 192.168.201.14
10099 11:46:01.578966
10100 11:46:01.580667 The DHCP server ip is 192.168.201.1
10101 11:46:01.581186
10102 11:46:01.587708 TFTP server IP predefined by user: 192.168.201.1
10103 11:46:01.588136
10104 11:46:01.594289 Bootfile predefined by user: 12074008/tftp-deploy-ndrpbirt/kernel/image.itb
10105 11:46:01.594824
10106 11:46:01.597252 Sending tftp read request... done.
10107 11:46:01.598061
10108 11:46:01.604942 Waiting for the transfer...
10109 11:46:01.605370
10110 11:46:02.210893 00000000 ################################################################
10111 11:46:02.211033
10112 11:46:02.793160 00080000 ################################################################
10113 11:46:02.793293
10114 11:46:03.368270 00100000 ################################################################
10115 11:46:03.368408
10116 11:46:03.924990 00180000 ################################################################
10117 11:46:03.925163
10118 11:46:04.487250 00200000 ################################################################
10119 11:46:04.487417
10120 11:46:05.070641 00280000 ################################################################
10121 11:46:05.070792
10122 11:46:05.632689 00300000 ################################################################
10123 11:46:05.632863
10124 11:46:06.228347 00380000 ################################################################
10125 11:46:06.228874
10126 11:46:06.900842 00400000 ################################################################
10127 11:46:06.901470
10128 11:46:07.608427 00480000 ################################################################
10129 11:46:07.608606
10130 11:46:08.266294 00500000 ################################################################
10131 11:46:08.266426
10132 11:46:08.900677 00580000 ################################################################
10133 11:46:08.900808
10134 11:46:09.477904 00600000 ################################################################
10135 11:46:09.478035
10136 11:46:10.078420 00680000 ################################################################
10137 11:46:10.078582
10138 11:46:10.750138 00700000 ################################################################
10139 11:46:10.750323
10140 11:46:11.360319 00780000 ################################################################
10141 11:46:11.360450
10142 11:46:11.945758 00800000 ################################################################
10143 11:46:11.946289
10144 11:46:12.573171 00880000 ################################################################
10145 11:46:12.573319
10146 11:46:13.270298 00900000 ################################################################
10147 11:46:13.270801
10148 11:46:13.968998 00980000 ################################################################
10149 11:46:13.969578
10150 11:46:14.679421 00a00000 ################################################################
10151 11:46:14.679909
10152 11:46:15.317938 00a80000 ################################################################
10153 11:46:15.318097
10154 11:46:15.976886 00b00000 ################################################################
10155 11:46:15.977397
10156 11:46:16.633540 00b80000 ################################################################
10157 11:46:16.633685
10158 11:46:17.335631 00c00000 ################################################################
10159 11:46:17.335807
10160 11:46:17.988143 00c80000 ################################################################
10161 11:46:17.988665
10162 11:46:18.688542 00d00000 ################################################################
10163 11:46:18.688686
10164 11:46:19.338029 00d80000 ################################################################
10165 11:46:19.338204
10166 11:46:19.974562 00e00000 ################################################################
10167 11:46:19.974708
10168 11:46:20.572800 00e80000 ################################################################
10169 11:46:20.572949
10170 11:46:21.222290 00f00000 ################################################################
10171 11:46:21.222440
10172 11:46:21.870115 00f80000 ################################################################
10173 11:46:21.870292
10174 11:46:22.503089 01000000 ################################################################
10175 11:46:22.503233
10176 11:46:23.124154 01080000 ################################################################
10177 11:46:23.124303
10178 11:46:23.772259 01100000 ################################################################
10179 11:46:23.772413
10180 11:46:24.357097 01180000 ################################################################
10181 11:46:24.357244
10182 11:46:24.951853 01200000 ################################################################
10183 11:46:24.952004
10184 11:46:25.525242 01280000 ################################################################
10185 11:46:25.525392
10186 11:46:26.075254 01300000 ################################################################
10187 11:46:26.075394
10188 11:46:26.708026 01380000 ################################################################
10189 11:46:26.708157
10190 11:46:27.370037 01400000 ################################################################
10191 11:46:27.370196
10192 11:46:27.968841 01480000 ################################################################
10193 11:46:27.969007
10194 11:46:28.648152 01500000 ################################################################
10195 11:46:28.648287
10196 11:46:29.307442 01580000 ################################################################
10197 11:46:29.307605
10198 11:46:30.015788 01600000 ################################################################
10199 11:46:30.016131
10200 11:46:30.590117 01680000 ################################################################
10201 11:46:30.590355
10202 11:46:31.249231 01700000 ################################################################
10203 11:46:31.249779
10204 11:46:31.918323 01780000 ################################################################
10205 11:46:31.918835
10206 11:46:32.613650 01800000 ################################################################
10207 11:46:32.614165
10208 11:46:33.331306 01880000 ################################################################
10209 11:46:33.331470
10210 11:46:34.024723 01900000 ################################################################
10211 11:46:34.025262
10212 11:46:34.734799 01980000 ################################################################
10213 11:46:34.735371
10214 11:46:35.422923 01a00000 ################################################################
10215 11:46:35.423431
10216 11:46:36.104690 01a80000 ################################################################
10217 11:46:36.105203
10218 11:46:36.782994 01b00000 ################################################################
10219 11:46:36.783483
10220 11:46:36.850910 01b80000 ####### done.
10221 11:46:36.851350
10222 11:46:36.854012 The bootfile was 28889306 bytes long.
10223 11:46:36.854479
10224 11:46:36.857508 Sending tftp read request... done.
10225 11:46:36.857940
10226 11:46:36.861724 Waiting for the transfer...
10227 11:46:36.862166
10228 11:46:36.862681 00000000 # done.
10229 11:46:36.863106
10230 11:46:36.868006 Command line loaded dynamically from TFTP file: 12074008/tftp-deploy-ndrpbirt/kernel/cmdline
10231 11:46:36.871346
10232 11:46:36.891306 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12074008/extract-nfsrootfs-s4qkpdjn,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10233 11:46:36.891820
10234 11:46:36.892263 Loading FIT.
10235 11:46:36.894927
10236 11:46:36.895355 Image ramdisk-1 has 17791746 bytes.
10237 11:46:36.895794
10238 11:46:36.897845 Image fdt-1 has 47278 bytes.
10239 11:46:36.898296
10240 11:46:36.902207 Image kernel-1 has 11048246 bytes.
10241 11:46:36.902800
10242 11:46:36.911119 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10243 11:46:36.911569
10244 11:46:36.927839 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10245 11:46:36.928284
10246 11:46:36.933927 Choosing best match conf-1 for compat google,spherion-rev2.
10247 11:46:36.937707
10248 11:46:36.942625 Connected to device vid:did:rid of 1ae0:0028:00
10249 11:46:36.949449
10250 11:46:36.952370 tpm_get_response: command 0x17b, return code 0x0
10251 11:46:36.952786
10252 11:46:36.955549 ec_init: CrosEC protocol v3 supported (256, 248)
10253 11:46:36.959896
10254 11:46:36.962869 tpm_cleanup: add release locality here.
10255 11:46:36.963286
10256 11:46:36.963613 Shutting down all USB controllers.
10257 11:46:36.966173
10258 11:46:36.966688 Removing current net device
10259 11:46:36.967025
10260 11:46:36.972969 Exiting depthcharge with code 4 at timestamp: 70955979
10261 11:46:36.973385
10262 11:46:36.976219 LZMA decompressing kernel-1 to 0x821a6718
10263 11:46:36.976636
10264 11:46:36.979881 LZMA decompressing kernel-1 to 0x40000000
10265 11:46:38.368691
10266 11:46:38.369202 jumping to kernel
10267 11:46:38.370796 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10268 11:46:38.371273 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10269 11:46:38.371643 Setting prompt string to ['Linux version [0-9]']
10270 11:46:38.371989 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10271 11:46:38.372330 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10272 11:46:38.450954
10273 11:46:38.453981 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10274 11:46:38.457655 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10275 11:46:38.458320 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10276 11:46:38.458734 Setting prompt string to []
10277 11:46:38.459151 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10278 11:46:38.459552 Using line separator: #'\n'#
10279 11:46:38.459886 No login prompt set.
10280 11:46:38.460232 Parsing kernel messages
10281 11:46:38.460538 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10282 11:46:38.461101 [login-action] Waiting for messages, (timeout 00:03:42)
10283 11:46:38.477733 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j23069-arm64-gcc-10-defconfig-arm64-chromebook-8pq2l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023
10284 11:46:38.480656 [ 0.000000] random: crng init done
10285 11:46:38.487692 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10286 11:46:38.490284 [ 0.000000] efi: UEFI not found.
10287 11:46:38.496670 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10288 11:46:38.506984 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10289 11:46:38.517129 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10290 11:46:38.522849 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10291 11:46:38.529857 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10292 11:46:38.536122 [ 0.000000] printk: bootconsole [mtk8250] enabled
10293 11:46:38.542859 [ 0.000000] NUMA: No NUMA configuration found
10294 11:46:38.549498 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10295 11:46:38.556269 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10296 11:46:38.556814 [ 0.000000] Zone ranges:
10297 11:46:38.562292 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10298 11:46:38.565798 [ 0.000000] DMA32 empty
10299 11:46:38.572966 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10300 11:46:38.575766 [ 0.000000] Movable zone start for each node
10301 11:46:38.578909 [ 0.000000] Early memory node ranges
10302 11:46:38.585614 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10303 11:46:38.592179 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10304 11:46:38.599220 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10305 11:46:38.605417 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10306 11:46:38.611811 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10307 11:46:38.619054 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10308 11:46:38.675261 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10309 11:46:38.681983 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10310 11:46:38.687937 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10311 11:46:38.691444 [ 0.000000] psci: probing for conduit method from DT.
10312 11:46:38.698761 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10313 11:46:38.701627 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10314 11:46:38.707794 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10315 11:46:38.711246 [ 0.000000] psci: SMC Calling Convention v1.2
10316 11:46:38.717632 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10317 11:46:38.721214 [ 0.000000] Detected VIPT I-cache on CPU0
10318 11:46:38.727371 [ 0.000000] CPU features: detected: GIC system register CPU interface
10319 11:46:38.734375 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10320 11:46:38.740736 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10321 11:46:38.748323 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10322 11:46:38.757144 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10323 11:46:38.764266 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10324 11:46:38.767041 [ 0.000000] alternatives: applying boot alternatives
10325 11:46:38.774154 [ 0.000000] Fallback order for Node 0: 0
10326 11:46:38.780947 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10327 11:46:38.783704 [ 0.000000] Policy zone: Normal
10328 11:46:38.806744 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12074008/extract-nfsrootfs-s4qkpdjn,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10329 11:46:38.816750 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10330 11:46:38.826974 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10331 11:46:38.836570 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10332 11:46:38.843521 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10333 11:46:38.846704 <6>[ 0.000000] software IO TLB: area num 8.
10334 11:46:38.903118 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10335 11:46:39.052918 <6>[ 0.000000] Memory: 7952248K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400520K reserved, 32768K cma-reserved)
10336 11:46:39.059386 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10337 11:46:39.065888 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10338 11:46:39.069133 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10339 11:46:39.075323 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10340 11:46:39.082128 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10341 11:46:39.085697 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10342 11:46:39.095579 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10343 11:46:39.101699 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10344 11:46:39.108502 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10345 11:46:39.115105 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10346 11:46:39.117792 <6>[ 0.000000] GICv3: 608 SPIs implemented
10347 11:46:39.121548 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10348 11:46:39.127883 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10349 11:46:39.130929 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10350 11:46:39.137839 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10351 11:46:39.151518 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10352 11:46:39.164745 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10353 11:46:39.170634 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10354 11:46:39.179349 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10355 11:46:39.192556 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10356 11:46:39.199180 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10357 11:46:39.205809 <6>[ 0.009182] Console: colour dummy device 80x25
10358 11:46:39.215193 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10359 11:46:39.222186 <6>[ 0.024374] pid_max: default: 32768 minimum: 301
10360 11:46:39.225619 <6>[ 0.029246] LSM: Security Framework initializing
10361 11:46:39.232418 <6>[ 0.034204] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10362 11:46:39.241734 <6>[ 0.042018] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10363 11:46:39.251699 <6>[ 0.051423] cblist_init_generic: Setting adjustable number of callback queues.
10364 11:46:39.254911 <6>[ 0.058912] cblist_init_generic: Setting shift to 3 and lim to 1.
10365 11:46:39.264586 <6>[ 0.065290] cblist_init_generic: Setting adjustable number of callback queues.
10366 11:46:39.271714 <6>[ 0.072717] cblist_init_generic: Setting shift to 3 and lim to 1.
10367 11:46:39.275137 <6>[ 0.079146] rcu: Hierarchical SRCU implementation.
10368 11:46:39.281476 <6>[ 0.084192] rcu: Max phase no-delay instances is 1000.
10369 11:46:39.288033 <6>[ 0.091246] EFI services will not be available.
10370 11:46:39.291458 <6>[ 0.096185] smp: Bringing up secondary CPUs ...
10371 11:46:39.299864 <6>[ 0.101230] Detected VIPT I-cache on CPU1
10372 11:46:39.306361 <6>[ 0.101301] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10373 11:46:39.313411 <6>[ 0.101332] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10374 11:46:39.316444 <6>[ 0.101671] Detected VIPT I-cache on CPU2
10375 11:46:39.326167 <6>[ 0.101722] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10376 11:46:39.332395 <6>[ 0.101740] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10377 11:46:39.335898 <6>[ 0.101998] Detected VIPT I-cache on CPU3
10378 11:46:39.342724 <6>[ 0.102043] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10379 11:46:39.349173 <6>[ 0.102057] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10380 11:46:39.355689 <6>[ 0.102362] CPU features: detected: Spectre-v4
10381 11:46:39.359078 <6>[ 0.102368] CPU features: detected: Spectre-BHB
10382 11:46:39.362540 <6>[ 0.102373] Detected PIPT I-cache on CPU4
10383 11:46:39.369035 <6>[ 0.102430] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10384 11:46:39.378750 <6>[ 0.102446] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10385 11:46:39.382413 <6>[ 0.102740] Detected PIPT I-cache on CPU5
10386 11:46:39.388916 <6>[ 0.102802] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10387 11:46:39.395246 <6>[ 0.102818] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10388 11:46:39.398292 <6>[ 0.103098] Detected PIPT I-cache on CPU6
10389 11:46:39.408492 <6>[ 0.103161] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10390 11:46:39.414850 <6>[ 0.103178] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10391 11:46:39.417948 <6>[ 0.103472] Detected PIPT I-cache on CPU7
10392 11:46:39.424604 <6>[ 0.103536] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10393 11:46:39.431140 <6>[ 0.103553] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10394 11:46:39.435439 <6>[ 0.103599] smp: Brought up 1 node, 8 CPUs
10395 11:46:39.441644 <6>[ 0.244979] SMP: Total of 8 processors activated.
10396 11:46:39.447556 <6>[ 0.249900] CPU features: detected: 32-bit EL0 Support
10397 11:46:39.454461 <6>[ 0.255296] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10398 11:46:39.461293 <6>[ 0.264096] CPU features: detected: Common not Private translations
10399 11:46:39.467575 <6>[ 0.270572] CPU features: detected: CRC32 instructions
10400 11:46:39.474056 <6>[ 0.275923] CPU features: detected: RCpc load-acquire (LDAPR)
10401 11:46:39.477228 <6>[ 0.281920] CPU features: detected: LSE atomic instructions
10402 11:46:39.484180 <6>[ 0.287701] CPU features: detected: Privileged Access Never
10403 11:46:39.491207 <6>[ 0.293516] CPU features: detected: RAS Extension Support
10404 11:46:39.497199 <6>[ 0.299125] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10405 11:46:39.500284 <6>[ 0.306345] CPU: All CPU(s) started at EL2
10406 11:46:39.507004 <6>[ 0.310688] alternatives: applying system-wide alternatives
10407 11:46:39.517422 <6>[ 0.321385] devtmpfs: initialized
10408 11:46:39.533393 <6>[ 0.330283] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10409 11:46:39.539490 <6>[ 0.340241] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10410 11:46:39.546381 <6>[ 0.348444] pinctrl core: initialized pinctrl subsystem
10411 11:46:39.549271 <6>[ 0.355116] DMI not present or invalid.
10412 11:46:39.556149 <6>[ 0.359538] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10413 11:46:39.566354 <6>[ 0.366435] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10414 11:46:39.572363 <6>[ 0.374019] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10415 11:46:39.582692 <6>[ 0.382248] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10416 11:46:39.586051 <6>[ 0.390499] audit: initializing netlink subsys (disabled)
10417 11:46:39.595875 <5>[ 0.396199] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10418 11:46:39.602623 <6>[ 0.396919] thermal_sys: Registered thermal governor 'step_wise'
10419 11:46:39.609127 <6>[ 0.404166] thermal_sys: Registered thermal governor 'power_allocator'
10420 11:46:39.611855 <6>[ 0.410422] cpuidle: using governor menu
10421 11:46:39.619283 <6>[ 0.421386] NET: Registered PF_QIPCRTR protocol family
10422 11:46:39.625630 <6>[ 0.426924] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10423 11:46:39.632121 <6>[ 0.434029] ASID allocator initialised with 32768 entries
10424 11:46:39.634811 <6>[ 0.440610] Serial: AMBA PL011 UART driver
10425 11:46:39.645595 <4>[ 0.449449] Trying to register duplicate clock ID: 134
10426 11:46:39.700155 <6>[ 0.507032] KASLR enabled
10427 11:46:39.714648 <6>[ 0.514686] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10428 11:46:39.721319 <6>[ 0.521703] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10429 11:46:39.727799 <6>[ 0.528192] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10430 11:46:39.734734 <6>[ 0.535199] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10431 11:46:39.741092 <6>[ 0.541688] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10432 11:46:39.747394 <6>[ 0.548691] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10433 11:46:39.753687 <6>[ 0.555178] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10434 11:46:39.760865 <6>[ 0.562185] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10435 11:46:39.763738 <6>[ 0.569683] ACPI: Interpreter disabled.
10436 11:46:39.772025 <6>[ 0.576087] iommu: Default domain type: Translated
10437 11:46:39.779182 <6>[ 0.581200] iommu: DMA domain TLB invalidation policy: strict mode
10438 11:46:39.782241 <5>[ 0.587859] SCSI subsystem initialized
10439 11:46:39.788983 <6>[ 0.592025] usbcore: registered new interface driver usbfs
10440 11:46:39.795151 <6>[ 0.597758] usbcore: registered new interface driver hub
10441 11:46:39.798637 <6>[ 0.603306] usbcore: registered new device driver usb
10442 11:46:39.805692 <6>[ 0.609413] pps_core: LinuxPPS API ver. 1 registered
10443 11:46:39.816105 <6>[ 0.614608] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10444 11:46:39.818831 <6>[ 0.623956] PTP clock support registered
10445 11:46:39.822144 <6>[ 0.628201] EDAC MC: Ver: 3.0.0
10446 11:46:39.829867 <6>[ 0.633344] FPGA manager framework
10447 11:46:39.836366 <6>[ 0.637022] Advanced Linux Sound Architecture Driver Initialized.
10448 11:46:39.839507 <6>[ 0.643786] vgaarb: loaded
10449 11:46:39.846236 <6>[ 0.646964] clocksource: Switched to clocksource arch_sys_counter
10450 11:46:39.849995 <5>[ 0.653396] VFS: Disk quotas dquot_6.6.0
10451 11:46:39.855821 <6>[ 0.657581] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10452 11:46:39.859154 <6>[ 0.664769] pnp: PnP ACPI: disabled
10453 11:46:39.867659 <6>[ 0.671398] NET: Registered PF_INET protocol family
10454 11:46:39.877760 <6>[ 0.676978] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10455 11:46:39.889295 <6>[ 0.689263] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10456 11:46:39.898877 <6>[ 0.698076] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10457 11:46:39.905035 <6>[ 0.706046] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10458 11:46:39.914988 <6>[ 0.714747] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10459 11:46:39.921868 <6>[ 0.724493] TCP: Hash tables configured (established 65536 bind 65536)
10460 11:46:39.928535 <6>[ 0.731351] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10461 11:46:39.938329 <6>[ 0.738548] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10462 11:46:39.945170 <6>[ 0.746248] NET: Registered PF_UNIX/PF_LOCAL protocol family
10463 11:46:39.951902 <6>[ 0.752424] RPC: Registered named UNIX socket transport module.
10464 11:46:39.954830 <6>[ 0.758578] RPC: Registered udp transport module.
10465 11:46:39.961518 <6>[ 0.763512] RPC: Registered tcp transport module.
10466 11:46:39.967796 <6>[ 0.768445] RPC: Registered tcp NFSv4.1 backchannel transport module.
10467 11:46:39.971700 <6>[ 0.775112] PCI: CLS 0 bytes, default 64
10468 11:46:39.974416 <6>[ 0.779506] Unpacking initramfs...
10469 11:46:39.998911 <6>[ 0.799088] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10470 11:46:40.008245 <6>[ 0.807733] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10471 11:46:40.012216 <6>[ 0.816509] kvm [1]: IPA Size Limit: 40 bits
10472 11:46:40.018418 <6>[ 0.821034] kvm [1]: GICv3: no GICV resource entry
10473 11:46:40.022033 <6>[ 0.826057] kvm [1]: disabling GICv2 emulation
10474 11:46:40.028417 <6>[ 0.830746] kvm [1]: GIC system register CPU interface enabled
10475 11:46:40.032165 <6>[ 0.836912] kvm [1]: vgic interrupt IRQ18
10476 11:46:40.038683 <6>[ 0.841271] kvm [1]: VHE mode initialized successfully
10477 11:46:40.044617 <5>[ 0.847776] Initialise system trusted keyrings
10478 11:46:40.051761 <6>[ 0.852641] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10479 11:46:40.059339 <6>[ 0.862647] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10480 11:46:40.065720 <5>[ 0.869053] NFS: Registering the id_resolver key type
10481 11:46:40.068912 <5>[ 0.874355] Key type id_resolver registered
10482 11:46:40.075987 <5>[ 0.878769] Key type id_legacy registered
10483 11:46:40.082145 <6>[ 0.883044] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10484 11:46:40.088374 <6>[ 0.889966] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10485 11:46:40.095129 <6>[ 0.897691] 9p: Installing v9fs 9p2000 file system support
10486 11:46:40.132705 <5>[ 0.936404] Key type asymmetric registered
10487 11:46:40.135598 <5>[ 0.940736] Asymmetric key parser 'x509' registered
10488 11:46:40.146298 <6>[ 0.945939] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10489 11:46:40.149708 <6>[ 0.953559] io scheduler mq-deadline registered
10490 11:46:40.152530 <6>[ 0.958327] io scheduler kyber registered
10491 11:46:40.172079 <6>[ 0.975399] EINJ: ACPI disabled.
10492 11:46:40.204852 <4>[ 1.000880] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10493 11:46:40.213962 <4>[ 1.011502] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10494 11:46:40.228406 <6>[ 1.032319] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10495 11:46:40.237093 <6>[ 1.040458] printk: console [ttyS0] disabled
10496 11:46:40.265201 <6>[ 1.065105] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10497 11:46:40.272024 <6>[ 1.074581] printk: console [ttyS0] enabled
10498 11:46:40.274660 <6>[ 1.074581] printk: console [ttyS0] enabled
10499 11:46:40.282050 <6>[ 1.083473] printk: bootconsole [mtk8250] disabled
10500 11:46:40.284992 <6>[ 1.083473] printk: bootconsole [mtk8250] disabled
10501 11:46:40.291636 <6>[ 1.094765] SuperH (H)SCI(F) driver initialized
10502 11:46:40.294994 <6>[ 1.100045] msm_serial: driver initialized
10503 11:46:40.308701 <6>[ 1.109121] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10504 11:46:40.319146 <6>[ 1.117669] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10505 11:46:40.325722 <6>[ 1.126212] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10506 11:46:40.336255 <6>[ 1.134840] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10507 11:46:40.344952 <6>[ 1.143547] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10508 11:46:40.351408 <6>[ 1.152271] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10509 11:46:40.361295 <6>[ 1.160816] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10510 11:46:40.368721 <6>[ 1.169625] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10511 11:46:40.377865 <6>[ 1.178168] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10512 11:46:40.390812 <6>[ 1.193947] loop: module loaded
10513 11:46:40.396581 <6>[ 1.199901] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10514 11:46:40.419428 <4>[ 1.223230] mtk-pmic-keys: Failed to locate of_node [id: -1]
10515 11:46:40.426372 <6>[ 1.230122] megasas: 07.719.03.00-rc1
10516 11:46:40.435710 <6>[ 1.239698] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10517 11:46:40.442942 <6>[ 1.246360] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10518 11:46:40.459689 <6>[ 1.262940] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10519 11:46:40.515607 <6>[ 1.312691] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10520 11:46:40.717599 <6>[ 1.521221] Freeing initrd memory: 17368K
10521 11:46:40.727651 <6>[ 1.531752] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10522 11:46:40.738899 <6>[ 1.542514] tun: Universal TUN/TAP device driver, 1.6
10523 11:46:40.742643 <6>[ 1.548568] thunder_xcv, ver 1.0
10524 11:46:40.745514 <6>[ 1.552071] thunder_bgx, ver 1.0
10525 11:46:40.748494 <6>[ 1.555565] nicpf, ver 1.0
10526 11:46:40.759502 <6>[ 1.559580] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10527 11:46:40.762743 <6>[ 1.567056] hns3: Copyright (c) 2017 Huawei Corporation.
10528 11:46:40.766732 <6>[ 1.572642] hclge is initializing
10529 11:46:40.772428 <6>[ 1.576218] e1000: Intel(R) PRO/1000 Network Driver
10530 11:46:40.779045 <6>[ 1.581348] e1000: Copyright (c) 1999-2006 Intel Corporation.
10531 11:46:40.782422 <6>[ 1.587360] e1000e: Intel(R) PRO/1000 Network Driver
10532 11:46:40.789057 <6>[ 1.592576] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10533 11:46:40.795764 <6>[ 1.598763] igb: Intel(R) Gigabit Ethernet Network Driver
10534 11:46:40.802329 <6>[ 1.604413] igb: Copyright (c) 2007-2014 Intel Corporation.
10535 11:46:40.809153 <6>[ 1.610249] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10536 11:46:40.815685 <6>[ 1.616766] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10537 11:46:40.818849 <6>[ 1.623231] sky2: driver version 1.30
10538 11:46:40.825433 <6>[ 1.628228] VFIO - User Level meta-driver version: 0.3
10539 11:46:40.833394 <6>[ 1.636502] usbcore: registered new interface driver usb-storage
10540 11:46:40.839005 <6>[ 1.642945] usbcore: registered new device driver onboard-usb-hub
10541 11:46:40.849063 <6>[ 1.652126] mt6397-rtc mt6359-rtc: registered as rtc0
10542 11:46:40.858228 <6>[ 1.657594] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T11:46:41 UTC (1700826401)
10543 11:46:40.861480 <6>[ 1.667168] i2c_dev: i2c /dev entries driver
10544 11:46:40.878839 <6>[ 1.678855] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10545 11:46:40.899010 <6>[ 1.702851] cpu cpu0: EM: created perf domain
10546 11:46:40.902039 <6>[ 1.707771] cpu cpu4: EM: created perf domain
10547 11:46:40.909755 <6>[ 1.713362] sdhci: Secure Digital Host Controller Interface driver
10548 11:46:40.916054 <6>[ 1.719795] sdhci: Copyright(c) Pierre Ossman
10549 11:46:40.922973 <6>[ 1.724750] Synopsys Designware Multimedia Card Interface Driver
10550 11:46:40.929187 <6>[ 1.731389] sdhci-pltfm: SDHCI platform and OF driver helper
10551 11:46:40.933168 <6>[ 1.731487] mmc0: CQHCI version 5.10
10552 11:46:40.939600 <6>[ 1.741443] ledtrig-cpu: registered to indicate activity on CPUs
10553 11:46:40.946030 <6>[ 1.748453] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10554 11:46:40.953195 <6>[ 1.755506] usbcore: registered new interface driver usbhid
10555 11:46:40.956158 <6>[ 1.761330] usbhid: USB HID core driver
10556 11:46:40.962978 <6>[ 1.765531] spi_master spi0: will run message pump with realtime priority
10557 11:46:41.006572 <6>[ 1.803766] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10558 11:46:41.026043 <6>[ 1.819789] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10559 11:46:41.029308 <6>[ 1.835006] mmc0: Command Queue Engine enabled
10560 11:46:41.036174 <6>[ 1.839773] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10561 11:46:41.042550 <6>[ 1.846491] cros-ec-spi spi0.0: Chrome EC device registered
10562 11:46:41.049629 <6>[ 1.847014] mmcblk0: mmc0:0001 DA4128 116 GiB
10563 11:46:41.057620 <6>[ 1.861415] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10564 11:46:41.065480 <6>[ 1.869329] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10565 11:46:41.072563 <6>[ 1.875477] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10566 11:46:41.079110 <6>[ 1.881399] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10567 11:46:41.094977 <6>[ 1.895749] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10568 11:46:41.103411 <6>[ 1.906403] NET: Registered PF_PACKET protocol family
10569 11:46:41.105781 <6>[ 1.911798] 9pnet: Installing 9P2000 support
10570 11:46:41.112321 <5>[ 1.916352] Key type dns_resolver registered
10571 11:46:41.115612 <6>[ 1.921352] registered taskstats version 1
10572 11:46:41.122361 <5>[ 1.925732] Loading compiled-in X.509 certificates
10573 11:46:41.154859 <4>[ 1.951947] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 11:46:41.164969 <4>[ 1.962731] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10575 11:46:41.171369 <3>[ 1.973284] debugfs: File 'uA_load' in directory '/' already present!
10576 11:46:41.177584 <3>[ 1.980001] debugfs: File 'min_uV' in directory '/' already present!
10577 11:46:41.184417 <3>[ 1.986611] debugfs: File 'max_uV' in directory '/' already present!
10578 11:46:41.190986 <3>[ 1.993225] debugfs: File 'constraint_flags' in directory '/' already present!
10579 11:46:41.202720 <3>[ 2.003368] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10580 11:46:41.215526 <6>[ 2.019761] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10581 11:46:41.222391 <6>[ 2.026586] xhci-mtk 11200000.usb: xHCI Host Controller
10582 11:46:41.229411 <6>[ 2.032099] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10583 11:46:41.239343 <6>[ 2.039944] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10584 11:46:41.246186 <6>[ 2.049422] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10585 11:46:41.252741 <6>[ 2.055633] xhci-mtk 11200000.usb: xHCI Host Controller
10586 11:46:41.259084 <6>[ 2.061131] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10587 11:46:41.265627 <6>[ 2.068793] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10588 11:46:41.272658 <6>[ 2.076671] hub 1-0:1.0: USB hub found
10589 11:46:41.276156 <6>[ 2.080698] hub 1-0:1.0: 1 port detected
10590 11:46:41.286281 <6>[ 2.084992] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10591 11:46:41.288991 <6>[ 2.093795] hub 2-0:1.0: USB hub found
10592 11:46:41.292609 <6>[ 2.097822] hub 2-0:1.0: 1 port detected
10593 11:46:41.303126 <6>[ 2.106259] mtk-msdc 11f70000.mmc: Got CD GPIO
10594 11:46:41.313594 <6>[ 2.114217] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10595 11:46:41.320345 <6>[ 2.122256] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10596 11:46:41.330320 <4>[ 2.130193] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10597 11:46:41.340012 <6>[ 2.139771] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10598 11:46:41.346987 <6>[ 2.147847] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10599 11:46:41.353763 <6>[ 2.155870] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10600 11:46:41.363330 <6>[ 2.163787] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10601 11:46:41.370164 <6>[ 2.171604] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10602 11:46:41.380247 <6>[ 2.179424] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10603 11:46:41.390419 <6>[ 2.189835] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10604 11:46:41.397067 <6>[ 2.198199] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10605 11:46:41.406367 <6>[ 2.206547] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10606 11:46:41.413297 <6>[ 2.214886] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10607 11:46:41.423151 <6>[ 2.223225] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10608 11:46:41.429297 <6>[ 2.231566] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10609 11:46:41.439550 <6>[ 2.239906] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10610 11:46:41.445862 <6>[ 2.248248] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10611 11:46:41.455715 <6>[ 2.256593] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10612 11:46:41.465590 <6>[ 2.264933] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10613 11:46:41.472561 <6>[ 2.273272] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10614 11:46:41.482688 <6>[ 2.281610] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10615 11:46:41.489246 <6>[ 2.289952] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10616 11:46:41.498768 <6>[ 2.298294] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10617 11:46:41.505549 <6>[ 2.306633] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10618 11:46:41.511950 <6>[ 2.315361] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10619 11:46:41.518911 <6>[ 2.322512] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10620 11:46:41.525468 <6>[ 2.329267] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10621 11:46:41.535823 <6>[ 2.336011] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10622 11:46:41.541901 <6>[ 2.342939] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10623 11:46:41.548499 <6>[ 2.349776] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10624 11:46:41.558435 <6>[ 2.358903] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10625 11:46:41.568437 <6>[ 2.368022] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10626 11:46:41.578852 <6>[ 2.377317] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10627 11:46:41.588202 <6>[ 2.386788] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10628 11:46:41.598399 <6>[ 2.396259] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10629 11:46:41.604943 <6>[ 2.405380] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10630 11:46:41.615040 <6>[ 2.414847] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10631 11:46:41.624173 <6>[ 2.423966] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10632 11:46:41.634390 <6>[ 2.433268] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10633 11:46:41.643997 <6>[ 2.443428] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10634 11:46:41.655061 <6>[ 2.455375] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10635 11:46:41.661532 <6>[ 2.465077] Trying to probe devices needed for running init ...
10636 11:46:41.706876 <6>[ 2.507215] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10637 11:46:41.861441 <6>[ 2.665105] hub 1-1:1.0: USB hub found
10638 11:46:41.864601 <6>[ 2.669628] hub 1-1:1.0: 4 ports detected
10639 11:46:41.873915 <6>[ 2.677707] hub 1-1:1.0: USB hub found
10640 11:46:41.877326 <6>[ 2.682049] hub 1-1:1.0: 4 ports detected
10641 11:46:41.986781 <6>[ 2.787559] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10642 11:46:42.013324 <6>[ 2.816999] hub 2-1:1.0: USB hub found
10643 11:46:42.016725 <6>[ 2.821499] hub 2-1:1.0: 3 ports detected
10644 11:46:42.025610 <6>[ 2.829637] hub 2-1:1.0: USB hub found
10645 11:46:42.029840 <6>[ 2.834088] hub 2-1:1.0: 3 ports detected
10646 11:46:42.203100 <6>[ 3.003277] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10647 11:46:42.335480 <6>[ 3.139113] hub 1-1.4:1.0: USB hub found
10648 11:46:42.338516 <6>[ 3.143771] hub 1-1.4:1.0: 2 ports detected
10649 11:46:42.348163 <6>[ 3.152481] hub 1-1.4:1.0: USB hub found
10650 11:46:42.351530 <6>[ 3.157106] hub 1-1.4:1.0: 2 ports detected
10651 11:46:42.419056 <6>[ 3.219487] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10652 11:46:42.650312 <6>[ 3.451276] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10653 11:46:42.842513 <6>[ 3.643279] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10654 11:46:53.960087 <6>[ 14.768239] ALSA device list:
10655 11:46:53.966495 <6>[ 14.771528] No soundcards found.
10656 11:46:53.974014 <6>[ 14.779494] Freeing unused kernel memory: 8384K
10657 11:46:53.978043 <6>[ 14.784477] Run /init as init process
10658 11:46:53.988798 Loading, please wait...
10659 11:46:54.010274 Starting version 247.3-7+deb11u2
10660 11:46:54.240785 <6>[ 15.042436] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10661 11:46:54.254097 <3>[ 15.056005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 11:46:54.261183 <6>[ 15.056522] remoteproc remoteproc0: scp is available
10663 11:46:54.267155 <6>[ 15.062356] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10664 11:46:54.273536 <3>[ 15.064237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 11:46:54.284505 <4>[ 15.065007] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10666 11:46:54.290697 <4>[ 15.065139] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10667 11:46:54.294750 <6>[ 15.069755] remoteproc remoteproc0: powering up scp
10668 11:46:54.301697 <3>[ 15.077649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 11:46:54.311371 <4>[ 15.084761] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10670 11:46:54.315110 <4>[ 15.084761] Fallback method does not support PEC.
10671 11:46:54.325538 <6>[ 15.085689] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10672 11:46:54.331571 <3>[ 15.097511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 11:46:54.338642 <6>[ 15.099830] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10674 11:46:54.348582 <3>[ 15.101761] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10675 11:46:54.355123 <3>[ 15.104966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 11:46:54.361752 <6>[ 15.111159] mc: Linux media interface: v0.10
10677 11:46:54.367821 <6>[ 15.114931] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10678 11:46:54.377877 <3>[ 15.125304] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10679 11:46:54.384678 <3>[ 15.126683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 11:46:54.391411 <3>[ 15.126693] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 11:46:54.401332 <3>[ 15.126697] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 11:46:54.407290 <3>[ 15.126792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 11:46:54.414430 <6>[ 15.132910] usbcore: registered new interface driver r8152
10684 11:46:54.424199 <6>[ 15.135263] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10685 11:46:54.430849 <3>[ 15.143331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 11:46:54.437180 <6>[ 15.145574] videodev: Linux video capture interface: v2.00
10687 11:46:54.447888 <6>[ 15.148937] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10688 11:46:54.453399 <3>[ 15.157699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 11:46:54.463465 <6>[ 15.170068] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10690 11:46:54.470111 <3>[ 15.170296] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 11:46:54.476720 <6>[ 15.215495] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10692 11:46:54.486673 <3>[ 15.218973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 11:46:54.493157 <6>[ 15.238829] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10694 11:46:54.503589 <6>[ 15.238867] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10695 11:46:54.510144 <6>[ 15.238874] remoteproc remoteproc0: remote processor scp is now up
10696 11:46:54.516701 <3>[ 15.241422] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 11:46:54.523553 <3>[ 15.241427] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 11:46:54.533056 <3>[ 15.241430] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 11:46:54.539831 <3>[ 15.241433] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 11:46:54.549922 <3>[ 15.241463] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 11:46:54.559139 <4>[ 15.250898] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10702 11:46:54.569119 <6>[ 15.263446] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10703 11:46:54.576228 <4>[ 15.264129] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10704 11:46:54.585995 <6>[ 15.273638] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10705 11:46:54.592725 <6>[ 15.284476] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10706 11:46:54.598640 <6>[ 15.306707] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10707 11:46:54.605959 <6>[ 15.312329] pci_bus 0000:00: root bus resource [bus 00-ff]
10708 11:46:54.612398 <6>[ 15.313754] usbcore: registered new interface driver cdc_ether
10709 11:46:54.618856 <6>[ 15.320221] usbcore: registered new interface driver r8153_ecm
10710 11:46:54.625352 <6>[ 15.323301] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10711 11:46:54.632446 <6>[ 15.326899] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10712 11:46:54.642885 <6>[ 15.326906] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10713 11:46:54.648867 <6>[ 15.326981] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10714 11:46:54.652061 <6>[ 15.327670] Bluetooth: Core ver 2.22
10715 11:46:54.659386 <6>[ 15.327758] NET: Registered PF_BLUETOOTH protocol family
10716 11:46:54.665101 <6>[ 15.327761] Bluetooth: HCI device and connection manager initialized
10717 11:46:54.672021 <6>[ 15.327780] Bluetooth: HCI socket layer initialized
10718 11:46:54.674727 <6>[ 15.327785] Bluetooth: L2CAP socket layer initialized
10719 11:46:54.681998 <6>[ 15.327797] Bluetooth: SCO socket layer initialized
10720 11:46:54.685133 <6>[ 15.347077] r8152 2-1.3:1.0 eth0: v1.12.13
10721 11:46:54.691418 <6>[ 15.351307] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10722 11:46:54.701395 <6>[ 15.352790] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10723 11:46:54.710985 <6>[ 15.354008] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10724 11:46:54.717790 <6>[ 15.354120] usbcore: registered new interface driver uvcvideo
10725 11:46:54.724287 <6>[ 15.366123] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10726 11:46:54.728665 <6>[ 15.368993] pci 0000:00:00.0: supports D1 D2
10727 11:46:54.734376 <6>[ 15.379500] usbcore: registered new interface driver btusb
10728 11:46:54.744427 <4>[ 15.380080] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10729 11:46:54.751231 <3>[ 15.380088] Bluetooth: hci0: Failed to load firmware file (-2)
10730 11:46:54.757832 <3>[ 15.380091] Bluetooth: hci0: Failed to set up firmware (-2)
10731 11:46:54.767264 <4>[ 15.380094] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10732 11:46:54.774300 <6>[ 15.386584] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10733 11:46:54.780915 <6>[ 15.387164] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10734 11:46:54.790361 <6>[ 15.592330] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10735 11:46:54.796874 <6>[ 15.600697] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10736 11:46:54.804539 <6>[ 15.607006] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10737 11:46:54.810471 <6>[ 15.614491] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10738 11:46:54.820286 <6>[ 15.621973] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10739 11:46:54.823696 <6>[ 15.629546] pci 0000:01:00.0: supports D1 D2
10740 11:46:54.830108 <6>[ 15.634064] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10741 11:46:54.849528 <6>[ 15.651185] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10742 11:46:54.855776 <6>[ 15.658089] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10743 11:46:54.862513 <6>[ 15.666177] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10744 11:46:54.872257 <6>[ 15.674175] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10745 11:46:54.879294 <6>[ 15.682177] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10746 11:46:54.889025 <6>[ 15.690177] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10747 11:46:54.892007 <6>[ 15.698177] pci 0000:00:00.0: PCI bridge to [bus 01]
10748 11:46:54.901726 <6>[ 15.703394] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10749 11:46:54.908810 <6>[ 15.711523] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10750 11:46:54.915253 <6>[ 15.718456] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10751 11:46:54.921742 <6>[ 15.725227] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10752 11:46:54.944669 <5>[ 15.746048] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10753 11:46:54.963896 <5>[ 15.765756] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10754 11:46:54.970579 <4>[ 15.772784] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10755 11:46:54.976693 <6>[ 15.781699] cfg80211: failed to load regulatory.db
10756 11:46:55.030712 <6>[ 15.832843] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10757 11:46:55.037622 <6>[ 15.840392] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10758 11:46:55.061716 <6>[ 15.867217] mt7921e 0000:01:00.0: ASIC revision: 79610010
10759 11:46:55.168015 <4>[ 15.967123] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10760 11:46:55.172049 Begin: Loading essential drivers ... done.
10761 11:46:55.178456 Begin: Running /scripts/init-premount ... done.
10762 11:46:55.184757 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10763 11:46:55.191406 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10764 11:46:55.198400 Device /sys/class/net/enx002432307c7b found
10765 11:46:55.198912 done.
10766 11:46:55.260943 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10767 11:46:55.296766 <4>[ 16.095404] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10768 11:46:55.416441 <4>[ 16.214999] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10769 11:46:55.536400 <4>[ 16.334875] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10770 11:46:55.656367 <4>[ 16.454932] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 11:46:55.775777 <4>[ 16.574676] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 11:46:55.896149 <4>[ 16.694909] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 11:46:56.015918 <4>[ 16.814833] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 11:46:56.127769 <4>[ 16.926812] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 11:46:56.185862 <6>[ 16.991282] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10776 11:46:56.247725 <4>[ 17.046787] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 11:46:56.351789 IP-Config: no response after 2 secs - giving up
10778 11:46:56.360041 <3>[ 17.165003] mt7921e 0000:01:00.0: hardware init failed
10779 11:46:56.392897 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10780 11:46:56.400121 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10781 11:46:56.406204 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10782 11:46:56.412819 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10783 11:46:56.419936 host : mt8192-asurada-spherion-r0-cbg-2
10784 11:46:56.425743 domain : lava-rack
10785 11:46:56.428938 rootserver: 192.168.201.1 rootpath:
10786 11:46:56.429358 filename :
10787 11:46:56.526349 done.
10788 11:46:56.534317 Begin: Running /scripts/nfs-bottom ... done.
10789 11:46:56.549453 Begin: Running /scripts/init-bottom ... done.
10790 11:46:57.817665 <6>[ 18.623300] NET: Registered PF_INET6 protocol family
10791 11:46:57.824577 <6>[ 18.630443] Segment Routing with IPv6
10792 11:46:57.827666 <6>[ 18.634406] In-situ OAM (IOAM) with IPv6
10793 11:46:57.964003 <30>[ 18.750045] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10794 11:46:57.970655 <30>[ 18.774472] systemd[1]: Detected architecture arm64.
10795 11:46:57.992540
10796 11:46:57.995729 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10797 11:46:57.996259
10798 11:46:58.012824 <30>[ 18.818449] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10799 11:46:59.000609 <30>[ 19.803551] systemd[1]: Queued start job for default target Graphical Interface.
10800 11:46:59.019845 <30>[ 19.825627] systemd[1]: Created slice system-getty.slice.
10801 11:46:59.026802 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10802 11:46:59.042960 <30>[ 19.848617] systemd[1]: Created slice system-modprobe.slice.
10803 11:46:59.049292 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10804 11:46:59.067095 <30>[ 19.872532] systemd[1]: Created slice system-serial\x2dgetty.slice.
10805 11:46:59.076640 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10806 11:46:59.090411 <30>[ 19.896291] systemd[1]: Created slice User and Session Slice.
10807 11:46:59.097126 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10808 11:46:59.117726 <30>[ 19.920116] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10809 11:46:59.127868 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10810 11:46:59.145761 <30>[ 19.948019] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10811 11:46:59.151946 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10812 11:46:59.176147 <30>[ 19.975411] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10813 11:46:59.182757 <30>[ 19.987576] systemd[1]: Reached target Local Encrypted Volumes.
10814 11:46:59.189635 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10815 11:46:59.206022 <30>[ 20.011808] systemd[1]: Reached target Paths.
10816 11:46:59.212470 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10817 11:46:59.225539 <30>[ 20.031241] systemd[1]: Reached target Remote File Systems.
10818 11:46:59.231751 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10819 11:46:59.249459 <30>[ 20.055242] systemd[1]: Reached target Slices.
10820 11:46:59.256156 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10821 11:46:59.273926 <30>[ 20.079335] systemd[1]: Reached target Swap.
10822 11:46:59.276893 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10823 11:46:59.301633 <30>[ 20.103791] systemd[1]: Listening on initctl Compatibility Named Pipe.
10824 11:46:59.307834 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10825 11:46:59.314515 <30>[ 20.120156] systemd[1]: Listening on Journal Audit Socket.
10826 11:46:59.320901 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10827 11:46:59.339032 <30>[ 20.144857] systemd[1]: Listening on Journal Socket (/dev/log).
10828 11:46:59.345679 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10829 11:46:59.362347 <30>[ 20.167820] systemd[1]: Listening on Journal Socket.
10830 11:46:59.368830 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10831 11:46:59.386176 <30>[ 20.188978] systemd[1]: Listening on Network Service Netlink Socket.
10832 11:46:59.393577 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10833 11:46:59.409107 <30>[ 20.214804] systemd[1]: Listening on udev Control Socket.
10834 11:46:59.415237 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10835 11:46:59.429636 <30>[ 20.235689] systemd[1]: Listening on udev Kernel Socket.
10836 11:46:59.436201 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10837 11:46:59.489753 <30>[ 20.295465] systemd[1]: Mounting Huge Pages File System...
10838 11:46:59.495942 Mounting [0;1;39mHuge Pages File System[0m...
10839 11:46:59.514134 <30>[ 20.319643] systemd[1]: Mounting POSIX Message Queue File System...
10840 11:46:59.520682 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10841 11:46:59.558018 <30>[ 20.363459] systemd[1]: Mounting Kernel Debug File System...
10842 11:46:59.563649 Mounting [0;1;39mKernel Debug File System[0m...
10843 11:46:59.580627 <30>[ 20.383625] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10844 11:46:59.596362 <30>[ 20.398671] systemd[1]: Starting Create list of static device nodes for the current kernel...
10845 11:46:59.606326 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10846 11:46:59.624769 <30>[ 20.430724] systemd[1]: Starting Load Kernel Module configfs...
10847 11:46:59.630865 Starting [0;1;39mLoad Kernel Module configfs[0m...
10848 11:46:59.649951 <30>[ 20.455917] systemd[1]: Starting Load Kernel Module drm...
10849 11:46:59.656420 Starting [0;1;39mLoad Kernel Module drm[0m...
10850 11:46:59.673771 <30>[ 20.480053] systemd[1]: Starting Load Kernel Module fuse...
10851 11:46:59.680850 Starting [0;1;39mLoad Kernel Module fuse[0m...
10852 11:46:59.702690 <30>[ 20.505638] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10853 11:46:59.720450 <6>[ 20.525978] fuse: init (API version 7.37)
10854 11:46:59.750351 <30>[ 20.556152] systemd[1]: Starting Journal Service...
10855 11:46:59.757121 Starting [0;1;39mJournal Service[0m...
10856 11:46:59.782521 <30>[ 20.588434] systemd[1]: Starting Load Kernel Modules...
10857 11:46:59.788733 Starting [0;1;39mLoad Kernel Modules[0m...
10858 11:46:59.808147 <30>[ 20.609943] systemd[1]: Starting Remount Root and Kernel File Systems...
10859 11:46:59.813480 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10860 11:46:59.828696 <30>[ 20.634655] systemd[1]: Starting Coldplug All udev Devices...
10861 11:46:59.835035 Starting [0;1;39mColdplug All udev Devices[0m...
10862 11:46:59.852497 <30>[ 20.658603] systemd[1]: Mounted Huge Pages File System.
10863 11:46:59.859399 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10864 11:46:59.874299 <30>[ 20.679795] systemd[1]: Mounted POSIX Message Queue File System.
10865 11:46:59.880020 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10866 11:46:59.897905 <30>[ 20.703695] systemd[1]: Mounted Kernel Debug File System.
10867 11:46:59.904741 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10868 11:46:59.917452 <3>[ 20.720503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 11:46:59.927628 <30>[ 20.730249] systemd[1]: Finished Create list of static device nodes for the current kernel.
10870 11:46:59.938100 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10871 11:46:59.947685 <3>[ 20.750205] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 11:46:59.954832 <30>[ 20.759917] systemd[1]: modprobe@configfs.service: Succeeded.
10873 11:46:59.961314 <30>[ 20.766774] systemd[1]: Finished Load Kernel Module configfs.
10874 11:46:59.967703 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10875 11:46:59.982659 <30>[ 20.788020] systemd[1]: modprobe@drm.service: Succeeded.
10876 11:46:59.988529 <30>[ 20.794486] systemd[1]: Finished Load Kernel Module drm.
10877 11:47:00.002312 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m<3>[ 20.804995] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 11:47:00.002829 .
10879 11:47:00.022943 <30>[ 20.828463] systemd[1]: modprobe@fuse.service: Succeeded.
10880 11:47:00.030017 <30>[ 20.835602] systemd[1]: Finished Load Kernel Module fuse.
10881 11:47:00.037099 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10882 11:47:00.047188 <3>[ 20.848349] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 11:47:00.055614 <30>[ 20.861392] systemd[1]: Finished Load Kernel Modules.
10884 11:47:00.062089 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10885 11:47:00.076203 <3>[ 20.878718] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 11:47:00.086894 <30>[ 20.889862] systemd[1]: Finished Remount Root and Kernel File Systems.
10887 11:47:00.093991 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10888 11:47:00.106853 <3>[ 20.909539] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 11:47:00.140208 <3>[ 20.942891] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 11:47:00.156570 <30>[ 20.962396] systemd[1]: Mounting FUSE Control File System...
10891 11:47:00.164348 Mounting [0;1;39mFUSE Control File System[0m...
10892 11:47:00.173511 <3>[ 20.974479] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 11:47:00.184259 <30>[ 20.987267] systemd[1]: Mounting Kernel Configuration File System...
10894 11:47:00.187992 Mounting [0;1;39mKernel Configuration File System[0m...
10895 11:47:00.201462 <3>[ 21.004102] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 11:47:00.216482 <30>[ 21.019526] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10897 11:47:00.227314 <30>[ 21.028758] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10898 11:47:00.236869 <3>[ 21.037901] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 11:47:00.243626 <30>[ 21.041251] systemd[1]: Starting Load/Save Random Seed...
10900 11:47:00.246544 Starting [0;1;39mLoad/Save Random Seed[0m...
10901 11:47:00.265543 <30>[ 21.071296] systemd[1]: Starting Apply Kernel Variables...
10902 11:47:00.272301 Starting [0;1;39mApply Kernel Variables[0m...
10903 11:47:00.289487 <30>[ 21.095196] systemd[1]: Starting Create System Users...
10904 11:47:00.296454 Starting [0;1;39mCreate System Users[0m...
10905 11:47:00.311015 <30>[ 21.117436] systemd[1]: Started Journal Service.
10906 11:47:00.318196 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10907 11:47:00.340332 <4>[ 21.135373] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10908 11:47:00.349129 <3>[ 21.151341] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10909 11:47:00.355846 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10910 11:47:00.375700 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10911 11:47:00.389483 See 'systemctl status systemd-udev-trigger.service' for details.
10912 11:47:00.406448 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10913 11:47:00.423343 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10914 11:47:00.439253 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10915 11:47:00.455491 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10916 11:47:00.510831 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10917 11:47:00.529311 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10918 11:47:00.592190 <46>[ 21.395066] systemd-journald[288]: Received client request to flush runtime journal.
10919 11:47:01.088304 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10920 11:47:01.101122 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10921 11:47:01.116540 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10922 11:47:01.164586 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10923 11:47:01.990402 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10924 11:47:02.049663 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10925 11:47:02.095595 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10926 11:47:02.158437 Starting [0;1;39mNetwork Service[0m...
10927 11:47:02.464054 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10928 11:47:02.482709 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10929 11:47:02.528356 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10930 11:47:02.822420 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10931 11:47:02.840060 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10932 11:47:02.877367 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10933 11:47:02.893651 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10934 11:47:02.914346 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10935 11:47:02.929263 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10936 11:47:02.975383 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10937 11:47:03.013003 Starting [0;1;39mNetwork Name Resolution[0m...
10938 11:47:03.041739 Starting [0;1;39mNetwork Time Synchronization[0m...
10939 11:47:03.065058 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10940 11:47:03.146138 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10941 11:47:03.501858 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10942 11:47:03.517052 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10943 11:47:03.535959 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10944 11:47:03.548885 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10945 11:47:03.564721 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10946 11:47:03.614833 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10947 11:47:03.640047 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10948 11:47:03.684528 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10949 11:47:03.704466 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10950 11:47:03.717080 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10951 11:47:03.909376 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10952 11:47:03.920288 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10953 11:47:03.936811 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10954 11:47:03.997471 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10955 11:47:04.474018 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10956 11:47:04.851640 Starting [0;1;39mUser Login Management[0m...
10957 11:47:04.867539 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10958 11:47:04.889459 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10959 11:47:04.908095 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10960 11:47:04.970510 Starting [0;1;39mPermit User Sessions[0m...
10961 11:47:05.084052 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10962 11:47:05.107028 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10963 11:47:05.170220 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10964 11:47:05.187269 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10965 11:47:05.208724 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10966 11:47:05.227010 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10967 11:47:05.247604 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10968 11:47:05.266591 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10969 11:47:05.324753 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10970 11:47:05.368454 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10971 11:47:05.451339
10972 11:47:05.451499
10973 11:47:05.453941 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10974 11:47:05.454039
10975 11:47:05.457357 debian-bullseye-arm64 login: root (automatic login)
10976 11:47:05.457455
10977 11:47:05.457542
10978 11:47:05.826985 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 11:29:03 UTC 2023 aarch64
10979 11:47:05.827135
10980 11:47:05.833660 The programs included with the Debian GNU/Linux system are free software;
10981 11:47:05.840412 the exact distribution terms for each program are described in the
10982 11:47:05.843451 individual files in /usr/share/doc/*/copyright.
10983 11:47:05.843535
10984 11:47:05.850100 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10985 11:47:05.853236 permitted by applicable law.
10986 11:47:06.808631 Matched prompt #10: / #
10988 11:47:06.808916 Setting prompt string to ['/ #']
10989 11:47:06.809010 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10991 11:47:06.809204 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10992 11:47:06.809294 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
10993 11:47:06.809363 Setting prompt string to ['/ #']
10994 11:47:06.809422 Forcing a shell prompt, looking for ['/ #']
10996 11:47:06.859654 / #
10997 11:47:06.859823 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10998 11:47:06.859903 Waiting using forced prompt support (timeout 00:02:30)
10999 11:47:06.864977
11000 11:47:06.865261 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11001 11:47:06.865354 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11003 11:47:06.965739 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12074008/extract-nfsrootfs-s4qkpdjn'
11004 11:47:06.971179 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12074008/extract-nfsrootfs-s4qkpdjn'
11006 11:47:07.071788 / # export NFS_SERVER_IP='192.168.201.1'
11007 11:47:07.077186 export NFS_SERVER_IP='192.168.201.1'
11008 11:47:07.077558 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11009 11:47:07.077726 end: 2.2 depthcharge-retry (duration 00:01:47) [common]
11010 11:47:07.077880 end: 2 depthcharge-action (duration 00:01:47) [common]
11011 11:47:07.078037 start: 3 lava-test-retry (timeout 00:07:18) [common]
11012 11:47:07.078185 start: 3.1 lava-test-shell (timeout 00:07:18) [common]
11013 11:47:07.078321 Using namespace: common
11015 11:47:07.178742 / # #
11016 11:47:07.178901 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11017 11:47:07.184066 #
11018 11:47:07.184333 Using /lava-12074008
11020 11:47:07.284669 / # export SHELL=/bin/bash
11021 11:47:07.290197 export SHELL=/bin/bash
11023 11:47:07.390764 / # . /lava-12074008/environment
11024 11:47:07.396313 . /lava-12074008/environment
11026 11:47:07.502798 / # /lava-12074008/bin/lava-test-runner /lava-12074008/0
11027 11:47:07.502935 Test shell timeout: 10s (minimum of the action and connection timeout)
11028 11:47:07.508283 /lava-12074008/bin/lava-test-runner /lava-12074008/0
11029 11:47:07.828726 + export TESTRUN_ID=0_timesync-off
11030 11:47:07.835456 + TESTRUN_ID=0_timesync-off
11031 11:47:07.835807 + cd /lava-12074008/0/tests/0_timesync-off
11032 11:47:07.838968 ++ cat uuid
11033 11:47:07.846572 + UUID=12074008_1.6.2.3.1
11034 11:47:07.846656 + set +x
11035 11:47:07.853151 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12074008_1.6.2.3.1>
11036 11:47:07.853414 Received signal: <STARTRUN> 0_timesync-off 12074008_1.6.2.3.1
11037 11:47:07.853488 Starting test lava.0_timesync-off (12074008_1.6.2.3.1)
11038 11:47:07.853575 Skipping test definition patterns.
11039 11:47:07.855980 + systemctl stop systemd-timesyncd
11040 11:47:07.938496 + set +x
11041 11:47:07.940957 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12074008_1.6.2.3.1>
11042 11:47:07.941221 Received signal: <ENDRUN> 0_timesync-off 12074008_1.6.2.3.1
11043 11:47:07.941314 Ending use of test pattern.
11044 11:47:07.941378 Ending test lava.0_timesync-off (12074008_1.6.2.3.1), duration 0.09
11046 11:47:08.023621 + export TESTRUN_ID=1_kselftest-dt
11047 11:47:08.027084 + TESTRUN_ID=1_kselftest-dt
11048 11:47:08.030310 + cd /lava-12074008/0/tests/1_kselftest-dt
11049 11:47:08.034126 ++ cat uuid
11050 11:47:08.038149 + UUID=12074008_1.6.2.3.5
11051 11:47:08.038232 + set +x
11052 11:47:08.044822 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12074008_1.6.2.3.5>
11053 11:47:08.045082 Received signal: <STARTRUN> 1_kselftest-dt 12074008_1.6.2.3.5
11054 11:47:08.045156 Starting test lava.1_kselftest-dt (12074008_1.6.2.3.5)
11055 11:47:08.045238 Skipping test definition patterns.
11056 11:47:08.048090 + cd ./automated/linux/kselftest/
11057 11:47:08.074193 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11058 11:47:08.120098 INFO: install_deps skipped
11059 11:47:08.245692 --2023-11-24 11:47:08-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11060 11:47:08.261576 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11061 11:47:08.395425 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11062 11:47:08.527827 HTTP request sent, awaiting response... 200 OK
11063 11:47:08.531871 Length: 2961876 (2.8M) [application/octet-stream]
11064 11:47:08.534158 Saving to: 'kselftest.tar.xz'
11065 11:47:08.534239
11066 11:47:08.534386
11067 11:47:08.793846 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11068 11:47:09.060124 kselftest.tar.xz 1%[ ] 47.81K 181KB/s
11069 11:47:09.346996 kselftest.tar.xz 7%[> ] 217.50K 410KB/s
11070 11:47:09.592339 kselftest.tar.xz 19%[==> ] 566.77K 693KB/s
11071 11:47:09.858779 kselftest.tar.xz 57%[==========> ] 1.63M 1.53MB/s
11072 11:47:10.030881 kselftest.tar.xz 86%[================> ] 2.44M 1.83MB/s
11073 11:47:10.037558 kselftest.tar.xz 100%[===================>] 2.82M 1.88MB/s in 1.5s
11074 11:47:10.037645
11075 11:47:10.295716 2023-11-24 11:47:10 (1.88 MB/s) - 'kselftest.tar.xz' saved [2961876/2961876]
11076 11:47:10.295868
11077 11:47:16.786925 skiplist:
11078 11:47:16.789799 ========================================
11079 11:47:16.793465 ========================================
11080 11:47:16.868185 ============== Tests to run ===============
11081 11:47:16.871563 ===========End Tests to run ===============
11082 11:47:16.878743 shardfile-dt fail
11083 11:47:16.904017 ./kselftest.sh: 131: cannot open /lava-12074008/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11084 11:47:16.907083 + ../../utils/send-to-lava.sh ./output/result.txt
11085 11:47:16.992408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11086 11:47:16.992555 + set +x
11087 11:47:16.992802 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11089 11:47:16.999240 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12074008_1.6.2.3.5>
11090 11:47:16.999512 Received signal: <ENDRUN> 1_kselftest-dt 12074008_1.6.2.3.5
11091 11:47:16.999591 Ending use of test pattern.
11092 11:47:16.999653 Ending test lava.1_kselftest-dt (12074008_1.6.2.3.5), duration 8.95
11094 11:47:16.999876 ok: lava_test_shell seems to have completed
11095 11:47:16.999966 shardfile-dt: fail
11096 11:47:17.000055 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11097 11:47:17.000137 end: 3 lava-test-retry (duration 00:00:10) [common]
11098 11:47:17.000221 start: 4 finalize (timeout 00:07:08) [common]
11099 11:47:17.000314 start: 4.1 power-off (timeout 00:00:30) [common]
11100 11:47:17.000465 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11101 11:47:17.070283 >> Command sent successfully.
11102 11:47:17.072660 Returned 0 in 0 seconds
11103 11:47:17.173125 end: 4.1 power-off (duration 00:00:00) [common]
11105 11:47:17.173513 start: 4.2 read-feedback (timeout 00:07:08) [common]
11107 11:47:17.174084 Listened to connection for namespace 'common' for up to 1s
11108 11:47:18.174365 Finalising connection for namespace 'common'
11109 11:47:18.174541 Disconnecting from shell: Finalise
11110 11:47:18.174622 / #
11111 11:47:18.274975 end: 4.2 read-feedback (duration 00:00:01) [common]
11112 11:47:18.275162 end: 4 finalize (duration 00:00:01) [common]
11113 11:47:18.275280 Cleaning after the job
11114 11:47:18.275379 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/ramdisk
11115 11:47:18.278325 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/kernel
11116 11:47:18.290726 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/dtb
11117 11:47:18.290964 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/nfsrootfs
11118 11:47:18.383416 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12074008/tftp-deploy-ndrpbirt/modules
11119 11:47:18.390643 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12074008
11120 11:47:19.024173 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12074008
11121 11:47:19.024364 Job finished correctly